Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 34
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 17
1 11:07:13.519718 lava-dispatcher, installed at version: 2024.01
2 11:07:13.519931 start: 0 validate
3 11:07:13.520057 Start time: 2024-03-03 11:07:13.520049+00:00 (UTC)
4 11:07:13.520177 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:07:13.520326 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20240129.0%2Farm64%2Finitrd.cpio.gz exists
6 11:07:13.787073 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:07:13.787239 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:07:15.786389 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:07:15.786552 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:07:16.043909 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:07:16.044127 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20240129.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:07:16.299957 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:07:16.300143 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:07:19.302979 validate duration: 5.78
16 11:07:19.303270 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:07:19.303366 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:07:19.303451 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:07:19.303610 Not decompressing ramdisk as can be used compressed.
20 11:07:19.303694 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20240129.0/arm64/initrd.cpio.gz
21 11:07:19.303758 saving as /var/lib/lava/dispatcher/tmp/12925630/tftp-deploy-kpoqbs7e/ramdisk/initrd.cpio.gz
22 11:07:19.303825 total size: 4663047 (4 MB)
23 11:07:19.305022 progress 0 % (0 MB)
24 11:07:19.306504 progress 5 % (0 MB)
25 11:07:19.307802 progress 10 % (0 MB)
26 11:07:19.309110 progress 15 % (0 MB)
27 11:07:19.310365 progress 20 % (0 MB)
28 11:07:19.311632 progress 25 % (1 MB)
29 11:07:19.312948 progress 30 % (1 MB)
30 11:07:19.314181 progress 35 % (1 MB)
31 11:07:19.315414 progress 40 % (1 MB)
32 11:07:19.316881 progress 45 % (2 MB)
33 11:07:19.318182 progress 50 % (2 MB)
34 11:07:19.319527 progress 55 % (2 MB)
35 11:07:19.320843 progress 60 % (2 MB)
36 11:07:19.322085 progress 65 % (2 MB)
37 11:07:19.323315 progress 70 % (3 MB)
38 11:07:19.324592 progress 75 % (3 MB)
39 11:07:19.325925 progress 80 % (3 MB)
40 11:07:19.327170 progress 85 % (3 MB)
41 11:07:19.328600 progress 90 % (4 MB)
42 11:07:19.330430 progress 95 % (4 MB)
43 11:07:19.332514 progress 100 % (4 MB)
44 11:07:19.332733 4 MB downloaded in 0.03 s (153.85 MB/s)
45 11:07:19.332949 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:07:19.333327 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:07:19.333462 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:07:19.333554 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:07:19.333677 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:07:19.333745 saving as /var/lib/lava/dispatcher/tmp/12925630/tftp-deploy-kpoqbs7e/kernel/Image
52 11:07:19.333810 total size: 51599872 (49 MB)
53 11:07:19.333871 No compression specified
54 11:07:19.334926 progress 0 % (0 MB)
55 11:07:19.348363 progress 5 % (2 MB)
56 11:07:19.362034 progress 10 % (4 MB)
57 11:07:19.375659 progress 15 % (7 MB)
58 11:07:19.389418 progress 20 % (9 MB)
59 11:07:19.403568 progress 25 % (12 MB)
60 11:07:19.417231 progress 30 % (14 MB)
61 11:07:19.430769 progress 35 % (17 MB)
62 11:07:19.444348 progress 40 % (19 MB)
63 11:07:19.458124 progress 45 % (22 MB)
64 11:07:19.471840 progress 50 % (24 MB)
65 11:07:19.485553 progress 55 % (27 MB)
66 11:07:19.505535 progress 60 % (29 MB)
67 11:07:19.526443 progress 65 % (32 MB)
68 11:07:19.540909 progress 70 % (34 MB)
69 11:07:19.556198 progress 75 % (36 MB)
70 11:07:19.572762 progress 80 % (39 MB)
71 11:07:19.589182 progress 85 % (41 MB)
72 11:07:19.606599 progress 90 % (44 MB)
73 11:07:19.628541 progress 95 % (46 MB)
74 11:07:19.651189 progress 100 % (49 MB)
75 11:07:19.651574 49 MB downloaded in 0.32 s (154.86 MB/s)
76 11:07:19.651812 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:07:19.652272 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:07:19.652420 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:07:19.652546 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:07:19.652744 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:07:19.652858 saving as /var/lib/lava/dispatcher/tmp/12925630/tftp-deploy-kpoqbs7e/dtb/mt8192-asurada-spherion-r0.dtb
83 11:07:19.652949 total size: 47278 (0 MB)
84 11:07:19.653039 No compression specified
85 11:07:19.654676 progress 69 % (0 MB)
86 11:07:19.655116 progress 100 % (0 MB)
87 11:07:19.655402 0 MB downloaded in 0.00 s (18.41 MB/s)
88 11:07:19.655625 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:07:19.655979 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:07:19.656113 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:07:19.656252 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:07:19.656457 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20240129.0/arm64/full.rootfs.tar.xz
94 11:07:19.656553 saving as /var/lib/lava/dispatcher/tmp/12925630/tftp-deploy-kpoqbs7e/nfsrootfs/full.rootfs.tar
95 11:07:19.656663 total size: 200856304 (191 MB)
96 11:07:19.656756 Using unxz to decompress xz
97 11:07:19.662454 progress 0 % (0 MB)
98 11:07:20.224895 progress 5 % (9 MB)
99 11:07:20.821786 progress 10 % (19 MB)
100 11:07:21.467459 progress 15 % (28 MB)
101 11:07:21.845190 progress 20 % (38 MB)
102 11:07:22.203993 progress 25 % (47 MB)
103 11:07:22.877064 progress 30 % (57 MB)
104 11:07:23.498254 progress 35 % (67 MB)
105 11:07:24.194945 progress 40 % (76 MB)
106 11:07:24.831337 progress 45 % (86 MB)
107 11:07:25.496283 progress 50 % (95 MB)
108 11:07:26.211748 progress 55 % (105 MB)
109 11:07:26.934854 progress 60 % (114 MB)
110 11:07:27.078170 progress 65 % (124 MB)
111 11:07:27.243502 progress 70 % (134 MB)
112 11:07:27.349531 progress 75 % (143 MB)
113 11:07:27.433451 progress 80 % (153 MB)
114 11:07:27.524038 progress 85 % (162 MB)
115 11:07:27.648696 progress 90 % (172 MB)
116 11:07:27.969944 progress 95 % (182 MB)
117 11:07:28.582303 progress 100 % (191 MB)
118 11:07:28.588216 191 MB downloaded in 8.93 s (21.45 MB/s)
119 11:07:28.588560 end: 1.4.1 http-download (duration 00:00:09) [common]
121 11:07:28.588968 end: 1.4 download-retry (duration 00:00:09) [common]
122 11:07:28.589101 start: 1.5 download-retry (timeout 00:09:51) [common]
123 11:07:28.589231 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 11:07:28.589444 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:07:28.589551 saving as /var/lib/lava/dispatcher/tmp/12925630/tftp-deploy-kpoqbs7e/modules/modules.tar
126 11:07:28.589648 total size: 8628476 (8 MB)
127 11:07:28.589750 Using unxz to decompress xz
128 11:07:28.859494 progress 0 % (0 MB)
129 11:07:28.886881 progress 5 % (0 MB)
130 11:07:28.914054 progress 10 % (0 MB)
131 11:07:28.942970 progress 15 % (1 MB)
132 11:07:28.970698 progress 20 % (1 MB)
133 11:07:28.998733 progress 25 % (2 MB)
134 11:07:29.028693 progress 30 % (2 MB)
135 11:07:29.065178 progress 35 % (2 MB)
136 11:07:29.097873 progress 40 % (3 MB)
137 11:07:29.127386 progress 45 % (3 MB)
138 11:07:29.153794 progress 50 % (4 MB)
139 11:07:29.183656 progress 55 % (4 MB)
140 11:07:29.210824 progress 60 % (4 MB)
141 11:07:29.245209 progress 65 % (5 MB)
142 11:07:29.274492 progress 70 % (5 MB)
143 11:07:29.306064 progress 75 % (6 MB)
144 11:07:29.340271 progress 80 % (6 MB)
145 11:07:29.373933 progress 85 % (7 MB)
146 11:07:29.407439 progress 90 % (7 MB)
147 11:07:29.443613 progress 95 % (7 MB)
148 11:07:29.473343 progress 100 % (8 MB)
149 11:07:29.479694 8 MB downloaded in 0.89 s (9.25 MB/s)
150 11:07:29.479997 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:07:29.480409 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:07:29.480519 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 11:07:29.480637 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 11:07:33.963362 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12925630/extract-nfsrootfs-uebyb0qu
156 11:07:33.963699 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:07:33.963872 start: 1.6.2 lava-overlay (timeout 00:09:45) [common]
158 11:07:33.964154 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9
159 11:07:33.964411 makedir: /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin
160 11:07:33.964587 makedir: /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/tests
161 11:07:33.964759 makedir: /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/results
162 11:07:33.964926 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-add-keys
163 11:07:33.965163 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-add-sources
164 11:07:33.965380 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-background-process-start
165 11:07:33.965592 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-background-process-stop
166 11:07:33.965803 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-common-functions
167 11:07:33.966014 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-echo-ipv4
168 11:07:33.966226 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-install-packages
169 11:07:33.966436 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-installed-packages
170 11:07:33.966648 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-os-build
171 11:07:33.966861 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-probe-channel
172 11:07:33.967078 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-probe-ip
173 11:07:33.967287 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-target-ip
174 11:07:33.967496 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-target-mac
175 11:07:33.967700 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-target-storage
176 11:07:33.967914 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-test-case
177 11:07:33.968126 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-test-event
178 11:07:33.968375 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-test-feedback
179 11:07:33.968548 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-test-raise
180 11:07:33.968719 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-test-reference
181 11:07:33.968885 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-test-runner
182 11:07:33.969048 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-test-set
183 11:07:33.969209 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-test-shell
184 11:07:33.969373 Updating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-add-keys (debian)
185 11:07:33.969579 Updating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-add-sources (debian)
186 11:07:33.969774 Updating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-install-packages (debian)
187 11:07:33.969951 Updating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-installed-packages (debian)
188 11:07:33.970125 Updating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/bin/lava-os-build (debian)
189 11:07:33.970277 Creating /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/environment
190 11:07:33.970404 LAVA metadata
191 11:07:33.970544 - LAVA_JOB_ID=12925630
192 11:07:33.970638 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:07:33.970819 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:45) [common]
194 11:07:33.970914 skipped lava-vland-overlay
195 11:07:33.971021 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:07:33.971131 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:45) [common]
197 11:07:33.971219 skipped lava-multinode-overlay
198 11:07:33.971320 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:07:33.971428 start: 1.6.2.3 test-definition (timeout 00:09:45) [common]
200 11:07:33.971535 Loading test definitions
201 11:07:33.971689 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:45) [common]
202 11:07:33.971790 Using /lava-12925630 at stage 0
203 11:07:33.972187 uuid=12925630_1.6.2.3.1 testdef=None
204 11:07:33.972331 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:07:33.972462 start: 1.6.2.3.2 test-overlay (timeout 00:09:45) [common]
206 11:07:33.973090 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:07:33.973463 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:45) [common]
209 11:07:33.974364 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:07:33.974769 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:45) [common]
212 11:07:33.975613 runner path: /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/0/tests/0_timesync-off test_uuid 12925630_1.6.2.3.1
213 11:07:33.975843 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:07:33.976201 start: 1.6.2.3.5 git-repo-action (timeout 00:09:45) [common]
216 11:07:33.976327 Using /lava-12925630 at stage 0
217 11:07:33.976481 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:07:33.976600 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/0/tests/1_kselftest-arm64'
219 11:07:37.185792 Running '/usr/bin/git checkout kernelci.org
220 11:07:37.347085 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 11:07:37.348066 uuid=12925630_1.6.2.3.5 testdef=None
222 11:07:37.348246 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 11:07:37.348663 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 11:07:37.349962 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:07:37.350364 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 11:07:37.352052 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:07:37.352470 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 11:07:37.353828 runner path: /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/0/tests/1_kselftest-arm64 test_uuid 12925630_1.6.2.3.5
232 11:07:37.353925 BOARD='mt8192-asurada-spherion-r0'
233 11:07:37.353991 BRANCH='cip'
234 11:07:37.354052 SKIPFILE='/dev/null'
235 11:07:37.354112 SKIP_INSTALL='True'
236 11:07:37.354172 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:07:37.354235 TST_CASENAME=''
238 11:07:37.354293 TST_CMDFILES='arm64'
239 11:07:37.354447 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:07:37.354667 Creating lava-test-runner.conf files
242 11:07:37.354734 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12925630/lava-overlay-7fsunny9/lava-12925630/0 for stage 0
243 11:07:37.354836 - 0_timesync-off
244 11:07:37.354909 - 1_kselftest-arm64
245 11:07:37.355013 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 11:07:37.355110 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 11:07:45.389568 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:07:45.389749 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:34) [common]
249 11:07:45.389878 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:07:45.389978 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 11:07:45.390073 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
252 11:07:45.525213 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:07:45.525748 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
254 11:07:45.525927 extracting modules file /var/lib/lava/dispatcher/tmp/12925630/tftp-deploy-kpoqbs7e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925630/extract-nfsrootfs-uebyb0qu
255 11:07:45.812736 extracting modules file /var/lib/lava/dispatcher/tmp/12925630/tftp-deploy-kpoqbs7e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925630/extract-overlay-ramdisk-_w519x9g/ramdisk
256 11:07:46.095807 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 11:07:46.095983 start: 1.6.5 apply-overlay-tftp (timeout 00:09:33) [common]
258 11:07:46.096080 [common] Applying overlay to NFS
259 11:07:46.096155 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925630/compress-overlay-kbhzx2if/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12925630/extract-nfsrootfs-uebyb0qu
260 11:07:47.149717 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:07:47.149902 start: 1.6.6 configure-preseed-file (timeout 00:09:32) [common]
262 11:07:47.150047 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:07:47.150168 start: 1.6.7 compress-ramdisk (timeout 00:09:32) [common]
264 11:07:47.150279 Building ramdisk /var/lib/lava/dispatcher/tmp/12925630/extract-overlay-ramdisk-_w519x9g/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12925630/extract-overlay-ramdisk-_w519x9g/ramdisk
265 11:07:47.463664 >> 119441 blocks
266 11:07:49.446109 rename /var/lib/lava/dispatcher/tmp/12925630/extract-overlay-ramdisk-_w519x9g/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12925630/tftp-deploy-kpoqbs7e/ramdisk/ramdisk.cpio.gz
267 11:07:49.446554 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:07:49.446673 start: 1.6.8 prepare-kernel (timeout 00:09:30) [common]
269 11:07:49.446778 start: 1.6.8.1 prepare-fit (timeout 00:09:30) [common]
270 11:07:49.446886 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12925630/tftp-deploy-kpoqbs7e/kernel/Image'
271 11:08:03.562875 Returned 0 in 14 seconds
272 11:08:03.663565 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12925630/tftp-deploy-kpoqbs7e/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12925630/tftp-deploy-kpoqbs7e/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12925630/tftp-deploy-kpoqbs7e/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12925630/tftp-deploy-kpoqbs7e/kernel/image.itb
273 11:08:04.026574 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:08:04.027081 output: Created: Sun Mar 3 11:08:03 2024
275 11:08:04.027219 output: Image 0 (kernel-1)
276 11:08:04.027356 output: Description:
277 11:08:04.027476 output: Created: Sun Mar 3 11:08:03 2024
278 11:08:04.027589 output: Type: Kernel Image
279 11:08:04.027705 output: Compression: lzma compressed
280 11:08:04.027829 output: Data Size: 12057697 Bytes = 11775.09 KiB = 11.50 MiB
281 11:08:04.027943 output: Architecture: AArch64
282 11:08:04.028050 output: OS: Linux
283 11:08:04.028161 output: Load Address: 0x00000000
284 11:08:04.028272 output: Entry Point: 0x00000000
285 11:08:04.028388 output: Hash algo: crc32
286 11:08:04.028501 output: Hash value: cf43f4f3
287 11:08:04.028613 output: Image 1 (fdt-1)
288 11:08:04.028721 output: Description: mt8192-asurada-spherion-r0
289 11:08:04.028831 output: Created: Sun Mar 3 11:08:03 2024
290 11:08:04.028946 output: Type: Flat Device Tree
291 11:08:04.029048 output: Compression: uncompressed
292 11:08:04.029153 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 11:08:04.029262 output: Architecture: AArch64
294 11:08:04.029371 output: Hash algo: crc32
295 11:08:04.029475 output: Hash value: cc4352de
296 11:08:04.029586 output: Image 2 (ramdisk-1)
297 11:08:04.029693 output: Description: unavailable
298 11:08:04.029803 output: Created: Sun Mar 3 11:08:03 2024
299 11:08:04.029909 output: Type: RAMDisk Image
300 11:08:04.030020 output: Compression: Unknown Compression
301 11:08:04.030127 output: Data Size: 17805670 Bytes = 17388.35 KiB = 16.98 MiB
302 11:08:04.030245 output: Architecture: AArch64
303 11:08:04.030356 output: OS: Linux
304 11:08:04.030460 output: Load Address: unavailable
305 11:08:04.030567 output: Entry Point: unavailable
306 11:08:04.030675 output: Hash algo: crc32
307 11:08:04.030778 output: Hash value: 94dfda34
308 11:08:04.030885 output: Default Configuration: 'conf-1'
309 11:08:04.030993 output: Configuration 0 (conf-1)
310 11:08:04.031098 output: Description: mt8192-asurada-spherion-r0
311 11:08:04.031206 output: Kernel: kernel-1
312 11:08:04.031310 output: Init Ramdisk: ramdisk-1
313 11:08:04.031418 output: FDT: fdt-1
314 11:08:04.031526 output: Loadables: kernel-1
315 11:08:04.031642 output:
316 11:08:04.031956 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 11:08:04.032130 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 11:08:04.032312 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 11:08:04.032484 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:15) [common]
320 11:08:04.032624 No LXC device requested
321 11:08:04.032767 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:08:04.032930 start: 1.8 deploy-device-env (timeout 00:09:15) [common]
323 11:08:04.033073 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:08:04.033200 Checking files for TFTP limit of 4294967296 bytes.
325 11:08:04.034045 end: 1 tftp-deploy (duration 00:00:45) [common]
326 11:08:04.034215 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:08:04.034346 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:08:04.034480 substitutions:
329 11:08:04.034555 - {DTB}: 12925630/tftp-deploy-kpoqbs7e/dtb/mt8192-asurada-spherion-r0.dtb
330 11:08:04.034625 - {INITRD}: 12925630/tftp-deploy-kpoqbs7e/ramdisk/ramdisk.cpio.gz
331 11:08:04.034687 - {KERNEL}: 12925630/tftp-deploy-kpoqbs7e/kernel/Image
332 11:08:04.034749 - {LAVA_MAC}: None
333 11:08:04.034811 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12925630/extract-nfsrootfs-uebyb0qu
334 11:08:04.034870 - {NFS_SERVER_IP}: 192.168.201.1
335 11:08:04.034927 - {PRESEED_CONFIG}: None
336 11:08:04.034988 - {PRESEED_LOCAL}: None
337 11:08:04.035047 - {RAMDISK}: 12925630/tftp-deploy-kpoqbs7e/ramdisk/ramdisk.cpio.gz
338 11:08:04.035106 - {ROOT_PART}: None
339 11:08:04.035161 - {ROOT}: None
340 11:08:04.035223 - {SERVER_IP}: 192.168.201.1
341 11:08:04.035289 - {TEE}: None
342 11:08:04.035375 Parsed boot commands:
343 11:08:04.035468 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:08:04.035664 Parsed boot commands: tftpboot 192.168.201.1 12925630/tftp-deploy-kpoqbs7e/kernel/image.itb 12925630/tftp-deploy-kpoqbs7e/kernel/cmdline
345 11:08:04.035761 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:08:04.035848 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:08:04.035943 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:08:04.036038 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:08:04.036112 Not connected, no need to disconnect.
350 11:08:04.036185 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:08:04.036280 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:08:04.036364 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 11:08:04.040560 Setting prompt string to ['lava-test: # ']
354 11:08:04.041019 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:08:04.041183 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:08:04.041329 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:08:04.041469 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:08:04.041842 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 11:08:09.174435 >> Command sent successfully.
360 11:08:09.176857 Returned 0 in 5 seconds
361 11:08:09.277322 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:08:09.277662 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:08:09.277761 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:08:09.277852 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:08:09.277919 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:08:09.277990 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:08:09.278264 [Enter `^Ec?' for help]
369 11:08:09.450729
370 11:08:09.450874
371 11:08:09.450950 F0: 102B 0000
372 11:08:09.451021
373 11:08:09.451087 F3: 1001 0000 [0200]
374 11:08:09.453848
375 11:08:09.453926 F3: 1001 0000
376 11:08:09.454021
377 11:08:09.454112 F7: 102D 0000
378 11:08:09.454202
379 11:08:09.457210 F1: 0000 0000
380 11:08:09.457289
381 11:08:09.457384 V0: 0000 0000 [0001]
382 11:08:09.457477
383 11:08:09.460512 00: 0007 8000
384 11:08:09.460595
385 11:08:09.460658 01: 0000 0000
386 11:08:09.460722
387 11:08:09.463925 BP: 0C00 0209 [0000]
388 11:08:09.464028
389 11:08:09.464122 G0: 1182 0000
390 11:08:09.464212
391 11:08:09.467969 EC: 0000 0021 [4000]
392 11:08:09.468073
393 11:08:09.468166 S7: 0000 0000 [0000]
394 11:08:09.468256
395 11:08:09.471291 CC: 0000 0000 [0001]
396 11:08:09.471397
397 11:08:09.471493 T0: 0000 0040 [010F]
398 11:08:09.471587
399 11:08:09.471703 Jump to BL
400 11:08:09.471797
401 11:08:09.497776
402 11:08:09.497900
403 11:08:09.497999
404 11:08:09.504431 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:08:09.508142 ARM64: Exception handlers installed.
406 11:08:09.511556 ARM64: Testing exception
407 11:08:09.514681 ARM64: Done test exception
408 11:08:09.521437 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:08:09.531872 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:08:09.538546 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:08:09.548110 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:08:09.554747 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:08:09.565306 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:08:09.576253 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:08:09.582741 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:08:09.600604 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:08:09.603695 WDT: Last reset was cold boot
418 11:08:09.607297 SPI1(PAD0) initialized at 2873684 Hz
419 11:08:09.610312 SPI5(PAD0) initialized at 992727 Hz
420 11:08:09.613651 VBOOT: Loading verstage.
421 11:08:09.620557 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:08:09.624031 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:08:09.627333 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:08:09.630538 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:08:09.637892 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:08:09.644259 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:08:09.655482 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 11:08:09.655627
429 11:08:09.655747
430 11:08:09.665885 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:08:09.669278 ARM64: Exception handlers installed.
432 11:08:09.669419 ARM64: Testing exception
433 11:08:09.672495 ARM64: Done test exception
434 11:08:09.676459 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:08:09.683089 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:08:09.696200 Probing TPM: . done!
437 11:08:09.696345 TPM ready after 0 ms
438 11:08:09.703510 Connected to device vid:did:rid of 1ae0:0028:00
439 11:08:09.709474 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 11:08:09.769210 Initialized TPM device CR50 revision 0
441 11:08:09.781283 tlcl_send_startup: Startup return code is 0
442 11:08:09.781402 TPM: setup succeeded
443 11:08:09.792405 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:08:09.801358 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:08:09.815299 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:08:09.822507 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:08:09.826530 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:08:09.829664 in-header: 03 07 00 00 08 00 00 00
449 11:08:09.833471 in-data: aa e4 47 04 13 02 00 00
450 11:08:09.833560 Chrome EC: UHEPI supported
451 11:08:09.840761 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:08:09.844717 in-header: 03 95 00 00 08 00 00 00
453 11:08:09.847923 in-data: 18 20 20 08 00 00 00 00
454 11:08:09.848042 Phase 1
455 11:08:09.851728 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:08:09.859649 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:08:09.866421 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:08:09.866567 Recovery requested (1009000e)
459 11:08:09.877274 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:08:09.882715 tlcl_extend: response is 0
461 11:08:09.894152 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:08:09.898030 tlcl_extend: response is 0
463 11:08:09.904897 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:08:09.924193 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 11:08:09.931431 BS: bootblock times (exec / console): total (unknown) / 149 ms
466 11:08:09.931519
467 11:08:09.931587
468 11:08:09.940849 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:08:09.944121 ARM64: Exception handlers installed.
470 11:08:09.947364 ARM64: Testing exception
471 11:08:09.947497 ARM64: Done test exception
472 11:08:09.969920 pmic_efuse_setting: Set efuses in 11 msecs
473 11:08:09.973134 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:08:09.979946 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:08:09.983426 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:08:09.990328 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:08:09.994159 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:08:09.997921 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:08:10.001688 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:08:10.009170 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:08:10.013153 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:08:10.016561 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:08:10.024541 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:08:10.027959 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:08:10.031275 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:08:10.034695 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:08:10.041972 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:08:10.049490 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:08:10.052578 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:08:10.060088 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:08:10.064168 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:08:10.071392 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:08:10.075317 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:08:10.082509 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:08:10.086379 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:08:10.093941 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:08:10.097143 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:08:10.104845 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:08:10.108820 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:08:10.115856 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:08:10.119970 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:08:10.123164 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:08:10.130561 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:08:10.134596 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:08:10.138645 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:08:10.145827 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:08:10.149089 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:08:10.153170 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:08:10.160602 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:08:10.164661 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:08:10.168660 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:08:10.171938 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:08:10.179356 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:08:10.183237 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:08:10.186967 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:08:10.190818 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:08:10.194045 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:08:10.197898 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:08:10.205231 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:08:10.209146 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:08:10.212797 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:08:10.216050 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:08:10.219755 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:08:10.223618 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:08:10.231016 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:08:10.242626 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:08:10.246416 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:08:10.253708 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:08:10.260658 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:08:10.268623 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:08:10.272651 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:08:10.275907 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:08:10.283907 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2c
534 11:08:10.287193 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:08:10.294992 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 11:08:10.298630 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:08:10.307343 [RTC]rtc_get_frequency_meter,154: input=15, output=759
538 11:08:10.316720 [RTC]rtc_get_frequency_meter,154: input=23, output=942
539 11:08:10.326490 [RTC]rtc_get_frequency_meter,154: input=19, output=850
540 11:08:10.336266 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 11:08:10.345447 [RTC]rtc_get_frequency_meter,154: input=16, output=781
542 11:08:10.355255 [RTC]rtc_get_frequency_meter,154: input=16, output=782
543 11:08:10.365458 [RTC]rtc_get_frequency_meter,154: input=17, output=804
544 11:08:10.368987 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 11:08:10.372682 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 11:08:10.375950 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:08:10.383444 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 11:08:10.386787 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:08:10.390932 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 11:08:10.394346 ADC[4]: Raw value=906203 ID=7
551 11:08:10.394460 ADC[3]: Raw value=213441 ID=1
552 11:08:10.398227 RAM Code: 0x71
553 11:08:10.402197 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:08:10.406341 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:08:10.417266 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:08:10.420564 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:08:10.424584 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:08:10.429251 in-header: 03 07 00 00 08 00 00 00
559 11:08:10.432278 in-data: aa e4 47 04 13 02 00 00
560 11:08:10.436172 Chrome EC: UHEPI supported
561 11:08:10.443547 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:08:10.446945 in-header: 03 95 00 00 08 00 00 00
563 11:08:10.450972 in-data: 18 20 20 08 00 00 00 00
564 11:08:10.451070 MRC: failed to locate region type 0.
565 11:08:10.458361 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:08:10.461732 DRAM-K: Running full calibration
567 11:08:10.469174 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:08:10.469298 header.status = 0x0
569 11:08:10.473275 header.version = 0x6 (expected: 0x6)
570 11:08:10.476845 header.size = 0xd00 (expected: 0xd00)
571 11:08:10.480450 header.flags = 0x0
572 11:08:10.483898 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:08:10.503332 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 11:08:10.510451 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:08:10.510574 dram_init: ddr_geometry: 2
576 11:08:10.514293 [EMI] MDL number = 2
577 11:08:10.514406 [EMI] Get MDL freq = 0
578 11:08:10.518169 dram_init: ddr_type: 0
579 11:08:10.522199 is_discrete_lpddr4: 1
580 11:08:10.522314 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:08:10.522425
582 11:08:10.526236
583 11:08:10.526350 [Bian_co] ETT version 0.0.0.1
584 11:08:10.529681 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:08:10.529761
586 11:08:10.533730 dramc_set_vcore_voltage set vcore to 650000
587 11:08:10.536988 Read voltage for 800, 4
588 11:08:10.537103 Vio18 = 0
589 11:08:10.541363 Vcore = 650000
590 11:08:10.541477 Vdram = 0
591 11:08:10.541574 Vddq = 0
592 11:08:10.541669 Vmddr = 0
593 11:08:10.544632 dram_init: config_dvfs: 1
594 11:08:10.548539 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:08:10.556166 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:08:10.559655 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 11:08:10.563765 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 11:08:10.567642 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 11:08:10.571254 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 11:08:10.571341 MEM_TYPE=3, freq_sel=18
601 11:08:10.574735 sv_algorithm_assistance_LP4_1600
602 11:08:10.581137 ============ PULL DRAM RESETB DOWN ============
603 11:08:10.584623 ========== PULL DRAM RESETB DOWN end =========
604 11:08:10.587708 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:08:10.590825 ===================================
606 11:08:10.595011 LPDDR4 DRAM CONFIGURATION
607 11:08:10.598747 ===================================
608 11:08:10.598860 EX_ROW_EN[0] = 0x0
609 11:08:10.602240 EX_ROW_EN[1] = 0x0
610 11:08:10.602327 LP4Y_EN = 0x0
611 11:08:10.606367 WORK_FSP = 0x0
612 11:08:10.606456 WL = 0x2
613 11:08:10.609631 RL = 0x2
614 11:08:10.609719 BL = 0x2
615 11:08:10.613564 RPST = 0x0
616 11:08:10.613673 RD_PRE = 0x0
617 11:08:10.613772 WR_PRE = 0x1
618 11:08:10.616757 WR_PST = 0x0
619 11:08:10.616840 DBI_WR = 0x0
620 11:08:10.620712 DBI_RD = 0x0
621 11:08:10.620819 OTF = 0x1
622 11:08:10.623911 ===================================
623 11:08:10.627026 ===================================
624 11:08:10.630390 ANA top config
625 11:08:10.633686 ===================================
626 11:08:10.636975 DLL_ASYNC_EN = 0
627 11:08:10.637054 ALL_SLAVE_EN = 1
628 11:08:10.640229 NEW_RANK_MODE = 1
629 11:08:10.643553 DLL_IDLE_MODE = 1
630 11:08:10.646648 LP45_APHY_COMB_EN = 1
631 11:08:10.650499 TX_ODT_DIS = 1
632 11:08:10.650608 NEW_8X_MODE = 1
633 11:08:10.653907 ===================================
634 11:08:10.657333 ===================================
635 11:08:10.660658 data_rate = 1600
636 11:08:10.664012 CKR = 1
637 11:08:10.667235 DQ_P2S_RATIO = 8
638 11:08:10.670648 ===================================
639 11:08:10.670774 CA_P2S_RATIO = 8
640 11:08:10.673919 DQ_CA_OPEN = 0
641 11:08:10.677237 DQ_SEMI_OPEN = 0
642 11:08:10.681086 CA_SEMI_OPEN = 0
643 11:08:10.684252 CA_FULL_RATE = 0
644 11:08:10.687811 DQ_CKDIV4_EN = 1
645 11:08:10.687927 CA_CKDIV4_EN = 1
646 11:08:10.690820 CA_PREDIV_EN = 0
647 11:08:10.694506 PH8_DLY = 0
648 11:08:10.697449 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:08:10.700811 DQ_AAMCK_DIV = 4
650 11:08:10.704517 CA_AAMCK_DIV = 4
651 11:08:10.704630 CA_ADMCK_DIV = 4
652 11:08:10.707569 DQ_TRACK_CA_EN = 0
653 11:08:10.711071 CA_PICK = 800
654 11:08:10.714419 CA_MCKIO = 800
655 11:08:10.717860 MCKIO_SEMI = 0
656 11:08:10.721727 PLL_FREQ = 3068
657 11:08:10.721842 DQ_UI_PI_RATIO = 32
658 11:08:10.726093 CA_UI_PI_RATIO = 0
659 11:08:10.729870 ===================================
660 11:08:10.733561 ===================================
661 11:08:10.733643 memory_type:LPDDR4
662 11:08:10.737752 GP_NUM : 10
663 11:08:10.737875 SRAM_EN : 1
664 11:08:10.740848 MD32_EN : 0
665 11:08:10.744325 ===================================
666 11:08:10.748356 [ANA_INIT] >>>>>>>>>>>>>>
667 11:08:10.748438 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:08:10.752207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:08:10.755263 ===================================
670 11:08:10.758755 data_rate = 1600,PCW = 0X7600
671 11:08:10.761935 ===================================
672 11:08:10.765290 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:08:10.772060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:08:10.775469 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:08:10.782002 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:08:10.785868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:08:10.788605 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:08:10.788693 [ANA_INIT] flow start
679 11:08:10.791954 [ANA_INIT] PLL >>>>>>>>
680 11:08:10.795794 [ANA_INIT] PLL <<<<<<<<
681 11:08:10.795883 [ANA_INIT] MIDPI >>>>>>>>
682 11:08:10.798832 [ANA_INIT] MIDPI <<<<<<<<
683 11:08:10.802415 [ANA_INIT] DLL >>>>>>>>
684 11:08:10.802512 [ANA_INIT] flow end
685 11:08:10.808895 ============ LP4 DIFF to SE enter ============
686 11:08:10.812279 ============ LP4 DIFF to SE exit ============
687 11:08:10.815581 [ANA_INIT] <<<<<<<<<<<<<
688 11:08:10.818821 [Flow] Enable top DCM control >>>>>
689 11:08:10.818934 [Flow] Enable top DCM control <<<<<
690 11:08:10.822119 Enable DLL master slave shuffle
691 11:08:10.828709 ==============================================================
692 11:08:10.831790 Gating Mode config
693 11:08:10.835564 ==============================================================
694 11:08:10.838917 Config description:
695 11:08:10.848570 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:08:10.855491 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:08:10.858569 SELPH_MODE 0: By rank 1: By Phase
698 11:08:10.865472 ==============================================================
699 11:08:10.868813 GAT_TRACK_EN = 1
700 11:08:10.872128 RX_GATING_MODE = 2
701 11:08:10.872246 RX_GATING_TRACK_MODE = 2
702 11:08:10.875659 SELPH_MODE = 1
703 11:08:10.879162 PICG_EARLY_EN = 1
704 11:08:10.882610 VALID_LAT_VALUE = 1
705 11:08:10.888662 ==============================================================
706 11:08:10.892148 Enter into Gating configuration >>>>
707 11:08:10.895474 Exit from Gating configuration <<<<
708 11:08:10.899000 Enter into DVFS_PRE_config >>>>>
709 11:08:10.908864 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:08:10.912023 Exit from DVFS_PRE_config <<<<<
711 11:08:10.915805 Enter into PICG configuration >>>>
712 11:08:10.919131 Exit from PICG configuration <<<<
713 11:08:10.922342 [RX_INPUT] configuration >>>>>
714 11:08:10.925673 [RX_INPUT] configuration <<<<<
715 11:08:10.929105 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:08:10.935671 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:08:10.942300 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:08:10.945591 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:08:10.951980 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:08:10.958941 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:08:10.962268 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:08:10.965572 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:08:10.972280 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:08:10.975372 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:08:10.979014 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:08:10.985657 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:08:10.988872 ===================================
728 11:08:10.988952 LPDDR4 DRAM CONFIGURATION
729 11:08:10.992438 ===================================
730 11:08:10.995727 EX_ROW_EN[0] = 0x0
731 11:08:10.995807 EX_ROW_EN[1] = 0x0
732 11:08:10.999028 LP4Y_EN = 0x0
733 11:08:11.002326 WORK_FSP = 0x0
734 11:08:11.002435 WL = 0x2
735 11:08:11.005541 RL = 0x2
736 11:08:11.005661 BL = 0x2
737 11:08:11.008845 RPST = 0x0
738 11:08:11.008950 RD_PRE = 0x0
739 11:08:11.012181 WR_PRE = 0x1
740 11:08:11.012313 WR_PST = 0x0
741 11:08:11.015901 DBI_WR = 0x0
742 11:08:11.016015 DBI_RD = 0x0
743 11:08:11.018943 OTF = 0x1
744 11:08:11.022228 ===================================
745 11:08:11.025875 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:08:11.028985 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:08:11.032640 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:08:11.035740 ===================================
749 11:08:11.039232 LPDDR4 DRAM CONFIGURATION
750 11:08:11.042576 ===================================
751 11:08:11.045530 EX_ROW_EN[0] = 0x10
752 11:08:11.045613 EX_ROW_EN[1] = 0x0
753 11:08:11.049417 LP4Y_EN = 0x0
754 11:08:11.049497 WORK_FSP = 0x0
755 11:08:11.052587 WL = 0x2
756 11:08:11.052697 RL = 0x2
757 11:08:11.055656 BL = 0x2
758 11:08:11.055765 RPST = 0x0
759 11:08:11.058763 RD_PRE = 0x0
760 11:08:11.058873 WR_PRE = 0x1
761 11:08:11.062660 WR_PST = 0x0
762 11:08:11.062765 DBI_WR = 0x0
763 11:08:11.065967 DBI_RD = 0x0
764 11:08:11.066068 OTF = 0x1
765 11:08:11.069179 ===================================
766 11:08:11.075716 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:08:11.080541 nWR fixed to 40
768 11:08:11.084130 [ModeRegInit_LP4] CH0 RK0
769 11:08:11.084238 [ModeRegInit_LP4] CH0 RK1
770 11:08:11.087224 [ModeRegInit_LP4] CH1 RK0
771 11:08:11.090757 [ModeRegInit_LP4] CH1 RK1
772 11:08:11.090865 match AC timing 13
773 11:08:11.097758 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:08:11.100940 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:08:11.104236 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:08:11.110845 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:08:11.114247 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:08:11.114352 [EMI DOE] emi_dcm 0
779 11:08:11.120678 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:08:11.120760 ==
781 11:08:11.124053 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:08:11.127480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:08:11.127558 ==
784 11:08:11.134125 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:08:11.137803 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:08:11.148298 [CA 0] Center 36 (6~67) winsize 62
787 11:08:11.151739 [CA 1] Center 36 (6~67) winsize 62
788 11:08:11.155214 [CA 2] Center 34 (4~65) winsize 62
789 11:08:11.158038 [CA 3] Center 34 (4~64) winsize 61
790 11:08:11.161170 [CA 4] Center 33 (3~64) winsize 62
791 11:08:11.164496 [CA 5] Center 33 (3~63) winsize 61
792 11:08:11.164641
793 11:08:11.168407 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 11:08:11.168517
795 11:08:11.171728 [CATrainingPosCal] consider 1 rank data
796 11:08:11.175147 u2DelayCellTimex100 = 270/100 ps
797 11:08:11.178537 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
798 11:08:11.181740 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
799 11:08:11.188300 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 11:08:11.191577 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
801 11:08:11.194760 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 11:08:11.197841 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
803 11:08:11.197978
804 11:08:11.201070 CA PerBit enable=1, Macro0, CA PI delay=33
805 11:08:11.201195
806 11:08:11.204666 [CBTSetCACLKResult] CA Dly = 33
807 11:08:11.204791 CS Dly: 4 (0~35)
808 11:08:11.207964 ==
809 11:08:11.208097 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:08:11.214379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:08:11.214520 ==
812 11:08:11.218395 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:08:11.224454 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:08:11.234535 [CA 0] Center 36 (6~67) winsize 62
815 11:08:11.237645 [CA 1] Center 36 (6~67) winsize 62
816 11:08:11.240893 [CA 2] Center 34 (4~65) winsize 62
817 11:08:11.244229 [CA 3] Center 33 (3~64) winsize 62
818 11:08:11.247827 [CA 4] Center 33 (3~63) winsize 61
819 11:08:11.250822 [CA 5] Center 32 (2~63) winsize 62
820 11:08:11.250952
821 11:08:11.254382 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 11:08:11.254519
823 11:08:11.258000 [CATrainingPosCal] consider 2 rank data
824 11:08:11.261280 u2DelayCellTimex100 = 270/100 ps
825 11:08:11.264510 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
826 11:08:11.267770 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
827 11:08:11.274226 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 11:08:11.277497 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
829 11:08:11.280883 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
830 11:08:11.284260 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
831 11:08:11.284379
832 11:08:11.287469 CA PerBit enable=1, Macro0, CA PI delay=33
833 11:08:11.287545
834 11:08:11.291171 [CBTSetCACLKResult] CA Dly = 33
835 11:08:11.291248 CS Dly: 4 (0~36)
836 11:08:11.291314
837 11:08:11.294744 ----->DramcWriteLeveling(PI) begin...
838 11:08:11.294820 ==
839 11:08:11.298637 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:08:11.301981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:08:11.302060 ==
842 11:08:11.305837 Write leveling (Byte 0): 32 => 32
843 11:08:11.309607 Write leveling (Byte 1): 30 => 30
844 11:08:11.313561 DramcWriteLeveling(PI) end<-----
845 11:08:11.313673
846 11:08:11.313769 ==
847 11:08:11.316730 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:08:11.320374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:08:11.320460 ==
850 11:08:11.323350 [Gating] SW mode calibration
851 11:08:11.330844 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:08:11.334077 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:08:11.340519 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:08:11.344015 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 11:08:11.347274 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 11:08:11.353868 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:08:11.357687 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:08:11.360873 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:08:11.367253 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:08:11.370374 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:08:11.374281 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:08:11.380948 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:08:11.384209 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:08:11.387502 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:08:11.394298 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:08:11.397430 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:08:11.401024 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:08:11.407511 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:08:11.410906 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:08:11.413866 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 11:08:11.420688 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
872 11:08:11.423993 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:08:11.427430 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:08:11.434062 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:08:11.437034 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:08:11.440912 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:08:11.443892 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:08:11.450799 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:08:11.453916 0 9 8 | B1->B0 | 2323 2d2d | 1 1 | (1 1) (0 0)
880 11:08:11.457355 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
881 11:08:11.463960 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:08:11.467365 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:08:11.470650 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:08:11.477370 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:08:11.480896 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:08:11.483990 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
887 11:08:11.490778 0 10 8 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
888 11:08:11.494136 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
889 11:08:11.497573 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:08:11.504612 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:08:11.507694 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:08:11.510696 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:08:11.514145 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:08:11.521233 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
895 11:08:11.524718 0 11 8 | B1->B0 | 2e2e 3f3f | 0 1 | (0 0) (1 1)
896 11:08:11.527463 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
897 11:08:11.534877 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:08:11.537556 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:08:11.540957 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:08:11.547849 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:08:11.551225 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 11:08:11.554669 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 11:08:11.560833 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 11:08:11.564206 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:08:11.567448 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:08:11.574647 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:08:11.577994 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:08:11.581226 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:08:11.584518 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:08:11.591323 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:08:11.594295 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:08:11.597945 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:08:11.604452 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:08:11.607791 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:08:11.611214 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:08:11.618233 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:08:11.621369 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:08:11.624863 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 11:08:11.631412 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 11:08:11.631526 Total UI for P1: 0, mck2ui 16
921 11:08:11.637951 best dqsien dly found for B0: ( 0, 14, 4)
922 11:08:11.641280 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
923 11:08:11.644629 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 11:08:11.648096 Total UI for P1: 0, mck2ui 16
925 11:08:11.651536 best dqsien dly found for B1: ( 0, 14, 10)
926 11:08:11.655574 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
927 11:08:11.658870 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
928 11:08:11.658987
929 11:08:11.662444 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
930 11:08:11.665562 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
931 11:08:11.668706 [Gating] SW calibration Done
932 11:08:11.668814 ==
933 11:08:11.672250 Dram Type= 6, Freq= 0, CH_0, rank 0
934 11:08:11.675258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 11:08:11.679148 ==
936 11:08:11.679258 RX Vref Scan: 0
937 11:08:11.679364
938 11:08:11.682452 RX Vref 0 -> 0, step: 1
939 11:08:11.682571
940 11:08:11.682685 RX Delay -130 -> 252, step: 16
941 11:08:11.689103 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
942 11:08:11.692292 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
943 11:08:11.695451 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
944 11:08:11.699380 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
945 11:08:11.702571 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
946 11:08:11.709022 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
947 11:08:11.712491 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
948 11:08:11.715946 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
949 11:08:11.719216 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
950 11:08:11.722541 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
951 11:08:11.729530 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
952 11:08:11.732757 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
953 11:08:11.735963 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
954 11:08:11.739475 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
955 11:08:11.742804 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
956 11:08:11.749608 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
957 11:08:11.749697 ==
958 11:08:11.752985 Dram Type= 6, Freq= 0, CH_0, rank 0
959 11:08:11.755823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 11:08:11.755938 ==
961 11:08:11.756033 DQS Delay:
962 11:08:11.759766 DQS0 = 0, DQS1 = 0
963 11:08:11.759854 DQM Delay:
964 11:08:11.762527 DQM0 = 89, DQM1 = 82
965 11:08:11.762647 DQ Delay:
966 11:08:11.765978 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
967 11:08:11.769396 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
968 11:08:11.772704 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
969 11:08:11.776189 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
970 11:08:11.776322
971 11:08:11.776393
972 11:08:11.776462 ==
973 11:08:11.779249 Dram Type= 6, Freq= 0, CH_0, rank 0
974 11:08:11.783268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 11:08:11.783355 ==
976 11:08:11.783421
977 11:08:11.783482
978 11:08:11.786315 TX Vref Scan disable
979 11:08:11.789548 == TX Byte 0 ==
980 11:08:11.793241 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
981 11:08:11.796119 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
982 11:08:11.799532 == TX Byte 1 ==
983 11:08:11.803180 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
984 11:08:11.806124 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
985 11:08:11.806208 ==
986 11:08:11.809605 Dram Type= 6, Freq= 0, CH_0, rank 0
987 11:08:11.813268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 11:08:11.816392 ==
989 11:08:11.827385 TX Vref=22, minBit 7, minWin=27, winSum=444
990 11:08:11.831466 TX Vref=24, minBit 12, minWin=27, winSum=453
991 11:08:11.834459 TX Vref=26, minBit 0, minWin=28, winSum=455
992 11:08:11.837565 TX Vref=28, minBit 8, minWin=28, winSum=458
993 11:08:11.841211 TX Vref=30, minBit 8, minWin=28, winSum=459
994 11:08:11.844311 TX Vref=32, minBit 2, minWin=28, winSum=455
995 11:08:11.850857 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
996 11:08:11.850989
997 11:08:11.854168 Final TX Range 1 Vref 30
998 11:08:11.854280
999 11:08:11.854378 ==
1000 11:08:11.858222 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 11:08:11.861460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 11:08:11.861541 ==
1003 11:08:11.861625
1004 11:08:11.861691
1005 11:08:11.864206 TX Vref Scan disable
1006 11:08:11.868177 == TX Byte 0 ==
1007 11:08:11.871415 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1008 11:08:11.874653 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1009 11:08:11.878030 == TX Byte 1 ==
1010 11:08:11.881349 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1011 11:08:11.884594 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1012 11:08:11.884703
1013 11:08:11.887586 [DATLAT]
1014 11:08:11.887663 Freq=800, CH0 RK0
1015 11:08:11.887747
1016 11:08:11.890988 DATLAT Default: 0xa
1017 11:08:11.891068 0, 0xFFFF, sum = 0
1018 11:08:11.894375 1, 0xFFFF, sum = 0
1019 11:08:11.894460 2, 0xFFFF, sum = 0
1020 11:08:11.897659 3, 0xFFFF, sum = 0
1021 11:08:11.897739 4, 0xFFFF, sum = 0
1022 11:08:11.900965 5, 0xFFFF, sum = 0
1023 11:08:11.901041 6, 0xFFFF, sum = 0
1024 11:08:11.904125 7, 0xFFFF, sum = 0
1025 11:08:11.907799 8, 0xFFFF, sum = 0
1026 11:08:11.907880 9, 0x0, sum = 1
1027 11:08:11.907947 10, 0x0, sum = 2
1028 11:08:11.910934 11, 0x0, sum = 3
1029 11:08:11.911015 12, 0x0, sum = 4
1030 11:08:11.914530 best_step = 10
1031 11:08:11.914632
1032 11:08:11.914726 ==
1033 11:08:11.917802 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 11:08:11.920677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 11:08:11.920757 ==
1036 11:08:11.923980 RX Vref Scan: 1
1037 11:08:11.924084
1038 11:08:11.924174 Set Vref Range= 32 -> 127
1039 11:08:11.924261
1040 11:08:11.927843 RX Vref 32 -> 127, step: 1
1041 11:08:11.927923
1042 11:08:11.930907 RX Delay -95 -> 252, step: 8
1043 11:08:11.931014
1044 11:08:11.934069 Set Vref, RX VrefLevel [Byte0]: 32
1045 11:08:11.937471 [Byte1]: 32
1046 11:08:11.937578
1047 11:08:11.940867 Set Vref, RX VrefLevel [Byte0]: 33
1048 11:08:11.943923 [Byte1]: 33
1049 11:08:11.947567
1050 11:08:11.947643 Set Vref, RX VrefLevel [Byte0]: 34
1051 11:08:11.950966 [Byte1]: 34
1052 11:08:11.955521
1053 11:08:11.955605 Set Vref, RX VrefLevel [Byte0]: 35
1054 11:08:11.958501 [Byte1]: 35
1055 11:08:11.963248
1056 11:08:11.963324 Set Vref, RX VrefLevel [Byte0]: 36
1057 11:08:11.966992 [Byte1]: 36
1058 11:08:11.970414
1059 11:08:11.970496 Set Vref, RX VrefLevel [Byte0]: 37
1060 11:08:11.974333 [Byte1]: 37
1061 11:08:11.978442
1062 11:08:11.978526 Set Vref, RX VrefLevel [Byte0]: 38
1063 11:08:11.981805 [Byte1]: 38
1064 11:08:11.986514
1065 11:08:11.986595 Set Vref, RX VrefLevel [Byte0]: 39
1066 11:08:11.989288 [Byte1]: 39
1067 11:08:11.994127
1068 11:08:11.994211 Set Vref, RX VrefLevel [Byte0]: 40
1069 11:08:11.997460 [Byte1]: 40
1070 11:08:12.000829
1071 11:08:12.000910 Set Vref, RX VrefLevel [Byte0]: 41
1072 11:08:12.004211 [Byte1]: 41
1073 11:08:12.008762
1074 11:08:12.008866 Set Vref, RX VrefLevel [Byte0]: 42
1075 11:08:12.011953 [Byte1]: 42
1076 11:08:12.016595
1077 11:08:12.016677 Set Vref, RX VrefLevel [Byte0]: 43
1078 11:08:12.019708 [Byte1]: 43
1079 11:08:12.024166
1080 11:08:12.024280 Set Vref, RX VrefLevel [Byte0]: 44
1081 11:08:12.027315 [Byte1]: 44
1082 11:08:12.031593
1083 11:08:12.031700 Set Vref, RX VrefLevel [Byte0]: 45
1084 11:08:12.035017 [Byte1]: 45
1085 11:08:12.039396
1086 11:08:12.039503 Set Vref, RX VrefLevel [Byte0]: 46
1087 11:08:12.042026 [Byte1]: 46
1088 11:08:12.046496
1089 11:08:12.046573 Set Vref, RX VrefLevel [Byte0]: 47
1090 11:08:12.050042 [Byte1]: 47
1091 11:08:12.054008
1092 11:08:12.054085 Set Vref, RX VrefLevel [Byte0]: 48
1093 11:08:12.057619 [Byte1]: 48
1094 11:08:12.062308
1095 11:08:12.062379 Set Vref, RX VrefLevel [Byte0]: 49
1096 11:08:12.065308 [Byte1]: 49
1097 11:08:12.069258
1098 11:08:12.069340 Set Vref, RX VrefLevel [Byte0]: 50
1099 11:08:12.072587 [Byte1]: 50
1100 11:08:12.076928
1101 11:08:12.077017 Set Vref, RX VrefLevel [Byte0]: 51
1102 11:08:12.080237 [Byte1]: 51
1103 11:08:12.084926
1104 11:08:12.085006 Set Vref, RX VrefLevel [Byte0]: 52
1105 11:08:12.088180 [Byte1]: 52
1106 11:08:12.092245
1107 11:08:12.092355 Set Vref, RX VrefLevel [Byte0]: 53
1108 11:08:12.095727 [Byte1]: 53
1109 11:08:12.100002
1110 11:08:12.100105 Set Vref, RX VrefLevel [Byte0]: 54
1111 11:08:12.103274 [Byte1]: 54
1112 11:08:12.107258
1113 11:08:12.107350 Set Vref, RX VrefLevel [Byte0]: 55
1114 11:08:12.110496 [Byte1]: 55
1115 11:08:12.115064
1116 11:08:12.115141 Set Vref, RX VrefLevel [Byte0]: 56
1117 11:08:12.118446 [Byte1]: 56
1118 11:08:12.122652
1119 11:08:12.122735 Set Vref, RX VrefLevel [Byte0]: 57
1120 11:08:12.125928 [Byte1]: 57
1121 11:08:12.130255
1122 11:08:12.130364 Set Vref, RX VrefLevel [Byte0]: 58
1123 11:08:12.133773 [Byte1]: 58
1124 11:08:12.137743
1125 11:08:12.137846 Set Vref, RX VrefLevel [Byte0]: 59
1126 11:08:12.140943 [Byte1]: 59
1127 11:08:12.145308
1128 11:08:12.145417 Set Vref, RX VrefLevel [Byte0]: 60
1129 11:08:12.148462 [Byte1]: 60
1130 11:08:12.153180
1131 11:08:12.153292 Set Vref, RX VrefLevel [Byte0]: 61
1132 11:08:12.156364 [Byte1]: 61
1133 11:08:12.160533
1134 11:08:12.160614 Set Vref, RX VrefLevel [Byte0]: 62
1135 11:08:12.163694 [Byte1]: 62
1136 11:08:12.168356
1137 11:08:12.168446 Set Vref, RX VrefLevel [Byte0]: 63
1138 11:08:12.171613 [Byte1]: 63
1139 11:08:12.176106
1140 11:08:12.176220 Set Vref, RX VrefLevel [Byte0]: 64
1141 11:08:12.179118 [Byte1]: 64
1142 11:08:12.183393
1143 11:08:12.183502 Set Vref, RX VrefLevel [Byte0]: 65
1144 11:08:12.186860 [Byte1]: 65
1145 11:08:12.190939
1146 11:08:12.191056 Set Vref, RX VrefLevel [Byte0]: 66
1147 11:08:12.194197 [Byte1]: 66
1148 11:08:12.198916
1149 11:08:12.198998 Set Vref, RX VrefLevel [Byte0]: 67
1150 11:08:12.202261 [Byte1]: 67
1151 11:08:12.206042
1152 11:08:12.206172 Set Vref, RX VrefLevel [Byte0]: 68
1153 11:08:12.209229 [Byte1]: 68
1154 11:08:12.214003
1155 11:08:12.214119 Set Vref, RX VrefLevel [Byte0]: 69
1156 11:08:12.217134 [Byte1]: 69
1157 11:08:12.221155
1158 11:08:12.221239 Set Vref, RX VrefLevel [Byte0]: 70
1159 11:08:12.224466 [Byte1]: 70
1160 11:08:12.228633
1161 11:08:12.228740 Set Vref, RX VrefLevel [Byte0]: 71
1162 11:08:12.232606 [Byte1]: 71
1163 11:08:12.236819
1164 11:08:12.236915 Set Vref, RX VrefLevel [Byte0]: 72
1165 11:08:12.240142 [Byte1]: 72
1166 11:08:12.244211
1167 11:08:12.244335 Set Vref, RX VrefLevel [Byte0]: 73
1168 11:08:12.247381 [Byte1]: 73
1169 11:08:12.251789
1170 11:08:12.251905 Set Vref, RX VrefLevel [Byte0]: 74
1171 11:08:12.255176 [Byte1]: 74
1172 11:08:12.259080
1173 11:08:12.259208 Set Vref, RX VrefLevel [Byte0]: 75
1174 11:08:12.263119 [Byte1]: 75
1175 11:08:12.266825
1176 11:08:12.266950 Set Vref, RX VrefLevel [Byte0]: 76
1177 11:08:12.270042 [Byte1]: 76
1178 11:08:12.274723
1179 11:08:12.274816 Set Vref, RX VrefLevel [Byte0]: 77
1180 11:08:12.278378 [Byte1]: 77
1181 11:08:12.282103
1182 11:08:12.282215 Set Vref, RX VrefLevel [Byte0]: 78
1183 11:08:12.285669 [Byte1]: 78
1184 11:08:12.289711
1185 11:08:12.289823 Final RX Vref Byte 0 = 56 to rank0
1186 11:08:12.293101 Final RX Vref Byte 1 = 57 to rank0
1187 11:08:12.296302 Final RX Vref Byte 0 = 56 to rank1
1188 11:08:12.299919 Final RX Vref Byte 1 = 57 to rank1==
1189 11:08:12.302774 Dram Type= 6, Freq= 0, CH_0, rank 0
1190 11:08:12.309970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1191 11:08:12.310110 ==
1192 11:08:12.310227 DQS Delay:
1193 11:08:12.310341 DQS0 = 0, DQS1 = 0
1194 11:08:12.313163 DQM Delay:
1195 11:08:12.313248 DQM0 = 92, DQM1 = 85
1196 11:08:12.316360 DQ Delay:
1197 11:08:12.319667 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1198 11:08:12.322863 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1199 11:08:12.326233 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
1200 11:08:12.329706 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1201 11:08:12.329788
1202 11:08:12.329853
1203 11:08:12.336361 [DQSOSCAuto] RK0, (LSB)MR18= 0x4940, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1204 11:08:12.339648 CH0 RK0: MR19=606, MR18=4940
1205 11:08:12.346671 CH0_RK0: MR19=0x606, MR18=0x4940, DQSOSC=391, MR23=63, INC=96, DEC=64
1206 11:08:12.346755
1207 11:08:12.350252 ----->DramcWriteLeveling(PI) begin...
1208 11:08:12.350363 ==
1209 11:08:12.353614 Dram Type= 6, Freq= 0, CH_0, rank 1
1210 11:08:12.356948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1211 11:08:12.357058 ==
1212 11:08:12.360163 Write leveling (Byte 0): 33 => 33
1213 11:08:12.363199 Write leveling (Byte 1): 29 => 29
1214 11:08:12.366833 DramcWriteLeveling(PI) end<-----
1215 11:08:12.366943
1216 11:08:12.367036 ==
1217 11:08:12.370231 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 11:08:12.413855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1219 11:08:12.413990 ==
1220 11:08:12.414099 [Gating] SW mode calibration
1221 11:08:12.414783 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1222 11:08:12.414871 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1223 11:08:12.414947 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1224 11:08:12.415063 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1225 11:08:12.415155 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1226 11:08:12.415244 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:08:12.415745 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:08:12.415841 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:08:12.458253 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:08:12.458598 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:08:12.458706 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:08:12.458816 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:08:12.458908 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:08:12.459010 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:08:12.459108 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:08:12.459584 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:08:12.459910 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:08:12.460012 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:08:12.469860 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:08:12.469947 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1241 11:08:12.472504 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1242 11:08:12.476186 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:08:12.482454 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:08:12.485981 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:08:12.489177 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 11:08:12.495672 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 11:08:12.498997 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 11:08:12.502946 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 11:08:12.509363 0 9 8 | B1->B0 | 2d2d 2727 | 0 0 | (0 0) (0 0)
1250 11:08:12.512651 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 11:08:12.516013 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 11:08:12.519336 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 11:08:12.525785 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 11:08:12.529450 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 11:08:12.532318 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 11:08:12.539194 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1257 11:08:12.542903 0 10 8 | B1->B0 | 2525 2c2c | 0 0 | (1 0) (0 1)
1258 11:08:12.546445 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 11:08:12.550381 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 11:08:12.554716 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 11:08:12.561996 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 11:08:12.565209 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 11:08:12.568683 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 11:08:12.572226 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1265 11:08:12.579286 0 11 8 | B1->B0 | 3e3e 3c3c | 0 0 | (0 0) (0 0)
1266 11:08:12.582183 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 11:08:12.585357 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 11:08:12.592459 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 11:08:12.595656 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 11:08:12.599403 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 11:08:12.605902 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 11:08:12.609239 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 11:08:12.612418 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1274 11:08:12.615732 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1275 11:08:12.622250 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:08:12.625577 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:08:12.628909 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:08:12.635733 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:08:12.639192 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:08:12.642406 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:08:12.649139 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 11:08:12.652111 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 11:08:12.655652 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 11:08:12.662154 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 11:08:12.665629 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 11:08:12.668907 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 11:08:12.675509 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 11:08:12.678806 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1289 11:08:12.682708 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1290 11:08:12.685923 Total UI for P1: 0, mck2ui 16
1291 11:08:12.688998 best dqsien dly found for B1: ( 0, 14, 4)
1292 11:08:12.695585 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1293 11:08:12.695714 Total UI for P1: 0, mck2ui 16
1294 11:08:12.698841 best dqsien dly found for B0: ( 0, 14, 6)
1295 11:08:12.705635 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1296 11:08:12.708830 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1297 11:08:12.708957
1298 11:08:12.711998 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1299 11:08:12.715202 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1300 11:08:12.719200 [Gating] SW calibration Done
1301 11:08:12.719288 ==
1302 11:08:12.722308 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 11:08:12.725266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 11:08:12.725350 ==
1305 11:08:12.728586 RX Vref Scan: 0
1306 11:08:12.728691
1307 11:08:12.728788 RX Vref 0 -> 0, step: 1
1308 11:08:12.728876
1309 11:08:12.732432 RX Delay -130 -> 252, step: 16
1310 11:08:12.735232 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1311 11:08:12.742523 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1312 11:08:12.745335 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1313 11:08:12.749339 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1314 11:08:12.752687 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1315 11:08:12.755387 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1316 11:08:12.758908 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1317 11:08:12.765828 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1318 11:08:12.768814 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1319 11:08:12.772205 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1320 11:08:12.775669 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1321 11:08:12.779068 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1322 11:08:12.785919 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1323 11:08:12.788770 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1324 11:08:12.792659 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1325 11:08:12.795724 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1326 11:08:12.795807 ==
1327 11:08:12.799298 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 11:08:12.805806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 11:08:12.805890 ==
1330 11:08:12.805955 DQS Delay:
1331 11:08:12.809082 DQS0 = 0, DQS1 = 0
1332 11:08:12.809165 DQM Delay:
1333 11:08:12.809231 DQM0 = 93, DQM1 = 84
1334 11:08:12.812310 DQ Delay:
1335 11:08:12.815519 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1336 11:08:12.818891 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1337 11:08:12.822688 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1338 11:08:12.825859 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1339 11:08:12.825969
1340 11:08:12.826063
1341 11:08:12.826153 ==
1342 11:08:12.829060 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 11:08:12.832421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 11:08:12.832520 ==
1345 11:08:12.832609
1346 11:08:12.832695
1347 11:08:12.835658 TX Vref Scan disable
1348 11:08:12.835741 == TX Byte 0 ==
1349 11:08:12.842331 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1350 11:08:12.845652 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1351 11:08:12.845736 == TX Byte 1 ==
1352 11:08:12.852326 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1353 11:08:12.855583 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1354 11:08:12.855667 ==
1355 11:08:12.858859 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 11:08:12.862233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 11:08:12.862317 ==
1358 11:08:12.877076 TX Vref=22, minBit 8, minWin=27, winSum=446
1359 11:08:12.880276 TX Vref=24, minBit 11, minWin=27, winSum=448
1360 11:08:12.883226 TX Vref=26, minBit 12, minWin=27, winSum=453
1361 11:08:12.886915 TX Vref=28, minBit 2, minWin=28, winSum=454
1362 11:08:12.889965 TX Vref=30, minBit 2, minWin=28, winSum=461
1363 11:08:12.896637 TX Vref=32, minBit 2, minWin=28, winSum=455
1364 11:08:12.900091 [TxChooseVref] Worse bit 2, Min win 28, Win sum 461, Final Vref 30
1365 11:08:12.900170
1366 11:08:12.903650 Final TX Range 1 Vref 30
1367 11:08:12.903735
1368 11:08:12.903798 ==
1369 11:08:12.906610 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 11:08:12.910171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 11:08:12.910245 ==
1372 11:08:12.910304
1373 11:08:12.913324
1374 11:08:12.913407 TX Vref Scan disable
1375 11:08:12.916653 == TX Byte 0 ==
1376 11:08:12.920332 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1377 11:08:12.923603 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1378 11:08:12.926837 == TX Byte 1 ==
1379 11:08:12.930486 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1380 11:08:12.933461 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1381 11:08:12.936925
1382 11:08:12.937046 [DATLAT]
1383 11:08:12.937161 Freq=800, CH0 RK1
1384 11:08:12.937271
1385 11:08:12.940011 DATLAT Default: 0xa
1386 11:08:12.940133 0, 0xFFFF, sum = 0
1387 11:08:12.943901 1, 0xFFFF, sum = 0
1388 11:08:12.944026 2, 0xFFFF, sum = 0
1389 11:08:12.947163 3, 0xFFFF, sum = 0
1390 11:08:12.947286 4, 0xFFFF, sum = 0
1391 11:08:12.950492 5, 0xFFFF, sum = 0
1392 11:08:12.950613 6, 0xFFFF, sum = 0
1393 11:08:12.953829 7, 0xFFFF, sum = 0
1394 11:08:12.953955 8, 0xFFFF, sum = 0
1395 11:08:12.957142 9, 0x0, sum = 1
1396 11:08:12.957267 10, 0x0, sum = 2
1397 11:08:12.960375 11, 0x0, sum = 3
1398 11:08:12.960499 12, 0x0, sum = 4
1399 11:08:12.963508 best_step = 10
1400 11:08:12.963625
1401 11:08:12.963732 ==
1402 11:08:12.966865 Dram Type= 6, Freq= 0, CH_0, rank 1
1403 11:08:12.970767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 11:08:12.970885 ==
1405 11:08:12.973985 RX Vref Scan: 0
1406 11:08:12.974106
1407 11:08:12.974216 RX Vref 0 -> 0, step: 1
1408 11:08:12.974321
1409 11:08:12.977248 RX Delay -95 -> 252, step: 8
1410 11:08:12.983949 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1411 11:08:12.987139 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1412 11:08:12.990272 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1413 11:08:12.993624 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1414 11:08:12.997237 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1415 11:08:13.003730 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1416 11:08:13.006944 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1417 11:08:13.010666 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1418 11:08:13.013556 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1419 11:08:13.017394 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1420 11:08:13.023898 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1421 11:08:13.027253 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1422 11:08:13.030333 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1423 11:08:13.034069 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1424 11:08:13.037162 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1425 11:08:13.044146 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1426 11:08:13.044267 ==
1427 11:08:13.047141 Dram Type= 6, Freq= 0, CH_0, rank 1
1428 11:08:13.050649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 11:08:13.050772 ==
1430 11:08:13.050878 DQS Delay:
1431 11:08:13.053654 DQS0 = 0, DQS1 = 0
1432 11:08:13.053772 DQM Delay:
1433 11:08:13.056873 DQM0 = 92, DQM1 = 83
1434 11:08:13.056993 DQ Delay:
1435 11:08:13.060238 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =88
1436 11:08:13.064307 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1437 11:08:13.066926 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1438 11:08:13.070317 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88
1439 11:08:13.070434
1440 11:08:13.070547
1441 11:08:13.077449 [DQSOSCAuto] RK1, (LSB)MR18= 0x4515, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1442 11:08:13.080812 CH0 RK1: MR19=606, MR18=4515
1443 11:08:13.086863 CH0_RK1: MR19=0x606, MR18=0x4515, DQSOSC=392, MR23=63, INC=96, DEC=64
1444 11:08:13.090820 [RxdqsGatingPostProcess] freq 800
1445 11:08:13.097139 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1446 11:08:13.100418 Pre-setting of DQS Precalculation
1447 11:08:13.104040 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1448 11:08:13.104123 ==
1449 11:08:13.107315 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 11:08:13.110794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 11:08:13.110877 ==
1452 11:08:13.117177 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1453 11:08:13.123709 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1454 11:08:13.132517 [CA 0] Center 36 (6~67) winsize 62
1455 11:08:13.135626 [CA 1] Center 36 (6~67) winsize 62
1456 11:08:13.138671 [CA 2] Center 34 (4~65) winsize 62
1457 11:08:13.142043 [CA 3] Center 34 (4~65) winsize 62
1458 11:08:13.145320 [CA 4] Center 35 (5~65) winsize 61
1459 11:08:13.148899 [CA 5] Center 34 (4~64) winsize 61
1460 11:08:13.148983
1461 11:08:13.152042 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1462 11:08:13.152122
1463 11:08:13.155561 [CATrainingPosCal] consider 1 rank data
1464 11:08:13.158772 u2DelayCellTimex100 = 270/100 ps
1465 11:08:13.162224 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1466 11:08:13.165835 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1467 11:08:13.172120 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1468 11:08:13.175503 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1469 11:08:13.178770 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1470 11:08:13.181849 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1471 11:08:13.181929
1472 11:08:13.185190 CA PerBit enable=1, Macro0, CA PI delay=34
1473 11:08:13.185270
1474 11:08:13.189174 [CBTSetCACLKResult] CA Dly = 34
1475 11:08:13.189245 CS Dly: 5 (0~36)
1476 11:08:13.189307 ==
1477 11:08:13.192368 Dram Type= 6, Freq= 0, CH_1, rank 1
1478 11:08:13.198902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1479 11:08:13.199017 ==
1480 11:08:13.202061 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1481 11:08:13.209159 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1482 11:08:13.218276 [CA 0] Center 36 (6~67) winsize 62
1483 11:08:13.222280 [CA 1] Center 36 (6~67) winsize 62
1484 11:08:13.225900 [CA 2] Center 35 (4~66) winsize 63
1485 11:08:13.229609 [CA 3] Center 34 (4~65) winsize 62
1486 11:08:13.233634 [CA 4] Center 35 (5~66) winsize 62
1487 11:08:13.233764 [CA 5] Center 34 (4~65) winsize 62
1488 11:08:13.236905
1489 11:08:13.240927 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1490 11:08:13.241045
1491 11:08:13.241157 [CATrainingPosCal] consider 2 rank data
1492 11:08:13.244221 u2DelayCellTimex100 = 270/100 ps
1493 11:08:13.247605 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1494 11:08:13.254170 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1495 11:08:13.257743 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1496 11:08:13.261224 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1497 11:08:13.264702 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1498 11:08:13.267899 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1499 11:08:13.268020
1500 11:08:13.271615 CA PerBit enable=1, Macro0, CA PI delay=34
1501 11:08:13.271739
1502 11:08:13.274626 [CBTSetCACLKResult] CA Dly = 34
1503 11:08:13.274748 CS Dly: 6 (0~39)
1504 11:08:13.274860
1505 11:08:13.278020 ----->DramcWriteLeveling(PI) begin...
1506 11:08:13.281392 ==
1507 11:08:13.284931 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 11:08:13.288211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1509 11:08:13.288320 ==
1510 11:08:13.291624 Write leveling (Byte 0): 29 => 29
1511 11:08:13.294967 Write leveling (Byte 1): 27 => 27
1512 11:08:13.298356 DramcWriteLeveling(PI) end<-----
1513 11:08:13.298439
1514 11:08:13.298504 ==
1515 11:08:13.301574 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 11:08:13.304825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1517 11:08:13.304908 ==
1518 11:08:13.307985 [Gating] SW mode calibration
1519 11:08:13.314510 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1520 11:08:13.318371 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1521 11:08:13.325053 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1522 11:08:13.328386 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1523 11:08:13.331623 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:08:13.338585 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:08:13.341301 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:08:13.345267 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:08:13.351872 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:08:13.354568 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:08:13.357869 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:08:13.365085 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:08:13.367969 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:08:13.371269 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:08:13.378328 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:08:13.381688 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:08:13.384753 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:08:13.388453 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:08:13.395148 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:08:13.398509 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1539 11:08:13.401463 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:08:13.408464 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:08:13.411550 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:08:13.414884 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 11:08:13.421872 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 11:08:13.424978 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 11:08:13.428196 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 11:08:13.434863 0 9 4 | B1->B0 | 2424 2626 | 0 1 | (0 0) (1 1)
1547 11:08:13.438092 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1548 11:08:13.441837 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 11:08:13.448332 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 11:08:13.451659 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 11:08:13.454944 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 11:08:13.461716 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 11:08:13.464838 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 11:08:13.468419 0 10 4 | B1->B0 | 3232 2d2d | 0 0 | (0 1) (0 0)
1555 11:08:13.475180 0 10 8 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
1556 11:08:13.478570 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 11:08:13.481567 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 11:08:13.485212 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 11:08:13.491421 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 11:08:13.495122 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 11:08:13.498396 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 11:08:13.505527 0 11 4 | B1->B0 | 2c2c 3838 | 0 0 | (0 0) (1 1)
1563 11:08:13.508608 0 11 8 | B1->B0 | 3f3e 4646 | 1 0 | (0 0) (0 0)
1564 11:08:13.511785 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 11:08:13.518252 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 11:08:13.521857 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 11:08:13.524840 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 11:08:13.531576 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 11:08:13.535155 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 11:08:13.538618 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1571 11:08:13.544901 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:08:13.548589 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:08:13.551815 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:08:13.558574 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:08:13.561818 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:08:13.565175 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:08:13.568582 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:08:13.575258 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:08:13.578463 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:08:13.581670 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 11:08:13.588636 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 11:08:13.591737 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 11:08:13.595021 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 11:08:13.602326 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 11:08:13.605197 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1586 11:08:13.608468 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1587 11:08:13.615170 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1588 11:08:13.615255 Total UI for P1: 0, mck2ui 16
1589 11:08:13.621978 best dqsien dly found for B1: ( 0, 14, 2)
1590 11:08:13.625315 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1591 11:08:13.628696 Total UI for P1: 0, mck2ui 16
1592 11:08:13.632048 best dqsien dly found for B0: ( 0, 14, 6)
1593 11:08:13.635350 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1594 11:08:13.638890 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1595 11:08:13.638973
1596 11:08:13.641828 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1597 11:08:13.645450 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1598 11:08:13.648885 [Gating] SW calibration Done
1599 11:08:13.648968 ==
1600 11:08:13.652268 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 11:08:13.655173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 11:08:13.655257 ==
1603 11:08:13.658948 RX Vref Scan: 0
1604 11:08:13.659030
1605 11:08:13.659096 RX Vref 0 -> 0, step: 1
1606 11:08:13.662143
1607 11:08:13.662225 RX Delay -130 -> 252, step: 16
1608 11:08:13.668427 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1609 11:08:13.671811 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1610 11:08:13.675176 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1611 11:08:13.678566 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1612 11:08:13.681928 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1613 11:08:13.688404 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1614 11:08:13.692305 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1615 11:08:13.695395 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1616 11:08:13.698920 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1617 11:08:13.701858 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1618 11:08:13.705701 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1619 11:08:13.711903 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1620 11:08:13.715446 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1621 11:08:13.718703 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1622 11:08:13.722030 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1623 11:08:13.728959 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1624 11:08:13.729044 ==
1625 11:08:13.732189 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 11:08:13.735438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 11:08:13.735522 ==
1628 11:08:13.735598 DQS Delay:
1629 11:08:13.738834 DQS0 = 0, DQS1 = 0
1630 11:08:13.738918 DQM Delay:
1631 11:08:13.742055 DQM0 = 94, DQM1 = 89
1632 11:08:13.742138 DQ Delay:
1633 11:08:13.745372 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1634 11:08:13.748658 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1635 11:08:13.752569 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1636 11:08:13.755803 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1637 11:08:13.755911
1638 11:08:13.756009
1639 11:08:13.756099 ==
1640 11:08:13.759061 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 11:08:13.762456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 11:08:13.762562 ==
1643 11:08:13.762669
1644 11:08:13.762768
1645 11:08:13.765768 TX Vref Scan disable
1646 11:08:13.768873 == TX Byte 0 ==
1647 11:08:13.772511 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1648 11:08:13.775415 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1649 11:08:13.778785 == TX Byte 1 ==
1650 11:08:13.781937 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1651 11:08:13.786201 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1652 11:08:13.786308 ==
1653 11:08:13.789473 Dram Type= 6, Freq= 0, CH_1, rank 0
1654 11:08:13.793310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1655 11:08:13.793417 ==
1656 11:08:13.807376 TX Vref=22, minBit 0, minWin=27, winSum=439
1657 11:08:13.810404 TX Vref=24, minBit 4, minWin=26, winSum=442
1658 11:08:13.814097 TX Vref=26, minBit 1, minWin=27, winSum=448
1659 11:08:13.817236 TX Vref=28, minBit 1, minWin=27, winSum=448
1660 11:08:13.820301 TX Vref=30, minBit 1, minWin=27, winSum=454
1661 11:08:13.823581 TX Vref=32, minBit 1, minWin=27, winSum=447
1662 11:08:13.830367 [TxChooseVref] Worse bit 1, Min win 27, Win sum 454, Final Vref 30
1663 11:08:13.830477
1664 11:08:13.833512 Final TX Range 1 Vref 30
1665 11:08:13.833596
1666 11:08:13.833661 ==
1667 11:08:13.837234 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 11:08:13.840629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1669 11:08:13.840713 ==
1670 11:08:13.840778
1671 11:08:13.843938
1672 11:08:13.844020 TX Vref Scan disable
1673 11:08:13.847127 == TX Byte 0 ==
1674 11:08:13.850306 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1675 11:08:13.853571 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1676 11:08:13.856884 == TX Byte 1 ==
1677 11:08:13.860229 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1678 11:08:13.863877 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1679 11:08:13.867297
1680 11:08:13.867376 [DATLAT]
1681 11:08:13.867440 Freq=800, CH1 RK0
1682 11:08:13.867499
1683 11:08:13.870624 DATLAT Default: 0xa
1684 11:08:13.870728 0, 0xFFFF, sum = 0
1685 11:08:13.873979 1, 0xFFFF, sum = 0
1686 11:08:13.874085 2, 0xFFFF, sum = 0
1687 11:08:13.877394 3, 0xFFFF, sum = 0
1688 11:08:13.877498 4, 0xFFFF, sum = 0
1689 11:08:13.880663 5, 0xFFFF, sum = 0
1690 11:08:13.880767 6, 0xFFFF, sum = 0
1691 11:08:13.884511 7, 0xFFFF, sum = 0
1692 11:08:13.884617 8, 0xFFFF, sum = 0
1693 11:08:13.887559 9, 0x0, sum = 1
1694 11:08:13.887659 10, 0x0, sum = 2
1695 11:08:13.891072 11, 0x0, sum = 3
1696 11:08:13.891179 12, 0x0, sum = 4
1697 11:08:13.894032 best_step = 10
1698 11:08:13.894117
1699 11:08:13.894183 ==
1700 11:08:13.897546 Dram Type= 6, Freq= 0, CH_1, rank 0
1701 11:08:13.901000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1702 11:08:13.901080 ==
1703 11:08:13.904263 RX Vref Scan: 1
1704 11:08:13.904350
1705 11:08:13.904413 Set Vref Range= 32 -> 127
1706 11:08:13.904473
1707 11:08:13.907434 RX Vref 32 -> 127, step: 1
1708 11:08:13.907517
1709 11:08:13.910833 RX Delay -63 -> 252, step: 8
1710 11:08:13.910917
1711 11:08:13.914525 Set Vref, RX VrefLevel [Byte0]: 32
1712 11:08:13.917338 [Byte1]: 32
1713 11:08:13.917422
1714 11:08:13.921059 Set Vref, RX VrefLevel [Byte0]: 33
1715 11:08:13.924152 [Byte1]: 33
1716 11:08:13.924261
1717 11:08:13.927707 Set Vref, RX VrefLevel [Byte0]: 34
1718 11:08:13.931085 [Byte1]: 34
1719 11:08:13.935150
1720 11:08:13.935232 Set Vref, RX VrefLevel [Byte0]: 35
1721 11:08:13.938299 [Byte1]: 35
1722 11:08:13.942219
1723 11:08:13.942302 Set Vref, RX VrefLevel [Byte0]: 36
1724 11:08:13.945451 [Byte1]: 36
1725 11:08:13.949432
1726 11:08:13.949515 Set Vref, RX VrefLevel [Byte0]: 37
1727 11:08:13.953293 [Byte1]: 37
1728 11:08:13.957321
1729 11:08:13.957404 Set Vref, RX VrefLevel [Byte0]: 38
1730 11:08:13.960533 [Byte1]: 38
1731 11:08:13.964488
1732 11:08:13.964570 Set Vref, RX VrefLevel [Byte0]: 39
1733 11:08:13.968259 [Byte1]: 39
1734 11:08:13.971983
1735 11:08:13.972091 Set Vref, RX VrefLevel [Byte0]: 40
1736 11:08:13.975306 [Byte1]: 40
1737 11:08:13.979384
1738 11:08:13.979466 Set Vref, RX VrefLevel [Byte0]: 41
1739 11:08:13.982698 [Byte1]: 41
1740 11:08:13.987452
1741 11:08:13.987534 Set Vref, RX VrefLevel [Byte0]: 42
1742 11:08:13.990674 [Byte1]: 42
1743 11:08:13.994547
1744 11:08:13.994629 Set Vref, RX VrefLevel [Byte0]: 43
1745 11:08:13.997750 [Byte1]: 43
1746 11:08:14.002171
1747 11:08:14.002282 Set Vref, RX VrefLevel [Byte0]: 44
1748 11:08:14.005329 [Byte1]: 44
1749 11:08:14.009844
1750 11:08:14.009947 Set Vref, RX VrefLevel [Byte0]: 45
1751 11:08:14.012994 [Byte1]: 45
1752 11:08:14.017279
1753 11:08:14.017362 Set Vref, RX VrefLevel [Byte0]: 46
1754 11:08:14.020211 [Byte1]: 46
1755 11:08:14.024449
1756 11:08:14.024531 Set Vref, RX VrefLevel [Byte0]: 47
1757 11:08:14.028050 [Byte1]: 47
1758 11:08:14.032259
1759 11:08:14.032352 Set Vref, RX VrefLevel [Byte0]: 48
1760 11:08:14.035497 [Byte1]: 48
1761 11:08:14.039869
1762 11:08:14.039975 Set Vref, RX VrefLevel [Byte0]: 49
1763 11:08:14.043075 [Byte1]: 49
1764 11:08:14.047296
1765 11:08:14.047403 Set Vref, RX VrefLevel [Byte0]: 50
1766 11:08:14.050763 [Byte1]: 50
1767 11:08:14.054846
1768 11:08:14.054950 Set Vref, RX VrefLevel [Byte0]: 51
1769 11:08:14.057905 [Byte1]: 51
1770 11:08:14.062501
1771 11:08:14.062582 Set Vref, RX VrefLevel [Byte0]: 52
1772 11:08:14.065767 [Byte1]: 52
1773 11:08:14.069741
1774 11:08:14.069822 Set Vref, RX VrefLevel [Byte0]: 53
1775 11:08:14.072924 [Byte1]: 53
1776 11:08:14.077427
1777 11:08:14.077510 Set Vref, RX VrefLevel [Byte0]: 54
1778 11:08:14.080709 [Byte1]: 54
1779 11:08:14.084768
1780 11:08:14.084842 Set Vref, RX VrefLevel [Byte0]: 55
1781 11:08:14.088051 [Byte1]: 55
1782 11:08:14.092156
1783 11:08:14.092260 Set Vref, RX VrefLevel [Byte0]: 56
1784 11:08:14.095642 [Byte1]: 56
1785 11:08:14.099723
1786 11:08:14.099804 Set Vref, RX VrefLevel [Byte0]: 57
1787 11:08:14.102896 [Byte1]: 57
1788 11:08:14.107273
1789 11:08:14.107373 Set Vref, RX VrefLevel [Byte0]: 58
1790 11:08:14.110272 [Byte1]: 58
1791 11:08:14.114877
1792 11:08:14.114975 Set Vref, RX VrefLevel [Byte0]: 59
1793 11:08:14.118157 [Byte1]: 59
1794 11:08:14.122145
1795 11:08:14.122228 Set Vref, RX VrefLevel [Byte0]: 60
1796 11:08:14.125575 [Byte1]: 60
1797 11:08:14.129474
1798 11:08:14.129574 Set Vref, RX VrefLevel [Byte0]: 61
1799 11:08:14.132880 [Byte1]: 61
1800 11:08:14.137375
1801 11:08:14.137474 Set Vref, RX VrefLevel [Byte0]: 62
1802 11:08:14.140328 [Byte1]: 62
1803 11:08:14.144531
1804 11:08:14.144615 Set Vref, RX VrefLevel [Byte0]: 63
1805 11:08:14.147917 [Byte1]: 63
1806 11:08:14.152182
1807 11:08:14.152302 Set Vref, RX VrefLevel [Byte0]: 64
1808 11:08:14.155343 [Byte1]: 64
1809 11:08:14.159712
1810 11:08:14.159818 Set Vref, RX VrefLevel [Byte0]: 65
1811 11:08:14.163080 [Byte1]: 65
1812 11:08:14.166922
1813 11:08:14.167028 Set Vref, RX VrefLevel [Byte0]: 66
1814 11:08:14.170378 [Byte1]: 66
1815 11:08:14.174573
1816 11:08:14.174676 Set Vref, RX VrefLevel [Byte0]: 67
1817 11:08:14.178196 [Byte1]: 67
1818 11:08:14.181894
1819 11:08:14.181973 Set Vref, RX VrefLevel [Byte0]: 68
1820 11:08:14.185220 [Byte1]: 68
1821 11:08:14.189727
1822 11:08:14.189812 Set Vref, RX VrefLevel [Byte0]: 69
1823 11:08:14.193041 [Byte1]: 69
1824 11:08:14.197019
1825 11:08:14.197131 Set Vref, RX VrefLevel [Byte0]: 70
1826 11:08:14.200283 [Byte1]: 70
1827 11:08:14.204901
1828 11:08:14.204978 Set Vref, RX VrefLevel [Byte0]: 71
1829 11:08:14.208255 [Byte1]: 71
1830 11:08:14.212168
1831 11:08:14.212271 Set Vref, RX VrefLevel [Byte0]: 72
1832 11:08:14.215396 [Byte1]: 72
1833 11:08:14.219900
1834 11:08:14.220002 Final RX Vref Byte 0 = 61 to rank0
1835 11:08:14.222647 Final RX Vref Byte 1 = 57 to rank0
1836 11:08:14.226650 Final RX Vref Byte 0 = 61 to rank1
1837 11:08:14.229296 Final RX Vref Byte 1 = 57 to rank1==
1838 11:08:14.233045 Dram Type= 6, Freq= 0, CH_1, rank 0
1839 11:08:14.239652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1840 11:08:14.239755 ==
1841 11:08:14.239855 DQS Delay:
1842 11:08:14.239949 DQS0 = 0, DQS1 = 0
1843 11:08:14.242919 DQM Delay:
1844 11:08:14.243019 DQM0 = 95, DQM1 = 90
1845 11:08:14.246111 DQ Delay:
1846 11:08:14.250002 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1847 11:08:14.253241 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1848 11:08:14.256407 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1849 11:08:14.259569 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =100
1850 11:08:14.259644
1851 11:08:14.259708
1852 11:08:14.266086 [DQSOSCAuto] RK0, (LSB)MR18= 0x314e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1853 11:08:14.269918 CH1 RK0: MR19=606, MR18=314E
1854 11:08:14.276532 CH1_RK0: MR19=0x606, MR18=0x314E, DQSOSC=390, MR23=63, INC=97, DEC=64
1855 11:08:14.276644
1856 11:08:14.279495 ----->DramcWriteLeveling(PI) begin...
1857 11:08:14.279602 ==
1858 11:08:14.282818 Dram Type= 6, Freq= 0, CH_1, rank 1
1859 11:08:14.286509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1860 11:08:14.286618 ==
1861 11:08:14.289476 Write leveling (Byte 0): 27 => 27
1862 11:08:14.293011 Write leveling (Byte 1): 27 => 27
1863 11:08:14.296489 DramcWriteLeveling(PI) end<-----
1864 11:08:14.296580
1865 11:08:14.296674 ==
1866 11:08:14.299829 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 11:08:14.303191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1868 11:08:14.303318 ==
1869 11:08:14.306509 [Gating] SW mode calibration
1870 11:08:14.313017 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1871 11:08:14.319600 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1872 11:08:14.322824 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1873 11:08:14.326154 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 11:08:14.332824 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 11:08:14.336652 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:08:14.339975 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:08:14.346546 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 11:08:14.349833 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:08:14.353457 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:08:14.359879 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:08:14.363556 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:08:14.366903 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:08:14.370317 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:08:14.376897 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:08:14.380036 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 11:08:14.383388 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:08:14.390300 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:08:14.393256 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1889 11:08:14.396991 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:08:14.403587 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:08:14.406502 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:08:14.409651 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:08:14.416469 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:08:14.419826 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:08:14.423164 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:08:14.430222 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:08:14.433656 0 9 4 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (0 0)
1898 11:08:14.437028 0 9 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
1899 11:08:14.443494 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 11:08:14.446909 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 11:08:14.450239 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 11:08:14.456811 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 11:08:14.459979 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 11:08:14.463316 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1905 11:08:14.466436 0 10 4 | B1->B0 | 2929 2e2e | 0 1 | (0 0) (1 0)
1906 11:08:14.473340 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:08:14.476717 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:08:14.480086 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 11:08:14.486715 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 11:08:14.490137 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 11:08:14.493491 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 11:08:14.500430 0 11 0 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
1913 11:08:14.503377 0 11 4 | B1->B0 | 3636 2727 | 0 0 | (1 1) (0 0)
1914 11:08:14.506814 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1915 11:08:14.513879 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 11:08:14.517231 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 11:08:14.520658 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 11:08:14.526840 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 11:08:14.529967 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 11:08:14.533815 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 11:08:14.540202 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1922 11:08:14.543603 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 11:08:14.546957 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 11:08:14.550279 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 11:08:14.556825 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 11:08:14.560199 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 11:08:14.563849 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 11:08:14.570345 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 11:08:14.573537 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 11:08:14.577050 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 11:08:14.583603 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 11:08:14.586841 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 11:08:14.590144 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 11:08:14.596891 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 11:08:14.600325 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 11:08:14.603691 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 11:08:14.610147 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 11:08:14.610257 Total UI for P1: 0, mck2ui 16
1939 11:08:14.613963 best dqsien dly found for B0: ( 0, 14, 2)
1940 11:08:14.616974 Total UI for P1: 0, mck2ui 16
1941 11:08:14.620238 best dqsien dly found for B1: ( 0, 14, 2)
1942 11:08:14.623539 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1943 11:08:14.630167 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1944 11:08:14.630276
1945 11:08:14.633948 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1946 11:08:14.636686 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1947 11:08:14.640682 [Gating] SW calibration Done
1948 11:08:14.640787 ==
1949 11:08:14.643920 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 11:08:14.647200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 11:08:14.647305 ==
1952 11:08:14.647401 RX Vref Scan: 0
1953 11:08:14.650301
1954 11:08:14.650410 RX Vref 0 -> 0, step: 1
1955 11:08:14.650506
1956 11:08:14.653472 RX Delay -130 -> 252, step: 16
1957 11:08:14.656949 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1958 11:08:14.660198 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1959 11:08:14.666875 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1960 11:08:14.670580 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1961 11:08:14.673813 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1962 11:08:14.677143 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1963 11:08:14.680364 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1964 11:08:14.687112 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1965 11:08:14.690400 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1966 11:08:14.693666 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1967 11:08:14.696879 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1968 11:08:14.700298 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1969 11:08:14.707005 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1970 11:08:14.710241 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1971 11:08:14.713475 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1972 11:08:14.717000 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1973 11:08:14.717102 ==
1974 11:08:14.720144 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 11:08:14.727136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 11:08:14.727247 ==
1977 11:08:14.727342 DQS Delay:
1978 11:08:14.727437 DQS0 = 0, DQS1 = 0
1979 11:08:14.730504 DQM Delay:
1980 11:08:14.730609 DQM0 = 93, DQM1 = 90
1981 11:08:14.733723 DQ Delay:
1982 11:08:14.736871 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1983 11:08:14.740704 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1984 11:08:14.744037 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1985 11:08:14.747375 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1986 11:08:14.747481
1987 11:08:14.747573
1988 11:08:14.747666 ==
1989 11:08:14.750614 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 11:08:14.753830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 11:08:14.753947 ==
1992 11:08:14.754041
1993 11:08:14.754140
1994 11:08:14.757169 TX Vref Scan disable
1995 11:08:14.757276 == TX Byte 0 ==
1996 11:08:14.763649 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1997 11:08:14.766913 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1998 11:08:14.767027 == TX Byte 1 ==
1999 11:08:14.773861 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2000 11:08:14.777352 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2001 11:08:14.777472 ==
2002 11:08:14.780258 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 11:08:14.783701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 11:08:14.783842 ==
2005 11:08:14.797795 TX Vref=22, minBit 4, minWin=26, winSum=439
2006 11:08:14.801242 TX Vref=24, minBit 1, minWin=26, winSum=442
2007 11:08:14.804231 TX Vref=26, minBit 1, minWin=27, winSum=446
2008 11:08:14.808172 TX Vref=28, minBit 2, minWin=27, winSum=447
2009 11:08:14.811507 TX Vref=30, minBit 2, minWin=27, winSum=451
2010 11:08:14.814772 TX Vref=32, minBit 2, minWin=27, winSum=446
2011 11:08:14.821341 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 30
2012 11:08:14.821464
2013 11:08:14.824694 Final TX Range 1 Vref 30
2014 11:08:14.824827
2015 11:08:14.824941 ==
2016 11:08:14.827739 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 11:08:14.831377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 11:08:14.831509 ==
2019 11:08:14.831626
2020 11:08:14.831745
2021 11:08:14.834516 TX Vref Scan disable
2022 11:08:14.838399 == TX Byte 0 ==
2023 11:08:14.841699 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2024 11:08:14.844849 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2025 11:08:14.848008 == TX Byte 1 ==
2026 11:08:14.851165 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2027 11:08:14.854453 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2028 11:08:14.854588
2029 11:08:14.858275 [DATLAT]
2030 11:08:14.858396 Freq=800, CH1 RK1
2031 11:08:14.858520
2032 11:08:14.861620 DATLAT Default: 0xa
2033 11:08:14.861744 0, 0xFFFF, sum = 0
2034 11:08:14.864915 1, 0xFFFF, sum = 0
2035 11:08:14.865051 2, 0xFFFF, sum = 0
2036 11:08:14.868007 3, 0xFFFF, sum = 0
2037 11:08:14.868132 4, 0xFFFF, sum = 0
2038 11:08:14.871231 5, 0xFFFF, sum = 0
2039 11:08:14.871364 6, 0xFFFF, sum = 0
2040 11:08:14.874632 7, 0xFFFF, sum = 0
2041 11:08:14.874770 8, 0xFFFF, sum = 0
2042 11:08:14.877923 9, 0x0, sum = 1
2043 11:08:14.878061 10, 0x0, sum = 2
2044 11:08:14.881165 11, 0x0, sum = 3
2045 11:08:14.881290 12, 0x0, sum = 4
2046 11:08:14.884678 best_step = 10
2047 11:08:14.884763
2048 11:08:14.884828 ==
2049 11:08:14.888478 Dram Type= 6, Freq= 0, CH_1, rank 1
2050 11:08:14.891540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2051 11:08:14.891624 ==
2052 11:08:14.894824 RX Vref Scan: 0
2053 11:08:14.894943
2054 11:08:14.895043 RX Vref 0 -> 0, step: 1
2055 11:08:14.895139
2056 11:08:14.897895 RX Delay -63 -> 252, step: 8
2057 11:08:14.901690 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2058 11:08:14.908256 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2059 11:08:14.911552 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2060 11:08:14.914595 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2061 11:08:14.918430 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2062 11:08:14.921676 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2063 11:08:14.924931 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2064 11:08:14.931287 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2065 11:08:14.935213 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2066 11:08:14.938523 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2067 11:08:14.941612 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2068 11:08:14.944848 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2069 11:08:14.951325 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2070 11:08:14.954596 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2071 11:08:14.957942 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2072 11:08:14.961327 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2073 11:08:14.961432 ==
2074 11:08:14.965240 Dram Type= 6, Freq= 0, CH_1, rank 1
2075 11:08:14.968556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2076 11:08:14.971664 ==
2077 11:08:14.971771 DQS Delay:
2078 11:08:14.971869 DQS0 = 0, DQS1 = 0
2079 11:08:14.974997 DQM Delay:
2080 11:08:14.975130 DQM0 = 97, DQM1 = 90
2081 11:08:14.978257 DQ Delay:
2082 11:08:14.978393 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2083 11:08:14.981540 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2084 11:08:14.984727 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2085 11:08:14.991891 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2086 11:08:14.991976
2087 11:08:14.992043
2088 11:08:14.998630 [DQSOSCAuto] RK1, (LSB)MR18= 0x4610, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2089 11:08:15.001724 CH1 RK1: MR19=606, MR18=4610
2090 11:08:15.008581 CH1_RK1: MR19=0x606, MR18=0x4610, DQSOSC=392, MR23=63, INC=96, DEC=64
2091 11:08:15.011859 [RxdqsGatingPostProcess] freq 800
2092 11:08:15.015003 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2093 11:08:15.018114 Pre-setting of DQS Precalculation
2094 11:08:15.025064 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2095 11:08:15.031677 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2096 11:08:15.038529 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2097 11:08:15.038617
2098 11:08:15.038686
2099 11:08:15.041807 [Calibration Summary] 1600 Mbps
2100 11:08:15.041910 CH 0, Rank 0
2101 11:08:15.045594 SW Impedance : PASS
2102 11:08:15.045688 DUTY Scan : NO K
2103 11:08:15.048817 ZQ Calibration : PASS
2104 11:08:15.052021 Jitter Meter : NO K
2105 11:08:15.052147 CBT Training : PASS
2106 11:08:15.055293 Write leveling : PASS
2107 11:08:15.058551 RX DQS gating : PASS
2108 11:08:15.058691 RX DQ/DQS(RDDQC) : PASS
2109 11:08:15.061887 TX DQ/DQS : PASS
2110 11:08:15.065043 RX DATLAT : PASS
2111 11:08:15.065179 RX DQ/DQS(Engine): PASS
2112 11:08:15.068829 TX OE : NO K
2113 11:08:15.068964 All Pass.
2114 11:08:15.069095
2115 11:08:15.072231 CH 0, Rank 1
2116 11:08:15.072370 SW Impedance : PASS
2117 11:08:15.075451 DUTY Scan : NO K
2118 11:08:15.078705 ZQ Calibration : PASS
2119 11:08:15.078842 Jitter Meter : NO K
2120 11:08:15.081933 CBT Training : PASS
2121 11:08:15.082075 Write leveling : PASS
2122 11:08:15.085374 RX DQS gating : PASS
2123 11:08:15.088462 RX DQ/DQS(RDDQC) : PASS
2124 11:08:15.088595 TX DQ/DQS : PASS
2125 11:08:15.092400 RX DATLAT : PASS
2126 11:08:15.095031 RX DQ/DQS(Engine): PASS
2127 11:08:15.095111 TX OE : NO K
2128 11:08:15.098860 All Pass.
2129 11:08:15.098966
2130 11:08:15.099071 CH 1, Rank 0
2131 11:08:15.102274 SW Impedance : PASS
2132 11:08:15.102385 DUTY Scan : NO K
2133 11:08:15.105512 ZQ Calibration : PASS
2134 11:08:15.108813 Jitter Meter : NO K
2135 11:08:15.108896 CBT Training : PASS
2136 11:08:15.111944 Write leveling : PASS
2137 11:08:15.115515 RX DQS gating : PASS
2138 11:08:15.115631 RX DQ/DQS(RDDQC) : PASS
2139 11:08:15.118776 TX DQ/DQS : PASS
2140 11:08:15.122154 RX DATLAT : PASS
2141 11:08:15.122263 RX DQ/DQS(Engine): PASS
2142 11:08:15.125492 TX OE : NO K
2143 11:08:15.125596 All Pass.
2144 11:08:15.125702
2145 11:08:15.128913 CH 1, Rank 1
2146 11:08:15.128993 SW Impedance : PASS
2147 11:08:15.131868 DUTY Scan : NO K
2148 11:08:15.131979 ZQ Calibration : PASS
2149 11:08:15.135578 Jitter Meter : NO K
2150 11:08:15.138584 CBT Training : PASS
2151 11:08:15.138700 Write leveling : PASS
2152 11:08:15.142145 RX DQS gating : PASS
2153 11:08:15.145082 RX DQ/DQS(RDDQC) : PASS
2154 11:08:15.145187 TX DQ/DQS : PASS
2155 11:08:15.148477 RX DATLAT : PASS
2156 11:08:15.151885 RX DQ/DQS(Engine): PASS
2157 11:08:15.151995 TX OE : NO K
2158 11:08:15.155341 All Pass.
2159 11:08:15.155449
2160 11:08:15.155554 DramC Write-DBI off
2161 11:08:15.158638 PER_BANK_REFRESH: Hybrid Mode
2162 11:08:15.158757 TX_TRACKING: ON
2163 11:08:15.162051 [GetDramInforAfterCalByMRR] Vendor 6.
2164 11:08:15.168474 [GetDramInforAfterCalByMRR] Revision 606.
2165 11:08:15.172068 [GetDramInforAfterCalByMRR] Revision 2 0.
2166 11:08:15.172201 MR0 0x3b3b
2167 11:08:15.172302 MR8 0x5151
2168 11:08:15.174957 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2169 11:08:15.175108
2170 11:08:15.178349 MR0 0x3b3b
2171 11:08:15.178450 MR8 0x5151
2172 11:08:15.182207 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2173 11:08:15.182335
2174 11:08:15.192049 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2175 11:08:15.195382 [FAST_K] Save calibration result to emmc
2176 11:08:15.198645 [FAST_K] Save calibration result to emmc
2177 11:08:15.201886 dram_init: config_dvfs: 1
2178 11:08:15.205189 dramc_set_vcore_voltage set vcore to 662500
2179 11:08:15.208439 Read voltage for 1200, 2
2180 11:08:15.208519 Vio18 = 0
2181 11:08:15.208586 Vcore = 662500
2182 11:08:15.211747 Vdram = 0
2183 11:08:15.211855 Vddq = 0
2184 11:08:15.212018 Vmddr = 0
2185 11:08:15.218816 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2186 11:08:15.221853 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2187 11:08:15.225709 MEM_TYPE=3, freq_sel=15
2188 11:08:15.229052 sv_algorithm_assistance_LP4_1600
2189 11:08:15.232408 ============ PULL DRAM RESETB DOWN ============
2190 11:08:15.235749 ========== PULL DRAM RESETB DOWN end =========
2191 11:08:15.242372 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2192 11:08:15.245765 ===================================
2193 11:08:15.245852 LPDDR4 DRAM CONFIGURATION
2194 11:08:15.249025 ===================================
2195 11:08:15.252216 EX_ROW_EN[0] = 0x0
2196 11:08:15.252334 EX_ROW_EN[1] = 0x0
2197 11:08:15.255487 LP4Y_EN = 0x0
2198 11:08:15.255578 WORK_FSP = 0x0
2199 11:08:15.259228 WL = 0x4
2200 11:08:15.259338 RL = 0x4
2201 11:08:15.262210 BL = 0x2
2202 11:08:15.266004 RPST = 0x0
2203 11:08:15.266089 RD_PRE = 0x0
2204 11:08:15.268971 WR_PRE = 0x1
2205 11:08:15.269057 WR_PST = 0x0
2206 11:08:15.272030 DBI_WR = 0x0
2207 11:08:15.272143 DBI_RD = 0x0
2208 11:08:15.275595 OTF = 0x1
2209 11:08:15.278966 ===================================
2210 11:08:15.282225 ===================================
2211 11:08:15.282339 ANA top config
2212 11:08:15.285740 ===================================
2213 11:08:15.288980 DLL_ASYNC_EN = 0
2214 11:08:15.292302 ALL_SLAVE_EN = 0
2215 11:08:15.292383 NEW_RANK_MODE = 1
2216 11:08:15.295826 DLL_IDLE_MODE = 1
2217 11:08:15.298703 LP45_APHY_COMB_EN = 1
2218 11:08:15.302027 TX_ODT_DIS = 1
2219 11:08:15.302139 NEW_8X_MODE = 1
2220 11:08:15.305873 ===================================
2221 11:08:15.309264 ===================================
2222 11:08:15.312637 data_rate = 2400
2223 11:08:15.315344 CKR = 1
2224 11:08:15.319252 DQ_P2S_RATIO = 8
2225 11:08:15.322606 ===================================
2226 11:08:15.325748 CA_P2S_RATIO = 8
2227 11:08:15.328839 DQ_CA_OPEN = 0
2228 11:08:15.328950 DQ_SEMI_OPEN = 0
2229 11:08:15.332114 CA_SEMI_OPEN = 0
2230 11:08:15.335471 CA_FULL_RATE = 0
2231 11:08:15.338705 DQ_CKDIV4_EN = 0
2232 11:08:15.342104 CA_CKDIV4_EN = 0
2233 11:08:15.345180 CA_PREDIV_EN = 0
2234 11:08:15.345292 PH8_DLY = 17
2235 11:08:15.348530 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2236 11:08:15.351759 DQ_AAMCK_DIV = 4
2237 11:08:15.355779 CA_AAMCK_DIV = 4
2238 11:08:15.359072 CA_ADMCK_DIV = 4
2239 11:08:15.361738 DQ_TRACK_CA_EN = 0
2240 11:08:15.361822 CA_PICK = 1200
2241 11:08:15.365572 CA_MCKIO = 1200
2242 11:08:15.368690 MCKIO_SEMI = 0
2243 11:08:15.372198 PLL_FREQ = 2366
2244 11:08:15.375562 DQ_UI_PI_RATIO = 32
2245 11:08:15.378930 CA_UI_PI_RATIO = 0
2246 11:08:15.382276 ===================================
2247 11:08:15.385570 ===================================
2248 11:08:15.385654 memory_type:LPDDR4
2249 11:08:15.388733 GP_NUM : 10
2250 11:08:15.391754 SRAM_EN : 1
2251 11:08:15.391835 MD32_EN : 0
2252 11:08:15.395479 ===================================
2253 11:08:15.398980 [ANA_INIT] >>>>>>>>>>>>>>
2254 11:08:15.402204 <<<<<< [CONFIGURE PHASE]: ANA_TX
2255 11:08:15.405663 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2256 11:08:15.409104 ===================================
2257 11:08:15.412410 data_rate = 2400,PCW = 0X5b00
2258 11:08:15.415371 ===================================
2259 11:08:15.419008 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2260 11:08:15.421946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2261 11:08:15.428606 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 11:08:15.431855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2263 11:08:15.435995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2264 11:08:15.438979 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2265 11:08:15.442327 [ANA_INIT] flow start
2266 11:08:15.445734 [ANA_INIT] PLL >>>>>>>>
2267 11:08:15.445847 [ANA_INIT] PLL <<<<<<<<
2268 11:08:15.448887 [ANA_INIT] MIDPI >>>>>>>>
2269 11:08:15.452359 [ANA_INIT] MIDPI <<<<<<<<
2270 11:08:15.455623 [ANA_INIT] DLL >>>>>>>>
2271 11:08:15.455705 [ANA_INIT] DLL <<<<<<<<
2272 11:08:15.458939 [ANA_INIT] flow end
2273 11:08:15.462150 ============ LP4 DIFF to SE enter ============
2274 11:08:15.465376 ============ LP4 DIFF to SE exit ============
2275 11:08:15.469265 [ANA_INIT] <<<<<<<<<<<<<
2276 11:08:15.472640 [Flow] Enable top DCM control >>>>>
2277 11:08:15.475905 [Flow] Enable top DCM control <<<<<
2278 11:08:15.478889 Enable DLL master slave shuffle
2279 11:08:15.482557 ==============================================================
2280 11:08:15.485817 Gating Mode config
2281 11:08:15.492411 ==============================================================
2282 11:08:15.492532 Config description:
2283 11:08:15.502553 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2284 11:08:15.508712 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2285 11:08:15.512638 SELPH_MODE 0: By rank 1: By Phase
2286 11:08:15.518982 ==============================================================
2287 11:08:15.522320 GAT_TRACK_EN = 1
2288 11:08:15.526073 RX_GATING_MODE = 2
2289 11:08:15.528962 RX_GATING_TRACK_MODE = 2
2290 11:08:15.532549 SELPH_MODE = 1
2291 11:08:15.535667 PICG_EARLY_EN = 1
2292 11:08:15.539035 VALID_LAT_VALUE = 1
2293 11:08:15.542415 ==============================================================
2294 11:08:15.545483 Enter into Gating configuration >>>>
2295 11:08:15.549220 Exit from Gating configuration <<<<
2296 11:08:15.552801 Enter into DVFS_PRE_config >>>>>
2297 11:08:15.562189 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2298 11:08:15.565927 Exit from DVFS_PRE_config <<<<<
2299 11:08:15.569271 Enter into PICG configuration >>>>
2300 11:08:15.572671 Exit from PICG configuration <<<<
2301 11:08:15.575989 [RX_INPUT] configuration >>>>>
2302 11:08:15.579257 [RX_INPUT] configuration <<<<<
2303 11:08:15.586221 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2304 11:08:15.589175 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2305 11:08:15.595588 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2306 11:08:15.602363 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2307 11:08:15.609161 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2308 11:08:15.615553 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2309 11:08:15.618849 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2310 11:08:15.622193 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2311 11:08:15.625961 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2312 11:08:15.632571 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2313 11:08:15.635897 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2314 11:08:15.639037 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2315 11:08:15.642582 ===================================
2316 11:08:15.645958 LPDDR4 DRAM CONFIGURATION
2317 11:08:15.648914 ===================================
2318 11:08:15.648994 EX_ROW_EN[0] = 0x0
2319 11:08:15.652362 EX_ROW_EN[1] = 0x0
2320 11:08:15.652449 LP4Y_EN = 0x0
2321 11:08:15.655816 WORK_FSP = 0x0
2322 11:08:15.655902 WL = 0x4
2323 11:08:15.658996 RL = 0x4
2324 11:08:15.659077 BL = 0x2
2325 11:08:15.662247 RPST = 0x0
2326 11:08:15.665767 RD_PRE = 0x0
2327 11:08:15.665879 WR_PRE = 0x1
2328 11:08:15.668963 WR_PST = 0x0
2329 11:08:15.669047 DBI_WR = 0x0
2330 11:08:15.672385 DBI_RD = 0x0
2331 11:08:15.672494 OTF = 0x1
2332 11:08:15.675649 ===================================
2333 11:08:15.679072 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2334 11:08:15.685622 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2335 11:08:15.689019 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2336 11:08:15.692320 ===================================
2337 11:08:15.695454 LPDDR4 DRAM CONFIGURATION
2338 11:08:15.699072 ===================================
2339 11:08:15.699198 EX_ROW_EN[0] = 0x10
2340 11:08:15.702659 EX_ROW_EN[1] = 0x0
2341 11:08:15.702781 LP4Y_EN = 0x0
2342 11:08:15.705591 WORK_FSP = 0x0
2343 11:08:15.705697 WL = 0x4
2344 11:08:15.708923 RL = 0x4
2345 11:08:15.709009 BL = 0x2
2346 11:08:15.712256 RPST = 0x0
2347 11:08:15.712377 RD_PRE = 0x0
2348 11:08:15.715558 WR_PRE = 0x1
2349 11:08:15.715640 WR_PST = 0x0
2350 11:08:15.719536 DBI_WR = 0x0
2351 11:08:15.719623 DBI_RD = 0x0
2352 11:08:15.722793 OTF = 0x1
2353 11:08:15.725689 ===================================
2354 11:08:15.732222 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2355 11:08:15.732323 ==
2356 11:08:15.735660 Dram Type= 6, Freq= 0, CH_0, rank 0
2357 11:08:15.738919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 11:08:15.739006 ==
2359 11:08:15.742187 [Duty_Offset_Calibration]
2360 11:08:15.742300 B0:2 B1:1 CA:1
2361 11:08:15.742394
2362 11:08:15.745446 [DutyScan_Calibration_Flow] k_type=0
2363 11:08:15.756186
2364 11:08:15.756304 ==CLK 0==
2365 11:08:15.759397 Final CLK duty delay cell = 0
2366 11:08:15.763030 [0] MAX Duty = 5187%(X100), DQS PI = 24
2367 11:08:15.766410 [0] MIN Duty = 4844%(X100), DQS PI = 48
2368 11:08:15.766530 [0] AVG Duty = 5015%(X100)
2369 11:08:15.769594
2370 11:08:15.773004 CH0 CLK Duty spec in!! Max-Min= 343%
2371 11:08:15.776041 [DutyScan_Calibration_Flow] ====Done====
2372 11:08:15.776149
2373 11:08:15.779699 [DutyScan_Calibration_Flow] k_type=1
2374 11:08:15.793872
2375 11:08:15.794017 ==DQS 0 ==
2376 11:08:15.797299 Final DQS duty delay cell = -4
2377 11:08:15.800542 [-4] MAX Duty = 5156%(X100), DQS PI = 24
2378 11:08:15.804435 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2379 11:08:15.807631 [-4] AVG Duty = 4969%(X100)
2380 11:08:15.807751
2381 11:08:15.807869 ==DQS 1 ==
2382 11:08:15.810722 Final DQS duty delay cell = -4
2383 11:08:15.813807 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2384 11:08:15.817730 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2385 11:08:15.821038 [-4] AVG Duty = 4906%(X100)
2386 11:08:15.821113
2387 11:08:15.824202 CH0 DQS 0 Duty spec in!! Max-Min= 374%
2388 11:08:15.824309
2389 11:08:15.827501 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2390 11:08:15.830697 [DutyScan_Calibration_Flow] ====Done====
2391 11:08:15.830769
2392 11:08:15.834594 [DutyScan_Calibration_Flow] k_type=3
2393 11:08:15.851362
2394 11:08:15.851447 ==DQM 0 ==
2395 11:08:15.854507 Final DQM duty delay cell = 0
2396 11:08:15.858073 [0] MAX Duty = 5156%(X100), DQS PI = 30
2397 11:08:15.861232 [0] MIN Duty = 4938%(X100), DQS PI = 0
2398 11:08:15.861310 [0] AVG Duty = 5047%(X100)
2399 11:08:15.864560
2400 11:08:15.864633 ==DQM 1 ==
2401 11:08:15.867824 Final DQM duty delay cell = 0
2402 11:08:15.871153 [0] MAX Duty = 5125%(X100), DQS PI = 60
2403 11:08:15.874152 [0] MIN Duty = 5031%(X100), DQS PI = 20
2404 11:08:15.874249 [0] AVG Duty = 5078%(X100)
2405 11:08:15.877632
2406 11:08:15.881274 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2407 11:08:15.881399
2408 11:08:15.884444 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2409 11:08:15.887583 [DutyScan_Calibration_Flow] ====Done====
2410 11:08:15.887705
2411 11:08:15.890827 [DutyScan_Calibration_Flow] k_type=2
2412 11:08:15.907577
2413 11:08:15.907712 ==DQ 0 ==
2414 11:08:15.910863 Final DQ duty delay cell = 0
2415 11:08:15.914137 [0] MAX Duty = 5031%(X100), DQS PI = 24
2416 11:08:15.917254 [0] MIN Duty = 4875%(X100), DQS PI = 62
2417 11:08:15.917328 [0] AVG Duty = 4953%(X100)
2418 11:08:15.920955
2419 11:08:15.921026 ==DQ 1 ==
2420 11:08:15.924011 Final DQ duty delay cell = 0
2421 11:08:15.927256 [0] MAX Duty = 5093%(X100), DQS PI = 8
2422 11:08:15.931070 [0] MIN Duty = 4938%(X100), DQS PI = 36
2423 11:08:15.931172 [0] AVG Duty = 5015%(X100)
2424 11:08:15.931264
2425 11:08:15.934262 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2426 11:08:15.934359
2427 11:08:15.940671 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2428 11:08:15.944405 [DutyScan_Calibration_Flow] ====Done====
2429 11:08:15.944478 ==
2430 11:08:15.947417 Dram Type= 6, Freq= 0, CH_1, rank 0
2431 11:08:15.950741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2432 11:08:15.950816 ==
2433 11:08:15.954168 [Duty_Offset_Calibration]
2434 11:08:15.954244 B0:1 B1:0 CA:0
2435 11:08:15.954305
2436 11:08:15.957540 [DutyScan_Calibration_Flow] k_type=0
2437 11:08:15.966851
2438 11:08:15.966979 ==CLK 0==
2439 11:08:15.970193 Final CLK duty delay cell = -4
2440 11:08:15.973516 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2441 11:08:15.976974 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2442 11:08:15.980320 [-4] AVG Duty = 4953%(X100)
2443 11:08:15.980442
2444 11:08:15.983496 CH1 CLK Duty spec in!! Max-Min= 156%
2445 11:08:15.986685 [DutyScan_Calibration_Flow] ====Done====
2446 11:08:15.986814
2447 11:08:15.990197 [DutyScan_Calibration_Flow] k_type=1
2448 11:08:16.006429
2449 11:08:16.006543 ==DQS 0 ==
2450 11:08:16.009630 Final DQS duty delay cell = 0
2451 11:08:16.013013 [0] MAX Duty = 5094%(X100), DQS PI = 24
2452 11:08:16.016359 [0] MIN Duty = 4875%(X100), DQS PI = 0
2453 11:08:16.016445 [0] AVG Duty = 4984%(X100)
2454 11:08:16.020160
2455 11:08:16.020263 ==DQS 1 ==
2456 11:08:16.023466 Final DQS duty delay cell = 0
2457 11:08:16.026661 [0] MAX Duty = 5218%(X100), DQS PI = 20
2458 11:08:16.029657 [0] MIN Duty = 4969%(X100), DQS PI = 10
2459 11:08:16.029734 [0] AVG Duty = 5093%(X100)
2460 11:08:16.033528
2461 11:08:16.036778 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2462 11:08:16.036862
2463 11:08:16.039964 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2464 11:08:16.043323 [DutyScan_Calibration_Flow] ====Done====
2465 11:08:16.043415
2466 11:08:16.046720 [DutyScan_Calibration_Flow] k_type=3
2467 11:08:16.062792
2468 11:08:16.062907 ==DQM 0 ==
2469 11:08:16.066666 Final DQM duty delay cell = 0
2470 11:08:16.070063 [0] MAX Duty = 5156%(X100), DQS PI = 6
2471 11:08:16.073034 [0] MIN Duty = 5031%(X100), DQS PI = 0
2472 11:08:16.073120 [0] AVG Duty = 5093%(X100)
2473 11:08:16.073186
2474 11:08:16.076560 ==DQM 1 ==
2475 11:08:16.079780 Final DQM duty delay cell = 0
2476 11:08:16.083320 [0] MAX Duty = 5031%(X100), DQS PI = 16
2477 11:08:16.086676 [0] MIN Duty = 4907%(X100), DQS PI = 36
2478 11:08:16.086787 [0] AVG Duty = 4969%(X100)
2479 11:08:16.086891
2480 11:08:16.090009 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2481 11:08:16.093381
2482 11:08:16.096630 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2483 11:08:16.099937 [DutyScan_Calibration_Flow] ====Done====
2484 11:08:16.100048
2485 11:08:16.102997 [DutyScan_Calibration_Flow] k_type=2
2486 11:08:16.118536
2487 11:08:16.118623 ==DQ 0 ==
2488 11:08:16.122254 Final DQ duty delay cell = -4
2489 11:08:16.125614 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2490 11:08:16.129186 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2491 11:08:16.132332 [-4] AVG Duty = 4984%(X100)
2492 11:08:16.132453
2493 11:08:16.132567 ==DQ 1 ==
2494 11:08:16.135609 Final DQ duty delay cell = 0
2495 11:08:16.138581 [0] MAX Duty = 5125%(X100), DQS PI = 20
2496 11:08:16.142443 [0] MIN Duty = 4969%(X100), DQS PI = 10
2497 11:08:16.142573 [0] AVG Duty = 5047%(X100)
2498 11:08:16.145687
2499 11:08:16.148842 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2500 11:08:16.148965
2501 11:08:16.152295 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2502 11:08:16.155643 [DutyScan_Calibration_Flow] ====Done====
2503 11:08:16.158895 nWR fixed to 30
2504 11:08:16.158980 [ModeRegInit_LP4] CH0 RK0
2505 11:08:16.162485 [ModeRegInit_LP4] CH0 RK1
2506 11:08:16.165712 [ModeRegInit_LP4] CH1 RK0
2507 11:08:16.165795 [ModeRegInit_LP4] CH1 RK1
2508 11:08:16.169006 match AC timing 7
2509 11:08:16.172327 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2510 11:08:16.175640 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2511 11:08:16.182473 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2512 11:08:16.185576 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2513 11:08:16.192183 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2514 11:08:16.192267 ==
2515 11:08:16.195435 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 11:08:16.199401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 11:08:16.199484 ==
2518 11:08:16.205940 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 11:08:16.209356 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2520 11:08:16.219089 [CA 0] Center 39 (8~70) winsize 63
2521 11:08:16.222582 [CA 1] Center 39 (8~70) winsize 63
2522 11:08:16.225934 [CA 2] Center 35 (5~66) winsize 62
2523 11:08:16.229175 [CA 3] Center 34 (4~65) winsize 62
2524 11:08:16.232366 [CA 4] Center 33 (3~64) winsize 62
2525 11:08:16.235575 [CA 5] Center 32 (3~62) winsize 60
2526 11:08:16.235697
2527 11:08:16.239010 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2528 11:08:16.239132
2529 11:08:16.242413 [CATrainingPosCal] consider 1 rank data
2530 11:08:16.245858 u2DelayCellTimex100 = 270/100 ps
2531 11:08:16.249406 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2532 11:08:16.252360 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2533 11:08:16.259389 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2534 11:08:16.262748 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2535 11:08:16.265991 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2536 11:08:16.269130 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2537 11:08:16.269214
2538 11:08:16.273065 CA PerBit enable=1, Macro0, CA PI delay=32
2539 11:08:16.273154
2540 11:08:16.275754 [CBTSetCACLKResult] CA Dly = 32
2541 11:08:16.275838 CS Dly: 6 (0~37)
2542 11:08:16.275905 ==
2543 11:08:16.279707 Dram Type= 6, Freq= 0, CH_0, rank 1
2544 11:08:16.286289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2545 11:08:16.286374 ==
2546 11:08:16.289354 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2547 11:08:16.295630 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2548 11:08:16.304871 [CA 0] Center 38 (8~69) winsize 62
2549 11:08:16.308203 [CA 1] Center 38 (8~69) winsize 62
2550 11:08:16.311493 [CA 2] Center 35 (4~66) winsize 63
2551 11:08:16.314814 [CA 3] Center 34 (4~65) winsize 62
2552 11:08:16.318125 [CA 4] Center 33 (3~64) winsize 62
2553 11:08:16.321312 [CA 5] Center 32 (3~62) winsize 60
2554 11:08:16.321397
2555 11:08:16.325107 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2556 11:08:16.325190
2557 11:08:16.328252 [CATrainingPosCal] consider 2 rank data
2558 11:08:16.332020 u2DelayCellTimex100 = 270/100 ps
2559 11:08:16.334977 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2560 11:08:16.338480 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2561 11:08:16.344907 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2562 11:08:16.348222 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2563 11:08:16.351448 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2564 11:08:16.355167 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2565 11:08:16.355249
2566 11:08:16.358132 CA PerBit enable=1, Macro0, CA PI delay=32
2567 11:08:16.358212
2568 11:08:16.361807 [CBTSetCACLKResult] CA Dly = 32
2569 11:08:16.361954 CS Dly: 6 (0~38)
2570 11:08:16.362072
2571 11:08:16.365203 ----->DramcWriteLeveling(PI) begin...
2572 11:08:16.365313 ==
2573 11:08:16.368479 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 11:08:16.375060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 11:08:16.375174 ==
2576 11:08:16.378193 Write leveling (Byte 0): 34 => 34
2577 11:08:16.381897 Write leveling (Byte 1): 29 => 29
2578 11:08:16.381982 DramcWriteLeveling(PI) end<-----
2579 11:08:16.384946
2580 11:08:16.385029 ==
2581 11:08:16.388291 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 11:08:16.391537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 11:08:16.391630 ==
2584 11:08:16.395434 [Gating] SW mode calibration
2585 11:08:16.402010 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2586 11:08:16.405380 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2587 11:08:16.412012 0 15 0 | B1->B0 | 2323 3433 | 0 1 | (0 0) (1 1)
2588 11:08:16.415389 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2589 11:08:16.418620 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 11:08:16.425268 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 11:08:16.428346 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 11:08:16.431639 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 11:08:16.438389 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 11:08:16.441715 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2595 11:08:16.445358 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2596 11:08:16.451714 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 11:08:16.455415 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 11:08:16.458710 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 11:08:16.465253 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 11:08:16.468594 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 11:08:16.471864 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2602 11:08:16.475027 1 0 28 | B1->B0 | 2c2c 4545 | 0 0 | (0 0) (1 1)
2603 11:08:16.481866 1 1 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
2604 11:08:16.485153 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 11:08:16.488296 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 11:08:16.494834 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 11:08:16.498347 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 11:08:16.501895 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 11:08:16.508577 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 11:08:16.511965 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2611 11:08:16.515302 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2612 11:08:16.521814 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 11:08:16.525060 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 11:08:16.528357 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 11:08:16.534903 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 11:08:16.538957 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 11:08:16.541710 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 11:08:16.548357 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 11:08:16.551563 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 11:08:16.554839 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 11:08:16.561745 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 11:08:16.565169 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 11:08:16.568172 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 11:08:16.571819 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 11:08:16.578491 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 11:08:16.581827 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2627 11:08:16.585226 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2628 11:08:16.588470 Total UI for P1: 0, mck2ui 16
2629 11:08:16.591899 best dqsien dly found for B0: ( 1, 3, 28)
2630 11:08:16.598709 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2631 11:08:16.598792 Total UI for P1: 0, mck2ui 16
2632 11:08:16.605401 best dqsien dly found for B1: ( 1, 4, 0)
2633 11:08:16.608747 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2634 11:08:16.611985 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2635 11:08:16.612095
2636 11:08:16.615284 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2637 11:08:16.618598 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2638 11:08:16.622219 [Gating] SW calibration Done
2639 11:08:16.622303 ==
2640 11:08:16.625325 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 11:08:16.628508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 11:08:16.628592 ==
2643 11:08:16.632155 RX Vref Scan: 0
2644 11:08:16.632293
2645 11:08:16.632410 RX Vref 0 -> 0, step: 1
2646 11:08:16.632524
2647 11:08:16.635603 RX Delay -40 -> 252, step: 8
2648 11:08:16.638897 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2649 11:08:16.642294 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2650 11:08:16.648628 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2651 11:08:16.652000 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2652 11:08:16.655322 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2653 11:08:16.658672 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2654 11:08:16.661898 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2655 11:08:16.669312 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2656 11:08:16.672540 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2657 11:08:16.675481 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2658 11:08:16.679218 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2659 11:08:16.682203 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2660 11:08:16.689196 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2661 11:08:16.692451 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2662 11:08:16.695879 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2663 11:08:16.699160 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2664 11:08:16.699241 ==
2665 11:08:16.702482 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 11:08:16.705925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 11:08:16.709168 ==
2668 11:08:16.709243 DQS Delay:
2669 11:08:16.709305 DQS0 = 0, DQS1 = 0
2670 11:08:16.712354 DQM Delay:
2671 11:08:16.712424 DQM0 = 121, DQM1 = 114
2672 11:08:16.715708 DQ Delay:
2673 11:08:16.719151 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2674 11:08:16.722453 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2675 11:08:16.725817 DQ8 =99, DQ9 =107, DQ10 =115, DQ11 =107
2676 11:08:16.729374 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2677 11:08:16.729451
2678 11:08:16.729516
2679 11:08:16.729577 ==
2680 11:08:16.732440 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 11:08:16.735601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 11:08:16.735674 ==
2683 11:08:16.735736
2684 11:08:16.739190
2685 11:08:16.739273 TX Vref Scan disable
2686 11:08:16.742493 == TX Byte 0 ==
2687 11:08:16.745930 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2688 11:08:16.749354 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2689 11:08:16.752357 == TX Byte 1 ==
2690 11:08:16.755786 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2691 11:08:16.758955 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2692 11:08:16.759049 ==
2693 11:08:16.762386 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 11:08:16.768898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 11:08:16.769009 ==
2696 11:08:16.779440 TX Vref=22, minBit 0, minWin=24, winSum=407
2697 11:08:16.783340 TX Vref=24, minBit 0, minWin=25, winSum=416
2698 11:08:16.786558 TX Vref=26, minBit 7, minWin=25, winSum=424
2699 11:08:16.789681 TX Vref=28, minBit 12, minWin=25, winSum=423
2700 11:08:16.793218 TX Vref=30, minBit 0, minWin=26, winSum=424
2701 11:08:16.796760 TX Vref=32, minBit 0, minWin=26, winSum=425
2702 11:08:16.803468 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 32
2703 11:08:16.803605
2704 11:08:16.806705 Final TX Range 1 Vref 32
2705 11:08:16.806835
2706 11:08:16.806954 ==
2707 11:08:16.810013 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 11:08:16.813223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 11:08:16.813371 ==
2710 11:08:16.813500
2711 11:08:16.813619
2712 11:08:16.816599 TX Vref Scan disable
2713 11:08:16.820009 == TX Byte 0 ==
2714 11:08:16.823224 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2715 11:08:16.826537 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2716 11:08:16.829790 == TX Byte 1 ==
2717 11:08:16.833193 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2718 11:08:16.836485 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2719 11:08:16.836564
2720 11:08:16.839791 [DATLAT]
2721 11:08:16.839866 Freq=1200, CH0 RK0
2722 11:08:16.839929
2723 11:08:16.843061 DATLAT Default: 0xd
2724 11:08:16.843132 0, 0xFFFF, sum = 0
2725 11:08:16.846989 1, 0xFFFF, sum = 0
2726 11:08:16.847074 2, 0xFFFF, sum = 0
2727 11:08:16.850325 3, 0xFFFF, sum = 0
2728 11:08:16.850410 4, 0xFFFF, sum = 0
2729 11:08:16.853604 5, 0xFFFF, sum = 0
2730 11:08:16.853693 6, 0xFFFF, sum = 0
2731 11:08:16.856884 7, 0xFFFF, sum = 0
2732 11:08:16.856957 8, 0xFFFF, sum = 0
2733 11:08:16.859912 9, 0xFFFF, sum = 0
2734 11:08:16.860025 10, 0xFFFF, sum = 0
2735 11:08:16.863085 11, 0xFFFF, sum = 0
2736 11:08:16.863162 12, 0x0, sum = 1
2737 11:08:16.867021 13, 0x0, sum = 2
2738 11:08:16.867098 14, 0x0, sum = 3
2739 11:08:16.870467 15, 0x0, sum = 4
2740 11:08:16.870552 best_step = 13
2741 11:08:16.870616
2742 11:08:16.870676 ==
2743 11:08:16.873724 Dram Type= 6, Freq= 0, CH_0, rank 0
2744 11:08:16.879877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2745 11:08:16.880006 ==
2746 11:08:16.880104 RX Vref Scan: 1
2747 11:08:16.880195
2748 11:08:16.883480 Set Vref Range= 32 -> 127
2749 11:08:16.883585
2750 11:08:16.886754 RX Vref 32 -> 127, step: 1
2751 11:08:16.886838
2752 11:08:16.889978 RX Delay -13 -> 252, step: 4
2753 11:08:16.890100
2754 11:08:16.890197 Set Vref, RX VrefLevel [Byte0]: 32
2755 11:08:16.893510 [Byte1]: 32
2756 11:08:16.898097
2757 11:08:16.898185 Set Vref, RX VrefLevel [Byte0]: 33
2758 11:08:16.901252 [Byte1]: 33
2759 11:08:16.905940
2760 11:08:16.906024 Set Vref, RX VrefLevel [Byte0]: 34
2761 11:08:16.909799 [Byte1]: 34
2762 11:08:16.914012
2763 11:08:16.914122 Set Vref, RX VrefLevel [Byte0]: 35
2764 11:08:16.916883 [Byte1]: 35
2765 11:08:16.921672
2766 11:08:16.921755 Set Vref, RX VrefLevel [Byte0]: 36
2767 11:08:16.925089 [Byte1]: 36
2768 11:08:16.929489
2769 11:08:16.929574 Set Vref, RX VrefLevel [Byte0]: 37
2770 11:08:16.932924 [Byte1]: 37
2771 11:08:16.937537
2772 11:08:16.937648 Set Vref, RX VrefLevel [Byte0]: 38
2773 11:08:16.940847 [Byte1]: 38
2774 11:08:16.945438
2775 11:08:16.945552 Set Vref, RX VrefLevel [Byte0]: 39
2776 11:08:16.948828 [Byte1]: 39
2777 11:08:16.953374
2778 11:08:16.953458 Set Vref, RX VrefLevel [Byte0]: 40
2779 11:08:16.956544 [Byte1]: 40
2780 11:08:16.961277
2781 11:08:16.961360 Set Vref, RX VrefLevel [Byte0]: 41
2782 11:08:16.964704 [Byte1]: 41
2783 11:08:16.968981
2784 11:08:16.969063 Set Vref, RX VrefLevel [Byte0]: 42
2785 11:08:16.972144 [Byte1]: 42
2786 11:08:16.976955
2787 11:08:16.977039 Set Vref, RX VrefLevel [Byte0]: 43
2788 11:08:16.980263 [Byte1]: 43
2789 11:08:16.984987
2790 11:08:16.985069 Set Vref, RX VrefLevel [Byte0]: 44
2791 11:08:16.988257 [Byte1]: 44
2792 11:08:16.992913
2793 11:08:16.992997 Set Vref, RX VrefLevel [Byte0]: 45
2794 11:08:16.996264 [Byte1]: 45
2795 11:08:17.000625
2796 11:08:17.000709 Set Vref, RX VrefLevel [Byte0]: 46
2797 11:08:17.004010 [Byte1]: 46
2798 11:08:17.008338
2799 11:08:17.008422 Set Vref, RX VrefLevel [Byte0]: 47
2800 11:08:17.011804 [Byte1]: 47
2801 11:08:17.016600
2802 11:08:17.016687 Set Vref, RX VrefLevel [Byte0]: 48
2803 11:08:17.019775 [Byte1]: 48
2804 11:08:17.024428
2805 11:08:17.024511 Set Vref, RX VrefLevel [Byte0]: 49
2806 11:08:17.027484 [Byte1]: 49
2807 11:08:17.032444
2808 11:08:17.032529 Set Vref, RX VrefLevel [Byte0]: 50
2809 11:08:17.035240 [Byte1]: 50
2810 11:08:17.039824
2811 11:08:17.039907 Set Vref, RX VrefLevel [Byte0]: 51
2812 11:08:17.043127 [Byte1]: 51
2813 11:08:17.047834
2814 11:08:17.047919 Set Vref, RX VrefLevel [Byte0]: 52
2815 11:08:17.051287 [Byte1]: 52
2816 11:08:17.055749
2817 11:08:17.055832 Set Vref, RX VrefLevel [Byte0]: 53
2818 11:08:17.059145 [Byte1]: 53
2819 11:08:17.063403
2820 11:08:17.063488 Set Vref, RX VrefLevel [Byte0]: 54
2821 11:08:17.067183 [Byte1]: 54
2822 11:08:17.071789
2823 11:08:17.071930 Set Vref, RX VrefLevel [Byte0]: 55
2824 11:08:17.074881 [Byte1]: 55
2825 11:08:17.079326
2826 11:08:17.079410 Set Vref, RX VrefLevel [Byte0]: 56
2827 11:08:17.082659 [Byte1]: 56
2828 11:08:17.087182
2829 11:08:17.087265 Set Vref, RX VrefLevel [Byte0]: 57
2830 11:08:17.090524 [Byte1]: 57
2831 11:08:17.095057
2832 11:08:17.095140 Set Vref, RX VrefLevel [Byte0]: 58
2833 11:08:17.098281 [Byte1]: 58
2834 11:08:17.102883
2835 11:08:17.102967 Set Vref, RX VrefLevel [Byte0]: 59
2836 11:08:17.106316 [Byte1]: 59
2837 11:08:17.110868
2838 11:08:17.110993 Set Vref, RX VrefLevel [Byte0]: 60
2839 11:08:17.114657 [Byte1]: 60
2840 11:08:17.118766
2841 11:08:17.118862 Set Vref, RX VrefLevel [Byte0]: 61
2842 11:08:17.121911 [Byte1]: 61
2843 11:08:17.126498
2844 11:08:17.126589 Set Vref, RX VrefLevel [Byte0]: 62
2845 11:08:17.129805 [Byte1]: 62
2846 11:08:17.134604
2847 11:08:17.134696 Set Vref, RX VrefLevel [Byte0]: 63
2848 11:08:17.137939 [Byte1]: 63
2849 11:08:17.142489
2850 11:08:17.142623 Set Vref, RX VrefLevel [Byte0]: 64
2851 11:08:17.145997 [Byte1]: 64
2852 11:08:17.150517
2853 11:08:17.150646 Set Vref, RX VrefLevel [Byte0]: 65
2854 11:08:17.153796 [Byte1]: 65
2855 11:08:17.158330
2856 11:08:17.158462 Set Vref, RX VrefLevel [Byte0]: 66
2857 11:08:17.161556 [Byte1]: 66
2858 11:08:17.166479
2859 11:08:17.166605 Set Vref, RX VrefLevel [Byte0]: 67
2860 11:08:17.169905 [Byte1]: 67
2861 11:08:17.174386
2862 11:08:17.174510 Set Vref, RX VrefLevel [Byte0]: 68
2863 11:08:17.177424 [Byte1]: 68
2864 11:08:17.182608
2865 11:08:17.182738 Set Vref, RX VrefLevel [Byte0]: 69
2866 11:08:17.185072 [Byte1]: 69
2867 11:08:17.189880
2868 11:08:17.190005 Final RX Vref Byte 0 = 58 to rank0
2869 11:08:17.193081 Final RX Vref Byte 1 = 54 to rank0
2870 11:08:17.196559 Final RX Vref Byte 0 = 58 to rank1
2871 11:08:17.199966 Final RX Vref Byte 1 = 54 to rank1==
2872 11:08:17.203159 Dram Type= 6, Freq= 0, CH_0, rank 0
2873 11:08:17.210156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2874 11:08:17.210300 ==
2875 11:08:17.210423 DQS Delay:
2876 11:08:17.210546 DQS0 = 0, DQS1 = 0
2877 11:08:17.213485 DQM Delay:
2878 11:08:17.213615 DQM0 = 120, DQM1 = 113
2879 11:08:17.216847 DQ Delay:
2880 11:08:17.220193 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =118
2881 11:08:17.223197 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2882 11:08:17.226708 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
2883 11:08:17.230249 DQ12 =120, DQ13 =116, DQ14 =126, DQ15 =122
2884 11:08:17.230389
2885 11:08:17.230506
2886 11:08:17.236809 [DQSOSCAuto] RK0, (LSB)MR18= 0x130d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2887 11:08:17.240202 CH0 RK0: MR19=404, MR18=130D
2888 11:08:17.246846 CH0_RK0: MR19=0x404, MR18=0x130D, DQSOSC=402, MR23=63, INC=40, DEC=27
2889 11:08:17.246988
2890 11:08:17.249915 ----->DramcWriteLeveling(PI) begin...
2891 11:08:17.250004 ==
2892 11:08:17.253309 Dram Type= 6, Freq= 0, CH_0, rank 1
2893 11:08:17.256639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2894 11:08:17.260031 ==
2895 11:08:17.260112 Write leveling (Byte 0): 34 => 34
2896 11:08:17.263380 Write leveling (Byte 1): 28 => 28
2897 11:08:17.266733 DramcWriteLeveling(PI) end<-----
2898 11:08:17.266876
2899 11:08:17.266995 ==
2900 11:08:17.269990 Dram Type= 6, Freq= 0, CH_0, rank 1
2901 11:08:17.276580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 11:08:17.276712 ==
2903 11:08:17.276844 [Gating] SW mode calibration
2904 11:08:17.286503 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2905 11:08:17.290402 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2906 11:08:17.293716 0 15 0 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 1)
2907 11:08:17.300005 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 11:08:17.303692 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 11:08:17.306851 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 11:08:17.313685 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 11:08:17.316824 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 11:08:17.320215 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 11:08:17.326703 0 15 28 | B1->B0 | 2f2f 2d2d | 0 0 | (1 0) (1 0)
2914 11:08:17.330426 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2915 11:08:17.333433 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 11:08:17.340210 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 11:08:17.343821 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 11:08:17.347015 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 11:08:17.353735 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 11:08:17.356860 1 0 24 | B1->B0 | 2525 2424 | 0 1 | (0 0) (0 0)
2921 11:08:17.360181 1 0 28 | B1->B0 | 4343 3f3f | 0 1 | (0 0) (0 0)
2922 11:08:17.363419 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 11:08:17.370649 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 11:08:17.373399 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 11:08:17.376740 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 11:08:17.383392 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 11:08:17.387291 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 11:08:17.390574 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 11:08:17.397273 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2930 11:08:17.400648 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 11:08:17.403900 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 11:08:17.410627 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 11:08:17.414028 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 11:08:17.417322 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 11:08:17.424015 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 11:08:17.427285 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 11:08:17.430449 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 11:08:17.437170 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 11:08:17.440157 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 11:08:17.443672 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 11:08:17.447243 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 11:08:17.453529 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 11:08:17.456934 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 11:08:17.460264 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 11:08:17.467088 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2946 11:08:17.470717 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2947 11:08:17.473832 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 11:08:17.477204 Total UI for P1: 0, mck2ui 16
2949 11:08:17.480669 best dqsien dly found for B0: ( 1, 3, 30)
2950 11:08:17.484107 Total UI for P1: 0, mck2ui 16
2951 11:08:17.487338 best dqsien dly found for B1: ( 1, 3, 30)
2952 11:08:17.490719 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2953 11:08:17.493884 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2954 11:08:17.493971
2955 11:08:17.500608 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2956 11:08:17.503876 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2957 11:08:17.503962 [Gating] SW calibration Done
2958 11:08:17.507212 ==
2959 11:08:17.510524 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 11:08:17.513928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 11:08:17.514014 ==
2962 11:08:17.514081 RX Vref Scan: 0
2963 11:08:17.514143
2964 11:08:17.517298 RX Vref 0 -> 0, step: 1
2965 11:08:17.517407
2966 11:08:17.520664 RX Delay -40 -> 252, step: 8
2967 11:08:17.523902 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2968 11:08:17.527304 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2969 11:08:17.530513 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2970 11:08:17.537019 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2971 11:08:17.540304 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2972 11:08:17.543701 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2973 11:08:17.546889 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2974 11:08:17.550735 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2975 11:08:17.557191 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2976 11:08:17.560784 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2977 11:08:17.563945 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2978 11:08:17.567706 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2979 11:08:17.571009 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2980 11:08:17.577588 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2981 11:08:17.580987 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2982 11:08:17.584162 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2983 11:08:17.584278 ==
2984 11:08:17.587195 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 11:08:17.590702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 11:08:17.590816 ==
2987 11:08:17.593976 DQS Delay:
2988 11:08:17.594064 DQS0 = 0, DQS1 = 0
2989 11:08:17.597164 DQM Delay:
2990 11:08:17.597248 DQM0 = 122, DQM1 = 114
2991 11:08:17.597314 DQ Delay:
2992 11:08:17.600727 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2993 11:08:17.607539 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2994 11:08:17.610877 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =107
2995 11:08:17.613999 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2996 11:08:17.614121
2997 11:08:17.614217
2998 11:08:17.614308 ==
2999 11:08:17.617204 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 11:08:17.620530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 11:08:17.620639 ==
3002 11:08:17.620734
3003 11:08:17.620824
3004 11:08:17.624459 TX Vref Scan disable
3005 11:08:17.627809 == TX Byte 0 ==
3006 11:08:17.631078 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3007 11:08:17.634452 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3008 11:08:17.637144 == TX Byte 1 ==
3009 11:08:17.640975 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3010 11:08:17.644422 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3011 11:08:17.644553 ==
3012 11:08:17.647671 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 11:08:17.650918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 11:08:17.651045 ==
3015 11:08:17.664567 TX Vref=22, minBit 1, minWin=25, winSum=412
3016 11:08:17.667735 TX Vref=24, minBit 0, minWin=26, winSum=423
3017 11:08:17.670882 TX Vref=26, minBit 0, minWin=26, winSum=424
3018 11:08:17.674264 TX Vref=28, minBit 0, minWin=26, winSum=424
3019 11:08:17.677621 TX Vref=30, minBit 5, minWin=25, winSum=424
3020 11:08:17.681226 TX Vref=32, minBit 2, minWin=26, winSum=426
3021 11:08:17.687670 [TxChooseVref] Worse bit 2, Min win 26, Win sum 426, Final Vref 32
3022 11:08:17.687807
3023 11:08:17.691017 Final TX Range 1 Vref 32
3024 11:08:17.691147
3025 11:08:17.691264 ==
3026 11:08:17.694368 Dram Type= 6, Freq= 0, CH_0, rank 1
3027 11:08:17.697729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3028 11:08:17.697850 ==
3029 11:08:17.697947
3030 11:08:17.701121
3031 11:08:17.701203 TX Vref Scan disable
3032 11:08:17.704246 == TX Byte 0 ==
3033 11:08:17.707351 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3034 11:08:17.710929 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3035 11:08:17.714135 == TX Byte 1 ==
3036 11:08:17.717543 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3037 11:08:17.720736 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3038 11:08:17.720866
3039 11:08:17.724514 [DATLAT]
3040 11:08:17.724639 Freq=1200, CH0 RK1
3041 11:08:17.724753
3042 11:08:17.727900 DATLAT Default: 0xd
3043 11:08:17.728027 0, 0xFFFF, sum = 0
3044 11:08:17.730727 1, 0xFFFF, sum = 0
3045 11:08:17.730856 2, 0xFFFF, sum = 0
3046 11:08:17.734394 3, 0xFFFF, sum = 0
3047 11:08:17.734523 4, 0xFFFF, sum = 0
3048 11:08:17.737678 5, 0xFFFF, sum = 0
3049 11:08:17.737808 6, 0xFFFF, sum = 0
3050 11:08:17.741394 7, 0xFFFF, sum = 0
3051 11:08:17.741521 8, 0xFFFF, sum = 0
3052 11:08:17.744267 9, 0xFFFF, sum = 0
3053 11:08:17.747853 10, 0xFFFF, sum = 0
3054 11:08:17.747982 11, 0xFFFF, sum = 0
3055 11:08:17.751193 12, 0x0, sum = 1
3056 11:08:17.751322 13, 0x0, sum = 2
3057 11:08:17.754460 14, 0x0, sum = 3
3058 11:08:17.754595 15, 0x0, sum = 4
3059 11:08:17.754714 best_step = 13
3060 11:08:17.754828
3061 11:08:17.757728 ==
3062 11:08:17.761119 Dram Type= 6, Freq= 0, CH_0, rank 1
3063 11:08:17.764447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 11:08:17.764535 ==
3065 11:08:17.764629 RX Vref Scan: 0
3066 11:08:17.764718
3067 11:08:17.767714 RX Vref 0 -> 0, step: 1
3068 11:08:17.767824
3069 11:08:17.771179 RX Delay -13 -> 252, step: 4
3070 11:08:17.774341 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3071 11:08:17.780606 iDelay=195, Bit 1, Center 122 (59 ~ 186) 128
3072 11:08:17.784494 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3073 11:08:17.787543 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3074 11:08:17.791190 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3075 11:08:17.794711 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3076 11:08:17.797795 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3077 11:08:17.804373 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3078 11:08:17.807733 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3079 11:08:17.811270 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3080 11:08:17.814482 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3081 11:08:17.817721 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3082 11:08:17.824264 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3083 11:08:17.827468 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3084 11:08:17.831167 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3085 11:08:17.834539 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3086 11:08:17.834628 ==
3087 11:08:17.837420 Dram Type= 6, Freq= 0, CH_0, rank 1
3088 11:08:17.844589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3089 11:08:17.844726 ==
3090 11:08:17.844833 DQS Delay:
3091 11:08:17.844943 DQS0 = 0, DQS1 = 0
3092 11:08:17.847801 DQM Delay:
3093 11:08:17.847924 DQM0 = 120, DQM1 = 111
3094 11:08:17.850994 DQ Delay:
3095 11:08:17.854652 DQ0 =120, DQ1 =122, DQ2 =116, DQ3 =118
3096 11:08:17.858027 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3097 11:08:17.860911 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =104
3098 11:08:17.864720 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =118
3099 11:08:17.864804
3100 11:08:17.864880
3101 11:08:17.874388 [DQSOSCAuto] RK1, (LSB)MR18= 0xced, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3102 11:08:17.874538 CH0 RK1: MR19=403, MR18=CED
3103 11:08:17.881435 CH0_RK1: MR19=0x403, MR18=0xCED, DQSOSC=405, MR23=63, INC=39, DEC=26
3104 11:08:17.884698 [RxdqsGatingPostProcess] freq 1200
3105 11:08:17.891564 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3106 11:08:17.894773 best DQS0 dly(2T, 0.5T) = (0, 11)
3107 11:08:17.894903 best DQS1 dly(2T, 0.5T) = (0, 12)
3108 11:08:17.897964 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3109 11:08:17.901561 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3110 11:08:17.904613 best DQS0 dly(2T, 0.5T) = (0, 11)
3111 11:08:17.908412 best DQS1 dly(2T, 0.5T) = (0, 11)
3112 11:08:17.911568 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3113 11:08:17.914843 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3114 11:08:17.918134 Pre-setting of DQS Precalculation
3115 11:08:17.921298 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3116 11:08:17.924711 ==
3117 11:08:17.927951 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 11:08:17.931355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 11:08:17.931441 ==
3120 11:08:17.935121 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3121 11:08:17.941542 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3122 11:08:17.950354 [CA 0] Center 37 (7~68) winsize 62
3123 11:08:17.953656 [CA 1] Center 37 (7~68) winsize 62
3124 11:08:17.957101 [CA 2] Center 35 (5~65) winsize 61
3125 11:08:17.960295 [CA 3] Center 34 (4~65) winsize 62
3126 11:08:17.963606 [CA 4] Center 35 (5~65) winsize 61
3127 11:08:17.967121 [CA 5] Center 33 (3~63) winsize 61
3128 11:08:17.967226
3129 11:08:17.970668 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3130 11:08:17.970782
3131 11:08:17.973729 [CATrainingPosCal] consider 1 rank data
3132 11:08:17.977242 u2DelayCellTimex100 = 270/100 ps
3133 11:08:17.980479 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3134 11:08:17.983709 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3135 11:08:17.990463 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3136 11:08:17.994263 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3137 11:08:17.997309 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3138 11:08:18.000239 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3139 11:08:18.000346
3140 11:08:18.003568 CA PerBit enable=1, Macro0, CA PI delay=33
3141 11:08:18.003649
3142 11:08:18.006904 [CBTSetCACLKResult] CA Dly = 33
3143 11:08:18.007022 CS Dly: 7 (0~38)
3144 11:08:18.010528 ==
3145 11:08:18.010642 Dram Type= 6, Freq= 0, CH_1, rank 1
3146 11:08:18.017268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3147 11:08:18.017365 ==
3148 11:08:18.020703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3149 11:08:18.027129 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3150 11:08:18.036654 [CA 0] Center 37 (7~68) winsize 62
3151 11:08:18.039881 [CA 1] Center 37 (7~68) winsize 62
3152 11:08:18.042944 [CA 2] Center 35 (5~65) winsize 61
3153 11:08:18.046047 [CA 3] Center 34 (4~65) winsize 62
3154 11:08:18.049911 [CA 4] Center 34 (4~65) winsize 62
3155 11:08:18.053052 [CA 5] Center 33 (4~63) winsize 60
3156 11:08:18.053136
3157 11:08:18.056317 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3158 11:08:18.056471
3159 11:08:18.059594 [CATrainingPosCal] consider 2 rank data
3160 11:08:18.062827 u2DelayCellTimex100 = 270/100 ps
3161 11:08:18.066186 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3162 11:08:18.069486 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3163 11:08:18.076155 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3164 11:08:18.079389 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3165 11:08:18.082650 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3166 11:08:18.086672 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3167 11:08:18.086782
3168 11:08:18.089832 CA PerBit enable=1, Macro0, CA PI delay=33
3169 11:08:18.089916
3170 11:08:18.092902 [CBTSetCACLKResult] CA Dly = 33
3171 11:08:18.092986 CS Dly: 8 (0~40)
3172 11:08:18.093052
3173 11:08:18.096543 ----->DramcWriteLeveling(PI) begin...
3174 11:08:18.096627 ==
3175 11:08:18.099655 Dram Type= 6, Freq= 0, CH_1, rank 0
3176 11:08:18.106491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3177 11:08:18.106575 ==
3178 11:08:18.110093 Write leveling (Byte 0): 25 => 25
3179 11:08:18.112914 Write leveling (Byte 1): 27 => 27
3180 11:08:18.113043 DramcWriteLeveling(PI) end<-----
3181 11:08:18.116683
3182 11:08:18.116808 ==
3183 11:08:18.119707 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 11:08:18.123429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 11:08:18.123536 ==
3186 11:08:18.126330 [Gating] SW mode calibration
3187 11:08:18.133430 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3188 11:08:18.136739 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3189 11:08:18.143436 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 11:08:18.146686 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 11:08:18.149930 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 11:08:18.156544 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 11:08:18.159567 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 11:08:18.163558 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 11:08:18.169482 0 15 24 | B1->B0 | 3232 2c2c | 0 0 | (0 1) (0 1)
3196 11:08:18.172896 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3197 11:08:18.176166 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 11:08:18.182885 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 11:08:18.186254 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 11:08:18.189574 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 11:08:18.196246 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 11:08:18.200175 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3203 11:08:18.203329 1 0 24 | B1->B0 | 3a3a 4242 | 0 1 | (0 0) (0 0)
3204 11:08:18.206645 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 11:08:18.212946 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 11:08:18.216659 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 11:08:18.220088 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 11:08:18.226710 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 11:08:18.229912 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 11:08:18.233382 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 11:08:18.239745 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3212 11:08:18.243093 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3213 11:08:18.246549 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 11:08:18.252968 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 11:08:18.256792 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 11:08:18.259803 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 11:08:18.266597 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 11:08:18.270222 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 11:08:18.273597 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 11:08:18.280146 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 11:08:18.283493 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 11:08:18.286951 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 11:08:18.290141 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 11:08:18.296900 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 11:08:18.300127 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 11:08:18.303567 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 11:08:18.310061 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3228 11:08:18.313305 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3229 11:08:18.316691 Total UI for P1: 0, mck2ui 16
3230 11:08:18.319939 best dqsien dly found for B0: ( 1, 3, 24)
3231 11:08:18.323346 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3232 11:08:18.326752 Total UI for P1: 0, mck2ui 16
3233 11:08:18.330459 best dqsien dly found for B1: ( 1, 3, 26)
3234 11:08:18.333641 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3235 11:08:18.336607 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3236 11:08:18.336690
3237 11:08:18.340110 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3238 11:08:18.346865 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3239 11:08:18.346984 [Gating] SW calibration Done
3240 11:08:18.347085 ==
3241 11:08:18.350648 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 11:08:18.357120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 11:08:18.357205 ==
3244 11:08:18.357271 RX Vref Scan: 0
3245 11:08:18.357332
3246 11:08:18.360184 RX Vref 0 -> 0, step: 1
3247 11:08:18.360309
3248 11:08:18.363581 RX Delay -40 -> 252, step: 8
3249 11:08:18.367122 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3250 11:08:18.370709 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3251 11:08:18.374111 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3252 11:08:18.377435 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3253 11:08:18.384061 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3254 11:08:18.387371 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3255 11:08:18.390800 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3256 11:08:18.393821 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3257 11:08:18.397224 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3258 11:08:18.403728 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3259 11:08:18.407115 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3260 11:08:18.410288 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3261 11:08:18.414012 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3262 11:08:18.417279 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3263 11:08:18.423829 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3264 11:08:18.427120 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3265 11:08:18.427207 ==
3266 11:08:18.430532 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 11:08:18.433831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 11:08:18.433914 ==
3269 11:08:18.437011 DQS Delay:
3270 11:08:18.437086 DQS0 = 0, DQS1 = 0
3271 11:08:18.437162 DQM Delay:
3272 11:08:18.440274 DQM0 = 119, DQM1 = 116
3273 11:08:18.440361 DQ Delay:
3274 11:08:18.443618 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3275 11:08:18.447326 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3276 11:08:18.453887 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3277 11:08:18.457161 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3278 11:08:18.457266
3279 11:08:18.457359
3280 11:08:18.457447 ==
3281 11:08:18.460449 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 11:08:18.463570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 11:08:18.463656 ==
3284 11:08:18.463752
3285 11:08:18.463841
3286 11:08:18.467250 TX Vref Scan disable
3287 11:08:18.467363 == TX Byte 0 ==
3288 11:08:18.473649 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3289 11:08:18.477459 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3290 11:08:18.477583 == TX Byte 1 ==
3291 11:08:18.484005 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3292 11:08:18.487167 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3293 11:08:18.487328 ==
3294 11:08:18.490566 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 11:08:18.494010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 11:08:18.494136 ==
3297 11:08:18.506281 TX Vref=22, minBit 11, minWin=24, winSum=412
3298 11:08:18.509678 TX Vref=24, minBit 10, minWin=25, winSum=417
3299 11:08:18.512909 TX Vref=26, minBit 9, minWin=25, winSum=423
3300 11:08:18.516238 TX Vref=28, minBit 1, minWin=26, winSum=426
3301 11:08:18.519658 TX Vref=30, minBit 9, minWin=26, winSum=432
3302 11:08:18.526562 TX Vref=32, minBit 10, minWin=25, winSum=428
3303 11:08:18.529926 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 30
3304 11:08:18.530055
3305 11:08:18.533168 Final TX Range 1 Vref 30
3306 11:08:18.533253
3307 11:08:18.533331 ==
3308 11:08:18.536419 Dram Type= 6, Freq= 0, CH_1, rank 0
3309 11:08:18.539641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3310 11:08:18.539750 ==
3311 11:08:18.542921
3312 11:08:18.542994
3313 11:08:18.543055 TX Vref Scan disable
3314 11:08:18.547059 == TX Byte 0 ==
3315 11:08:18.549758 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3316 11:08:18.553045 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3317 11:08:18.556371 == TX Byte 1 ==
3318 11:08:18.560265 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3319 11:08:18.563228 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3320 11:08:18.566657
3321 11:08:18.566797 [DATLAT]
3322 11:08:18.566913 Freq=1200, CH1 RK0
3323 11:08:18.567037
3324 11:08:18.570188 DATLAT Default: 0xd
3325 11:08:18.570319 0, 0xFFFF, sum = 0
3326 11:08:18.573443 1, 0xFFFF, sum = 0
3327 11:08:18.573576 2, 0xFFFF, sum = 0
3328 11:08:18.576506 3, 0xFFFF, sum = 0
3329 11:08:18.576641 4, 0xFFFF, sum = 0
3330 11:08:18.580032 5, 0xFFFF, sum = 0
3331 11:08:18.580161 6, 0xFFFF, sum = 0
3332 11:08:18.582984 7, 0xFFFF, sum = 0
3333 11:08:18.586772 8, 0xFFFF, sum = 0
3334 11:08:18.586909 9, 0xFFFF, sum = 0
3335 11:08:18.589965 10, 0xFFFF, sum = 0
3336 11:08:18.590099 11, 0xFFFF, sum = 0
3337 11:08:18.593179 12, 0x0, sum = 1
3338 11:08:18.593309 13, 0x0, sum = 2
3339 11:08:18.596656 14, 0x0, sum = 3
3340 11:08:18.596790 15, 0x0, sum = 4
3341 11:08:18.596915 best_step = 13
3342 11:08:18.597031
3343 11:08:18.599828 ==
3344 11:08:18.599938 Dram Type= 6, Freq= 0, CH_1, rank 0
3345 11:08:18.606644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3346 11:08:18.606778 ==
3347 11:08:18.606896 RX Vref Scan: 1
3348 11:08:18.607017
3349 11:08:18.610294 Set Vref Range= 32 -> 127
3350 11:08:18.610398
3351 11:08:18.613237 RX Vref 32 -> 127, step: 1
3352 11:08:18.613318
3353 11:08:18.617029 RX Delay -5 -> 252, step: 4
3354 11:08:18.617110
3355 11:08:18.620025 Set Vref, RX VrefLevel [Byte0]: 32
3356 11:08:18.623290 [Byte1]: 32
3357 11:08:18.623396
3358 11:08:18.627116 Set Vref, RX VrefLevel [Byte0]: 33
3359 11:08:18.630337 [Byte1]: 33
3360 11:08:18.630417
3361 11:08:18.633571 Set Vref, RX VrefLevel [Byte0]: 34
3362 11:08:18.637006 [Byte1]: 34
3363 11:08:18.640249
3364 11:08:18.640348 Set Vref, RX VrefLevel [Byte0]: 35
3365 11:08:18.644020 [Byte1]: 35
3366 11:08:18.648662
3367 11:08:18.648742 Set Vref, RX VrefLevel [Byte0]: 36
3368 11:08:18.651927 [Byte1]: 36
3369 11:08:18.656659
3370 11:08:18.656737 Set Vref, RX VrefLevel [Byte0]: 37
3371 11:08:18.659223 [Byte1]: 37
3372 11:08:18.663872
3373 11:08:18.663954 Set Vref, RX VrefLevel [Byte0]: 38
3374 11:08:18.667263 [Byte1]: 38
3375 11:08:18.672266
3376 11:08:18.672359 Set Vref, RX VrefLevel [Byte0]: 39
3377 11:08:18.675241 [Byte1]: 39
3378 11:08:18.679949
3379 11:08:18.680057 Set Vref, RX VrefLevel [Byte0]: 40
3380 11:08:18.683241 [Byte1]: 40
3381 11:08:18.687620
3382 11:08:18.687702 Set Vref, RX VrefLevel [Byte0]: 41
3383 11:08:18.691183 [Byte1]: 41
3384 11:08:18.695524
3385 11:08:18.695607 Set Vref, RX VrefLevel [Byte0]: 42
3386 11:08:18.698630 [Byte1]: 42
3387 11:08:18.703273
3388 11:08:18.703354 Set Vref, RX VrefLevel [Byte0]: 43
3389 11:08:18.706600 [Byte1]: 43
3390 11:08:18.711347
3391 11:08:18.711429 Set Vref, RX VrefLevel [Byte0]: 44
3392 11:08:18.714689 [Byte1]: 44
3393 11:08:18.719247
3394 11:08:18.719345 Set Vref, RX VrefLevel [Byte0]: 45
3395 11:08:18.722336 [Byte1]: 45
3396 11:08:18.727130
3397 11:08:18.727212 Set Vref, RX VrefLevel [Byte0]: 46
3398 11:08:18.730071 [Byte1]: 46
3399 11:08:18.734663
3400 11:08:18.734740 Set Vref, RX VrefLevel [Byte0]: 47
3401 11:08:18.738210 [Byte1]: 47
3402 11:08:18.742455
3403 11:08:18.742557 Set Vref, RX VrefLevel [Byte0]: 48
3404 11:08:18.746285 [Byte1]: 48
3405 11:08:18.750183
3406 11:08:18.750265 Set Vref, RX VrefLevel [Byte0]: 49
3407 11:08:18.753541 [Byte1]: 49
3408 11:08:18.758328
3409 11:08:18.758410 Set Vref, RX VrefLevel [Byte0]: 50
3410 11:08:18.761664 [Byte1]: 50
3411 11:08:18.766270
3412 11:08:18.766352 Set Vref, RX VrefLevel [Byte0]: 51
3413 11:08:18.769601 [Byte1]: 51
3414 11:08:18.774185
3415 11:08:18.774267 Set Vref, RX VrefLevel [Byte0]: 52
3416 11:08:18.777655 [Byte1]: 52
3417 11:08:18.782200
3418 11:08:18.782282 Set Vref, RX VrefLevel [Byte0]: 53
3419 11:08:18.785317 [Byte1]: 53
3420 11:08:18.789509
3421 11:08:18.789591 Set Vref, RX VrefLevel [Byte0]: 54
3422 11:08:18.792934 [Byte1]: 54
3423 11:08:18.797304
3424 11:08:18.797430 Set Vref, RX VrefLevel [Byte0]: 55
3425 11:08:18.800769 [Byte1]: 55
3426 11:08:18.805608
3427 11:08:18.805736 Set Vref, RX VrefLevel [Byte0]: 56
3428 11:08:18.808539 [Byte1]: 56
3429 11:08:18.813581
3430 11:08:18.813709 Set Vref, RX VrefLevel [Byte0]: 57
3431 11:08:18.816888 [Byte1]: 57
3432 11:08:18.820854
3433 11:08:18.820983 Set Vref, RX VrefLevel [Byte0]: 58
3434 11:08:18.824392 [Byte1]: 58
3435 11:08:18.828909
3436 11:08:18.829038 Set Vref, RX VrefLevel [Byte0]: 59
3437 11:08:18.832084 [Byte1]: 59
3438 11:08:18.836622
3439 11:08:18.836747 Set Vref, RX VrefLevel [Byte0]: 60
3440 11:08:18.839948 [Byte1]: 60
3441 11:08:18.844785
3442 11:08:18.844891 Set Vref, RX VrefLevel [Byte0]: 61
3443 11:08:18.847948 [Byte1]: 61
3444 11:08:18.852616
3445 11:08:18.852700 Set Vref, RX VrefLevel [Byte0]: 62
3446 11:08:18.858931 [Byte1]: 62
3447 11:08:18.859017
3448 11:08:18.862359 Set Vref, RX VrefLevel [Byte0]: 63
3449 11:08:18.865534 [Byte1]: 63
3450 11:08:18.865663
3451 11:08:18.868950 Set Vref, RX VrefLevel [Byte0]: 64
3452 11:08:18.872249 [Byte1]: 64
3453 11:08:18.876153
3454 11:08:18.876274 Set Vref, RX VrefLevel [Byte0]: 65
3455 11:08:18.879529 [Byte1]: 65
3456 11:08:18.884032
3457 11:08:18.884144 Set Vref, RX VrefLevel [Byte0]: 66
3458 11:08:18.887300 [Byte1]: 66
3459 11:08:18.891807
3460 11:08:18.891931 Set Vref, RX VrefLevel [Byte0]: 67
3461 11:08:18.895193 [Byte1]: 67
3462 11:08:18.899747
3463 11:08:18.899858 Set Vref, RX VrefLevel [Byte0]: 68
3464 11:08:18.902973 [Byte1]: 68
3465 11:08:18.907575
3466 11:08:18.907659 Set Vref, RX VrefLevel [Byte0]: 69
3467 11:08:18.910586 [Byte1]: 69
3468 11:08:18.915346
3469 11:08:18.915430 Set Vref, RX VrefLevel [Byte0]: 70
3470 11:08:18.918316 [Byte1]: 70
3471 11:08:18.923357
3472 11:08:18.923441 Final RX Vref Byte 0 = 53 to rank0
3473 11:08:18.926751 Final RX Vref Byte 1 = 48 to rank0
3474 11:08:18.929772 Final RX Vref Byte 0 = 53 to rank1
3475 11:08:18.933032 Final RX Vref Byte 1 = 48 to rank1==
3476 11:08:18.936764 Dram Type= 6, Freq= 0, CH_1, rank 0
3477 11:08:18.943116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3478 11:08:18.943208 ==
3479 11:08:18.943277 DQS Delay:
3480 11:08:18.943339 DQS0 = 0, DQS1 = 0
3481 11:08:18.946278 DQM Delay:
3482 11:08:18.946361 DQM0 = 119, DQM1 = 116
3483 11:08:18.949578 DQ Delay:
3484 11:08:18.952992 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =116
3485 11:08:18.956312 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3486 11:08:18.960270 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3487 11:08:18.963330 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3488 11:08:18.963417
3489 11:08:18.963484
3490 11:08:18.969827 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3491 11:08:18.973333 CH1 RK0: MR19=404, MR18=215
3492 11:08:18.980308 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3493 11:08:18.980396
3494 11:08:18.982899 ----->DramcWriteLeveling(PI) begin...
3495 11:08:18.982985 ==
3496 11:08:18.987034 Dram Type= 6, Freq= 0, CH_1, rank 1
3497 11:08:18.989707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3498 11:08:18.989793 ==
3499 11:08:18.993078 Write leveling (Byte 0): 26 => 26
3500 11:08:18.996865 Write leveling (Byte 1): 29 => 29
3501 11:08:19.000163 DramcWriteLeveling(PI) end<-----
3502 11:08:19.000273
3503 11:08:19.000353 ==
3504 11:08:19.003571 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 11:08:19.006816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 11:08:19.009987 ==
3507 11:08:19.010072 [Gating] SW mode calibration
3508 11:08:19.016619 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3509 11:08:19.023595 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3510 11:08:19.026731 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3511 11:08:19.033869 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 11:08:19.036995 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 11:08:19.040351 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 11:08:19.046760 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 11:08:19.050278 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
3516 11:08:19.053621 0 15 24 | B1->B0 | 2929 3232 | 0 1 | (1 0) (1 0)
3517 11:08:19.057164 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3518 11:08:19.063825 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 11:08:19.067298 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 11:08:19.070512 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 11:08:19.076769 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 11:08:19.080508 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 11:08:19.083886 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3524 11:08:19.090431 1 0 24 | B1->B0 | 4646 3434 | 0 0 | (0 0) (0 0)
3525 11:08:19.093895 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3526 11:08:19.096771 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 11:08:19.103337 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 11:08:19.107308 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 11:08:19.110630 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 11:08:19.117177 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 11:08:19.120573 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3532 11:08:19.123473 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3533 11:08:19.130380 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3534 11:08:19.133821 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 11:08:19.137156 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 11:08:19.143487 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 11:08:19.147210 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 11:08:19.150294 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 11:08:19.156833 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 11:08:19.160359 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 11:08:19.163300 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 11:08:19.166694 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 11:08:19.173301 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 11:08:19.176593 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 11:08:19.180026 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 11:08:19.186665 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 11:08:19.189805 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 11:08:19.193461 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3549 11:08:19.200199 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3550 11:08:19.203259 Total UI for P1: 0, mck2ui 16
3551 11:08:19.206610 best dqsien dly found for B1: ( 1, 3, 24)
3552 11:08:19.209649 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3553 11:08:19.213123 Total UI for P1: 0, mck2ui 16
3554 11:08:19.216400 best dqsien dly found for B0: ( 1, 3, 26)
3555 11:08:19.219676 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3556 11:08:19.223044 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3557 11:08:19.223132
3558 11:08:19.226344 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3559 11:08:19.232814 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3560 11:08:19.232902 [Gating] SW calibration Done
3561 11:08:19.232991 ==
3562 11:08:19.236630 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 11:08:19.243182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 11:08:19.243297 ==
3565 11:08:19.243392 RX Vref Scan: 0
3566 11:08:19.243482
3567 11:08:19.246310 RX Vref 0 -> 0, step: 1
3568 11:08:19.246411
3569 11:08:19.249493 RX Delay -40 -> 252, step: 8
3570 11:08:19.252677 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3571 11:08:19.255954 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3572 11:08:19.259219 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3573 11:08:19.266371 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3574 11:08:19.269615 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3575 11:08:19.272698 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3576 11:08:19.276273 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3577 11:08:19.279506 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3578 11:08:19.282749 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3579 11:08:19.289162 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3580 11:08:19.292549 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3581 11:08:19.295876 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3582 11:08:19.299020 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3583 11:08:19.305977 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3584 11:08:19.309301 iDelay=200, Bit 14, Center 119 (56 ~ 183) 128
3585 11:08:19.312395 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3586 11:08:19.312504 ==
3587 11:08:19.315982 Dram Type= 6, Freq= 0, CH_1, rank 1
3588 11:08:19.318912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3589 11:08:19.319025 ==
3590 11:08:19.322592 DQS Delay:
3591 11:08:19.322684 DQS0 = 0, DQS1 = 0
3592 11:08:19.325799 DQM Delay:
3593 11:08:19.325905 DQM0 = 120, DQM1 = 117
3594 11:08:19.329186 DQ Delay:
3595 11:08:19.332594 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3596 11:08:19.335772 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3597 11:08:19.338867 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3598 11:08:19.342017 DQ12 =127, DQ13 =127, DQ14 =119, DQ15 =123
3599 11:08:19.342095
3600 11:08:19.342158
3601 11:08:19.342235 ==
3602 11:08:19.345485 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 11:08:19.349363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 11:08:19.349445 ==
3605 11:08:19.349508
3606 11:08:19.349567
3607 11:08:19.352525 TX Vref Scan disable
3608 11:08:19.355741 == TX Byte 0 ==
3609 11:08:19.359375 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3610 11:08:19.362527 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3611 11:08:19.365823 == TX Byte 1 ==
3612 11:08:19.369136 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3613 11:08:19.372404 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3614 11:08:19.372502 ==
3615 11:08:19.375642 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 11:08:19.378965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 11:08:19.382255 ==
3618 11:08:19.392423 TX Vref=22, minBit 9, minWin=25, winSum=418
3619 11:08:19.395699 TX Vref=24, minBit 10, minWin=25, winSum=427
3620 11:08:19.399198 TX Vref=26, minBit 2, minWin=26, winSum=433
3621 11:08:19.402177 TX Vref=28, minBit 8, minWin=26, winSum=432
3622 11:08:19.405453 TX Vref=30, minBit 9, minWin=26, winSum=436
3623 11:08:19.412801 TX Vref=32, minBit 9, minWin=26, winSum=436
3624 11:08:19.415315 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
3625 11:08:19.415403
3626 11:08:19.420087 Final TX Range 1 Vref 30
3627 11:08:19.420217
3628 11:08:19.420344 ==
3629 11:08:19.421941 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 11:08:19.425747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 11:08:19.428794 ==
3632 11:08:19.428920
3633 11:08:19.429032
3634 11:08:19.429143 TX Vref Scan disable
3635 11:08:19.432199 == TX Byte 0 ==
3636 11:08:19.435124 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3637 11:08:19.441958 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3638 11:08:19.442085 == TX Byte 1 ==
3639 11:08:19.445151 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3640 11:08:19.449102 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3641 11:08:19.452419
3642 11:08:19.452542 [DATLAT]
3643 11:08:19.452656 Freq=1200, CH1 RK1
3644 11:08:19.452767
3645 11:08:19.455265 DATLAT Default: 0xd
3646 11:08:19.455385 0, 0xFFFF, sum = 0
3647 11:08:19.458508 1, 0xFFFF, sum = 0
3648 11:08:19.458634 2, 0xFFFF, sum = 0
3649 11:08:19.462294 3, 0xFFFF, sum = 0
3650 11:08:19.465309 4, 0xFFFF, sum = 0
3651 11:08:19.465439 5, 0xFFFF, sum = 0
3652 11:08:19.468615 6, 0xFFFF, sum = 0
3653 11:08:19.468737 7, 0xFFFF, sum = 0
3654 11:08:19.471798 8, 0xFFFF, sum = 0
3655 11:08:19.471920 9, 0xFFFF, sum = 0
3656 11:08:19.475120 10, 0xFFFF, sum = 0
3657 11:08:19.475247 11, 0xFFFF, sum = 0
3658 11:08:19.478659 12, 0x0, sum = 1
3659 11:08:19.478784 13, 0x0, sum = 2
3660 11:08:19.481993 14, 0x0, sum = 3
3661 11:08:19.482115 15, 0x0, sum = 4
3662 11:08:19.482232 best_step = 13
3663 11:08:19.482343
3664 11:08:19.485439 ==
3665 11:08:19.488727 Dram Type= 6, Freq= 0, CH_1, rank 1
3666 11:08:19.492017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3667 11:08:19.492141 ==
3668 11:08:19.492256 RX Vref Scan: 0
3669 11:08:19.492378
3670 11:08:19.495320 RX Vref 0 -> 0, step: 1
3671 11:08:19.495443
3672 11:08:19.498551 RX Delay -5 -> 252, step: 4
3673 11:08:19.501912 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3674 11:08:19.509032 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3675 11:08:19.512148 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3676 11:08:19.515368 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3677 11:08:19.518649 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3678 11:08:19.522192 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3679 11:08:19.525298 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3680 11:08:19.532253 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3681 11:08:19.535227 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3682 11:08:19.539069 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3683 11:08:19.542156 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3684 11:08:19.545283 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3685 11:08:19.551732 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3686 11:08:19.555031 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3687 11:08:19.558676 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3688 11:08:19.561794 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3689 11:08:19.561872 ==
3690 11:08:19.565174 Dram Type= 6, Freq= 0, CH_1, rank 1
3691 11:08:19.571919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3692 11:08:19.572027 ==
3693 11:08:19.572135 DQS Delay:
3694 11:08:19.575037 DQS0 = 0, DQS1 = 0
3695 11:08:19.575136 DQM Delay:
3696 11:08:19.578367 DQM0 = 120, DQM1 = 116
3697 11:08:19.578470 DQ Delay:
3698 11:08:19.582311 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3699 11:08:19.585631 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3700 11:08:19.588943 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3701 11:08:19.591661 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3702 11:08:19.591762
3703 11:08:19.591857
3704 11:08:19.601661 [DQSOSCAuto] RK1, (LSB)MR18= 0x14f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3705 11:08:19.601751 CH1 RK1: MR19=403, MR18=14F1
3706 11:08:19.608904 CH1_RK1: MR19=0x403, MR18=0x14F1, DQSOSC=402, MR23=63, INC=40, DEC=27
3707 11:08:19.611659 [RxdqsGatingPostProcess] freq 1200
3708 11:08:19.618267 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3709 11:08:19.621702 best DQS0 dly(2T, 0.5T) = (0, 11)
3710 11:08:19.625397 best DQS1 dly(2T, 0.5T) = (0, 11)
3711 11:08:19.628548 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3712 11:08:19.631553 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3713 11:08:19.635097 best DQS0 dly(2T, 0.5T) = (0, 11)
3714 11:08:19.635180 best DQS1 dly(2T, 0.5T) = (0, 11)
3715 11:08:19.638245 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3716 11:08:19.641751 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3717 11:08:19.644740 Pre-setting of DQS Precalculation
3718 11:08:19.651704 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3719 11:08:19.658243 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3720 11:08:19.664731 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3721 11:08:19.664811
3722 11:08:19.664875
3723 11:08:19.668302 [Calibration Summary] 2400 Mbps
3724 11:08:19.671690 CH 0, Rank 0
3725 11:08:19.671797 SW Impedance : PASS
3726 11:08:19.674896 DUTY Scan : NO K
3727 11:08:19.678356 ZQ Calibration : PASS
3728 11:08:19.678463 Jitter Meter : NO K
3729 11:08:19.681510 CBT Training : PASS
3730 11:08:19.681612 Write leveling : PASS
3731 11:08:19.684856 RX DQS gating : PASS
3732 11:08:19.687866 RX DQ/DQS(RDDQC) : PASS
3733 11:08:19.687978 TX DQ/DQS : PASS
3734 11:08:19.691257 RX DATLAT : PASS
3735 11:08:19.694631 RX DQ/DQS(Engine): PASS
3736 11:08:19.694737 TX OE : NO K
3737 11:08:19.697968 All Pass.
3738 11:08:19.698043
3739 11:08:19.698105 CH 0, Rank 1
3740 11:08:19.701228 SW Impedance : PASS
3741 11:08:19.701330 DUTY Scan : NO K
3742 11:08:19.704663 ZQ Calibration : PASS
3743 11:08:19.707892 Jitter Meter : NO K
3744 11:08:19.707990 CBT Training : PASS
3745 11:08:19.711275 Write leveling : PASS
3746 11:08:19.714624 RX DQS gating : PASS
3747 11:08:19.714739 RX DQ/DQS(RDDQC) : PASS
3748 11:08:19.717851 TX DQ/DQS : PASS
3749 11:08:19.721232 RX DATLAT : PASS
3750 11:08:19.721362 RX DQ/DQS(Engine): PASS
3751 11:08:19.724685 TX OE : NO K
3752 11:08:19.724770 All Pass.
3753 11:08:19.724835
3754 11:08:19.727660 CH 1, Rank 0
3755 11:08:19.727744 SW Impedance : PASS
3756 11:08:19.731450 DUTY Scan : NO K
3757 11:08:19.734420 ZQ Calibration : PASS
3758 11:08:19.734548 Jitter Meter : NO K
3759 11:08:19.737661 CBT Training : PASS
3760 11:08:19.741121 Write leveling : PASS
3761 11:08:19.741245 RX DQS gating : PASS
3762 11:08:19.744248 RX DQ/DQS(RDDQC) : PASS
3763 11:08:19.744377 TX DQ/DQS : PASS
3764 11:08:19.747765 RX DATLAT : PASS
3765 11:08:19.750857 RX DQ/DQS(Engine): PASS
3766 11:08:19.750943 TX OE : NO K
3767 11:08:19.754315 All Pass.
3768 11:08:19.754442
3769 11:08:19.754556 CH 1, Rank 1
3770 11:08:19.757597 SW Impedance : PASS
3771 11:08:19.757718 DUTY Scan : NO K
3772 11:08:19.761307 ZQ Calibration : PASS
3773 11:08:19.764174 Jitter Meter : NO K
3774 11:08:19.764307 CBT Training : PASS
3775 11:08:19.767848 Write leveling : PASS
3776 11:08:19.771186 RX DQS gating : PASS
3777 11:08:19.771303 RX DQ/DQS(RDDQC) : PASS
3778 11:08:19.774533 TX DQ/DQS : PASS
3779 11:08:19.777597 RX DATLAT : PASS
3780 11:08:19.777690 RX DQ/DQS(Engine): PASS
3781 11:08:19.780716 TX OE : NO K
3782 11:08:19.780825 All Pass.
3783 11:08:19.780923
3784 11:08:19.784263 DramC Write-DBI off
3785 11:08:19.787662 PER_BANK_REFRESH: Hybrid Mode
3786 11:08:19.787738 TX_TRACKING: ON
3787 11:08:19.797316 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3788 11:08:19.800631 [FAST_K] Save calibration result to emmc
3789 11:08:19.803752 dramc_set_vcore_voltage set vcore to 650000
3790 11:08:19.807566 Read voltage for 600, 5
3791 11:08:19.807694 Vio18 = 0
3792 11:08:19.807809 Vcore = 650000
3793 11:08:19.810916 Vdram = 0
3794 11:08:19.811038 Vddq = 0
3795 11:08:19.811147 Vmddr = 0
3796 11:08:19.817447 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3797 11:08:19.820773 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3798 11:08:19.824166 MEM_TYPE=3, freq_sel=19
3799 11:08:19.827486 sv_algorithm_assistance_LP4_1600
3800 11:08:19.830164 ============ PULL DRAM RESETB DOWN ============
3801 11:08:19.834016 ========== PULL DRAM RESETB DOWN end =========
3802 11:08:19.840531 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3803 11:08:19.843489 ===================================
3804 11:08:19.846863 LPDDR4 DRAM CONFIGURATION
3805 11:08:19.850032 ===================================
3806 11:08:19.850138 EX_ROW_EN[0] = 0x0
3807 11:08:19.853392 EX_ROW_EN[1] = 0x0
3808 11:08:19.853472 LP4Y_EN = 0x0
3809 11:08:19.856547 WORK_FSP = 0x0
3810 11:08:19.856646 WL = 0x2
3811 11:08:19.859960 RL = 0x2
3812 11:08:19.860042 BL = 0x2
3813 11:08:19.863700 RPST = 0x0
3814 11:08:19.863810 RD_PRE = 0x0
3815 11:08:19.866941 WR_PRE = 0x1
3816 11:08:19.867029 WR_PST = 0x0
3817 11:08:19.870221 DBI_WR = 0x0
3818 11:08:19.870338 DBI_RD = 0x0
3819 11:08:19.873433 OTF = 0x1
3820 11:08:19.876263 ===================================
3821 11:08:19.879766 ===================================
3822 11:08:19.879877 ANA top config
3823 11:08:19.883055 ===================================
3824 11:08:19.886366 DLL_ASYNC_EN = 0
3825 11:08:19.889623 ALL_SLAVE_EN = 1
3826 11:08:19.892909 NEW_RANK_MODE = 1
3827 11:08:19.896308 DLL_IDLE_MODE = 1
3828 11:08:19.896422 LP45_APHY_COMB_EN = 1
3829 11:08:19.899561 TX_ODT_DIS = 1
3830 11:08:19.903280 NEW_8X_MODE = 1
3831 11:08:19.906325 ===================================
3832 11:08:19.909732 ===================================
3833 11:08:19.913015 data_rate = 1200
3834 11:08:19.916247 CKR = 1
3835 11:08:19.916362 DQ_P2S_RATIO = 8
3836 11:08:19.919831 ===================================
3837 11:08:19.922872 CA_P2S_RATIO = 8
3838 11:08:19.926104 DQ_CA_OPEN = 0
3839 11:08:19.929435 DQ_SEMI_OPEN = 0
3840 11:08:19.932636 CA_SEMI_OPEN = 0
3841 11:08:19.935902 CA_FULL_RATE = 0
3842 11:08:19.935986 DQ_CKDIV4_EN = 1
3843 11:08:19.939303 CA_CKDIV4_EN = 1
3844 11:08:19.942526 CA_PREDIV_EN = 0
3845 11:08:19.946498 PH8_DLY = 0
3846 11:08:19.949658 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3847 11:08:19.952670 DQ_AAMCK_DIV = 4
3848 11:08:19.952784 CA_AAMCK_DIV = 4
3849 11:08:19.956253 CA_ADMCK_DIV = 4
3850 11:08:19.959527 DQ_TRACK_CA_EN = 0
3851 11:08:19.962869 CA_PICK = 600
3852 11:08:19.965960 CA_MCKIO = 600
3853 11:08:19.969216 MCKIO_SEMI = 0
3854 11:08:19.972480 PLL_FREQ = 2288
3855 11:08:19.972592 DQ_UI_PI_RATIO = 32
3856 11:08:19.975895 CA_UI_PI_RATIO = 0
3857 11:08:19.979180 ===================================
3858 11:08:19.982345 ===================================
3859 11:08:19.985829 memory_type:LPDDR4
3860 11:08:19.989602 GP_NUM : 10
3861 11:08:19.989685 SRAM_EN : 1
3862 11:08:19.992522 MD32_EN : 0
3863 11:08:19.996061 ===================================
3864 11:08:19.999390 [ANA_INIT] >>>>>>>>>>>>>>
3865 11:08:19.999469 <<<<<< [CONFIGURE PHASE]: ANA_TX
3866 11:08:20.002776 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3867 11:08:20.006254 ===================================
3868 11:08:20.008872 data_rate = 1200,PCW = 0X5800
3869 11:08:20.012146 ===================================
3870 11:08:20.015627 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3871 11:08:20.022639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3872 11:08:20.029178 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3873 11:08:20.032712 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3874 11:08:20.036173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3875 11:08:20.039428 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3876 11:08:20.042269 [ANA_INIT] flow start
3877 11:08:20.042352 [ANA_INIT] PLL >>>>>>>>
3878 11:08:20.045826 [ANA_INIT] PLL <<<<<<<<
3879 11:08:20.049375 [ANA_INIT] MIDPI >>>>>>>>
3880 11:08:20.049483 [ANA_INIT] MIDPI <<<<<<<<
3881 11:08:20.052700 [ANA_INIT] DLL >>>>>>>>
3882 11:08:20.055823 [ANA_INIT] flow end
3883 11:08:20.059377 ============ LP4 DIFF to SE enter ============
3884 11:08:20.062421 ============ LP4 DIFF to SE exit ============
3885 11:08:20.065683 [ANA_INIT] <<<<<<<<<<<<<
3886 11:08:20.068999 [Flow] Enable top DCM control >>>>>
3887 11:08:20.072246 [Flow] Enable top DCM control <<<<<
3888 11:08:20.075399 Enable DLL master slave shuffle
3889 11:08:20.078751 ==============================================================
3890 11:08:20.082111 Gating Mode config
3891 11:08:20.088746 ==============================================================
3892 11:08:20.088863 Config description:
3893 11:08:20.098574 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3894 11:08:20.105327 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3895 11:08:20.112421 SELPH_MODE 0: By rank 1: By Phase
3896 11:08:20.114990 ==============================================================
3897 11:08:20.119140 GAT_TRACK_EN = 1
3898 11:08:20.122231 RX_GATING_MODE = 2
3899 11:08:20.125688 RX_GATING_TRACK_MODE = 2
3900 11:08:20.128542 SELPH_MODE = 1
3901 11:08:20.132378 PICG_EARLY_EN = 1
3902 11:08:20.135495 VALID_LAT_VALUE = 1
3903 11:08:20.138846 ==============================================================
3904 11:08:20.142236 Enter into Gating configuration >>>>
3905 11:08:20.145440 Exit from Gating configuration <<<<
3906 11:08:20.148701 Enter into DVFS_PRE_config >>>>>
3907 11:08:20.161724 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3908 11:08:20.161816 Exit from DVFS_PRE_config <<<<<
3909 11:08:20.165651 Enter into PICG configuration >>>>
3910 11:08:20.168758 Exit from PICG configuration <<<<
3911 11:08:20.171944 [RX_INPUT] configuration >>>>>
3912 11:08:20.175168 [RX_INPUT] configuration <<<<<
3913 11:08:20.182039 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3914 11:08:20.185470 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3915 11:08:20.191851 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3916 11:08:20.199012 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3917 11:08:20.205155 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3918 11:08:20.212059 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3919 11:08:20.215110 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3920 11:08:20.218968 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3921 11:08:20.222081 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3922 11:08:20.228954 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3923 11:08:20.231703 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3924 11:08:20.235051 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3925 11:08:20.238862 ===================================
3926 11:08:20.242108 LPDDR4 DRAM CONFIGURATION
3927 11:08:20.245368 ===================================
3928 11:08:20.245452 EX_ROW_EN[0] = 0x0
3929 11:08:20.248642 EX_ROW_EN[1] = 0x0
3930 11:08:20.252033 LP4Y_EN = 0x0
3931 11:08:20.252116 WORK_FSP = 0x0
3932 11:08:20.255399 WL = 0x2
3933 11:08:20.255482 RL = 0x2
3934 11:08:20.258634 BL = 0x2
3935 11:08:20.258717 RPST = 0x0
3936 11:08:20.261889 RD_PRE = 0x0
3937 11:08:20.261976 WR_PRE = 0x1
3938 11:08:20.265061 WR_PST = 0x0
3939 11:08:20.265147 DBI_WR = 0x0
3940 11:08:20.268397 DBI_RD = 0x0
3941 11:08:20.268482 OTF = 0x1
3942 11:08:20.272128 ===================================
3943 11:08:20.275240 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3944 11:08:20.282047 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3945 11:08:20.285236 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3946 11:08:20.288612 ===================================
3947 11:08:20.292180 LPDDR4 DRAM CONFIGURATION
3948 11:08:20.295399 ===================================
3949 11:08:20.295491 EX_ROW_EN[0] = 0x10
3950 11:08:20.298667 EX_ROW_EN[1] = 0x0
3951 11:08:20.298743 LP4Y_EN = 0x0
3952 11:08:20.301689 WORK_FSP = 0x0
3953 11:08:20.301804 WL = 0x2
3954 11:08:20.305014 RL = 0x2
3955 11:08:20.305119 BL = 0x2
3956 11:08:20.308701 RPST = 0x0
3957 11:08:20.311574 RD_PRE = 0x0
3958 11:08:20.311692 WR_PRE = 0x1
3959 11:08:20.314891 WR_PST = 0x0
3960 11:08:20.315010 DBI_WR = 0x0
3961 11:08:20.318760 DBI_RD = 0x0
3962 11:08:20.318873 OTF = 0x1
3963 11:08:20.322046 ===================================
3964 11:08:20.328199 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3965 11:08:20.331785 nWR fixed to 30
3966 11:08:20.335668 [ModeRegInit_LP4] CH0 RK0
3967 11:08:20.335783 [ModeRegInit_LP4] CH0 RK1
3968 11:08:20.338350 [ModeRegInit_LP4] CH1 RK0
3969 11:08:20.341727 [ModeRegInit_LP4] CH1 RK1
3970 11:08:20.341819 match AC timing 17
3971 11:08:20.348807 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3972 11:08:20.352221 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3973 11:08:20.355579 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3974 11:08:20.362192 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3975 11:08:20.365572 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3976 11:08:20.365662 ==
3977 11:08:20.368855 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 11:08:20.372109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3979 11:08:20.372195 ==
3980 11:08:20.378700 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3981 11:08:20.385030 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3982 11:08:20.388222 [CA 0] Center 36 (5~67) winsize 63
3983 11:08:20.391459 [CA 1] Center 36 (5~67) winsize 63
3984 11:08:20.394814 [CA 2] Center 34 (3~65) winsize 63
3985 11:08:20.398163 [CA 3] Center 33 (3~64) winsize 62
3986 11:08:20.401654 [CA 4] Center 33 (2~64) winsize 63
3987 11:08:20.404812 [CA 5] Center 32 (2~63) winsize 62
3988 11:08:20.404893
3989 11:08:20.408444 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3990 11:08:20.408546
3991 11:08:20.411588 [CATrainingPosCal] consider 1 rank data
3992 11:08:20.415354 u2DelayCellTimex100 = 270/100 ps
3993 11:08:20.418174 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3994 11:08:20.421630 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3995 11:08:20.425084 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3996 11:08:20.428481 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3997 11:08:20.431455 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3998 11:08:20.438380 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3999 11:08:20.438515
4000 11:08:20.441584 CA PerBit enable=1, Macro0, CA PI delay=32
4001 11:08:20.441710
4002 11:08:20.445140 [CBTSetCACLKResult] CA Dly = 32
4003 11:08:20.445225 CS Dly: 4 (0~35)
4004 11:08:20.445293 ==
4005 11:08:20.448560 Dram Type= 6, Freq= 0, CH_0, rank 1
4006 11:08:20.451657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 11:08:20.454738 ==
4008 11:08:20.458142 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4009 11:08:20.464815 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4010 11:08:20.468127 [CA 0] Center 35 (5~66) winsize 62
4011 11:08:20.471320 [CA 1] Center 35 (5~66) winsize 62
4012 11:08:20.475084 [CA 2] Center 34 (3~65) winsize 63
4013 11:08:20.478350 [CA 3] Center 34 (3~65) winsize 63
4014 11:08:20.481671 [CA 4] Center 33 (2~64) winsize 63
4015 11:08:20.484888 [CA 5] Center 32 (2~63) winsize 62
4016 11:08:20.485012
4017 11:08:20.488177 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4018 11:08:20.488314
4019 11:08:20.491367 [CATrainingPosCal] consider 2 rank data
4020 11:08:20.494604 u2DelayCellTimex100 = 270/100 ps
4021 11:08:20.497728 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4022 11:08:20.501622 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4023 11:08:20.505000 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4024 11:08:20.511520 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4025 11:08:20.514691 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4026 11:08:20.517913 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4027 11:08:20.518004
4028 11:08:20.521358 CA PerBit enable=1, Macro0, CA PI delay=32
4029 11:08:20.521456
4030 11:08:20.524608 [CBTSetCACLKResult] CA Dly = 32
4031 11:08:20.524689 CS Dly: 4 (0~36)
4032 11:08:20.524752
4033 11:08:20.527668 ----->DramcWriteLeveling(PI) begin...
4034 11:08:20.527768 ==
4035 11:08:20.531260 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 11:08:20.537470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 11:08:20.537549 ==
4038 11:08:20.541208 Write leveling (Byte 0): 33 => 33
4039 11:08:20.544436 Write leveling (Byte 1): 31 => 31
4040 11:08:20.544511 DramcWriteLeveling(PI) end<-----
4041 11:08:20.547563
4042 11:08:20.547659 ==
4043 11:08:20.550981 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 11:08:20.553945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 11:08:20.554047 ==
4046 11:08:20.557647 [Gating] SW mode calibration
4047 11:08:20.564414 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4048 11:08:20.567693 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4049 11:08:20.574453 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4050 11:08:20.577498 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4051 11:08:20.580823 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 11:08:20.587360 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 1)
4053 11:08:20.590691 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
4054 11:08:20.593941 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 11:08:20.600880 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 11:08:20.604194 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 11:08:20.607416 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 11:08:20.613961 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 11:08:20.617289 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4060 11:08:20.620751 0 10 12 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
4061 11:08:20.627535 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (1 1) (0 0)
4062 11:08:20.630916 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 11:08:20.634049 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 11:08:20.641036 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 11:08:20.644553 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 11:08:20.647579 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 11:08:20.653947 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 11:08:20.657258 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4069 11:08:20.660519 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4070 11:08:20.663804 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 11:08:20.670739 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 11:08:20.674022 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 11:08:20.677293 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 11:08:20.684299 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 11:08:20.687542 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 11:08:20.690799 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 11:08:20.697035 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 11:08:20.700944 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 11:08:20.704205 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 11:08:20.710509 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 11:08:20.713960 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 11:08:20.717299 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 11:08:20.723745 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 11:08:20.727499 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 11:08:20.730729 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 11:08:20.734165 Total UI for P1: 0, mck2ui 16
4087 11:08:20.737376 best dqsien dly found for B0: ( 0, 13, 14)
4088 11:08:20.740676 Total UI for P1: 0, mck2ui 16
4089 11:08:20.743785 best dqsien dly found for B1: ( 0, 13, 14)
4090 11:08:20.747514 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4091 11:08:20.750891 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4092 11:08:20.751001
4093 11:08:20.757231 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4094 11:08:20.760562 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4095 11:08:20.760689 [Gating] SW calibration Done
4096 11:08:20.763745 ==
4097 11:08:20.766497 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 11:08:20.770448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 11:08:20.770571 ==
4100 11:08:20.770684 RX Vref Scan: 0
4101 11:08:20.770796
4102 11:08:20.773156 RX Vref 0 -> 0, step: 1
4103 11:08:20.773278
4104 11:08:20.776453 RX Delay -230 -> 252, step: 16
4105 11:08:20.779748 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4106 11:08:20.783660 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4107 11:08:20.790337 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4108 11:08:20.793266 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4109 11:08:20.796483 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4110 11:08:20.799812 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4111 11:08:20.806671 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4112 11:08:20.809855 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4113 11:08:20.813515 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4114 11:08:20.816623 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4115 11:08:20.819965 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4116 11:08:20.826535 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4117 11:08:20.829812 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4118 11:08:20.833641 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4119 11:08:20.836899 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4120 11:08:20.843497 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4121 11:08:20.843626 ==
4122 11:08:20.846661 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 11:08:20.849901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 11:08:20.850028 ==
4125 11:08:20.850144 DQS Delay:
4126 11:08:20.853108 DQS0 = 0, DQS1 = 0
4127 11:08:20.853231 DQM Delay:
4128 11:08:20.856944 DQM0 = 50, DQM1 = 45
4129 11:08:20.857068 DQ Delay:
4130 11:08:20.859937 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4131 11:08:20.863099 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =65
4132 11:08:20.866822 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4133 11:08:20.870037 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4134 11:08:20.870165
4135 11:08:20.870274
4136 11:08:20.870388 ==
4137 11:08:20.873303 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 11:08:20.876648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 11:08:20.876773 ==
4140 11:08:20.879976
4141 11:08:20.880101
4142 11:08:20.880216 TX Vref Scan disable
4143 11:08:20.883368 == TX Byte 0 ==
4144 11:08:20.886639 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4145 11:08:20.889912 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4146 11:08:20.893385 == TX Byte 1 ==
4147 11:08:20.896715 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4148 11:08:20.899971 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4149 11:08:20.900094 ==
4150 11:08:20.903148 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 11:08:20.909828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 11:08:20.909953 ==
4153 11:08:20.910063
4154 11:08:20.910173
4155 11:08:20.910284 TX Vref Scan disable
4156 11:08:20.914726 == TX Byte 0 ==
4157 11:08:20.918241 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4158 11:08:20.924423 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4159 11:08:20.924509 == TX Byte 1 ==
4160 11:08:20.927961 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4161 11:08:20.931104 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4162 11:08:20.934290
4163 11:08:20.934372 [DATLAT]
4164 11:08:20.934438 Freq=600, CH0 RK0
4165 11:08:20.934499
4166 11:08:20.937443 DATLAT Default: 0x9
4167 11:08:20.937552 0, 0xFFFF, sum = 0
4168 11:08:20.941292 1, 0xFFFF, sum = 0
4169 11:08:20.941376 2, 0xFFFF, sum = 0
4170 11:08:20.944630 3, 0xFFFF, sum = 0
4171 11:08:20.947928 4, 0xFFFF, sum = 0
4172 11:08:20.948013 5, 0xFFFF, sum = 0
4173 11:08:20.951223 6, 0xFFFF, sum = 0
4174 11:08:20.951308 7, 0xFFFF, sum = 0
4175 11:08:20.951374 8, 0x0, sum = 1
4176 11:08:20.954476 9, 0x0, sum = 2
4177 11:08:20.954559 10, 0x0, sum = 3
4178 11:08:20.957746 11, 0x0, sum = 4
4179 11:08:20.957833 best_step = 9
4180 11:08:20.957897
4181 11:08:20.957957 ==
4182 11:08:20.960854 Dram Type= 6, Freq= 0, CH_0, rank 0
4183 11:08:20.967671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 11:08:20.967755 ==
4185 11:08:20.967820 RX Vref Scan: 1
4186 11:08:20.967881
4187 11:08:20.970416 RX Vref 0 -> 0, step: 1
4188 11:08:20.970499
4189 11:08:20.973763 RX Delay -163 -> 252, step: 8
4190 11:08:20.973859
4191 11:08:20.977281 Set Vref, RX VrefLevel [Byte0]: 58
4192 11:08:20.980360 [Byte1]: 54
4193 11:08:20.980443
4194 11:08:20.983733 Final RX Vref Byte 0 = 58 to rank0
4195 11:08:20.987650 Final RX Vref Byte 1 = 54 to rank0
4196 11:08:20.990399 Final RX Vref Byte 0 = 58 to rank1
4197 11:08:20.994252 Final RX Vref Byte 1 = 54 to rank1==
4198 11:08:20.997562 Dram Type= 6, Freq= 0, CH_0, rank 0
4199 11:08:21.000190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 11:08:21.000323 ==
4201 11:08:21.004120 DQS Delay:
4202 11:08:21.004243 DQS0 = 0, DQS1 = 0
4203 11:08:21.007386 DQM Delay:
4204 11:08:21.007511 DQM0 = 52, DQM1 = 48
4205 11:08:21.007623 DQ Delay:
4206 11:08:21.010625 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =48
4207 11:08:21.014000 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4208 11:08:21.017366 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =44
4209 11:08:21.020719 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =52
4210 11:08:21.020844
4211 11:08:21.020957
4212 11:08:21.030405 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4213 11:08:21.033599 CH0 RK0: MR19=808, MR18=6D60
4214 11:08:21.040183 CH0_RK0: MR19=0x808, MR18=0x6D60, DQSOSC=389, MR23=63, INC=173, DEC=115
4215 11:08:21.040315
4216 11:08:21.043745 ----->DramcWriteLeveling(PI) begin...
4217 11:08:21.043870 ==
4218 11:08:21.047110 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 11:08:21.050186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 11:08:21.050313 ==
4221 11:08:21.053676 Write leveling (Byte 0): 34 => 34
4222 11:08:21.057027 Write leveling (Byte 1): 33 => 33
4223 11:08:21.060165 DramcWriteLeveling(PI) end<-----
4224 11:08:21.060297
4225 11:08:21.060415 ==
4226 11:08:21.063613 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 11:08:21.066977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 11:08:21.067101 ==
4229 11:08:21.070631 [Gating] SW mode calibration
4230 11:08:21.077210 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4231 11:08:21.083400 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4232 11:08:21.087147 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4233 11:08:21.089937 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4234 11:08:21.096447 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4235 11:08:21.099738 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
4236 11:08:21.103127 0 9 16 | B1->B0 | 2d2d 2a2a | 0 0 | (0 0) (0 0)
4237 11:08:21.109706 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 11:08:21.113523 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 11:08:21.116723 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 11:08:21.123429 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 11:08:21.126676 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 11:08:21.130003 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 11:08:21.136539 0 10 12 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
4244 11:08:21.139960 0 10 16 | B1->B0 | 3d3d 3f3f | 0 0 | (1 1) (0 0)
4245 11:08:21.143294 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 11:08:21.149882 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 11:08:21.152958 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 11:08:21.156430 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 11:08:21.159607 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 11:08:21.166224 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4251 11:08:21.169590 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 11:08:21.173144 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4253 11:08:21.179505 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 11:08:21.182706 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 11:08:21.186148 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 11:08:21.193168 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 11:08:21.196332 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 11:08:21.199949 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 11:08:21.206550 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 11:08:21.209987 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 11:08:21.213191 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 11:08:21.219338 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 11:08:21.222699 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 11:08:21.226036 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 11:08:21.232893 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 11:08:21.236199 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 11:08:21.239475 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4268 11:08:21.246339 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4269 11:08:21.249615 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4270 11:08:21.252969 Total UI for P1: 0, mck2ui 16
4271 11:08:21.256260 best dqsien dly found for B0: ( 0, 13, 14)
4272 11:08:21.259408 Total UI for P1: 0, mck2ui 16
4273 11:08:21.262562 best dqsien dly found for B1: ( 0, 13, 16)
4274 11:08:21.266273 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4275 11:08:21.269619 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4276 11:08:21.269702
4277 11:08:21.272838 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4278 11:08:21.276238 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4279 11:08:21.279359 [Gating] SW calibration Done
4280 11:08:21.279435 ==
4281 11:08:21.282367 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 11:08:21.285782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 11:08:21.289352 ==
4284 11:08:21.289481 RX Vref Scan: 0
4285 11:08:21.289596
4286 11:08:21.292305 RX Vref 0 -> 0, step: 1
4287 11:08:21.292414
4288 11:08:21.295813 RX Delay -230 -> 252, step: 16
4289 11:08:21.299233 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4290 11:08:21.302556 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4291 11:08:21.305785 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4292 11:08:21.309185 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4293 11:08:21.316173 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4294 11:08:21.319028 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4295 11:08:21.322319 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4296 11:08:21.325941 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4297 11:08:21.332245 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4298 11:08:21.336135 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4299 11:08:21.339442 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4300 11:08:21.342818 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4301 11:08:21.349515 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4302 11:08:21.352272 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4303 11:08:21.355690 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4304 11:08:21.359653 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4305 11:08:21.359735 ==
4306 11:08:21.362397 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 11:08:21.365674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 11:08:21.369388 ==
4309 11:08:21.369473 DQS Delay:
4310 11:08:21.369539 DQS0 = 0, DQS1 = 0
4311 11:08:21.372541 DQM Delay:
4312 11:08:21.372624 DQM0 = 50, DQM1 = 43
4313 11:08:21.375609 DQ Delay:
4314 11:08:21.379433 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4315 11:08:21.379512 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4316 11:08:21.382663 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4317 11:08:21.389196 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4318 11:08:21.389275
4319 11:08:21.389339
4320 11:08:21.389405 ==
4321 11:08:21.392240 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 11:08:21.396034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 11:08:21.396111 ==
4324 11:08:21.396181
4325 11:08:21.396241
4326 11:08:21.399326 TX Vref Scan disable
4327 11:08:21.399435 == TX Byte 0 ==
4328 11:08:21.405524 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4329 11:08:21.408845 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4330 11:08:21.408926 == TX Byte 1 ==
4331 11:08:21.415772 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4332 11:08:21.419159 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4333 11:08:21.419243 ==
4334 11:08:21.422354 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 11:08:21.425319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 11:08:21.425397 ==
4337 11:08:21.425462
4338 11:08:21.425543
4339 11:08:21.428686 TX Vref Scan disable
4340 11:08:21.432538 == TX Byte 0 ==
4341 11:08:21.435474 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4342 11:08:21.442033 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4343 11:08:21.442142 == TX Byte 1 ==
4344 11:08:21.445576 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4345 11:08:21.452167 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4346 11:08:21.452251
4347 11:08:21.452331 [DATLAT]
4348 11:08:21.452393 Freq=600, CH0 RK1
4349 11:08:21.452452
4350 11:08:21.455296 DATLAT Default: 0x9
4351 11:08:21.455380 0, 0xFFFF, sum = 0
4352 11:08:21.458539 1, 0xFFFF, sum = 0
4353 11:08:21.458620 2, 0xFFFF, sum = 0
4354 11:08:21.462542 3, 0xFFFF, sum = 0
4355 11:08:21.462647 4, 0xFFFF, sum = 0
4356 11:08:21.465262 5, 0xFFFF, sum = 0
4357 11:08:21.468481 6, 0xFFFF, sum = 0
4358 11:08:21.468580 7, 0xFFFF, sum = 0
4359 11:08:21.471712 8, 0x0, sum = 1
4360 11:08:21.471819 9, 0x0, sum = 2
4361 11:08:21.471930 10, 0x0, sum = 3
4362 11:08:21.475033 11, 0x0, sum = 4
4363 11:08:21.475108 best_step = 9
4364 11:08:21.475172
4365 11:08:21.475233 ==
4366 11:08:21.478769 Dram Type= 6, Freq= 0, CH_0, rank 1
4367 11:08:21.485204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 11:08:21.485315 ==
4369 11:08:21.485429 RX Vref Scan: 0
4370 11:08:21.485525
4371 11:08:21.488545 RX Vref 0 -> 0, step: 1
4372 11:08:21.488656
4373 11:08:21.491898 RX Delay -163 -> 252, step: 8
4374 11:08:21.495012 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4375 11:08:21.502229 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4376 11:08:21.504786 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4377 11:08:21.508751 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4378 11:08:21.511879 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4379 11:08:21.515205 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4380 11:08:21.521448 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4381 11:08:21.525219 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4382 11:08:21.528643 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4383 11:08:21.531972 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4384 11:08:21.535113 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4385 11:08:21.541608 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4386 11:08:21.544673 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4387 11:08:21.548420 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4388 11:08:21.551832 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4389 11:08:21.557949 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4390 11:08:21.558029 ==
4391 11:08:21.561457 Dram Type= 6, Freq= 0, CH_0, rank 1
4392 11:08:21.564534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 11:08:21.564639 ==
4394 11:08:21.564742 DQS Delay:
4395 11:08:21.568003 DQS0 = 0, DQS1 = 0
4396 11:08:21.568080 DQM Delay:
4397 11:08:21.571479 DQM0 = 53, DQM1 = 45
4398 11:08:21.571587 DQ Delay:
4399 11:08:21.574719 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4400 11:08:21.578124 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =60
4401 11:08:21.581309 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4402 11:08:21.584652 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4403 11:08:21.584753
4404 11:08:21.584849
4405 11:08:21.591570 [DQSOSCAuto] RK1, (LSB)MR18= 0x6323, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4406 11:08:21.594874 CH0 RK1: MR19=808, MR18=6323
4407 11:08:21.601352 CH0_RK1: MR19=0x808, MR18=0x6323, DQSOSC=391, MR23=63, INC=171, DEC=114
4408 11:08:21.605014 [RxdqsGatingPostProcess] freq 600
4409 11:08:21.611651 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4410 11:08:21.614839 Pre-setting of DQS Precalculation
4411 11:08:21.618131 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4412 11:08:21.618211 ==
4413 11:08:21.621402 Dram Type= 6, Freq= 0, CH_1, rank 0
4414 11:08:21.624712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 11:08:21.624789 ==
4416 11:08:21.631479 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4417 11:08:21.638240 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4418 11:08:21.641540 [CA 0] Center 36 (5~67) winsize 63
4419 11:08:21.644638 [CA 1] Center 36 (5~67) winsize 63
4420 11:08:21.647778 [CA 2] Center 35 (4~66) winsize 63
4421 11:08:21.651335 [CA 3] Center 34 (4~65) winsize 62
4422 11:08:21.654457 [CA 4] Center 34 (4~65) winsize 62
4423 11:08:21.658154 [CA 5] Center 34 (4~65) winsize 62
4424 11:08:21.658229
4425 11:08:21.661129 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4426 11:08:21.661235
4427 11:08:21.664369 [CATrainingPosCal] consider 1 rank data
4428 11:08:21.668029 u2DelayCellTimex100 = 270/100 ps
4429 11:08:21.671021 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4430 11:08:21.674812 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4431 11:08:21.677929 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4432 11:08:21.681007 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4433 11:08:21.684629 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4434 11:08:21.687936 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4435 11:08:21.688043
4436 11:08:21.694453 CA PerBit enable=1, Macro0, CA PI delay=34
4437 11:08:21.694571
4438 11:08:21.694667 [CBTSetCACLKResult] CA Dly = 34
4439 11:08:21.698224 CS Dly: 5 (0~36)
4440 11:08:21.698334 ==
4441 11:08:21.701536 Dram Type= 6, Freq= 0, CH_1, rank 1
4442 11:08:21.704573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4443 11:08:21.704646 ==
4444 11:08:21.711215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4445 11:08:21.717936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4446 11:08:21.721146 [CA 0] Center 36 (6~67) winsize 62
4447 11:08:21.724446 [CA 1] Center 36 (6~67) winsize 62
4448 11:08:21.727682 [CA 2] Center 35 (5~66) winsize 62
4449 11:08:21.731015 [CA 3] Center 35 (4~66) winsize 63
4450 11:08:21.734274 [CA 4] Center 35 (4~66) winsize 63
4451 11:08:21.737687 [CA 5] Center 34 (4~65) winsize 62
4452 11:08:21.737795
4453 11:08:21.740937 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4454 11:08:21.741044
4455 11:08:21.744330 [CATrainingPosCal] consider 2 rank data
4456 11:08:21.747554 u2DelayCellTimex100 = 270/100 ps
4457 11:08:21.750937 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4458 11:08:21.754152 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4459 11:08:21.757345 CA2 delay=35 (5~66),Diff = 1 PI (9 cell)
4460 11:08:21.760969 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4461 11:08:21.764114 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4462 11:08:21.771432 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4463 11:08:21.771515
4464 11:08:21.774626 CA PerBit enable=1, Macro0, CA PI delay=34
4465 11:08:21.774735
4466 11:08:21.777762 [CBTSetCACLKResult] CA Dly = 34
4467 11:08:21.777839 CS Dly: 6 (0~38)
4468 11:08:21.777903
4469 11:08:21.780835 ----->DramcWriteLeveling(PI) begin...
4470 11:08:21.780919 ==
4471 11:08:21.784670 Dram Type= 6, Freq= 0, CH_1, rank 0
4472 11:08:21.787782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4473 11:08:21.790897 ==
4474 11:08:21.790970 Write leveling (Byte 0): 31 => 31
4475 11:08:21.794341 Write leveling (Byte 1): 31 => 31
4476 11:08:21.797478 DramcWriteLeveling(PI) end<-----
4477 11:08:21.797557
4478 11:08:21.797621 ==
4479 11:08:21.800926 Dram Type= 6, Freq= 0, CH_1, rank 0
4480 11:08:21.807507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 11:08:21.807612 ==
4482 11:08:21.807705 [Gating] SW mode calibration
4483 11:08:21.817589 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4484 11:08:21.820724 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4485 11:08:21.827401 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4486 11:08:21.830509 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4487 11:08:21.833772 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4488 11:08:21.840492 0 9 12 | B1->B0 | 3232 2e2e | 1 1 | (1 0) (1 0)
4489 11:08:21.843910 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 11:08:21.847439 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 11:08:21.850715 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 11:08:21.857268 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 11:08:21.860620 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 11:08:21.863744 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 11:08:21.870186 0 10 8 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
4496 11:08:21.873393 0 10 12 | B1->B0 | 3b3b 3b3b | 0 0 | (0 0) (0 0)
4497 11:08:21.877180 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 11:08:21.883750 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 11:08:21.886877 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 11:08:21.892981 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 11:08:21.896242 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 11:08:21.900166 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 11:08:21.903147 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 11:08:21.909895 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4505 11:08:21.913263 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 11:08:21.916707 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 11:08:21.923008 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 11:08:21.926232 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 11:08:21.929527 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 11:08:21.936325 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 11:08:21.939529 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 11:08:21.942781 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 11:08:21.949539 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 11:08:21.952867 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 11:08:21.956202 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 11:08:21.962889 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 11:08:21.966229 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 11:08:21.969458 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 11:08:21.975686 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 11:08:21.978925 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4521 11:08:21.982746 Total UI for P1: 0, mck2ui 16
4522 11:08:21.985902 best dqsien dly found for B0: ( 0, 13, 10)
4523 11:08:21.988981 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4524 11:08:21.992236 Total UI for P1: 0, mck2ui 16
4525 11:08:21.995925 best dqsien dly found for B1: ( 0, 13, 12)
4526 11:08:21.998836 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4527 11:08:22.005693 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4528 11:08:22.005776
4529 11:08:22.009065 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4530 11:08:22.012100 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4531 11:08:22.015759 [Gating] SW calibration Done
4532 11:08:22.015856 ==
4533 11:08:22.018760 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 11:08:22.022383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 11:08:22.022466 ==
4536 11:08:22.025217 RX Vref Scan: 0
4537 11:08:22.025328
4538 11:08:22.025423 RX Vref 0 -> 0, step: 1
4539 11:08:22.025505
4540 11:08:22.028715 RX Delay -230 -> 252, step: 16
4541 11:08:22.032138 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4542 11:08:22.038695 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4543 11:08:22.042294 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4544 11:08:22.045433 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4545 11:08:22.048536 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4546 11:08:22.055146 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4547 11:08:22.058488 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4548 11:08:22.061822 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4549 11:08:22.065170 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4550 11:08:22.068484 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4551 11:08:22.075078 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4552 11:08:22.078370 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4553 11:08:22.081594 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4554 11:08:22.084688 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4555 11:08:22.091376 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4556 11:08:22.094827 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4557 11:08:22.094933 ==
4558 11:08:22.098111 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 11:08:22.101408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 11:08:22.101520 ==
4561 11:08:22.104790 DQS Delay:
4562 11:08:22.104904 DQS0 = 0, DQS1 = 0
4563 11:08:22.104998 DQM Delay:
4564 11:08:22.108519 DQM0 = 47, DQM1 = 45
4565 11:08:22.108597 DQ Delay:
4566 11:08:22.111411 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4567 11:08:22.115060 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4568 11:08:22.118296 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4569 11:08:22.121633 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4570 11:08:22.121746
4571 11:08:22.121839
4572 11:08:22.124831 ==
4573 11:08:22.124908 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 11:08:22.131411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 11:08:22.131546 ==
4576 11:08:22.131661
4577 11:08:22.131774
4578 11:08:22.134512 TX Vref Scan disable
4579 11:08:22.134639 == TX Byte 0 ==
4580 11:08:22.137828 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4581 11:08:22.144194 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4582 11:08:22.144308 == TX Byte 1 ==
4583 11:08:22.147800 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4584 11:08:22.154619 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4585 11:08:22.154726 ==
4586 11:08:22.157880 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 11:08:22.161122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 11:08:22.161226 ==
4589 11:08:22.161321
4590 11:08:22.161412
4591 11:08:22.164532 TX Vref Scan disable
4592 11:08:22.167912 == TX Byte 0 ==
4593 11:08:22.171181 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4594 11:08:22.174514 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4595 11:08:22.177806 == TX Byte 1 ==
4596 11:08:22.181036 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4597 11:08:22.184387 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4598 11:08:22.184496
4599 11:08:22.187611 [DATLAT]
4600 11:08:22.187721 Freq=600, CH1 RK0
4601 11:08:22.187818
4602 11:08:22.191285 DATLAT Default: 0x9
4603 11:08:22.191399 0, 0xFFFF, sum = 0
4604 11:08:22.194544 1, 0xFFFF, sum = 0
4605 11:08:22.194681 2, 0xFFFF, sum = 0
4606 11:08:22.197874 3, 0xFFFF, sum = 0
4607 11:08:22.198009 4, 0xFFFF, sum = 0
4608 11:08:22.201236 5, 0xFFFF, sum = 0
4609 11:08:22.201363 6, 0xFFFF, sum = 0
4610 11:08:22.204505 7, 0xFFFF, sum = 0
4611 11:08:22.204630 8, 0x0, sum = 1
4612 11:08:22.207772 9, 0x0, sum = 2
4613 11:08:22.207900 10, 0x0, sum = 3
4614 11:08:22.211095 11, 0x0, sum = 4
4615 11:08:22.211224 best_step = 9
4616 11:08:22.211338
4617 11:08:22.211451 ==
4618 11:08:22.214364 Dram Type= 6, Freq= 0, CH_1, rank 0
4619 11:08:22.217536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 11:08:22.220547 ==
4621 11:08:22.220672 RX Vref Scan: 1
4622 11:08:22.220770
4623 11:08:22.224147 RX Vref 0 -> 0, step: 1
4624 11:08:22.224254
4625 11:08:22.227366 RX Delay -163 -> 252, step: 8
4626 11:08:22.227477
4627 11:08:22.230897 Set Vref, RX VrefLevel [Byte0]: 53
4628 11:08:22.231010 [Byte1]: 48
4629 11:08:22.235810
4630 11:08:22.235921 Final RX Vref Byte 0 = 53 to rank0
4631 11:08:22.239149 Final RX Vref Byte 1 = 48 to rank0
4632 11:08:22.242239 Final RX Vref Byte 0 = 53 to rank1
4633 11:08:22.245349 Final RX Vref Byte 1 = 48 to rank1==
4634 11:08:22.248825 Dram Type= 6, Freq= 0, CH_1, rank 0
4635 11:08:22.255647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4636 11:08:22.255773 ==
4637 11:08:22.255874 DQS Delay:
4638 11:08:22.255973 DQS0 = 0, DQS1 = 0
4639 11:08:22.259085 DQM Delay:
4640 11:08:22.259169 DQM0 = 48, DQM1 = 44
4641 11:08:22.262367 DQ Delay:
4642 11:08:22.265360 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4643 11:08:22.265472 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4644 11:08:22.269169 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4645 11:08:22.275304 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4646 11:08:22.275413
4647 11:08:22.275513
4648 11:08:22.282154 [DQSOSCAuto] RK0, (LSB)MR18= 0x456a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4649 11:08:22.285231 CH1 RK0: MR19=808, MR18=456A
4650 11:08:22.292036 CH1_RK0: MR19=0x808, MR18=0x456A, DQSOSC=389, MR23=63, INC=173, DEC=115
4651 11:08:22.292126
4652 11:08:22.295173 ----->DramcWriteLeveling(PI) begin...
4653 11:08:22.295297 ==
4654 11:08:22.298944 Dram Type= 6, Freq= 0, CH_1, rank 1
4655 11:08:22.302263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4656 11:08:22.302342 ==
4657 11:08:22.305528 Write leveling (Byte 0): 31 => 31
4658 11:08:22.308617 Write leveling (Byte 1): 31 => 31
4659 11:08:22.312134 DramcWriteLeveling(PI) end<-----
4660 11:08:22.312209
4661 11:08:22.312283 ==
4662 11:08:22.315221 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 11:08:22.318497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 11:08:22.318610 ==
4665 11:08:22.321793 [Gating] SW mode calibration
4666 11:08:22.328799 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4667 11:08:22.335034 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4668 11:08:22.338223 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4669 11:08:22.345377 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4670 11:08:22.348148 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4671 11:08:22.351589 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
4672 11:08:22.357974 0 9 16 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 0)
4673 11:08:22.361638 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 11:08:22.364639 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 11:08:22.368124 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 11:08:22.375027 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 11:08:22.378402 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 11:08:22.381520 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 11:08:22.388102 0 10 12 | B1->B0 | 3737 3737 | 0 0 | (1 1) (0 0)
4680 11:08:22.391516 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 11:08:22.394865 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 11:08:22.401349 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 11:08:22.404955 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 11:08:22.408126 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 11:08:22.414804 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 11:08:22.418122 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4687 11:08:22.421339 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4688 11:08:22.428131 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 11:08:22.431602 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 11:08:22.434677 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 11:08:22.441589 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 11:08:22.444890 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 11:08:22.447523 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 11:08:22.454492 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 11:08:22.457605 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 11:08:22.461252 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 11:08:22.467793 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 11:08:22.471088 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 11:08:22.474223 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 11:08:22.480892 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 11:08:22.484427 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 11:08:22.487688 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4703 11:08:22.494431 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4704 11:08:22.494517 Total UI for P1: 0, mck2ui 16
4705 11:08:22.501046 best dqsien dly found for B1: ( 0, 13, 8)
4706 11:08:22.504253 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4707 11:08:22.507588 Total UI for P1: 0, mck2ui 16
4708 11:08:22.511224 best dqsien dly found for B0: ( 0, 13, 12)
4709 11:08:22.514373 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4710 11:08:22.517549 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4711 11:08:22.517625
4712 11:08:22.520719 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4713 11:08:22.524457 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4714 11:08:22.527777 [Gating] SW calibration Done
4715 11:08:22.527861 ==
4716 11:08:22.531218 Dram Type= 6, Freq= 0, CH_1, rank 1
4717 11:08:22.534430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4718 11:08:22.534514 ==
4719 11:08:22.537698 RX Vref Scan: 0
4720 11:08:22.537781
4721 11:08:22.540853 RX Vref 0 -> 0, step: 1
4722 11:08:22.540939
4723 11:08:22.541028 RX Delay -230 -> 252, step: 16
4724 11:08:22.547793 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4725 11:08:22.551203 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4726 11:08:22.554430 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4727 11:08:22.557797 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4728 11:08:22.564337 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4729 11:08:22.567443 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4730 11:08:22.571129 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4731 11:08:22.574196 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4732 11:08:22.577500 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4733 11:08:22.584342 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4734 11:08:22.587617 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4735 11:08:22.590904 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4736 11:08:22.594019 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4737 11:08:22.600862 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4738 11:08:22.604254 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4739 11:08:22.607551 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4740 11:08:22.607674 ==
4741 11:08:22.610878 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 11:08:22.613909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 11:08:22.617258 ==
4744 11:08:22.617345 DQS Delay:
4745 11:08:22.617431 DQS0 = 0, DQS1 = 0
4746 11:08:22.620519 DQM Delay:
4747 11:08:22.620647 DQM0 = 51, DQM1 = 49
4748 11:08:22.624203 DQ Delay:
4749 11:08:22.624347 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4750 11:08:22.627297 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4751 11:08:22.630401 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4752 11:08:22.633882 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4753 11:08:22.633994
4754 11:08:22.637168
4755 11:08:22.637250 ==
4756 11:08:22.640419 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 11:08:22.644305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 11:08:22.644447 ==
4759 11:08:22.644560
4760 11:08:22.644681
4761 11:08:22.647618 TX Vref Scan disable
4762 11:08:22.647741 == TX Byte 0 ==
4763 11:08:22.654162 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4764 11:08:22.657594 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4765 11:08:22.657720 == TX Byte 1 ==
4766 11:08:22.664174 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4767 11:08:22.667549 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4768 11:08:22.667631 ==
4769 11:08:22.670639 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 11:08:22.674123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 11:08:22.674208 ==
4772 11:08:22.674274
4773 11:08:22.674334
4774 11:08:22.677359 TX Vref Scan disable
4775 11:08:22.680660 == TX Byte 0 ==
4776 11:08:22.683820 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4777 11:08:22.686927 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4778 11:08:22.690523 == TX Byte 1 ==
4779 11:08:22.693376 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4780 11:08:22.696855 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4781 11:08:22.696957
4782 11:08:22.700402 [DATLAT]
4783 11:08:22.700510 Freq=600, CH1 RK1
4784 11:08:22.700618
4785 11:08:22.703340 DATLAT Default: 0x9
4786 11:08:22.703454 0, 0xFFFF, sum = 0
4787 11:08:22.706993 1, 0xFFFF, sum = 0
4788 11:08:22.707102 2, 0xFFFF, sum = 0
4789 11:08:22.709994 3, 0xFFFF, sum = 0
4790 11:08:22.710074 4, 0xFFFF, sum = 0
4791 11:08:22.713429 5, 0xFFFF, sum = 0
4792 11:08:22.713526 6, 0xFFFF, sum = 0
4793 11:08:22.716788 7, 0xFFFF, sum = 0
4794 11:08:22.716895 8, 0x0, sum = 1
4795 11:08:22.719928 9, 0x0, sum = 2
4796 11:08:22.720038 10, 0x0, sum = 3
4797 11:08:22.723275 11, 0x0, sum = 4
4798 11:08:22.723382 best_step = 9
4799 11:08:22.723472
4800 11:08:22.723579 ==
4801 11:08:22.726650 Dram Type= 6, Freq= 0, CH_1, rank 1
4802 11:08:22.733606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4803 11:08:22.733686 ==
4804 11:08:22.733770 RX Vref Scan: 0
4805 11:08:22.733834
4806 11:08:22.736783 RX Vref 0 -> 0, step: 1
4807 11:08:22.736864
4808 11:08:22.739781 RX Delay -163 -> 252, step: 8
4809 11:08:22.743685 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4810 11:08:22.746663 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4811 11:08:22.753861 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4812 11:08:22.757166 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4813 11:08:22.760386 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4814 11:08:22.763803 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4815 11:08:22.767182 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4816 11:08:22.773700 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4817 11:08:22.776513 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4818 11:08:22.779817 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4819 11:08:22.783215 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4820 11:08:22.786624 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4821 11:08:22.793218 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4822 11:08:22.796567 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4823 11:08:22.799824 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4824 11:08:22.803130 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4825 11:08:22.803258 ==
4826 11:08:22.806682 Dram Type= 6, Freq= 0, CH_1, rank 1
4827 11:08:22.813429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4828 11:08:22.813555 ==
4829 11:08:22.813672 DQS Delay:
4830 11:08:22.816679 DQS0 = 0, DQS1 = 0
4831 11:08:22.816807 DQM Delay:
4832 11:08:22.816915 DQM0 = 49, DQM1 = 46
4833 11:08:22.819942 DQ Delay:
4834 11:08:22.823202 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4835 11:08:22.826490 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4836 11:08:22.829756 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4837 11:08:22.833352 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4838 11:08:22.833432
4839 11:08:22.833497
4840 11:08:22.839362 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f26, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 389 ps
4841 11:08:22.842551 CH1 RK1: MR19=808, MR18=6F26
4842 11:08:22.849499 CH1_RK1: MR19=0x808, MR18=0x6F26, DQSOSC=389, MR23=63, INC=173, DEC=115
4843 11:08:22.853034 [RxdqsGatingPostProcess] freq 600
4844 11:08:22.859686 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4845 11:08:22.859802 Pre-setting of DQS Precalculation
4846 11:08:22.866235 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4847 11:08:22.873040 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4848 11:08:22.879667 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4849 11:08:22.879749
4850 11:08:22.879818
4851 11:08:22.882984 [Calibration Summary] 1200 Mbps
4852 11:08:22.883060 CH 0, Rank 0
4853 11:08:22.886313 SW Impedance : PASS
4854 11:08:22.889583 DUTY Scan : NO K
4855 11:08:22.889662 ZQ Calibration : PASS
4856 11:08:22.893006 Jitter Meter : NO K
4857 11:08:22.896166 CBT Training : PASS
4858 11:08:22.896243 Write leveling : PASS
4859 11:08:22.899350 RX DQS gating : PASS
4860 11:08:22.902688 RX DQ/DQS(RDDQC) : PASS
4861 11:08:22.902768 TX DQ/DQS : PASS
4862 11:08:22.905985 RX DATLAT : PASS
4863 11:08:22.909436 RX DQ/DQS(Engine): PASS
4864 11:08:22.909523 TX OE : NO K
4865 11:08:22.912596 All Pass.
4866 11:08:22.912669
4867 11:08:22.912751 CH 0, Rank 1
4868 11:08:22.916585 SW Impedance : PASS
4869 11:08:22.916659 DUTY Scan : NO K
4870 11:08:22.919789 ZQ Calibration : PASS
4871 11:08:22.922966 Jitter Meter : NO K
4872 11:08:22.923046 CBT Training : PASS
4873 11:08:22.926071 Write leveling : PASS
4874 11:08:22.926206 RX DQS gating : PASS
4875 11:08:22.929330 RX DQ/DQS(RDDQC) : PASS
4876 11:08:22.933283 TX DQ/DQS : PASS
4877 11:08:22.933370 RX DATLAT : PASS
4878 11:08:22.936077 RX DQ/DQS(Engine): PASS
4879 11:08:22.939765 TX OE : NO K
4880 11:08:22.939877 All Pass.
4881 11:08:22.939972
4882 11:08:22.940063 CH 1, Rank 0
4883 11:08:22.943119 SW Impedance : PASS
4884 11:08:22.946459 DUTY Scan : NO K
4885 11:08:22.946543 ZQ Calibration : PASS
4886 11:08:22.949626 Jitter Meter : NO K
4887 11:08:22.952980 CBT Training : PASS
4888 11:08:22.953065 Write leveling : PASS
4889 11:08:22.955854 RX DQS gating : PASS
4890 11:08:22.959367 RX DQ/DQS(RDDQC) : PASS
4891 11:08:22.959460 TX DQ/DQS : PASS
4892 11:08:22.962435 RX DATLAT : PASS
4893 11:08:22.965791 RX DQ/DQS(Engine): PASS
4894 11:08:22.965911 TX OE : NO K
4895 11:08:22.966019 All Pass.
4896 11:08:22.969683
4897 11:08:22.969770 CH 1, Rank 1
4898 11:08:22.972545 SW Impedance : PASS
4899 11:08:22.972634 DUTY Scan : NO K
4900 11:08:22.976173 ZQ Calibration : PASS
4901 11:08:22.976277 Jitter Meter : NO K
4902 11:08:22.979574 CBT Training : PASS
4903 11:08:22.982484 Write leveling : PASS
4904 11:08:22.982615 RX DQS gating : PASS
4905 11:08:22.985836 RX DQ/DQS(RDDQC) : PASS
4906 11:08:22.989023 TX DQ/DQS : PASS
4907 11:08:22.989151 RX DATLAT : PASS
4908 11:08:22.992503 RX DQ/DQS(Engine): PASS
4909 11:08:22.995741 TX OE : NO K
4910 11:08:22.995868 All Pass.
4911 11:08:22.995984
4912 11:08:22.998988 DramC Write-DBI off
4913 11:08:22.999112 PER_BANK_REFRESH: Hybrid Mode
4914 11:08:23.002777 TX_TRACKING: ON
4915 11:08:23.009476 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4916 11:08:23.016039 [FAST_K] Save calibration result to emmc
4917 11:08:23.019439 dramc_set_vcore_voltage set vcore to 662500
4918 11:08:23.019566 Read voltage for 933, 3
4919 11:08:23.022135 Vio18 = 0
4920 11:08:23.022261 Vcore = 662500
4921 11:08:23.022376 Vdram = 0
4922 11:08:23.026027 Vddq = 0
4923 11:08:23.026149 Vmddr = 0
4924 11:08:23.029031 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4925 11:08:23.035527 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4926 11:08:23.039031 MEM_TYPE=3, freq_sel=17
4927 11:08:23.042253 sv_algorithm_assistance_LP4_1600
4928 11:08:23.045468 ============ PULL DRAM RESETB DOWN ============
4929 11:08:23.049261 ========== PULL DRAM RESETB DOWN end =========
4930 11:08:23.052442 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4931 11:08:23.055551 ===================================
4932 11:08:23.059233 LPDDR4 DRAM CONFIGURATION
4933 11:08:23.062195 ===================================
4934 11:08:23.065689 EX_ROW_EN[0] = 0x0
4935 11:08:23.065817 EX_ROW_EN[1] = 0x0
4936 11:08:23.068636 LP4Y_EN = 0x0
4937 11:08:23.068754 WORK_FSP = 0x0
4938 11:08:23.072737 WL = 0x3
4939 11:08:23.072827 RL = 0x3
4940 11:08:23.075988 BL = 0x2
4941 11:08:23.076120 RPST = 0x0
4942 11:08:23.079191 RD_PRE = 0x0
4943 11:08:23.082227 WR_PRE = 0x1
4944 11:08:23.082362 WR_PST = 0x0
4945 11:08:23.085839 DBI_WR = 0x0
4946 11:08:23.085977 DBI_RD = 0x0
4947 11:08:23.088743 OTF = 0x1
4948 11:08:23.092209 ===================================
4949 11:08:23.095884 ===================================
4950 11:08:23.096015 ANA top config
4951 11:08:23.098752 ===================================
4952 11:08:23.102082 DLL_ASYNC_EN = 0
4953 11:08:23.105422 ALL_SLAVE_EN = 1
4954 11:08:23.105506 NEW_RANK_MODE = 1
4955 11:08:23.108656 DLL_IDLE_MODE = 1
4956 11:08:23.111887 LP45_APHY_COMB_EN = 1
4957 11:08:23.115328 TX_ODT_DIS = 1
4958 11:08:23.115463 NEW_8X_MODE = 1
4959 11:08:23.118679 ===================================
4960 11:08:23.121892 ===================================
4961 11:08:23.125191 data_rate = 1866
4962 11:08:23.128495 CKR = 1
4963 11:08:23.131865 DQ_P2S_RATIO = 8
4964 11:08:23.135138 ===================================
4965 11:08:23.138393 CA_P2S_RATIO = 8
4966 11:08:23.141646 DQ_CA_OPEN = 0
4967 11:08:23.141758 DQ_SEMI_OPEN = 0
4968 11:08:23.145645 CA_SEMI_OPEN = 0
4969 11:08:23.148351 CA_FULL_RATE = 0
4970 11:08:23.152141 DQ_CKDIV4_EN = 1
4971 11:08:23.155206 CA_CKDIV4_EN = 1
4972 11:08:23.158278 CA_PREDIV_EN = 0
4973 11:08:23.158359 PH8_DLY = 0
4974 11:08:23.161933 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4975 11:08:23.165251 DQ_AAMCK_DIV = 4
4976 11:08:23.168501 CA_AAMCK_DIV = 4
4977 11:08:23.172244 CA_ADMCK_DIV = 4
4978 11:08:23.175160 DQ_TRACK_CA_EN = 0
4979 11:08:23.175299 CA_PICK = 933
4980 11:08:23.178850 CA_MCKIO = 933
4981 11:08:23.182031 MCKIO_SEMI = 0
4982 11:08:23.185275 PLL_FREQ = 3732
4983 11:08:23.188592 DQ_UI_PI_RATIO = 32
4984 11:08:23.191954 CA_UI_PI_RATIO = 0
4985 11:08:23.195163 ===================================
4986 11:08:23.198107 ===================================
4987 11:08:23.198222 memory_type:LPDDR4
4988 11:08:23.201916 GP_NUM : 10
4989 11:08:23.205097 SRAM_EN : 1
4990 11:08:23.205216 MD32_EN : 0
4991 11:08:23.208045 ===================================
4992 11:08:23.211458 [ANA_INIT] >>>>>>>>>>>>>>
4993 11:08:23.215070 <<<<<< [CONFIGURE PHASE]: ANA_TX
4994 11:08:23.218380 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4995 11:08:23.221822 ===================================
4996 11:08:23.225291 data_rate = 1866,PCW = 0X8f00
4997 11:08:23.228634 ===================================
4998 11:08:23.231982 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4999 11:08:23.234718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5000 11:08:23.241697 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5001 11:08:23.244753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5002 11:08:23.251526 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5003 11:08:23.254811 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5004 11:08:23.254922 [ANA_INIT] flow start
5005 11:08:23.258102 [ANA_INIT] PLL >>>>>>>>
5006 11:08:23.261191 [ANA_INIT] PLL <<<<<<<<
5007 11:08:23.261280 [ANA_INIT] MIDPI >>>>>>>>
5008 11:08:23.264499 [ANA_INIT] MIDPI <<<<<<<<
5009 11:08:23.268081 [ANA_INIT] DLL >>>>>>>>
5010 11:08:23.268174 [ANA_INIT] flow end
5011 11:08:23.274505 ============ LP4 DIFF to SE enter ============
5012 11:08:23.277850 ============ LP4 DIFF to SE exit ============
5013 11:08:23.277932 [ANA_INIT] <<<<<<<<<<<<<
5014 11:08:23.281443 [Flow] Enable top DCM control >>>>>
5015 11:08:23.284699 [Flow] Enable top DCM control <<<<<
5016 11:08:23.287630 Enable DLL master slave shuffle
5017 11:08:23.294367 ==============================================================
5018 11:08:23.294459 Gating Mode config
5019 11:08:23.301376 ==============================================================
5020 11:08:23.304524 Config description:
5021 11:08:23.314477 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5022 11:08:23.320809 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5023 11:08:23.324247 SELPH_MODE 0: By rank 1: By Phase
5024 11:08:23.331398 ==============================================================
5025 11:08:23.334660 GAT_TRACK_EN = 1
5026 11:08:23.338137 RX_GATING_MODE = 2
5027 11:08:23.338222 RX_GATING_TRACK_MODE = 2
5028 11:08:23.341232 SELPH_MODE = 1
5029 11:08:23.344570 PICG_EARLY_EN = 1
5030 11:08:23.347753 VALID_LAT_VALUE = 1
5031 11:08:23.354576 ==============================================================
5032 11:08:23.358028 Enter into Gating configuration >>>>
5033 11:08:23.361231 Exit from Gating configuration <<<<
5034 11:08:23.364351 Enter into DVFS_PRE_config >>>>>
5035 11:08:23.374179 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5036 11:08:23.377372 Exit from DVFS_PRE_config <<<<<
5037 11:08:23.381040 Enter into PICG configuration >>>>
5038 11:08:23.384170 Exit from PICG configuration <<<<
5039 11:08:23.387412 [RX_INPUT] configuration >>>>>
5040 11:08:23.390550 [RX_INPUT] configuration <<<<<
5041 11:08:23.394412 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5042 11:08:23.400701 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5043 11:08:23.407297 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5044 11:08:23.414193 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5045 11:08:23.417609 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5046 11:08:23.424434 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5047 11:08:23.427740 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5048 11:08:23.433965 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5049 11:08:23.437592 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5050 11:08:23.440573 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5051 11:08:23.443842 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5052 11:08:23.450929 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5053 11:08:23.454099 ===================================
5054 11:08:23.454217 LPDDR4 DRAM CONFIGURATION
5055 11:08:23.457276 ===================================
5056 11:08:23.460617 EX_ROW_EN[0] = 0x0
5057 11:08:23.463708 EX_ROW_EN[1] = 0x0
5058 11:08:23.463819 LP4Y_EN = 0x0
5059 11:08:23.467020 WORK_FSP = 0x0
5060 11:08:23.467131 WL = 0x3
5061 11:08:23.470902 RL = 0x3
5062 11:08:23.470994 BL = 0x2
5063 11:08:23.474148 RPST = 0x0
5064 11:08:23.474234 RD_PRE = 0x0
5065 11:08:23.477520 WR_PRE = 0x1
5066 11:08:23.477644 WR_PST = 0x0
5067 11:08:23.480843 DBI_WR = 0x0
5068 11:08:23.480967 DBI_RD = 0x0
5069 11:08:23.484002 OTF = 0x1
5070 11:08:23.487692 ===================================
5071 11:08:23.490626 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5072 11:08:23.493883 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5073 11:08:23.500918 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5074 11:08:23.504008 ===================================
5075 11:08:23.504148 LPDDR4 DRAM CONFIGURATION
5076 11:08:23.507169 ===================================
5077 11:08:23.510618 EX_ROW_EN[0] = 0x10
5078 11:08:23.510744 EX_ROW_EN[1] = 0x0
5079 11:08:23.514144 LP4Y_EN = 0x0
5080 11:08:23.517292 WORK_FSP = 0x0
5081 11:08:23.517403 WL = 0x3
5082 11:08:23.520760 RL = 0x3
5083 11:08:23.520887 BL = 0x2
5084 11:08:23.524001 RPST = 0x0
5085 11:08:23.524107 RD_PRE = 0x0
5086 11:08:23.527254 WR_PRE = 0x1
5087 11:08:23.527333 WR_PST = 0x0
5088 11:08:23.530483 DBI_WR = 0x0
5089 11:08:23.530565 DBI_RD = 0x0
5090 11:08:23.534070 OTF = 0x1
5091 11:08:23.537462 ===================================
5092 11:08:23.543944 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5093 11:08:23.547290 nWR fixed to 30
5094 11:08:23.547378 [ModeRegInit_LP4] CH0 RK0
5095 11:08:23.550408 [ModeRegInit_LP4] CH0 RK1
5096 11:08:23.553578 [ModeRegInit_LP4] CH1 RK0
5097 11:08:23.553701 [ModeRegInit_LP4] CH1 RK1
5098 11:08:23.557208 match AC timing 9
5099 11:08:23.560722 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5100 11:08:23.563485 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5101 11:08:23.570406 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5102 11:08:23.573601 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5103 11:08:23.580316 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5104 11:08:23.580401 ==
5105 11:08:23.583609 Dram Type= 6, Freq= 0, CH_0, rank 0
5106 11:08:23.587033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 11:08:23.587119 ==
5108 11:08:23.593518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5109 11:08:23.600457 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5110 11:08:23.603452 [CA 0] Center 37 (6~68) winsize 63
5111 11:08:23.606603 [CA 1] Center 37 (6~68) winsize 63
5112 11:08:23.609916 [CA 2] Center 34 (4~65) winsize 62
5113 11:08:23.613193 [CA 3] Center 34 (3~65) winsize 63
5114 11:08:23.616416 [CA 4] Center 33 (3~64) winsize 62
5115 11:08:23.616503 [CA 5] Center 32 (2~62) winsize 61
5116 11:08:23.619744
5117 11:08:23.623126 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5118 11:08:23.623213
5119 11:08:23.626856 [CATrainingPosCal] consider 1 rank data
5120 11:08:23.629819 u2DelayCellTimex100 = 270/100 ps
5121 11:08:23.633295 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5122 11:08:23.636774 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5123 11:08:23.640185 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5124 11:08:23.643534 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5125 11:08:23.646628 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5126 11:08:23.649967 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5127 11:08:23.650060
5128 11:08:23.653287 CA PerBit enable=1, Macro0, CA PI delay=32
5129 11:08:23.653381
5130 11:08:23.656661 [CBTSetCACLKResult] CA Dly = 32
5131 11:08:23.659963 CS Dly: 5 (0~36)
5132 11:08:23.660082 ==
5133 11:08:23.663205 Dram Type= 6, Freq= 0, CH_0, rank 1
5134 11:08:23.666493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 11:08:23.666583 ==
5136 11:08:23.673276 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5137 11:08:23.679764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5138 11:08:23.683533 [CA 0] Center 37 (6~68) winsize 63
5139 11:08:23.686437 [CA 1] Center 37 (6~68) winsize 63
5140 11:08:23.689677 [CA 2] Center 34 (4~65) winsize 62
5141 11:08:23.692990 [CA 3] Center 34 (4~64) winsize 61
5142 11:08:23.696308 [CA 4] Center 33 (3~64) winsize 62
5143 11:08:23.699747 [CA 5] Center 32 (2~62) winsize 61
5144 11:08:23.699862
5145 11:08:23.702889 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5146 11:08:23.702972
5147 11:08:23.706823 [CATrainingPosCal] consider 2 rank data
5148 11:08:23.709946 u2DelayCellTimex100 = 270/100 ps
5149 11:08:23.713178 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5150 11:08:23.716320 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5151 11:08:23.719824 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5152 11:08:23.723110 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5153 11:08:23.726431 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5154 11:08:23.729765 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5155 11:08:23.729889
5156 11:08:23.736317 CA PerBit enable=1, Macro0, CA PI delay=32
5157 11:08:23.736446
5158 11:08:23.736562 [CBTSetCACLKResult] CA Dly = 32
5159 11:08:23.740046 CS Dly: 5 (0~37)
5160 11:08:23.740169
5161 11:08:23.743174 ----->DramcWriteLeveling(PI) begin...
5162 11:08:23.743298 ==
5163 11:08:23.746287 Dram Type= 6, Freq= 0, CH_0, rank 0
5164 11:08:23.749788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 11:08:23.749892 ==
5166 11:08:23.753375 Write leveling (Byte 0): 33 => 33
5167 11:08:23.756693 Write leveling (Byte 1): 31 => 31
5168 11:08:23.759927 DramcWriteLeveling(PI) end<-----
5169 11:08:23.760010
5170 11:08:23.760075 ==
5171 11:08:23.763289 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 11:08:23.766521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 11:08:23.766643 ==
5174 11:08:23.769913 [Gating] SW mode calibration
5175 11:08:23.776587 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5176 11:08:23.783170 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5177 11:08:23.786269 0 14 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5178 11:08:23.792853 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 11:08:23.796164 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 11:08:23.799626 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 11:08:23.806167 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 11:08:23.809547 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 11:08:23.812848 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5184 11:08:23.819451 0 14 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
5185 11:08:23.823328 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
5186 11:08:23.826439 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 11:08:23.832917 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 11:08:23.836229 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 11:08:23.839456 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 11:08:23.843321 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 11:08:23.849774 0 15 24 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
5192 11:08:23.853208 0 15 28 | B1->B0 | 2323 3f3f | 0 1 | (0 0) (0 0)
5193 11:08:23.856461 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5194 11:08:23.863209 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 11:08:23.866106 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 11:08:23.869499 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 11:08:23.875927 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 11:08:23.879289 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 11:08:23.882571 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5200 11:08:23.889275 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5201 11:08:23.892653 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5202 11:08:23.896132 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 11:08:23.902836 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 11:08:23.906010 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 11:08:23.909145 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 11:08:23.916148 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 11:08:23.919350 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 11:08:23.922503 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 11:08:23.929358 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 11:08:23.932311 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 11:08:23.936135 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 11:08:23.942443 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 11:08:23.946129 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 11:08:23.948941 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 11:08:23.955963 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 11:08:23.959390 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5217 11:08:23.962641 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 11:08:23.966031 Total UI for P1: 0, mck2ui 16
5219 11:08:23.969339 best dqsien dly found for B0: ( 1, 2, 28)
5220 11:08:23.972439 Total UI for P1: 0, mck2ui 16
5221 11:08:23.975768 best dqsien dly found for B1: ( 1, 2, 30)
5222 11:08:23.979160 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5223 11:08:23.982125 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5224 11:08:23.982205
5225 11:08:23.985842 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5226 11:08:23.992259 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5227 11:08:23.992382 [Gating] SW calibration Done
5228 11:08:23.992458 ==
5229 11:08:23.995605 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 11:08:24.002110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 11:08:24.002253 ==
5232 11:08:24.002366 RX Vref Scan: 0
5233 11:08:24.002459
5234 11:08:24.005561 RX Vref 0 -> 0, step: 1
5235 11:08:24.005682
5236 11:08:24.008790 RX Delay -80 -> 252, step: 8
5237 11:08:24.012107 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5238 11:08:24.015981 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5239 11:08:24.019283 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5240 11:08:24.025955 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5241 11:08:24.029212 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5242 11:08:24.032272 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5243 11:08:24.035868 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5244 11:08:24.038814 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5245 11:08:24.042587 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5246 11:08:24.048831 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5247 11:08:24.052604 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5248 11:08:24.055848 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5249 11:08:24.059035 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5250 11:08:24.062041 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5251 11:08:24.065507 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5252 11:08:24.072124 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5253 11:08:24.072239 ==
5254 11:08:24.075665 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 11:08:24.078691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 11:08:24.078772 ==
5257 11:08:24.078846 DQS Delay:
5258 11:08:24.082111 DQS0 = 0, DQS1 = 0
5259 11:08:24.082190 DQM Delay:
5260 11:08:24.085467 DQM0 = 105, DQM1 = 94
5261 11:08:24.085545 DQ Delay:
5262 11:08:24.089359 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5263 11:08:24.092261 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5264 11:08:24.095468 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5265 11:08:24.099037 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =103
5266 11:08:24.099119
5267 11:08:24.099186
5268 11:08:24.099278 ==
5269 11:08:24.102454 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 11:08:24.108533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 11:08:24.108620 ==
5272 11:08:24.108688
5273 11:08:24.108774
5274 11:08:24.108843 TX Vref Scan disable
5275 11:08:24.112578 == TX Byte 0 ==
5276 11:08:24.115810 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5277 11:08:24.119219 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5278 11:08:24.122524 == TX Byte 1 ==
5279 11:08:24.125777 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5280 11:08:24.129208 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5281 11:08:24.132534 ==
5282 11:08:24.135863 Dram Type= 6, Freq= 0, CH_0, rank 0
5283 11:08:24.139151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 11:08:24.139256 ==
5285 11:08:24.139350
5286 11:08:24.139414
5287 11:08:24.142303 TX Vref Scan disable
5288 11:08:24.142408 == TX Byte 0 ==
5289 11:08:24.148713 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5290 11:08:24.152214 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5291 11:08:24.152322 == TX Byte 1 ==
5292 11:08:24.158663 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5293 11:08:24.161867 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5294 11:08:24.161977
5295 11:08:24.162070 [DATLAT]
5296 11:08:24.165211 Freq=933, CH0 RK0
5297 11:08:24.165318
5298 11:08:24.165412 DATLAT Default: 0xd
5299 11:08:24.168890 0, 0xFFFF, sum = 0
5300 11:08:24.169010 1, 0xFFFF, sum = 0
5301 11:08:24.172205 2, 0xFFFF, sum = 0
5302 11:08:24.172316 3, 0xFFFF, sum = 0
5303 11:08:24.175415 4, 0xFFFF, sum = 0
5304 11:08:24.175495 5, 0xFFFF, sum = 0
5305 11:08:24.178440 6, 0xFFFF, sum = 0
5306 11:08:24.181868 7, 0xFFFF, sum = 0
5307 11:08:24.181981 8, 0xFFFF, sum = 0
5308 11:08:24.185170 9, 0xFFFF, sum = 0
5309 11:08:24.185267 10, 0x0, sum = 1
5310 11:08:24.188708 11, 0x0, sum = 2
5311 11:08:24.188789 12, 0x0, sum = 3
5312 11:08:24.188856 13, 0x0, sum = 4
5313 11:08:24.192000 best_step = 11
5314 11:08:24.192106
5315 11:08:24.192197 ==
5316 11:08:24.195013 Dram Type= 6, Freq= 0, CH_0, rank 0
5317 11:08:24.198758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 11:08:24.198865 ==
5319 11:08:24.201970 RX Vref Scan: 1
5320 11:08:24.202078
5321 11:08:24.202175 RX Vref 0 -> 0, step: 1
5322 11:08:24.205290
5323 11:08:24.205399 RX Delay -53 -> 252, step: 4
5324 11:08:24.205496
5325 11:08:24.208600 Set Vref, RX VrefLevel [Byte0]: 58
5326 11:08:24.211636 [Byte1]: 54
5327 11:08:24.216464
5328 11:08:24.216574 Final RX Vref Byte 0 = 58 to rank0
5329 11:08:24.219718 Final RX Vref Byte 1 = 54 to rank0
5330 11:08:24.223044 Final RX Vref Byte 0 = 58 to rank1
5331 11:08:24.225896 Final RX Vref Byte 1 = 54 to rank1==
5332 11:08:24.229279 Dram Type= 6, Freq= 0, CH_0, rank 0
5333 11:08:24.235952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 11:08:24.236046 ==
5335 11:08:24.236144 DQS Delay:
5336 11:08:24.236259 DQS0 = 0, DQS1 = 0
5337 11:08:24.239272 DQM Delay:
5338 11:08:24.239342 DQM0 = 105, DQM1 = 96
5339 11:08:24.242564 DQ Delay:
5340 11:08:24.246365 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5341 11:08:24.249627 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =112
5342 11:08:24.252800 DQ8 =86, DQ9 =88, DQ10 =96, DQ11 =92
5343 11:08:24.256137 DQ12 =100, DQ13 =102, DQ14 =104, DQ15 =104
5344 11:08:24.256220
5345 11:08:24.256293
5346 11:08:24.262417 [DQSOSCAuto] RK0, (LSB)MR18= 0x3129, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5347 11:08:24.265757 CH0 RK0: MR19=505, MR18=3129
5348 11:08:24.272893 CH0_RK0: MR19=0x505, MR18=0x3129, DQSOSC=406, MR23=63, INC=65, DEC=43
5349 11:08:24.272978
5350 11:08:24.276109 ----->DramcWriteLeveling(PI) begin...
5351 11:08:24.276219 ==
5352 11:08:24.279535 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 11:08:24.282711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 11:08:24.286026 ==
5355 11:08:24.286144 Write leveling (Byte 0): 33 => 33
5356 11:08:24.289277 Write leveling (Byte 1): 31 => 31
5357 11:08:24.292717 DramcWriteLeveling(PI) end<-----
5358 11:08:24.292814
5359 11:08:24.292880 ==
5360 11:08:24.295763 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 11:08:24.302244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 11:08:24.302353 ==
5363 11:08:24.302449 [Gating] SW mode calibration
5364 11:08:24.312374 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5365 11:08:24.315549 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5366 11:08:24.319213 0 14 0 | B1->B0 | 3131 3131 | 0 0 | (0 0) (0 0)
5367 11:08:24.325852 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 11:08:24.328914 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 11:08:24.332310 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 11:08:24.339098 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 11:08:24.342470 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 11:08:24.345777 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
5373 11:08:24.352205 0 14 28 | B1->B0 | 2626 2727 | 1 0 | (0 0) (1 0)
5374 11:08:24.355350 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5375 11:08:24.358636 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 11:08:24.365239 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 11:08:24.369172 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 11:08:24.372555 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 11:08:24.379066 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 11:08:24.382242 0 15 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5381 11:08:24.385442 0 15 28 | B1->B0 | 3a3a 3535 | 0 0 | (1 1) (0 0)
5382 11:08:24.392107 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5383 11:08:24.395433 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 11:08:24.398681 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 11:08:24.405179 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 11:08:24.409157 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 11:08:24.411832 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 11:08:24.419149 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 11:08:24.421947 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5390 11:08:24.425303 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5391 11:08:24.431778 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 11:08:24.434911 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 11:08:24.438109 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 11:08:24.444724 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 11:08:24.448439 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 11:08:24.451634 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 11:08:24.458466 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 11:08:24.461788 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 11:08:24.465053 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 11:08:24.468173 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 11:08:24.475327 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 11:08:24.478684 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 11:08:24.481981 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 11:08:24.488351 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5405 11:08:24.491662 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5406 11:08:24.494934 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 11:08:24.498180 Total UI for P1: 0, mck2ui 16
5408 11:08:24.501497 best dqsien dly found for B0: ( 1, 2, 26)
5409 11:08:24.504792 Total UI for P1: 0, mck2ui 16
5410 11:08:24.508167 best dqsien dly found for B1: ( 1, 2, 28)
5411 11:08:24.511830 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5412 11:08:24.515070 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5413 11:08:24.515176
5414 11:08:24.521470 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5415 11:08:24.524659 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5416 11:08:24.527876 [Gating] SW calibration Done
5417 11:08:24.527986 ==
5418 11:08:24.531218 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 11:08:24.534614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 11:08:24.534693 ==
5421 11:08:24.534766 RX Vref Scan: 0
5422 11:08:24.534827
5423 11:08:24.538468 RX Vref 0 -> 0, step: 1
5424 11:08:24.538541
5425 11:08:24.541756 RX Delay -80 -> 252, step: 8
5426 11:08:24.545206 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5427 11:08:24.547930 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5428 11:08:24.555024 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5429 11:08:24.558503 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5430 11:08:24.561611 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5431 11:08:24.564630 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5432 11:08:24.568170 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5433 11:08:24.571730 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5434 11:08:24.577934 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5435 11:08:24.581144 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5436 11:08:24.584620 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5437 11:08:24.587946 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5438 11:08:24.591175 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5439 11:08:24.594490 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5440 11:08:24.601105 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5441 11:08:24.604348 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5442 11:08:24.604454 ==
5443 11:08:24.607566 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 11:08:24.611468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 11:08:24.611573 ==
5446 11:08:24.614704 DQS Delay:
5447 11:08:24.614818 DQS0 = 0, DQS1 = 0
5448 11:08:24.614912 DQM Delay:
5449 11:08:24.617836 DQM0 = 106, DQM1 = 95
5450 11:08:24.617920 DQ Delay:
5451 11:08:24.621160 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =103
5452 11:08:24.624342 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5453 11:08:24.627694 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5454 11:08:24.630851 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5455 11:08:24.630958
5456 11:08:24.631060
5457 11:08:24.634744 ==
5458 11:08:24.637405 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 11:08:24.640670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 11:08:24.640776 ==
5461 11:08:24.640879
5462 11:08:24.640970
5463 11:08:24.644519 TX Vref Scan disable
5464 11:08:24.644596 == TX Byte 0 ==
5465 11:08:24.647238 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5466 11:08:24.654486 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5467 11:08:24.654568 == TX Byte 1 ==
5468 11:08:24.657757 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5469 11:08:24.664423 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5470 11:08:24.664529 ==
5471 11:08:24.667764 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 11:08:24.671080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 11:08:24.671187 ==
5474 11:08:24.671280
5475 11:08:24.671368
5476 11:08:24.673776 TX Vref Scan disable
5477 11:08:24.677155 == TX Byte 0 ==
5478 11:08:24.680367 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5479 11:08:24.683666 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5480 11:08:24.687266 == TX Byte 1 ==
5481 11:08:24.690956 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5482 11:08:24.693851 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5483 11:08:24.693931
5484 11:08:24.697308 [DATLAT]
5485 11:08:24.697412 Freq=933, CH0 RK1
5486 11:08:24.697507
5487 11:08:24.700687 DATLAT Default: 0xb
5488 11:08:24.700772 0, 0xFFFF, sum = 0
5489 11:08:24.704134 1, 0xFFFF, sum = 0
5490 11:08:24.704245 2, 0xFFFF, sum = 0
5491 11:08:24.707520 3, 0xFFFF, sum = 0
5492 11:08:24.707603 4, 0xFFFF, sum = 0
5493 11:08:24.710631 5, 0xFFFF, sum = 0
5494 11:08:24.710743 6, 0xFFFF, sum = 0
5495 11:08:24.713801 7, 0xFFFF, sum = 0
5496 11:08:24.713884 8, 0xFFFF, sum = 0
5497 11:08:24.717569 9, 0xFFFF, sum = 0
5498 11:08:24.717674 10, 0x0, sum = 1
5499 11:08:24.720363 11, 0x0, sum = 2
5500 11:08:24.720442 12, 0x0, sum = 3
5501 11:08:24.724088 13, 0x0, sum = 4
5502 11:08:24.724197 best_step = 11
5503 11:08:24.724298
5504 11:08:24.724389 ==
5505 11:08:24.727168 Dram Type= 6, Freq= 0, CH_0, rank 1
5506 11:08:24.730769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 11:08:24.733680 ==
5508 11:08:24.733790 RX Vref Scan: 0
5509 11:08:24.733903
5510 11:08:24.737361 RX Vref 0 -> 0, step: 1
5511 11:08:24.737457
5512 11:08:24.740537 RX Delay -45 -> 252, step: 4
5513 11:08:24.743848 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5514 11:08:24.746932 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5515 11:08:24.754309 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5516 11:08:24.757549 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5517 11:08:24.760210 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5518 11:08:24.763591 iDelay=199, Bit 5, Center 100 (15 ~ 186) 172
5519 11:08:24.766863 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5520 11:08:24.770199 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5521 11:08:24.776837 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5522 11:08:24.780133 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5523 11:08:24.783495 iDelay=199, Bit 10, Center 96 (15 ~ 178) 164
5524 11:08:24.787504 iDelay=199, Bit 11, Center 90 (11 ~ 170) 160
5525 11:08:24.790117 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5526 11:08:24.797149 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5527 11:08:24.800444 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5528 11:08:24.803599 iDelay=199, Bit 15, Center 104 (23 ~ 186) 164
5529 11:08:24.803704 ==
5530 11:08:24.807147 Dram Type= 6, Freq= 0, CH_0, rank 1
5531 11:08:24.810531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 11:08:24.810647 ==
5533 11:08:24.813802 DQS Delay:
5534 11:08:24.813913 DQS0 = 0, DQS1 = 0
5535 11:08:24.817121 DQM Delay:
5536 11:08:24.817234 DQM0 = 105, DQM1 = 95
5537 11:08:24.817337 DQ Delay:
5538 11:08:24.823392 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5539 11:08:24.826690 DQ4 =106, DQ5 =100, DQ6 =110, DQ7 =112
5540 11:08:24.830187 DQ8 =86, DQ9 =86, DQ10 =96, DQ11 =90
5541 11:08:24.833306 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5542 11:08:24.833437
5543 11:08:24.833544
5544 11:08:24.840028 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5545 11:08:24.843351 CH0 RK1: MR19=505, MR18=2C05
5546 11:08:24.849787 CH0_RK1: MR19=0x505, MR18=0x2C05, DQSOSC=408, MR23=63, INC=65, DEC=43
5547 11:08:24.853024 [RxdqsGatingPostProcess] freq 933
5548 11:08:24.859446 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5549 11:08:24.859531 best DQS0 dly(2T, 0.5T) = (0, 10)
5550 11:08:24.862964 best DQS1 dly(2T, 0.5T) = (0, 10)
5551 11:08:24.866335 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5552 11:08:24.869432 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5553 11:08:24.873071 best DQS0 dly(2T, 0.5T) = (0, 10)
5554 11:08:24.876244 best DQS1 dly(2T, 0.5T) = (0, 10)
5555 11:08:24.879647 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5556 11:08:24.882912 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5557 11:08:24.886223 Pre-setting of DQS Precalculation
5558 11:08:24.892952 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5559 11:08:24.893031 ==
5560 11:08:24.896182 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 11:08:24.899536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 11:08:24.899635 ==
5563 11:08:24.906219 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5564 11:08:24.909290 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5565 11:08:24.913468 [CA 0] Center 36 (6~67) winsize 62
5566 11:08:24.916495 [CA 1] Center 37 (6~68) winsize 63
5567 11:08:24.919736 [CA 2] Center 35 (5~65) winsize 61
5568 11:08:24.923445 [CA 3] Center 34 (4~65) winsize 62
5569 11:08:24.926732 [CA 4] Center 34 (4~65) winsize 62
5570 11:08:24.929870 [CA 5] Center 33 (3~64) winsize 62
5571 11:08:24.929953
5572 11:08:24.933207 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5573 11:08:24.933290
5574 11:08:24.936524 [CATrainingPosCal] consider 1 rank data
5575 11:08:24.939863 u2DelayCellTimex100 = 270/100 ps
5576 11:08:24.943149 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5577 11:08:24.949871 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5578 11:08:24.953215 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5579 11:08:24.956451 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5580 11:08:24.959652 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5581 11:08:24.963043 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5582 11:08:24.963137
5583 11:08:24.966385 CA PerBit enable=1, Macro0, CA PI delay=33
5584 11:08:24.966487
5585 11:08:24.969435 [CBTSetCACLKResult] CA Dly = 33
5586 11:08:24.973014 CS Dly: 7 (0~38)
5587 11:08:24.973094 ==
5588 11:08:24.975974 Dram Type= 6, Freq= 0, CH_1, rank 1
5589 11:08:24.979301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5590 11:08:24.979381 ==
5591 11:08:24.986396 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5592 11:08:24.989125 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5593 11:08:24.993284 [CA 0] Center 36 (6~67) winsize 62
5594 11:08:24.996525 [CA 1] Center 37 (6~68) winsize 63
5595 11:08:25.000340 [CA 2] Center 35 (5~65) winsize 61
5596 11:08:25.003162 [CA 3] Center 34 (4~65) winsize 62
5597 11:08:25.007129 [CA 4] Center 34 (4~65) winsize 62
5598 11:08:25.010480 [CA 5] Center 33 (3~64) winsize 62
5599 11:08:25.010571
5600 11:08:25.013922 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5601 11:08:25.014007
5602 11:08:25.016568 [CATrainingPosCal] consider 2 rank data
5603 11:08:25.020412 u2DelayCellTimex100 = 270/100 ps
5604 11:08:25.023312 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5605 11:08:25.027008 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5606 11:08:25.033325 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5607 11:08:25.036443 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5608 11:08:25.039802 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5609 11:08:25.043184 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5610 11:08:25.043313
5611 11:08:25.046424 CA PerBit enable=1, Macro0, CA PI delay=33
5612 11:08:25.046550
5613 11:08:25.049829 [CBTSetCACLKResult] CA Dly = 33
5614 11:08:25.049915 CS Dly: 8 (0~40)
5615 11:08:25.049983
5616 11:08:25.053276 ----->DramcWriteLeveling(PI) begin...
5617 11:08:25.056548 ==
5618 11:08:25.059816 Dram Type= 6, Freq= 0, CH_1, rank 0
5619 11:08:25.062982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 11:08:25.063091 ==
5621 11:08:25.066848 Write leveling (Byte 0): 28 => 28
5622 11:08:25.069592 Write leveling (Byte 1): 26 => 26
5623 11:08:25.073066 DramcWriteLeveling(PI) end<-----
5624 11:08:25.073151
5625 11:08:25.073217 ==
5626 11:08:25.076307 Dram Type= 6, Freq= 0, CH_1, rank 0
5627 11:08:25.079577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5628 11:08:25.079691 ==
5629 11:08:25.082850 [Gating] SW mode calibration
5630 11:08:25.089809 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5631 11:08:25.096413 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5632 11:08:25.100098 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 11:08:25.103112 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 11:08:25.106540 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 11:08:25.113146 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 11:08:25.116615 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 11:08:25.119528 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 11:08:25.126459 0 14 24 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
5639 11:08:25.129473 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
5640 11:08:25.133214 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 11:08:25.139738 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 11:08:25.143282 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 11:08:25.146318 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 11:08:25.153127 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 11:08:25.156333 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 11:08:25.159697 0 15 24 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
5647 11:08:25.166485 0 15 28 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
5648 11:08:25.169787 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 11:08:25.173167 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 11:08:25.179876 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 11:08:25.183263 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 11:08:25.186538 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 11:08:25.193105 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 11:08:25.196818 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5655 11:08:25.200136 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 11:08:25.206734 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 11:08:25.210038 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 11:08:25.213235 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 11:08:25.216187 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 11:08:25.223286 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 11:08:25.226490 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 11:08:25.229549 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 11:08:25.236148 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 11:08:25.239681 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 11:08:25.242812 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 11:08:25.249388 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 11:08:25.252929 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 11:08:25.256247 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 11:08:25.262447 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 11:08:25.266230 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5671 11:08:25.269392 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5672 11:08:25.272730 Total UI for P1: 0, mck2ui 16
5673 11:08:25.275957 best dqsien dly found for B0: ( 1, 2, 24)
5674 11:08:25.282718 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5675 11:08:25.282801 Total UI for P1: 0, mck2ui 16
5676 11:08:25.289107 best dqsien dly found for B1: ( 1, 2, 26)
5677 11:08:25.292977 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5678 11:08:25.296167 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5679 11:08:25.296294
5680 11:08:25.299281 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5681 11:08:25.302632 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5682 11:08:25.305905 [Gating] SW calibration Done
5683 11:08:25.306017 ==
5684 11:08:25.309241 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 11:08:25.312592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 11:08:25.312673 ==
5687 11:08:25.315941 RX Vref Scan: 0
5688 11:08:25.316054
5689 11:08:25.316162 RX Vref 0 -> 0, step: 1
5690 11:08:25.316261
5691 11:08:25.319153 RX Delay -80 -> 252, step: 8
5692 11:08:25.322340 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5693 11:08:25.329521 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5694 11:08:25.332729 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5695 11:08:25.336036 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5696 11:08:25.339435 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5697 11:08:25.342666 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5698 11:08:25.346119 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5699 11:08:25.352686 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5700 11:08:25.355819 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5701 11:08:25.358844 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5702 11:08:25.362497 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5703 11:08:25.365823 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5704 11:08:25.369010 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5705 11:08:25.375435 iDelay=208, Bit 13, Center 111 (24 ~ 199) 176
5706 11:08:25.379057 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5707 11:08:25.382229 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5708 11:08:25.382344 ==
5709 11:08:25.385887 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 11:08:25.389165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 11:08:25.392607 ==
5712 11:08:25.392714 DQS Delay:
5713 11:08:25.392816 DQS0 = 0, DQS1 = 0
5714 11:08:25.395915 DQM Delay:
5715 11:08:25.396022 DQM0 = 103, DQM1 = 99
5716 11:08:25.399064 DQ Delay:
5717 11:08:25.402280 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5718 11:08:25.405555 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5719 11:08:25.408772 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5720 11:08:25.412161 DQ12 =107, DQ13 =111, DQ14 =103, DQ15 =107
5721 11:08:25.412245
5722 11:08:25.412320
5723 11:08:25.412385 ==
5724 11:08:25.415493 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 11:08:25.418722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 11:08:25.418807 ==
5727 11:08:25.418872
5728 11:08:25.418933
5729 11:08:25.422090 TX Vref Scan disable
5730 11:08:25.425373 == TX Byte 0 ==
5731 11:08:25.428490 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5732 11:08:25.432441 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5733 11:08:25.435556 == TX Byte 1 ==
5734 11:08:25.438898 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5735 11:08:25.442232 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5736 11:08:25.442342 ==
5737 11:08:25.445524 Dram Type= 6, Freq= 0, CH_1, rank 0
5738 11:08:25.448802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 11:08:25.451505 ==
5740 11:08:25.451606
5741 11:08:25.451709
5742 11:08:25.451801 TX Vref Scan disable
5743 11:08:25.455490 == TX Byte 0 ==
5744 11:08:25.458712 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5745 11:08:25.465407 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5746 11:08:25.465515 == TX Byte 1 ==
5747 11:08:25.468720 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5748 11:08:25.475498 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5749 11:08:25.475606
5750 11:08:25.475711 [DATLAT]
5751 11:08:25.475803 Freq=933, CH1 RK0
5752 11:08:25.475899
5753 11:08:25.478694 DATLAT Default: 0xd
5754 11:08:25.478794 0, 0xFFFF, sum = 0
5755 11:08:25.481594 1, 0xFFFF, sum = 0
5756 11:08:25.481695 2, 0xFFFF, sum = 0
5757 11:08:25.485306 3, 0xFFFF, sum = 0
5758 11:08:25.488309 4, 0xFFFF, sum = 0
5759 11:08:25.488449 5, 0xFFFF, sum = 0
5760 11:08:25.491907 6, 0xFFFF, sum = 0
5761 11:08:25.492049 7, 0xFFFF, sum = 0
5762 11:08:25.495190 8, 0xFFFF, sum = 0
5763 11:08:25.495332 9, 0xFFFF, sum = 0
5764 11:08:25.498601 10, 0x0, sum = 1
5765 11:08:25.498719 11, 0x0, sum = 2
5766 11:08:25.498818 12, 0x0, sum = 3
5767 11:08:25.502153 13, 0x0, sum = 4
5768 11:08:25.502240 best_step = 11
5769 11:08:25.502335
5770 11:08:25.502424 ==
5771 11:08:25.505383 Dram Type= 6, Freq= 0, CH_1, rank 0
5772 11:08:25.511901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 11:08:25.512024 ==
5774 11:08:25.512122 RX Vref Scan: 1
5775 11:08:25.512224
5776 11:08:25.515202 RX Vref 0 -> 0, step: 1
5777 11:08:25.515311
5778 11:08:25.518230 RX Delay -45 -> 252, step: 4
5779 11:08:25.518337
5780 11:08:25.521603 Set Vref, RX VrefLevel [Byte0]: 53
5781 11:08:25.525157 [Byte1]: 48
5782 11:08:25.525300
5783 11:08:25.528264 Final RX Vref Byte 0 = 53 to rank0
5784 11:08:25.531666 Final RX Vref Byte 1 = 48 to rank0
5785 11:08:25.535350 Final RX Vref Byte 0 = 53 to rank1
5786 11:08:25.538442 Final RX Vref Byte 1 = 48 to rank1==
5787 11:08:25.541596 Dram Type= 6, Freq= 0, CH_1, rank 0
5788 11:08:25.545594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 11:08:25.545724 ==
5790 11:08:25.548258 DQS Delay:
5791 11:08:25.548387 DQS0 = 0, DQS1 = 0
5792 11:08:25.551665 DQM Delay:
5793 11:08:25.551787 DQM0 = 103, DQM1 = 99
5794 11:08:25.551901 DQ Delay:
5795 11:08:25.555032 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5796 11:08:25.558263 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5797 11:08:25.561566 DQ8 =90, DQ9 =90, DQ10 =98, DQ11 =92
5798 11:08:25.568189 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =108
5799 11:08:25.568325
5800 11:08:25.568442
5801 11:08:25.574909 [DQSOSCAuto] RK0, (LSB)MR18= 0x162d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5802 11:08:25.578300 CH1 RK0: MR19=505, MR18=162D
5803 11:08:25.584889 CH1_RK0: MR19=0x505, MR18=0x162D, DQSOSC=407, MR23=63, INC=65, DEC=43
5804 11:08:25.585018
5805 11:08:25.588692 ----->DramcWriteLeveling(PI) begin...
5806 11:08:25.588817 ==
5807 11:08:25.591683 Dram Type= 6, Freq= 0, CH_1, rank 1
5808 11:08:25.594947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 11:08:25.595072 ==
5810 11:08:25.598648 Write leveling (Byte 0): 25 => 25
5811 11:08:25.601394 Write leveling (Byte 1): 29 => 29
5812 11:08:25.604771 DramcWriteLeveling(PI) end<-----
5813 11:08:25.604856
5814 11:08:25.604921 ==
5815 11:08:25.608058 Dram Type= 6, Freq= 0, CH_1, rank 1
5816 11:08:25.611258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 11:08:25.611344 ==
5818 11:08:25.615237 [Gating] SW mode calibration
5819 11:08:25.621407 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5820 11:08:25.628085 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5821 11:08:25.631222 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 11:08:25.638157 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 11:08:25.641538 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 11:08:25.644597 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 11:08:25.651056 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 11:08:25.654690 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 11:08:25.658042 0 14 24 | B1->B0 | 2f2f 3131 | 1 1 | (1 0) (1 1)
5828 11:08:25.661093 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5829 11:08:25.667653 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 11:08:25.670986 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 11:08:25.674232 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 11:08:25.680917 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 11:08:25.684228 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 11:08:25.687704 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 11:08:25.694219 0 15 24 | B1->B0 | 3737 2c2b | 0 1 | (0 0) (0 0)
5836 11:08:25.698171 0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5837 11:08:25.701157 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 11:08:25.707706 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 11:08:25.710968 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 11:08:25.714205 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 11:08:25.720639 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 11:08:25.724467 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5843 11:08:25.727700 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5844 11:08:25.734162 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5845 11:08:25.737975 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 11:08:25.741295 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 11:08:25.747873 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 11:08:25.750817 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 11:08:25.754138 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 11:08:25.761228 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 11:08:25.764149 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 11:08:25.767226 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 11:08:25.773986 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 11:08:25.777226 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 11:08:25.780949 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 11:08:25.787616 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 11:08:25.791035 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 11:08:25.793702 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 11:08:25.800737 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 11:08:25.803731 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5861 11:08:25.807625 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5862 11:08:25.810851 Total UI for P1: 0, mck2ui 16
5863 11:08:25.814224 best dqsien dly found for B0: ( 1, 2, 28)
5864 11:08:25.817547 Total UI for P1: 0, mck2ui 16
5865 11:08:25.820911 best dqsien dly found for B1: ( 1, 2, 28)
5866 11:08:25.824196 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5867 11:08:25.827341 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5868 11:08:25.827426
5869 11:08:25.830559 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5870 11:08:25.837275 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5871 11:08:25.837402 [Gating] SW calibration Done
5872 11:08:25.837517 ==
5873 11:08:25.840355 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 11:08:25.847314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 11:08:25.847425 ==
5876 11:08:25.847521 RX Vref Scan: 0
5877 11:08:25.847612
5878 11:08:25.850641 RX Vref 0 -> 0, step: 1
5879 11:08:25.850762
5880 11:08:25.853898 RX Delay -80 -> 252, step: 8
5881 11:08:25.857047 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5882 11:08:25.860279 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5883 11:08:25.863570 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5884 11:08:25.866857 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5885 11:08:25.873551 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5886 11:08:25.877414 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5887 11:08:25.880673 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5888 11:08:25.883812 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5889 11:08:25.886938 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5890 11:08:25.890441 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5891 11:08:25.896789 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5892 11:08:25.900109 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5893 11:08:25.903536 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5894 11:08:25.906608 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5895 11:08:25.910280 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5896 11:08:25.917024 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5897 11:08:25.917174 ==
5898 11:08:25.920220 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 11:08:25.923589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 11:08:25.923734 ==
5901 11:08:25.923851 DQS Delay:
5902 11:08:25.926750 DQS0 = 0, DQS1 = 0
5903 11:08:25.926834 DQM Delay:
5904 11:08:25.929991 DQM0 = 102, DQM1 = 99
5905 11:08:25.930131 DQ Delay:
5906 11:08:25.933874 DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =99
5907 11:08:25.937127 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5908 11:08:25.940446 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =91
5909 11:08:25.943678 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5910 11:08:25.943786
5911 11:08:25.943883
5912 11:08:25.943976 ==
5913 11:08:25.946969 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 11:08:25.953194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 11:08:25.953288 ==
5916 11:08:25.953360
5917 11:08:25.953465
5918 11:08:25.953575 TX Vref Scan disable
5919 11:08:25.956548 == TX Byte 0 ==
5920 11:08:25.960241 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5921 11:08:25.966639 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5922 11:08:25.966773 == TX Byte 1 ==
5923 11:08:25.969977 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5924 11:08:25.976531 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5925 11:08:25.976659 ==
5926 11:08:25.979892 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 11:08:25.983128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 11:08:25.983254 ==
5929 11:08:25.983366
5930 11:08:25.983476
5931 11:08:25.986514 TX Vref Scan disable
5932 11:08:25.986634 == TX Byte 0 ==
5933 11:08:25.993192 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5934 11:08:25.996420 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5935 11:08:25.996550 == TX Byte 1 ==
5936 11:08:26.003513 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5937 11:08:26.006542 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5938 11:08:26.006662
5939 11:08:26.006778 [DATLAT]
5940 11:08:26.010053 Freq=933, CH1 RK1
5941 11:08:26.010191
5942 11:08:26.010318 DATLAT Default: 0xb
5943 11:08:26.013553 0, 0xFFFF, sum = 0
5944 11:08:26.013638 1, 0xFFFF, sum = 0
5945 11:08:26.016617 2, 0xFFFF, sum = 0
5946 11:08:26.016700 3, 0xFFFF, sum = 0
5947 11:08:26.020049 4, 0xFFFF, sum = 0
5948 11:08:26.020161 5, 0xFFFF, sum = 0
5949 11:08:26.023080 6, 0xFFFF, sum = 0
5950 11:08:26.026419 7, 0xFFFF, sum = 0
5951 11:08:26.026527 8, 0xFFFF, sum = 0
5952 11:08:26.030019 9, 0xFFFF, sum = 0
5953 11:08:26.030105 10, 0x0, sum = 1
5954 11:08:26.030172 11, 0x0, sum = 2
5955 11:08:26.032990 12, 0x0, sum = 3
5956 11:08:26.033117 13, 0x0, sum = 4
5957 11:08:26.036599 best_step = 11
5958 11:08:26.036723
5959 11:08:26.036837 ==
5960 11:08:26.039651 Dram Type= 6, Freq= 0, CH_1, rank 1
5961 11:08:26.043368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5962 11:08:26.043497 ==
5963 11:08:26.046582 RX Vref Scan: 0
5964 11:08:26.046669
5965 11:08:26.046745 RX Vref 0 -> 0, step: 1
5966 11:08:26.046814
5967 11:08:26.049943 RX Delay -45 -> 252, step: 4
5968 11:08:26.057013 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5969 11:08:26.060601 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5970 11:08:26.063881 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5971 11:08:26.067056 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5972 11:08:26.070382 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5973 11:08:26.076928 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5974 11:08:26.080129 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5975 11:08:26.084046 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5976 11:08:26.087359 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5977 11:08:26.090601 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5978 11:08:26.093956 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5979 11:08:26.100649 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5980 11:08:26.103854 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5981 11:08:26.107150 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5982 11:08:26.110389 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5983 11:08:26.116903 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5984 11:08:26.117018 ==
5985 11:08:26.120801 Dram Type= 6, Freq= 0, CH_1, rank 1
5986 11:08:26.124122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5987 11:08:26.124230 ==
5988 11:08:26.124339 DQS Delay:
5989 11:08:26.127279 DQS0 = 0, DQS1 = 0
5990 11:08:26.127381 DQM Delay:
5991 11:08:26.130514 DQM0 = 104, DQM1 = 100
5992 11:08:26.130604 DQ Delay:
5993 11:08:26.133577 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5994 11:08:26.137166 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5995 11:08:26.140135 DQ8 =88, DQ9 =88, DQ10 =102, DQ11 =94
5996 11:08:26.143490 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5997 11:08:26.143569
5998 11:08:26.143635
5999 11:08:26.153208 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bfe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
6000 11:08:26.156978 CH1 RK1: MR19=504, MR18=2BFE
6001 11:08:26.160406 CH1_RK1: MR19=0x504, MR18=0x2BFE, DQSOSC=408, MR23=63, INC=65, DEC=43
6002 11:08:26.163524 [RxdqsGatingPostProcess] freq 933
6003 11:08:26.170303 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6004 11:08:26.173272 best DQS0 dly(2T, 0.5T) = (0, 10)
6005 11:08:26.176686 best DQS1 dly(2T, 0.5T) = (0, 10)
6006 11:08:26.180252 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6007 11:08:26.183460 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6008 11:08:26.186787 best DQS0 dly(2T, 0.5T) = (0, 10)
6009 11:08:26.190031 best DQS1 dly(2T, 0.5T) = (0, 10)
6010 11:08:26.193257 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6011 11:08:26.196592 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6012 11:08:26.196671 Pre-setting of DQS Precalculation
6013 11:08:26.203278 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6014 11:08:26.209874 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6015 11:08:26.216630 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6016 11:08:26.216714
6017 11:08:26.216779
6018 11:08:26.219951 [Calibration Summary] 1866 Mbps
6019 11:08:26.223106 CH 0, Rank 0
6020 11:08:26.223196 SW Impedance : PASS
6021 11:08:26.226349 DUTY Scan : NO K
6022 11:08:26.229639 ZQ Calibration : PASS
6023 11:08:26.229722 Jitter Meter : NO K
6024 11:08:26.233254 CBT Training : PASS
6025 11:08:26.236436 Write leveling : PASS
6026 11:08:26.236519 RX DQS gating : PASS
6027 11:08:26.239782 RX DQ/DQS(RDDQC) : PASS
6028 11:08:26.243080 TX DQ/DQS : PASS
6029 11:08:26.243163 RX DATLAT : PASS
6030 11:08:26.246364 RX DQ/DQS(Engine): PASS
6031 11:08:26.246447 TX OE : NO K
6032 11:08:26.249715 All Pass.
6033 11:08:26.249797
6034 11:08:26.249862 CH 0, Rank 1
6035 11:08:26.253142 SW Impedance : PASS
6036 11:08:26.253225 DUTY Scan : NO K
6037 11:08:26.256442 ZQ Calibration : PASS
6038 11:08:26.260135 Jitter Meter : NO K
6039 11:08:26.260217 CBT Training : PASS
6040 11:08:26.263205 Write leveling : PASS
6041 11:08:26.266851 RX DQS gating : PASS
6042 11:08:26.266933 RX DQ/DQS(RDDQC) : PASS
6043 11:08:26.270052 TX DQ/DQS : PASS
6044 11:08:26.273458 RX DATLAT : PASS
6045 11:08:26.273540 RX DQ/DQS(Engine): PASS
6046 11:08:26.276442 TX OE : NO K
6047 11:08:26.276528 All Pass.
6048 11:08:26.276594
6049 11:08:26.279767 CH 1, Rank 0
6050 11:08:26.279850 SW Impedance : PASS
6051 11:08:26.283233 DUTY Scan : NO K
6052 11:08:26.286504 ZQ Calibration : PASS
6053 11:08:26.286587 Jitter Meter : NO K
6054 11:08:26.289676 CBT Training : PASS
6055 11:08:26.289759 Write leveling : PASS
6056 11:08:26.293241 RX DQS gating : PASS
6057 11:08:26.296361 RX DQ/DQS(RDDQC) : PASS
6058 11:08:26.296444 TX DQ/DQS : PASS
6059 11:08:26.299492 RX DATLAT : PASS
6060 11:08:26.303409 RX DQ/DQS(Engine): PASS
6061 11:08:26.303493 TX OE : NO K
6062 11:08:26.306624 All Pass.
6063 11:08:26.306707
6064 11:08:26.306772 CH 1, Rank 1
6065 11:08:26.309879 SW Impedance : PASS
6066 11:08:26.309962 DUTY Scan : NO K
6067 11:08:26.313249 ZQ Calibration : PASS
6068 11:08:26.316583 Jitter Meter : NO K
6069 11:08:26.316667 CBT Training : PASS
6070 11:08:26.319864 Write leveling : PASS
6071 11:08:26.323248 RX DQS gating : PASS
6072 11:08:26.323372 RX DQ/DQS(RDDQC) : PASS
6073 11:08:26.326429 TX DQ/DQS : PASS
6074 11:08:26.326512 RX DATLAT : PASS
6075 11:08:26.329658 RX DQ/DQS(Engine): PASS
6076 11:08:26.332949 TX OE : NO K
6077 11:08:26.333031 All Pass.
6078 11:08:26.333096
6079 11:08:26.336443 DramC Write-DBI off
6080 11:08:26.339399 PER_BANK_REFRESH: Hybrid Mode
6081 11:08:26.339483 TX_TRACKING: ON
6082 11:08:26.349715 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6083 11:08:26.352897 [FAST_K] Save calibration result to emmc
6084 11:08:26.356159 dramc_set_vcore_voltage set vcore to 650000
6085 11:08:26.359631 Read voltage for 400, 6
6086 11:08:26.359715 Vio18 = 0
6087 11:08:26.359781 Vcore = 650000
6088 11:08:26.362931 Vdram = 0
6089 11:08:26.363014 Vddq = 0
6090 11:08:26.363081 Vmddr = 0
6091 11:08:26.369452 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6092 11:08:26.372794 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6093 11:08:26.375559 MEM_TYPE=3, freq_sel=20
6094 11:08:26.379461 sv_algorithm_assistance_LP4_800
6095 11:08:26.382790 ============ PULL DRAM RESETB DOWN ============
6096 11:08:26.385653 ========== PULL DRAM RESETB DOWN end =========
6097 11:08:26.392662 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6098 11:08:26.395802 ===================================
6099 11:08:26.395887 LPDDR4 DRAM CONFIGURATION
6100 11:08:26.399024 ===================================
6101 11:08:26.402510 EX_ROW_EN[0] = 0x0
6102 11:08:26.405381 EX_ROW_EN[1] = 0x0
6103 11:08:26.405506 LP4Y_EN = 0x0
6104 11:08:26.408798 WORK_FSP = 0x0
6105 11:08:26.408922 WL = 0x2
6106 11:08:26.412411 RL = 0x2
6107 11:08:26.412537 BL = 0x2
6108 11:08:26.415328 RPST = 0x0
6109 11:08:26.415415 RD_PRE = 0x0
6110 11:08:26.418605 WR_PRE = 0x1
6111 11:08:26.418690 WR_PST = 0x0
6112 11:08:26.422538 DBI_WR = 0x0
6113 11:08:26.422623 DBI_RD = 0x0
6114 11:08:26.425540 OTF = 0x1
6115 11:08:26.428794 ===================================
6116 11:08:26.432003 ===================================
6117 11:08:26.432130 ANA top config
6118 11:08:26.435363 ===================================
6119 11:08:26.438670 DLL_ASYNC_EN = 0
6120 11:08:26.442066 ALL_SLAVE_EN = 1
6121 11:08:26.445254 NEW_RANK_MODE = 1
6122 11:08:26.445382 DLL_IDLE_MODE = 1
6123 11:08:26.448952 LP45_APHY_COMB_EN = 1
6124 11:08:26.452171 TX_ODT_DIS = 1
6125 11:08:26.455286 NEW_8X_MODE = 1
6126 11:08:26.458585 ===================================
6127 11:08:26.461971 ===================================
6128 11:08:26.465185 data_rate = 800
6129 11:08:26.465315 CKR = 1
6130 11:08:26.468666 DQ_P2S_RATIO = 4
6131 11:08:26.472080 ===================================
6132 11:08:26.475411 CA_P2S_RATIO = 4
6133 11:08:26.478771 DQ_CA_OPEN = 0
6134 11:08:26.482145 DQ_SEMI_OPEN = 1
6135 11:08:26.485527 CA_SEMI_OPEN = 1
6136 11:08:26.485654 CA_FULL_RATE = 0
6137 11:08:26.488935 DQ_CKDIV4_EN = 0
6138 11:08:26.492103 CA_CKDIV4_EN = 1
6139 11:08:26.495300 CA_PREDIV_EN = 0
6140 11:08:26.498994 PH8_DLY = 0
6141 11:08:26.499116 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6142 11:08:26.502315 DQ_AAMCK_DIV = 0
6143 11:08:26.505022 CA_AAMCK_DIV = 0
6144 11:08:26.508742 CA_ADMCK_DIV = 4
6145 11:08:26.511844 DQ_TRACK_CA_EN = 0
6146 11:08:26.514985 CA_PICK = 800
6147 11:08:26.518797 CA_MCKIO = 400
6148 11:08:26.518921 MCKIO_SEMI = 400
6149 11:08:26.522238 PLL_FREQ = 3016
6150 11:08:26.525346 DQ_UI_PI_RATIO = 32
6151 11:08:26.528399 CA_UI_PI_RATIO = 32
6152 11:08:26.531931 ===================================
6153 11:08:26.534888 ===================================
6154 11:08:26.538401 memory_type:LPDDR4
6155 11:08:26.538521 GP_NUM : 10
6156 11:08:26.541772 SRAM_EN : 1
6157 11:08:26.545478 MD32_EN : 0
6158 11:08:26.548436 ===================================
6159 11:08:26.548545 [ANA_INIT] >>>>>>>>>>>>>>
6160 11:08:26.551620 <<<<<< [CONFIGURE PHASE]: ANA_TX
6161 11:08:26.554883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6162 11:08:26.558789 ===================================
6163 11:08:26.561783 data_rate = 800,PCW = 0X7400
6164 11:08:26.565147 ===================================
6165 11:08:26.568558 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6166 11:08:26.575258 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6167 11:08:26.585280 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6168 11:08:26.588749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6169 11:08:26.595298 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6170 11:08:26.598500 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6171 11:08:26.598627 [ANA_INIT] flow start
6172 11:08:26.601893 [ANA_INIT] PLL >>>>>>>>
6173 11:08:26.605161 [ANA_INIT] PLL <<<<<<<<
6174 11:08:26.605251 [ANA_INIT] MIDPI >>>>>>>>
6175 11:08:26.608502 [ANA_INIT] MIDPI <<<<<<<<
6176 11:08:26.611741 [ANA_INIT] DLL >>>>>>>>
6177 11:08:26.611825 [ANA_INIT] flow end
6178 11:08:26.614774 ============ LP4 DIFF to SE enter ============
6179 11:08:26.621726 ============ LP4 DIFF to SE exit ============
6180 11:08:26.621837 [ANA_INIT] <<<<<<<<<<<<<
6181 11:08:26.624727 [Flow] Enable top DCM control >>>>>
6182 11:08:26.628241 [Flow] Enable top DCM control <<<<<
6183 11:08:26.631469 Enable DLL master slave shuffle
6184 11:08:26.638066 ==============================================================
6185 11:08:26.638152 Gating Mode config
6186 11:08:26.645167 ==============================================================
6187 11:08:26.648178 Config description:
6188 11:08:26.658279 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6189 11:08:26.664829 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6190 11:08:26.668017 SELPH_MODE 0: By rank 1: By Phase
6191 11:08:26.674915 ==============================================================
6192 11:08:26.677983 GAT_TRACK_EN = 0
6193 11:08:26.681381 RX_GATING_MODE = 2
6194 11:08:26.681470 RX_GATING_TRACK_MODE = 2
6195 11:08:26.684696 SELPH_MODE = 1
6196 11:08:26.687943 PICG_EARLY_EN = 1
6197 11:08:26.691236 VALID_LAT_VALUE = 1
6198 11:08:26.697870 ==============================================================
6199 11:08:26.701129 Enter into Gating configuration >>>>
6200 11:08:26.704456 Exit from Gating configuration <<<<
6201 11:08:26.707749 Enter into DVFS_PRE_config >>>>>
6202 11:08:26.717684 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6203 11:08:26.721004 Exit from DVFS_PRE_config <<<<<
6204 11:08:26.724184 Enter into PICG configuration >>>>
6205 11:08:26.727985 Exit from PICG configuration <<<<
6206 11:08:26.731160 [RX_INPUT] configuration >>>>>
6207 11:08:26.734423 [RX_INPUT] configuration <<<<<
6208 11:08:26.737583 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6209 11:08:26.744320 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6210 11:08:26.751241 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6211 11:08:26.757651 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6212 11:08:26.761396 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6213 11:08:26.768058 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6214 11:08:26.771400 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6215 11:08:26.777775 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6216 11:08:26.780913 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6217 11:08:26.784584 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6218 11:08:26.788038 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6219 11:08:26.794444 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6220 11:08:26.797395 ===================================
6221 11:08:26.797486 LPDDR4 DRAM CONFIGURATION
6222 11:08:26.800615 ===================================
6223 11:08:26.804324 EX_ROW_EN[0] = 0x0
6224 11:08:26.807562 EX_ROW_EN[1] = 0x0
6225 11:08:26.807665 LP4Y_EN = 0x0
6226 11:08:26.810794 WORK_FSP = 0x0
6227 11:08:26.810893 WL = 0x2
6228 11:08:26.814167 RL = 0x2
6229 11:08:26.814266 BL = 0x2
6230 11:08:26.817539 RPST = 0x0
6231 11:08:26.817618 RD_PRE = 0x0
6232 11:08:26.820818 WR_PRE = 0x1
6233 11:08:26.820907 WR_PST = 0x0
6234 11:08:26.824138 DBI_WR = 0x0
6235 11:08:26.824242 DBI_RD = 0x0
6236 11:08:26.827443 OTF = 0x1
6237 11:08:26.830753 ===================================
6238 11:08:26.834092 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6239 11:08:26.837314 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6240 11:08:26.844466 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6241 11:08:26.847295 ===================================
6242 11:08:26.847373 LPDDR4 DRAM CONFIGURATION
6243 11:08:26.850940 ===================================
6244 11:08:26.853832 EX_ROW_EN[0] = 0x10
6245 11:08:26.857299 EX_ROW_EN[1] = 0x0
6246 11:08:26.857376 LP4Y_EN = 0x0
6247 11:08:26.860623 WORK_FSP = 0x0
6248 11:08:26.860697 WL = 0x2
6249 11:08:26.864213 RL = 0x2
6250 11:08:26.864344 BL = 0x2
6251 11:08:26.867485 RPST = 0x0
6252 11:08:26.867607 RD_PRE = 0x0
6253 11:08:26.870663 WR_PRE = 0x1
6254 11:08:26.870780 WR_PST = 0x0
6255 11:08:26.874391 DBI_WR = 0x0
6256 11:08:26.874518 DBI_RD = 0x0
6257 11:08:26.877268 OTF = 0x1
6258 11:08:26.880528 ===================================
6259 11:08:26.887206 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6260 11:08:26.890630 nWR fixed to 30
6261 11:08:26.890758 [ModeRegInit_LP4] CH0 RK0
6262 11:08:26.893712 [ModeRegInit_LP4] CH0 RK1
6263 11:08:26.897049 [ModeRegInit_LP4] CH1 RK0
6264 11:08:26.900896 [ModeRegInit_LP4] CH1 RK1
6265 11:08:26.901021 match AC timing 19
6266 11:08:26.903815 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6267 11:08:26.910617 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6268 11:08:26.914217 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6269 11:08:26.917396 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6270 11:08:26.923818 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6271 11:08:26.923926 ==
6272 11:08:26.927180 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 11:08:26.930535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 11:08:26.930646 ==
6275 11:08:26.937210 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6276 11:08:26.943916 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6277 11:08:26.944000 [CA 0] Center 36 (8~64) winsize 57
6278 11:08:26.947307 [CA 1] Center 36 (8~64) winsize 57
6279 11:08:26.950628 [CA 2] Center 36 (8~64) winsize 57
6280 11:08:26.953643 [CA 3] Center 36 (8~64) winsize 57
6281 11:08:26.956808 [CA 4] Center 36 (8~64) winsize 57
6282 11:08:26.960647 [CA 5] Center 36 (8~64) winsize 57
6283 11:08:26.960752
6284 11:08:26.963845 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6285 11:08:26.963930
6286 11:08:26.967048 [CATrainingPosCal] consider 1 rank data
6287 11:08:26.970133 u2DelayCellTimex100 = 270/100 ps
6288 11:08:26.973577 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 11:08:26.977290 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 11:08:26.983435 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 11:08:26.987136 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 11:08:26.990562 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 11:08:26.993812 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 11:08:26.993918
6295 11:08:26.997129 CA PerBit enable=1, Macro0, CA PI delay=36
6296 11:08:26.997233
6297 11:08:27.000304 [CBTSetCACLKResult] CA Dly = 36
6298 11:08:27.000389 CS Dly: 1 (0~32)
6299 11:08:27.000476 ==
6300 11:08:27.003692 Dram Type= 6, Freq= 0, CH_0, rank 1
6301 11:08:27.010263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 11:08:27.010375 ==
6303 11:08:27.013464 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6304 11:08:27.020366 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6305 11:08:27.023441 [CA 0] Center 36 (8~64) winsize 57
6306 11:08:27.027163 [CA 1] Center 36 (8~64) winsize 57
6307 11:08:27.030679 [CA 2] Center 36 (8~64) winsize 57
6308 11:08:27.033555 [CA 3] Center 36 (8~64) winsize 57
6309 11:08:27.037219 [CA 4] Center 36 (8~64) winsize 57
6310 11:08:27.040417 [CA 5] Center 36 (8~64) winsize 57
6311 11:08:27.040500
6312 11:08:27.043738 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6313 11:08:27.043842
6314 11:08:27.047055 [CATrainingPosCal] consider 2 rank data
6315 11:08:27.050357 u2DelayCellTimex100 = 270/100 ps
6316 11:08:27.053567 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 11:08:27.056822 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 11:08:27.060061 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 11:08:27.063754 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 11:08:27.067078 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 11:08:27.070390 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 11:08:27.073636
6323 11:08:27.076970 CA PerBit enable=1, Macro0, CA PI delay=36
6324 11:08:27.077084
6325 11:08:27.080195 [CBTSetCACLKResult] CA Dly = 36
6326 11:08:27.080316 CS Dly: 1 (0~32)
6327 11:08:27.080410
6328 11:08:27.083547 ----->DramcWriteLeveling(PI) begin...
6329 11:08:27.083623 ==
6330 11:08:27.086999 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 11:08:27.089834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 11:08:27.093333 ==
6333 11:08:27.093408 Write leveling (Byte 0): 40 => 8
6334 11:08:27.096460 Write leveling (Byte 1): 40 => 8
6335 11:08:27.100148 DramcWriteLeveling(PI) end<-----
6336 11:08:27.100253
6337 11:08:27.100357 ==
6338 11:08:27.103250 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 11:08:27.110248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 11:08:27.110366 ==
6341 11:08:27.110463 [Gating] SW mode calibration
6342 11:08:27.119983 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6343 11:08:27.123270 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6344 11:08:27.126531 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6345 11:08:27.133476 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6346 11:08:27.136507 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 11:08:27.139780 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6348 11:08:27.146301 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6349 11:08:27.149535 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6350 11:08:27.152929 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 11:08:27.159754 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 11:08:27.162994 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6353 11:08:27.166687 Total UI for P1: 0, mck2ui 16
6354 11:08:27.169768 best dqsien dly found for B0: ( 0, 14, 24)
6355 11:08:27.173178 Total UI for P1: 0, mck2ui 16
6356 11:08:27.176413 best dqsien dly found for B1: ( 0, 14, 24)
6357 11:08:27.179677 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6358 11:08:27.182888 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6359 11:08:27.182973
6360 11:08:27.186231 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6361 11:08:27.189853 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6362 11:08:27.192934 [Gating] SW calibration Done
6363 11:08:27.193041 ==
6364 11:08:27.196615 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 11:08:27.202725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 11:08:27.202834 ==
6367 11:08:27.202928 RX Vref Scan: 0
6368 11:08:27.203030
6369 11:08:27.206641 RX Vref 0 -> 0, step: 1
6370 11:08:27.206759
6371 11:08:27.209747 RX Delay -410 -> 252, step: 16
6372 11:08:27.212694 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6373 11:08:27.216337 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6374 11:08:27.222753 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6375 11:08:27.225973 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6376 11:08:27.229161 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6377 11:08:27.232491 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6378 11:08:27.239503 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6379 11:08:27.242648 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6380 11:08:27.246007 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6381 11:08:27.249384 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6382 11:08:27.252947 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6383 11:08:27.259461 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6384 11:08:27.262860 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6385 11:08:27.266146 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6386 11:08:27.272616 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6387 11:08:27.276442 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6388 11:08:27.276526 ==
6389 11:08:27.279386 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 11:08:27.282741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 11:08:27.282836 ==
6392 11:08:27.286032 DQS Delay:
6393 11:08:27.286107 DQS0 = 27, DQS1 = 35
6394 11:08:27.286176 DQM Delay:
6395 11:08:27.289262 DQM0 = 12, DQM1 = 11
6396 11:08:27.289365 DQ Delay:
6397 11:08:27.293117 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6398 11:08:27.296450 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6399 11:08:27.299688 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6400 11:08:27.302900 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6401 11:08:27.303004
6402 11:08:27.303092
6403 11:08:27.303181 ==
6404 11:08:27.305941 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 11:08:27.309388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 11:08:27.309502 ==
6407 11:08:27.309569
6408 11:08:27.312751
6409 11:08:27.312832 TX Vref Scan disable
6410 11:08:27.316522 == TX Byte 0 ==
6411 11:08:27.319768 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6412 11:08:27.322816 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6413 11:08:27.325804 == TX Byte 1 ==
6414 11:08:27.329569 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6415 11:08:27.332776 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6416 11:08:27.332854 ==
6417 11:08:27.336179 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 11:08:27.339393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 11:08:27.342490 ==
6420 11:08:27.342566
6421 11:08:27.342626
6422 11:08:27.342686 TX Vref Scan disable
6423 11:08:27.345589 == TX Byte 0 ==
6424 11:08:27.349582 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6425 11:08:27.352922 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6426 11:08:27.356396 == TX Byte 1 ==
6427 11:08:27.359011 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6428 11:08:27.362297 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6429 11:08:27.362401
6430 11:08:27.362492 [DATLAT]
6431 11:08:27.366136 Freq=400, CH0 RK0
6432 11:08:27.366244
6433 11:08:27.369190 DATLAT Default: 0xf
6434 11:08:27.369264 0, 0xFFFF, sum = 0
6435 11:08:27.372982 1, 0xFFFF, sum = 0
6436 11:08:27.373060 2, 0xFFFF, sum = 0
6437 11:08:27.376252 3, 0xFFFF, sum = 0
6438 11:08:27.376359 4, 0xFFFF, sum = 0
6439 11:08:27.379621 5, 0xFFFF, sum = 0
6440 11:08:27.379727 6, 0xFFFF, sum = 0
6441 11:08:27.382654 7, 0xFFFF, sum = 0
6442 11:08:27.382763 8, 0xFFFF, sum = 0
6443 11:08:27.385747 9, 0xFFFF, sum = 0
6444 11:08:27.385852 10, 0xFFFF, sum = 0
6445 11:08:27.389561 11, 0xFFFF, sum = 0
6446 11:08:27.389699 12, 0xFFFF, sum = 0
6447 11:08:27.392803 13, 0x0, sum = 1
6448 11:08:27.392936 14, 0x0, sum = 2
6449 11:08:27.396093 15, 0x0, sum = 3
6450 11:08:27.396226 16, 0x0, sum = 4
6451 11:08:27.398859 best_step = 14
6452 11:08:27.398986
6453 11:08:27.399103 ==
6454 11:08:27.402176 Dram Type= 6, Freq= 0, CH_0, rank 0
6455 11:08:27.405557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 11:08:27.405694 ==
6457 11:08:27.409616 RX Vref Scan: 1
6458 11:08:27.409749
6459 11:08:27.409867 RX Vref 0 -> 0, step: 1
6460 11:08:27.409986
6461 11:08:27.412097 RX Delay -311 -> 252, step: 8
6462 11:08:27.412207
6463 11:08:27.415716 Set Vref, RX VrefLevel [Byte0]: 58
6464 11:08:27.419125 [Byte1]: 54
6465 11:08:27.423378
6466 11:08:27.423491 Final RX Vref Byte 0 = 58 to rank0
6467 11:08:27.426824 Final RX Vref Byte 1 = 54 to rank0
6468 11:08:27.430094 Final RX Vref Byte 0 = 58 to rank1
6469 11:08:27.433215 Final RX Vref Byte 1 = 54 to rank1==
6470 11:08:27.436796 Dram Type= 6, Freq= 0, CH_0, rank 0
6471 11:08:27.439865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 11:08:27.443626 ==
6473 11:08:27.443707 DQS Delay:
6474 11:08:27.443777 DQS0 = 28, DQS1 = 36
6475 11:08:27.446977 DQM Delay:
6476 11:08:27.447085 DQM0 = 11, DQM1 = 12
6477 11:08:27.450004 DQ Delay:
6478 11:08:27.450108 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6479 11:08:27.453562 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6480 11:08:27.456769 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6481 11:08:27.460121 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6482 11:08:27.460198
6483 11:08:27.460262
6484 11:08:27.470120 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbb9, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6485 11:08:27.473430 CH0 RK0: MR19=C0C, MR18=CBB9
6486 11:08:27.480348 CH0_RK0: MR19=0xC0C, MR18=0xCBB9, DQSOSC=384, MR23=63, INC=400, DEC=267
6487 11:08:27.480457 ==
6488 11:08:27.483228 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 11:08:27.486614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 11:08:27.486729 ==
6491 11:08:27.489749 [Gating] SW mode calibration
6492 11:08:27.496585 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6493 11:08:27.502972 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6494 11:08:27.506241 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 11:08:27.509491 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6496 11:08:27.512770 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 11:08:27.519730 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6498 11:08:27.522999 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 11:08:27.526622 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 11:08:27.532883 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 11:08:27.536307 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 11:08:27.539582 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 11:08:27.543407 Total UI for P1: 0, mck2ui 16
6504 11:08:27.546321 best dqsien dly found for B0: ( 0, 14, 24)
6505 11:08:27.549912 Total UI for P1: 0, mck2ui 16
6506 11:08:27.553121 best dqsien dly found for B1: ( 0, 14, 24)
6507 11:08:27.556228 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6508 11:08:27.559886 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6509 11:08:27.559989
6510 11:08:27.566316 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6511 11:08:27.569652 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6512 11:08:27.569757 [Gating] SW calibration Done
6513 11:08:27.572936 ==
6514 11:08:27.576246 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 11:08:27.579605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 11:08:27.579708 ==
6517 11:08:27.579803 RX Vref Scan: 0
6518 11:08:27.579892
6519 11:08:27.582938 RX Vref 0 -> 0, step: 1
6520 11:08:27.583012
6521 11:08:27.586161 RX Delay -410 -> 252, step: 16
6522 11:08:27.589929 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6523 11:08:27.596432 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6524 11:08:27.599887 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6525 11:08:27.602862 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6526 11:08:27.606571 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6527 11:08:27.609691 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6528 11:08:27.616663 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6529 11:08:27.620009 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6530 11:08:27.623387 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6531 11:08:27.626122 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6532 11:08:27.633234 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6533 11:08:27.636631 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6534 11:08:27.639739 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6535 11:08:27.642615 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6536 11:08:27.649503 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6537 11:08:27.652790 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6538 11:08:27.652876 ==
6539 11:08:27.656322 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 11:08:27.659257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 11:08:27.659343 ==
6542 11:08:27.662880 DQS Delay:
6543 11:08:27.662965 DQS0 = 27, DQS1 = 35
6544 11:08:27.666522 DQM Delay:
6545 11:08:27.666607 DQM0 = 14, DQM1 = 11
6546 11:08:27.666693 DQ Delay:
6547 11:08:27.669740 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6548 11:08:27.672682 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6549 11:08:27.675916 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6550 11:08:27.679295 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6551 11:08:27.679380
6552 11:08:27.679466
6553 11:08:27.679547 ==
6554 11:08:27.682710 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 11:08:27.689220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 11:08:27.689307 ==
6557 11:08:27.689393
6558 11:08:27.689472
6559 11:08:27.689551 TX Vref Scan disable
6560 11:08:27.692493 == TX Byte 0 ==
6561 11:08:27.695843 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6562 11:08:27.699793 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6563 11:08:27.702869 == TX Byte 1 ==
6564 11:08:27.705928 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6565 11:08:27.709568 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6566 11:08:27.709655 ==
6567 11:08:27.712595 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 11:08:27.719145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 11:08:27.719231 ==
6570 11:08:27.719316
6571 11:08:27.719396
6572 11:08:27.719474 TX Vref Scan disable
6573 11:08:27.722751 == TX Byte 0 ==
6574 11:08:27.725987 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6575 11:08:27.729328 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6576 11:08:27.732508 == TX Byte 1 ==
6577 11:08:27.735891 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6578 11:08:27.739222 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6579 11:08:27.739308
6580 11:08:27.742616 [DATLAT]
6581 11:08:27.742701 Freq=400, CH0 RK1
6582 11:08:27.742786
6583 11:08:27.745871 DATLAT Default: 0xe
6584 11:08:27.745956 0, 0xFFFF, sum = 0
6585 11:08:27.749235 1, 0xFFFF, sum = 0
6586 11:08:27.749323 2, 0xFFFF, sum = 0
6587 11:08:27.753031 3, 0xFFFF, sum = 0
6588 11:08:27.753118 4, 0xFFFF, sum = 0
6589 11:08:27.756105 5, 0xFFFF, sum = 0
6590 11:08:27.756221 6, 0xFFFF, sum = 0
6591 11:08:27.759380 7, 0xFFFF, sum = 0
6592 11:08:27.759464 8, 0xFFFF, sum = 0
6593 11:08:27.762551 9, 0xFFFF, sum = 0
6594 11:08:27.762635 10, 0xFFFF, sum = 0
6595 11:08:27.766016 11, 0xFFFF, sum = 0
6596 11:08:27.769533 12, 0xFFFF, sum = 0
6597 11:08:27.769616 13, 0x0, sum = 1
6598 11:08:27.769683 14, 0x0, sum = 2
6599 11:08:27.772906 15, 0x0, sum = 3
6600 11:08:27.772990 16, 0x0, sum = 4
6601 11:08:27.775712 best_step = 14
6602 11:08:27.775793
6603 11:08:27.775887 ==
6604 11:08:27.779343 Dram Type= 6, Freq= 0, CH_0, rank 1
6605 11:08:27.782813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 11:08:27.782896 ==
6607 11:08:27.786007 RX Vref Scan: 0
6608 11:08:27.786090
6609 11:08:27.786154 RX Vref 0 -> 0, step: 1
6610 11:08:27.786214
6611 11:08:27.789214 RX Delay -311 -> 252, step: 8
6612 11:08:27.797269 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6613 11:08:27.800574 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6614 11:08:27.803824 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6615 11:08:27.807141 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6616 11:08:27.813898 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6617 11:08:27.817381 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6618 11:08:27.820483 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6619 11:08:27.823709 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6620 11:08:27.830368 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6621 11:08:27.833649 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6622 11:08:27.836881 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6623 11:08:27.840597 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6624 11:08:27.847019 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6625 11:08:27.850375 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6626 11:08:27.853739 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6627 11:08:27.860623 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6628 11:08:27.860752 ==
6629 11:08:27.863827 Dram Type= 6, Freq= 0, CH_0, rank 1
6630 11:08:27.867111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 11:08:27.867211 ==
6632 11:08:27.867301 DQS Delay:
6633 11:08:27.870445 DQS0 = 24, DQS1 = 32
6634 11:08:27.870526 DQM Delay:
6635 11:08:27.873740 DQM0 = 9, DQM1 = 9
6636 11:08:27.873822 DQ Delay:
6637 11:08:27.876828 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6638 11:08:27.880174 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6639 11:08:27.883540 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6640 11:08:27.886753 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6641 11:08:27.886864
6642 11:08:27.886955
6643 11:08:27.893514 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6644 11:08:27.896932 CH0 RK1: MR19=C0C, MR18=BD5C
6645 11:08:27.903290 CH0_RK1: MR19=0xC0C, MR18=0xBD5C, DQSOSC=386, MR23=63, INC=396, DEC=264
6646 11:08:27.906885 [RxdqsGatingPostProcess] freq 400
6647 11:08:27.910406 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6648 11:08:27.913462 best DQS0 dly(2T, 0.5T) = (0, 10)
6649 11:08:27.916806 best DQS1 dly(2T, 0.5T) = (0, 10)
6650 11:08:27.920111 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6651 11:08:27.923329 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6652 11:08:27.926650 best DQS0 dly(2T, 0.5T) = (0, 10)
6653 11:08:27.929947 best DQS1 dly(2T, 0.5T) = (0, 10)
6654 11:08:27.933219 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6655 11:08:27.936626 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6656 11:08:27.939887 Pre-setting of DQS Precalculation
6657 11:08:27.943506 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6658 11:08:27.946593 ==
6659 11:08:27.946677 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 11:08:27.953723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 11:08:27.953807 ==
6662 11:08:27.957090 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6663 11:08:27.963726 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6664 11:08:27.966933 [CA 0] Center 36 (8~64) winsize 57
6665 11:08:27.970298 [CA 1] Center 36 (8~64) winsize 57
6666 11:08:27.973608 [CA 2] Center 36 (8~64) winsize 57
6667 11:08:27.976899 [CA 3] Center 36 (8~64) winsize 57
6668 11:08:27.980148 [CA 4] Center 36 (8~64) winsize 57
6669 11:08:27.983261 [CA 5] Center 36 (8~64) winsize 57
6670 11:08:27.983358
6671 11:08:27.986607 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6672 11:08:27.986686
6673 11:08:27.989995 [CATrainingPosCal] consider 1 rank data
6674 11:08:27.993282 u2DelayCellTimex100 = 270/100 ps
6675 11:08:27.996556 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 11:08:27.999883 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 11:08:28.003254 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 11:08:28.006532 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 11:08:28.009745 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 11:08:28.016490 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 11:08:28.016573
6682 11:08:28.019906 CA PerBit enable=1, Macro0, CA PI delay=36
6683 11:08:28.020008
6684 11:08:28.023190 [CBTSetCACLKResult] CA Dly = 36
6685 11:08:28.023295 CS Dly: 1 (0~32)
6686 11:08:28.023388 ==
6687 11:08:28.026371 Dram Type= 6, Freq= 0, CH_1, rank 1
6688 11:08:28.029723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 11:08:28.029830 ==
6690 11:08:28.036642 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6691 11:08:28.043129 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6692 11:08:28.046525 [CA 0] Center 36 (8~64) winsize 57
6693 11:08:28.049682 [CA 1] Center 36 (8~64) winsize 57
6694 11:08:28.053098 [CA 2] Center 36 (8~64) winsize 57
6695 11:08:28.056453 [CA 3] Center 36 (8~64) winsize 57
6696 11:08:28.059613 [CA 4] Center 36 (8~64) winsize 57
6697 11:08:28.059697 [CA 5] Center 36 (8~64) winsize 57
6698 11:08:28.063356
6699 11:08:28.066413 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6700 11:08:28.066526
6701 11:08:28.070198 [CATrainingPosCal] consider 2 rank data
6702 11:08:28.073063 u2DelayCellTimex100 = 270/100 ps
6703 11:08:28.076665 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 11:08:28.079945 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 11:08:28.083278 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 11:08:28.086614 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 11:08:28.089784 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 11:08:28.093054 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 11:08:28.093182
6710 11:08:28.096318 CA PerBit enable=1, Macro0, CA PI delay=36
6711 11:08:28.096442
6712 11:08:28.099565 [CBTSetCACLKResult] CA Dly = 36
6713 11:08:28.102937 CS Dly: 1 (0~32)
6714 11:08:28.103052
6715 11:08:28.106311 ----->DramcWriteLeveling(PI) begin...
6716 11:08:28.106401 ==
6717 11:08:28.109667 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 11:08:28.112994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 11:08:28.113094 ==
6720 11:08:28.116224 Write leveling (Byte 0): 40 => 8
6721 11:08:28.119683 Write leveling (Byte 1): 40 => 8
6722 11:08:28.122959 DramcWriteLeveling(PI) end<-----
6723 11:08:28.123068
6724 11:08:28.123161 ==
6725 11:08:28.126166 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 11:08:28.129458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 11:08:28.129534 ==
6728 11:08:28.133234 [Gating] SW mode calibration
6729 11:08:28.139823 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6730 11:08:28.146268 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6731 11:08:28.149331 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6732 11:08:28.155803 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6733 11:08:28.159161 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 11:08:28.162378 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6735 11:08:28.169087 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6736 11:08:28.172349 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6737 11:08:28.175754 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 11:08:28.178996 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 11:08:28.186118 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6740 11:08:28.189175 Total UI for P1: 0, mck2ui 16
6741 11:08:28.192704 best dqsien dly found for B0: ( 0, 14, 24)
6742 11:08:28.196049 Total UI for P1: 0, mck2ui 16
6743 11:08:28.198895 best dqsien dly found for B1: ( 0, 14, 24)
6744 11:08:28.202274 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6745 11:08:28.205955 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6746 11:08:28.206065
6747 11:08:28.209263 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6748 11:08:28.212530 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6749 11:08:28.215814 [Gating] SW calibration Done
6750 11:08:28.215938 ==
6751 11:08:28.219176 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 11:08:28.222613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 11:08:28.222719 ==
6754 11:08:28.226051 RX Vref Scan: 0
6755 11:08:28.226135
6756 11:08:28.229316 RX Vref 0 -> 0, step: 1
6757 11:08:28.229395
6758 11:08:28.229473 RX Delay -410 -> 252, step: 16
6759 11:08:28.235763 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6760 11:08:28.238899 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6761 11:08:28.242275 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6762 11:08:28.245479 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6763 11:08:28.252363 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6764 11:08:28.255552 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6765 11:08:28.259245 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6766 11:08:28.262294 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6767 11:08:28.269006 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6768 11:08:28.272276 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6769 11:08:28.275531 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6770 11:08:28.278883 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6771 11:08:28.285567 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6772 11:08:28.288869 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6773 11:08:28.292246 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6774 11:08:28.295687 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6775 11:08:28.298895 ==
6776 11:08:28.302708 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 11:08:28.306016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 11:08:28.306128 ==
6779 11:08:28.306222 DQS Delay:
6780 11:08:28.309157 DQS0 = 27, DQS1 = 35
6781 11:08:28.309237 DQM Delay:
6782 11:08:28.312356 DQM0 = 11, DQM1 = 13
6783 11:08:28.312434 DQ Delay:
6784 11:08:28.315706 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6785 11:08:28.319090 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6786 11:08:28.322390 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6787 11:08:28.325469 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6788 11:08:28.325557
6789 11:08:28.325624
6790 11:08:28.325687 ==
6791 11:08:28.328821 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 11:08:28.332144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 11:08:28.332246 ==
6794 11:08:28.332347
6795 11:08:28.332409
6796 11:08:28.335423 TX Vref Scan disable
6797 11:08:28.335500 == TX Byte 0 ==
6798 11:08:28.342427 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6799 11:08:28.345704 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6800 11:08:28.345781 == TX Byte 1 ==
6801 11:08:28.352249 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6802 11:08:28.355367 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6803 11:08:28.355447 ==
6804 11:08:28.358724 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 11:08:28.362087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 11:08:28.362173 ==
6807 11:08:28.362238
6808 11:08:28.362299
6809 11:08:28.365437 TX Vref Scan disable
6810 11:08:28.365549 == TX Byte 0 ==
6811 11:08:28.371833 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6812 11:08:28.375386 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6813 11:08:28.375468 == TX Byte 1 ==
6814 11:08:28.382016 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6815 11:08:28.385443 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6816 11:08:28.385562
6817 11:08:28.385656 [DATLAT]
6818 11:08:28.389025 Freq=400, CH1 RK0
6819 11:08:28.389108
6820 11:08:28.389172 DATLAT Default: 0xf
6821 11:08:28.392148 0, 0xFFFF, sum = 0
6822 11:08:28.392235 1, 0xFFFF, sum = 0
6823 11:08:28.395429 2, 0xFFFF, sum = 0
6824 11:08:28.395510 3, 0xFFFF, sum = 0
6825 11:08:28.398699 4, 0xFFFF, sum = 0
6826 11:08:28.398775 5, 0xFFFF, sum = 0
6827 11:08:28.402120 6, 0xFFFF, sum = 0
6828 11:08:28.402198 7, 0xFFFF, sum = 0
6829 11:08:28.405251 8, 0xFFFF, sum = 0
6830 11:08:28.405363 9, 0xFFFF, sum = 0
6831 11:08:28.408684 10, 0xFFFF, sum = 0
6832 11:08:28.408773 11, 0xFFFF, sum = 0
6833 11:08:28.411901 12, 0xFFFF, sum = 0
6834 11:08:28.411984 13, 0x0, sum = 1
6835 11:08:28.415307 14, 0x0, sum = 2
6836 11:08:28.415384 15, 0x0, sum = 3
6837 11:08:28.418634 16, 0x0, sum = 4
6838 11:08:28.418721 best_step = 14
6839 11:08:28.418785
6840 11:08:28.418845 ==
6841 11:08:28.422476 Dram Type= 6, Freq= 0, CH_1, rank 0
6842 11:08:28.428598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 11:08:28.428684 ==
6844 11:08:28.428751 RX Vref Scan: 1
6845 11:08:28.428812
6846 11:08:28.432173 RX Vref 0 -> 0, step: 1
6847 11:08:28.432247
6848 11:08:28.435613 RX Delay -311 -> 252, step: 8
6849 11:08:28.435690
6850 11:08:28.438721 Set Vref, RX VrefLevel [Byte0]: 53
6851 11:08:28.442200 [Byte1]: 48
6852 11:08:28.442306
6853 11:08:28.445257 Final RX Vref Byte 0 = 53 to rank0
6854 11:08:28.448656 Final RX Vref Byte 1 = 48 to rank0
6855 11:08:28.451888 Final RX Vref Byte 0 = 53 to rank1
6856 11:08:28.455210 Final RX Vref Byte 1 = 48 to rank1==
6857 11:08:28.458996 Dram Type= 6, Freq= 0, CH_1, rank 0
6858 11:08:28.461979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 11:08:28.465160 ==
6860 11:08:28.465248 DQS Delay:
6861 11:08:28.465316 DQS0 = 32, DQS1 = 32
6862 11:08:28.468522 DQM Delay:
6863 11:08:28.468603 DQM0 = 13, DQM1 = 11
6864 11:08:28.471872 DQ Delay:
6865 11:08:28.475155 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6866 11:08:28.475234 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6867 11:08:28.478422 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6868 11:08:28.481791 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6869 11:08:28.481893
6870 11:08:28.481984
6871 11:08:28.491841 [DQSOSCAuto] RK0, (LSB)MR18= 0x92ca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6872 11:08:28.495096 CH1 RK0: MR19=C0C, MR18=92CA
6873 11:08:28.501577 CH1_RK0: MR19=0xC0C, MR18=0x92CA, DQSOSC=384, MR23=63, INC=400, DEC=267
6874 11:08:28.501689 ==
6875 11:08:28.504935 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 11:08:28.508558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 11:08:28.508674 ==
6878 11:08:28.511698 [Gating] SW mode calibration
6879 11:08:28.518558 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6880 11:08:28.521927 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6881 11:08:28.528628 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6882 11:08:28.531887 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6883 11:08:28.535248 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 11:08:28.541454 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6885 11:08:28.545178 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6886 11:08:28.548199 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6887 11:08:28.555054 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 11:08:28.558406 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 11:08:28.561694 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6890 11:08:28.564840 Total UI for P1: 0, mck2ui 16
6891 11:08:28.568195 best dqsien dly found for B0: ( 0, 14, 24)
6892 11:08:28.571883 Total UI for P1: 0, mck2ui 16
6893 11:08:28.574913 best dqsien dly found for B1: ( 0, 14, 24)
6894 11:08:28.578171 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6895 11:08:28.581588 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6896 11:08:28.581696
6897 11:08:28.588237 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6898 11:08:28.591219 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6899 11:08:28.594628 [Gating] SW calibration Done
6900 11:08:28.594757 ==
6901 11:08:28.598473 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 11:08:28.601563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 11:08:28.601688 ==
6904 11:08:28.601795 RX Vref Scan: 0
6905 11:08:28.601896
6906 11:08:28.604735 RX Vref 0 -> 0, step: 1
6907 11:08:28.604859
6908 11:08:28.607850 RX Delay -410 -> 252, step: 16
6909 11:08:28.611661 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6910 11:08:28.618254 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6911 11:08:28.621286 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6912 11:08:28.624999 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6913 11:08:28.628205 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6914 11:08:28.631534 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6915 11:08:28.638205 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6916 11:08:28.641562 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6917 11:08:28.644828 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6918 11:08:28.648156 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6919 11:08:28.654730 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6920 11:08:28.658139 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6921 11:08:28.661483 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6922 11:08:28.667799 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6923 11:08:28.671129 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6924 11:08:28.674164 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6925 11:08:28.674243 ==
6926 11:08:28.677837 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 11:08:28.680779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 11:08:28.684244 ==
6929 11:08:28.684367 DQS Delay:
6930 11:08:28.684437 DQS0 = 35, DQS1 = 35
6931 11:08:28.687428 DQM Delay:
6932 11:08:28.687537 DQM0 = 18, DQM1 = 14
6933 11:08:28.691173 DQ Delay:
6934 11:08:28.691279 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6935 11:08:28.694236 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6936 11:08:28.697596 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6937 11:08:28.701140 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6938 11:08:28.701227
6939 11:08:28.701294
6940 11:08:28.704196 ==
6941 11:08:28.707488 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 11:08:28.710751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 11:08:28.710839 ==
6944 11:08:28.710939
6945 11:08:28.711031
6946 11:08:28.714571 TX Vref Scan disable
6947 11:08:28.714656 == TX Byte 0 ==
6948 11:08:28.717783 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6949 11:08:28.724424 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6950 11:08:28.724504 == TX Byte 1 ==
6951 11:08:28.727966 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6952 11:08:28.730930 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6953 11:08:28.734399 ==
6954 11:08:28.737405 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 11:08:28.741352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 11:08:28.741437 ==
6957 11:08:28.741502
6958 11:08:28.741563
6959 11:08:28.744659 TX Vref Scan disable
6960 11:08:28.744738 == TX Byte 0 ==
6961 11:08:28.747972 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6962 11:08:28.754673 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6963 11:08:28.754755 == TX Byte 1 ==
6964 11:08:28.757827 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6965 11:08:28.760617 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6966 11:08:28.764508
6967 11:08:28.764611 [DATLAT]
6968 11:08:28.764708 Freq=400, CH1 RK1
6969 11:08:28.764798
6970 11:08:28.767800 DATLAT Default: 0xe
6971 11:08:28.767903 0, 0xFFFF, sum = 0
6972 11:08:28.771176 1, 0xFFFF, sum = 0
6973 11:08:28.771257 2, 0xFFFF, sum = 0
6974 11:08:28.774565 3, 0xFFFF, sum = 0
6975 11:08:28.774677 4, 0xFFFF, sum = 0
6976 11:08:28.777710 5, 0xFFFF, sum = 0
6977 11:08:28.777791 6, 0xFFFF, sum = 0
6978 11:08:28.780966 7, 0xFFFF, sum = 0
6979 11:08:28.784141 8, 0xFFFF, sum = 0
6980 11:08:28.784250 9, 0xFFFF, sum = 0
6981 11:08:28.787300 10, 0xFFFF, sum = 0
6982 11:08:28.787383 11, 0xFFFF, sum = 0
6983 11:08:28.790706 12, 0xFFFF, sum = 0
6984 11:08:28.790816 13, 0x0, sum = 1
6985 11:08:28.794011 14, 0x0, sum = 2
6986 11:08:28.794089 15, 0x0, sum = 3
6987 11:08:28.797711 16, 0x0, sum = 4
6988 11:08:28.797790 best_step = 14
6989 11:08:28.797854
6990 11:08:28.797918 ==
6991 11:08:28.800715 Dram Type= 6, Freq= 0, CH_1, rank 1
6992 11:08:28.804386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6993 11:08:28.804470 ==
6994 11:08:28.807479 RX Vref Scan: 0
6995 11:08:28.807557
6996 11:08:28.810778 RX Vref 0 -> 0, step: 1
6997 11:08:28.810885
6998 11:08:28.810981 RX Delay -311 -> 252, step: 8
6999 11:08:28.819486 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
7000 11:08:28.822786 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
7001 11:08:28.826138 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
7002 11:08:28.829583 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
7003 11:08:28.835808 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
7004 11:08:28.839610 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
7005 11:08:28.842628 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
7006 11:08:28.845982 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7007 11:08:28.852846 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
7008 11:08:28.856167 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7009 11:08:28.859448 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
7010 11:08:28.862763 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
7011 11:08:28.869287 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7012 11:08:28.872551 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7013 11:08:28.875820 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7014 11:08:28.882442 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7015 11:08:28.882525 ==
7016 11:08:28.885697 Dram Type= 6, Freq= 0, CH_1, rank 1
7017 11:08:28.889049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7018 11:08:28.889133 ==
7019 11:08:28.889214 DQS Delay:
7020 11:08:28.892292 DQS0 = 28, DQS1 = 32
7021 11:08:28.892375 DQM Delay:
7022 11:08:28.895942 DQM0 = 10, DQM1 = 11
7023 11:08:28.896055 DQ Delay:
7024 11:08:28.899437 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7025 11:08:28.902701 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7026 11:08:28.905804 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7027 11:08:28.909251 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7028 11:08:28.909338
7029 11:08:28.909404
7030 11:08:28.916380 [DQSOSCAuto] RK1, (LSB)MR18= 0xc253, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
7031 11:08:28.919481 CH1 RK1: MR19=C0C, MR18=C253
7032 11:08:28.925786 CH1_RK1: MR19=0xC0C, MR18=0xC253, DQSOSC=385, MR23=63, INC=398, DEC=265
7033 11:08:28.929045 [RxdqsGatingPostProcess] freq 400
7034 11:08:28.932799 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7035 11:08:28.936263 best DQS0 dly(2T, 0.5T) = (0, 10)
7036 11:08:28.939157 best DQS1 dly(2T, 0.5T) = (0, 10)
7037 11:08:28.942448 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7038 11:08:28.945783 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7039 11:08:28.949142 best DQS0 dly(2T, 0.5T) = (0, 10)
7040 11:08:28.952624 best DQS1 dly(2T, 0.5T) = (0, 10)
7041 11:08:28.955581 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7042 11:08:28.959311 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7043 11:08:28.962855 Pre-setting of DQS Precalculation
7044 11:08:28.965751 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7045 11:08:28.975609 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7046 11:08:28.982291 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7047 11:08:28.982384
7048 11:08:28.982451
7049 11:08:28.985680 [Calibration Summary] 800 Mbps
7050 11:08:28.985763 CH 0, Rank 0
7051 11:08:28.988992 SW Impedance : PASS
7052 11:08:28.989071 DUTY Scan : NO K
7053 11:08:28.992360 ZQ Calibration : PASS
7054 11:08:28.995647 Jitter Meter : NO K
7055 11:08:28.995773 CBT Training : PASS
7056 11:08:28.998858 Write leveling : PASS
7057 11:08:29.002122 RX DQS gating : PASS
7058 11:08:29.002203 RX DQ/DQS(RDDQC) : PASS
7059 11:08:29.005364 TX DQ/DQS : PASS
7060 11:08:29.008580 RX DATLAT : PASS
7061 11:08:29.008662 RX DQ/DQS(Engine): PASS
7062 11:08:29.012522 TX OE : NO K
7063 11:08:29.012603 All Pass.
7064 11:08:29.012668
7065 11:08:29.015145 CH 0, Rank 1
7066 11:08:29.015225 SW Impedance : PASS
7067 11:08:29.018457 DUTY Scan : NO K
7068 11:08:29.022382 ZQ Calibration : PASS
7069 11:08:29.022467 Jitter Meter : NO K
7070 11:08:29.025595 CBT Training : PASS
7071 11:08:29.025681 Write leveling : NO K
7072 11:08:29.028834 RX DQS gating : PASS
7073 11:08:29.032216 RX DQ/DQS(RDDQC) : PASS
7074 11:08:29.032330 TX DQ/DQS : PASS
7075 11:08:29.035362 RX DATLAT : PASS
7076 11:08:29.038677 RX DQ/DQS(Engine): PASS
7077 11:08:29.038754 TX OE : NO K
7078 11:08:29.041872 All Pass.
7079 11:08:29.041949
7080 11:08:29.042013 CH 1, Rank 0
7081 11:08:29.045324 SW Impedance : PASS
7082 11:08:29.045408 DUTY Scan : NO K
7083 11:08:29.048570 ZQ Calibration : PASS
7084 11:08:29.052362 Jitter Meter : NO K
7085 11:08:29.052447 CBT Training : PASS
7086 11:08:29.055465 Write leveling : PASS
7087 11:08:29.058949 RX DQS gating : PASS
7088 11:08:29.059058 RX DQ/DQS(RDDQC) : PASS
7089 11:08:29.062241 TX DQ/DQS : PASS
7090 11:08:29.062359 RX DATLAT : PASS
7091 11:08:29.065282 RX DQ/DQS(Engine): PASS
7092 11:08:29.068753 TX OE : NO K
7093 11:08:29.068838 All Pass.
7094 11:08:29.068907
7095 11:08:29.068977 CH 1, Rank 1
7096 11:08:29.071804 SW Impedance : PASS
7097 11:08:29.075508 DUTY Scan : NO K
7098 11:08:29.075605 ZQ Calibration : PASS
7099 11:08:29.078396 Jitter Meter : NO K
7100 11:08:29.081874 CBT Training : PASS
7101 11:08:29.081962 Write leveling : NO K
7102 11:08:29.085008 RX DQS gating : PASS
7103 11:08:29.088815 RX DQ/DQS(RDDQC) : PASS
7104 11:08:29.088930 TX DQ/DQS : PASS
7105 11:08:29.091533 RX DATLAT : PASS
7106 11:08:29.094835 RX DQ/DQS(Engine): PASS
7107 11:08:29.094948 TX OE : NO K
7108 11:08:29.098313 All Pass.
7109 11:08:29.098418
7110 11:08:29.098519 DramC Write-DBI off
7111 11:08:29.101601 PER_BANK_REFRESH: Hybrid Mode
7112 11:08:29.101709 TX_TRACKING: ON
7113 11:08:29.111523 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7114 11:08:29.114728 [FAST_K] Save calibration result to emmc
7115 11:08:29.118162 dramc_set_vcore_voltage set vcore to 725000
7116 11:08:29.121584 Read voltage for 1600, 0
7117 11:08:29.121718 Vio18 = 0
7118 11:08:29.124888 Vcore = 725000
7119 11:08:29.125015 Vdram = 0
7120 11:08:29.125125 Vddq = 0
7121 11:08:29.128231 Vmddr = 0
7122 11:08:29.131360 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7123 11:08:29.138560 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7124 11:08:29.138686 MEM_TYPE=3, freq_sel=13
7125 11:08:29.141740 sv_algorithm_assistance_LP4_3733
7126 11:08:29.148462 ============ PULL DRAM RESETB DOWN ============
7127 11:08:29.151843 ========== PULL DRAM RESETB DOWN end =========
7128 11:08:29.155139 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7129 11:08:29.158512 ===================================
7130 11:08:29.161835 LPDDR4 DRAM CONFIGURATION
7131 11:08:29.164527 ===================================
7132 11:08:29.164653 EX_ROW_EN[0] = 0x0
7133 11:08:29.168264 EX_ROW_EN[1] = 0x0
7134 11:08:29.171246 LP4Y_EN = 0x0
7135 11:08:29.171370 WORK_FSP = 0x1
7136 11:08:29.174846 WL = 0x5
7137 11:08:29.174972 RL = 0x5
7138 11:08:29.178072 BL = 0x2
7139 11:08:29.178194 RPST = 0x0
7140 11:08:29.181572 RD_PRE = 0x0
7141 11:08:29.181694 WR_PRE = 0x1
7142 11:08:29.184630 WR_PST = 0x1
7143 11:08:29.184752 DBI_WR = 0x0
7144 11:08:29.188418 DBI_RD = 0x0
7145 11:08:29.188543 OTF = 0x1
7146 11:08:29.191474 ===================================
7147 11:08:29.194897 ===================================
7148 11:08:29.197839 ANA top config
7149 11:08:29.201228 ===================================
7150 11:08:29.201352 DLL_ASYNC_EN = 0
7151 11:08:29.204903 ALL_SLAVE_EN = 0
7152 11:08:29.208178 NEW_RANK_MODE = 1
7153 11:08:29.211620 DLL_IDLE_MODE = 1
7154 11:08:29.214853 LP45_APHY_COMB_EN = 1
7155 11:08:29.214959 TX_ODT_DIS = 0
7156 11:08:29.217795 NEW_8X_MODE = 1
7157 11:08:29.221532 ===================================
7158 11:08:29.224813 ===================================
7159 11:08:29.228107 data_rate = 3200
7160 11:08:29.231349 CKR = 1
7161 11:08:29.234643 DQ_P2S_RATIO = 8
7162 11:08:29.237898 ===================================
7163 11:08:29.237981 CA_P2S_RATIO = 8
7164 11:08:29.241089 DQ_CA_OPEN = 0
7165 11:08:29.244419 DQ_SEMI_OPEN = 0
7166 11:08:29.247758 CA_SEMI_OPEN = 0
7167 11:08:29.251113 CA_FULL_RATE = 0
7168 11:08:29.254460 DQ_CKDIV4_EN = 0
7169 11:08:29.254565 CA_CKDIV4_EN = 0
7170 11:08:29.257752 CA_PREDIV_EN = 0
7171 11:08:29.261094 PH8_DLY = 12
7172 11:08:29.265160 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7173 11:08:29.268597 DQ_AAMCK_DIV = 4
7174 11:08:29.271212 CA_AAMCK_DIV = 4
7175 11:08:29.271295 CA_ADMCK_DIV = 4
7176 11:08:29.274477 DQ_TRACK_CA_EN = 0
7177 11:08:29.278343 CA_PICK = 1600
7178 11:08:29.281498 CA_MCKIO = 1600
7179 11:08:29.284437 MCKIO_SEMI = 0
7180 11:08:29.287950 PLL_FREQ = 3068
7181 11:08:29.291396 DQ_UI_PI_RATIO = 32
7182 11:08:29.291526 CA_UI_PI_RATIO = 0
7183 11:08:29.294338 ===================================
7184 11:08:29.297985 ===================================
7185 11:08:29.301295 memory_type:LPDDR4
7186 11:08:29.304382 GP_NUM : 10
7187 11:08:29.304467 SRAM_EN : 1
7188 11:08:29.308195 MD32_EN : 0
7189 11:08:29.311232 ===================================
7190 11:08:29.314614 [ANA_INIT] >>>>>>>>>>>>>>
7191 11:08:29.317813 <<<<<< [CONFIGURE PHASE]: ANA_TX
7192 11:08:29.321027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7193 11:08:29.324572 ===================================
7194 11:08:29.324671 data_rate = 3200,PCW = 0X7600
7195 11:08:29.327595 ===================================
7196 11:08:29.331320 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7197 11:08:29.337453 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7198 11:08:29.344488 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7199 11:08:29.347774 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7200 11:08:29.351014 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7201 11:08:29.354282 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7202 11:08:29.357606 [ANA_INIT] flow start
7203 11:08:29.360859 [ANA_INIT] PLL >>>>>>>>
7204 11:08:29.360959 [ANA_INIT] PLL <<<<<<<<
7205 11:08:29.364225 [ANA_INIT] MIDPI >>>>>>>>
7206 11:08:29.367477 [ANA_INIT] MIDPI <<<<<<<<
7207 11:08:29.367579 [ANA_INIT] DLL >>>>>>>>
7208 11:08:29.370792 [ANA_INIT] DLL <<<<<<<<
7209 11:08:29.373984 [ANA_INIT] flow end
7210 11:08:29.377150 ============ LP4 DIFF to SE enter ============
7211 11:08:29.380412 ============ LP4 DIFF to SE exit ============
7212 11:08:29.383668 [ANA_INIT] <<<<<<<<<<<<<
7213 11:08:29.386967 [Flow] Enable top DCM control >>>>>
7214 11:08:29.390278 [Flow] Enable top DCM control <<<<<
7215 11:08:29.394145 Enable DLL master slave shuffle
7216 11:08:29.397211 ==============================================================
7217 11:08:29.400216 Gating Mode config
7218 11:08:29.407333 ==============================================================
7219 11:08:29.407416 Config description:
7220 11:08:29.417235 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7221 11:08:29.423513 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7222 11:08:29.430028 SELPH_MODE 0: By rank 1: By Phase
7223 11:08:29.433369 ==============================================================
7224 11:08:29.436561 GAT_TRACK_EN = 1
7225 11:08:29.440196 RX_GATING_MODE = 2
7226 11:08:29.443165 RX_GATING_TRACK_MODE = 2
7227 11:08:29.446727 SELPH_MODE = 1
7228 11:08:29.449920 PICG_EARLY_EN = 1
7229 11:08:29.453491 VALID_LAT_VALUE = 1
7230 11:08:29.456717 ==============================================================
7231 11:08:29.460093 Enter into Gating configuration >>>>
7232 11:08:29.463011 Exit from Gating configuration <<<<
7233 11:08:29.466121 Enter into DVFS_PRE_config >>>>>
7234 11:08:29.480011 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7235 11:08:29.483383 Exit from DVFS_PRE_config <<<<<
7236 11:08:29.486649 Enter into PICG configuration >>>>
7237 11:08:29.486733 Exit from PICG configuration <<<<
7238 11:08:29.489916 [RX_INPUT] configuration >>>>>
7239 11:08:29.493283 [RX_INPUT] configuration <<<<<
7240 11:08:29.499858 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7241 11:08:29.503289 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7242 11:08:29.509787 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7243 11:08:29.515988 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7244 11:08:29.522760 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7245 11:08:29.529431 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7246 11:08:29.532823 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7247 11:08:29.536236 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7248 11:08:29.542740 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7249 11:08:29.545869 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7250 11:08:29.549017 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7251 11:08:29.552851 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7252 11:08:29.555917 ===================================
7253 11:08:29.558990 LPDDR4 DRAM CONFIGURATION
7254 11:08:29.562550 ===================================
7255 11:08:29.565824 EX_ROW_EN[0] = 0x0
7256 11:08:29.565908 EX_ROW_EN[1] = 0x0
7257 11:08:29.569181 LP4Y_EN = 0x0
7258 11:08:29.569265 WORK_FSP = 0x1
7259 11:08:29.572290 WL = 0x5
7260 11:08:29.572376 RL = 0x5
7261 11:08:29.576071 BL = 0x2
7262 11:08:29.576156 RPST = 0x0
7263 11:08:29.579190 RD_PRE = 0x0
7264 11:08:29.579309 WR_PRE = 0x1
7265 11:08:29.582332 WR_PST = 0x1
7266 11:08:29.582427 DBI_WR = 0x0
7267 11:08:29.586215 DBI_RD = 0x0
7268 11:08:29.589357 OTF = 0x1
7269 11:08:29.592643 ===================================
7270 11:08:29.595397 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7271 11:08:29.599269 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7272 11:08:29.602558 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7273 11:08:29.605873 ===================================
7274 11:08:29.609249 LPDDR4 DRAM CONFIGURATION
7275 11:08:29.611922 ===================================
7276 11:08:29.615262 EX_ROW_EN[0] = 0x10
7277 11:08:29.615341 EX_ROW_EN[1] = 0x0
7278 11:08:29.619117 LP4Y_EN = 0x0
7279 11:08:29.619227 WORK_FSP = 0x1
7280 11:08:29.622016 WL = 0x5
7281 11:08:29.622095 RL = 0x5
7282 11:08:29.625633 BL = 0x2
7283 11:08:29.625713 RPST = 0x0
7284 11:08:29.628624 RD_PRE = 0x0
7285 11:08:29.628704 WR_PRE = 0x1
7286 11:08:29.632169 WR_PST = 0x1
7287 11:08:29.632283 DBI_WR = 0x0
7288 11:08:29.635409 DBI_RD = 0x0
7289 11:08:29.635509 OTF = 0x1
7290 11:08:29.638781 ===================================
7291 11:08:29.645341 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7292 11:08:29.645427 ==
7293 11:08:29.649112 Dram Type= 6, Freq= 0, CH_0, rank 0
7294 11:08:29.655577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7295 11:08:29.655688 ==
7296 11:08:29.655786 [Duty_Offset_Calibration]
7297 11:08:29.658642 B0:2 B1:1 CA:1
7298 11:08:29.658749
7299 11:08:29.661927 [DutyScan_Calibration_Flow] k_type=0
7300 11:08:29.671186
7301 11:08:29.671312 ==CLK 0==
7302 11:08:29.674548 Final CLK duty delay cell = 0
7303 11:08:29.678322 [0] MAX Duty = 5156%(X100), DQS PI = 22
7304 11:08:29.681485 [0] MIN Duty = 4907%(X100), DQS PI = 0
7305 11:08:29.681609 [0] AVG Duty = 5031%(X100)
7306 11:08:29.684630
7307 11:08:29.684757 CH0 CLK Duty spec in!! Max-Min= 249%
7308 11:08:29.691543 [DutyScan_Calibration_Flow] ====Done====
7309 11:08:29.691670
7310 11:08:29.694586 [DutyScan_Calibration_Flow] k_type=1
7311 11:08:29.710816
7312 11:08:29.710905 ==DQS 0 ==
7313 11:08:29.714105 Final DQS duty delay cell = -4
7314 11:08:29.716895 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7315 11:08:29.720132 [-4] MIN Duty = 4688%(X100), DQS PI = 0
7316 11:08:29.723429 [-4] AVG Duty = 4922%(X100)
7317 11:08:29.723511
7318 11:08:29.723576 ==DQS 1 ==
7319 11:08:29.726782 Final DQS duty delay cell = 0
7320 11:08:29.730561 [0] MAX Duty = 5187%(X100), DQS PI = 10
7321 11:08:29.733708 [0] MIN Duty = 5031%(X100), DQS PI = 32
7322 11:08:29.736665 [0] AVG Duty = 5109%(X100)
7323 11:08:29.736747
7324 11:08:29.740162 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7325 11:08:29.740244
7326 11:08:29.743752 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7327 11:08:29.747247 [DutyScan_Calibration_Flow] ====Done====
7328 11:08:29.747329
7329 11:08:29.750426 [DutyScan_Calibration_Flow] k_type=3
7330 11:08:29.767849
7331 11:08:29.767932 ==DQM 0 ==
7332 11:08:29.771441 Final DQM duty delay cell = 0
7333 11:08:29.774454 [0] MAX Duty = 5187%(X100), DQS PI = 30
7334 11:08:29.777791 [0] MIN Duty = 4875%(X100), DQS PI = 60
7335 11:08:29.780951 [0] AVG Duty = 5031%(X100)
7336 11:08:29.781034
7337 11:08:29.781099 ==DQM 1 ==
7338 11:08:29.784331 Final DQM duty delay cell = 0
7339 11:08:29.787684 [0] MAX Duty = 5187%(X100), DQS PI = 6
7340 11:08:29.791161 [0] MIN Duty = 5031%(X100), DQS PI = 48
7341 11:08:29.794792 [0] AVG Duty = 5109%(X100)
7342 11:08:29.794874
7343 11:08:29.797908 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7344 11:08:29.797991
7345 11:08:29.801244 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7346 11:08:29.804536 [DutyScan_Calibration_Flow] ====Done====
7347 11:08:29.804618
7348 11:08:29.807499 [DutyScan_Calibration_Flow] k_type=2
7349 11:08:29.825121
7350 11:08:29.825264 ==DQ 0 ==
7351 11:08:29.828329 Final DQ duty delay cell = 0
7352 11:08:29.831655 [0] MAX Duty = 5062%(X100), DQS PI = 26
7353 11:08:29.834854 [0] MIN Duty = 4907%(X100), DQS PI = 0
7354 11:08:29.834984 [0] AVG Duty = 4984%(X100)
7355 11:08:29.835100
7356 11:08:29.838173 ==DQ 1 ==
7357 11:08:29.841579 Final DQ duty delay cell = 0
7358 11:08:29.845474 [0] MAX Duty = 5124%(X100), DQS PI = 22
7359 11:08:29.848425 [0] MIN Duty = 4907%(X100), DQS PI = 34
7360 11:08:29.848555 [0] AVG Duty = 5015%(X100)
7361 11:08:29.848674
7362 11:08:29.852190 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7363 11:08:29.852322
7364 11:08:29.855032 CH0 DQ 1 Duty spec in!! Max-Min= 217%
7365 11:08:29.862135 [DutyScan_Calibration_Flow] ====Done====
7366 11:08:29.862267 ==
7367 11:08:29.865531 Dram Type= 6, Freq= 0, CH_1, rank 0
7368 11:08:29.868711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7369 11:08:29.868843 ==
7370 11:08:29.871869 [Duty_Offset_Calibration]
7371 11:08:29.871996 B0:1 B1:0 CA:0
7372 11:08:29.872105
7373 11:08:29.875001 [DutyScan_Calibration_Flow] k_type=0
7374 11:08:29.884828
7375 11:08:29.884951 ==CLK 0==
7376 11:08:29.887690 Final CLK duty delay cell = -4
7377 11:08:29.891525 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7378 11:08:29.894188 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7379 11:08:29.897479 [-4] AVG Duty = 4922%(X100)
7380 11:08:29.897608
7381 11:08:29.901287 CH1 CLK Duty spec in!! Max-Min= 156%
7382 11:08:29.904406 [DutyScan_Calibration_Flow] ====Done====
7383 11:08:29.904539
7384 11:08:29.907682 [DutyScan_Calibration_Flow] k_type=1
7385 11:08:29.924544
7386 11:08:29.924690 ==DQS 0 ==
7387 11:08:29.927655 Final DQS duty delay cell = 0
7388 11:08:29.931356 [0] MAX Duty = 5094%(X100), DQS PI = 22
7389 11:08:29.934478 [0] MIN Duty = 4844%(X100), DQS PI = 42
7390 11:08:29.937564 [0] AVG Duty = 4969%(X100)
7391 11:08:29.937643
7392 11:08:29.937707 ==DQS 1 ==
7393 11:08:29.941254 Final DQS duty delay cell = 0
7394 11:08:29.944469 [0] MAX Duty = 5249%(X100), DQS PI = 16
7395 11:08:29.947850 [0] MIN Duty = 4969%(X100), DQS PI = 8
7396 11:08:29.951103 [0] AVG Duty = 5109%(X100)
7397 11:08:29.951185
7398 11:08:29.954218 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7399 11:08:29.954301
7400 11:08:29.957542 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7401 11:08:29.961222 [DutyScan_Calibration_Flow] ====Done====
7402 11:08:29.961306
7403 11:08:29.964276 [DutyScan_Calibration_Flow] k_type=3
7404 11:08:29.981396
7405 11:08:29.981485 ==DQM 0 ==
7406 11:08:29.984754 Final DQM duty delay cell = 0
7407 11:08:29.987839 [0] MAX Duty = 5218%(X100), DQS PI = 20
7408 11:08:29.991792 [0] MIN Duty = 4969%(X100), DQS PI = 48
7409 11:08:29.994779 [0] AVG Duty = 5093%(X100)
7410 11:08:29.994855
7411 11:08:29.994918 ==DQM 1 ==
7412 11:08:29.998171 Final DQM duty delay cell = 0
7413 11:08:30.001126 [0] MAX Duty = 5093%(X100), DQS PI = 16
7414 11:08:30.004568 [0] MIN Duty = 4907%(X100), DQS PI = 50
7415 11:08:30.007906 [0] AVG Duty = 5000%(X100)
7416 11:08:30.007991
7417 11:08:30.011057 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7418 11:08:30.011137
7419 11:08:30.015027 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7420 11:08:30.017765 [DutyScan_Calibration_Flow] ====Done====
7421 11:08:30.017849
7422 11:08:30.021515 [DutyScan_Calibration_Flow] k_type=2
7423 11:08:30.037473
7424 11:08:30.037563 ==DQ 0 ==
7425 11:08:30.040727 Final DQ duty delay cell = -4
7426 11:08:30.044269 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7427 11:08:30.047866 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7428 11:08:30.051039 [-4] AVG Duty = 4968%(X100)
7429 11:08:30.051123
7430 11:08:30.051189 ==DQ 1 ==
7431 11:08:30.054327 Final DQ duty delay cell = 0
7432 11:08:30.057534 [0] MAX Duty = 5125%(X100), DQS PI = 18
7433 11:08:30.060774 [0] MIN Duty = 4938%(X100), DQS PI = 8
7434 11:08:30.064280 [0] AVG Duty = 5031%(X100)
7435 11:08:30.064373
7436 11:08:30.067287 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7437 11:08:30.067371
7438 11:08:30.070553 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7439 11:08:30.074123 [DutyScan_Calibration_Flow] ====Done====
7440 11:08:30.077678 nWR fixed to 30
7441 11:08:30.077763 [ModeRegInit_LP4] CH0 RK0
7442 11:08:30.080739 [ModeRegInit_LP4] CH0 RK1
7443 11:08:30.083892 [ModeRegInit_LP4] CH1 RK0
7444 11:08:30.087261 [ModeRegInit_LP4] CH1 RK1
7445 11:08:30.087345 match AC timing 5
7446 11:08:30.093975 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7447 11:08:30.097360 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7448 11:08:30.100591 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7449 11:08:30.107504 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7450 11:08:30.111023 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7451 11:08:30.111108 [MiockJmeterHQA]
7452 11:08:30.111174
7453 11:08:30.113832 [DramcMiockJmeter] u1RxGatingPI = 0
7454 11:08:30.117384 0 : 4252, 4027
7455 11:08:30.117470 4 : 4363, 4138
7456 11:08:30.120576 8 : 4253, 4026
7457 11:08:30.120663 12 : 4253, 4026
7458 11:08:30.120732 16 : 4253, 4027
7459 11:08:30.123797 20 : 4253, 4026
7460 11:08:30.123884 24 : 4257, 4032
7461 11:08:30.127596 28 : 4363, 4137
7462 11:08:30.127683 32 : 4252, 4027
7463 11:08:30.130790 36 : 4363, 4137
7464 11:08:30.130902 40 : 4255, 4029
7465 11:08:30.131003 44 : 4253, 4026
7466 11:08:30.133794 48 : 4252, 4027
7467 11:08:30.133897 52 : 4363, 4137
7468 11:08:30.137017 56 : 4252, 4026
7469 11:08:30.137101 60 : 4363, 4138
7470 11:08:30.140995 64 : 4253, 4026
7471 11:08:30.141111 68 : 4250, 4027
7472 11:08:30.144060 72 : 4250, 4026
7473 11:08:30.144217 76 : 4250, 4026
7474 11:08:30.144339 80 : 4360, 4137
7475 11:08:30.147313 84 : 4253, 4027
7476 11:08:30.147417 88 : 4361, 113
7477 11:08:30.150503 92 : 4360, 0
7478 11:08:30.150611 96 : 4252, 0
7479 11:08:30.150705 100 : 4250, 0
7480 11:08:30.154424 104 : 4253, 0
7481 11:08:30.154524 108 : 4361, 0
7482 11:08:30.157411 112 : 4361, 0
7483 11:08:30.157510 116 : 4363, 0
7484 11:08:30.157604 120 : 4253, 0
7485 11:08:30.160554 124 : 4250, 0
7486 11:08:30.160633 128 : 4250, 0
7487 11:08:30.160695 132 : 4250, 0
7488 11:08:30.163816 136 : 4250, 0
7489 11:08:30.163919 140 : 4250, 0
7490 11:08:30.167056 144 : 4252, 0
7491 11:08:30.167157 148 : 4250, 0
7492 11:08:30.167248 152 : 4250, 0
7493 11:08:30.170390 156 : 4252, 0
7494 11:08:30.170488 160 : 4361, 0
7495 11:08:30.173770 164 : 4360, 0
7496 11:08:30.173872 168 : 4363, 0
7497 11:08:30.173964 172 : 4250, 0
7498 11:08:30.177117 176 : 4250, 0
7499 11:08:30.177191 180 : 4250, 0
7500 11:08:30.180991 184 : 4255, 0
7501 11:08:30.181095 188 : 4250, 0
7502 11:08:30.181189 192 : 4250, 0
7503 11:08:30.184102 196 : 4252, 0
7504 11:08:30.184201 200 : 4250, 0
7505 11:08:30.187024 204 : 4250, 1123
7506 11:08:30.187139 208 : 4250, 3952
7507 11:08:30.187238 212 : 4250, 4027
7508 11:08:30.190767 216 : 4250, 4027
7509 11:08:30.190873 220 : 4250, 4026
7510 11:08:30.193783 224 : 4250, 4026
7511 11:08:30.193865 228 : 4252, 4027
7512 11:08:30.197025 232 : 4250, 4027
7513 11:08:30.197113 236 : 4250, 4027
7514 11:08:30.200914 240 : 4360, 4137
7515 11:08:30.201001 244 : 4363, 4137
7516 11:08:30.203555 248 : 4248, 4025
7517 11:08:30.203632 252 : 4361, 4138
7518 11:08:30.206866 256 : 4360, 4137
7519 11:08:30.206974 260 : 4253, 4026
7520 11:08:30.210278 264 : 4252, 4027
7521 11:08:30.210358 268 : 4250, 4026
7522 11:08:30.213534 272 : 4250, 4027
7523 11:08:30.213613 276 : 4253, 4026
7524 11:08:30.213677 280 : 4250, 4027
7525 11:08:30.217296 284 : 4250, 4026
7526 11:08:30.217374 288 : 4250, 4027
7527 11:08:30.220373 292 : 4360, 4137
7528 11:08:30.220454 296 : 4361, 4137
7529 11:08:30.223423 300 : 4250, 4027
7530 11:08:30.223537 304 : 4361, 4138
7531 11:08:30.227154 308 : 4360, 4041
7532 11:08:30.227272 312 : 4250, 2237
7533 11:08:30.230166 316 : 4250, 15
7534 11:08:30.230269
7535 11:08:30.230361 MIOCK jitter meter ch=0
7536 11:08:30.230448
7537 11:08:30.233662 1T = (316-88) = 228 dly cells
7538 11:08:30.240026 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7539 11:08:30.240131 ==
7540 11:08:30.243513 Dram Type= 6, Freq= 0, CH_0, rank 0
7541 11:08:30.246901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7542 11:08:30.246986 ==
7543 11:08:30.253325 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7544 11:08:30.256576 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7545 11:08:30.263091 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7546 11:08:30.266696 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7547 11:08:30.276625 [CA 0] Center 43 (12~74) winsize 63
7548 11:08:30.279929 [CA 1] Center 43 (13~74) winsize 62
7549 11:08:30.283261 [CA 2] Center 38 (9~68) winsize 60
7550 11:08:30.286464 [CA 3] Center 38 (8~68) winsize 61
7551 11:08:30.289865 [CA 4] Center 37 (7~67) winsize 61
7552 11:08:30.293047 [CA 5] Center 36 (7~65) winsize 59
7553 11:08:30.293150
7554 11:08:30.296213 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7555 11:08:30.296320
7556 11:08:30.299889 [CATrainingPosCal] consider 1 rank data
7557 11:08:30.302947 u2DelayCellTimex100 = 285/100 ps
7558 11:08:30.306179 CA0 delay=43 (12~74),Diff = 7 PI (23 cell)
7559 11:08:30.312849 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7560 11:08:30.316169 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7561 11:08:30.319382 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7562 11:08:30.323293 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7563 11:08:30.326459 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7564 11:08:30.326560
7565 11:08:30.329460 CA PerBit enable=1, Macro0, CA PI delay=36
7566 11:08:30.329556
7567 11:08:30.332686 [CBTSetCACLKResult] CA Dly = 36
7568 11:08:30.336078 CS Dly: 9 (0~40)
7569 11:08:30.339981 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7570 11:08:30.343051 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7571 11:08:30.343160 ==
7572 11:08:30.345986 Dram Type= 6, Freq= 0, CH_0, rank 1
7573 11:08:30.349502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7574 11:08:30.352841 ==
7575 11:08:30.356237 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7576 11:08:30.359406 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7577 11:08:30.366159 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7578 11:08:30.369248 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7579 11:08:30.380180 [CA 0] Center 42 (12~73) winsize 62
7580 11:08:30.383394 [CA 1] Center 42 (12~73) winsize 62
7581 11:08:30.386118 [CA 2] Center 37 (8~67) winsize 60
7582 11:08:30.389518 [CA 3] Center 37 (7~68) winsize 62
7583 11:08:30.392807 [CA 4] Center 35 (5~65) winsize 61
7584 11:08:30.396141 [CA 5] Center 35 (5~65) winsize 61
7585 11:08:30.396246
7586 11:08:30.399962 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7587 11:08:30.400066
7588 11:08:30.403194 [CATrainingPosCal] consider 2 rank data
7589 11:08:30.406285 u2DelayCellTimex100 = 285/100 ps
7590 11:08:30.409519 CA0 delay=42 (12~73),Diff = 6 PI (20 cell)
7591 11:08:30.416786 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7592 11:08:30.419985 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
7593 11:08:30.423378 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7594 11:08:30.426580 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7595 11:08:30.429863 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7596 11:08:30.429968
7597 11:08:30.433044 CA PerBit enable=1, Macro0, CA PI delay=36
7598 11:08:30.433129
7599 11:08:30.436173 [CBTSetCACLKResult] CA Dly = 36
7600 11:08:30.436279 CS Dly: 9 (0~41)
7601 11:08:30.442889 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7602 11:08:30.446158 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7603 11:08:30.446238
7604 11:08:30.449511 ----->DramcWriteLeveling(PI) begin...
7605 11:08:30.449596 ==
7606 11:08:30.452806 Dram Type= 6, Freq= 0, CH_0, rank 0
7607 11:08:30.456016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7608 11:08:30.459747 ==
7609 11:08:30.459827 Write leveling (Byte 0): 35 => 35
7610 11:08:30.463014 Write leveling (Byte 1): 30 => 30
7611 11:08:30.466092 DramcWriteLeveling(PI) end<-----
7612 11:08:30.466171
7613 11:08:30.466242 ==
7614 11:08:30.469768 Dram Type= 6, Freq= 0, CH_0, rank 0
7615 11:08:30.476181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7616 11:08:30.476268 ==
7617 11:08:30.476349 [Gating] SW mode calibration
7618 11:08:30.486143 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7619 11:08:30.489517 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7620 11:08:30.492562 1 4 0 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7621 11:08:30.499287 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7622 11:08:30.502652 1 4 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7623 11:08:30.506250 1 4 12 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
7624 11:08:30.512631 1 4 16 | B1->B0 | 2525 3737 | 0 0 | (1 1) (0 0)
7625 11:08:30.515749 1 4 20 | B1->B0 | 3434 3a3a | 1 1 | (0 0) (1 1)
7626 11:08:30.519624 1 4 24 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7627 11:08:30.526228 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7628 11:08:30.529503 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7629 11:08:30.532718 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7630 11:08:30.539027 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 0)
7631 11:08:30.542281 1 5 12 | B1->B0 | 3434 2a29 | 1 1 | (1 1) (0 1)
7632 11:08:30.546254 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
7633 11:08:30.552824 1 5 20 | B1->B0 | 2525 2828 | 0 0 | (0 0) (1 1)
7634 11:08:30.555547 1 5 24 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7635 11:08:30.559457 1 5 28 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7636 11:08:30.565778 1 6 0 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
7637 11:08:30.569072 1 6 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7638 11:08:30.572188 1 6 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7639 11:08:30.579335 1 6 12 | B1->B0 | 2323 4544 | 0 1 | (0 0) (0 0)
7640 11:08:30.582119 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7641 11:08:30.585910 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 11:08:30.592799 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 11:08:30.595716 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 11:08:30.599101 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 11:08:30.605823 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 11:08:30.608840 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7647 11:08:30.612318 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7648 11:08:30.618953 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7649 11:08:30.621905 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7650 11:08:30.625486 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 11:08:30.632476 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 11:08:30.635689 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 11:08:30.638931 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 11:08:30.645303 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 11:08:30.648548 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 11:08:30.651813 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 11:08:30.658416 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 11:08:30.661678 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 11:08:30.664976 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 11:08:30.668279 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 11:08:30.675294 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 11:08:30.678663 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7663 11:08:30.681897 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7664 11:08:30.688541 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7665 11:08:30.691773 Total UI for P1: 0, mck2ui 16
7666 11:08:30.695074 best dqsien dly found for B0: ( 1, 9, 10)
7667 11:08:30.698267 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7668 11:08:30.701631 Total UI for P1: 0, mck2ui 16
7669 11:08:30.704802 best dqsien dly found for B1: ( 1, 9, 16)
7670 11:08:30.708549 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7671 11:08:30.711665 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7672 11:08:30.711739
7673 11:08:30.715300 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7674 11:08:30.721561 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7675 11:08:30.721644 [Gating] SW calibration Done
7676 11:08:30.721710 ==
7677 11:08:30.725272 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 11:08:30.731573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 11:08:30.731653 ==
7680 11:08:30.731718 RX Vref Scan: 0
7681 11:08:30.731786
7682 11:08:30.735034 RX Vref 0 -> 0, step: 1
7683 11:08:30.735122
7684 11:08:30.738431 RX Delay 0 -> 252, step: 8
7685 11:08:30.741494 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7686 11:08:30.744844 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7687 11:08:30.748203 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7688 11:08:30.751671 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7689 11:08:30.758278 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7690 11:08:30.761692 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7691 11:08:30.765053 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7692 11:08:30.768339 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7693 11:08:30.771691 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7694 11:08:30.777940 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7695 11:08:30.781155 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7696 11:08:30.784509 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7697 11:08:30.787800 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7698 11:08:30.791215 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7699 11:08:30.797810 iDelay=200, Bit 14, Center 143 (96 ~ 191) 96
7700 11:08:30.801118 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7701 11:08:30.801248 ==
7702 11:08:30.804493 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 11:08:30.808365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 11:08:30.808487 ==
7705 11:08:30.811030 DQS Delay:
7706 11:08:30.811157 DQS0 = 0, DQS1 = 0
7707 11:08:30.811277 DQM Delay:
7708 11:08:30.814777 DQM0 = 137, DQM1 = 130
7709 11:08:30.814899 DQ Delay:
7710 11:08:30.817997 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7711 11:08:30.821475 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7712 11:08:30.824767 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7713 11:08:30.831205 DQ12 =131, DQ13 =139, DQ14 =143, DQ15 =135
7714 11:08:30.831329
7715 11:08:30.831443
7716 11:08:30.831556 ==
7717 11:08:30.834242 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 11:08:30.838167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 11:08:30.838246 ==
7720 11:08:30.838317
7721 11:08:30.838381
7722 11:08:30.841241 TX Vref Scan disable
7723 11:08:30.841316 == TX Byte 0 ==
7724 11:08:30.847955 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7725 11:08:30.851244 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7726 11:08:30.851320 == TX Byte 1 ==
7727 11:08:30.857919 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7728 11:08:30.860913 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7729 11:08:30.860989 ==
7730 11:08:30.864247 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 11:08:30.867414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 11:08:30.867514 ==
7733 11:08:30.880972
7734 11:08:30.883987 TX Vref early break, caculate TX vref
7735 11:08:30.887602 TX Vref=16, minBit 0, minWin=22, winSum=375
7736 11:08:30.890698 TX Vref=18, minBit 9, minWin=23, winSum=387
7737 11:08:30.893991 TX Vref=20, minBit 0, minWin=24, winSum=401
7738 11:08:30.897252 TX Vref=22, minBit 7, minWin=24, winSum=411
7739 11:08:30.900603 TX Vref=24, minBit 0, minWin=25, winSum=422
7740 11:08:30.907777 TX Vref=26, minBit 6, minWin=25, winSum=427
7741 11:08:30.911214 TX Vref=28, minBit 2, minWin=24, winSum=425
7742 11:08:30.914506 TX Vref=30, minBit 1, minWin=24, winSum=410
7743 11:08:30.917310 TX Vref=32, minBit 1, minWin=24, winSum=402
7744 11:08:30.924337 [TxChooseVref] Worse bit 6, Min win 25, Win sum 427, Final Vref 26
7745 11:08:30.924425
7746 11:08:30.927576 Final TX Range 0 Vref 26
7747 11:08:30.927671
7748 11:08:30.927737 ==
7749 11:08:30.930751 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 11:08:30.934025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 11:08:30.934107 ==
7752 11:08:30.934171
7753 11:08:30.934231
7754 11:08:30.937272 TX Vref Scan disable
7755 11:08:30.940479 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7756 11:08:30.944257 == TX Byte 0 ==
7757 11:08:30.947564 u2DelayCellOfst[0]=10 cells (3 PI)
7758 11:08:30.950667 u2DelayCellOfst[1]=13 cells (4 PI)
7759 11:08:30.953671 u2DelayCellOfst[2]=10 cells (3 PI)
7760 11:08:30.957533 u2DelayCellOfst[3]=10 cells (3 PI)
7761 11:08:30.960851 u2DelayCellOfst[4]=6 cells (2 PI)
7762 11:08:30.960936 u2DelayCellOfst[5]=0 cells (0 PI)
7763 11:08:30.964170 u2DelayCellOfst[6]=17 cells (5 PI)
7764 11:08:30.966890 u2DelayCellOfst[7]=17 cells (5 PI)
7765 11:08:30.974210 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7766 11:08:30.977213 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7767 11:08:30.977299 == TX Byte 1 ==
7768 11:08:30.980740 u2DelayCellOfst[8]=0 cells (0 PI)
7769 11:08:30.983570 u2DelayCellOfst[9]=0 cells (0 PI)
7770 11:08:30.986882 u2DelayCellOfst[10]=6 cells (2 PI)
7771 11:08:30.990327 u2DelayCellOfst[11]=3 cells (1 PI)
7772 11:08:30.993517 u2DelayCellOfst[12]=10 cells (3 PI)
7773 11:08:30.997377 u2DelayCellOfst[13]=10 cells (3 PI)
7774 11:08:31.000450 u2DelayCellOfst[14]=17 cells (5 PI)
7775 11:08:31.003626 u2DelayCellOfst[15]=10 cells (3 PI)
7776 11:08:31.006869 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7777 11:08:31.010042 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7778 11:08:31.013355 DramC Write-DBI on
7779 11:08:31.013482 ==
7780 11:08:31.016749 Dram Type= 6, Freq= 0, CH_0, rank 0
7781 11:08:31.020045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7782 11:08:31.020153 ==
7783 11:08:31.020254
7784 11:08:31.023292
7785 11:08:31.023377 TX Vref Scan disable
7786 11:08:31.027042 == TX Byte 0 ==
7787 11:08:31.030371 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7788 11:08:31.033705 == TX Byte 1 ==
7789 11:08:31.036600 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7790 11:08:31.036679 DramC Write-DBI off
7791 11:08:31.036761
7792 11:08:31.040413 [DATLAT]
7793 11:08:31.040507 Freq=1600, CH0 RK0
7794 11:08:31.040588
7795 11:08:31.043599 DATLAT Default: 0xf
7796 11:08:31.043701 0, 0xFFFF, sum = 0
7797 11:08:31.046884 1, 0xFFFF, sum = 0
7798 11:08:31.046960 2, 0xFFFF, sum = 0
7799 11:08:31.049844 3, 0xFFFF, sum = 0
7800 11:08:31.049956 4, 0xFFFF, sum = 0
7801 11:08:31.053909 5, 0xFFFF, sum = 0
7802 11:08:31.054009 6, 0xFFFF, sum = 0
7803 11:08:31.057172 7, 0xFFFF, sum = 0
7804 11:08:31.057258 8, 0xFFFF, sum = 0
7805 11:08:31.060300 9, 0xFFFF, sum = 0
7806 11:08:31.063437 10, 0xFFFF, sum = 0
7807 11:08:31.063517 11, 0xFFFF, sum = 0
7808 11:08:31.066692 12, 0xFFFF, sum = 0
7809 11:08:31.066767 13, 0xFFFF, sum = 0
7810 11:08:31.070190 14, 0x0, sum = 1
7811 11:08:31.070264 15, 0x0, sum = 2
7812 11:08:31.073379 16, 0x0, sum = 3
7813 11:08:31.073464 17, 0x0, sum = 4
7814 11:08:31.073531 best_step = 15
7815 11:08:31.073591
7816 11:08:31.076754 ==
7817 11:08:31.080081 Dram Type= 6, Freq= 0, CH_0, rank 0
7818 11:08:31.083375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7819 11:08:31.083465 ==
7820 11:08:31.083551 RX Vref Scan: 1
7821 11:08:31.083631
7822 11:08:31.086704 Set Vref Range= 24 -> 127
7823 11:08:31.086813
7824 11:08:31.089834 RX Vref 24 -> 127, step: 1
7825 11:08:31.089919
7826 11:08:31.093078 RX Delay 27 -> 252, step: 4
7827 11:08:31.093165
7828 11:08:31.096911 Set Vref, RX VrefLevel [Byte0]: 24
7829 11:08:31.100075 [Byte1]: 24
7830 11:08:31.100160
7831 11:08:31.103038 Set Vref, RX VrefLevel [Byte0]: 25
7832 11:08:31.106446 [Byte1]: 25
7833 11:08:31.106531
7834 11:08:31.110073 Set Vref, RX VrefLevel [Byte0]: 26
7835 11:08:31.112776 [Byte1]: 26
7836 11:08:31.116904
7837 11:08:31.116986 Set Vref, RX VrefLevel [Byte0]: 27
7838 11:08:31.120011 [Byte1]: 27
7839 11:08:31.124327
7840 11:08:31.124413 Set Vref, RX VrefLevel [Byte0]: 28
7841 11:08:31.127173 [Byte1]: 28
7842 11:08:31.131509
7843 11:08:31.131594 Set Vref, RX VrefLevel [Byte0]: 29
7844 11:08:31.134875 [Byte1]: 29
7845 11:08:31.139470
7846 11:08:31.139555 Set Vref, RX VrefLevel [Byte0]: 30
7847 11:08:31.142725 [Byte1]: 30
7848 11:08:31.146811
7849 11:08:31.146896 Set Vref, RX VrefLevel [Byte0]: 31
7850 11:08:31.150069 [Byte1]: 31
7851 11:08:31.154396
7852 11:08:31.154480 Set Vref, RX VrefLevel [Byte0]: 32
7853 11:08:31.157763 [Byte1]: 32
7854 11:08:31.161635
7855 11:08:31.161718 Set Vref, RX VrefLevel [Byte0]: 33
7856 11:08:31.164820 [Byte1]: 33
7857 11:08:31.169615
7858 11:08:31.169700 Set Vref, RX VrefLevel [Byte0]: 34
7859 11:08:31.172544 [Byte1]: 34
7860 11:08:31.176570
7861 11:08:31.176644 Set Vref, RX VrefLevel [Byte0]: 35
7862 11:08:31.179913 [Byte1]: 35
7863 11:08:31.184534
7864 11:08:31.184618 Set Vref, RX VrefLevel [Byte0]: 36
7865 11:08:31.187827 [Byte1]: 36
7866 11:08:31.191778
7867 11:08:31.191887 Set Vref, RX VrefLevel [Byte0]: 37
7868 11:08:31.194874 [Byte1]: 37
7869 11:08:31.199663
7870 11:08:31.199742 Set Vref, RX VrefLevel [Byte0]: 38
7871 11:08:31.202528 [Byte1]: 38
7872 11:08:31.207202
7873 11:08:31.207282 Set Vref, RX VrefLevel [Byte0]: 39
7874 11:08:31.210396 [Byte1]: 39
7875 11:08:31.214242
7876 11:08:31.214346 Set Vref, RX VrefLevel [Byte0]: 40
7877 11:08:31.217644 [Byte1]: 40
7878 11:08:31.222182
7879 11:08:31.222267 Set Vref, RX VrefLevel [Byte0]: 41
7880 11:08:31.225287 [Byte1]: 41
7881 11:08:31.229622
7882 11:08:31.229706 Set Vref, RX VrefLevel [Byte0]: 42
7883 11:08:31.232881 [Byte1]: 42
7884 11:08:31.236925
7885 11:08:31.237008 Set Vref, RX VrefLevel [Byte0]: 43
7886 11:08:31.240484 [Byte1]: 43
7887 11:08:31.244540
7888 11:08:31.244624 Set Vref, RX VrefLevel [Byte0]: 44
7889 11:08:31.247629 [Byte1]: 44
7890 11:08:31.251872
7891 11:08:31.251956 Set Vref, RX VrefLevel [Byte0]: 45
7892 11:08:31.255612 [Byte1]: 45
7893 11:08:31.259410
7894 11:08:31.259523 Set Vref, RX VrefLevel [Byte0]: 46
7895 11:08:31.263215 [Byte1]: 46
7896 11:08:31.267696
7897 11:08:31.267779 Set Vref, RX VrefLevel [Byte0]: 47
7898 11:08:31.270826 [Byte1]: 47
7899 11:08:31.274747
7900 11:08:31.274839 Set Vref, RX VrefLevel [Byte0]: 48
7901 11:08:31.277993 [Byte1]: 48
7902 11:08:31.282660
7903 11:08:31.282760 Set Vref, RX VrefLevel [Byte0]: 49
7904 11:08:31.285408 [Byte1]: 49
7905 11:08:31.289945
7906 11:08:31.290057 Set Vref, RX VrefLevel [Byte0]: 50
7907 11:08:31.293372 [Byte1]: 50
7908 11:08:31.297370
7909 11:08:31.297472 Set Vref, RX VrefLevel [Byte0]: 51
7910 11:08:31.300732 [Byte1]: 51
7911 11:08:31.304794
7912 11:08:31.304883 Set Vref, RX VrefLevel [Byte0]: 52
7913 11:08:31.308168 [Byte1]: 52
7914 11:08:31.312520
7915 11:08:31.312631 Set Vref, RX VrefLevel [Byte0]: 53
7916 11:08:31.315623 [Byte1]: 53
7917 11:08:31.320020
7918 11:08:31.320106 Set Vref, RX VrefLevel [Byte0]: 54
7919 11:08:31.323218 [Byte1]: 54
7920 11:08:31.327242
7921 11:08:31.327352 Set Vref, RX VrefLevel [Byte0]: 55
7922 11:08:31.330558 [Byte1]: 55
7923 11:08:31.334861
7924 11:08:31.334971 Set Vref, RX VrefLevel [Byte0]: 56
7925 11:08:31.338138 [Byte1]: 56
7926 11:08:31.342645
7927 11:08:31.342752 Set Vref, RX VrefLevel [Byte0]: 57
7928 11:08:31.345946 [Byte1]: 57
7929 11:08:31.349844
7930 11:08:31.349921 Set Vref, RX VrefLevel [Byte0]: 58
7931 11:08:31.353471 [Byte1]: 58
7932 11:08:31.357414
7933 11:08:31.357522 Set Vref, RX VrefLevel [Byte0]: 59
7934 11:08:31.360775 [Byte1]: 59
7935 11:08:31.364847
7936 11:08:31.364960 Set Vref, RX VrefLevel [Byte0]: 60
7937 11:08:31.368195 [Byte1]: 60
7938 11:08:31.372592
7939 11:08:31.372682 Set Vref, RX VrefLevel [Byte0]: 61
7940 11:08:31.376101 [Byte1]: 61
7941 11:08:31.380351
7942 11:08:31.380439 Set Vref, RX VrefLevel [Byte0]: 62
7943 11:08:31.383779 [Byte1]: 62
7944 11:08:31.387854
7945 11:08:31.387966 Set Vref, RX VrefLevel [Byte0]: 63
7946 11:08:31.390814 [Byte1]: 63
7947 11:08:31.395091
7948 11:08:31.395173 Set Vref, RX VrefLevel [Byte0]: 64
7949 11:08:31.398413 [Byte1]: 64
7950 11:08:31.402857
7951 11:08:31.402969 Set Vref, RX VrefLevel [Byte0]: 65
7952 11:08:31.406260 [Byte1]: 65
7953 11:08:31.410241
7954 11:08:31.410352 Set Vref, RX VrefLevel [Byte0]: 66
7955 11:08:31.413685 [Byte1]: 66
7956 11:08:31.417728
7957 11:08:31.417806 Set Vref, RX VrefLevel [Byte0]: 67
7958 11:08:31.420922 [Byte1]: 67
7959 11:08:31.425627
7960 11:08:31.425713 Set Vref, RX VrefLevel [Byte0]: 68
7961 11:08:31.428554 [Byte1]: 68
7962 11:08:31.433211
7963 11:08:31.433295 Set Vref, RX VrefLevel [Byte0]: 69
7964 11:08:31.436026 [Byte1]: 69
7965 11:08:31.440736
7966 11:08:31.440849 Set Vref, RX VrefLevel [Byte0]: 70
7967 11:08:31.444042 [Byte1]: 70
7968 11:08:31.447838
7969 11:08:31.447955 Set Vref, RX VrefLevel [Byte0]: 71
7970 11:08:31.451721 [Byte1]: 71
7971 11:08:31.455844
7972 11:08:31.455961 Set Vref, RX VrefLevel [Byte0]: 72
7973 11:08:31.458616 [Byte1]: 72
7974 11:08:31.463380
7975 11:08:31.463489 Set Vref, RX VrefLevel [Byte0]: 73
7976 11:08:31.466007 [Byte1]: 73
7977 11:08:31.470569
7978 11:08:31.470661 Set Vref, RX VrefLevel [Byte0]: 74
7979 11:08:31.474195 [Byte1]: 74
7980 11:08:31.478132
7981 11:08:31.478236 Final RX Vref Byte 0 = 59 to rank0
7982 11:08:31.481421 Final RX Vref Byte 1 = 61 to rank0
7983 11:08:31.484514 Final RX Vref Byte 0 = 59 to rank1
7984 11:08:31.488237 Final RX Vref Byte 1 = 61 to rank1==
7985 11:08:31.491294 Dram Type= 6, Freq= 0, CH_0, rank 0
7986 11:08:31.497927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 11:08:31.498039 ==
7988 11:08:31.498138 DQS Delay:
7989 11:08:31.501348 DQS0 = 0, DQS1 = 0
7990 11:08:31.501451 DQM Delay:
7991 11:08:31.501543 DQM0 = 134, DQM1 = 127
7992 11:08:31.504705 DQ Delay:
7993 11:08:31.508151 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7994 11:08:31.511174 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7995 11:08:31.514370 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7996 11:08:31.518209 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =136
7997 11:08:31.518318
7998 11:08:31.518413
7999 11:08:31.518502
8000 11:08:31.521197 [DramC_TX_OE_Calibration] TA2
8001 11:08:31.524629 Original DQ_B0 (3 6) =30, OEN = 27
8002 11:08:31.527946 Original DQ_B1 (3 6) =30, OEN = 27
8003 11:08:31.531387 24, 0x0, End_B0=24 End_B1=24
8004 11:08:31.531501 25, 0x0, End_B0=25 End_B1=25
8005 11:08:31.534416 26, 0x0, End_B0=26 End_B1=26
8006 11:08:31.537877 27, 0x0, End_B0=27 End_B1=27
8007 11:08:31.541184 28, 0x0, End_B0=28 End_B1=28
8008 11:08:31.544516 29, 0x0, End_B0=29 End_B1=29
8009 11:08:31.544594 30, 0x0, End_B0=30 End_B1=30
8010 11:08:31.548118 31, 0x4141, End_B0=30 End_B1=30
8011 11:08:31.550821 Byte0 end_step=30 best_step=27
8012 11:08:31.554169 Byte1 end_step=30 best_step=27
8013 11:08:31.557900 Byte0 TX OE(2T, 0.5T) = (3, 3)
8014 11:08:31.561218 Byte1 TX OE(2T, 0.5T) = (3, 3)
8015 11:08:31.561304
8016 11:08:31.561378
8017 11:08:31.567429 [DQSOSCAuto] RK0, (LSB)MR18= 0x231f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
8018 11:08:31.570728 CH0 RK0: MR19=303, MR18=231F
8019 11:08:31.577829 CH0_RK0: MR19=0x303, MR18=0x231F, DQSOSC=392, MR23=63, INC=24, DEC=16
8020 11:08:31.577937
8021 11:08:31.580503 ----->DramcWriteLeveling(PI) begin...
8022 11:08:31.580606 ==
8023 11:08:31.583737 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 11:08:31.587144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 11:08:31.587227 ==
8026 11:08:31.590923 Write leveling (Byte 0): 35 => 35
8027 11:08:31.594201 Write leveling (Byte 1): 28 => 28
8028 11:08:31.597506 DramcWriteLeveling(PI) end<-----
8029 11:08:31.597589
8030 11:08:31.597654 ==
8031 11:08:31.600842 Dram Type= 6, Freq= 0, CH_0, rank 1
8032 11:08:31.603993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8033 11:08:31.604076 ==
8034 11:08:31.607202 [Gating] SW mode calibration
8035 11:08:31.613528 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8036 11:08:31.620567 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8037 11:08:31.624167 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8038 11:08:31.630820 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8039 11:08:31.634056 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8040 11:08:31.636964 1 4 12 | B1->B0 | 2323 1616 | 0 1 | (0 0) (0 0)
8041 11:08:31.643796 1 4 16 | B1->B0 | 2e2e 3535 | 1 1 | (1 1) (1 1)
8042 11:08:31.647329 1 4 20 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
8043 11:08:31.650492 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8044 11:08:31.657236 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8045 11:08:31.660585 1 5 0 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
8046 11:08:31.663825 1 5 4 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
8047 11:08:31.666794 1 5 8 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
8048 11:08:31.673660 1 5 12 | B1->B0 | 3434 3534 | 1 1 | (1 0) (0 1)
8049 11:08:31.677181 1 5 16 | B1->B0 | 2c2c 2928 | 0 1 | (0 0) (0 0)
8050 11:08:31.680296 1 5 20 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (1 1)
8051 11:08:31.686699 1 5 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8052 11:08:31.690091 1 5 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8053 11:08:31.693531 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8054 11:08:31.700475 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8055 11:08:31.703792 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 11:08:31.706462 1 6 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
8057 11:08:31.713167 1 6 16 | B1->B0 | 3d3d 4645 | 0 1 | (0 0) (0 0)
8058 11:08:31.716875 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 11:08:31.719897 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8060 11:08:31.726592 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 11:08:31.730007 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 11:08:31.733521 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 11:08:31.740023 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 11:08:31.743310 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8065 11:08:31.746717 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8066 11:08:31.753128 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 11:08:31.756713 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 11:08:31.759513 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 11:08:31.766364 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 11:08:31.769531 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 11:08:31.773259 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 11:08:31.779471 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 11:08:31.782949 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 11:08:31.786285 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 11:08:31.792613 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 11:08:31.796046 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 11:08:31.799371 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 11:08:31.805931 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 11:08:31.809358 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 11:08:31.812933 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8081 11:08:31.819688 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8082 11:08:31.822919 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 11:08:31.826051 Total UI for P1: 0, mck2ui 16
8084 11:08:31.829196 best dqsien dly found for B0: ( 1, 9, 14)
8085 11:08:31.833089 Total UI for P1: 0, mck2ui 16
8086 11:08:31.835774 best dqsien dly found for B1: ( 1, 9, 14)
8087 11:08:31.839032 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8088 11:08:31.842458 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8089 11:08:31.842568
8090 11:08:31.845651 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8091 11:08:31.849155 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8092 11:08:31.852504 [Gating] SW calibration Done
8093 11:08:31.852628 ==
8094 11:08:31.855689 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 11:08:31.858875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 11:08:31.862715 ==
8097 11:08:31.862821 RX Vref Scan: 0
8098 11:08:31.862915
8099 11:08:31.865391 RX Vref 0 -> 0, step: 1
8100 11:08:31.865491
8101 11:08:31.865580 RX Delay 0 -> 252, step: 8
8102 11:08:31.872455 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8103 11:08:31.875765 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8104 11:08:31.879056 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8105 11:08:31.882282 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8106 11:08:31.885624 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8107 11:08:31.892608 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8108 11:08:31.895701 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8109 11:08:31.899100 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8110 11:08:31.901995 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8111 11:08:31.905896 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8112 11:08:31.912480 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8113 11:08:31.915750 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8114 11:08:31.919098 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8115 11:08:31.922014 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8116 11:08:31.928745 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8117 11:08:31.931938 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8118 11:08:31.932018 ==
8119 11:08:31.935264 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 11:08:31.939053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 11:08:31.939141 ==
8122 11:08:31.939245 DQS Delay:
8123 11:08:31.942004 DQS0 = 0, DQS1 = 0
8124 11:08:31.942117 DQM Delay:
8125 11:08:31.945582 DQM0 = 137, DQM1 = 130
8126 11:08:31.945666 DQ Delay:
8127 11:08:31.948848 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8128 11:08:31.952248 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8129 11:08:31.955843 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8130 11:08:31.959121 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8131 11:08:31.962304
8132 11:08:31.962385
8133 11:08:31.962450 ==
8134 11:08:31.965506 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 11:08:31.968672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 11:08:31.968784 ==
8137 11:08:31.968882
8138 11:08:31.968970
8139 11:08:31.972083 TX Vref Scan disable
8140 11:08:31.972186 == TX Byte 0 ==
8141 11:08:31.978761 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8142 11:08:31.982192 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8143 11:08:31.982319 == TX Byte 1 ==
8144 11:08:31.988469 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8145 11:08:31.991550 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8146 11:08:31.991662 ==
8147 11:08:31.995036 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 11:08:31.998380 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 11:08:31.998504 ==
8150 11:08:32.012669
8151 11:08:32.016392 TX Vref early break, caculate TX vref
8152 11:08:32.019294 TX Vref=16, minBit 1, minWin=23, winSum=389
8153 11:08:32.022636 TX Vref=18, minBit 2, minWin=23, winSum=395
8154 11:08:32.026080 TX Vref=20, minBit 3, minWin=23, winSum=403
8155 11:08:32.029897 TX Vref=22, minBit 1, minWin=24, winSum=412
8156 11:08:32.032621 TX Vref=24, minBit 0, minWin=25, winSum=420
8157 11:08:32.039382 TX Vref=26, minBit 1, minWin=25, winSum=424
8158 11:08:32.042678 TX Vref=28, minBit 7, minWin=25, winSum=426
8159 11:08:32.045981 TX Vref=30, minBit 0, minWin=25, winSum=417
8160 11:08:32.049701 TX Vref=32, minBit 4, minWin=24, winSum=410
8161 11:08:32.052968 TX Vref=34, minBit 0, minWin=24, winSum=403
8162 11:08:32.059625 [TxChooseVref] Worse bit 7, Min win 25, Win sum 426, Final Vref 28
8163 11:08:32.059775
8164 11:08:32.062894 Final TX Range 0 Vref 28
8165 11:08:32.063020
8166 11:08:32.063130 ==
8167 11:08:32.066126 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 11:08:32.069469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 11:08:32.069594 ==
8170 11:08:32.069708
8171 11:08:32.069818
8172 11:08:32.072650 TX Vref Scan disable
8173 11:08:32.079523 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8174 11:08:32.079650 == TX Byte 0 ==
8175 11:08:32.082936 u2DelayCellOfst[0]=13 cells (4 PI)
8176 11:08:32.086343 u2DelayCellOfst[1]=17 cells (5 PI)
8177 11:08:32.089141 u2DelayCellOfst[2]=10 cells (3 PI)
8178 11:08:32.092461 u2DelayCellOfst[3]=10 cells (3 PI)
8179 11:08:32.095891 u2DelayCellOfst[4]=10 cells (3 PI)
8180 11:08:32.099287 u2DelayCellOfst[5]=0 cells (0 PI)
8181 11:08:32.102600 u2DelayCellOfst[6]=17 cells (5 PI)
8182 11:08:32.105965 u2DelayCellOfst[7]=13 cells (4 PI)
8183 11:08:32.109175 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8184 11:08:32.112442 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8185 11:08:32.116252 == TX Byte 1 ==
8186 11:08:32.116347 u2DelayCellOfst[8]=0 cells (0 PI)
8187 11:08:32.119002 u2DelayCellOfst[9]=0 cells (0 PI)
8188 11:08:32.122915 u2DelayCellOfst[10]=6 cells (2 PI)
8189 11:08:32.126156 u2DelayCellOfst[11]=3 cells (1 PI)
8190 11:08:32.129357 u2DelayCellOfst[12]=13 cells (4 PI)
8191 11:08:32.132794 u2DelayCellOfst[13]=10 cells (3 PI)
8192 11:08:32.135535 u2DelayCellOfst[14]=13 cells (4 PI)
8193 11:08:32.139625 u2DelayCellOfst[15]=13 cells (4 PI)
8194 11:08:32.142507 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8195 11:08:32.149111 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8196 11:08:32.149208 DramC Write-DBI on
8197 11:08:32.149284 ==
8198 11:08:32.152603 Dram Type= 6, Freq= 0, CH_0, rank 1
8199 11:08:32.155522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8200 11:08:32.159160 ==
8201 11:08:32.159245
8202 11:08:32.159310
8203 11:08:32.159400 TX Vref Scan disable
8204 11:08:32.162414 == TX Byte 0 ==
8205 11:08:32.166151 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8206 11:08:32.169072 == TX Byte 1 ==
8207 11:08:32.172254 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8208 11:08:32.176065 DramC Write-DBI off
8209 11:08:32.176187
8210 11:08:32.176282 [DATLAT]
8211 11:08:32.176359 Freq=1600, CH0 RK1
8212 11:08:32.176419
8213 11:08:32.179351 DATLAT Default: 0xf
8214 11:08:32.179434 0, 0xFFFF, sum = 0
8215 11:08:32.182544 1, 0xFFFF, sum = 0
8216 11:08:32.185853 2, 0xFFFF, sum = 0
8217 11:08:32.185977 3, 0xFFFF, sum = 0
8218 11:08:32.189263 4, 0xFFFF, sum = 0
8219 11:08:32.189388 5, 0xFFFF, sum = 0
8220 11:08:32.192599 6, 0xFFFF, sum = 0
8221 11:08:32.192726 7, 0xFFFF, sum = 0
8222 11:08:32.195852 8, 0xFFFF, sum = 0
8223 11:08:32.195972 9, 0xFFFF, sum = 0
8224 11:08:32.199200 10, 0xFFFF, sum = 0
8225 11:08:32.199326 11, 0xFFFF, sum = 0
8226 11:08:32.202652 12, 0xFFFF, sum = 0
8227 11:08:32.202778 13, 0xFFFF, sum = 0
8228 11:08:32.205466 14, 0x0, sum = 1
8229 11:08:32.205592 15, 0x0, sum = 2
8230 11:08:32.208827 16, 0x0, sum = 3
8231 11:08:32.208934 17, 0x0, sum = 4
8232 11:08:32.212203 best_step = 15
8233 11:08:32.212332
8234 11:08:32.212444 ==
8235 11:08:32.215696 Dram Type= 6, Freq= 0, CH_0, rank 1
8236 11:08:32.218917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8237 11:08:32.219044 ==
8238 11:08:32.222755 RX Vref Scan: 0
8239 11:08:32.222861
8240 11:08:32.222955 RX Vref 0 -> 0, step: 1
8241 11:08:32.223045
8242 11:08:32.226030 RX Delay 19 -> 252, step: 4
8243 11:08:32.228811 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8244 11:08:32.235524 iDelay=191, Bit 1, Center 136 (91 ~ 182) 92
8245 11:08:32.238922 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8246 11:08:32.242497 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8247 11:08:32.245912 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8248 11:08:32.249385 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8249 11:08:32.255491 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8250 11:08:32.258717 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8251 11:08:32.262209 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8252 11:08:32.265485 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8253 11:08:32.268716 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8254 11:08:32.275061 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8255 11:08:32.278581 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8256 11:08:32.281867 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8257 11:08:32.285848 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8258 11:08:32.292064 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8259 11:08:32.292190 ==
8260 11:08:32.295238 Dram Type= 6, Freq= 0, CH_0, rank 1
8261 11:08:32.298344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 11:08:32.298470 ==
8263 11:08:32.298567 DQS Delay:
8264 11:08:32.301666 DQS0 = 0, DQS1 = 0
8265 11:08:32.301793 DQM Delay:
8266 11:08:32.305096 DQM0 = 133, DQM1 = 127
8267 11:08:32.305183 DQ Delay:
8268 11:08:32.308690 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =132
8269 11:08:32.312181 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140
8270 11:08:32.314879 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8271 11:08:32.318213 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
8272 11:08:32.318303
8273 11:08:32.318378
8274 11:08:32.318440
8275 11:08:32.321607 [DramC_TX_OE_Calibration] TA2
8276 11:08:32.325064 Original DQ_B0 (3 6) =30, OEN = 27
8277 11:08:32.328257 Original DQ_B1 (3 6) =30, OEN = 27
8278 11:08:32.331688 24, 0x0, End_B0=24 End_B1=24
8279 11:08:32.334792 25, 0x0, End_B0=25 End_B1=25
8280 11:08:32.334899 26, 0x0, End_B0=26 End_B1=26
8281 11:08:32.338201 27, 0x0, End_B0=27 End_B1=27
8282 11:08:32.341634 28, 0x0, End_B0=28 End_B1=28
8283 11:08:32.344952 29, 0x0, End_B0=29 End_B1=29
8284 11:08:32.348232 30, 0x0, End_B0=30 End_B1=30
8285 11:08:32.348347 31, 0x4141, End_B0=30 End_B1=30
8286 11:08:32.351685 Byte0 end_step=30 best_step=27
8287 11:08:32.355020 Byte1 end_step=30 best_step=27
8288 11:08:32.358504 Byte0 TX OE(2T, 0.5T) = (3, 3)
8289 11:08:32.361911 Byte1 TX OE(2T, 0.5T) = (3, 3)
8290 11:08:32.362047
8291 11:08:32.362165
8292 11:08:32.368569 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8293 11:08:32.371471 CH0 RK1: MR19=303, MR18=2008
8294 11:08:32.378362 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8295 11:08:32.381597 [RxdqsGatingPostProcess] freq 1600
8296 11:08:32.388476 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8297 11:08:32.388602 best DQS0 dly(2T, 0.5T) = (1, 1)
8298 11:08:32.391568 best DQS1 dly(2T, 0.5T) = (1, 1)
8299 11:08:32.394699 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8300 11:08:32.398064 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8301 11:08:32.401341 best DQS0 dly(2T, 0.5T) = (1, 1)
8302 11:08:32.405203 best DQS1 dly(2T, 0.5T) = (1, 1)
8303 11:08:32.408171 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8304 11:08:32.411537 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8305 11:08:32.414755 Pre-setting of DQS Precalculation
8306 11:08:32.418210 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8307 11:08:32.418296 ==
8308 11:08:32.421914 Dram Type= 6, Freq= 0, CH_1, rank 0
8309 11:08:32.427978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 11:08:32.428060 ==
8311 11:08:32.431229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8312 11:08:32.438010 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8313 11:08:32.441266 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8314 11:08:32.448195 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8315 11:08:32.455847 [CA 0] Center 42 (13~72) winsize 60
8316 11:08:32.459166 [CA 1] Center 42 (13~72) winsize 60
8317 11:08:32.462555 [CA 2] Center 39 (10~68) winsize 59
8318 11:08:32.465283 [CA 3] Center 38 (9~68) winsize 60
8319 11:08:32.468775 [CA 4] Center 38 (9~68) winsize 60
8320 11:08:32.472241 [CA 5] Center 37 (8~67) winsize 60
8321 11:08:32.472369
8322 11:08:32.475582 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8323 11:08:32.475702
8324 11:08:32.478902 [CATrainingPosCal] consider 1 rank data
8325 11:08:32.482258 u2DelayCellTimex100 = 285/100 ps
8326 11:08:32.485685 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8327 11:08:32.492304 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8328 11:08:32.495689 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8329 11:08:32.498737 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
8330 11:08:32.502486 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8331 11:08:32.505697 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8332 11:08:32.505801
8333 11:08:32.509207 CA PerBit enable=1, Macro0, CA PI delay=37
8334 11:08:32.509321
8335 11:08:32.512500 [CBTSetCACLKResult] CA Dly = 37
8336 11:08:32.515857 CS Dly: 10 (0~41)
8337 11:08:32.519136 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8338 11:08:32.522385 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8339 11:08:32.522510 ==
8340 11:08:32.525616 Dram Type= 6, Freq= 0, CH_1, rank 1
8341 11:08:32.529256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8342 11:08:32.529345 ==
8343 11:08:32.535833 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8344 11:08:32.538950 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8345 11:08:32.545434 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8346 11:08:32.549048 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8347 11:08:32.559013 [CA 0] Center 42 (12~72) winsize 61
8348 11:08:32.562145 [CA 1] Center 41 (12~71) winsize 60
8349 11:08:32.565615 [CA 2] Center 38 (9~68) winsize 60
8350 11:08:32.568950 [CA 3] Center 38 (9~67) winsize 59
8351 11:08:32.572157 [CA 4] Center 38 (9~68) winsize 60
8352 11:08:32.575553 [CA 5] Center 37 (7~67) winsize 61
8353 11:08:32.575656
8354 11:08:32.578942 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8355 11:08:32.579026
8356 11:08:32.582241 [CATrainingPosCal] consider 2 rank data
8357 11:08:32.585490 u2DelayCellTimex100 = 285/100 ps
8358 11:08:32.589014 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8359 11:08:32.595451 CA1 delay=42 (13~71),Diff = 5 PI (17 cell)
8360 11:08:32.598719 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8361 11:08:32.602276 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8362 11:08:32.605513 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8363 11:08:32.608779 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8364 11:08:32.608915
8365 11:08:32.612479 CA PerBit enable=1, Macro0, CA PI delay=37
8366 11:08:32.612604
8367 11:08:32.615765 [CBTSetCACLKResult] CA Dly = 37
8368 11:08:32.619118 CS Dly: 12 (0~45)
8369 11:08:32.621969 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8370 11:08:32.625400 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8371 11:08:32.625485
8372 11:08:32.628915 ----->DramcWriteLeveling(PI) begin...
8373 11:08:32.629026 ==
8374 11:08:32.632369 Dram Type= 6, Freq= 0, CH_1, rank 0
8375 11:08:32.635544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8376 11:08:32.638720 ==
8377 11:08:32.638805 Write leveling (Byte 0): 27 => 27
8378 11:08:32.642328 Write leveling (Byte 1): 28 => 28
8379 11:08:32.645782 DramcWriteLeveling(PI) end<-----
8380 11:08:32.645906
8381 11:08:32.646021 ==
8382 11:08:32.648880 Dram Type= 6, Freq= 0, CH_1, rank 0
8383 11:08:32.655463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8384 11:08:32.655593 ==
8385 11:08:32.655712 [Gating] SW mode calibration
8386 11:08:32.665733 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8387 11:08:32.668893 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8388 11:08:32.675821 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 11:08:32.678604 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 11:08:32.682236 1 4 8 | B1->B0 | 2424 2c2c | 0 1 | (0 0) (1 1)
8391 11:08:32.685370 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8392 11:08:32.691964 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 11:08:32.695198 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 11:08:32.698573 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 11:08:32.705277 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 11:08:32.708766 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 11:08:32.712129 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 11:08:32.718308 1 5 8 | B1->B0 | 3434 2e2e | 0 1 | (0 1) (1 0)
8399 11:08:32.721957 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
8400 11:08:32.725112 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 11:08:32.731799 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 11:08:32.735253 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 11:08:32.738608 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 11:08:32.745339 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 11:08:32.748755 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 11:08:32.751883 1 6 8 | B1->B0 | 2c2c 4242 | 1 0 | (0 0) (0 0)
8407 11:08:32.758260 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8408 11:08:32.761765 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 11:08:32.764820 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 11:08:32.771597 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 11:08:32.774978 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 11:08:32.778210 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 11:08:32.784752 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 11:08:32.787925 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8415 11:08:32.791221 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8416 11:08:32.798352 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 11:08:32.801625 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 11:08:32.804495 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 11:08:32.811205 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 11:08:32.814671 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 11:08:32.818179 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 11:08:32.824779 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 11:08:32.828052 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 11:08:32.831090 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 11:08:32.838118 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 11:08:32.840883 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 11:08:32.844189 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 11:08:32.851313 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 11:08:32.854566 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 11:08:32.857865 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8431 11:08:32.864181 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8432 11:08:32.867829 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 11:08:32.870908 Total UI for P1: 0, mck2ui 16
8434 11:08:32.874362 best dqsien dly found for B0: ( 1, 9, 10)
8435 11:08:32.877951 Total UI for P1: 0, mck2ui 16
8436 11:08:32.881209 best dqsien dly found for B1: ( 1, 9, 10)
8437 11:08:32.884425 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8438 11:08:32.887551 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8439 11:08:32.887635
8440 11:08:32.890784 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8441 11:08:32.894021 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8442 11:08:32.898004 [Gating] SW calibration Done
8443 11:08:32.898087 ==
8444 11:08:32.901365 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 11:08:32.904667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 11:08:32.904751 ==
8447 11:08:32.907852 RX Vref Scan: 0
8448 11:08:32.907935
8449 11:08:32.911069 RX Vref 0 -> 0, step: 1
8450 11:08:32.911152
8451 11:08:32.911218 RX Delay 0 -> 252, step: 8
8452 11:08:32.917355 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8453 11:08:32.920905 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8454 11:08:32.924162 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8455 11:08:32.927628 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8456 11:08:32.930630 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8457 11:08:32.937458 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8458 11:08:32.941001 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8459 11:08:32.943971 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8460 11:08:32.947235 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8461 11:08:32.951051 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8462 11:08:32.957043 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8463 11:08:32.960502 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8464 11:08:32.963779 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8465 11:08:32.967697 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8466 11:08:32.970804 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8467 11:08:32.977368 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8468 11:08:32.977449 ==
8469 11:08:32.980570 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 11:08:32.983704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 11:08:32.983786 ==
8472 11:08:32.983850 DQS Delay:
8473 11:08:32.986965 DQS0 = 0, DQS1 = 0
8474 11:08:32.987050 DQM Delay:
8475 11:08:32.990243 DQM0 = 137, DQM1 = 133
8476 11:08:32.990325 DQ Delay:
8477 11:08:32.993749 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8478 11:08:32.996984 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8479 11:08:33.000668 DQ8 =123, DQ9 =123, DQ10 =131, DQ11 =127
8480 11:08:33.003963 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =139
8481 11:08:33.004044
8482 11:08:33.004131
8483 11:08:33.007358 ==
8484 11:08:33.010623 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 11:08:33.013926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 11:08:33.014007 ==
8487 11:08:33.014071
8488 11:08:33.014130
8489 11:08:33.017411 TX Vref Scan disable
8490 11:08:33.017493 == TX Byte 0 ==
8491 11:08:33.024125 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8492 11:08:33.027294 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8493 11:08:33.027375 == TX Byte 1 ==
8494 11:08:33.033841 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8495 11:08:33.036910 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8496 11:08:33.036991 ==
8497 11:08:33.040579 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 11:08:33.043544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 11:08:33.043626 ==
8500 11:08:33.056503
8501 11:08:33.059727 TX Vref early break, caculate TX vref
8502 11:08:33.062810 TX Vref=16, minBit 9, minWin=22, winSum=377
8503 11:08:33.066239 TX Vref=18, minBit 1, minWin=23, winSum=385
8504 11:08:33.069524 TX Vref=20, minBit 1, minWin=23, winSum=397
8505 11:08:33.072832 TX Vref=22, minBit 1, minWin=24, winSum=404
8506 11:08:33.076841 TX Vref=24, minBit 0, minWin=25, winSum=414
8507 11:08:33.082927 TX Vref=26, minBit 1, minWin=25, winSum=422
8508 11:08:33.086292 TX Vref=28, minBit 2, minWin=25, winSum=424
8509 11:08:33.089705 TX Vref=30, minBit 0, minWin=25, winSum=420
8510 11:08:33.093007 TX Vref=32, minBit 2, minWin=24, winSum=409
8511 11:08:33.096312 TX Vref=34, minBit 0, minWin=23, winSum=398
8512 11:08:33.103267 [TxChooseVref] Worse bit 2, Min win 25, Win sum 424, Final Vref 28
8513 11:08:33.103369
8514 11:08:33.106716 Final TX Range 0 Vref 28
8515 11:08:33.106802
8516 11:08:33.106867 ==
8517 11:08:33.109730 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 11:08:33.112786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 11:08:33.112868 ==
8520 11:08:33.112933
8521 11:08:33.112992
8522 11:08:33.116737 TX Vref Scan disable
8523 11:08:33.123034 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8524 11:08:33.123116 == TX Byte 0 ==
8525 11:08:33.126429 u2DelayCellOfst[0]=17 cells (5 PI)
8526 11:08:33.129815 u2DelayCellOfst[1]=10 cells (3 PI)
8527 11:08:33.133242 u2DelayCellOfst[2]=0 cells (0 PI)
8528 11:08:33.135965 u2DelayCellOfst[3]=6 cells (2 PI)
8529 11:08:33.139807 u2DelayCellOfst[4]=6 cells (2 PI)
8530 11:08:33.142768 u2DelayCellOfst[5]=17 cells (5 PI)
8531 11:08:33.142879 u2DelayCellOfst[6]=17 cells (5 PI)
8532 11:08:33.146041 u2DelayCellOfst[7]=6 cells (2 PI)
8533 11:08:33.152771 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8534 11:08:33.156253 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8535 11:08:33.156385 == TX Byte 1 ==
8536 11:08:33.159554 u2DelayCellOfst[8]=0 cells (0 PI)
8537 11:08:33.162620 u2DelayCellOfst[9]=6 cells (2 PI)
8538 11:08:33.165900 u2DelayCellOfst[10]=13 cells (4 PI)
8539 11:08:33.169545 u2DelayCellOfst[11]=3 cells (1 PI)
8540 11:08:33.172566 u2DelayCellOfst[12]=17 cells (5 PI)
8541 11:08:33.175984 u2DelayCellOfst[13]=17 cells (5 PI)
8542 11:08:33.179219 u2DelayCellOfst[14]=20 cells (6 PI)
8543 11:08:33.182880 u2DelayCellOfst[15]=17 cells (5 PI)
8544 11:08:33.186378 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8545 11:08:33.189633 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8546 11:08:33.193071 DramC Write-DBI on
8547 11:08:33.193154 ==
8548 11:08:33.196348 Dram Type= 6, Freq= 0, CH_1, rank 0
8549 11:08:33.199112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8550 11:08:33.199223 ==
8551 11:08:33.199322
8552 11:08:33.202455
8553 11:08:33.202566 TX Vref Scan disable
8554 11:08:33.206022 == TX Byte 0 ==
8555 11:08:33.209313 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8556 11:08:33.212618 == TX Byte 1 ==
8557 11:08:33.216153 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8558 11:08:33.216263 DramC Write-DBI off
8559 11:08:33.216378
8560 11:08:33.219003 [DATLAT]
8561 11:08:33.219077 Freq=1600, CH1 RK0
8562 11:08:33.219139
8563 11:08:33.222665 DATLAT Default: 0xf
8564 11:08:33.222742 0, 0xFFFF, sum = 0
8565 11:08:33.226132 1, 0xFFFF, sum = 0
8566 11:08:33.226234 2, 0xFFFF, sum = 0
8567 11:08:33.229128 3, 0xFFFF, sum = 0
8568 11:08:33.229210 4, 0xFFFF, sum = 0
8569 11:08:33.232705 5, 0xFFFF, sum = 0
8570 11:08:33.232788 6, 0xFFFF, sum = 0
8571 11:08:33.236006 7, 0xFFFF, sum = 0
8572 11:08:33.236114 8, 0xFFFF, sum = 0
8573 11:08:33.239382 9, 0xFFFF, sum = 0
8574 11:08:33.242690 10, 0xFFFF, sum = 0
8575 11:08:33.242799 11, 0xFFFF, sum = 0
8576 11:08:33.246059 12, 0xFFFF, sum = 0
8577 11:08:33.246141 13, 0xFFFF, sum = 0
8578 11:08:33.249514 14, 0x0, sum = 1
8579 11:08:33.249596 15, 0x0, sum = 2
8580 11:08:33.252478 16, 0x0, sum = 3
8581 11:08:33.252587 17, 0x0, sum = 4
8582 11:08:33.252681 best_step = 15
8583 11:08:33.255638
8584 11:08:33.255743 ==
8585 11:08:33.259437 Dram Type= 6, Freq= 0, CH_1, rank 0
8586 11:08:33.262780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8587 11:08:33.262889 ==
8588 11:08:33.262983 RX Vref Scan: 1
8589 11:08:33.263073
8590 11:08:33.265832 Set Vref Range= 24 -> 127
8591 11:08:33.265914
8592 11:08:33.269336 RX Vref 24 -> 127, step: 1
8593 11:08:33.269418
8594 11:08:33.272518 RX Delay 27 -> 252, step: 4
8595 11:08:33.272603
8596 11:08:33.275970 Set Vref, RX VrefLevel [Byte0]: 24
8597 11:08:33.279171 [Byte1]: 24
8598 11:08:33.279253
8599 11:08:33.282430 Set Vref, RX VrefLevel [Byte0]: 25
8600 11:08:33.286042 [Byte1]: 25
8601 11:08:33.286124
8602 11:08:33.289127 Set Vref, RX VrefLevel [Byte0]: 26
8603 11:08:33.292403 [Byte1]: 26
8604 11:08:33.295640
8605 11:08:33.295749 Set Vref, RX VrefLevel [Byte0]: 27
8606 11:08:33.299229 [Byte1]: 27
8607 11:08:33.303151
8608 11:08:33.303230 Set Vref, RX VrefLevel [Byte0]: 28
8609 11:08:33.306564 [Byte1]: 28
8610 11:08:33.310604
8611 11:08:33.310722 Set Vref, RX VrefLevel [Byte0]: 29
8612 11:08:33.313857 [Byte1]: 29
8613 11:08:33.318622
8614 11:08:33.318746 Set Vref, RX VrefLevel [Byte0]: 30
8615 11:08:33.321898 [Byte1]: 30
8616 11:08:33.325853
8617 11:08:33.325962 Set Vref, RX VrefLevel [Byte0]: 31
8618 11:08:33.329270 [Byte1]: 31
8619 11:08:33.333261
8620 11:08:33.333373 Set Vref, RX VrefLevel [Byte0]: 32
8621 11:08:33.336825 [Byte1]: 32
8622 11:08:33.341244
8623 11:08:33.341360 Set Vref, RX VrefLevel [Byte0]: 33
8624 11:08:33.344245 [Byte1]: 33
8625 11:08:33.348213
8626 11:08:33.348318 Set Vref, RX VrefLevel [Byte0]: 34
8627 11:08:33.351684 [Byte1]: 34
8628 11:08:33.356263
8629 11:08:33.356362 Set Vref, RX VrefLevel [Byte0]: 35
8630 11:08:33.359647 [Byte1]: 35
8631 11:08:33.363166
8632 11:08:33.363275 Set Vref, RX VrefLevel [Byte0]: 36
8633 11:08:33.367132 [Byte1]: 36
8634 11:08:33.371364
8635 11:08:33.371464 Set Vref, RX VrefLevel [Byte0]: 37
8636 11:08:33.374593 [Byte1]: 37
8637 11:08:33.378499
8638 11:08:33.378608 Set Vref, RX VrefLevel [Byte0]: 38
8639 11:08:33.381848 [Byte1]: 38
8640 11:08:33.385972
8641 11:08:33.386076 Set Vref, RX VrefLevel [Byte0]: 39
8642 11:08:33.389482 [Byte1]: 39
8643 11:08:33.393622
8644 11:08:33.393716 Set Vref, RX VrefLevel [Byte0]: 40
8645 11:08:33.396786 [Byte1]: 40
8646 11:08:33.401385
8647 11:08:33.401483 Set Vref, RX VrefLevel [Byte0]: 41
8648 11:08:33.404431 [Byte1]: 41
8649 11:08:33.408544
8650 11:08:33.408658 Set Vref, RX VrefLevel [Byte0]: 42
8651 11:08:33.411981 [Byte1]: 42
8652 11:08:33.416664
8653 11:08:33.416745 Set Vref, RX VrefLevel [Byte0]: 43
8654 11:08:33.419353 [Byte1]: 43
8655 11:08:33.423478
8656 11:08:33.423562 Set Vref, RX VrefLevel [Byte0]: 44
8657 11:08:33.426851 [Byte1]: 44
8658 11:08:33.431672
8659 11:08:33.431787 Set Vref, RX VrefLevel [Byte0]: 45
8660 11:08:33.434435 [Byte1]: 45
8661 11:08:33.438964
8662 11:08:33.439072 Set Vref, RX VrefLevel [Byte0]: 46
8663 11:08:33.442279 [Byte1]: 46
8664 11:08:33.446194
8665 11:08:33.446301 Set Vref, RX VrefLevel [Byte0]: 47
8666 11:08:33.449904 [Byte1]: 47
8667 11:08:33.454205
8668 11:08:33.454315 Set Vref, RX VrefLevel [Byte0]: 48
8669 11:08:33.457388 [Byte1]: 48
8670 11:08:33.461487
8671 11:08:33.461602 Set Vref, RX VrefLevel [Byte0]: 49
8672 11:08:33.464781 [Byte1]: 49
8673 11:08:33.469202
8674 11:08:33.469320 Set Vref, RX VrefLevel [Byte0]: 50
8675 11:08:33.472390 [Byte1]: 50
8676 11:08:33.476413
8677 11:08:33.476524 Set Vref, RX VrefLevel [Byte0]: 51
8678 11:08:33.479809 [Byte1]: 51
8679 11:08:33.484148
8680 11:08:33.484257 Set Vref, RX VrefLevel [Byte0]: 52
8681 11:08:33.487530 [Byte1]: 52
8682 11:08:33.491651
8683 11:08:33.491732 Set Vref, RX VrefLevel [Byte0]: 53
8684 11:08:33.494887 [Byte1]: 53
8685 11:08:33.499032
8686 11:08:33.499142 Set Vref, RX VrefLevel [Byte0]: 54
8687 11:08:33.502486 [Byte1]: 54
8688 11:08:33.506955
8689 11:08:33.507038 Set Vref, RX VrefLevel [Byte0]: 55
8690 11:08:33.509765 [Byte1]: 55
8691 11:08:33.514192
8692 11:08:33.514274 Set Vref, RX VrefLevel [Byte0]: 56
8693 11:08:33.517265 [Byte1]: 56
8694 11:08:33.522061
8695 11:08:33.522144 Set Vref, RX VrefLevel [Byte0]: 57
8696 11:08:33.525104 [Byte1]: 57
8697 11:08:33.529029
8698 11:08:33.529111 Set Vref, RX VrefLevel [Byte0]: 58
8699 11:08:33.532839 [Byte1]: 58
8700 11:08:33.536647
8701 11:08:33.536729 Set Vref, RX VrefLevel [Byte0]: 59
8702 11:08:33.539959 [Byte1]: 59
8703 11:08:33.544536
8704 11:08:33.544618 Set Vref, RX VrefLevel [Byte0]: 60
8705 11:08:33.547679 [Byte1]: 60
8706 11:08:33.551566
8707 11:08:33.551649 Set Vref, RX VrefLevel [Byte0]: 61
8708 11:08:33.555548 [Byte1]: 61
8709 11:08:33.559307
8710 11:08:33.559388 Set Vref, RX VrefLevel [Byte0]: 62
8711 11:08:33.562513 [Byte1]: 62
8712 11:08:33.567421
8713 11:08:33.567503 Set Vref, RX VrefLevel [Byte0]: 63
8714 11:08:33.570331 [Byte1]: 63
8715 11:08:33.574186
8716 11:08:33.574267 Set Vref, RX VrefLevel [Byte0]: 64
8717 11:08:33.577979 [Byte1]: 64
8718 11:08:33.581784
8719 11:08:33.581869 Set Vref, RX VrefLevel [Byte0]: 65
8720 11:08:33.585700 [Byte1]: 65
8721 11:08:33.589482
8722 11:08:33.589563 Set Vref, RX VrefLevel [Byte0]: 66
8723 11:08:33.592643 [Byte1]: 66
8724 11:08:33.597316
8725 11:08:33.597413 Set Vref, RX VrefLevel [Byte0]: 67
8726 11:08:33.600075 [Byte1]: 67
8727 11:08:33.604933
8728 11:08:33.605030 Set Vref, RX VrefLevel [Byte0]: 68
8729 11:08:33.607670 [Byte1]: 68
8730 11:08:33.612463
8731 11:08:33.612576 Set Vref, RX VrefLevel [Byte0]: 69
8732 11:08:33.615162 [Byte1]: 69
8733 11:08:33.619740
8734 11:08:33.619821 Set Vref, RX VrefLevel [Byte0]: 70
8735 11:08:33.623193 [Byte1]: 70
8736 11:08:33.626982
8737 11:08:33.627063 Set Vref, RX VrefLevel [Byte0]: 71
8738 11:08:33.630179 [Byte1]: 71
8739 11:08:33.634753
8740 11:08:33.634834 Set Vref, RX VrefLevel [Byte0]: 72
8741 11:08:33.638087 [Byte1]: 72
8742 11:08:33.642572
8743 11:08:33.642652 Set Vref, RX VrefLevel [Byte0]: 73
8744 11:08:33.645772 [Byte1]: 73
8745 11:08:33.649921
8746 11:08:33.650002 Set Vref, RX VrefLevel [Byte0]: 74
8747 11:08:33.653060 [Byte1]: 74
8748 11:08:33.657491
8749 11:08:33.657573 Set Vref, RX VrefLevel [Byte0]: 75
8750 11:08:33.660873 [Byte1]: 75
8751 11:08:33.664704
8752 11:08:33.664787 Set Vref, RX VrefLevel [Byte0]: 76
8753 11:08:33.667876 [Byte1]: 76
8754 11:08:33.672247
8755 11:08:33.672367 Final RX Vref Byte 0 = 58 to rank0
8756 11:08:33.675672 Final RX Vref Byte 1 = 56 to rank0
8757 11:08:33.679408 Final RX Vref Byte 0 = 58 to rank1
8758 11:08:33.682544 Final RX Vref Byte 1 = 56 to rank1==
8759 11:08:33.685909 Dram Type= 6, Freq= 0, CH_1, rank 0
8760 11:08:33.692213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8761 11:08:33.692324 ==
8762 11:08:33.692404 DQS Delay:
8763 11:08:33.692464 DQS0 = 0, DQS1 = 0
8764 11:08:33.695590 DQM Delay:
8765 11:08:33.695671 DQM0 = 134, DQM1 = 131
8766 11:08:33.698786 DQ Delay:
8767 11:08:33.702703 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8768 11:08:33.705443 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8769 11:08:33.708773 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8770 11:08:33.712080 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8771 11:08:33.712161
8772 11:08:33.712225
8773 11:08:33.712308
8774 11:08:33.715359 [DramC_TX_OE_Calibration] TA2
8775 11:08:33.719210 Original DQ_B0 (3 6) =30, OEN = 27
8776 11:08:33.722578 Original DQ_B1 (3 6) =30, OEN = 27
8777 11:08:33.725274 24, 0x0, End_B0=24 End_B1=24
8778 11:08:33.725358 25, 0x0, End_B0=25 End_B1=25
8779 11:08:33.729123 26, 0x0, End_B0=26 End_B1=26
8780 11:08:33.732361 27, 0x0, End_B0=27 End_B1=27
8781 11:08:33.735794 28, 0x0, End_B0=28 End_B1=28
8782 11:08:33.735877 29, 0x0, End_B0=29 End_B1=29
8783 11:08:33.739087 30, 0x0, End_B0=30 End_B1=30
8784 11:08:33.742474 31, 0x4141, End_B0=30 End_B1=30
8785 11:08:33.745207 Byte0 end_step=30 best_step=27
8786 11:08:33.748914 Byte1 end_step=30 best_step=27
8787 11:08:33.751977 Byte0 TX OE(2T, 0.5T) = (3, 3)
8788 11:08:33.752059 Byte1 TX OE(2T, 0.5T) = (3, 3)
8789 11:08:33.755590
8790 11:08:33.755670
8791 11:08:33.762292 [DQSOSCAuto] RK0, (LSB)MR18= 0x1825, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
8792 11:08:33.765491 CH1 RK0: MR19=303, MR18=1825
8793 11:08:33.771871 CH1_RK0: MR19=0x303, MR18=0x1825, DQSOSC=391, MR23=63, INC=24, DEC=16
8794 11:08:33.771954
8795 11:08:33.775732 ----->DramcWriteLeveling(PI) begin...
8796 11:08:33.775814 ==
8797 11:08:33.778938 Dram Type= 6, Freq= 0, CH_1, rank 1
8798 11:08:33.782075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8799 11:08:33.782167 ==
8800 11:08:33.785603 Write leveling (Byte 0): 25 => 25
8801 11:08:33.788294 Write leveling (Byte 1): 30 => 30
8802 11:08:33.791970 DramcWriteLeveling(PI) end<-----
8803 11:08:33.792052
8804 11:08:33.792116 ==
8805 11:08:33.795540 Dram Type= 6, Freq= 0, CH_1, rank 1
8806 11:08:33.798742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8807 11:08:33.798825 ==
8808 11:08:33.801808 [Gating] SW mode calibration
8809 11:08:33.808409 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8810 11:08:33.814952 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8811 11:08:33.818327 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 11:08:33.825085 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 11:08:33.828322 1 4 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8814 11:08:33.831720 1 4 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (0 0)
8815 11:08:33.834943 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 11:08:33.841556 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 11:08:33.845050 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 11:08:33.848270 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 11:08:33.854865 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 11:08:33.858267 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8821 11:08:33.861465 1 5 8 | B1->B0 | 3232 3434 | 0 1 | (1 0) (1 0)
8822 11:08:33.868223 1 5 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 1)
8823 11:08:33.871261 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 11:08:33.874617 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 11:08:33.881010 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 11:08:33.884199 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 11:08:33.887396 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 11:08:33.894419 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 11:08:33.897868 1 6 8 | B1->B0 | 4040 2424 | 1 0 | (0 0) (0 0)
8830 11:08:33.900808 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 11:08:33.907545 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 11:08:33.911265 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 11:08:33.914637 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 11:08:33.920736 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 11:08:33.924099 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 11:08:33.928076 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8837 11:08:33.933928 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8838 11:08:33.937971 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8839 11:08:33.941230 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 11:08:33.947771 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 11:08:33.951065 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 11:08:33.954376 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 11:08:33.960848 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 11:08:33.964216 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 11:08:33.967450 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 11:08:33.973939 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 11:08:33.977911 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 11:08:33.981232 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 11:08:33.987253 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 11:08:33.991151 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 11:08:33.994484 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 11:08:33.997781 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8853 11:08:34.004078 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8854 11:08:34.007639 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8855 11:08:34.010830 Total UI for P1: 0, mck2ui 16
8856 11:08:34.014018 best dqsien dly found for B1: ( 1, 9, 6)
8857 11:08:34.017278 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 11:08:34.021098 Total UI for P1: 0, mck2ui 16
8859 11:08:34.024085 best dqsien dly found for B0: ( 1, 9, 12)
8860 11:08:34.027499 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8861 11:08:34.030592 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8862 11:08:34.030673
8863 11:08:34.037742 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8864 11:08:34.040972 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8865 11:08:34.044086 [Gating] SW calibration Done
8866 11:08:34.044229 ==
8867 11:08:34.047357 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 11:08:34.050723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 11:08:34.050881 ==
8870 11:08:34.050975 RX Vref Scan: 0
8871 11:08:34.051062
8872 11:08:34.054145 RX Vref 0 -> 0, step: 1
8873 11:08:34.054247
8874 11:08:34.057502 RX Delay 0 -> 252, step: 8
8875 11:08:34.060929 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8876 11:08:34.064225 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8877 11:08:34.067736 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8878 11:08:34.074430 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8879 11:08:34.077671 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8880 11:08:34.080433 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8881 11:08:34.083713 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8882 11:08:34.087149 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8883 11:08:34.094302 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8884 11:08:34.097436 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8885 11:08:34.100640 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8886 11:08:34.104000 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8887 11:08:34.107465 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8888 11:08:34.113789 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8889 11:08:34.117014 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8890 11:08:34.121053 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8891 11:08:34.121139 ==
8892 11:08:34.123569 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 11:08:34.127028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 11:08:34.130218 ==
8895 11:08:34.130330 DQS Delay:
8896 11:08:34.130419 DQS0 = 0, DQS1 = 0
8897 11:08:34.133772 DQM Delay:
8898 11:08:34.133871 DQM0 = 136, DQM1 = 133
8899 11:08:34.137678 DQ Delay:
8900 11:08:34.140602 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8901 11:08:34.143982 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8902 11:08:34.146930 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8903 11:08:34.150593 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8904 11:08:34.150673
8905 11:08:34.150745
8906 11:08:34.150806 ==
8907 11:08:34.153727 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 11:08:34.157057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 11:08:34.157144 ==
8910 11:08:34.157254
8911 11:08:34.157347
8912 11:08:34.160387 TX Vref Scan disable
8913 11:08:34.163847 == TX Byte 0 ==
8914 11:08:34.167185 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8915 11:08:34.170572 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8916 11:08:34.174023 == TX Byte 1 ==
8917 11:08:34.177526 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8918 11:08:34.180728 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8919 11:08:34.180820 ==
8920 11:08:34.184048 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 11:08:34.190544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 11:08:34.190661 ==
8923 11:08:34.202030
8924 11:08:34.205852 TX Vref early break, caculate TX vref
8925 11:08:34.208955 TX Vref=16, minBit 0, minWin=23, winSum=381
8926 11:08:34.211731 TX Vref=18, minBit 0, minWin=24, winSum=390
8927 11:08:34.215879 TX Vref=20, minBit 0, minWin=24, winSum=406
8928 11:08:34.218459 TX Vref=22, minBit 0, minWin=24, winSum=410
8929 11:08:34.221859 TX Vref=24, minBit 0, minWin=25, winSum=421
8930 11:08:34.228960 TX Vref=26, minBit 0, minWin=26, winSum=426
8931 11:08:34.231644 TX Vref=28, minBit 0, minWin=25, winSum=425
8932 11:08:34.235127 TX Vref=30, minBit 1, minWin=25, winSum=418
8933 11:08:34.238486 TX Vref=32, minBit 0, minWin=24, winSum=411
8934 11:08:34.242354 TX Vref=34, minBit 0, minWin=24, winSum=402
8935 11:08:34.248991 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 26
8936 11:08:34.249085
8937 11:08:34.252055 Final TX Range 0 Vref 26
8938 11:08:34.252165
8939 11:08:34.252258 ==
8940 11:08:34.255405 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 11:08:34.258724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 11:08:34.258808 ==
8943 11:08:34.258873
8944 11:08:34.258932
8945 11:08:34.262035 TX Vref Scan disable
8946 11:08:34.268616 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8947 11:08:34.268699 == TX Byte 0 ==
8948 11:08:34.272192 u2DelayCellOfst[0]=17 cells (5 PI)
8949 11:08:34.275332 u2DelayCellOfst[1]=10 cells (3 PI)
8950 11:08:34.278665 u2DelayCellOfst[2]=0 cells (0 PI)
8951 11:08:34.281950 u2DelayCellOfst[3]=6 cells (2 PI)
8952 11:08:34.285159 u2DelayCellOfst[4]=6 cells (2 PI)
8953 11:08:34.288589 u2DelayCellOfst[5]=17 cells (5 PI)
8954 11:08:34.291877 u2DelayCellOfst[6]=17 cells (5 PI)
8955 11:08:34.291990 u2DelayCellOfst[7]=6 cells (2 PI)
8956 11:08:34.298554 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8957 11:08:34.301732 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8958 11:08:34.301815 == TX Byte 1 ==
8959 11:08:34.305002 u2DelayCellOfst[8]=0 cells (0 PI)
8960 11:08:34.308263 u2DelayCellOfst[9]=3 cells (1 PI)
8961 11:08:34.311512 u2DelayCellOfst[10]=10 cells (3 PI)
8962 11:08:34.314543 u2DelayCellOfst[11]=3 cells (1 PI)
8963 11:08:34.318280 u2DelayCellOfst[12]=13 cells (4 PI)
8964 11:08:34.321585 u2DelayCellOfst[13]=17 cells (5 PI)
8965 11:08:34.324672 u2DelayCellOfst[14]=17 cells (5 PI)
8966 11:08:34.327869 u2DelayCellOfst[15]=17 cells (5 PI)
8967 11:08:34.331085 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8968 11:08:34.338299 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8969 11:08:34.338382 DramC Write-DBI on
8970 11:08:34.338447 ==
8971 11:08:34.341652 Dram Type= 6, Freq= 0, CH_1, rank 1
8972 11:08:34.345000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8973 11:08:34.348086 ==
8974 11:08:34.348194
8975 11:08:34.348294
8976 11:08:34.348359 TX Vref Scan disable
8977 11:08:34.351330 == TX Byte 0 ==
8978 11:08:34.354679 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8979 11:08:34.358140 == TX Byte 1 ==
8980 11:08:34.361393 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8981 11:08:34.364373 DramC Write-DBI off
8982 11:08:34.364483
8983 11:08:34.364582 [DATLAT]
8984 11:08:34.364676 Freq=1600, CH1 RK1
8985 11:08:34.364769
8986 11:08:34.368277 DATLAT Default: 0xf
8987 11:08:34.368375 0, 0xFFFF, sum = 0
8988 11:08:34.371557 1, 0xFFFF, sum = 0
8989 11:08:34.371652 2, 0xFFFF, sum = 0
8990 11:08:34.374681 3, 0xFFFF, sum = 0
8991 11:08:34.377750 4, 0xFFFF, sum = 0
8992 11:08:34.377876 5, 0xFFFF, sum = 0
8993 11:08:34.381244 6, 0xFFFF, sum = 0
8994 11:08:34.381329 7, 0xFFFF, sum = 0
8995 11:08:34.384507 8, 0xFFFF, sum = 0
8996 11:08:34.384620 9, 0xFFFF, sum = 0
8997 11:08:34.387900 10, 0xFFFF, sum = 0
8998 11:08:34.387982 11, 0xFFFF, sum = 0
8999 11:08:34.391331 12, 0xFFFF, sum = 0
9000 11:08:34.391421 13, 0xFFFF, sum = 0
9001 11:08:34.394401 14, 0x0, sum = 1
9002 11:08:34.394509 15, 0x0, sum = 2
9003 11:08:34.397953 16, 0x0, sum = 3
9004 11:08:34.398038 17, 0x0, sum = 4
9005 11:08:34.401003 best_step = 15
9006 11:08:34.401136
9007 11:08:34.401213 ==
9008 11:08:34.404990 Dram Type= 6, Freq= 0, CH_1, rank 1
9009 11:08:34.408183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9010 11:08:34.408296 ==
9011 11:08:34.408404 RX Vref Scan: 0
9012 11:08:34.408491
9013 11:08:34.411562 RX Vref 0 -> 0, step: 1
9014 11:08:34.411676
9015 11:08:34.414957 RX Delay 19 -> 252, step: 4
9016 11:08:34.418447 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9017 11:08:34.424387 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9018 11:08:34.428041 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9019 11:08:34.431277 iDelay=195, Bit 3, Center 128 (79 ~ 178) 100
9020 11:08:34.434860 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9021 11:08:34.438104 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9022 11:08:34.440860 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9023 11:08:34.447581 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9024 11:08:34.450867 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9025 11:08:34.454140 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
9026 11:08:34.457451 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9027 11:08:34.461395 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9028 11:08:34.468175 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9029 11:08:34.470928 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9030 11:08:34.474277 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9031 11:08:34.477715 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9032 11:08:34.477804 ==
9033 11:08:34.481257 Dram Type= 6, Freq= 0, CH_1, rank 1
9034 11:08:34.488085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9035 11:08:34.488202 ==
9036 11:08:34.488304 DQS Delay:
9037 11:08:34.491395 DQS0 = 0, DQS1 = 0
9038 11:08:34.491510 DQM Delay:
9039 11:08:34.494503 DQM0 = 133, DQM1 = 131
9040 11:08:34.494630 DQ Delay:
9041 11:08:34.497701 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =128
9042 11:08:34.500714 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9043 11:08:34.504047 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =126
9044 11:08:34.507464 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9045 11:08:34.507544
9046 11:08:34.507612
9047 11:08:34.507698
9048 11:08:34.510806 [DramC_TX_OE_Calibration] TA2
9049 11:08:34.514446 Original DQ_B0 (3 6) =30, OEN = 27
9050 11:08:34.517743 Original DQ_B1 (3 6) =30, OEN = 27
9051 11:08:34.521255 24, 0x0, End_B0=24 End_B1=24
9052 11:08:34.521371 25, 0x0, End_B0=25 End_B1=25
9053 11:08:34.524193 26, 0x0, End_B0=26 End_B1=26
9054 11:08:34.527889 27, 0x0, End_B0=27 End_B1=27
9055 11:08:34.531166 28, 0x0, End_B0=28 End_B1=28
9056 11:08:34.534189 29, 0x0, End_B0=29 End_B1=29
9057 11:08:34.534302 30, 0x0, End_B0=30 End_B1=30
9058 11:08:34.537752 31, 0x4141, End_B0=30 End_B1=30
9059 11:08:34.540874 Byte0 end_step=30 best_step=27
9060 11:08:34.544025 Byte1 end_step=30 best_step=27
9061 11:08:34.547273 Byte0 TX OE(2T, 0.5T) = (3, 3)
9062 11:08:34.551296 Byte1 TX OE(2T, 0.5T) = (3, 3)
9063 11:08:34.551404
9064 11:08:34.551497
9065 11:08:34.557377 [DQSOSCAuto] RK1, (LSB)MR18= 0x2308, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9066 11:08:34.560932 CH1 RK1: MR19=303, MR18=2308
9067 11:08:34.567474 CH1_RK1: MR19=0x303, MR18=0x2308, DQSOSC=392, MR23=63, INC=24, DEC=16
9068 11:08:34.570781 [RxdqsGatingPostProcess] freq 1600
9069 11:08:34.574299 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9070 11:08:34.577522 best DQS0 dly(2T, 0.5T) = (1, 1)
9071 11:08:34.580750 best DQS1 dly(2T, 0.5T) = (1, 1)
9072 11:08:34.583994 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9073 11:08:34.587343 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9074 11:08:34.590550 best DQS0 dly(2T, 0.5T) = (1, 1)
9075 11:08:34.593869 best DQS1 dly(2T, 0.5T) = (1, 1)
9076 11:08:34.597185 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9077 11:08:34.600485 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9078 11:08:34.603768 Pre-setting of DQS Precalculation
9079 11:08:34.607016 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9080 11:08:34.614133 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9081 11:08:34.623933 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9082 11:08:34.624024
9083 11:08:34.624090
9084 11:08:34.624152 [Calibration Summary] 3200 Mbps
9085 11:08:34.627338 CH 0, Rank 0
9086 11:08:34.630487 SW Impedance : PASS
9087 11:08:34.630572 DUTY Scan : NO K
9088 11:08:34.633951 ZQ Calibration : PASS
9089 11:08:34.634036 Jitter Meter : NO K
9090 11:08:34.637292 CBT Training : PASS
9091 11:08:34.640687 Write leveling : PASS
9092 11:08:34.640772 RX DQS gating : PASS
9093 11:08:34.643958 RX DQ/DQS(RDDQC) : PASS
9094 11:08:34.647274 TX DQ/DQS : PASS
9095 11:08:34.647359 RX DATLAT : PASS
9096 11:08:34.650764 RX DQ/DQS(Engine): PASS
9097 11:08:34.653732 TX OE : PASS
9098 11:08:34.653848 All Pass.
9099 11:08:34.653950
9100 11:08:34.654043 CH 0, Rank 1
9101 11:08:34.657048 SW Impedance : PASS
9102 11:08:34.660537 DUTY Scan : NO K
9103 11:08:34.660621 ZQ Calibration : PASS
9104 11:08:34.663833 Jitter Meter : NO K
9105 11:08:34.663917 CBT Training : PASS
9106 11:08:34.667096 Write leveling : PASS
9107 11:08:34.670763 RX DQS gating : PASS
9108 11:08:34.670847 RX DQ/DQS(RDDQC) : PASS
9109 11:08:34.673842 TX DQ/DQS : PASS
9110 11:08:34.677601 RX DATLAT : PASS
9111 11:08:34.677683 RX DQ/DQS(Engine): PASS
9112 11:08:34.680873 TX OE : PASS
9113 11:08:34.680981 All Pass.
9114 11:08:34.681083
9115 11:08:34.684177 CH 1, Rank 0
9116 11:08:34.684313 SW Impedance : PASS
9117 11:08:34.686995 DUTY Scan : NO K
9118 11:08:34.690360 ZQ Calibration : PASS
9119 11:08:34.690442 Jitter Meter : NO K
9120 11:08:34.694223 CBT Training : PASS
9121 11:08:34.697512 Write leveling : PASS
9122 11:08:34.697594 RX DQS gating : PASS
9123 11:08:34.700747 RX DQ/DQS(RDDQC) : PASS
9124 11:08:34.704119 TX DQ/DQS : PASS
9125 11:08:34.704228 RX DATLAT : PASS
9126 11:08:34.707378 RX DQ/DQS(Engine): PASS
9127 11:08:34.710714 TX OE : PASS
9128 11:08:34.710797 All Pass.
9129 11:08:34.710863
9130 11:08:34.710923 CH 1, Rank 1
9131 11:08:34.713516 SW Impedance : PASS
9132 11:08:34.716883 DUTY Scan : NO K
9133 11:08:34.716990 ZQ Calibration : PASS
9134 11:08:34.720264 Jitter Meter : NO K
9135 11:08:34.723582 CBT Training : PASS
9136 11:08:34.723682 Write leveling : PASS
9137 11:08:34.726645 RX DQS gating : PASS
9138 11:08:34.726728 RX DQ/DQS(RDDQC) : PASS
9139 11:08:34.730240 TX DQ/DQS : PASS
9140 11:08:34.733754 RX DATLAT : PASS
9141 11:08:34.733836 RX DQ/DQS(Engine): PASS
9142 11:08:34.736982 TX OE : PASS
9143 11:08:34.737064 All Pass.
9144 11:08:34.737129
9145 11:08:34.740294 DramC Write-DBI on
9146 11:08:34.743730 PER_BANK_REFRESH: Hybrid Mode
9147 11:08:34.743812 TX_TRACKING: ON
9148 11:08:34.753462 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9149 11:08:34.760553 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9150 11:08:34.766863 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9151 11:08:34.770747 [FAST_K] Save calibration result to emmc
9152 11:08:34.773619 sync common calibartion params.
9153 11:08:34.777240 sync cbt_mode0:1, 1:1
9154 11:08:34.780413 dram_init: ddr_geometry: 2
9155 11:08:34.780495 dram_init: ddr_geometry: 2
9156 11:08:34.783724 dram_init: ddr_geometry: 2
9157 11:08:34.786963 0:dram_rank_size:100000000
9158 11:08:34.790133 1:dram_rank_size:100000000
9159 11:08:34.793846 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9160 11:08:34.797025 DFS_SHUFFLE_HW_MODE: ON
9161 11:08:34.800419 dramc_set_vcore_voltage set vcore to 725000
9162 11:08:34.803693 Read voltage for 1600, 0
9163 11:08:34.803775 Vio18 = 0
9164 11:08:34.803840 Vcore = 725000
9165 11:08:34.806859 Vdram = 0
9166 11:08:34.806941 Vddq = 0
9167 11:08:34.807006 Vmddr = 0
9168 11:08:34.810131 switch to 3200 Mbps bootup
9169 11:08:34.813428 [DramcRunTimeConfig]
9170 11:08:34.813509 PHYPLL
9171 11:08:34.813572 DPM_CONTROL_AFTERK: ON
9172 11:08:34.816711 PER_BANK_REFRESH: ON
9173 11:08:34.820016 REFRESH_OVERHEAD_REDUCTION: ON
9174 11:08:34.820096 CMD_PICG_NEW_MODE: OFF
9175 11:08:34.823425 XRTWTW_NEW_MODE: ON
9176 11:08:34.826645 XRTRTR_NEW_MODE: ON
9177 11:08:34.826725 TX_TRACKING: ON
9178 11:08:34.826789 RDSEL_TRACKING: OFF
9179 11:08:34.829989 DQS Precalculation for DVFS: ON
9180 11:08:34.833198 RX_TRACKING: OFF
9181 11:08:34.833278 HW_GATING DBG: ON
9182 11:08:34.837003 ZQCS_ENABLE_LP4: ON
9183 11:08:34.837084 RX_PICG_NEW_MODE: ON
9184 11:08:34.840018 TX_PICG_NEW_MODE: ON
9185 11:08:34.843252 ENABLE_RX_DCM_DPHY: ON
9186 11:08:34.847088 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9187 11:08:34.847168 DUMMY_READ_FOR_TRACKING: OFF
9188 11:08:34.850418 !!! SPM_CONTROL_AFTERK: OFF
9189 11:08:34.853691 !!! SPM could not control APHY
9190 11:08:34.857321 IMPEDANCE_TRACKING: ON
9191 11:08:34.857401 TEMP_SENSOR: ON
9192 11:08:34.859840 HW_SAVE_FOR_SR: OFF
9193 11:08:34.859921 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9194 11:08:34.866789 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9195 11:08:34.866869 Read ODT Tracking: ON
9196 11:08:34.870072 Refresh Rate DeBounce: ON
9197 11:08:34.870153 DFS_NO_QUEUE_FLUSH: ON
9198 11:08:34.873297 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9199 11:08:34.876640 ENABLE_DFS_RUNTIME_MRW: OFF
9200 11:08:34.879946 DDR_RESERVE_NEW_MODE: ON
9201 11:08:34.880026 MR_CBT_SWITCH_FREQ: ON
9202 11:08:34.883344 =========================
9203 11:08:34.902515 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9204 11:08:34.905966 dram_init: ddr_geometry: 2
9205 11:08:34.924048 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9206 11:08:34.927386 dram_init: dram init end (result: 0)
9207 11:08:34.934000 DRAM-K: Full calibration passed in 24460 msecs
9208 11:08:34.937178 MRC: failed to locate region type 0.
9209 11:08:34.937260 DRAM rank0 size:0x100000000,
9210 11:08:34.940552 DRAM rank1 size=0x100000000
9211 11:08:34.950689 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9212 11:08:34.957592 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9213 11:08:34.964143 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9214 11:08:34.970987 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9215 11:08:34.973679 DRAM rank0 size:0x100000000,
9216 11:08:34.977527 DRAM rank1 size=0x100000000
9217 11:08:34.977610 CBMEM:
9218 11:08:34.980769 IMD: root @ 0xfffff000 254 entries.
9219 11:08:34.983974 IMD: root @ 0xffffec00 62 entries.
9220 11:08:34.987188 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9221 11:08:34.990478 WARNING: RO_VPD is uninitialized or empty.
9222 11:08:34.997025 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9223 11:08:35.004408 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9224 11:08:35.016652 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9225 11:08:35.028644 BS: romstage times (exec / console): total (unknown) / 23994 ms
9226 11:08:35.028754
9227 11:08:35.028847
9228 11:08:35.038699 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9229 11:08:35.041879 ARM64: Exception handlers installed.
9230 11:08:35.045091 ARM64: Testing exception
9231 11:08:35.048229 ARM64: Done test exception
9232 11:08:35.048356 Enumerating buses...
9233 11:08:35.051465 Show all devs... Before device enumeration.
9234 11:08:35.054755 Root Device: enabled 1
9235 11:08:35.058555 CPU_CLUSTER: 0: enabled 1
9236 11:08:35.058638 CPU: 00: enabled 1
9237 11:08:35.061555 Compare with tree...
9238 11:08:35.061665 Root Device: enabled 1
9239 11:08:35.064924 CPU_CLUSTER: 0: enabled 1
9240 11:08:35.068237 CPU: 00: enabled 1
9241 11:08:35.068373 Root Device scanning...
9242 11:08:35.071458 scan_static_bus for Root Device
9243 11:08:35.074707 CPU_CLUSTER: 0 enabled
9244 11:08:35.078355 scan_static_bus for Root Device done
9245 11:08:35.081333 scan_bus: bus Root Device finished in 8 msecs
9246 11:08:35.081416 done
9247 11:08:35.087956 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9248 11:08:35.091478 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9249 11:08:35.098395 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9250 11:08:35.101702 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9251 11:08:35.105026 Allocating resources...
9252 11:08:35.108402 Reading resources...
9253 11:08:35.111713 Root Device read_resources bus 0 link: 0
9254 11:08:35.111793 DRAM rank0 size:0x100000000,
9255 11:08:35.114869 DRAM rank1 size=0x100000000
9256 11:08:35.117968 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9257 11:08:35.121315 CPU: 00 missing read_resources
9258 11:08:35.124674 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9259 11:08:35.131221 Root Device read_resources bus 0 link: 0 done
9260 11:08:35.131302 Done reading resources.
9261 11:08:35.138203 Show resources in subtree (Root Device)...After reading.
9262 11:08:35.141248 Root Device child on link 0 CPU_CLUSTER: 0
9263 11:08:35.144669 CPU_CLUSTER: 0 child on link 0 CPU: 00
9264 11:08:35.154446 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9265 11:08:35.154532 CPU: 00
9266 11:08:35.157695 Root Device assign_resources, bus 0 link: 0
9267 11:08:35.160908 CPU_CLUSTER: 0 missing set_resources
9268 11:08:35.164664 Root Device assign_resources, bus 0 link: 0 done
9269 11:08:35.167689 Done setting resources.
9270 11:08:35.174755 Show resources in subtree (Root Device)...After assigning values.
9271 11:08:35.178280 Root Device child on link 0 CPU_CLUSTER: 0
9272 11:08:35.180970 CPU_CLUSTER: 0 child on link 0 CPU: 00
9273 11:08:35.191074 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9274 11:08:35.191163 CPU: 00
9275 11:08:35.194380 Done allocating resources.
9276 11:08:35.197823 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9277 11:08:35.201343 Enabling resources...
9278 11:08:35.201428 done.
9279 11:08:35.207819 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9280 11:08:35.207958 Initializing devices...
9281 11:08:35.211187 Root Device init
9282 11:08:35.211273 init hardware done!
9283 11:08:35.214686 0x00000018: ctrlr->caps
9284 11:08:35.217851 52.000 MHz: ctrlr->f_max
9285 11:08:35.217996 0.400 MHz: ctrlr->f_min
9286 11:08:35.221220 0x40ff8080: ctrlr->voltages
9287 11:08:35.221303 sclk: 390625
9288 11:08:35.224525 Bus Width = 1
9289 11:08:35.224618 sclk: 390625
9290 11:08:35.224684 Bus Width = 1
9291 11:08:35.227962 Early init status = 3
9292 11:08:35.234767 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9293 11:08:35.237589 in-header: 03 fc 00 00 01 00 00 00
9294 11:08:35.237717 in-data: 00
9295 11:08:35.244560 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9296 11:08:35.248011 in-header: 03 fd 00 00 00 00 00 00
9297 11:08:35.250860 in-data:
9298 11:08:35.254086 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9299 11:08:35.257537 in-header: 03 fc 00 00 01 00 00 00
9300 11:08:35.260772 in-data: 00
9301 11:08:35.264330 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9302 11:08:35.268560 in-header: 03 fd 00 00 00 00 00 00
9303 11:08:35.271543 in-data:
9304 11:08:35.275025 [SSUSB] Setting up USB HOST controller...
9305 11:08:35.278255 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9306 11:08:35.281649 [SSUSB] phy power-on done.
9307 11:08:35.285182 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9308 11:08:35.291950 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9309 11:08:35.295275 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9310 11:08:35.302217 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9311 11:08:35.308695 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9312 11:08:35.315215 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9313 11:08:35.321500 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9314 11:08:35.328089 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9315 11:08:35.331732 SPM: binary array size = 0x9dc
9316 11:08:35.335216 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9317 11:08:35.341505 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9318 11:08:35.348372 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9319 11:08:35.351861 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9320 11:08:35.358160 configure_display: Starting display init
9321 11:08:35.391977 anx7625_power_on_init: Init interface.
9322 11:08:35.395261 anx7625_disable_pd_protocol: Disabled PD feature.
9323 11:08:35.398358 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9324 11:08:35.426031 anx7625_start_dp_work: Secure OCM version=00
9325 11:08:35.429398 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9326 11:08:35.444176 sp_tx_get_edid_block: EDID Block = 1
9327 11:08:35.546838 Extracted contents:
9328 11:08:35.549810 header: 00 ff ff ff ff ff ff 00
9329 11:08:35.553401 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9330 11:08:35.557005 version: 01 04
9331 11:08:35.560170 basic params: 95 1f 11 78 0a
9332 11:08:35.563590 chroma info: 76 90 94 55 54 90 27 21 50 54
9333 11:08:35.566724 established: 00 00 00
9334 11:08:35.573748 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9335 11:08:35.576329 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9336 11:08:35.583133 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9337 11:08:35.590238 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9338 11:08:35.596969 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9339 11:08:35.600209 extensions: 00
9340 11:08:35.600342 checksum: fb
9341 11:08:35.600457
9342 11:08:35.603439 Manufacturer: IVO Model 57d Serial Number 0
9343 11:08:35.606867 Made week 0 of 2020
9344 11:08:35.606991 EDID version: 1.4
9345 11:08:35.609553 Digital display
9346 11:08:35.613406 6 bits per primary color channel
9347 11:08:35.613533 DisplayPort interface
9348 11:08:35.616696 Maximum image size: 31 cm x 17 cm
9349 11:08:35.620121 Gamma: 220%
9350 11:08:35.620248 Check DPMS levels
9351 11:08:35.623243 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9352 11:08:35.626702 First detailed timing is preferred timing
9353 11:08:35.629949 Established timings supported:
9354 11:08:35.633467 Standard timings supported:
9355 11:08:35.636121 Detailed timings
9356 11:08:35.639650 Hex of detail: 383680a07038204018303c0035ae10000019
9357 11:08:35.642981 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9358 11:08:35.649529 0780 0798 07c8 0820 hborder 0
9359 11:08:35.652783 0438 043b 0447 0458 vborder 0
9360 11:08:35.656228 -hsync -vsync
9361 11:08:35.656339 Did detailed timing
9362 11:08:35.662915 Hex of detail: 000000000000000000000000000000000000
9363 11:08:35.662999 Manufacturer-specified data, tag 0
9364 11:08:35.669738 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9365 11:08:35.672579 ASCII string: InfoVision
9366 11:08:35.676136 Hex of detail: 000000fe00523134304e574635205248200a
9367 11:08:35.679320 ASCII string: R140NWF5 RH
9368 11:08:35.679403 Checksum
9369 11:08:35.682889 Checksum: 0xfb (valid)
9370 11:08:35.686054 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9371 11:08:35.689314 DSI data_rate: 832800000 bps
9372 11:08:35.696394 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9373 11:08:35.699080 anx7625_parse_edid: pixelclock(138800).
9374 11:08:35.703023 hactive(1920), hsync(48), hfp(24), hbp(88)
9375 11:08:35.706341 vactive(1080), vsync(12), vfp(3), vbp(17)
9376 11:08:35.709271 anx7625_dsi_config: config dsi.
9377 11:08:35.715756 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9378 11:08:35.729124 anx7625_dsi_config: success to config DSI
9379 11:08:35.732492 anx7625_dp_start: MIPI phy setup OK.
9380 11:08:35.735206 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9381 11:08:35.738366 mtk_ddp_mode_set invalid vrefresh 60
9382 11:08:35.741848 main_disp_path_setup
9383 11:08:35.741932 ovl_layer_smi_id_en
9384 11:08:35.745217 ovl_layer_smi_id_en
9385 11:08:35.745337 ccorr_config
9386 11:08:35.745408 aal_config
9387 11:08:35.748615 gamma_config
9388 11:08:35.748719 postmask_config
9389 11:08:35.751877 dither_config
9390 11:08:35.755153 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9391 11:08:35.762240 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9392 11:08:35.765522 Root Device init finished in 551 msecs
9393 11:08:35.768223 CPU_CLUSTER: 0 init
9394 11:08:35.774986 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9395 11:08:35.782180 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9396 11:08:35.782265 APU_MBOX 0x190000b0 = 0x10001
9397 11:08:35.785630 APU_MBOX 0x190001b0 = 0x10001
9398 11:08:35.788168 APU_MBOX 0x190005b0 = 0x10001
9399 11:08:35.791521 APU_MBOX 0x190006b0 = 0x10001
9400 11:08:35.798467 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9401 11:08:35.808039 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9402 11:08:35.820374 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9403 11:08:35.826973 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9404 11:08:35.838403 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9405 11:08:35.847646 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9406 11:08:35.850843 CPU_CLUSTER: 0 init finished in 81 msecs
9407 11:08:35.854221 Devices initialized
9408 11:08:35.857660 Show all devs... After init.
9409 11:08:35.857743 Root Device: enabled 1
9410 11:08:35.860948 CPU_CLUSTER: 0: enabled 1
9411 11:08:35.864292 CPU: 00: enabled 1
9412 11:08:35.867538 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9413 11:08:35.870975 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9414 11:08:35.874500 ELOG: NV offset 0x57f000 size 0x1000
9415 11:08:35.881312 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9416 11:08:35.887407 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9417 11:08:35.890923 ELOG: Event(17) added with size 13 at 2024-03-03 11:05:48 UTC
9418 11:08:35.894298 out: cmd=0x121: 03 db 21 01 00 00 00 00
9419 11:08:35.898292 in-header: 03 dc 00 00 2c 00 00 00
9420 11:08:35.911640 in-data: 83 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9421 11:08:35.918129 ELOG: Event(A1) added with size 10 at 2024-03-03 11:05:48 UTC
9422 11:08:35.924666 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9423 11:08:35.931460 ELOG: Event(A0) added with size 9 at 2024-03-03 11:05:48 UTC
9424 11:08:35.934328 elog_add_boot_reason: Logged dev mode boot
9425 11:08:35.937748 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9426 11:08:35.941223 Finalize devices...
9427 11:08:35.941338 Devices finalized
9428 11:08:35.947860 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9429 11:08:35.950927 Writing coreboot table at 0xffe64000
9430 11:08:35.954348 0. 000000000010a000-0000000000113fff: RAMSTAGE
9431 11:08:35.957461 1. 0000000040000000-00000000400fffff: RAM
9432 11:08:35.960922 2. 0000000040100000-000000004032afff: RAMSTAGE
9433 11:08:35.967572 3. 000000004032b000-00000000545fffff: RAM
9434 11:08:35.971402 4. 0000000054600000-000000005465ffff: BL31
9435 11:08:35.974158 5. 0000000054660000-00000000ffe63fff: RAM
9436 11:08:35.977595 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9437 11:08:35.984423 7. 0000000100000000-000000023fffffff: RAM
9438 11:08:35.984548 Passing 5 GPIOs to payload:
9439 11:08:35.991233 NAME | PORT | POLARITY | VALUE
9440 11:08:35.994082 EC in RW | 0x000000aa | low | undefined
9441 11:08:36.001083 EC interrupt | 0x00000005 | low | undefined
9442 11:08:36.004306 TPM interrupt | 0x000000ab | high | undefined
9443 11:08:36.007857 SD card detect | 0x00000011 | high | undefined
9444 11:08:36.013934 speaker enable | 0x00000093 | high | undefined
9445 11:08:36.017533 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9446 11:08:36.021046 in-header: 03 f9 00 00 02 00 00 00
9447 11:08:36.021176 in-data: 02 00
9448 11:08:36.024364 ADC[4]: Raw value=904726 ID=7
9449 11:08:36.027168 ADC[3]: Raw value=213441 ID=1
9450 11:08:36.027252 RAM Code: 0x71
9451 11:08:36.030670 ADC[6]: Raw value=75332 ID=0
9452 11:08:36.033917 ADC[5]: Raw value=213072 ID=1
9453 11:08:36.034002 SKU Code: 0x1
9454 11:08:36.040922 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 8707
9455 11:08:36.044159 coreboot table: 964 bytes.
9456 11:08:36.047325 IMD ROOT 0. 0xfffff000 0x00001000
9457 11:08:36.051152 IMD SMALL 1. 0xffffe000 0x00001000
9458 11:08:36.054269 RO MCACHE 2. 0xffffc000 0x00001104
9459 11:08:36.057729 CONSOLE 3. 0xfff7c000 0x00080000
9460 11:08:36.060869 FMAP 4. 0xfff7b000 0x00000452
9461 11:08:36.064302 TIME STAMP 5. 0xfff7a000 0x00000910
9462 11:08:36.067968 VBOOT WORK 6. 0xfff66000 0x00014000
9463 11:08:36.070485 RAMOOPS 7. 0xffe66000 0x00100000
9464 11:08:36.074200 COREBOOT 8. 0xffe64000 0x00002000
9465 11:08:36.074287 IMD small region:
9466 11:08:36.077271 IMD ROOT 0. 0xffffec00 0x00000400
9467 11:08:36.080616 VPD 1. 0xffffeb80 0x0000006c
9468 11:08:36.083874 MMC STATUS 2. 0xffffeb60 0x00000004
9469 11:08:36.091396 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9470 11:08:36.091484 Probing TPM: done!
9471 11:08:36.097982 Connected to device vid:did:rid of 1ae0:0028:00
9472 11:08:36.104138 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9473 11:08:36.111540 Initialized TPM device CR50 revision 0
9474 11:08:36.111625 Checking cr50 for pending updates
9475 11:08:36.117225 Reading cr50 TPM mode
9476 11:08:36.126243 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9477 11:08:36.132371 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9478 11:08:36.172454 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9479 11:08:36.176273 Checking segment from ROM address 0x40100000
9480 11:08:36.179393 Checking segment from ROM address 0x4010001c
9481 11:08:36.186101 Loading segment from ROM address 0x40100000
9482 11:08:36.186188 code (compression=0)
9483 11:08:36.196447 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9484 11:08:36.202745 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9485 11:08:36.202858 it's not compressed!
9486 11:08:36.209372 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9487 11:08:36.212794 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9488 11:08:36.233554 Loading segment from ROM address 0x4010001c
9489 11:08:36.233679 Entry Point 0x80000000
9490 11:08:36.236323 Loaded segments
9491 11:08:36.239705 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9492 11:08:36.246570 Jumping to boot code at 0x80000000(0xffe64000)
9493 11:08:36.253123 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9494 11:08:36.259884 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9495 11:08:36.267349 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9496 11:08:36.270688 Checking segment from ROM address 0x40100000
9497 11:08:36.274184 Checking segment from ROM address 0x4010001c
9498 11:08:36.280951 Loading segment from ROM address 0x40100000
9499 11:08:36.281039 code (compression=1)
9500 11:08:36.287387 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9501 11:08:36.297425 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9502 11:08:36.297517 using LZMA
9503 11:08:36.305724 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9504 11:08:36.312586 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9505 11:08:36.315796 Loading segment from ROM address 0x4010001c
9506 11:08:36.315874 Entry Point 0x54601000
9507 11:08:36.319642 Loaded segments
9508 11:08:36.322773 NOTICE: MT8192 bl31_setup
9509 11:08:36.329335 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9510 11:08:36.333160 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9511 11:08:36.335923 WARNING: region 0:
9512 11:08:36.339280 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 11:08:36.339386 WARNING: region 1:
9514 11:08:36.346301 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9515 11:08:36.349527 WARNING: region 2:
9516 11:08:36.352531 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9517 11:08:36.356221 WARNING: region 3:
9518 11:08:36.359311 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9519 11:08:36.362700 WARNING: region 4:
9520 11:08:36.369556 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9521 11:08:36.369686 WARNING: region 5:
9522 11:08:36.372797 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 11:08:36.376272 WARNING: region 6:
9524 11:08:36.379781 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9525 11:08:36.382567 WARNING: region 7:
9526 11:08:36.385936 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 11:08:36.392694 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9528 11:08:36.395923 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9529 11:08:36.399637 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9530 11:08:36.406438 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9531 11:08:36.409205 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9532 11:08:36.413251 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9533 11:08:36.419372 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9534 11:08:36.422727 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9535 11:08:36.429358 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9536 11:08:36.432689 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9537 11:08:36.436203 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9538 11:08:36.442501 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9539 11:08:36.446197 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9540 11:08:36.449338 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9541 11:08:36.456238 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9542 11:08:36.459206 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9543 11:08:36.466061 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9544 11:08:36.469181 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9545 11:08:36.472822 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9546 11:08:36.479341 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9547 11:08:36.482773 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9548 11:08:36.486294 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9549 11:08:36.492570 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9550 11:08:36.495961 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9551 11:08:36.502789 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9552 11:08:36.505933 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9553 11:08:36.509211 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9554 11:08:36.515928 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9555 11:08:36.519612 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9556 11:08:36.522927 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9557 11:08:36.529612 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9558 11:08:36.532968 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9559 11:08:36.536331 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9560 11:08:36.542989 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9561 11:08:36.546272 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9562 11:08:36.549535 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9563 11:08:36.552913 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9564 11:08:36.559689 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9565 11:08:36.563288 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9566 11:08:36.566518 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9567 11:08:36.569884 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9568 11:08:36.576733 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9569 11:08:36.579722 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9570 11:08:36.582828 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9571 11:08:36.586318 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9572 11:08:36.592663 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9573 11:08:36.595964 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9574 11:08:36.599816 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9575 11:08:36.606057 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9576 11:08:36.609529 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9577 11:08:36.616122 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9578 11:08:36.619337 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9579 11:08:36.623105 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9580 11:08:36.629370 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9581 11:08:36.633206 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9582 11:08:36.639938 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9583 11:08:36.643351 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9584 11:08:36.646037 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9585 11:08:36.652836 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9586 11:08:36.656136 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9587 11:08:36.662979 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9588 11:08:36.666190 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9589 11:08:36.672915 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9590 11:08:36.676469 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9591 11:08:36.683208 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9592 11:08:36.686057 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9593 11:08:36.689398 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9594 11:08:36.695881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9595 11:08:36.699291 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9596 11:08:36.706151 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9597 11:08:36.709616 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9598 11:08:36.716103 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9599 11:08:36.719410 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9600 11:08:36.722723 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9601 11:08:36.729893 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9602 11:08:36.733113 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9603 11:08:36.739670 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9604 11:08:36.742877 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9605 11:08:36.749758 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9606 11:08:36.753006 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9607 11:08:36.756436 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9608 11:08:36.763171 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9609 11:08:36.766503 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9610 11:08:36.773296 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9611 11:08:36.776721 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9612 11:08:36.782942 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9613 11:08:36.786348 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9614 11:08:36.789685 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9615 11:08:36.796420 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9616 11:08:36.800456 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9617 11:08:36.806646 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9618 11:08:36.810039 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9619 11:08:36.816677 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9620 11:08:36.819874 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9621 11:08:36.823423 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9622 11:08:36.829951 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9623 11:08:36.833322 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9624 11:08:36.836680 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9625 11:08:36.843377 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9626 11:08:36.846493 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9627 11:08:36.849874 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9628 11:08:36.853205 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9629 11:08:36.860385 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9630 11:08:36.863642 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9631 11:08:36.870290 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9632 11:08:36.873546 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9633 11:08:36.877033 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9634 11:08:36.883211 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9635 11:08:36.886508 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9636 11:08:36.893266 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9637 11:08:36.896771 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9638 11:08:36.900188 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9639 11:08:36.906501 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9640 11:08:36.909821 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9641 11:08:36.917077 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9642 11:08:36.920241 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9643 11:08:36.923525 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9644 11:08:36.930222 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9645 11:08:36.933324 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9646 11:08:36.936749 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9647 11:08:36.940197 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9648 11:08:36.946639 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9649 11:08:36.950288 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9650 11:08:36.953197 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9651 11:08:36.956745 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9652 11:08:36.963569 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9653 11:08:36.966825 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9654 11:08:36.973856 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9655 11:08:36.976776 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9656 11:08:36.980565 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9657 11:08:36.986865 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9658 11:08:36.990303 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9659 11:08:36.993990 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9660 11:08:37.000618 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9661 11:08:37.003936 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9662 11:08:37.010491 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9663 11:08:37.013781 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9664 11:08:37.017251 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9665 11:08:37.024145 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9666 11:08:37.027620 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9667 11:08:37.030933 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9668 11:08:37.037574 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9669 11:08:37.040889 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9670 11:08:37.047074 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9671 11:08:37.050417 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9672 11:08:37.053833 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9673 11:08:37.060474 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9674 11:08:37.063733 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9675 11:08:37.070855 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9676 11:08:37.074327 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9677 11:08:37.077647 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9678 11:08:37.084212 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9679 11:08:37.087115 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9680 11:08:37.090648 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9681 11:08:37.097677 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9682 11:08:37.100804 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9683 11:08:37.107361 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9684 11:08:37.110701 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9685 11:08:37.113833 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9686 11:08:37.120865 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9687 11:08:37.123986 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9688 11:08:37.130819 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9689 11:08:37.134334 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9690 11:08:37.137494 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9691 11:08:37.143987 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9692 11:08:37.146970 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9693 11:08:37.150285 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9694 11:08:37.157069 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9695 11:08:37.160456 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9696 11:08:37.167234 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9697 11:08:37.170364 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9698 11:08:37.176923 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9699 11:08:37.180327 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9700 11:08:37.183896 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9701 11:08:37.190548 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9702 11:08:37.193792 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9703 11:08:37.196955 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9704 11:08:37.204003 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9705 11:08:37.207146 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9706 11:08:37.213742 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9707 11:08:37.216935 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9708 11:08:37.220208 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9709 11:08:37.226904 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9710 11:08:37.230334 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9711 11:08:37.236643 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9712 11:08:37.240343 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9713 11:08:37.243762 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9714 11:08:37.249986 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9715 11:08:37.253570 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9716 11:08:37.260235 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9717 11:08:37.263572 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9718 11:08:37.266777 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9719 11:08:37.273842 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9720 11:08:37.277025 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9721 11:08:37.283618 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9722 11:08:37.286925 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9723 11:08:37.290302 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9724 11:08:37.296877 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9725 11:08:37.300031 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9726 11:08:37.306748 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9727 11:08:37.309825 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9728 11:08:37.313637 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9729 11:08:37.320474 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9730 11:08:37.323336 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9731 11:08:37.329994 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9732 11:08:37.333306 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9733 11:08:37.340444 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9734 11:08:37.343582 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9735 11:08:37.346713 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9736 11:08:37.353208 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9737 11:08:37.356424 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9738 11:08:37.363329 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9739 11:08:37.366560 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9740 11:08:37.369711 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9741 11:08:37.376231 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9742 11:08:37.379930 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9743 11:08:37.386346 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9744 11:08:37.389623 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9745 11:08:37.396318 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9746 11:08:37.399621 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9747 11:08:37.403040 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9748 11:08:37.409683 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9749 11:08:37.412930 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9750 11:08:37.419875 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9751 11:08:37.423124 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9752 11:08:37.429371 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9753 11:08:37.433278 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9754 11:08:37.436614 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9755 11:08:37.442494 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9756 11:08:37.446471 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9757 11:08:37.449786 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9758 11:08:37.453015 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9759 11:08:37.459598 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9760 11:08:37.462585 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9761 11:08:37.465825 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9762 11:08:37.472491 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9763 11:08:37.475714 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9764 11:08:37.479556 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9765 11:08:37.486171 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9766 11:08:37.489483 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9767 11:08:37.492877 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9768 11:08:37.499289 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9769 11:08:37.502563 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9770 11:08:37.506025 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9771 11:08:37.512447 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9772 11:08:37.515643 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9773 11:08:37.522664 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9774 11:08:37.525737 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9775 11:08:37.529117 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9776 11:08:37.535498 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9777 11:08:37.539162 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9778 11:08:37.545697 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9779 11:08:37.548984 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9780 11:08:37.552327 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9781 11:08:37.559087 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9782 11:08:37.562362 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9783 11:08:37.565513 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9784 11:08:37.572256 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9785 11:08:37.575553 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9786 11:08:37.578944 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9787 11:08:37.585574 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9788 11:08:37.588885 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9789 11:08:37.595455 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9790 11:08:37.598672 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9791 11:08:37.601956 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9792 11:08:37.608502 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9793 11:08:37.612230 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9794 11:08:37.615356 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9795 11:08:37.622099 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9796 11:08:37.625476 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9797 11:08:37.628507 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9798 11:08:37.631943 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9799 11:08:37.638249 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9800 11:08:37.641864 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9801 11:08:37.645127 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9802 11:08:37.648738 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9803 11:08:37.655335 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9804 11:08:37.658139 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9805 11:08:37.661462 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9806 11:08:37.664870 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9807 11:08:37.671487 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9808 11:08:37.675352 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9809 11:08:37.678431 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9810 11:08:37.684835 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9811 11:08:37.688095 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9812 11:08:37.694811 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9813 11:08:37.698066 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9814 11:08:37.702017 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9815 11:08:37.708348 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9816 11:08:37.711627 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9817 11:08:37.718300 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9818 11:08:37.721549 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9819 11:08:37.724877 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9820 11:08:37.731345 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9821 11:08:37.734580 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9822 11:08:37.741463 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9823 11:08:37.744936 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9824 11:08:37.747814 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9825 11:08:37.754409 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9826 11:08:37.757769 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9827 11:08:37.764811 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9828 11:08:37.767846 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9829 11:08:37.774441 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9830 11:08:37.777689 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9831 11:08:37.780982 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9832 11:08:37.787845 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9833 11:08:37.790978 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9834 11:08:37.797929 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9835 11:08:37.801250 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9836 11:08:37.804643 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9837 11:08:37.811108 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9838 11:08:37.814317 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9839 11:08:37.820983 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9840 11:08:37.824218 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9841 11:08:37.827469 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9842 11:08:37.834143 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9843 11:08:37.837467 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9844 11:08:37.844221 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9845 11:08:37.847519 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9846 11:08:37.853983 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9847 11:08:37.857359 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9848 11:08:37.861062 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9849 11:08:37.867405 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9850 11:08:37.870667 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9851 11:08:37.877580 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9852 11:08:37.881015 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9853 11:08:37.884185 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9854 11:08:37.890742 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9855 11:08:37.894373 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9856 11:08:37.897293 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9857 11:08:37.903807 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9858 11:08:37.907437 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9859 11:08:37.913997 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9860 11:08:37.917364 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9861 11:08:37.923952 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9862 11:08:37.927128 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9863 11:08:37.930670 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9864 11:08:37.937068 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9865 11:08:37.940324 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9866 11:08:37.946989 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9867 11:08:37.950283 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9868 11:08:37.953579 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9869 11:08:37.960652 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9870 11:08:37.963995 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9871 11:08:37.970309 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9872 11:08:37.974048 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9873 11:08:37.977226 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9874 11:08:37.984071 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9875 11:08:37.986791 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9876 11:08:37.993989 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9877 11:08:37.997018 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9878 11:08:38.003597 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9879 11:08:38.006930 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9880 11:08:38.010270 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9881 11:08:38.016918 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9882 11:08:38.020580 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9883 11:08:38.026914 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9884 11:08:38.030495 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9885 11:08:38.037209 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9886 11:08:38.040007 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9887 11:08:38.043213 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9888 11:08:38.050341 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9889 11:08:38.053603 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9890 11:08:38.060082 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9891 11:08:38.063317 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9892 11:08:38.069966 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9893 11:08:38.073236 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9894 11:08:38.076472 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9895 11:08:38.083239 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9896 11:08:38.086436 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9897 11:08:38.093480 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9898 11:08:38.096895 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9899 11:08:38.103135 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9900 11:08:38.106231 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9901 11:08:38.113099 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9902 11:08:38.116476 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9903 11:08:38.119789 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9904 11:08:38.126270 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9905 11:08:38.129594 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9906 11:08:38.136134 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9907 11:08:38.139406 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9908 11:08:38.146255 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9909 11:08:38.149837 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9910 11:08:38.152638 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9911 11:08:38.159332 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9912 11:08:38.162843 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9913 11:08:38.169771 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9914 11:08:38.172717 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9915 11:08:38.179950 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9916 11:08:38.183273 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9917 11:08:38.186385 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9918 11:08:38.192797 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9919 11:08:38.196519 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9920 11:08:38.203170 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9921 11:08:38.206418 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9922 11:08:38.213207 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9923 11:08:38.216451 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9924 11:08:38.219743 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9925 11:08:38.226332 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9926 11:08:38.229556 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9927 11:08:38.236065 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9928 11:08:38.239385 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9929 11:08:38.242666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9930 11:08:38.249245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9931 11:08:38.252472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9932 11:08:38.259362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9933 11:08:38.262588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9934 11:08:38.269497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9935 11:08:38.272724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9936 11:08:38.279341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9937 11:08:38.282741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9938 11:08:38.289042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9939 11:08:38.292596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9940 11:08:38.299286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9941 11:08:38.302331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9942 11:08:38.309352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9943 11:08:38.312520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9944 11:08:38.318736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9945 11:08:38.322733 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9946 11:08:38.328707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9947 11:08:38.332658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9948 11:08:38.335802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9949 11:08:38.342572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9950 11:08:38.345315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9951 11:08:38.351952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9952 11:08:38.355726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9953 11:08:38.362221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9954 11:08:38.365497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9955 11:08:38.372049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9956 11:08:38.378573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9957 11:08:38.382045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9958 11:08:38.388551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9959 11:08:38.392576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9960 11:08:38.398571 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9961 11:08:38.401992 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9962 11:08:38.402075 INFO: [APUAPC] vio 0
9963 11:08:38.409225 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9964 11:08:38.412540 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9965 11:08:38.416026 INFO: [APUAPC] D0_APC_0: 0x400510
9966 11:08:38.419210 INFO: [APUAPC] D0_APC_1: 0x0
9967 11:08:38.422563 INFO: [APUAPC] D0_APC_2: 0x1540
9968 11:08:38.425827 INFO: [APUAPC] D0_APC_3: 0x0
9969 11:08:38.429546 INFO: [APUAPC] D1_APC_0: 0xffffffff
9970 11:08:38.432710 INFO: [APUAPC] D1_APC_1: 0xffffffff
9971 11:08:38.436164 INFO: [APUAPC] D1_APC_2: 0x3fffff
9972 11:08:38.439523 INFO: [APUAPC] D1_APC_3: 0x0
9973 11:08:38.442773 INFO: [APUAPC] D2_APC_0: 0xffffffff
9974 11:08:38.446017 INFO: [APUAPC] D2_APC_1: 0xffffffff
9975 11:08:38.449440 INFO: [APUAPC] D2_APC_2: 0x3fffff
9976 11:08:38.452684 INFO: [APUAPC] D2_APC_3: 0x0
9977 11:08:38.455889 INFO: [APUAPC] D3_APC_0: 0xffffffff
9978 11:08:38.459087 INFO: [APUAPC] D3_APC_1: 0xffffffff
9979 11:08:38.462308 INFO: [APUAPC] D3_APC_2: 0x3fffff
9980 11:08:38.466277 INFO: [APUAPC] D3_APC_3: 0x0
9981 11:08:38.469413 INFO: [APUAPC] D4_APC_0: 0xffffffff
9982 11:08:38.472810 INFO: [APUAPC] D4_APC_1: 0xffffffff
9983 11:08:38.476077 INFO: [APUAPC] D4_APC_2: 0x3fffff
9984 11:08:38.476158 INFO: [APUAPC] D4_APC_3: 0x0
9985 11:08:38.479297 INFO: [APUAPC] D5_APC_0: 0xffffffff
9986 11:08:38.482332 INFO: [APUAPC] D5_APC_1: 0xffffffff
9987 11:08:38.485851 INFO: [APUAPC] D5_APC_2: 0x3fffff
9988 11:08:38.488911 INFO: [APUAPC] D5_APC_3: 0x0
9989 11:08:38.492813 INFO: [APUAPC] D6_APC_0: 0xffffffff
9990 11:08:38.496019 INFO: [APUAPC] D6_APC_1: 0xffffffff
9991 11:08:38.499494 INFO: [APUAPC] D6_APC_2: 0x3fffff
9992 11:08:38.502120 INFO: [APUAPC] D6_APC_3: 0x0
9993 11:08:38.506063 INFO: [APUAPC] D7_APC_0: 0xffffffff
9994 11:08:38.509394 INFO: [APUAPC] D7_APC_1: 0xffffffff
9995 11:08:38.512435 INFO: [APUAPC] D7_APC_2: 0x3fffff
9996 11:08:38.515716 INFO: [APUAPC] D7_APC_3: 0x0
9997 11:08:38.518773 INFO: [APUAPC] D8_APC_0: 0xffffffff
9998 11:08:38.522236 INFO: [APUAPC] D8_APC_1: 0xffffffff
9999 11:08:38.525482 INFO: [APUAPC] D8_APC_2: 0x3fffff
10000 11:08:38.529121 INFO: [APUAPC] D8_APC_3: 0x0
10001 11:08:38.532130 INFO: [APUAPC] D9_APC_0: 0xffffffff
10002 11:08:38.535361 INFO: [APUAPC] D9_APC_1: 0xffffffff
10003 11:08:38.539002 INFO: [APUAPC] D9_APC_2: 0x3fffff
10004 11:08:38.542338 INFO: [APUAPC] D9_APC_3: 0x0
10005 11:08:38.545647 INFO: [APUAPC] D10_APC_0: 0xffffffff
10006 11:08:38.549208 INFO: [APUAPC] D10_APC_1: 0xffffffff
10007 11:08:38.552424 INFO: [APUAPC] D10_APC_2: 0x3fffff
10008 11:08:38.555597 INFO: [APUAPC] D10_APC_3: 0x0
10009 11:08:38.558502 INFO: [APUAPC] D11_APC_0: 0xffffffff
10010 11:08:38.562276 INFO: [APUAPC] D11_APC_1: 0xffffffff
10011 11:08:38.565600 INFO: [APUAPC] D11_APC_2: 0x3fffff
10012 11:08:38.569018 INFO: [APUAPC] D11_APC_3: 0x0
10013 11:08:38.572207 INFO: [APUAPC] D12_APC_0: 0xffffffff
10014 11:08:38.575546 INFO: [APUAPC] D12_APC_1: 0xffffffff
10015 11:08:38.578830 INFO: [APUAPC] D12_APC_2: 0x3fffff
10016 11:08:38.582129 INFO: [APUAPC] D12_APC_3: 0x0
10017 11:08:38.585462 INFO: [APUAPC] D13_APC_0: 0xffffffff
10018 11:08:38.588573 INFO: [APUAPC] D13_APC_1: 0xffffffff
10019 11:08:38.592189 INFO: [APUAPC] D13_APC_2: 0x3fffff
10020 11:08:38.595354 INFO: [APUAPC] D13_APC_3: 0x0
10021 11:08:38.599150 INFO: [APUAPC] D14_APC_0: 0xffffffff
10022 11:08:38.602405 INFO: [APUAPC] D14_APC_1: 0xffffffff
10023 11:08:38.605710 INFO: [APUAPC] D14_APC_2: 0x3fffff
10024 11:08:38.609015 INFO: [APUAPC] D14_APC_3: 0x0
10025 11:08:38.612222 INFO: [APUAPC] D15_APC_0: 0xffffffff
10026 11:08:38.615689 INFO: [APUAPC] D15_APC_1: 0xffffffff
10027 11:08:38.618960 INFO: [APUAPC] D15_APC_2: 0x3fffff
10028 11:08:38.622318 INFO: [APUAPC] D15_APC_3: 0x0
10029 11:08:38.625684 INFO: [APUAPC] APC_CON: 0x4
10030 11:08:38.628916 INFO: [NOCDAPC] D0_APC_0: 0x0
10031 11:08:38.631982 INFO: [NOCDAPC] D0_APC_1: 0x0
10032 11:08:38.635348 INFO: [NOCDAPC] D1_APC_0: 0x0
10033 11:08:38.638548 INFO: [NOCDAPC] D1_APC_1: 0xfff
10034 11:08:38.638629 INFO: [NOCDAPC] D2_APC_0: 0x0
10035 11:08:38.641585 INFO: [NOCDAPC] D2_APC_1: 0xfff
10036 11:08:38.645379 INFO: [NOCDAPC] D3_APC_0: 0x0
10037 11:08:38.648463 INFO: [NOCDAPC] D3_APC_1: 0xfff
10038 11:08:38.651696 INFO: [NOCDAPC] D4_APC_0: 0x0
10039 11:08:38.654844 INFO: [NOCDAPC] D4_APC_1: 0xfff
10040 11:08:38.658343 INFO: [NOCDAPC] D5_APC_0: 0x0
10041 11:08:38.661891 INFO: [NOCDAPC] D5_APC_1: 0xfff
10042 11:08:38.665443 INFO: [NOCDAPC] D6_APC_0: 0x0
10043 11:08:38.668601 INFO: [NOCDAPC] D6_APC_1: 0xfff
10044 11:08:38.668682 INFO: [NOCDAPC] D7_APC_0: 0x0
10045 11:08:38.672079 INFO: [NOCDAPC] D7_APC_1: 0xfff
10046 11:08:38.675434 INFO: [NOCDAPC] D8_APC_0: 0x0
10047 11:08:38.678256 INFO: [NOCDAPC] D8_APC_1: 0xfff
10048 11:08:38.681738 INFO: [NOCDAPC] D9_APC_0: 0x0
10049 11:08:38.685035 INFO: [NOCDAPC] D9_APC_1: 0xfff
10050 11:08:38.688323 INFO: [NOCDAPC] D10_APC_0: 0x0
10051 11:08:38.691590 INFO: [NOCDAPC] D10_APC_1: 0xfff
10052 11:08:38.695425 INFO: [NOCDAPC] D11_APC_0: 0x0
10053 11:08:38.698694 INFO: [NOCDAPC] D11_APC_1: 0xfff
10054 11:08:38.701840 INFO: [NOCDAPC] D12_APC_0: 0x0
10055 11:08:38.705089 INFO: [NOCDAPC] D12_APC_1: 0xfff
10056 11:08:38.708397 INFO: [NOCDAPC] D13_APC_0: 0x0
10057 11:08:38.711733 INFO: [NOCDAPC] D13_APC_1: 0xfff
10058 11:08:38.711810 INFO: [NOCDAPC] D14_APC_0: 0x0
10059 11:08:38.715252 INFO: [NOCDAPC] D14_APC_1: 0xfff
10060 11:08:38.718503 INFO: [NOCDAPC] D15_APC_0: 0x0
10061 11:08:38.721817 INFO: [NOCDAPC] D15_APC_1: 0xfff
10062 11:08:38.725023 INFO: [NOCDAPC] APC_CON: 0x4
10063 11:08:38.728363 INFO: [APUAPC] set_apusys_apc done
10064 11:08:38.731708 INFO: [DEVAPC] devapc_init done
10065 11:08:38.735043 INFO: GICv3 without legacy support detected.
10066 11:08:38.741941 INFO: ARM GICv3 driver initialized in EL3
10067 11:08:38.744621 INFO: Maximum SPI INTID supported: 639
10068 11:08:38.748456 INFO: BL31: Initializing runtime services
10069 11:08:38.754565 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10070 11:08:38.754649 INFO: SPM: enable CPC mode
10071 11:08:38.761629 INFO: mcdi ready for mcusys-off-idle and system suspend
10072 11:08:38.764754 INFO: BL31: Preparing for EL3 exit to normal world
10073 11:08:38.767883 INFO: Entry point address = 0x80000000
10074 11:08:38.771691 INFO: SPSR = 0x8
10075 11:08:38.777508
10076 11:08:38.777590
10077 11:08:38.777654
10078 11:08:38.780730 Starting depthcharge on Spherion...
10079 11:08:38.780824
10080 11:08:38.780900 Wipe memory regions:
10081 11:08:38.780974
10082 11:08:38.781710 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10083 11:08:38.781812 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10084 11:08:38.781895 Setting prompt string to ['asurada:']
10085 11:08:38.781980 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10086 11:08:38.783777 [0x00000040000000, 0x00000054600000)
10087 11:08:38.906139
10088 11:08:38.906268 [0x00000054660000, 0x00000080000000)
10089 11:08:39.166576
10090 11:08:39.166724 [0x000000821a7280, 0x000000ffe64000)
10091 11:08:39.911445
10092 11:08:39.911585 [0x00000100000000, 0x00000240000000)
10093 11:08:41.801278
10094 11:08:41.804379 Initializing XHCI USB controller at 0x11200000.
10095 11:08:42.841919
10096 11:08:42.845358 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10097 11:08:42.845444
10098 11:08:42.845528
10099 11:08:42.845607
10100 11:08:42.845913 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10102 11:08:42.946283 asurada: tftpboot 192.168.201.1 12925630/tftp-deploy-kpoqbs7e/kernel/image.itb 12925630/tftp-deploy-kpoqbs7e/kernel/cmdline
10103 11:08:42.946418 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10104 11:08:42.946518 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10105 11:08:42.951047 tftpboot 192.168.201.1 12925630/tftp-deploy-kpoqbs7e/kernel/image.ittp-deploy-kpoqbs7e/kernel/cmdline
10106 11:08:42.951133
10107 11:08:42.951217 Waiting for link
10108 11:08:43.111254
10109 11:08:43.111389 R8152: Initializing
10110 11:08:43.111479
10111 11:08:43.114523 Version 9 (ocp_data = 6010)
10112 11:08:43.114607
10113 11:08:43.117876 R8152: Done initializing
10114 11:08:43.117959
10115 11:08:43.118042 Adding net device
10116 11:08:45.063699
10117 11:08:45.063833 done.
10118 11:08:45.063901
10119 11:08:45.063962 MAC: 00:e0:4c:78:7a:aa
10120 11:08:45.064020
10121 11:08:45.067399 Sending DHCP discover... done.
10122 11:08:45.067514
10123 11:08:45.070586 Waiting for reply... done.
10124 11:08:45.070672
10125 11:08:45.073914 Sending DHCP request... done.
10126 11:08:45.073998
10127 11:08:45.074081 Waiting for reply... done.
10128 11:08:45.074161
10129 11:08:45.077128 My ip is 192.168.201.12
10130 11:08:45.077211
10131 11:08:45.080400 The DHCP server ip is 192.168.201.1
10132 11:08:45.080482
10133 11:08:45.083646 TFTP server IP predefined by user: 192.168.201.1
10134 11:08:45.083728
10135 11:08:45.090303 Bootfile predefined by user: 12925630/tftp-deploy-kpoqbs7e/kernel/image.itb
10136 11:08:45.090387
10137 11:08:45.093704 Sending tftp read request... done.
10138 11:08:45.093785
10139 11:08:45.096943 Waiting for the transfer...
10140 11:08:45.097057
10141 11:08:45.365778 00000000 ################################################################
10142 11:08:45.365914
10143 11:08:45.631506 00080000 ################################################################
10144 11:08:45.631640
10145 11:08:45.920591 00100000 ################################################################
10146 11:08:45.920730
10147 11:08:46.194761 00180000 ################################################################
10148 11:08:46.194898
10149 11:08:46.462967 00200000 ################################################################
10150 11:08:46.463155
10151 11:08:46.730925 00280000 ################################################################
10152 11:08:46.731073
10153 11:08:46.996283 00300000 ################################################################
10154 11:08:46.996427
10155 11:08:47.272503 00380000 ################################################################
10156 11:08:47.272639
10157 11:08:47.531068 00400000 ################################################################
10158 11:08:47.531235
10159 11:08:47.800806 00480000 ################################################################
10160 11:08:47.800935
10161 11:08:48.058044 00500000 ################################################################
10162 11:08:48.058266
10163 11:08:48.327165 00580000 ################################################################
10164 11:08:48.327298
10165 11:08:48.593754 00600000 ################################################################
10166 11:08:48.593889
10167 11:08:48.866175 00680000 ################################################################
10168 11:08:48.866310
10169 11:08:49.131955 00700000 ################################################################
10170 11:08:49.132127
10171 11:08:49.390765 00780000 ################################################################
10172 11:08:49.390901
10173 11:08:49.653887 00800000 ################################################################
10174 11:08:49.654027
10175 11:08:49.930137 00880000 ################################################################
10176 11:08:49.930271
10177 11:08:50.214167 00900000 ################################################################
10178 11:08:50.214341
10179 11:08:50.498698 00980000 ################################################################
10180 11:08:50.498969
10181 11:08:50.773454 00a00000 ################################################################
10182 11:08:50.773591
10183 11:08:51.065260 00a80000 ################################################################
10184 11:08:51.065399
10185 11:08:51.358675 00b00000 ################################################################
10186 11:08:51.358834
10187 11:08:51.655163 00b80000 ################################################################
10188 11:08:51.655302
10189 11:08:51.920881 00c00000 ################################################################
10190 11:08:51.921016
10191 11:08:52.177941 00c80000 ################################################################
10192 11:08:52.178088
10193 11:08:52.439983 00d00000 ################################################################
10194 11:08:52.440117
10195 11:08:52.706350 00d80000 ################################################################
10196 11:08:52.706486
10197 11:08:52.961044 00e00000 ################################################################
10198 11:08:52.961180
10199 11:08:53.221553 00e80000 ################################################################
10200 11:08:53.221716
10201 11:08:53.495233 00f00000 ################################################################
10202 11:08:53.495435
10203 11:08:53.769031 00f80000 ################################################################
10204 11:08:53.769216
10205 11:08:54.033017 01000000 ################################################################
10206 11:08:54.033218
10207 11:08:54.304399 01080000 ################################################################
10208 11:08:54.304541
10209 11:08:54.568766 01100000 ################################################################
10210 11:08:54.568964
10211 11:08:54.842376 01180000 ################################################################
10212 11:08:54.842516
10213 11:08:55.131458 01200000 ################################################################
10214 11:08:55.131595
10215 11:08:55.407683 01280000 ################################################################
10216 11:08:55.407848
10217 11:08:55.673360 01300000 ################################################################
10218 11:08:55.673499
10219 11:08:55.932175 01380000 ################################################################
10220 11:08:55.932350
10221 11:08:56.189685 01400000 ################################################################
10222 11:08:56.189822
10223 11:08:56.450263 01480000 ################################################################
10224 11:08:56.450422
10225 11:08:56.712328 01500000 ################################################################
10226 11:08:56.712462
10227 11:08:56.971928 01580000 ################################################################
10228 11:08:56.972068
10229 11:08:57.244711 01600000 ################################################################
10230 11:08:57.244864
10231 11:08:57.521437 01680000 ################################################################
10232 11:08:57.521588
10233 11:08:57.793488 01700000 ################################################################
10234 11:08:57.793653
10235 11:08:58.070794 01780000 ################################################################
10236 11:08:58.070956
10237 11:08:58.327173 01800000 ################################################################
10238 11:08:58.327360
10239 11:08:58.590903 01880000 ################################################################
10240 11:08:58.591098
10241 11:08:58.846998 01900000 ################################################################
10242 11:08:58.847135
10243 11:08:59.110924 01980000 ################################################################
10244 11:08:59.111058
10245 11:08:59.373175 01a00000 ################################################################
10246 11:08:59.373316
10247 11:08:59.661828 01a80000 ################################################################
10248 11:08:59.661979
10249 11:08:59.937606 01b00000 ################################################################
10250 11:08:59.937810
10251 11:09:00.191417 01b80000 ################################################################
10252 11:09:00.191555
10253 11:09:00.458364 01c00000 ################################################################
10254 11:09:00.458502
10255 11:09:00.471314 01c80000 #### done.
10256 11:09:00.471432
10257 11:09:00.474469 The bootfile was 29912682 bytes long.
10258 11:09:00.474555
10259 11:09:00.477621 Sending tftp read request... done.
10260 11:09:00.477708
10261 11:09:00.480895 Waiting for the transfer...
10262 11:09:00.480979
10263 11:09:00.481045 00000000 # done.
10264 11:09:00.481109
10265 11:09:00.491247 Command line loaded dynamically from TFTP file: 12925630/tftp-deploy-kpoqbs7e/kernel/cmdline
10266 11:09:00.491333
10267 11:09:00.510842 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12925630/extract-nfsrootfs-uebyb0qu,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10268 11:09:00.510938
10269 11:09:00.514435 Loading FIT.
10270 11:09:00.514510
10271 11:09:00.517443 Image ramdisk-1 has 17805670 bytes.
10272 11:09:00.517529
10273 11:09:00.520580 Image fdt-1 has 47278 bytes.
10274 11:09:00.520654
10275 11:09:00.520718 Image kernel-1 has 12057697 bytes.
10276 11:09:00.524494
10277 11:09:00.530868 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10278 11:09:00.530953
10279 11:09:00.547447 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10280 11:09:00.550622
10281 11:09:00.553859 Choosing best match conf-1 for compat google,spherion-rev2.
10282 11:09:00.558395
10283 11:09:00.563320 Connected to device vid:did:rid of 1ae0:0028:00
10284 11:09:00.571319
10285 11:09:00.574542 tpm_get_response: command 0x17b, return code 0x0
10286 11:09:00.574625
10287 11:09:00.581177 ec_init: CrosEC protocol v3 supported (256, 248)
10288 11:09:00.581273
10289 11:09:00.584598 tpm_cleanup: add release locality here.
10290 11:09:00.584713
10291 11:09:00.587749 Shutting down all USB controllers.
10292 11:09:00.587824
10293 11:09:00.591160 Removing current net device
10294 11:09:00.591246
10295 11:09:00.594856 Exiting depthcharge with code 4 at timestamp: 51095564
10296 11:09:00.594946
10297 11:09:00.598133 LZMA decompressing kernel-1 to 0x821a6718
10298 11:09:00.598219
10299 11:09:00.604659 LZMA decompressing kernel-1 to 0x40000000
10300 11:09:02.103875
10301 11:09:02.104015 jumping to kernel
10302 11:09:02.104507 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10303 11:09:02.104607 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10304 11:09:02.104685 Setting prompt string to ['Linux version [0-9]']
10305 11:09:02.104753 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10306 11:09:02.104820 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10307 11:09:02.185667
10308 11:09:02.188992 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10309 11:09:02.192763 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10310 11:09:02.192862 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10311 11:09:02.192937 Setting prompt string to []
10312 11:09:02.193014 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10313 11:09:02.193088 Using line separator: #'\n'#
10314 11:09:02.193166 No login prompt set.
10315 11:09:02.193273 Parsing kernel messages
10316 11:09:02.193329 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10317 11:09:02.193470 [login-action] Waiting for messages, (timeout 00:04:02)
10318 11:09:02.193539 Waiting using forced prompt support (timeout 00:02:01)
10319 11:09:02.212522 [ 0.000000] Linux version 6.1.80-cip16 (KernelCI@build-j128891-arm64-gcc-10-defconfig-arm64-chromebook-nrg4h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024
10320 11:09:02.215757 [ 0.000000] random: crng init done
10321 11:09:02.222403 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10322 11:09:02.225651 [ 0.000000] efi: UEFI not found.
10323 11:09:02.232256 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10324 11:09:02.239230 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10325 11:09:02.248539 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10326 11:09:02.258722 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10327 11:09:02.265699 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10328 11:09:02.271869 [ 0.000000] printk: bootconsole [mtk8250] enabled
10329 11:09:02.275244 [ 0.000000] NUMA: No NUMA configuration found
10330 11:09:02.285288 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10331 11:09:02.288622 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10332 11:09:02.291830 [ 0.000000] Zone ranges:
10333 11:09:02.298781 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10334 11:09:02.302151 [ 0.000000] DMA32 empty
10335 11:09:02.308868 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10336 11:09:02.311678 [ 0.000000] Movable zone start for each node
10337 11:09:02.315264 [ 0.000000] Early memory node ranges
10338 11:09:02.321729 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10339 11:09:02.328560 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10340 11:09:02.334878 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10341 11:09:02.338378 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10342 11:09:02.345183 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10343 11:09:02.351952 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10344 11:09:02.410228 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10345 11:09:02.416774 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10346 11:09:02.423609 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10347 11:09:02.427060 [ 0.000000] psci: probing for conduit method from DT.
10348 11:09:02.433675 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10349 11:09:02.436707 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10350 11:09:02.443727 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10351 11:09:02.446797 [ 0.000000] psci: SMC Calling Convention v1.2
10352 11:09:02.453711 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10353 11:09:02.456846 [ 0.000000] Detected VIPT I-cache on CPU0
10354 11:09:02.463244 [ 0.000000] CPU features: detected: GIC system register CPU interface
10355 11:09:02.469864 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10356 11:09:02.476739 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10357 11:09:02.483176 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10358 11:09:02.489769 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10359 11:09:02.499540 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10360 11:09:02.502821 [ 0.000000] alternatives: applying boot alternatives
10361 11:09:02.509907 [ 0.000000] Fallback order for Node 0: 0
10362 11:09:02.516215 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10363 11:09:02.519562 [ 0.000000] Policy zone: Normal
10364 11:09:02.542915 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12925630/extract-nfsrootfs-uebyb0qu,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10365 11:09:02.552955 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10366 11:09:02.563402 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10367 11:09:02.572958 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10368 11:09:02.579547 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10369 11:09:02.583396 <6>[ 0.000000] software IO TLB: area num 8.
10370 11:09:02.639914 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10371 11:09:02.788634 <6>[ 0.000000] Memory: 7949804K/8385536K available (18048K kernel code, 4118K rwdata, 19616K rodata, 8448K init, 616K bss, 402964K reserved, 32768K cma-reserved)
10372 11:09:02.795287 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10373 11:09:02.802322 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10374 11:09:02.805363 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10375 11:09:02.811593 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10376 11:09:02.818617 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10377 11:09:02.821720 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10378 11:09:02.831900 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10379 11:09:02.838498 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10380 11:09:02.841543 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10381 11:09:02.849617 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10382 11:09:02.857702 <6>[ 0.000000] GICv3: 608 SPIs implemented
10383 11:09:02.859783 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10384 11:09:02.862787 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10385 11:09:02.866612 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10386 11:09:02.873596 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10387 11:09:02.886694 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10388 11:09:02.899604 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10389 11:09:02.906479 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10390 11:09:02.915224 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10391 11:09:02.928557 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10392 11:09:02.934830 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10393 11:09:02.942303 <6>[ 0.009174] Console: colour dummy device 80x25
10394 11:09:02.951630 <6>[ 0.013932] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10395 11:09:02.958509 <6>[ 0.024374] pid_max: default: 32768 minimum: 301
10396 11:09:02.961794 <6>[ 0.029274] LSM: Security Framework initializing
10397 11:09:02.968647 <6>[ 0.034214] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10398 11:09:02.978111 <6>[ 0.041996] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10399 11:09:02.984751 <6>[ 0.051477] cblist_init_generic: Setting adjustable number of callback queues.
10400 11:09:02.991799 <6>[ 0.058964] cblist_init_generic: Setting shift to 3 and lim to 1.
10401 11:09:03.001784 <6>[ 0.065343] cblist_init_generic: Setting adjustable number of callback queues.
10402 11:09:03.008721 <6>[ 0.072771] cblist_init_generic: Setting shift to 3 and lim to 1.
10403 11:09:03.011772 <6>[ 0.079175] rcu: Hierarchical SRCU implementation.
10404 11:09:03.018506 <6>[ 0.084190] rcu: Max phase no-delay instances is 1000.
10405 11:09:03.024985 <6>[ 0.091217] EFI services will not be available.
10406 11:09:03.028094 <6>[ 0.096172] smp: Bringing up secondary CPUs ...
10407 11:09:03.036228 <6>[ 0.101230] Detected VIPT I-cache on CPU1
10408 11:09:03.042628 <6>[ 0.101301] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10409 11:09:03.049717 <6>[ 0.101335] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10410 11:09:03.052900 <6>[ 0.101676] Detected VIPT I-cache on CPU2
10411 11:09:03.059507 <6>[ 0.101727] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10412 11:09:03.065952 <6>[ 0.101743] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10413 11:09:03.073004 <6>[ 0.102000] Detected VIPT I-cache on CPU3
10414 11:09:03.079504 <6>[ 0.102046] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10415 11:09:03.086220 <6>[ 0.102060] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10416 11:09:03.089169 <6>[ 0.102367] CPU features: detected: Spectre-v4
10417 11:09:03.096281 <6>[ 0.102374] CPU features: detected: Spectre-BHB
10418 11:09:03.099691 <6>[ 0.102379] Detected PIPT I-cache on CPU4
10419 11:09:03.105967 <6>[ 0.102434] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10420 11:09:03.112426 <6>[ 0.102451] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10421 11:09:03.119347 <6>[ 0.102751] Detected PIPT I-cache on CPU5
10422 11:09:03.126006 <6>[ 0.102813] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10423 11:09:03.132260 <6>[ 0.102829] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10424 11:09:03.135996 <6>[ 0.103110] Detected PIPT I-cache on CPU6
10425 11:09:03.142443 <6>[ 0.103175] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10426 11:09:03.149485 <6>[ 0.103192] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10427 11:09:03.155602 <6>[ 0.103493] Detected PIPT I-cache on CPU7
10428 11:09:03.162584 <6>[ 0.103558] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10429 11:09:03.169034 <6>[ 0.103575] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10430 11:09:03.172133 <6>[ 0.103623] smp: Brought up 1 node, 8 CPUs
10431 11:09:03.178629 <6>[ 0.244950] SMP: Total of 8 processors activated.
10432 11:09:03.181968 <6>[ 0.249870] CPU features: detected: 32-bit EL0 Support
10433 11:09:03.192152 <6>[ 0.255267] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10434 11:09:03.198371 <6>[ 0.264070] CPU features: detected: Common not Private translations
10435 11:09:03.202285 <6>[ 0.270546] CPU features: detected: CRC32 instructions
10436 11:09:03.208625 <6>[ 0.275898] CPU features: detected: RCpc load-acquire (LDAPR)
10437 11:09:03.215124 <6>[ 0.281857] CPU features: detected: LSE atomic instructions
10438 11:09:03.222092 <6>[ 0.287639] CPU features: detected: Privileged Access Never
10439 11:09:03.224991 <6>[ 0.293419] CPU features: detected: RAS Extension Support
10440 11:09:03.235384 <6>[ 0.299062] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10441 11:09:03.238398 <6>[ 0.306279] CPU: All CPU(s) started at EL2
10442 11:09:03.244775 <6>[ 0.310623] alternatives: applying system-wide alternatives
10443 11:09:03.253750 <6>[ 0.321437] devtmpfs: initialized
10444 11:09:03.266369 <6>[ 0.330379] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10445 11:09:03.276161 <6>[ 0.340341] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10446 11:09:03.283233 <6>[ 0.348372] pinctrl core: initialized pinctrl subsystem
10447 11:09:03.286133 <6>[ 0.355033] DMI not present or invalid.
10448 11:09:03.293250 <6>[ 0.359446] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10449 11:09:03.303010 <6>[ 0.366308] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10450 11:09:03.309343 <6>[ 0.373903] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10451 11:09:03.319241 <6>[ 0.382129] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10452 11:09:03.322936 <6>[ 0.390371] audit: initializing netlink subsys (disabled)
10453 11:09:03.332936 <5>[ 0.396064] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10454 11:09:03.339594 <6>[ 0.396774] thermal_sys: Registered thermal governor 'step_wise'
10455 11:09:03.346069 <6>[ 0.404033] thermal_sys: Registered thermal governor 'power_allocator'
10456 11:09:03.349330 <6>[ 0.410290] cpuidle: using governor menu
10457 11:09:03.352508 <6>[ 0.421254] NET: Registered PF_QIPCRTR protocol family
10458 11:09:03.362539 <6>[ 0.426736] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10459 11:09:03.366153 <6>[ 0.433842] ASID allocator initialised with 32768 entries
10460 11:09:03.373163 <6>[ 0.440423] Serial: AMBA PL011 UART driver
10461 11:09:03.381937 <4>[ 0.449176] Trying to register duplicate clock ID: 134
10462 11:09:03.436280 <6>[ 0.506970] KASLR enabled
10463 11:09:03.450773 <6>[ 0.514826] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10464 11:09:03.457646 <6>[ 0.521840] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10465 11:09:03.463843 <6>[ 0.528331] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10466 11:09:03.470442 <6>[ 0.535339] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10467 11:09:03.477235 <6>[ 0.541825] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10468 11:09:03.483519 <6>[ 0.548828] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10469 11:09:03.490030 <6>[ 0.555313] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10470 11:09:03.497048 <6>[ 0.562318] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10471 11:09:03.500186 <6>[ 0.569856] ACPI: Interpreter disabled.
10472 11:09:03.509067 <6>[ 0.576267] iommu: Default domain type: Translated
10473 11:09:03.515660 <6>[ 0.581382] iommu: DMA domain TLB invalidation policy: strict mode
10474 11:09:03.518797 <5>[ 0.588044] SCSI subsystem initialized
10475 11:09:03.525333 <6>[ 0.592213] usbcore: registered new interface driver usbfs
10476 11:09:03.532354 <6>[ 0.597943] usbcore: registered new interface driver hub
10477 11:09:03.534935 <6>[ 0.603492] usbcore: registered new device driver usb
10478 11:09:03.542448 <6>[ 0.609589] pps_core: LinuxPPS API ver. 1 registered
10479 11:09:03.552471 <6>[ 0.614783] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10480 11:09:03.555785 <6>[ 0.624131] PTP clock support registered
10481 11:09:03.558673 <6>[ 0.628373] EDAC MC: Ver: 3.0.0
10482 11:09:03.565996 <6>[ 0.633528] FPGA manager framework
10483 11:09:03.572707 <6>[ 0.637207] Advanced Linux Sound Architecture Driver Initialized.
10484 11:09:03.575876 <6>[ 0.643990] vgaarb: loaded
10485 11:09:03.582705 <6>[ 0.647170] clocksource: Switched to clocksource arch_sys_counter
10486 11:09:03.585875 <5>[ 0.653600] VFS: Disk quotas dquot_6.6.0
10487 11:09:03.592630 <6>[ 0.657787] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10488 11:09:03.595712 <6>[ 0.664976] pnp: PnP ACPI: disabled
10489 11:09:03.604216 <6>[ 0.671635] NET: Registered PF_INET protocol family
10490 11:09:03.611147 <6>[ 0.677224] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10491 11:09:03.625088 <6>[ 0.689532] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10492 11:09:03.635440 <6>[ 0.698350] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10493 11:09:03.642000 <6>[ 0.706320] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10494 11:09:03.648984 <6>[ 0.715023] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10495 11:09:03.660722 <6>[ 0.724774] TCP: Hash tables configured (established 65536 bind 65536)
10496 11:09:03.667113 <6>[ 0.731634] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10497 11:09:03.674038 <6>[ 0.738832] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10498 11:09:03.680471 <6>[ 0.746533] NET: Registered PF_UNIX/PF_LOCAL protocol family
10499 11:09:03.687546 <6>[ 0.752711] RPC: Registered named UNIX socket transport module.
10500 11:09:03.690659 <6>[ 0.758865] RPC: Registered udp transport module.
10501 11:09:03.697552 <6>[ 0.763799] RPC: Registered tcp transport module.
10502 11:09:03.703978 <6>[ 0.768731] RPC: Registered tcp NFSv4.1 backchannel transport module.
10503 11:09:03.706971 <6>[ 0.775401] PCI: CLS 0 bytes, default 64
10504 11:09:03.710282 <6>[ 0.779682] Unpacking initramfs...
10505 11:09:03.727634 <6>[ 0.791796] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10506 11:09:03.737988 <6>[ 0.800463] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10507 11:09:03.740636 <6>[ 0.809318] kvm [1]: IPA Size Limit: 40 bits
10508 11:09:03.747658 <6>[ 0.813845] kvm [1]: GICv3: no GICV resource entry
10509 11:09:03.750630 <6>[ 0.818865] kvm [1]: disabling GICv2 emulation
10510 11:09:03.757595 <6>[ 0.823554] kvm [1]: GIC system register CPU interface enabled
10511 11:09:03.760784 <6>[ 0.829711] kvm [1]: vgic interrupt IRQ18
10512 11:09:03.767603 <6>[ 0.834063] kvm [1]: VHE mode initialized successfully
10513 11:09:03.774463 <5>[ 0.840576] Initialise system trusted keyrings
10514 11:09:03.780960 <6>[ 0.845372] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10515 11:09:03.788576 <6>[ 0.855618] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10516 11:09:03.794895 <5>[ 0.862031] NFS: Registering the id_resolver key type
10517 11:09:03.798194 <5>[ 0.867337] Key type id_resolver registered
10518 11:09:03.805124 <5>[ 0.871751] Key type id_legacy registered
10519 11:09:03.811579 <6>[ 0.876036] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10520 11:09:03.818115 <6>[ 0.882957] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10521 11:09:03.824918 <6>[ 0.890669] 9p: Installing v9fs 9p2000 file system support
10522 11:09:03.861113 <5>[ 0.928330] Key type asymmetric registered
10523 11:09:03.864149 <5>[ 0.932660] Asymmetric key parser 'x509' registered
10524 11:09:03.874045 <6>[ 0.937804] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10525 11:09:03.877417 <6>[ 0.945436] io scheduler mq-deadline registered
10526 11:09:03.880909 <6>[ 0.950218] io scheduler kyber registered
10527 11:09:03.899511 <6>[ 0.967331] EINJ: ACPI disabled.
10528 11:09:03.932180 <4>[ 0.992883] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10529 11:09:03.941670 <4>[ 1.003521] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10530 11:09:03.956857 <6>[ 1.024364] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10531 11:09:03.964737 <6>[ 1.032278] printk: console [ttyS0] disabled
10532 11:09:03.992736 <6>[ 1.056902] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10533 11:09:03.999464 <6>[ 1.066378] printk: console [ttyS0] enabled
10534 11:09:04.002837 <6>[ 1.066378] printk: console [ttyS0] enabled
10535 11:09:04.009289 <6>[ 1.075272] printk: bootconsole [mtk8250] disabled
10536 11:09:04.012497 <6>[ 1.075272] printk: bootconsole [mtk8250] disabled
10537 11:09:04.019542 <6>[ 1.086497] SuperH (H)SCI(F) driver initialized
10538 11:09:04.022711 <6>[ 1.091758] msm_serial: driver initialized
10539 11:09:04.036767 <6>[ 1.100784] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10540 11:09:04.046760 <6>[ 1.109330] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10541 11:09:04.052975 <6>[ 1.117872] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10542 11:09:04.063127 <6>[ 1.126500] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10543 11:09:04.069963 <6>[ 1.135215] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10544 11:09:04.079622 <6>[ 1.143935] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10545 11:09:04.089749 <6>[ 1.152476] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10546 11:09:04.096670 <6>[ 1.161287] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10547 11:09:04.106399 <6>[ 1.169831] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10548 11:09:04.117923 <6>[ 1.185633] loop: module loaded
10549 11:09:04.124503 <6>[ 1.191661] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10550 11:09:04.147940 <4>[ 1.215092] mtk-pmic-keys: Failed to locate of_node [id: -1]
10551 11:09:04.154291 <6>[ 1.222091] megasas: 07.719.03.00-rc1
10552 11:09:04.164218 <6>[ 1.232000] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10553 11:09:04.171572 <6>[ 1.238561] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10554 11:09:04.187660 <6>[ 1.255084] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10555 11:09:04.244302 <6>[ 1.305004] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10556 11:09:04.455454 <6>[ 1.523268] Freeing initrd memory: 17384K
10557 11:09:04.465708 <6>[ 1.533495] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10558 11:09:04.477190 <6>[ 1.544564] tun: Universal TUN/TAP device driver, 1.6
10559 11:09:04.480732 <6>[ 1.550636] thunder_xcv, ver 1.0
10560 11:09:04.483508 <6>[ 1.554139] thunder_bgx, ver 1.0
10561 11:09:04.487030 <6>[ 1.557635] nicpf, ver 1.0
10562 11:09:04.497301 <6>[ 1.561654] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10563 11:09:04.500622 <6>[ 1.569130] hns3: Copyright (c) 2017 Huawei Corporation.
10564 11:09:04.507274 <6>[ 1.574719] hclge is initializing
10565 11:09:04.510665 <6>[ 1.578301] e1000: Intel(R) PRO/1000 Network Driver
10566 11:09:04.517920 <6>[ 1.583430] e1000: Copyright (c) 1999-2006 Intel Corporation.
10567 11:09:04.521147 <6>[ 1.589443] e1000e: Intel(R) PRO/1000 Network Driver
10568 11:09:04.527500 <6>[ 1.594658] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10569 11:09:04.534526 <6>[ 1.600844] igb: Intel(R) Gigabit Ethernet Network Driver
10570 11:09:04.541320 <6>[ 1.606495] igb: Copyright (c) 2007-2014 Intel Corporation.
10571 11:09:04.547821 <6>[ 1.612333] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10572 11:09:04.551018 <6>[ 1.618850] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10573 11:09:04.557871 <6>[ 1.625313] sky2: driver version 1.30
10574 11:09:04.564097 <6>[ 1.630311] VFIO - User Level meta-driver version: 0.3
10575 11:09:04.571193 <6>[ 1.638561] usbcore: registered new interface driver usb-storage
10576 11:09:04.577590 <6>[ 1.645013] usbcore: registered new device driver onboard-usb-hub
10577 11:09:04.586917 <6>[ 1.654194] mt6397-rtc mt6359-rtc: registered as rtc0
10578 11:09:04.596564 <6>[ 1.659660] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T11:06:16 UTC (1709463976)
10579 11:09:04.600192 <6>[ 1.669216] i2c_dev: i2c /dev entries driver
10580 11:09:04.616607 <6>[ 1.680934] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10581 11:09:04.637496 <6>[ 1.704934] cpu cpu0: EM: created perf domain
10582 11:09:04.640644 <6>[ 1.709872] cpu cpu4: EM: created perf domain
10583 11:09:04.647870 <6>[ 1.715518] sdhci: Secure Digital Host Controller Interface driver
10584 11:09:04.654455 <6>[ 1.721947] sdhci: Copyright(c) Pierre Ossman
10585 11:09:04.661712 <6>[ 1.726915] Synopsys Designware Multimedia Card Interface Driver
10586 11:09:04.668057 <6>[ 1.733554] sdhci-pltfm: SDHCI platform and OF driver helper
10587 11:09:04.671330 <6>[ 1.733675] mmc0: CQHCI version 5.10
10588 11:09:04.677744 <6>[ 1.743637] ledtrig-cpu: registered to indicate activity on CPUs
10589 11:09:04.684974 <6>[ 1.750722] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10590 11:09:04.691441 <6>[ 1.757785] usbcore: registered new interface driver usbhid
10591 11:09:04.694634 <6>[ 1.763608] usbhid: USB HID core driver
10592 11:09:04.701082 <6>[ 1.767803] spi_master spi0: will run message pump with realtime priority
10593 11:09:04.746862 <6>[ 1.807881] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10594 11:09:04.766211 <6>[ 1.823847] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10595 11:09:04.770152 <6>[ 1.837414] mmc0: Command Queue Engine enabled
10596 11:09:04.776693 <6>[ 1.842173] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10597 11:09:04.783588 <6>[ 1.849329] cros-ec-spi spi0.0: Chrome EC device registered
10598 11:09:04.786856 <6>[ 1.849640] mmcblk0: mmc0:0001 DA4128 116 GiB
10599 11:09:04.797603 <6>[ 1.864871] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10600 11:09:04.804774 <6>[ 1.872431] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10601 11:09:04.811842 <6>[ 1.878366] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10602 11:09:04.818221 <6>[ 1.884464] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10603 11:09:04.831744 <6>[ 1.896104] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10604 11:09:04.839142 <6>[ 1.906869] NET: Registered PF_PACKET protocol family
10605 11:09:04.846232 <6>[ 1.912334] 9pnet: Installing 9P2000 support
10606 11:09:04.849430 <5>[ 1.916917] Key type dns_resolver registered
10607 11:09:04.852580 <6>[ 1.922079] registered taskstats version 1
10608 11:09:04.859577 <5>[ 1.926504] Loading compiled-in X.509 certificates
10609 11:09:04.890620 <4>[ 1.951476] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 11:09:04.900270 <4>[ 1.962260] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 11:09:04.907454 <3>[ 1.972805] debugfs: File 'uA_load' in directory '/' already present!
10612 11:09:04.913796 <3>[ 1.979510] debugfs: File 'min_uV' in directory '/' already present!
10613 11:09:04.920554 <3>[ 1.986120] debugfs: File 'max_uV' in directory '/' already present!
10614 11:09:04.927143 <3>[ 1.992733] debugfs: File 'constraint_flags' in directory '/' already present!
10615 11:09:04.937940 <3>[ 2.002314] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10616 11:09:04.950660 <6>[ 2.018220] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10617 11:09:04.957701 <6>[ 2.025068] xhci-mtk 11200000.usb: xHCI Host Controller
10618 11:09:04.964033 <6>[ 2.030573] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10619 11:09:04.974217 <6>[ 2.038451] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10620 11:09:04.981198 <6>[ 2.047900] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10621 11:09:04.987311 <6>[ 2.054012] xhci-mtk 11200000.usb: xHCI Host Controller
10622 11:09:04.994029 <6>[ 2.059507] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10623 11:09:05.001182 <6>[ 2.067345] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10624 11:09:05.007762 <6>[ 2.075146] hub 1-0:1.0: USB hub found
10625 11:09:05.010913 <6>[ 2.079196] hub 1-0:1.0: 1 port detected
10626 11:09:05.020712 <6>[ 2.083535] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10627 11:09:05.024247 <6>[ 2.092389] hub 2-0:1.0: USB hub found
10628 11:09:05.027582 <6>[ 2.096419] hub 2-0:1.0: 1 port detected
10629 11:09:05.036753 <6>[ 2.104463] mtk-msdc 11f70000.mmc: Got CD GPIO
10630 11:09:05.049725 <6>[ 2.113747] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10631 11:09:05.056699 <6>[ 2.121804] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10632 11:09:05.066281 <4>[ 2.129724] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10633 11:09:05.076083 <6>[ 2.139253] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10634 11:09:05.082592 <6>[ 2.147330] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10635 11:09:05.089666 <6>[ 2.155342] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10636 11:09:05.099559 <6>[ 2.163264] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10637 11:09:05.105805 <6>[ 2.171082] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10638 11:09:05.116031 <6>[ 2.178898] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10639 11:09:05.126287 <6>[ 2.189364] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10640 11:09:05.132510 <6>[ 2.197725] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10641 11:09:05.142432 <6>[ 2.206070] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10642 11:09:05.149390 <6>[ 2.214409] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10643 11:09:05.159540 <6>[ 2.222746] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10644 11:09:05.165831 <6>[ 2.231085] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10645 11:09:05.176199 <6>[ 2.239421] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10646 11:09:05.182463 <6>[ 2.247758] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10647 11:09:05.192861 <6>[ 2.256098] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10648 11:09:05.199322 <6>[ 2.264435] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10649 11:09:05.209190 <6>[ 2.272771] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10650 11:09:05.215552 <6>[ 2.281109] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10651 11:09:05.225621 <6>[ 2.289445] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10652 11:09:05.232087 <6>[ 2.297783] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10653 11:09:05.242431 <6>[ 2.306120] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10654 11:09:05.248711 <6>[ 2.314858] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10655 11:09:05.255352 <6>[ 2.321819] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10656 11:09:05.261835 <6>[ 2.328586] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10657 11:09:05.268667 <6>[ 2.335352] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10658 11:09:05.275433 <6>[ 2.342284] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10659 11:09:05.285045 <6>[ 2.349138] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10660 11:09:05.294932 <6>[ 2.358267] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10661 11:09:05.305087 <6>[ 2.367385] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10662 11:09:05.314944 <6>[ 2.376678] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10663 11:09:05.321545 <6>[ 2.386146] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10664 11:09:05.331320 <6>[ 2.395614] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10665 11:09:05.341970 <6>[ 2.404733] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10666 11:09:05.351641 <6>[ 2.414199] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10667 11:09:05.361602 <6>[ 2.423321] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10668 11:09:05.371693 <6>[ 2.432616] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10669 11:09:05.381259 <6>[ 2.442782] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10670 11:09:05.391399 <6>[ 2.454466] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10671 11:09:05.397532 <6>[ 2.464168] Trying to probe devices needed for running init ...
10672 11:09:05.442941 <6>[ 2.507417] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10673 11:09:05.598136 <6>[ 2.665604] hub 1-1:1.0: USB hub found
10674 11:09:05.601145 <6>[ 2.670129] hub 1-1:1.0: 4 ports detected
10675 11:09:05.610843 <6>[ 2.678402] hub 1-1:1.0: USB hub found
10676 11:09:05.613825 <6>[ 2.682736] hub 1-1:1.0: 4 ports detected
10677 11:09:05.723498 <6>[ 2.787803] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10678 11:09:05.749463 <6>[ 2.816858] hub 2-1:1.0: USB hub found
10679 11:09:05.752239 <6>[ 2.821359] hub 2-1:1.0: 3 ports detected
10680 11:09:05.761820 <6>[ 2.829569] hub 2-1:1.0: USB hub found
10681 11:09:05.765051 <6>[ 2.834015] hub 2-1:1.0: 3 ports detected
10682 11:09:05.939011 <6>[ 3.003468] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10683 11:09:06.071645 <6>[ 3.138865] hub 1-1.4:1.0: USB hub found
10684 11:09:06.074897 <6>[ 3.143477] hub 1-1.4:1.0: 2 ports detected
10685 11:09:06.084132 <6>[ 3.151563] hub 1-1.4:1.0: USB hub found
10686 11:09:06.087086 <6>[ 3.156161] hub 1-1.4:1.0: 2 ports detected
10687 11:09:06.155300 <6>[ 3.219577] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10688 11:09:06.382873 <6>[ 3.447462] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10689 11:09:06.574952 <6>[ 3.639488] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10690 11:09:17.696198 <6>[ 14.768504] ALSA device list:
10691 11:09:17.702804 <6>[ 14.771793] No soundcards found.
10692 11:09:17.710985 <6>[ 14.779735] Freeing unused kernel memory: 8448K
10693 11:09:17.714279 <6>[ 14.785171] Run /init as init process
10694 11:09:17.723994 Loading, please wait...
10695 11:09:17.742190 Starting version 247.3-7+deb11u4
10696 11:09:17.926850 <6>[ 14.992397] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10697 11:09:17.956494 <6>[ 15.022352] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10698 11:09:17.960223 <6>[ 15.023376] remoteproc remoteproc0: scp is available
10699 11:09:17.970313 <3>[ 15.026651] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 11:09:17.976673 <3>[ 15.026662] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 11:09:17.986612 <3>[ 15.026665] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 11:09:17.992985 <6>[ 15.030446] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10703 11:09:17.999531 <6>[ 15.035506] remoteproc remoteproc0: powering up scp
10704 11:09:18.006280 <6>[ 15.043297] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10705 11:09:18.016122 <6>[ 15.051354] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10706 11:09:18.023188 <3>[ 15.052641] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 11:09:18.033309 <3>[ 15.052662] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 11:09:18.039464 <3>[ 15.052669] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 11:09:18.049882 <3>[ 15.052680] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 11:09:18.056917 <3>[ 15.052691] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 11:09:18.067158 <3>[ 15.054325] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 11:09:18.073630 <3>[ 15.057941] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 11:09:18.079813 <3>[ 15.057957] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 11:09:18.090124 <3>[ 15.057965] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 11:09:18.096476 <3>[ 15.060528] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 11:09:18.102972 <6>[ 15.068145] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10717 11:09:18.109595 <6>[ 15.078594] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10718 11:09:18.119722 <3>[ 15.082009] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10719 11:09:18.122830 <6>[ 15.093561] mc: Linux media interface: v0.10
10720 11:09:18.129620 <4>[ 15.095128] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10721 11:09:18.139905 <4>[ 15.095509] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10722 11:09:18.146193 <3>[ 15.098548] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 11:09:18.153083 <3>[ 15.098601] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 11:09:18.162932 <3>[ 15.098620] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 11:09:18.169852 <3>[ 15.100831] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 11:09:18.176235 <6>[ 15.102645] usbcore: registered new device driver r8152-cfgselector
10727 11:09:18.186287 <4>[ 15.105324] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10728 11:09:18.189503 <4>[ 15.105324] Fallback method does not support PEC.
10729 11:09:18.199375 <3>[ 15.121967] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10730 11:09:18.209190 <6>[ 15.188196] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10731 11:09:18.219274 <6>[ 15.191529] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10732 11:09:18.225588 <6>[ 15.193807] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10733 11:09:18.232127 <6>[ 15.193851] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10734 11:09:18.238813 <6>[ 15.193858] remoteproc remoteproc0: remote processor scp is now up
10735 11:09:18.248905 <6>[ 15.197874] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10736 11:09:18.256008 <6>[ 15.206363] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10737 11:09:18.265939 <6>[ 15.209120] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10738 11:09:18.275952 <4>[ 15.210458] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10739 11:09:18.282965 <4>[ 15.210468] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10740 11:09:18.289268 <6>[ 15.221740] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10741 11:09:18.296191 <6>[ 15.228658] pci_bus 0000:00: root bus resource [bus 00-ff]
10742 11:09:18.302577 <6>[ 15.228978] videodev: Linux video capture interface: v2.00
10743 11:09:18.309610 <6>[ 15.243814] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10744 11:09:18.316198 <6>[ 15.244683] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10745 11:09:18.322661 <6>[ 15.265380] Bluetooth: Core ver 2.22
10746 11:09:18.325999 <6>[ 15.267275] r8152 2-1.3:1.0 eth0: v1.12.13
10747 11:09:18.332630 <6>[ 15.267349] usbcore: registered new interface driver r8152
10748 11:09:18.342312 <6>[ 15.273586] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10749 11:09:18.348753 <6>[ 15.273637] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10750 11:09:18.352181 <6>[ 15.283748] NET: Registered PF_BLUETOOTH protocol family
10751 11:09:18.358866 <6>[ 15.292015] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10752 11:09:18.365406 <6>[ 15.292333] usbcore: registered new interface driver cdc_ether
10753 11:09:18.372259 <6>[ 15.299041] Bluetooth: HCI device and connection manager initialized
10754 11:09:18.379075 <6>[ 15.299733] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10755 11:09:18.392172 <6>[ 15.300892] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10756 11:09:18.398604 <6>[ 15.300982] usbcore: registered new interface driver uvcvideo
10757 11:09:18.402318 <6>[ 15.307616] pci 0000:00:00.0: supports D1 D2
10758 11:09:18.408662 <6>[ 15.308531] usbcore: registered new interface driver r8153_ecm
10759 11:09:18.415153 <6>[ 15.314015] Bluetooth: HCI socket layer initialized
10760 11:09:18.421551 <6>[ 15.315614] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10761 11:09:18.428478 <6>[ 15.323012] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10762 11:09:18.431584 <6>[ 15.329881] Bluetooth: L2CAP socket layer initialized
10763 11:09:18.441942 <6>[ 15.340271] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10764 11:09:18.445120 <6>[ 15.348294] Bluetooth: SCO socket layer initialized
10765 11:09:18.451882 <6>[ 15.348991] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10766 11:09:18.458335 <6>[ 15.356393] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10767 11:09:18.468332 <3>[ 15.376143] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10768 11:09:18.474670 <6>[ 15.384310] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10769 11:09:18.481177 <6>[ 15.415873] usbcore: registered new interface driver btusb
10770 11:09:18.491570 <4>[ 15.417048] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10771 11:09:18.498198 <3>[ 15.417063] Bluetooth: hci0: Failed to load firmware file (-2)
10772 11:09:18.504404 <3>[ 15.417070] Bluetooth: hci0: Failed to set up firmware (-2)
10773 11:09:18.514672 <4>[ 15.417077] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10774 11:09:18.521028 <6>[ 15.421486] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10775 11:09:18.527935 <6>[ 15.594989] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10776 11:09:18.534303 <6>[ 15.602569] pci 0000:01:00.0: supports D1 D2
10777 11:09:18.540888 <6>[ 15.607090] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10778 11:09:18.561741 <6>[ 15.627452] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10779 11:09:18.568189 <6>[ 15.634355] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10780 11:09:18.574884 <6>[ 15.642438] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10781 11:09:18.584847 <6>[ 15.650446] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10782 11:09:18.591624 <6>[ 15.658449] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10783 11:09:18.601661 <6>[ 15.666450] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10784 11:09:18.605156 <6>[ 15.674451] pci 0000:00:00.0: PCI bridge to [bus 01]
10785 11:09:18.614695 <6>[ 15.679667] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10786 11:09:18.621451 <6>[ 15.687795] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10787 11:09:18.628239 <6>[ 15.694635] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10788 11:09:18.634610 <6>[ 15.701431] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10789 11:09:18.650421 <5>[ 15.715895] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10790 11:09:18.672113 <5>[ 15.737952] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10791 11:09:18.678551 <5>[ 15.745359] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10792 11:09:18.688983 <4>[ 15.753791] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10793 11:09:18.691926 <6>[ 15.762673] cfg80211: failed to load regulatory.db
10794 11:09:18.742537 <6>[ 15.807973] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10795 11:09:18.748818 <6>[ 15.815472] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10796 11:09:18.773336 <6>[ 15.842127] mt7921e 0000:01:00.0: ASIC revision: 79610010
10797 11:09:18.876983 <6>[ 15.942795] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10798 11:09:18.880001 <6>[ 15.942795]
10799 11:09:18.895890 Begin: Loading essential drivers ... done.
10800 11:09:18.899620 Begin: Running /scripts/init-premount ... done.
10801 11:09:18.905813 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10802 11:09:18.915704 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10803 11:09:18.919325 Device /sys/class/net/enx00e04c787aaa found
10804 11:09:18.919408 done.
10805 11:09:18.989377 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10806 11:09:19.146711 <6>[ 16.212530] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10807 11:09:19.986914 <6>[ 17.055955] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10808 11:09:19.993488 <6>[ 17.062990] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10809 11:09:20.090188 IP-Config: no response after 2 secs - giving up
10810 11:09:20.134100 IP-Config: wlp1s0 hardware address d8:f3:bc:78:17:6f mtu 1500 DHCP
10811 11:09:20.849198 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10812 11:09:20.857269 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10813 11:09:20.864016 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10814 11:09:20.870743 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10815 11:09:20.877536 host : mt8192-asurada-spherion-r0-cbg-0
10816 11:09:20.883826 domain : lava-rack
10817 11:09:20.890308 rootserver: 192.168.201.1 rootpath:
10818 11:09:20.890395 filename :
10819 11:09:21.015976 done.
10820 11:09:21.022104 Begin: Running /scripts/nfs-bottom ... done.
10821 11:09:21.040106 Begin: Running /scripts/init-bottom ... done.
10822 11:09:22.216137 <6>[ 19.285824] NET: Registered PF_INET6 protocol family
10823 11:09:22.224263 <6>[ 19.293704] Segment Routing with IPv6
10824 11:09:22.227299 <6>[ 19.297697] In-situ OAM (IOAM) with IPv6
10825 11:09:22.374295 <30>[ 19.426961] systemd[1]: systemd 247.3-7+deb11u4 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10826 11:09:22.382219 <30>[ 19.451418] systemd[1]: Detected architecture arm64.
10827 11:09:22.402118
10828 11:09:22.405165 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10829 11:09:22.405288
10830 11:09:22.420296 <30>[ 19.489766] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10831 11:09:23.177496 <30>[ 20.243725] systemd[1]: Queued start job for default target Graphical Interface.
10832 11:09:23.208270 <30>[ 20.278026] systemd[1]: Created slice system-getty.slice.
10833 11:09:23.215078 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10834 11:09:23.230966 <30>[ 20.300803] systemd[1]: Created slice system-modprobe.slice.
10835 11:09:23.237546 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10836 11:09:23.256039 <30>[ 20.325566] systemd[1]: Created slice system-serial\x2dgetty.slice.
10837 11:09:23.266395 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10838 11:09:23.278616 <30>[ 20.348529] systemd[1]: Created slice User and Session Slice.
10839 11:09:23.285567 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10840 11:09:23.306423 <30>[ 20.372314] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10841 11:09:23.315843 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10842 11:09:23.334026 <30>[ 20.400213] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10843 11:09:23.340648 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10844 11:09:23.364964 <30>[ 20.427621] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10845 11:09:23.371283 <30>[ 20.439754] systemd[1]: Reached target Local Encrypted Volumes.
10846 11:09:23.377745 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10847 11:09:23.394418 <30>[ 20.464031] systemd[1]: Reached target Paths.
10848 11:09:23.397638 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10849 11:09:23.413990 <30>[ 20.483462] systemd[1]: Reached target Remote File Systems.
10850 11:09:23.420413 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10851 11:09:23.438232 <30>[ 20.507826] systemd[1]: Reached target Slices.
10852 11:09:23.444888 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10853 11:09:23.457783 <30>[ 20.527459] systemd[1]: Reached target Swap.
10854 11:09:23.460845 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10855 11:09:23.481863 <30>[ 20.547948] systemd[1]: Listening on initctl Compatibility Named Pipe.
10856 11:09:23.488211 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10857 11:09:23.494894 <30>[ 20.564001] systemd[1]: Listening on Journal Audit Socket.
10858 11:09:23.501088 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10859 11:09:23.519157 <30>[ 20.588680] systemd[1]: Listening on Journal Socket (/dev/log).
10860 11:09:23.525353 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10861 11:09:23.542320 <30>[ 20.612015] systemd[1]: Listening on Journal Socket.
10862 11:09:23.549049 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10863 11:09:23.566699 <30>[ 20.632855] systemd[1]: Listening on Network Service Netlink Socket.
10864 11:09:23.572932 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10865 11:09:23.588488 <30>[ 20.658033] systemd[1]: Listening on udev Control Socket.
10866 11:09:23.594939 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10867 11:09:23.610213 <30>[ 20.679893] systemd[1]: Listening on udev Kernel Socket.
10868 11:09:23.616936 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10869 11:09:23.657897 <30>[ 20.727526] systemd[1]: Mounting Huge Pages File System...
10870 11:09:23.664575 Mounting [0;1;39mHuge Pages File System[0m...
10871 11:09:23.682398 <30>[ 20.751799] systemd[1]: Mounting POSIX Message Queue File System...
10872 11:09:23.689495 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10873 11:09:23.710817 <30>[ 20.780052] systemd[1]: Mounting Kernel Debug File System...
10874 11:09:23.716823 Mounting [0;1;39mKernel Debug File System[0m...
10875 11:09:23.733910 <30>[ 20.799959] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10876 11:09:23.765604 <30>[ 20.831987] systemd[1]: Starting Create list of static device nodes for the current kernel...
10877 11:09:23.772518 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10878 11:09:23.794877 <30>[ 20.864265] systemd[1]: Starting Load Kernel Module configfs...
10879 11:09:23.801388 Starting [0;1;39mLoad Kernel Module configfs[0m...
10880 11:09:23.817228 <30>[ 20.886518] systemd[1]: Starting Load Kernel Module drm...
10881 11:09:23.823785 Starting [0;1;39mLoad Kernel Module drm[0m...
10882 11:09:23.842705 <30>[ 20.912240] systemd[1]: Starting Load Kernel Module fuse...
10883 11:09:23.848824 Starting [0;1;39mLoad Kernel Module fuse[0m...
10884 11:09:23.874937 <6>[ 20.944447] fuse: init (API version 7.37)
10885 11:09:23.884556 <30>[ 20.946153] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10886 11:09:23.926460 <30>[ 20.996011] systemd[1]: Starting Journal Service...
10887 11:09:23.929795 Starting [0;1;39mJournal Service[0m...
10888 11:09:23.952171 <30>[ 21.022055] systemd[1]: Starting Load Kernel Modules...
10889 11:09:23.959339 Starting [0;1;39mLoad Kernel Modules[0m...
10890 11:09:23.981339 <30>[ 21.047406] systemd[1]: Starting Remount Root and Kernel File Systems...
10891 11:09:23.987655 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10892 11:09:24.008988 <30>[ 21.078263] systemd[1]: Starting Coldplug All udev Devices...
10893 11:09:24.015422 Starting [0;1;39mColdplug All udev Devices[0m...
10894 11:09:24.035885 <30>[ 21.105700] systemd[1]: Mounted Huge Pages File System.
10895 11:09:24.042585 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10896 11:09:24.058501 <30>[ 21.128068] systemd[1]: Mounted POSIX Message Queue File System.
10897 11:09:24.065215 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10898 11:09:24.083588 <30>[ 21.152195] systemd[1]: Mounted Kernel Debug File System.
10899 11:09:24.093012 [[0;32m OK [<3>[ 21.158671] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 11:09:24.099933 0m] Mounted [0;1;39mKernel Debug File System[0m.
10901 11:09:24.118658 <30>[ 21.184532] systemd[1]: Finished Create list of static device nodes for the current kernel.
10902 11:09:24.135249 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current<3>[ 21.199580] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 11:09:24.135340 kernel[0m.
10904 11:09:24.150635 <30>[ 21.220365] systemd[1]: modprobe@configfs.service: Succeeded.
10905 11:09:24.157395 <30>[ 21.227205] systemd[1]: Finished Load Kernel Module configfs.
10906 11:09:24.184796 [[0;32m OK [<3>[ 21.248813] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 11:09:24.187868 0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10908 11:09:24.203024 <30>[ 21.272252] systemd[1]: modprobe@drm.service: Succeeded.
10909 11:09:24.210256 <30>[ 21.278574] systemd[1]: Finished Load Kernel Module drm.
10910 11:09:24.220113 [[0;32m OK [<3>[ 21.284760] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 11:09:24.223595 0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10912 11:09:24.239781 <30>[ 21.308988] systemd[1]: modprobe@fuse.service: Succeeded.
10913 11:09:24.246398 <30>[ 21.315928] systemd[1]: Finished Load Kernel Module fuse.
10914 11:09:24.256412 <3>[ 21.316157] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 11:09:24.263186 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10916 11:09:24.280783 <30>[ 21.349882] systemd[1]: Finished Load Kernel Modules.
10917 11:09:24.290835 <3>[ 21.352595] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 11:09:24.294013 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10919 11:09:24.312870 <30>[ 21.381722] systemd[1]: Finished Remount Root and Kernel File Systems.
10920 11:09:24.322764 <3>[ 21.387903] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 11:09:24.329006 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10922 11:09:24.353532 <3>[ 21.419765] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 11:09:24.376952 <30>[ 21.446251] systemd[1]: Mounting FUSE Control File System...
10924 11:09:24.386775 <3>[ 21.452105] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 11:09:24.393337 Mounting [0;1;39mFUSE Control File System[0m...
10926 11:09:24.412027 <30>[ 21.480586] systemd[1]: Mounting Kernel Configuration File System...
10927 11:09:24.421919 <3>[ 21.487236] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 11:09:24.428381 Mounting [0;1;39mKernel Configuration File System[0m...
10929 11:09:24.451256 <30>[ 21.516925] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10930 11:09:24.460892 <30>[ 21.526207] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10931 11:09:24.518844 <30>[ 21.588282] systemd[1]: Starting Load/Save Random Seed...
10932 11:09:24.525489 Starting [0;1;39mLoad/Save Random Seed[0m...
10933 11:09:24.545004 <4>[ 21.604688] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10934 11:09:24.554781 <3>[ 21.620335] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10935 11:09:24.558521 <30>[ 21.623575] systemd[1]: Starting Apply Kernel Variables...
10936 11:09:24.564675 Starting [0;1;39mApply Kernel Variables[0m...
10937 11:09:24.582182 <30>[ 21.651850] systemd[1]: Starting Create System Users...
10938 11:09:24.588941 Starting [0;1;39mCreate System Users[0m...
10939 11:09:24.604089 <30>[ 21.673805] systemd[1]: Started Journal Service.
10940 11:09:24.610700 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10941 11:09:24.634479 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10942 11:09:24.645869 See 'systemctl status systemd-udev-trigger.service' for details.
10943 11:09:24.662664 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10944 11:09:24.678144 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10945 11:09:24.695951 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10946 11:09:24.715769 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10947 11:09:24.732026 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10948 11:09:24.782471 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10949 11:09:24.800253 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10950 11:09:24.820213 <46>[ 21.886605] systemd-journald[290]: Received client request to flush runtime journal.
10951 11:09:24.875856 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10952 11:09:24.890144 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10953 11:09:24.906419 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10954 11:09:24.963319 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10955 11:09:26.225965 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10956 11:09:26.266578 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10957 11:09:26.288899 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10958 11:09:26.308815 Starting [0;1;39mNetwork Service[0m...
10959 11:09:26.653027 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10960 11:09:26.670453 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10961 11:09:26.720044 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10962 11:09:26.886459 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10963 11:09:26.914423 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10964 11:09:26.950471 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10965 11:09:27.031630 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10966 11:09:27.046377 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10967 11:09:27.062089 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10968 11:09:27.101740 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10969 11:09:27.146419 Starting [0;1;39mNetwork Name Resolution[0m...
10970 11:09:27.174094 Starting [0;1;39mNetwork Time Synchronization[0m...
10971 11:09:27.195039 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10972 11:09:27.246029 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10973 11:09:27.376648 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10974 11:09:27.394104 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10975 11:09:27.412713 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10976 11:09:27.425974 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10977 11:09:27.441618 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10978 11:09:27.554927 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10979 11:09:27.599885 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10980 11:09:27.641337 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10981 11:09:27.764251 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10982 11:09:27.777597 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10983 11:09:28.121274 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10984 11:09:28.137184 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10985 11:09:28.153679 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10986 11:09:28.194235 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10987 11:09:28.762098 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10988 11:09:28.882544 Starting [0;1;39mUser Login Management[0m...
10989 11:09:28.928220 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10990 11:09:28.950122 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10991 11:09:28.972650 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10992 11:09:29.022416 Starting [0;1;39mPermit User Sessions[0m...
10993 11:09:29.134648 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10994 11:09:29.151769 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10995 11:09:29.206892 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10996 11:09:29.224773 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10997 11:09:29.241361 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10998 11:09:29.258539 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10999 11:09:29.278648 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11000 11:09:29.294256 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11001 11:09:29.338225 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11002 11:09:29.400662 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11003 11:09:29.462269
11004 11:09:29.462373
11005 11:09:29.465253 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11006 11:09:29.465328
11007 11:09:29.468800 debian-bullseye-arm64 login: root (automatic login)
11008 11:09:29.468875
11009 11:09:29.468937
11010 11:09:29.780069 Linux debian-bullseye-arm64 6.1.80-cip16 #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024 aarch64
11011 11:09:29.780282
11012 11:09:29.786896 The programs included with the Debian GNU/Linux system are free software;
11013 11:09:29.793543 the exact distribution terms for each program are described in the
11014 11:09:29.796617 individual files in /usr/share/doc/*/copyright.
11015 11:09:29.796750
11016 11:09:29.803540 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11017 11:09:29.806575 permitted by applicable law.
11018 11:09:30.579400 Matched prompt #10: / #
11020 11:09:30.579861 Setting prompt string to ['/ #']
11021 11:09:30.580018 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11023 11:09:30.580405 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11024 11:09:30.580557 start: 2.2.6 expect-shell-connection (timeout 00:03:33) [common]
11025 11:09:30.580677 Setting prompt string to ['/ #']
11026 11:09:30.580787 Forcing a shell prompt, looking for ['/ #']
11028 11:09:30.631080 / #
11029 11:09:30.631231 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11030 11:09:30.631355 Waiting using forced prompt support (timeout 00:02:30)
11031 11:09:30.636206
11032 11:09:30.636537 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11033 11:09:30.636690 start: 2.2.7 export-device-env (timeout 00:03:33) [common]
11035 11:09:30.737081 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12925630/extract-nfsrootfs-uebyb0qu'
11036 11:09:30.742204 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12925630/extract-nfsrootfs-uebyb0qu'
11038 11:09:30.842772 / # export NFS_SERVER_IP='192.168.201.1'
11039 11:09:30.847906 export NFS_SERVER_IP='192.168.201.1'
11040 11:09:30.848258 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11041 11:09:30.848461 end: 2.2 depthcharge-retry (duration 00:01:27) [common]
11042 11:09:30.848615 end: 2 depthcharge-action (duration 00:01:27) [common]
11043 11:09:30.848770 start: 3 lava-test-retry (timeout 00:07:48) [common]
11044 11:09:30.848928 start: 3.1 lava-test-shell (timeout 00:07:48) [common]
11045 11:09:30.849062 Using namespace: common
11047 11:09:30.949456 / # #
11048 11:09:30.949629 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11049 11:09:30.954697 #
11050 11:09:30.955018 Using /lava-12925630
11052 11:09:31.055438 / # export SHELL=/bin/bash
11053 11:09:31.060793 export SHELL=/bin/bash
11055 11:09:31.161286 / # . /lava-12925630/environment
11056 11:09:31.166627 . /lava-12925630/environment
11058 11:09:31.271961 / # /lava-12925630/bin/lava-test-runner /lava-12925630/0
11059 11:09:31.272080 Test shell timeout: 10s (minimum of the action and connection timeout)
11060 11:09:31.276825 /lava-12925630/bin/lava-test-runner /lava-12925630/0
11061 11:09:31.513801 + export TESTRUN_ID=0_timesync-off
11062 11:09:31.517378 + TESTRUN_ID=0_timesync-off
11063 11:09:31.520546 + cd /lava-12925630/0/tests/0_timesync-off
11064 11:09:31.523692 ++ cat uuid
11065 11:09:31.523775 + UUID=12925630_1.6.2.3.1
11066 11:09:31.526759 + set +x
11067 11:09:31.530338 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12925630_1.6.2.3.1>
11068 11:09:31.530599 Received signal: <STARTRUN> 0_timesync-off 12925630_1.6.2.3.1
11069 11:09:31.530675 Starting test lava.0_timesync-off (12925630_1.6.2.3.1)
11070 11:09:31.530767 Skipping test definition patterns.
11071 11:09:31.533667 + systemctl stop systemd-timesyncd
11072 11:09:31.579742 + set +x
11073 11:09:31.583294 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12925630_1.6.2.3.1>
11074 11:09:31.583548 Received signal: <ENDRUN> 0_timesync-off 12925630_1.6.2.3.1
11075 11:09:31.583631 Ending use of test pattern.
11076 11:09:31.583693 Ending test lava.0_timesync-off (12925630_1.6.2.3.1), duration 0.05
11078 11:09:31.645255 + export TESTRUN_ID=1_kselftest-arm64
11079 11:09:31.645363 + TESTRUN_ID=1_kselftest-arm64
11080 11:09:31.651651 + cd /lava-12925630/0/tests/1_kselftest-arm64
11081 11:09:31.651739 ++ cat uuid
11082 11:09:31.654900 + UUID=12925630_1.6.2.3.5
11083 11:09:31.654983 + set +x
11084 11:09:31.658134 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 12925630_1.6.2.3.5>
11085 11:09:31.658426 Received signal: <STARTRUN> 1_kselftest-arm64 12925630_1.6.2.3.5
11086 11:09:31.658496 Starting test lava.1_kselftest-arm64 (12925630_1.6.2.3.5)
11087 11:09:31.658576 Skipping test definition patterns.
11088 11:09:31.661337 + cd ./automated/linux/kselftest/
11089 11:09:31.687908 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11090 11:09:31.712125 INFO: install_deps skipped
11091 11:09:31.824457 --2024-03-03 11:06:42-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11092 11:09:31.985433 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11093 11:09:32.118575 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11094 11:09:32.250796 HTTP request sent, awaiting response... 200 OK
11095 11:09:32.254626 Length: 1746012 (1.7M) [application/octet-stream]
11096 11:09:32.257605 Saving to: 'kselftest.tar.xz'
11097 11:09:32.257687
11098 11:09:32.257752
11099 11:09:32.516091 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11100 11:09:32.781361 kselftest.tar.xz 2%[ ] 43.57K 165KB/s
11101 11:09:33.229304 kselftest.tar.xz 12%[=> ] 214.67K 406KB/s
11102 11:09:33.313283 kselftest.tar.xz 49%[========> ] 836.37K 856KB/s
11103 11:09:33.319823 kselftest.tar.xz 100%[===================>] 1.67M 1.57MB/s in 1.1s
11104 11:09:33.319940
11105 11:09:33.472591 2024-03-03 11:06:44 (1.57 MB/s) - 'kselftest.tar.xz' saved [1746012/1746012]
11106 11:09:33.472751
11107 11:09:37.313123 skiplist:
11108 11:09:37.316329 ========================================
11109 11:09:37.319806 ========================================
11110 11:09:37.354161 arm64:tags_test
11111 11:09:37.357176 arm64:run_tags_test.sh
11112 11:09:37.357304 arm64:fake_sigreturn_bad_magic
11113 11:09:37.360803 arm64:fake_sigreturn_bad_size
11114 11:09:37.363923 arm64:fake_sigreturn_bad_size_for_magic0
11115 11:09:37.367115 arm64:fake_sigreturn_duplicated_fpsimd
11116 11:09:37.370813 arm64:fake_sigreturn_misaligned_sp
11117 11:09:37.373946 arm64:fake_sigreturn_missing_fpsimd
11118 11:09:37.377045 arm64:fake_sigreturn_sme_change_vl
11119 11:09:37.380707 arm64:fake_sigreturn_sve_change_vl
11120 11:09:37.383963 arm64:mangle_pstate_invalid_compat_toggle
11121 11:09:37.387051 arm64:mangle_pstate_invalid_daif_bits
11122 11:09:37.390176 arm64:mangle_pstate_invalid_mode_el1h
11123 11:09:37.393801 arm64:mangle_pstate_invalid_mode_el1t
11124 11:09:37.396974 arm64:mangle_pstate_invalid_mode_el2h
11125 11:09:37.400079 arm64:mangle_pstate_invalid_mode_el2t
11126 11:09:37.403861 arm64:mangle_pstate_invalid_mode_el3h
11127 11:09:37.406836 arm64:mangle_pstate_invalid_mode_el3t
11128 11:09:37.410516 arm64:sme_trap_no_sm
11129 11:09:37.413580 arm64:sme_trap_non_streaming
11130 11:09:37.413700 arm64:sme_trap_za
11131 11:09:37.416632 arm64:sme_vl
11132 11:09:37.416753 arm64:ssve_regs
11133 11:09:37.420056 arm64:sve_regs
11134 11:09:37.420171 arm64:sve_vl
11135 11:09:37.420277 arm64:za_no_regs
11136 11:09:37.423475 arm64:za_regs
11137 11:09:37.423594 arm64:pac
11138 11:09:37.427107 arm64:fp-stress
11139 11:09:37.427228 arm64:sve-ptrace
11140 11:09:37.430156 arm64:sve-probe-vls
11141 11:09:37.430278 arm64:vec-syscfg
11142 11:09:37.430390 arm64:za-fork
11143 11:09:37.433568 arm64:za-ptrace
11144 11:09:37.436657 arm64:check_buffer_fill
11145 11:09:37.436775 arm64:check_child_memory
11146 11:09:37.440200 arm64:check_gcr_el1_cswitch
11147 11:09:37.443345 arm64:check_ksm_options
11148 11:09:37.443464 arm64:check_mmap_options
11149 11:09:37.446695 arm64:check_prctl
11150 11:09:37.450040 arm64:check_tags_inclusion
11151 11:09:37.450159 arm64:check_user_mem
11152 11:09:37.450270 arm64:btitest
11153 11:09:37.453380 arm64:nobtitest
11154 11:09:37.453501 arm64:hwcap
11155 11:09:37.456927 arm64:ptrace
11156 11:09:37.457046 arm64:syscall-abi
11157 11:09:37.457156 arm64:tpidr2
11158 11:09:37.463501 ============== Tests to run ===============
11159 11:09:37.463639 arm64:tags_test
11160 11:09:37.466812 arm64:run_tags_test.sh
11161 11:09:37.469674 arm64:fake_sigreturn_bad_magic
11162 11:09:37.469803 arm64:fake_sigreturn_bad_size
11163 11:09:37.473333 arm64:fake_sigreturn_bad_size_for_magic0
11164 11:09:37.479617 arm64:fake_sigreturn_duplicated_fpsimd
11165 11:09:37.479739 arm64:fake_sigreturn_misaligned_sp
11166 11:09:37.483492 arm64:fake_sigreturn_missing_fpsimd
11167 11:09:37.486580 arm64:fake_sigreturn_sme_change_vl
11168 11:09:37.489741 arm64:fake_sigreturn_sve_change_vl
11169 11:09:37.493624 arm64:mangle_pstate_invalid_compat_toggle
11170 11:09:37.496637 arm64:mangle_pstate_invalid_daif_bits
11171 11:09:37.499840 arm64:mangle_pstate_invalid_mode_el1h
11172 11:09:37.503654 arm64:mangle_pstate_invalid_mode_el1t
11173 11:09:37.506719 arm64:mangle_pstate_invalid_mode_el2h
11174 11:09:37.513059 arm64:mangle_pstate_invalid_mode_el2t
11175 11:09:37.517136 arm64:mangle_pstate_invalid_mode_el3h
11176 11:09:37.517258 arm64:mangle_pstate_invalid_mode_el3t
11177 11:09:37.520340 arm64:sme_trap_no_sm
11178 11:09:37.523395 arm64:sme_trap_non_streaming
11179 11:09:37.523515 arm64:sme_trap_za
11180 11:09:37.526962 arm64:sme_vl
11181 11:09:37.527083 arm64:ssve_regs
11182 11:09:37.529826 arm64:sve_regs
11183 11:09:37.529912 arm64:sve_vl
11184 11:09:37.529978 arm64:za_no_regs
11185 11:09:37.533478 arm64:za_regs
11186 11:09:37.533558 arm64:pac
11187 11:09:37.536638 arm64:fp-stress
11188 11:09:37.536745 arm64:sve-ptrace
11189 11:09:37.540261 arm64:sve-probe-vls
11190 11:09:37.540386 arm64:vec-syscfg
11191 11:09:37.540452 arm64:za-fork
11192 11:09:37.543206 arm64:za-ptrace
11193 11:09:37.546304 arm64:check_buffer_fill
11194 11:09:37.546385 arm64:check_child_memory
11195 11:09:37.549947 arm64:check_gcr_el1_cswitch
11196 11:09:37.552932 arm64:check_ksm_options
11197 11:09:37.553016 arm64:check_mmap_options
11198 11:09:37.556511 arm64:check_prctl
11199 11:09:37.559843 arm64:check_tags_inclusion
11200 11:09:37.559923 arm64:check_user_mem
11201 11:09:37.563244 arm64:btitest
11202 11:09:37.563324 arm64:nobtitest
11203 11:09:37.563388 arm64:hwcap
11204 11:09:37.566135 arm64:ptrace
11205 11:09:37.566216 arm64:syscall-abi
11206 11:09:37.569605 arm64:tpidr2
11207 11:09:37.572933 ===========End Tests to run ===============
11208 11:09:37.573058 shardfile-arm64 pass
11209 11:09:37.761046 <12>[ 34.832117] kselftest: Running tests in arm64
11210 11:09:37.771130 TAP version 13
11211 11:09:37.783013 1..48
11212 11:09:37.796946 # selftests: arm64: tags_test
11213 11:09:38.220952 ok 1 selftests: arm64: tags_test
11214 11:09:38.234886 # selftests: arm64: run_tags_test.sh
11215 11:09:38.271407 # --------------------
11216 11:09:38.274372 # running tags test
11217 11:09:38.274455 # --------------------
11218 11:09:38.278135 # [PASS]
11219 11:09:38.281410 ok 2 selftests: arm64: run_tags_test.sh
11220 11:09:38.292613 # selftests: arm64: fake_sigreturn_bad_magic
11221 11:09:38.354635 # Registered handlers for all signals.
11222 11:09:38.354773 # Detected MINSTKSIGSZ:4720
11223 11:09:38.358149 # Testcase initialized.
11224 11:09:38.361268 # uc context validated.
11225 11:09:38.364827 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11226 11:09:38.367700 # Handled SIG_COPYCTX
11227 11:09:38.367781 # Available space:3568
11228 11:09:38.374614 # Using badly built context - ERR: BAD MAGIC !
11229 11:09:38.381040 # SIG_OK -- SP:0xFFFFDAF82020 si_addr@:0xffffdaf82020 si_code:2 token@:0xffffdaf80dc0 offset:-4704
11230 11:09:38.384631 # ==>> completed. PASS(1)
11231 11:09:38.391062 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11232 11:09:38.397810 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDAF80DC0
11233 11:09:38.401448 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11234 11:09:38.407582 # selftests: arm64: fake_sigreturn_bad_size
11235 11:09:38.431235 # Registered handlers for all signals.
11236 11:09:38.431331 # Detected MINSTKSIGSZ:4720
11237 11:09:38.434512 # Testcase initialized.
11238 11:09:38.438261 # uc context validated.
11239 11:09:38.441522 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11240 11:09:38.444592 # Handled SIG_COPYCTX
11241 11:09:38.444673 # Available space:3568
11242 11:09:38.447797 # uc context validated.
11243 11:09:38.454628 # Using badly built context - ERR: Bad size for esr_context
11244 11:09:38.461065 # SIG_OK -- SP:0xFFFFC9BF4F90 si_addr@:0xffffc9bf4f90 si_code:2 token@:0xffffc9bf3d30 offset:-4704
11245 11:09:38.464898 # ==>> completed. PASS(1)
11246 11:09:38.471059 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11247 11:09:38.478079 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC9BF3D30
11248 11:09:38.481282 ok 4 selftests: arm64: fake_sigreturn_bad_size
11249 11:09:38.488034 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11250 11:09:38.494894 # Registered handlers for all signals.
11251 11:09:38.494976 # Detected MINSTKSIGSZ:4720
11252 11:09:38.498110 # Testcase initialized.
11253 11:09:38.501210 # uc context validated.
11254 11:09:38.504926 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11255 11:09:38.507903 # Handled SIG_COPYCTX
11256 11:09:38.507983 # Available space:3568
11257 11:09:38.514329 # Using badly built context - ERR: Bad size for terminator
11258 11:09:38.524437 # SIG_OK -- SP:0xFFFFD83339B0 si_addr@:0xffffd83339b0 si_code:2 token@:0xffffd8332750 offset:-4704
11259 11:09:38.524520 # ==>> completed. PASS(1)
11260 11:09:38.534477 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11261 11:09:38.541235 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD8332750
11262 11:09:38.544665 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11263 11:09:38.551155 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11264 11:09:38.558730 # Registered handlers for all signals.
11265 11:09:38.558813 # Detected MINSTKSIGSZ:4720
11266 11:09:38.561833 # Testcase initialized.
11267 11:09:38.565606 # uc context validated.
11268 11:09:38.568446 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11269 11:09:38.571792 # Handled SIG_COPYCTX
11270 11:09:38.571875 # Available space:3568
11271 11:09:38.578511 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11272 11:09:38.588531 # SIG_OK -- SP:0xFFFFE97276C0 si_addr@:0xffffe97276c0 si_code:2 token@:0xffffe9726460 offset:-4704
11273 11:09:38.588641 # ==>> completed. PASS(1)
11274 11:09:38.598585 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11275 11:09:38.605445 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE9726460
11276 11:09:38.608128 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11277 11:09:38.611409 # selftests: arm64: fake_sigreturn_misaligned_sp
11278 11:09:38.627630 # Registered handlers for all signals.
11279 11:09:38.627713 # Detected MINSTKSIGSZ:4720
11280 11:09:38.630542 # Testcase initialized.
11281 11:09:38.633889 # uc context validated.
11282 11:09:38.637588 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11283 11:09:38.640783 # Handled SIG_COPYCTX
11284 11:09:38.647096 # SIG_OK -- SP:0xFFFFEE86D023 si_addr@:0xffffee86d023 si_code:2 token@:0xffffee86d023 offset:0
11285 11:09:38.650770 # ==>> completed. PASS(1)
11286 11:09:38.657313 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11287 11:09:38.664025 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEE86D023
11288 11:09:38.667242 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11289 11:09:38.673993 # selftests: arm64: fake_sigreturn_missing_fpsimd
11290 11:09:38.698989 # Registered handlers for all signals.
11291 11:09:38.699073 # Detected MINSTKSIGSZ:4720
11292 11:09:38.702281 # Testcase initialized.
11293 11:09:38.705303 # uc context validated.
11294 11:09:38.708283 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11295 11:09:38.711911 # Handled SIG_COPYCTX
11296 11:09:38.715507 # Mangling template header. Spare space:4096
11297 11:09:38.718556 # Using badly built context - ERR: Missing FPSIMD
11298 11:09:38.728651 # SIG_OK -- SP:0xFFFFDD4C7EA0 si_addr@:0xffffdd4c7ea0 si_code:2 token@:0xffffdd4c6c40 offset:-4704
11299 11:09:38.731505 # ==>> completed. PASS(1)
11300 11:09:38.738214 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11301 11:09:38.745295 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDD4C6C40
11302 11:09:38.748162 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11303 11:09:38.754507 # selftests: arm64: fake_sigreturn_sme_change_vl
11304 11:09:38.766160 # Registered handlers for all signals.
11305 11:09:38.766241 # Detected MINSTKSIGSZ:4720
11306 11:09:38.769612 # ==>> completed. SKIP.
11307 11:09:38.776068 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11308 11:09:38.779546 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11309 11:09:38.785997 # selftests: arm64: fake_sigreturn_sve_change_vl
11310 11:09:38.848501 # Registered handlers for all signals.
11311 11:09:38.848597 # Detected MINSTKSIGSZ:4720
11312 11:09:38.851829 # ==>> completed. SKIP.
11313 11:09:38.857908 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11314 11:09:38.861742 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11315 11:09:38.868019 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11316 11:09:38.901533 # Registered handlers for all signals.
11317 11:09:38.901619 # Detected MINSTKSIGSZ:4720
11318 11:09:38.904497 # Testcase initialized.
11319 11:09:38.907944 # uc context validated.
11320 11:09:38.908025 # Handled SIG_TRIG
11321 11:09:38.917872 # SIG_OK -- SP:0xFFFFE669A1F0 si_addr@:0xffffe669a1f0 si_code:2 token@:(nil) offset:-281474547425776
11322 11:09:38.921173 # ==>> completed. PASS(1)
11323 11:09:38.927865 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11324 11:09:38.934382 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11325 11:09:38.937413 # selftests: arm64: mangle_pstate_invalid_daif_bits
11326 11:09:38.965158 # Registered handlers for all signals.
11327 11:09:38.965241 # Detected MINSTKSIGSZ:4720
11328 11:09:38.968214 # Testcase initialized.
11329 11:09:38.972016 # uc context validated.
11330 11:09:38.972097 # Handled SIG_TRIG
11331 11:09:38.982041 # SIG_OK -- SP:0xFFFFE0D2BD20 si_addr@:0xffffe0d2bd20 si_code:2 token@:(nil) offset:-281474453650720
11332 11:09:38.985206 # ==>> completed. PASS(1)
11333 11:09:38.991322 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11334 11:09:38.995091 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11335 11:09:39.001841 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11336 11:09:39.033390 # Registered handlers for all signals.
11337 11:09:39.033475 # Detected MINSTKSIGSZ:4720
11338 11:09:39.037023 # Testcase initialized.
11339 11:09:39.039967 # uc context validated.
11340 11:09:39.040074 # Handled SIG_TRIG
11341 11:09:39.049982 # SIG_OK -- SP:0xFFFFD47A5C70 si_addr@:0xffffd47a5c70 si_code:2 token@:(nil) offset:-281474246532208
11342 11:09:39.053225 # ==>> completed. PASS(1)
11343 11:09:39.060217 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11344 11:09:39.063632 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11345 11:09:39.070029 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11346 11:09:39.100963 # Registered handlers for all signals.
11347 11:09:39.101046 # Detected MINSTKSIGSZ:4720
11348 11:09:39.104078 # Testcase initialized.
11349 11:09:39.107761 # uc context validated.
11350 11:09:39.107842 # Handled SIG_TRIG
11351 11:09:39.117565 # SIG_OK -- SP:0xFFFFC5866380 si_addr@:0xffffc5866380 si_code:2 token@:(nil) offset:-281473995662208
11352 11:09:39.120815 # ==>> completed. PASS(1)
11353 11:09:39.127490 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11354 11:09:39.130535 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11355 11:09:39.137179 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11356 11:09:39.177190 # Registered handlers for all signals.
11357 11:09:39.177283 # Detected MINSTKSIGSZ:4720
11358 11:09:39.180258 # Testcase initialized.
11359 11:09:39.184014 # uc context validated.
11360 11:09:39.184121 # Handled SIG_TRIG
11361 11:09:39.194015 # SIG_OK -- SP:0xFFFFF55356E0 si_addr@:0xfffff55356e0 si_code:2 token@:(nil) offset:-281474797623008
11362 11:09:39.197259 # ==>> completed. PASS(1)
11363 11:09:39.203530 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11364 11:09:39.207345 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11365 11:09:39.213554 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11366 11:09:39.257304 # Registered handlers for all signals.
11367 11:09:39.257391 # Detected MINSTKSIGSZ:4720
11368 11:09:39.260592 # Testcase initialized.
11369 11:09:39.263958 # uc context validated.
11370 11:09:39.264039 # Handled SIG_TRIG
11371 11:09:39.274206 # SIG_OK -- SP:0xFFFFE5E0EAB0 si_addr@:0xffffe5e0eab0 si_code:2 token@:(nil) offset:-281474538465968
11372 11:09:39.277361 # ==>> completed. PASS(1)
11373 11:09:39.283573 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11374 11:09:39.286922 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11375 11:09:39.293341 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11376 11:09:39.331900 # Registered handlers for all signals.
11377 11:09:39.331985 # Detected MINSTKSIGSZ:4720
11378 11:09:39.334769 # Testcase initialized.
11379 11:09:39.338309 # uc context validated.
11380 11:09:39.338390 # Handled SIG_TRIG
11381 11:09:39.348442 # SIG_OK -- SP:0xFFFFDB8F1670 si_addr@:0xffffdb8f1670 si_code:2 token@:(nil) offset:-281474365331056
11382 11:09:39.351601 # ==>> completed. PASS(1)
11383 11:09:39.358374 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11384 11:09:39.361603 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11385 11:09:39.368139 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11386 11:09:39.392789 # Registered handlers for all signals.
11387 11:09:39.392872 # Detected MINSTKSIGSZ:4720
11388 11:09:39.395976 # Testcase initialized.
11389 11:09:39.399642 # uc context validated.
11390 11:09:39.399722 # Handled SIG_TRIG
11391 11:09:39.409348 # SIG_OK -- SP:0xFFFFF2E8E030 si_addr@:0xfffff2e8e030 si_code:2 token@:(nil) offset:-281474757091376
11392 11:09:39.412770 # ==>> completed. PASS(1)
11393 11:09:39.419093 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11394 11:09:39.422856 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11395 11:09:39.425365 # selftests: arm64: sme_trap_no_sm
11396 11:09:39.465412 # Registered handlers for all signals.
11397 11:09:39.465494 # Detected MINSTKSIGSZ:4720
11398 11:09:39.468591 # ==>> completed. SKIP.
11399 11:09:39.478535 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11400 11:09:39.481653 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11401 11:09:39.484836 # selftests: arm64: sme_trap_non_streaming
11402 11:09:39.538526 # Registered handlers for all signals.
11403 11:09:39.538621 # Detected MINSTKSIGSZ:4720
11404 11:09:39.541490 # ==>> completed. SKIP.
11405 11:09:39.551710 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11406 11:09:39.558090 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11407 11:09:39.561250 # selftests: arm64: sme_trap_za
11408 11:09:39.608687 # Registered handlers for all signals.
11409 11:09:39.608775 # Detected MINSTKSIGSZ:4720
11410 11:09:39.612173 # Testcase initialized.
11411 11:09:39.621828 # SIG_OK -- SP:0xFFFFE6A23080 si_addr@:0xaaaab17c2510 si_code:1 token@:(nil) offset:-187650098865424
11412 11:09:39.621911 # ==>> completed. PASS(1)
11413 11:09:39.631816 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11414 11:09:39.635052 ok 21 selftests: arm64: sme_trap_za
11415 11:09:39.635127 # selftests: arm64: sme_vl
11416 11:09:39.678036 # Registered handlers for all signals.
11417 11:09:39.678129 # Detected MINSTKSIGSZ:4720
11418 11:09:39.681237 # ==>> completed. SKIP.
11419 11:09:39.684463 # # SME VL :: Check that we get the right SME VL reported
11420 11:09:39.687646 ok 22 selftests: arm64: sme_vl # SKIP
11421 11:09:39.694375 # selftests: arm64: ssve_regs
11422 11:09:39.751587 # Registered handlers for all signals.
11423 11:09:39.751680 # Detected MINSTKSIGSZ:4720
11424 11:09:39.754624 # ==>> completed. SKIP.
11425 11:09:39.761374 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11426 11:09:39.764570 ok 23 selftests: arm64: ssve_regs # SKIP
11427 11:09:39.767768 # selftests: arm64: sve_regs
11428 11:09:39.813286 # Registered handlers for all signals.
11429 11:09:39.813372 # Detected MINSTKSIGSZ:4720
11430 11:09:39.816525 # ==>> completed. SKIP.
11431 11:09:39.823647 # # SVE registers :: Check that we get the right SVE registers reported
11432 11:09:39.826383 ok 24 selftests: arm64: sve_regs # SKIP
11433 11:09:39.830001 # selftests: arm64: sve_vl
11434 11:09:39.881439 # Registered handlers for all signals.
11435 11:09:39.881528 # Detected MINSTKSIGSZ:4720
11436 11:09:39.884906 # ==>> completed. SKIP.
11437 11:09:39.891263 # # SVE VL :: Check that we get the right SVE VL reported
11438 11:09:39.894850 ok 25 selftests: arm64: sve_vl # SKIP
11439 11:09:39.897842 # selftests: arm64: za_no_regs
11440 11:09:39.933335 # Registered handlers for all signals.
11441 11:09:39.933419 # Detected MINSTKSIGSZ:4720
11442 11:09:39.936911 # ==>> completed. SKIP.
11443 11:09:39.943586 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11444 11:09:39.946633 ok 26 selftests: arm64: za_no_regs # SKIP
11445 11:09:39.951189 # selftests: arm64: za_regs
11446 11:09:40.009383 # Registered handlers for all signals.
11447 11:09:40.009472 # Detected MINSTKSIGSZ:4720
11448 11:09:40.012780 # ==>> completed. SKIP.
11449 11:09:40.019104 # # ZA register :: Check that we get the right ZA registers reported
11450 11:09:40.022200 ok 27 selftests: arm64: za_regs # SKIP
11451 11:09:40.025667 # selftests: arm64: pac
11452 11:09:40.074239 # TAP version 13
11453 11:09:40.074331 # 1..7
11454 11:09:40.077580 # # Starting 7 tests from 1 test cases.
11455 11:09:40.081295 # # RUN global.corrupt_pac ...
11456 11:09:40.084222 # # SKIP PAUTH not enabled
11457 11:09:40.087567 # # OK global.corrupt_pac
11458 11:09:40.090883 # ok 1 # SKIP PAUTH not enabled
11459 11:09:40.097787 # # RUN global.pac_instructions_not_nop ...
11460 11:09:40.101019 # # SKIP PAUTH not enabled
11461 11:09:40.104223 # # OK global.pac_instructions_not_nop
11462 11:09:40.107420 # ok 2 # SKIP PAUTH not enabled
11463 11:09:40.113823 # # RUN global.pac_instructions_not_nop_generic ...
11464 11:09:40.117635 # # SKIP Generic PAUTH not enabled
11465 11:09:40.120651 # # OK global.pac_instructions_not_nop_generic
11466 11:09:40.123871 # ok 3 # SKIP Generic PAUTH not enabled
11467 11:09:40.130443 # # RUN global.single_thread_different_keys ...
11468 11:09:40.134207 # # SKIP PAUTH not enabled
11469 11:09:40.140254 # # OK global.single_thread_different_keys
11470 11:09:40.140382 # ok 4 # SKIP PAUTH not enabled
11471 11:09:40.147389 # # RUN global.exec_changed_keys ...
11472 11:09:40.150569 # # SKIP PAUTH not enabled
11473 11:09:40.154087 # # OK global.exec_changed_keys
11474 11:09:40.157244 # ok 5 # SKIP PAUTH not enabled
11475 11:09:40.160453 # # RUN global.context_switch_keep_keys ...
11476 11:09:40.163520 # # SKIP PAUTH not enabled
11477 11:09:40.170499 # # OK global.context_switch_keep_keys
11478 11:09:40.170582 # ok 6 # SKIP PAUTH not enabled
11479 11:09:40.177439 # # RUN global.context_switch_keep_keys_generic ...
11480 11:09:40.180537 # # SKIP Generic PAUTH not enabled
11481 11:09:40.187213 # # OK global.context_switch_keep_keys_generic
11482 11:09:40.190557 # ok 7 # SKIP Generic PAUTH not enabled
11483 11:09:40.193781 # # PASSED: 7 / 7 tests passed.
11484 11:09:40.196983 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11485 11:09:40.200173 ok 28 selftests: arm64: pac
11486 11:09:40.203321 # selftests: arm64: fp-stress
11487 11:09:49.083434 <6>[ 46.159249] vpu: disabling
11488 11:09:49.086982 <6>[ 46.162297] vproc2: disabling
11489 11:09:49.090520 <6>[ 46.165569] vproc1: disabling
11490 11:09:49.093340 <6>[ 46.168842] vaud18: disabling
11491 11:09:49.099949 <6>[ 46.172261] vsram_others: disabling
11492 11:09:49.100033 <6>[ 46.176147] va09: disabling
11493 11:09:49.106800 <6>[ 46.179262] vsram_md: disabling
11494 11:09:49.106883 <6>[ 46.182755] Vgpu: disabling
11495 11:09:50.134680 # TAP version 13
11496 11:09:50.134838 # 1..16
11497 11:09:50.137789 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11498 11:09:50.141297 # # Will run for 10s
11499 11:09:50.141380 # # Started FPSIMD-0-0
11500 11:09:50.144737 # # Started FPSIMD-0-1
11501 11:09:50.147802 # # Started FPSIMD-1-0
11502 11:09:50.147885 # # Started FPSIMD-1-1
11503 11:09:50.150919 # # Started FPSIMD-2-0
11504 11:09:50.151001 # # Started FPSIMD-2-1
11505 11:09:50.154365 # # Started FPSIMD-3-0
11506 11:09:50.158041 # # Started FPSIMD-3-1
11507 11:09:50.158123 # # Started FPSIMD-4-0
11508 11:09:50.161423 # # Started FPSIMD-4-1
11509 11:09:50.164444 # # Started FPSIMD-5-0
11510 11:09:50.164527 # # Started FPSIMD-5-1
11511 11:09:50.167764 # # Started FPSIMD-6-0
11512 11:09:50.171099 # # Started FPSIMD-6-1
11513 11:09:50.171181 # # Started FPSIMD-7-0
11514 11:09:50.174593 # # Started FPSIMD-7-1
11515 11:09:50.177449 # # FPSIMD-3-0: Vector length: 128 bits
11516 11:09:50.181309 # # FPSIMD-3-0: PID: 1161
11517 11:09:50.184467 # # FPSIMD-1-1: Vector length: 128 bits
11518 11:09:50.184550 # # FPSIMD-1-1: PID: 1158
11519 11:09:50.187518 # # FPSIMD-1-0: Vector length: 128 bits
11520 11:09:50.191294 # # FPSIMD-1-0: PID: 1157
11521 11:09:50.194503 # # FPSIMD-0-1: Vector length: 128 bits
11522 11:09:50.197674 # # FPSIMD-0-1: PID: 1156
11523 11:09:50.200915 # # FPSIMD-2-1: Vector length: 128 bits
11524 11:09:50.204453 # # FPSIMD-2-1: PID: 1160
11525 11:09:50.207756 # # FPSIMD-3-1: Vector length: 128 bits
11526 11:09:50.207838 # # FPSIMD-3-1: PID: 1162
11527 11:09:50.214094 # # FPSIMD-6-1: Vector length: 128 bits
11528 11:09:50.214177 # # FPSIMD-6-1: PID: 1168
11529 11:09:50.217557 # # FPSIMD-7-1: Vector length: 128 bits
11530 11:09:50.220716 # # FPSIMD-7-1: PID: 1170
11531 11:09:50.224215 # # FPSIMD-5-0: Vector length: 128 bits
11532 11:09:50.227191 # # FPSIMD-5-0: PID: 1165
11533 11:09:50.230507 # # FPSIMD-4-1: Vector length: 128 bits
11534 11:09:50.234307 # # FPSIMD-4-1: PID: 1164
11535 11:09:50.237200 # # FPSIMD-2-0: Vector length: 128 bits
11536 11:09:50.237286 # # FPSIMD-2-0: PID: 1159
11537 11:09:50.240937 # # FPSIMD-4-0: Vector length: 128 bits
11538 11:09:50.243993 # # FPSIMD-4-0: PID: 1163
11539 11:09:50.247018 # # FPSIMD-6-0: Vector length: 128 bits
11540 11:09:50.250413 # # FPSIMD-6-0: PID: 1167
11541 11:09:50.253840 # # FPSIMD-5-1: Vector length: 128 bits
11542 11:09:50.257001 # # FPSIMD-5-1: PID: 1166
11543 11:09:50.260634 # # FPSIMD-0-0: Vector length: 128 bits
11544 11:09:50.260717 # # FPSIMD-0-0: PID: 1155
11545 11:09:50.266946 # # FPSIMD-7-0: Vector length: 128 bits
11546 11:09:50.267028 # # FPSIMD-7-0: PID: 1169
11547 11:09:50.270485 # # Finishing up...
11548 11:09:50.276884 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1079320, signals=10
11549 11:09:50.283591 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1406728, signals=10
11550 11:09:50.290274 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1165901, signals=10
11551 11:09:50.299778 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1280070, signals=10
11552 11:09:50.306662 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1400714, signals=10
11553 11:09:50.313397 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1813050, signals=10
11554 11:09:50.319675 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=2170805, signals=10
11555 11:09:50.323101 # ok 1 FPSIMD-0-0
11556 11:09:50.323183 # ok 2 FPSIMD-0-1
11557 11:09:50.326291 # ok 3 FPSIMD-1-0
11558 11:09:50.326372 # ok 4 FPSIMD-1-1
11559 11:09:50.329883 # ok 5 FPSIMD-2-0
11560 11:09:50.329964 # ok 6 FPSIMD-2-1
11561 11:09:50.333038 # ok 7 FPSIMD-3-0
11562 11:09:50.333120 # ok 8 FPSIMD-3-1
11563 11:09:50.336175 # ok 9 FPSIMD-4-0
11564 11:09:50.336283 # ok 10 FPSIMD-4-1
11565 11:09:50.339864 # ok 11 FPSIMD-5-0
11566 11:09:50.339972 # ok 12 FPSIMD-5-1
11567 11:09:50.343148 # ok 13 FPSIMD-6-0
11568 11:09:50.343230 # ok 14 FPSIMD-6-1
11569 11:09:50.346306 # ok 15 FPSIMD-7-0
11570 11:09:50.346388 # ok 16 FPSIMD-7-1
11571 11:09:50.353240 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=983263, signals=9
11572 11:09:50.362786 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=952178, signals=10
11573 11:09:50.369698 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1032774, signals=9
11574 11:09:50.375928 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1135081, signals=10
11575 11:09:50.382886 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1174232, signals=10
11576 11:09:50.389392 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=982924, signals=9
11577 11:09:50.395776 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=953972, signals=10
11578 11:09:50.402563 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1008987, signals=10
11579 11:09:50.412656 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1764461, signals=10
11580 11:09:50.415931 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11581 11:09:50.419136 ok 29 selftests: arm64: fp-stress
11582 11:09:50.422733 # selftests: arm64: sve-ptrace
11583 11:09:50.422815 # TAP version 13
11584 11:09:50.425566 # 1..4104
11585 11:09:50.429203 # ok 2 # SKIP SVE not available
11586 11:09:50.432469 # # Planned tests != run tests (4104 != 1)
11587 11:09:50.435947 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11588 11:09:50.439158 ok 30 selftests: arm64: sve-ptrace # SKIP
11589 11:09:50.442346 # selftests: arm64: sve-probe-vls
11590 11:09:50.445513 # TAP version 13
11591 11:09:50.445596 # 1..2
11592 11:09:50.449352 # ok 2 # SKIP SVE not available
11593 11:09:50.452441 # # Planned tests != run tests (2 != 1)
11594 11:09:50.455865 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11595 11:09:50.462214 ok 31 selftests: arm64: sve-probe-vls # SKIP
11596 11:09:50.462349 # selftests: arm64: vec-syscfg
11597 11:09:50.465563 # TAP version 13
11598 11:09:50.465646 # 1..20
11599 11:09:50.469087 # ok 1 # SKIP SVE not supported
11600 11:09:50.471967 # ok 2 # SKIP SVE not supported
11601 11:09:50.475466 # ok 3 # SKIP SVE not supported
11602 11:09:50.478741 # ok 4 # SKIP SVE not supported
11603 11:09:50.482321 # ok 5 # SKIP SVE not supported
11604 11:09:50.482403 # ok 6 # SKIP SVE not supported
11605 11:09:50.485540 # ok 7 # SKIP SVE not supported
11606 11:09:50.488686 # ok 8 # SKIP SVE not supported
11607 11:09:50.491870 # ok 9 # SKIP SVE not supported
11608 11:09:50.495037 # ok 10 # SKIP SVE not supported
11609 11:09:50.498893 # ok 11 # SKIP SME not supported
11610 11:09:50.501954 # ok 12 # SKIP SME not supported
11611 11:09:50.504981 # ok 13 # SKIP SME not supported
11612 11:09:50.505063 # ok 14 # SKIP SME not supported
11613 11:09:50.508225 # ok 15 # SKIP SME not supported
11614 11:09:50.512222 # ok 16 # SKIP SME not supported
11615 11:09:50.514774 # ok 17 # SKIP SME not supported
11616 11:09:50.518331 # ok 18 # SKIP SME not supported
11617 11:09:50.521606 # ok 19 # SKIP SME not supported
11618 11:09:50.525203 # ok 20 # SKIP SME not supported
11619 11:09:50.528262 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11620 11:09:50.531995 ok 32 selftests: arm64: vec-syscfg
11621 11:09:50.535107 # selftests: arm64: za-fork
11622 11:09:50.537941 # TAP version 13
11623 11:09:50.538023 # 1..1
11624 11:09:50.538088 # # PID: 1245
11625 11:09:50.541900 # # SME support not present
11626 11:09:50.541983 # ok 0 skipped
11627 11:09:50.548251 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11628 11:09:50.551419 ok 33 selftests: arm64: za-fork
11629 11:09:50.554556 # selftests: arm64: za-ptrace
11630 11:09:50.554638 # TAP version 13
11631 11:09:50.554703 # 1..1
11632 11:09:50.558276 # ok 2 # SKIP SME not available
11633 11:09:50.564506 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11634 11:09:50.568150 ok 34 selftests: arm64: za-ptrace # SKIP
11635 11:09:50.571328 # selftests: arm64: check_buffer_fill
11636 11:09:50.574409 # # SKIP: MTE features unavailable
11637 11:09:50.578002 ok 35 selftests: arm64: check_buffer_fill # SKIP
11638 11:09:50.584403 # selftests: arm64: check_child_memory
11639 11:09:50.634779 # # SKIP: MTE features unavailable
11640 11:09:50.642950 ok 36 selftests: arm64: check_child_memory # SKIP
11641 11:09:50.657439 # selftests: arm64: check_gcr_el1_cswitch
11642 11:09:50.706501 # # SKIP: MTE features unavailable
11643 11:09:50.713840 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11644 11:09:50.727609 # selftests: arm64: check_ksm_options
11645 11:09:50.773229 # # SKIP: MTE features unavailable
11646 11:09:50.780675 ok 38 selftests: arm64: check_ksm_options # SKIP
11647 11:09:50.795950 # selftests: arm64: check_mmap_options
11648 11:09:50.837721 # # SKIP: MTE features unavailable
11649 11:09:50.844680 ok 39 selftests: arm64: check_mmap_options # SKIP
11650 11:09:50.854291 # selftests: arm64: check_prctl
11651 11:09:50.911371 # TAP version 13
11652 11:09:50.911464 # 1..5
11653 11:09:50.914901 # ok 1 check_basic_read
11654 11:09:50.914984 # ok 2 NONE
11655 11:09:50.918158 # ok 3 # SKIP SYNC
11656 11:09:50.918241 # ok 4 # SKIP ASYNC
11657 11:09:50.921282 # ok 5 # SKIP SYNC+ASYNC
11658 11:09:50.924594 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11659 11:09:50.927619 ok 40 selftests: arm64: check_prctl
11660 11:09:50.934260 # selftests: arm64: check_tags_inclusion
11661 11:09:50.976417 # # SKIP: MTE features unavailable
11662 11:09:50.983898 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11663 11:09:50.993713 # selftests: arm64: check_user_mem
11664 11:09:51.052437 # # SKIP: MTE features unavailable
11665 11:09:51.058933 ok 42 selftests: arm64: check_user_mem # SKIP
11666 11:09:51.068595 # selftests: arm64: btitest
11667 11:09:51.118825 # TAP version 13
11668 11:09:51.118913 # 1..18
11669 11:09:51.122084 # # HWCAP_PACA not present
11670 11:09:51.125505 # # HWCAP2_BTI not present
11671 11:09:51.125587 # # Test binary built for BTI
11672 11:09:51.131736 # ok 1 nohint_func/call_using_br_x0 # SKIP
11673 11:09:51.135312 # ok 1 nohint_func/call_using_br_x16 # SKIP
11674 11:09:51.138298 # ok 1 nohint_func/call_using_blr # SKIP
11675 11:09:51.141594 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11676 11:09:51.145266 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11677 11:09:51.151573 # ok 1 bti_none_func/call_using_blr # SKIP
11678 11:09:51.155155 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11679 11:09:51.158353 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11680 11:09:51.161380 # ok 1 bti_c_func/call_using_blr # SKIP
11681 11:09:51.165199 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11682 11:09:51.168240 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11683 11:09:51.171939 # ok 1 bti_j_func/call_using_blr # SKIP
11684 11:09:51.175295 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11685 11:09:51.181426 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11686 11:09:51.184961 # ok 1 bti_jc_func/call_using_blr # SKIP
11687 11:09:51.188252 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11688 11:09:51.191663 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11689 11:09:51.194804 # ok 1 paciasp_func/call_using_blr # SKIP
11690 11:09:51.201252 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11691 11:09:51.205004 # # WARNING - EXPECTED TEST COUNT WRONG
11692 11:09:51.208159 ok 43 selftests: arm64: btitest
11693 11:09:51.208268 # selftests: arm64: nobtitest
11694 11:09:51.211329 # TAP version 13
11695 11:09:51.211412 # 1..18
11696 11:09:51.214487 # # HWCAP_PACA not present
11697 11:09:51.218243 # # HWCAP2_BTI not present
11698 11:09:51.221302 # # Test binary not built for BTI
11699 11:09:51.224947 # ok 1 nohint_func/call_using_br_x0 # SKIP
11700 11:09:51.228013 # ok 1 nohint_func/call_using_br_x16 # SKIP
11701 11:09:51.231663 # ok 1 nohint_func/call_using_blr # SKIP
11702 11:09:51.234684 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11703 11:09:51.237694 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11704 11:09:51.244935 # ok 1 bti_none_func/call_using_blr # SKIP
11705 11:09:51.248170 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11706 11:09:51.251060 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11707 11:09:51.254416 # ok 1 bti_c_func/call_using_blr # SKIP
11708 11:09:51.257758 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11709 11:09:51.260981 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11710 11:09:51.264576 # ok 1 bti_j_func/call_using_blr # SKIP
11711 11:09:51.267617 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11712 11:09:51.274637 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11713 11:09:51.277732 # ok 1 bti_jc_func/call_using_blr # SKIP
11714 11:09:51.280667 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11715 11:09:51.284086 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11716 11:09:51.287791 # ok 1 paciasp_func/call_using_blr # SKIP
11717 11:09:51.294132 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11718 11:09:51.297146 # # WARNING - EXPECTED TEST COUNT WRONG
11719 11:09:51.300572 ok 44 selftests: arm64: nobtitest
11720 11:09:51.300670 # selftests: arm64: hwcap
11721 11:09:51.303928 # TAP version 13
11722 11:09:51.304024 # 1..28
11723 11:09:51.307088 # ok 1 cpuinfo_match_RNG
11724 11:09:51.310672 # # SIGILL reported for RNG
11725 11:09:51.310767 # ok 2 # SKIP sigill_RNG
11726 11:09:51.313871 # ok 3 cpuinfo_match_SME
11727 11:09:51.316997 # ok 4 sigill_SME
11728 11:09:51.317070 # ok 5 cpuinfo_match_SVE
11729 11:09:51.320682 # ok 6 sigill_SVE
11730 11:09:51.320751 # ok 7 cpuinfo_match_SVE 2
11731 11:09:51.323873 # # SIGILL reported for SVE 2
11732 11:09:51.327460 # ok 8 # SKIP sigill_SVE 2
11733 11:09:51.330543 # ok 9 cpuinfo_match_SVE AES
11734 11:09:51.333662 # # SIGILL reported for SVE AES
11735 11:09:51.333743 # ok 10 # SKIP sigill_SVE AES
11736 11:09:51.337162 # ok 11 cpuinfo_match_SVE2 PMULL
11737 11:09:51.340184 # # SIGILL reported for SVE2 PMULL
11738 11:09:51.343892 # ok 12 # SKIP sigill_SVE2 PMULL
11739 11:09:51.347136 # ok 13 cpuinfo_match_SVE2 BITPERM
11740 11:09:51.350247 # # SIGILL reported for SVE2 BITPERM
11741 11:09:51.353361 # ok 14 # SKIP sigill_SVE2 BITPERM
11742 11:09:51.357112 # ok 15 cpuinfo_match_SVE2 SHA3
11743 11:09:51.360351 # # SIGILL reported for SVE2 SHA3
11744 11:09:51.363683 # ok 16 # SKIP sigill_SVE2 SHA3
11745 11:09:51.367032 # ok 17 cpuinfo_match_SVE2 SM4
11746 11:09:51.367112 # # SIGILL reported for SVE2 SM4
11747 11:09:51.370180 # ok 18 # SKIP sigill_SVE2 SM4
11748 11:09:51.373253 # ok 19 cpuinfo_match_SVE2 I8MM
11749 11:09:51.376666 # # SIGILL reported for SVE2 I8MM
11750 11:09:51.380173 # ok 20 # SKIP sigill_SVE2 I8MM
11751 11:09:51.383565 # ok 21 cpuinfo_match_SVE2 F32MM
11752 11:09:51.386627 # # SIGILL reported for SVE2 F32MM
11753 11:09:51.390109 # ok 22 # SKIP sigill_SVE2 F32MM
11754 11:09:51.392965 # ok 23 cpuinfo_match_SVE2 F64MM
11755 11:09:51.396767 # # SIGILL reported for SVE2 F64MM
11756 11:09:51.396848 # ok 24 # SKIP sigill_SVE2 F64MM
11757 11:09:51.400079 # ok 25 cpuinfo_match_SVE2 BF16
11758 11:09:51.403070 # # SIGILL reported for SVE2 BF16
11759 11:09:51.406744 # ok 26 # SKIP sigill_SVE2 BF16
11760 11:09:51.409857 # ok 27 cpuinfo_match_SVE2 EBF16
11761 11:09:51.413565 # ok 28 # SKIP sigill_SVE2 EBF16
11762 11:09:51.416551 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11763 11:09:51.419868 ok 45 selftests: arm64: hwcap
11764 11:09:51.423446 # selftests: arm64: ptrace
11765 11:09:51.423530 # TAP version 13
11766 11:09:51.426397 # 1..7
11767 11:09:51.426477 # # Parent is 1487, child is 1488
11768 11:09:51.430070 # ok 1 read_tpidr_one
11769 11:09:51.433135 # ok 2 write_tpidr_one
11770 11:09:51.433224 # ok 3 verify_tpidr_one
11771 11:09:51.436836 # ok 4 count_tpidrs
11772 11:09:51.436917 # ok 5 tpidr2_write
11773 11:09:51.439872 # ok 6 tpidr2_read
11774 11:09:51.443057 # ok 7 write_tpidr_only
11775 11:09:51.446468 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11776 11:09:51.449942 ok 46 selftests: arm64: ptrace
11777 11:09:51.453112 # selftests: arm64: syscall-abi
11778 11:09:51.453194 # TAP version 13
11779 11:09:51.456251 # 1..2
11780 11:09:51.456377 # ok 1 getpid() FPSIMD
11781 11:09:51.459434 # ok 2 sched_yield() FPSIMD
11782 11:09:51.463220 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11783 11:09:51.466380 ok 47 selftests: arm64: syscall-abi
11784 11:09:51.469441 # selftests: arm64: tpidr2
11785 11:09:51.483293 # TAP version 13
11786 11:09:51.483374 # 1..5
11787 11:09:51.487114 # # PID: 1524
11788 11:09:51.487221 # # SME support not present
11789 11:09:51.489900 # ok 0 skipped, TPIDR2 not supported
11790 11:09:51.493312 # ok 1 skipped, TPIDR2 not supported
11791 11:09:51.496577 # ok 2 skipped, TPIDR2 not supported
11792 11:09:51.499855 # ok 3 skipped, TPIDR2 not supported
11793 11:09:51.503010 # ok 4 skipped, TPIDR2 not supported
11794 11:09:51.509648 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11795 11:09:51.513203 ok 48 selftests: arm64: tpidr2
11796 11:09:52.054729 Traceback (most recent call last):
11797 11:09:52.064563 File "/lava-12925630/0/tests/1_kselftest-arm64/automated/linux/kselftest/./parse-output.py", line 4, in <module>
11798 11:09:52.067538 from tap import parser
11799 11:09:52.070836 ModuleNotFoundError: No module named 'tap'
11800 11:09:52.086326 + ../../utils/send-to-lava.sh ./output/result.txt
11801 11:09:52.141890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11802 11:09:52.141985 + set +x
11803 11:09:52.142276 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11805 11:09:52.148536 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 12925630_1.6.2.3.5>
11806 11:09:52.148788 Received signal: <ENDRUN> 1_kselftest-arm64 12925630_1.6.2.3.5
11807 11:09:52.148861 Ending use of test pattern.
11808 11:09:52.148923 Ending test lava.1_kselftest-arm64 (12925630_1.6.2.3.5), duration 20.49
11810 11:09:52.151718 <LAVA_TEST_RUNNER EXIT>
11811 11:09:52.151969 ok: lava_test_shell seems to have completed
11812 11:09:52.152065 shardfile-arm64: pass
11813 11:09:52.152203 end: 3.1 lava-test-shell (duration 00:00:21) [common]
11814 11:09:52.152366 end: 3 lava-test-retry (duration 00:00:21) [common]
11815 11:09:52.152456 start: 4 finalize (timeout 00:07:27) [common]
11816 11:09:52.152547 start: 4.1 power-off (timeout 00:00:30) [common]
11817 11:09:52.152701 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11818 11:09:52.228035 >> Command sent successfully.
11819 11:09:52.230459 Returned 0 in 0 seconds
11820 11:09:52.330832 end: 4.1 power-off (duration 00:00:00) [common]
11822 11:09:52.331254 start: 4.2 read-feedback (timeout 00:07:27) [common]
11823 11:09:52.331563 Listened to connection for namespace 'common' for up to 1s
11824 11:09:53.332410 Finalising connection for namespace 'common'
11825 11:09:53.332592 Disconnecting from shell: Finalise
11826 11:09:53.332674 / #
11827 11:09:53.432967 end: 4.2 read-feedback (duration 00:00:01) [common]
11828 11:09:53.433133 end: 4 finalize (duration 00:00:01) [common]
11829 11:09:53.433253 Cleaning after the job
11830 11:09:53.433353 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925630/tftp-deploy-kpoqbs7e/ramdisk
11831 11:09:53.436137 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925630/tftp-deploy-kpoqbs7e/kernel
11832 11:09:53.448877 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925630/tftp-deploy-kpoqbs7e/dtb
11833 11:09:53.449055 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925630/tftp-deploy-kpoqbs7e/nfsrootfs
11834 11:09:53.542477 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925630/tftp-deploy-kpoqbs7e/modules
11835 11:09:53.549489 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12925630
11836 11:09:54.259287 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12925630
11837 11:09:54.259453 Job finished correctly