Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 36
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 17
1 11:04:17.879473 lava-dispatcher, installed at version: 2024.01
2 11:04:17.879701 start: 0 validate
3 11:04:17.879880 Start time: 2024-03-03 11:04:17.879872+00:00 (UTC)
4 11:04:17.880016 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:04:17.880152 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20240129.0%2Farm64%2Finitrd.cpio.gz exists
6 11:04:18.147751 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:04:18.147986 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:04:43.921452 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:04:43.921693 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:04:44.188029 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:04:44.188295 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20240129.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:04:44.452336 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:04:44.452510 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:04:48.953956 validate duration: 31.07
16 11:04:48.954211 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:04:48.954307 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:04:48.954393 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:04:48.954561 Not decompressing ramdisk as can be used compressed.
20 11:04:48.954646 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20240129.0/arm64/initrd.cpio.gz
21 11:04:48.954710 saving as /var/lib/lava/dispatcher/tmp/12925640/tftp-deploy-4frbx01r/ramdisk/initrd.cpio.gz
22 11:04:48.954782 total size: 4663047 (4 MB)
23 11:04:49.220115 progress 0 % (0 MB)
24 11:04:49.222506 progress 5 % (0 MB)
25 11:04:49.224475 progress 10 % (0 MB)
26 11:04:49.226566 progress 15 % (0 MB)
27 11:04:49.228521 progress 20 % (0 MB)
28 11:04:49.230600 progress 25 % (1 MB)
29 11:04:49.232555 progress 30 % (1 MB)
30 11:04:49.234512 progress 35 % (1 MB)
31 11:04:49.236579 progress 40 % (1 MB)
32 11:04:49.238788 progress 45 % (2 MB)
33 11:04:49.240721 progress 50 % (2 MB)
34 11:04:49.242823 progress 55 % (2 MB)
35 11:04:49.244755 progress 60 % (2 MB)
36 11:04:49.246692 progress 65 % (2 MB)
37 11:04:49.248771 progress 70 % (3 MB)
38 11:04:49.250708 progress 75 % (3 MB)
39 11:04:49.252781 progress 80 % (3 MB)
40 11:04:49.254744 progress 85 % (3 MB)
41 11:04:49.257044 progress 90 % (4 MB)
42 11:04:49.259001 progress 95 % (4 MB)
43 11:04:49.260957 progress 100 % (4 MB)
44 11:04:49.261174 4 MB downloaded in 0.31 s (14.51 MB/s)
45 11:04:49.261400 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:04:49.261785 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:04:49.261927 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:04:49.262048 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:04:49.262242 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:04:49.262342 saving as /var/lib/lava/dispatcher/tmp/12925640/tftp-deploy-4frbx01r/kernel/Image
52 11:04:49.262459 total size: 51599872 (49 MB)
53 11:04:49.262555 No compression specified
54 11:04:49.264100 progress 0 % (0 MB)
55 11:04:49.285871 progress 5 % (2 MB)
56 11:04:49.308166 progress 10 % (4 MB)
57 11:04:49.328851 progress 15 % (7 MB)
58 11:04:49.342405 progress 20 % (9 MB)
59 11:04:49.356135 progress 25 % (12 MB)
60 11:04:49.369971 progress 30 % (14 MB)
61 11:04:49.383936 progress 35 % (17 MB)
62 11:04:49.397846 progress 40 % (19 MB)
63 11:04:49.411985 progress 45 % (22 MB)
64 11:04:49.428944 progress 50 % (24 MB)
65 11:04:49.449492 progress 55 % (27 MB)
66 11:04:49.469945 progress 60 % (29 MB)
67 11:04:49.489649 progress 65 % (32 MB)
68 11:04:49.505232 progress 70 % (34 MB)
69 11:04:49.519687 progress 75 % (36 MB)
70 11:04:49.533715 progress 80 % (39 MB)
71 11:04:49.548187 progress 85 % (41 MB)
72 11:04:49.562880 progress 90 % (44 MB)
73 11:04:49.577138 progress 95 % (46 MB)
74 11:04:49.591660 progress 100 % (49 MB)
75 11:04:49.591909 49 MB downloaded in 0.33 s (149.37 MB/s)
76 11:04:49.592065 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:04:49.592304 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:04:49.592392 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:04:49.592534 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:04:49.592678 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:04:49.592748 saving as /var/lib/lava/dispatcher/tmp/12925640/tftp-deploy-4frbx01r/dtb/mt8192-asurada-spherion-r0.dtb
83 11:04:49.592810 total size: 47278 (0 MB)
84 11:04:49.592871 No compression specified
85 11:04:49.594191 progress 69 % (0 MB)
86 11:04:49.594535 progress 100 % (0 MB)
87 11:04:49.594729 0 MB downloaded in 0.00 s (23.52 MB/s)
88 11:04:49.594859 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:04:49.595081 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:04:49.595166 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:04:49.595294 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:04:49.595467 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20240129.0/arm64/full.rootfs.tar.xz
94 11:04:49.595541 saving as /var/lib/lava/dispatcher/tmp/12925640/tftp-deploy-4frbx01r/nfsrootfs/full.rootfs.tar
95 11:04:49.595603 total size: 200856304 (191 MB)
96 11:04:49.595670 Using unxz to decompress xz
97 11:04:49.600405 progress 0 % (0 MB)
98 11:04:50.226442 progress 5 % (9 MB)
99 11:04:50.769797 progress 10 % (19 MB)
100 11:04:51.542220 progress 15 % (28 MB)
101 11:04:51.991010 progress 20 % (38 MB)
102 11:04:52.383444 progress 25 % (47 MB)
103 11:04:53.015221 progress 30 % (57 MB)
104 11:04:53.596550 progress 35 % (67 MB)
105 11:04:54.217314 progress 40 % (76 MB)
106 11:04:54.866535 progress 45 % (86 MB)
107 11:04:55.531063 progress 50 % (95 MB)
108 11:04:56.276522 progress 55 % (105 MB)
109 11:04:57.015666 progress 60 % (114 MB)
110 11:04:57.145556 progress 65 % (124 MB)
111 11:04:57.312611 progress 70 % (134 MB)
112 11:04:57.423984 progress 75 % (143 MB)
113 11:04:57.510351 progress 80 % (153 MB)
114 11:04:57.612718 progress 85 % (162 MB)
115 11:04:57.731891 progress 90 % (172 MB)
116 11:04:58.052178 progress 95 % (182 MB)
117 11:04:58.700244 progress 100 % (191 MB)
118 11:04:58.706447 191 MB downloaded in 9.11 s (21.02 MB/s)
119 11:04:58.706797 end: 1.4.1 http-download (duration 00:00:09) [common]
121 11:04:58.707148 end: 1.4 download-retry (duration 00:00:09) [common]
122 11:04:58.707242 start: 1.5 download-retry (timeout 00:09:50) [common]
123 11:04:58.707334 start: 1.5.1 http-download (timeout 00:09:50) [common]
124 11:04:58.707494 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:04:58.707567 saving as /var/lib/lava/dispatcher/tmp/12925640/tftp-deploy-4frbx01r/modules/modules.tar
126 11:04:58.707631 total size: 8628476 (8 MB)
127 11:04:58.707700 Using unxz to decompress xz
128 11:04:58.711888 progress 0 % (0 MB)
129 11:04:58.738758 progress 5 % (0 MB)
130 11:04:58.766817 progress 10 % (0 MB)
131 11:04:58.793350 progress 15 % (1 MB)
132 11:04:58.818064 progress 20 % (1 MB)
133 11:04:58.844601 progress 25 % (2 MB)
134 11:04:58.870685 progress 30 % (2 MB)
135 11:04:58.899941 progress 35 % (2 MB)
136 11:04:58.926103 progress 40 % (3 MB)
137 11:04:58.958486 progress 45 % (3 MB)
138 11:04:58.993584 progress 50 % (4 MB)
139 11:04:59.029315 progress 55 % (4 MB)
140 11:04:59.057710 progress 60 % (4 MB)
141 11:04:59.084669 progress 65 % (5 MB)
142 11:04:59.111199 progress 70 % (5 MB)
143 11:04:59.137344 progress 75 % (6 MB)
144 11:04:59.165901 progress 80 % (6 MB)
145 11:04:59.192316 progress 85 % (7 MB)
146 11:04:59.218701 progress 90 % (7 MB)
147 11:04:59.249985 progress 95 % (7 MB)
148 11:04:59.279792 progress 100 % (8 MB)
149 11:04:59.285068 8 MB downloaded in 0.58 s (14.25 MB/s)
150 11:04:59.285365 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:04:59.285686 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:04:59.285782 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 11:04:59.285882 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 11:05:03.233797 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12925640/extract-nfsrootfs-966tkp70
156 11:05:03.234041 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:05:03.234177 start: 1.6.2 lava-overlay (timeout 00:09:46) [common]
158 11:05:03.234353 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6
159 11:05:03.234528 makedir: /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin
160 11:05:03.234668 makedir: /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/tests
161 11:05:03.234800 makedir: /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/results
162 11:05:03.234932 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-add-keys
163 11:05:03.235110 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-add-sources
164 11:05:03.235246 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-background-process-start
165 11:05:03.235379 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-background-process-stop
166 11:05:03.235509 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-common-functions
167 11:05:03.235639 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-echo-ipv4
168 11:05:03.235771 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-install-packages
169 11:05:03.235900 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-installed-packages
170 11:05:03.236030 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-os-build
171 11:05:03.236159 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-probe-channel
172 11:05:03.236291 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-probe-ip
173 11:05:03.236421 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-target-ip
174 11:05:03.236550 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-target-mac
175 11:05:03.236678 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-target-storage
176 11:05:03.236809 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-test-case
177 11:05:03.236940 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-test-event
178 11:05:03.237067 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-test-feedback
179 11:05:03.237195 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-test-raise
180 11:05:03.237323 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-test-reference
181 11:05:03.237452 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-test-runner
182 11:05:03.237580 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-test-set
183 11:05:03.237707 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-test-shell
184 11:05:03.237838 Updating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-add-keys (debian)
185 11:05:03.238016 Updating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-add-sources (debian)
186 11:05:03.238171 Updating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-install-packages (debian)
187 11:05:03.238320 Updating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-installed-packages (debian)
188 11:05:03.238476 Updating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/bin/lava-os-build (debian)
189 11:05:03.238616 Creating /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/environment
190 11:05:03.238750 LAVA metadata
191 11:05:03.238823 - LAVA_JOB_ID=12925640
192 11:05:03.238888 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:05:03.239002 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:46) [common]
194 11:05:03.239070 skipped lava-vland-overlay
195 11:05:03.239147 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:05:03.239228 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:46) [common]
197 11:05:03.239289 skipped lava-multinode-overlay
198 11:05:03.239361 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:05:03.239440 start: 1.6.2.3 test-definition (timeout 00:09:46) [common]
200 11:05:03.239517 Loading test definitions
201 11:05:03.239606 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:46) [common]
202 11:05:03.239677 Using /lava-12925640 at stage 0
203 11:05:03.239977 uuid=12925640_1.6.2.3.1 testdef=None
204 11:05:03.240068 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:05:03.240156 start: 1.6.2.3.2 test-overlay (timeout 00:09:46) [common]
206 11:05:03.240620 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:05:03.240842 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:46) [common]
209 11:05:03.241512 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:05:03.241743 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:46) [common]
212 11:05:03.242337 runner path: /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/0/tests/0_timesync-off test_uuid 12925640_1.6.2.3.1
213 11:05:03.242738 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:05:03.243012 start: 1.6.2.3.5 git-repo-action (timeout 00:09:46) [common]
216 11:05:03.243106 Using /lava-12925640 at stage 0
217 11:05:03.243224 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:05:03.243312 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/0/tests/1_kselftest-dt'
219 11:05:08.489668 Running '/usr/bin/git checkout kernelci.org
220 11:05:08.638899 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 11:05:08.639724 uuid=12925640_1.6.2.3.5 testdef=None
222 11:05:08.639896 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 11:05:08.640166 start: 1.6.2.3.6 test-overlay (timeout 00:09:40) [common]
225 11:05:08.641008 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:05:08.641243 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:40) [common]
228 11:05:08.642243 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:05:08.642500 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:40) [common]
231 11:05:08.643465 runner path: /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/0/tests/1_kselftest-dt test_uuid 12925640_1.6.2.3.5
232 11:05:08.643557 BOARD='mt8192-asurada-spherion-r0'
233 11:05:08.643624 BRANCH='cip'
234 11:05:08.643685 SKIPFILE='/dev/null'
235 11:05:08.643745 SKIP_INSTALL='True'
236 11:05:08.643803 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:05:08.643864 TST_CASENAME=''
238 11:05:08.643920 TST_CMDFILES='dt'
239 11:05:08.644068 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:05:08.644280 Creating lava-test-runner.conf files
242 11:05:08.644348 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12925640/lava-overlay-fd_e7eo6/lava-12925640/0 for stage 0
243 11:05:08.644450 - 0_timesync-off
244 11:05:08.644522 - 1_kselftest-dt
245 11:05:08.644621 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 11:05:08.644711 start: 1.6.2.4 compress-overlay (timeout 00:09:40) [common]
247 11:05:16.621504 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:05:16.621689 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:32) [common]
249 11:05:16.621803 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:05:16.621928 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 11:05:16.622037 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:32) [common]
252 11:05:16.755974 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:05:16.756390 start: 1.6.4 extract-modules (timeout 00:09:32) [common]
254 11:05:16.756528 extracting modules file /var/lib/lava/dispatcher/tmp/12925640/tftp-deploy-4frbx01r/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925640/extract-nfsrootfs-966tkp70
255 11:05:17.005718 extracting modules file /var/lib/lava/dispatcher/tmp/12925640/tftp-deploy-4frbx01r/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925640/extract-overlay-ramdisk-uz55skc4/ramdisk
256 11:05:17.264654 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 11:05:17.264826 start: 1.6.5 apply-overlay-tftp (timeout 00:09:32) [common]
258 11:05:17.264922 [common] Applying overlay to NFS
259 11:05:17.264994 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925640/compress-overlay-7uux5mr_/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12925640/extract-nfsrootfs-966tkp70
260 11:05:18.227232 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:05:18.227410 start: 1.6.6 configure-preseed-file (timeout 00:09:31) [common]
262 11:05:18.227518 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:05:18.227614 start: 1.6.7 compress-ramdisk (timeout 00:09:31) [common]
264 11:05:18.227697 Building ramdisk /var/lib/lava/dispatcher/tmp/12925640/extract-overlay-ramdisk-uz55skc4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12925640/extract-overlay-ramdisk-uz55skc4/ramdisk
265 11:05:18.579555 >> 119441 blocks
266 11:05:20.658140 rename /var/lib/lava/dispatcher/tmp/12925640/extract-overlay-ramdisk-uz55skc4/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12925640/tftp-deploy-4frbx01r/ramdisk/ramdisk.cpio.gz
267 11:05:20.658605 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:05:20.658730 start: 1.6.8 prepare-kernel (timeout 00:09:28) [common]
269 11:05:20.658832 start: 1.6.8.1 prepare-fit (timeout 00:09:28) [common]
270 11:05:20.658947 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12925640/tftp-deploy-4frbx01r/kernel/Image'
271 11:05:35.114207 Returned 0 in 14 seconds
272 11:05:35.215010 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12925640/tftp-deploy-4frbx01r/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12925640/tftp-deploy-4frbx01r/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12925640/tftp-deploy-4frbx01r/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12925640/tftp-deploy-4frbx01r/kernel/image.itb
273 11:05:35.902351 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:05:35.902794 output: Created: Sun Mar 3 11:05:35 2024
275 11:05:35.902867 output: Image 0 (kernel-1)
276 11:05:35.902936 output: Description:
277 11:05:35.903002 output: Created: Sun Mar 3 11:05:35 2024
278 11:05:35.903068 output: Type: Kernel Image
279 11:05:35.903131 output: Compression: lzma compressed
280 11:05:35.903193 output: Data Size: 12057697 Bytes = 11775.09 KiB = 11.50 MiB
281 11:05:35.903254 output: Architecture: AArch64
282 11:05:35.903310 output: OS: Linux
283 11:05:35.903367 output: Load Address: 0x00000000
284 11:05:35.903424 output: Entry Point: 0x00000000
285 11:05:35.903477 output: Hash algo: crc32
286 11:05:35.903530 output: Hash value: cf43f4f3
287 11:05:35.903585 output: Image 1 (fdt-1)
288 11:05:35.903639 output: Description: mt8192-asurada-spherion-r0
289 11:05:35.903692 output: Created: Sun Mar 3 11:05:35 2024
290 11:05:35.903744 output: Type: Flat Device Tree
291 11:05:35.903797 output: Compression: uncompressed
292 11:05:35.903849 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 11:05:35.903903 output: Architecture: AArch64
294 11:05:35.903955 output: Hash algo: crc32
295 11:05:35.904008 output: Hash value: cc4352de
296 11:05:35.904060 output: Image 2 (ramdisk-1)
297 11:05:35.904112 output: Description: unavailable
298 11:05:35.904164 output: Created: Sun Mar 3 11:05:35 2024
299 11:05:35.904216 output: Type: RAMDisk Image
300 11:05:35.904268 output: Compression: Unknown Compression
301 11:05:35.904321 output: Data Size: 17806133 Bytes = 17388.80 KiB = 16.98 MiB
302 11:05:35.904373 output: Architecture: AArch64
303 11:05:35.904442 output: OS: Linux
304 11:05:35.904495 output: Load Address: unavailable
305 11:05:35.904548 output: Entry Point: unavailable
306 11:05:35.904602 output: Hash algo: crc32
307 11:05:35.904655 output: Hash value: 995047bc
308 11:05:35.904708 output: Default Configuration: 'conf-1'
309 11:05:35.904761 output: Configuration 0 (conf-1)
310 11:05:35.904814 output: Description: mt8192-asurada-spherion-r0
311 11:05:35.904867 output: Kernel: kernel-1
312 11:05:35.904921 output: Init Ramdisk: ramdisk-1
313 11:05:35.904974 output: FDT: fdt-1
314 11:05:35.905026 output: Loadables: kernel-1
315 11:05:35.905079 output:
316 11:05:35.905294 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 11:05:35.905399 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 11:05:35.905507 end: 1.6 prepare-tftp-overlay (duration 00:00:37) [common]
319 11:05:35.905606 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:13) [common]
320 11:05:35.905691 No LXC device requested
321 11:05:35.905772 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:05:35.905863 start: 1.8 deploy-device-env (timeout 00:09:13) [common]
323 11:05:35.905946 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:05:35.906016 Checking files for TFTP limit of 4294967296 bytes.
325 11:05:35.906544 end: 1 tftp-deploy (duration 00:00:47) [common]
326 11:05:35.906655 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:05:35.906750 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:05:35.906887 substitutions:
329 11:05:35.906958 - {DTB}: 12925640/tftp-deploy-4frbx01r/dtb/mt8192-asurada-spherion-r0.dtb
330 11:05:35.907054 - {INITRD}: 12925640/tftp-deploy-4frbx01r/ramdisk/ramdisk.cpio.gz
331 11:05:35.907129 - {KERNEL}: 12925640/tftp-deploy-4frbx01r/kernel/Image
332 11:05:35.907203 - {LAVA_MAC}: None
333 11:05:35.907291 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12925640/extract-nfsrootfs-966tkp70
334 11:05:35.907378 - {NFS_SERVER_IP}: 192.168.201.1
335 11:05:35.907435 - {PRESEED_CONFIG}: None
336 11:05:35.907504 - {PRESEED_LOCAL}: None
337 11:05:35.907559 - {RAMDISK}: 12925640/tftp-deploy-4frbx01r/ramdisk/ramdisk.cpio.gz
338 11:05:35.907613 - {ROOT_PART}: None
339 11:05:35.907689 - {ROOT}: None
340 11:05:35.907844 - {SERVER_IP}: 192.168.201.1
341 11:05:35.907934 - {TEE}: None
342 11:05:35.908024 Parsed boot commands:
343 11:05:35.908110 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:05:35.908307 Parsed boot commands: tftpboot 192.168.201.1 12925640/tftp-deploy-4frbx01r/kernel/image.itb 12925640/tftp-deploy-4frbx01r/kernel/cmdline
345 11:05:35.908403 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:05:35.908491 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:05:35.908586 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:05:35.908679 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:05:35.908756 Not connected, no need to disconnect.
350 11:05:35.908833 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:05:35.908916 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:05:35.908988 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
353 11:05:35.913141 Setting prompt string to ['lava-test: # ']
354 11:05:35.913536 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:05:35.913650 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:05:35.913754 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:05:35.913855 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:05:35.914066 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
359 11:05:41.049148 >> Command sent successfully.
360 11:05:41.052532 Returned 0 in 5 seconds
361 11:05:41.152919 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:05:41.153300 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:05:41.153404 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:05:41.153507 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:05:41.153577 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:05:41.153645 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:05:41.153936 [Enter `^Ec?' for help]
369 11:05:41.328247
370 11:05:41.328398
371 11:05:41.328509 F0: 102B 0000
372 11:05:41.328574
373 11:05:41.328641 F3: 1001 0000 [0200]
374 11:05:41.331395
375 11:05:41.331470 F3: 1001 0000
376 11:05:41.331532
377 11:05:41.331592 F7: 102D 0000
378 11:05:41.331651
379 11:05:41.334768 F1: 0000 0000
380 11:05:41.334878
381 11:05:41.334986 V0: 0000 0000 [0001]
382 11:05:41.335056
383 11:05:41.337910 00: 0007 8000
384 11:05:41.338054
385 11:05:41.338161 01: 0000 0000
386 11:05:41.338274
387 11:05:41.341127 BP: 0C00 0209 [0000]
388 11:05:41.341249
389 11:05:41.341359 G0: 1182 0000
390 11:05:41.341473
391 11:05:41.345164 EC: 0000 0021 [4000]
392 11:05:41.345288
393 11:05:41.345416 S7: 0000 0000 [0000]
394 11:05:41.345555
395 11:05:41.348540 CC: 0000 0000 [0001]
396 11:05:41.348662
397 11:05:41.348777 T0: 0000 0040 [010F]
398 11:05:41.348892
399 11:05:41.349013 Jump to BL
400 11:05:41.349151
401 11:05:41.375516
402 11:05:41.375661
403 11:05:41.375779
404 11:05:41.382304 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:05:41.385983 ARM64: Exception handlers installed.
406 11:05:41.389352 ARM64: Testing exception
407 11:05:41.392711 ARM64: Done test exception
408 11:05:41.399437 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:05:41.409801 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:05:41.416758 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:05:41.427246 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:05:41.433166 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:05:41.440365 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:05:41.451793 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:05:41.458744 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:05:41.477837 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:05:41.481555 WDT: Last reset was cold boot
418 11:05:41.484684 SPI1(PAD0) initialized at 2873684 Hz
419 11:05:41.488017 SPI5(PAD0) initialized at 992727 Hz
420 11:05:41.491515 VBOOT: Loading verstage.
421 11:05:41.497937 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:05:41.501468 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:05:41.504811 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:05:41.507885 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:05:41.515222 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:05:41.521761 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:05:41.532600 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
428 11:05:41.532687
429 11:05:41.532753
430 11:05:41.542770 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:05:41.546174 ARM64: Exception handlers installed.
432 11:05:41.549307 ARM64: Testing exception
433 11:05:41.549390 ARM64: Done test exception
434 11:05:41.556551 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:05:41.559547 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:05:41.575117 Probing TPM: . done!
437 11:05:41.575203 TPM ready after 0 ms
438 11:05:41.582149 Connected to device vid:did:rid of 1ae0:0028:00
439 11:05:41.588812 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 11:05:41.645304 Initialized TPM device CR50 revision 0
441 11:05:41.656659 tlcl_send_startup: Startup return code is 0
442 11:05:41.656754 TPM: setup succeeded
443 11:05:41.668457 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:05:41.676923 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:05:41.688140 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:05:41.697758 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:05:41.700557 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:05:41.709323 in-header: 03 07 00 00 08 00 00 00
449 11:05:41.713051 in-data: aa e4 47 04 13 02 00 00
450 11:05:41.716594 Chrome EC: UHEPI supported
451 11:05:41.724434 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:05:41.728145 in-header: 03 ad 00 00 08 00 00 00
453 11:05:41.728226 in-data: 00 20 20 08 00 00 00 00
454 11:05:41.731998 Phase 1
455 11:05:41.735217 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:05:41.738992 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:05:41.746905 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:05:41.750057 Recovery requested (1009000e)
459 11:05:41.757755 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:05:41.763527 tlcl_extend: response is 0
461 11:05:41.772503 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:05:41.777719 tlcl_extend: response is 0
463 11:05:41.785401 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:05:41.805015 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
465 11:05:41.811840 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:05:41.811970
467 11:05:41.812037
468 11:05:41.822684 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:05:41.826481 ARM64: Exception handlers installed.
470 11:05:41.826616 ARM64: Testing exception
471 11:05:41.829896 ARM64: Done test exception
472 11:05:41.850474 pmic_efuse_setting: Set efuses in 11 msecs
473 11:05:41.854613 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:05:41.861047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:05:41.864608 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:05:41.871563 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:05:41.875380 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:05:41.878907 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:05:41.882435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:05:41.890131 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:05:41.893688 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:05:41.897502 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:05:41.904840 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:05:41.908369 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:05:41.911626 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:05:41.914832 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:05:41.923035 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:05:41.930009 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:05:41.933438 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:05:41.940965 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:05:41.944348 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:05:41.952316 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:05:41.955726 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:05:41.963426 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:05:41.966893 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:05:41.974860 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:05:41.977748 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:05:41.985787 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:05:41.989112 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:05:41.996285 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:05:42.000396 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:05:42.003570 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:05:42.011288 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:05:42.014827 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:05:42.018687 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:05:42.025766 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:05:42.029664 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:05:42.033324 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:05:42.040726 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:05:42.044245 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:05:42.047824 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:05:42.055654 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:05:42.059176 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:05:42.062427 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:05:42.066403 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:05:42.070140 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:05:42.077676 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:05:42.081550 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:05:42.084949 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:05:42.088596 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:05:42.092353 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:05:42.096505 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:05:42.100297 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:05:42.107485 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:05:42.114415 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:05:42.122318 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:05:42.125661 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:05:42.133618 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:05:42.144285 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:05:42.148407 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:05:42.151711 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:05:42.154966 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:05:42.163593 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x26
534 11:05:42.171005 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:05:42.174433 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 11:05:42.177340 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:05:42.188184 [RTC]rtc_get_frequency_meter,154: input=15, output=790
538 11:05:42.197734 [RTC]rtc_get_frequency_meter,154: input=23, output=980
539 11:05:42.207237 [RTC]rtc_get_frequency_meter,154: input=19, output=886
540 11:05:42.216794 [RTC]rtc_get_frequency_meter,154: input=17, output=836
541 11:05:42.226249 [RTC]rtc_get_frequency_meter,154: input=16, output=814
542 11:05:42.235542 [RTC]rtc_get_frequency_meter,154: input=15, output=790
543 11:05:42.245532 [RTC]rtc_get_frequency_meter,154: input=16, output=814
544 11:05:42.248417 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
545 11:05:42.256631 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
546 11:05:42.259798 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:05:42.263781 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 11:05:42.267472 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:05:42.271011 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 11:05:42.274797 ADC[4]: Raw value=901328 ID=7
551 11:05:42.278148 ADC[3]: Raw value=213336 ID=1
552 11:05:42.278259 RAM Code: 0x71
553 11:05:42.281618 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:05:42.289577 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:05:42.296758 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:05:42.304006 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:05:42.307629 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:05:42.311669 in-header: 03 07 00 00 08 00 00 00
559 11:05:42.311756 in-data: aa e4 47 04 13 02 00 00
560 11:05:42.315723 Chrome EC: UHEPI supported
561 11:05:42.323193 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:05:42.326885 in-header: 03 ed 00 00 08 00 00 00
563 11:05:42.330693 in-data: 80 20 60 08 00 00 00 00
564 11:05:42.330821 MRC: failed to locate region type 0.
565 11:05:42.337992 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:05:42.341528 DRAM-K: Running full calibration
567 11:05:42.349549 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:05:42.349682 header.status = 0x0
569 11:05:42.352708 header.version = 0x6 (expected: 0x6)
570 11:05:42.356232 header.size = 0xd00 (expected: 0xd00)
571 11:05:42.360280 header.flags = 0x0
572 11:05:42.363068 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:05:42.382816 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
574 11:05:42.390141 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:05:42.394021 dram_init: ddr_geometry: 2
576 11:05:42.394161 [EMI] MDL number = 2
577 11:05:42.397270 [EMI] Get MDL freq = 0
578 11:05:42.397401 dram_init: ddr_type: 0
579 11:05:42.401042 is_discrete_lpddr4: 1
580 11:05:42.405758 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:05:42.405893
582 11:05:42.406011
583 11:05:42.406122 [Bian_co] ETT version 0.0.0.1
584 11:05:42.408736 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:05:42.412932
586 11:05:42.417110 dramc_set_vcore_voltage set vcore to 650000
587 11:05:42.417237 Read voltage for 800, 4
588 11:05:42.417355 Vio18 = 0
589 11:05:42.420261 Vcore = 650000
590 11:05:42.420387 Vdram = 0
591 11:05:42.420504 Vddq = 0
592 11:05:42.420619 Vmddr = 0
593 11:05:42.423873 dram_init: config_dvfs: 1
594 11:05:42.430171 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:05:42.433397 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:05:42.436840 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
597 11:05:42.443429 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
598 11:05:42.447245 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
599 11:05:42.450595 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
600 11:05:42.454248 MEM_TYPE=3, freq_sel=18
601 11:05:42.454375 sv_algorithm_assistance_LP4_1600
602 11:05:42.460468 ============ PULL DRAM RESETB DOWN ============
603 11:05:42.464234 ========== PULL DRAM RESETB DOWN end =========
604 11:05:42.467449 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:05:42.470534 ===================================
606 11:05:42.474164 LPDDR4 DRAM CONFIGURATION
607 11:05:42.477271 ===================================
608 11:05:42.480535 EX_ROW_EN[0] = 0x0
609 11:05:42.480623 EX_ROW_EN[1] = 0x0
610 11:05:42.483870 LP4Y_EN = 0x0
611 11:05:42.483962 WORK_FSP = 0x0
612 11:05:42.487621 WL = 0x2
613 11:05:42.487707 RL = 0x2
614 11:05:42.490523 BL = 0x2
615 11:05:42.490620 RPST = 0x0
616 11:05:42.493805 RD_PRE = 0x0
617 11:05:42.493881 WR_PRE = 0x1
618 11:05:42.497322 WR_PST = 0x0
619 11:05:42.497399 DBI_WR = 0x0
620 11:05:42.500589 DBI_RD = 0x0
621 11:05:42.500667 OTF = 0x1
622 11:05:42.503904 ===================================
623 11:05:42.507162 ===================================
624 11:05:42.510425 ANA top config
625 11:05:42.513795 ===================================
626 11:05:42.517186 DLL_ASYNC_EN = 0
627 11:05:42.517294 ALL_SLAVE_EN = 1
628 11:05:42.520635 NEW_RANK_MODE = 1
629 11:05:42.524374 DLL_IDLE_MODE = 1
630 11:05:42.527590 LP45_APHY_COMB_EN = 1
631 11:05:42.527721 TX_ODT_DIS = 1
632 11:05:42.530275 NEW_8X_MODE = 1
633 11:05:42.533815 ===================================
634 11:05:42.537576 ===================================
635 11:05:42.540414 data_rate = 1600
636 11:05:42.543771 CKR = 1
637 11:05:42.547144 DQ_P2S_RATIO = 8
638 11:05:42.550459 ===================================
639 11:05:42.550537 CA_P2S_RATIO = 8
640 11:05:42.553779 DQ_CA_OPEN = 0
641 11:05:42.557461 DQ_SEMI_OPEN = 0
642 11:05:42.560721 CA_SEMI_OPEN = 0
643 11:05:42.564038 CA_FULL_RATE = 0
644 11:05:42.567929 DQ_CKDIV4_EN = 1
645 11:05:42.568011 CA_CKDIV4_EN = 1
646 11:05:42.570479 CA_PREDIV_EN = 0
647 11:05:42.574370 PH8_DLY = 0
648 11:05:42.577463 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:05:42.580640 DQ_AAMCK_DIV = 4
650 11:05:42.580748 CA_AAMCK_DIV = 4
651 11:05:42.584280 CA_ADMCK_DIV = 4
652 11:05:42.587708 DQ_TRACK_CA_EN = 0
653 11:05:42.590991 CA_PICK = 800
654 11:05:42.594031 CA_MCKIO = 800
655 11:05:42.597617 MCKIO_SEMI = 0
656 11:05:42.601249 PLL_FREQ = 3068
657 11:05:42.601329 DQ_UI_PI_RATIO = 32
658 11:05:42.605087 CA_UI_PI_RATIO = 0
659 11:05:42.608969 ===================================
660 11:05:42.612208 ===================================
661 11:05:42.615763 memory_type:LPDDR4
662 11:05:42.615857 GP_NUM : 10
663 11:05:42.620072 SRAM_EN : 1
664 11:05:42.620159 MD32_EN : 0
665 11:05:42.623350 ===================================
666 11:05:42.627221 [ANA_INIT] >>>>>>>>>>>>>>
667 11:05:42.631133 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:05:42.631215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:05:42.634684 ===================================
670 11:05:42.638031 data_rate = 1600,PCW = 0X7600
671 11:05:42.641901 ===================================
672 11:05:42.644969 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:05:42.651362 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:05:42.654705 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:05:42.661435 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:05:42.665665 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:05:42.668488 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:05:42.668564 [ANA_INIT] flow start
679 11:05:42.671985 [ANA_INIT] PLL >>>>>>>>
680 11:05:42.675041 [ANA_INIT] PLL <<<<<<<<
681 11:05:42.675119 [ANA_INIT] MIDPI >>>>>>>>
682 11:05:42.678146 [ANA_INIT] MIDPI <<<<<<<<
683 11:05:42.681964 [ANA_INIT] DLL >>>>>>>>
684 11:05:42.682039 [ANA_INIT] flow end
685 11:05:42.688451 ============ LP4 DIFF to SE enter ============
686 11:05:42.691597 ============ LP4 DIFF to SE exit ============
687 11:05:42.695059 [ANA_INIT] <<<<<<<<<<<<<
688 11:05:42.698346 [Flow] Enable top DCM control >>>>>
689 11:05:42.698463 [Flow] Enable top DCM control <<<<<
690 11:05:42.701856 Enable DLL master slave shuffle
691 11:05:42.708666 ==============================================================
692 11:05:42.711753 Gating Mode config
693 11:05:42.715503 ==============================================================
694 11:05:42.718654 Config description:
695 11:05:42.728652 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:05:42.735488 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:05:42.739004 SELPH_MODE 0: By rank 1: By Phase
698 11:05:42.745412 ==============================================================
699 11:05:42.748792 GAT_TRACK_EN = 1
700 11:05:42.752232 RX_GATING_MODE = 2
701 11:05:42.752307 RX_GATING_TRACK_MODE = 2
702 11:05:42.755415 SELPH_MODE = 1
703 11:05:42.758969 PICG_EARLY_EN = 1
704 11:05:42.762303 VALID_LAT_VALUE = 1
705 11:05:42.768873 ==============================================================
706 11:05:42.772266 Enter into Gating configuration >>>>
707 11:05:42.775140 Exit from Gating configuration <<<<
708 11:05:42.778478 Enter into DVFS_PRE_config >>>>>
709 11:05:42.788588 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:05:42.792164 Exit from DVFS_PRE_config <<<<<
711 11:05:42.795584 Enter into PICG configuration >>>>
712 11:05:42.798791 Exit from PICG configuration <<<<
713 11:05:42.802509 [RX_INPUT] configuration >>>>>
714 11:05:42.805678 [RX_INPUT] configuration <<<<<
715 11:05:42.808844 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:05:42.815601 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:05:42.822357 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:05:42.825512 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:05:42.832270 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:05:42.839450 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:05:42.842380 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:05:42.845864 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:05:42.852562 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:05:42.855991 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:05:42.859495 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:05:42.862377 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:05:42.866088 ===================================
728 11:05:42.869142 LPDDR4 DRAM CONFIGURATION
729 11:05:42.872983 ===================================
730 11:05:42.876190 EX_ROW_EN[0] = 0x0
731 11:05:42.876268 EX_ROW_EN[1] = 0x0
732 11:05:42.879608 LP4Y_EN = 0x0
733 11:05:42.879692 WORK_FSP = 0x0
734 11:05:42.882976 WL = 0x2
735 11:05:42.883063 RL = 0x2
736 11:05:42.886378 BL = 0x2
737 11:05:42.886475 RPST = 0x0
738 11:05:42.889617 RD_PRE = 0x0
739 11:05:42.889690 WR_PRE = 0x1
740 11:05:42.892999 WR_PST = 0x0
741 11:05:42.893071 DBI_WR = 0x0
742 11:05:42.896648 DBI_RD = 0x0
743 11:05:42.896721 OTF = 0x1
744 11:05:42.899756 ===================================
745 11:05:42.906120 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:05:42.909533 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:05:42.913219 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:05:42.916356 ===================================
749 11:05:42.919821 LPDDR4 DRAM CONFIGURATION
750 11:05:42.923245 ===================================
751 11:05:42.923323 EX_ROW_EN[0] = 0x10
752 11:05:42.926640 EX_ROW_EN[1] = 0x0
753 11:05:42.929821 LP4Y_EN = 0x0
754 11:05:42.929893 WORK_FSP = 0x0
755 11:05:42.932973 WL = 0x2
756 11:05:42.933044 RL = 0x2
757 11:05:42.936594 BL = 0x2
758 11:05:42.936670 RPST = 0x0
759 11:05:42.940103 RD_PRE = 0x0
760 11:05:42.940180 WR_PRE = 0x1
761 11:05:42.943513 WR_PST = 0x0
762 11:05:42.943589 DBI_WR = 0x0
763 11:05:42.946575 DBI_RD = 0x0
764 11:05:42.946650 OTF = 0x1
765 11:05:42.949515 ===================================
766 11:05:42.956646 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:05:42.960711 nWR fixed to 40
768 11:05:42.963812 [ModeRegInit_LP4] CH0 RK0
769 11:05:42.963888 [ModeRegInit_LP4] CH0 RK1
770 11:05:42.967019 [ModeRegInit_LP4] CH1 RK0
771 11:05:42.970319 [ModeRegInit_LP4] CH1 RK1
772 11:05:42.970446 match AC timing 13
773 11:05:42.977478 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:05:42.980560 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:05:42.983804 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:05:42.990496 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:05:42.993857 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:05:42.993944 [EMI DOE] emi_dcm 0
779 11:05:43.000623 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:05:43.000705 ==
781 11:05:43.003823 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:05:43.007115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:05:43.007194 ==
784 11:05:43.013662 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:05:43.017015 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:05:43.028085 [CA 0] Center 37 (6~68) winsize 63
787 11:05:43.031285 [CA 1] Center 37 (6~68) winsize 63
788 11:05:43.034522 [CA 2] Center 35 (5~66) winsize 62
789 11:05:43.038675 [CA 3] Center 34 (4~65) winsize 62
790 11:05:43.041450 [CA 4] Center 34 (4~65) winsize 62
791 11:05:43.044581 [CA 5] Center 33 (3~64) winsize 62
792 11:05:43.044661
793 11:05:43.048282 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 11:05:43.048410
795 11:05:43.051330 [CATrainingPosCal] consider 1 rank data
796 11:05:43.055049 u2DelayCellTimex100 = 270/100 ps
797 11:05:43.057888 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
798 11:05:43.061610 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 11:05:43.064848 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 11:05:43.071743 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 11:05:43.075229 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
802 11:05:43.078206 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 11:05:43.078283
804 11:05:43.081631 CA PerBit enable=1, Macro0, CA PI delay=33
805 11:05:43.081708
806 11:05:43.085138 [CBTSetCACLKResult] CA Dly = 33
807 11:05:43.085257 CS Dly: 4 (0~35)
808 11:05:43.085338 ==
809 11:05:43.088133 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:05:43.094785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:05:43.094899 ==
812 11:05:43.098162 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:05:43.105179 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:05:43.114383 [CA 0] Center 37 (7~68) winsize 62
815 11:05:43.117733 [CA 1] Center 37 (7~68) winsize 62
816 11:05:43.121192 [CA 2] Center 35 (5~66) winsize 62
817 11:05:43.124155 [CA 3] Center 35 (4~66) winsize 63
818 11:05:43.127423 [CA 4] Center 34 (4~65) winsize 62
819 11:05:43.130910 [CA 5] Center 33 (3~64) winsize 62
820 11:05:43.130987
821 11:05:43.134598 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 11:05:43.134696
823 11:05:43.137442 [CATrainingPosCal] consider 2 rank data
824 11:05:43.140775 u2DelayCellTimex100 = 270/100 ps
825 11:05:43.144124 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 11:05:43.147691 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 11:05:43.150936 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 11:05:43.158174 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 11:05:43.161193 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
830 11:05:43.164435 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 11:05:43.164560
832 11:05:43.167572 CA PerBit enable=1, Macro0, CA PI delay=33
833 11:05:43.167684
834 11:05:43.170956 [CBTSetCACLKResult] CA Dly = 33
835 11:05:43.171061 CS Dly: 5 (0~37)
836 11:05:43.171155
837 11:05:43.174331 ----->DramcWriteLeveling(PI) begin...
838 11:05:43.174465 ==
839 11:05:43.177753 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:05:43.185428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:05:43.185512 ==
842 11:05:43.185577 Write leveling (Byte 0): 31 => 31
843 11:05:43.189372 Write leveling (Byte 1): 31 => 31
844 11:05:43.192467 DramcWriteLeveling(PI) end<-----
845 11:05:43.192553
846 11:05:43.192666 ==
847 11:05:43.196545 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:05:43.200115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:05:43.200221 ==
850 11:05:43.203755 [Gating] SW mode calibration
851 11:05:43.210197 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:05:43.214078 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:05:43.221061 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:05:43.224390 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 11:05:43.227801 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
856 11:05:43.234341 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
857 11:05:43.237938 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:05:43.241005 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:05:43.247586 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:05:43.251511 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:05:43.254967 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:05:43.261016 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:05:43.264560 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:05:43.268006 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:05:43.271163 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:05:43.278005 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:05:43.281869 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:05:43.285108 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:05:43.291171 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:05:43.294538 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 11:05:43.298407 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 11:05:43.305151 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:05:43.307873 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:05:43.311106 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:05:43.318408 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:05:43.321592 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:05:43.324513 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:05:43.331292 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:05:43.334941 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 11:05:43.338047 0 9 12 | B1->B0 | 2828 3131 | 0 0 | (0 0) (0 0)
881 11:05:43.341725 0 9 16 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
882 11:05:43.347789 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:05:43.351599 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:05:43.355066 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:05:43.361477 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:05:43.364745 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 11:05:43.368089 0 10 8 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
888 11:05:43.374809 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
889 11:05:43.378758 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:05:43.381492 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:05:43.388320 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:05:43.391742 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:05:43.395455 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:05:43.401558 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 11:05:43.405253 0 11 8 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
896 11:05:43.408566 0 11 12 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
897 11:05:43.411695 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:05:43.418678 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:05:43.422009 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:05:43.425428 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:05:43.432014 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 11:05:43.435599 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 11:05:43.438689 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 11:05:43.445327 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 11:05:43.449473 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:05:43.452452 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:05:43.458899 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:05:43.462222 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:05:43.465623 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:05:43.468924 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:05:43.475683 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:05:43.479531 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:05:43.482261 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:05:43.488953 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:05:43.492657 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:05:43.496364 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:05:43.502719 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:05:43.506009 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 11:05:43.509306 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 11:05:43.516188 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 11:05:43.516274 Total UI for P1: 0, mck2ui 16
922 11:05:43.519313 best dqsien dly found for B0: ( 0, 14, 8)
923 11:05:43.523189 Total UI for P1: 0, mck2ui 16
924 11:05:43.526688 best dqsien dly found for B1: ( 0, 14, 10)
925 11:05:43.529887 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 11:05:43.536153 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 11:05:43.536239
928 11:05:43.539396 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 11:05:43.543552 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 11:05:43.546368 [Gating] SW calibration Done
931 11:05:43.546494 ==
932 11:05:43.549492 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:05:43.553622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:05:43.553703 ==
935 11:05:43.553769 RX Vref Scan: 0
936 11:05:43.553830
937 11:05:43.556590 RX Vref 0 -> 0, step: 1
938 11:05:43.556673
939 11:05:43.559786 RX Delay -130 -> 252, step: 16
940 11:05:43.563363 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 11:05:43.566321 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 11:05:43.573093 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 11:05:43.576518 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 11:05:43.579507 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 11:05:43.583464 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 11:05:43.586980 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
947 11:05:43.589891 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
948 11:05:43.597260 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 11:05:43.599997 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 11:05:43.603533 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 11:05:43.606843 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 11:05:43.610152 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 11:05:43.617089 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 11:05:43.620083 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 11:05:43.623318 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 11:05:43.623471 ==
957 11:05:43.626586 Dram Type= 6, Freq= 0, CH_0, rank 0
958 11:05:43.630173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 11:05:43.630301 ==
960 11:05:43.633678 DQS Delay:
961 11:05:43.633800 DQS0 = 0, DQS1 = 0
962 11:05:43.637230 DQM Delay:
963 11:05:43.637358 DQM0 = 84, DQM1 = 77
964 11:05:43.637470 DQ Delay:
965 11:05:43.640492 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 11:05:43.643621 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
967 11:05:43.647416 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
968 11:05:43.650724 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 11:05:43.650847
970 11:05:43.650962
971 11:05:43.651099 ==
972 11:05:43.653595 Dram Type= 6, Freq= 0, CH_0, rank 0
973 11:05:43.660714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 11:05:43.660798 ==
975 11:05:43.660863
976 11:05:43.660925
977 11:05:43.660983 TX Vref Scan disable
978 11:05:43.664133 == TX Byte 0 ==
979 11:05:43.667246 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
980 11:05:43.671021 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
981 11:05:43.674191 == TX Byte 1 ==
982 11:05:43.677102 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
983 11:05:43.681085 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
984 11:05:43.683846 ==
985 11:05:43.687321 Dram Type= 6, Freq= 0, CH_0, rank 0
986 11:05:43.690780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 11:05:43.690864 ==
988 11:05:43.703343 TX Vref=22, minBit 5, minWin=27, winSum=441
989 11:05:43.706514 TX Vref=24, minBit 5, minWin=27, winSum=443
990 11:05:43.709875 TX Vref=26, minBit 5, minWin=27, winSum=448
991 11:05:43.713074 TX Vref=28, minBit 13, minWin=27, winSum=451
992 11:05:43.716829 TX Vref=30, minBit 12, minWin=27, winSum=456
993 11:05:43.719636 TX Vref=32, minBit 2, minWin=28, winSum=454
994 11:05:43.726808 [TxChooseVref] Worse bit 2, Min win 28, Win sum 454, Final Vref 32
995 11:05:43.726892
996 11:05:43.729948 Final TX Range 1 Vref 32
997 11:05:43.730060
998 11:05:43.730153 ==
999 11:05:43.733667 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 11:05:43.736548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 11:05:43.736631 ==
1002 11:05:43.736699
1003 11:05:43.739963
1004 11:05:43.740137 TX Vref Scan disable
1005 11:05:43.743120 == TX Byte 0 ==
1006 11:05:43.746616 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1007 11:05:43.750404 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1008 11:05:43.753775 == TX Byte 1 ==
1009 11:05:43.756410 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1010 11:05:43.759972 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1011 11:05:43.760059
1012 11:05:43.763321 [DATLAT]
1013 11:05:43.763402 Freq=800, CH0 RK0
1014 11:05:43.763474
1015 11:05:43.766932 DATLAT Default: 0xa
1016 11:05:43.767015 0, 0xFFFF, sum = 0
1017 11:05:43.770684 1, 0xFFFF, sum = 0
1018 11:05:43.770770 2, 0xFFFF, sum = 0
1019 11:05:43.773267 3, 0xFFFF, sum = 0
1020 11:05:43.773350 4, 0xFFFF, sum = 0
1021 11:05:43.776788 5, 0xFFFF, sum = 0
1022 11:05:43.776871 6, 0xFFFF, sum = 0
1023 11:05:43.780140 7, 0xFFFF, sum = 0
1024 11:05:43.780223 8, 0xFFFF, sum = 0
1025 11:05:43.783412 9, 0x0, sum = 1
1026 11:05:43.783555 10, 0x0, sum = 2
1027 11:05:43.786962 11, 0x0, sum = 3
1028 11:05:43.787044 12, 0x0, sum = 4
1029 11:05:43.790105 best_step = 10
1030 11:05:43.790221
1031 11:05:43.790283 ==
1032 11:05:43.793475 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 11:05:43.797109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 11:05:43.797191 ==
1035 11:05:43.800715 RX Vref Scan: 1
1036 11:05:43.800795
1037 11:05:43.800858 Set Vref Range= 32 -> 127
1038 11:05:43.800917
1039 11:05:43.803839 RX Vref 32 -> 127, step: 1
1040 11:05:43.803920
1041 11:05:43.807282 RX Delay -111 -> 252, step: 8
1042 11:05:43.807363
1043 11:05:43.810208 Set Vref, RX VrefLevel [Byte0]: 32
1044 11:05:43.813795 [Byte1]: 32
1045 11:05:43.813877
1046 11:05:43.817033 Set Vref, RX VrefLevel [Byte0]: 33
1047 11:05:43.820604 [Byte1]: 33
1048 11:05:43.820685
1049 11:05:43.824144 Set Vref, RX VrefLevel [Byte0]: 34
1050 11:05:43.827702 [Byte1]: 34
1051 11:05:43.831431
1052 11:05:43.831512 Set Vref, RX VrefLevel [Byte0]: 35
1053 11:05:43.834406 [Byte1]: 35
1054 11:05:43.838836
1055 11:05:43.838917 Set Vref, RX VrefLevel [Byte0]: 36
1056 11:05:43.841962 [Byte1]: 36
1057 11:05:43.846344
1058 11:05:43.846480 Set Vref, RX VrefLevel [Byte0]: 37
1059 11:05:43.849892 [Byte1]: 37
1060 11:05:43.854245
1061 11:05:43.854355 Set Vref, RX VrefLevel [Byte0]: 38
1062 11:05:43.857677 [Byte1]: 38
1063 11:05:43.862796
1064 11:05:43.862899 Set Vref, RX VrefLevel [Byte0]: 39
1065 11:05:43.866211 [Byte1]: 39
1066 11:05:43.870282
1067 11:05:43.870390 Set Vref, RX VrefLevel [Byte0]: 40
1068 11:05:43.873366 [Byte1]: 40
1069 11:05:43.877279
1070 11:05:43.877357 Set Vref, RX VrefLevel [Byte0]: 41
1071 11:05:43.880962 [Byte1]: 41
1072 11:05:43.884911
1073 11:05:43.885029 Set Vref, RX VrefLevel [Byte0]: 42
1074 11:05:43.888469 [Byte1]: 42
1075 11:05:43.892740
1076 11:05:43.892844 Set Vref, RX VrefLevel [Byte0]: 43
1077 11:05:43.895984 [Byte1]: 43
1078 11:05:43.900318
1079 11:05:43.900417 Set Vref, RX VrefLevel [Byte0]: 44
1080 11:05:43.903457 [Byte1]: 44
1081 11:05:43.907797
1082 11:05:43.907873 Set Vref, RX VrefLevel [Byte0]: 45
1083 11:05:43.911086 [Byte1]: 45
1084 11:05:43.915507
1085 11:05:43.915605 Set Vref, RX VrefLevel [Byte0]: 46
1086 11:05:43.918832 [Byte1]: 46
1087 11:05:43.922933
1088 11:05:43.923026 Set Vref, RX VrefLevel [Byte0]: 47
1089 11:05:43.926227 [Byte1]: 47
1090 11:05:43.930536
1091 11:05:43.930616 Set Vref, RX VrefLevel [Byte0]: 48
1092 11:05:43.933929 [Byte1]: 48
1093 11:05:43.938586
1094 11:05:43.938667 Set Vref, RX VrefLevel [Byte0]: 49
1095 11:05:43.941413 [Byte1]: 49
1096 11:05:43.945591
1097 11:05:43.945699 Set Vref, RX VrefLevel [Byte0]: 50
1098 11:05:43.949486 [Byte1]: 50
1099 11:05:43.953290
1100 11:05:43.953371 Set Vref, RX VrefLevel [Byte0]: 51
1101 11:05:43.956868 [Byte1]: 51
1102 11:05:43.961265
1103 11:05:43.961347 Set Vref, RX VrefLevel [Byte0]: 52
1104 11:05:43.964427 [Byte1]: 52
1105 11:05:43.969211
1106 11:05:43.969316 Set Vref, RX VrefLevel [Byte0]: 53
1107 11:05:43.972072 [Byte1]: 53
1108 11:05:43.976507
1109 11:05:43.976610 Set Vref, RX VrefLevel [Byte0]: 54
1110 11:05:43.979813 [Byte1]: 54
1111 11:05:43.984720
1112 11:05:43.984918 Set Vref, RX VrefLevel [Byte0]: 55
1113 11:05:43.987387 [Byte1]: 55
1114 11:05:43.991621
1115 11:05:43.991702 Set Vref, RX VrefLevel [Byte0]: 56
1116 11:05:43.995011 [Byte1]: 56
1117 11:05:43.999805
1118 11:05:43.999886 Set Vref, RX VrefLevel [Byte0]: 57
1119 11:05:44.002373 [Byte1]: 57
1120 11:05:44.007161
1121 11:05:44.007241 Set Vref, RX VrefLevel [Byte0]: 58
1122 11:05:44.010494 [Byte1]: 58
1123 11:05:44.014719
1124 11:05:44.014801 Set Vref, RX VrefLevel [Byte0]: 59
1125 11:05:44.017920 [Byte1]: 59
1126 11:05:44.022363
1127 11:05:44.022467 Set Vref, RX VrefLevel [Byte0]: 60
1128 11:05:44.025795 [Byte1]: 60
1129 11:05:44.030089
1130 11:05:44.030168 Set Vref, RX VrefLevel [Byte0]: 61
1131 11:05:44.033616 [Byte1]: 61
1132 11:05:44.037359
1133 11:05:44.037439 Set Vref, RX VrefLevel [Byte0]: 62
1134 11:05:44.040887 [Byte1]: 62
1135 11:05:44.045171
1136 11:05:44.045257 Set Vref, RX VrefLevel [Byte0]: 63
1137 11:05:44.048769 [Byte1]: 63
1138 11:05:44.052935
1139 11:05:44.053074 Set Vref, RX VrefLevel [Byte0]: 64
1140 11:05:44.055853 [Byte1]: 64
1141 11:05:44.060876
1142 11:05:44.060986 Set Vref, RX VrefLevel [Byte0]: 65
1143 11:05:44.064880 [Byte1]: 65
1144 11:05:44.068677
1145 11:05:44.068784 Set Vref, RX VrefLevel [Byte0]: 66
1146 11:05:44.071334 [Byte1]: 66
1147 11:05:44.075936
1148 11:05:44.076033 Set Vref, RX VrefLevel [Byte0]: 67
1149 11:05:44.079130 [Byte1]: 67
1150 11:05:44.083782
1151 11:05:44.083871 Set Vref, RX VrefLevel [Byte0]: 68
1152 11:05:44.086945 [Byte1]: 68
1153 11:05:44.091433
1154 11:05:44.091521 Set Vref, RX VrefLevel [Byte0]: 69
1155 11:05:44.094693 [Byte1]: 69
1156 11:05:44.098894
1157 11:05:44.098975 Set Vref, RX VrefLevel [Byte0]: 70
1158 11:05:44.102214 [Byte1]: 70
1159 11:05:44.106253
1160 11:05:44.106334 Set Vref, RX VrefLevel [Byte0]: 71
1161 11:05:44.109997 [Byte1]: 71
1162 11:05:44.114249
1163 11:05:44.114371 Set Vref, RX VrefLevel [Byte0]: 72
1164 11:05:44.117490 [Byte1]: 72
1165 11:05:44.121494
1166 11:05:44.121574 Set Vref, RX VrefLevel [Byte0]: 73
1167 11:05:44.124891 [Byte1]: 73
1168 11:05:44.129220
1169 11:05:44.129301 Set Vref, RX VrefLevel [Byte0]: 74
1170 11:05:44.132381 [Byte1]: 74
1171 11:05:44.136837
1172 11:05:44.136945 Set Vref, RX VrefLevel [Byte0]: 75
1173 11:05:44.140239 [Byte1]: 75
1174 11:05:44.144575
1175 11:05:44.144652 Set Vref, RX VrefLevel [Byte0]: 76
1176 11:05:44.147857 [Byte1]: 76
1177 11:05:44.152358
1178 11:05:44.152438 Set Vref, RX VrefLevel [Byte0]: 77
1179 11:05:44.155779 [Byte1]: 77
1180 11:05:44.160119
1181 11:05:44.160200 Final RX Vref Byte 0 = 63 to rank0
1182 11:05:44.163415 Final RX Vref Byte 1 = 59 to rank0
1183 11:05:44.166579 Final RX Vref Byte 0 = 63 to rank1
1184 11:05:44.169888 Final RX Vref Byte 1 = 59 to rank1==
1185 11:05:44.173507 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 11:05:44.176667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 11:05:44.179929 ==
1188 11:05:44.180011 DQS Delay:
1189 11:05:44.180075 DQS0 = 0, DQS1 = 0
1190 11:05:44.183740 DQM Delay:
1191 11:05:44.183821 DQM0 = 88, DQM1 = 79
1192 11:05:44.186684 DQ Delay:
1193 11:05:44.186812 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1194 11:05:44.189958 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1195 11:05:44.193607 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1196 11:05:44.197068 DQ12 =88, DQ13 =80, DQ14 =88, DQ15 =88
1197 11:05:44.197180
1198 11:05:44.199902
1199 11:05:44.206811 [DQSOSCAuto] RK0, (LSB)MR18= 0x2910, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1200 11:05:44.210288 CH0 RK0: MR19=606, MR18=2910
1201 11:05:44.216955 CH0_RK0: MR19=0x606, MR18=0x2910, DQSOSC=399, MR23=63, INC=92, DEC=61
1202 11:05:44.217038
1203 11:05:44.220427 ----->DramcWriteLeveling(PI) begin...
1204 11:05:44.220510 ==
1205 11:05:44.224117 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 11:05:44.226917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 11:05:44.227000 ==
1208 11:05:44.230126 Write leveling (Byte 0): 31 => 31
1209 11:05:44.233270 Write leveling (Byte 1): 29 => 29
1210 11:05:44.236687 DramcWriteLeveling(PI) end<-----
1211 11:05:44.236769
1212 11:05:44.236833 ==
1213 11:05:44.240183 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 11:05:44.243962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 11:05:44.244044 ==
1216 11:05:44.247085 [Gating] SW mode calibration
1217 11:05:44.253478 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 11:05:44.260233 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 11:05:44.303924 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 11:05:44.304337 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1221 11:05:44.304422 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1222 11:05:44.304676 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:05:44.304745 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:05:44.304817 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:05:44.304880 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:05:44.304939 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:05:44.305008 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:05:44.305261 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:05:44.344755 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:05:44.345044 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:05:44.345142 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:05:44.345233 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:05:44.345689 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:05:44.346158 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:05:44.347067 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:05:44.347148 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1237 11:05:44.347398 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1238 11:05:44.349418 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:05:44.352638 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:05:44.356266 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:05:44.359623 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:05:44.362910 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:05:44.369469 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:05:44.372960 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:05:44.376525 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1246 11:05:44.383055 0 9 12 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
1247 11:05:44.386450 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 11:05:44.389615 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 11:05:44.396206 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 11:05:44.399567 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 11:05:44.403189 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 11:05:44.409711 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 1)
1253 11:05:44.413196 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
1254 11:05:44.416302 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1255 11:05:44.419856 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 11:05:44.426831 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 11:05:44.429779 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 11:05:44.433116 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 11:05:44.441189 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 11:05:44.444275 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1261 11:05:44.447979 0 11 8 | B1->B0 | 2c2c 4141 | 0 1 | (0 0) (0 0)
1262 11:05:44.451545 0 11 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
1263 11:05:44.458110 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 11:05:44.461897 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 11:05:44.465592 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 11:05:44.469083 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 11:05:44.475484 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 11:05:44.479528 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 11:05:44.482339 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1270 11:05:44.488967 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1271 11:05:44.492661 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:05:44.495542 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:05:44.498984 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:05:44.505831 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:05:44.509463 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:05:44.512556 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:05:44.519664 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:05:44.522752 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:05:44.525834 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:05:44.532991 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:05:44.536290 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 11:05:44.539583 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 11:05:44.546026 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 11:05:44.549674 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1285 11:05:44.552989 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1286 11:05:44.555918 Total UI for P1: 0, mck2ui 16
1287 11:05:44.559467 best dqsien dly found for B0: ( 0, 14, 4)
1288 11:05:44.563305 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1289 11:05:44.566426 Total UI for P1: 0, mck2ui 16
1290 11:05:44.569687 best dqsien dly found for B1: ( 0, 14, 8)
1291 11:05:44.573460 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1292 11:05:44.576761 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1293 11:05:44.576846
1294 11:05:44.583146 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1295 11:05:44.586733 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1296 11:05:44.586815 [Gating] SW calibration Done
1297 11:05:44.589509 ==
1298 11:05:44.589616 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 11:05:44.597016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 11:05:44.597098 ==
1301 11:05:44.597162 RX Vref Scan: 0
1302 11:05:44.597223
1303 11:05:44.600033 RX Vref 0 -> 0, step: 1
1304 11:05:44.600114
1305 11:05:44.603278 RX Delay -130 -> 252, step: 16
1306 11:05:44.606605 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1307 11:05:44.609508 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1308 11:05:44.612957 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1309 11:05:44.619724 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1310 11:05:44.622853 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1311 11:05:44.626705 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1312 11:05:44.630337 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1313 11:05:44.633272 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1314 11:05:44.639952 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1315 11:05:44.643235 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1316 11:05:44.646647 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1317 11:05:44.650193 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1318 11:05:44.653536 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1319 11:05:44.659913 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1320 11:05:44.663226 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1321 11:05:44.667093 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1322 11:05:44.667213 ==
1323 11:05:44.670001 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 11:05:44.673443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 11:05:44.673566 ==
1326 11:05:44.676919 DQS Delay:
1327 11:05:44.677045 DQS0 = 0, DQS1 = 0
1328 11:05:44.680127 DQM Delay:
1329 11:05:44.680250 DQM0 = 86, DQM1 = 75
1330 11:05:44.680364 DQ Delay:
1331 11:05:44.683180 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1332 11:05:44.686888 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1333 11:05:44.690258 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1334 11:05:44.693577 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1335 11:05:44.693699
1336 11:05:44.693814
1337 11:05:44.693923 ==
1338 11:05:44.696750 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 11:05:44.704231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 11:05:44.704357 ==
1341 11:05:44.704473
1342 11:05:44.704584
1343 11:05:44.704691 TX Vref Scan disable
1344 11:05:44.707329 == TX Byte 0 ==
1345 11:05:44.710621 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1346 11:05:44.717293 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1347 11:05:44.717419 == TX Byte 1 ==
1348 11:05:44.721110 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1349 11:05:44.727275 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1350 11:05:44.727403 ==
1351 11:05:44.730693 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 11:05:44.733758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 11:05:44.733882 ==
1354 11:05:44.746380 TX Vref=22, minBit 3, minWin=27, winSum=443
1355 11:05:44.749800 TX Vref=24, minBit 3, minWin=27, winSum=446
1356 11:05:44.753607 TX Vref=26, minBit 9, minWin=27, winSum=451
1357 11:05:44.756514 TX Vref=28, minBit 9, minWin=27, winSum=452
1358 11:05:44.759894 TX Vref=30, minBit 2, minWin=28, winSum=456
1359 11:05:44.763157 TX Vref=32, minBit 2, minWin=28, winSum=454
1360 11:05:44.770013 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 30
1361 11:05:44.770156
1362 11:05:44.773346 Final TX Range 1 Vref 30
1363 11:05:44.773471
1364 11:05:44.773624 ==
1365 11:05:44.776882 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 11:05:44.780083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 11:05:44.780203 ==
1368 11:05:44.780315
1369 11:05:44.780423
1370 11:05:44.783394 TX Vref Scan disable
1371 11:05:44.786678 == TX Byte 0 ==
1372 11:05:44.790056 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1373 11:05:44.793343 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1374 11:05:44.796431 == TX Byte 1 ==
1375 11:05:44.799682 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1376 11:05:44.803304 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1377 11:05:44.803425
1378 11:05:44.806565 [DATLAT]
1379 11:05:44.806686 Freq=800, CH0 RK1
1380 11:05:44.806800
1381 11:05:44.810073 DATLAT Default: 0xa
1382 11:05:44.810193 0, 0xFFFF, sum = 0
1383 11:05:44.813774 1, 0xFFFF, sum = 0
1384 11:05:44.813899 2, 0xFFFF, sum = 0
1385 11:05:44.816707 3, 0xFFFF, sum = 0
1386 11:05:44.816833 4, 0xFFFF, sum = 0
1387 11:05:44.819864 5, 0xFFFF, sum = 0
1388 11:05:44.819989 6, 0xFFFF, sum = 0
1389 11:05:44.823675 7, 0xFFFF, sum = 0
1390 11:05:44.823800 8, 0xFFFF, sum = 0
1391 11:05:44.826644 9, 0x0, sum = 1
1392 11:05:44.826765 10, 0x0, sum = 2
1393 11:05:44.829960 11, 0x0, sum = 3
1394 11:05:44.830085 12, 0x0, sum = 4
1395 11:05:44.833517 best_step = 10
1396 11:05:44.833637
1397 11:05:44.833749 ==
1398 11:05:44.836814 Dram Type= 6, Freq= 0, CH_0, rank 1
1399 11:05:44.840174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 11:05:44.840298 ==
1401 11:05:44.843705 RX Vref Scan: 0
1402 11:05:44.843826
1403 11:05:44.843940 RX Vref 0 -> 0, step: 1
1404 11:05:44.844050
1405 11:05:44.846666 RX Delay -95 -> 252, step: 8
1406 11:05:44.850487 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1407 11:05:44.856992 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1408 11:05:44.860420 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1409 11:05:44.864436 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1410 11:05:44.867118 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1411 11:05:44.870278 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1412 11:05:44.877472 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1413 11:05:44.880464 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1414 11:05:44.883872 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1415 11:05:44.887175 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1416 11:05:44.890521 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1417 11:05:44.897277 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1418 11:05:44.901076 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1419 11:05:44.903872 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1420 11:05:44.907320 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1421 11:05:44.910860 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1422 11:05:44.910947 ==
1423 11:05:44.914001 Dram Type= 6, Freq= 0, CH_0, rank 1
1424 11:05:44.920889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 11:05:44.920971 ==
1426 11:05:44.921037 DQS Delay:
1427 11:05:44.924826 DQS0 = 0, DQS1 = 0
1428 11:05:44.924908 DQM Delay:
1429 11:05:44.924972 DQM0 = 87, DQM1 = 78
1430 11:05:44.927506 DQ Delay:
1431 11:05:44.930681 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1432 11:05:44.934165 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1433 11:05:44.937280 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1434 11:05:44.940518 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1435 11:05:44.940602
1436 11:05:44.940667
1437 11:05:44.947236 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1438 11:05:44.950807 CH0 RK1: MR19=606, MR18=2C16
1439 11:05:44.957530 CH0_RK1: MR19=0x606, MR18=0x2C16, DQSOSC=398, MR23=63, INC=93, DEC=62
1440 11:05:44.960912 [RxdqsGatingPostProcess] freq 800
1441 11:05:44.964189 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1442 11:05:44.967576 Pre-setting of DQS Precalculation
1443 11:05:44.974324 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1444 11:05:44.974465 ==
1445 11:05:44.977886 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 11:05:44.981198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 11:05:44.981306 ==
1448 11:05:44.987636 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1449 11:05:44.990925 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1450 11:05:45.001682 [CA 0] Center 36 (6~66) winsize 61
1451 11:05:45.004632 [CA 1] Center 36 (6~66) winsize 61
1452 11:05:45.008106 [CA 2] Center 35 (5~65) winsize 61
1453 11:05:45.011695 [CA 3] Center 34 (3~65) winsize 63
1454 11:05:45.014815 [CA 4] Center 34 (4~65) winsize 62
1455 11:05:45.018105 [CA 5] Center 33 (3~64) winsize 62
1456 11:05:45.018201
1457 11:05:45.021452 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1458 11:05:45.021530
1459 11:05:45.024570 [CATrainingPosCal] consider 1 rank data
1460 11:05:45.028057 u2DelayCellTimex100 = 270/100 ps
1461 11:05:45.031785 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1462 11:05:45.035442 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1463 11:05:45.041272 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1464 11:05:45.044535 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1465 11:05:45.048021 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1466 11:05:45.051287 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1467 11:05:45.051380
1468 11:05:45.054727 CA PerBit enable=1, Macro0, CA PI delay=33
1469 11:05:45.054807
1470 11:05:45.058045 [CBTSetCACLKResult] CA Dly = 33
1471 11:05:45.058125 CS Dly: 4 (0~35)
1472 11:05:45.058208 ==
1473 11:05:45.060993 Dram Type= 6, Freq= 0, CH_1, rank 1
1474 11:05:45.067816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 11:05:45.067925 ==
1476 11:05:45.071078 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1477 11:05:45.078119 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1478 11:05:45.087576 [CA 0] Center 36 (6~66) winsize 61
1479 11:05:45.090595 [CA 1] Center 36 (6~66) winsize 61
1480 11:05:45.094148 [CA 2] Center 34 (4~65) winsize 62
1481 11:05:45.097776 [CA 3] Center 33 (3~64) winsize 62
1482 11:05:45.101191 [CA 4] Center 34 (3~65) winsize 63
1483 11:05:45.104741 [CA 5] Center 33 (3~64) winsize 62
1484 11:05:45.104866
1485 11:05:45.108412 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1486 11:05:45.108501
1487 11:05:45.112413 [CATrainingPosCal] consider 2 rank data
1488 11:05:45.116019 u2DelayCellTimex100 = 270/100 ps
1489 11:05:45.119998 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1490 11:05:45.123972 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1491 11:05:45.127641 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1492 11:05:45.130958 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1493 11:05:45.134673 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1494 11:05:45.138301 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1495 11:05:45.138434
1496 11:05:45.141592 CA PerBit enable=1, Macro0, CA PI delay=33
1497 11:05:45.141665
1498 11:05:45.144939 [CBTSetCACLKResult] CA Dly = 33
1499 11:05:45.145030 CS Dly: 5 (0~37)
1500 11:05:45.145107
1501 11:05:45.148289 ----->DramcWriteLeveling(PI) begin...
1502 11:05:45.148381 ==
1503 11:05:45.151496 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 11:05:45.154934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 11:05:45.158075 ==
1506 11:05:45.158159 Write leveling (Byte 0): 28 => 28
1507 11:05:45.161405 Write leveling (Byte 1): 29 => 29
1508 11:05:45.165437 DramcWriteLeveling(PI) end<-----
1509 11:05:45.165516
1510 11:05:45.165577 ==
1511 11:05:45.168190 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 11:05:45.174762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1513 11:05:45.174843 ==
1514 11:05:45.174926 [Gating] SW mode calibration
1515 11:05:45.185079 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1516 11:05:45.188455 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1517 11:05:45.191691 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1518 11:05:45.198348 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1519 11:05:45.201825 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1520 11:05:45.205371 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:05:45.211605 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:05:45.215395 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:05:45.218774 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:05:45.225100 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:05:45.228794 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:05:45.232023 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:05:45.238724 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:05:45.241833 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:05:45.245344 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:05:45.251753 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:05:45.255221 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:05:45.258451 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:05:45.261783 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:05:45.269041 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1535 11:05:45.271938 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1536 11:05:45.275725 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:05:45.281903 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:05:45.285425 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:05:45.289034 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:05:45.295258 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:05:45.298866 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:05:45.301931 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 11:05:45.308814 0 9 8 | B1->B0 | 2525 2626 | 1 1 | (0 0) (1 1)
1544 11:05:45.312401 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 11:05:45.315550 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 11:05:45.319276 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 11:05:45.325741 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 11:05:45.329308 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1549 11:05:45.332431 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 11:05:45.338890 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1551 11:05:45.343198 0 10 8 | B1->B0 | 3030 2f2f | 0 1 | (0 1) (1 0)
1552 11:05:45.345907 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1553 11:05:45.353181 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1554 11:05:45.356134 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 11:05:45.359390 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1556 11:05:45.366092 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 11:05:45.369437 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 11:05:45.372691 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 11:05:45.375826 0 11 8 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
1560 11:05:45.383176 0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1561 11:05:45.386173 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 11:05:45.389969 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 11:05:45.396101 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 11:05:45.399599 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 11:05:45.403175 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 11:05:45.409619 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 11:05:45.413660 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:05:45.416762 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:05:45.423177 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:05:45.426441 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:05:45.429810 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:05:45.436240 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:05:45.439675 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:05:45.443080 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:05:45.446718 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:05:45.453376 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:05:45.456669 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:05:45.459993 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:05:45.466656 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:05:45.469828 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 11:05:45.473760 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 11:05:45.480289 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1583 11:05:45.483513 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1584 11:05:45.487122 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 11:05:45.490111 Total UI for P1: 0, mck2ui 16
1586 11:05:45.493810 best dqsien dly found for B0: ( 0, 14, 6)
1587 11:05:45.497080 Total UI for P1: 0, mck2ui 16
1588 11:05:45.501071 best dqsien dly found for B1: ( 0, 14, 6)
1589 11:05:45.503551 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1590 11:05:45.507158 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1591 11:05:45.507239
1592 11:05:45.510610 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1593 11:05:45.516673 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1594 11:05:45.516756 [Gating] SW calibration Done
1595 11:05:45.516818 ==
1596 11:05:45.519970 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 11:05:45.526839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 11:05:45.526920 ==
1599 11:05:45.526984 RX Vref Scan: 0
1600 11:05:45.527043
1601 11:05:45.530106 RX Vref 0 -> 0, step: 1
1602 11:05:45.530213
1603 11:05:45.534006 RX Delay -130 -> 252, step: 16
1604 11:05:45.536881 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1605 11:05:45.540342 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1606 11:05:45.543540 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1607 11:05:45.547314 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1608 11:05:45.553843 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1609 11:05:45.557557 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1610 11:05:45.560393 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1611 11:05:45.564229 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1612 11:05:45.566989 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1613 11:05:45.571002 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1614 11:05:45.577597 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1615 11:05:45.580784 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1616 11:05:45.584017 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1617 11:05:45.587784 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1618 11:05:45.593867 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1619 11:05:45.597412 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1620 11:05:45.597495 ==
1621 11:05:45.600691 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 11:05:45.603915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 11:05:45.603998 ==
1624 11:05:45.604063 DQS Delay:
1625 11:05:45.607817 DQS0 = 0, DQS1 = 0
1626 11:05:45.607893 DQM Delay:
1627 11:05:45.610568 DQM0 = 84, DQM1 = 76
1628 11:05:45.610665 DQ Delay:
1629 11:05:45.614229 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1630 11:05:45.617606 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =85
1631 11:05:45.620759 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1632 11:05:45.624373 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1633 11:05:45.624448
1634 11:05:45.624509
1635 11:05:45.624570 ==
1636 11:05:45.627375 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 11:05:45.631079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 11:05:45.631156 ==
1639 11:05:45.634182
1640 11:05:45.634257
1641 11:05:45.634319 TX Vref Scan disable
1642 11:05:45.637634 == TX Byte 0 ==
1643 11:05:45.641050 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1644 11:05:45.644314 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1645 11:05:45.647675 == TX Byte 1 ==
1646 11:05:45.651089 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1647 11:05:45.654462 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1648 11:05:45.654587 ==
1649 11:05:45.657965 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 11:05:45.664332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 11:05:45.664461 ==
1652 11:05:45.676223 TX Vref=22, minBit 0, minWin=27, winSum=437
1653 11:05:45.679786 TX Vref=24, minBit 1, minWin=27, winSum=441
1654 11:05:45.683130 TX Vref=26, minBit 1, minWin=27, winSum=448
1655 11:05:45.687076 TX Vref=28, minBit 8, minWin=27, winSum=449
1656 11:05:45.690532 TX Vref=30, minBit 0, minWin=27, winSum=451
1657 11:05:45.693412 TX Vref=32, minBit 0, minWin=28, winSum=454
1658 11:05:45.700671 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
1659 11:05:45.700814
1660 11:05:45.703778 Final TX Range 1 Vref 32
1661 11:05:45.703872
1662 11:05:45.703935 ==
1663 11:05:45.707051 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 11:05:45.710372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1665 11:05:45.710482 ==
1666 11:05:45.710545
1667 11:05:45.710604
1668 11:05:45.713793 TX Vref Scan disable
1669 11:05:45.717405 == TX Byte 0 ==
1670 11:05:45.720676 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1671 11:05:45.723968 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1672 11:05:45.727457 == TX Byte 1 ==
1673 11:05:45.730517 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1674 11:05:45.733809 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1675 11:05:45.733880
1676 11:05:45.733942 [DATLAT]
1677 11:05:45.737457 Freq=800, CH1 RK0
1678 11:05:45.737544
1679 11:05:45.737609 DATLAT Default: 0xa
1680 11:05:45.741017 0, 0xFFFF, sum = 0
1681 11:05:45.741143 1, 0xFFFF, sum = 0
1682 11:05:45.743966 2, 0xFFFF, sum = 0
1683 11:05:45.744048 3, 0xFFFF, sum = 0
1684 11:05:45.747447 4, 0xFFFF, sum = 0
1685 11:05:45.750762 5, 0xFFFF, sum = 0
1686 11:05:45.750835 6, 0xFFFF, sum = 0
1687 11:05:45.754124 7, 0xFFFF, sum = 0
1688 11:05:45.754202 8, 0xFFFF, sum = 0
1689 11:05:45.754304 9, 0x0, sum = 1
1690 11:05:45.757214 10, 0x0, sum = 2
1691 11:05:45.757289 11, 0x0, sum = 3
1692 11:05:45.760603 12, 0x0, sum = 4
1693 11:05:45.760676 best_step = 10
1694 11:05:45.760745
1695 11:05:45.760807 ==
1696 11:05:45.763966 Dram Type= 6, Freq= 0, CH_1, rank 0
1697 11:05:45.771069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1698 11:05:45.771154 ==
1699 11:05:45.771239 RX Vref Scan: 1
1700 11:05:45.771347
1701 11:05:45.774346 Set Vref Range= 32 -> 127
1702 11:05:45.774454
1703 11:05:45.777533 RX Vref 32 -> 127, step: 1
1704 11:05:45.777616
1705 11:05:45.781276 RX Delay -111 -> 252, step: 8
1706 11:05:45.781361
1707 11:05:45.784193 Set Vref, RX VrefLevel [Byte0]: 32
1708 11:05:45.784280 [Byte1]: 32
1709 11:05:45.788509
1710 11:05:45.788616 Set Vref, RX VrefLevel [Byte0]: 33
1711 11:05:45.792498 [Byte1]: 33
1712 11:05:45.796566
1713 11:05:45.796652 Set Vref, RX VrefLevel [Byte0]: 34
1714 11:05:45.799571 [Byte1]: 34
1715 11:05:45.804066
1716 11:05:45.804152 Set Vref, RX VrefLevel [Byte0]: 35
1717 11:05:45.807201 [Byte1]: 35
1718 11:05:45.811446
1719 11:05:45.811532 Set Vref, RX VrefLevel [Byte0]: 36
1720 11:05:45.814703 [Byte1]: 36
1721 11:05:45.819155
1722 11:05:45.819240 Set Vref, RX VrefLevel [Byte0]: 37
1723 11:05:45.822481 [Byte1]: 37
1724 11:05:45.826710
1725 11:05:45.826796 Set Vref, RX VrefLevel [Byte0]: 38
1726 11:05:45.830126 [Byte1]: 38
1727 11:05:45.834160
1728 11:05:45.837956 Set Vref, RX VrefLevel [Byte0]: 39
1729 11:05:45.838041 [Byte1]: 39
1730 11:05:45.842277
1731 11:05:45.842414 Set Vref, RX VrefLevel [Byte0]: 40
1732 11:05:45.845415 [Byte1]: 40
1733 11:05:45.849844
1734 11:05:45.849967 Set Vref, RX VrefLevel [Byte0]: 41
1735 11:05:45.853020 [Byte1]: 41
1736 11:05:45.857629
1737 11:05:45.857737 Set Vref, RX VrefLevel [Byte0]: 42
1738 11:05:45.861100 [Byte1]: 42
1739 11:05:45.865831
1740 11:05:45.865913 Set Vref, RX VrefLevel [Byte0]: 43
1741 11:05:45.868431 [Byte1]: 43
1742 11:05:45.872553
1743 11:05:45.872635 Set Vref, RX VrefLevel [Byte0]: 44
1744 11:05:45.876372 [Byte1]: 44
1745 11:05:45.880207
1746 11:05:45.880289 Set Vref, RX VrefLevel [Byte0]: 45
1747 11:05:45.883959 [Byte1]: 45
1748 11:05:45.888238
1749 11:05:45.888321 Set Vref, RX VrefLevel [Byte0]: 46
1750 11:05:45.891480 [Byte1]: 46
1751 11:05:45.895605
1752 11:05:45.895687 Set Vref, RX VrefLevel [Byte0]: 47
1753 11:05:45.899083 [Byte1]: 47
1754 11:05:45.903323
1755 11:05:45.903405 Set Vref, RX VrefLevel [Byte0]: 48
1756 11:05:45.906884 [Byte1]: 48
1757 11:05:45.910972
1758 11:05:45.911054 Set Vref, RX VrefLevel [Byte0]: 49
1759 11:05:45.914210 [Byte1]: 49
1760 11:05:45.918798
1761 11:05:45.918922 Set Vref, RX VrefLevel [Byte0]: 50
1762 11:05:45.922217 [Byte1]: 50
1763 11:05:45.926080
1764 11:05:45.926184 Set Vref, RX VrefLevel [Byte0]: 51
1765 11:05:45.929455 [Byte1]: 51
1766 11:05:45.933983
1767 11:05:45.934064 Set Vref, RX VrefLevel [Byte0]: 52
1768 11:05:45.937220 [Byte1]: 52
1769 11:05:45.941800
1770 11:05:45.941908 Set Vref, RX VrefLevel [Byte0]: 53
1771 11:05:45.944687 [Byte1]: 53
1772 11:05:45.949466
1773 11:05:45.949548 Set Vref, RX VrefLevel [Byte0]: 54
1774 11:05:45.952780 [Byte1]: 54
1775 11:05:45.956779
1776 11:05:45.956860 Set Vref, RX VrefLevel [Byte0]: 55
1777 11:05:45.960220 [Byte1]: 55
1778 11:05:45.964351
1779 11:05:45.964433 Set Vref, RX VrefLevel [Byte0]: 56
1780 11:05:45.968134 [Byte1]: 56
1781 11:05:45.972348
1782 11:05:45.972429 Set Vref, RX VrefLevel [Byte0]: 57
1783 11:05:45.975571 [Byte1]: 57
1784 11:05:45.979779
1785 11:05:45.979861 Set Vref, RX VrefLevel [Byte0]: 58
1786 11:05:45.983287 [Byte1]: 58
1787 11:05:45.987318
1788 11:05:45.987400 Set Vref, RX VrefLevel [Byte0]: 59
1789 11:05:45.991026 [Byte1]: 59
1790 11:05:45.995004
1791 11:05:45.995122 Set Vref, RX VrefLevel [Byte0]: 60
1792 11:05:45.998797 [Byte1]: 60
1793 11:05:46.002646
1794 11:05:46.002751 Set Vref, RX VrefLevel [Byte0]: 61
1795 11:05:46.006509 [Byte1]: 61
1796 11:05:46.010287
1797 11:05:46.010394 Set Vref, RX VrefLevel [Byte0]: 62
1798 11:05:46.013813 [Byte1]: 62
1799 11:05:46.017969
1800 11:05:46.018071 Set Vref, RX VrefLevel [Byte0]: 63
1801 11:05:46.021585 [Byte1]: 63
1802 11:05:46.025521
1803 11:05:46.025630 Set Vref, RX VrefLevel [Byte0]: 64
1804 11:05:46.029010 [Byte1]: 64
1805 11:05:46.033247
1806 11:05:46.033354 Set Vref, RX VrefLevel [Byte0]: 65
1807 11:05:46.036704 [Byte1]: 65
1808 11:05:46.041051
1809 11:05:46.041152 Set Vref, RX VrefLevel [Byte0]: 66
1810 11:05:46.044312 [Byte1]: 66
1811 11:05:46.048696
1812 11:05:46.048799 Set Vref, RX VrefLevel [Byte0]: 67
1813 11:05:46.051991 [Byte1]: 67
1814 11:05:46.056333
1815 11:05:46.056439 Set Vref, RX VrefLevel [Byte0]: 68
1816 11:05:46.059602 [Byte1]: 68
1817 11:05:46.064460
1818 11:05:46.064559 Set Vref, RX VrefLevel [Byte0]: 69
1819 11:05:46.067242 [Byte1]: 69
1820 11:05:46.072195
1821 11:05:46.072274 Set Vref, RX VrefLevel [Byte0]: 70
1822 11:05:46.075274 [Byte1]: 70
1823 11:05:46.079415
1824 11:05:46.079488 Set Vref, RX VrefLevel [Byte0]: 71
1825 11:05:46.082376 [Byte1]: 71
1826 11:05:46.086796
1827 11:05:46.086901 Set Vref, RX VrefLevel [Byte0]: 72
1828 11:05:46.090385 [Byte1]: 72
1829 11:05:46.094391
1830 11:05:46.094485 Set Vref, RX VrefLevel [Byte0]: 73
1831 11:05:46.098656 [Byte1]: 73
1832 11:05:46.102011
1833 11:05:46.102118 Set Vref, RX VrefLevel [Byte0]: 74
1834 11:05:46.105364 [Byte1]: 74
1835 11:05:46.109918
1836 11:05:46.110024 Set Vref, RX VrefLevel [Byte0]: 75
1837 11:05:46.113149 [Byte1]: 75
1838 11:05:46.117987
1839 11:05:46.118097 Set Vref, RX VrefLevel [Byte0]: 76
1840 11:05:46.121074 [Byte1]: 76
1841 11:05:46.125167
1842 11:05:46.125271 Set Vref, RX VrefLevel [Byte0]: 77
1843 11:05:46.128729 [Byte1]: 77
1844 11:05:46.132594
1845 11:05:46.132706 Set Vref, RX VrefLevel [Byte0]: 78
1846 11:05:46.135797 [Byte1]: 78
1847 11:05:46.140165
1848 11:05:46.140279 Set Vref, RX VrefLevel [Byte0]: 79
1849 11:05:46.143552 [Byte1]: 79
1850 11:05:46.148073
1851 11:05:46.148182 Set Vref, RX VrefLevel [Byte0]: 80
1852 11:05:46.151851 [Byte1]: 80
1853 11:05:46.156069
1854 11:05:46.156178 Final RX Vref Byte 0 = 58 to rank0
1855 11:05:46.159143 Final RX Vref Byte 1 = 57 to rank0
1856 11:05:46.162560 Final RX Vref Byte 0 = 58 to rank1
1857 11:05:46.165784 Final RX Vref Byte 1 = 57 to rank1==
1858 11:05:46.169347 Dram Type= 6, Freq= 0, CH_1, rank 0
1859 11:05:46.172604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1860 11:05:46.176360 ==
1861 11:05:46.176473 DQS Delay:
1862 11:05:46.176569 DQS0 = 0, DQS1 = 0
1863 11:05:46.179442 DQM Delay:
1864 11:05:46.179544 DQM0 = 83, DQM1 = 75
1865 11:05:46.182912 DQ Delay:
1866 11:05:46.183014 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1867 11:05:46.186202 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =76
1868 11:05:46.189651 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =76
1869 11:05:46.192617 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1870 11:05:46.192727
1871 11:05:46.192824
1872 11:05:46.202936 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b00, (MSB)MR19= 0x606, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
1873 11:05:46.206858 CH1 RK0: MR19=606, MR18=2B00
1874 11:05:46.209638 CH1_RK0: MR19=0x606, MR18=0x2B00, DQSOSC=398, MR23=63, INC=93, DEC=62
1875 11:05:46.209742
1876 11:05:46.216737 ----->DramcWriteLeveling(PI) begin...
1877 11:05:46.216845 ==
1878 11:05:46.219818 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 11:05:46.223090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 11:05:46.223196 ==
1881 11:05:46.226124 Write leveling (Byte 0): 29 => 29
1882 11:05:46.230006 Write leveling (Byte 1): 30 => 30
1883 11:05:46.232892 DramcWriteLeveling(PI) end<-----
1884 11:05:46.232996
1885 11:05:46.233091 ==
1886 11:05:46.236464 Dram Type= 6, Freq= 0, CH_1, rank 1
1887 11:05:46.239704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1888 11:05:46.239810 ==
1889 11:05:46.243318 [Gating] SW mode calibration
1890 11:05:46.249942 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1891 11:05:46.253079 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1892 11:05:46.259723 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1893 11:05:46.263319 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1894 11:05:46.266541 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:05:46.273220 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:05:46.276816 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:05:46.279815 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:05:46.286629 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 11:05:46.289841 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 11:05:46.293178 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 11:05:46.300267 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:05:46.303566 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 11:05:46.306741 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 11:05:46.310085 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:05:46.316630 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:05:46.320052 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:05:46.323892 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:05:46.330251 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1909 11:05:46.333450 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1910 11:05:46.337109 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1911 11:05:46.344022 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 11:05:46.347292 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 11:05:46.350442 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 11:05:46.357066 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 11:05:46.360546 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 11:05:46.363392 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 11:05:46.370201 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
1918 11:05:46.373513 0 9 8 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
1919 11:05:46.377303 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1920 11:05:46.383335 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1921 11:05:46.387148 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1922 11:05:46.390001 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1923 11:05:46.393924 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1924 11:05:46.400140 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
1925 11:05:46.403482 0 10 4 | B1->B0 | 2f2f 2e2e | 1 0 | (1 0) (0 1)
1926 11:05:46.409916 0 10 8 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
1927 11:05:46.413249 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 11:05:46.416662 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 11:05:46.420132 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1930 11:05:46.427719 0 10 24 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1931 11:05:46.430680 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1932 11:05:46.433361 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1933 11:05:46.439715 0 11 4 | B1->B0 | 2d2d 3535 | 1 0 | (0 0) (0 0)
1934 11:05:46.443197 0 11 8 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
1935 11:05:46.446434 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 11:05:46.453738 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 11:05:46.456729 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 11:05:46.460086 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 11:05:46.466468 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1940 11:05:46.470001 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1941 11:05:46.473225 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1942 11:05:46.480081 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 11:05:46.483350 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 11:05:46.487015 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 11:05:46.493316 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 11:05:46.496694 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 11:05:46.500191 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 11:05:46.503393 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 11:05:46.510096 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 11:05:46.513509 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 11:05:46.517217 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 11:05:46.523604 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 11:05:46.527021 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 11:05:46.530241 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 11:05:46.536800 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 11:05:46.540417 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 11:05:46.543719 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1958 11:05:46.550300 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1959 11:05:46.550385 Total UI for P1: 0, mck2ui 16
1960 11:05:46.556944 best dqsien dly found for B0: ( 0, 14, 4)
1961 11:05:46.557076 Total UI for P1: 0, mck2ui 16
1962 11:05:46.560641 best dqsien dly found for B1: ( 0, 14, 6)
1963 11:05:46.563897 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1964 11:05:46.570912 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1965 11:05:46.571041
1966 11:05:46.573794 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1967 11:05:46.576957 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1968 11:05:46.580915 [Gating] SW calibration Done
1969 11:05:46.581039 ==
1970 11:05:46.584234 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 11:05:46.587313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 11:05:46.587438 ==
1973 11:05:46.587555 RX Vref Scan: 0
1974 11:05:46.587664
1975 11:05:46.590867 RX Vref 0 -> 0, step: 1
1976 11:05:46.590988
1977 11:05:46.593562 RX Delay -130 -> 252, step: 16
1978 11:05:46.597269 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1979 11:05:46.600561 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1980 11:05:46.607034 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1981 11:05:46.610536 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1982 11:05:46.613726 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1983 11:05:46.617471 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1984 11:05:46.620782 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1985 11:05:46.627516 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1986 11:05:46.631094 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1987 11:05:46.634028 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1988 11:05:46.637557 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1989 11:05:46.640818 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1990 11:05:46.647707 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1991 11:05:46.650539 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1992 11:05:46.654008 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1993 11:05:46.657462 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1994 11:05:46.657587 ==
1995 11:05:46.661153 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 11:05:46.664063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 11:05:46.667727 ==
1998 11:05:46.667837 DQS Delay:
1999 11:05:46.667931 DQS0 = 0, DQS1 = 0
2000 11:05:46.671157 DQM Delay:
2001 11:05:46.671254 DQM0 = 80, DQM1 = 76
2002 11:05:46.671344 DQ Delay:
2003 11:05:46.674080 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
2004 11:05:46.677939 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =69
2005 11:05:46.681106 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
2006 11:05:46.684402 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2007 11:05:46.684486
2008 11:05:46.684552
2009 11:05:46.687661 ==
2010 11:05:46.690787 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 11:05:46.694329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 11:05:46.694465 ==
2013 11:05:46.694584
2014 11:05:46.694699
2015 11:05:46.697519 TX Vref Scan disable
2016 11:05:46.697635 == TX Byte 0 ==
2017 11:05:46.700810 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2018 11:05:46.707437 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2019 11:05:46.707563 == TX Byte 1 ==
2020 11:05:46.710747 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2021 11:05:46.717345 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2022 11:05:46.717473 ==
2023 11:05:46.720934 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 11:05:46.724433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 11:05:46.724557 ==
2026 11:05:46.737069 TX Vref=22, minBit 1, minWin=27, winSum=444
2027 11:05:46.740871 TX Vref=24, minBit 0, minWin=27, winSum=446
2028 11:05:46.744376 TX Vref=26, minBit 12, minWin=27, winSum=448
2029 11:05:46.747690 TX Vref=28, minBit 1, minWin=27, winSum=449
2030 11:05:46.750827 TX Vref=30, minBit 0, minWin=28, winSum=451
2031 11:05:46.754068 TX Vref=32, minBit 0, minWin=28, winSum=452
2032 11:05:46.760793 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 32
2033 11:05:46.760924
2034 11:05:46.764039 Final TX Range 1 Vref 32
2035 11:05:46.764125
2036 11:05:46.764190 ==
2037 11:05:46.767379 Dram Type= 6, Freq= 0, CH_1, rank 1
2038 11:05:46.770920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2039 11:05:46.771002 ==
2040 11:05:46.771068
2041 11:05:46.773900
2042 11:05:46.774007 TX Vref Scan disable
2043 11:05:46.777405 == TX Byte 0 ==
2044 11:05:46.780715 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2045 11:05:46.784240 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2046 11:05:46.787312 == TX Byte 1 ==
2047 11:05:46.791098 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2048 11:05:46.794169 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2049 11:05:46.794257
2050 11:05:46.797565 [DATLAT]
2051 11:05:46.797637 Freq=800, CH1 RK1
2052 11:05:46.797700
2053 11:05:46.801023 DATLAT Default: 0xa
2054 11:05:46.801106 0, 0xFFFF, sum = 0
2055 11:05:46.804413 1, 0xFFFF, sum = 0
2056 11:05:46.804496 2, 0xFFFF, sum = 0
2057 11:05:46.807900 3, 0xFFFF, sum = 0
2058 11:05:46.807985 4, 0xFFFF, sum = 0
2059 11:05:46.810720 5, 0xFFFF, sum = 0
2060 11:05:46.810804 6, 0xFFFF, sum = 0
2061 11:05:46.814384 7, 0xFFFF, sum = 0
2062 11:05:46.814478 8, 0xFFFF, sum = 0
2063 11:05:46.817867 9, 0x0, sum = 1
2064 11:05:46.817951 10, 0x0, sum = 2
2065 11:05:46.821251 11, 0x0, sum = 3
2066 11:05:46.821336 12, 0x0, sum = 4
2067 11:05:46.824677 best_step = 10
2068 11:05:46.824758
2069 11:05:46.824820 ==
2070 11:05:46.827915 Dram Type= 6, Freq= 0, CH_1, rank 1
2071 11:05:46.831430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2072 11:05:46.831518 ==
2073 11:05:46.834548 RX Vref Scan: 0
2074 11:05:46.834631
2075 11:05:46.834696 RX Vref 0 -> 0, step: 1
2076 11:05:46.834756
2077 11:05:46.837866 RX Delay -111 -> 252, step: 8
2078 11:05:46.844874 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2079 11:05:46.848139 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2080 11:05:46.851601 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2081 11:05:46.854583 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2082 11:05:46.857783 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2083 11:05:46.861137 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2084 11:05:46.867771 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2085 11:05:46.871384 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2086 11:05:46.874610 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2087 11:05:46.878171 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2088 11:05:46.881595 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2089 11:05:46.888468 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2090 11:05:46.891507 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2091 11:05:46.895021 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2092 11:05:46.898367 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2093 11:05:46.901611 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2094 11:05:46.901694 ==
2095 11:05:46.905244 Dram Type= 6, Freq= 0, CH_1, rank 1
2096 11:05:46.911472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2097 11:05:46.911557 ==
2098 11:05:46.911622 DQS Delay:
2099 11:05:46.915221 DQS0 = 0, DQS1 = 0
2100 11:05:46.915304 DQM Delay:
2101 11:05:46.915389 DQM0 = 80, DQM1 = 75
2102 11:05:46.919071 DQ Delay:
2103 11:05:46.921768 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2104 11:05:46.925099 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2105 11:05:46.928356 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2106 11:05:46.931716 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2107 11:05:46.931799
2108 11:05:46.931863
2109 11:05:46.938636 [DQSOSCAuto] RK1, (LSB)MR18= 0x232e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2110 11:05:46.941821 CH1 RK1: MR19=606, MR18=232E
2111 11:05:46.948629 CH1_RK1: MR19=0x606, MR18=0x232E, DQSOSC=398, MR23=63, INC=93, DEC=62
2112 11:05:46.952165 [RxdqsGatingPostProcess] freq 800
2113 11:05:46.955497 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2114 11:05:46.958869 Pre-setting of DQS Precalculation
2115 11:05:46.965355 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2116 11:05:46.972106 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2117 11:05:46.978935 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2118 11:05:46.979063
2119 11:05:46.979179
2120 11:05:46.982330 [Calibration Summary] 1600 Mbps
2121 11:05:46.982490 CH 0, Rank 0
2122 11:05:46.985539 SW Impedance : PASS
2123 11:05:46.988507 DUTY Scan : NO K
2124 11:05:46.988659 ZQ Calibration : PASS
2125 11:05:46.992086 Jitter Meter : NO K
2126 11:05:46.992206 CBT Training : PASS
2127 11:05:46.995501 Write leveling : PASS
2128 11:05:46.999174 RX DQS gating : PASS
2129 11:05:46.999298 RX DQ/DQS(RDDQC) : PASS
2130 11:05:47.002122 TX DQ/DQS : PASS
2131 11:05:47.005869 RX DATLAT : PASS
2132 11:05:47.005993 RX DQ/DQS(Engine): PASS
2133 11:05:47.008780 TX OE : NO K
2134 11:05:47.008900 All Pass.
2135 11:05:47.009011
2136 11:05:47.012073 CH 0, Rank 1
2137 11:05:47.012191 SW Impedance : PASS
2138 11:05:47.015696 DUTY Scan : NO K
2139 11:05:47.019239 ZQ Calibration : PASS
2140 11:05:47.019394 Jitter Meter : NO K
2141 11:05:47.022239 CBT Training : PASS
2142 11:05:47.025395 Write leveling : PASS
2143 11:05:47.025481 RX DQS gating : PASS
2144 11:05:47.028840 RX DQ/DQS(RDDQC) : PASS
2145 11:05:47.028924 TX DQ/DQS : PASS
2146 11:05:47.032770 RX DATLAT : PASS
2147 11:05:47.035787 RX DQ/DQS(Engine): PASS
2148 11:05:47.035884 TX OE : NO K
2149 11:05:47.039311 All Pass.
2150 11:05:47.039398
2151 11:05:47.039485 CH 1, Rank 0
2152 11:05:47.042490 SW Impedance : PASS
2153 11:05:47.042595 DUTY Scan : NO K
2154 11:05:47.045814 ZQ Calibration : PASS
2155 11:05:47.048916 Jitter Meter : NO K
2156 11:05:47.049000 CBT Training : PASS
2157 11:05:47.052761 Write leveling : PASS
2158 11:05:47.055691 RX DQS gating : PASS
2159 11:05:47.055815 RX DQ/DQS(RDDQC) : PASS
2160 11:05:47.059054 TX DQ/DQS : PASS
2161 11:05:47.062507 RX DATLAT : PASS
2162 11:05:47.062630 RX DQ/DQS(Engine): PASS
2163 11:05:47.065875 TX OE : NO K
2164 11:05:47.065959 All Pass.
2165 11:05:47.066042
2166 11:05:47.069086 CH 1, Rank 1
2167 11:05:47.069214 SW Impedance : PASS
2168 11:05:47.073079 DUTY Scan : NO K
2169 11:05:47.073163 ZQ Calibration : PASS
2170 11:05:47.075637 Jitter Meter : NO K
2171 11:05:47.079674 CBT Training : PASS
2172 11:05:47.079758 Write leveling : PASS
2173 11:05:47.082769 RX DQS gating : PASS
2174 11:05:47.085959 RX DQ/DQS(RDDQC) : PASS
2175 11:05:47.086045 TX DQ/DQS : PASS
2176 11:05:47.089367 RX DATLAT : PASS
2177 11:05:47.092691 RX DQ/DQS(Engine): PASS
2178 11:05:47.092778 TX OE : NO K
2179 11:05:47.092865 All Pass.
2180 11:05:47.095876
2181 11:05:47.095962 DramC Write-DBI off
2182 11:05:47.099730 PER_BANK_REFRESH: Hybrid Mode
2183 11:05:47.099815 TX_TRACKING: ON
2184 11:05:47.102864 [GetDramInforAfterCalByMRR] Vendor 6.
2185 11:05:47.106443 [GetDramInforAfterCalByMRR] Revision 606.
2186 11:05:47.112829 [GetDramInforAfterCalByMRR] Revision 2 0.
2187 11:05:47.112915 MR0 0x3b3b
2188 11:05:47.113001 MR8 0x5151
2189 11:05:47.115885 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2190 11:05:47.115969
2191 11:05:47.119940 MR0 0x3b3b
2192 11:05:47.120026 MR8 0x5151
2193 11:05:47.122974 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2194 11:05:47.123060
2195 11:05:47.132959 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2196 11:05:47.136218 [FAST_K] Save calibration result to emmc
2197 11:05:47.139641 [FAST_K] Save calibration result to emmc
2198 11:05:47.142934 dram_init: config_dvfs: 1
2199 11:05:47.146257 dramc_set_vcore_voltage set vcore to 662500
2200 11:05:47.146367 Read voltage for 1200, 2
2201 11:05:47.149505 Vio18 = 0
2202 11:05:47.149590 Vcore = 662500
2203 11:05:47.149675 Vdram = 0
2204 11:05:47.153008 Vddq = 0
2205 11:05:47.153093 Vmddr = 0
2206 11:05:47.156144 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2207 11:05:47.162884 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2208 11:05:47.166782 MEM_TYPE=3, freq_sel=15
2209 11:05:47.169862 sv_algorithm_assistance_LP4_1600
2210 11:05:47.173037 ============ PULL DRAM RESETB DOWN ============
2211 11:05:47.176815 ========== PULL DRAM RESETB DOWN end =========
2212 11:05:47.179954 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2213 11:05:47.183217 ===================================
2214 11:05:47.186910 LPDDR4 DRAM CONFIGURATION
2215 11:05:47.189952 ===================================
2216 11:05:47.193679 EX_ROW_EN[0] = 0x0
2217 11:05:47.193779 EX_ROW_EN[1] = 0x0
2218 11:05:47.196426 LP4Y_EN = 0x0
2219 11:05:47.196524 WORK_FSP = 0x0
2220 11:05:47.200458 WL = 0x4
2221 11:05:47.200565 RL = 0x4
2222 11:05:47.203083 BL = 0x2
2223 11:05:47.203166 RPST = 0x0
2224 11:05:47.206478 RD_PRE = 0x0
2225 11:05:47.206562 WR_PRE = 0x1
2226 11:05:47.210101 WR_PST = 0x0
2227 11:05:47.210191 DBI_WR = 0x0
2228 11:05:47.213431 DBI_RD = 0x0
2229 11:05:47.213534 OTF = 0x1
2230 11:05:47.216623 ===================================
2231 11:05:47.220630 ===================================
2232 11:05:47.223412 ANA top config
2233 11:05:47.226924 ===================================
2234 11:05:47.230032 DLL_ASYNC_EN = 0
2235 11:05:47.230140 ALL_SLAVE_EN = 0
2236 11:05:47.233365 NEW_RANK_MODE = 1
2237 11:05:47.237005 DLL_IDLE_MODE = 1
2238 11:05:47.239966 LP45_APHY_COMB_EN = 1
2239 11:05:47.240050 TX_ODT_DIS = 1
2240 11:05:47.243435 NEW_8X_MODE = 1
2241 11:05:47.247036 ===================================
2242 11:05:47.250256 ===================================
2243 11:05:47.253694 data_rate = 2400
2244 11:05:47.257056 CKR = 1
2245 11:05:47.260787 DQ_P2S_RATIO = 8
2246 11:05:47.263832 ===================================
2247 11:05:47.263917 CA_P2S_RATIO = 8
2248 11:05:47.267295 DQ_CA_OPEN = 0
2249 11:05:47.270346 DQ_SEMI_OPEN = 0
2250 11:05:47.274198 CA_SEMI_OPEN = 0
2251 11:05:47.277050 CA_FULL_RATE = 0
2252 11:05:47.280234 DQ_CKDIV4_EN = 0
2253 11:05:47.280316 CA_CKDIV4_EN = 0
2254 11:05:47.284051 CA_PREDIV_EN = 0
2255 11:05:47.287620 PH8_DLY = 17
2256 11:05:47.290671 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2257 11:05:47.294126 DQ_AAMCK_DIV = 4
2258 11:05:47.297235 CA_AAMCK_DIV = 4
2259 11:05:47.297319 CA_ADMCK_DIV = 4
2260 11:05:47.300752 DQ_TRACK_CA_EN = 0
2261 11:05:47.304251 CA_PICK = 1200
2262 11:05:47.307429 CA_MCKIO = 1200
2263 11:05:47.311256 MCKIO_SEMI = 0
2264 11:05:47.314162 PLL_FREQ = 2366
2265 11:05:47.317716 DQ_UI_PI_RATIO = 32
2266 11:05:47.317799 CA_UI_PI_RATIO = 0
2267 11:05:47.320997 ===================================
2268 11:05:47.324030 ===================================
2269 11:05:47.327890 memory_type:LPDDR4
2270 11:05:47.330721 GP_NUM : 10
2271 11:05:47.330806 SRAM_EN : 1
2272 11:05:47.334257 MD32_EN : 0
2273 11:05:47.337448 ===================================
2274 11:05:47.341202 [ANA_INIT] >>>>>>>>>>>>>>
2275 11:05:47.341288 <<<<<< [CONFIGURE PHASE]: ANA_TX
2276 11:05:47.344408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2277 11:05:47.347486 ===================================
2278 11:05:47.350992 data_rate = 2400,PCW = 0X5b00
2279 11:05:47.354267 ===================================
2280 11:05:47.357829 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2281 11:05:47.364387 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2282 11:05:47.371233 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2283 11:05:47.374280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2284 11:05:47.377776 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2285 11:05:47.381083 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2286 11:05:47.384550 [ANA_INIT] flow start
2287 11:05:47.384631 [ANA_INIT] PLL >>>>>>>>
2288 11:05:47.388323 [ANA_INIT] PLL <<<<<<<<
2289 11:05:47.391300 [ANA_INIT] MIDPI >>>>>>>>
2290 11:05:47.391382 [ANA_INIT] MIDPI <<<<<<<<
2291 11:05:47.394753 [ANA_INIT] DLL >>>>>>>>
2292 11:05:47.397822 [ANA_INIT] DLL <<<<<<<<
2293 11:05:47.397903 [ANA_INIT] flow end
2294 11:05:47.401288 ============ LP4 DIFF to SE enter ============
2295 11:05:47.407889 ============ LP4 DIFF to SE exit ============
2296 11:05:47.407971 [ANA_INIT] <<<<<<<<<<<<<
2297 11:05:47.411241 [Flow] Enable top DCM control >>>>>
2298 11:05:47.414822 [Flow] Enable top DCM control <<<<<
2299 11:05:47.417952 Enable DLL master slave shuffle
2300 11:05:47.424630 ==============================================================
2301 11:05:47.424711 Gating Mode config
2302 11:05:47.431440 ==============================================================
2303 11:05:47.434684 Config description:
2304 11:05:47.441460 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2305 11:05:47.448014 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2306 11:05:47.455101 SELPH_MODE 0: By rank 1: By Phase
2307 11:05:47.461792 ==============================================================
2308 11:05:47.461875 GAT_TRACK_EN = 1
2309 11:05:47.464995 RX_GATING_MODE = 2
2310 11:05:47.468442 RX_GATING_TRACK_MODE = 2
2311 11:05:47.471657 SELPH_MODE = 1
2312 11:05:47.475491 PICG_EARLY_EN = 1
2313 11:05:47.478237 VALID_LAT_VALUE = 1
2314 11:05:47.485092 ==============================================================
2315 11:05:47.488333 Enter into Gating configuration >>>>
2316 11:05:47.492005 Exit from Gating configuration <<<<
2317 11:05:47.495016 Enter into DVFS_PRE_config >>>>>
2318 11:05:47.505582 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2319 11:05:47.508512 Exit from DVFS_PRE_config <<<<<
2320 11:05:47.511869 Enter into PICG configuration >>>>
2321 11:05:47.515662 Exit from PICG configuration <<<<
2322 11:05:47.515767 [RX_INPUT] configuration >>>>>
2323 11:05:47.518606 [RX_INPUT] configuration <<<<<
2324 11:05:47.525388 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2325 11:05:47.529231 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2326 11:05:47.535821 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2327 11:05:47.542371 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2328 11:05:47.548991 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2329 11:05:47.555459 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2330 11:05:47.559087 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2331 11:05:47.562387 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2332 11:05:47.566046 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2333 11:05:47.572675 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2334 11:05:47.575741 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2335 11:05:47.579030 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2336 11:05:47.582782 ===================================
2337 11:05:47.586554 LPDDR4 DRAM CONFIGURATION
2338 11:05:47.588906 ===================================
2339 11:05:47.589008 EX_ROW_EN[0] = 0x0
2340 11:05:47.592589 EX_ROW_EN[1] = 0x0
2341 11:05:47.596389 LP4Y_EN = 0x0
2342 11:05:47.596488 WORK_FSP = 0x0
2343 11:05:47.599219 WL = 0x4
2344 11:05:47.599321 RL = 0x4
2345 11:05:47.602761 BL = 0x2
2346 11:05:47.602859 RPST = 0x0
2347 11:05:47.606508 RD_PRE = 0x0
2348 11:05:47.606609 WR_PRE = 0x1
2349 11:05:47.609332 WR_PST = 0x0
2350 11:05:47.609427 DBI_WR = 0x0
2351 11:05:47.612859 DBI_RD = 0x0
2352 11:05:47.612958 OTF = 0x1
2353 11:05:47.616437 ===================================
2354 11:05:47.619409 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2355 11:05:47.626308 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2356 11:05:47.629372 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2357 11:05:47.632920 ===================================
2358 11:05:47.636163 LPDDR4 DRAM CONFIGURATION
2359 11:05:47.639629 ===================================
2360 11:05:47.639793 EX_ROW_EN[0] = 0x10
2361 11:05:47.643156 EX_ROW_EN[1] = 0x0
2362 11:05:47.643295 LP4Y_EN = 0x0
2363 11:05:47.646157 WORK_FSP = 0x0
2364 11:05:47.646295 WL = 0x4
2365 11:05:47.649630 RL = 0x4
2366 11:05:47.649759 BL = 0x2
2367 11:05:47.652938 RPST = 0x0
2368 11:05:47.653078 RD_PRE = 0x0
2369 11:05:47.656091 WR_PRE = 0x1
2370 11:05:47.656214 WR_PST = 0x0
2371 11:05:47.659418 DBI_WR = 0x0
2372 11:05:47.659542 DBI_RD = 0x0
2373 11:05:47.663016 OTF = 0x1
2374 11:05:47.666526 ===================================
2375 11:05:47.673468 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2376 11:05:47.673646 ==
2377 11:05:47.676374 Dram Type= 6, Freq= 0, CH_0, rank 0
2378 11:05:47.679933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2379 11:05:47.680089 ==
2380 11:05:47.683152 [Duty_Offset_Calibration]
2381 11:05:47.683275 B0:2 B1:-1 CA:1
2382 11:05:47.683395
2383 11:05:47.685966 [DutyScan_Calibration_Flow] k_type=0
2384 11:05:47.696262
2385 11:05:47.696369 ==CLK 0==
2386 11:05:47.699563 Final CLK duty delay cell = -4
2387 11:05:47.703062 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2388 11:05:47.706102 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2389 11:05:47.709416 [-4] AVG Duty = 4953%(X100)
2390 11:05:47.709522
2391 11:05:47.712570 CH0 CLK Duty spec in!! Max-Min= 156%
2392 11:05:47.715860 [DutyScan_Calibration_Flow] ====Done====
2393 11:05:47.715995
2394 11:05:47.719430 [DutyScan_Calibration_Flow] k_type=1
2395 11:05:47.734026
2396 11:05:47.734152 ==DQS 0 ==
2397 11:05:47.737192 Final DQS duty delay cell = -4
2398 11:05:47.740778 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2399 11:05:47.743907 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2400 11:05:47.747793 [-4] AVG Duty = 4938%(X100)
2401 11:05:47.747920
2402 11:05:47.748037 ==DQS 1 ==
2403 11:05:47.750782 Final DQS duty delay cell = -4
2404 11:05:47.754035 [-4] MAX Duty = 5124%(X100), DQS PI = 14
2405 11:05:47.757706 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2406 11:05:47.761228 [-4] AVG Duty = 5062%(X100)
2407 11:05:47.761355
2408 11:05:47.764333 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2409 11:05:47.764461
2410 11:05:47.767863 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2411 11:05:47.771357 [DutyScan_Calibration_Flow] ====Done====
2412 11:05:47.771471
2413 11:05:47.774015 [DutyScan_Calibration_Flow] k_type=3
2414 11:05:47.791177
2415 11:05:47.791332 ==DQM 0 ==
2416 11:05:47.794720 Final DQM duty delay cell = 0
2417 11:05:47.797914 [0] MAX Duty = 5031%(X100), DQS PI = 54
2418 11:05:47.801522 [0] MIN Duty = 4907%(X100), DQS PI = 2
2419 11:05:47.801630 [0] AVG Duty = 4969%(X100)
2420 11:05:47.805368
2421 11:05:47.805471 ==DQM 1 ==
2422 11:05:47.807986 Final DQM duty delay cell = 0
2423 11:05:47.811686 [0] MAX Duty = 5156%(X100), DQS PI = 62
2424 11:05:47.815096 [0] MIN Duty = 4969%(X100), DQS PI = 10
2425 11:05:47.815204 [0] AVG Duty = 5062%(X100)
2426 11:05:47.815298
2427 11:05:47.819292 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2428 11:05:47.821910
2429 11:05:47.824842 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2430 11:05:47.828382 [DutyScan_Calibration_Flow] ====Done====
2431 11:05:47.828478
2432 11:05:47.831649 [DutyScan_Calibration_Flow] k_type=2
2433 11:05:47.846935
2434 11:05:47.847042 ==DQ 0 ==
2435 11:05:47.850276 Final DQ duty delay cell = -4
2436 11:05:47.853928 [-4] MAX Duty = 5062%(X100), DQS PI = 56
2437 11:05:47.857220 [-4] MIN Duty = 4875%(X100), DQS PI = 18
2438 11:05:47.860736 [-4] AVG Duty = 4968%(X100)
2439 11:05:47.860818
2440 11:05:47.860882 ==DQ 1 ==
2441 11:05:47.864062 Final DQ duty delay cell = 0
2442 11:05:47.867266 [0] MAX Duty = 5031%(X100), DQS PI = 18
2443 11:05:47.870358 [0] MIN Duty = 4907%(X100), DQS PI = 46
2444 11:05:47.870454 [0] AVG Duty = 4969%(X100)
2445 11:05:47.873857
2446 11:05:47.877161 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2447 11:05:47.877244
2448 11:05:47.880381 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2449 11:05:47.884462 [DutyScan_Calibration_Flow] ====Done====
2450 11:05:47.884544 ==
2451 11:05:47.887320 Dram Type= 6, Freq= 0, CH_1, rank 0
2452 11:05:47.890671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2453 11:05:47.890754 ==
2454 11:05:47.893781 [Duty_Offset_Calibration]
2455 11:05:47.893891 B0:1 B1:1 CA:2
2456 11:05:47.893988
2457 11:05:47.897049 [DutyScan_Calibration_Flow] k_type=0
2458 11:05:47.907568
2459 11:05:47.907650 ==CLK 0==
2460 11:05:47.911161 Final CLK duty delay cell = 0
2461 11:05:47.914488 [0] MAX Duty = 5187%(X100), DQS PI = 24
2462 11:05:47.917689 [0] MIN Duty = 4938%(X100), DQS PI = 48
2463 11:05:47.917793 [0] AVG Duty = 5062%(X100)
2464 11:05:47.920789
2465 11:05:47.920891 CH1 CLK Duty spec in!! Max-Min= 249%
2466 11:05:47.927561 [DutyScan_Calibration_Flow] ====Done====
2467 11:05:47.927671
2468 11:05:47.930892 [DutyScan_Calibration_Flow] k_type=1
2469 11:05:47.946774
2470 11:05:47.946861 ==DQS 0 ==
2471 11:05:47.949929 Final DQS duty delay cell = 0
2472 11:05:47.953502 [0] MAX Duty = 5031%(X100), DQS PI = 18
2473 11:05:47.956916 [0] MIN Duty = 4844%(X100), DQS PI = 50
2474 11:05:47.957021 [0] AVG Duty = 4937%(X100)
2475 11:05:47.960472
2476 11:05:47.960576 ==DQS 1 ==
2477 11:05:47.963523 Final DQS duty delay cell = 0
2478 11:05:47.966863 [0] MAX Duty = 5062%(X100), DQS PI = 36
2479 11:05:47.970283 [0] MIN Duty = 4907%(X100), DQS PI = 8
2480 11:05:47.970387 [0] AVG Duty = 4984%(X100)
2481 11:05:47.970465
2482 11:05:47.977068 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2483 11:05:47.977176
2484 11:05:47.980379 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2485 11:05:47.984150 [DutyScan_Calibration_Flow] ====Done====
2486 11:05:47.984230
2487 11:05:47.987292 [DutyScan_Calibration_Flow] k_type=3
2488 11:05:48.003657
2489 11:05:48.003743 ==DQM 0 ==
2490 11:05:48.006707 Final DQM duty delay cell = 0
2491 11:05:48.010136 [0] MAX Duty = 5093%(X100), DQS PI = 18
2492 11:05:48.013337 [0] MIN Duty = 4875%(X100), DQS PI = 50
2493 11:05:48.013420 [0] AVG Duty = 4984%(X100)
2494 11:05:48.016888
2495 11:05:48.016971 ==DQM 1 ==
2496 11:05:48.019720 Final DQM duty delay cell = 0
2497 11:05:48.023413 [0] MAX Duty = 5156%(X100), DQS PI = 62
2498 11:05:48.026602 [0] MIN Duty = 4938%(X100), DQS PI = 24
2499 11:05:48.026687 [0] AVG Duty = 5047%(X100)
2500 11:05:48.029977
2501 11:05:48.033638 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2502 11:05:48.033759
2503 11:05:48.036379 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2504 11:05:48.040404 [DutyScan_Calibration_Flow] ====Done====
2505 11:05:48.040485
2506 11:05:48.043084 [DutyScan_Calibration_Flow] k_type=2
2507 11:05:48.059710
2508 11:05:48.059793 ==DQ 0 ==
2509 11:05:48.063331 Final DQ duty delay cell = 0
2510 11:05:48.066590 [0] MAX Duty = 5124%(X100), DQS PI = 18
2511 11:05:48.069779 [0] MIN Duty = 4938%(X100), DQS PI = 50
2512 11:05:48.069887 [0] AVG Duty = 5031%(X100)
2513 11:05:48.073084
2514 11:05:48.073163 ==DQ 1 ==
2515 11:05:48.076603 Final DQ duty delay cell = 0
2516 11:05:48.079997 [0] MAX Duty = 5124%(X100), DQS PI = 56
2517 11:05:48.083054 [0] MIN Duty = 5031%(X100), DQS PI = 2
2518 11:05:48.083129 [0] AVG Duty = 5077%(X100)
2519 11:05:48.083191
2520 11:05:48.086552 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2521 11:05:48.086632
2522 11:05:48.089819 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2523 11:05:48.096687 [DutyScan_Calibration_Flow] ====Done====
2524 11:05:48.100405 nWR fixed to 30
2525 11:05:48.100508 [ModeRegInit_LP4] CH0 RK0
2526 11:05:48.103554 [ModeRegInit_LP4] CH0 RK1
2527 11:05:48.106840 [ModeRegInit_LP4] CH1 RK0
2528 11:05:48.106919 [ModeRegInit_LP4] CH1 RK1
2529 11:05:48.110268 match AC timing 7
2530 11:05:48.113382 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2531 11:05:48.116923 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2532 11:05:48.123181 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2533 11:05:48.126625 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2534 11:05:48.133750 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2535 11:05:48.133832 ==
2536 11:05:48.137074 Dram Type= 6, Freq= 0, CH_0, rank 0
2537 11:05:48.139965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2538 11:05:48.140049 ==
2539 11:05:48.143374 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2540 11:05:48.150240 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2541 11:05:48.159712 [CA 0] Center 40 (10~71) winsize 62
2542 11:05:48.163162 [CA 1] Center 39 (9~70) winsize 62
2543 11:05:48.166886 [CA 2] Center 36 (6~67) winsize 62
2544 11:05:48.169502 [CA 3] Center 36 (5~67) winsize 63
2545 11:05:48.173047 [CA 4] Center 35 (5~65) winsize 61
2546 11:05:48.176345 [CA 5] Center 34 (4~64) winsize 61
2547 11:05:48.176429
2548 11:05:48.179606 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2549 11:05:48.179689
2550 11:05:48.183209 [CATrainingPosCal] consider 1 rank data
2551 11:05:48.186235 u2DelayCellTimex100 = 270/100 ps
2552 11:05:48.190223 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2553 11:05:48.193052 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2554 11:05:48.199948 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2555 11:05:48.203066 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2556 11:05:48.206703 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2557 11:05:48.209839 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2558 11:05:48.209922
2559 11:05:48.213077 CA PerBit enable=1, Macro0, CA PI delay=34
2560 11:05:48.213176
2561 11:05:48.216523 [CBTSetCACLKResult] CA Dly = 34
2562 11:05:48.216606 CS Dly: 7 (0~38)
2563 11:05:48.216690 ==
2564 11:05:48.220353 Dram Type= 6, Freq= 0, CH_0, rank 1
2565 11:05:48.226705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2566 11:05:48.226803 ==
2567 11:05:48.230325 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2568 11:05:48.236461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2569 11:05:48.245517 [CA 0] Center 39 (9~70) winsize 62
2570 11:05:48.248952 [CA 1] Center 40 (10~70) winsize 61
2571 11:05:48.252215 [CA 2] Center 36 (6~67) winsize 62
2572 11:05:48.256004 [CA 3] Center 36 (5~67) winsize 63
2573 11:05:48.259010 [CA 4] Center 34 (4~65) winsize 62
2574 11:05:48.262685 [CA 5] Center 34 (4~64) winsize 61
2575 11:05:48.262768
2576 11:05:48.266154 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2577 11:05:48.266238
2578 11:05:48.269096 [CATrainingPosCal] consider 2 rank data
2579 11:05:48.272493 u2DelayCellTimex100 = 270/100 ps
2580 11:05:48.275748 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2581 11:05:48.279252 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2582 11:05:48.285884 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2583 11:05:48.289489 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2584 11:05:48.292763 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2585 11:05:48.295878 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2586 11:05:48.295963
2587 11:05:48.299284 CA PerBit enable=1, Macro0, CA PI delay=34
2588 11:05:48.299368
2589 11:05:48.302526 [CBTSetCACLKResult] CA Dly = 34
2590 11:05:48.302684 CS Dly: 8 (0~41)
2591 11:05:48.302831
2592 11:05:48.306122 ----->DramcWriteLeveling(PI) begin...
2593 11:05:48.306233 ==
2594 11:05:48.309467 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 11:05:48.316249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 11:05:48.316335 ==
2597 11:05:48.319677 Write leveling (Byte 0): 32 => 32
2598 11:05:48.322669 Write leveling (Byte 1): 30 => 30
2599 11:05:48.322774 DramcWriteLeveling(PI) end<-----
2600 11:05:48.322906
2601 11:05:48.326337 ==
2602 11:05:48.329577 Dram Type= 6, Freq= 0, CH_0, rank 0
2603 11:05:48.332919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2604 11:05:48.333003 ==
2605 11:05:48.336179 [Gating] SW mode calibration
2606 11:05:48.342729 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2607 11:05:48.346546 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2608 11:05:48.353039 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 11:05:48.356390 0 15 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2610 11:05:48.359618 0 15 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2611 11:05:48.366392 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2612 11:05:48.369706 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2613 11:05:48.373115 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2614 11:05:48.376363 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2615 11:05:48.383281 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2616 11:05:48.386592 1 0 0 | B1->B0 | 3434 2e2e | 0 1 | (0 0) (1 1)
2617 11:05:48.389933 1 0 4 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2618 11:05:48.397161 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2619 11:05:48.400023 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2620 11:05:48.403682 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2621 11:05:48.410240 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2622 11:05:48.413186 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2623 11:05:48.416952 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2624 11:05:48.423617 1 1 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2625 11:05:48.426927 1 1 4 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
2626 11:05:48.430090 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 11:05:48.433668 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 11:05:48.440539 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 11:05:48.443790 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2630 11:05:48.447211 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2631 11:05:48.453837 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2632 11:05:48.457435 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2633 11:05:48.460253 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2634 11:05:48.467393 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 11:05:48.470773 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 11:05:48.474006 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 11:05:48.480492 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 11:05:48.483903 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 11:05:48.487112 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 11:05:48.494070 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 11:05:48.497554 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 11:05:48.501069 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 11:05:48.503961 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 11:05:48.510870 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 11:05:48.514114 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 11:05:48.517473 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 11:05:48.524439 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2648 11:05:48.527250 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2649 11:05:48.530722 Total UI for P1: 0, mck2ui 16
2650 11:05:48.533916 best dqsien dly found for B0: ( 1, 3, 30)
2651 11:05:48.537701 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2652 11:05:48.544410 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2653 11:05:48.544516 Total UI for P1: 0, mck2ui 16
2654 11:05:48.548194 best dqsien dly found for B1: ( 1, 4, 2)
2655 11:05:48.551550 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2656 11:05:48.557579 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2657 11:05:48.557687
2658 11:05:48.560960 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2659 11:05:48.564562 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2660 11:05:48.567884 [Gating] SW calibration Done
2661 11:05:48.567971 ==
2662 11:05:48.571256 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 11:05:48.574352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 11:05:48.574456 ==
2665 11:05:48.574523 RX Vref Scan: 0
2666 11:05:48.574585
2667 11:05:48.577648 RX Vref 0 -> 0, step: 1
2668 11:05:48.577735
2669 11:05:48.581105 RX Delay -40 -> 252, step: 8
2670 11:05:48.584793 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2671 11:05:48.587883 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2672 11:05:48.594522 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2673 11:05:48.597773 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2674 11:05:48.601251 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2675 11:05:48.605106 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2676 11:05:48.607946 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2677 11:05:48.611313 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2678 11:05:48.618317 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2679 11:05:48.621461 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2680 11:05:48.625220 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2681 11:05:48.628894 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2682 11:05:48.631555 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2683 11:05:48.638280 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2684 11:05:48.641463 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2685 11:05:48.645176 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2686 11:05:48.645258 ==
2687 11:05:48.648104 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 11:05:48.651940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 11:05:48.652023 ==
2690 11:05:48.655204 DQS Delay:
2691 11:05:48.655286 DQS0 = 0, DQS1 = 0
2692 11:05:48.655352 DQM Delay:
2693 11:05:48.658642 DQM0 = 116, DQM1 = 108
2694 11:05:48.658725 DQ Delay:
2695 11:05:48.661836 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2696 11:05:48.665378 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2697 11:05:48.668297 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2698 11:05:48.675082 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2699 11:05:48.675166
2700 11:05:48.675231
2701 11:05:48.675292 ==
2702 11:05:48.678613 Dram Type= 6, Freq= 0, CH_0, rank 0
2703 11:05:48.681749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2704 11:05:48.681833 ==
2705 11:05:48.681900
2706 11:05:48.681961
2707 11:05:48.685462 TX Vref Scan disable
2708 11:05:48.685545 == TX Byte 0 ==
2709 11:05:48.691632 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2710 11:05:48.695177 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2711 11:05:48.695266 == TX Byte 1 ==
2712 11:05:48.701887 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2713 11:05:48.705240 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2714 11:05:48.705352 ==
2715 11:05:48.708751 Dram Type= 6, Freq= 0, CH_0, rank 0
2716 11:05:48.711690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2717 11:05:48.711775 ==
2718 11:05:48.724969 TX Vref=22, minBit 7, minWin=24, winSum=413
2719 11:05:48.728395 TX Vref=24, minBit 5, minWin=25, winSum=419
2720 11:05:48.731355 TX Vref=26, minBit 0, minWin=26, winSum=426
2721 11:05:48.734753 TX Vref=28, minBit 0, minWin=26, winSum=428
2722 11:05:48.738121 TX Vref=30, minBit 1, minWin=26, winSum=431
2723 11:05:48.741527 TX Vref=32, minBit 0, minWin=26, winSum=431
2724 11:05:48.748349 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
2725 11:05:48.748434
2726 11:05:48.751881 Final TX Range 1 Vref 30
2727 11:05:48.751965
2728 11:05:48.752030 ==
2729 11:05:48.754852 Dram Type= 6, Freq= 0, CH_0, rank 0
2730 11:05:48.758128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2731 11:05:48.758214 ==
2732 11:05:48.758279
2733 11:05:48.758339
2734 11:05:48.762035 TX Vref Scan disable
2735 11:05:48.764827 == TX Byte 0 ==
2736 11:05:48.768584 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2737 11:05:48.771684 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2738 11:05:48.774842 == TX Byte 1 ==
2739 11:05:48.778527 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2740 11:05:48.782019 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2741 11:05:48.782132
2742 11:05:48.785236 [DATLAT]
2743 11:05:48.785316 Freq=1200, CH0 RK0
2744 11:05:48.785380
2745 11:05:48.788378 DATLAT Default: 0xd
2746 11:05:48.788458 0, 0xFFFF, sum = 0
2747 11:05:48.791516 1, 0xFFFF, sum = 0
2748 11:05:48.791598 2, 0xFFFF, sum = 0
2749 11:05:48.795145 3, 0xFFFF, sum = 0
2750 11:05:48.795226 4, 0xFFFF, sum = 0
2751 11:05:48.798560 5, 0xFFFF, sum = 0
2752 11:05:48.798776 6, 0xFFFF, sum = 0
2753 11:05:48.801770 7, 0xFFFF, sum = 0
2754 11:05:48.801852 8, 0xFFFF, sum = 0
2755 11:05:48.805248 9, 0xFFFF, sum = 0
2756 11:05:48.805330 10, 0xFFFF, sum = 0
2757 11:05:48.808339 11, 0xFFFF, sum = 0
2758 11:05:48.808422 12, 0x0, sum = 1
2759 11:05:48.811533 13, 0x0, sum = 2
2760 11:05:48.811620 14, 0x0, sum = 3
2761 11:05:48.815304 15, 0x0, sum = 4
2762 11:05:48.815390 best_step = 13
2763 11:05:48.815493
2764 11:05:48.815591 ==
2765 11:05:48.818751 Dram Type= 6, Freq= 0, CH_0, rank 0
2766 11:05:48.825202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2767 11:05:48.825319 ==
2768 11:05:48.825403 RX Vref Scan: 1
2769 11:05:48.825483
2770 11:05:48.828439 Set Vref Range= 32 -> 127
2771 11:05:48.828515
2772 11:05:48.831657 RX Vref 32 -> 127, step: 1
2773 11:05:48.831755
2774 11:05:48.831853 RX Delay -21 -> 252, step: 4
2775 11:05:48.835249
2776 11:05:48.835377 Set Vref, RX VrefLevel [Byte0]: 32
2777 11:05:48.838671 [Byte1]: 32
2778 11:05:48.842702
2779 11:05:48.842786 Set Vref, RX VrefLevel [Byte0]: 33
2780 11:05:48.846254 [Byte1]: 33
2781 11:05:48.851210
2782 11:05:48.851295 Set Vref, RX VrefLevel [Byte0]: 34
2783 11:05:48.854004 [Byte1]: 34
2784 11:05:48.859103
2785 11:05:48.859187 Set Vref, RX VrefLevel [Byte0]: 35
2786 11:05:48.862118 [Byte1]: 35
2787 11:05:48.866627
2788 11:05:48.866736 Set Vref, RX VrefLevel [Byte0]: 36
2789 11:05:48.870125 [Byte1]: 36
2790 11:05:48.874332
2791 11:05:48.874458 Set Vref, RX VrefLevel [Byte0]: 37
2792 11:05:48.877703 [Byte1]: 37
2793 11:05:48.882737
2794 11:05:48.882817 Set Vref, RX VrefLevel [Byte0]: 38
2795 11:05:48.885765 [Byte1]: 38
2796 11:05:48.890143
2797 11:05:48.890247 Set Vref, RX VrefLevel [Byte0]: 39
2798 11:05:48.893809 [Byte1]: 39
2799 11:05:48.898193
2800 11:05:48.898312 Set Vref, RX VrefLevel [Byte0]: 40
2801 11:05:48.901736 [Byte1]: 40
2802 11:05:48.906088
2803 11:05:48.906212 Set Vref, RX VrefLevel [Byte0]: 41
2804 11:05:48.909885 [Byte1]: 41
2805 11:05:48.914271
2806 11:05:48.914383 Set Vref, RX VrefLevel [Byte0]: 42
2807 11:05:48.917382 [Byte1]: 42
2808 11:05:48.921964
2809 11:05:48.922048 Set Vref, RX VrefLevel [Byte0]: 43
2810 11:05:48.925488 [Byte1]: 43
2811 11:05:48.929950
2812 11:05:48.930039 Set Vref, RX VrefLevel [Byte0]: 44
2813 11:05:48.933284 [Byte1]: 44
2814 11:05:48.938043
2815 11:05:48.938147 Set Vref, RX VrefLevel [Byte0]: 45
2816 11:05:48.941368 [Byte1]: 45
2817 11:05:48.946114
2818 11:05:48.946200 Set Vref, RX VrefLevel [Byte0]: 46
2819 11:05:48.949210 [Byte1]: 46
2820 11:05:48.953856
2821 11:05:48.953941 Set Vref, RX VrefLevel [Byte0]: 47
2822 11:05:48.957120 [Byte1]: 47
2823 11:05:48.961755
2824 11:05:48.961883 Set Vref, RX VrefLevel [Byte0]: 48
2825 11:05:48.965073 [Byte1]: 48
2826 11:05:48.969441
2827 11:05:48.969529 Set Vref, RX VrefLevel [Byte0]: 49
2828 11:05:48.972762 [Byte1]: 49
2829 11:05:48.977321
2830 11:05:48.977419 Set Vref, RX VrefLevel [Byte0]: 50
2831 11:05:48.980762 [Byte1]: 50
2832 11:05:48.985432
2833 11:05:48.985555 Set Vref, RX VrefLevel [Byte0]: 51
2834 11:05:48.989184 [Byte1]: 51
2835 11:05:48.993725
2836 11:05:48.993811 Set Vref, RX VrefLevel [Byte0]: 52
2837 11:05:48.997289 [Byte1]: 52
2838 11:05:49.001637
2839 11:05:49.001761 Set Vref, RX VrefLevel [Byte0]: 53
2840 11:05:49.004661 [Byte1]: 53
2841 11:05:49.009387
2842 11:05:49.009509 Set Vref, RX VrefLevel [Byte0]: 54
2843 11:05:49.012625 [Byte1]: 54
2844 11:05:49.017281
2845 11:05:49.017402 Set Vref, RX VrefLevel [Byte0]: 55
2846 11:05:49.020349 [Byte1]: 55
2847 11:05:49.025025
2848 11:05:49.025148 Set Vref, RX VrefLevel [Byte0]: 56
2849 11:05:49.028709 [Byte1]: 56
2850 11:05:49.033665
2851 11:05:49.033791 Set Vref, RX VrefLevel [Byte0]: 57
2852 11:05:49.036702 [Byte1]: 57
2853 11:05:49.041009
2854 11:05:49.041136 Set Vref, RX VrefLevel [Byte0]: 58
2855 11:05:49.044252 [Byte1]: 58
2856 11:05:49.049435
2857 11:05:49.049563 Set Vref, RX VrefLevel [Byte0]: 59
2858 11:05:49.052120 [Byte1]: 59
2859 11:05:49.057042
2860 11:05:49.057163 Set Vref, RX VrefLevel [Byte0]: 60
2861 11:05:49.060558 [Byte1]: 60
2862 11:05:49.064913
2863 11:05:49.065036 Set Vref, RX VrefLevel [Byte0]: 61
2864 11:05:49.068043 [Byte1]: 61
2865 11:05:49.072841
2866 11:05:49.072964 Set Vref, RX VrefLevel [Byte0]: 62
2867 11:05:49.075859 [Byte1]: 62
2868 11:05:49.080663
2869 11:05:49.080804 Set Vref, RX VrefLevel [Byte0]: 63
2870 11:05:49.083994 [Byte1]: 63
2871 11:05:49.088626
2872 11:05:49.088787 Set Vref, RX VrefLevel [Byte0]: 64
2873 11:05:49.091949 [Byte1]: 64
2874 11:05:49.096528
2875 11:05:49.096740 Set Vref, RX VrefLevel [Byte0]: 65
2876 11:05:49.100035 [Byte1]: 65
2877 11:05:49.104617
2878 11:05:49.104803 Set Vref, RX VrefLevel [Byte0]: 66
2879 11:05:49.107901 [Byte1]: 66
2880 11:05:49.112489
2881 11:05:49.112636 Set Vref, RX VrefLevel [Byte0]: 67
2882 11:05:49.115601 [Byte1]: 67
2883 11:05:49.120518
2884 11:05:49.120640 Set Vref, RX VrefLevel [Byte0]: 68
2885 11:05:49.123701 [Byte1]: 68
2886 11:05:49.127957
2887 11:05:49.128080 Set Vref, RX VrefLevel [Byte0]: 69
2888 11:05:49.131604 [Byte1]: 69
2889 11:05:49.136015
2890 11:05:49.136138 Final RX Vref Byte 0 = 52 to rank0
2891 11:05:49.139780 Final RX Vref Byte 1 = 50 to rank0
2892 11:05:49.143124 Final RX Vref Byte 0 = 52 to rank1
2893 11:05:49.146162 Final RX Vref Byte 1 = 50 to rank1==
2894 11:05:49.149376 Dram Type= 6, Freq= 0, CH_0, rank 0
2895 11:05:49.152789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2896 11:05:49.156173 ==
2897 11:05:49.156246 DQS Delay:
2898 11:05:49.156308 DQS0 = 0, DQS1 = 0
2899 11:05:49.159572 DQM Delay:
2900 11:05:49.159655 DQM0 = 115, DQM1 = 104
2901 11:05:49.162917 DQ Delay:
2902 11:05:49.166119 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2903 11:05:49.170000 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2904 11:05:49.173644 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2905 11:05:49.176519 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
2906 11:05:49.176661
2907 11:05:49.176764
2908 11:05:49.183054 [DQSOSCAuto] RK0, (LSB)MR18= 0xfeed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2909 11:05:49.186085 CH0 RK0: MR19=303, MR18=FEED
2910 11:05:49.193386 CH0_RK0: MR19=0x303, MR18=0xFEED, DQSOSC=410, MR23=63, INC=39, DEC=26
2911 11:05:49.193470
2912 11:05:49.196708 ----->DramcWriteLeveling(PI) begin...
2913 11:05:49.196793 ==
2914 11:05:49.200007 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 11:05:49.203263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 11:05:49.203338 ==
2917 11:05:49.206818 Write leveling (Byte 0): 31 => 31
2918 11:05:49.209658 Write leveling (Byte 1): 30 => 30
2919 11:05:49.213587 DramcWriteLeveling(PI) end<-----
2920 11:05:49.213658
2921 11:05:49.213723 ==
2922 11:05:49.216494 Dram Type= 6, Freq= 0, CH_0, rank 1
2923 11:05:49.220171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2924 11:05:49.223385 ==
2925 11:05:49.223461 [Gating] SW mode calibration
2926 11:05:49.229856 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2927 11:05:49.236299 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2928 11:05:49.239786 0 15 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
2929 11:05:49.246987 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2930 11:05:49.249833 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2931 11:05:49.253244 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2932 11:05:49.260149 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2933 11:05:49.263497 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2934 11:05:49.266288 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2935 11:05:49.270230 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
2936 11:05:49.277307 1 0 0 | B1->B0 | 3030 2929 | 0 0 | (1 0) (1 1)
2937 11:05:49.280053 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2938 11:05:49.283550 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2939 11:05:49.290336 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2940 11:05:49.293195 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2941 11:05:49.296954 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2942 11:05:49.303465 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2943 11:05:49.306751 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2944 11:05:49.310295 1 1 0 | B1->B0 | 3737 4545 | 0 0 | (0 0) (1 1)
2945 11:05:49.316890 1 1 4 | B1->B0 | 4544 4646 | 1 0 | (0 0) (0 0)
2946 11:05:49.320024 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 11:05:49.323423 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 11:05:49.330430 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 11:05:49.333604 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 11:05:49.336840 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2951 11:05:49.340631 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2952 11:05:49.347013 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2953 11:05:49.350600 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 11:05:49.353765 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 11:05:49.360567 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 11:05:49.363698 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 11:05:49.367259 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 11:05:49.374244 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 11:05:49.376971 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 11:05:49.380269 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 11:05:49.386941 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 11:05:49.390680 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 11:05:49.393783 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 11:05:49.400695 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 11:05:49.404451 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 11:05:49.407228 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 11:05:49.410712 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2968 11:05:49.417672 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2969 11:05:49.421187 Total UI for P1: 0, mck2ui 16
2970 11:05:49.424709 best dqsien dly found for B0: ( 1, 3, 28)
2971 11:05:49.427609 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 11:05:49.430870 Total UI for P1: 0, mck2ui 16
2973 11:05:49.434232 best dqsien dly found for B1: ( 1, 3, 30)
2974 11:05:49.437369 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2975 11:05:49.440616 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2976 11:05:49.440724
2977 11:05:49.444659 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2978 11:05:49.447467 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2979 11:05:49.450592 [Gating] SW calibration Done
2980 11:05:49.450705 ==
2981 11:05:49.454534 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 11:05:49.457298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 11:05:49.461039 ==
2984 11:05:49.461111 RX Vref Scan: 0
2985 11:05:49.461171
2986 11:05:49.464030 RX Vref 0 -> 0, step: 1
2987 11:05:49.464116
2988 11:05:49.468099 RX Delay -40 -> 252, step: 8
2989 11:05:49.471098 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2990 11:05:49.474094 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2991 11:05:49.477182 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2992 11:05:49.480862 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2993 11:05:49.487754 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2994 11:05:49.491038 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2995 11:05:49.494357 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2996 11:05:49.497378 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2997 11:05:49.500735 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2998 11:05:49.504545 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2999 11:05:49.510917 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3000 11:05:49.514344 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3001 11:05:49.517662 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3002 11:05:49.521052 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3003 11:05:49.524115 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3004 11:05:49.531039 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3005 11:05:49.531147 ==
3006 11:05:49.534820 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 11:05:49.537889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 11:05:49.537990 ==
3009 11:05:49.538084 DQS Delay:
3010 11:05:49.541372 DQS0 = 0, DQS1 = 0
3011 11:05:49.541456 DQM Delay:
3012 11:05:49.544651 DQM0 = 115, DQM1 = 106
3013 11:05:49.544728 DQ Delay:
3014 11:05:49.547865 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
3015 11:05:49.551500 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
3016 11:05:49.554763 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3017 11:05:49.558022 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =111
3018 11:05:49.558105
3019 11:05:49.558169
3020 11:05:49.558229 ==
3021 11:05:49.561274 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 11:05:49.567901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 11:05:49.568011 ==
3024 11:05:49.568104
3025 11:05:49.568167
3026 11:05:49.568226 TX Vref Scan disable
3027 11:05:49.571613 == TX Byte 0 ==
3028 11:05:49.574617 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3029 11:05:49.578005 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3030 11:05:49.581663 == TX Byte 1 ==
3031 11:05:49.584850 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3032 11:05:49.588642 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3033 11:05:49.591693 ==
3034 11:05:49.594722 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 11:05:49.598373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 11:05:49.598480 ==
3037 11:05:49.609238 TX Vref=22, minBit 1, minWin=26, winSum=426
3038 11:05:49.612609 TX Vref=24, minBit 1, minWin=26, winSum=432
3039 11:05:49.616264 TX Vref=26, minBit 3, minWin=25, winSum=431
3040 11:05:49.619313 TX Vref=28, minBit 12, minWin=26, winSum=439
3041 11:05:49.622838 TX Vref=30, minBit 12, minWin=26, winSum=437
3042 11:05:49.629272 TX Vref=32, minBit 4, minWin=26, winSum=433
3043 11:05:49.633353 [TxChooseVref] Worse bit 12, Min win 26, Win sum 439, Final Vref 28
3044 11:05:49.633459
3045 11:05:49.636057 Final TX Range 1 Vref 28
3046 11:05:49.636139
3047 11:05:49.636203 ==
3048 11:05:49.639012 Dram Type= 6, Freq= 0, CH_0, rank 1
3049 11:05:49.642828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 11:05:49.646410 ==
3051 11:05:49.646530
3052 11:05:49.646644
3053 11:05:49.646704 TX Vref Scan disable
3054 11:05:49.649420 == TX Byte 0 ==
3055 11:05:49.652412 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3056 11:05:49.656383 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3057 11:05:49.659185 == TX Byte 1 ==
3058 11:05:49.662865 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3059 11:05:49.666162 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3060 11:05:49.666283
3061 11:05:49.669278 [DATLAT]
3062 11:05:49.669375 Freq=1200, CH0 RK1
3063 11:05:49.669459
3064 11:05:49.672619 DATLAT Default: 0xd
3065 11:05:49.672731 0, 0xFFFF, sum = 0
3066 11:05:49.675822 1, 0xFFFF, sum = 0
3067 11:05:49.675925 2, 0xFFFF, sum = 0
3068 11:05:49.679690 3, 0xFFFF, sum = 0
3069 11:05:49.679794 4, 0xFFFF, sum = 0
3070 11:05:49.682972 5, 0xFFFF, sum = 0
3071 11:05:49.683112 6, 0xFFFF, sum = 0
3072 11:05:49.686296 7, 0xFFFF, sum = 0
3073 11:05:49.689789 8, 0xFFFF, sum = 0
3074 11:05:49.689904 9, 0xFFFF, sum = 0
3075 11:05:49.693077 10, 0xFFFF, sum = 0
3076 11:05:49.693231 11, 0xFFFF, sum = 0
3077 11:05:49.696161 12, 0x0, sum = 1
3078 11:05:49.696264 13, 0x0, sum = 2
3079 11:05:49.696368 14, 0x0, sum = 3
3080 11:05:49.699625 15, 0x0, sum = 4
3081 11:05:49.699732 best_step = 13
3082 11:05:49.699814
3083 11:05:49.702949 ==
3084 11:05:49.703049 Dram Type= 6, Freq= 0, CH_0, rank 1
3085 11:05:49.709910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 11:05:49.710010 ==
3087 11:05:49.710109 RX Vref Scan: 0
3088 11:05:49.710201
3089 11:05:49.712825 RX Vref 0 -> 0, step: 1
3090 11:05:49.712922
3091 11:05:49.716183 RX Delay -21 -> 252, step: 4
3092 11:05:49.719859 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3093 11:05:49.723049 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3094 11:05:49.729511 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3095 11:05:49.732827 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3096 11:05:49.736550 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3097 11:05:49.739877 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3098 11:05:49.743369 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3099 11:05:49.750024 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3100 11:05:49.753024 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3101 11:05:49.756512 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3102 11:05:49.760107 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3103 11:05:49.763263 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3104 11:05:49.766657 iDelay=195, Bit 12, Center 112 (43 ~ 182) 140
3105 11:05:49.773274 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3106 11:05:49.777040 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3107 11:05:49.779755 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3108 11:05:49.779853 ==
3109 11:05:49.783144 Dram Type= 6, Freq= 0, CH_0, rank 1
3110 11:05:49.786540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 11:05:49.789868 ==
3112 11:05:49.789970 DQS Delay:
3113 11:05:49.790059 DQS0 = 0, DQS1 = 0
3114 11:05:49.793035 DQM Delay:
3115 11:05:49.793142 DQM0 = 114, DQM1 = 104
3116 11:05:49.796440 DQ Delay:
3117 11:05:49.799815 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3118 11:05:49.803135 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3119 11:05:49.806620 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3120 11:05:49.810146 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =114
3121 11:05:49.810244
3122 11:05:49.810344
3123 11:05:49.816585 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3124 11:05:49.819996 CH0 RK1: MR19=403, MR18=2F4
3125 11:05:49.826845 CH0_RK1: MR19=0x403, MR18=0x2F4, DQSOSC=409, MR23=63, INC=39, DEC=26
3126 11:05:49.830003 [RxdqsGatingPostProcess] freq 1200
3127 11:05:49.833451 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3128 11:05:49.836836 best DQS0 dly(2T, 0.5T) = (0, 11)
3129 11:05:49.840182 best DQS1 dly(2T, 0.5T) = (0, 12)
3130 11:05:49.843518 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3131 11:05:49.846628 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3132 11:05:49.850311 best DQS0 dly(2T, 0.5T) = (0, 11)
3133 11:05:49.853597 best DQS1 dly(2T, 0.5T) = (0, 11)
3134 11:05:49.856898 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3135 11:05:49.860234 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3136 11:05:49.863618 Pre-setting of DQS Precalculation
3137 11:05:49.866901 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3138 11:05:49.867025 ==
3139 11:05:49.870278 Dram Type= 6, Freq= 0, CH_1, rank 0
3140 11:05:49.876995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3141 11:05:49.877153 ==
3142 11:05:49.880461 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3143 11:05:49.886948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3144 11:05:49.895384 [CA 0] Center 38 (8~68) winsize 61
3145 11:05:49.898600 [CA 1] Center 38 (8~68) winsize 61
3146 11:05:49.901884 [CA 2] Center 35 (5~65) winsize 61
3147 11:05:49.905160 [CA 3] Center 34 (4~65) winsize 62
3148 11:05:49.908711 [CA 4] Center 34 (4~65) winsize 62
3149 11:05:49.911996 [CA 5] Center 34 (4~64) winsize 61
3150 11:05:49.912121
3151 11:05:49.915437 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3152 11:05:49.915587
3153 11:05:49.918326 [CATrainingPosCal] consider 1 rank data
3154 11:05:49.921923 u2DelayCellTimex100 = 270/100 ps
3155 11:05:49.925680 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3156 11:05:49.928839 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3157 11:05:49.932004 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3158 11:05:49.939192 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3159 11:05:49.942073 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3160 11:05:49.945550 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3161 11:05:49.945695
3162 11:05:49.948970 CA PerBit enable=1, Macro0, CA PI delay=34
3163 11:05:49.949091
3164 11:05:49.952516 [CBTSetCACLKResult] CA Dly = 34
3165 11:05:49.952656 CS Dly: 6 (0~37)
3166 11:05:49.952800 ==
3167 11:05:49.955852 Dram Type= 6, Freq= 0, CH_1, rank 1
3168 11:05:49.962413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3169 11:05:49.962546 ==
3170 11:05:49.966004 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3171 11:05:49.972287 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3172 11:05:49.980706 [CA 0] Center 38 (8~68) winsize 61
3173 11:05:49.984548 [CA 1] Center 38 (8~68) winsize 61
3174 11:05:49.987677 [CA 2] Center 34 (4~65) winsize 62
3175 11:05:49.990706 [CA 3] Center 34 (4~65) winsize 62
3176 11:05:49.994107 [CA 4] Center 34 (4~65) winsize 62
3177 11:05:49.997520 [CA 5] Center 33 (3~64) winsize 62
3178 11:05:49.997627
3179 11:05:50.001145 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3180 11:05:50.001228
3181 11:05:50.004446 [CATrainingPosCal] consider 2 rank data
3182 11:05:50.007738 u2DelayCellTimex100 = 270/100 ps
3183 11:05:50.011055 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3184 11:05:50.014307 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3185 11:05:50.017428 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3186 11:05:50.024564 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3187 11:05:50.027808 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3188 11:05:50.031590 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3189 11:05:50.031717
3190 11:05:50.034564 CA PerBit enable=1, Macro0, CA PI delay=34
3191 11:05:50.034687
3192 11:05:50.037789 [CBTSetCACLKResult] CA Dly = 34
3193 11:05:50.037912 CS Dly: 7 (0~40)
3194 11:05:50.038025
3195 11:05:50.041205 ----->DramcWriteLeveling(PI) begin...
3196 11:05:50.041336 ==
3197 11:05:50.044719 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 11:05:50.051104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 11:05:50.051231 ==
3200 11:05:50.054387 Write leveling (Byte 0): 26 => 26
3201 11:05:50.058003 Write leveling (Byte 1): 28 => 28
3202 11:05:50.058087 DramcWriteLeveling(PI) end<-----
3203 11:05:50.058152
3204 11:05:50.061463 ==
3205 11:05:50.064434 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 11:05:50.067686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 11:05:50.067770 ==
3208 11:05:50.071123 [Gating] SW mode calibration
3209 11:05:50.077863 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3210 11:05:50.081502 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3211 11:05:50.087725 0 15 0 | B1->B0 | 2b2b 2727 | 0 0 | (0 0) (0 0)
3212 11:05:50.091869 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3213 11:05:50.094896 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3214 11:05:50.101352 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3215 11:05:50.104657 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3216 11:05:50.108236 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3217 11:05:50.115057 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3218 11:05:50.117887 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (0 1) (1 0)
3219 11:05:50.121157 1 0 0 | B1->B0 | 2424 2d2d | 0 0 | (1 0) (0 1)
3220 11:05:50.124619 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 11:05:50.131505 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3222 11:05:50.134666 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3223 11:05:50.138182 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3224 11:05:50.145483 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3225 11:05:50.148293 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3226 11:05:50.151382 1 0 28 | B1->B0 | 3030 2626 | 0 0 | (0 0) (0 0)
3227 11:05:50.158515 1 1 0 | B1->B0 | 4242 3333 | 0 0 | (0 0) (0 0)
3228 11:05:50.161472 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 11:05:50.164812 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 11:05:50.171423 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 11:05:50.174744 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3232 11:05:50.177975 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3233 11:05:50.184703 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3234 11:05:50.188185 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3235 11:05:50.191948 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3236 11:05:50.195293 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 11:05:50.201510 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 11:05:50.205019 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 11:05:50.208105 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 11:05:50.215348 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 11:05:50.218959 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 11:05:50.221982 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 11:05:50.228148 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 11:05:50.231985 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 11:05:50.235123 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 11:05:50.242062 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 11:05:50.245530 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 11:05:50.248494 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 11:05:50.252696 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 11:05:50.258870 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3251 11:05:50.261980 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3252 11:05:50.265272 Total UI for P1: 0, mck2ui 16
3253 11:05:50.268512 best dqsien dly found for B0: ( 1, 3, 28)
3254 11:05:50.271945 Total UI for P1: 0, mck2ui 16
3255 11:05:50.275359 best dqsien dly found for B1: ( 1, 3, 30)
3256 11:05:50.278610 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3257 11:05:50.282220 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3258 11:05:50.282300
3259 11:05:50.285814 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3260 11:05:50.288835 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3261 11:05:50.292133 [Gating] SW calibration Done
3262 11:05:50.292214 ==
3263 11:05:50.295390 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 11:05:50.298776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 11:05:50.301967 ==
3266 11:05:50.302063 RX Vref Scan: 0
3267 11:05:50.302128
3268 11:05:50.305086 RX Vref 0 -> 0, step: 1
3269 11:05:50.305166
3270 11:05:50.308839 RX Delay -40 -> 252, step: 8
3271 11:05:50.311950 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3272 11:05:50.315565 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3273 11:05:50.318355 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3274 11:05:50.321996 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3275 11:05:50.328920 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3276 11:05:50.331979 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3277 11:05:50.335230 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3278 11:05:50.338778 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3279 11:05:50.342207 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3280 11:05:50.345466 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3281 11:05:50.352007 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3282 11:05:50.355922 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3283 11:05:50.359259 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3284 11:05:50.362477 iDelay=200, Bit 13, Center 119 (56 ~ 183) 128
3285 11:05:50.365482 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3286 11:05:50.372277 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3287 11:05:50.372357 ==
3288 11:05:50.376158 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 11:05:50.379002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 11:05:50.379079 ==
3291 11:05:50.379142 DQS Delay:
3292 11:05:50.382800 DQS0 = 0, DQS1 = 0
3293 11:05:50.382876 DQM Delay:
3294 11:05:50.385519 DQM0 = 116, DQM1 = 109
3295 11:05:50.385594 DQ Delay:
3296 11:05:50.388884 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3297 11:05:50.392244 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3298 11:05:50.395679 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3299 11:05:50.399309 DQ12 =123, DQ13 =119, DQ14 =111, DQ15 =111
3300 11:05:50.399387
3301 11:05:50.399488
3302 11:05:50.402803 ==
3303 11:05:50.402879 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 11:05:50.409436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 11:05:50.409533 ==
3306 11:05:50.409628
3307 11:05:50.409702
3308 11:05:50.412169 TX Vref Scan disable
3309 11:05:50.412243 == TX Byte 0 ==
3310 11:05:50.416011 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3311 11:05:50.422529 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3312 11:05:50.422639 == TX Byte 1 ==
3313 11:05:50.425765 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3314 11:05:50.432314 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3315 11:05:50.432393 ==
3316 11:05:50.435706 Dram Type= 6, Freq= 0, CH_1, rank 0
3317 11:05:50.439072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3318 11:05:50.439194 ==
3319 11:05:50.451485 TX Vref=22, minBit 0, minWin=25, winSum=413
3320 11:05:50.454031 TX Vref=24, minBit 1, minWin=25, winSum=420
3321 11:05:50.457710 TX Vref=26, minBit 1, minWin=25, winSum=422
3322 11:05:50.461098 TX Vref=28, minBit 0, minWin=26, winSum=427
3323 11:05:50.464003 TX Vref=30, minBit 0, minWin=26, winSum=429
3324 11:05:50.470880 TX Vref=32, minBit 3, minWin=25, winSum=430
3325 11:05:50.473988 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 30
3326 11:05:50.474100
3327 11:05:50.477581 Final TX Range 1 Vref 30
3328 11:05:50.477661
3329 11:05:50.477723 ==
3330 11:05:50.481065 Dram Type= 6, Freq= 0, CH_1, rank 0
3331 11:05:50.484643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3332 11:05:50.484771 ==
3333 11:05:50.484886
3334 11:05:50.484997
3335 11:05:50.487634 TX Vref Scan disable
3336 11:05:50.490790 == TX Byte 0 ==
3337 11:05:50.494180 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3338 11:05:50.497587 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3339 11:05:50.501101 == TX Byte 1 ==
3340 11:05:50.504386 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3341 11:05:50.507608 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3342 11:05:50.507731
3343 11:05:50.511011 [DATLAT]
3344 11:05:50.511121 Freq=1200, CH1 RK0
3345 11:05:50.511216
3346 11:05:50.514321 DATLAT Default: 0xd
3347 11:05:50.514452 0, 0xFFFF, sum = 0
3348 11:05:50.517539 1, 0xFFFF, sum = 0
3349 11:05:50.517666 2, 0xFFFF, sum = 0
3350 11:05:50.521030 3, 0xFFFF, sum = 0
3351 11:05:50.521160 4, 0xFFFF, sum = 0
3352 11:05:50.524531 5, 0xFFFF, sum = 0
3353 11:05:50.524657 6, 0xFFFF, sum = 0
3354 11:05:50.528127 7, 0xFFFF, sum = 0
3355 11:05:50.528251 8, 0xFFFF, sum = 0
3356 11:05:50.531237 9, 0xFFFF, sum = 0
3357 11:05:50.531363 10, 0xFFFF, sum = 0
3358 11:05:50.534349 11, 0xFFFF, sum = 0
3359 11:05:50.534455 12, 0x0, sum = 1
3360 11:05:50.538193 13, 0x0, sum = 2
3361 11:05:50.538272 14, 0x0, sum = 3
3362 11:05:50.541358 15, 0x0, sum = 4
3363 11:05:50.541444 best_step = 13
3364 11:05:50.541507
3365 11:05:50.541566 ==
3366 11:05:50.544435 Dram Type= 6, Freq= 0, CH_1, rank 0
3367 11:05:50.551166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3368 11:05:50.551248 ==
3369 11:05:50.551313 RX Vref Scan: 1
3370 11:05:50.551385
3371 11:05:50.554542 Set Vref Range= 32 -> 127
3372 11:05:50.554636
3373 11:05:50.557813 RX Vref 32 -> 127, step: 1
3374 11:05:50.557891
3375 11:05:50.557955 RX Delay -21 -> 252, step: 4
3376 11:05:50.561479
3377 11:05:50.561555 Set Vref, RX VrefLevel [Byte0]: 32
3378 11:05:50.564526 [Byte1]: 32
3379 11:05:50.568955
3380 11:05:50.569037 Set Vref, RX VrefLevel [Byte0]: 33
3381 11:05:50.572471 [Byte1]: 33
3382 11:05:50.576676
3383 11:05:50.576766 Set Vref, RX VrefLevel [Byte0]: 34
3384 11:05:50.580430 [Byte1]: 34
3385 11:05:50.585056
3386 11:05:50.585139 Set Vref, RX VrefLevel [Byte0]: 35
3387 11:05:50.588179 [Byte1]: 35
3388 11:05:50.592736
3389 11:05:50.592817 Set Vref, RX VrefLevel [Byte0]: 36
3390 11:05:50.595920 [Byte1]: 36
3391 11:05:50.601237
3392 11:05:50.601342 Set Vref, RX VrefLevel [Byte0]: 37
3393 11:05:50.604248 [Byte1]: 37
3394 11:05:50.608896
3395 11:05:50.608972 Set Vref, RX VrefLevel [Byte0]: 38
3396 11:05:50.611906 [Byte1]: 38
3397 11:05:50.616678
3398 11:05:50.616757 Set Vref, RX VrefLevel [Byte0]: 39
3399 11:05:50.619773 [Byte1]: 39
3400 11:05:50.624367
3401 11:05:50.624443 Set Vref, RX VrefLevel [Byte0]: 40
3402 11:05:50.628013 [Byte1]: 40
3403 11:05:50.632302
3404 11:05:50.632424 Set Vref, RX VrefLevel [Byte0]: 41
3405 11:05:50.636154 [Byte1]: 41
3406 11:05:50.640170
3407 11:05:50.640296 Set Vref, RX VrefLevel [Byte0]: 42
3408 11:05:50.643566 [Byte1]: 42
3409 11:05:50.648257
3410 11:05:50.648373 Set Vref, RX VrefLevel [Byte0]: 43
3411 11:05:50.651438 [Byte1]: 43
3412 11:05:50.656212
3413 11:05:50.656290 Set Vref, RX VrefLevel [Byte0]: 44
3414 11:05:50.659163 [Byte1]: 44
3415 11:05:50.663934
3416 11:05:50.664018 Set Vref, RX VrefLevel [Byte0]: 45
3417 11:05:50.667471 [Byte1]: 45
3418 11:05:50.672243
3419 11:05:50.672327 Set Vref, RX VrefLevel [Byte0]: 46
3420 11:05:50.675358 [Byte1]: 46
3421 11:05:50.679819
3422 11:05:50.679903 Set Vref, RX VrefLevel [Byte0]: 47
3423 11:05:50.683151 [Byte1]: 47
3424 11:05:50.687555
3425 11:05:50.687637 Set Vref, RX VrefLevel [Byte0]: 48
3426 11:05:50.691000 [Byte1]: 48
3427 11:05:50.695661
3428 11:05:50.695749 Set Vref, RX VrefLevel [Byte0]: 49
3429 11:05:50.699252 [Byte1]: 49
3430 11:05:50.703343
3431 11:05:50.703423 Set Vref, RX VrefLevel [Byte0]: 50
3432 11:05:50.707038 [Byte1]: 50
3433 11:05:50.711290
3434 11:05:50.711380 Set Vref, RX VrefLevel [Byte0]: 51
3435 11:05:50.715139 [Byte1]: 51
3436 11:05:50.719601
3437 11:05:50.719680 Set Vref, RX VrefLevel [Byte0]: 52
3438 11:05:50.723609 [Byte1]: 52
3439 11:05:50.727782
3440 11:05:50.727883 Set Vref, RX VrefLevel [Byte0]: 53
3441 11:05:50.730978 [Byte1]: 53
3442 11:05:50.735414
3443 11:05:50.735499 Set Vref, RX VrefLevel [Byte0]: 54
3444 11:05:50.738793 [Byte1]: 54
3445 11:05:50.743084
3446 11:05:50.743165 Set Vref, RX VrefLevel [Byte0]: 55
3447 11:05:50.746342 [Byte1]: 55
3448 11:05:50.750980
3449 11:05:50.751061 Set Vref, RX VrefLevel [Byte0]: 56
3450 11:05:50.754262 [Byte1]: 56
3451 11:05:50.759305
3452 11:05:50.759392 Set Vref, RX VrefLevel [Byte0]: 57
3453 11:05:50.762634 [Byte1]: 57
3454 11:05:50.767561
3455 11:05:50.767652 Set Vref, RX VrefLevel [Byte0]: 58
3456 11:05:50.770143 [Byte1]: 58
3457 11:05:50.774980
3458 11:05:50.775063 Set Vref, RX VrefLevel [Byte0]: 59
3459 11:05:50.778474 [Byte1]: 59
3460 11:05:50.782687
3461 11:05:50.782768 Set Vref, RX VrefLevel [Byte0]: 60
3462 11:05:50.786100 [Byte1]: 60
3463 11:05:50.790598
3464 11:05:50.790680 Set Vref, RX VrefLevel [Byte0]: 61
3465 11:05:50.794061 [Byte1]: 61
3466 11:05:50.798426
3467 11:05:50.798511 Set Vref, RX VrefLevel [Byte0]: 62
3468 11:05:50.801949 [Byte1]: 62
3469 11:05:50.806664
3470 11:05:50.806748 Set Vref, RX VrefLevel [Byte0]: 63
3471 11:05:50.809966 [Byte1]: 63
3472 11:05:50.814647
3473 11:05:50.814730 Set Vref, RX VrefLevel [Byte0]: 64
3474 11:05:50.817869 [Byte1]: 64
3475 11:05:50.822260
3476 11:05:50.822340 Set Vref, RX VrefLevel [Byte0]: 65
3477 11:05:50.825686 [Byte1]: 65
3478 11:05:50.830854
3479 11:05:50.830975 Set Vref, RX VrefLevel [Byte0]: 66
3480 11:05:50.833789 [Byte1]: 66
3481 11:05:50.838012
3482 11:05:50.838120 Set Vref, RX VrefLevel [Byte0]: 67
3483 11:05:50.841430 [Byte1]: 67
3484 11:05:50.846182
3485 11:05:50.846265 Set Vref, RX VrefLevel [Byte0]: 68
3486 11:05:50.849303 [Byte1]: 68
3487 11:05:50.854269
3488 11:05:50.854352 Set Vref, RX VrefLevel [Byte0]: 69
3489 11:05:50.857801 [Byte1]: 69
3490 11:05:50.862031
3491 11:05:50.862130 Set Vref, RX VrefLevel [Byte0]: 70
3492 11:05:50.865517 [Byte1]: 70
3493 11:05:50.869926
3494 11:05:50.870024 Final RX Vref Byte 0 = 57 to rank0
3495 11:05:50.873249 Final RX Vref Byte 1 = 49 to rank0
3496 11:05:50.876708 Final RX Vref Byte 0 = 57 to rank1
3497 11:05:50.880129 Final RX Vref Byte 1 = 49 to rank1==
3498 11:05:50.883218 Dram Type= 6, Freq= 0, CH_1, rank 0
3499 11:05:50.886542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 11:05:50.890377 ==
3501 11:05:50.890468 DQS Delay:
3502 11:05:50.890534 DQS0 = 0, DQS1 = 0
3503 11:05:50.893544 DQM Delay:
3504 11:05:50.893626 DQM0 = 116, DQM1 = 109
3505 11:05:50.896982 DQ Delay:
3506 11:05:50.900412 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3507 11:05:50.903756 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =114
3508 11:05:50.907413 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =106
3509 11:05:50.910324 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3510 11:05:50.910416
3511 11:05:50.910483
3512 11:05:50.916919 [DQSOSCAuto] RK0, (LSB)MR18= 0xfce1, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3513 11:05:50.920695 CH1 RK0: MR19=303, MR18=FCE1
3514 11:05:50.927045 CH1_RK0: MR19=0x303, MR18=0xFCE1, DQSOSC=411, MR23=63, INC=38, DEC=25
3515 11:05:50.927131
3516 11:05:50.930894 ----->DramcWriteLeveling(PI) begin...
3517 11:05:50.930982 ==
3518 11:05:50.934323 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 11:05:50.937269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 11:05:50.937352 ==
3521 11:05:50.940346 Write leveling (Byte 0): 27 => 27
3522 11:05:50.943758 Write leveling (Byte 1): 28 => 28
3523 11:05:50.946902 DramcWriteLeveling(PI) end<-----
3524 11:05:50.946985
3525 11:05:50.947050 ==
3526 11:05:50.950600 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 11:05:50.953790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 11:05:50.953873 ==
3529 11:05:50.956920 [Gating] SW mode calibration
3530 11:05:50.963712 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3531 11:05:50.970638 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3532 11:05:50.973875 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3533 11:05:50.980618 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3534 11:05:50.983918 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3535 11:05:50.987363 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3536 11:05:50.993840 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3537 11:05:50.997128 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3538 11:05:51.000850 0 15 24 | B1->B0 | 3232 2929 | 1 0 | (1 1) (1 0)
3539 11:05:51.003986 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 1) (0 0)
3540 11:05:51.010537 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3541 11:05:51.014667 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3542 11:05:51.017198 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3543 11:05:51.024262 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3544 11:05:51.027288 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3545 11:05:51.030417 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3546 11:05:51.037361 1 0 24 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
3547 11:05:51.040764 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3548 11:05:51.044054 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 11:05:51.050777 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3550 11:05:51.054095 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3551 11:05:51.057232 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3552 11:05:51.064124 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3553 11:05:51.067135 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3554 11:05:51.070487 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3555 11:05:51.077492 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3556 11:05:51.080552 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 11:05:51.084477 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 11:05:51.087262 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 11:05:51.094137 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 11:05:51.097315 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 11:05:51.100597 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 11:05:51.107427 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 11:05:51.110786 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 11:05:51.113869 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 11:05:51.120734 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 11:05:51.124000 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 11:05:51.127644 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 11:05:51.134125 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 11:05:51.137184 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 11:05:51.140670 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3571 11:05:51.147309 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3572 11:05:51.147393 Total UI for P1: 0, mck2ui 16
3573 11:05:51.153868 best dqsien dly found for B0: ( 1, 3, 24)
3574 11:05:51.157278 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3575 11:05:51.160540 Total UI for P1: 0, mck2ui 16
3576 11:05:51.164275 best dqsien dly found for B1: ( 1, 3, 28)
3577 11:05:51.167216 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3578 11:05:51.170859 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3579 11:05:51.170943
3580 11:05:51.173864 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3581 11:05:51.177523 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3582 11:05:51.180650 [Gating] SW calibration Done
3583 11:05:51.180734 ==
3584 11:05:51.183912 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 11:05:51.187719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 11:05:51.187830 ==
3587 11:05:51.190886 RX Vref Scan: 0
3588 11:05:51.190969
3589 11:05:51.194009 RX Vref 0 -> 0, step: 1
3590 11:05:51.194093
3591 11:05:51.194158 RX Delay -40 -> 252, step: 8
3592 11:05:51.200578 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3593 11:05:51.204036 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3594 11:05:51.207312 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3595 11:05:51.210831 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3596 11:05:51.213677 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3597 11:05:51.220419 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3598 11:05:51.223812 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3599 11:05:51.227130 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3600 11:05:51.230886 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3601 11:05:51.234097 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3602 11:05:51.240947 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3603 11:05:51.244119 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3604 11:05:51.247365 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3605 11:05:51.250672 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3606 11:05:51.253881 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3607 11:05:51.260842 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3608 11:05:51.260920 ==
3609 11:05:51.264448 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 11:05:51.267586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 11:05:51.267670 ==
3612 11:05:51.267736 DQS Delay:
3613 11:05:51.270597 DQS0 = 0, DQS1 = 0
3614 11:05:51.270687 DQM Delay:
3615 11:05:51.273850 DQM0 = 112, DQM1 = 108
3616 11:05:51.273957 DQ Delay:
3617 11:05:51.277418 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =111
3618 11:05:51.280533 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3619 11:05:51.285400 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3620 11:05:51.287856 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3621 11:05:51.287939
3622 11:05:51.288007
3623 11:05:51.288069 ==
3624 11:05:51.290653 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 11:05:51.297251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 11:05:51.297333 ==
3627 11:05:51.297400
3628 11:05:51.297458
3629 11:05:51.297515 TX Vref Scan disable
3630 11:05:51.300702 == TX Byte 0 ==
3631 11:05:51.304166 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3632 11:05:51.310690 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3633 11:05:51.310770 == TX Byte 1 ==
3634 11:05:51.314611 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3635 11:05:51.320964 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3636 11:05:51.321045 ==
3637 11:05:51.323982 Dram Type= 6, Freq= 0, CH_1, rank 1
3638 11:05:51.327933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3639 11:05:51.328037 ==
3640 11:05:51.338994 TX Vref=22, minBit 2, minWin=25, winSum=420
3641 11:05:51.342544 TX Vref=24, minBit 7, minWin=25, winSum=424
3642 11:05:51.345642 TX Vref=26, minBit 2, minWin=26, winSum=430
3643 11:05:51.348980 TX Vref=28, minBit 2, minWin=26, winSum=432
3644 11:05:51.352575 TX Vref=30, minBit 2, minWin=26, winSum=433
3645 11:05:51.355440 TX Vref=32, minBit 4, minWin=26, winSum=437
3646 11:05:51.361921 [TxChooseVref] Worse bit 4, Min win 26, Win sum 437, Final Vref 32
3647 11:05:51.362004
3648 11:05:51.365339 Final TX Range 1 Vref 32
3649 11:05:51.365420
3650 11:05:51.365483 ==
3651 11:05:51.368703 Dram Type= 6, Freq= 0, CH_1, rank 1
3652 11:05:51.371983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3653 11:05:51.372065 ==
3654 11:05:51.372128
3655 11:05:51.375620
3656 11:05:51.375700 TX Vref Scan disable
3657 11:05:51.378629 == TX Byte 0 ==
3658 11:05:51.381932 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3659 11:05:51.385589 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3660 11:05:51.388596 == TX Byte 1 ==
3661 11:05:51.391957 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3662 11:05:51.395257 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3663 11:05:51.395338
3664 11:05:51.398609 [DATLAT]
3665 11:05:51.398689 Freq=1200, CH1 RK1
3666 11:05:51.398753
3667 11:05:51.401906 DATLAT Default: 0xd
3668 11:05:51.401986 0, 0xFFFF, sum = 0
3669 11:05:51.405211 1, 0xFFFF, sum = 0
3670 11:05:51.405293 2, 0xFFFF, sum = 0
3671 11:05:51.408688 3, 0xFFFF, sum = 0
3672 11:05:51.408770 4, 0xFFFF, sum = 0
3673 11:05:51.412088 5, 0xFFFF, sum = 0
3674 11:05:51.412170 6, 0xFFFF, sum = 0
3675 11:05:51.415236 7, 0xFFFF, sum = 0
3676 11:05:51.415363 8, 0xFFFF, sum = 0
3677 11:05:51.418698 9, 0xFFFF, sum = 0
3678 11:05:51.418823 10, 0xFFFF, sum = 0
3679 11:05:51.421877 11, 0xFFFF, sum = 0
3680 11:05:51.425240 12, 0x0, sum = 1
3681 11:05:51.425322 13, 0x0, sum = 2
3682 11:05:51.425387 14, 0x0, sum = 3
3683 11:05:51.428834 15, 0x0, sum = 4
3684 11:05:51.428917 best_step = 13
3685 11:05:51.428980
3686 11:05:51.429039 ==
3687 11:05:51.431922 Dram Type= 6, Freq= 0, CH_1, rank 1
3688 11:05:51.438414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3689 11:05:51.438511 ==
3690 11:05:51.438574 RX Vref Scan: 0
3691 11:05:51.438634
3692 11:05:51.442320 RX Vref 0 -> 0, step: 1
3693 11:05:51.442413
3694 11:05:51.445632 RX Delay -21 -> 252, step: 4
3695 11:05:51.448676 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3696 11:05:51.452296 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3697 11:05:51.459278 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3698 11:05:51.461920 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3699 11:05:51.465068 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3700 11:05:51.468364 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3701 11:05:51.472058 iDelay=191, Bit 6, Center 120 (55 ~ 186) 132
3702 11:05:51.478675 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3703 11:05:51.481886 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3704 11:05:51.485299 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3705 11:05:51.488783 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3706 11:05:51.492233 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3707 11:05:51.498512 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3708 11:05:51.501857 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3709 11:05:51.505176 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3710 11:05:51.508433 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3711 11:05:51.508514 ==
3712 11:05:51.511582 Dram Type= 6, Freq= 0, CH_1, rank 1
3713 11:05:51.518457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3714 11:05:51.518556 ==
3715 11:05:51.518619 DQS Delay:
3716 11:05:51.518679 DQS0 = 0, DQS1 = 0
3717 11:05:51.522227 DQM Delay:
3718 11:05:51.522307 DQM0 = 113, DQM1 = 109
3719 11:05:51.525295 DQ Delay:
3720 11:05:51.528946 DQ0 =114, DQ1 =110, DQ2 =104, DQ3 =112
3721 11:05:51.532231 DQ4 =114, DQ5 =122, DQ6 =120, DQ7 =110
3722 11:05:51.535055 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =100
3723 11:05:51.538627 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =118
3724 11:05:51.538744
3725 11:05:51.538873
3726 11:05:51.545362 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3727 11:05:51.548519 CH1 RK1: MR19=303, MR18=F7FF
3728 11:05:51.555480 CH1_RK1: MR19=0x303, MR18=0xF7FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3729 11:05:51.558382 [RxdqsGatingPostProcess] freq 1200
3730 11:05:51.566730 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3731 11:05:51.568633 best DQS0 dly(2T, 0.5T) = (0, 11)
3732 11:05:51.568716 best DQS1 dly(2T, 0.5T) = (0, 11)
3733 11:05:51.571832 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3734 11:05:51.575457 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3735 11:05:51.578855 best DQS0 dly(2T, 0.5T) = (0, 11)
3736 11:05:51.581568 best DQS1 dly(2T, 0.5T) = (0, 11)
3737 11:05:51.585423 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3738 11:05:51.589121 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3739 11:05:51.591636 Pre-setting of DQS Precalculation
3740 11:05:51.598433 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3741 11:05:51.605079 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3742 11:05:51.611668 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3743 11:05:51.611751
3744 11:05:51.611816
3745 11:05:51.615157 [Calibration Summary] 2400 Mbps
3746 11:05:51.615239 CH 0, Rank 0
3747 11:05:51.618550 SW Impedance : PASS
3748 11:05:51.622161 DUTY Scan : NO K
3749 11:05:51.622242 ZQ Calibration : PASS
3750 11:05:51.625086 Jitter Meter : NO K
3751 11:05:51.628299 CBT Training : PASS
3752 11:05:51.628427 Write leveling : PASS
3753 11:05:51.631762 RX DQS gating : PASS
3754 11:05:51.631844 RX DQ/DQS(RDDQC) : PASS
3755 11:05:51.635315 TX DQ/DQS : PASS
3756 11:05:51.638386 RX DATLAT : PASS
3757 11:05:51.638487 RX DQ/DQS(Engine): PASS
3758 11:05:51.641833 TX OE : NO K
3759 11:05:51.641914 All Pass.
3760 11:05:51.641977
3761 11:05:51.645206 CH 0, Rank 1
3762 11:05:51.645288 SW Impedance : PASS
3763 11:05:51.648606 DUTY Scan : NO K
3764 11:05:51.651504 ZQ Calibration : PASS
3765 11:05:51.651618 Jitter Meter : NO K
3766 11:05:51.655310 CBT Training : PASS
3767 11:05:51.658289 Write leveling : PASS
3768 11:05:51.658383 RX DQS gating : PASS
3769 11:05:51.661709 RX DQ/DQS(RDDQC) : PASS
3770 11:05:51.664834 TX DQ/DQS : PASS
3771 11:05:51.664916 RX DATLAT : PASS
3772 11:05:51.668380 RX DQ/DQS(Engine): PASS
3773 11:05:51.671669 TX OE : NO K
3774 11:05:51.671751 All Pass.
3775 11:05:51.671815
3776 11:05:51.671875 CH 1, Rank 0
3777 11:05:51.675676 SW Impedance : PASS
3778 11:05:51.678352 DUTY Scan : NO K
3779 11:05:51.678467 ZQ Calibration : PASS
3780 11:05:51.681593 Jitter Meter : NO K
3781 11:05:51.681675 CBT Training : PASS
3782 11:05:51.685177 Write leveling : PASS
3783 11:05:51.688817 RX DQS gating : PASS
3784 11:05:51.688898 RX DQ/DQS(RDDQC) : PASS
3785 11:05:51.691607 TX DQ/DQS : PASS
3786 11:05:51.694869 RX DATLAT : PASS
3787 11:05:51.694951 RX DQ/DQS(Engine): PASS
3788 11:05:51.698182 TX OE : NO K
3789 11:05:51.698301 All Pass.
3790 11:05:51.698393
3791 11:05:51.701861 CH 1, Rank 1
3792 11:05:51.701943 SW Impedance : PASS
3793 11:05:51.705141 DUTY Scan : NO K
3794 11:05:51.709092 ZQ Calibration : PASS
3795 11:05:51.709173 Jitter Meter : NO K
3796 11:05:51.711935 CBT Training : PASS
3797 11:05:51.715117 Write leveling : PASS
3798 11:05:51.715199 RX DQS gating : PASS
3799 11:05:51.718745 RX DQ/DQS(RDDQC) : PASS
3800 11:05:51.718826 TX DQ/DQS : PASS
3801 11:05:51.722277 RX DATLAT : PASS
3802 11:05:51.724932 RX DQ/DQS(Engine): PASS
3803 11:05:51.725013 TX OE : NO K
3804 11:05:51.728535 All Pass.
3805 11:05:51.728632
3806 11:05:51.728698 DramC Write-DBI off
3807 11:05:51.731965 PER_BANK_REFRESH: Hybrid Mode
3808 11:05:51.735306 TX_TRACKING: ON
3809 11:05:51.742198 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3810 11:05:51.745519 [FAST_K] Save calibration result to emmc
3811 11:05:51.748847 dramc_set_vcore_voltage set vcore to 650000
3812 11:05:51.752234 Read voltage for 600, 5
3813 11:05:51.752314 Vio18 = 0
3814 11:05:51.755147 Vcore = 650000
3815 11:05:51.755253 Vdram = 0
3816 11:05:51.755344 Vddq = 0
3817 11:05:51.758496 Vmddr = 0
3818 11:05:51.761744 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3819 11:05:51.768394 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3820 11:05:51.768515 MEM_TYPE=3, freq_sel=19
3821 11:05:51.771755 sv_algorithm_assistance_LP4_1600
3822 11:05:51.778649 ============ PULL DRAM RESETB DOWN ============
3823 11:05:51.782251 ========== PULL DRAM RESETB DOWN end =========
3824 11:05:51.785346 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3825 11:05:51.788768 ===================================
3826 11:05:51.791728 LPDDR4 DRAM CONFIGURATION
3827 11:05:51.794905 ===================================
3828 11:05:51.794986 EX_ROW_EN[0] = 0x0
3829 11:05:51.798786 EX_ROW_EN[1] = 0x0
3830 11:05:51.801938 LP4Y_EN = 0x0
3831 11:05:51.802044 WORK_FSP = 0x0
3832 11:05:51.805315 WL = 0x2
3833 11:05:51.805421 RL = 0x2
3834 11:05:51.808737 BL = 0x2
3835 11:05:51.808812 RPST = 0x0
3836 11:05:51.811588 RD_PRE = 0x0
3837 11:05:51.811697 WR_PRE = 0x1
3838 11:05:51.815251 WR_PST = 0x0
3839 11:05:51.815354 DBI_WR = 0x0
3840 11:05:51.818307 DBI_RD = 0x0
3841 11:05:51.818433 OTF = 0x1
3842 11:05:51.821722 ===================================
3843 11:05:51.825223 ===================================
3844 11:05:51.828530 ANA top config
3845 11:05:51.831743 ===================================
3846 11:05:51.831849 DLL_ASYNC_EN = 0
3847 11:05:51.835173 ALL_SLAVE_EN = 1
3848 11:05:51.838183 NEW_RANK_MODE = 1
3849 11:05:51.842286 DLL_IDLE_MODE = 1
3850 11:05:51.845245 LP45_APHY_COMB_EN = 1
3851 11:05:51.845350 TX_ODT_DIS = 1
3852 11:05:51.848554 NEW_8X_MODE = 1
3853 11:05:51.851592 ===================================
3854 11:05:51.855042 ===================================
3855 11:05:51.858390 data_rate = 1200
3856 11:05:51.861963 CKR = 1
3857 11:05:51.864787 DQ_P2S_RATIO = 8
3858 11:05:51.868490 ===================================
3859 11:05:51.868629 CA_P2S_RATIO = 8
3860 11:05:51.871578 DQ_CA_OPEN = 0
3861 11:05:51.875224 DQ_SEMI_OPEN = 0
3862 11:05:51.878653 CA_SEMI_OPEN = 0
3863 11:05:51.881528 CA_FULL_RATE = 0
3864 11:05:51.885119 DQ_CKDIV4_EN = 1
3865 11:05:51.885224 CA_CKDIV4_EN = 1
3866 11:05:51.888607 CA_PREDIV_EN = 0
3867 11:05:51.891998 PH8_DLY = 0
3868 11:05:51.894987 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3869 11:05:51.898698 DQ_AAMCK_DIV = 4
3870 11:05:51.898807 CA_AAMCK_DIV = 4
3871 11:05:51.901581 CA_ADMCK_DIV = 4
3872 11:05:51.905205 DQ_TRACK_CA_EN = 0
3873 11:05:51.908429 CA_PICK = 600
3874 11:05:51.912099 CA_MCKIO = 600
3875 11:05:51.915372 MCKIO_SEMI = 0
3876 11:05:51.918432 PLL_FREQ = 2288
3877 11:05:51.918541 DQ_UI_PI_RATIO = 32
3878 11:05:51.921893 CA_UI_PI_RATIO = 0
3879 11:05:51.925071 ===================================
3880 11:05:51.928727 ===================================
3881 11:05:51.931695 memory_type:LPDDR4
3882 11:05:51.935384 GP_NUM : 10
3883 11:05:51.935467 SRAM_EN : 1
3884 11:05:51.938314 MD32_EN : 0
3885 11:05:51.942338 ===================================
3886 11:05:51.942427 [ANA_INIT] >>>>>>>>>>>>>>
3887 11:05:51.944995 <<<<<< [CONFIGURE PHASE]: ANA_TX
3888 11:05:51.948783 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3889 11:05:51.951659 ===================================
3890 11:05:51.955294 data_rate = 1200,PCW = 0X5800
3891 11:05:51.958421 ===================================
3892 11:05:51.961705 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3893 11:05:51.968466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3894 11:05:51.972208 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3895 11:05:51.978338 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3896 11:05:51.981908 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3897 11:05:51.985278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3898 11:05:51.988923 [ANA_INIT] flow start
3899 11:05:51.989029 [ANA_INIT] PLL >>>>>>>>
3900 11:05:51.991840 [ANA_INIT] PLL <<<<<<<<
3901 11:05:51.995558 [ANA_INIT] MIDPI >>>>>>>>
3902 11:05:51.995662 [ANA_INIT] MIDPI <<<<<<<<
3903 11:05:51.998791 [ANA_INIT] DLL >>>>>>>>
3904 11:05:52.001962 [ANA_INIT] flow end
3905 11:05:52.006018 ============ LP4 DIFF to SE enter ============
3906 11:05:52.008635 ============ LP4 DIFF to SE exit ============
3907 11:05:52.012322 [ANA_INIT] <<<<<<<<<<<<<
3908 11:05:52.015747 [Flow] Enable top DCM control >>>>>
3909 11:05:52.018583 [Flow] Enable top DCM control <<<<<
3910 11:05:52.022263 Enable DLL master slave shuffle
3911 11:05:52.025815 ==============================================================
3912 11:05:52.028537 Gating Mode config
3913 11:05:52.032462 ==============================================================
3914 11:05:52.035162 Config description:
3915 11:05:52.045576 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3916 11:05:52.052080 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3917 11:05:52.054877 SELPH_MODE 0: By rank 1: By Phase
3918 11:05:52.061849 ==============================================================
3919 11:05:52.065116 GAT_TRACK_EN = 1
3920 11:05:52.068519 RX_GATING_MODE = 2
3921 11:05:52.072100 RX_GATING_TRACK_MODE = 2
3922 11:05:52.075274 SELPH_MODE = 1
3923 11:05:52.078390 PICG_EARLY_EN = 1
3924 11:05:52.081822 VALID_LAT_VALUE = 1
3925 11:05:52.084973 ==============================================================
3926 11:05:52.088433 Enter into Gating configuration >>>>
3927 11:05:52.091327 Exit from Gating configuration <<<<
3928 11:05:52.095053 Enter into DVFS_PRE_config >>>>>
3929 11:05:52.105296 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3930 11:05:52.108197 Exit from DVFS_PRE_config <<<<<
3931 11:05:52.111574 Enter into PICG configuration >>>>
3932 11:05:52.115006 Exit from PICG configuration <<<<
3933 11:05:52.118492 [RX_INPUT] configuration >>>>>
3934 11:05:52.121602 [RX_INPUT] configuration <<<<<
3935 11:05:52.128536 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3936 11:05:52.131539 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3937 11:05:52.138224 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3938 11:05:52.144961 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3939 11:05:52.151697 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3940 11:05:52.158327 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3941 11:05:52.161664 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3942 11:05:52.164809 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3943 11:05:52.168143 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3944 11:05:52.174906 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3945 11:05:52.178179 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3946 11:05:52.181277 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3947 11:05:52.184929 ===================================
3948 11:05:52.187858 LPDDR4 DRAM CONFIGURATION
3949 11:05:52.191096 ===================================
3950 11:05:52.191180 EX_ROW_EN[0] = 0x0
3951 11:05:52.194332 EX_ROW_EN[1] = 0x0
3952 11:05:52.198007 LP4Y_EN = 0x0
3953 11:05:52.198090 WORK_FSP = 0x0
3954 11:05:52.201132 WL = 0x2
3955 11:05:52.201245 RL = 0x2
3956 11:05:52.204865 BL = 0x2
3957 11:05:52.204949 RPST = 0x0
3958 11:05:52.207995 RD_PRE = 0x0
3959 11:05:52.208075 WR_PRE = 0x1
3960 11:05:52.211051 WR_PST = 0x0
3961 11:05:52.211133 DBI_WR = 0x0
3962 11:05:52.214355 DBI_RD = 0x0
3963 11:05:52.214470 OTF = 0x1
3964 11:05:52.218050 ===================================
3965 11:05:52.221803 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3966 11:05:52.228317 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3967 11:05:52.231478 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3968 11:05:52.234460 ===================================
3969 11:05:52.237981 LPDDR4 DRAM CONFIGURATION
3970 11:05:52.241165 ===================================
3971 11:05:52.241247 EX_ROW_EN[0] = 0x10
3972 11:05:52.244787 EX_ROW_EN[1] = 0x0
3973 11:05:52.244884 LP4Y_EN = 0x0
3974 11:05:52.248161 WORK_FSP = 0x0
3975 11:05:52.248242 WL = 0x2
3976 11:05:52.251539 RL = 0x2
3977 11:05:52.251620 BL = 0x2
3978 11:05:52.254782 RPST = 0x0
3979 11:05:52.254862 RD_PRE = 0x0
3980 11:05:52.258335 WR_PRE = 0x1
3981 11:05:52.258439 WR_PST = 0x0
3982 11:05:52.261475 DBI_WR = 0x0
3983 11:05:52.261556 DBI_RD = 0x0
3984 11:05:52.264834 OTF = 0x1
3985 11:05:52.268248 ===================================
3986 11:05:52.274838 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3987 11:05:52.278457 nWR fixed to 30
3988 11:05:52.281050 [ModeRegInit_LP4] CH0 RK0
3989 11:05:52.281131 [ModeRegInit_LP4] CH0 RK1
3990 11:05:52.284821 [ModeRegInit_LP4] CH1 RK0
3991 11:05:52.288411 [ModeRegInit_LP4] CH1 RK1
3992 11:05:52.288493 match AC timing 17
3993 11:05:52.294893 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3994 11:05:52.297941 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3995 11:05:52.301330 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3996 11:05:52.307988 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3997 11:05:52.311450 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3998 11:05:52.311532 ==
3999 11:05:52.314706 Dram Type= 6, Freq= 0, CH_0, rank 0
4000 11:05:52.317965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4001 11:05:52.318048 ==
4002 11:05:52.324429 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4003 11:05:52.331187 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4004 11:05:52.334530 [CA 0] Center 36 (6~66) winsize 61
4005 11:05:52.338051 [CA 1] Center 36 (6~66) winsize 61
4006 11:05:52.341396 [CA 2] Center 34 (4~65) winsize 62
4007 11:05:52.344590 [CA 3] Center 34 (4~65) winsize 62
4008 11:05:52.347708 [CA 4] Center 34 (4~64) winsize 61
4009 11:05:52.351191 [CA 5] Center 33 (3~64) winsize 62
4010 11:05:52.351310
4011 11:05:52.354859 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4012 11:05:52.354940
4013 11:05:52.357960 [CATrainingPosCal] consider 1 rank data
4014 11:05:52.361128 u2DelayCellTimex100 = 270/100 ps
4015 11:05:52.365214 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4016 11:05:52.368116 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4017 11:05:52.371531 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4018 11:05:52.374698 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4019 11:05:52.378187 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4020 11:05:52.381075 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4021 11:05:52.381159
4022 11:05:52.388039 CA PerBit enable=1, Macro0, CA PI delay=33
4023 11:05:52.388123
4024 11:05:52.388190 [CBTSetCACLKResult] CA Dly = 33
4025 11:05:52.391107 CS Dly: 4 (0~35)
4026 11:05:52.391178 ==
4027 11:05:52.394503 Dram Type= 6, Freq= 0, CH_0, rank 1
4028 11:05:52.397804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 11:05:52.397889 ==
4030 11:05:52.404628 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4031 11:05:52.411325 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4032 11:05:52.414698 [CA 0] Center 36 (6~67) winsize 62
4033 11:05:52.418292 [CA 1] Center 36 (6~66) winsize 61
4034 11:05:52.421594 [CA 2] Center 34 (4~65) winsize 62
4035 11:05:52.425140 [CA 3] Center 34 (4~65) winsize 62
4036 11:05:52.428216 [CA 4] Center 33 (3~64) winsize 62
4037 11:05:52.431104 [CA 5] Center 33 (3~64) winsize 62
4038 11:05:52.431185
4039 11:05:52.434600 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4040 11:05:52.434681
4041 11:05:52.438055 [CATrainingPosCal] consider 2 rank data
4042 11:05:52.441336 u2DelayCellTimex100 = 270/100 ps
4043 11:05:52.444695 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4044 11:05:52.447881 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4045 11:05:52.451221 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4046 11:05:52.454784 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4047 11:05:52.457979 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4048 11:05:52.461764 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4049 11:05:52.461850
4050 11:05:52.467908 CA PerBit enable=1, Macro0, CA PI delay=33
4051 11:05:52.467990
4052 11:05:52.468054 [CBTSetCACLKResult] CA Dly = 33
4053 11:05:52.471911 CS Dly: 4 (0~36)
4054 11:05:52.471993
4055 11:05:52.475168 ----->DramcWriteLeveling(PI) begin...
4056 11:05:52.475251 ==
4057 11:05:52.478150 Dram Type= 6, Freq= 0, CH_0, rank 0
4058 11:05:52.481934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4059 11:05:52.482016 ==
4060 11:05:52.484807 Write leveling (Byte 0): 31 => 31
4061 11:05:52.487869 Write leveling (Byte 1): 29 => 29
4062 11:05:52.491431 DramcWriteLeveling(PI) end<-----
4063 11:05:52.491513
4064 11:05:52.491576 ==
4065 11:05:52.494827 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 11:05:52.498289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 11:05:52.501411 ==
4068 11:05:52.501507 [Gating] SW mode calibration
4069 11:05:52.511443 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4070 11:05:52.514766 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4071 11:05:52.518051 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4072 11:05:52.524689 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4073 11:05:52.528547 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4074 11:05:52.531944 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4075 11:05:52.537972 0 9 16 | B1->B0 | 3131 2f2f | 1 1 | (0 0) (0 0)
4076 11:05:52.541423 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
4077 11:05:52.544599 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4078 11:05:52.551643 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4079 11:05:52.554950 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4080 11:05:52.558021 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4081 11:05:52.562005 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4082 11:05:52.567901 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4083 11:05:52.571484 0 10 16 | B1->B0 | 3030 3737 | 0 1 | (0 0) (1 1)
4084 11:05:52.575071 0 10 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4085 11:05:52.581405 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 11:05:52.585014 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4087 11:05:52.587972 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4088 11:05:52.595007 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4089 11:05:52.598178 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4090 11:05:52.601410 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4091 11:05:52.608298 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4092 11:05:52.611252 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 11:05:52.614914 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 11:05:52.621528 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 11:05:52.624712 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 11:05:52.628531 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 11:05:52.634855 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 11:05:52.638348 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 11:05:52.641533 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 11:05:52.647860 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 11:05:52.651353 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 11:05:52.654625 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 11:05:52.658082 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 11:05:52.664563 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 11:05:52.667930 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 11:05:52.671720 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4107 11:05:52.678350 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4108 11:05:52.681442 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4109 11:05:52.684670 Total UI for P1: 0, mck2ui 16
4110 11:05:52.688466 best dqsien dly found for B0: ( 0, 13, 14)
4111 11:05:52.691521 Total UI for P1: 0, mck2ui 16
4112 11:05:52.694726 best dqsien dly found for B1: ( 0, 13, 18)
4113 11:05:52.698202 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4114 11:05:52.701223 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4115 11:05:52.701335
4116 11:05:52.704612 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4117 11:05:52.708135 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4118 11:05:52.711138 [Gating] SW calibration Done
4119 11:05:52.711224 ==
4120 11:05:52.714691 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 11:05:52.721140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 11:05:52.721238 ==
4123 11:05:52.721326 RX Vref Scan: 0
4124 11:05:52.721408
4125 11:05:52.725124 RX Vref 0 -> 0, step: 1
4126 11:05:52.725211
4127 11:05:52.728226 RX Delay -230 -> 252, step: 16
4128 11:05:52.731473 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4129 11:05:52.734658 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4130 11:05:52.737875 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4131 11:05:52.744722 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4132 11:05:52.748340 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4133 11:05:52.751449 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4134 11:05:52.754908 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4135 11:05:52.757834 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4136 11:05:52.764371 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4137 11:05:52.768273 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4138 11:05:52.771576 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4139 11:05:52.774701 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4140 11:05:52.781578 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4141 11:05:52.785117 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4142 11:05:52.788333 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4143 11:05:52.791505 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4144 11:05:52.791588 ==
4145 11:05:52.795279 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 11:05:52.801478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 11:05:52.801562 ==
4148 11:05:52.801627 DQS Delay:
4149 11:05:52.804925 DQS0 = 0, DQS1 = 0
4150 11:05:52.805007 DQM Delay:
4151 11:05:52.805073 DQM0 = 39, DQM1 = 32
4152 11:05:52.808169 DQ Delay:
4153 11:05:52.811670 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4154 11:05:52.814567 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4155 11:05:52.818442 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4156 11:05:52.821803 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4157 11:05:52.821890
4158 11:05:52.821977
4159 11:05:52.822086 ==
4160 11:05:52.824470 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 11:05:52.828143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 11:05:52.828231 ==
4163 11:05:52.828318
4164 11:05:52.828400
4165 11:05:52.831230 TX Vref Scan disable
4166 11:05:52.831316 == TX Byte 0 ==
4167 11:05:52.837926 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4168 11:05:52.841577 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4169 11:05:52.841664 == TX Byte 1 ==
4170 11:05:52.847916 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4171 11:05:52.851740 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4172 11:05:52.851827 ==
4173 11:05:52.854528 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 11:05:52.858164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 11:05:52.858276 ==
4176 11:05:52.858379
4177 11:05:52.858473
4178 11:05:52.861606 TX Vref Scan disable
4179 11:05:52.865170 == TX Byte 0 ==
4180 11:05:52.868153 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4181 11:05:52.875112 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4182 11:05:52.875222 == TX Byte 1 ==
4183 11:05:52.878229 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4184 11:05:52.884591 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4185 11:05:52.884674
4186 11:05:52.884739 [DATLAT]
4187 11:05:52.884800 Freq=600, CH0 RK0
4188 11:05:52.884860
4189 11:05:52.887776 DATLAT Default: 0x9
4190 11:05:52.887858 0, 0xFFFF, sum = 0
4191 11:05:52.891193 1, 0xFFFF, sum = 0
4192 11:05:52.891277 2, 0xFFFF, sum = 0
4193 11:05:52.894844 3, 0xFFFF, sum = 0
4194 11:05:52.898071 4, 0xFFFF, sum = 0
4195 11:05:52.898183 5, 0xFFFF, sum = 0
4196 11:05:52.901007 6, 0xFFFF, sum = 0
4197 11:05:52.901092 7, 0xFFFF, sum = 0
4198 11:05:52.904390 8, 0x0, sum = 1
4199 11:05:52.904474 9, 0x0, sum = 2
4200 11:05:52.904540 10, 0x0, sum = 3
4201 11:05:52.907903 11, 0x0, sum = 4
4202 11:05:52.907987 best_step = 9
4203 11:05:52.908052
4204 11:05:52.908114 ==
4205 11:05:52.911824 Dram Type= 6, Freq= 0, CH_0, rank 0
4206 11:05:52.918222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 11:05:52.918306 ==
4208 11:05:52.918371 RX Vref Scan: 1
4209 11:05:52.918440
4210 11:05:52.921432 RX Vref 0 -> 0, step: 1
4211 11:05:52.921514
4212 11:05:52.924801 RX Delay -195 -> 252, step: 8
4213 11:05:52.924927
4214 11:05:52.928073 Set Vref, RX VrefLevel [Byte0]: 52
4215 11:05:52.931623 [Byte1]: 50
4216 11:05:52.931749
4217 11:05:52.935144 Final RX Vref Byte 0 = 52 to rank0
4218 11:05:52.938383 Final RX Vref Byte 1 = 50 to rank0
4219 11:05:52.941192 Final RX Vref Byte 0 = 52 to rank1
4220 11:05:52.944994 Final RX Vref Byte 1 = 50 to rank1==
4221 11:05:52.947724 Dram Type= 6, Freq= 0, CH_0, rank 0
4222 11:05:52.951350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 11:05:52.951478 ==
4224 11:05:52.954535 DQS Delay:
4225 11:05:52.954658 DQS0 = 0, DQS1 = 0
4226 11:05:52.954773 DQM Delay:
4227 11:05:52.957925 DQM0 = 42, DQM1 = 33
4228 11:05:52.958047 DQ Delay:
4229 11:05:52.961137 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4230 11:05:52.964501 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4231 11:05:52.967861 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4232 11:05:52.971492 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4233 11:05:52.971582
4234 11:05:52.971653
4235 11:05:52.981310 [DQSOSCAuto] RK0, (LSB)MR18= 0x411f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
4236 11:05:52.984650 CH0 RK0: MR19=808, MR18=411F
4237 11:05:52.987709 CH0_RK0: MR19=0x808, MR18=0x411F, DQSOSC=397, MR23=63, INC=166, DEC=110
4238 11:05:52.987796
4239 11:05:52.991057 ----->DramcWriteLeveling(PI) begin...
4240 11:05:52.994856 ==
4241 11:05:52.994939 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 11:05:53.000988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 11:05:53.001073 ==
4244 11:05:53.004681 Write leveling (Byte 0): 31 => 31
4245 11:05:53.008097 Write leveling (Byte 1): 30 => 30
4246 11:05:53.011493 DramcWriteLeveling(PI) end<-----
4247 11:05:53.011586
4248 11:05:53.011675 ==
4249 11:05:53.014528 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 11:05:53.018111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 11:05:53.018217 ==
4252 11:05:53.021285 [Gating] SW mode calibration
4253 11:05:53.028170 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4254 11:05:53.031289 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4255 11:05:53.038115 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4256 11:05:53.041474 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4257 11:05:53.044473 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4258 11:05:53.051505 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
4259 11:05:53.054314 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
4260 11:05:53.057916 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4261 11:05:53.064909 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4262 11:05:53.067764 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4263 11:05:53.071201 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4264 11:05:53.077852 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4265 11:05:53.080934 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4266 11:05:53.084450 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
4267 11:05:53.090956 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
4268 11:05:53.094440 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 11:05:53.097681 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4270 11:05:53.104937 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4271 11:05:53.107859 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4272 11:05:53.111402 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 11:05:53.118118 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 11:05:53.120760 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 11:05:53.124463 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4276 11:05:53.131123 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 11:05:53.133905 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 11:05:53.137304 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 11:05:53.144159 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 11:05:53.147474 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 11:05:53.150905 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 11:05:53.153941 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 11:05:53.160607 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 11:05:53.164366 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 11:05:53.167311 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 11:05:53.174088 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 11:05:53.177400 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 11:05:53.180280 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 11:05:53.187082 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 11:05:53.190808 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4291 11:05:53.193924 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4292 11:05:53.197552 Total UI for P1: 0, mck2ui 16
4293 11:05:53.200233 best dqsien dly found for B0: ( 0, 13, 12)
4294 11:05:53.203732 Total UI for P1: 0, mck2ui 16
4295 11:05:53.206823 best dqsien dly found for B1: ( 0, 13, 14)
4296 11:05:53.210893 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4297 11:05:53.217149 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4298 11:05:53.217256
4299 11:05:53.220245 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4300 11:05:53.223656 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4301 11:05:53.227365 [Gating] SW calibration Done
4302 11:05:53.227448 ==
4303 11:05:53.230078 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 11:05:53.233498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 11:05:53.233608 ==
4306 11:05:53.237254 RX Vref Scan: 0
4307 11:05:53.237347
4308 11:05:53.237414 RX Vref 0 -> 0, step: 1
4309 11:05:53.237475
4310 11:05:53.240287 RX Delay -230 -> 252, step: 16
4311 11:05:53.243443 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4312 11:05:53.249952 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4313 11:05:53.253603 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4314 11:05:53.256632 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4315 11:05:53.259917 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4316 11:05:53.263285 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4317 11:05:53.270590 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4318 11:05:53.273651 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4319 11:05:53.276915 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4320 11:05:53.279971 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4321 11:05:53.286867 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4322 11:05:53.290258 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4323 11:05:53.293716 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4324 11:05:53.296668 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4325 11:05:53.303762 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4326 11:05:53.306533 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4327 11:05:53.306645 ==
4328 11:05:53.309949 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 11:05:53.313704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 11:05:53.313788 ==
4331 11:05:53.313854 DQS Delay:
4332 11:05:53.317426 DQS0 = 0, DQS1 = 0
4333 11:05:53.317511 DQM Delay:
4334 11:05:53.320071 DQM0 = 40, DQM1 = 32
4335 11:05:53.320164 DQ Delay:
4336 11:05:53.323579 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4337 11:05:53.326413 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4338 11:05:53.330460 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4339 11:05:53.333554 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4340 11:05:53.333675
4341 11:05:53.333785
4342 11:05:53.333890 ==
4343 11:05:53.336429 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 11:05:53.340041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 11:05:53.343018 ==
4346 11:05:53.343143
4347 11:05:53.343259
4348 11:05:53.343373 TX Vref Scan disable
4349 11:05:53.346740 == TX Byte 0 ==
4350 11:05:53.349795 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4351 11:05:53.353193 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4352 11:05:53.356514 == TX Byte 1 ==
4353 11:05:53.359808 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4354 11:05:53.363099 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4355 11:05:53.366503 ==
4356 11:05:53.369588 Dram Type= 6, Freq= 0, CH_0, rank 1
4357 11:05:53.373095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 11:05:53.373222 ==
4359 11:05:53.373336
4360 11:05:53.373446
4361 11:05:53.376580 TX Vref Scan disable
4362 11:05:53.376703 == TX Byte 0 ==
4363 11:05:53.383282 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4364 11:05:53.386374 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4365 11:05:53.386507 == TX Byte 1 ==
4366 11:05:53.392959 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4367 11:05:53.396472 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4368 11:05:53.396596
4369 11:05:53.396709 [DATLAT]
4370 11:05:53.400099 Freq=600, CH0 RK1
4371 11:05:53.400226
4372 11:05:53.400335 DATLAT Default: 0x9
4373 11:05:53.403107 0, 0xFFFF, sum = 0
4374 11:05:53.403233 1, 0xFFFF, sum = 0
4375 11:05:53.406586 2, 0xFFFF, sum = 0
4376 11:05:53.406707 3, 0xFFFF, sum = 0
4377 11:05:53.409877 4, 0xFFFF, sum = 0
4378 11:05:53.413054 5, 0xFFFF, sum = 0
4379 11:05:53.413180 6, 0xFFFF, sum = 0
4380 11:05:53.416499 7, 0xFFFF, sum = 0
4381 11:05:53.416626 8, 0x0, sum = 1
4382 11:05:53.416743 9, 0x0, sum = 2
4383 11:05:53.420077 10, 0x0, sum = 3
4384 11:05:53.420201 11, 0x0, sum = 4
4385 11:05:53.423123 best_step = 9
4386 11:05:53.423243
4387 11:05:53.423357 ==
4388 11:05:53.426351 Dram Type= 6, Freq= 0, CH_0, rank 1
4389 11:05:53.429639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 11:05:53.429714 ==
4391 11:05:53.433468 RX Vref Scan: 0
4392 11:05:53.433550
4393 11:05:53.433614 RX Vref 0 -> 0, step: 1
4394 11:05:53.433674
4395 11:05:53.436472 RX Delay -195 -> 252, step: 8
4396 11:05:53.443876 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4397 11:05:53.446991 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4398 11:05:53.450782 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4399 11:05:53.453813 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4400 11:05:53.460324 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4401 11:05:53.463902 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4402 11:05:53.467232 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4403 11:05:53.470733 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4404 11:05:53.473885 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4405 11:05:53.480459 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4406 11:05:53.483456 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4407 11:05:53.486865 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4408 11:05:53.490682 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4409 11:05:53.497332 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4410 11:05:53.500583 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4411 11:05:53.503999 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4412 11:05:53.504081 ==
4413 11:05:53.507140 Dram Type= 6, Freq= 0, CH_0, rank 1
4414 11:05:53.510337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 11:05:53.510426 ==
4416 11:05:53.513914 DQS Delay:
4417 11:05:53.513996 DQS0 = 0, DQS1 = 0
4418 11:05:53.517323 DQM Delay:
4419 11:05:53.517404 DQM0 = 40, DQM1 = 33
4420 11:05:53.517468 DQ Delay:
4421 11:05:53.520394 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4422 11:05:53.523781 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4423 11:05:53.526888 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4424 11:05:53.530774 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4425 11:05:53.530857
4426 11:05:53.530920
4427 11:05:53.540368 [DQSOSCAuto] RK1, (LSB)MR18= 0x472a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4428 11:05:53.543842 CH0 RK1: MR19=808, MR18=472A
4429 11:05:53.550427 CH0_RK1: MR19=0x808, MR18=0x472A, DQSOSC=396, MR23=63, INC=167, DEC=111
4430 11:05:53.550509 [RxdqsGatingPostProcess] freq 600
4431 11:05:53.556946 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4432 11:05:53.560326 Pre-setting of DQS Precalculation
4433 11:05:53.563855 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4434 11:05:53.567029 ==
4435 11:05:53.567111 Dram Type= 6, Freq= 0, CH_1, rank 0
4436 11:05:53.573682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 11:05:53.573765 ==
4438 11:05:53.577070 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4439 11:05:53.584061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4440 11:05:53.586942 [CA 0] Center 35 (5~65) winsize 61
4441 11:05:53.590810 [CA 1] Center 35 (5~66) winsize 62
4442 11:05:53.593795 [CA 2] Center 33 (3~64) winsize 62
4443 11:05:53.597594 [CA 3] Center 33 (3~64) winsize 62
4444 11:05:53.600638 [CA 4] Center 34 (3~65) winsize 63
4445 11:05:53.604015 [CA 5] Center 33 (3~64) winsize 62
4446 11:05:53.604098
4447 11:05:53.607772 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4448 11:05:53.607854
4449 11:05:53.611206 [CATrainingPosCal] consider 1 rank data
4450 11:05:53.613935 u2DelayCellTimex100 = 270/100 ps
4451 11:05:53.616957 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4452 11:05:53.623792 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4453 11:05:53.627411 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4454 11:05:53.630588 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4455 11:05:53.633722 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4456 11:05:53.637161 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4457 11:05:53.637247
4458 11:05:53.640379 CA PerBit enable=1, Macro0, CA PI delay=33
4459 11:05:53.640461
4460 11:05:53.643629 [CBTSetCACLKResult] CA Dly = 33
4461 11:05:53.643722 CS Dly: 5 (0~36)
4462 11:05:53.647193 ==
4463 11:05:53.647276 Dram Type= 6, Freq= 0, CH_1, rank 1
4464 11:05:53.653476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 11:05:53.653607 ==
4466 11:05:53.656953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4467 11:05:53.663458 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4468 11:05:53.667157 [CA 0] Center 35 (5~66) winsize 62
4469 11:05:53.670481 [CA 1] Center 35 (5~66) winsize 62
4470 11:05:53.674416 [CA 2] Center 34 (4~65) winsize 62
4471 11:05:53.677946 [CA 3] Center 34 (3~65) winsize 63
4472 11:05:53.680990 [CA 4] Center 34 (3~65) winsize 63
4473 11:05:53.684250 [CA 5] Center 33 (3~64) winsize 62
4474 11:05:53.684376
4475 11:05:53.687342 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4476 11:05:53.687468
4477 11:05:53.690718 [CATrainingPosCal] consider 2 rank data
4478 11:05:53.694260 u2DelayCellTimex100 = 270/100 ps
4479 11:05:53.697669 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4480 11:05:53.701007 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4481 11:05:53.707864 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4482 11:05:53.710632 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4483 11:05:53.714104 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4484 11:05:53.717489 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4485 11:05:53.717613
4486 11:05:53.720598 CA PerBit enable=1, Macro0, CA PI delay=33
4487 11:05:53.720726
4488 11:05:53.724513 [CBTSetCACLKResult] CA Dly = 33
4489 11:05:53.724639 CS Dly: 5 (0~36)
4490 11:05:53.724756
4491 11:05:53.727962 ----->DramcWriteLeveling(PI) begin...
4492 11:05:53.728097 ==
4493 11:05:53.730757 Dram Type= 6, Freq= 0, CH_1, rank 0
4494 11:05:53.737427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4495 11:05:53.737521 ==
4496 11:05:53.740683 Write leveling (Byte 0): 31 => 31
4497 11:05:53.744531 Write leveling (Byte 1): 31 => 31
4498 11:05:53.744633 DramcWriteLeveling(PI) end<-----
4499 11:05:53.747210
4500 11:05:53.747311 ==
4501 11:05:53.750992 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 11:05:53.753968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 11:05:53.754055 ==
4504 11:05:53.757264 [Gating] SW mode calibration
4505 11:05:53.763966 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4506 11:05:53.767568 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4507 11:05:53.773896 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4508 11:05:53.777096 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4509 11:05:53.780403 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4510 11:05:53.787446 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4511 11:05:53.790880 0 9 16 | B1->B0 | 2929 2727 | 0 0 | (0 0) (0 0)
4512 11:05:53.793949 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4513 11:05:53.800622 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4514 11:05:53.803814 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4515 11:05:53.807322 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4516 11:05:53.814113 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4517 11:05:53.817448 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4518 11:05:53.821124 0 10 12 | B1->B0 | 2525 2a2a | 1 1 | (0 0) (0 0)
4519 11:05:53.827366 0 10 16 | B1->B0 | 3e3e 4242 | 0 0 | (0 0) (0 0)
4520 11:05:53.830606 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 11:05:53.834416 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4522 11:05:53.840808 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 11:05:53.843681 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4524 11:05:53.847724 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4525 11:05:53.850587 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4526 11:05:53.857396 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4527 11:05:53.860816 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4528 11:05:53.863969 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 11:05:53.870364 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 11:05:53.873718 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 11:05:53.877471 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 11:05:53.883538 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 11:05:53.887466 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 11:05:53.890223 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 11:05:53.897271 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 11:05:53.900635 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 11:05:53.904429 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 11:05:53.910602 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 11:05:53.914172 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 11:05:53.917370 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 11:05:53.923612 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 11:05:53.927192 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 11:05:53.930671 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4544 11:05:53.933849 Total UI for P1: 0, mck2ui 16
4545 11:05:53.937276 best dqsien dly found for B0: ( 0, 13, 14)
4546 11:05:53.940670 Total UI for P1: 0, mck2ui 16
4547 11:05:53.943790 best dqsien dly found for B1: ( 0, 13, 14)
4548 11:05:53.947062 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4549 11:05:53.950819 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4550 11:05:53.950900
4551 11:05:53.953960 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4552 11:05:53.960716 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4553 11:05:53.960848 [Gating] SW calibration Done
4554 11:05:53.964063 ==
4555 11:05:53.964143 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 11:05:53.970309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 11:05:53.970465 ==
4558 11:05:53.970561 RX Vref Scan: 0
4559 11:05:53.970650
4560 11:05:53.974255 RX Vref 0 -> 0, step: 1
4561 11:05:53.974346
4562 11:05:53.977230 RX Delay -230 -> 252, step: 16
4563 11:05:53.981078 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4564 11:05:53.983775 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4565 11:05:53.990468 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4566 11:05:53.993676 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4567 11:05:53.996995 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4568 11:05:54.000555 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4569 11:05:54.003833 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4570 11:05:54.010654 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4571 11:05:54.013923 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4572 11:05:54.017310 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4573 11:05:54.020836 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4574 11:05:54.023869 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4575 11:05:54.030900 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4576 11:05:54.033744 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4577 11:05:54.037214 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4578 11:05:54.040509 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4579 11:05:54.040591 ==
4580 11:05:54.043908 Dram Type= 6, Freq= 0, CH_1, rank 0
4581 11:05:54.050622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 11:05:54.050706 ==
4583 11:05:54.050770 DQS Delay:
4584 11:05:54.054195 DQS0 = 0, DQS1 = 0
4585 11:05:54.054311 DQM Delay:
4586 11:05:54.054412 DQM0 = 43, DQM1 = 35
4587 11:05:54.057161 DQ Delay:
4588 11:05:54.060622 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4589 11:05:54.063897 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41
4590 11:05:54.067651 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =33
4591 11:05:54.071217 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4592 11:05:54.071300
4593 11:05:54.071365
4594 11:05:54.071425 ==
4595 11:05:54.074003 Dram Type= 6, Freq= 0, CH_1, rank 0
4596 11:05:54.077228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 11:05:54.077306 ==
4598 11:05:54.077370
4599 11:05:54.077429
4600 11:05:54.080773 TX Vref Scan disable
4601 11:05:54.080866 == TX Byte 0 ==
4602 11:05:54.087809 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4603 11:05:54.090834 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4604 11:05:54.090970 == TX Byte 1 ==
4605 11:05:54.097338 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4606 11:05:54.101001 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4607 11:05:54.101122 ==
4608 11:05:54.104313 Dram Type= 6, Freq= 0, CH_1, rank 0
4609 11:05:54.107434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 11:05:54.107559 ==
4611 11:05:54.107665
4612 11:05:54.110842
4613 11:05:54.110948 TX Vref Scan disable
4614 11:05:54.114021 == TX Byte 0 ==
4615 11:05:54.117702 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4616 11:05:54.124239 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4617 11:05:54.124362 == TX Byte 1 ==
4618 11:05:54.127470 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4619 11:05:54.130629 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4620 11:05:54.134149
4621 11:05:54.134267 [DATLAT]
4622 11:05:54.134361 Freq=600, CH1 RK0
4623 11:05:54.134491
4624 11:05:54.137413 DATLAT Default: 0x9
4625 11:05:54.137537 0, 0xFFFF, sum = 0
4626 11:05:54.140839 1, 0xFFFF, sum = 0
4627 11:05:54.140977 2, 0xFFFF, sum = 0
4628 11:05:54.144399 3, 0xFFFF, sum = 0
4629 11:05:54.144517 4, 0xFFFF, sum = 0
4630 11:05:54.147403 5, 0xFFFF, sum = 0
4631 11:05:54.147515 6, 0xFFFF, sum = 0
4632 11:05:54.150815 7, 0xFFFF, sum = 0
4633 11:05:54.150964 8, 0x0, sum = 1
4634 11:05:54.154538 9, 0x0, sum = 2
4635 11:05:54.154619 10, 0x0, sum = 3
4636 11:05:54.157687 11, 0x0, sum = 4
4637 11:05:54.157769 best_step = 9
4638 11:05:54.157874
4639 11:05:54.157967 ==
4640 11:05:54.161062 Dram Type= 6, Freq= 0, CH_1, rank 0
4641 11:05:54.167723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 11:05:54.167802 ==
4643 11:05:54.167866 RX Vref Scan: 1
4644 11:05:54.167925
4645 11:05:54.170969 RX Vref 0 -> 0, step: 1
4646 11:05:54.171039
4647 11:05:54.174606 RX Delay -195 -> 252, step: 8
4648 11:05:54.174678
4649 11:05:54.177788 Set Vref, RX VrefLevel [Byte0]: 57
4650 11:05:54.180993 [Byte1]: 49
4651 11:05:54.181062
4652 11:05:54.184258 Final RX Vref Byte 0 = 57 to rank0
4653 11:05:54.187441 Final RX Vref Byte 1 = 49 to rank0
4654 11:05:54.191399 Final RX Vref Byte 0 = 57 to rank1
4655 11:05:54.194540 Final RX Vref Byte 1 = 49 to rank1==
4656 11:05:54.197513 Dram Type= 6, Freq= 0, CH_1, rank 0
4657 11:05:54.201014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 11:05:54.201085 ==
4659 11:05:54.204692 DQS Delay:
4660 11:05:54.204800 DQS0 = 0, DQS1 = 0
4661 11:05:54.204894 DQM Delay:
4662 11:05:54.207746 DQM0 = 40, DQM1 = 33
4663 11:05:54.207827 DQ Delay:
4664 11:05:54.210764 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4665 11:05:54.213979 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4666 11:05:54.217638 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4667 11:05:54.220778 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4668 11:05:54.220864
4669 11:05:54.220933
4670 11:05:54.230611 [DQSOSCAuto] RK0, (LSB)MR18= 0x4107, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4671 11:05:54.230748 CH1 RK0: MR19=808, MR18=4107
4672 11:05:54.238023 CH1_RK0: MR19=0x808, MR18=0x4107, DQSOSC=397, MR23=63, INC=166, DEC=110
4673 11:05:54.238132
4674 11:05:54.240912 ----->DramcWriteLeveling(PI) begin...
4675 11:05:54.244170 ==
4676 11:05:54.244251 Dram Type= 6, Freq= 0, CH_1, rank 1
4677 11:05:54.251448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4678 11:05:54.251571 ==
4679 11:05:54.254084 Write leveling (Byte 0): 31 => 31
4680 11:05:54.257691 Write leveling (Byte 1): 31 => 31
4681 11:05:54.261066 DramcWriteLeveling(PI) end<-----
4682 11:05:54.261167
4683 11:05:54.261257 ==
4684 11:05:54.264216 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 11:05:54.267938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 11:05:54.268020 ==
4687 11:05:54.271091 [Gating] SW mode calibration
4688 11:05:54.278075 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4689 11:05:54.280948 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4690 11:05:54.288010 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4691 11:05:54.290454 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4692 11:05:54.294052 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4693 11:05:54.300659 0 9 12 | B1->B0 | 3030 2d2d | 1 0 | (1 1) (0 0)
4694 11:05:54.303989 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4695 11:05:54.307403 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4696 11:05:54.314181 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4697 11:05:54.317513 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4698 11:05:54.320913 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4699 11:05:54.327580 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4700 11:05:54.331281 0 10 8 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
4701 11:05:54.334029 0 10 12 | B1->B0 | 2b2b 3c3c | 1 0 | (0 0) (0 0)
4702 11:05:54.341055 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4703 11:05:54.344457 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4704 11:05:54.347308 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4705 11:05:54.354134 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4706 11:05:54.357418 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4707 11:05:54.360507 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 11:05:54.364155 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4709 11:05:54.370708 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 11:05:54.374694 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4711 11:05:54.377708 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 11:05:54.383930 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 11:05:54.387483 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 11:05:54.391011 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 11:05:54.397142 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 11:05:54.400597 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 11:05:54.404422 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 11:05:54.411433 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 11:05:54.414156 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 11:05:54.417698 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 11:05:54.424493 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 11:05:54.427550 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 11:05:54.430932 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 11:05:54.437898 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4725 11:05:54.440804 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4726 11:05:54.443828 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4727 11:05:54.447232 Total UI for P1: 0, mck2ui 16
4728 11:05:54.451289 best dqsien dly found for B0: ( 0, 13, 10)
4729 11:05:54.454410 Total UI for P1: 0, mck2ui 16
4730 11:05:54.457340 best dqsien dly found for B1: ( 0, 13, 14)
4731 11:05:54.461185 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4732 11:05:54.464469 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4733 11:05:54.464553
4734 11:05:54.467401 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4735 11:05:54.474034 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4736 11:05:54.474117 [Gating] SW calibration Done
4737 11:05:54.474184 ==
4738 11:05:54.477667 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 11:05:54.484256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 11:05:54.484337 ==
4741 11:05:54.484402 RX Vref Scan: 0
4742 11:05:54.484463
4743 11:05:54.487696 RX Vref 0 -> 0, step: 1
4744 11:05:54.487771
4745 11:05:54.490574 RX Delay -230 -> 252, step: 16
4746 11:05:54.493691 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4747 11:05:54.497132 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4748 11:05:54.503566 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4749 11:05:54.506903 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4750 11:05:54.510256 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4751 11:05:54.513452 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4752 11:05:54.516946 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4753 11:05:54.523494 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4754 11:05:54.526874 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4755 11:05:54.530149 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4756 11:05:54.533628 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4757 11:05:54.539928 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4758 11:05:54.543495 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4759 11:05:54.546806 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4760 11:05:54.550269 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4761 11:05:54.556888 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4762 11:05:54.556995 ==
4763 11:05:54.560395 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 11:05:54.563416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 11:05:54.563520 ==
4766 11:05:54.563616 DQS Delay:
4767 11:05:54.566648 DQS0 = 0, DQS1 = 0
4768 11:05:54.566751 DQM Delay:
4769 11:05:54.569944 DQM0 = 41, DQM1 = 36
4770 11:05:54.570050 DQ Delay:
4771 11:05:54.573188 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4772 11:05:54.576513 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4773 11:05:54.580172 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4774 11:05:54.583514 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4775 11:05:54.583616
4776 11:05:54.583713
4777 11:05:54.583804 ==
4778 11:05:54.586585 Dram Type= 6, Freq= 0, CH_1, rank 1
4779 11:05:54.589910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4780 11:05:54.590015 ==
4781 11:05:54.590111
4782 11:05:54.593148
4783 11:05:54.593252 TX Vref Scan disable
4784 11:05:54.596662 == TX Byte 0 ==
4785 11:05:54.600007 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4786 11:05:54.603037 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4787 11:05:54.606232 == TX Byte 1 ==
4788 11:05:54.609784 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4789 11:05:54.613176 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4790 11:05:54.613280 ==
4791 11:05:54.616148 Dram Type= 6, Freq= 0, CH_1, rank 1
4792 11:05:54.622932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4793 11:05:54.623040 ==
4794 11:05:54.623138
4795 11:05:54.623228
4796 11:05:54.623316 TX Vref Scan disable
4797 11:05:54.627916 == TX Byte 0 ==
4798 11:05:54.630920 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4799 11:05:54.637564 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4800 11:05:54.637652 == TX Byte 1 ==
4801 11:05:54.641083 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4802 11:05:54.644007 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4803 11:05:54.647472
4804 11:05:54.647549 [DATLAT]
4805 11:05:54.647616 Freq=600, CH1 RK1
4806 11:05:54.647678
4807 11:05:54.650829 DATLAT Default: 0x9
4808 11:05:54.650921 0, 0xFFFF, sum = 0
4809 11:05:54.654648 1, 0xFFFF, sum = 0
4810 11:05:54.654730 2, 0xFFFF, sum = 0
4811 11:05:54.657823 3, 0xFFFF, sum = 0
4812 11:05:54.657899 4, 0xFFFF, sum = 0
4813 11:05:54.660971 5, 0xFFFF, sum = 0
4814 11:05:54.664502 6, 0xFFFF, sum = 0
4815 11:05:54.664576 7, 0xFFFF, sum = 0
4816 11:05:54.664642 8, 0x0, sum = 1
4817 11:05:54.667670 9, 0x0, sum = 2
4818 11:05:54.667743 10, 0x0, sum = 3
4819 11:05:54.671000 11, 0x0, sum = 4
4820 11:05:54.671095 best_step = 9
4821 11:05:54.671159
4822 11:05:54.671217 ==
4823 11:05:54.674152 Dram Type= 6, Freq= 0, CH_1, rank 1
4824 11:05:54.680750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4825 11:05:54.680852 ==
4826 11:05:54.680944 RX Vref Scan: 0
4827 11:05:54.681032
4828 11:05:54.684045 RX Vref 0 -> 0, step: 1
4829 11:05:54.684120
4830 11:05:54.687400 RX Delay -179 -> 252, step: 8
4831 11:05:54.691001 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4832 11:05:54.697719 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4833 11:05:54.700697 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4834 11:05:54.703849 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4835 11:05:54.707302 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4836 11:05:54.710652 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4837 11:05:54.717413 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4838 11:05:54.720724 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4839 11:05:54.723867 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4840 11:05:54.727722 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4841 11:05:54.733876 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4842 11:05:54.737846 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4843 11:05:54.740689 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4844 11:05:54.744024 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4845 11:05:54.750866 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4846 11:05:54.753989 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4847 11:05:54.754075 ==
4848 11:05:54.757041 Dram Type= 6, Freq= 0, CH_1, rank 1
4849 11:05:54.760871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4850 11:05:54.760949 ==
4851 11:05:54.761012 DQS Delay:
4852 11:05:54.764386 DQS0 = 0, DQS1 = 0
4853 11:05:54.764466 DQM Delay:
4854 11:05:54.767205 DQM0 = 39, DQM1 = 33
4855 11:05:54.767279 DQ Delay:
4856 11:05:54.771101 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4857 11:05:54.774321 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4858 11:05:54.777125 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4859 11:05:54.780507 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4860 11:05:54.780585
4861 11:05:54.780647
4862 11:05:54.790775 [DQSOSCAuto] RK1, (LSB)MR18= 0x3746, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4863 11:05:54.790867 CH1 RK1: MR19=808, MR18=3746
4864 11:05:54.797220 CH1_RK1: MR19=0x808, MR18=0x3746, DQSOSC=396, MR23=63, INC=167, DEC=111
4865 11:05:54.801039 [RxdqsGatingPostProcess] freq 600
4866 11:05:54.807591 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4867 11:05:54.811143 Pre-setting of DQS Precalculation
4868 11:05:54.814212 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4869 11:05:54.821055 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4870 11:05:54.827311 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4871 11:05:54.827395
4872 11:05:54.830928
4873 11:05:54.831010 [Calibration Summary] 1200 Mbps
4874 11:05:54.834287 CH 0, Rank 0
4875 11:05:54.834377 SW Impedance : PASS
4876 11:05:54.837201 DUTY Scan : NO K
4877 11:05:54.840494 ZQ Calibration : PASS
4878 11:05:54.840577 Jitter Meter : NO K
4879 11:05:54.843920 CBT Training : PASS
4880 11:05:54.847507 Write leveling : PASS
4881 11:05:54.847589 RX DQS gating : PASS
4882 11:05:54.850562 RX DQ/DQS(RDDQC) : PASS
4883 11:05:54.854026 TX DQ/DQS : PASS
4884 11:05:54.854111 RX DATLAT : PASS
4885 11:05:54.857647 RX DQ/DQS(Engine): PASS
4886 11:05:54.857758 TX OE : NO K
4887 11:05:54.860944 All Pass.
4888 11:05:54.861022
4889 11:05:54.861084 CH 0, Rank 1
4890 11:05:54.864154 SW Impedance : PASS
4891 11:05:54.864229 DUTY Scan : NO K
4892 11:05:54.867280 ZQ Calibration : PASS
4893 11:05:54.870675 Jitter Meter : NO K
4894 11:05:54.870755 CBT Training : PASS
4895 11:05:54.873726 Write leveling : PASS
4896 11:05:54.877585 RX DQS gating : PASS
4897 11:05:54.877664 RX DQ/DQS(RDDQC) : PASS
4898 11:05:54.880801 TX DQ/DQS : PASS
4899 11:05:54.884306 RX DATLAT : PASS
4900 11:05:54.884385 RX DQ/DQS(Engine): PASS
4901 11:05:54.887451 TX OE : NO K
4902 11:05:54.887527 All Pass.
4903 11:05:54.887589
4904 11:05:54.890928 CH 1, Rank 0
4905 11:05:54.891002 SW Impedance : PASS
4906 11:05:54.894008 DUTY Scan : NO K
4907 11:05:54.897640 ZQ Calibration : PASS
4908 11:05:54.897741 Jitter Meter : NO K
4909 11:05:54.900857 CBT Training : PASS
4910 11:05:54.900940 Write leveling : PASS
4911 11:05:54.904240 RX DQS gating : PASS
4912 11:05:54.907554 RX DQ/DQS(RDDQC) : PASS
4913 11:05:54.907630 TX DQ/DQS : PASS
4914 11:05:54.911069 RX DATLAT : PASS
4915 11:05:54.914002 RX DQ/DQS(Engine): PASS
4916 11:05:54.914110 TX OE : NO K
4917 11:05:54.917864 All Pass.
4918 11:05:54.917946
4919 11:05:54.918010 CH 1, Rank 1
4920 11:05:54.920598 SW Impedance : PASS
4921 11:05:54.920670 DUTY Scan : NO K
4922 11:05:54.924237 ZQ Calibration : PASS
4923 11:05:54.927294 Jitter Meter : NO K
4924 11:05:54.927369 CBT Training : PASS
4925 11:05:54.930616 Write leveling : PASS
4926 11:05:54.934131 RX DQS gating : PASS
4927 11:05:54.934233 RX DQ/DQS(RDDQC) : PASS
4928 11:05:54.937178 TX DQ/DQS : PASS
4929 11:05:54.940938 RX DATLAT : PASS
4930 11:05:54.941015 RX DQ/DQS(Engine): PASS
4931 11:05:54.943917 TX OE : NO K
4932 11:05:54.943996 All Pass.
4933 11:05:54.944056
4934 11:05:54.947332 DramC Write-DBI off
4935 11:05:54.950336 PER_BANK_REFRESH: Hybrid Mode
4936 11:05:54.950443 TX_TRACKING: ON
4937 11:05:54.960327 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4938 11:05:54.963897 [FAST_K] Save calibration result to emmc
4939 11:05:54.967253 dramc_set_vcore_voltage set vcore to 662500
4940 11:05:54.970442 Read voltage for 933, 3
4941 11:05:54.970520 Vio18 = 0
4942 11:05:54.970582 Vcore = 662500
4943 11:05:54.973490 Vdram = 0
4944 11:05:54.973560 Vddq = 0
4945 11:05:54.973619 Vmddr = 0
4946 11:05:54.980153 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4947 11:05:54.983628 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4948 11:05:54.986957 MEM_TYPE=3, freq_sel=17
4949 11:05:54.990077 sv_algorithm_assistance_LP4_1600
4950 11:05:54.993487 ============ PULL DRAM RESETB DOWN ============
4951 11:05:54.997515 ========== PULL DRAM RESETB DOWN end =========
4952 11:05:55.004091 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4953 11:05:55.006925 ===================================
4954 11:05:55.007008 LPDDR4 DRAM CONFIGURATION
4955 11:05:55.010931 ===================================
4956 11:05:55.013789 EX_ROW_EN[0] = 0x0
4957 11:05:55.017093 EX_ROW_EN[1] = 0x0
4958 11:05:55.017167 LP4Y_EN = 0x0
4959 11:05:55.020439 WORK_FSP = 0x0
4960 11:05:55.020510 WL = 0x3
4961 11:05:55.023707 RL = 0x3
4962 11:05:55.023778 BL = 0x2
4963 11:05:55.027043 RPST = 0x0
4964 11:05:55.027120 RD_PRE = 0x0
4965 11:05:55.030365 WR_PRE = 0x1
4966 11:05:55.030473 WR_PST = 0x0
4967 11:05:55.034277 DBI_WR = 0x0
4968 11:05:55.034376 DBI_RD = 0x0
4969 11:05:55.037505 OTF = 0x1
4970 11:05:55.040482 ===================================
4971 11:05:55.044119 ===================================
4972 11:05:55.044190 ANA top config
4973 11:05:55.047424 ===================================
4974 11:05:55.051103 DLL_ASYNC_EN = 0
4975 11:05:55.053596 ALL_SLAVE_EN = 1
4976 11:05:55.053667 NEW_RANK_MODE = 1
4977 11:05:55.057164 DLL_IDLE_MODE = 1
4978 11:05:55.060580 LP45_APHY_COMB_EN = 1
4979 11:05:55.063945 TX_ODT_DIS = 1
4980 11:05:55.067040 NEW_8X_MODE = 1
4981 11:05:55.070390 ===================================
4982 11:05:55.073697 ===================================
4983 11:05:55.073771 data_rate = 1866
4984 11:05:55.077058 CKR = 1
4985 11:05:55.080573 DQ_P2S_RATIO = 8
4986 11:05:55.084218 ===================================
4987 11:05:55.086866 CA_P2S_RATIO = 8
4988 11:05:55.090138 DQ_CA_OPEN = 0
4989 11:05:55.093538 DQ_SEMI_OPEN = 0
4990 11:05:55.093636 CA_SEMI_OPEN = 0
4991 11:05:55.096890 CA_FULL_RATE = 0
4992 11:05:55.100442 DQ_CKDIV4_EN = 1
4993 11:05:55.103475 CA_CKDIV4_EN = 1
4994 11:05:55.107200 CA_PREDIV_EN = 0
4995 11:05:55.110347 PH8_DLY = 0
4996 11:05:55.110453 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4997 11:05:55.113764 DQ_AAMCK_DIV = 4
4998 11:05:55.116649 CA_AAMCK_DIV = 4
4999 11:05:55.120538 CA_ADMCK_DIV = 4
5000 11:05:55.123518 DQ_TRACK_CA_EN = 0
5001 11:05:55.127213 CA_PICK = 933
5002 11:05:55.127294 CA_MCKIO = 933
5003 11:05:55.130585 MCKIO_SEMI = 0
5004 11:05:55.133946 PLL_FREQ = 3732
5005 11:05:55.137238 DQ_UI_PI_RATIO = 32
5006 11:05:55.140110 CA_UI_PI_RATIO = 0
5007 11:05:55.143433 ===================================
5008 11:05:55.146887 ===================================
5009 11:05:55.150805 memory_type:LPDDR4
5010 11:05:55.150911 GP_NUM : 10
5011 11:05:55.153574 SRAM_EN : 1
5012 11:05:55.153683 MD32_EN : 0
5013 11:05:55.157633 ===================================
5014 11:05:55.160622 [ANA_INIT] >>>>>>>>>>>>>>
5015 11:05:55.163773 <<<<<< [CONFIGURE PHASE]: ANA_TX
5016 11:05:55.167121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5017 11:05:55.171167 ===================================
5018 11:05:55.173944 data_rate = 1866,PCW = 0X8f00
5019 11:05:55.177140 ===================================
5020 11:05:55.180524 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5021 11:05:55.183912 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5022 11:05:55.190335 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5023 11:05:55.194153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5024 11:05:55.196871 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5025 11:05:55.200683 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5026 11:05:55.203586 [ANA_INIT] flow start
5027 11:05:55.207920 [ANA_INIT] PLL >>>>>>>>
5028 11:05:55.208026 [ANA_INIT] PLL <<<<<<<<
5029 11:05:55.210856 [ANA_INIT] MIDPI >>>>>>>>
5030 11:05:55.214183 [ANA_INIT] MIDPI <<<<<<<<
5031 11:05:55.217177 [ANA_INIT] DLL >>>>>>>>
5032 11:05:55.217331 [ANA_INIT] flow end
5033 11:05:55.220809 ============ LP4 DIFF to SE enter ============
5034 11:05:55.227155 ============ LP4 DIFF to SE exit ============
5035 11:05:55.227264 [ANA_INIT] <<<<<<<<<<<<<
5036 11:05:55.230462 [Flow] Enable top DCM control >>>>>
5037 11:05:55.234098 [Flow] Enable top DCM control <<<<<
5038 11:05:55.237277 Enable DLL master slave shuffle
5039 11:05:55.243859 ==============================================================
5040 11:05:55.244017 Gating Mode config
5041 11:05:55.251220 ==============================================================
5042 11:05:55.254359 Config description:
5043 11:05:55.260882 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5044 11:05:55.267769 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5045 11:05:55.273910 SELPH_MODE 0: By rank 1: By Phase
5046 11:05:55.277447 ==============================================================
5047 11:05:55.280650 GAT_TRACK_EN = 1
5048 11:05:55.283810 RX_GATING_MODE = 2
5049 11:05:55.287314 RX_GATING_TRACK_MODE = 2
5050 11:05:55.290583 SELPH_MODE = 1
5051 11:05:55.294105 PICG_EARLY_EN = 1
5052 11:05:55.297094 VALID_LAT_VALUE = 1
5053 11:05:55.304116 ==============================================================
5054 11:05:55.307230 Enter into Gating configuration >>>>
5055 11:05:55.310566 Exit from Gating configuration <<<<
5056 11:05:55.314071 Enter into DVFS_PRE_config >>>>>
5057 11:05:55.324232 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5058 11:05:55.327385 Exit from DVFS_PRE_config <<<<<
5059 11:05:55.330738 Enter into PICG configuration >>>>
5060 11:05:55.334304 Exit from PICG configuration <<<<
5061 11:05:55.334376 [RX_INPUT] configuration >>>>>
5062 11:05:55.337327 [RX_INPUT] configuration <<<<<
5063 11:05:55.344206 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5064 11:05:55.347236 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5065 11:05:55.354036 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5066 11:05:55.360890 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5067 11:05:55.367326 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5068 11:05:55.373789 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5069 11:05:55.377397 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5070 11:05:55.380548 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5071 11:05:55.386994 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5072 11:05:55.390646 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5073 11:05:55.394186 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5074 11:05:55.397053 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5075 11:05:55.400291 ===================================
5076 11:05:55.404009 LPDDR4 DRAM CONFIGURATION
5077 11:05:55.407410 ===================================
5078 11:05:55.410279 EX_ROW_EN[0] = 0x0
5079 11:05:55.410351 EX_ROW_EN[1] = 0x0
5080 11:05:55.413967 LP4Y_EN = 0x0
5081 11:05:55.414080 WORK_FSP = 0x0
5082 11:05:55.417181 WL = 0x3
5083 11:05:55.417254 RL = 0x3
5084 11:05:55.420401 BL = 0x2
5085 11:05:55.420473 RPST = 0x0
5086 11:05:55.424191 RD_PRE = 0x0
5087 11:05:55.424311 WR_PRE = 0x1
5088 11:05:55.427347 WR_PST = 0x0
5089 11:05:55.427472 DBI_WR = 0x0
5090 11:05:55.430617 DBI_RD = 0x0
5091 11:05:55.433699 OTF = 0x1
5092 11:05:55.436702 ===================================
5093 11:05:55.440706 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5094 11:05:55.443858 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5095 11:05:55.447003 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5096 11:05:55.450581 ===================================
5097 11:05:55.453454 LPDDR4 DRAM CONFIGURATION
5098 11:05:55.457049 ===================================
5099 11:05:55.460282 EX_ROW_EN[0] = 0x10
5100 11:05:55.460407 EX_ROW_EN[1] = 0x0
5101 11:05:55.463313 LP4Y_EN = 0x0
5102 11:05:55.463385 WORK_FSP = 0x0
5103 11:05:55.466751 WL = 0x3
5104 11:05:55.466830 RL = 0x3
5105 11:05:55.470036 BL = 0x2
5106 11:05:55.470102 RPST = 0x0
5107 11:05:55.473798 RD_PRE = 0x0
5108 11:05:55.473868 WR_PRE = 0x1
5109 11:05:55.476779 WR_PST = 0x0
5110 11:05:55.476859 DBI_WR = 0x0
5111 11:05:55.480608 DBI_RD = 0x0
5112 11:05:55.480689 OTF = 0x1
5113 11:05:55.483901 ===================================
5114 11:05:55.490201 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5115 11:05:55.494827 nWR fixed to 30
5116 11:05:55.498743 [ModeRegInit_LP4] CH0 RK0
5117 11:05:55.498828 [ModeRegInit_LP4] CH0 RK1
5118 11:05:55.501836 [ModeRegInit_LP4] CH1 RK0
5119 11:05:55.505197 [ModeRegInit_LP4] CH1 RK1
5120 11:05:55.505307 match AC timing 9
5121 11:05:55.511917 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5122 11:05:55.515082 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5123 11:05:55.518463 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5124 11:05:55.524920 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5125 11:05:55.528154 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5126 11:05:55.528234 ==
5127 11:05:55.531493 Dram Type= 6, Freq= 0, CH_0, rank 0
5128 11:05:55.534883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5129 11:05:55.534961 ==
5130 11:05:55.541717 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5131 11:05:55.549106 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5132 11:05:55.551495 [CA 0] Center 38 (8~69) winsize 62
5133 11:05:55.554754 [CA 1] Center 38 (8~69) winsize 62
5134 11:05:55.558137 [CA 2] Center 35 (5~66) winsize 62
5135 11:05:55.561722 [CA 3] Center 35 (4~66) winsize 63
5136 11:05:55.565099 [CA 4] Center 34 (4~64) winsize 61
5137 11:05:55.568357 [CA 5] Center 34 (4~64) winsize 61
5138 11:05:55.568461
5139 11:05:55.571736 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5140 11:05:55.571848
5141 11:05:55.575479 [CATrainingPosCal] consider 1 rank data
5142 11:05:55.578274 u2DelayCellTimex100 = 270/100 ps
5143 11:05:55.582096 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5144 11:05:55.585131 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5145 11:05:55.588496 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5146 11:05:55.591794 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5147 11:05:55.595047 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5148 11:05:55.598566 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5149 11:05:55.598640
5150 11:05:55.602089 CA PerBit enable=1, Macro0, CA PI delay=34
5151 11:05:55.602204
5152 11:05:55.605616 [CBTSetCACLKResult] CA Dly = 34
5153 11:05:55.608340 CS Dly: 6 (0~37)
5154 11:05:55.608447 ==
5155 11:05:55.612379 Dram Type= 6, Freq= 0, CH_0, rank 1
5156 11:05:55.615631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5157 11:05:55.615708 ==
5158 11:05:55.621938 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5159 11:05:55.628882 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5160 11:05:55.631816 [CA 0] Center 38 (7~69) winsize 63
5161 11:05:55.635465 [CA 1] Center 38 (7~69) winsize 63
5162 11:05:55.639211 [CA 2] Center 35 (5~66) winsize 62
5163 11:05:55.641918 [CA 3] Center 35 (5~66) winsize 62
5164 11:05:55.645308 [CA 4] Center 34 (3~65) winsize 63
5165 11:05:55.648484 [CA 5] Center 33 (3~64) winsize 62
5166 11:05:55.648590
5167 11:05:55.651618 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5168 11:05:55.651702
5169 11:05:55.655137 [CATrainingPosCal] consider 2 rank data
5170 11:05:55.658102 u2DelayCellTimex100 = 270/100 ps
5171 11:05:55.661758 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5172 11:05:55.665264 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5173 11:05:55.668201 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5174 11:05:55.671928 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5175 11:05:55.675046 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5176 11:05:55.678644 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5177 11:05:55.678749
5178 11:05:55.681855 CA PerBit enable=1, Macro0, CA PI delay=34
5179 11:05:55.685025
5180 11:05:55.685125 [CBTSetCACLKResult] CA Dly = 34
5181 11:05:55.688089 CS Dly: 7 (0~39)
5182 11:05:55.688194
5183 11:05:55.691535 ----->DramcWriteLeveling(PI) begin...
5184 11:05:55.691639 ==
5185 11:05:55.694617 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 11:05:55.698364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 11:05:55.698477 ==
5188 11:05:55.701999 Write leveling (Byte 0): 33 => 33
5189 11:05:55.705071 Write leveling (Byte 1): 26 => 26
5190 11:05:55.708373 DramcWriteLeveling(PI) end<-----
5191 11:05:55.708475
5192 11:05:55.708567 ==
5193 11:05:55.711860 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 11:05:55.714926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 11:05:55.718339 ==
5196 11:05:55.718454 [Gating] SW mode calibration
5197 11:05:55.725073 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5198 11:05:55.731544 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5199 11:05:55.734425 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
5200 11:05:55.741140 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5201 11:05:55.744776 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5202 11:05:55.748098 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5203 11:05:55.754445 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5204 11:05:55.757866 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5205 11:05:55.761032 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5206 11:05:55.767684 0 14 28 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5207 11:05:55.771567 0 15 0 | B1->B0 | 3434 2e2e | 0 1 | (0 0) (1 0)
5208 11:05:55.774467 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5209 11:05:55.781244 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5210 11:05:55.784749 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5211 11:05:55.788025 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5212 11:05:55.791433 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5213 11:05:55.798161 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5214 11:05:55.801377 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5215 11:05:55.804759 1 0 0 | B1->B0 | 3535 4241 | 0 1 | (1 1) (0 0)
5216 11:05:55.811696 1 0 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5217 11:05:55.815076 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 11:05:55.817744 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5219 11:05:55.825344 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5220 11:05:55.827916 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5221 11:05:55.831094 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5222 11:05:55.837816 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 11:05:55.841850 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5224 11:05:55.844421 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 11:05:55.851265 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 11:05:55.854279 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 11:05:55.858175 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 11:05:55.864853 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 11:05:55.867970 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 11:05:55.871515 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 11:05:55.878296 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 11:05:55.881423 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 11:05:55.884580 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 11:05:55.887801 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 11:05:55.894929 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 11:05:55.898158 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 11:05:55.901435 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5238 11:05:55.908115 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5239 11:05:55.911290 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5240 11:05:55.914918 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5241 11:05:55.918242 Total UI for P1: 0, mck2ui 16
5242 11:05:55.921511 best dqsien dly found for B0: ( 1, 2, 28)
5243 11:05:55.924817 Total UI for P1: 0, mck2ui 16
5244 11:05:55.928374 best dqsien dly found for B1: ( 1, 2, 28)
5245 11:05:55.931770 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5246 11:05:55.934888 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5247 11:05:55.935007
5248 11:05:55.941636 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5249 11:05:55.944421 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5250 11:05:55.947656 [Gating] SW calibration Done
5251 11:05:55.947757 ==
5252 11:05:55.951144 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 11:05:55.954516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 11:05:55.954592 ==
5255 11:05:55.954654 RX Vref Scan: 0
5256 11:05:55.954713
5257 11:05:55.958302 RX Vref 0 -> 0, step: 1
5258 11:05:55.958384
5259 11:05:55.960907 RX Delay -80 -> 252, step: 8
5260 11:05:55.964393 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5261 11:05:55.967634 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5262 11:05:55.971484 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5263 11:05:55.978101 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5264 11:05:55.981227 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5265 11:05:55.984297 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5266 11:05:55.987753 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5267 11:05:55.991475 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5268 11:05:55.994602 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5269 11:05:56.001245 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5270 11:05:56.004621 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5271 11:05:56.007826 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5272 11:05:56.010931 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5273 11:05:56.014523 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5274 11:05:56.020976 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5275 11:05:56.024273 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5276 11:05:56.024361 ==
5277 11:05:56.027729 Dram Type= 6, Freq= 0, CH_0, rank 0
5278 11:05:56.030972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 11:05:56.031076 ==
5280 11:05:56.031149 DQS Delay:
5281 11:05:56.034724 DQS0 = 0, DQS1 = 0
5282 11:05:56.034811 DQM Delay:
5283 11:05:56.037810 DQM0 = 97, DQM1 = 88
5284 11:05:56.037914 DQ Delay:
5285 11:05:56.041147 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5286 11:05:56.044260 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5287 11:05:56.047648 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5288 11:05:56.051058 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5289 11:05:56.051163
5290 11:05:56.051261
5291 11:05:56.051351 ==
5292 11:05:56.054588 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 11:05:56.058101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 11:05:56.058203 ==
5295 11:05:56.061097
5296 11:05:56.061199
5297 11:05:56.061290 TX Vref Scan disable
5298 11:05:56.064501 == TX Byte 0 ==
5299 11:05:56.067780 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5300 11:05:56.071048 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5301 11:05:56.074609 == TX Byte 1 ==
5302 11:05:56.077859 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5303 11:05:56.081128 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5304 11:05:56.081235 ==
5305 11:05:56.084479 Dram Type= 6, Freq= 0, CH_0, rank 0
5306 11:05:56.091317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 11:05:56.091428 ==
5308 11:05:56.091522
5309 11:05:56.091613
5310 11:05:56.091705 TX Vref Scan disable
5311 11:05:56.095532 == TX Byte 0 ==
5312 11:05:56.099278 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5313 11:05:56.105537 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5314 11:05:56.105644 == TX Byte 1 ==
5315 11:05:56.108890 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5316 11:05:56.112091 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5317 11:05:56.115443
5318 11:05:56.115550 [DATLAT]
5319 11:05:56.115647 Freq=933, CH0 RK0
5320 11:05:56.115736
5321 11:05:56.118623 DATLAT Default: 0xd
5322 11:05:56.118707 0, 0xFFFF, sum = 0
5323 11:05:56.122133 1, 0xFFFF, sum = 0
5324 11:05:56.122209 2, 0xFFFF, sum = 0
5325 11:05:56.125280 3, 0xFFFF, sum = 0
5326 11:05:56.125360 4, 0xFFFF, sum = 0
5327 11:05:56.129362 5, 0xFFFF, sum = 0
5328 11:05:56.129438 6, 0xFFFF, sum = 0
5329 11:05:56.132362 7, 0xFFFF, sum = 0
5330 11:05:56.135736 8, 0xFFFF, sum = 0
5331 11:05:56.135811 9, 0xFFFF, sum = 0
5332 11:05:56.139077 10, 0x0, sum = 1
5333 11:05:56.139152 11, 0x0, sum = 2
5334 11:05:56.139221 12, 0x0, sum = 3
5335 11:05:56.142456 13, 0x0, sum = 4
5336 11:05:56.142533 best_step = 11
5337 11:05:56.142596
5338 11:05:56.142655 ==
5339 11:05:56.145623 Dram Type= 6, Freq= 0, CH_0, rank 0
5340 11:05:56.152744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 11:05:56.152824 ==
5342 11:05:56.152887 RX Vref Scan: 1
5343 11:05:56.152947
5344 11:05:56.155546 RX Vref 0 -> 0, step: 1
5345 11:05:56.155628
5346 11:05:56.158755 RX Delay -61 -> 252, step: 4
5347 11:05:56.158843
5348 11:05:56.162125 Set Vref, RX VrefLevel [Byte0]: 52
5349 11:05:56.165842 [Byte1]: 50
5350 11:05:56.165928
5351 11:05:56.169055 Final RX Vref Byte 0 = 52 to rank0
5352 11:05:56.172160 Final RX Vref Byte 1 = 50 to rank0
5353 11:05:56.175507 Final RX Vref Byte 0 = 52 to rank1
5354 11:05:56.178880 Final RX Vref Byte 1 = 50 to rank1==
5355 11:05:56.182104 Dram Type= 6, Freq= 0, CH_0, rank 0
5356 11:05:56.185348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 11:05:56.185428 ==
5358 11:05:56.188781 DQS Delay:
5359 11:05:56.188854 DQS0 = 0, DQS1 = 0
5360 11:05:56.192476 DQM Delay:
5361 11:05:56.192554 DQM0 = 97, DQM1 = 88
5362 11:05:56.192618 DQ Delay:
5363 11:05:56.195511 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5364 11:05:56.198450 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =104
5365 11:05:56.201755 DQ8 =78, DQ9 =74, DQ10 =90, DQ11 =80
5366 11:05:56.205330 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =98
5367 11:05:56.205400
5368 11:05:56.205460
5369 11:05:56.215393 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5370 11:05:56.218586 CH0 RK0: MR19=504, MR18=10FB
5371 11:05:56.225119 CH0_RK0: MR19=0x504, MR18=0x10FB, DQSOSC=416, MR23=63, INC=62, DEC=41
5372 11:05:56.225200
5373 11:05:56.228458 ----->DramcWriteLeveling(PI) begin...
5374 11:05:56.228536 ==
5375 11:05:56.231701 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 11:05:56.235110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 11:05:56.235231 ==
5378 11:05:56.238379 Write leveling (Byte 0): 33 => 33
5379 11:05:56.241674 Write leveling (Byte 1): 31 => 31
5380 11:05:56.245041 DramcWriteLeveling(PI) end<-----
5381 11:05:56.245123
5382 11:05:56.245188 ==
5383 11:05:56.248517 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 11:05:56.251988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 11:05:56.252071 ==
5386 11:05:56.255597 [Gating] SW mode calibration
5387 11:05:56.261887 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5388 11:05:56.268420 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5389 11:05:56.272253 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5390 11:05:56.275509 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
5391 11:05:56.281795 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5392 11:05:56.285434 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5393 11:05:56.289041 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5394 11:05:56.295561 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5395 11:05:56.298914 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5396 11:05:56.301786 0 14 28 | B1->B0 | 3131 2c2c | 1 1 | (1 0) (0 0)
5397 11:05:56.308402 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
5398 11:05:56.311881 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5399 11:05:56.315094 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5400 11:05:56.318357 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5401 11:05:56.325270 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5402 11:05:56.328681 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5403 11:05:56.331834 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5404 11:05:56.338644 0 15 28 | B1->B0 | 2525 3737 | 0 1 | (0 0) (1 1)
5405 11:05:56.342276 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5406 11:05:56.345026 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 11:05:56.352228 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 11:05:56.354846 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 11:05:56.358596 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5410 11:05:56.365281 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5411 11:05:56.368801 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 11:05:56.372320 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5413 11:05:56.378362 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5414 11:05:56.381754 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5415 11:05:56.385061 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 11:05:56.391888 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 11:05:56.394967 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 11:05:56.398411 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 11:05:56.405054 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 11:05:56.408630 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 11:05:56.411953 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 11:05:56.418131 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 11:05:56.421684 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 11:05:56.425055 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 11:05:56.428725 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 11:05:56.435234 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 11:05:56.438546 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 11:05:56.442282 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5429 11:05:56.448493 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5430 11:05:56.448579 Total UI for P1: 0, mck2ui 16
5431 11:05:56.455238 best dqsien dly found for B0: ( 1, 2, 28)
5432 11:05:56.458499 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5433 11:05:56.461829 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5434 11:05:56.465267 Total UI for P1: 0, mck2ui 16
5435 11:05:56.469116 best dqsien dly found for B1: ( 1, 3, 2)
5436 11:05:56.471768 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5437 11:05:56.475034 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5438 11:05:56.475119
5439 11:05:56.481793 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5440 11:05:56.485009 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5441 11:05:56.485095 [Gating] SW calibration Done
5442 11:05:56.488342 ==
5443 11:05:56.488428 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 11:05:56.495627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 11:05:56.495716 ==
5446 11:05:56.495785 RX Vref Scan: 0
5447 11:05:56.495852
5448 11:05:56.498629 RX Vref 0 -> 0, step: 1
5449 11:05:56.498715
5450 11:05:56.501769 RX Delay -80 -> 252, step: 8
5451 11:05:56.505052 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5452 11:05:56.508399 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5453 11:05:56.512031 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5454 11:05:56.515097 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5455 11:05:56.521816 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5456 11:05:56.524822 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5457 11:05:56.528335 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5458 11:05:56.531921 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5459 11:05:56.535373 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5460 11:05:56.538350 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5461 11:05:56.544980 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5462 11:05:56.548302 iDelay=200, Bit 11, Center 75 (-16 ~ 167) 184
5463 11:05:56.551532 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5464 11:05:56.554895 iDelay=200, Bit 13, Center 91 (0 ~ 183) 184
5465 11:05:56.558294 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5466 11:05:56.561884 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5467 11:05:56.565173 ==
5468 11:05:56.568426 Dram Type= 6, Freq= 0, CH_0, rank 1
5469 11:05:56.571815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5470 11:05:56.571920 ==
5471 11:05:56.572022 DQS Delay:
5472 11:05:56.575401 DQS0 = 0, DQS1 = 0
5473 11:05:56.575488 DQM Delay:
5474 11:05:56.578644 DQM0 = 96, DQM1 = 87
5475 11:05:56.578723 DQ Delay:
5476 11:05:56.581512 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =95
5477 11:05:56.585398 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5478 11:05:56.588035 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =75
5479 11:05:56.591475 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5480 11:05:56.591552
5481 11:05:56.591616
5482 11:05:56.591675 ==
5483 11:05:56.595083 Dram Type= 6, Freq= 0, CH_0, rank 1
5484 11:05:56.598165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 11:05:56.598237 ==
5486 11:05:56.598298
5487 11:05:56.598367
5488 11:05:56.601704 TX Vref Scan disable
5489 11:05:56.605525 == TX Byte 0 ==
5490 11:05:56.608276 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5491 11:05:56.611828 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5492 11:05:56.615264 == TX Byte 1 ==
5493 11:05:56.619154 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5494 11:05:56.621732 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5495 11:05:56.621819 ==
5496 11:05:56.624999 Dram Type= 6, Freq= 0, CH_0, rank 1
5497 11:05:56.628407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 11:05:56.631905 ==
5499 11:05:56.631981
5500 11:05:56.632054
5501 11:05:56.632116 TX Vref Scan disable
5502 11:05:56.635131 == TX Byte 0 ==
5503 11:05:56.639136 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5504 11:05:56.641915 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5505 11:05:56.645343 == TX Byte 1 ==
5506 11:05:56.648608 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5507 11:05:56.652335 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5508 11:05:56.655350
5509 11:05:56.655460 [DATLAT]
5510 11:05:56.655562 Freq=933, CH0 RK1
5511 11:05:56.655667
5512 11:05:56.658433 DATLAT Default: 0xb
5513 11:05:56.658536 0, 0xFFFF, sum = 0
5514 11:05:56.661838 1, 0xFFFF, sum = 0
5515 11:05:56.661924 2, 0xFFFF, sum = 0
5516 11:05:56.665305 3, 0xFFFF, sum = 0
5517 11:05:56.665391 4, 0xFFFF, sum = 0
5518 11:05:56.668655 5, 0xFFFF, sum = 0
5519 11:05:56.668767 6, 0xFFFF, sum = 0
5520 11:05:56.672302 7, 0xFFFF, sum = 0
5521 11:05:56.675042 8, 0xFFFF, sum = 0
5522 11:05:56.675154 9, 0xFFFF, sum = 0
5523 11:05:56.678989 10, 0x0, sum = 1
5524 11:05:56.679102 11, 0x0, sum = 2
5525 11:05:56.679205 12, 0x0, sum = 3
5526 11:05:56.682193 13, 0x0, sum = 4
5527 11:05:56.682319 best_step = 11
5528 11:05:56.682442
5529 11:05:56.682523 ==
5530 11:05:56.685130 Dram Type= 6, Freq= 0, CH_0, rank 1
5531 11:05:56.691844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 11:05:56.691929 ==
5533 11:05:56.692014 RX Vref Scan: 0
5534 11:05:56.692096
5535 11:05:56.695230 RX Vref 0 -> 0, step: 1
5536 11:05:56.695312
5537 11:05:56.698755 RX Delay -61 -> 252, step: 4
5538 11:05:56.702096 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5539 11:05:56.705439 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5540 11:05:56.711939 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5541 11:05:56.715714 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5542 11:05:56.718615 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5543 11:05:56.722290 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5544 11:05:56.725142 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5545 11:05:56.728747 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5546 11:05:56.735206 iDelay=199, Bit 8, Center 78 (-9 ~ 166) 176
5547 11:05:56.738455 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5548 11:05:56.742339 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5549 11:05:56.745597 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5550 11:05:56.748870 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5551 11:05:56.755396 iDelay=199, Bit 13, Center 92 (7 ~ 178) 172
5552 11:05:56.759111 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5553 11:05:56.761742 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5554 11:05:56.761872 ==
5555 11:05:56.765746 Dram Type= 6, Freq= 0, CH_0, rank 1
5556 11:05:56.769149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 11:05:56.769268 ==
5558 11:05:56.772387 DQS Delay:
5559 11:05:56.772516 DQS0 = 0, DQS1 = 0
5560 11:05:56.772629 DQM Delay:
5561 11:05:56.775218 DQM0 = 95, DQM1 = 87
5562 11:05:56.775344 DQ Delay:
5563 11:05:56.778763 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5564 11:05:56.781918 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =102
5565 11:05:56.785612 DQ8 =78, DQ9 =78, DQ10 =88, DQ11 =78
5566 11:05:56.788750 DQ12 =90, DQ13 =92, DQ14 =98, DQ15 =94
5567 11:05:56.788882
5568 11:05:56.788996
5569 11:05:56.798288 [DQSOSCAuto] RK1, (LSB)MR18= 0x1603, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5570 11:05:56.802370 CH0 RK1: MR19=505, MR18=1603
5571 11:05:56.805002 CH0_RK1: MR19=0x505, MR18=0x1603, DQSOSC=414, MR23=63, INC=63, DEC=42
5572 11:05:56.808537 [RxdqsGatingPostProcess] freq 933
5573 11:05:56.814984 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5574 11:05:56.818742 best DQS0 dly(2T, 0.5T) = (0, 10)
5575 11:05:56.822348 best DQS1 dly(2T, 0.5T) = (0, 10)
5576 11:05:56.825516 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5577 11:05:56.828318 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5578 11:05:56.831597 best DQS0 dly(2T, 0.5T) = (0, 10)
5579 11:05:56.835892 best DQS1 dly(2T, 0.5T) = (0, 11)
5580 11:05:56.838328 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5581 11:05:56.838452 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5582 11:05:56.841851 Pre-setting of DQS Precalculation
5583 11:05:56.848614 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5584 11:05:56.848695 ==
5585 11:05:56.852177 Dram Type= 6, Freq= 0, CH_1, rank 0
5586 11:05:56.855378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5587 11:05:56.855488 ==
5588 11:05:56.862029 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5589 11:05:56.868616 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5590 11:05:56.871745 [CA 0] Center 36 (6~67) winsize 62
5591 11:05:56.875438 [CA 1] Center 37 (7~67) winsize 61
5592 11:05:56.879263 [CA 2] Center 34 (4~65) winsize 62
5593 11:05:56.882121 [CA 3] Center 33 (3~64) winsize 62
5594 11:05:56.885509 [CA 4] Center 34 (3~65) winsize 63
5595 11:05:56.885596 [CA 5] Center 33 (3~63) winsize 61
5596 11:05:56.888917
5597 11:05:56.892368 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5598 11:05:56.892452
5599 11:05:56.895690 [CATrainingPosCal] consider 1 rank data
5600 11:05:56.899318 u2DelayCellTimex100 = 270/100 ps
5601 11:05:56.902054 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5602 11:05:56.905388 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5603 11:05:56.908996 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5604 11:05:56.912376 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5605 11:05:56.915615 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5606 11:05:56.918772 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5607 11:05:56.918938
5608 11:05:56.922187 CA PerBit enable=1, Macro0, CA PI delay=33
5609 11:05:56.922278
5610 11:05:56.925157 [CBTSetCACLKResult] CA Dly = 33
5611 11:05:56.928782 CS Dly: 4 (0~35)
5612 11:05:56.928866 ==
5613 11:05:56.932185 Dram Type= 6, Freq= 0, CH_1, rank 1
5614 11:05:56.935319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5615 11:05:56.935428 ==
5616 11:05:56.942152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5617 11:05:56.948297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5618 11:05:56.951703 [CA 0] Center 36 (6~67) winsize 62
5619 11:05:56.955288 [CA 1] Center 37 (7~67) winsize 61
5620 11:05:56.958250 [CA 2] Center 34 (3~65) winsize 63
5621 11:05:56.961699 [CA 3] Center 33 (3~64) winsize 62
5622 11:05:56.964931 [CA 4] Center 34 (4~65) winsize 62
5623 11:05:56.968184 [CA 5] Center 33 (3~64) winsize 62
5624 11:05:56.968302
5625 11:05:56.972136 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5626 11:05:56.972208
5627 11:05:56.975411 [CATrainingPosCal] consider 2 rank data
5628 11:05:56.978657 u2DelayCellTimex100 = 270/100 ps
5629 11:05:56.981939 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5630 11:05:56.985068 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5631 11:05:56.988678 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5632 11:05:56.992305 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5633 11:05:56.995355 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5634 11:05:56.998367 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5635 11:05:56.998455
5636 11:05:57.002160 CA PerBit enable=1, Macro0, CA PI delay=33
5637 11:05:57.002264
5638 11:05:57.005335 [CBTSetCACLKResult] CA Dly = 33
5639 11:05:57.008643 CS Dly: 5 (0~38)
5640 11:05:57.008747
5641 11:05:57.012114 ----->DramcWriteLeveling(PI) begin...
5642 11:05:57.012214 ==
5643 11:05:57.015554 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 11:05:57.018614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 11:05:57.018705 ==
5646 11:05:57.021511 Write leveling (Byte 0): 25 => 25
5647 11:05:57.024831 Write leveling (Byte 1): 30 => 30
5648 11:05:57.028994 DramcWriteLeveling(PI) end<-----
5649 11:05:57.029081
5650 11:05:57.029151 ==
5651 11:05:57.031703 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 11:05:57.034952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 11:05:57.035030 ==
5654 11:05:57.038704 [Gating] SW mode calibration
5655 11:05:57.044886 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5656 11:05:57.051805 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5657 11:05:57.055006 0 14 0 | B1->B0 | 3131 3232 | 1 0 | (1 1) (0 0)
5658 11:05:57.061763 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5659 11:05:57.064822 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5660 11:05:57.068489 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5661 11:05:57.075553 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5662 11:05:57.078737 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5663 11:05:57.082127 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5664 11:05:57.084848 0 14 28 | B1->B0 | 2f2f 3131 | 1 1 | (1 0) (1 0)
5665 11:05:57.091675 0 15 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
5666 11:05:57.094929 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5667 11:05:57.098178 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5668 11:05:57.104978 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5669 11:05:57.108503 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5670 11:05:57.111963 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5671 11:05:57.118333 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 11:05:57.121820 0 15 28 | B1->B0 | 2929 2d2d | 0 1 | (0 0) (0 0)
5673 11:05:57.125044 1 0 0 | B1->B0 | 4646 3f3f | 0 1 | (0 0) (0 0)
5674 11:05:57.131584 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5675 11:05:57.135155 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 11:05:57.138670 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5677 11:05:57.144897 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5678 11:05:57.148204 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 11:05:57.151855 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 11:05:57.158527 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 11:05:57.161595 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 11:05:57.165099 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 11:05:57.171965 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 11:05:57.175304 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 11:05:57.178305 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 11:05:57.181727 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 11:05:57.188519 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 11:05:57.192301 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 11:05:57.195074 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 11:05:57.201725 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 11:05:57.205028 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 11:05:57.208833 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 11:05:57.214749 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 11:05:57.218114 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 11:05:57.221975 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5696 11:05:57.228563 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5697 11:05:57.228648 Total UI for P1: 0, mck2ui 16
5698 11:05:57.234852 best dqsien dly found for B0: ( 1, 2, 26)
5699 11:05:57.234938 Total UI for P1: 0, mck2ui 16
5700 11:05:57.241417 best dqsien dly found for B1: ( 1, 2, 24)
5701 11:05:57.245328 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5702 11:05:57.248599 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5703 11:05:57.248680
5704 11:05:57.251420 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5705 11:05:57.254821 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5706 11:05:57.258454 [Gating] SW calibration Done
5707 11:05:57.258567 ==
5708 11:05:57.261665 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 11:05:57.264853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 11:05:57.264956 ==
5711 11:05:57.268330 RX Vref Scan: 0
5712 11:05:57.268404
5713 11:05:57.268466 RX Vref 0 -> 0, step: 1
5714 11:05:57.268529
5715 11:05:57.271667 RX Delay -80 -> 252, step: 8
5716 11:05:57.274969 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5717 11:05:57.281586 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5718 11:05:57.284654 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5719 11:05:57.288172 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5720 11:05:57.291355 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5721 11:05:57.295070 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5722 11:05:57.298419 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5723 11:05:57.304967 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5724 11:05:57.307904 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5725 11:05:57.311770 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5726 11:05:57.314885 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5727 11:05:57.318034 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5728 11:05:57.324725 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5729 11:05:57.327959 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5730 11:05:57.331283 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5731 11:05:57.334631 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5732 11:05:57.334712 ==
5733 11:05:57.337669 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 11:05:57.341187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 11:05:57.341269 ==
5736 11:05:57.344930 DQS Delay:
5737 11:05:57.345012 DQS0 = 0, DQS1 = 0
5738 11:05:57.347824 DQM Delay:
5739 11:05:57.347896 DQM0 = 96, DQM1 = 88
5740 11:05:57.347964 DQ Delay:
5741 11:05:57.350952 DQ0 =99, DQ1 =95, DQ2 =79, DQ3 =95
5742 11:05:57.354919 DQ4 =95, DQ5 =111, DQ6 =107, DQ7 =91
5743 11:05:57.357846 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5744 11:05:57.361647 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5745 11:05:57.361753
5746 11:05:57.361852
5747 11:05:57.364548 ==
5748 11:05:57.367965 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 11:05:57.371250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 11:05:57.371333 ==
5751 11:05:57.371396
5752 11:05:57.371455
5753 11:05:57.374246 TX Vref Scan disable
5754 11:05:57.374349 == TX Byte 0 ==
5755 11:05:57.381070 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5756 11:05:57.384145 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5757 11:05:57.384233 == TX Byte 1 ==
5758 11:05:57.391246 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5759 11:05:57.394519 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5760 11:05:57.394600 ==
5761 11:05:57.397622 Dram Type= 6, Freq= 0, CH_1, rank 0
5762 11:05:57.401110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 11:05:57.401193 ==
5764 11:05:57.401261
5765 11:05:57.401330
5766 11:05:57.404587 TX Vref Scan disable
5767 11:05:57.407767 == TX Byte 0 ==
5768 11:05:57.410848 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5769 11:05:57.414530 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5770 11:05:57.418089 == TX Byte 1 ==
5771 11:05:57.421105 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5772 11:05:57.424444 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5773 11:05:57.424526
5774 11:05:57.427995 [DATLAT]
5775 11:05:57.428081 Freq=933, CH1 RK0
5776 11:05:57.428151
5777 11:05:57.430931 DATLAT Default: 0xd
5778 11:05:57.431050 0, 0xFFFF, sum = 0
5779 11:05:57.434426 1, 0xFFFF, sum = 0
5780 11:05:57.434512 2, 0xFFFF, sum = 0
5781 11:05:57.437745 3, 0xFFFF, sum = 0
5782 11:05:57.437831 4, 0xFFFF, sum = 0
5783 11:05:57.441008 5, 0xFFFF, sum = 0
5784 11:05:57.441094 6, 0xFFFF, sum = 0
5785 11:05:57.444092 7, 0xFFFF, sum = 0
5786 11:05:57.444172 8, 0xFFFF, sum = 0
5787 11:05:57.447855 9, 0xFFFF, sum = 0
5788 11:05:57.447938 10, 0x0, sum = 1
5789 11:05:57.451070 11, 0x0, sum = 2
5790 11:05:57.451156 12, 0x0, sum = 3
5791 11:05:57.454688 13, 0x0, sum = 4
5792 11:05:57.454769 best_step = 11
5793 11:05:57.454841
5794 11:05:57.454906 ==
5795 11:05:57.458160 Dram Type= 6, Freq= 0, CH_1, rank 0
5796 11:05:57.460755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5797 11:05:57.464296 ==
5798 11:05:57.464382 RX Vref Scan: 1
5799 11:05:57.464469
5800 11:05:57.467756 RX Vref 0 -> 0, step: 1
5801 11:05:57.467841
5802 11:05:57.471288 RX Delay -61 -> 252, step: 4
5803 11:05:57.471400
5804 11:05:57.474357 Set Vref, RX VrefLevel [Byte0]: 57
5805 11:05:57.474451 [Byte1]: 49
5806 11:05:57.479277
5807 11:05:57.479359 Final RX Vref Byte 0 = 57 to rank0
5808 11:05:57.482600 Final RX Vref Byte 1 = 49 to rank0
5809 11:05:57.486390 Final RX Vref Byte 0 = 57 to rank1
5810 11:05:57.489526 Final RX Vref Byte 1 = 49 to rank1==
5811 11:05:57.492867 Dram Type= 6, Freq= 0, CH_1, rank 0
5812 11:05:57.499218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 11:05:57.499333 ==
5814 11:05:57.499429 DQS Delay:
5815 11:05:57.499520 DQS0 = 0, DQS1 = 0
5816 11:05:57.502657 DQM Delay:
5817 11:05:57.502759 DQM0 = 97, DQM1 = 90
5818 11:05:57.506414 DQ Delay:
5819 11:05:57.509104 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =96
5820 11:05:57.512985 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =94
5821 11:05:57.516027 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
5822 11:05:57.519249 DQ12 =100, DQ13 =96, DQ14 =100, DQ15 =94
5823 11:05:57.519331
5824 11:05:57.519395
5825 11:05:57.525837 [DQSOSCAuto] RK0, (LSB)MR18= 0x15f2, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 415 ps
5826 11:05:57.529124 CH1 RK0: MR19=504, MR18=15F2
5827 11:05:57.535930 CH1_RK0: MR19=0x504, MR18=0x15F2, DQSOSC=415, MR23=63, INC=62, DEC=41
5828 11:05:57.536014
5829 11:05:57.539822 ----->DramcWriteLeveling(PI) begin...
5830 11:05:57.539906 ==
5831 11:05:57.543149 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 11:05:57.546195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 11:05:57.546305 ==
5834 11:05:57.549362 Write leveling (Byte 0): 27 => 27
5835 11:05:57.552705 Write leveling (Byte 1): 29 => 29
5836 11:05:57.556107 DramcWriteLeveling(PI) end<-----
5837 11:05:57.556196
5838 11:05:57.556261 ==
5839 11:05:57.559233 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 11:05:57.562814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 11:05:57.562898 ==
5842 11:05:57.565737 [Gating] SW mode calibration
5843 11:05:57.572681 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5844 11:05:57.579375 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5845 11:05:57.583064 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5846 11:05:57.586056 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5847 11:05:57.592618 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5848 11:05:57.596149 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5849 11:05:57.599216 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5850 11:05:57.605919 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5851 11:05:57.609674 0 14 24 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (0 1)
5852 11:05:57.612486 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5853 11:05:57.619073 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5854 11:05:57.622885 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5855 11:05:57.626303 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5856 11:05:57.632722 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5857 11:05:57.636065 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5858 11:05:57.639179 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5859 11:05:57.646315 0 15 24 | B1->B0 | 2525 3030 | 0 1 | (0 0) (0 0)
5860 11:05:57.649265 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5861 11:05:57.652458 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5862 11:05:57.659382 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 11:05:57.662392 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5864 11:05:57.665825 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5865 11:05:57.672586 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5866 11:05:57.675906 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 11:05:57.679769 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5868 11:05:57.683220 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 11:05:57.689870 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 11:05:57.692744 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 11:05:57.695950 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 11:05:57.702668 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 11:05:57.705929 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 11:05:57.709759 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 11:05:57.716397 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 11:05:57.719207 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 11:05:57.722659 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 11:05:57.729258 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 11:05:57.732590 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 11:05:57.736197 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 11:05:57.742662 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 11:05:57.746273 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 11:05:57.749443 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5884 11:05:57.756313 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5885 11:05:57.756399 Total UI for P1: 0, mck2ui 16
5886 11:05:57.762819 best dqsien dly found for B0: ( 1, 2, 24)
5887 11:05:57.765919 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5888 11:05:57.769274 Total UI for P1: 0, mck2ui 16
5889 11:05:57.772521 best dqsien dly found for B1: ( 1, 2, 26)
5890 11:05:57.776528 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5891 11:05:57.779373 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5892 11:05:57.779458
5893 11:05:57.782698 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5894 11:05:57.785827 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5895 11:05:57.789274 [Gating] SW calibration Done
5896 11:05:57.789351 ==
5897 11:05:57.792468 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 11:05:57.795949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 11:05:57.796033 ==
5900 11:05:57.799261 RX Vref Scan: 0
5901 11:05:57.799372
5902 11:05:57.802993 RX Vref 0 -> 0, step: 1
5903 11:05:57.803104
5904 11:05:57.803203 RX Delay -80 -> 252, step: 8
5905 11:05:57.809208 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5906 11:05:57.812541 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5907 11:05:57.815979 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5908 11:05:57.819462 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5909 11:05:57.822330 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5910 11:05:57.825593 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5911 11:05:57.832505 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5912 11:05:57.836345 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5913 11:05:57.839387 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5914 11:05:57.842607 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5915 11:05:57.846216 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5916 11:05:57.849142 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5917 11:05:57.855784 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5918 11:05:57.859191 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5919 11:05:57.862899 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5920 11:05:57.866596 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5921 11:05:57.866704 ==
5922 11:05:57.869221 Dram Type= 6, Freq= 0, CH_1, rank 1
5923 11:05:57.872565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5924 11:05:57.875943 ==
5925 11:05:57.876019 DQS Delay:
5926 11:05:57.876081 DQS0 = 0, DQS1 = 0
5927 11:05:57.879337 DQM Delay:
5928 11:05:57.879412 DQM0 = 94, DQM1 = 89
5929 11:05:57.883001 DQ Delay:
5930 11:05:57.883074 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5931 11:05:57.886009 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5932 11:05:57.889271 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5933 11:05:57.892475 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =99
5934 11:05:57.892555
5935 11:05:57.896122
5936 11:05:57.896238 ==
5937 11:05:57.899604 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 11:05:57.902776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 11:05:57.902898 ==
5940 11:05:57.903020
5941 11:05:57.903130
5942 11:05:57.906328 TX Vref Scan disable
5943 11:05:57.906465 == TX Byte 0 ==
5944 11:05:57.912848 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5945 11:05:57.915915 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5946 11:05:57.916036 == TX Byte 1 ==
5947 11:05:57.922698 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5948 11:05:57.926107 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5949 11:05:57.926230 ==
5950 11:05:57.929425 Dram Type= 6, Freq= 0, CH_1, rank 1
5951 11:05:57.932878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5952 11:05:57.932998 ==
5953 11:05:57.933113
5954 11:05:57.933224
5955 11:05:57.935921 TX Vref Scan disable
5956 11:05:57.939115 == TX Byte 0 ==
5957 11:05:57.942446 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5958 11:05:57.945993 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5959 11:05:57.949200 == TX Byte 1 ==
5960 11:05:57.952883 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5961 11:05:57.955848 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5962 11:05:57.955934
5963 11:05:57.959054 [DATLAT]
5964 11:05:57.959132 Freq=933, CH1 RK1
5965 11:05:57.959196
5966 11:05:57.962370 DATLAT Default: 0xb
5967 11:05:57.962471 0, 0xFFFF, sum = 0
5968 11:05:57.966638 1, 0xFFFF, sum = 0
5969 11:05:57.966719 2, 0xFFFF, sum = 0
5970 11:05:57.969257 3, 0xFFFF, sum = 0
5971 11:05:57.969343 4, 0xFFFF, sum = 0
5972 11:05:57.972575 5, 0xFFFF, sum = 0
5973 11:05:57.972704 6, 0xFFFF, sum = 0
5974 11:05:57.975769 7, 0xFFFF, sum = 0
5975 11:05:57.975897 8, 0xFFFF, sum = 0
5976 11:05:57.979148 9, 0xFFFF, sum = 0
5977 11:05:57.979279 10, 0x0, sum = 1
5978 11:05:57.982805 11, 0x0, sum = 2
5979 11:05:57.982930 12, 0x0, sum = 3
5980 11:05:57.986147 13, 0x0, sum = 4
5981 11:05:57.986280 best_step = 11
5982 11:05:57.986391
5983 11:05:57.986521 ==
5984 11:05:57.989854 Dram Type= 6, Freq= 0, CH_1, rank 1
5985 11:05:57.992816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5986 11:05:57.992896 ==
5987 11:05:57.995985 RX Vref Scan: 0
5988 11:05:57.996069
5989 11:05:57.999135 RX Vref 0 -> 0, step: 1
5990 11:05:57.999235
5991 11:05:57.999338 RX Delay -61 -> 252, step: 4
5992 11:05:58.007395 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5993 11:05:58.010606 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5994 11:05:58.013689 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5995 11:05:58.016897 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5996 11:05:58.020766 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5997 11:05:58.026894 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5998 11:05:58.030335 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5999 11:05:58.033925 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
6000 11:05:58.037790 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
6001 11:05:58.040277 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
6002 11:05:58.043509 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
6003 11:05:58.050440 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
6004 11:05:58.053687 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
6005 11:05:58.056880 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
6006 11:05:58.060661 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
6007 11:05:58.063585 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
6008 11:05:58.063665 ==
6009 11:05:58.066871 Dram Type= 6, Freq= 0, CH_1, rank 1
6010 11:05:58.073819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6011 11:05:58.073900 ==
6012 11:05:58.073974 DQS Delay:
6013 11:05:58.076926 DQS0 = 0, DQS1 = 0
6014 11:05:58.077007 DQM Delay:
6015 11:05:58.077087 DQM0 = 95, DQM1 = 90
6016 11:05:58.080414 DQ Delay:
6017 11:05:58.083527 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =92
6018 11:05:58.087393 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =92
6019 11:05:58.090263 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =84
6020 11:05:58.093726 DQ12 =94, DQ13 =98, DQ14 =100, DQ15 =98
6021 11:05:58.093844
6022 11:05:58.093948
6023 11:05:58.100462 [DQSOSCAuto] RK1, (LSB)MR18= 0xe17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
6024 11:05:58.103549 CH1 RK1: MR19=505, MR18=E17
6025 11:05:58.110327 CH1_RK1: MR19=0x505, MR18=0xE17, DQSOSC=414, MR23=63, INC=63, DEC=42
6026 11:05:58.113828 [RxdqsGatingPostProcess] freq 933
6027 11:05:58.117055 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6028 11:05:58.120311 best DQS0 dly(2T, 0.5T) = (0, 10)
6029 11:05:58.123685 best DQS1 dly(2T, 0.5T) = (0, 10)
6030 11:05:58.126987 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6031 11:05:58.131101 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6032 11:05:58.133605 best DQS0 dly(2T, 0.5T) = (0, 10)
6033 11:05:58.137392 best DQS1 dly(2T, 0.5T) = (0, 10)
6034 11:05:58.140354 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6035 11:05:58.144292 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6036 11:05:58.147309 Pre-setting of DQS Precalculation
6037 11:05:58.150368 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6038 11:05:58.157479 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6039 11:05:58.167568 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6040 11:05:58.167652
6041 11:05:58.167719
6042 11:05:58.170372 [Calibration Summary] 1866 Mbps
6043 11:05:58.170469 CH 0, Rank 0
6044 11:05:58.174317 SW Impedance : PASS
6045 11:05:58.174425 DUTY Scan : NO K
6046 11:05:58.177062 ZQ Calibration : PASS
6047 11:05:58.177145 Jitter Meter : NO K
6048 11:05:58.180286 CBT Training : PASS
6049 11:05:58.184361 Write leveling : PASS
6050 11:05:58.184440 RX DQS gating : PASS
6051 11:05:58.187042 RX DQ/DQS(RDDQC) : PASS
6052 11:05:58.190408 TX DQ/DQS : PASS
6053 11:05:58.190487 RX DATLAT : PASS
6054 11:05:58.193742 RX DQ/DQS(Engine): PASS
6055 11:05:58.197242 TX OE : NO K
6056 11:05:58.197322 All Pass.
6057 11:05:58.197390
6058 11:05:58.197453 CH 0, Rank 1
6059 11:05:58.200367 SW Impedance : PASS
6060 11:05:58.203757 DUTY Scan : NO K
6061 11:05:58.203836 ZQ Calibration : PASS
6062 11:05:58.207262 Jitter Meter : NO K
6063 11:05:58.210952 CBT Training : PASS
6064 11:05:58.211029 Write leveling : PASS
6065 11:05:58.213996 RX DQS gating : PASS
6066 11:05:58.214102 RX DQ/DQS(RDDQC) : PASS
6067 11:05:58.217256 TX DQ/DQS : PASS
6068 11:05:58.220322 RX DATLAT : PASS
6069 11:05:58.220410 RX DQ/DQS(Engine): PASS
6070 11:05:58.223726 TX OE : NO K
6071 11:05:58.223806 All Pass.
6072 11:05:58.223869
6073 11:05:58.227678 CH 1, Rank 0
6074 11:05:58.227759 SW Impedance : PASS
6075 11:05:58.230311 DUTY Scan : NO K
6076 11:05:58.233915 ZQ Calibration : PASS
6077 11:05:58.233992 Jitter Meter : NO K
6078 11:05:58.237794 CBT Training : PASS
6079 11:05:58.240645 Write leveling : PASS
6080 11:05:58.240720 RX DQS gating : PASS
6081 11:05:58.243668 RX DQ/DQS(RDDQC) : PASS
6082 11:05:58.247235 TX DQ/DQS : PASS
6083 11:05:58.247313 RX DATLAT : PASS
6084 11:05:58.250475 RX DQ/DQS(Engine): PASS
6085 11:05:58.254050 TX OE : NO K
6086 11:05:58.254152 All Pass.
6087 11:05:58.254243
6088 11:05:58.254338 CH 1, Rank 1
6089 11:05:58.257410 SW Impedance : PASS
6090 11:05:58.260157 DUTY Scan : NO K
6091 11:05:58.260240 ZQ Calibration : PASS
6092 11:05:58.263937 Jitter Meter : NO K
6093 11:05:58.264016 CBT Training : PASS
6094 11:05:58.267320 Write leveling : PASS
6095 11:05:58.270417 RX DQS gating : PASS
6096 11:05:58.270496 RX DQ/DQS(RDDQC) : PASS
6097 11:05:58.273860 TX DQ/DQS : PASS
6098 11:05:58.276968 RX DATLAT : PASS
6099 11:05:58.277052 RX DQ/DQS(Engine): PASS
6100 11:05:58.280320 TX OE : NO K
6101 11:05:58.280397 All Pass.
6102 11:05:58.280459
6103 11:05:58.283529 DramC Write-DBI off
6104 11:05:58.286905 PER_BANK_REFRESH: Hybrid Mode
6105 11:05:58.286984 TX_TRACKING: ON
6106 11:05:58.297158 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6107 11:05:58.300604 [FAST_K] Save calibration result to emmc
6108 11:05:58.303993 dramc_set_vcore_voltage set vcore to 650000
6109 11:05:58.307417 Read voltage for 400, 6
6110 11:05:58.307499 Vio18 = 0
6111 11:05:58.307564 Vcore = 650000
6112 11:05:58.310554 Vdram = 0
6113 11:05:58.310636 Vddq = 0
6114 11:05:58.310701 Vmddr = 0
6115 11:05:58.316787 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6116 11:05:58.320114 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6117 11:05:58.323655 MEM_TYPE=3, freq_sel=20
6118 11:05:58.326917 sv_algorithm_assistance_LP4_800
6119 11:05:58.330357 ============ PULL DRAM RESETB DOWN ============
6120 11:05:58.333827 ========== PULL DRAM RESETB DOWN end =========
6121 11:05:58.340458 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6122 11:05:58.343723 ===================================
6123 11:05:58.343816 LPDDR4 DRAM CONFIGURATION
6124 11:05:58.347079 ===================================
6125 11:05:58.350344 EX_ROW_EN[0] = 0x0
6126 11:05:58.353651 EX_ROW_EN[1] = 0x0
6127 11:05:58.353734 LP4Y_EN = 0x0
6128 11:05:58.357185 WORK_FSP = 0x0
6129 11:05:58.357267 WL = 0x2
6130 11:05:58.360506 RL = 0x2
6131 11:05:58.360589 BL = 0x2
6132 11:05:58.363694 RPST = 0x0
6133 11:05:58.363776 RD_PRE = 0x0
6134 11:05:58.367131 WR_PRE = 0x1
6135 11:05:58.367214 WR_PST = 0x0
6136 11:05:58.370363 DBI_WR = 0x0
6137 11:05:58.370466 DBI_RD = 0x0
6138 11:05:58.373977 OTF = 0x1
6139 11:05:58.376900 ===================================
6140 11:05:58.380155 ===================================
6141 11:05:58.380249 ANA top config
6142 11:05:58.383558 ===================================
6143 11:05:58.387232 DLL_ASYNC_EN = 0
6144 11:05:58.390385 ALL_SLAVE_EN = 1
6145 11:05:58.393727 NEW_RANK_MODE = 1
6146 11:05:58.393826 DLL_IDLE_MODE = 1
6147 11:05:58.397185 LP45_APHY_COMB_EN = 1
6148 11:05:58.400306 TX_ODT_DIS = 1
6149 11:05:58.404138 NEW_8X_MODE = 1
6150 11:05:58.406791 ===================================
6151 11:05:58.410198 ===================================
6152 11:05:58.414010 data_rate = 800
6153 11:05:58.414093 CKR = 1
6154 11:05:58.417251 DQ_P2S_RATIO = 4
6155 11:05:58.420043 ===================================
6156 11:05:58.423616 CA_P2S_RATIO = 4
6157 11:05:58.427079 DQ_CA_OPEN = 0
6158 11:05:58.430226 DQ_SEMI_OPEN = 1
6159 11:05:58.430306 CA_SEMI_OPEN = 1
6160 11:05:58.433613 CA_FULL_RATE = 0
6161 11:05:58.437193 DQ_CKDIV4_EN = 0
6162 11:05:58.440549 CA_CKDIV4_EN = 1
6163 11:05:58.443639 CA_PREDIV_EN = 0
6164 11:05:58.446873 PH8_DLY = 0
6165 11:05:58.446955 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6166 11:05:58.450898 DQ_AAMCK_DIV = 0
6167 11:05:58.453694 CA_AAMCK_DIV = 0
6168 11:05:58.456829 CA_ADMCK_DIV = 4
6169 11:05:58.460175 DQ_TRACK_CA_EN = 0
6170 11:05:58.463450 CA_PICK = 800
6171 11:05:58.463532 CA_MCKIO = 400
6172 11:05:58.467318 MCKIO_SEMI = 400
6173 11:05:58.470361 PLL_FREQ = 3016
6174 11:05:58.473769 DQ_UI_PI_RATIO = 32
6175 11:05:58.476879 CA_UI_PI_RATIO = 32
6176 11:05:58.480538 ===================================
6177 11:05:58.483620 ===================================
6178 11:05:58.487081 memory_type:LPDDR4
6179 11:05:58.487164 GP_NUM : 10
6180 11:05:58.490555 SRAM_EN : 1
6181 11:05:58.490639 MD32_EN : 0
6182 11:05:58.493913 ===================================
6183 11:05:58.496723 [ANA_INIT] >>>>>>>>>>>>>>
6184 11:05:58.500233 <<<<<< [CONFIGURE PHASE]: ANA_TX
6185 11:05:58.503462 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6186 11:05:58.507012 ===================================
6187 11:05:58.510059 data_rate = 800,PCW = 0X7400
6188 11:05:58.513852 ===================================
6189 11:05:58.516930 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6190 11:05:58.523407 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6191 11:05:58.533618 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6192 11:05:58.536861 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6193 11:05:58.540027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6194 11:05:58.543391 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6195 11:05:58.546537 [ANA_INIT] flow start
6196 11:05:58.549969 [ANA_INIT] PLL >>>>>>>>
6197 11:05:58.550052 [ANA_INIT] PLL <<<<<<<<
6198 11:05:58.553221 [ANA_INIT] MIDPI >>>>>>>>
6199 11:05:58.556664 [ANA_INIT] MIDPI <<<<<<<<
6200 11:05:58.560081 [ANA_INIT] DLL >>>>>>>>
6201 11:05:58.560165 [ANA_INIT] flow end
6202 11:05:58.563516 ============ LP4 DIFF to SE enter ============
6203 11:05:58.569790 ============ LP4 DIFF to SE exit ============
6204 11:05:58.569874 [ANA_INIT] <<<<<<<<<<<<<
6205 11:05:58.572969 [Flow] Enable top DCM control >>>>>
6206 11:05:58.576406 [Flow] Enable top DCM control <<<<<
6207 11:05:58.579893 Enable DLL master slave shuffle
6208 11:05:58.586386 ==============================================================
6209 11:05:58.586483 Gating Mode config
6210 11:05:58.592844 ==============================================================
6211 11:05:58.596359 Config description:
6212 11:05:58.606252 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6213 11:05:58.612960 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6214 11:05:58.616595 SELPH_MODE 0: By rank 1: By Phase
6215 11:05:58.623073 ==============================================================
6216 11:05:58.626363 GAT_TRACK_EN = 0
6217 11:05:58.626465 RX_GATING_MODE = 2
6218 11:05:58.629689 RX_GATING_TRACK_MODE = 2
6219 11:05:58.633131 SELPH_MODE = 1
6220 11:05:58.636182 PICG_EARLY_EN = 1
6221 11:05:58.639806 VALID_LAT_VALUE = 1
6222 11:05:58.646528 ==============================================================
6223 11:05:58.649526 Enter into Gating configuration >>>>
6224 11:05:58.653217 Exit from Gating configuration <<<<
6225 11:05:58.656093 Enter into DVFS_PRE_config >>>>>
6226 11:05:58.666608 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6227 11:05:58.669902 Exit from DVFS_PRE_config <<<<<
6228 11:05:58.673357 Enter into PICG configuration >>>>
6229 11:05:58.676282 Exit from PICG configuration <<<<
6230 11:05:58.679361 [RX_INPUT] configuration >>>>>
6231 11:05:58.683584 [RX_INPUT] configuration <<<<<
6232 11:05:58.686721 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6233 11:05:58.693189 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6234 11:05:58.699902 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6235 11:05:58.703398 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6236 11:05:58.709796 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6237 11:05:58.716205 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6238 11:05:58.719451 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6239 11:05:58.723223 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6240 11:05:58.729981 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6241 11:05:58.733067 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6242 11:05:58.736315 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6243 11:05:58.742958 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6244 11:05:58.746231 ===================================
6245 11:05:58.746316 LPDDR4 DRAM CONFIGURATION
6246 11:05:58.749620 ===================================
6247 11:05:58.752730 EX_ROW_EN[0] = 0x0
6248 11:05:58.752814 EX_ROW_EN[1] = 0x0
6249 11:05:58.756312 LP4Y_EN = 0x0
6250 11:05:58.756395 WORK_FSP = 0x0
6251 11:05:58.759963 WL = 0x2
6252 11:05:58.760046 RL = 0x2
6253 11:05:58.762854 BL = 0x2
6254 11:05:58.766631 RPST = 0x0
6255 11:05:58.766715 RD_PRE = 0x0
6256 11:05:58.769595 WR_PRE = 0x1
6257 11:05:58.769678 WR_PST = 0x0
6258 11:05:58.772919 DBI_WR = 0x0
6259 11:05:58.773002 DBI_RD = 0x0
6260 11:05:58.776793 OTF = 0x1
6261 11:05:58.779702 ===================================
6262 11:05:58.782889 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6263 11:05:58.786424 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6264 11:05:58.789880 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6265 11:05:58.793510 ===================================
6266 11:05:58.797012 LPDDR4 DRAM CONFIGURATION
6267 11:05:58.800038 ===================================
6268 11:05:58.803366 EX_ROW_EN[0] = 0x10
6269 11:05:58.803450 EX_ROW_EN[1] = 0x0
6270 11:05:58.806903 LP4Y_EN = 0x0
6271 11:05:58.806986 WORK_FSP = 0x0
6272 11:05:58.810245 WL = 0x2
6273 11:05:58.810353 RL = 0x2
6274 11:05:58.813535 BL = 0x2
6275 11:05:58.813618 RPST = 0x0
6276 11:05:58.816739 RD_PRE = 0x0
6277 11:05:58.816822 WR_PRE = 0x1
6278 11:05:58.820028 WR_PST = 0x0
6279 11:05:58.820115 DBI_WR = 0x0
6280 11:05:58.823408 DBI_RD = 0x0
6281 11:05:58.823491 OTF = 0x1
6282 11:05:58.826738 ===================================
6283 11:05:58.833573 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6284 11:05:58.837750 nWR fixed to 30
6285 11:05:58.841031 [ModeRegInit_LP4] CH0 RK0
6286 11:05:58.841114 [ModeRegInit_LP4] CH0 RK1
6287 11:05:58.844667 [ModeRegInit_LP4] CH1 RK0
6288 11:05:58.848096 [ModeRegInit_LP4] CH1 RK1
6289 11:05:58.848216 match AC timing 19
6290 11:05:58.854715 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6291 11:05:58.858130 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6292 11:05:58.861045 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6293 11:05:58.867845 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6294 11:05:58.871465 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6295 11:05:58.871571 ==
6296 11:05:58.874734 Dram Type= 6, Freq= 0, CH_0, rank 0
6297 11:05:58.877705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 11:05:58.877810 ==
6299 11:05:58.884783 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6300 11:05:58.891065 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6301 11:05:58.894316 [CA 0] Center 36 (8~64) winsize 57
6302 11:05:58.897671 [CA 1] Center 36 (8~64) winsize 57
6303 11:05:58.900925 [CA 2] Center 36 (8~64) winsize 57
6304 11:05:58.901041 [CA 3] Center 36 (8~64) winsize 57
6305 11:05:58.904550 [CA 4] Center 36 (8~64) winsize 57
6306 11:05:58.907517 [CA 5] Center 36 (8~64) winsize 57
6307 11:05:58.907600
6308 11:05:58.914275 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6309 11:05:58.914359
6310 11:05:58.917381 [CATrainingPosCal] consider 1 rank data
6311 11:05:58.921419 u2DelayCellTimex100 = 270/100 ps
6312 11:05:58.924714 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 11:05:58.928051 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 11:05:58.931311 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 11:05:58.934264 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 11:05:58.937481 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 11:05:58.941616 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 11:05:58.941700
6319 11:05:58.944650 CA PerBit enable=1, Macro0, CA PI delay=36
6320 11:05:58.944740
6321 11:05:58.947614 [CBTSetCACLKResult] CA Dly = 36
6322 11:05:58.951023 CS Dly: 1 (0~32)
6323 11:05:58.951106 ==
6324 11:05:58.954112 Dram Type= 6, Freq= 0, CH_0, rank 1
6325 11:05:58.957771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 11:05:58.957856 ==
6327 11:05:58.964068 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6328 11:05:58.967993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6329 11:05:58.970817 [CA 0] Center 36 (8~64) winsize 57
6330 11:05:58.974436 [CA 1] Center 36 (8~64) winsize 57
6331 11:05:58.977333 [CA 2] Center 36 (8~64) winsize 57
6332 11:05:58.981178 [CA 3] Center 36 (8~64) winsize 57
6333 11:05:58.984603 [CA 4] Center 36 (8~64) winsize 57
6334 11:05:58.988013 [CA 5] Center 36 (8~64) winsize 57
6335 11:05:58.988098
6336 11:05:58.990959 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6337 11:05:58.991044
6338 11:05:58.994275 [CATrainingPosCal] consider 2 rank data
6339 11:05:58.997827 u2DelayCellTimex100 = 270/100 ps
6340 11:05:59.000973 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6341 11:05:59.004530 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 11:05:59.007667 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6343 11:05:59.011730 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6344 11:05:59.017712 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6345 11:05:59.021505 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 11:05:59.021588
6347 11:05:59.024257 CA PerBit enable=1, Macro0, CA PI delay=36
6348 11:05:59.024341
6349 11:05:59.027657 [CBTSetCACLKResult] CA Dly = 36
6350 11:05:59.027741 CS Dly: 1 (0~32)
6351 11:05:59.027807
6352 11:05:59.031235 ----->DramcWriteLeveling(PI) begin...
6353 11:05:59.031320 ==
6354 11:05:59.034431 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 11:05:59.041325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 11:05:59.041409 ==
6357 11:05:59.041476 Write leveling (Byte 0): 40 => 8
6358 11:05:59.045037 Write leveling (Byte 1): 32 => 0
6359 11:05:59.048151 DramcWriteLeveling(PI) end<-----
6360 11:05:59.048235
6361 11:05:59.048299 ==
6362 11:05:59.051510 Dram Type= 6, Freq= 0, CH_0, rank 0
6363 11:05:59.058155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6364 11:05:59.058239 ==
6365 11:05:59.058303 [Gating] SW mode calibration
6366 11:05:59.067901 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6367 11:05:59.071456 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6368 11:05:59.075087 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6369 11:05:59.081343 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6370 11:05:59.084844 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6371 11:05:59.087887 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6372 11:05:59.094687 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6373 11:05:59.097860 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6374 11:05:59.101239 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6375 11:05:59.108166 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6376 11:05:59.111619 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6377 11:05:59.114801 Total UI for P1: 0, mck2ui 16
6378 11:05:59.118142 best dqsien dly found for B0: ( 0, 14, 24)
6379 11:05:59.121561 Total UI for P1: 0, mck2ui 16
6380 11:05:59.124674 best dqsien dly found for B1: ( 0, 14, 24)
6381 11:05:59.128352 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6382 11:05:59.131163 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6383 11:05:59.131291
6384 11:05:59.134662 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6385 11:05:59.137845 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6386 11:05:59.141945 [Gating] SW calibration Done
6387 11:05:59.142072 ==
6388 11:05:59.144858 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 11:05:59.147875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 11:05:59.151409 ==
6391 11:05:59.151535 RX Vref Scan: 0
6392 11:05:59.151651
6393 11:05:59.154858 RX Vref 0 -> 0, step: 1
6394 11:05:59.154978
6395 11:05:59.158438 RX Delay -410 -> 252, step: 16
6396 11:05:59.161721 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6397 11:05:59.164714 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6398 11:05:59.168014 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6399 11:05:59.175105 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6400 11:05:59.178637 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6401 11:05:59.181814 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6402 11:05:59.185236 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6403 11:05:59.191800 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6404 11:05:59.194720 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6405 11:05:59.198290 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6406 11:05:59.201718 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6407 11:05:59.208333 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6408 11:05:59.211744 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6409 11:05:59.214686 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6410 11:05:59.217936 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6411 11:05:59.225028 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6412 11:05:59.225158 ==
6413 11:05:59.228046 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 11:05:59.231673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 11:05:59.231809 ==
6416 11:05:59.231941 DQS Delay:
6417 11:05:59.235002 DQS0 = 35, DQS1 = 51
6418 11:05:59.235125 DQM Delay:
6419 11:05:59.238045 DQM0 = 6, DQM1 = 10
6420 11:05:59.238174 DQ Delay:
6421 11:05:59.241472 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6422 11:05:59.244797 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6423 11:05:59.248219 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6424 11:05:59.251824 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6425 11:05:59.251951
6426 11:05:59.252081
6427 11:05:59.252196 ==
6428 11:05:59.254973 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 11:05:59.258215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 11:05:59.258341 ==
6431 11:05:59.258473
6432 11:05:59.258591
6433 11:05:59.261471 TX Vref Scan disable
6434 11:05:59.261592 == TX Byte 0 ==
6435 11:05:59.268250 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6436 11:05:59.271418 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6437 11:05:59.271551 == TX Byte 1 ==
6438 11:05:59.278332 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6439 11:05:59.281305 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6440 11:05:59.281441 ==
6441 11:05:59.285118 Dram Type= 6, Freq= 0, CH_0, rank 0
6442 11:05:59.288281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 11:05:59.288416 ==
6444 11:05:59.288544
6445 11:05:59.288660
6446 11:05:59.291556 TX Vref Scan disable
6447 11:05:59.291693 == TX Byte 0 ==
6448 11:05:59.298104 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6449 11:05:59.301680 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6450 11:05:59.301819 == TX Byte 1 ==
6451 11:05:59.308235 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6452 11:05:59.311575 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6453 11:05:59.311710
6454 11:05:59.311833 [DATLAT]
6455 11:05:59.314839 Freq=400, CH0 RK0
6456 11:05:59.314975
6457 11:05:59.315096 DATLAT Default: 0xf
6458 11:05:59.318513 0, 0xFFFF, sum = 0
6459 11:05:59.318641 1, 0xFFFF, sum = 0
6460 11:05:59.321280 2, 0xFFFF, sum = 0
6461 11:05:59.321409 3, 0xFFFF, sum = 0
6462 11:05:59.324539 4, 0xFFFF, sum = 0
6463 11:05:59.324678 5, 0xFFFF, sum = 0
6464 11:05:59.328025 6, 0xFFFF, sum = 0
6465 11:05:59.328158 7, 0xFFFF, sum = 0
6466 11:05:59.331401 8, 0xFFFF, sum = 0
6467 11:05:59.334671 9, 0xFFFF, sum = 0
6468 11:05:59.334815 10, 0xFFFF, sum = 0
6469 11:05:59.338281 11, 0xFFFF, sum = 0
6470 11:05:59.338425 12, 0xFFFF, sum = 0
6471 11:05:59.341341 13, 0x0, sum = 1
6472 11:05:59.341476 14, 0x0, sum = 2
6473 11:05:59.344873 15, 0x0, sum = 3
6474 11:05:59.345009 16, 0x0, sum = 4
6475 11:05:59.345140 best_step = 14
6476 11:05:59.345252
6477 11:05:59.348043 ==
6478 11:05:59.351982 Dram Type= 6, Freq= 0, CH_0, rank 0
6479 11:05:59.354357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 11:05:59.354482 ==
6481 11:05:59.354582 RX Vref Scan: 1
6482 11:05:59.354681
6483 11:05:59.357752 RX Vref 0 -> 0, step: 1
6484 11:05:59.357833
6485 11:05:59.361544 RX Delay -343 -> 252, step: 8
6486 11:05:59.361682
6487 11:05:59.365012 Set Vref, RX VrefLevel [Byte0]: 52
6488 11:05:59.367760 [Byte1]: 50
6489 11:05:59.371741
6490 11:05:59.371875 Final RX Vref Byte 0 = 52 to rank0
6491 11:05:59.375137 Final RX Vref Byte 1 = 50 to rank0
6492 11:05:59.378372 Final RX Vref Byte 0 = 52 to rank1
6493 11:05:59.381521 Final RX Vref Byte 1 = 50 to rank1==
6494 11:05:59.384953 Dram Type= 6, Freq= 0, CH_0, rank 0
6495 11:05:59.391534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 11:05:59.391668 ==
6497 11:05:59.391801 DQS Delay:
6498 11:05:59.391920 DQS0 = 44, DQS1 = 60
6499 11:05:59.395350 DQM Delay:
6500 11:05:59.395486 DQM0 = 11, DQM1 = 14
6501 11:05:59.398529 DQ Delay:
6502 11:05:59.401612 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6503 11:05:59.401746 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6504 11:05:59.405679 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6505 11:05:59.408478 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =28
6506 11:05:59.408614
6507 11:05:59.408744
6508 11:05:59.418504 [DQSOSCAuto] RK0, (LSB)MR18= 0x814f, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6509 11:05:59.421610 CH0 RK0: MR19=C0C, MR18=814F
6510 11:05:59.428685 CH0_RK0: MR19=0xC0C, MR18=0x814F, DQSOSC=393, MR23=63, INC=382, DEC=254
6511 11:05:59.428826 ==
6512 11:05:59.431515 Dram Type= 6, Freq= 0, CH_0, rank 1
6513 11:05:59.434793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6514 11:05:59.434928 ==
6515 11:05:59.438154 [Gating] SW mode calibration
6516 11:05:59.444825 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6517 11:05:59.448182 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6518 11:05:59.455173 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6519 11:05:59.459018 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6520 11:05:59.462000 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6521 11:05:59.468289 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6522 11:05:59.471849 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6523 11:05:59.476150 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6524 11:05:59.482017 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6525 11:05:59.485448 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6526 11:05:59.488419 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6527 11:05:59.492133 Total UI for P1: 0, mck2ui 16
6528 11:05:59.495400 best dqsien dly found for B0: ( 0, 14, 24)
6529 11:05:59.498183 Total UI for P1: 0, mck2ui 16
6530 11:05:59.501485 best dqsien dly found for B1: ( 0, 14, 24)
6531 11:05:59.504916 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6532 11:05:59.508476 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6533 11:05:59.508584
6534 11:05:59.514803 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6535 11:05:59.518451 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6536 11:05:59.518576 [Gating] SW calibration Done
6537 11:05:59.521549 ==
6538 11:05:59.524803 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 11:05:59.528308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 11:05:59.528433 ==
6541 11:05:59.528550 RX Vref Scan: 0
6542 11:05:59.528657
6543 11:05:59.531373 RX Vref 0 -> 0, step: 1
6544 11:05:59.531519
6545 11:05:59.534749 RX Delay -410 -> 252, step: 16
6546 11:05:59.538531 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6547 11:05:59.541424 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6548 11:05:59.548323 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6549 11:05:59.551601 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6550 11:05:59.554938 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6551 11:05:59.558407 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6552 11:05:59.564905 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6553 11:05:59.568422 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6554 11:05:59.571755 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6555 11:05:59.575136 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6556 11:05:59.581438 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6557 11:05:59.585645 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6558 11:05:59.589417 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6559 11:05:59.591997 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6560 11:05:59.598468 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6561 11:05:59.601435 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6562 11:05:59.601544 ==
6563 11:05:59.604980 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 11:05:59.608185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 11:05:59.608324 ==
6566 11:05:59.612101 DQS Delay:
6567 11:05:59.612230 DQS0 = 43, DQS1 = 51
6568 11:05:59.615309 DQM Delay:
6569 11:05:59.615441 DQM0 = 11, DQM1 = 10
6570 11:05:59.615569 DQ Delay:
6571 11:05:59.618580 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6572 11:05:59.621911 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6573 11:05:59.625067 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6574 11:05:59.628624 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6575 11:05:59.628749
6576 11:05:59.628876
6577 11:05:59.628990 ==
6578 11:05:59.631761 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 11:05:59.635092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 11:05:59.635223 ==
6581 11:05:59.638498
6582 11:05:59.638639
6583 11:05:59.638755 TX Vref Scan disable
6584 11:05:59.641879 == TX Byte 0 ==
6585 11:05:59.645411 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6586 11:05:59.648809 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6587 11:05:59.651740 == TX Byte 1 ==
6588 11:05:59.655080 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6589 11:05:59.658902 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6590 11:05:59.659012 ==
6591 11:05:59.661880 Dram Type= 6, Freq= 0, CH_0, rank 1
6592 11:05:59.665162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6593 11:05:59.668504 ==
6594 11:05:59.668585
6595 11:05:59.668646
6596 11:05:59.668715 TX Vref Scan disable
6597 11:05:59.671860 == TX Byte 0 ==
6598 11:05:59.675527 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6599 11:05:59.678340 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6600 11:05:59.681502 == TX Byte 1 ==
6601 11:05:59.684907 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6602 11:05:59.688443 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6603 11:05:59.688525
6604 11:05:59.688590 [DATLAT]
6605 11:05:59.691507 Freq=400, CH0 RK1
6606 11:05:59.691590
6607 11:05:59.695141 DATLAT Default: 0xe
6608 11:05:59.695283 0, 0xFFFF, sum = 0
6609 11:05:59.698097 1, 0xFFFF, sum = 0
6610 11:05:59.698228 2, 0xFFFF, sum = 0
6611 11:05:59.701373 3, 0xFFFF, sum = 0
6612 11:05:59.701510 4, 0xFFFF, sum = 0
6613 11:05:59.705131 5, 0xFFFF, sum = 0
6614 11:05:59.705267 6, 0xFFFF, sum = 0
6615 11:05:59.708357 7, 0xFFFF, sum = 0
6616 11:05:59.708442 8, 0xFFFF, sum = 0
6617 11:05:59.711842 9, 0xFFFF, sum = 0
6618 11:05:59.711926 10, 0xFFFF, sum = 0
6619 11:05:59.715052 11, 0xFFFF, sum = 0
6620 11:05:59.715136 12, 0xFFFF, sum = 0
6621 11:05:59.718567 13, 0x0, sum = 1
6622 11:05:59.718701 14, 0x0, sum = 2
6623 11:05:59.721921 15, 0x0, sum = 3
6624 11:05:59.722046 16, 0x0, sum = 4
6625 11:05:59.724972 best_step = 14
6626 11:05:59.725087
6627 11:05:59.725186 ==
6628 11:05:59.728340 Dram Type= 6, Freq= 0, CH_0, rank 1
6629 11:05:59.731400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 11:05:59.731484 ==
6631 11:05:59.735082 RX Vref Scan: 0
6632 11:05:59.735206
6633 11:05:59.735318 RX Vref 0 -> 0, step: 1
6634 11:05:59.735439
6635 11:05:59.738090 RX Delay -343 -> 252, step: 8
6636 11:05:59.745786 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6637 11:05:59.749008 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6638 11:05:59.752513 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6639 11:05:59.755803 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6640 11:05:59.762709 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6641 11:05:59.766143 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6642 11:05:59.769307 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6643 11:05:59.772543 iDelay=217, Bit 7, Center -24 (-263 ~ 216) 480
6644 11:05:59.779219 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6645 11:05:59.782704 iDelay=217, Bit 9, Center -56 (-295 ~ 184) 480
6646 11:05:59.786079 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6647 11:05:59.789561 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6648 11:05:59.796066 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6649 11:05:59.799115 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6650 11:05:59.802477 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6651 11:05:59.809358 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6652 11:05:59.809498 ==
6653 11:05:59.812645 Dram Type= 6, Freq= 0, CH_0, rank 1
6654 11:05:59.815981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 11:05:59.816106 ==
6656 11:05:59.816230 DQS Delay:
6657 11:05:59.819484 DQS0 = 48, DQS1 = 60
6658 11:05:59.819618 DQM Delay:
6659 11:05:59.822608 DQM0 = 14, DQM1 = 13
6660 11:05:59.822743 DQ Delay:
6661 11:05:59.826382 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6662 11:05:59.830363 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =24
6663 11:05:59.832560 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6664 11:05:59.835927 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6665 11:05:59.836066
6666 11:05:59.836182
6667 11:05:59.842662 [DQSOSCAuto] RK1, (LSB)MR18= 0x9569, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6668 11:05:59.845911 CH0 RK1: MR19=C0C, MR18=9569
6669 11:05:59.852573 CH0_RK1: MR19=0xC0C, MR18=0x9569, DQSOSC=391, MR23=63, INC=386, DEC=257
6670 11:05:59.855738 [RxdqsGatingPostProcess] freq 400
6671 11:05:59.859029 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6672 11:05:59.862805 best DQS0 dly(2T, 0.5T) = (0, 10)
6673 11:05:59.865805 best DQS1 dly(2T, 0.5T) = (0, 10)
6674 11:05:59.869458 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6675 11:05:59.872394 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6676 11:05:59.876201 best DQS0 dly(2T, 0.5T) = (0, 10)
6677 11:05:59.879604 best DQS1 dly(2T, 0.5T) = (0, 10)
6678 11:05:59.882962 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6679 11:05:59.886287 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6680 11:05:59.889693 Pre-setting of DQS Precalculation
6681 11:05:59.892590 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6682 11:05:59.892727 ==
6683 11:05:59.896381 Dram Type= 6, Freq= 0, CH_1, rank 0
6684 11:05:59.902660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 11:05:59.902800 ==
6686 11:05:59.906082 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6687 11:05:59.912697 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6688 11:05:59.916138 [CA 0] Center 36 (8~64) winsize 57
6689 11:05:59.919445 [CA 1] Center 36 (8~64) winsize 57
6690 11:05:59.922759 [CA 2] Center 36 (8~64) winsize 57
6691 11:05:59.926310 [CA 3] Center 36 (8~64) winsize 57
6692 11:05:59.929747 [CA 4] Center 36 (8~64) winsize 57
6693 11:05:59.933226 [CA 5] Center 36 (8~64) winsize 57
6694 11:05:59.933350
6695 11:05:59.936564 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6696 11:05:59.936694
6697 11:05:59.939435 [CATrainingPosCal] consider 1 rank data
6698 11:05:59.943231 u2DelayCellTimex100 = 270/100 ps
6699 11:05:59.946135 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 11:05:59.949763 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 11:05:59.953076 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 11:05:59.956495 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 11:05:59.960029 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 11:05:59.962851 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 11:05:59.962980
6706 11:05:59.969314 CA PerBit enable=1, Macro0, CA PI delay=36
6707 11:05:59.969444
6708 11:05:59.969571 [CBTSetCACLKResult] CA Dly = 36
6709 11:05:59.973016 CS Dly: 1 (0~32)
6710 11:05:59.973154 ==
6711 11:05:59.976256 Dram Type= 6, Freq= 0, CH_1, rank 1
6712 11:05:59.979853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 11:05:59.979989 ==
6714 11:05:59.986065 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6715 11:05:59.992769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6716 11:05:59.996558 [CA 0] Center 36 (8~64) winsize 57
6717 11:05:59.999879 [CA 1] Center 36 (8~64) winsize 57
6718 11:06:00.002939 [CA 2] Center 36 (8~64) winsize 57
6719 11:06:00.003065 [CA 3] Center 36 (8~64) winsize 57
6720 11:06:00.006313 [CA 4] Center 36 (8~64) winsize 57
6721 11:06:00.009833 [CA 5] Center 36 (8~64) winsize 57
6722 11:06:00.009969
6723 11:06:00.013194 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6724 11:06:00.016710
6725 11:06:00.019577 [CATrainingPosCal] consider 2 rank data
6726 11:06:00.019714 u2DelayCellTimex100 = 270/100 ps
6727 11:06:00.026623 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6728 11:06:00.030027 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 11:06:00.033076 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6730 11:06:00.036399 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6731 11:06:00.039599 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6732 11:06:00.043059 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 11:06:00.043193
6734 11:06:00.046757 CA PerBit enable=1, Macro0, CA PI delay=36
6735 11:06:00.046892
6736 11:06:00.049510 [CBTSetCACLKResult] CA Dly = 36
6737 11:06:00.052941 CS Dly: 1 (0~32)
6738 11:06:00.053077
6739 11:06:00.056424 ----->DramcWriteLeveling(PI) begin...
6740 11:06:00.056560 ==
6741 11:06:00.059494 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 11:06:00.063143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 11:06:00.063271 ==
6744 11:06:00.066262 Write leveling (Byte 0): 40 => 8
6745 11:06:00.069522 Write leveling (Byte 1): 40 => 8
6746 11:06:00.072969 DramcWriteLeveling(PI) end<-----
6747 11:06:00.073100
6748 11:06:00.073222 ==
6749 11:06:00.076151 Dram Type= 6, Freq= 0, CH_1, rank 0
6750 11:06:00.080128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6751 11:06:00.080255 ==
6752 11:06:00.082755 [Gating] SW mode calibration
6753 11:06:00.090139 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6754 11:06:00.096253 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6755 11:06:00.099279 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6756 11:06:00.102849 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6757 11:06:00.109675 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6758 11:06:00.112721 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6759 11:06:00.116075 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6760 11:06:00.119664 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6761 11:06:00.126622 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6762 11:06:00.129807 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6763 11:06:00.133057 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6764 11:06:00.136386 Total UI for P1: 0, mck2ui 16
6765 11:06:00.139475 best dqsien dly found for B0: ( 0, 14, 24)
6766 11:06:00.143238 Total UI for P1: 0, mck2ui 16
6767 11:06:00.146134 best dqsien dly found for B1: ( 0, 14, 24)
6768 11:06:00.149530 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6769 11:06:00.153187 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6770 11:06:00.156537
6771 11:06:00.159692 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6772 11:06:00.163584 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6773 11:06:00.166533 [Gating] SW calibration Done
6774 11:06:00.166656 ==
6775 11:06:00.169701 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 11:06:00.173411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 11:06:00.173502 ==
6778 11:06:00.173568 RX Vref Scan: 0
6779 11:06:00.173635
6780 11:06:00.176106 RX Vref 0 -> 0, step: 1
6781 11:06:00.176180
6782 11:06:00.179724 RX Delay -410 -> 252, step: 16
6783 11:06:00.183265 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6784 11:06:00.189616 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6785 11:06:00.192882 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6786 11:06:00.196573 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6787 11:06:00.199428 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6788 11:06:00.206148 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6789 11:06:00.209406 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6790 11:06:00.212872 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6791 11:06:00.216472 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6792 11:06:00.223088 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6793 11:06:00.226204 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6794 11:06:00.230194 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6795 11:06:00.232861 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6796 11:06:00.239418 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6797 11:06:00.243370 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6798 11:06:00.246604 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6799 11:06:00.246724 ==
6800 11:06:00.249571 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 11:06:00.252758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 11:06:00.252866 ==
6803 11:06:00.256213 DQS Delay:
6804 11:06:00.256317 DQS0 = 51, DQS1 = 59
6805 11:06:00.259615 DQM Delay:
6806 11:06:00.259719 DQM0 = 19, DQM1 = 16
6807 11:06:00.262834 DQ Delay:
6808 11:06:00.262916 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6809 11:06:00.266248 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6810 11:06:00.269619 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6811 11:06:00.273040 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6812 11:06:00.273172
6813 11:06:00.273301
6814 11:06:00.276287 ==
6815 11:06:00.276415 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 11:06:00.283452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 11:06:00.283588 ==
6818 11:06:00.283714
6819 11:06:00.283835
6820 11:06:00.286245 TX Vref Scan disable
6821 11:06:00.286381 == TX Byte 0 ==
6822 11:06:00.289991 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6823 11:06:00.296421 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6824 11:06:00.296559 == TX Byte 1 ==
6825 11:06:00.299557 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6826 11:06:00.303620 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6827 11:06:00.306400 ==
6828 11:06:00.309764 Dram Type= 6, Freq= 0, CH_1, rank 0
6829 11:06:00.313080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 11:06:00.313217 ==
6831 11:06:00.313336
6832 11:06:00.313463
6833 11:06:00.316449 TX Vref Scan disable
6834 11:06:00.316573 == TX Byte 0 ==
6835 11:06:00.319686 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6836 11:06:00.326334 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6837 11:06:00.326461 == TX Byte 1 ==
6838 11:06:00.329693 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6839 11:06:00.333048 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6840 11:06:00.336442
6841 11:06:00.336566 [DATLAT]
6842 11:06:00.336695 Freq=400, CH1 RK0
6843 11:06:00.336813
6844 11:06:00.339679 DATLAT Default: 0xf
6845 11:06:00.339812 0, 0xFFFF, sum = 0
6846 11:06:00.343111 1, 0xFFFF, sum = 0
6847 11:06:00.343251 2, 0xFFFF, sum = 0
6848 11:06:00.346319 3, 0xFFFF, sum = 0
6849 11:06:00.346468 4, 0xFFFF, sum = 0
6850 11:06:00.349659 5, 0xFFFF, sum = 0
6851 11:06:00.349803 6, 0xFFFF, sum = 0
6852 11:06:00.353067 7, 0xFFFF, sum = 0
6853 11:06:00.353209 8, 0xFFFF, sum = 0
6854 11:06:00.356763 9, 0xFFFF, sum = 0
6855 11:06:00.360025 10, 0xFFFF, sum = 0
6856 11:06:00.360167 11, 0xFFFF, sum = 0
6857 11:06:00.362828 12, 0xFFFF, sum = 0
6858 11:06:00.362963 13, 0x0, sum = 1
6859 11:06:00.366486 14, 0x0, sum = 2
6860 11:06:00.366625 15, 0x0, sum = 3
6861 11:06:00.370013 16, 0x0, sum = 4
6862 11:06:00.370145 best_step = 14
6863 11:06:00.370260
6864 11:06:00.370374 ==
6865 11:06:00.373286 Dram Type= 6, Freq= 0, CH_1, rank 0
6866 11:06:00.376080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 11:06:00.376202 ==
6868 11:06:00.379407 RX Vref Scan: 1
6869 11:06:00.379495
6870 11:06:00.382920 RX Vref 0 -> 0, step: 1
6871 11:06:00.383066
6872 11:06:00.383181 RX Delay -359 -> 252, step: 8
6873 11:06:00.383307
6874 11:06:00.386277 Set Vref, RX VrefLevel [Byte0]: 57
6875 11:06:00.389625 [Byte1]: 49
6876 11:06:00.395005
6877 11:06:00.395140 Final RX Vref Byte 0 = 57 to rank0
6878 11:06:00.398417 Final RX Vref Byte 1 = 49 to rank0
6879 11:06:00.401897 Final RX Vref Byte 0 = 57 to rank1
6880 11:06:00.405087 Final RX Vref Byte 1 = 49 to rank1==
6881 11:06:00.408396 Dram Type= 6, Freq= 0, CH_1, rank 0
6882 11:06:00.415399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 11:06:00.415491 ==
6884 11:06:00.415558 DQS Delay:
6885 11:06:00.415624 DQS0 = 48, DQS1 = 60
6886 11:06:00.418616 DQM Delay:
6887 11:06:00.418729 DQM0 = 12, DQM1 = 13
6888 11:06:00.421937 DQ Delay:
6889 11:06:00.422044 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6890 11:06:00.425174 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6891 11:06:00.429115 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6892 11:06:00.431733 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6893 11:06:00.431810
6894 11:06:00.431873
6895 11:06:00.442035 [DQSOSCAuto] RK0, (LSB)MR18= 0x832a, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6896 11:06:00.445000 CH1 RK0: MR19=C0C, MR18=832A
6897 11:06:00.451893 CH1_RK0: MR19=0xC0C, MR18=0x832A, DQSOSC=393, MR23=63, INC=382, DEC=254
6898 11:06:00.452026 ==
6899 11:06:00.455296 Dram Type= 6, Freq= 0, CH_1, rank 1
6900 11:06:00.458782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6901 11:06:00.458916 ==
6902 11:06:00.461678 [Gating] SW mode calibration
6903 11:06:00.468448 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6904 11:06:00.471776 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6905 11:06:00.478866 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6906 11:06:00.482569 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6907 11:06:00.485444 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6908 11:06:00.492126 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6909 11:06:00.495376 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6910 11:06:00.498252 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6911 11:06:00.505492 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6912 11:06:00.508754 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6913 11:06:00.511726 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6914 11:06:00.515317 Total UI for P1: 0, mck2ui 16
6915 11:06:00.518728 best dqsien dly found for B0: ( 0, 14, 24)
6916 11:06:00.521972 Total UI for P1: 0, mck2ui 16
6917 11:06:00.525195 best dqsien dly found for B1: ( 0, 14, 24)
6918 11:06:00.528415 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6919 11:06:00.531860 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6920 11:06:00.531936
6921 11:06:00.535048 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6922 11:06:00.541715 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6923 11:06:00.541799 [Gating] SW calibration Done
6924 11:06:00.545173 ==
6925 11:06:00.545256 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 11:06:00.551908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 11:06:00.551992 ==
6928 11:06:00.552092 RX Vref Scan: 0
6929 11:06:00.552182
6930 11:06:00.555239 RX Vref 0 -> 0, step: 1
6931 11:06:00.555311
6932 11:06:00.558420 RX Delay -410 -> 252, step: 16
6933 11:06:00.561577 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6934 11:06:00.565322 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6935 11:06:00.571388 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6936 11:06:00.574913 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6937 11:06:00.578366 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6938 11:06:00.581601 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6939 11:06:00.588736 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6940 11:06:00.591526 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6941 11:06:00.594785 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6942 11:06:00.598091 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6943 11:06:00.605294 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6944 11:06:00.608375 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6945 11:06:00.611599 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6946 11:06:00.615216 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6947 11:06:00.621794 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6948 11:06:00.624915 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6949 11:06:00.624996 ==
6950 11:06:00.628023 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 11:06:00.631575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 11:06:00.631660 ==
6953 11:06:00.635158 DQS Delay:
6954 11:06:00.635234 DQS0 = 43, DQS1 = 51
6955 11:06:00.638276 DQM Delay:
6956 11:06:00.638375 DQM0 = 9, DQM1 = 10
6957 11:06:00.638459 DQ Delay:
6958 11:06:00.641593 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6959 11:06:00.645011 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6960 11:06:00.648240 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6961 11:06:00.651638 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6962 11:06:00.651772
6963 11:06:00.651893
6964 11:06:00.652016 ==
6965 11:06:00.655045 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 11:06:00.658911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 11:06:00.661469 ==
6968 11:06:00.661550
6969 11:06:00.661614
6970 11:06:00.661673 TX Vref Scan disable
6971 11:06:00.664618 == TX Byte 0 ==
6972 11:06:00.668002 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6973 11:06:00.671273 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6974 11:06:00.674738 == TX Byte 1 ==
6975 11:06:00.678147 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6976 11:06:00.681413 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6977 11:06:00.681498 ==
6978 11:06:00.685090 Dram Type= 6, Freq= 0, CH_1, rank 1
6979 11:06:00.688403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6980 11:06:00.691469 ==
6981 11:06:00.691592
6982 11:06:00.691709
6983 11:06:00.691828 TX Vref Scan disable
6984 11:06:00.694863 == TX Byte 0 ==
6985 11:06:00.698298 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6986 11:06:00.701513 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6987 11:06:00.704983 == TX Byte 1 ==
6988 11:06:00.708891 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6989 11:06:00.711746 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6990 11:06:00.711876
6991 11:06:00.711990 [DATLAT]
6992 11:06:00.715277 Freq=400, CH1 RK1
6993 11:06:00.715409
6994 11:06:00.718341 DATLAT Default: 0xe
6995 11:06:00.718474 0, 0xFFFF, sum = 0
6996 11:06:00.721967 1, 0xFFFF, sum = 0
6997 11:06:00.722092 2, 0xFFFF, sum = 0
6998 11:06:00.725067 3, 0xFFFF, sum = 0
6999 11:06:00.725195 4, 0xFFFF, sum = 0
7000 11:06:00.728181 5, 0xFFFF, sum = 0
7001 11:06:00.728307 6, 0xFFFF, sum = 0
7002 11:06:00.731585 7, 0xFFFF, sum = 0
7003 11:06:00.731712 8, 0xFFFF, sum = 0
7004 11:06:00.734992 9, 0xFFFF, sum = 0
7005 11:06:00.735123 10, 0xFFFF, sum = 0
7006 11:06:00.738052 11, 0xFFFF, sum = 0
7007 11:06:00.738187 12, 0xFFFF, sum = 0
7008 11:06:00.741451 13, 0x0, sum = 1
7009 11:06:00.741574 14, 0x0, sum = 2
7010 11:06:00.745167 15, 0x0, sum = 3
7011 11:06:00.745296 16, 0x0, sum = 4
7012 11:06:00.748191 best_step = 14
7013 11:06:00.748316
7014 11:06:00.748433 ==
7015 11:06:00.751370 Dram Type= 6, Freq= 0, CH_1, rank 1
7016 11:06:00.754579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7017 11:06:00.754711 ==
7018 11:06:00.758070 RX Vref Scan: 0
7019 11:06:00.758189
7020 11:06:00.758299 RX Vref 0 -> 0, step: 1
7021 11:06:00.758429
7022 11:06:00.761673 RX Delay -343 -> 252, step: 8
7023 11:06:00.769054 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7024 11:06:00.772500 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7025 11:06:00.775992 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7026 11:06:00.779231 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
7027 11:06:00.785700 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
7028 11:06:00.789027 iDelay=217, Bit 5, Center -24 (-263 ~ 216) 480
7029 11:06:00.792129 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7030 11:06:00.795662 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7031 11:06:00.802548 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7032 11:06:00.805889 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7033 11:06:00.808851 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
7034 11:06:00.812510 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7035 11:06:00.820026 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
7036 11:06:00.822880 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7037 11:06:00.826143 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7038 11:06:00.829240 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
7039 11:06:00.832501 ==
7040 11:06:00.835955 Dram Type= 6, Freq= 0, CH_1, rank 1
7041 11:06:00.839735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7042 11:06:00.839864 ==
7043 11:06:00.839982 DQS Delay:
7044 11:06:00.842258 DQS0 = 52, DQS1 = 56
7045 11:06:00.842376 DQM Delay:
7046 11:06:00.845688 DQM0 = 13, DQM1 = 10
7047 11:06:00.845813 DQ Delay:
7048 11:06:00.849312 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7049 11:06:00.852458 DQ4 =12, DQ5 =28, DQ6 =24, DQ7 =8
7050 11:06:00.855927 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7051 11:06:00.859708 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
7052 11:06:00.859835
7053 11:06:00.859948
7054 11:06:00.865756 [DQSOSCAuto] RK1, (LSB)MR18= 0x768d, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 394 ps
7055 11:06:00.869316 CH1 RK1: MR19=C0C, MR18=768D
7056 11:06:00.875888 CH1_RK1: MR19=0xC0C, MR18=0x768D, DQSOSC=392, MR23=63, INC=384, DEC=256
7057 11:06:00.879127 [RxdqsGatingPostProcess] freq 400
7058 11:06:00.882344 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7059 11:06:00.886099 best DQS0 dly(2T, 0.5T) = (0, 10)
7060 11:06:00.889350 best DQS1 dly(2T, 0.5T) = (0, 10)
7061 11:06:00.892991 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7062 11:06:00.896344 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7063 11:06:00.899430 best DQS0 dly(2T, 0.5T) = (0, 10)
7064 11:06:00.902350 best DQS1 dly(2T, 0.5T) = (0, 10)
7065 11:06:00.905898 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7066 11:06:00.909379 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7067 11:06:00.912791 Pre-setting of DQS Precalculation
7068 11:06:00.915776 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7069 11:06:00.922957 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7070 11:06:00.932278 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7071 11:06:00.932362
7072 11:06:00.932426
7073 11:06:00.935718 [Calibration Summary] 800 Mbps
7074 11:06:00.935791 CH 0, Rank 0
7075 11:06:00.939281 SW Impedance : PASS
7076 11:06:00.939440 DUTY Scan : NO K
7077 11:06:00.942704 ZQ Calibration : PASS
7078 11:06:00.945845 Jitter Meter : NO K
7079 11:06:00.945928 CBT Training : PASS
7080 11:06:00.949291 Write leveling : PASS
7081 11:06:00.949367 RX DQS gating : PASS
7082 11:06:00.952480 RX DQ/DQS(RDDQC) : PASS
7083 11:06:00.955876 TX DQ/DQS : PASS
7084 11:06:00.955959 RX DATLAT : PASS
7085 11:06:00.959757 RX DQ/DQS(Engine): PASS
7086 11:06:00.962574 TX OE : NO K
7087 11:06:00.962653 All Pass.
7088 11:06:00.962750
7089 11:06:00.962846 CH 0, Rank 1
7090 11:06:00.965974 SW Impedance : PASS
7091 11:06:00.969363 DUTY Scan : NO K
7092 11:06:00.969446 ZQ Calibration : PASS
7093 11:06:00.972807 Jitter Meter : NO K
7094 11:06:00.975749 CBT Training : PASS
7095 11:06:00.975848 Write leveling : NO K
7096 11:06:00.979189 RX DQS gating : PASS
7097 11:06:00.982342 RX DQ/DQS(RDDQC) : PASS
7098 11:06:00.982464 TX DQ/DQS : PASS
7099 11:06:00.986314 RX DATLAT : PASS
7100 11:06:00.986444 RX DQ/DQS(Engine): PASS
7101 11:06:00.989450 TX OE : NO K
7102 11:06:00.989523 All Pass.
7103 11:06:00.989602
7104 11:06:00.992380 CH 1, Rank 0
7105 11:06:00.992459 SW Impedance : PASS
7106 11:06:00.996072 DUTY Scan : NO K
7107 11:06:00.999465 ZQ Calibration : PASS
7108 11:06:00.999541 Jitter Meter : NO K
7109 11:06:01.002543 CBT Training : PASS
7110 11:06:01.005689 Write leveling : PASS
7111 11:06:01.005767 RX DQS gating : PASS
7112 11:06:01.009478 RX DQ/DQS(RDDQC) : PASS
7113 11:06:01.012416 TX DQ/DQS : PASS
7114 11:06:01.012493 RX DATLAT : PASS
7115 11:06:01.015772 RX DQ/DQS(Engine): PASS
7116 11:06:01.019421 TX OE : NO K
7117 11:06:01.019513 All Pass.
7118 11:06:01.019626
7119 11:06:01.019703 CH 1, Rank 1
7120 11:06:01.022729 SW Impedance : PASS
7121 11:06:01.025986 DUTY Scan : NO K
7122 11:06:01.026101 ZQ Calibration : PASS
7123 11:06:01.029258 Jitter Meter : NO K
7124 11:06:01.029411 CBT Training : PASS
7125 11:06:01.032445 Write leveling : NO K
7126 11:06:01.036669 RX DQS gating : PASS
7127 11:06:01.036746 RX DQ/DQS(RDDQC) : PASS
7128 11:06:01.039681 TX DQ/DQS : PASS
7129 11:06:01.042906 RX DATLAT : PASS
7130 11:06:01.042981 RX DQ/DQS(Engine): PASS
7131 11:06:01.046280 TX OE : NO K
7132 11:06:01.046378 All Pass.
7133 11:06:01.046492
7134 11:06:01.049760 DramC Write-DBI off
7135 11:06:01.052701 PER_BANK_REFRESH: Hybrid Mode
7136 11:06:01.052797 TX_TRACKING: ON
7137 11:06:01.062796 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7138 11:06:01.066165 [FAST_K] Save calibration result to emmc
7139 11:06:01.069284 dramc_set_vcore_voltage set vcore to 725000
7140 11:06:01.072655 Read voltage for 1600, 0
7141 11:06:01.072730 Vio18 = 0
7142 11:06:01.072791 Vcore = 725000
7143 11:06:01.075889 Vdram = 0
7144 11:06:01.075962 Vddq = 0
7145 11:06:01.076023 Vmddr = 0
7146 11:06:01.083080 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7147 11:06:01.085896 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7148 11:06:01.089140 MEM_TYPE=3, freq_sel=13
7149 11:06:01.093017 sv_algorithm_assistance_LP4_3733
7150 11:06:01.095938 ============ PULL DRAM RESETB DOWN ============
7151 11:06:01.100063 ========== PULL DRAM RESETB DOWN end =========
7152 11:06:01.105907 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7153 11:06:01.109421 ===================================
7154 11:06:01.109507 LPDDR4 DRAM CONFIGURATION
7155 11:06:01.112684 ===================================
7156 11:06:01.116019 EX_ROW_EN[0] = 0x0
7157 11:06:01.119463 EX_ROW_EN[1] = 0x0
7158 11:06:01.119548 LP4Y_EN = 0x0
7159 11:06:01.122825 WORK_FSP = 0x1
7160 11:06:01.122910 WL = 0x5
7161 11:06:01.126067 RL = 0x5
7162 11:06:01.126153 BL = 0x2
7163 11:06:01.129645 RPST = 0x0
7164 11:06:01.129731 RD_PRE = 0x0
7165 11:06:01.132375 WR_PRE = 0x1
7166 11:06:01.132459 WR_PST = 0x1
7167 11:06:01.135790 DBI_WR = 0x0
7168 11:06:01.135875 DBI_RD = 0x0
7169 11:06:01.139365 OTF = 0x1
7170 11:06:01.142518 ===================================
7171 11:06:01.146201 ===================================
7172 11:06:01.146307 ANA top config
7173 11:06:01.149431 ===================================
7174 11:06:01.152489 DLL_ASYNC_EN = 0
7175 11:06:01.155918 ALL_SLAVE_EN = 0
7176 11:06:01.159735 NEW_RANK_MODE = 1
7177 11:06:01.159814 DLL_IDLE_MODE = 1
7178 11:06:01.162496 LP45_APHY_COMB_EN = 1
7179 11:06:01.165851 TX_ODT_DIS = 0
7180 11:06:01.169112 NEW_8X_MODE = 1
7181 11:06:01.172836 ===================================
7182 11:06:01.175525 ===================================
7183 11:06:01.179201 data_rate = 3200
7184 11:06:01.179286 CKR = 1
7185 11:06:01.182767 DQ_P2S_RATIO = 8
7186 11:06:01.185511 ===================================
7187 11:06:01.188903 CA_P2S_RATIO = 8
7188 11:06:01.192703 DQ_CA_OPEN = 0
7189 11:06:01.195962 DQ_SEMI_OPEN = 0
7190 11:06:01.199095 CA_SEMI_OPEN = 0
7191 11:06:01.199181 CA_FULL_RATE = 0
7192 11:06:01.202184 DQ_CKDIV4_EN = 0
7193 11:06:01.205964 CA_CKDIV4_EN = 0
7194 11:06:01.209139 CA_PREDIV_EN = 0
7195 11:06:01.212269 PH8_DLY = 12
7196 11:06:01.215693 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7197 11:06:01.215770 DQ_AAMCK_DIV = 4
7198 11:06:01.218912 CA_AAMCK_DIV = 4
7199 11:06:01.223226 CA_ADMCK_DIV = 4
7200 11:06:01.225766 DQ_TRACK_CA_EN = 0
7201 11:06:01.228977 CA_PICK = 1600
7202 11:06:01.232646 CA_MCKIO = 1600
7203 11:06:01.232720 MCKIO_SEMI = 0
7204 11:06:01.236036 PLL_FREQ = 3068
7205 11:06:01.239123 DQ_UI_PI_RATIO = 32
7206 11:06:01.242440 CA_UI_PI_RATIO = 0
7207 11:06:01.245953 ===================================
7208 11:06:01.249077 ===================================
7209 11:06:01.252637 memory_type:LPDDR4
7210 11:06:01.252718 GP_NUM : 10
7211 11:06:01.256004 SRAM_EN : 1
7212 11:06:01.258834 MD32_EN : 0
7213 11:06:01.262329 ===================================
7214 11:06:01.262437 [ANA_INIT] >>>>>>>>>>>>>>
7215 11:06:01.265856 <<<<<< [CONFIGURE PHASE]: ANA_TX
7216 11:06:01.269130 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7217 11:06:01.272765 ===================================
7218 11:06:01.275431 data_rate = 3200,PCW = 0X7600
7219 11:06:01.279138 ===================================
7220 11:06:01.282343 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7221 11:06:01.289043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7222 11:06:01.292368 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7223 11:06:01.298762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7224 11:06:01.302123 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7225 11:06:01.306371 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7226 11:06:01.306469 [ANA_INIT] flow start
7227 11:06:01.309107 [ANA_INIT] PLL >>>>>>>>
7228 11:06:01.312121 [ANA_INIT] PLL <<<<<<<<
7229 11:06:01.315356 [ANA_INIT] MIDPI >>>>>>>>
7230 11:06:01.315437 [ANA_INIT] MIDPI <<<<<<<<
7231 11:06:01.319274 [ANA_INIT] DLL >>>>>>>>
7232 11:06:01.322359 [ANA_INIT] DLL <<<<<<<<
7233 11:06:01.322483 [ANA_INIT] flow end
7234 11:06:01.325287 ============ LP4 DIFF to SE enter ============
7235 11:06:01.332472 ============ LP4 DIFF to SE exit ============
7236 11:06:01.332580 [ANA_INIT] <<<<<<<<<<<<<
7237 11:06:01.335981 [Flow] Enable top DCM control >>>>>
7238 11:06:01.338640 [Flow] Enable top DCM control <<<<<
7239 11:06:01.342325 Enable DLL master slave shuffle
7240 11:06:01.348764 ==============================================================
7241 11:06:01.348866 Gating Mode config
7242 11:06:01.355834 ==============================================================
7243 11:06:01.358863 Config description:
7244 11:06:01.365463 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7245 11:06:01.372145 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7246 11:06:01.378601 SELPH_MODE 0: By rank 1: By Phase
7247 11:06:01.385501 ==============================================================
7248 11:06:01.388530 GAT_TRACK_EN = 1
7249 11:06:01.388636 RX_GATING_MODE = 2
7250 11:06:01.392501 RX_GATING_TRACK_MODE = 2
7251 11:06:01.395406 SELPH_MODE = 1
7252 11:06:01.398936 PICG_EARLY_EN = 1
7253 11:06:01.402265 VALID_LAT_VALUE = 1
7254 11:06:01.409145 ==============================================================
7255 11:06:01.412191 Enter into Gating configuration >>>>
7256 11:06:01.415731 Exit from Gating configuration <<<<
7257 11:06:01.418801 Enter into DVFS_PRE_config >>>>>
7258 11:06:01.429373 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7259 11:06:01.432157 Exit from DVFS_PRE_config <<<<<
7260 11:06:01.435677 Enter into PICG configuration >>>>
7261 11:06:01.438866 Exit from PICG configuration <<<<
7262 11:06:01.442367 [RX_INPUT] configuration >>>>>
7263 11:06:01.442492 [RX_INPUT] configuration <<<<<
7264 11:06:01.449031 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7265 11:06:01.455805 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7266 11:06:01.458742 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7267 11:06:01.465735 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7268 11:06:01.471962 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7269 11:06:01.478830 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7270 11:06:01.482136 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7271 11:06:01.485542 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7272 11:06:01.492026 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7273 11:06:01.495809 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7274 11:06:01.499014 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7275 11:06:01.502756 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7276 11:06:01.505444 ===================================
7277 11:06:01.508754 LPDDR4 DRAM CONFIGURATION
7278 11:06:01.512627 ===================================
7279 11:06:01.515894 EX_ROW_EN[0] = 0x0
7280 11:06:01.516019 EX_ROW_EN[1] = 0x0
7281 11:06:01.518987 LP4Y_EN = 0x0
7282 11:06:01.519110 WORK_FSP = 0x1
7283 11:06:01.522057 WL = 0x5
7284 11:06:01.522180 RL = 0x5
7285 11:06:01.525583 BL = 0x2
7286 11:06:01.525709 RPST = 0x0
7287 11:06:01.529026 RD_PRE = 0x0
7288 11:06:01.529134 WR_PRE = 0x1
7289 11:06:01.532460 WR_PST = 0x1
7290 11:06:01.532565 DBI_WR = 0x0
7291 11:06:01.535517 DBI_RD = 0x0
7292 11:06:01.535619 OTF = 0x1
7293 11:06:01.538758 ===================================
7294 11:06:01.545767 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7295 11:06:01.549126 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7296 11:06:01.552481 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7297 11:06:01.556102 ===================================
7298 11:06:01.559226 LPDDR4 DRAM CONFIGURATION
7299 11:06:01.562153 ===================================
7300 11:06:01.565488 EX_ROW_EN[0] = 0x10
7301 11:06:01.565592 EX_ROW_EN[1] = 0x0
7302 11:06:01.568995 LP4Y_EN = 0x0
7303 11:06:01.569072 WORK_FSP = 0x1
7304 11:06:01.572018 WL = 0x5
7305 11:06:01.572098 RL = 0x5
7306 11:06:01.575675 BL = 0x2
7307 11:06:01.575756 RPST = 0x0
7308 11:06:01.578974 RD_PRE = 0x0
7309 11:06:01.579056 WR_PRE = 0x1
7310 11:06:01.582600 WR_PST = 0x1
7311 11:06:01.582682 DBI_WR = 0x0
7312 11:06:01.585442 DBI_RD = 0x0
7313 11:06:01.585522 OTF = 0x1
7314 11:06:01.588803 ===================================
7315 11:06:01.595497 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7316 11:06:01.595606 ==
7317 11:06:01.599078 Dram Type= 6, Freq= 0, CH_0, rank 0
7318 11:06:01.605023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7319 11:06:01.605130 ==
7320 11:06:01.605223 [Duty_Offset_Calibration]
7321 11:06:01.608509 B0:2 B1:-1 CA:1
7322 11:06:01.608608
7323 11:06:01.611770 [DutyScan_Calibration_Flow] k_type=0
7324 11:06:01.620202
7325 11:06:01.620307 ==CLK 0==
7326 11:06:01.623491 Final CLK duty delay cell = -4
7327 11:06:01.627971 [-4] MAX Duty = 5031%(X100), DQS PI = 6
7328 11:06:01.630592 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7329 11:06:01.633812 [-4] AVG Duty = 4937%(X100)
7330 11:06:01.633913
7331 11:06:01.637089 CH0 CLK Duty spec in!! Max-Min= 187%
7332 11:06:01.640634 [DutyScan_Calibration_Flow] ====Done====
7333 11:06:01.640735
7334 11:06:01.644150 [DutyScan_Calibration_Flow] k_type=1
7335 11:06:01.659594
7336 11:06:01.659705 ==DQS 0 ==
7337 11:06:01.663197 Final DQS duty delay cell = 0
7338 11:06:01.666194 [0] MAX Duty = 5125%(X100), DQS PI = 22
7339 11:06:01.669924 [0] MIN Duty = 5000%(X100), DQS PI = 14
7340 11:06:01.673239 [0] AVG Duty = 5062%(X100)
7341 11:06:01.673340
7342 11:06:01.673434 ==DQS 1 ==
7343 11:06:01.676460 Final DQS duty delay cell = -4
7344 11:06:01.679555 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7345 11:06:01.683188 [-4] MIN Duty = 5031%(X100), DQS PI = 20
7346 11:06:01.686144 [-4] AVG Duty = 5062%(X100)
7347 11:06:01.686246
7348 11:06:01.689952 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7349 11:06:01.690055
7350 11:06:01.693635 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7351 11:06:01.696360 [DutyScan_Calibration_Flow] ====Done====
7352 11:06:01.696465
7353 11:06:01.699623 [DutyScan_Calibration_Flow] k_type=3
7354 11:06:01.717057
7355 11:06:01.717169 ==DQM 0 ==
7356 11:06:01.720402 Final DQM duty delay cell = 0
7357 11:06:01.723848 [0] MAX Duty = 5000%(X100), DQS PI = 20
7358 11:06:01.727117 [0] MIN Duty = 4875%(X100), DQS PI = 6
7359 11:06:01.727246 [0] AVG Duty = 4937%(X100)
7360 11:06:01.730479
7361 11:06:01.730595 ==DQM 1 ==
7362 11:06:01.733656 Final DQM duty delay cell = 0
7363 11:06:01.736995 [0] MAX Duty = 5218%(X100), DQS PI = 58
7364 11:06:01.740379 [0] MIN Duty = 4969%(X100), DQS PI = 18
7365 11:06:01.740499 [0] AVG Duty = 5093%(X100)
7366 11:06:01.743519
7367 11:06:01.747034 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7368 11:06:01.747119
7369 11:06:01.750251 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7370 11:06:01.753498 [DutyScan_Calibration_Flow] ====Done====
7371 11:06:01.753600
7372 11:06:01.756848 [DutyScan_Calibration_Flow] k_type=2
7373 11:06:01.773512
7374 11:06:01.773594 ==DQ 0 ==
7375 11:06:01.776748 Final DQ duty delay cell = -4
7376 11:06:01.779936 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7377 11:06:01.783597 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7378 11:06:01.786798 [-4] AVG Duty = 4937%(X100)
7379 11:06:01.786878
7380 11:06:01.786941 ==DQ 1 ==
7381 11:06:01.789978 Final DQ duty delay cell = 0
7382 11:06:01.793411 [0] MAX Duty = 5031%(X100), DQS PI = 30
7383 11:06:01.796625 [0] MIN Duty = 4938%(X100), DQS PI = 2
7384 11:06:01.800237 [0] AVG Duty = 4984%(X100)
7385 11:06:01.800349
7386 11:06:01.803887 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7387 11:06:01.804004
7388 11:06:01.806609 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7389 11:06:01.810284 [DutyScan_Calibration_Flow] ====Done====
7390 11:06:01.810413 ==
7391 11:06:01.812971 Dram Type= 6, Freq= 0, CH_1, rank 0
7392 11:06:01.816552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7393 11:06:01.816674 ==
7394 11:06:01.819835 [Duty_Offset_Calibration]
7395 11:06:01.819916 B0:1 B1:1 CA:2
7396 11:06:01.819978
7397 11:06:01.823443 [DutyScan_Calibration_Flow] k_type=0
7398 11:06:01.833614
7399 11:06:01.833696 ==CLK 0==
7400 11:06:01.836872 Final CLK duty delay cell = 0
7401 11:06:01.840680 [0] MAX Duty = 5187%(X100), DQS PI = 24
7402 11:06:01.843781 [0] MIN Duty = 4938%(X100), DQS PI = 50
7403 11:06:01.846855 [0] AVG Duty = 5062%(X100)
7404 11:06:01.846969
7405 11:06:01.850990 CH1 CLK Duty spec in!! Max-Min= 249%
7406 11:06:01.853932 [DutyScan_Calibration_Flow] ====Done====
7407 11:06:01.854013
7408 11:06:01.856740 [DutyScan_Calibration_Flow] k_type=1
7409 11:06:01.873549
7410 11:06:01.873627 ==DQS 0 ==
7411 11:06:01.876749 Final DQS duty delay cell = 0
7412 11:06:01.879945 [0] MAX Duty = 5062%(X100), DQS PI = 20
7413 11:06:01.883560 [0] MIN Duty = 4813%(X100), DQS PI = 52
7414 11:06:01.886689 [0] AVG Duty = 4937%(X100)
7415 11:06:01.886770
7416 11:06:01.886832 ==DQS 1 ==
7417 11:06:01.890300 Final DQS duty delay cell = 0
7418 11:06:01.893364 [0] MAX Duty = 5062%(X100), DQS PI = 34
7419 11:06:01.896879 [0] MIN Duty = 4938%(X100), DQS PI = 12
7420 11:06:01.900143 [0] AVG Duty = 5000%(X100)
7421 11:06:01.900236
7422 11:06:01.903342 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7423 11:06:01.903467
7424 11:06:01.906581 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7425 11:06:01.909971 [DutyScan_Calibration_Flow] ====Done====
7426 11:06:01.910057
7427 11:06:01.912927 [DutyScan_Calibration_Flow] k_type=3
7428 11:06:01.930496
7429 11:06:01.930576 ==DQM 0 ==
7430 11:06:01.933318 Final DQM duty delay cell = 0
7431 11:06:01.937266 [0] MAX Duty = 5156%(X100), DQS PI = 20
7432 11:06:01.940282 [0] MIN Duty = 4844%(X100), DQS PI = 52
7433 11:06:01.943774 [0] AVG Duty = 5000%(X100)
7434 11:06:01.943848
7435 11:06:01.943909 ==DQM 1 ==
7436 11:06:01.946828 Final DQM duty delay cell = 0
7437 11:06:01.950354 [0] MAX Duty = 5156%(X100), DQS PI = 60
7438 11:06:01.953680 [0] MIN Duty = 4907%(X100), DQS PI = 20
7439 11:06:01.956924 [0] AVG Duty = 5031%(X100)
7440 11:06:01.956997
7441 11:06:01.960474 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7442 11:06:01.960570
7443 11:06:01.963659 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7444 11:06:01.967023 [DutyScan_Calibration_Flow] ====Done====
7445 11:06:01.967128
7446 11:06:01.970318 [DutyScan_Calibration_Flow] k_type=2
7447 11:06:01.987014
7448 11:06:01.987100 ==DQ 0 ==
7449 11:06:01.990709 Final DQ duty delay cell = 0
7450 11:06:01.994085 [0] MAX Duty = 5156%(X100), DQS PI = 22
7451 11:06:01.997212 [0] MIN Duty = 4907%(X100), DQS PI = 52
7452 11:06:01.997295 [0] AVG Duty = 5031%(X100)
7453 11:06:02.000699
7454 11:06:02.000777 ==DQ 1 ==
7455 11:06:02.003754 Final DQ duty delay cell = 0
7456 11:06:02.006995 [0] MAX Duty = 5093%(X100), DQS PI = 6
7457 11:06:02.010599 [0] MIN Duty = 5031%(X100), DQS PI = 0
7458 11:06:02.010678 [0] AVG Duty = 5062%(X100)
7459 11:06:02.010750
7460 11:06:02.013859 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7461 11:06:02.017070
7462 11:06:02.017147 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7463 11:06:02.023973 [DutyScan_Calibration_Flow] ====Done====
7464 11:06:02.027695 nWR fixed to 30
7465 11:06:02.027773 [ModeRegInit_LP4] CH0 RK0
7466 11:06:02.030479 [ModeRegInit_LP4] CH0 RK1
7467 11:06:02.033744 [ModeRegInit_LP4] CH1 RK0
7468 11:06:02.033846 [ModeRegInit_LP4] CH1 RK1
7469 11:06:02.037106 match AC timing 5
7470 11:06:02.040420 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7471 11:06:02.043553 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7472 11:06:02.050475 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7473 11:06:02.053918 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7474 11:06:02.060334 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7475 11:06:02.060410 [MiockJmeterHQA]
7476 11:06:02.060472
7477 11:06:02.063449 [DramcMiockJmeter] u1RxGatingPI = 0
7478 11:06:02.067163 0 : 4365, 4140
7479 11:06:02.067251 4 : 4364, 4137
7480 11:06:02.067322 8 : 4255, 4029
7481 11:06:02.070094 12 : 4253, 4027
7482 11:06:02.070170 16 : 4257, 4032
7483 11:06:02.073898 20 : 4363, 4138
7484 11:06:02.073978 24 : 4367, 4140
7485 11:06:02.077573 28 : 4252, 4027
7486 11:06:02.077695 32 : 4252, 4027
7487 11:06:02.077765 36 : 4368, 4142
7488 11:06:02.080242 40 : 4257, 4029
7489 11:06:02.080312 44 : 4252, 4027
7490 11:06:02.083861 48 : 4252, 4027
7491 11:06:02.083992 52 : 4366, 4140
7492 11:06:02.086716 56 : 4252, 4027
7493 11:06:02.086844 60 : 4255, 4029
7494 11:06:02.090092 64 : 4250, 4027
7495 11:06:02.090218 68 : 4363, 4140
7496 11:06:02.090332 72 : 4363, 4137
7497 11:06:02.093953 76 : 4250, 4027
7498 11:06:02.094078 80 : 4255, 4029
7499 11:06:02.097464 84 : 4360, 4138
7500 11:06:02.097570 88 : 4255, 4029
7501 11:06:02.100485 92 : 4250, 4027
7502 11:06:02.100586 96 : 4254, 3382
7503 11:06:02.100678 100 : 4250, 0
7504 11:06:02.103709 104 : 4250, 0
7505 11:06:02.103790 108 : 4257, 0
7506 11:06:02.106718 112 : 4250, 0
7507 11:06:02.106792 116 : 4253, 0
7508 11:06:02.106861 120 : 4252, 0
7509 11:06:02.110111 124 : 4365, 0
7510 11:06:02.110184 128 : 4255, 0
7511 11:06:02.113848 132 : 4250, 0
7512 11:06:02.113921 136 : 4250, 0
7513 11:06:02.113983 140 : 4368, 0
7514 11:06:02.117201 144 : 4253, 0
7515 11:06:02.117275 148 : 4250, 0
7516 11:06:02.117345 152 : 4253, 0
7517 11:06:02.120716 156 : 4255, 0
7518 11:06:02.120789 160 : 4363, 0
7519 11:06:02.123909 164 : 4366, 0
7520 11:06:02.124013 168 : 4247, 0
7521 11:06:02.124117 172 : 4250, 0
7522 11:06:02.126857 176 : 4253, 0
7523 11:06:02.126971 180 : 4250, 0
7524 11:06:02.130120 184 : 4252, 0
7525 11:06:02.130203 188 : 4250, 0
7526 11:06:02.130267 192 : 4254, 0
7527 11:06:02.133960 196 : 4253, 0
7528 11:06:02.134036 200 : 4250, 0
7529 11:06:02.137144 204 : 4250, 0
7530 11:06:02.137225 208 : 4252, 0
7531 11:06:02.137288 212 : 4364, 146
7532 11:06:02.140398 216 : 4255, 3644
7533 11:06:02.140486 220 : 4250, 4027
7534 11:06:02.144092 224 : 4250, 4027
7535 11:06:02.144165 228 : 4253, 4029
7536 11:06:02.147102 232 : 4361, 4137
7537 11:06:02.147177 236 : 4363, 4140
7538 11:06:02.150213 240 : 4252, 4029
7539 11:06:02.150286 244 : 4363, 4140
7540 11:06:02.150348 248 : 4253, 4029
7541 11:06:02.154073 252 : 4363, 4140
7542 11:06:02.154150 256 : 4366, 4140
7543 11:06:02.157242 260 : 4250, 4027
7544 11:06:02.157353 264 : 4249, 4027
7545 11:06:02.160127 268 : 4255, 4029
7546 11:06:02.160208 272 : 4250, 4027
7547 11:06:02.163398 276 : 4252, 4027
7548 11:06:02.163480 280 : 4253, 4029
7549 11:06:02.166745 284 : 4255, 4029
7550 11:06:02.166819 288 : 4255, 4030
7551 11:06:02.170297 292 : 4363, 4140
7552 11:06:02.170420 296 : 4250, 4027
7553 11:06:02.173496 300 : 4250, 4026
7554 11:06:02.173577 304 : 4250, 4027
7555 11:06:02.176729 308 : 4361, 4137
7556 11:06:02.176830 312 : 4363, 4139
7557 11:06:02.176900 316 : 4250, 4026
7558 11:06:02.180456 320 : 4250, 4027
7559 11:06:02.180539 324 : 4250, 4027
7560 11:06:02.183369 328 : 4253, 4030
7561 11:06:02.183449 332 : 4252, 2830
7562 11:06:02.186787 336 : 4257, 81
7563 11:06:02.186869
7564 11:06:02.186932 MIOCK jitter meter ch=0
7565 11:06:02.186989
7566 11:06:02.189982 1T = (336-100) = 236 dly cells
7567 11:06:02.196758 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7568 11:06:02.196841 ==
7569 11:06:02.200068 Dram Type= 6, Freq= 0, CH_0, rank 0
7570 11:06:02.203332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7571 11:06:02.203406 ==
7572 11:06:02.210118 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7573 11:06:02.213236 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7574 11:06:02.220428 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7575 11:06:02.223211 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7576 11:06:02.234205 [CA 0] Center 44 (14~75) winsize 62
7577 11:06:02.237586 [CA 1] Center 43 (13~74) winsize 62
7578 11:06:02.240791 [CA 2] Center 39 (10~68) winsize 59
7579 11:06:02.243846 [CA 3] Center 39 (10~68) winsize 59
7580 11:06:02.247179 [CA 4] Center 37 (8~67) winsize 60
7581 11:06:02.250451 [CA 5] Center 37 (7~67) winsize 61
7582 11:06:02.250557
7583 11:06:02.253789 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7584 11:06:02.253870
7585 11:06:02.257164 [CATrainingPosCal] consider 1 rank data
7586 11:06:02.260574 u2DelayCellTimex100 = 275/100 ps
7587 11:06:02.263602 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7588 11:06:02.270414 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7589 11:06:02.273888 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7590 11:06:02.276957 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7591 11:06:02.280489 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7592 11:06:02.284213 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7593 11:06:02.284290
7594 11:06:02.287107 CA PerBit enable=1, Macro0, CA PI delay=37
7595 11:06:02.287229
7596 11:06:02.290302 [CBTSetCACLKResult] CA Dly = 37
7597 11:06:02.294039 CS Dly: 10 (0~41)
7598 11:06:02.296921 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7599 11:06:02.300307 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7600 11:06:02.300383 ==
7601 11:06:02.303771 Dram Type= 6, Freq= 0, CH_0, rank 1
7602 11:06:02.306746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 11:06:02.310557 ==
7604 11:06:02.313713 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7605 11:06:02.317068 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7606 11:06:02.323889 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7607 11:06:02.326784 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7608 11:06:02.337505 [CA 0] Center 44 (14~75) winsize 62
7609 11:06:02.340905 [CA 1] Center 44 (14~75) winsize 62
7610 11:06:02.344487 [CA 2] Center 40 (11~69) winsize 59
7611 11:06:02.347940 [CA 3] Center 39 (10~69) winsize 60
7612 11:06:02.351009 [CA 4] Center 38 (9~68) winsize 60
7613 11:06:02.354325 [CA 5] Center 37 (7~67) winsize 61
7614 11:06:02.354431
7615 11:06:02.357502 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7616 11:06:02.357575
7617 11:06:02.361208 [CATrainingPosCal] consider 2 rank data
7618 11:06:02.363966 u2DelayCellTimex100 = 275/100 ps
7619 11:06:02.367681 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7620 11:06:02.373859 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7621 11:06:02.377423 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7622 11:06:02.380915 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7623 11:06:02.384220 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
7624 11:06:02.387536 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7625 11:06:02.387619
7626 11:06:02.390907 CA PerBit enable=1, Macro0, CA PI delay=37
7627 11:06:02.391055
7628 11:06:02.394500 [CBTSetCACLKResult] CA Dly = 37
7629 11:06:02.397676 CS Dly: 11 (0~44)
7630 11:06:02.401074 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7631 11:06:02.403880 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7632 11:06:02.403984
7633 11:06:02.407463 ----->DramcWriteLeveling(PI) begin...
7634 11:06:02.407616 ==
7635 11:06:02.410582 Dram Type= 6, Freq= 0, CH_0, rank 0
7636 11:06:02.416864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7637 11:06:02.416999 ==
7638 11:06:02.420200 Write leveling (Byte 0): 33 => 33
7639 11:06:02.420338 Write leveling (Byte 1): 27 => 27
7640 11:06:02.423640 DramcWriteLeveling(PI) end<-----
7641 11:06:02.423770
7642 11:06:02.427268 ==
7643 11:06:02.427389 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 11:06:02.433535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 11:06:02.433642 ==
7646 11:06:02.436955 [Gating] SW mode calibration
7647 11:06:02.443342 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7648 11:06:02.446911 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7649 11:06:02.453951 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7650 11:06:02.456899 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 11:06:02.459956 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 11:06:02.466931 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 11:06:02.470034 1 4 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7654 11:06:02.473420 1 4 20 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7655 11:06:02.479834 1 4 24 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
7656 11:06:02.483054 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7657 11:06:02.486890 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7658 11:06:02.493348 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7659 11:06:02.497101 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7660 11:06:02.499717 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7661 11:06:02.506846 1 5 16 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7662 11:06:02.509874 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7663 11:06:02.513150 1 5 24 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
7664 11:06:02.519703 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7665 11:06:02.523037 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 11:06:02.527155 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7667 11:06:02.532901 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7668 11:06:02.536642 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7669 11:06:02.539715 1 6 16 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7670 11:06:02.546283 1 6 20 | B1->B0 | 2929 4545 | 0 0 | (0 0) (0 0)
7671 11:06:02.549810 1 6 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7672 11:06:02.552825 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7673 11:06:02.556407 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7674 11:06:02.563535 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 11:06:02.566407 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7676 11:06:02.569921 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7677 11:06:02.575972 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7678 11:06:02.579361 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7679 11:06:02.582649 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 11:06:02.589129 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 11:06:02.592995 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 11:06:02.595826 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 11:06:02.602545 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 11:06:02.605904 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 11:06:02.609340 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 11:06:02.615867 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 11:06:02.619604 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 11:06:02.622324 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 11:06:02.629111 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 11:06:02.632958 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 11:06:02.636522 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 11:06:02.642581 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7693 11:06:02.645626 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7694 11:06:02.649283 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7695 11:06:02.655694 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7696 11:06:02.655773 Total UI for P1: 0, mck2ui 16
7697 11:06:02.662284 best dqsien dly found for B0: ( 1, 9, 16)
7698 11:06:02.666077 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7699 11:06:02.669428 Total UI for P1: 0, mck2ui 16
7700 11:06:02.672703 best dqsien dly found for B1: ( 1, 9, 22)
7701 11:06:02.675698 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7702 11:06:02.679163 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7703 11:06:02.679269
7704 11:06:02.682475 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7705 11:06:02.685959 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7706 11:06:02.688820 [Gating] SW calibration Done
7707 11:06:02.688894 ==
7708 11:06:02.692697 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 11:06:02.695527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 11:06:02.699186 ==
7711 11:06:02.699270 RX Vref Scan: 0
7712 11:06:02.699336
7713 11:06:02.702122 RX Vref 0 -> 0, step: 1
7714 11:06:02.702251
7715 11:06:02.702363 RX Delay 0 -> 252, step: 8
7716 11:06:02.708558 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7717 11:06:02.712500 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7718 11:06:02.715378 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7719 11:06:02.719298 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7720 11:06:02.722272 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7721 11:06:02.729167 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7722 11:06:02.732106 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7723 11:06:02.735285 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7724 11:06:02.738760 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7725 11:06:02.741892 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7726 11:06:02.749106 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7727 11:06:02.752318 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7728 11:06:02.755317 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7729 11:06:02.758620 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7730 11:06:02.762365 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7731 11:06:02.768682 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7732 11:06:02.768761 ==
7733 11:06:02.772394 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 11:06:02.775458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 11:06:02.775534 ==
7736 11:06:02.775606 DQS Delay:
7737 11:06:02.779069 DQS0 = 0, DQS1 = 0
7738 11:06:02.779198 DQM Delay:
7739 11:06:02.782111 DQM0 = 132, DQM1 = 125
7740 11:06:02.782216 DQ Delay:
7741 11:06:02.785517 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7742 11:06:02.788792 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7743 11:06:02.792142 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7744 11:06:02.795417 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7745 11:06:02.795542
7746 11:06:02.798560
7747 11:06:02.798684 ==
7748 11:06:02.802250 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 11:06:02.805352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 11:06:02.805456 ==
7751 11:06:02.805528
7752 11:06:02.805597
7753 11:06:02.809205 TX Vref Scan disable
7754 11:06:02.809328 == TX Byte 0 ==
7755 11:06:02.812318 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7756 11:06:02.819326 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7757 11:06:02.819404 == TX Byte 1 ==
7758 11:06:02.822336 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7759 11:06:02.829467 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7760 11:06:02.829545 ==
7761 11:06:02.832236 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 11:06:02.836527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 11:06:02.836611 ==
7764 11:06:02.850539
7765 11:06:02.853722 TX Vref early break, caculate TX vref
7766 11:06:02.857309 TX Vref=16, minBit 1, minWin=21, winSum=356
7767 11:06:02.860988 TX Vref=18, minBit 2, minWin=21, winSum=362
7768 11:06:02.863878 TX Vref=20, minBit 3, minWin=22, winSum=374
7769 11:06:02.867003 TX Vref=22, minBit 4, minWin=22, winSum=384
7770 11:06:02.870240 TX Vref=24, minBit 0, minWin=24, winSum=402
7771 11:06:02.876877 TX Vref=26, minBit 1, minWin=24, winSum=406
7772 11:06:02.880259 TX Vref=28, minBit 4, minWin=24, winSum=417
7773 11:06:02.883563 TX Vref=30, minBit 4, minWin=24, winSum=415
7774 11:06:02.886821 TX Vref=32, minBit 4, minWin=23, winSum=407
7775 11:06:02.890137 TX Vref=34, minBit 4, minWin=23, winSum=398
7776 11:06:02.893937 TX Vref=36, minBit 0, minWin=23, winSum=387
7777 11:06:02.900133 [TxChooseVref] Worse bit 4, Min win 24, Win sum 417, Final Vref 28
7778 11:06:02.900221
7779 11:06:02.903678 Final TX Range 0 Vref 28
7780 11:06:02.903778
7781 11:06:02.903849 ==
7782 11:06:02.907078 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 11:06:02.910245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 11:06:02.910351 ==
7785 11:06:02.910439
7786 11:06:02.910498
7787 11:06:02.913791 TX Vref Scan disable
7788 11:06:02.920396 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7789 11:06:02.920516 == TX Byte 0 ==
7790 11:06:02.923779 u2DelayCellOfst[0]=14 cells (4 PI)
7791 11:06:02.927091 u2DelayCellOfst[1]=17 cells (5 PI)
7792 11:06:02.930675 u2DelayCellOfst[2]=10 cells (3 PI)
7793 11:06:02.933771 u2DelayCellOfst[3]=10 cells (3 PI)
7794 11:06:02.937122 u2DelayCellOfst[4]=7 cells (2 PI)
7795 11:06:02.940716 u2DelayCellOfst[5]=0 cells (0 PI)
7796 11:06:02.943647 u2DelayCellOfst[6]=21 cells (6 PI)
7797 11:06:02.947166 u2DelayCellOfst[7]=17 cells (5 PI)
7798 11:06:02.950476 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7799 11:06:02.953889 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7800 11:06:02.957059 == TX Byte 1 ==
7801 11:06:02.960384 u2DelayCellOfst[8]=0 cells (0 PI)
7802 11:06:02.960463 u2DelayCellOfst[9]=0 cells (0 PI)
7803 11:06:02.963561 u2DelayCellOfst[10]=7 cells (2 PI)
7804 11:06:02.966824 u2DelayCellOfst[11]=0 cells (0 PI)
7805 11:06:02.970187 u2DelayCellOfst[12]=14 cells (4 PI)
7806 11:06:02.973834 u2DelayCellOfst[13]=10 cells (3 PI)
7807 11:06:02.977029 u2DelayCellOfst[14]=17 cells (5 PI)
7808 11:06:02.980328 u2DelayCellOfst[15]=10 cells (3 PI)
7809 11:06:02.983813 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7810 11:06:02.990201 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7811 11:06:02.990306 DramC Write-DBI on
7812 11:06:02.990406 ==
7813 11:06:02.993518 Dram Type= 6, Freq= 0, CH_0, rank 0
7814 11:06:02.997604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7815 11:06:03.000051 ==
7816 11:06:03.000153
7817 11:06:03.000244
7818 11:06:03.000332 TX Vref Scan disable
7819 11:06:03.003649 == TX Byte 0 ==
7820 11:06:03.007310 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7821 11:06:03.010718 == TX Byte 1 ==
7822 11:06:03.013746 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7823 11:06:03.017170 DramC Write-DBI off
7824 11:06:03.017252
7825 11:06:03.017316 [DATLAT]
7826 11:06:03.017377 Freq=1600, CH0 RK0
7827 11:06:03.017437
7828 11:06:03.020707 DATLAT Default: 0xf
7829 11:06:03.020789 0, 0xFFFF, sum = 0
7830 11:06:03.023859 1, 0xFFFF, sum = 0
7831 11:06:03.023946 2, 0xFFFF, sum = 0
7832 11:06:03.027342 3, 0xFFFF, sum = 0
7833 11:06:03.030524 4, 0xFFFF, sum = 0
7834 11:06:03.030609 5, 0xFFFF, sum = 0
7835 11:06:03.034140 6, 0xFFFF, sum = 0
7836 11:06:03.034249 7, 0xFFFF, sum = 0
7837 11:06:03.037036 8, 0xFFFF, sum = 0
7838 11:06:03.037121 9, 0xFFFF, sum = 0
7839 11:06:03.040665 10, 0xFFFF, sum = 0
7840 11:06:03.040749 11, 0xFFFF, sum = 0
7841 11:06:03.044113 12, 0xFFFF, sum = 0
7842 11:06:03.044224 13, 0xFFFF, sum = 0
7843 11:06:03.047013 14, 0x0, sum = 1
7844 11:06:03.047124 15, 0x0, sum = 2
7845 11:06:03.050433 16, 0x0, sum = 3
7846 11:06:03.050542 17, 0x0, sum = 4
7847 11:06:03.054028 best_step = 15
7848 11:06:03.054133
7849 11:06:03.054224 ==
7850 11:06:03.057220 Dram Type= 6, Freq= 0, CH_0, rank 0
7851 11:06:03.061012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7852 11:06:03.061116 ==
7853 11:06:03.061208 RX Vref Scan: 1
7854 11:06:03.061296
7855 11:06:03.064089 Set Vref Range= 24 -> 127
7856 11:06:03.064195
7857 11:06:03.067442 RX Vref 24 -> 127, step: 1
7858 11:06:03.067546
7859 11:06:03.071023 RX Delay 11 -> 252, step: 4
7860 11:06:03.071131
7861 11:06:03.073893 Set Vref, RX VrefLevel [Byte0]: 24
7862 11:06:03.077317 [Byte1]: 24
7863 11:06:03.077423
7864 11:06:03.080795 Set Vref, RX VrefLevel [Byte0]: 25
7865 11:06:03.083887 [Byte1]: 25
7866 11:06:03.083992
7867 11:06:03.087366 Set Vref, RX VrefLevel [Byte0]: 26
7868 11:06:03.090555 [Byte1]: 26
7869 11:06:03.094524
7870 11:06:03.094627 Set Vref, RX VrefLevel [Byte0]: 27
7871 11:06:03.097878 [Byte1]: 27
7872 11:06:03.102182
7873 11:06:03.102258 Set Vref, RX VrefLevel [Byte0]: 28
7874 11:06:03.105248 [Byte1]: 28
7875 11:06:03.109603
7876 11:06:03.109684 Set Vref, RX VrefLevel [Byte0]: 29
7877 11:06:03.112775 [Byte1]: 29
7878 11:06:03.117228
7879 11:06:03.117333 Set Vref, RX VrefLevel [Byte0]: 30
7880 11:06:03.120600 [Byte1]: 30
7881 11:06:03.124669
7882 11:06:03.124777 Set Vref, RX VrefLevel [Byte0]: 31
7883 11:06:03.127940 [Byte1]: 31
7884 11:06:03.132275
7885 11:06:03.132391 Set Vref, RX VrefLevel [Byte0]: 32
7886 11:06:03.135944 [Byte1]: 32
7887 11:06:03.140356
7888 11:06:03.140461 Set Vref, RX VrefLevel [Byte0]: 33
7889 11:06:03.143311 [Byte1]: 33
7890 11:06:03.147392
7891 11:06:03.147471 Set Vref, RX VrefLevel [Byte0]: 34
7892 11:06:03.150879 [Byte1]: 34
7893 11:06:03.155112
7894 11:06:03.155188 Set Vref, RX VrefLevel [Byte0]: 35
7895 11:06:03.158527 [Byte1]: 35
7896 11:06:03.162583
7897 11:06:03.162660 Set Vref, RX VrefLevel [Byte0]: 36
7898 11:06:03.166213 [Byte1]: 36
7899 11:06:03.170295
7900 11:06:03.170371 Set Vref, RX VrefLevel [Byte0]: 37
7901 11:06:03.174043 [Byte1]: 37
7902 11:06:03.178149
7903 11:06:03.178224 Set Vref, RX VrefLevel [Byte0]: 38
7904 11:06:03.181280 [Byte1]: 38
7905 11:06:03.185695
7906 11:06:03.185772 Set Vref, RX VrefLevel [Byte0]: 39
7907 11:06:03.189022 [Byte1]: 39
7908 11:06:03.193623
7909 11:06:03.193728 Set Vref, RX VrefLevel [Byte0]: 40
7910 11:06:03.196510 [Byte1]: 40
7911 11:06:03.200842
7912 11:06:03.200932 Set Vref, RX VrefLevel [Byte0]: 41
7913 11:06:03.204813 [Byte1]: 41
7914 11:06:03.208603
7915 11:06:03.208716 Set Vref, RX VrefLevel [Byte0]: 42
7916 11:06:03.211659 [Byte1]: 42
7917 11:06:03.216298
7918 11:06:03.216377 Set Vref, RX VrefLevel [Byte0]: 43
7919 11:06:03.219985 [Byte1]: 43
7920 11:06:03.223927
7921 11:06:03.224012 Set Vref, RX VrefLevel [Byte0]: 44
7922 11:06:03.227305 [Byte1]: 44
7923 11:06:03.231244
7924 11:06:03.231322 Set Vref, RX VrefLevel [Byte0]: 45
7925 11:06:03.234665 [Byte1]: 45
7926 11:06:03.239304
7927 11:06:03.239396 Set Vref, RX VrefLevel [Byte0]: 46
7928 11:06:03.242402 [Byte1]: 46
7929 11:06:03.246511
7930 11:06:03.246599 Set Vref, RX VrefLevel [Byte0]: 47
7931 11:06:03.249960 [Byte1]: 47
7932 11:06:03.254081
7933 11:06:03.254158 Set Vref, RX VrefLevel [Byte0]: 48
7934 11:06:03.257524 [Byte1]: 48
7935 11:06:03.262151
7936 11:06:03.262228 Set Vref, RX VrefLevel [Byte0]: 49
7937 11:06:03.264795 [Byte1]: 49
7938 11:06:03.269755
7939 11:06:03.269831 Set Vref, RX VrefLevel [Byte0]: 50
7940 11:06:03.272514 [Byte1]: 50
7941 11:06:03.276956
7942 11:06:03.277058 Set Vref, RX VrefLevel [Byte0]: 51
7943 11:06:03.280346 [Byte1]: 51
7944 11:06:03.284804
7945 11:06:03.284886 Set Vref, RX VrefLevel [Byte0]: 52
7946 11:06:03.288127 [Byte1]: 52
7947 11:06:03.292037
7948 11:06:03.292113 Set Vref, RX VrefLevel [Byte0]: 53
7949 11:06:03.295595 [Byte1]: 53
7950 11:06:03.300267
7951 11:06:03.300354 Set Vref, RX VrefLevel [Byte0]: 54
7952 11:06:03.303257 [Byte1]: 54
7953 11:06:03.307938
7954 11:06:03.308024 Set Vref, RX VrefLevel [Byte0]: 55
7955 11:06:03.310864 [Byte1]: 55
7956 11:06:03.314935
7957 11:06:03.315020 Set Vref, RX VrefLevel [Byte0]: 56
7958 11:06:03.318623 [Byte1]: 56
7959 11:06:03.322825
7960 11:06:03.322904 Set Vref, RX VrefLevel [Byte0]: 57
7961 11:06:03.325731 [Byte1]: 57
7962 11:06:03.330586
7963 11:06:03.330690 Set Vref, RX VrefLevel [Byte0]: 58
7964 11:06:03.333501 [Byte1]: 58
7965 11:06:03.337873
7966 11:06:03.337952 Set Vref, RX VrefLevel [Byte0]: 59
7967 11:06:03.340930 [Byte1]: 59
7968 11:06:03.345440
7969 11:06:03.345542 Set Vref, RX VrefLevel [Byte0]: 60
7970 11:06:03.348670 [Byte1]: 60
7971 11:06:03.352914
7972 11:06:03.353023 Set Vref, RX VrefLevel [Byte0]: 61
7973 11:06:03.356279 [Byte1]: 61
7974 11:06:03.360839
7975 11:06:03.360943 Set Vref, RX VrefLevel [Byte0]: 62
7976 11:06:03.363707 [Byte1]: 62
7977 11:06:03.368526
7978 11:06:03.368616 Set Vref, RX VrefLevel [Byte0]: 63
7979 11:06:03.371557 [Byte1]: 63
7980 11:06:03.375793
7981 11:06:03.375882 Set Vref, RX VrefLevel [Byte0]: 64
7982 11:06:03.379025 [Byte1]: 64
7983 11:06:03.383533
7984 11:06:03.383648 Set Vref, RX VrefLevel [Byte0]: 65
7985 11:06:03.386860 [Byte1]: 65
7986 11:06:03.391373
7987 11:06:03.391469 Set Vref, RX VrefLevel [Byte0]: 66
7988 11:06:03.394260 [Byte1]: 66
7989 11:06:03.398606
7990 11:06:03.398687 Set Vref, RX VrefLevel [Byte0]: 67
7991 11:06:03.402093 [Byte1]: 67
7992 11:06:03.406919
7993 11:06:03.407027 Set Vref, RX VrefLevel [Byte0]: 68
7994 11:06:03.409854 [Byte1]: 68
7995 11:06:03.413750
7996 11:06:03.413859 Set Vref, RX VrefLevel [Byte0]: 69
7997 11:06:03.417585 [Byte1]: 69
7998 11:06:03.421428
7999 11:06:03.421510 Set Vref, RX VrefLevel [Byte0]: 70
8000 11:06:03.425135 [Byte1]: 70
8001 11:06:03.430125
8002 11:06:03.430242 Set Vref, RX VrefLevel [Byte0]: 71
8003 11:06:03.432407 [Byte1]: 71
8004 11:06:03.437221
8005 11:06:03.437300 Set Vref, RX VrefLevel [Byte0]: 72
8006 11:06:03.440022 [Byte1]: 72
8007 11:06:03.444397
8008 11:06:03.444479 Set Vref, RX VrefLevel [Byte0]: 73
8009 11:06:03.447884 [Byte1]: 73
8010 11:06:03.452175
8011 11:06:03.452258 Set Vref, RX VrefLevel [Byte0]: 74
8012 11:06:03.455643 [Byte1]: 74
8013 11:06:03.459907
8014 11:06:03.460012 Set Vref, RX VrefLevel [Byte0]: 75
8015 11:06:03.462947 [Byte1]: 75
8016 11:06:03.467366
8017 11:06:03.467496 Set Vref, RX VrefLevel [Byte0]: 76
8018 11:06:03.470376 [Byte1]: 76
8019 11:06:03.474843
8020 11:06:03.474947 Final RX Vref Byte 0 = 56 to rank0
8021 11:06:03.478376 Final RX Vref Byte 1 = 64 to rank0
8022 11:06:03.481630 Final RX Vref Byte 0 = 56 to rank1
8023 11:06:03.484950 Final RX Vref Byte 1 = 64 to rank1==
8024 11:06:03.488626 Dram Type= 6, Freq= 0, CH_0, rank 0
8025 11:06:03.491501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 11:06:03.495275 ==
8027 11:06:03.495379 DQS Delay:
8028 11:06:03.495470 DQS0 = 0, DQS1 = 0
8029 11:06:03.498158 DQM Delay:
8030 11:06:03.498259 DQM0 = 129, DQM1 = 122
8031 11:06:03.501503 DQ Delay:
8032 11:06:03.504896 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
8033 11:06:03.508584 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
8034 11:06:03.511832 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8035 11:06:03.515128 DQ12 =128, DQ13 =128, DQ14 =130, DQ15 =132
8036 11:06:03.515216
8037 11:06:03.515283
8038 11:06:03.515349
8039 11:06:03.518615 [DramC_TX_OE_Calibration] TA2
8040 11:06:03.522125 Original DQ_B0 (3 6) =30, OEN = 27
8041 11:06:03.524864 Original DQ_B1 (3 6) =30, OEN = 27
8042 11:06:03.524986 24, 0x0, End_B0=24 End_B1=24
8043 11:06:03.528286 25, 0x0, End_B0=25 End_B1=25
8044 11:06:03.531883 26, 0x0, End_B0=26 End_B1=26
8045 11:06:03.535112 27, 0x0, End_B0=27 End_B1=27
8046 11:06:03.538822 28, 0x0, End_B0=28 End_B1=28
8047 11:06:03.538959 29, 0x0, End_B0=29 End_B1=29
8048 11:06:03.541868 30, 0x0, End_B0=30 End_B1=30
8049 11:06:03.545494 31, 0x4141, End_B0=30 End_B1=30
8050 11:06:03.549004 Byte0 end_step=30 best_step=27
8051 11:06:03.551823 Byte1 end_step=30 best_step=27
8052 11:06:03.551906 Byte0 TX OE(2T, 0.5T) = (3, 3)
8053 11:06:03.555366 Byte1 TX OE(2T, 0.5T) = (3, 3)
8054 11:06:03.555444
8055 11:06:03.555527
8056 11:06:03.565066 [DQSOSCAuto] RK0, (LSB)MR18= 0x1206, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
8057 11:06:03.568380 CH0 RK0: MR19=303, MR18=1206
8058 11:06:03.571588 CH0_RK0: MR19=0x303, MR18=0x1206, DQSOSC=400, MR23=63, INC=23, DEC=15
8059 11:06:03.574933
8060 11:06:03.578365 ----->DramcWriteLeveling(PI) begin...
8061 11:06:03.578454 ==
8062 11:06:03.582246 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 11:06:03.585286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 11:06:03.585398 ==
8065 11:06:03.588574 Write leveling (Byte 0): 35 => 35
8066 11:06:03.591845 Write leveling (Byte 1): 26 => 26
8067 11:06:03.595123 DramcWriteLeveling(PI) end<-----
8068 11:06:03.595209
8069 11:06:03.595274 ==
8070 11:06:03.598582 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 11:06:03.602348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 11:06:03.602450 ==
8073 11:06:03.605616 [Gating] SW mode calibration
8074 11:06:03.612016 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8075 11:06:03.619098 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8076 11:06:03.622222 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 11:06:03.625317 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 11:06:03.628713 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8079 11:06:03.635322 1 4 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8080 11:06:03.638615 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8081 11:06:03.641961 1 4 20 | B1->B0 | 2726 3434 | 1 1 | (0 0) (1 1)
8082 11:06:03.649190 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8083 11:06:03.651831 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8084 11:06:03.655322 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8085 11:06:03.662062 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8086 11:06:03.665511 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8087 11:06:03.668608 1 5 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (0 1)
8088 11:06:03.675609 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8089 11:06:03.679045 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
8090 11:06:03.682233 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8091 11:06:03.688943 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8092 11:06:03.692255 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8093 11:06:03.695285 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8094 11:06:03.701976 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
8095 11:06:03.705753 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8096 11:06:03.709192 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8097 11:06:03.712492 1 6 20 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
8098 11:06:03.718739 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8099 11:06:03.722142 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 11:06:03.725615 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8101 11:06:03.732249 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8102 11:06:03.735461 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8103 11:06:03.738870 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8104 11:06:03.745355 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8105 11:06:03.748720 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8106 11:06:03.752298 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8107 11:06:03.758740 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 11:06:03.762425 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 11:06:03.765646 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 11:06:03.772656 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 11:06:03.775692 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 11:06:03.778977 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 11:06:03.785513 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 11:06:03.789219 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 11:06:03.792510 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 11:06:03.799157 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 11:06:03.802243 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 11:06:03.805746 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8119 11:06:03.809349 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8120 11:06:03.815457 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8121 11:06:03.819096 Total UI for P1: 0, mck2ui 16
8122 11:06:03.822284 best dqsien dly found for B0: ( 1, 9, 10)
8123 11:06:03.825671 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8124 11:06:03.829009 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8125 11:06:03.832378 Total UI for P1: 0, mck2ui 16
8126 11:06:03.835360 best dqsien dly found for B1: ( 1, 9, 18)
8127 11:06:03.839123 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8128 11:06:03.842605 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8129 11:06:03.842736
8130 11:06:03.848958 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8131 11:06:03.852416 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8132 11:06:03.855760 [Gating] SW calibration Done
8133 11:06:03.855885 ==
8134 11:06:03.859259 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 11:06:03.862240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 11:06:03.862349 ==
8137 11:06:03.862444 RX Vref Scan: 0
8138 11:06:03.862511
8139 11:06:03.866457 RX Vref 0 -> 0, step: 1
8140 11:06:03.866566
8141 11:06:03.868888 RX Delay 0 -> 252, step: 8
8142 11:06:03.872516 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8143 11:06:03.875674 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8144 11:06:03.878949 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8145 11:06:03.885507 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8146 11:06:03.889260 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8147 11:06:03.892386 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8148 11:06:03.895402 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8149 11:06:03.898896 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8150 11:06:03.905833 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8151 11:06:03.909049 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8152 11:06:03.912301 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8153 11:06:03.915685 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8154 11:06:03.918781 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8155 11:06:03.925881 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8156 11:06:03.929256 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8157 11:06:03.932566 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8158 11:06:03.932676 ==
8159 11:06:03.935883 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 11:06:03.939131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 11:06:03.939210 ==
8162 11:06:03.942679 DQS Delay:
8163 11:06:03.942758 DQS0 = 0, DQS1 = 0
8164 11:06:03.945547 DQM Delay:
8165 11:06:03.945615 DQM0 = 131, DQM1 = 126
8166 11:06:03.945679 DQ Delay:
8167 11:06:03.952269 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8168 11:06:03.955580 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8169 11:06:03.958945 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
8170 11:06:03.962071 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
8171 11:06:03.962146
8172 11:06:03.962208
8173 11:06:03.962274 ==
8174 11:06:03.965846 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 11:06:03.968850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 11:06:03.968919 ==
8177 11:06:03.968983
8178 11:06:03.969041
8179 11:06:03.972581 TX Vref Scan disable
8180 11:06:03.975768 == TX Byte 0 ==
8181 11:06:03.978928 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8182 11:06:03.982202 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8183 11:06:03.985421 == TX Byte 1 ==
8184 11:06:03.988721 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8185 11:06:03.992348 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8186 11:06:03.992439 ==
8187 11:06:03.995488 Dram Type= 6, Freq= 0, CH_0, rank 1
8188 11:06:03.998719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8189 11:06:04.001829 ==
8190 11:06:04.015620
8191 11:06:04.019532 TX Vref early break, caculate TX vref
8192 11:06:04.022261 TX Vref=16, minBit 1, minWin=22, winSum=375
8193 11:06:04.025977 TX Vref=18, minBit 9, minWin=22, winSum=380
8194 11:06:04.029239 TX Vref=20, minBit 0, minWin=23, winSum=390
8195 11:06:04.032452 TX Vref=22, minBit 9, minWin=23, winSum=396
8196 11:06:04.035721 TX Vref=24, minBit 4, minWin=24, winSum=405
8197 11:06:04.042470 TX Vref=26, minBit 2, minWin=25, winSum=412
8198 11:06:04.045973 TX Vref=28, minBit 4, minWin=25, winSum=421
8199 11:06:04.049146 TX Vref=30, minBit 4, minWin=25, winSum=416
8200 11:06:04.052499 TX Vref=32, minBit 8, minWin=24, winSum=411
8201 11:06:04.055882 TX Vref=34, minBit 7, minWin=24, winSum=402
8202 11:06:04.059260 TX Vref=36, minBit 13, minWin=23, winSum=396
8203 11:06:04.065936 [TxChooseVref] Worse bit 4, Min win 25, Win sum 421, Final Vref 28
8204 11:06:04.066013
8205 11:06:04.069619 Final TX Range 0 Vref 28
8206 11:06:04.069689
8207 11:06:04.069755 ==
8208 11:06:04.072763 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 11:06:04.076093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 11:06:04.076222 ==
8211 11:06:04.076342
8212 11:06:04.076457
8213 11:06:04.079203 TX Vref Scan disable
8214 11:06:04.085793 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8215 11:06:04.085918 == TX Byte 0 ==
8216 11:06:04.089153 u2DelayCellOfst[0]=14 cells (4 PI)
8217 11:06:04.092836 u2DelayCellOfst[1]=17 cells (5 PI)
8218 11:06:04.095713 u2DelayCellOfst[2]=10 cells (3 PI)
8219 11:06:04.099157 u2DelayCellOfst[3]=10 cells (3 PI)
8220 11:06:04.102893 u2DelayCellOfst[4]=10 cells (3 PI)
8221 11:06:04.106247 u2DelayCellOfst[5]=0 cells (0 PI)
8222 11:06:04.109179 u2DelayCellOfst[6]=17 cells (5 PI)
8223 11:06:04.112496 u2DelayCellOfst[7]=17 cells (5 PI)
8224 11:06:04.116360 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8225 11:06:04.119186 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8226 11:06:04.122569 == TX Byte 1 ==
8227 11:06:04.122694 u2DelayCellOfst[8]=0 cells (0 PI)
8228 11:06:04.125782 u2DelayCellOfst[9]=0 cells (0 PI)
8229 11:06:04.129674 u2DelayCellOfst[10]=3 cells (1 PI)
8230 11:06:04.132564 u2DelayCellOfst[11]=0 cells (0 PI)
8231 11:06:04.136154 u2DelayCellOfst[12]=10 cells (3 PI)
8232 11:06:04.139052 u2DelayCellOfst[13]=10 cells (3 PI)
8233 11:06:04.142660 u2DelayCellOfst[14]=14 cells (4 PI)
8234 11:06:04.146146 u2DelayCellOfst[15]=10 cells (3 PI)
8235 11:06:04.149172 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8236 11:06:04.156089 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8237 11:06:04.156169 DramC Write-DBI on
8238 11:06:04.156234 ==
8239 11:06:04.159742 Dram Type= 6, Freq= 0, CH_0, rank 1
8240 11:06:04.163132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8241 11:06:04.165863 ==
8242 11:06:04.165937
8243 11:06:04.165999
8244 11:06:04.166056 TX Vref Scan disable
8245 11:06:04.169599 == TX Byte 0 ==
8246 11:06:04.172759 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8247 11:06:04.176106 == TX Byte 1 ==
8248 11:06:04.179666 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8249 11:06:04.183344 DramC Write-DBI off
8250 11:06:04.183422
8251 11:06:04.183503 [DATLAT]
8252 11:06:04.183594 Freq=1600, CH0 RK1
8253 11:06:04.183656
8254 11:06:04.185816 DATLAT Default: 0xf
8255 11:06:04.185920 0, 0xFFFF, sum = 0
8256 11:06:04.189489 1, 0xFFFF, sum = 0
8257 11:06:04.189567 2, 0xFFFF, sum = 0
8258 11:06:04.193104 3, 0xFFFF, sum = 0
8259 11:06:04.195936 4, 0xFFFF, sum = 0
8260 11:06:04.196019 5, 0xFFFF, sum = 0
8261 11:06:04.199002 6, 0xFFFF, sum = 0
8262 11:06:04.199080 7, 0xFFFF, sum = 0
8263 11:06:04.202802 8, 0xFFFF, sum = 0
8264 11:06:04.202906 9, 0xFFFF, sum = 0
8265 11:06:04.206109 10, 0xFFFF, sum = 0
8266 11:06:04.206220 11, 0xFFFF, sum = 0
8267 11:06:04.209758 12, 0xFFFF, sum = 0
8268 11:06:04.209861 13, 0xFFFF, sum = 0
8269 11:06:04.212589 14, 0x0, sum = 1
8270 11:06:04.212690 15, 0x0, sum = 2
8271 11:06:04.215878 16, 0x0, sum = 3
8272 11:06:04.215986 17, 0x0, sum = 4
8273 11:06:04.219230 best_step = 15
8274 11:06:04.219330
8275 11:06:04.219419 ==
8276 11:06:04.222550 Dram Type= 6, Freq= 0, CH_0, rank 1
8277 11:06:04.225728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8278 11:06:04.225803 ==
8279 11:06:04.225865 RX Vref Scan: 0
8280 11:06:04.229239
8281 11:06:04.229321 RX Vref 0 -> 0, step: 1
8282 11:06:04.229386
8283 11:06:04.232835 RX Delay 11 -> 252, step: 4
8284 11:06:04.236111 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8285 11:06:04.242692 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8286 11:06:04.245995 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8287 11:06:04.249496 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8288 11:06:04.252454 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8289 11:06:04.255960 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8290 11:06:04.262650 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8291 11:06:04.265755 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8292 11:06:04.269026 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8293 11:06:04.272484 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8294 11:06:04.276026 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8295 11:06:04.282901 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8296 11:06:04.286214 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8297 11:06:04.289989 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8298 11:06:04.292454 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8299 11:06:04.295665 iDelay=191, Bit 15, Center 132 (75 ~ 190) 116
8300 11:06:04.299386 ==
8301 11:06:04.299468 Dram Type= 6, Freq= 0, CH_0, rank 1
8302 11:06:04.305873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8303 11:06:04.305972 ==
8304 11:06:04.306039 DQS Delay:
8305 11:06:04.309658 DQS0 = 0, DQS1 = 0
8306 11:06:04.309771 DQM Delay:
8307 11:06:04.312326 DQM0 = 126, DQM1 = 123
8308 11:06:04.312428 DQ Delay:
8309 11:06:04.315669 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8310 11:06:04.319605 DQ4 =124, DQ5 =114, DQ6 =134, DQ7 =134
8311 11:06:04.322249 DQ8 =114, DQ9 =112, DQ10 =122, DQ11 =116
8312 11:06:04.325598 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8313 11:06:04.325728
8314 11:06:04.325841
8315 11:06:04.325952
8316 11:06:04.329128 [DramC_TX_OE_Calibration] TA2
8317 11:06:04.332347 Original DQ_B0 (3 6) =30, OEN = 27
8318 11:06:04.336140 Original DQ_B1 (3 6) =30, OEN = 27
8319 11:06:04.339700 24, 0x0, End_B0=24 End_B1=24
8320 11:06:04.342522 25, 0x0, End_B0=25 End_B1=25
8321 11:06:04.342651 26, 0x0, End_B0=26 End_B1=26
8322 11:06:04.345833 27, 0x0, End_B0=27 End_B1=27
8323 11:06:04.349009 28, 0x0, End_B0=28 End_B1=28
8324 11:06:04.352364 29, 0x0, End_B0=29 End_B1=29
8325 11:06:04.352449 30, 0x0, End_B0=30 End_B1=30
8326 11:06:04.355729 31, 0x4141, End_B0=30 End_B1=30
8327 11:06:04.359045 Byte0 end_step=30 best_step=27
8328 11:06:04.362709 Byte1 end_step=30 best_step=27
8329 11:06:04.366048 Byte0 TX OE(2T, 0.5T) = (3, 3)
8330 11:06:04.369187 Byte1 TX OE(2T, 0.5T) = (3, 3)
8331 11:06:04.369313
8332 11:06:04.369419
8333 11:06:04.375820 [DQSOSCAuto] RK1, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8334 11:06:04.379408 CH0 RK1: MR19=303, MR18=1509
8335 11:06:04.386115 CH0_RK1: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
8336 11:06:04.389339 [RxdqsGatingPostProcess] freq 1600
8337 11:06:04.392668 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8338 11:06:04.396012 best DQS0 dly(2T, 0.5T) = (1, 1)
8339 11:06:04.399291 best DQS1 dly(2T, 0.5T) = (1, 1)
8340 11:06:04.402749 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8341 11:06:04.406149 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8342 11:06:04.409302 best DQS0 dly(2T, 0.5T) = (1, 1)
8343 11:06:04.412682 best DQS1 dly(2T, 0.5T) = (1, 1)
8344 11:06:04.415709 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8345 11:06:04.418946 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8346 11:06:04.422730 Pre-setting of DQS Precalculation
8347 11:06:04.425930 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8348 11:06:04.426017 ==
8349 11:06:04.428923 Dram Type= 6, Freq= 0, CH_1, rank 0
8350 11:06:04.432243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 11:06:04.432326 ==
8352 11:06:04.438941 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8353 11:06:04.442530 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8354 11:06:04.448937 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8355 11:06:04.452511 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8356 11:06:04.462268 [CA 0] Center 43 (14~73) winsize 60
8357 11:06:04.465952 [CA 1] Center 43 (14~72) winsize 59
8358 11:06:04.469300 [CA 2] Center 38 (9~67) winsize 59
8359 11:06:04.472514 [CA 3] Center 37 (8~66) winsize 59
8360 11:06:04.476014 [CA 4] Center 38 (8~68) winsize 61
8361 11:06:04.479188 [CA 5] Center 36 (7~66) winsize 60
8362 11:06:04.479299
8363 11:06:04.482572 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8364 11:06:04.482656
8365 11:06:04.485712 [CATrainingPosCal] consider 1 rank data
8366 11:06:04.488747 u2DelayCellTimex100 = 275/100 ps
8367 11:06:04.492352 CA0 delay=43 (14~73),Diff = 7 PI (24 cell)
8368 11:06:04.498966 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8369 11:06:04.502255 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8370 11:06:04.505898 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8371 11:06:04.508862 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8372 11:06:04.512463 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8373 11:06:04.512557
8374 11:06:04.516019 CA PerBit enable=1, Macro0, CA PI delay=36
8375 11:06:04.516114
8376 11:06:04.519054 [CBTSetCACLKResult] CA Dly = 36
8377 11:06:04.522644 CS Dly: 9 (0~40)
8378 11:06:04.525460 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8379 11:06:04.528967 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8380 11:06:04.529044 ==
8381 11:06:04.532472 Dram Type= 6, Freq= 0, CH_1, rank 1
8382 11:06:04.535471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8383 11:06:04.535549 ==
8384 11:06:04.542290 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8385 11:06:04.545641 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8386 11:06:04.552111 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8387 11:06:04.555790 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8388 11:06:04.565591 [CA 0] Center 43 (14~72) winsize 59
8389 11:06:04.569331 [CA 1] Center 43 (14~72) winsize 59
8390 11:06:04.572365 [CA 2] Center 38 (9~67) winsize 59
8391 11:06:04.575615 [CA 3] Center 37 (8~67) winsize 60
8392 11:06:04.579213 [CA 4] Center 38 (8~68) winsize 61
8393 11:06:04.581992 [CA 5] Center 37 (8~66) winsize 59
8394 11:06:04.582101
8395 11:06:04.585505 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8396 11:06:04.585583
8397 11:06:04.588795 [CATrainingPosCal] consider 2 rank data
8398 11:06:04.591953 u2DelayCellTimex100 = 275/100 ps
8399 11:06:04.595599 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8400 11:06:04.602492 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8401 11:06:04.605859 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8402 11:06:04.608677 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8403 11:06:04.612421 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8404 11:06:04.615814 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8405 11:06:04.615896
8406 11:06:04.619390 CA PerBit enable=1, Macro0, CA PI delay=37
8407 11:06:04.619509
8408 11:06:04.622731 [CBTSetCACLKResult] CA Dly = 37
8409 11:06:04.622814 CS Dly: 11 (0~45)
8410 11:06:04.629158 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8411 11:06:04.632394 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8412 11:06:04.632506
8413 11:06:04.635886 ----->DramcWriteLeveling(PI) begin...
8414 11:06:04.635970 ==
8415 11:06:04.638916 Dram Type= 6, Freq= 0, CH_1, rank 0
8416 11:06:04.642313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 11:06:04.642405 ==
8418 11:06:04.645533 Write leveling (Byte 0): 27 => 27
8419 11:06:04.648827 Write leveling (Byte 1): 27 => 27
8420 11:06:04.652531 DramcWriteLeveling(PI) end<-----
8421 11:06:04.652621
8422 11:06:04.652701 ==
8423 11:06:04.655903 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 11:06:04.662604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8425 11:06:04.662735 ==
8426 11:06:04.662852 [Gating] SW mode calibration
8427 11:06:04.672131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8428 11:06:04.675509 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8429 11:06:04.679077 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 11:06:04.685206 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 11:06:04.688695 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 11:06:04.692552 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 11:06:04.699082 1 4 16 | B1->B0 | 2e2e 2727 | 1 1 | (1 1) (1 1)
8434 11:06:04.701928 1 4 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8435 11:06:04.705854 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8436 11:06:04.712266 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8437 11:06:04.715354 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8438 11:06:04.718731 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8439 11:06:04.725792 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8440 11:06:04.729750 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8441 11:06:04.732263 1 5 16 | B1->B0 | 2a2a 3333 | 1 0 | (1 0) (0 1)
8442 11:06:04.738816 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8443 11:06:04.742111 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8444 11:06:04.745363 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8445 11:06:04.752436 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8446 11:06:04.755782 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8447 11:06:04.758790 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 11:06:04.762612 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 11:06:04.768818 1 6 16 | B1->B0 | 3d3d 2d2d | 0 1 | (0 0) (0 0)
8450 11:06:04.772753 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8451 11:06:04.775931 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8452 11:06:04.782594 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8453 11:06:04.786135 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8454 11:06:04.789591 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8455 11:06:04.795686 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8456 11:06:04.798920 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 11:06:04.802449 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8458 11:06:04.809434 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8459 11:06:04.812805 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 11:06:04.815315 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 11:06:04.822283 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 11:06:04.825658 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 11:06:04.829063 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 11:06:04.835551 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 11:06:04.839179 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 11:06:04.842951 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 11:06:04.849094 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 11:06:04.852601 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 11:06:04.855371 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 11:06:04.859708 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 11:06:04.866007 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8472 11:06:04.868855 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 11:06:04.872381 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8474 11:06:04.878861 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8475 11:06:04.882466 Total UI for P1: 0, mck2ui 16
8476 11:06:04.886321 best dqsien dly found for B0: ( 1, 9, 16)
8477 11:06:04.886441 Total UI for P1: 0, mck2ui 16
8478 11:06:04.892032 best dqsien dly found for B1: ( 1, 9, 16)
8479 11:06:04.895564 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8480 11:06:04.898910 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8481 11:06:04.899020
8482 11:06:04.902239 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8483 11:06:04.905724 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8484 11:06:04.909112 [Gating] SW calibration Done
8485 11:06:04.909218 ==
8486 11:06:04.912251 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 11:06:04.915987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 11:06:04.916093 ==
8489 11:06:04.918958 RX Vref Scan: 0
8490 11:06:04.919042
8491 11:06:04.919125 RX Vref 0 -> 0, step: 1
8492 11:06:04.919225
8493 11:06:04.922117 RX Delay 0 -> 252, step: 8
8494 11:06:04.925794 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8495 11:06:04.932107 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8496 11:06:04.935504 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8497 11:06:04.939288 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8498 11:06:04.942241 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8499 11:06:04.945649 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8500 11:06:04.952220 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8501 11:06:04.955336 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8502 11:06:04.959095 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8503 11:06:04.962414 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8504 11:06:04.965529 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8505 11:06:04.972224 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8506 11:06:04.975367 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8507 11:06:04.979035 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8508 11:06:04.982167 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8509 11:06:04.985752 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8510 11:06:04.988747 ==
8511 11:06:04.988851 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 11:06:04.995648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 11:06:04.995756 ==
8514 11:06:04.995858 DQS Delay:
8515 11:06:04.998854 DQS0 = 0, DQS1 = 0
8516 11:06:04.998937 DQM Delay:
8517 11:06:05.002284 DQM0 = 134, DQM1 = 126
8518 11:06:05.002389 DQ Delay:
8519 11:06:05.005685 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8520 11:06:05.008933 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8521 11:06:05.012329 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8522 11:06:05.015596 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8523 11:06:05.015702
8524 11:06:05.015804
8525 11:06:05.015904 ==
8526 11:06:05.018909 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 11:06:05.025453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 11:06:05.025540 ==
8529 11:06:05.025606
8530 11:06:05.025666
8531 11:06:05.025725 TX Vref Scan disable
8532 11:06:05.028862 == TX Byte 0 ==
8533 11:06:05.031969 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8534 11:06:05.035333 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8535 11:06:05.039303 == TX Byte 1 ==
8536 11:06:05.041916 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8537 11:06:05.048722 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8538 11:06:05.048830 ==
8539 11:06:05.051973 Dram Type= 6, Freq= 0, CH_1, rank 0
8540 11:06:05.055673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8541 11:06:05.055774 ==
8542 11:06:05.068858
8543 11:06:05.072046 TX Vref early break, caculate TX vref
8544 11:06:05.075712 TX Vref=16, minBit 5, minWin=21, winSum=360
8545 11:06:05.078865 TX Vref=18, minBit 8, minWin=21, winSum=370
8546 11:06:05.082320 TX Vref=20, minBit 5, minWin=22, winSum=378
8547 11:06:05.085170 TX Vref=22, minBit 5, minWin=23, winSum=390
8548 11:06:05.088544 TX Vref=24, minBit 1, minWin=24, winSum=403
8549 11:06:05.095338 TX Vref=26, minBit 5, minWin=25, winSum=412
8550 11:06:05.098532 TX Vref=28, minBit 5, minWin=25, winSum=418
8551 11:06:05.102206 TX Vref=30, minBit 0, minWin=25, winSum=415
8552 11:06:05.105371 TX Vref=32, minBit 0, minWin=24, winSum=408
8553 11:06:05.108982 TX Vref=34, minBit 0, minWin=24, winSum=397
8554 11:06:05.111803 TX Vref=36, minBit 5, minWin=23, winSum=387
8555 11:06:05.118819 [TxChooseVref] Worse bit 5, Min win 25, Win sum 418, Final Vref 28
8556 11:06:05.118941
8557 11:06:05.122261 Final TX Range 0 Vref 28
8558 11:06:05.122388
8559 11:06:05.122509 ==
8560 11:06:05.125659 Dram Type= 6, Freq= 0, CH_1, rank 0
8561 11:06:05.129399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8562 11:06:05.129527 ==
8563 11:06:05.129641
8564 11:06:05.129750
8565 11:06:05.132700 TX Vref Scan disable
8566 11:06:05.138652 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8567 11:06:05.138760 == TX Byte 0 ==
8568 11:06:05.142012 u2DelayCellOfst[0]=17 cells (5 PI)
8569 11:06:05.145589 u2DelayCellOfst[1]=14 cells (4 PI)
8570 11:06:05.149012 u2DelayCellOfst[2]=0 cells (0 PI)
8571 11:06:05.151966 u2DelayCellOfst[3]=7 cells (2 PI)
8572 11:06:05.155613 u2DelayCellOfst[4]=10 cells (3 PI)
8573 11:06:05.158846 u2DelayCellOfst[5]=17 cells (5 PI)
8574 11:06:05.162022 u2DelayCellOfst[6]=17 cells (5 PI)
8575 11:06:05.165244 u2DelayCellOfst[7]=7 cells (2 PI)
8576 11:06:05.168895 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8577 11:06:05.172141 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8578 11:06:05.172269 == TX Byte 1 ==
8579 11:06:05.175515 u2DelayCellOfst[8]=0 cells (0 PI)
8580 11:06:05.178600 u2DelayCellOfst[9]=0 cells (0 PI)
8581 11:06:05.181853 u2DelayCellOfst[10]=7 cells (2 PI)
8582 11:06:05.185754 u2DelayCellOfst[11]=3 cells (1 PI)
8583 11:06:05.188324 u2DelayCellOfst[12]=10 cells (3 PI)
8584 11:06:05.191754 u2DelayCellOfst[13]=14 cells (4 PI)
8585 11:06:05.195181 u2DelayCellOfst[14]=14 cells (4 PI)
8586 11:06:05.198649 u2DelayCellOfst[15]=14 cells (4 PI)
8587 11:06:05.202044 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8588 11:06:05.208569 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8589 11:06:05.208652 DramC Write-DBI on
8590 11:06:05.208717 ==
8591 11:06:05.211781 Dram Type= 6, Freq= 0, CH_1, rank 0
8592 11:06:05.215051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8593 11:06:05.215128 ==
8594 11:06:05.218403
8595 11:06:05.218479
8596 11:06:05.218541 TX Vref Scan disable
8597 11:06:05.221937 == TX Byte 0 ==
8598 11:06:05.225328 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8599 11:06:05.228409 == TX Byte 1 ==
8600 11:06:05.232269 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8601 11:06:05.232371 DramC Write-DBI off
8602 11:06:05.232468
8603 11:06:05.235256 [DATLAT]
8604 11:06:05.235328 Freq=1600, CH1 RK0
8605 11:06:05.235389
8606 11:06:05.238630 DATLAT Default: 0xf
8607 11:06:05.238732 0, 0xFFFF, sum = 0
8608 11:06:05.241947 1, 0xFFFF, sum = 0
8609 11:06:05.242044 2, 0xFFFF, sum = 0
8610 11:06:05.245460 3, 0xFFFF, sum = 0
8611 11:06:05.245584 4, 0xFFFF, sum = 0
8612 11:06:05.248916 5, 0xFFFF, sum = 0
8613 11:06:05.249031 6, 0xFFFF, sum = 0
8614 11:06:05.252413 7, 0xFFFF, sum = 0
8615 11:06:05.255281 8, 0xFFFF, sum = 0
8616 11:06:05.255383 9, 0xFFFF, sum = 0
8617 11:06:05.258820 10, 0xFFFF, sum = 0
8618 11:06:05.258921 11, 0xFFFF, sum = 0
8619 11:06:05.262239 12, 0xFFFF, sum = 0
8620 11:06:05.262348 13, 0xFFFF, sum = 0
8621 11:06:05.265203 14, 0x0, sum = 1
8622 11:06:05.265303 15, 0x0, sum = 2
8623 11:06:05.268439 16, 0x0, sum = 3
8624 11:06:05.268511 17, 0x0, sum = 4
8625 11:06:05.268580 best_step = 15
8626 11:06:05.272188
8627 11:06:05.272266 ==
8628 11:06:05.275171 Dram Type= 6, Freq= 0, CH_1, rank 0
8629 11:06:05.278477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8630 11:06:05.278549 ==
8631 11:06:05.278618 RX Vref Scan: 1
8632 11:06:05.278677
8633 11:06:05.282065 Set Vref Range= 24 -> 127
8634 11:06:05.282133
8635 11:06:05.285473 RX Vref 24 -> 127, step: 1
8636 11:06:05.285604
8637 11:06:05.288803 RX Delay 11 -> 252, step: 4
8638 11:06:05.288924
8639 11:06:05.292080 Set Vref, RX VrefLevel [Byte0]: 24
8640 11:06:05.295406 [Byte1]: 24
8641 11:06:05.295535
8642 11:06:05.298832 Set Vref, RX VrefLevel [Byte0]: 25
8643 11:06:05.301934 [Byte1]: 25
8644 11:06:05.302061
8645 11:06:05.305534 Set Vref, RX VrefLevel [Byte0]: 26
8646 11:06:05.308893 [Byte1]: 26
8647 11:06:05.312219
8648 11:06:05.312351 Set Vref, RX VrefLevel [Byte0]: 27
8649 11:06:05.315325 [Byte1]: 27
8650 11:06:05.319966
8651 11:06:05.320047 Set Vref, RX VrefLevel [Byte0]: 28
8652 11:06:05.323346 [Byte1]: 28
8653 11:06:05.327212
8654 11:06:05.327288 Set Vref, RX VrefLevel [Byte0]: 29
8655 11:06:05.330391 [Byte1]: 29
8656 11:06:05.335056
8657 11:06:05.335139 Set Vref, RX VrefLevel [Byte0]: 30
8658 11:06:05.338289 [Byte1]: 30
8659 11:06:05.342742
8660 11:06:05.342821 Set Vref, RX VrefLevel [Byte0]: 31
8661 11:06:05.345736 [Byte1]: 31
8662 11:06:05.349885
8663 11:06:05.349963 Set Vref, RX VrefLevel [Byte0]: 32
8664 11:06:05.353327 [Byte1]: 32
8665 11:06:05.357516
8666 11:06:05.357596 Set Vref, RX VrefLevel [Byte0]: 33
8667 11:06:05.361076 [Byte1]: 33
8668 11:06:05.365637
8669 11:06:05.365711 Set Vref, RX VrefLevel [Byte0]: 34
8670 11:06:05.368543 [Byte1]: 34
8671 11:06:05.373197
8672 11:06:05.373299 Set Vref, RX VrefLevel [Byte0]: 35
8673 11:06:05.376346 [Byte1]: 35
8674 11:06:05.380319
8675 11:06:05.380392 Set Vref, RX VrefLevel [Byte0]: 36
8676 11:06:05.384027 [Byte1]: 36
8677 11:06:05.388500
8678 11:06:05.388587 Set Vref, RX VrefLevel [Byte0]: 37
8679 11:06:05.391451 [Byte1]: 37
8680 11:06:05.395938
8681 11:06:05.396014 Set Vref, RX VrefLevel [Byte0]: 38
8682 11:06:05.398974 [Byte1]: 38
8683 11:06:05.403340
8684 11:06:05.403419 Set Vref, RX VrefLevel [Byte0]: 39
8685 11:06:05.406989 [Byte1]: 39
8686 11:06:05.411196
8687 11:06:05.411274 Set Vref, RX VrefLevel [Byte0]: 40
8688 11:06:05.414102 [Byte1]: 40
8689 11:06:05.418697
8690 11:06:05.418772 Set Vref, RX VrefLevel [Byte0]: 41
8691 11:06:05.425074 [Byte1]: 41
8692 11:06:05.425150
8693 11:06:05.428296 Set Vref, RX VrefLevel [Byte0]: 42
8694 11:06:05.431856 [Byte1]: 42
8695 11:06:05.431931
8696 11:06:05.435009 Set Vref, RX VrefLevel [Byte0]: 43
8697 11:06:05.438684 [Byte1]: 43
8698 11:06:05.438761
8699 11:06:05.441853 Set Vref, RX VrefLevel [Byte0]: 44
8700 11:06:05.445011 [Byte1]: 44
8701 11:06:05.449043
8702 11:06:05.449149 Set Vref, RX VrefLevel [Byte0]: 45
8703 11:06:05.452445 [Byte1]: 45
8704 11:06:05.457023
8705 11:06:05.457106 Set Vref, RX VrefLevel [Byte0]: 46
8706 11:06:05.460024 [Byte1]: 46
8707 11:06:05.464721
8708 11:06:05.464795 Set Vref, RX VrefLevel [Byte0]: 47
8709 11:06:05.467917 [Byte1]: 47
8710 11:06:05.471879
8711 11:06:05.471957 Set Vref, RX VrefLevel [Byte0]: 48
8712 11:06:05.475241 [Byte1]: 48
8713 11:06:05.479582
8714 11:06:05.479658 Set Vref, RX VrefLevel [Byte0]: 49
8715 11:06:05.483288 [Byte1]: 49
8716 11:06:05.487189
8717 11:06:05.487272 Set Vref, RX VrefLevel [Byte0]: 50
8718 11:06:05.490555 [Byte1]: 50
8719 11:06:05.495052
8720 11:06:05.495125 Set Vref, RX VrefLevel [Byte0]: 51
8721 11:06:05.497930 [Byte1]: 51
8722 11:06:05.502112
8723 11:06:05.502199 Set Vref, RX VrefLevel [Byte0]: 52
8724 11:06:05.505761 [Byte1]: 52
8725 11:06:05.509971
8726 11:06:05.510049 Set Vref, RX VrefLevel [Byte0]: 53
8727 11:06:05.513357 [Byte1]: 53
8728 11:06:05.517868
8729 11:06:05.517951 Set Vref, RX VrefLevel [Byte0]: 54
8730 11:06:05.523979 [Byte1]: 54
8731 11:06:05.524087
8732 11:06:05.527500 Set Vref, RX VrefLevel [Byte0]: 55
8733 11:06:05.530844 [Byte1]: 55
8734 11:06:05.530949
8735 11:06:05.534130 Set Vref, RX VrefLevel [Byte0]: 56
8736 11:06:05.537333 [Byte1]: 56
8737 11:06:05.537418
8738 11:06:05.540640 Set Vref, RX VrefLevel [Byte0]: 57
8739 11:06:05.544289 [Byte1]: 57
8740 11:06:05.548038
8741 11:06:05.548110 Set Vref, RX VrefLevel [Byte0]: 58
8742 11:06:05.551471 [Byte1]: 58
8743 11:06:05.555610
8744 11:06:05.555685 Set Vref, RX VrefLevel [Byte0]: 59
8745 11:06:05.559293 [Byte1]: 59
8746 11:06:05.563193
8747 11:06:05.563269 Set Vref, RX VrefLevel [Byte0]: 60
8748 11:06:05.566741 [Byte1]: 60
8749 11:06:05.571195
8750 11:06:05.571273 Set Vref, RX VrefLevel [Byte0]: 61
8751 11:06:05.574256 [Byte1]: 61
8752 11:06:05.578667
8753 11:06:05.578773 Set Vref, RX VrefLevel [Byte0]: 62
8754 11:06:05.581894 [Byte1]: 62
8755 11:06:05.586252
8756 11:06:05.586365 Set Vref, RX VrefLevel [Byte0]: 63
8757 11:06:05.589541 [Byte1]: 63
8758 11:06:05.593948
8759 11:06:05.594050 Set Vref, RX VrefLevel [Byte0]: 64
8760 11:06:05.597136 [Byte1]: 64
8761 11:06:05.601155
8762 11:06:05.601261 Set Vref, RX VrefLevel [Byte0]: 65
8763 11:06:05.604635 [Byte1]: 65
8764 11:06:05.609253
8765 11:06:05.609345 Set Vref, RX VrefLevel [Byte0]: 66
8766 11:06:05.612314 [Byte1]: 66
8767 11:06:05.616505
8768 11:06:05.616619 Set Vref, RX VrefLevel [Byte0]: 67
8769 11:06:05.620011 [Byte1]: 67
8770 11:06:05.624036
8771 11:06:05.624120 Set Vref, RX VrefLevel [Byte0]: 68
8772 11:06:05.627319 [Byte1]: 68
8773 11:06:05.632052
8774 11:06:05.632143 Set Vref, RX VrefLevel [Byte0]: 69
8775 11:06:05.635438 [Byte1]: 69
8776 11:06:05.639510
8777 11:06:05.639591 Set Vref, RX VrefLevel [Byte0]: 70
8778 11:06:05.642514 [Byte1]: 70
8779 11:06:05.647101
8780 11:06:05.647213 Set Vref, RX VrefLevel [Byte0]: 71
8781 11:06:05.650053 [Byte1]: 71
8782 11:06:05.654549
8783 11:06:05.654631 Set Vref, RX VrefLevel [Byte0]: 72
8784 11:06:05.658134 [Byte1]: 72
8785 11:06:05.662208
8786 11:06:05.662284 Set Vref, RX VrefLevel [Byte0]: 73
8787 11:06:05.665683 [Byte1]: 73
8788 11:06:05.670231
8789 11:06:05.670310 Set Vref, RX VrefLevel [Byte0]: 74
8790 11:06:05.672999 [Byte1]: 74
8791 11:06:05.677684
8792 11:06:05.677758 Set Vref, RX VrefLevel [Byte0]: 75
8793 11:06:05.680812 [Byte1]: 75
8794 11:06:05.685225
8795 11:06:05.685299 Final RX Vref Byte 0 = 57 to rank0
8796 11:06:05.688375 Final RX Vref Byte 1 = 56 to rank0
8797 11:06:05.692005 Final RX Vref Byte 0 = 57 to rank1
8798 11:06:05.695198 Final RX Vref Byte 1 = 56 to rank1==
8799 11:06:05.698885 Dram Type= 6, Freq= 0, CH_1, rank 0
8800 11:06:05.705586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 11:06:05.705670 ==
8802 11:06:05.705736 DQS Delay:
8803 11:06:05.705797 DQS0 = 0, DQS1 = 0
8804 11:06:05.708641 DQM Delay:
8805 11:06:05.708723 DQM0 = 131, DQM1 = 124
8806 11:06:05.711743 DQ Delay:
8807 11:06:05.715492 DQ0 =134, DQ1 =124, DQ2 =120, DQ3 =130
8808 11:06:05.719249 DQ4 =130, DQ5 =142, DQ6 =144, DQ7 =128
8809 11:06:05.722286 DQ8 =110, DQ9 =114, DQ10 =126, DQ11 =118
8810 11:06:05.725499 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8811 11:06:05.725574
8812 11:06:05.725643
8813 11:06:05.725702
8814 11:06:05.728492 [DramC_TX_OE_Calibration] TA2
8815 11:06:05.732061 Original DQ_B0 (3 6) =30, OEN = 27
8816 11:06:05.735529 Original DQ_B1 (3 6) =30, OEN = 27
8817 11:06:05.738526 24, 0x0, End_B0=24 End_B1=24
8818 11:06:05.738602 25, 0x0, End_B0=25 End_B1=25
8819 11:06:05.741751 26, 0x0, End_B0=26 End_B1=26
8820 11:06:05.745037 27, 0x0, End_B0=27 End_B1=27
8821 11:06:05.748696 28, 0x0, End_B0=28 End_B1=28
8822 11:06:05.748822 29, 0x0, End_B0=29 End_B1=29
8823 11:06:05.751718 30, 0x0, End_B0=30 End_B1=30
8824 11:06:05.755530 31, 0x4141, End_B0=30 End_B1=30
8825 11:06:05.758559 Byte0 end_step=30 best_step=27
8826 11:06:05.761962 Byte1 end_step=30 best_step=27
8827 11:06:05.765197 Byte0 TX OE(2T, 0.5T) = (3, 3)
8828 11:06:05.765272 Byte1 TX OE(2T, 0.5T) = (3, 3)
8829 11:06:05.765342
8830 11:06:05.765401
8831 11:06:05.775410 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8832 11:06:05.778436 CH1 RK0: MR19=302, MR18=12FE
8833 11:06:05.785090 CH1_RK0: MR19=0x302, MR18=0x12FE, DQSOSC=400, MR23=63, INC=23, DEC=15
8834 11:06:05.785170
8835 11:06:05.788599 ----->DramcWriteLeveling(PI) begin...
8836 11:06:05.788682 ==
8837 11:06:05.791783 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 11:06:05.795513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 11:06:05.795588 ==
8840 11:06:05.798860 Write leveling (Byte 0): 25 => 25
8841 11:06:05.802414 Write leveling (Byte 1): 25 => 25
8842 11:06:05.805702 DramcWriteLeveling(PI) end<-----
8843 11:06:05.805807
8844 11:06:05.805899 ==
8845 11:06:05.808417 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 11:06:05.812292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 11:06:05.812373 ==
8848 11:06:05.815240 [Gating] SW mode calibration
8849 11:06:05.821912 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8850 11:06:05.829095 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8851 11:06:05.832198 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8852 11:06:05.835450 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8853 11:06:05.841946 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
8854 11:06:05.845622 1 4 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
8855 11:06:05.848357 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8856 11:06:05.855546 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8857 11:06:05.858429 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8858 11:06:05.861710 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8859 11:06:05.868721 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8860 11:06:05.871805 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8861 11:06:05.874914 1 5 8 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
8862 11:06:05.878316 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8863 11:06:05.885007 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8864 11:06:05.888115 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8865 11:06:05.891509 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8866 11:06:05.898263 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8867 11:06:05.901585 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8868 11:06:05.904930 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8869 11:06:05.911868 1 6 8 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
8870 11:06:05.915241 1 6 12 | B1->B0 | 3636 4545 | 1 0 | (0 0) (0 0)
8871 11:06:05.918107 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8872 11:06:05.924808 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8873 11:06:05.928181 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8874 11:06:05.931669 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8875 11:06:05.938252 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8876 11:06:05.941652 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8877 11:06:05.945020 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8878 11:06:05.951621 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8879 11:06:05.954806 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8880 11:06:05.957939 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 11:06:05.964510 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 11:06:05.967898 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 11:06:05.971239 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 11:06:05.978274 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 11:06:05.981594 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 11:06:05.985212 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 11:06:05.988389 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8888 11:06:05.995475 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8889 11:06:05.998546 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8890 11:06:06.001727 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 11:06:06.008610 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 11:06:06.011633 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8893 11:06:06.015335 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8894 11:06:06.021530 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8895 11:06:06.021608 Total UI for P1: 0, mck2ui 16
8896 11:06:06.028209 best dqsien dly found for B0: ( 1, 9, 6)
8897 11:06:06.031709 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8898 11:06:06.035230 Total UI for P1: 0, mck2ui 16
8899 11:06:06.038120 best dqsien dly found for B1: ( 1, 9, 12)
8900 11:06:06.041899 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8901 11:06:06.044858 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8902 11:06:06.044933
8903 11:06:06.048253 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8904 11:06:06.051787 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8905 11:06:06.055358 [Gating] SW calibration Done
8906 11:06:06.055436 ==
8907 11:06:06.058408 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 11:06:06.061925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 11:06:06.062033 ==
8910 11:06:06.064886 RX Vref Scan: 0
8911 11:06:06.064999
8912 11:06:06.068719 RX Vref 0 -> 0, step: 1
8913 11:06:06.068824
8914 11:06:06.068914 RX Delay 0 -> 252, step: 8
8915 11:06:06.074972 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8916 11:06:06.078457 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8917 11:06:06.081744 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8918 11:06:06.084872 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8919 11:06:06.088552 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8920 11:06:06.095090 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8921 11:06:06.098375 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8922 11:06:06.102052 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8923 11:06:06.104819 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8924 11:06:06.108578 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8925 11:06:06.115103 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8926 11:06:06.118602 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8927 11:06:06.121726 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8928 11:06:06.125080 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8929 11:06:06.128366 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8930 11:06:06.135023 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8931 11:06:06.135104 ==
8932 11:06:06.138742 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 11:06:06.141593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 11:06:06.141704 ==
8935 11:06:06.141800 DQS Delay:
8936 11:06:06.144876 DQS0 = 0, DQS1 = 0
8937 11:06:06.144950 DQM Delay:
8938 11:06:06.148351 DQM0 = 132, DQM1 = 127
8939 11:06:06.148430 DQ Delay:
8940 11:06:06.151531 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8941 11:06:06.154635 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8942 11:06:06.158076 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8943 11:06:06.161666 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8944 11:06:06.161766
8945 11:06:06.164757
8946 11:06:06.164863 ==
8947 11:06:06.168607 Dram Type= 6, Freq= 0, CH_1, rank 1
8948 11:06:06.171929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8949 11:06:06.172023 ==
8950 11:06:06.172086
8951 11:06:06.172144
8952 11:06:06.174792 TX Vref Scan disable
8953 11:06:06.174868 == TX Byte 0 ==
8954 11:06:06.181081 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8955 11:06:06.184743 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8956 11:06:06.184842 == TX Byte 1 ==
8957 11:06:06.191481 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8958 11:06:06.194791 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8959 11:06:06.194880 ==
8960 11:06:06.198333 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 11:06:06.201414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 11:06:06.201525 ==
8963 11:06:06.215509
8964 11:06:06.218795 TX Vref early break, caculate TX vref
8965 11:06:06.222329 TX Vref=16, minBit 0, minWin=23, winSum=380
8966 11:06:06.225642 TX Vref=18, minBit 6, minWin=24, winSum=398
8967 11:06:06.228869 TX Vref=20, minBit 8, minWin=24, winSum=401
8968 11:06:06.232432 TX Vref=22, minBit 5, minWin=24, winSum=410
8969 11:06:06.235826 TX Vref=24, minBit 6, minWin=25, winSum=417
8970 11:06:06.239039 TX Vref=26, minBit 0, minWin=26, winSum=424
8971 11:06:06.245579 TX Vref=28, minBit 0, minWin=26, winSum=428
8972 11:06:06.249004 TX Vref=30, minBit 1, minWin=26, winSum=430
8973 11:06:06.252418 TX Vref=32, minBit 0, minWin=25, winSum=421
8974 11:06:06.255285 TX Vref=34, minBit 0, minWin=25, winSum=410
8975 11:06:06.258528 TX Vref=36, minBit 0, minWin=24, winSum=406
8976 11:06:06.265625 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
8977 11:06:06.265733
8978 11:06:06.268689 Final TX Range 0 Vref 30
8979 11:06:06.268789
8980 11:06:06.268878 ==
8981 11:06:06.272308 Dram Type= 6, Freq= 0, CH_1, rank 1
8982 11:06:06.275498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8983 11:06:06.275586 ==
8984 11:06:06.275675
8985 11:06:06.275757
8986 11:06:06.278838 TX Vref Scan disable
8987 11:06:06.285491 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8988 11:06:06.285593 == TX Byte 0 ==
8989 11:06:06.289000 u2DelayCellOfst[0]=17 cells (5 PI)
8990 11:06:06.292168 u2DelayCellOfst[1]=10 cells (3 PI)
8991 11:06:06.295679 u2DelayCellOfst[2]=0 cells (0 PI)
8992 11:06:06.298755 u2DelayCellOfst[3]=3 cells (1 PI)
8993 11:06:06.302100 u2DelayCellOfst[4]=10 cells (3 PI)
8994 11:06:06.306485 u2DelayCellOfst[5]=21 cells (6 PI)
8995 11:06:06.308593 u2DelayCellOfst[6]=17 cells (5 PI)
8996 11:06:06.312560 u2DelayCellOfst[7]=7 cells (2 PI)
8997 11:06:06.315184 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8998 11:06:06.319008 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8999 11:06:06.321897 == TX Byte 1 ==
9000 11:06:06.321984 u2DelayCellOfst[8]=0 cells (0 PI)
9001 11:06:06.325653 u2DelayCellOfst[9]=3 cells (1 PI)
9002 11:06:06.328827 u2DelayCellOfst[10]=10 cells (3 PI)
9003 11:06:06.331944 u2DelayCellOfst[11]=3 cells (1 PI)
9004 11:06:06.335264 u2DelayCellOfst[12]=10 cells (3 PI)
9005 11:06:06.339116 u2DelayCellOfst[13]=14 cells (4 PI)
9006 11:06:06.341776 u2DelayCellOfst[14]=14 cells (4 PI)
9007 11:06:06.345298 u2DelayCellOfst[15]=17 cells (5 PI)
9008 11:06:06.348725 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9009 11:06:06.355499 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9010 11:06:06.355630 DramC Write-DBI on
9011 11:06:06.355743 ==
9012 11:06:06.358803 Dram Type= 6, Freq= 0, CH_1, rank 1
9013 11:06:06.362078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9014 11:06:06.365525 ==
9015 11:06:06.365649
9016 11:06:06.365765
9017 11:06:06.365877 TX Vref Scan disable
9018 11:06:06.368443 == TX Byte 0 ==
9019 11:06:06.372057 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9020 11:06:06.375481 == TX Byte 1 ==
9021 11:06:06.379016 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9022 11:06:06.379144 DramC Write-DBI off
9023 11:06:06.382405
9024 11:06:06.382529 [DATLAT]
9025 11:06:06.382642 Freq=1600, CH1 RK1
9026 11:06:06.382753
9027 11:06:06.385342 DATLAT Default: 0xf
9028 11:06:06.385469 0, 0xFFFF, sum = 0
9029 11:06:06.388704 1, 0xFFFF, sum = 0
9030 11:06:06.388832 2, 0xFFFF, sum = 0
9031 11:06:06.392134 3, 0xFFFF, sum = 0
9032 11:06:06.395378 4, 0xFFFF, sum = 0
9033 11:06:06.395508 5, 0xFFFF, sum = 0
9034 11:06:06.398728 6, 0xFFFF, sum = 0
9035 11:06:06.398854 7, 0xFFFF, sum = 0
9036 11:06:06.401893 8, 0xFFFF, sum = 0
9037 11:06:06.402021 9, 0xFFFF, sum = 0
9038 11:06:06.405332 10, 0xFFFF, sum = 0
9039 11:06:06.405460 11, 0xFFFF, sum = 0
9040 11:06:06.408710 12, 0xFFFF, sum = 0
9041 11:06:06.408834 13, 0xFFFF, sum = 0
9042 11:06:06.411935 14, 0x0, sum = 1
9043 11:06:06.412064 15, 0x0, sum = 2
9044 11:06:06.415136 16, 0x0, sum = 3
9045 11:06:06.415264 17, 0x0, sum = 4
9046 11:06:06.418686 best_step = 15
9047 11:06:06.418810
9048 11:06:06.418923 ==
9049 11:06:06.421945 Dram Type= 6, Freq= 0, CH_1, rank 1
9050 11:06:06.425328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9051 11:06:06.425452 ==
9052 11:06:06.425566 RX Vref Scan: 0
9053 11:06:06.425674
9054 11:06:06.428628 RX Vref 0 -> 0, step: 1
9055 11:06:06.428751
9056 11:06:06.432016 RX Delay 11 -> 252, step: 4
9057 11:06:06.435349 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
9058 11:06:06.441687 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9059 11:06:06.445059 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9060 11:06:06.448850 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9061 11:06:06.452055 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
9062 11:06:06.455513 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9063 11:06:06.458906 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9064 11:06:06.465502 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
9065 11:06:06.468630 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9066 11:06:06.471950 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9067 11:06:06.475299 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9068 11:06:06.481950 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
9069 11:06:06.485464 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9070 11:06:06.488554 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9071 11:06:06.491924 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9072 11:06:06.495407 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9073 11:06:06.495507 ==
9074 11:06:06.498289 Dram Type= 6, Freq= 0, CH_1, rank 1
9075 11:06:06.505086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9076 11:06:06.505170 ==
9077 11:06:06.505236 DQS Delay:
9078 11:06:06.508527 DQS0 = 0, DQS1 = 0
9079 11:06:06.508609 DQM Delay:
9080 11:06:06.511875 DQM0 = 129, DQM1 = 126
9081 11:06:06.511964 DQ Delay:
9082 11:06:06.515168 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9083 11:06:06.518556 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9084 11:06:06.521826 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =116
9085 11:06:06.525348 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
9086 11:06:06.525430
9087 11:06:06.525506
9088 11:06:06.525574
9089 11:06:06.528847 [DramC_TX_OE_Calibration] TA2
9090 11:06:06.531844 Original DQ_B0 (3 6) =30, OEN = 27
9091 11:06:06.535530 Original DQ_B1 (3 6) =30, OEN = 27
9092 11:06:06.538925 24, 0x0, End_B0=24 End_B1=24
9093 11:06:06.539008 25, 0x0, End_B0=25 End_B1=25
9094 11:06:06.542145 26, 0x0, End_B0=26 End_B1=26
9095 11:06:06.545617 27, 0x0, End_B0=27 End_B1=27
9096 11:06:06.548717 28, 0x0, End_B0=28 End_B1=28
9097 11:06:06.552261 29, 0x0, End_B0=29 End_B1=29
9098 11:06:06.552345 30, 0x0, End_B0=30 End_B1=30
9099 11:06:06.555428 31, 0x4141, End_B0=30 End_B1=30
9100 11:06:06.558740 Byte0 end_step=30 best_step=27
9101 11:06:06.562022 Byte1 end_step=30 best_step=27
9102 11:06:06.565413 Byte0 TX OE(2T, 0.5T) = (3, 3)
9103 11:06:06.565495 Byte1 TX OE(2T, 0.5T) = (3, 3)
9104 11:06:06.569536
9105 11:06:06.569617
9106 11:06:06.575567 [DQSOSCAuto] RK1, (LSB)MR18= 0xe14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
9107 11:06:06.578714 CH1 RK1: MR19=303, MR18=E14
9108 11:06:06.585899 CH1_RK1: MR19=0x303, MR18=0xE14, DQSOSC=399, MR23=63, INC=23, DEC=15
9109 11:06:06.588509 [RxdqsGatingPostProcess] freq 1600
9110 11:06:06.592350 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9111 11:06:06.595334 best DQS0 dly(2T, 0.5T) = (1, 1)
9112 11:06:06.598803 best DQS1 dly(2T, 0.5T) = (1, 1)
9113 11:06:06.601929 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9114 11:06:06.606198 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9115 11:06:06.608909 best DQS0 dly(2T, 0.5T) = (1, 1)
9116 11:06:06.612377 best DQS1 dly(2T, 0.5T) = (1, 1)
9117 11:06:06.615578 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9118 11:06:06.618825 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9119 11:06:06.618963 Pre-setting of DQS Precalculation
9120 11:06:06.625383 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9121 11:06:06.631899 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9122 11:06:06.638935 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9123 11:06:06.639061
9124 11:06:06.639183
9125 11:06:06.642129 [Calibration Summary] 3200 Mbps
9126 11:06:06.645410 CH 0, Rank 0
9127 11:06:06.645524 SW Impedance : PASS
9128 11:06:06.648851 DUTY Scan : NO K
9129 11:06:06.651754 ZQ Calibration : PASS
9130 11:06:06.651846 Jitter Meter : NO K
9131 11:06:06.655661 CBT Training : PASS
9132 11:06:06.655798 Write leveling : PASS
9133 11:06:06.658755 RX DQS gating : PASS
9134 11:06:06.661963 RX DQ/DQS(RDDQC) : PASS
9135 11:06:06.662107 TX DQ/DQS : PASS
9136 11:06:06.665305 RX DATLAT : PASS
9137 11:06:06.669167 RX DQ/DQS(Engine): PASS
9138 11:06:06.669298 TX OE : PASS
9139 11:06:06.672023 All Pass.
9140 11:06:06.672183
9141 11:06:06.672297 CH 0, Rank 1
9142 11:06:06.675612 SW Impedance : PASS
9143 11:06:06.675779 DUTY Scan : NO K
9144 11:06:06.678668 ZQ Calibration : PASS
9145 11:06:06.681806 Jitter Meter : NO K
9146 11:06:06.681930 CBT Training : PASS
9147 11:06:06.685251 Write leveling : PASS
9148 11:06:06.688598 RX DQS gating : PASS
9149 11:06:06.688728 RX DQ/DQS(RDDQC) : PASS
9150 11:06:06.692038 TX DQ/DQS : PASS
9151 11:06:06.695628 RX DATLAT : PASS
9152 11:06:06.695755 RX DQ/DQS(Engine): PASS
9153 11:06:06.698419 TX OE : PASS
9154 11:06:06.698542 All Pass.
9155 11:06:06.698664
9156 11:06:06.701985 CH 1, Rank 0
9157 11:06:06.702117 SW Impedance : PASS
9158 11:06:06.705280 DUTY Scan : NO K
9159 11:06:06.705395 ZQ Calibration : PASS
9160 11:06:06.708680 Jitter Meter : NO K
9161 11:06:06.712317 CBT Training : PASS
9162 11:06:06.712398 Write leveling : PASS
9163 11:06:06.715324 RX DQS gating : PASS
9164 11:06:06.718839 RX DQ/DQS(RDDQC) : PASS
9165 11:06:06.718919 TX DQ/DQS : PASS
9166 11:06:06.721770 RX DATLAT : PASS
9167 11:06:06.725123 RX DQ/DQS(Engine): PASS
9168 11:06:06.725203 TX OE : PASS
9169 11:06:06.728404 All Pass.
9170 11:06:06.728483
9171 11:06:06.728566 CH 1, Rank 1
9172 11:06:06.731655 SW Impedance : PASS
9173 11:06:06.731744 DUTY Scan : NO K
9174 11:06:06.734932 ZQ Calibration : PASS
9175 11:06:06.738212 Jitter Meter : NO K
9176 11:06:06.738290 CBT Training : PASS
9177 11:06:06.741603 Write leveling : PASS
9178 11:06:06.745264 RX DQS gating : PASS
9179 11:06:06.745346 RX DQ/DQS(RDDQC) : PASS
9180 11:06:06.748140 TX DQ/DQS : PASS
9181 11:06:06.751642 RX DATLAT : PASS
9182 11:06:06.751769 RX DQ/DQS(Engine): PASS
9183 11:06:06.755102 TX OE : PASS
9184 11:06:06.755212 All Pass.
9185 11:06:06.755310
9186 11:06:06.758331 DramC Write-DBI on
9187 11:06:06.761848 PER_BANK_REFRESH: Hybrid Mode
9188 11:06:06.761953 TX_TRACKING: ON
9189 11:06:06.771493 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9190 11:06:06.778720 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9191 11:06:06.784880 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9192 11:06:06.788562 [FAST_K] Save calibration result to emmc
9193 11:06:06.791633 sync common calibartion params.
9194 11:06:06.794806 sync cbt_mode0:1, 1:1
9195 11:06:06.794936 dram_init: ddr_geometry: 2
9196 11:06:06.798035 dram_init: ddr_geometry: 2
9197 11:06:06.801749 dram_init: ddr_geometry: 2
9198 11:06:06.804995 0:dram_rank_size:100000000
9199 11:06:06.805124 1:dram_rank_size:100000000
9200 11:06:06.811617 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9201 11:06:06.814901 DFS_SHUFFLE_HW_MODE: ON
9202 11:06:06.818414 dramc_set_vcore_voltage set vcore to 725000
9203 11:06:06.821644 Read voltage for 1600, 0
9204 11:06:06.821771 Vio18 = 0
9205 11:06:06.821887 Vcore = 725000
9206 11:06:06.822001 Vdram = 0
9207 11:06:06.825221 Vddq = 0
9208 11:06:06.825345 Vmddr = 0
9209 11:06:06.828739 switch to 3200 Mbps bootup
9210 11:06:06.828863 [DramcRunTimeConfig]
9211 11:06:06.831481 PHYPLL
9212 11:06:06.831602 DPM_CONTROL_AFTERK: ON
9213 11:06:06.834743 PER_BANK_REFRESH: ON
9214 11:06:06.838249 REFRESH_OVERHEAD_REDUCTION: ON
9215 11:06:06.838376 CMD_PICG_NEW_MODE: OFF
9216 11:06:06.841450 XRTWTW_NEW_MODE: ON
9217 11:06:06.841578 XRTRTR_NEW_MODE: ON
9218 11:06:06.845309 TX_TRACKING: ON
9219 11:06:06.845434 RDSEL_TRACKING: OFF
9220 11:06:06.848221 DQS Precalculation for DVFS: ON
9221 11:06:06.851995 RX_TRACKING: OFF
9222 11:06:06.852124 HW_GATING DBG: ON
9223 11:06:06.855264 ZQCS_ENABLE_LP4: ON
9224 11:06:06.855388 RX_PICG_NEW_MODE: ON
9225 11:06:06.858230 TX_PICG_NEW_MODE: ON
9226 11:06:06.858339 ENABLE_RX_DCM_DPHY: ON
9227 11:06:06.862140 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9228 11:06:06.865118 DUMMY_READ_FOR_TRACKING: OFF
9229 11:06:06.869397 !!! SPM_CONTROL_AFTERK: OFF
9230 11:06:06.871655 !!! SPM could not control APHY
9231 11:06:06.871774 IMPEDANCE_TRACKING: ON
9232 11:06:06.875206 TEMP_SENSOR: ON
9233 11:06:06.875338 HW_SAVE_FOR_SR: OFF
9234 11:06:06.878801 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9235 11:06:06.881895 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9236 11:06:06.885188 Read ODT Tracking: ON
9237 11:06:06.885315 Refresh Rate DeBounce: ON
9238 11:06:06.888372 DFS_NO_QUEUE_FLUSH: ON
9239 11:06:06.892167 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9240 11:06:06.895072 ENABLE_DFS_RUNTIME_MRW: OFF
9241 11:06:06.895207 DDR_RESERVE_NEW_MODE: ON
9242 11:06:06.898559 MR_CBT_SWITCH_FREQ: ON
9243 11:06:06.901952 =========================
9244 11:06:06.920199 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9245 11:06:06.923447 dram_init: ddr_geometry: 2
9246 11:06:06.941629 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9247 11:06:06.945200 dram_init: dram init end (result: 0)
9248 11:06:06.951933 DRAM-K: Full calibration passed in 24598 msecs
9249 11:06:06.954472 MRC: failed to locate region type 0.
9250 11:06:06.954583 DRAM rank0 size:0x100000000,
9251 11:06:06.958037 DRAM rank1 size=0x100000000
9252 11:06:06.968496 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9253 11:06:06.974677 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9254 11:06:06.981717 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9255 11:06:06.988757 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9256 11:06:06.991786 DRAM rank0 size:0x100000000,
9257 11:06:06.994730 DRAM rank1 size=0x100000000
9258 11:06:06.994859 CBMEM:
9259 11:06:06.998042 IMD: root @ 0xfffff000 254 entries.
9260 11:06:07.001685 IMD: root @ 0xffffec00 62 entries.
9261 11:06:07.005157 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9262 11:06:07.008271 WARNING: RO_VPD is uninitialized or empty.
9263 11:06:07.014827 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9264 11:06:07.022075 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9265 11:06:07.034302 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9266 11:06:07.046123 BS: romstage times (exec / console): total (unknown) / 24095 ms
9267 11:06:07.046253
9268 11:06:07.046377
9269 11:06:07.055779 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9270 11:06:07.059600 ARM64: Exception handlers installed.
9271 11:06:07.062475 ARM64: Testing exception
9272 11:06:07.065847 ARM64: Done test exception
9273 11:06:07.065971 Enumerating buses...
9274 11:06:07.069411 Show all devs... Before device enumeration.
9275 11:06:07.072645 Root Device: enabled 1
9276 11:06:07.075833 CPU_CLUSTER: 0: enabled 1
9277 11:06:07.075960 CPU: 00: enabled 1
9278 11:06:07.078918 Compare with tree...
9279 11:06:07.079049 Root Device: enabled 1
9280 11:06:07.082544 CPU_CLUSTER: 0: enabled 1
9281 11:06:07.086047 CPU: 00: enabled 1
9282 11:06:07.086169 Root Device scanning...
9283 11:06:07.088855 scan_static_bus for Root Device
9284 11:06:07.092127 CPU_CLUSTER: 0 enabled
9285 11:06:07.095406 scan_static_bus for Root Device done
9286 11:06:07.099000 scan_bus: bus Root Device finished in 8 msecs
9287 11:06:07.099128 done
9288 11:06:07.105569 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9289 11:06:07.109074 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9290 11:06:07.115839 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9291 11:06:07.119034 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9292 11:06:07.122353 Allocating resources...
9293 11:06:07.125508 Reading resources...
9294 11:06:07.128977 Root Device read_resources bus 0 link: 0
9295 11:06:07.129104 DRAM rank0 size:0x100000000,
9296 11:06:07.132524 DRAM rank1 size=0x100000000
9297 11:06:07.135361 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9298 11:06:07.138632 CPU: 00 missing read_resources
9299 11:06:07.141931 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9300 11:06:07.148543 Root Device read_resources bus 0 link: 0 done
9301 11:06:07.148668 Done reading resources.
9302 11:06:07.155082 Show resources in subtree (Root Device)...After reading.
9303 11:06:07.158288 Root Device child on link 0 CPU_CLUSTER: 0
9304 11:06:07.161779 CPU_CLUSTER: 0 child on link 0 CPU: 00
9305 11:06:07.171743 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9306 11:06:07.171863 CPU: 00
9307 11:06:07.175125 Root Device assign_resources, bus 0 link: 0
9308 11:06:07.178318 CPU_CLUSTER: 0 missing set_resources
9309 11:06:07.185101 Root Device assign_resources, bus 0 link: 0 done
9310 11:06:07.185186 Done setting resources.
9311 11:06:07.191780 Show resources in subtree (Root Device)...After assigning values.
9312 11:06:07.195293 Root Device child on link 0 CPU_CLUSTER: 0
9313 11:06:07.198490 CPU_CLUSTER: 0 child on link 0 CPU: 00
9314 11:06:07.208355 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9315 11:06:07.208462 CPU: 00
9316 11:06:07.211705 Done allocating resources.
9317 11:06:07.214974 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9318 11:06:07.218379 Enabling resources...
9319 11:06:07.218489 done.
9320 11:06:07.225396 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9321 11:06:07.225481 Initializing devices...
9322 11:06:07.228860 Root Device init
9323 11:06:07.228978 init hardware done!
9324 11:06:07.231855 0x00000018: ctrlr->caps
9325 11:06:07.235484 52.000 MHz: ctrlr->f_max
9326 11:06:07.235570 0.400 MHz: ctrlr->f_min
9327 11:06:07.238420 0x40ff8080: ctrlr->voltages
9328 11:06:07.238508 sclk: 390625
9329 11:06:07.242135 Bus Width = 1
9330 11:06:07.242220 sclk: 390625
9331 11:06:07.242323 Bus Width = 1
9332 11:06:07.245686 Early init status = 3
9333 11:06:07.252117 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9334 11:06:07.255570 in-header: 03 fc 00 00 01 00 00 00
9335 11:06:07.255654 in-data: 00
9336 11:06:07.261744 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9337 11:06:07.265322 in-header: 03 fd 00 00 00 00 00 00
9338 11:06:07.268444 in-data:
9339 11:06:07.271798 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9340 11:06:07.275845 in-header: 03 fc 00 00 01 00 00 00
9341 11:06:07.278952 in-data: 00
9342 11:06:07.282408 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9343 11:06:07.288415 in-header: 03 fd 00 00 00 00 00 00
9344 11:06:07.291671 in-data:
9345 11:06:07.294748 [SSUSB] Setting up USB HOST controller...
9346 11:06:07.298320 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9347 11:06:07.301428 [SSUSB] phy power-on done.
9348 11:06:07.304828 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9349 11:06:07.311320 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9350 11:06:07.314608 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9351 11:06:07.321575 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9352 11:06:07.328206 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9353 11:06:07.334686 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9354 11:06:07.341332 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9355 11:06:07.348197 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9356 11:06:07.348311 SPM: binary array size = 0x9dc
9357 11:06:07.355289 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9358 11:06:07.362119 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9359 11:06:07.368332 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9360 11:06:07.371263 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9361 11:06:07.374762 configure_display: Starting display init
9362 11:06:07.411548 anx7625_power_on_init: Init interface.
9363 11:06:07.414755 anx7625_disable_pd_protocol: Disabled PD feature.
9364 11:06:07.417868 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9365 11:06:07.445951 anx7625_start_dp_work: Secure OCM version=00
9366 11:06:07.449257 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9367 11:06:07.464168 sp_tx_get_edid_block: EDID Block = 1
9368 11:06:07.566531 Extracted contents:
9369 11:06:07.569809 header: 00 ff ff ff ff ff ff 00
9370 11:06:07.573076 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9371 11:06:07.576430 version: 01 04
9372 11:06:07.579840 basic params: 95 1f 11 78 0a
9373 11:06:07.583090 chroma info: 76 90 94 55 54 90 27 21 50 54
9374 11:06:07.586523 established: 00 00 00
9375 11:06:07.589904 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9376 11:06:07.596649 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9377 11:06:07.603501 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9378 11:06:07.610162 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9379 11:06:07.616647 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9380 11:06:07.616731 extensions: 00
9381 11:06:07.619975 checksum: fb
9382 11:06:07.620057
9383 11:06:07.623314 Manufacturer: IVO Model 57d Serial Number 0
9384 11:06:07.626867 Made week 0 of 2020
9385 11:06:07.626949 EDID version: 1.4
9386 11:06:07.629855 Digital display
9387 11:06:07.633603 6 bits per primary color channel
9388 11:06:07.633687 DisplayPort interface
9389 11:06:07.637050 Maximum image size: 31 cm x 17 cm
9390 11:06:07.637179 Gamma: 220%
9391 11:06:07.640193 Check DPMS levels
9392 11:06:07.643529 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9393 11:06:07.646852 First detailed timing is preferred timing
9394 11:06:07.649879 Established timings supported:
9395 11:06:07.653221 Standard timings supported:
9396 11:06:07.653307 Detailed timings
9397 11:06:07.659807 Hex of detail: 383680a07038204018303c0035ae10000019
9398 11:06:07.662901 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9399 11:06:07.666261 0780 0798 07c8 0820 hborder 0
9400 11:06:07.673331 0438 043b 0447 0458 vborder 0
9401 11:06:07.673417 -hsync -vsync
9402 11:06:07.676361 Did detailed timing
9403 11:06:07.679956 Hex of detail: 000000000000000000000000000000000000
9404 11:06:07.683262 Manufacturer-specified data, tag 0
9405 11:06:07.689827 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9406 11:06:07.689913 ASCII string: InfoVision
9407 11:06:07.696606 Hex of detail: 000000fe00523134304e574635205248200a
9408 11:06:07.696696 ASCII string: R140NWF5 RH
9409 11:06:07.699973 Checksum
9410 11:06:07.700059 Checksum: 0xfb (valid)
9411 11:06:07.706208 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9412 11:06:07.706333 DSI data_rate: 832800000 bps
9413 11:06:07.713959 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9414 11:06:07.717761 anx7625_parse_edid: pixelclock(138800).
9415 11:06:07.720876 hactive(1920), hsync(48), hfp(24), hbp(88)
9416 11:06:07.723850 vactive(1080), vsync(12), vfp(3), vbp(17)
9417 11:06:07.727076 anx7625_dsi_config: config dsi.
9418 11:06:07.734140 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9419 11:06:07.748329 anx7625_dsi_config: success to config DSI
9420 11:06:07.751575 anx7625_dp_start: MIPI phy setup OK.
9421 11:06:07.755372 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9422 11:06:07.758957 mtk_ddp_mode_set invalid vrefresh 60
9423 11:06:07.762130 main_disp_path_setup
9424 11:06:07.762208 ovl_layer_smi_id_en
9425 11:06:07.765534 ovl_layer_smi_id_en
9426 11:06:07.765635 ccorr_config
9427 11:06:07.765735 aal_config
9428 11:06:07.768369 gamma_config
9429 11:06:07.768454 postmask_config
9430 11:06:07.772039 dither_config
9431 11:06:07.775355 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9432 11:06:07.782016 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9433 11:06:07.785006 Root Device init finished in 553 msecs
9434 11:06:07.785095 CPU_CLUSTER: 0 init
9435 11:06:07.795110 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9436 11:06:07.798304 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9437 11:06:07.802498 APU_MBOX 0x190000b0 = 0x10001
9438 11:06:07.805423 APU_MBOX 0x190001b0 = 0x10001
9439 11:06:07.808514 APU_MBOX 0x190005b0 = 0x10001
9440 11:06:07.811826 APU_MBOX 0x190006b0 = 0x10001
9441 11:06:07.815378 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9442 11:06:07.827369 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9443 11:06:07.840237 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9444 11:06:07.846642 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9445 11:06:07.858064 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9446 11:06:07.866984 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9447 11:06:07.870538 CPU_CLUSTER: 0 init finished in 81 msecs
9448 11:06:07.873929 Devices initialized
9449 11:06:07.877283 Show all devs... After init.
9450 11:06:07.877367 Root Device: enabled 1
9451 11:06:07.880923 CPU_CLUSTER: 0: enabled 1
9452 11:06:07.884690 CPU: 00: enabled 1
9453 11:06:07.887380 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9454 11:06:07.890727 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9455 11:06:07.893743 ELOG: NV offset 0x57f000 size 0x1000
9456 11:06:07.900744 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9457 11:06:07.906833 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9458 11:06:07.910580 ELOG: Event(17) added with size 13 at 2024-03-03 11:06:09 UTC
9459 11:06:07.914022 out: cmd=0x121: 03 db 21 01 00 00 00 00
9460 11:06:07.917790 in-header: 03 bf 00 00 2c 00 00 00
9461 11:06:07.931469 in-data: a0 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9462 11:06:07.937799 ELOG: Event(A1) added with size 10 at 2024-03-03 11:06:09 UTC
9463 11:06:07.944502 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9464 11:06:07.951133 ELOG: Event(A0) added with size 9 at 2024-03-03 11:06:09 UTC
9465 11:06:07.954243 elog_add_boot_reason: Logged dev mode boot
9466 11:06:07.958064 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9467 11:06:07.961648 Finalize devices...
9468 11:06:07.961764 Devices finalized
9469 11:06:07.968119 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9470 11:06:07.970966 Writing coreboot table at 0xffe64000
9471 11:06:07.974691 0. 000000000010a000-0000000000113fff: RAMSTAGE
9472 11:06:07.978137 1. 0000000040000000-00000000400fffff: RAM
9473 11:06:07.981424 2. 0000000040100000-000000004032afff: RAMSTAGE
9474 11:06:07.988300 3. 000000004032b000-00000000545fffff: RAM
9475 11:06:07.991208 4. 0000000054600000-000000005465ffff: BL31
9476 11:06:07.994845 5. 0000000054660000-00000000ffe63fff: RAM
9477 11:06:07.997723 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9478 11:06:08.004845 7. 0000000100000000-000000023fffffff: RAM
9479 11:06:08.004924 Passing 5 GPIOs to payload:
9480 11:06:08.011103 NAME | PORT | POLARITY | VALUE
9481 11:06:08.014525 EC in RW | 0x000000aa | low | undefined
9482 11:06:08.021000 EC interrupt | 0x00000005 | low | undefined
9483 11:06:08.024831 TPM interrupt | 0x000000ab | high | undefined
9484 11:06:08.028026 SD card detect | 0x00000011 | high | undefined
9485 11:06:08.034790 speaker enable | 0x00000093 | high | undefined
9486 11:06:08.037842 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9487 11:06:08.041200 in-header: 03 f9 00 00 02 00 00 00
9488 11:06:08.041318 in-data: 02 00
9489 11:06:08.044187 ADC[4]: Raw value=900590 ID=7
9490 11:06:08.047645 ADC[3]: Raw value=213336 ID=1
9491 11:06:08.047768 RAM Code: 0x71
9492 11:06:08.051224 ADC[6]: Raw value=74557 ID=0
9493 11:06:08.054284 ADC[5]: Raw value=211860 ID=1
9494 11:06:08.054366 SKU Code: 0x1
9495 11:06:08.061022 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum db2f
9496 11:06:08.064563 coreboot table: 964 bytes.
9497 11:06:08.067757 IMD ROOT 0. 0xfffff000 0x00001000
9498 11:06:08.070885 IMD SMALL 1. 0xffffe000 0x00001000
9499 11:06:08.074406 RO MCACHE 2. 0xffffc000 0x00001104
9500 11:06:08.077986 CONSOLE 3. 0xfff7c000 0x00080000
9501 11:06:08.081770 FMAP 4. 0xfff7b000 0x00000452
9502 11:06:08.084565 TIME STAMP 5. 0xfff7a000 0x00000910
9503 11:06:08.087615 VBOOT WORK 6. 0xfff66000 0x00014000
9504 11:06:08.090920 RAMOOPS 7. 0xffe66000 0x00100000
9505 11:06:08.094528 COREBOOT 8. 0xffe64000 0x00002000
9506 11:06:08.094610 IMD small region:
9507 11:06:08.097672 IMD ROOT 0. 0xffffec00 0x00000400
9508 11:06:08.101356 VPD 1. 0xffffeb80 0x0000006c
9509 11:06:08.104928 MMC STATUS 2. 0xffffeb60 0x00000004
9510 11:06:08.111113 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9511 11:06:08.111196 Probing TPM: done!
9512 11:06:08.117651 Connected to device vid:did:rid of 1ae0:0028:00
9513 11:06:08.124397 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9514 11:06:08.127869 Initialized TPM device CR50 revision 0
9515 11:06:08.131386 Checking cr50 for pending updates
9516 11:06:08.137601 Reading cr50 TPM mode
9517 11:06:08.146069 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9518 11:06:08.152603 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9519 11:06:08.193108 read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps
9520 11:06:08.196338 Checking segment from ROM address 0x40100000
9521 11:06:08.199581 Checking segment from ROM address 0x4010001c
9522 11:06:08.206921 Loading segment from ROM address 0x40100000
9523 11:06:08.207006 code (compression=0)
9524 11:06:08.213612 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9525 11:06:08.223542 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9526 11:06:08.223655 it's not compressed!
9527 11:06:08.229733 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9528 11:06:08.233192 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9529 11:06:08.253239 Loading segment from ROM address 0x4010001c
9530 11:06:08.253345 Entry Point 0x80000000
9531 11:06:08.256701 Loaded segments
9532 11:06:08.260119 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9533 11:06:08.266935 Jumping to boot code at 0x80000000(0xffe64000)
9534 11:06:08.273665 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9535 11:06:08.280279 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9536 11:06:08.287546 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9537 11:06:08.290828 Checking segment from ROM address 0x40100000
9538 11:06:08.294037 Checking segment from ROM address 0x4010001c
9539 11:06:08.301397 Loading segment from ROM address 0x40100000
9540 11:06:08.301479 code (compression=1)
9541 11:06:08.307926 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9542 11:06:08.317786 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9543 11:06:08.317880 using LZMA
9544 11:06:08.326176 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9545 11:06:08.333286 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9546 11:06:08.336391 Loading segment from ROM address 0x4010001c
9547 11:06:08.336483 Entry Point 0x54601000
9548 11:06:08.339753 Loaded segments
9549 11:06:08.343198 NOTICE: MT8192 bl31_setup
9550 11:06:08.349436 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9551 11:06:08.353228 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9552 11:06:08.356663 WARNING: region 0:
9553 11:06:08.359305 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9554 11:06:08.359386 WARNING: region 1:
9555 11:06:08.365989 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9556 11:06:08.369372 WARNING: region 2:
9557 11:06:08.372821 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9558 11:06:08.376240 WARNING: region 3:
9559 11:06:08.379407 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9560 11:06:08.382655 WARNING: region 4:
9561 11:06:08.389750 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9562 11:06:08.389848 WARNING: region 5:
9563 11:06:08.392685 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9564 11:06:08.395964 WARNING: region 6:
9565 11:06:08.399334 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9566 11:06:08.402564 WARNING: region 7:
9567 11:06:08.405914 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9568 11:06:08.412873 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9569 11:06:08.416135 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9570 11:06:08.419264 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9571 11:06:08.426253 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9572 11:06:08.429606 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9573 11:06:08.432703 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9574 11:06:08.439775 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9575 11:06:08.443355 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9576 11:06:08.449666 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9577 11:06:08.452808 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9578 11:06:08.456303 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9579 11:06:08.463164 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9580 11:06:08.466327 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9581 11:06:08.469685 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9582 11:06:08.476260 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9583 11:06:08.479431 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9584 11:06:08.482990 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9585 11:06:08.490116 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9586 11:06:08.493076 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9587 11:06:08.496513 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9588 11:06:08.503297 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9589 11:06:08.506930 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9590 11:06:08.513151 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9591 11:06:08.516654 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9592 11:06:08.519923 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9593 11:06:08.526544 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9594 11:06:08.530016 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9595 11:06:08.537042 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9596 11:06:08.540233 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9597 11:06:08.543993 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9598 11:06:08.550156 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9599 11:06:08.553469 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9600 11:06:08.557210 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9601 11:06:08.563757 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9602 11:06:08.567158 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9603 11:06:08.570665 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9604 11:06:08.573821 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9605 11:06:08.580344 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9606 11:06:08.583592 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9607 11:06:08.587185 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9608 11:06:08.590166 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9609 11:06:08.593406 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9610 11:06:08.600548 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9611 11:06:08.603769 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9612 11:06:08.607269 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9613 11:06:08.613630 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9614 11:06:08.617146 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9615 11:06:08.620705 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9616 11:06:08.624007 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9617 11:06:08.630863 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9618 11:06:08.633893 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9619 11:06:08.640411 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9620 11:06:08.643865 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9621 11:06:08.647870 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9622 11:06:08.654448 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9623 11:06:08.657321 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9624 11:06:08.664068 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9625 11:06:08.668414 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9626 11:06:08.674144 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9627 11:06:08.677538 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9628 11:06:08.681224 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9629 11:06:08.687650 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9630 11:06:08.691058 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9631 11:06:08.697616 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9632 11:06:08.701041 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9633 11:06:08.708274 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9634 11:06:08.711345 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9635 11:06:08.714724 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9636 11:06:08.721223 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9637 11:06:08.724849 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9638 11:06:08.731298 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9639 11:06:08.734559 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9640 11:06:08.738161 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9641 11:06:08.744712 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9642 11:06:08.748253 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9643 11:06:08.754651 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9644 11:06:08.758689 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9645 11:06:08.764549 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9646 11:06:08.768319 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9647 11:06:08.774821 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9648 11:06:08.778104 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9649 11:06:08.781644 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9650 11:06:08.788085 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9651 11:06:08.791744 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9652 11:06:08.798225 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9653 11:06:08.801362 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9654 11:06:08.804882 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9655 11:06:08.811849 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9656 11:06:08.815266 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9657 11:06:08.821550 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9658 11:06:08.825247 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9659 11:06:08.831940 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9660 11:06:08.834880 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9661 11:06:08.838242 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9662 11:06:08.845021 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9663 11:06:08.848356 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9664 11:06:08.855247 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9665 11:06:08.858416 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9666 11:06:08.861796 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9667 11:06:08.865474 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9668 11:06:08.871947 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9669 11:06:08.875538 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9670 11:06:08.879010 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9671 11:06:08.885200 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9672 11:06:08.888901 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9673 11:06:08.892074 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9674 11:06:08.898940 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9675 11:06:08.902008 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9676 11:06:08.908859 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9677 11:06:08.912028 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9678 11:06:08.915554 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9679 11:06:08.922300 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9680 11:06:08.926071 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9681 11:06:08.932398 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9682 11:06:08.935783 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9683 11:06:08.938791 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9684 11:06:08.942318 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9685 11:06:08.949176 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9686 11:06:08.952518 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9687 11:06:08.955759 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9688 11:06:08.962824 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9689 11:06:08.965896 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9690 11:06:08.968982 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9691 11:06:08.972634 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9692 11:06:08.979808 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9693 11:06:08.983417 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9694 11:06:08.989499 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9695 11:06:08.992571 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9696 11:06:08.995947 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9697 11:06:09.002929 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9698 11:06:09.006218 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9699 11:06:09.009695 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9700 11:06:09.016166 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9701 11:06:09.019716 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9702 11:06:09.026642 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9703 11:06:09.029636 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9704 11:06:09.032869 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9705 11:06:09.039859 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9706 11:06:09.043232 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9707 11:06:09.046362 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9708 11:06:09.053041 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9709 11:06:09.056622 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9710 11:06:09.062899 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9711 11:06:09.066710 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9712 11:06:09.070111 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9713 11:06:09.076654 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9714 11:06:09.079891 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9715 11:06:09.082992 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9716 11:06:09.090101 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9717 11:06:09.093179 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9718 11:06:09.100638 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9719 11:06:09.103402 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9720 11:06:09.106741 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9721 11:06:09.113544 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9722 11:06:09.116579 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9723 11:06:09.120355 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9724 11:06:09.126797 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9725 11:06:09.130436 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9726 11:06:09.136597 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9727 11:06:09.140201 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9728 11:06:09.143512 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9729 11:06:09.150319 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9730 11:06:09.153611 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9731 11:06:09.160053 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9732 11:06:09.163759 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9733 11:06:09.167074 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9734 11:06:09.173532 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9735 11:06:09.176836 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9736 11:06:09.180178 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9737 11:06:09.186785 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9738 11:06:09.190383 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9739 11:06:09.196807 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9740 11:06:09.200464 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9741 11:06:09.204440 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9742 11:06:09.210372 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9743 11:06:09.213778 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9744 11:06:09.220484 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9745 11:06:09.224011 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9746 11:06:09.226651 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9747 11:06:09.233927 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9748 11:06:09.236843 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9749 11:06:09.240374 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9750 11:06:09.246916 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9751 11:06:09.249980 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9752 11:06:09.256650 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9753 11:06:09.260348 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9754 11:06:09.263703 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9755 11:06:09.270350 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9756 11:06:09.273271 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9757 11:06:09.280716 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9758 11:06:09.283617 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9759 11:06:09.287006 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9760 11:06:09.293649 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9761 11:06:09.297081 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9762 11:06:09.303986 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9763 11:06:09.306799 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9764 11:06:09.310317 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9765 11:06:09.316828 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9766 11:06:09.320498 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9767 11:06:09.326732 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9768 11:06:09.330269 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9769 11:06:09.333739 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9770 11:06:09.340408 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9771 11:06:09.343853 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9772 11:06:09.350401 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9773 11:06:09.353407 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9774 11:06:09.360430 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9775 11:06:09.363629 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9776 11:06:09.366642 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9777 11:06:09.373454 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9778 11:06:09.376858 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9779 11:06:09.383921 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9780 11:06:09.386852 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9781 11:06:09.393723 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9782 11:06:09.396996 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9783 11:06:09.399882 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9784 11:06:09.406936 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9785 11:06:09.410131 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9786 11:06:09.416713 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9787 11:06:09.420501 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9788 11:06:09.423463 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9789 11:06:09.430113 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9790 11:06:09.433549 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9791 11:06:09.440261 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9792 11:06:09.443685 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9793 11:06:09.447035 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9794 11:06:09.453838 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9795 11:06:09.456938 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9796 11:06:09.463543 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9797 11:06:09.466909 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9798 11:06:09.469938 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9799 11:06:09.473797 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9800 11:06:09.476955 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9801 11:06:09.483820 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9802 11:06:09.487022 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9803 11:06:09.490302 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9804 11:06:09.496875 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9805 11:06:09.501034 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9806 11:06:09.503687 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9807 11:06:09.510117 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9808 11:06:09.514077 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9809 11:06:09.520563 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9810 11:06:09.523469 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9811 11:06:09.527125 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9812 11:06:09.533701 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9813 11:06:09.536581 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9814 11:06:09.540115 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9815 11:06:09.546796 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9816 11:06:09.550300 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9817 11:06:09.553398 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9818 11:06:09.560021 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9819 11:06:09.563675 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9820 11:06:09.570271 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9821 11:06:09.573745 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9822 11:06:09.577371 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9823 11:06:09.583448 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9824 11:06:09.587002 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9825 11:06:09.590311 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9826 11:06:09.597396 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9827 11:06:09.600340 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9828 11:06:09.603932 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9829 11:06:09.610111 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9830 11:06:09.613420 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9831 11:06:09.616886 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9832 11:06:09.623589 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9833 11:06:09.626699 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9834 11:06:09.633543 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9835 11:06:09.637407 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9836 11:06:09.639991 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9837 11:06:09.643813 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9838 11:06:09.650299 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9839 11:06:09.654089 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9840 11:06:09.656750 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9841 11:06:09.660560 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9842 11:06:09.666637 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9843 11:06:09.670316 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9844 11:06:09.673488 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9845 11:06:09.676511 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9846 11:06:09.683337 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9847 11:06:09.686832 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9848 11:06:09.689761 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9849 11:06:09.693432 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9850 11:06:09.699957 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9851 11:06:09.702910 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9852 11:06:09.709994 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9853 11:06:09.713276 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9854 11:06:09.719860 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9855 11:06:09.723186 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9856 11:06:09.726729 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9857 11:06:09.733406 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9858 11:06:09.736645 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9859 11:06:09.739760 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9860 11:06:09.746971 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9861 11:06:09.749921 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9862 11:06:09.756951 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9863 11:06:09.760224 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9864 11:06:09.767138 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9865 11:06:09.770045 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9866 11:06:09.773128 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9867 11:06:09.780037 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9868 11:06:09.783342 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9869 11:06:09.790363 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9870 11:06:09.793521 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9871 11:06:09.796564 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9872 11:06:09.803334 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9873 11:06:09.806801 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9874 11:06:09.813270 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9875 11:06:09.816961 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9876 11:06:09.821171 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9877 11:06:09.826976 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9878 11:06:09.830382 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9879 11:06:09.836858 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9880 11:06:09.840584 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9881 11:06:09.843617 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9882 11:06:09.849932 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9883 11:06:09.853394 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9884 11:06:09.859851 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9885 11:06:09.863495 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9886 11:06:09.866905 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9887 11:06:09.873533 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9888 11:06:09.877088 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9889 11:06:09.880348 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9890 11:06:09.887228 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9891 11:06:09.890556 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9892 11:06:09.896863 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9893 11:06:09.900736 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9894 11:06:09.907053 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9895 11:06:09.910179 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9896 11:06:09.913973 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9897 11:06:09.920576 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9898 11:06:09.923737 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9899 11:06:09.930321 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9900 11:06:09.933980 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9901 11:06:09.936681 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9902 11:06:09.943480 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9903 11:06:09.946877 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9904 11:06:09.953745 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9905 11:06:09.957327 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9906 11:06:09.960310 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9907 11:06:09.966836 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9908 11:06:09.970122 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9909 11:06:09.977051 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9910 11:06:09.980120 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9911 11:06:09.983857 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9912 11:06:09.990290 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9913 11:06:09.993784 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9914 11:06:09.996992 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9915 11:06:10.003658 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9916 11:06:10.007366 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9917 11:06:10.013980 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9918 11:06:10.017205 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9919 11:06:10.023671 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9920 11:06:10.027337 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9921 11:06:10.030751 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9922 11:06:10.037308 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9923 11:06:10.040571 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9924 11:06:10.047048 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9925 11:06:10.050582 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9926 11:06:10.057324 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9927 11:06:10.060612 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9928 11:06:10.063865 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9929 11:06:10.070693 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9930 11:06:10.074129 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9931 11:06:10.080859 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9932 11:06:10.083857 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9933 11:06:10.087464 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9934 11:06:10.093667 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9935 11:06:10.097003 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9936 11:06:10.103846 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9937 11:06:10.107412 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9938 11:06:10.113723 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9939 11:06:10.117145 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9940 11:06:10.121224 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9941 11:06:10.127587 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9942 11:06:10.131222 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9943 11:06:10.137315 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9944 11:06:10.140533 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9945 11:06:10.144230 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9946 11:06:10.151345 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9947 11:06:10.153939 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9948 11:06:10.161111 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9949 11:06:10.164456 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9950 11:06:10.170755 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9951 11:06:10.174068 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9952 11:06:10.181063 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9953 11:06:10.184361 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9954 11:06:10.187700 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9955 11:06:10.193855 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9956 11:06:10.197315 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9957 11:06:10.203897 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9958 11:06:10.207774 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9959 11:06:10.214234 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9960 11:06:10.217241 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9961 11:06:10.221082 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9962 11:06:10.227295 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9963 11:06:10.230676 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9964 11:06:10.237403 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9965 11:06:10.240722 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9966 11:06:10.247251 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9967 11:06:10.250793 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9968 11:06:10.253761 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9969 11:06:10.260648 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9970 11:06:10.264434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9971 11:06:10.271147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9972 11:06:10.273914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9973 11:06:10.277285 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9974 11:06:10.283904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9975 11:06:10.287725 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9976 11:06:10.293875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9977 11:06:10.297280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9978 11:06:10.303962 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9979 11:06:10.307162 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9980 11:06:10.313872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9981 11:06:10.317204 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9982 11:06:10.324273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9983 11:06:10.327114 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9984 11:06:10.334204 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9985 11:06:10.337323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9986 11:06:10.343998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9987 11:06:10.347332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9988 11:06:10.354085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9989 11:06:10.357338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9990 11:06:10.363794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9991 11:06:10.367797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9992 11:06:10.373784 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9993 11:06:10.377442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9994 11:06:10.383951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9995 11:06:10.387054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9996 11:06:10.393816 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9997 11:06:10.397469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9998 11:06:10.403807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9999 11:06:10.407174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10000 11:06:10.414103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10001 11:06:10.417458 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10002 11:06:10.420622 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10003 11:06:10.424234 INFO: [APUAPC] vio 0
10004 11:06:10.427030 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10005 11:06:10.433777 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10006 11:06:10.437318 INFO: [APUAPC] D0_APC_0: 0x400510
10007 11:06:10.440615 INFO: [APUAPC] D0_APC_1: 0x0
10008 11:06:10.443978 INFO: [APUAPC] D0_APC_2: 0x1540
10009 11:06:10.444102 INFO: [APUAPC] D0_APC_3: 0x0
10010 11:06:10.447256 INFO: [APUAPC] D1_APC_0: 0xffffffff
10011 11:06:10.451074 INFO: [APUAPC] D1_APC_1: 0xffffffff
10012 11:06:10.453992 INFO: [APUAPC] D1_APC_2: 0x3fffff
10013 11:06:10.457480 INFO: [APUAPC] D1_APC_3: 0x0
10014 11:06:10.461136 INFO: [APUAPC] D2_APC_0: 0xffffffff
10015 11:06:10.464097 INFO: [APUAPC] D2_APC_1: 0xffffffff
10016 11:06:10.467590 INFO: [APUAPC] D2_APC_2: 0x3fffff
10017 11:06:10.470803 INFO: [APUAPC] D2_APC_3: 0x0
10018 11:06:10.474214 INFO: [APUAPC] D3_APC_0: 0xffffffff
10019 11:06:10.477283 INFO: [APUAPC] D3_APC_1: 0xffffffff
10020 11:06:10.480449 INFO: [APUAPC] D3_APC_2: 0x3fffff
10021 11:06:10.483887 INFO: [APUAPC] D3_APC_3: 0x0
10022 11:06:10.487205 INFO: [APUAPC] D4_APC_0: 0xffffffff
10023 11:06:10.491068 INFO: [APUAPC] D4_APC_1: 0xffffffff
10024 11:06:10.494142 INFO: [APUAPC] D4_APC_2: 0x3fffff
10025 11:06:10.498000 INFO: [APUAPC] D4_APC_3: 0x0
10026 11:06:10.501108 INFO: [APUAPC] D5_APC_0: 0xffffffff
10027 11:06:10.504296 INFO: [APUAPC] D5_APC_1: 0xffffffff
10028 11:06:10.507174 INFO: [APUAPC] D5_APC_2: 0x3fffff
10029 11:06:10.510859 INFO: [APUAPC] D5_APC_3: 0x0
10030 11:06:10.514198 INFO: [APUAPC] D6_APC_0: 0xffffffff
10031 11:06:10.517279 INFO: [APUAPC] D6_APC_1: 0xffffffff
10032 11:06:10.520981 INFO: [APUAPC] D6_APC_2: 0x3fffff
10033 11:06:10.524023 INFO: [APUAPC] D6_APC_3: 0x0
10034 11:06:10.527589 INFO: [APUAPC] D7_APC_0: 0xffffffff
10035 11:06:10.530861 INFO: [APUAPC] D7_APC_1: 0xffffffff
10036 11:06:10.533908 INFO: [APUAPC] D7_APC_2: 0x3fffff
10037 11:06:10.537391 INFO: [APUAPC] D7_APC_3: 0x0
10038 11:06:10.540740 INFO: [APUAPC] D8_APC_0: 0xffffffff
10039 11:06:10.544263 INFO: [APUAPC] D8_APC_1: 0xffffffff
10040 11:06:10.547147 INFO: [APUAPC] D8_APC_2: 0x3fffff
10041 11:06:10.550622 INFO: [APUAPC] D8_APC_3: 0x0
10042 11:06:10.554371 INFO: [APUAPC] D9_APC_0: 0xffffffff
10043 11:06:10.557771 INFO: [APUAPC] D9_APC_1: 0xffffffff
10044 11:06:10.560643 INFO: [APUAPC] D9_APC_2: 0x3fffff
10045 11:06:10.560765 INFO: [APUAPC] D9_APC_3: 0x0
10046 11:06:10.567582 INFO: [APUAPC] D10_APC_0: 0xffffffff
10047 11:06:10.570633 INFO: [APUAPC] D10_APC_1: 0xffffffff
10048 11:06:10.574015 INFO: [APUAPC] D10_APC_2: 0x3fffff
10049 11:06:10.574161 INFO: [APUAPC] D10_APC_3: 0x0
10050 11:06:10.580963 INFO: [APUAPC] D11_APC_0: 0xffffffff
10051 11:06:10.583959 INFO: [APUAPC] D11_APC_1: 0xffffffff
10052 11:06:10.587207 INFO: [APUAPC] D11_APC_2: 0x3fffff
10053 11:06:10.591015 INFO: [APUAPC] D11_APC_3: 0x0
10054 11:06:10.594235 INFO: [APUAPC] D12_APC_0: 0xffffffff
10055 11:06:10.597829 INFO: [APUAPC] D12_APC_1: 0xffffffff
10056 11:06:10.600773 INFO: [APUAPC] D12_APC_2: 0x3fffff
10057 11:06:10.604128 INFO: [APUAPC] D12_APC_3: 0x0
10058 11:06:10.607576 INFO: [APUAPC] D13_APC_0: 0xffffffff
10059 11:06:10.610825 INFO: [APUAPC] D13_APC_1: 0xffffffff
10060 11:06:10.614159 INFO: [APUAPC] D13_APC_2: 0x3fffff
10061 11:06:10.617214 INFO: [APUAPC] D13_APC_3: 0x0
10062 11:06:10.620566 INFO: [APUAPC] D14_APC_0: 0xffffffff
10063 11:06:10.624296 INFO: [APUAPC] D14_APC_1: 0xffffffff
10064 11:06:10.627514 INFO: [APUAPC] D14_APC_2: 0x3fffff
10065 11:06:10.630623 INFO: [APUAPC] D14_APC_3: 0x0
10066 11:06:10.633911 INFO: [APUAPC] D15_APC_0: 0xffffffff
10067 11:06:10.637217 INFO: [APUAPC] D15_APC_1: 0xffffffff
10068 11:06:10.640517 INFO: [APUAPC] D15_APC_2: 0x3fffff
10069 11:06:10.644100 INFO: [APUAPC] D15_APC_3: 0x0
10070 11:06:10.644183 INFO: [APUAPC] APC_CON: 0x4
10071 11:06:10.647783 INFO: [NOCDAPC] D0_APC_0: 0x0
10072 11:06:10.650971 INFO: [NOCDAPC] D0_APC_1: 0x0
10073 11:06:10.654274 INFO: [NOCDAPC] D1_APC_0: 0x0
10074 11:06:10.657254 INFO: [NOCDAPC] D1_APC_1: 0xfff
10075 11:06:10.660790 INFO: [NOCDAPC] D2_APC_0: 0x0
10076 11:06:10.664244 INFO: [NOCDAPC] D2_APC_1: 0xfff
10077 11:06:10.667530 INFO: [NOCDAPC] D3_APC_0: 0x0
10078 11:06:10.670824 INFO: [NOCDAPC] D3_APC_1: 0xfff
10079 11:06:10.670907 INFO: [NOCDAPC] D4_APC_0: 0x0
10080 11:06:10.674050 INFO: [NOCDAPC] D4_APC_1: 0xfff
10081 11:06:10.677418 INFO: [NOCDAPC] D5_APC_0: 0x0
10082 11:06:10.680814 INFO: [NOCDAPC] D5_APC_1: 0xfff
10083 11:06:10.684751 INFO: [NOCDAPC] D6_APC_0: 0x0
10084 11:06:10.687353 INFO: [NOCDAPC] D6_APC_1: 0xfff
10085 11:06:10.690645 INFO: [NOCDAPC] D7_APC_0: 0x0
10086 11:06:10.694330 INFO: [NOCDAPC] D7_APC_1: 0xfff
10087 11:06:10.697703 INFO: [NOCDAPC] D8_APC_0: 0x0
10088 11:06:10.700884 INFO: [NOCDAPC] D8_APC_1: 0xfff
10089 11:06:10.700967 INFO: [NOCDAPC] D9_APC_0: 0x0
10090 11:06:10.704019 INFO: [NOCDAPC] D9_APC_1: 0xfff
10091 11:06:10.707206 INFO: [NOCDAPC] D10_APC_0: 0x0
10092 11:06:10.710798 INFO: [NOCDAPC] D10_APC_1: 0xfff
10093 11:06:10.714182 INFO: [NOCDAPC] D11_APC_0: 0x0
10094 11:06:10.717503 INFO: [NOCDAPC] D11_APC_1: 0xfff
10095 11:06:10.720822 INFO: [NOCDAPC] D12_APC_0: 0x0
10096 11:06:10.724416 INFO: [NOCDAPC] D12_APC_1: 0xfff
10097 11:06:10.727351 INFO: [NOCDAPC] D13_APC_0: 0x0
10098 11:06:10.731047 INFO: [NOCDAPC] D13_APC_1: 0xfff
10099 11:06:10.734266 INFO: [NOCDAPC] D14_APC_0: 0x0
10100 11:06:10.737543 INFO: [NOCDAPC] D14_APC_1: 0xfff
10101 11:06:10.740778 INFO: [NOCDAPC] D15_APC_0: 0x0
10102 11:06:10.744555 INFO: [NOCDAPC] D15_APC_1: 0xfff
10103 11:06:10.744668 INFO: [NOCDAPC] APC_CON: 0x4
10104 11:06:10.747958 INFO: [APUAPC] set_apusys_apc done
10105 11:06:10.750897 INFO: [DEVAPC] devapc_init done
10106 11:06:10.757534 INFO: GICv3 without legacy support detected.
10107 11:06:10.760450 INFO: ARM GICv3 driver initialized in EL3
10108 11:06:10.764156 INFO: Maximum SPI INTID supported: 639
10109 11:06:10.767281 INFO: BL31: Initializing runtime services
10110 11:06:10.773896 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10111 11:06:10.777517 INFO: SPM: enable CPC mode
10112 11:06:10.780898 INFO: mcdi ready for mcusys-off-idle and system suspend
10113 11:06:10.787319 INFO: BL31: Preparing for EL3 exit to normal world
10114 11:06:10.790728 INFO: Entry point address = 0x80000000
10115 11:06:10.790838 INFO: SPSR = 0x8
10116 11:06:10.797395
10117 11:06:10.797508
10118 11:06:10.797572
10119 11:06:10.801389 Starting depthcharge on Spherion...
10120 11:06:10.801470
10121 11:06:10.801570 Wipe memory regions:
10122 11:06:10.801663
10123 11:06:10.802331 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10124 11:06:10.802490 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10125 11:06:10.802574 Setting prompt string to ['asurada:']
10126 11:06:10.802659 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10127 11:06:10.804164 [0x00000040000000, 0x00000054600000)
10128 11:06:10.926737
10129 11:06:10.926865 [0x00000054660000, 0x00000080000000)
10130 11:06:11.187275
10131 11:06:11.187432 [0x000000821a7280, 0x000000ffe64000)
10132 11:06:11.931909
10133 11:06:11.932051 [0x00000100000000, 0x00000240000000)
10134 11:06:13.821471
10135 11:06:13.824736 Initializing XHCI USB controller at 0x11200000.
10136 11:06:14.862597
10137 11:06:14.865819 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10138 11:06:14.865951
10139 11:06:14.866063
10140 11:06:14.866175
10141 11:06:14.866498 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10143 11:06:14.966914 asurada: tftpboot 192.168.201.1 12925640/tftp-deploy-4frbx01r/kernel/image.itb 12925640/tftp-deploy-4frbx01r/kernel/cmdline
10144 11:06:14.967107 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10145 11:06:14.967242 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10146 11:06:14.971582 tftpboot 192.168.201.1 12925640/tftp-deploy-4frbx01r/kernel/image.ittp-deploy-4frbx01r/kernel/cmdline
10147 11:06:14.971708
10148 11:06:14.971822 Waiting for link
10149 11:06:15.132045
10150 11:06:15.132228 R8152: Initializing
10151 11:06:15.132346
10152 11:06:15.135085 Version 6 (ocp_data = 5c30)
10153 11:06:15.135210
10154 11:06:15.138228 R8152: Done initializing
10155 11:06:15.138352
10156 11:06:15.138500 Adding net device
10157 11:06:17.025418
10158 11:06:17.025566 done.
10159 11:06:17.025637
10160 11:06:17.025699 MAC: 00:24:32:30:78:52
10161 11:06:17.025758
10162 11:06:17.028326 Sending DHCP discover... done.
10163 11:06:17.028430
10164 11:06:17.031892 Waiting for reply... done.
10165 11:06:17.031976
10166 11:06:17.034963 Sending DHCP request... done.
10167 11:06:17.035046
10168 11:06:17.038762 Waiting for reply... done.
10169 11:06:17.038844
10170 11:06:17.038909 My ip is 192.168.201.14
10171 11:06:17.038970
10172 11:06:17.041913 The DHCP server ip is 192.168.201.1
10173 11:06:17.041996
10174 11:06:17.048595 TFTP server IP predefined by user: 192.168.201.1
10175 11:06:17.048679
10176 11:06:17.055172 Bootfile predefined by user: 12925640/tftp-deploy-4frbx01r/kernel/image.itb
10177 11:06:17.055280
10178 11:06:17.058833 Sending tftp read request... done.
10179 11:06:17.058915
10180 11:06:17.062250 Waiting for the transfer...
10181 11:06:17.062330
10182 11:06:17.609803 00000000 ################################################################
10183 11:06:17.609956
10184 11:06:18.151215 00080000 ################################################################
10185 11:06:18.151368
10186 11:06:18.714837 00100000 ################################################################
10187 11:06:18.714986
10188 11:06:19.285616 00180000 ################################################################
10189 11:06:19.285747
10190 11:06:19.840446 00200000 ################################################################
10191 11:06:19.840583
10192 11:06:20.399294 00280000 ################################################################
10193 11:06:20.399441
10194 11:06:20.958059 00300000 ################################################################
10195 11:06:20.958214
10196 11:06:21.522884 00380000 ################################################################
10197 11:06:21.523030
10198 11:06:22.070376 00400000 ################################################################
10199 11:06:22.070542
10200 11:06:22.618159 00480000 ################################################################
10201 11:06:22.618340
10202 11:06:23.157571 00500000 ################################################################
10203 11:06:23.157708
10204 11:06:23.697194 00580000 ################################################################
10205 11:06:23.697343
10206 11:06:24.257363 00600000 ################################################################
10207 11:06:24.257502
10208 11:06:24.808180 00680000 ################################################################
10209 11:06:24.808335
10210 11:06:25.354594 00700000 ################################################################
10211 11:06:25.354798
10212 11:06:25.875510 00780000 ################################################################
10213 11:06:25.875764
10214 11:06:26.405275 00800000 ################################################################
10215 11:06:26.405495
10216 11:06:26.937107 00880000 ################################################################
10217 11:06:26.937242
10218 11:06:27.479578 00900000 ################################################################
10219 11:06:27.479779
10220 11:06:28.021906 00980000 ################################################################
10221 11:06:28.022045
10222 11:06:28.570693 00a00000 ################################################################
10223 11:06:28.570840
10224 11:06:29.135261 00a80000 ################################################################
10225 11:06:29.135425
10226 11:06:29.711249 00b00000 ################################################################
10227 11:06:29.711382
10228 11:06:30.258191 00b80000 ################################################################
10229 11:06:30.258325
10230 11:06:30.795042 00c00000 ################################################################
10231 11:06:30.795183
10232 11:06:31.359855 00c80000 ################################################################
10233 11:06:31.359987
10234 11:06:31.920763 00d00000 ################################################################
10235 11:06:31.920897
10236 11:06:32.467011 00d80000 ################################################################
10237 11:06:32.467207
10238 11:06:33.028743 00e00000 ################################################################
10239 11:06:33.028947
10240 11:06:33.602366 00e80000 ################################################################
10241 11:06:33.602599
10242 11:06:34.131350 00f00000 ################################################################
10243 11:06:34.131502
10244 11:06:34.661642 00f80000 ################################################################
10245 11:06:34.661796
10246 11:06:35.194531 01000000 ################################################################
10247 11:06:35.194671
10248 11:06:35.732455 01080000 ################################################################
10249 11:06:35.732599
10250 11:06:36.280398 01100000 ################################################################
10251 11:06:36.280550
10252 11:06:36.817801 01180000 ################################################################
10253 11:06:36.817953
10254 11:06:37.344695 01200000 ################################################################
10255 11:06:37.344897
10256 11:06:37.880775 01280000 ################################################################
10257 11:06:37.880910
10258 11:06:38.442779 01300000 ################################################################
10259 11:06:38.442969
10260 11:06:38.993716 01380000 ################################################################
10261 11:06:38.993915
10262 11:06:39.696730 01400000 ################################################################
10263 11:06:39.696884
10264 11:06:40.369843 01480000 ################################################################
10265 11:06:40.370058
10266 11:06:40.938587 01500000 ################################################################
10267 11:06:40.938728
10268 11:06:41.495807 01580000 ################################################################
10269 11:06:41.495965
10270 11:06:42.056388 01600000 ################################################################
10271 11:06:42.056523
10272 11:06:42.766523 01680000 ################################################################
10273 11:06:42.766739
10274 11:06:43.432656 01700000 ################################################################
10275 11:06:43.432789
10276 11:06:44.013616 01780000 ################################################################
10277 11:06:44.013747
10278 11:06:44.580042 01800000 ################################################################
10279 11:06:44.580225
10280 11:06:45.150770 01880000 ################################################################
10281 11:06:45.150925
10282 11:06:45.703858 01900000 ################################################################
10283 11:06:45.704005
10284 11:06:46.252090 01980000 ################################################################
10285 11:06:46.252288
10286 11:06:46.817241 01a00000 ################################################################
10287 11:06:46.817399
10288 11:06:47.384566 01a80000 ################################################################
10289 11:06:47.384716
10290 11:06:47.954054 01b00000 ################################################################
10291 11:06:47.954198
10292 11:06:48.528612 01b80000 ################################################################
10293 11:06:48.528752
10294 11:06:49.114361 01c00000 ################################################################
10295 11:06:49.114510
10296 11:06:49.144680 01c80000 #### done.
10297 11:06:49.144779
10298 11:06:49.147918 The bootfile was 29913146 bytes long.
10299 11:06:49.148007
10300 11:06:49.151012 Sending tftp read request... done.
10301 11:06:49.151101
10302 11:06:49.151190 Waiting for the transfer...
10303 11:06:49.151279
10304 11:06:49.154516 00000000 # done.
10305 11:06:49.154625
10306 11:06:49.161385 Command line loaded dynamically from TFTP file: 12925640/tftp-deploy-4frbx01r/kernel/cmdline
10307 11:06:49.161486
10308 11:06:49.184777 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12925640/extract-nfsrootfs-966tkp70,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10309 11:06:49.184881
10310 11:06:49.184967 Loading FIT.
10311 11:06:49.185047
10312 11:06:49.188077 Image ramdisk-1 has 17806133 bytes.
10313 11:06:49.188154
10314 11:06:49.191321 Image fdt-1 has 47278 bytes.
10315 11:06:49.191401
10316 11:06:49.194997 Image kernel-1 has 12057697 bytes.
10317 11:06:49.195076
10318 11:06:49.204876 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10319 11:06:49.204960
10320 11:06:49.221237 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10321 11:06:49.221339
10322 11:06:49.224401 Choosing best match conf-1 for compat google,spherion-rev2.
10323 11:06:49.228004
10324 11:06:49.231298 Connected to device vid:did:rid of 1ae0:0028:00
10325 11:06:49.242957
10326 11:06:49.246358 tpm_get_response: command 0x17b, return code 0x0
10327 11:06:49.246491
10328 11:06:49.253118 ec_init: CrosEC protocol v3 supported (256, 248)
10329 11:06:49.253290
10330 11:06:49.256529 tpm_cleanup: add release locality here.
10331 11:06:49.256613
10332 11:06:49.259725 Shutting down all USB controllers.
10333 11:06:49.259806
10334 11:06:49.263030 Removing current net device
10335 11:06:49.263111
10336 11:06:49.266379 Exiting depthcharge with code 4 at timestamp: 67890169
10337 11:06:49.266514
10338 11:06:49.269919 LZMA decompressing kernel-1 to 0x821a6718
10339 11:06:49.270001
10340 11:06:49.276521 LZMA decompressing kernel-1 to 0x40000000
10341 11:06:50.775652
10342 11:06:50.775792 jumping to kernel
10343 11:06:50.776243 end: 2.2.4 bootloader-commands (duration 00:00:40) [common]
10344 11:06:50.776361 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10345 11:06:50.776475 Setting prompt string to ['Linux version [0-9]']
10346 11:06:50.776580 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10347 11:06:50.776677 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10348 11:06:50.858018
10349 11:06:50.861714 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10350 11:06:50.865329 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10351 11:06:50.865429 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10352 11:06:50.865501 Setting prompt string to []
10353 11:06:50.865577 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10354 11:06:50.865651 Using line separator: #'\n'#
10355 11:06:50.865712 No login prompt set.
10356 11:06:50.865772 Parsing kernel messages
10357 11:06:50.865827 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10358 11:06:50.865931 [login-action] Waiting for messages, (timeout 00:03:45)
10359 11:06:50.865996 Waiting using forced prompt support (timeout 00:01:53)
10360 11:06:50.884513 [ 0.000000] Linux version 6.1.80-cip16 (KernelCI@build-j128891-arm64-gcc-10-defconfig-arm64-chromebook-nrg4h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024
10361 11:06:50.887960 [ 0.000000] random: crng init done
10362 11:06:50.891312 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10363 11:06:50.894596 [ 0.000000] efi: UEFI not found.
10364 11:06:50.904571 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10365 11:06:50.911038 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10366 11:06:50.921392 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10367 11:06:50.931143 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10368 11:06:50.937545 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10369 11:06:50.941217 [ 0.000000] printk: bootconsole [mtk8250] enabled
10370 11:06:50.950405 [ 0.000000] NUMA: No NUMA configuration found
10371 11:06:50.956354 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10372 11:06:50.963471 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10373 11:06:50.963568 [ 0.000000] Zone ranges:
10374 11:06:50.969675 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10375 11:06:50.973074 [ 0.000000] DMA32 empty
10376 11:06:50.979692 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10377 11:06:50.983155 [ 0.000000] Movable zone start for each node
10378 11:06:50.986699 [ 0.000000] Early memory node ranges
10379 11:06:50.993196 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10380 11:06:50.999925 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10381 11:06:51.006861 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10382 11:06:51.013519 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10383 11:06:51.019509 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10384 11:06:51.026516 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10385 11:06:51.082692 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10386 11:06:51.089245 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10387 11:06:51.095780 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10388 11:06:51.098824 [ 0.000000] psci: probing for conduit method from DT.
10389 11:06:51.106033 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10390 11:06:51.109209 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10391 11:06:51.116694 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10392 11:06:51.118806 [ 0.000000] psci: SMC Calling Convention v1.2
10393 11:06:51.125478 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10394 11:06:51.129182 [ 0.000000] Detected VIPT I-cache on CPU0
10395 11:06:51.135831 [ 0.000000] CPU features: detected: GIC system register CPU interface
10396 11:06:51.142499 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10397 11:06:51.149117 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10398 11:06:51.156181 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10399 11:06:51.162384 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10400 11:06:51.168805 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10401 11:06:51.175678 [ 0.000000] alternatives: applying boot alternatives
10402 11:06:51.178763 [ 0.000000] Fallback order for Node 0: 0
10403 11:06:51.185633 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10404 11:06:51.189151 [ 0.000000] Policy zone: Normal
10405 11:06:51.212499 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12925640/extract-nfsrootfs-966tkp70,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10406 11:06:51.222945 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10407 11:06:51.235629 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10408 11:06:51.244861 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10409 11:06:51.251405 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10410 11:06:51.255084 <6>[ 0.000000] software IO TLB: area num 8.
10411 11:06:51.311450 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10412 11:06:51.460162 <6>[ 0.000000] Memory: 7949804K/8385536K available (18048K kernel code, 4118K rwdata, 19616K rodata, 8448K init, 616K bss, 402964K reserved, 32768K cma-reserved)
10413 11:06:51.467028 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10414 11:06:51.473746 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10415 11:06:51.477080 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10416 11:06:51.483615 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10417 11:06:51.490492 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10418 11:06:51.493319 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10419 11:06:51.503494 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10420 11:06:51.510137 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10421 11:06:51.513248 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10422 11:06:51.521532 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10423 11:06:51.524380 <6>[ 0.000000] GICv3: 608 SPIs implemented
10424 11:06:51.531228 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10425 11:06:51.534246 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10426 11:06:51.537862 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10427 11:06:51.548099 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10428 11:06:51.557746 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10429 11:06:51.570956 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10430 11:06:51.578196 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10431 11:06:51.586451 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10432 11:06:51.600770 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10433 11:06:51.606764 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10434 11:06:51.613602 <6>[ 0.009176] Console: colour dummy device 80x25
10435 11:06:51.623504 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10436 11:06:51.626509 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10437 11:06:51.633161 <6>[ 0.029221] LSM: Security Framework initializing
10438 11:06:51.639699 <6>[ 0.034159] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10439 11:06:51.650057 <6>[ 0.041973] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10440 11:06:51.656868 <6>[ 0.051395] cblist_init_generic: Setting adjustable number of callback queues.
10441 11:06:51.663519 <6>[ 0.058838] cblist_init_generic: Setting shift to 3 and lim to 1.
10442 11:06:51.673665 <6>[ 0.065178] cblist_init_generic: Setting adjustable number of callback queues.
10443 11:06:51.676187 <6>[ 0.072605] cblist_init_generic: Setting shift to 3 and lim to 1.
10444 11:06:51.682850 <6>[ 0.079047] rcu: Hierarchical SRCU implementation.
10445 11:06:51.689716 <6>[ 0.084062] rcu: Max phase no-delay instances is 1000.
10446 11:06:51.696032 <6>[ 0.091088] EFI services will not be available.
10447 11:06:51.699506 <6>[ 0.096071] smp: Bringing up secondary CPUs ...
10448 11:06:51.707429 <6>[ 0.101153] Detected VIPT I-cache on CPU1
10449 11:06:51.713810 <6>[ 0.101222] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10450 11:06:51.721251 <6>[ 0.101254] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10451 11:06:51.724512 <6>[ 0.101584] Detected VIPT I-cache on CPU2
10452 11:06:51.730968 <6>[ 0.101632] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10453 11:06:51.737098 <6>[ 0.101648] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10454 11:06:51.743910 <6>[ 0.101905] Detected VIPT I-cache on CPU3
10455 11:06:51.750465 <6>[ 0.101951] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10456 11:06:51.757221 <6>[ 0.101965] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10457 11:06:51.760636 <6>[ 0.102270] CPU features: detected: Spectre-v4
10458 11:06:51.767111 <6>[ 0.102276] CPU features: detected: Spectre-BHB
10459 11:06:51.770575 <6>[ 0.102281] Detected PIPT I-cache on CPU4
10460 11:06:51.777268 <6>[ 0.102339] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10461 11:06:51.783891 <6>[ 0.102355] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10462 11:06:51.790405 <6>[ 0.102645] Detected PIPT I-cache on CPU5
10463 11:06:51.797063 <6>[ 0.102708] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10464 11:06:51.803742 <6>[ 0.102723] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10465 11:06:51.807039 <6>[ 0.103006] Detected PIPT I-cache on CPU6
10466 11:06:51.814046 <6>[ 0.103071] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10467 11:06:51.820752 <6>[ 0.103087] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10468 11:06:51.823986 <6>[ 0.103386] Detected PIPT I-cache on CPU7
10469 11:06:51.833684 <6>[ 0.103450] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10470 11:06:51.840647 <6>[ 0.103466] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10471 11:06:51.843836 <6>[ 0.103513] smp: Brought up 1 node, 8 CPUs
10472 11:06:51.847178 <6>[ 0.244813] SMP: Total of 8 processors activated.
10473 11:06:51.853456 <6>[ 0.249735] CPU features: detected: 32-bit EL0 Support
10474 11:06:51.863809 <6>[ 0.255098] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10475 11:06:51.870702 <6>[ 0.263953] CPU features: detected: Common not Private translations
10476 11:06:51.873687 <6>[ 0.270429] CPU features: detected: CRC32 instructions
10477 11:06:51.880279 <6>[ 0.275781] CPU features: detected: RCpc load-acquire (LDAPR)
10478 11:06:51.887198 <6>[ 0.281741] CPU features: detected: LSE atomic instructions
10479 11:06:51.893517 <6>[ 0.287522] CPU features: detected: Privileged Access Never
10480 11:06:51.897203 <6>[ 0.293302] CPU features: detected: RAS Extension Support
10481 11:06:51.903844 <6>[ 0.298945] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10482 11:06:51.910327 <6>[ 0.306164] CPU: All CPU(s) started at EL2
10483 11:06:51.913567 <6>[ 0.310481] alternatives: applying system-wide alternatives
10484 11:06:51.924844 <6>[ 0.321294] devtmpfs: initialized
10485 11:06:51.940872 <6>[ 0.330347] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10486 11:06:51.947531 <6>[ 0.340309] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10487 11:06:51.950868 <6>[ 0.348143] pinctrl core: initialized pinctrl subsystem
10488 11:06:51.958659 <6>[ 0.354819] DMI not present or invalid.
10489 11:06:51.965231 <6>[ 0.359233] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10490 11:06:51.972266 <6>[ 0.366094] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10491 11:06:51.982135 <6>[ 0.373685] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10492 11:06:51.988717 <6>[ 0.381901] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10493 11:06:51.995314 <6>[ 0.390140] audit: initializing netlink subsys (disabled)
10494 11:06:52.001661 <5>[ 0.395834] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10495 11:06:52.008456 <6>[ 0.396547] thermal_sys: Registered thermal governor 'step_wise'
10496 11:06:52.015270 <6>[ 0.403803] thermal_sys: Registered thermal governor 'power_allocator'
10497 11:06:52.018702 <6>[ 0.410058] cpuidle: using governor menu
10498 11:06:52.025107 <6>[ 0.421021] NET: Registered PF_QIPCRTR protocol family
10499 11:06:52.032097 <6>[ 0.426506] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10500 11:06:52.038792 <6>[ 0.433612] ASID allocator initialised with 32768 entries
10501 11:06:52.041749 <6>[ 0.440196] Serial: AMBA PL011 UART driver
10502 11:06:52.052965 <4>[ 0.449007] Trying to register duplicate clock ID: 134
10503 11:06:52.109151 <6>[ 0.508845] KASLR enabled
10504 11:06:52.123690 <6>[ 0.516561] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10505 11:06:52.130363 <6>[ 0.523572] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10506 11:06:52.137070 <6>[ 0.530061] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10507 11:06:52.143931 <6>[ 0.537067] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10508 11:06:52.150065 <6>[ 0.543557] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10509 11:06:52.156708 <6>[ 0.550561] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10510 11:06:52.163892 <6>[ 0.557049] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10511 11:06:52.170472 <6>[ 0.564053] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10512 11:06:52.173560 <6>[ 0.571588] ACPI: Interpreter disabled.
10513 11:06:52.182317 <6>[ 0.578029] iommu: Default domain type: Translated
10514 11:06:52.188653 <6>[ 0.583141] iommu: DMA domain TLB invalidation policy: strict mode
10515 11:06:52.192228 <5>[ 0.589806] SCSI subsystem initialized
10516 11:06:52.198305 <6>[ 0.593969] usbcore: registered new interface driver usbfs
10517 11:06:52.204762 <6>[ 0.599704] usbcore: registered new interface driver hub
10518 11:06:52.208388 <6>[ 0.605257] usbcore: registered new device driver usb
10519 11:06:52.215232 <6>[ 0.611361] pps_core: LinuxPPS API ver. 1 registered
10520 11:06:52.225156 <6>[ 0.616556] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10521 11:06:52.228644 <6>[ 0.625903] PTP clock support registered
10522 11:06:52.232050 <6>[ 0.630145] EDAC MC: Ver: 3.0.0
10523 11:06:52.239542 <6>[ 0.635303] FPGA manager framework
10524 11:06:52.246148 <6>[ 0.638982] Advanced Linux Sound Architecture Driver Initialized.
10525 11:06:52.249130 <6>[ 0.645766] vgaarb: loaded
10526 11:06:52.256081 <6>[ 0.648942] clocksource: Switched to clocksource arch_sys_counter
10527 11:06:52.259496 <5>[ 0.655371] VFS: Disk quotas dquot_6.6.0
10528 11:06:52.265782 <6>[ 0.659557] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10529 11:06:52.269228 <6>[ 0.666729] pnp: PnP ACPI: disabled
10530 11:06:52.277310 <6>[ 0.673401] NET: Registered PF_INET protocol family
10531 11:06:52.286942 <6>[ 0.678990] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10532 11:06:52.298451 <6>[ 0.691310] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10533 11:06:52.308744 <6>[ 0.700123] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10534 11:06:52.315553 <6>[ 0.708094] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10535 11:06:52.321799 <6>[ 0.716748] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10536 11:06:52.333407 <6>[ 0.726504] TCP: Hash tables configured (established 65536 bind 65536)
10537 11:06:52.340429 <6>[ 0.733310] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10538 11:06:52.346873 <6>[ 0.740506] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10539 11:06:52.353878 <6>[ 0.748205] NET: Registered PF_UNIX/PF_LOCAL protocol family
10540 11:06:52.360578 <6>[ 0.754382] RPC: Registered named UNIX socket transport module.
10541 11:06:52.363163 <6>[ 0.760535] RPC: Registered udp transport module.
10542 11:06:52.370137 <6>[ 0.765466] RPC: Registered tcp transport module.
10543 11:06:52.376435 <6>[ 0.770398] RPC: Registered tcp NFSv4.1 backchannel transport module.
10544 11:06:52.380124 <6>[ 0.777066] PCI: CLS 0 bytes, default 64
10545 11:06:52.383198 <6>[ 0.781476] Unpacking initramfs...
10546 11:06:52.400714 <6>[ 0.793570] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10547 11:06:52.410763 <6>[ 0.802237] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10548 11:06:52.413965 <6>[ 0.811089] kvm [1]: IPA Size Limit: 40 bits
10549 11:06:52.420438 <6>[ 0.815618] kvm [1]: GICv3: no GICV resource entry
10550 11:06:52.424297 <6>[ 0.820641] kvm [1]: disabling GICv2 emulation
10551 11:06:52.430827 <6>[ 0.825327] kvm [1]: GIC system register CPU interface enabled
10552 11:06:52.433772 <6>[ 0.831488] kvm [1]: vgic interrupt IRQ18
10553 11:06:52.440590 <6>[ 0.835844] kvm [1]: VHE mode initialized successfully
10554 11:06:52.447907 <5>[ 0.842406] Initialise system trusted keyrings
10555 11:06:52.453639 <6>[ 0.847206] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10556 11:06:52.461007 <6>[ 0.857419] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10557 11:06:52.467842 <5>[ 0.863837] NFS: Registering the id_resolver key type
10558 11:06:52.471481 <5>[ 0.869143] Key type id_resolver registered
10559 11:06:52.478486 <5>[ 0.873558] Key type id_legacy registered
10560 11:06:52.484670 <6>[ 0.877837] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10561 11:06:52.491107 <6>[ 0.884760] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10562 11:06:52.497989 <6>[ 0.892497] 9p: Installing v9fs 9p2000 file system support
10563 11:06:52.534604 <5>[ 0.930175] Key type asymmetric registered
10564 11:06:52.537448 <5>[ 0.934506] Asymmetric key parser 'x509' registered
10565 11:06:52.547449 <6>[ 0.939651] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10566 11:06:52.551039 <6>[ 0.947278] io scheduler mq-deadline registered
10567 11:06:52.554037 <6>[ 0.952062] io scheduler kyber registered
10568 11:06:52.573327 <6>[ 0.969166] EINJ: ACPI disabled.
10569 11:06:52.605467 <4>[ 0.994971] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10570 11:06:52.615427 <4>[ 1.005608] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10571 11:06:52.630155 <6>[ 1.026551] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10572 11:06:52.638156 <6>[ 1.034578] printk: console [ttyS0] disabled
10573 11:06:52.666388 <6>[ 1.059207] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10574 11:06:52.673241 <6>[ 1.068673] printk: console [ttyS0] enabled
10575 11:06:52.676272 <6>[ 1.068673] printk: console [ttyS0] enabled
10576 11:06:52.683085 <6>[ 1.077566] printk: bootconsole [mtk8250] disabled
10577 11:06:52.686503 <6>[ 1.077566] printk: bootconsole [mtk8250] disabled
10578 11:06:52.692825 <6>[ 1.088779] SuperH (H)SCI(F) driver initialized
10579 11:06:52.696344 <6>[ 1.094068] msm_serial: driver initialized
10580 11:06:52.710561 <6>[ 1.103124] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10581 11:06:52.720679 <6>[ 1.111670] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10582 11:06:52.726864 <6>[ 1.120212] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10583 11:06:52.736924 <6>[ 1.128841] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10584 11:06:52.743380 <6>[ 1.137553] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10585 11:06:52.753681 <6>[ 1.146266] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10586 11:06:52.763703 <6>[ 1.154814] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10587 11:06:52.770124 <6>[ 1.163629] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10588 11:06:52.780178 <6>[ 1.172176] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10589 11:06:52.791489 <6>[ 1.187882] loop: module loaded
10590 11:06:52.798957 <6>[ 1.193914] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10591 11:06:52.821092 <4>[ 1.217290] mtk-pmic-keys: Failed to locate of_node [id: -1]
10592 11:06:52.828433 <6>[ 1.224184] megasas: 07.719.03.00-rc1
10593 11:06:52.837747 <6>[ 1.233815] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10594 11:06:52.844385 <6>[ 1.240337] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10595 11:06:52.861083 <6>[ 1.256991] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10596 11:06:52.917660 <6>[ 1.307132] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10597 11:06:53.132319 <6>[ 1.528625] Freeing initrd memory: 17384K
10598 11:06:53.142546 <6>[ 1.538864] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10599 11:06:53.153324 <6>[ 1.549671] tun: Universal TUN/TAP device driver, 1.6
10600 11:06:53.156912 <6>[ 1.555727] thunder_xcv, ver 1.0
10601 11:06:53.160162 <6>[ 1.559233] thunder_bgx, ver 1.0
10602 11:06:53.163591 <6>[ 1.562726] nicpf, ver 1.0
10603 11:06:53.173649 <6>[ 1.566743] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10604 11:06:53.177165 <6>[ 1.574221] hns3: Copyright (c) 2017 Huawei Corporation.
10605 11:06:53.180648 <6>[ 1.579810] hclge is initializing
10606 11:06:53.187105 <6>[ 1.583388] e1000: Intel(R) PRO/1000 Network Driver
10607 11:06:53.193723 <6>[ 1.588517] e1000: Copyright (c) 1999-2006 Intel Corporation.
10608 11:06:53.197273 <6>[ 1.594529] e1000e: Intel(R) PRO/1000 Network Driver
10609 11:06:53.204138 <6>[ 1.599744] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10610 11:06:53.210752 <6>[ 1.605928] igb: Intel(R) Gigabit Ethernet Network Driver
10611 11:06:53.217195 <6>[ 1.611578] igb: Copyright (c) 2007-2014 Intel Corporation.
10612 11:06:53.223916 <6>[ 1.617413] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10613 11:06:53.230580 <6>[ 1.623930] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10614 11:06:53.234064 <6>[ 1.630393] sky2: driver version 1.30
10615 11:06:53.240678 <6>[ 1.635379] VFIO - User Level meta-driver version: 0.3
10616 11:06:53.247616 <6>[ 1.643627] usbcore: registered new interface driver usb-storage
10617 11:06:53.254176 <6>[ 1.650073] usbcore: registered new device driver onboard-usb-hub
10618 11:06:53.262945 <6>[ 1.659212] mt6397-rtc mt6359-rtc: registered as rtc0
10619 11:06:53.273487 <6>[ 1.664675] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T11:06:55 UTC (1709464015)
10620 11:06:53.276434 <6>[ 1.674239] i2c_dev: i2c /dev entries driver
10621 11:06:53.292869 <6>[ 1.686035] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10622 11:06:53.313704 <6>[ 1.710031] cpu cpu0: EM: created perf domain
10623 11:06:53.317336 <6>[ 1.714950] cpu cpu4: EM: created perf domain
10624 11:06:53.324754 <6>[ 1.720544] sdhci: Secure Digital Host Controller Interface driver
10625 11:06:53.331306 <6>[ 1.726978] sdhci: Copyright(c) Pierre Ossman
10626 11:06:53.338224 <6>[ 1.731931] Synopsys Designware Multimedia Card Interface Driver
10627 11:06:53.344658 <6>[ 1.738568] sdhci-pltfm: SDHCI platform and OF driver helper
10628 11:06:53.347890 <6>[ 1.738614] mmc0: CQHCI version 5.10
10629 11:06:53.354614 <6>[ 1.748642] ledtrig-cpu: registered to indicate activity on CPUs
10630 11:06:53.361482 <6>[ 1.755664] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10631 11:06:53.368346 <6>[ 1.762736] usbcore: registered new interface driver usbhid
10632 11:06:53.371530 <6>[ 1.768558] usbhid: USB HID core driver
10633 11:06:53.378175 <6>[ 1.772723] spi_master spi0: will run message pump with realtime priority
10634 11:06:53.424303 <6>[ 1.813689] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10635 11:06:53.443606 <6>[ 1.829473] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10636 11:06:53.450853 <6>[ 1.844305] cros-ec-spi spi0.0: Chrome EC device registered
10637 11:06:53.454759 <6>[ 1.850375] mmc0: Command Queue Engine enabled
10638 11:06:53.460484 <6>[ 1.855128] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10639 11:06:53.467379 <6>[ 1.862715] mmcblk0: mmc0:0001 DA4128 116 GiB
10640 11:06:53.474325 <6>[ 1.863308] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10641 11:06:53.480469 <6>[ 1.872282] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10642 11:06:53.487335 <6>[ 1.877877] NET: Registered PF_PACKET protocol family
10643 11:06:53.490794 <6>[ 1.884105] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10644 11:06:53.497551 <6>[ 1.888070] 9pnet: Installing 9P2000 support
10645 11:06:53.500844 <6>[ 1.893887] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10646 11:06:53.507329 <5>[ 1.897763] Key type dns_resolver registered
10647 11:06:53.513744 <6>[ 1.903627] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10648 11:06:53.517591 <6>[ 1.908040] registered taskstats version 1
10649 11:06:53.524197 <5>[ 1.918396] Loading compiled-in X.509 certificates
10650 11:06:53.551140 <4>[ 1.940263] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10651 11:06:53.561446 <4>[ 1.950956] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10652 11:06:53.567484 <3>[ 1.961503] debugfs: File 'uA_load' in directory '/' already present!
10653 11:06:53.574511 <3>[ 1.968209] debugfs: File 'min_uV' in directory '/' already present!
10654 11:06:53.580924 <3>[ 1.974866] debugfs: File 'max_uV' in directory '/' already present!
10655 11:06:53.587546 <3>[ 1.981477] debugfs: File 'constraint_flags' in directory '/' already present!
10656 11:06:53.597749 <3>[ 1.990594] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10657 11:06:53.608417 <6>[ 2.003910] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10658 11:06:53.614354 <6>[ 2.010890] xhci-mtk 11200000.usb: xHCI Host Controller
10659 11:06:53.621570 <6>[ 2.016399] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10660 11:06:53.631241 <6>[ 2.024226] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10661 11:06:53.637965 <6>[ 2.033640] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10662 11:06:53.644793 <6>[ 2.039704] xhci-mtk 11200000.usb: xHCI Host Controller
10663 11:06:53.651298 <6>[ 2.045181] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10664 11:06:53.658132 <6>[ 2.052827] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10665 11:06:53.664673 <6>[ 2.060422] hub 1-0:1.0: USB hub found
10666 11:06:53.668353 <6>[ 2.064430] hub 1-0:1.0: 1 port detected
10667 11:06:53.674961 <6>[ 2.068695] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10668 11:06:53.681718 <6>[ 2.077328] hub 2-0:1.0: USB hub found
10669 11:06:53.684881 <6>[ 2.081355] hub 2-0:1.0: 1 port detected
10670 11:06:53.693358 <6>[ 2.089681] mtk-msdc 11f70000.mmc: Got CD GPIO
10671 11:06:53.703995 <6>[ 2.096624] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10672 11:06:53.710851 <6>[ 2.104649] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10673 11:06:53.720319 <4>[ 2.112542] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10674 11:06:53.730778 <6>[ 2.122068] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10675 11:06:53.737353 <6>[ 2.130148] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10676 11:06:53.744533 <6>[ 2.138164] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10677 11:06:53.754182 <6>[ 2.146077] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10678 11:06:53.760332 <6>[ 2.153898] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10679 11:06:53.770408 <6>[ 2.161715] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10680 11:06:53.780884 <6>[ 2.172194] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10681 11:06:53.787298 <6>[ 2.180556] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10682 11:06:53.797336 <6>[ 2.188899] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10683 11:06:53.804354 <6>[ 2.197241] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10684 11:06:53.813908 <6>[ 2.205579] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10685 11:06:53.821028 <6>[ 2.213920] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10686 11:06:53.830572 <6>[ 2.222257] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10687 11:06:53.836962 <6>[ 2.230595] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10688 11:06:53.847557 <6>[ 2.238933] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10689 11:06:53.853652 <6>[ 2.247270] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10690 11:06:53.864428 <6>[ 2.255614] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10691 11:06:53.870884 <6>[ 2.263952] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10692 11:06:53.880347 <6>[ 2.272290] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10693 11:06:53.887348 <6>[ 2.280627] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10694 11:06:53.897253 <6>[ 2.288965] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10695 11:06:53.903902 <6>[ 2.297701] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10696 11:06:53.910631 <6>[ 2.304862] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10697 11:06:53.917677 <6>[ 2.311627] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10698 11:06:53.924519 <6>[ 2.318397] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10699 11:06:53.930707 <6>[ 2.325329] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10700 11:06:53.940209 <6>[ 2.332178] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10701 11:06:53.951354 <6>[ 2.341308] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10702 11:06:53.957019 <6>[ 2.350427] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10703 11:06:53.966682 <6>[ 2.359722] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10704 11:06:53.977178 <6>[ 2.369188] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10705 11:06:53.986831 <6>[ 2.378658] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10706 11:06:53.996804 <6>[ 2.387778] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10707 11:06:54.006640 <6>[ 2.397244] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10708 11:06:54.013930 <6>[ 2.406362] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10709 11:06:54.023404 <6>[ 2.415657] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10710 11:06:54.033602 <6>[ 2.425818] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10711 11:06:54.039907 <6>[ 2.429240] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10712 11:06:54.049852 <6>[ 2.437507] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10713 11:06:54.056994 <6>[ 2.452467] Trying to probe devices needed for running init ...
10714 11:06:54.072638 <6>[ 2.468450] hub 2-1:1.0: USB hub found
10715 11:06:54.075302 <6>[ 2.472891] hub 2-1:1.0: 3 ports detected
10716 11:06:54.084592 <6>[ 2.479759] hub 2-1:1.0: USB hub found
10717 11:06:54.087443 <6>[ 2.484103] hub 2-1:1.0: 3 ports detected
10718 11:06:54.196556 <6>[ 2.589216] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10719 11:06:54.350815 <6>[ 2.747164] hub 1-1:1.0: USB hub found
10720 11:06:54.354209 <6>[ 2.751682] hub 1-1:1.0: 4 ports detected
10721 11:06:54.364321 <6>[ 2.760346] hub 1-1:1.0: USB hub found
10722 11:06:54.367347 <6>[ 2.764721] hub 1-1:1.0: 4 ports detected
10723 11:06:54.428516 <6>[ 2.821306] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10724 11:06:54.688748 <6>[ 3.081255] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10725 11:06:54.820961 <6>[ 3.217202] hub 1-1.4:1.0: USB hub found
10726 11:06:54.824527 <6>[ 3.221868] hub 1-1.4:1.0: 2 ports detected
10727 11:06:54.834643 <6>[ 3.230557] hub 1-1.4:1.0: USB hub found
10728 11:06:54.837295 <6>[ 3.235166] hub 1-1.4:1.0: 2 ports detected
10729 11:06:55.136256 <6>[ 3.529224] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10730 11:06:55.328285 <6>[ 3.721225] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10731 11:07:06.333897 <6>[ 14.734278] ALSA device list:
10732 11:07:06.340076 <6>[ 14.737569] No soundcards found.
10733 11:07:06.348043 <6>[ 14.745488] Freeing unused kernel memory: 8448K
10734 11:07:06.350840 <6>[ 14.750899] Run /init as init process
10735 11:07:06.360424 Loading, please wait...
10736 11:07:06.375946 Starting version 247.3-7+deb11u4
10737 11:07:06.608355 <6>[ 15.002886] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10738 11:07:06.618873 <6>[ 15.016087] remoteproc remoteproc0: scp is available
10739 11:07:06.625624 <6>[ 15.021790] remoteproc remoteproc0: powering up scp
10740 11:07:06.631842 <6>[ 15.027006] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10741 11:07:06.639476 <6>[ 15.037204] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10742 11:07:06.650717 <3>[ 15.043782] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10743 11:07:06.656591 <3>[ 15.051956] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 11:07:06.666121 <6>[ 15.055889] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10745 11:07:06.672856 <3>[ 15.060059] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 11:07:06.682706 <6>[ 15.067648] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10747 11:07:06.689953 <6>[ 15.084434] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10748 11:07:06.702147 <3>[ 15.096460] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 11:07:06.705432 <6>[ 15.096845] mc: Linux media interface: v0.10
10750 11:07:06.715690 <3>[ 15.104620] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 11:07:06.722437 <4>[ 15.105693] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10752 11:07:06.728566 <6>[ 15.107582] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10753 11:07:06.735732 <4>[ 15.107692] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10754 11:07:06.745860 <4>[ 15.130776] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10755 11:07:06.749362 <4>[ 15.130776] Fallback method does not support PEC.
10756 11:07:06.759855 <3>[ 15.132138] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 11:07:06.765953 <6>[ 15.133346] usbcore: registered new device driver r8152-cfgselector
10758 11:07:06.770074 <6>[ 15.134406] videodev: Linux video capture interface: v2.00
10759 11:07:06.779748 <3>[ 15.155188] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10760 11:07:06.786680 <3>[ 15.161136] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10761 11:07:06.796449 <3>[ 15.161141] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10762 11:07:06.802983 <3>[ 15.161189] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10763 11:07:06.813350 <6>[ 15.163812] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10764 11:07:06.819997 <6>[ 15.163835] remoteproc remoteproc0: remote processor scp is now up
10765 11:07:06.826486 <6>[ 15.163875] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10766 11:07:06.833505 <6>[ 15.183523] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10767 11:07:06.843501 <3>[ 15.190272] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 11:07:06.850169 <3>[ 15.190278] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 11:07:06.859444 <3>[ 15.190280] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 11:07:06.866253 <3>[ 15.190342] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10771 11:07:06.876708 <3>[ 15.190357] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 11:07:06.883342 <3>[ 15.190361] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10773 11:07:06.889848 <3>[ 15.190376] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 11:07:06.899858 <3>[ 15.190379] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10775 11:07:06.906437 <3>[ 15.190420] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 11:07:06.912739 <6>[ 15.214279] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10777 11:07:06.922671 <6>[ 15.218656] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10778 11:07:06.933115 <6>[ 15.219815] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10779 11:07:06.939110 <3>[ 15.221897] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10780 11:07:06.945995 <6>[ 15.222202] pci_bus 0000:00: root bus resource [bus 00-ff]
10781 11:07:06.953069 <6>[ 15.222208] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10782 11:07:06.962657 <6>[ 15.222211] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10783 11:07:06.969101 <6>[ 15.222242] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10784 11:07:06.975972 <6>[ 15.222257] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10785 11:07:06.982766 <6>[ 15.222322] pci 0000:00:00.0: supports D1 D2
10786 11:07:06.989741 <6>[ 15.222325] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10787 11:07:06.996094 <6>[ 15.223454] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10788 11:07:07.002984 <6>[ 15.223530] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10789 11:07:07.009434 <6>[ 15.223556] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10790 11:07:07.019112 <6>[ 15.223574] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10791 11:07:07.025708 <6>[ 15.223590] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10792 11:07:07.029260 <6>[ 15.223694] pci 0000:01:00.0: supports D1 D2
10793 11:07:07.036254 <6>[ 15.223696] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10794 11:07:07.042384 <6>[ 15.233038] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10795 11:07:07.052783 <6>[ 15.233798] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10796 11:07:07.063039 <6>[ 15.237492] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10797 11:07:07.072600 <6>[ 15.237732] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10798 11:07:07.079238 <6>[ 15.246751] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10799 11:07:07.089732 <4>[ 15.276235] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10800 11:07:07.095316 <6>[ 15.277885] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10801 11:07:07.098629 <6>[ 15.278604] Bluetooth: Core ver 2.22
10802 11:07:07.105631 <6>[ 15.278680] NET: Registered PF_BLUETOOTH protocol family
10803 11:07:07.112483 <6>[ 15.278683] Bluetooth: HCI device and connection manager initialized
10804 11:07:07.118623 <6>[ 15.278711] Bluetooth: HCI socket layer initialized
10805 11:07:07.122255 <6>[ 15.278723] Bluetooth: L2CAP socket layer initialized
10806 11:07:07.128615 <6>[ 15.278743] Bluetooth: SCO socket layer initialized
10807 11:07:07.135634 <4>[ 15.285998] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10808 11:07:07.145417 <6>[ 15.294033] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10809 11:07:07.152068 <6>[ 15.294050] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10810 11:07:07.158883 <6>[ 15.294065] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10811 11:07:07.165312 <6>[ 15.294080] pci 0000:00:00.0: PCI bridge to [bus 01]
10812 11:07:07.171610 <6>[ 15.294089] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10813 11:07:07.181598 <6>[ 15.294154] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10814 11:07:07.191732 <6>[ 15.303736] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10815 11:07:07.198305 <6>[ 15.310469] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10816 11:07:07.205248 <6>[ 15.311237] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10817 11:07:07.211663 <6>[ 15.317418] usbcore: registered new interface driver uvcvideo
10818 11:07:07.218590 <6>[ 15.325951] usbcore: registered new interface driver btusb
10819 11:07:07.221440 <6>[ 15.326029] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10820 11:07:07.228276 <6>[ 15.326528] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10821 11:07:07.238296 <4>[ 15.327258] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10822 11:07:07.244915 <3>[ 15.327265] Bluetooth: hci0: Failed to load firmware file (-2)
10823 11:07:07.251241 <3>[ 15.327267] Bluetooth: hci0: Failed to set up firmware (-2)
10824 11:07:07.261100 <4>[ 15.327269] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10825 11:07:07.271628 <5>[ 15.346130] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10826 11:07:07.274439 <6>[ 15.673002] r8152 2-1.3:1.0 eth0: v1.12.13
10827 11:07:07.280936 <6>[ 15.677561] usbcore: registered new interface driver r8152
10828 11:07:07.287969 <5>[ 15.680720] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10829 11:07:07.294255 <5>[ 15.690364] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10830 11:07:07.304506 <4>[ 15.698805] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10831 11:07:07.311019 <6>[ 15.699255] usbcore: registered new interface driver cdc_ether
10832 11:07:07.317834 <6>[ 15.707682] cfg80211: failed to load regulatory.db
10833 11:07:07.324400 <6>[ 15.721213] usbcore: registered new interface driver r8153_ecm
10834 11:07:07.347012 <6>[ 15.744753] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10835 11:07:07.363679 <6>[ 15.757632] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10836 11:07:07.369756 <6>[ 15.765185] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10837 11:07:07.394137 <6>[ 15.791829] mt7921e 0000:01:00.0: ASIC revision: 79610010
10838 11:07:07.498153 <6>[ 15.892526] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10839 11:07:07.501832 <6>[ 15.892526]
10840 11:07:07.512996 Begin: Loading essential drivers ... done.
10841 11:07:07.516862 Begin: Running /scripts/init-premount ... done.
10842 11:07:07.522976 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10843 11:07:07.533246 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10844 11:07:07.536354 Device /sys/class/net/enx002432307852 found
10845 11:07:07.536438 done.
10846 11:07:07.603158 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10847 11:07:07.767140 <6>[ 16.161623] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10848 11:07:08.529690 <6>[ 16.927394] r8152 2-1.3:1.0 enx002432307852: carrier on
10849 11:07:08.616577 <6>[ 17.014491] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10850 11:07:08.766843 IP-Config: no response after 2 secs - giving up
10851 11:07:08.802307 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10852 11:07:08.823485 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:3d mtu 1500 DHCP
10853 11:07:09.538664 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10854 11:07:09.545169 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10855 11:07:09.551824 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10856 11:07:09.558232 host : mt8192-asurada-spherion-r0-cbg-3
10857 11:07:09.565091 domain : lava-rack
10858 11:07:09.568557 rootserver: 192.168.201.1 rootpath:
10859 11:07:09.571638 filename :
10860 11:07:09.675586 done.
10861 11:07:09.683444 Begin: Running /scripts/nfs-bottom ... done.
10862 11:07:09.704903 Begin: Running /scripts/init-bottom ... done.
10863 11:07:10.930610 <6>[ 19.328542] NET: Registered PF_INET6 protocol family
10864 11:07:10.937298 <6>[ 19.335635] Segment Routing with IPv6
10865 11:07:10.940438 <6>[ 19.339619] In-situ OAM (IOAM) with IPv6
10866 11:07:11.085492 <30>[ 19.463717] systemd[1]: systemd 247.3-7+deb11u4 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10867 11:07:11.089401 <30>[ 19.488111] systemd[1]: Detected architecture arm64.
10868 11:07:11.111522
10869 11:07:11.114762 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10870 11:07:11.114870
10871 11:07:11.133556 <30>[ 19.531908] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10872 11:07:12.032806 <30>[ 20.427965] systemd[1]: Queued start job for default target Graphical Interface.
10873 11:07:12.065070 <30>[ 20.463699] systemd[1]: Created slice system-getty.slice.
10874 11:07:12.071937 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10875 11:07:12.088089 <30>[ 20.486578] systemd[1]: Created slice system-modprobe.slice.
10876 11:07:12.095299 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10877 11:07:12.112288 <30>[ 20.510485] systemd[1]: Created slice system-serial\x2dgetty.slice.
10878 11:07:12.122491 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10879 11:07:12.135914 <30>[ 20.534276] systemd[1]: Created slice User and Session Slice.
10880 11:07:12.142611 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10881 11:07:12.163182 <30>[ 20.558070] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10882 11:07:12.172878 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10883 11:07:12.191423 <30>[ 20.585986] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10884 11:07:12.197405 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10885 11:07:12.221754 <30>[ 20.613352] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10886 11:07:12.228179 <30>[ 20.625512] systemd[1]: Reached target Local Encrypted Volumes.
10887 11:07:12.235318 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10888 11:07:12.252034 <30>[ 20.649814] systemd[1]: Reached target Paths.
10889 11:07:12.258267 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10890 11:07:12.270645 <30>[ 20.669223] systemd[1]: Reached target Remote File Systems.
10891 11:07:12.277334 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10892 11:07:12.295091 <30>[ 20.693599] systemd[1]: Reached target Slices.
10893 11:07:12.301560 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10894 11:07:12.314683 <30>[ 20.713229] systemd[1]: Reached target Swap.
10895 11:07:12.318349 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10896 11:07:12.338814 <30>[ 20.733696] systemd[1]: Listening on initctl Compatibility Named Pipe.
10897 11:07:12.345347 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10898 11:07:12.352089 <30>[ 20.749886] systemd[1]: Listening on Journal Audit Socket.
10899 11:07:12.358697 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10900 11:07:12.375992 <30>[ 20.774558] systemd[1]: Listening on Journal Socket (/dev/log).
10901 11:07:12.382337 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10902 11:07:12.399325 <30>[ 20.797805] systemd[1]: Listening on Journal Socket.
10903 11:07:12.406646 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10904 11:07:12.423434 <30>[ 20.818787] systemd[1]: Listening on Network Service Netlink Socket.
10905 11:07:12.430048 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10906 11:07:12.445593 <30>[ 20.844337] systemd[1]: Listening on udev Control Socket.
10907 11:07:12.452501 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10908 11:07:12.467606 <30>[ 20.865673] systemd[1]: Listening on udev Kernel Socket.
10909 11:07:12.473840 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10910 11:07:12.530876 <30>[ 20.929359] systemd[1]: Mounting Huge Pages File System...
10911 11:07:12.537361 Mounting [0;1;39mHuge Pages File System[0m...
10912 11:07:12.555054 <30>[ 20.953395] systemd[1]: Mounting POSIX Message Queue File System...
10913 11:07:12.561681 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10914 11:07:12.603355 <30>[ 21.001552] systemd[1]: Mounting Kernel Debug File System...
10915 11:07:12.610064 Mounting [0;1;39mKernel Debug File System[0m...
10916 11:07:12.626367 <30>[ 21.021712] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10917 11:07:12.643270 <30>[ 21.037638] systemd[1]: Starting Create list of static device nodes for the current kernel...
10918 11:07:12.649209 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10919 11:07:12.691014 <30>[ 21.089538] systemd[1]: Starting Load Kernel Module configfs...
10920 11:07:12.697466 Starting [0;1;39mLoad Kernel Module configfs[0m...
10921 11:07:12.719293 <30>[ 21.117730] systemd[1]: Starting Load Kernel Module drm...
10922 11:07:12.726077 Starting [0;1;39mLoad Kernel Module drm[0m...
10923 11:07:12.747394 <30>[ 21.145898] systemd[1]: Starting Load Kernel Module fuse...
10924 11:07:12.754210 Starting [0;1;39mLoad Kernel Module fuse[0m...
10925 11:07:12.793360 <30>[ 21.188219] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10926 11:07:12.799943 <6>[ 21.188424] fuse: init (API version 7.37)
10927 11:07:12.807369 <30>[ 21.205557] systemd[1]: Starting Journal Service...
10928 11:07:12.810596 Starting [0;1;39mJournal Service[0m...
10929 11:07:12.838618 <30>[ 21.236822] systemd[1]: Starting Load Kernel Modules...
10930 11:07:12.844751 Starting [0;1;39mLoad Kernel Modules[0m...
10931 11:07:12.866257 <30>[ 21.261221] systemd[1]: Starting Remount Root and Kernel File Systems...
10932 11:07:12.872453 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10933 11:07:12.890701 <30>[ 21.289147] systemd[1]: Starting Coldplug All udev Devices...
10934 11:07:12.897603 Starting [0;1;39mColdplug All udev Devices[0m...
10935 11:07:12.916250 <30>[ 21.314793] systemd[1]: Mounted Huge Pages File System.
10936 11:07:12.922972 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10937 11:07:12.939783 <30>[ 21.337834] systemd[1]: Mounted POSIX Message Queue File System.
10938 11:07:12.946355 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10939 11:07:12.956523 <3>[ 21.350693] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 11:07:12.963432 <30>[ 21.361541] systemd[1]: Mounted Kernel Debug File System.
10941 11:07:12.970168 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10942 11:07:12.990123 <3>[ 21.384976] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 11:07:12.999504 <30>[ 21.394953] systemd[1]: Finished Create list of static device nodes for the current kernel.
10944 11:07:13.009371 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10945 11:07:13.023538 <30>[ 21.421989] systemd[1]: modprobe@configfs.service: Succeeded.
10946 11:07:13.030663 <30>[ 21.428792] systemd[1]: Finished Load Kernel Module configfs.
10947 11:07:13.044248 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 21.439150] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 11:07:13.047496 l Module configfs[0m.
10949 11:07:13.067875 <30>[ 21.466138] systemd[1]: modprobe@drm.service: Succeeded.
10950 11:07:13.075035 <30>[ 21.472732] systemd[1]: Finished Load Kernel Module drm.
10951 11:07:13.088020 [[0;32m OK [0m] Finished [0<3>[ 21.479942] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 11:07:13.091214 ;1;39mLoad Kernel Module drm[0m.
10953 11:07:13.109067 <30>[ 21.506788] systemd[1]: modprobe@fuse.service: Succeeded.
10954 11:07:13.119108 <3>[ 21.510095] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 11:07:13.122446 <30>[ 21.513564] systemd[1]: Finished Load Kernel Module fuse.
10956 11:07:13.129223 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10957 11:07:13.147755 <3>[ 21.542938] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 11:07:13.155635 <30>[ 21.554141] systemd[1]: Finished Load Kernel Modules.
10959 11:07:13.162427 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10960 11:07:13.178540 <3>[ 21.573533] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 11:07:13.188966 <30>[ 21.584120] systemd[1]: Finished Remount Root and Kernel File Systems.
10962 11:07:13.195636 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10963 11:07:13.209600 <3>[ 21.603702] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 11:07:13.241951 <3>[ 21.637491] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 11:07:13.266596 <30>[ 21.663757] systemd[1]: Mounting FUSE Control File System...
10966 11:07:13.276677 <3>[ 21.669695] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 11:07:13.279613 Mounting [0;1;39mFUSE Control File System[0m...
10968 11:07:13.300922 <30>[ 21.695983] systemd[1]: Mounting Kernel Configuration File System...
10969 11:07:13.305156 Mounting [0;1;39mKernel Configuration File System[0m...
10970 11:07:13.331683 <30>[ 21.726944] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10971 11:07:13.341947 <30>[ 21.736126] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10972 11:07:13.376072 <30>[ 21.774351] systemd[1]: Starting Load/Save Random Seed...
10973 11:07:13.382747 Starting [0;1;39mLoad/Save Random Seed[0m...
10974 11:07:13.398235 <30>[ 21.796899] systemd[1]: Starting Apply Kernel Variables...
10975 11:07:13.405397 Starting [0;1;39mApply Kernel Variables[0m...
10976 11:07:13.427844 <4>[ 21.815921] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10977 11:07:13.437246 <3>[ 21.831627] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10978 11:07:13.463539 <30>[ 21.861789] systemd[1]: Starting Create System Users...
10979 11:07:13.469745 Starting [0;1;39mCreate System Users[0m...
10980 11:07:13.485537 <30>[ 21.884227] systemd[1]: Started Journal Service.
10981 11:07:13.491970 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10982 11:07:13.516047 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10983 11:07:13.530494 See 'systemctl status systemd-udev-trigger.service' for details.
10984 11:07:13.547746 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10985 11:07:13.564114 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10986 11:07:13.580420 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10987 11:07:13.596795 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10988 11:07:13.617069 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10989 11:07:13.663650 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10990 11:07:13.683093 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10991 11:07:13.728937 <46>[ 22.124406] systemd-journald[298]: Received client request to flush runtime journal.
10992 11:07:14.499243 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10993 11:07:14.515639 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10994 11:07:14.530567 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10995 11:07:14.595050 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10996 11:07:15.167001 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10997 11:07:15.211238 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10998 11:07:15.268574 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10999 11:07:15.311696 Starting [0;1;39mNetwork Service[0m...
11000 11:07:15.606741 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11001 11:07:15.630884 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11002 11:07:15.675047 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11003 11:07:15.980867 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11004 11:07:15.997934 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11005 11:07:16.031663 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11006 11:07:16.083661 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11007 11:07:16.102810 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11008 11:07:16.127017 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11009 11:07:16.147344 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11010 11:07:16.199416 Starting [0;1;39mNetwork Name Resolution[0m...
11011 11:07:16.228162 Starting [0;1;39mNetwork Time Synchronization[0m...
11012 11:07:16.246842 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11013 11:07:16.306764 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11014 11:07:16.467410 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11015 11:07:16.483720 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11016 11:07:16.502123 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11017 11:07:16.515544 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11018 11:07:16.530404 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11019 11:07:16.657205 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11020 11:07:16.704864 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11021 11:07:16.731729 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11022 11:07:16.756281 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11023 11:07:16.770320 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11024 11:07:16.967644 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11025 11:07:16.982817 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11026 11:07:16.998701 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11027 11:07:17.063550 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11028 11:07:17.554880 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11029 11:07:17.910988 Starting [0;1;39mUser Login Management[0m...
11030 11:07:17.928496 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11031 11:07:17.945410 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11032 11:07:17.961464 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11033 11:07:17.999606 Starting [0;1;39mPermit User Sessions[0m...
11034 11:07:18.120192 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11035 11:07:18.171721 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11036 11:07:18.189033 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11037 11:07:18.210879 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11038 11:07:18.232397 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11039 11:07:18.267065 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11040 11:07:18.288717 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11041 11:07:18.307536 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11042 11:07:18.353780 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11043 11:07:18.403245 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11044 11:07:18.472848
11045 11:07:18.473060
11046 11:07:18.476082 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11047 11:07:18.476226
11048 11:07:18.505014 debian-bullseye-arm64 login: root (automatic login)
11049 11:07:18.505137
11050 11:07:18.505217
11051 11:07:18.888539 Linux debian-bullseye-arm64 6.1.80-cip16 #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024 aarch64
11052 11:07:18.888690
11053 11:07:18.894736 The programs included with the Debian GNU/Linux system are free software;
11054 11:07:18.902088 the exact distribution terms for each program are described in the
11055 11:07:18.905296 individual files in /usr/share/doc/*/copyright.
11056 11:07:18.905428
11057 11:07:18.911409 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11058 11:07:18.914883 permitted by applicable law.
11059 11:07:19.812233 Matched prompt #10: / #
11061 11:07:19.812615 Setting prompt string to ['/ #']
11062 11:07:19.812753 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11064 11:07:19.813060 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11065 11:07:19.813192 start: 2.2.6 expect-shell-connection (timeout 00:03:16) [common]
11066 11:07:19.813301 Setting prompt string to ['/ #']
11067 11:07:19.813396 Forcing a shell prompt, looking for ['/ #']
11069 11:07:19.863725 / #
11070 11:07:19.863900 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11071 11:07:19.864010 Waiting using forced prompt support (timeout 00:02:30)
11072 11:07:19.869302
11073 11:07:19.869584 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11074 11:07:19.869694 start: 2.2.7 export-device-env (timeout 00:03:16) [common]
11076 11:07:19.970055 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12925640/extract-nfsrootfs-966tkp70'
11077 11:07:19.976333 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12925640/extract-nfsrootfs-966tkp70'
11079 11:07:20.076890 / # export NFS_SERVER_IP='192.168.201.1'
11080 11:07:20.083564 export NFS_SERVER_IP='192.168.201.1'
11081 11:07:20.083861 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11082 11:07:20.083975 end: 2.2 depthcharge-retry (duration 00:01:44) [common]
11083 11:07:20.084082 end: 2 depthcharge-action (duration 00:01:44) [common]
11084 11:07:20.084189 start: 3 lava-test-retry (timeout 00:07:29) [common]
11085 11:07:20.084293 start: 3.1 lava-test-shell (timeout 00:07:29) [common]
11086 11:07:20.084384 Using namespace: common
11088 11:07:20.184725 / # #
11089 11:07:20.184962 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11090 11:07:20.190157 #
11091 11:07:20.190463 Using /lava-12925640
11093 11:07:20.290844 / # export SHELL=/bin/bash
11094 11:07:20.296221 export SHELL=/bin/bash
11096 11:07:20.396870 / # . /lava-12925640/environment
11097 11:07:20.402512 . /lava-12925640/environment
11099 11:07:20.509100 / # /lava-12925640/bin/lava-test-runner /lava-12925640/0
11100 11:07:20.509282 Test shell timeout: 10s (minimum of the action and connection timeout)
11101 11:07:20.514730 /lava-12925640/bin/lava-test-runner /lava-12925640/0
11102 11:07:20.829642 + export TESTRUN_ID=0_timesync-off
11103 11:07:20.832319 + TESTRUN_ID=0_timesync-off
11104 11:07:20.836024 + cd /lava-12925640/0/tests/0_timesync-off
11105 11:07:20.838702 ++ cat uuid
11106 11:07:20.845927 + UUID=12925640_1.6.2.3.1
11107 11:07:20.846036 + set +x
11108 11:07:20.852608 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12925640_1.6.2.3.1>
11109 11:07:20.852880 Received signal: <STARTRUN> 0_timesync-off 12925640_1.6.2.3.1
11110 11:07:20.852991 Starting test lava.0_timesync-off (12925640_1.6.2.3.1)
11111 11:07:20.853106 Skipping test definition patterns.
11112 11:07:20.856126 + systemctl stop systemd-timesyncd
11113 11:07:20.924975 + set +x
11114 11:07:20.928244 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12925640_1.6.2.3.1>
11115 11:07:20.928554 Received signal: <ENDRUN> 0_timesync-off 12925640_1.6.2.3.1
11116 11:07:20.928643 Ending use of test pattern.
11117 11:07:20.928707 Ending test lava.0_timesync-off (12925640_1.6.2.3.1), duration 0.08
11119 11:07:21.020760 + export TESTRUN_ID=1_kselftest-dt
11120 11:07:21.023736 + TESTRUN_ID=1_kselftest-dt
11121 11:07:21.027003 + cd /lava-12925640/0/tests/1_kselftest-dt
11122 11:07:21.029898 ++ cat uuid
11123 11:07:21.037856 + UUID=12925640_1.6.2.3.5
11124 11:07:21.037945 + set +x
11125 11:07:21.043913 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 12925640_1.6.2.3.5>
11126 11:07:21.044189 Received signal: <STARTRUN> 1_kselftest-dt 12925640_1.6.2.3.5
11127 11:07:21.044267 Starting test lava.1_kselftest-dt (12925640_1.6.2.3.5)
11128 11:07:21.044407 Skipping test definition patterns.
11129 11:07:21.047695 + cd ./automated/linux/kselftest/
11130 11:07:21.070789 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11131 11:07:21.123091 INFO: install_deps skipped
11132 11:07:21.258958 --2024-03-03 11:07:21-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11133 11:07:21.271346 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11134 11:07:21.405756 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11135 11:07:21.539701 HTTP request sent, awaiting response... 200 OK
11136 11:07:21.543090 Length: 1746012 (1.7M) [application/octet-stream]
11137 11:07:21.546384 Saving to: 'kselftest.tar.xz'
11138 11:07:21.546482
11139 11:07:21.546548
11140 11:07:21.807089 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11141 11:07:22.074276 kselftest.tar.xz 2%[ ] 47.81K 180KB/s
11142 11:07:22.610886 kselftest.tar.xz 12%[=> ] 217.50K 408KB/s
11143 11:07:22.617064 kselftest.tar.xz 49%[========> ] 838.27K 784KB/s
11144 11:07:22.623727 kselftest.tar.xz 100%[===================>] 1.67M 1.54MB/s in 1.1s
11145 11:07:22.623855
11146 11:07:22.780205 2024-03-03 11:07:22 (1.54 MB/s) - 'kselftest.tar.xz' saved [1746012/1746012]
11147 11:07:22.780417
11148 11:07:28.110164 skiplist:
11149 11:07:28.113714 ========================================
11150 11:07:28.116822 ========================================
11151 11:07:28.195945 ============== Tests to run ===============
11152 11:07:28.202700 ===========End Tests to run ===============
11153 11:07:28.209120 shardfile-dt fail
11154 11:07:28.233601 ./kselftest.sh: 131: cannot open /lava-12925640/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11155 11:07:28.237103 + ../../utils/send-to-lava.sh ./output/result.txt
11156 11:07:28.313041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11157 11:07:28.313260 + set +x
11158 11:07:28.313577 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11160 11:07:28.320526 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 12925640_1.6.2.3.5>
11161 11:07:28.320675 <LAVA_TEST_RUNNER EXIT>
11162 11:07:28.320972 Received signal: <ENDRUN> 1_kselftest-dt 12925640_1.6.2.3.5
11163 11:07:28.321095 Ending use of test pattern.
11164 11:07:28.321207 Ending test lava.1_kselftest-dt (12925640_1.6.2.3.5), duration 7.28
11166 11:07:28.321615 ok: lava_test_shell seems to have completed
11167 11:07:28.321775 shardfile-dt: fail
11168 11:07:28.321923 end: 3.1 lava-test-shell (duration 00:00:08) [common]
11169 11:07:28.322067 end: 3 lava-test-retry (duration 00:00:08) [common]
11170 11:07:28.322210 start: 4 finalize (timeout 00:07:21) [common]
11171 11:07:28.322366 start: 4.1 power-off (timeout 00:00:30) [common]
11172 11:07:28.322651 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11173 11:07:28.408123 >> Command sent successfully.
11174 11:07:28.411551 Returned 0 in 0 seconds
11175 11:07:28.512006 end: 4.1 power-off (duration 00:00:00) [common]
11177 11:07:28.512345 start: 4.2 read-feedback (timeout 00:07:20) [common]
11178 11:07:28.512628 Listened to connection for namespace 'common' for up to 1s
11179 11:07:28.512918 Listened to connection for namespace 'common' for up to 1s
11180 11:07:29.513571 Finalising connection for namespace 'common'
11181 11:07:29.513759 Disconnecting from shell: Finalise
11182 11:07:29.513841 / #
11183 11:07:29.614184 end: 4.2 read-feedback (duration 00:00:01) [common]
11184 11:07:29.614367 end: 4 finalize (duration 00:00:01) [common]
11185 11:07:29.614500 Cleaning after the job
11186 11:07:29.614605 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925640/tftp-deploy-4frbx01r/ramdisk
11187 11:07:29.617443 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925640/tftp-deploy-4frbx01r/kernel
11188 11:07:29.630129 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925640/tftp-deploy-4frbx01r/dtb
11189 11:07:29.630369 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925640/tftp-deploy-4frbx01r/nfsrootfs
11190 11:07:29.719926 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925640/tftp-deploy-4frbx01r/modules
11191 11:07:29.727357 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12925640
11192 11:07:30.375565 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12925640
11193 11:07:30.375756 Job finished correctly