Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 38
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 17
1 11:04:07.893195 lava-dispatcher, installed at version: 2024.01
2 11:04:07.893426 start: 0 validate
3 11:04:07.893607 Start time: 2024-03-03 11:04:07.893599+00:00 (UTC)
4 11:04:07.893745 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:04:07.893881 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20240129.0%2Farm64%2Finitrd.cpio.gz exists
6 11:04:08.161744 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:04:08.162241 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:04:40.743361 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:04:40.744106 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:04:41.013866 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:04:41.014554 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20240129.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:04:41.545270 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:04:41.545985 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:04:43.556672 validate duration: 35.66
16 11:04:43.556932 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:04:43.557027 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:04:43.557111 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:04:43.557240 Not decompressing ramdisk as can be used compressed.
20 11:04:43.557323 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20240129.0/arm64/initrd.cpio.gz
21 11:04:43.557387 saving as /var/lib/lava/dispatcher/tmp/12925624/tftp-deploy-7i8qwhg8/ramdisk/initrd.cpio.gz
22 11:04:43.557453 total size: 4663047 (4 MB)
23 11:04:43.823176 progress 0 % (0 MB)
24 11:04:43.825445 progress 5 % (0 MB)
25 11:04:43.827502 progress 10 % (0 MB)
26 11:04:43.829464 progress 15 % (0 MB)
27 11:04:43.831487 progress 20 % (0 MB)
28 11:04:43.833445 progress 25 % (1 MB)
29 11:04:43.835535 progress 30 % (1 MB)
30 11:04:43.837626 progress 35 % (1 MB)
31 11:04:43.839538 progress 40 % (1 MB)
32 11:04:43.841908 progress 45 % (2 MB)
33 11:04:43.843900 progress 50 % (2 MB)
34 11:04:43.845872 progress 55 % (2 MB)
35 11:04:43.847839 progress 60 % (2 MB)
36 11:04:43.849828 progress 65 % (2 MB)
37 11:04:43.851841 progress 70 % (3 MB)
38 11:04:43.853798 progress 75 % (3 MB)
39 11:04:43.855790 progress 80 % (3 MB)
40 11:04:43.857806 progress 85 % (3 MB)
41 11:04:43.860038 progress 90 % (4 MB)
42 11:04:43.862055 progress 95 % (4 MB)
43 11:04:43.863976 progress 100 % (4 MB)
44 11:04:43.864186 4 MB downloaded in 0.31 s (14.50 MB/s)
45 11:04:43.864405 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:04:43.864820 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:04:43.864945 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:04:43.865074 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:04:43.865261 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:04:43.865368 saving as /var/lib/lava/dispatcher/tmp/12925624/tftp-deploy-7i8qwhg8/kernel/Image
52 11:04:43.865460 total size: 51599872 (49 MB)
53 11:04:43.865565 No compression specified
54 11:04:43.867081 progress 0 % (0 MB)
55 11:04:43.887304 progress 5 % (2 MB)
56 11:04:43.900787 progress 10 % (4 MB)
57 11:04:43.914242 progress 15 % (7 MB)
58 11:04:43.927623 progress 20 % (9 MB)
59 11:04:43.940958 progress 25 % (12 MB)
60 11:04:43.954519 progress 30 % (14 MB)
61 11:04:43.968039 progress 35 % (17 MB)
62 11:04:43.981482 progress 40 % (19 MB)
63 11:04:43.995221 progress 45 % (22 MB)
64 11:04:44.008855 progress 50 % (24 MB)
65 11:04:44.022463 progress 55 % (27 MB)
66 11:04:44.035742 progress 60 % (29 MB)
67 11:04:44.049147 progress 65 % (32 MB)
68 11:04:44.062642 progress 70 % (34 MB)
69 11:04:44.076023 progress 75 % (36 MB)
70 11:04:44.089342 progress 80 % (39 MB)
71 11:04:44.103277 progress 85 % (41 MB)
72 11:04:44.117088 progress 90 % (44 MB)
73 11:04:44.130213 progress 95 % (46 MB)
74 11:04:44.143419 progress 100 % (49 MB)
75 11:04:44.143698 49 MB downloaded in 0.28 s (176.86 MB/s)
76 11:04:44.143851 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:04:44.144089 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:04:44.144179 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:04:44.144268 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:04:44.144414 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:04:44.144484 saving as /var/lib/lava/dispatcher/tmp/12925624/tftp-deploy-7i8qwhg8/dtb/mt8192-asurada-spherion-r0.dtb
83 11:04:44.144547 total size: 47278 (0 MB)
84 11:04:44.144609 No compression specified
85 11:04:44.145740 progress 69 % (0 MB)
86 11:04:44.146015 progress 100 % (0 MB)
87 11:04:44.146172 0 MB downloaded in 0.00 s (27.78 MB/s)
88 11:04:44.146295 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:04:44.146517 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:04:44.146604 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:04:44.146687 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:04:44.146803 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20240129.0/arm64/full.rootfs.tar.xz
94 11:04:44.146871 saving as /var/lib/lava/dispatcher/tmp/12925624/tftp-deploy-7i8qwhg8/nfsrootfs/full.rootfs.tar
95 11:04:44.146933 total size: 200856304 (191 MB)
96 11:04:44.146994 Using unxz to decompress xz
97 11:04:44.151459 progress 0 % (0 MB)
98 11:04:44.690146 progress 5 % (9 MB)
99 11:04:45.224670 progress 10 % (19 MB)
100 11:04:45.836593 progress 15 % (28 MB)
101 11:04:46.219273 progress 20 % (38 MB)
102 11:04:46.549893 progress 25 % (47 MB)
103 11:04:47.167756 progress 30 % (57 MB)
104 11:04:47.753930 progress 35 % (67 MB)
105 11:04:48.362850 progress 40 % (76 MB)
106 11:04:48.955564 progress 45 % (86 MB)
107 11:04:49.560935 progress 50 % (95 MB)
108 11:04:50.207042 progress 55 % (105 MB)
109 11:04:50.884175 progress 60 % (114 MB)
110 11:04:51.003459 progress 65 % (124 MB)
111 11:04:51.143462 progress 70 % (134 MB)
112 11:04:51.239497 progress 75 % (143 MB)
113 11:04:51.311750 progress 80 % (153 MB)
114 11:04:51.389776 progress 85 % (162 MB)
115 11:04:51.489310 progress 90 % (172 MB)
116 11:04:51.785953 progress 95 % (182 MB)
117 11:04:52.381270 progress 100 % (191 MB)
118 11:04:52.387425 191 MB downloaded in 8.24 s (23.25 MB/s)
119 11:04:52.387830 end: 1.4.1 http-download (duration 00:00:08) [common]
121 11:04:52.388248 end: 1.4 download-retry (duration 00:00:08) [common]
122 11:04:52.388406 start: 1.5 download-retry (timeout 00:09:51) [common]
123 11:04:52.388553 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 11:04:52.388774 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:04:52.388879 saving as /var/lib/lava/dispatcher/tmp/12925624/tftp-deploy-7i8qwhg8/modules/modules.tar
126 11:04:52.388975 total size: 8628476 (8 MB)
127 11:04:52.389075 Using unxz to decompress xz
128 11:04:52.659323 progress 0 % (0 MB)
129 11:04:52.680336 progress 5 % (0 MB)
130 11:04:52.705406 progress 10 % (0 MB)
131 11:04:52.730398 progress 15 % (1 MB)
132 11:04:52.754300 progress 20 % (1 MB)
133 11:04:52.779699 progress 25 % (2 MB)
134 11:04:52.804683 progress 30 % (2 MB)
135 11:04:52.834008 progress 35 % (2 MB)
136 11:04:52.860615 progress 40 % (3 MB)
137 11:04:52.886248 progress 45 % (3 MB)
138 11:04:52.911911 progress 50 % (4 MB)
139 11:04:52.938359 progress 55 % (4 MB)
140 11:04:52.962588 progress 60 % (4 MB)
141 11:04:52.989903 progress 65 % (5 MB)
142 11:04:53.016266 progress 70 % (5 MB)
143 11:04:53.042263 progress 75 % (6 MB)
144 11:04:53.069908 progress 80 % (6 MB)
145 11:04:53.096383 progress 85 % (7 MB)
146 11:04:53.123521 progress 90 % (7 MB)
147 11:04:53.156173 progress 95 % (7 MB)
148 11:04:53.187017 progress 100 % (8 MB)
149 11:04:53.192393 8 MB downloaded in 0.80 s (10.24 MB/s)
150 11:04:53.192745 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:04:53.193151 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:04:53.193276 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 11:04:53.193405 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 11:04:56.834150 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12925624/extract-nfsrootfs-beawcsqf
156 11:04:56.834375 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:04:56.834478 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 11:04:56.834656 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz
159 11:04:56.834788 makedir: /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin
160 11:04:56.834950 makedir: /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/tests
161 11:04:56.835086 makedir: /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/results
162 11:04:56.835194 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-add-keys
163 11:04:56.835346 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-add-sources
164 11:04:56.835494 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-background-process-start
165 11:04:56.835626 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-background-process-stop
166 11:04:56.835756 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-common-functions
167 11:04:56.835887 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-echo-ipv4
168 11:04:56.836014 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-install-packages
169 11:04:56.836143 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-installed-packages
170 11:04:56.836267 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-os-build
171 11:04:56.836391 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-probe-channel
172 11:04:56.836516 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-probe-ip
173 11:04:56.836641 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-target-ip
174 11:04:56.836764 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-target-mac
175 11:04:56.836907 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-target-storage
176 11:04:56.837034 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-test-case
177 11:04:56.837160 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-test-event
178 11:04:56.837283 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-test-feedback
179 11:04:56.837408 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-test-raise
180 11:04:56.837572 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-test-reference
181 11:04:56.837703 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-test-runner
182 11:04:56.837829 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-test-set
183 11:04:56.837953 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-test-shell
184 11:04:56.838082 Updating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-add-keys (debian)
185 11:04:56.838244 Updating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-add-sources (debian)
186 11:04:56.838397 Updating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-install-packages (debian)
187 11:04:56.838541 Updating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-installed-packages (debian)
188 11:04:56.838680 Updating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/bin/lava-os-build (debian)
189 11:04:56.838803 Creating /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/environment
190 11:04:56.838919 LAVA metadata
191 11:04:56.838993 - LAVA_JOB_ID=12925624
192 11:04:56.839057 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:04:56.839167 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 11:04:56.839234 skipped lava-vland-overlay
195 11:04:56.839309 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:04:56.839387 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 11:04:56.839447 skipped lava-multinode-overlay
198 11:04:56.839530 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:04:56.839608 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 11:04:56.839683 Loading test definitions
201 11:04:56.839768 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 11:04:56.839839 Using /lava-12925624 at stage 0
203 11:04:56.840136 uuid=12925624_1.6.2.3.1 testdef=None
204 11:04:56.840223 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:04:56.840308 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 11:04:56.840763 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:04:56.840978 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 11:04:56.841585 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:04:56.841814 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 11:04:56.842353 runner path: /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/0/tests/0_timesync-off test_uuid 12925624_1.6.2.3.1
213 11:04:56.842513 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:04:56.842735 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 11:04:56.842807 Using /lava-12925624 at stage 0
217 11:04:56.842905 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:04:56.842991 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/0/tests/1_kselftest-rtc'
219 11:05:01.953335 Running '/usr/bin/git checkout kernelci.org
220 11:05:02.103950 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 11:05:02.104712 uuid=12925624_1.6.2.3.5 testdef=None
222 11:05:02.104873 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 11:05:02.105120 start: 1.6.2.3.6 test-overlay (timeout 00:09:41) [common]
225 11:05:02.105995 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:05:02.106223 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:41) [common]
228 11:05:02.107196 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:05:02.107478 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:41) [common]
231 11:05:02.108402 runner path: /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/0/tests/1_kselftest-rtc test_uuid 12925624_1.6.2.3.5
232 11:05:02.108491 BOARD='mt8192-asurada-spherion-r0'
233 11:05:02.108555 BRANCH='cip'
234 11:05:02.108614 SKIPFILE='/dev/null'
235 11:05:02.108671 SKIP_INSTALL='True'
236 11:05:02.108726 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:05:02.108785 TST_CASENAME=''
238 11:05:02.108839 TST_CMDFILES='rtc'
239 11:05:02.108979 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:05:02.109182 Creating lava-test-runner.conf files
242 11:05:02.109246 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12925624/lava-overlay-jpa68pvz/lava-12925624/0 for stage 0
243 11:05:02.109354 - 0_timesync-off
244 11:05:02.109488 - 1_kselftest-rtc
245 11:05:02.109614 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 11:05:02.109750 start: 1.6.2.4 compress-overlay (timeout 00:09:41) [common]
247 11:05:09.675454 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:05:09.675600 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:34) [common]
249 11:05:09.675691 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:05:09.675789 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 11:05:09.675879 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
252 11:05:09.797366 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:05:09.797810 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
254 11:05:09.797921 extracting modules file /var/lib/lava/dispatcher/tmp/12925624/tftp-deploy-7i8qwhg8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925624/extract-nfsrootfs-beawcsqf
255 11:05:10.021427 extracting modules file /var/lib/lava/dispatcher/tmp/12925624/tftp-deploy-7i8qwhg8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925624/extract-overlay-ramdisk-rj01u9d0/ramdisk
256 11:05:10.260873 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:05:10.261032 start: 1.6.5 apply-overlay-tftp (timeout 00:09:33) [common]
258 11:05:10.261122 [common] Applying overlay to NFS
259 11:05:10.261193 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925624/compress-overlay-rcez1xmc/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12925624/extract-nfsrootfs-beawcsqf
260 11:05:11.184214 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:05:11.184417 start: 1.6.6 configure-preseed-file (timeout 00:09:32) [common]
262 11:05:11.184514 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:05:11.184604 start: 1.6.7 compress-ramdisk (timeout 00:09:32) [common]
264 11:05:11.184686 Building ramdisk /var/lib/lava/dispatcher/tmp/12925624/extract-overlay-ramdisk-rj01u9d0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12925624/extract-overlay-ramdisk-rj01u9d0/ramdisk
265 11:05:11.521466 >> 119441 blocks
266 11:05:13.449363 rename /var/lib/lava/dispatcher/tmp/12925624/extract-overlay-ramdisk-rj01u9d0/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12925624/tftp-deploy-7i8qwhg8/ramdisk/ramdisk.cpio.gz
267 11:05:13.449874 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:05:13.450002 start: 1.6.8 prepare-kernel (timeout 00:09:30) [common]
269 11:05:13.450099 start: 1.6.8.1 prepare-fit (timeout 00:09:30) [common]
270 11:05:13.450205 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12925624/tftp-deploy-7i8qwhg8/kernel/Image'
271 11:05:26.522382 Returned 0 in 13 seconds
272 11:05:26.623015 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12925624/tftp-deploy-7i8qwhg8/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12925624/tftp-deploy-7i8qwhg8/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12925624/tftp-deploy-7i8qwhg8/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12925624/tftp-deploy-7i8qwhg8/kernel/image.itb
273 11:05:26.990888 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:05:26.991286 output: Created: Sun Mar 3 11:05:26 2024
275 11:05:26.991363 output: Image 0 (kernel-1)
276 11:05:26.991429 output: Description:
277 11:05:26.991495 output: Created: Sun Mar 3 11:05:26 2024
278 11:05:26.991559 output: Type: Kernel Image
279 11:05:26.991619 output: Compression: lzma compressed
280 11:05:26.991683 output: Data Size: 12057697 Bytes = 11775.09 KiB = 11.50 MiB
281 11:05:26.991744 output: Architecture: AArch64
282 11:05:26.991804 output: OS: Linux
283 11:05:26.991863 output: Load Address: 0x00000000
284 11:05:26.991922 output: Entry Point: 0x00000000
285 11:05:26.991991 output: Hash algo: crc32
286 11:05:26.992051 output: Hash value: cf43f4f3
287 11:05:26.992105 output: Image 1 (fdt-1)
288 11:05:26.992160 output: Description: mt8192-asurada-spherion-r0
289 11:05:26.992218 output: Created: Sun Mar 3 11:05:26 2024
290 11:05:26.992272 output: Type: Flat Device Tree
291 11:05:26.992327 output: Compression: uncompressed
292 11:05:26.992379 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 11:05:26.992433 output: Architecture: AArch64
294 11:05:26.992487 output: Hash algo: crc32
295 11:05:26.992540 output: Hash value: cc4352de
296 11:05:26.992593 output: Image 2 (ramdisk-1)
297 11:05:26.992646 output: Description: unavailable
298 11:05:26.992702 output: Created: Sun Mar 3 11:05:26 2024
299 11:05:26.992756 output: Type: RAMDisk Image
300 11:05:26.992809 output: Compression: Unknown Compression
301 11:05:26.992862 output: Data Size: 17805938 Bytes = 17388.61 KiB = 16.98 MiB
302 11:05:26.992935 output: Architecture: AArch64
303 11:05:26.993033 output: OS: Linux
304 11:05:26.993126 output: Load Address: unavailable
305 11:05:26.993219 output: Entry Point: unavailable
306 11:05:26.993315 output: Hash algo: crc32
307 11:05:26.993409 output: Hash value: 53fd1cf4
308 11:05:26.993510 output: Default Configuration: 'conf-1'
309 11:05:26.993605 output: Configuration 0 (conf-1)
310 11:05:26.993698 output: Description: mt8192-asurada-spherion-r0
311 11:05:26.993792 output: Kernel: kernel-1
312 11:05:26.993890 output: Init Ramdisk: ramdisk-1
313 11:05:26.993988 output: FDT: fdt-1
314 11:05:26.994081 output: Loadables: kernel-1
315 11:05:26.994175 output:
316 11:05:26.994447 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 11:05:26.994594 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 11:05:26.994747 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 11:05:26.994885 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:17) [common]
320 11:05:26.994987 No LXC device requested
321 11:05:26.995087 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:05:26.995203 start: 1.8 deploy-device-env (timeout 00:09:17) [common]
323 11:05:26.995298 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:05:26.995401 Checking files for TFTP limit of 4294967296 bytes.
325 11:05:26.996082 end: 1 tftp-deploy (duration 00:00:43) [common]
326 11:05:26.996222 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:05:26.996350 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:05:26.996528 substitutions:
329 11:05:26.996621 - {DTB}: 12925624/tftp-deploy-7i8qwhg8/dtb/mt8192-asurada-spherion-r0.dtb
330 11:05:26.996720 - {INITRD}: 12925624/tftp-deploy-7i8qwhg8/ramdisk/ramdisk.cpio.gz
331 11:05:26.996810 - {KERNEL}: 12925624/tftp-deploy-7i8qwhg8/kernel/Image
332 11:05:26.996899 - {LAVA_MAC}: None
333 11:05:26.996987 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12925624/extract-nfsrootfs-beawcsqf
334 11:05:26.997074 - {NFS_SERVER_IP}: 192.168.201.1
335 11:05:26.997159 - {PRESEED_CONFIG}: None
336 11:05:26.997249 - {PRESEED_LOCAL}: None
337 11:05:26.997335 - {RAMDISK}: 12925624/tftp-deploy-7i8qwhg8/ramdisk/ramdisk.cpio.gz
338 11:05:26.997421 - {ROOT_PART}: None
339 11:05:26.997508 - {ROOT}: None
340 11:05:26.997566 - {SERVER_IP}: 192.168.201.1
341 11:05:26.997621 - {TEE}: None
342 11:05:26.997675 Parsed boot commands:
343 11:05:26.997728 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:05:26.997917 Parsed boot commands: tftpboot 192.168.201.1 12925624/tftp-deploy-7i8qwhg8/kernel/image.itb 12925624/tftp-deploy-7i8qwhg8/kernel/cmdline
345 11:05:26.998018 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:05:26.998104 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:05:26.998198 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:05:26.998289 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:05:26.998366 Not connected, no need to disconnect.
350 11:05:26.998442 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:05:26.998526 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:05:26.998597 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 11:05:27.002787 Setting prompt string to ['lava-test: # ']
354 11:05:27.003186 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:05:27.003299 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:05:27.003401 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:05:27.003495 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:05:27.003740 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 11:05:32.139709 >> Command sent successfully.
360 11:05:32.142483 Returned 0 in 5 seconds
361 11:05:32.242888 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:05:32.243372 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:05:32.243517 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:05:32.243643 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:05:32.243724 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:05:32.243892 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:05:32.244390 [Enter `^Ec?' for help]
369 11:05:32.415764
370 11:05:32.415928
371 11:05:32.416044 F0: 102B 0000
372 11:05:32.416151
373 11:05:32.416262 F3: 1001 0000 [0200]
374 11:05:32.416357
375 11:05:32.419346 F3: 1001 0000
376 11:05:32.419428
377 11:05:32.419531 F7: 102D 0000
378 11:05:32.419637
379 11:05:32.419732 F1: 0000 0000
380 11:05:32.419823
381 11:05:32.422770 V0: 0000 0000 [0001]
382 11:05:32.422879
383 11:05:32.422984 00: 0007 8000
384 11:05:32.423083
385 11:05:32.426534 01: 0000 0000
386 11:05:32.426617
387 11:05:32.426684 BP: 0C00 0209 [0000]
388 11:05:32.426747
389 11:05:32.430111 G0: 1182 0000
390 11:05:32.430195
391 11:05:32.430263 EC: 0000 0021 [4000]
392 11:05:32.430326
393 11:05:32.433390 S7: 0000 0000 [0000]
394 11:05:32.433524
395 11:05:32.433631 CC: 0000 0000 [0001]
396 11:05:32.433719
397 11:05:32.436942 T0: 0000 0040 [010F]
398 11:05:32.437031
399 11:05:32.437100 Jump to BL
400 11:05:32.437164
401 11:05:32.462332
402 11:05:32.462446
403 11:05:32.462545
404 11:05:32.470163 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:05:32.474020 ARM64: Exception handlers installed.
406 11:05:32.477662 ARM64: Testing exception
407 11:05:32.477748 ARM64: Done test exception
408 11:05:32.485082 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:05:32.496292 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:05:32.503366 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:05:32.513100 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:05:32.519843 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:05:32.529997 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:05:32.540334 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:05:32.547074 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:05:32.565239 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:05:32.568429 WDT: Last reset was cold boot
418 11:05:32.571894 SPI1(PAD0) initialized at 2873684 Hz
419 11:05:32.574969 SPI5(PAD0) initialized at 992727 Hz
420 11:05:32.578443 VBOOT: Loading verstage.
421 11:05:32.585080 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:05:32.588633 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:05:32.591923 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:05:32.595050 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:05:32.602590 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:05:32.608834 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:05:32.619876 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 11:05:32.619961
429 11:05:32.620028
430 11:05:32.629789 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:05:32.633319 ARM64: Exception handlers installed.
432 11:05:32.636392 ARM64: Testing exception
433 11:05:32.636476 ARM64: Done test exception
434 11:05:32.643750 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:05:32.647064 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:05:32.660972 Probing TPM: . done!
437 11:05:32.661058 TPM ready after 0 ms
438 11:05:32.667562 Connected to device vid:did:rid of 1ae0:0028:00
439 11:05:32.675002 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 11:05:32.714440 Initialized TPM device CR50 revision 0
441 11:05:32.726605 tlcl_send_startup: Startup return code is 0
442 11:05:32.726694 TPM: setup succeeded
443 11:05:32.738023 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:05:32.746854 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:05:32.758334 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:05:32.768381 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:05:32.771601 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:05:32.775498 in-header: 03 07 00 00 08 00 00 00
449 11:05:32.779165 in-data: aa e4 47 04 13 02 00 00
450 11:05:32.782581 Chrome EC: UHEPI supported
451 11:05:32.789240 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:05:32.793342 in-header: 03 9d 00 00 08 00 00 00
453 11:05:32.796919 in-data: 10 20 20 08 00 00 00 00
454 11:05:32.797003 Phase 1
455 11:05:32.804108 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:05:32.807983 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:05:32.815202 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:05:32.815287 Recovery requested (1009000e)
459 11:05:32.824316 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:05:32.829843 tlcl_extend: response is 0
461 11:05:32.837908 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:05:32.842988 tlcl_extend: response is 0
463 11:05:32.849667 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:05:32.871068 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 11:05:32.878335 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:05:32.878421
467 11:05:32.878488
468 11:05:32.885675 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:05:32.889580 ARM64: Exception handlers installed.
470 11:05:32.893254 ARM64: Testing exception
471 11:05:32.896409 ARM64: Done test exception
472 11:05:32.912903 pmic_efuse_setting: Set efuses in 11 msecs
473 11:05:32.921618 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:05:32.925583 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:05:32.929146 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:05:32.936714 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:05:32.940237 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:05:32.943887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:05:32.951224 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:05:32.957647 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:05:32.958618 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:05:32.961687 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:05:32.968351 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:05:32.971872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:05:32.978301 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:05:32.981759 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:05:32.988295 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:05:32.995163 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:05:32.998323 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:05:33.004985 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:05:33.011559 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:05:33.015487 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:05:33.022394 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:05:33.029299 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:05:33.033034 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:05:33.039858 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:05:33.043337 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:05:33.050284 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:05:33.056774 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:05:33.060047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:05:33.066647 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:05:33.069890 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:05:33.073877 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:05:33.081137 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:05:33.085099 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:05:33.088784 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:05:33.096319 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:05:33.100340 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:05:33.103629 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:05:33.110730 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:05:33.113974 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:05:33.120805 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:05:33.123955 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:05:33.127346 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:05:33.133985 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:05:33.137074 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:05:33.140551 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:05:33.147386 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:05:33.150893 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:05:33.153851 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:05:33.157374 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:05:33.164108 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:05:33.167354 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:05:33.170607 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:05:33.177310 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:05:33.187431 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:05:33.190755 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:05:33.200395 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:05:33.207051 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:05:33.213674 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:05:33.217075 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:05:33.220537 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:05:33.228577 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x16
534 11:05:33.235305 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:05:33.238339 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 11:05:33.244904 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:05:33.253020 [RTC]rtc_get_frequency_meter,154: input=15, output=794
538 11:05:33.256392 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 11:05:33.263218 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 11:05:33.266394 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 11:05:33.269960 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 11:05:33.272877 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 11:05:33.276462 ADC[4]: Raw value=894821 ID=7
544 11:05:33.279594 ADC[3]: Raw value=213810 ID=1
545 11:05:33.283176 RAM Code: 0x71
546 11:05:33.286522 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 11:05:33.289655 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 11:05:33.300379 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 11:05:33.306852 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 11:05:33.310210 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 11:05:33.313856 in-header: 03 07 00 00 08 00 00 00
552 11:05:33.317020 in-data: aa e4 47 04 13 02 00 00
553 11:05:33.320119 Chrome EC: UHEPI supported
554 11:05:33.323676 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 11:05:33.327637 in-header: 03 d5 00 00 08 00 00 00
556 11:05:33.331758 in-data: 98 20 60 08 00 00 00 00
557 11:05:33.335309 MRC: failed to locate region type 0.
558 11:05:33.342733 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 11:05:33.345987 DRAM-K: Running full calibration
560 11:05:33.352799 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 11:05:33.352915 header.status = 0x0
562 11:05:33.356186 header.version = 0x6 (expected: 0x6)
563 11:05:33.359863 header.size = 0xd00 (expected: 0xd00)
564 11:05:33.359947 header.flags = 0x0
565 11:05:33.366671 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 11:05:33.385202 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
567 11:05:33.391955 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 11:05:33.395156 dram_init: ddr_geometry: 2
569 11:05:33.398438 [EMI] MDL number = 2
570 11:05:33.398545 [EMI] Get MDL freq = 0
571 11:05:33.401942 dram_init: ddr_type: 0
572 11:05:33.402055 is_discrete_lpddr4: 1
573 11:05:33.404939 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 11:05:33.405046
575 11:05:33.405140
576 11:05:33.408540 [Bian_co] ETT version 0.0.0.1
577 11:05:33.415259 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 11:05:33.415369
579 11:05:33.418593 dramc_set_vcore_voltage set vcore to 650000
580 11:05:33.418697 Read voltage for 800, 4
581 11:05:33.421786 Vio18 = 0
582 11:05:33.421865 Vcore = 650000
583 11:05:33.421929 Vdram = 0
584 11:05:33.425173 Vddq = 0
585 11:05:33.425274 Vmddr = 0
586 11:05:33.428704 dram_init: config_dvfs: 1
587 11:05:33.431717 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 11:05:33.438326 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 11:05:33.441895 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 11:05:33.445242 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 11:05:33.448636 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 11:05:33.452175 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 11:05:33.455379 MEM_TYPE=3, freq_sel=18
594 11:05:33.458547 sv_algorithm_assistance_LP4_1600
595 11:05:33.462025 ============ PULL DRAM RESETB DOWN ============
596 11:05:33.465393 ========== PULL DRAM RESETB DOWN end =========
597 11:05:33.471941 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 11:05:33.475258 ===================================
599 11:05:33.478408 LPDDR4 DRAM CONFIGURATION
600 11:05:33.482036 ===================================
601 11:05:33.482138 EX_ROW_EN[0] = 0x0
602 11:05:33.485403 EX_ROW_EN[1] = 0x0
603 11:05:33.485499 LP4Y_EN = 0x0
604 11:05:33.488591 WORK_FSP = 0x0
605 11:05:33.488675 WL = 0x2
606 11:05:33.491756 RL = 0x2
607 11:05:33.491839 BL = 0x2
608 11:05:33.495312 RPST = 0x0
609 11:05:33.495395 RD_PRE = 0x0
610 11:05:33.498546 WR_PRE = 0x1
611 11:05:33.498630 WR_PST = 0x0
612 11:05:33.501935 DBI_WR = 0x0
613 11:05:33.502018 DBI_RD = 0x0
614 11:05:33.505012 OTF = 0x1
615 11:05:33.508486 ===================================
616 11:05:33.511754 ===================================
617 11:05:33.511838 ANA top config
618 11:05:33.515118 ===================================
619 11:05:33.518217 DLL_ASYNC_EN = 0
620 11:05:33.521501 ALL_SLAVE_EN = 1
621 11:05:33.524992 NEW_RANK_MODE = 1
622 11:05:33.525080 DLL_IDLE_MODE = 1
623 11:05:33.528494 LP45_APHY_COMB_EN = 1
624 11:05:33.531579 TX_ODT_DIS = 1
625 11:05:33.535183 NEW_8X_MODE = 1
626 11:05:33.538423 ===================================
627 11:05:33.541684 ===================================
628 11:05:33.544813 data_rate = 1600
629 11:05:33.544896 CKR = 1
630 11:05:33.548146 DQ_P2S_RATIO = 8
631 11:05:33.551800 ===================================
632 11:05:33.555140 CA_P2S_RATIO = 8
633 11:05:33.558703 DQ_CA_OPEN = 0
634 11:05:33.562147 DQ_SEMI_OPEN = 0
635 11:05:33.562231 CA_SEMI_OPEN = 0
636 11:05:33.565822 CA_FULL_RATE = 0
637 11:05:33.569296 DQ_CKDIV4_EN = 1
638 11:05:33.572858 CA_CKDIV4_EN = 1
639 11:05:33.572942 CA_PREDIV_EN = 0
640 11:05:33.576752 PH8_DLY = 0
641 11:05:33.580359 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 11:05:33.583849 DQ_AAMCK_DIV = 4
643 11:05:33.587852 CA_AAMCK_DIV = 4
644 11:05:33.587937 CA_ADMCK_DIV = 4
645 11:05:33.591213 DQ_TRACK_CA_EN = 0
646 11:05:33.595052 CA_PICK = 800
647 11:05:33.598681 CA_MCKIO = 800
648 11:05:33.598766 MCKIO_SEMI = 0
649 11:05:33.602377 PLL_FREQ = 3068
650 11:05:33.606126 DQ_UI_PI_RATIO = 32
651 11:05:33.609639 CA_UI_PI_RATIO = 0
652 11:05:33.613403 ===================================
653 11:05:33.613546 ===================================
654 11:05:33.617447 memory_type:LPDDR4
655 11:05:33.621092 GP_NUM : 10
656 11:05:33.621201 SRAM_EN : 1
657 11:05:33.624475 MD32_EN : 0
658 11:05:33.628300 ===================================
659 11:05:33.628412 [ANA_INIT] >>>>>>>>>>>>>>
660 11:05:33.632102 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 11:05:33.635854 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 11:05:33.639520 ===================================
663 11:05:33.643266 data_rate = 1600,PCW = 0X7600
664 11:05:33.643372 ===================================
665 11:05:33.646716 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 11:05:33.653231 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 11:05:33.660030 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 11:05:33.663109 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 11:05:33.666531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 11:05:33.670396 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 11:05:33.673885 [ANA_INIT] flow start
672 11:05:33.673963 [ANA_INIT] PLL >>>>>>>>
673 11:05:33.677458 [ANA_INIT] PLL <<<<<<<<
674 11:05:33.681296 [ANA_INIT] MIDPI >>>>>>>>
675 11:05:33.681404 [ANA_INIT] MIDPI <<<<<<<<
676 11:05:33.684699 [ANA_INIT] DLL >>>>>>>>
677 11:05:33.684801 [ANA_INIT] flow end
678 11:05:33.692400 ============ LP4 DIFF to SE enter ============
679 11:05:33.695963 ============ LP4 DIFF to SE exit ============
680 11:05:33.696071 [ANA_INIT] <<<<<<<<<<<<<
681 11:05:33.699623 [Flow] Enable top DCM control >>>>>
682 11:05:33.703408 [Flow] Enable top DCM control <<<<<
683 11:05:33.707306 Enable DLL master slave shuffle
684 11:05:33.710684 ==============================================================
685 11:05:33.714323 Gating Mode config
686 11:05:33.717731 ==============================================================
687 11:05:33.720871 Config description:
688 11:05:33.730957 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 11:05:33.737497 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 11:05:33.740665 SELPH_MODE 0: By rank 1: By Phase
691 11:05:33.747489 ==============================================================
692 11:05:33.750633 GAT_TRACK_EN = 1
693 11:05:33.754242 RX_GATING_MODE = 2
694 11:05:33.757311 RX_GATING_TRACK_MODE = 2
695 11:05:33.760759 SELPH_MODE = 1
696 11:05:33.764104 PICG_EARLY_EN = 1
697 11:05:33.764249 VALID_LAT_VALUE = 1
698 11:05:33.770877 ==============================================================
699 11:05:33.773954 Enter into Gating configuration >>>>
700 11:05:33.777460 Exit from Gating configuration <<<<
701 11:05:33.780684 Enter into DVFS_PRE_config >>>>>
702 11:05:33.790799 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 11:05:33.794106 Exit from DVFS_PRE_config <<<<<
704 11:05:33.797302 Enter into PICG configuration >>>>
705 11:05:33.800830 Exit from PICG configuration <<<<
706 11:05:33.804073 [RX_INPUT] configuration >>>>>
707 11:05:33.807501 [RX_INPUT] configuration <<<<<
708 11:05:33.810911 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 11:05:33.817571 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 11:05:33.824085 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 11:05:33.830967 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 11:05:33.837466 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 11:05:33.840937 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 11:05:33.847552 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 11:05:33.850675 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 11:05:33.854052 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 11:05:33.857400 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 11:05:33.864042 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 11:05:33.867392 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 11:05:33.870801 ===================================
721 11:05:33.873917 LPDDR4 DRAM CONFIGURATION
722 11:05:33.877324 ===================================
723 11:05:33.877434 EX_ROW_EN[0] = 0x0
724 11:05:33.880900 EX_ROW_EN[1] = 0x0
725 11:05:33.880983 LP4Y_EN = 0x0
726 11:05:33.884064 WORK_FSP = 0x0
727 11:05:33.884147 WL = 0x2
728 11:05:33.887313 RL = 0x2
729 11:05:33.887397 BL = 0x2
730 11:05:33.890786 RPST = 0x0
731 11:05:33.890870 RD_PRE = 0x0
732 11:05:33.894025 WR_PRE = 0x1
733 11:05:33.894109 WR_PST = 0x0
734 11:05:33.897496 DBI_WR = 0x0
735 11:05:33.900713 DBI_RD = 0x0
736 11:05:33.900796 OTF = 0x1
737 11:05:33.904144 ===================================
738 11:05:33.907197 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 11:05:33.910645 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 11:05:33.917411 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 11:05:33.920638 ===================================
742 11:05:33.920722 LPDDR4 DRAM CONFIGURATION
743 11:05:33.924153 ===================================
744 11:05:33.927327 EX_ROW_EN[0] = 0x10
745 11:05:33.930570 EX_ROW_EN[1] = 0x0
746 11:05:33.930653 LP4Y_EN = 0x0
747 11:05:33.933800 WORK_FSP = 0x0
748 11:05:33.933884 WL = 0x2
749 11:05:33.937159 RL = 0x2
750 11:05:33.937243 BL = 0x2
751 11:05:33.940629 RPST = 0x0
752 11:05:33.940713 RD_PRE = 0x0
753 11:05:33.944122 WR_PRE = 0x1
754 11:05:33.944206 WR_PST = 0x0
755 11:05:33.947115 DBI_WR = 0x0
756 11:05:33.947201 DBI_RD = 0x0
757 11:05:33.950398 OTF = 0x1
758 11:05:33.953957 ===================================
759 11:05:33.960383 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 11:05:33.963925 nWR fixed to 40
761 11:05:33.967293 [ModeRegInit_LP4] CH0 RK0
762 11:05:33.967377 [ModeRegInit_LP4] CH0 RK1
763 11:05:33.970365 [ModeRegInit_LP4] CH1 RK0
764 11:05:33.973702 [ModeRegInit_LP4] CH1 RK1
765 11:05:33.973812 match AC timing 13
766 11:05:33.980372 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 11:05:33.983939 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 11:05:33.987007 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 11:05:33.994027 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 11:05:33.997046 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 11:05:33.997129 [EMI DOE] emi_dcm 0
772 11:05:34.003794 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 11:05:34.003881 ==
774 11:05:34.007173 Dram Type= 6, Freq= 0, CH_0, rank 0
775 11:05:34.010478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 11:05:34.010562 ==
777 11:05:34.017085 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 11:05:34.020480 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 11:05:34.031293 [CA 0] Center 38 (7~69) winsize 63
780 11:05:34.035146 [CA 1] Center 37 (7~68) winsize 62
781 11:05:34.038961 [CA 2] Center 35 (5~66) winsize 62
782 11:05:34.042200 [CA 3] Center 35 (5~66) winsize 62
783 11:05:34.046200 [CA 4] Center 34 (4~65) winsize 62
784 11:05:34.049893 [CA 5] Center 34 (3~65) winsize 63
785 11:05:34.049977
786 11:05:34.053268 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 11:05:34.053352
788 11:05:34.057118 [CATrainingPosCal] consider 1 rank data
789 11:05:34.057202 u2DelayCellTimex100 = 270/100 ps
790 11:05:34.060727 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 11:05:34.068063 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 11:05:34.068149 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 11:05:34.075123 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 11:05:34.078800 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 11:05:34.082185 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
796 11:05:34.082269
797 11:05:34.086186 CA PerBit enable=1, Macro0, CA PI delay=34
798 11:05:34.086270
799 11:05:34.086336 [CBTSetCACLKResult] CA Dly = 34
800 11:05:34.089768 CS Dly: 6 (0~37)
801 11:05:34.089853 ==
802 11:05:34.093726 Dram Type= 6, Freq= 0, CH_0, rank 1
803 11:05:34.097261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 11:05:34.097371 ==
805 11:05:34.100788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 11:05:34.107416 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 11:05:34.118096 [CA 0] Center 38 (7~69) winsize 63
808 11:05:34.121499 [CA 1] Center 38 (7~69) winsize 63
809 11:05:34.125432 [CA 2] Center 35 (5~66) winsize 62
810 11:05:34.129343 [CA 3] Center 35 (5~66) winsize 62
811 11:05:34.132892 [CA 4] Center 34 (4~65) winsize 62
812 11:05:34.136291 [CA 5] Center 34 (4~65) winsize 62
813 11:05:34.136375
814 11:05:34.140183 [CmdBusTrainingLP45] Vref(ca) range 1: 34
815 11:05:34.140272
816 11:05:34.143774 [CATrainingPosCal] consider 2 rank data
817 11:05:34.143857 u2DelayCellTimex100 = 270/100 ps
818 11:05:34.147412 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 11:05:34.150933 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 11:05:34.154721 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 11:05:34.158461 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 11:05:34.162337 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 11:05:34.165548 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
824 11:05:34.165631
825 11:05:34.169410 CA PerBit enable=1, Macro0, CA PI delay=34
826 11:05:34.169532
827 11:05:34.172887 [CBTSetCACLKResult] CA Dly = 34
828 11:05:34.176996 CS Dly: 6 (0~37)
829 11:05:34.177079
830 11:05:34.180367 ----->DramcWriteLeveling(PI) begin...
831 11:05:34.180522 ==
832 11:05:34.183905 Dram Type= 6, Freq= 0, CH_0, rank 0
833 11:05:34.187687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 11:05:34.187772 ==
835 11:05:34.191394 Write leveling (Byte 0): 33 => 33
836 11:05:34.191479 Write leveling (Byte 1): 29 => 29
837 11:05:34.195304 DramcWriteLeveling(PI) end<-----
838 11:05:34.195388
839 11:05:34.195454 ==
840 11:05:34.198787 Dram Type= 6, Freq= 0, CH_0, rank 0
841 11:05:34.202569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 11:05:34.202653 ==
843 11:05:34.206362 [Gating] SW mode calibration
844 11:05:34.213554 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 11:05:34.217600 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 11:05:34.224646 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 11:05:34.228435 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 11:05:34.231869 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
849 11:05:34.235686 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 11:05:34.239706 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 11:05:34.247172 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 11:05:34.251029 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 11:05:34.254399 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 11:05:34.258025 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 11:05:34.261678 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:05:34.268911 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:05:34.272715 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:05:34.276150 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:05:34.279953 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:05:34.283604 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:05:34.290963 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:05:34.294393 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:05:34.298050 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:05:34.302044 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
865 11:05:34.305682 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
866 11:05:34.313048 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:05:34.316531 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:05:34.320500 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:05:34.323948 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:05:34.327689 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 11:05:34.335297 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 11:05:34.338867 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
873 11:05:34.342505 0 9 12 | B1->B0 | 2525 3232 | 1 0 | (0 0) (0 0)
874 11:05:34.345879 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 11:05:34.349744 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 11:05:34.356574 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 11:05:34.359546 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 11:05:34.363083 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 11:05:34.369735 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 11:05:34.373047 0 10 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
881 11:05:34.376426 0 10 12 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
882 11:05:34.382892 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 11:05:34.386315 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 11:05:34.389774 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 11:05:34.392945 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 11:05:34.399726 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 11:05:34.402948 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 11:05:34.406563 0 11 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
889 11:05:34.413234 0 11 12 | B1->B0 | 3636 3f3f | 0 0 | (0 0) (0 0)
890 11:05:34.416389 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 11:05:34.419762 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 11:05:34.426403 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 11:05:34.429815 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 11:05:34.432914 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 11:05:34.439633 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 11:05:34.443154 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
897 11:05:34.446282 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
898 11:05:34.453499 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 11:05:34.456403 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 11:05:34.459645 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 11:05:34.466351 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 11:05:34.469525 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 11:05:34.473127 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 11:05:34.479780 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:05:34.482844 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:05:34.486322 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:05:34.492879 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:05:34.496227 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:05:34.499696 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:05:34.502837 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:05:34.509433 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
912 11:05:34.512963 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:05:34.516161 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
914 11:05:34.519586 Total UI for P1: 0, mck2ui 16
915 11:05:34.522879 best dqsien dly found for B0: ( 0, 14, 10)
916 11:05:34.529726 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 11:05:34.529810 Total UI for P1: 0, mck2ui 16
918 11:05:34.536333 best dqsien dly found for B1: ( 0, 14, 14)
919 11:05:34.539633 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
920 11:05:34.543147 best DQS1 dly(MCK, UI, PI) = (0, 14, 14)
921 11:05:34.543288
922 11:05:34.546364 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
923 11:05:34.549413 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 14)
924 11:05:34.552858 [Gating] SW calibration Done
925 11:05:34.552967 ==
926 11:05:34.556523 Dram Type= 6, Freq= 0, CH_0, rank 0
927 11:05:34.559527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 11:05:34.559611 ==
929 11:05:34.563008 RX Vref Scan: 0
930 11:05:34.563090
931 11:05:34.563157 RX Vref 0 -> 0, step: 1
932 11:05:34.563219
933 11:05:34.566251 RX Delay -130 -> 252, step: 16
934 11:05:34.569822 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
935 11:05:34.576454 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
936 11:05:34.579482 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
937 11:05:34.582951 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
938 11:05:34.586333 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
939 11:05:34.589717 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
940 11:05:34.596178 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
941 11:05:34.599821 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
942 11:05:34.603026 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
943 11:05:34.606201 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
944 11:05:34.609573 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
945 11:05:34.616320 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
946 11:05:34.619702 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
947 11:05:34.622772 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
948 11:05:34.626136 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
949 11:05:34.632825 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
950 11:05:34.632909 ==
951 11:05:34.636356 Dram Type= 6, Freq= 0, CH_0, rank 0
952 11:05:34.639768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 11:05:34.639852 ==
954 11:05:34.639919 DQS Delay:
955 11:05:34.642989 DQS0 = 0, DQS1 = 0
956 11:05:34.643105 DQM Delay:
957 11:05:34.646108 DQM0 = 79, DQM1 = 69
958 11:05:34.646182 DQ Delay:
959 11:05:34.649637 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =77
960 11:05:34.652728 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
961 11:05:34.656296 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
962 11:05:34.659402 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
963 11:05:34.659479
964 11:05:34.659561
965 11:05:34.659627 ==
966 11:05:34.663457 Dram Type= 6, Freq= 0, CH_0, rank 0
967 11:05:34.666918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 11:05:34.667023 ==
969 11:05:34.667119
970 11:05:34.667208
971 11:05:34.670493 TX Vref Scan disable
972 11:05:34.670594 == TX Byte 0 ==
973 11:05:34.677101 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
974 11:05:34.680166 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
975 11:05:34.680249 == TX Byte 1 ==
976 11:05:34.686798 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
977 11:05:34.690045 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
978 11:05:34.690158 ==
979 11:05:34.693465 Dram Type= 6, Freq= 0, CH_0, rank 0
980 11:05:34.696722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 11:05:34.696836 ==
982 11:05:34.711347 TX Vref=22, minBit 11, minWin=26, winSum=435
983 11:05:34.714546 TX Vref=24, minBit 0, minWin=27, winSum=438
984 11:05:34.717947 TX Vref=26, minBit 3, minWin=27, winSum=442
985 11:05:34.721170 TX Vref=28, minBit 0, minWin=27, winSum=445
986 11:05:34.724472 TX Vref=30, minBit 9, minWin=27, winSum=442
987 11:05:34.731193 TX Vref=32, minBit 4, minWin=27, winSum=441
988 11:05:34.734826 [TxChooseVref] Worse bit 0, Min win 27, Win sum 445, Final Vref 28
989 11:05:34.734900
990 11:05:34.738158 Final TX Range 1 Vref 28
991 11:05:34.738236
992 11:05:34.738303 ==
993 11:05:34.741393 Dram Type= 6, Freq= 0, CH_0, rank 0
994 11:05:34.744772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 11:05:34.744871 ==
996 11:05:34.744961
997 11:05:34.747932
998 11:05:34.748032 TX Vref Scan disable
999 11:05:34.751315 == TX Byte 0 ==
1000 11:05:34.754741 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1001 11:05:34.761277 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1002 11:05:34.761382 == TX Byte 1 ==
1003 11:05:34.764455 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1004 11:05:34.771021 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1005 11:05:34.771122
1006 11:05:34.771225 [DATLAT]
1007 11:05:34.771318 Freq=800, CH0 RK0
1008 11:05:34.771417
1009 11:05:34.774585 DATLAT Default: 0xa
1010 11:05:34.774692 0, 0xFFFF, sum = 0
1011 11:05:34.778135 1, 0xFFFF, sum = 0
1012 11:05:34.778240 2, 0xFFFF, sum = 0
1013 11:05:34.781139 3, 0xFFFF, sum = 0
1014 11:05:34.781240 4, 0xFFFF, sum = 0
1015 11:05:34.784466 5, 0xFFFF, sum = 0
1016 11:05:34.787954 6, 0xFFFF, sum = 0
1017 11:05:34.788059 7, 0xFFFF, sum = 0
1018 11:05:34.791430 8, 0xFFFF, sum = 0
1019 11:05:34.791539 9, 0x0, sum = 1
1020 11:05:34.791636 10, 0x0, sum = 2
1021 11:05:34.794557 11, 0x0, sum = 3
1022 11:05:34.794658 12, 0x0, sum = 4
1023 11:05:34.797966 best_step = 10
1024 11:05:34.798064
1025 11:05:34.798158 ==
1026 11:05:34.801311 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 11:05:34.804824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 11:05:34.804921 ==
1029 11:05:34.807829 RX Vref Scan: 1
1030 11:05:34.807897
1031 11:05:34.807956 Set Vref Range= 32 -> 127
1032 11:05:34.808013
1033 11:05:34.811249 RX Vref 32 -> 127, step: 1
1034 11:05:34.811349
1035 11:05:34.814432 RX Delay -111 -> 252, step: 8
1036 11:05:34.814534
1037 11:05:34.817894 Set Vref, RX VrefLevel [Byte0]: 32
1038 11:05:34.821410 [Byte1]: 32
1039 11:05:34.821540
1040 11:05:34.824425 Set Vref, RX VrefLevel [Byte0]: 33
1041 11:05:34.827969 [Byte1]: 33
1042 11:05:34.831865
1043 11:05:34.831974 Set Vref, RX VrefLevel [Byte0]: 34
1044 11:05:34.834987 [Byte1]: 34
1045 11:05:34.839583
1046 11:05:34.839690 Set Vref, RX VrefLevel [Byte0]: 35
1047 11:05:34.842851 [Byte1]: 35
1048 11:05:34.847133
1049 11:05:34.847220 Set Vref, RX VrefLevel [Byte0]: 36
1050 11:05:34.850488 [Byte1]: 36
1051 11:05:34.854684
1052 11:05:34.854765 Set Vref, RX VrefLevel [Byte0]: 37
1053 11:05:34.858044 [Byte1]: 37
1054 11:05:34.862190
1055 11:05:34.862271 Set Vref, RX VrefLevel [Byte0]: 38
1056 11:05:34.865717 [Byte1]: 38
1057 11:05:34.870050
1058 11:05:34.870132 Set Vref, RX VrefLevel [Byte0]: 39
1059 11:05:34.873047 [Byte1]: 39
1060 11:05:34.877756
1061 11:05:34.877838 Set Vref, RX VrefLevel [Byte0]: 40
1062 11:05:34.880832 [Byte1]: 40
1063 11:05:34.885249
1064 11:05:34.885331 Set Vref, RX VrefLevel [Byte0]: 41
1065 11:05:34.888743 [Byte1]: 41
1066 11:05:34.892899
1067 11:05:34.892982 Set Vref, RX VrefLevel [Byte0]: 42
1068 11:05:34.896111 [Byte1]: 42
1069 11:05:34.900454
1070 11:05:34.900536 Set Vref, RX VrefLevel [Byte0]: 43
1071 11:05:34.904080 [Byte1]: 43
1072 11:05:34.908291
1073 11:05:34.908375 Set Vref, RX VrefLevel [Byte0]: 44
1074 11:05:34.911389 [Byte1]: 44
1075 11:05:34.916002
1076 11:05:34.916084 Set Vref, RX VrefLevel [Byte0]: 45
1077 11:05:34.919450 [Byte1]: 45
1078 11:05:34.923892
1079 11:05:34.923973 Set Vref, RX VrefLevel [Byte0]: 46
1080 11:05:34.927442 [Byte1]: 46
1081 11:05:34.931662
1082 11:05:34.931743 Set Vref, RX VrefLevel [Byte0]: 47
1083 11:05:34.934762 [Byte1]: 47
1084 11:05:34.939146
1085 11:05:34.939228 Set Vref, RX VrefLevel [Byte0]: 48
1086 11:05:34.942419 [Byte1]: 48
1087 11:05:34.946655
1088 11:05:34.946736 Set Vref, RX VrefLevel [Byte0]: 49
1089 11:05:34.950138 [Byte1]: 49
1090 11:05:34.954168
1091 11:05:34.954250 Set Vref, RX VrefLevel [Byte0]: 50
1092 11:05:34.957429 [Byte1]: 50
1093 11:05:34.961697
1094 11:05:34.961780 Set Vref, RX VrefLevel [Byte0]: 51
1095 11:05:34.965019 [Byte1]: 51
1096 11:05:34.969539
1097 11:05:34.969614 Set Vref, RX VrefLevel [Byte0]: 52
1098 11:05:34.972527 [Byte1]: 52
1099 11:05:34.976955
1100 11:05:34.977036 Set Vref, RX VrefLevel [Byte0]: 53
1101 11:05:34.980478 [Byte1]: 53
1102 11:05:34.984945
1103 11:05:34.985026 Set Vref, RX VrefLevel [Byte0]: 54
1104 11:05:34.987896 [Byte1]: 54
1105 11:05:34.992125
1106 11:05:34.992207 Set Vref, RX VrefLevel [Byte0]: 55
1107 11:05:34.995426 [Byte1]: 55
1108 11:05:34.999730
1109 11:05:34.999812 Set Vref, RX VrefLevel [Byte0]: 56
1110 11:05:35.003259 [Byte1]: 56
1111 11:05:35.007519
1112 11:05:35.007600 Set Vref, RX VrefLevel [Byte0]: 57
1113 11:05:35.010745 [Byte1]: 57
1114 11:05:35.015373
1115 11:05:35.015454 Set Vref, RX VrefLevel [Byte0]: 58
1116 11:05:35.018398 [Byte1]: 58
1117 11:05:35.022698
1118 11:05:35.022779 Set Vref, RX VrefLevel [Byte0]: 59
1119 11:05:35.026155 [Byte1]: 59
1120 11:05:35.030627
1121 11:05:35.030708 Set Vref, RX VrefLevel [Byte0]: 60
1122 11:05:35.033722 [Byte1]: 60
1123 11:05:35.038096
1124 11:05:35.038178 Set Vref, RX VrefLevel [Byte0]: 61
1125 11:05:35.041401 [Byte1]: 61
1126 11:05:35.045856
1127 11:05:35.045937 Set Vref, RX VrefLevel [Byte0]: 62
1128 11:05:35.048977 [Byte1]: 62
1129 11:05:35.053209
1130 11:05:35.053291 Set Vref, RX VrefLevel [Byte0]: 63
1131 11:05:35.056900 [Byte1]: 63
1132 11:05:35.061205
1133 11:05:35.061286 Set Vref, RX VrefLevel [Byte0]: 64
1134 11:05:35.064602 [Byte1]: 64
1135 11:05:35.068567
1136 11:05:35.068652 Set Vref, RX VrefLevel [Byte0]: 65
1137 11:05:35.071950 [Byte1]: 65
1138 11:05:35.076591
1139 11:05:35.076673 Set Vref, RX VrefLevel [Byte0]: 66
1140 11:05:35.079737 [Byte1]: 66
1141 11:05:35.084079
1142 11:05:35.084161 Set Vref, RX VrefLevel [Byte0]: 67
1143 11:05:35.087312 [Byte1]: 67
1144 11:05:35.091565
1145 11:05:35.091647 Set Vref, RX VrefLevel [Byte0]: 68
1146 11:05:35.095137 [Byte1]: 68
1147 11:05:35.099380
1148 11:05:35.099461 Set Vref, RX VrefLevel [Byte0]: 69
1149 11:05:35.102701 [Byte1]: 69
1150 11:05:35.106831
1151 11:05:35.106912 Set Vref, RX VrefLevel [Byte0]: 70
1152 11:05:35.110397 [Byte1]: 70
1153 11:05:35.114497
1154 11:05:35.114578 Set Vref, RX VrefLevel [Byte0]: 71
1155 11:05:35.117888 [Byte1]: 71
1156 11:05:35.122299
1157 11:05:35.122380 Set Vref, RX VrefLevel [Byte0]: 72
1158 11:05:35.125867 [Byte1]: 72
1159 11:05:35.130092
1160 11:05:35.130173 Set Vref, RX VrefLevel [Byte0]: 73
1161 11:05:35.133101 [Byte1]: 73
1162 11:05:35.137430
1163 11:05:35.137550 Set Vref, RX VrefLevel [Byte0]: 74
1164 11:05:35.140719 [Byte1]: 74
1165 11:05:35.145178
1166 11:05:35.145260 Set Vref, RX VrefLevel [Byte0]: 75
1167 11:05:35.148277 [Byte1]: 75
1168 11:05:35.152722
1169 11:05:35.152803 Set Vref, RX VrefLevel [Byte0]: 76
1170 11:05:35.156105 [Byte1]: 76
1171 11:05:35.160478
1172 11:05:35.160559 Set Vref, RX VrefLevel [Byte0]: 77
1173 11:05:35.163920 [Byte1]: 77
1174 11:05:35.168026
1175 11:05:35.168107 Set Vref, RX VrefLevel [Byte0]: 78
1176 11:05:35.171441 [Byte1]: 78
1177 11:05:35.175735
1178 11:05:35.175816 Final RX Vref Byte 0 = 58 to rank0
1179 11:05:35.179325 Final RX Vref Byte 1 = 61 to rank0
1180 11:05:35.182325 Final RX Vref Byte 0 = 58 to rank1
1181 11:05:35.185751 Final RX Vref Byte 1 = 61 to rank1==
1182 11:05:35.189086 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 11:05:35.192512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 11:05:35.195942 ==
1185 11:05:35.196024 DQS Delay:
1186 11:05:35.196089 DQS0 = 0, DQS1 = 0
1187 11:05:35.199155 DQM Delay:
1188 11:05:35.199237 DQM0 = 81, DQM1 = 68
1189 11:05:35.202726 DQ Delay:
1190 11:05:35.205903 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1191 11:05:35.205985 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1192 11:05:35.209051 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1193 11:05:35.212496 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1194 11:05:35.216051
1195 11:05:35.216133
1196 11:05:35.222644 [DQSOSCAuto] RK0, (LSB)MR18= 0x2928, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1197 11:05:35.225830 CH0 RK0: MR19=606, MR18=2928
1198 11:05:35.232507 CH0_RK0: MR19=0x606, MR18=0x2928, DQSOSC=399, MR23=63, INC=92, DEC=61
1199 11:05:35.232590
1200 11:05:35.235987 ----->DramcWriteLeveling(PI) begin...
1201 11:05:35.236070 ==
1202 11:05:35.239433 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 11:05:35.242689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 11:05:35.242771 ==
1205 11:05:35.245917 Write leveling (Byte 0): 31 => 31
1206 11:05:35.249390 Write leveling (Byte 1): 29 => 29
1207 11:05:35.252646 DramcWriteLeveling(PI) end<-----
1208 11:05:35.252729
1209 11:05:35.252794 ==
1210 11:05:35.256036 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 11:05:35.259197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 11:05:35.259272 ==
1213 11:05:35.262587 [Gating] SW mode calibration
1214 11:05:35.269433 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 11:05:35.276473 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 11:05:35.279645 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 11:05:35.282829 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1218 11:05:35.289520 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1219 11:05:35.292838 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:05:35.295966 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:05:35.302731 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:05:35.306037 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:05:35.309327 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:05:35.315983 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:05:35.319247 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:05:35.322581 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:05:35.325795 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:05:35.332557 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:05:35.335743 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:05:35.379973 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:05:35.380345 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:05:35.380445 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:05:35.380536 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1234 11:05:35.380616 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1235 11:05:35.380721 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:05:35.380816 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:05:35.380939 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:05:35.381033 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:05:35.381145 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:05:35.424008 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:05:35.424346 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:05:35.424447 0 9 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1243 11:05:35.424529 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1244 11:05:35.424612 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 11:05:35.424888 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 11:05:35.424982 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 11:05:35.425102 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 11:05:35.425200 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 11:05:35.425324 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1250 11:05:35.428743 0 10 8 | B1->B0 | 2f2f 2828 | 1 1 | (1 0) (1 0)
1251 11:05:35.431909 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 11:05:35.438486 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 11:05:35.441906 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 11:05:35.445298 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 11:05:35.451852 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 11:05:35.455379 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 11:05:35.458810 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1258 11:05:35.462030 0 11 8 | B1->B0 | 3131 4242 | 0 0 | (1 1) (0 0)
1259 11:05:35.468825 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1260 11:05:35.472026 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 11:05:35.475319 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 11:05:35.482018 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 11:05:35.485415 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 11:05:35.488823 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 11:05:35.495456 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 11:05:35.499152 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1267 11:05:35.502991 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 11:05:35.506794 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 11:05:35.513438 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 11:05:35.517036 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:05:35.520261 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:05:35.524063 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:05:35.531112 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:05:35.534586 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:05:35.537743 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:05:35.541183 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:05:35.547876 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:05:35.551390 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:05:35.554421 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:05:35.561370 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:05:35.564661 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1282 11:05:35.567896 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1283 11:05:35.574484 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1284 11:05:35.574560 Total UI for P1: 0, mck2ui 16
1285 11:05:35.581161 best dqsien dly found for B0: ( 0, 14, 6)
1286 11:05:35.584549 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 11:05:35.587712 Total UI for P1: 0, mck2ui 16
1288 11:05:35.591119 best dqsien dly found for B1: ( 0, 14, 10)
1289 11:05:35.594134 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1290 11:05:35.597716 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1291 11:05:35.597790
1292 11:05:35.600832 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1293 11:05:35.604412 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1294 11:05:35.607585 [Gating] SW calibration Done
1295 11:05:35.607684 ==
1296 11:05:35.610863 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 11:05:35.614290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 11:05:35.617731 ==
1299 11:05:35.617806 RX Vref Scan: 0
1300 11:05:35.617879
1301 11:05:35.620864 RX Vref 0 -> 0, step: 1
1302 11:05:35.620943
1303 11:05:35.624015 RX Delay -130 -> 252, step: 16
1304 11:05:35.627479 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1305 11:05:35.630775 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1306 11:05:35.634264 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1307 11:05:35.637248 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1308 11:05:35.644122 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1309 11:05:35.647319 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1310 11:05:35.650767 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1311 11:05:35.653881 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1312 11:05:35.657353 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1313 11:05:35.663930 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1314 11:05:35.667267 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1315 11:05:35.670401 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1316 11:05:35.673767 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1317 11:05:35.677392 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1318 11:05:35.683993 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1319 11:05:35.687097 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1320 11:05:35.687190 ==
1321 11:05:35.690598 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 11:05:35.693901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 11:05:35.693996 ==
1324 11:05:35.697242 DQS Delay:
1325 11:05:35.697325 DQS0 = 0, DQS1 = 0
1326 11:05:35.697391 DQM Delay:
1327 11:05:35.700696 DQM0 = 80, DQM1 = 69
1328 11:05:35.700778 DQ Delay:
1329 11:05:35.703772 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1330 11:05:35.707270 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
1331 11:05:35.710406 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1332 11:05:35.713835 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1333 11:05:35.713924
1334 11:05:35.713988
1335 11:05:35.714048 ==
1336 11:05:35.717270 Dram Type= 6, Freq= 0, CH_0, rank 1
1337 11:05:35.723726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1338 11:05:35.723804 ==
1339 11:05:35.723868
1340 11:05:35.723928
1341 11:05:35.723997 TX Vref Scan disable
1342 11:05:35.727256 == TX Byte 0 ==
1343 11:05:35.730761 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1344 11:05:35.734281 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1345 11:05:35.737703 == TX Byte 1 ==
1346 11:05:35.740683 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1347 11:05:35.744129 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1348 11:05:35.747374 ==
1349 11:05:35.750929 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 11:05:35.754294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 11:05:35.754383 ==
1352 11:05:35.766558 TX Vref=22, minBit 0, minWin=27, winSum=436
1353 11:05:35.769684 TX Vref=24, minBit 2, minWin=27, winSum=439
1354 11:05:35.773462 TX Vref=26, minBit 2, minWin=27, winSum=440
1355 11:05:35.776514 TX Vref=28, minBit 1, minWin=27, winSum=445
1356 11:05:35.780010 TX Vref=30, minBit 8, minWin=27, winSum=446
1357 11:05:35.783359 TX Vref=32, minBit 1, minWin=27, winSum=443
1358 11:05:35.789858 [TxChooseVref] Worse bit 8, Min win 27, Win sum 446, Final Vref 30
1359 11:05:35.789939
1360 11:05:35.793402 Final TX Range 1 Vref 30
1361 11:05:35.793533
1362 11:05:35.793598 ==
1363 11:05:35.796479 Dram Type= 6, Freq= 0, CH_0, rank 1
1364 11:05:35.800080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1365 11:05:35.800161 ==
1366 11:05:35.800225
1367 11:05:35.803241
1368 11:05:35.803311 TX Vref Scan disable
1369 11:05:35.806506 == TX Byte 0 ==
1370 11:05:35.809755 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1371 11:05:35.813327 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1372 11:05:35.816766 == TX Byte 1 ==
1373 11:05:35.819838 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1374 11:05:35.823463 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1375 11:05:35.826493
1376 11:05:35.826592 [DATLAT]
1377 11:05:35.826658 Freq=800, CH0 RK1
1378 11:05:35.826719
1379 11:05:35.829768 DATLAT Default: 0xa
1380 11:05:35.829853 0, 0xFFFF, sum = 0
1381 11:05:35.833279 1, 0xFFFF, sum = 0
1382 11:05:35.833361 2, 0xFFFF, sum = 0
1383 11:05:35.836360 3, 0xFFFF, sum = 0
1384 11:05:35.836455 4, 0xFFFF, sum = 0
1385 11:05:35.839832 5, 0xFFFF, sum = 0
1386 11:05:35.843231 6, 0xFFFF, sum = 0
1387 11:05:35.843315 7, 0xFFFF, sum = 0
1388 11:05:35.846636 8, 0xFFFF, sum = 0
1389 11:05:35.846719 9, 0x0, sum = 1
1390 11:05:35.846785 10, 0x0, sum = 2
1391 11:05:35.849742 11, 0x0, sum = 3
1392 11:05:35.849825 12, 0x0, sum = 4
1393 11:05:35.853231 best_step = 10
1394 11:05:35.853322
1395 11:05:35.853387 ==
1396 11:05:35.856342 Dram Type= 6, Freq= 0, CH_0, rank 1
1397 11:05:35.859977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1398 11:05:35.860061 ==
1399 11:05:35.863255 RX Vref Scan: 0
1400 11:05:35.863335
1401 11:05:35.863418 RX Vref 0 -> 0, step: 1
1402 11:05:35.863481
1403 11:05:35.866262 RX Delay -111 -> 252, step: 8
1404 11:05:35.873100 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1405 11:05:35.876618 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1406 11:05:35.879936 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1407 11:05:35.883045 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1408 11:05:35.886689 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1409 11:05:35.893326 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1410 11:05:35.896634 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1411 11:05:35.899763 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1412 11:05:35.903394 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1413 11:05:35.906510 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1414 11:05:35.912995 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1415 11:05:35.916347 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1416 11:05:35.919610 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1417 11:05:35.923116 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1418 11:05:35.930017 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1419 11:05:35.932912 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1420 11:05:35.933018 ==
1421 11:05:35.936367 Dram Type= 6, Freq= 0, CH_0, rank 1
1422 11:05:35.939760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1423 11:05:35.939835 ==
1424 11:05:35.939896 DQS Delay:
1425 11:05:35.943268 DQS0 = 0, DQS1 = 0
1426 11:05:35.943340 DQM Delay:
1427 11:05:35.946310 DQM0 = 78, DQM1 = 70
1428 11:05:35.946379 DQ Delay:
1429 11:05:35.949659 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1430 11:05:35.953177 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1431 11:05:35.956448 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1432 11:05:35.959561 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =80
1433 11:05:35.959633
1434 11:05:35.959692
1435 11:05:35.969894 [DQSOSCAuto] RK1, (LSB)MR18= 0x4721, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1436 11:05:35.969971 CH0 RK1: MR19=606, MR18=4721
1437 11:05:35.976413 CH0_RK1: MR19=0x606, MR18=0x4721, DQSOSC=392, MR23=63, INC=96, DEC=64
1438 11:05:35.979891 [RxdqsGatingPostProcess] freq 800
1439 11:05:35.986243 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1440 11:05:35.989815 Pre-setting of DQS Precalculation
1441 11:05:35.993264 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1442 11:05:35.993363 ==
1443 11:05:35.996578 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 11:05:35.999693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 11:05:35.999770 ==
1446 11:05:36.006569 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1447 11:05:36.012867 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1448 11:05:36.021466 [CA 0] Center 36 (6~66) winsize 61
1449 11:05:36.024864 [CA 1] Center 36 (6~67) winsize 62
1450 11:05:36.028056 [CA 2] Center 34 (5~64) winsize 60
1451 11:05:36.031710 [CA 3] Center 34 (4~64) winsize 61
1452 11:05:36.034994 [CA 4] Center 34 (4~65) winsize 62
1453 11:05:36.038316 [CA 5] Center 33 (3~64) winsize 62
1454 11:05:36.038390
1455 11:05:36.041622 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1456 11:05:36.041692
1457 11:05:36.045097 [CATrainingPosCal] consider 1 rank data
1458 11:05:36.048463 u2DelayCellTimex100 = 270/100 ps
1459 11:05:36.051842 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1460 11:05:36.054922 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1461 11:05:36.061524 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1462 11:05:36.065019 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1463 11:05:36.068146 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1464 11:05:36.071750 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1465 11:05:36.071823
1466 11:05:36.075280 CA PerBit enable=1, Macro0, CA PI delay=33
1467 11:05:36.075357
1468 11:05:36.078144 [CBTSetCACLKResult] CA Dly = 33
1469 11:05:36.078218 CS Dly: 5 (0~36)
1470 11:05:36.078280 ==
1471 11:05:36.081665 Dram Type= 6, Freq= 0, CH_1, rank 1
1472 11:05:36.088337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1473 11:05:36.088410 ==
1474 11:05:36.091517 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1475 11:05:36.098260 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1476 11:05:36.107569 [CA 0] Center 37 (7~67) winsize 61
1477 11:05:36.111121 [CA 1] Center 36 (6~67) winsize 62
1478 11:05:36.114241 [CA 2] Center 34 (4~65) winsize 62
1479 11:05:36.117749 [CA 3] Center 34 (4~64) winsize 61
1480 11:05:36.121047 [CA 4] Center 34 (4~65) winsize 62
1481 11:05:36.124306 [CA 5] Center 33 (3~64) winsize 62
1482 11:05:36.124388
1483 11:05:36.127831 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1484 11:05:36.127921
1485 11:05:36.131152 [CATrainingPosCal] consider 2 rank data
1486 11:05:36.134447 u2DelayCellTimex100 = 270/100 ps
1487 11:05:36.137887 CA0 delay=36 (7~66),Diff = 3 PI (21 cell)
1488 11:05:36.141101 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1489 11:05:36.147818 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1490 11:05:36.151109 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1491 11:05:36.154506 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1492 11:05:36.158264 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1493 11:05:36.158347
1494 11:05:36.161968 CA PerBit enable=1, Macro0, CA PI delay=33
1495 11:05:36.162051
1496 11:05:36.165334 [CBTSetCACLKResult] CA Dly = 33
1497 11:05:36.165443 CS Dly: 6 (0~38)
1498 11:05:36.165561
1499 11:05:36.169667 ----->DramcWriteLeveling(PI) begin...
1500 11:05:36.169753 ==
1501 11:05:36.173416 Dram Type= 6, Freq= 0, CH_1, rank 0
1502 11:05:36.177118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1503 11:05:36.177201 ==
1504 11:05:36.181078 Write leveling (Byte 0): 26 => 26
1505 11:05:36.184562 Write leveling (Byte 1): 27 => 27
1506 11:05:36.184646 DramcWriteLeveling(PI) end<-----
1507 11:05:36.184711
1508 11:05:36.188518 ==
1509 11:05:36.188624 Dram Type= 6, Freq= 0, CH_1, rank 0
1510 11:05:36.192414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1511 11:05:36.195515 ==
1512 11:05:36.195592 [Gating] SW mode calibration
1513 11:05:36.205748 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1514 11:05:36.209299 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1515 11:05:36.212449 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1516 11:05:36.219144 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1517 11:05:36.222367 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1518 11:05:36.225750 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:05:36.232531 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:05:36.235746 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:05:36.238885 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:05:36.245807 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:05:36.248869 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:05:36.252395 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:05:36.258976 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:05:36.262310 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:05:36.265695 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:05:36.272147 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:05:36.275349 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:05:36.279090 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:05:36.285525 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:05:36.288786 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1533 11:05:36.291971 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1534 11:05:36.295508 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1535 11:05:36.301800 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:05:36.305295 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:05:36.308766 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:05:36.315464 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:05:36.318419 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:05:36.321855 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1541 11:05:36.328724 0 9 8 | B1->B0 | 2525 2a2a | 1 0 | (0 0) (0 0)
1542 11:05:36.331731 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 11:05:36.335252 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 11:05:36.341749 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 11:05:36.345109 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 11:05:36.348607 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 11:05:36.355491 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 11:05:36.358608 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1549 11:05:36.361790 0 10 8 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (1 1)
1550 11:05:36.368607 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 11:05:36.371799 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 11:05:36.375009 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 11:05:36.381847 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 11:05:36.385425 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 11:05:36.388345 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 11:05:36.395062 0 11 4 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
1557 11:05:36.398445 0 11 8 | B1->B0 | 3636 3939 | 0 0 | (0 0) (0 0)
1558 11:05:36.401679 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 11:05:36.408342 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 11:05:36.411765 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 11:05:36.415305 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 11:05:36.418345 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 11:05:36.425212 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 11:05:36.428514 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1565 11:05:36.431608 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1566 11:05:36.438679 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 11:05:36.441720 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:05:36.445158 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:05:36.451526 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:05:36.454851 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:05:36.458259 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:05:36.464738 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:05:36.468117 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:05:36.471396 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:05:36.478280 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:05:36.481397 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:05:36.484841 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:05:36.491550 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:05:36.494767 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:05:36.498266 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 11:05:36.504794 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1582 11:05:36.504882 Total UI for P1: 0, mck2ui 16
1583 11:05:36.511448 best dqsien dly found for B1: ( 0, 14, 6)
1584 11:05:36.514722 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 11:05:36.518081 Total UI for P1: 0, mck2ui 16
1586 11:05:36.521385 best dqsien dly found for B0: ( 0, 14, 8)
1587 11:05:36.524723 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1588 11:05:36.528069 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1589 11:05:36.528152
1590 11:05:36.531395 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1591 11:05:36.534859 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1592 11:05:36.537918 [Gating] SW calibration Done
1593 11:05:36.538000 ==
1594 11:05:36.541377 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 11:05:36.544560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 11:05:36.544644 ==
1597 11:05:36.548049 RX Vref Scan: 0
1598 11:05:36.548131
1599 11:05:36.551145 RX Vref 0 -> 0, step: 1
1600 11:05:36.551227
1601 11:05:36.551310 RX Delay -130 -> 252, step: 16
1602 11:05:36.558141 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1603 11:05:36.561266 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1604 11:05:36.564766 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1605 11:05:36.568158 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1606 11:05:36.571292 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1607 11:05:36.578275 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1608 11:05:36.581381 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1609 11:05:36.584809 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1610 11:05:36.587917 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1611 11:05:36.591514 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1612 11:05:36.598159 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1613 11:05:36.601480 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1614 11:05:36.604737 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1615 11:05:36.608077 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1616 11:05:36.611567 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1617 11:05:36.617915 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1618 11:05:36.617999 ==
1619 11:05:36.621286 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 11:05:36.624685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 11:05:36.624769 ==
1622 11:05:36.624833 DQS Delay:
1623 11:05:36.628003 DQS0 = 0, DQS1 = 0
1624 11:05:36.628085 DQM Delay:
1625 11:05:36.631377 DQM0 = 80, DQM1 = 70
1626 11:05:36.631459 DQ Delay:
1627 11:05:36.634634 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =77
1628 11:05:36.638046 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1629 11:05:36.641363 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1630 11:05:36.644741 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1631 11:05:36.644823
1632 11:05:36.644887
1633 11:05:36.644947 ==
1634 11:05:36.647871 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 11:05:36.651398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 11:05:36.651481 ==
1637 11:05:36.651547
1638 11:05:36.654595
1639 11:05:36.654677 TX Vref Scan disable
1640 11:05:36.658077 == TX Byte 0 ==
1641 11:05:36.661652 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1642 11:05:36.664765 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1643 11:05:36.667862 == TX Byte 1 ==
1644 11:05:36.671386 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1645 11:05:36.674440 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1646 11:05:36.674522 ==
1647 11:05:36.677876 Dram Type= 6, Freq= 0, CH_1, rank 0
1648 11:05:36.684494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1649 11:05:36.684577 ==
1650 11:05:36.696179 TX Vref=22, minBit 1, minWin=27, winSum=443
1651 11:05:36.699617 TX Vref=24, minBit 1, minWin=27, winSum=445
1652 11:05:36.702887 TX Vref=26, minBit 1, minWin=27, winSum=447
1653 11:05:36.706559 TX Vref=28, minBit 5, minWin=27, winSum=449
1654 11:05:36.709464 TX Vref=30, minBit 6, minWin=27, winSum=452
1655 11:05:36.716247 TX Vref=32, minBit 5, minWin=27, winSum=448
1656 11:05:36.719340 [TxChooseVref] Worse bit 6, Min win 27, Win sum 452, Final Vref 30
1657 11:05:36.719423
1658 11:05:36.723351 Final TX Range 1 Vref 30
1659 11:05:36.723433
1660 11:05:36.723498 ==
1661 11:05:36.726335 Dram Type= 6, Freq= 0, CH_1, rank 0
1662 11:05:36.729385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1663 11:05:36.729502 ==
1664 11:05:36.729571
1665 11:05:36.733151
1666 11:05:36.733241 TX Vref Scan disable
1667 11:05:36.736502 == TX Byte 0 ==
1668 11:05:36.740067 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1669 11:05:36.743617 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1670 11:05:36.746918 == TX Byte 1 ==
1671 11:05:36.750103 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1672 11:05:36.753351 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1673 11:05:36.753434
1674 11:05:36.756804 [DATLAT]
1675 11:05:36.756886 Freq=800, CH1 RK0
1676 11:05:36.756951
1677 11:05:36.759884 DATLAT Default: 0xa
1678 11:05:36.759967 0, 0xFFFF, sum = 0
1679 11:05:36.763290 1, 0xFFFF, sum = 0
1680 11:05:36.763377 2, 0xFFFF, sum = 0
1681 11:05:36.766649 3, 0xFFFF, sum = 0
1682 11:05:36.766733 4, 0xFFFF, sum = 0
1683 11:05:36.770067 5, 0xFFFF, sum = 0
1684 11:05:36.770151 6, 0xFFFF, sum = 0
1685 11:05:36.773583 7, 0xFFFF, sum = 0
1686 11:05:36.773667 8, 0xFFFF, sum = 0
1687 11:05:36.776765 9, 0x0, sum = 1
1688 11:05:36.776849 10, 0x0, sum = 2
1689 11:05:36.780191 11, 0x0, sum = 3
1690 11:05:36.780274 12, 0x0, sum = 4
1691 11:05:36.783385 best_step = 10
1692 11:05:36.783467
1693 11:05:36.783532 ==
1694 11:05:36.786574 Dram Type= 6, Freq= 0, CH_1, rank 0
1695 11:05:36.790014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1696 11:05:36.790097 ==
1697 11:05:36.793437 RX Vref Scan: 1
1698 11:05:36.793566
1699 11:05:36.793633 Set Vref Range= 32 -> 127
1700 11:05:36.793695
1701 11:05:36.796604 RX Vref 32 -> 127, step: 1
1702 11:05:36.796686
1703 11:05:36.800105 RX Delay -111 -> 252, step: 8
1704 11:05:36.800188
1705 11:05:36.803307 Set Vref, RX VrefLevel [Byte0]: 32
1706 11:05:36.806799 [Byte1]: 32
1707 11:05:36.806881
1708 11:05:36.810013 Set Vref, RX VrefLevel [Byte0]: 33
1709 11:05:36.813364 [Byte1]: 33
1710 11:05:36.816601
1711 11:05:36.816683 Set Vref, RX VrefLevel [Byte0]: 34
1712 11:05:36.820092 [Byte1]: 34
1713 11:05:36.824370
1714 11:05:36.824452 Set Vref, RX VrefLevel [Byte0]: 35
1715 11:05:36.827707 [Byte1]: 35
1716 11:05:36.831829
1717 11:05:36.831911 Set Vref, RX VrefLevel [Byte0]: 36
1718 11:05:36.835278 [Byte1]: 36
1719 11:05:36.839526
1720 11:05:36.839607 Set Vref, RX VrefLevel [Byte0]: 37
1721 11:05:36.843056 [Byte1]: 37
1722 11:05:36.847244
1723 11:05:36.847326 Set Vref, RX VrefLevel [Byte0]: 38
1724 11:05:36.850581 [Byte1]: 38
1725 11:05:36.854806
1726 11:05:36.854888 Set Vref, RX VrefLevel [Byte0]: 39
1727 11:05:36.857952 [Byte1]: 39
1728 11:05:36.862455
1729 11:05:36.862538 Set Vref, RX VrefLevel [Byte0]: 40
1730 11:05:36.865753 [Byte1]: 40
1731 11:05:36.870169
1732 11:05:36.870251 Set Vref, RX VrefLevel [Byte0]: 41
1733 11:05:36.873396 [Byte1]: 41
1734 11:05:36.877465
1735 11:05:36.880942 Set Vref, RX VrefLevel [Byte0]: 42
1736 11:05:36.881024 [Byte1]: 42
1737 11:05:36.885256
1738 11:05:36.885338 Set Vref, RX VrefLevel [Byte0]: 43
1739 11:05:36.888622 [Byte1]: 43
1740 11:05:36.893084
1741 11:05:36.893166 Set Vref, RX VrefLevel [Byte0]: 44
1742 11:05:36.896446 [Byte1]: 44
1743 11:05:36.901115
1744 11:05:36.901197 Set Vref, RX VrefLevel [Byte0]: 45
1745 11:05:36.904315 [Byte1]: 45
1746 11:05:36.908469
1747 11:05:36.908551 Set Vref, RX VrefLevel [Byte0]: 46
1748 11:05:36.911659 [Byte1]: 46
1749 11:05:36.915849
1750 11:05:36.915931 Set Vref, RX VrefLevel [Byte0]: 47
1751 11:05:36.919394 [Byte1]: 47
1752 11:05:36.923667
1753 11:05:36.923753 Set Vref, RX VrefLevel [Byte0]: 48
1754 11:05:36.927084 [Byte1]: 48
1755 11:05:36.931415
1756 11:05:36.931497 Set Vref, RX VrefLevel [Byte0]: 49
1757 11:05:36.934515 [Byte1]: 49
1758 11:05:36.939031
1759 11:05:36.939114 Set Vref, RX VrefLevel [Byte0]: 50
1760 11:05:36.942141 [Byte1]: 50
1761 11:05:36.946953
1762 11:05:36.947035 Set Vref, RX VrefLevel [Byte0]: 51
1763 11:05:36.949832 [Byte1]: 51
1764 11:05:36.954428
1765 11:05:36.954509 Set Vref, RX VrefLevel [Byte0]: 52
1766 11:05:36.957433 [Byte1]: 52
1767 11:05:36.962050
1768 11:05:36.962132 Set Vref, RX VrefLevel [Byte0]: 53
1769 11:05:36.965096 [Byte1]: 53
1770 11:05:36.969602
1771 11:05:36.969683 Set Vref, RX VrefLevel [Byte0]: 54
1772 11:05:36.973022 [Byte1]: 54
1773 11:05:36.977058
1774 11:05:36.977140 Set Vref, RX VrefLevel [Byte0]: 55
1775 11:05:36.980599 [Byte1]: 55
1776 11:05:36.984873
1777 11:05:36.984956 Set Vref, RX VrefLevel [Byte0]: 56
1778 11:05:36.988032 [Byte1]: 56
1779 11:05:36.992350
1780 11:05:36.992433 Set Vref, RX VrefLevel [Byte0]: 57
1781 11:05:36.995796 [Byte1]: 57
1782 11:05:37.000147
1783 11:05:37.000229 Set Vref, RX VrefLevel [Byte0]: 58
1784 11:05:37.003389 [Byte1]: 58
1785 11:05:37.007788
1786 11:05:37.007871 Set Vref, RX VrefLevel [Byte0]: 59
1787 11:05:37.011188 [Byte1]: 59
1788 11:05:37.015558
1789 11:05:37.015641 Set Vref, RX VrefLevel [Byte0]: 60
1790 11:05:37.018556 [Byte1]: 60
1791 11:05:37.023127
1792 11:05:37.023209 Set Vref, RX VrefLevel [Byte0]: 61
1793 11:05:37.026304 [Byte1]: 61
1794 11:05:37.030513
1795 11:05:37.030594 Set Vref, RX VrefLevel [Byte0]: 62
1796 11:05:37.034167 [Byte1]: 62
1797 11:05:37.038483
1798 11:05:37.038566 Set Vref, RX VrefLevel [Byte0]: 63
1799 11:05:37.041445 [Byte1]: 63
1800 11:05:37.046032
1801 11:05:37.046114 Set Vref, RX VrefLevel [Byte0]: 64
1802 11:05:37.049824 [Byte1]: 64
1803 11:05:37.053734
1804 11:05:37.053816 Set Vref, RX VrefLevel [Byte0]: 65
1805 11:05:37.056947 [Byte1]: 65
1806 11:05:37.061137
1807 11:05:37.061219 Set Vref, RX VrefLevel [Byte0]: 66
1808 11:05:37.064614 [Byte1]: 66
1809 11:05:37.068854
1810 11:05:37.068936 Set Vref, RX VrefLevel [Byte0]: 67
1811 11:05:37.072385 [Byte1]: 67
1812 11:05:37.076478
1813 11:05:37.076560 Set Vref, RX VrefLevel [Byte0]: 68
1814 11:05:37.079701 [Byte1]: 68
1815 11:05:37.084041
1816 11:05:37.084127 Set Vref, RX VrefLevel [Byte0]: 69
1817 11:05:37.087556 [Byte1]: 69
1818 11:05:37.091906
1819 11:05:37.091988 Set Vref, RX VrefLevel [Byte0]: 70
1820 11:05:37.095130 [Byte1]: 70
1821 11:05:37.099521
1822 11:05:37.099603 Set Vref, RX VrefLevel [Byte0]: 71
1823 11:05:37.102739 [Byte1]: 71
1824 11:05:37.107066
1825 11:05:37.107148 Set Vref, RX VrefLevel [Byte0]: 72
1826 11:05:37.110439 [Byte1]: 72
1827 11:05:37.114587
1828 11:05:37.114670 Set Vref, RX VrefLevel [Byte0]: 73
1829 11:05:37.117945 [Byte1]: 73
1830 11:05:37.122232
1831 11:05:37.122314 Set Vref, RX VrefLevel [Byte0]: 74
1832 11:05:37.125702 [Byte1]: 74
1833 11:05:37.130301
1834 11:05:37.130383 Set Vref, RX VrefLevel [Byte0]: 75
1835 11:05:37.133347 [Byte1]: 75
1836 11:05:37.137756
1837 11:05:37.137837 Set Vref, RX VrefLevel [Byte0]: 76
1838 11:05:37.140867 [Byte1]: 76
1839 11:05:37.145327
1840 11:05:37.145409 Final RX Vref Byte 0 = 56 to rank0
1841 11:05:37.148781 Final RX Vref Byte 1 = 62 to rank0
1842 11:05:37.152112 Final RX Vref Byte 0 = 56 to rank1
1843 11:05:37.155343 Final RX Vref Byte 1 = 62 to rank1==
1844 11:05:37.158617 Dram Type= 6, Freq= 0, CH_1, rank 0
1845 11:05:37.165341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1846 11:05:37.165436 ==
1847 11:05:37.165533 DQS Delay:
1848 11:05:37.165597 DQS0 = 0, DQS1 = 0
1849 11:05:37.168754 DQM Delay:
1850 11:05:37.168837 DQM0 = 81, DQM1 = 70
1851 11:05:37.171858 DQ Delay:
1852 11:05:37.175248 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1853 11:05:37.178716 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1854 11:05:37.178799 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1855 11:05:37.185315 DQ12 =76, DQ13 =76, DQ14 =76, DQ15 =76
1856 11:05:37.185423
1857 11:05:37.185546
1858 11:05:37.192129 [DQSOSCAuto] RK0, (LSB)MR18= 0xe19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1859 11:05:37.195277 CH1 RK0: MR19=606, MR18=E19
1860 11:05:37.201805 CH1_RK0: MR19=0x606, MR18=0xE19, DQSOSC=403, MR23=63, INC=90, DEC=60
1861 11:05:37.201888
1862 11:05:37.205030 ----->DramcWriteLeveling(PI) begin...
1863 11:05:37.205114 ==
1864 11:05:37.208350 Dram Type= 6, Freq= 0, CH_1, rank 1
1865 11:05:37.211725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1866 11:05:37.211829 ==
1867 11:05:37.215086 Write leveling (Byte 0): 24 => 24
1868 11:05:37.218479 Write leveling (Byte 1): 30 => 30
1869 11:05:37.222040 DramcWriteLeveling(PI) end<-----
1870 11:05:37.222123
1871 11:05:37.222188 ==
1872 11:05:37.225227 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 11:05:37.228629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1874 11:05:37.228716 ==
1875 11:05:37.232073 [Gating] SW mode calibration
1876 11:05:37.238766 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1877 11:05:37.245284 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1878 11:05:37.248538 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1879 11:05:37.252112 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1880 11:05:37.258976 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:05:37.262025 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:05:37.265443 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:05:37.271966 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:05:37.275408 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:05:37.278581 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 11:05:37.281968 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:05:37.288557 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:05:37.292106 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:05:37.295129 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:05:37.301787 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:05:37.305308 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:05:37.308716 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:05:37.315187 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:05:37.318556 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:05:37.321800 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1896 11:05:37.328477 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1897 11:05:37.331978 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:05:37.335315 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 11:05:37.341684 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 11:05:37.345075 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 11:05:37.348277 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:05:37.355129 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 11:05:37.358636 0 9 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1904 11:05:37.361842 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1905 11:05:37.368428 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 11:05:37.371669 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 11:05:37.374970 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 11:05:37.381721 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 11:05:37.385132 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 11:05:37.388373 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 11:05:37.395118 0 10 4 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (0 0)
1912 11:05:37.398482 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1913 11:05:37.401652 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 11:05:37.408306 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 11:05:37.411757 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 11:05:37.414930 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 11:05:37.418356 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 11:05:37.424774 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1919 11:05:37.427990 0 11 4 | B1->B0 | 2727 3636 | 1 0 | (0 0) (0 0)
1920 11:05:37.431424 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1921 11:05:37.438171 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 11:05:37.441709 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 11:05:37.444742 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 11:05:37.451596 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 11:05:37.454994 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 11:05:37.458354 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 11:05:37.464985 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1928 11:05:37.468125 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1929 11:05:37.471587 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 11:05:37.478107 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 11:05:37.481749 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 11:05:37.484815 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 11:05:37.491587 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 11:05:37.494666 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 11:05:37.498026 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 11:05:37.504473 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 11:05:37.507887 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 11:05:37.511141 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 11:05:37.517956 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 11:05:37.521352 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 11:05:37.524776 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 11:05:37.531413 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 11:05:37.534666 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1944 11:05:37.537984 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1945 11:05:37.541078 Total UI for P1: 0, mck2ui 16
1946 11:05:37.544567 best dqsien dly found for B0: ( 0, 14, 4)
1947 11:05:37.547971 Total UI for P1: 0, mck2ui 16
1948 11:05:37.550974 best dqsien dly found for B1: ( 0, 14, 6)
1949 11:05:37.554454 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1950 11:05:37.557836 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1951 11:05:37.558025
1952 11:05:37.560913 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1953 11:05:37.564385 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1954 11:05:37.567725 [Gating] SW calibration Done
1955 11:05:37.567808 ==
1956 11:05:37.570980 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 11:05:37.577650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 11:05:37.577732 ==
1959 11:05:37.577797 RX Vref Scan: 0
1960 11:05:37.577858
1961 11:05:37.581086 RX Vref 0 -> 0, step: 1
1962 11:05:37.581168
1963 11:05:37.584536 RX Delay -130 -> 252, step: 16
1964 11:05:37.588130 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1965 11:05:37.591103 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1966 11:05:37.594778 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1967 11:05:37.597898 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1968 11:05:37.604375 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1969 11:05:37.607752 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1970 11:05:37.611226 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1971 11:05:37.614378 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1972 11:05:37.617839 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1973 11:05:37.624514 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1974 11:05:37.627708 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1975 11:05:37.631218 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1976 11:05:37.634607 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1977 11:05:37.637562 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1978 11:05:37.644693 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1979 11:05:37.647808 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1980 11:05:37.647891 ==
1981 11:05:37.651246 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 11:05:37.654309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 11:05:37.654392 ==
1984 11:05:37.657649 DQS Delay:
1985 11:05:37.657731 DQS0 = 0, DQS1 = 0
1986 11:05:37.657797 DQM Delay:
1987 11:05:37.660857 DQM0 = 79, DQM1 = 72
1988 11:05:37.660939 DQ Delay:
1989 11:05:37.664297 DQ0 =77, DQ1 =69, DQ2 =69, DQ3 =77
1990 11:05:37.667835 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1991 11:05:37.671102 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1992 11:05:37.674259 DQ12 =85, DQ13 =77, DQ14 =77, DQ15 =77
1993 11:05:37.674341
1994 11:05:37.674408
1995 11:05:37.674468 ==
1996 11:05:37.677744 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 11:05:37.684277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 11:05:37.684361 ==
1999 11:05:37.684426
2000 11:05:37.684486
2001 11:05:37.684544 TX Vref Scan disable
2002 11:05:37.687807 == TX Byte 0 ==
2003 11:05:37.691390 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
2004 11:05:37.697977 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
2005 11:05:37.698060 == TX Byte 1 ==
2006 11:05:37.701053 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2007 11:05:37.707797 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2008 11:05:37.707879 ==
2009 11:05:37.711392 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 11:05:37.714256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 11:05:37.714340 ==
2012 11:05:37.727837 TX Vref=22, minBit 9, minWin=27, winSum=455
2013 11:05:37.730965 TX Vref=24, minBit 2, minWin=28, winSum=459
2014 11:05:37.734405 TX Vref=26, minBit 10, minWin=28, winSum=462
2015 11:05:37.737564 TX Vref=28, minBit 2, minWin=28, winSum=466
2016 11:05:37.741064 TX Vref=30, minBit 13, minWin=28, winSum=469
2017 11:05:37.747511 TX Vref=32, minBit 5, minWin=28, winSum=466
2018 11:05:37.750933 [TxChooseVref] Worse bit 13, Min win 28, Win sum 469, Final Vref 30
2019 11:05:37.751016
2020 11:05:37.754531 Final TX Range 1 Vref 30
2021 11:05:37.754614
2022 11:05:37.754679 ==
2023 11:05:37.757665 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 11:05:37.761056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 11:05:37.764319 ==
2026 11:05:37.764409
2027 11:05:37.764475
2028 11:05:37.764535 TX Vref Scan disable
2029 11:05:37.767899 == TX Byte 0 ==
2030 11:05:37.771269 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
2031 11:05:37.777743 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
2032 11:05:37.777825 == TX Byte 1 ==
2033 11:05:37.781213 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2034 11:05:37.784689 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2035 11:05:37.787840
2036 11:05:37.787921 [DATLAT]
2037 11:05:37.787986 Freq=800, CH1 RK1
2038 11:05:37.788047
2039 11:05:37.791027 DATLAT Default: 0xa
2040 11:05:37.791109 0, 0xFFFF, sum = 0
2041 11:05:37.794541 1, 0xFFFF, sum = 0
2042 11:05:37.794625 2, 0xFFFF, sum = 0
2043 11:05:37.797872 3, 0xFFFF, sum = 0
2044 11:05:37.797957 4, 0xFFFF, sum = 0
2045 11:05:37.801414 5, 0xFFFF, sum = 0
2046 11:05:37.801553 6, 0xFFFF, sum = 0
2047 11:05:37.804817 7, 0xFFFF, sum = 0
2048 11:05:37.804905 8, 0xFFFF, sum = 0
2049 11:05:37.807896 9, 0x0, sum = 1
2050 11:05:37.807979 10, 0x0, sum = 2
2051 11:05:37.811429 11, 0x0, sum = 3
2052 11:05:37.811512 12, 0x0, sum = 4
2053 11:05:37.814780 best_step = 10
2054 11:05:37.814862
2055 11:05:37.814927 ==
2056 11:05:37.817901 Dram Type= 6, Freq= 0, CH_1, rank 1
2057 11:05:37.821363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2058 11:05:37.821472 ==
2059 11:05:37.824523 RX Vref Scan: 0
2060 11:05:37.824605
2061 11:05:37.824670 RX Vref 0 -> 0, step: 1
2062 11:05:37.824731
2063 11:05:37.828031 RX Delay -111 -> 252, step: 8
2064 11:05:37.834272 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2065 11:05:37.837623 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2066 11:05:37.841044 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2067 11:05:37.844478 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2068 11:05:37.851082 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2069 11:05:37.854432 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2070 11:05:37.857472 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2071 11:05:37.861141 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2072 11:05:37.864392 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2073 11:05:37.867711 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2074 11:05:37.874400 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2075 11:05:37.877718 iDelay=209, Bit 11, Center 72 (-47 ~ 192) 240
2076 11:05:37.880847 iDelay=209, Bit 12, Center 84 (-39 ~ 208) 248
2077 11:05:37.884191 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2078 11:05:37.891117 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2079 11:05:37.894070 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2080 11:05:37.894152 ==
2081 11:05:37.897360 Dram Type= 6, Freq= 0, CH_1, rank 1
2082 11:05:37.900652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2083 11:05:37.900735 ==
2084 11:05:37.903958 DQS Delay:
2085 11:05:37.904040 DQS0 = 0, DQS1 = 0
2086 11:05:37.904106 DQM Delay:
2087 11:05:37.907389 DQM0 = 77, DQM1 = 74
2088 11:05:37.907471 DQ Delay:
2089 11:05:37.910822 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2090 11:05:37.914063 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2091 11:05:37.917446 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =72
2092 11:05:37.920641 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
2093 11:05:37.920724
2094 11:05:37.920788
2095 11:05:37.930593 [DQSOSCAuto] RK1, (LSB)MR18= 0x253d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2096 11:05:37.930677 CH1 RK1: MR19=606, MR18=253D
2097 11:05:37.937638 CH1_RK1: MR19=0x606, MR18=0x253D, DQSOSC=394, MR23=63, INC=95, DEC=63
2098 11:05:37.940709 [RxdqsGatingPostProcess] freq 800
2099 11:05:37.947580 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2100 11:05:37.950681 Pre-setting of DQS Precalculation
2101 11:05:37.954171 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2102 11:05:37.960713 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2103 11:05:37.970626 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2104 11:05:37.970709
2105 11:05:37.970774
2106 11:05:37.970834 [Calibration Summary] 1600 Mbps
2107 11:05:37.974080 CH 0, Rank 0
2108 11:05:37.974181 SW Impedance : PASS
2109 11:05:37.977438 DUTY Scan : NO K
2110 11:05:37.980881 ZQ Calibration : PASS
2111 11:05:37.980963 Jitter Meter : NO K
2112 11:05:37.983837 CBT Training : PASS
2113 11:05:37.987493 Write leveling : PASS
2114 11:05:37.987597 RX DQS gating : PASS
2115 11:05:37.990509 RX DQ/DQS(RDDQC) : PASS
2116 11:05:37.994085 TX DQ/DQS : PASS
2117 11:05:37.994168 RX DATLAT : PASS
2118 11:05:37.997458 RX DQ/DQS(Engine): PASS
2119 11:05:38.000880 TX OE : NO K
2120 11:05:38.000970 All Pass.
2121 11:05:38.001051
2122 11:05:38.001157 CH 0, Rank 1
2123 11:05:38.003895 SW Impedance : PASS
2124 11:05:38.007331 DUTY Scan : NO K
2125 11:05:38.007414 ZQ Calibration : PASS
2126 11:05:38.010758 Jitter Meter : NO K
2127 11:05:38.014231 CBT Training : PASS
2128 11:05:38.014313 Write leveling : PASS
2129 11:05:38.017391 RX DQS gating : PASS
2130 11:05:38.020651 RX DQ/DQS(RDDQC) : PASS
2131 11:05:38.020734 TX DQ/DQS : PASS
2132 11:05:38.024137 RX DATLAT : PASS
2133 11:05:38.024220 RX DQ/DQS(Engine): PASS
2134 11:05:38.027325 TX OE : NO K
2135 11:05:38.027408 All Pass.
2136 11:05:38.027472
2137 11:05:38.030703 CH 1, Rank 0
2138 11:05:38.030786 SW Impedance : PASS
2139 11:05:38.034136 DUTY Scan : NO K
2140 11:05:38.037258 ZQ Calibration : PASS
2141 11:05:38.037367 Jitter Meter : NO K
2142 11:05:38.040781 CBT Training : PASS
2143 11:05:38.044081 Write leveling : PASS
2144 11:05:38.044163 RX DQS gating : PASS
2145 11:05:38.047500 RX DQ/DQS(RDDQC) : PASS
2146 11:05:38.050674 TX DQ/DQS : PASS
2147 11:05:38.050756 RX DATLAT : PASS
2148 11:05:38.054172 RX DQ/DQS(Engine): PASS
2149 11:05:38.057382 TX OE : NO K
2150 11:05:38.057488 All Pass.
2151 11:05:38.057573
2152 11:05:38.057634 CH 1, Rank 1
2153 11:05:38.060715 SW Impedance : PASS
2154 11:05:38.064110 DUTY Scan : NO K
2155 11:05:38.064192 ZQ Calibration : PASS
2156 11:05:38.067272 Jitter Meter : NO K
2157 11:05:38.067355 CBT Training : PASS
2158 11:05:38.070660 Write leveling : PASS
2159 11:05:38.073940 RX DQS gating : PASS
2160 11:05:38.074022 RX DQ/DQS(RDDQC) : PASS
2161 11:05:38.077376 TX DQ/DQS : PASS
2162 11:05:38.080769 RX DATLAT : PASS
2163 11:05:38.080851 RX DQ/DQS(Engine): PASS
2164 11:05:38.084288 TX OE : NO K
2165 11:05:38.084374 All Pass.
2166 11:05:38.084440
2167 11:05:38.087507 DramC Write-DBI off
2168 11:05:38.090743 PER_BANK_REFRESH: Hybrid Mode
2169 11:05:38.090826 TX_TRACKING: ON
2170 11:05:38.094269 [GetDramInforAfterCalByMRR] Vendor 6.
2171 11:05:38.097366 [GetDramInforAfterCalByMRR] Revision 606.
2172 11:05:38.100911 [GetDramInforAfterCalByMRR] Revision 2 0.
2173 11:05:38.104276 MR0 0x3b3b
2174 11:05:38.104358 MR8 0x5151
2175 11:05:38.107694 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2176 11:05:38.107776
2177 11:05:38.107841 MR0 0x3b3b
2178 11:05:38.110755 MR8 0x5151
2179 11:05:38.114264 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2180 11:05:38.114347
2181 11:05:38.121146 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2182 11:05:38.127486 [FAST_K] Save calibration result to emmc
2183 11:05:38.131000 [FAST_K] Save calibration result to emmc
2184 11:05:38.131083 dram_init: config_dvfs: 1
2185 11:05:38.137454 dramc_set_vcore_voltage set vcore to 662500
2186 11:05:38.137575 Read voltage for 1200, 2
2187 11:05:38.140717 Vio18 = 0
2188 11:05:38.140817 Vcore = 662500
2189 11:05:38.140896 Vdram = 0
2190 11:05:38.140957 Vddq = 0
2191 11:05:38.144137 Vmddr = 0
2192 11:05:38.147621 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2193 11:05:38.153992 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2194 11:05:38.157395 MEM_TYPE=3, freq_sel=15
2195 11:05:38.157524 sv_algorithm_assistance_LP4_1600
2196 11:05:38.164147 ============ PULL DRAM RESETB DOWN ============
2197 11:05:38.167377 ========== PULL DRAM RESETB DOWN end =========
2198 11:05:38.170867 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2199 11:05:38.174268 ===================================
2200 11:05:38.177490 LPDDR4 DRAM CONFIGURATION
2201 11:05:38.180758 ===================================
2202 11:05:38.184259 EX_ROW_EN[0] = 0x0
2203 11:05:38.184349 EX_ROW_EN[1] = 0x0
2204 11:05:38.187353 LP4Y_EN = 0x0
2205 11:05:38.187435 WORK_FSP = 0x0
2206 11:05:38.190756 WL = 0x4
2207 11:05:38.190839 RL = 0x4
2208 11:05:38.193801 BL = 0x2
2209 11:05:38.193882 RPST = 0x0
2210 11:05:38.197421 RD_PRE = 0x0
2211 11:05:38.197560 WR_PRE = 0x1
2212 11:05:38.200708 WR_PST = 0x0
2213 11:05:38.200790 DBI_WR = 0x0
2214 11:05:38.204305 DBI_RD = 0x0
2215 11:05:38.204421 OTF = 0x1
2216 11:05:38.207398 ===================================
2217 11:05:38.210813 ===================================
2218 11:05:38.214310 ANA top config
2219 11:05:38.217362 ===================================
2220 11:05:38.217471 DLL_ASYNC_EN = 0
2221 11:05:38.221067 ALL_SLAVE_EN = 0
2222 11:05:38.224379 NEW_RANK_MODE = 1
2223 11:05:38.227528 DLL_IDLE_MODE = 1
2224 11:05:38.230829 LP45_APHY_COMB_EN = 1
2225 11:05:38.230911 TX_ODT_DIS = 1
2226 11:05:38.234342 NEW_8X_MODE = 1
2227 11:05:38.237494 ===================================
2228 11:05:38.240813 ===================================
2229 11:05:38.244148 data_rate = 2400
2230 11:05:38.247486 CKR = 1
2231 11:05:38.251005 DQ_P2S_RATIO = 8
2232 11:05:38.254109 ===================================
2233 11:05:38.254192 CA_P2S_RATIO = 8
2234 11:05:38.257507 DQ_CA_OPEN = 0
2235 11:05:38.261026 DQ_SEMI_OPEN = 0
2236 11:05:38.263959 CA_SEMI_OPEN = 0
2237 11:05:38.267331 CA_FULL_RATE = 0
2238 11:05:38.270663 DQ_CKDIV4_EN = 0
2239 11:05:38.270746 CA_CKDIV4_EN = 0
2240 11:05:38.274133 CA_PREDIV_EN = 0
2241 11:05:38.277348 PH8_DLY = 17
2242 11:05:38.280848 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2243 11:05:38.283880 DQ_AAMCK_DIV = 4
2244 11:05:38.287400 CA_AAMCK_DIV = 4
2245 11:05:38.287537 CA_ADMCK_DIV = 4
2246 11:05:38.290910 DQ_TRACK_CA_EN = 0
2247 11:05:38.294036 CA_PICK = 1200
2248 11:05:38.297487 CA_MCKIO = 1200
2249 11:05:38.300978 MCKIO_SEMI = 0
2250 11:05:38.304134 PLL_FREQ = 2366
2251 11:05:38.307544 DQ_UI_PI_RATIO = 32
2252 11:05:38.311025 CA_UI_PI_RATIO = 0
2253 11:05:38.311107 ===================================
2254 11:05:38.313992 ===================================
2255 11:05:38.317472 memory_type:LPDDR4
2256 11:05:38.320702 GP_NUM : 10
2257 11:05:38.320784 SRAM_EN : 1
2258 11:05:38.324108 MD32_EN : 0
2259 11:05:38.327273 ===================================
2260 11:05:38.330661 [ANA_INIT] >>>>>>>>>>>>>>
2261 11:05:38.333975 <<<<<< [CONFIGURE PHASE]: ANA_TX
2262 11:05:38.337504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2263 11:05:38.340673 ===================================
2264 11:05:38.340756 data_rate = 2400,PCW = 0X5b00
2265 11:05:38.344130 ===================================
2266 11:05:38.347227 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2267 11:05:38.353836 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2268 11:05:38.360701 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2269 11:05:38.364100 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2270 11:05:38.367311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2271 11:05:38.370776 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2272 11:05:38.373886 [ANA_INIT] flow start
2273 11:05:38.377292 [ANA_INIT] PLL >>>>>>>>
2274 11:05:38.377383 [ANA_INIT] PLL <<<<<<<<
2275 11:05:38.380541 [ANA_INIT] MIDPI >>>>>>>>
2276 11:05:38.384183 [ANA_INIT] MIDPI <<<<<<<<
2277 11:05:38.384265 [ANA_INIT] DLL >>>>>>>>
2278 11:05:38.387464 [ANA_INIT] DLL <<<<<<<<
2279 11:05:38.390552 [ANA_INIT] flow end
2280 11:05:38.393741 ============ LP4 DIFF to SE enter ============
2281 11:05:38.397084 ============ LP4 DIFF to SE exit ============
2282 11:05:38.400419 [ANA_INIT] <<<<<<<<<<<<<
2283 11:05:38.403966 [Flow] Enable top DCM control >>>>>
2284 11:05:38.407492 [Flow] Enable top DCM control <<<<<
2285 11:05:38.410517 Enable DLL master slave shuffle
2286 11:05:38.413853 ==============================================================
2287 11:05:38.417344 Gating Mode config
2288 11:05:38.423794 ==============================================================
2289 11:05:38.423877 Config description:
2290 11:05:38.433961 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2291 11:05:38.440765 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2292 11:05:38.443817 SELPH_MODE 0: By rank 1: By Phase
2293 11:05:38.450509 ==============================================================
2294 11:05:38.453969 GAT_TRACK_EN = 1
2295 11:05:38.457003 RX_GATING_MODE = 2
2296 11:05:38.460352 RX_GATING_TRACK_MODE = 2
2297 11:05:38.463756 SELPH_MODE = 1
2298 11:05:38.467104 PICG_EARLY_EN = 1
2299 11:05:38.467187 VALID_LAT_VALUE = 1
2300 11:05:38.473718 ==============================================================
2301 11:05:38.477170 Enter into Gating configuration >>>>
2302 11:05:38.480342 Exit from Gating configuration <<<<
2303 11:05:38.483797 Enter into DVFS_PRE_config >>>>>
2304 11:05:38.493775 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2305 11:05:38.497245 Exit from DVFS_PRE_config <<<<<
2306 11:05:38.500734 Enter into PICG configuration >>>>
2307 11:05:38.503713 Exit from PICG configuration <<<<
2308 11:05:38.507020 [RX_INPUT] configuration >>>>>
2309 11:05:38.510450 [RX_INPUT] configuration <<<<<
2310 11:05:38.513496 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2311 11:05:38.520523 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2312 11:05:38.527290 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2313 11:05:38.533902 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2314 11:05:38.540285 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2315 11:05:38.543713 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2316 11:05:38.550351 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2317 11:05:38.553815 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2318 11:05:38.556960 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2319 11:05:38.560361 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2320 11:05:38.566833 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2321 11:05:38.570381 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2322 11:05:38.573690 ===================================
2323 11:05:38.577060 LPDDR4 DRAM CONFIGURATION
2324 11:05:38.580150 ===================================
2325 11:05:38.580233 EX_ROW_EN[0] = 0x0
2326 11:05:38.583594 EX_ROW_EN[1] = 0x0
2327 11:05:38.583677 LP4Y_EN = 0x0
2328 11:05:38.586774 WORK_FSP = 0x0
2329 11:05:38.586857 WL = 0x4
2330 11:05:38.590253 RL = 0x4
2331 11:05:38.590335 BL = 0x2
2332 11:05:38.593513 RPST = 0x0
2333 11:05:38.593609 RD_PRE = 0x0
2334 11:05:38.596959 WR_PRE = 0x1
2335 11:05:38.600129 WR_PST = 0x0
2336 11:05:38.600212 DBI_WR = 0x0
2337 11:05:38.603516 DBI_RD = 0x0
2338 11:05:38.603598 OTF = 0x1
2339 11:05:38.606703 ===================================
2340 11:05:38.610163 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2341 11:05:38.613634 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2342 11:05:38.620252 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2343 11:05:38.623494 ===================================
2344 11:05:38.626709 LPDDR4 DRAM CONFIGURATION
2345 11:05:38.630160 ===================================
2346 11:05:38.630247 EX_ROW_EN[0] = 0x10
2347 11:05:38.633446 EX_ROW_EN[1] = 0x0
2348 11:05:38.633575 LP4Y_EN = 0x0
2349 11:05:38.636956 WORK_FSP = 0x0
2350 11:05:38.637056 WL = 0x4
2351 11:05:38.640163 RL = 0x4
2352 11:05:38.640270 BL = 0x2
2353 11:05:38.643662 RPST = 0x0
2354 11:05:38.643768 RD_PRE = 0x0
2355 11:05:38.646893 WR_PRE = 0x1
2356 11:05:38.646969 WR_PST = 0x0
2357 11:05:38.650352 DBI_WR = 0x0
2358 11:05:38.650425 DBI_RD = 0x0
2359 11:05:38.653423 OTF = 0x1
2360 11:05:38.656824 ===================================
2361 11:05:38.663470 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2362 11:05:38.663547 ==
2363 11:05:38.666875 Dram Type= 6, Freq= 0, CH_0, rank 0
2364 11:05:38.669947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2365 11:05:38.670020 ==
2366 11:05:38.673631 [Duty_Offset_Calibration]
2367 11:05:38.673713 B0:2 B1:0 CA:3
2368 11:05:38.673782
2369 11:05:38.676632 [DutyScan_Calibration_Flow] k_type=0
2370 11:05:38.687602
2371 11:05:38.687709 ==CLK 0==
2372 11:05:38.690498 Final CLK duty delay cell = 0
2373 11:05:38.694136 [0] MAX Duty = 5031%(X100), DQS PI = 12
2374 11:05:38.697414 [0] MIN Duty = 4906%(X100), DQS PI = 54
2375 11:05:38.697545 [0] AVG Duty = 4968%(X100)
2376 11:05:38.700820
2377 11:05:38.704157 CH0 CLK Duty spec in!! Max-Min= 125%
2378 11:05:38.707211 [DutyScan_Calibration_Flow] ====Done====
2379 11:05:38.707293
2380 11:05:38.710710 [DutyScan_Calibration_Flow] k_type=1
2381 11:05:38.725584
2382 11:05:38.725666 ==DQS 0 ==
2383 11:05:38.729126 Final DQS duty delay cell = 0
2384 11:05:38.732460 [0] MAX Duty = 5062%(X100), DQS PI = 14
2385 11:05:38.735532 [0] MIN Duty = 4907%(X100), DQS PI = 2
2386 11:05:38.738847 [0] AVG Duty = 4984%(X100)
2387 11:05:38.738928
2388 11:05:38.738991 ==DQS 1 ==
2389 11:05:38.742281 Final DQS duty delay cell = -4
2390 11:05:38.745514 [-4] MAX Duty = 4969%(X100), DQS PI = 6
2391 11:05:38.749296 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2392 11:05:38.752232 [-4] AVG Duty = 4922%(X100)
2393 11:05:38.752314
2394 11:05:38.755630 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2395 11:05:38.755726
2396 11:05:38.759112 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2397 11:05:38.762181 [DutyScan_Calibration_Flow] ====Done====
2398 11:05:38.762262
2399 11:05:38.765616 [DutyScan_Calibration_Flow] k_type=3
2400 11:05:38.783142
2401 11:05:38.783222 ==DQM 0 ==
2402 11:05:38.786493 Final DQM duty delay cell = 0
2403 11:05:38.789860 [0] MAX Duty = 5124%(X100), DQS PI = 28
2404 11:05:38.793103 [0] MIN Duty = 4876%(X100), DQS PI = 0
2405 11:05:38.793184 [0] AVG Duty = 5000%(X100)
2406 11:05:38.796607
2407 11:05:38.796688 ==DQM 1 ==
2408 11:05:38.799957 Final DQM duty delay cell = 4
2409 11:05:38.803478 [4] MAX Duty = 5124%(X100), DQS PI = 0
2410 11:05:38.806300 [4] MIN Duty = 5000%(X100), DQS PI = 30
2411 11:05:38.806385 [4] AVG Duty = 5062%(X100)
2412 11:05:38.809631
2413 11:05:38.813132 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2414 11:05:38.813216
2415 11:05:38.816749 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2416 11:05:38.819662 [DutyScan_Calibration_Flow] ====Done====
2417 11:05:38.819750
2418 11:05:38.823146 [DutyScan_Calibration_Flow] k_type=2
2419 11:05:38.837943
2420 11:05:38.838027 ==DQ 0 ==
2421 11:05:38.841437 Final DQ duty delay cell = -4
2422 11:05:38.844563 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2423 11:05:38.848192 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2424 11:05:38.851554 [-4] AVG Duty = 4969%(X100)
2425 11:05:38.851639
2426 11:05:38.851727 ==DQ 1 ==
2427 11:05:38.854588 Final DQ duty delay cell = -4
2428 11:05:38.858007 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2429 11:05:38.861328 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2430 11:05:38.864618 [-4] AVG Duty = 4938%(X100)
2431 11:05:38.864700
2432 11:05:38.868085 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2433 11:05:38.868167
2434 11:05:38.871353 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2435 11:05:38.874809 [DutyScan_Calibration_Flow] ====Done====
2436 11:05:38.874891 ==
2437 11:05:38.878108 Dram Type= 6, Freq= 0, CH_1, rank 0
2438 11:05:38.881200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2439 11:05:38.881283 ==
2440 11:05:38.884561 [Duty_Offset_Calibration]
2441 11:05:38.884643 B0:1 B1:-2 CA:0
2442 11:05:38.884709
2443 11:05:38.888049 [DutyScan_Calibration_Flow] k_type=0
2444 11:05:38.898775
2445 11:05:38.898858 ==CLK 0==
2446 11:05:38.901747 Final CLK duty delay cell = 0
2447 11:05:38.905137 [0] MAX Duty = 5031%(X100), DQS PI = 16
2448 11:05:38.908744 [0] MIN Duty = 4876%(X100), DQS PI = 58
2449 11:05:38.908827 [0] AVG Duty = 4953%(X100)
2450 11:05:38.911977
2451 11:05:38.915449 CH1 CLK Duty spec in!! Max-Min= 155%
2452 11:05:38.918780 [DutyScan_Calibration_Flow] ====Done====
2453 11:05:38.918862
2454 11:05:38.921827 [DutyScan_Calibration_Flow] k_type=1
2455 11:05:38.937306
2456 11:05:38.937388 ==DQS 0 ==
2457 11:05:38.940531 Final DQS duty delay cell = -4
2458 11:05:38.943929 [-4] MAX Duty = 4969%(X100), DQS PI = 8
2459 11:05:38.947111 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2460 11:05:38.950572 [-4] AVG Duty = 4922%(X100)
2461 11:05:38.950655
2462 11:05:38.950720 ==DQS 1 ==
2463 11:05:38.954136 Final DQS duty delay cell = 0
2464 11:05:38.957056 [0] MAX Duty = 5093%(X100), DQS PI = 0
2465 11:05:38.960552 [0] MIN Duty = 4875%(X100), DQS PI = 26
2466 11:05:38.963753 [0] AVG Duty = 4984%(X100)
2467 11:05:38.963835
2468 11:05:38.967185 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2469 11:05:38.967267
2470 11:05:38.970548 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2471 11:05:38.973968 [DutyScan_Calibration_Flow] ====Done====
2472 11:05:38.974050
2473 11:05:38.977255 [DutyScan_Calibration_Flow] k_type=3
2474 11:05:38.993626
2475 11:05:38.993709 ==DQM 0 ==
2476 11:05:38.997010 Final DQM duty delay cell = 0
2477 11:05:39.000347 [0] MAX Duty = 5000%(X100), DQS PI = 22
2478 11:05:39.003709 [0] MIN Duty = 4844%(X100), DQS PI = 56
2479 11:05:39.007329 [0] AVG Duty = 4922%(X100)
2480 11:05:39.007411
2481 11:05:39.007476 ==DQM 1 ==
2482 11:05:39.010324 Final DQM duty delay cell = 0
2483 11:05:39.013536 [0] MAX Duty = 5062%(X100), DQS PI = 38
2484 11:05:39.016911 [0] MIN Duty = 4907%(X100), DQS PI = 2
2485 11:05:39.020586 [0] AVG Duty = 4984%(X100)
2486 11:05:39.020668
2487 11:05:39.023620 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2488 11:05:39.023703
2489 11:05:39.027034 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2490 11:05:39.030486 [DutyScan_Calibration_Flow] ====Done====
2491 11:05:39.030592
2492 11:05:39.033675 [DutyScan_Calibration_Flow] k_type=2
2493 11:05:39.050200
2494 11:05:39.050283 ==DQ 0 ==
2495 11:05:39.053500 Final DQ duty delay cell = 0
2496 11:05:39.056856 [0] MAX Duty = 5093%(X100), DQS PI = 26
2497 11:05:39.060498 [0] MIN Duty = 4907%(X100), DQS PI = 56
2498 11:05:39.060582 [0] AVG Duty = 5000%(X100)
2499 11:05:39.063437
2500 11:05:39.063521 ==DQ 1 ==
2501 11:05:39.067077 Final DQ duty delay cell = 0
2502 11:05:39.070042 [0] MAX Duty = 5125%(X100), DQS PI = 36
2503 11:05:39.073442 [0] MIN Duty = 4969%(X100), DQS PI = 26
2504 11:05:39.073568 [0] AVG Duty = 5047%(X100)
2505 11:05:39.073654
2506 11:05:39.076913 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2507 11:05:39.080213
2508 11:05:39.083602 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2509 11:05:39.086561 [DutyScan_Calibration_Flow] ====Done====
2510 11:05:39.090027 nWR fixed to 30
2511 11:05:39.090112 [ModeRegInit_LP4] CH0 RK0
2512 11:05:39.093378 [ModeRegInit_LP4] CH0 RK1
2513 11:05:39.096827 [ModeRegInit_LP4] CH1 RK0
2514 11:05:39.099941 [ModeRegInit_LP4] CH1 RK1
2515 11:05:39.100026 match AC timing 7
2516 11:05:39.103271 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2517 11:05:39.109840 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2518 11:05:39.113379 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2519 11:05:39.116616 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2520 11:05:39.123161 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2521 11:05:39.123243 ==
2522 11:05:39.126843 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 11:05:39.129780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 11:05:39.129857 ==
2525 11:05:39.136500 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2526 11:05:39.143062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2527 11:05:39.150382 [CA 0] Center 40 (10~71) winsize 62
2528 11:05:39.153427 [CA 1] Center 40 (10~70) winsize 61
2529 11:05:39.156928 [CA 2] Center 36 (6~66) winsize 61
2530 11:05:39.160379 [CA 3] Center 35 (5~66) winsize 62
2531 11:05:39.163904 [CA 4] Center 34 (4~65) winsize 62
2532 11:05:39.166798 [CA 5] Center 33 (3~64) winsize 62
2533 11:05:39.166901
2534 11:05:39.170350 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2535 11:05:39.170431
2536 11:05:39.173791 [CATrainingPosCal] consider 1 rank data
2537 11:05:39.176838 u2DelayCellTimex100 = 270/100 ps
2538 11:05:39.180348 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2539 11:05:39.186896 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2540 11:05:39.190530 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2541 11:05:39.193422 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2542 11:05:39.196779 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2543 11:05:39.200297 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2544 11:05:39.200372
2545 11:05:39.203770 CA PerBit enable=1, Macro0, CA PI delay=33
2546 11:05:39.203841
2547 11:05:39.206808 [CBTSetCACLKResult] CA Dly = 33
2548 11:05:39.210308 CS Dly: 7 (0~38)
2549 11:05:39.210382 ==
2550 11:05:39.213326 Dram Type= 6, Freq= 0, CH_0, rank 1
2551 11:05:39.216866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2552 11:05:39.216948 ==
2553 11:05:39.223169 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2554 11:05:39.226426 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2555 11:05:39.236478 [CA 0] Center 40 (10~70) winsize 61
2556 11:05:39.239638 [CA 1] Center 39 (9~70) winsize 62
2557 11:05:39.243303 [CA 2] Center 35 (5~66) winsize 62
2558 11:05:39.246463 [CA 3] Center 35 (5~66) winsize 62
2559 11:05:39.249717 [CA 4] Center 34 (4~65) winsize 62
2560 11:05:39.253027 [CA 5] Center 33 (3~64) winsize 62
2561 11:05:39.253097
2562 11:05:39.256341 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2563 11:05:39.256418
2564 11:05:39.259717 [CATrainingPosCal] consider 2 rank data
2565 11:05:39.263007 u2DelayCellTimex100 = 270/100 ps
2566 11:05:39.266516 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2567 11:05:39.273034 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2568 11:05:39.276465 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2569 11:05:39.279539 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2570 11:05:39.283128 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2571 11:05:39.286262 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2572 11:05:39.286336
2573 11:05:39.289746 CA PerBit enable=1, Macro0, CA PI delay=33
2574 11:05:39.289824
2575 11:05:39.292817 [CBTSetCACLKResult] CA Dly = 33
2576 11:05:39.296276 CS Dly: 8 (0~40)
2577 11:05:39.296376
2578 11:05:39.299622 ----->DramcWriteLeveling(PI) begin...
2579 11:05:39.299704 ==
2580 11:05:39.303025 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 11:05:39.306129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2582 11:05:39.306208 ==
2583 11:05:39.309620 Write leveling (Byte 0): 34 => 34
2584 11:05:39.313023 Write leveling (Byte 1): 31 => 31
2585 11:05:39.316142 DramcWriteLeveling(PI) end<-----
2586 11:05:39.316214
2587 11:05:39.316276 ==
2588 11:05:39.319661 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 11:05:39.323064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 11:05:39.323146 ==
2591 11:05:39.326460 [Gating] SW mode calibration
2592 11:05:39.332977 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2593 11:05:39.339661 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2594 11:05:39.343148 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 11:05:39.346341 0 15 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2596 11:05:39.353067 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 11:05:39.356523 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 11:05:39.359848 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 11:05:39.363120 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 11:05:39.369633 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 11:05:39.372828 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2602 11:05:39.376519 1 0 0 | B1->B0 | 3232 2929 | 0 0 | (0 1) (0 1)
2603 11:05:39.383315 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 11:05:39.386350 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 11:05:39.389719 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 11:05:39.396376 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 11:05:39.399928 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 11:05:39.403153 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 11:05:39.409423 1 0 28 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
2610 11:05:39.413008 1 1 0 | B1->B0 | 2727 3232 | 0 0 | (0 0) (0 0)
2611 11:05:39.416381 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2612 11:05:39.422707 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 11:05:39.426340 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 11:05:39.429612 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 11:05:39.436154 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 11:05:39.439393 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 11:05:39.443087 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 11:05:39.449443 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2619 11:05:39.452974 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2620 11:05:39.456158 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 11:05:39.462847 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 11:05:39.466310 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 11:05:39.469468 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 11:05:39.472924 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 11:05:39.479470 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 11:05:39.482952 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 11:05:39.486374 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 11:05:39.493146 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 11:05:39.496418 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 11:05:39.499464 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 11:05:39.506297 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 11:05:39.509410 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 11:05:39.512978 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2634 11:05:39.519734 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2635 11:05:39.523124 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2636 11:05:39.526420 Total UI for P1: 0, mck2ui 16
2637 11:05:39.529424 best dqsien dly found for B0: ( 1, 3, 30)
2638 11:05:39.532979 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2639 11:05:39.536274 Total UI for P1: 0, mck2ui 16
2640 11:05:39.539665 best dqsien dly found for B1: ( 1, 4, 4)
2641 11:05:39.543144 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2642 11:05:39.546510 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2643 11:05:39.546599
2644 11:05:39.549841 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2645 11:05:39.553148 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2646 11:05:39.556608 [Gating] SW calibration Done
2647 11:05:39.556690 ==
2648 11:05:39.559743 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 11:05:39.566588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 11:05:39.566671 ==
2651 11:05:39.566736 RX Vref Scan: 0
2652 11:05:39.566796
2653 11:05:39.569647 RX Vref 0 -> 0, step: 1
2654 11:05:39.569729
2655 11:05:39.573352 RX Delay -40 -> 252, step: 8
2656 11:05:39.576679 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2657 11:05:39.580119 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2658 11:05:39.583134 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2659 11:05:39.586710 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2660 11:05:39.593391 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2661 11:05:39.596570 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2662 11:05:39.599642 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2663 11:05:39.603065 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2664 11:05:39.606248 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2665 11:05:39.609654 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2666 11:05:39.616757 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2667 11:05:39.619759 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2668 11:05:39.623080 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2669 11:05:39.626439 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2670 11:05:39.633136 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2671 11:05:39.636507 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2672 11:05:39.636590 ==
2673 11:05:39.639792 Dram Type= 6, Freq= 0, CH_0, rank 0
2674 11:05:39.643069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2675 11:05:39.643165 ==
2676 11:05:39.643280 DQS Delay:
2677 11:05:39.646323 DQS0 = 0, DQS1 = 0
2678 11:05:39.646409 DQM Delay:
2679 11:05:39.649747 DQM0 = 112, DQM1 = 102
2680 11:05:39.649816 DQ Delay:
2681 11:05:39.653076 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2682 11:05:39.656233 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =119
2683 11:05:39.659507 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2684 11:05:39.662962 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2685 11:05:39.663039
2686 11:05:39.666110
2687 11:05:39.666178 ==
2688 11:05:39.669601 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 11:05:39.672820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 11:05:39.672892 ==
2691 11:05:39.672960
2692 11:05:39.673021
2693 11:05:39.676420 TX Vref Scan disable
2694 11:05:39.676496 == TX Byte 0 ==
2695 11:05:39.682951 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2696 11:05:39.686070 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2697 11:05:39.686158 == TX Byte 1 ==
2698 11:05:39.692717 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2699 11:05:39.696296 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2700 11:05:39.696405 ==
2701 11:05:39.699264 Dram Type= 6, Freq= 0, CH_0, rank 0
2702 11:05:39.702811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2703 11:05:39.702895 ==
2704 11:05:39.715076 TX Vref=22, minBit 1, minWin=25, winSum=415
2705 11:05:39.718447 TX Vref=24, minBit 0, minWin=25, winSum=419
2706 11:05:39.721798 TX Vref=26, minBit 3, minWin=26, winSum=429
2707 11:05:39.724898 TX Vref=28, minBit 0, minWin=27, winSum=432
2708 11:05:39.728379 TX Vref=30, minBit 12, minWin=26, winSum=433
2709 11:05:39.735075 TX Vref=32, minBit 1, minWin=26, winSum=427
2710 11:05:39.738444 [TxChooseVref] Worse bit 0, Min win 27, Win sum 432, Final Vref 28
2711 11:05:39.738527
2712 11:05:39.741614 Final TX Range 1 Vref 28
2713 11:05:39.741697
2714 11:05:39.741761 ==
2715 11:05:39.745223 Dram Type= 6, Freq= 0, CH_0, rank 0
2716 11:05:39.748444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2717 11:05:39.751634 ==
2718 11:05:39.751716
2719 11:05:39.751781
2720 11:05:39.751841 TX Vref Scan disable
2721 11:05:39.754951 == TX Byte 0 ==
2722 11:05:39.758478 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2723 11:05:39.765322 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2724 11:05:39.765434 == TX Byte 1 ==
2725 11:05:39.768086 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2726 11:05:39.774996 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2727 11:05:39.775079
2728 11:05:39.775143 [DATLAT]
2729 11:05:39.775203 Freq=1200, CH0 RK0
2730 11:05:39.775261
2731 11:05:39.778321 DATLAT Default: 0xd
2732 11:05:39.778403 0, 0xFFFF, sum = 0
2733 11:05:39.781429 1, 0xFFFF, sum = 0
2734 11:05:39.781558 2, 0xFFFF, sum = 0
2735 11:05:39.784981 3, 0xFFFF, sum = 0
2736 11:05:39.788357 4, 0xFFFF, sum = 0
2737 11:05:39.788452 5, 0xFFFF, sum = 0
2738 11:05:39.791477 6, 0xFFFF, sum = 0
2739 11:05:39.791561 7, 0xFFFF, sum = 0
2740 11:05:39.795085 8, 0xFFFF, sum = 0
2741 11:05:39.795169 9, 0xFFFF, sum = 0
2742 11:05:39.798355 10, 0xFFFF, sum = 0
2743 11:05:39.798439 11, 0xFFFF, sum = 0
2744 11:05:39.801769 12, 0x0, sum = 1
2745 11:05:39.801853 13, 0x0, sum = 2
2746 11:05:39.804730 14, 0x0, sum = 3
2747 11:05:39.804813 15, 0x0, sum = 4
2748 11:05:39.804880 best_step = 13
2749 11:05:39.808369
2750 11:05:39.808451 ==
2751 11:05:39.811675 Dram Type= 6, Freq= 0, CH_0, rank 0
2752 11:05:39.814778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2753 11:05:39.814864 ==
2754 11:05:39.814931 RX Vref Scan: 1
2755 11:05:39.814992
2756 11:05:39.818364 Set Vref Range= 32 -> 127
2757 11:05:39.818473
2758 11:05:39.821535 RX Vref 32 -> 127, step: 1
2759 11:05:39.821618
2760 11:05:39.824949 RX Delay -37 -> 252, step: 4
2761 11:05:39.825031
2762 11:05:39.828234 Set Vref, RX VrefLevel [Byte0]: 32
2763 11:05:39.831614 [Byte1]: 32
2764 11:05:39.831697
2765 11:05:39.834735 Set Vref, RX VrefLevel [Byte0]: 33
2766 11:05:39.838089 [Byte1]: 33
2767 11:05:39.841748
2768 11:05:39.841830 Set Vref, RX VrefLevel [Byte0]: 34
2769 11:05:39.844843 [Byte1]: 34
2770 11:05:39.849483
2771 11:05:39.849595 Set Vref, RX VrefLevel [Byte0]: 35
2772 11:05:39.853025 [Byte1]: 35
2773 11:05:39.857801
2774 11:05:39.857884 Set Vref, RX VrefLevel [Byte0]: 36
2775 11:05:39.861026 [Byte1]: 36
2776 11:05:39.865614
2777 11:05:39.865696 Set Vref, RX VrefLevel [Byte0]: 37
2778 11:05:39.868769 [Byte1]: 37
2779 11:05:39.873577
2780 11:05:39.873660 Set Vref, RX VrefLevel [Byte0]: 38
2781 11:05:39.876734 [Byte1]: 38
2782 11:05:39.881804
2783 11:05:39.881885 Set Vref, RX VrefLevel [Byte0]: 39
2784 11:05:39.884965 [Byte1]: 39
2785 11:05:39.889544
2786 11:05:39.889623 Set Vref, RX VrefLevel [Byte0]: 40
2787 11:05:39.892865 [Byte1]: 40
2788 11:05:39.897452
2789 11:05:39.897579 Set Vref, RX VrefLevel [Byte0]: 41
2790 11:05:39.900902 [Byte1]: 41
2791 11:05:39.905687
2792 11:05:39.905762 Set Vref, RX VrefLevel [Byte0]: 42
2793 11:05:39.908791 [Byte1]: 42
2794 11:05:39.913618
2795 11:05:39.913692 Set Vref, RX VrefLevel [Byte0]: 43
2796 11:05:39.917096 [Byte1]: 43
2797 11:05:39.921709
2798 11:05:39.921792 Set Vref, RX VrefLevel [Byte0]: 44
2799 11:05:39.924856 [Byte1]: 44
2800 11:05:39.929581
2801 11:05:39.929654 Set Vref, RX VrefLevel [Byte0]: 45
2802 11:05:39.932984 [Byte1]: 45
2803 11:05:39.937710
2804 11:05:39.937785 Set Vref, RX VrefLevel [Byte0]: 46
2805 11:05:39.941069 [Byte1]: 46
2806 11:05:39.945690
2807 11:05:39.945765 Set Vref, RX VrefLevel [Byte0]: 47
2808 11:05:39.949121 [Byte1]: 47
2809 11:05:39.953499
2810 11:05:39.953577 Set Vref, RX VrefLevel [Byte0]: 48
2811 11:05:39.956923 [Byte1]: 48
2812 11:05:39.961441
2813 11:05:39.961582 Set Vref, RX VrefLevel [Byte0]: 49
2814 11:05:39.965039 [Byte1]: 49
2815 11:05:39.969743
2816 11:05:39.969823 Set Vref, RX VrefLevel [Byte0]: 50
2817 11:05:39.972968 [Byte1]: 50
2818 11:05:39.977443
2819 11:05:39.977567 Set Vref, RX VrefLevel [Byte0]: 51
2820 11:05:39.980914 [Byte1]: 51
2821 11:05:39.985751
2822 11:05:39.985831 Set Vref, RX VrefLevel [Byte0]: 52
2823 11:05:39.988919 [Byte1]: 52
2824 11:05:39.993470
2825 11:05:39.993586 Set Vref, RX VrefLevel [Byte0]: 53
2826 11:05:39.997110 [Byte1]: 53
2827 11:05:40.001806
2828 11:05:40.001888 Set Vref, RX VrefLevel [Byte0]: 54
2829 11:05:40.004860 [Byte1]: 54
2830 11:05:40.009666
2831 11:05:40.009740 Set Vref, RX VrefLevel [Byte0]: 55
2832 11:05:40.013024 [Byte1]: 55
2833 11:05:40.017825
2834 11:05:40.017899 Set Vref, RX VrefLevel [Byte0]: 56
2835 11:05:40.020820 [Byte1]: 56
2836 11:05:40.025715
2837 11:05:40.025792 Set Vref, RX VrefLevel [Byte0]: 57
2838 11:05:40.028965 [Byte1]: 57
2839 11:05:40.033749
2840 11:05:40.033830 Set Vref, RX VrefLevel [Byte0]: 58
2841 11:05:40.036952 [Byte1]: 58
2842 11:05:40.041417
2843 11:05:40.041516 Set Vref, RX VrefLevel [Byte0]: 59
2844 11:05:40.048032 [Byte1]: 59
2845 11:05:40.048115
2846 11:05:40.051431 Set Vref, RX VrefLevel [Byte0]: 60
2847 11:05:40.054868 [Byte1]: 60
2848 11:05:40.054942
2849 11:05:40.057973 Set Vref, RX VrefLevel [Byte0]: 61
2850 11:05:40.061433 [Byte1]: 61
2851 11:05:40.065651
2852 11:05:40.065726 Set Vref, RX VrefLevel [Byte0]: 62
2853 11:05:40.068805 [Byte1]: 62
2854 11:05:40.073883
2855 11:05:40.073956 Set Vref, RX VrefLevel [Byte0]: 63
2856 11:05:40.076850 [Byte1]: 63
2857 11:05:40.081570
2858 11:05:40.081645 Set Vref, RX VrefLevel [Byte0]: 64
2859 11:05:40.084991 [Byte1]: 64
2860 11:05:40.089774
2861 11:05:40.089854 Set Vref, RX VrefLevel [Byte0]: 65
2862 11:05:40.093070 [Byte1]: 65
2863 11:05:40.097702
2864 11:05:40.097786 Set Vref, RX VrefLevel [Byte0]: 66
2865 11:05:40.100895 [Byte1]: 66
2866 11:05:40.105762
2867 11:05:40.105851 Set Vref, RX VrefLevel [Byte0]: 67
2868 11:05:40.108811 [Byte1]: 67
2869 11:05:40.113752
2870 11:05:40.113825 Set Vref, RX VrefLevel [Byte0]: 68
2871 11:05:40.117103 [Byte1]: 68
2872 11:05:40.121898
2873 11:05:40.121978 Set Vref, RX VrefLevel [Byte0]: 69
2874 11:05:40.125131 [Byte1]: 69
2875 11:05:40.129744
2876 11:05:40.129828 Set Vref, RX VrefLevel [Byte0]: 70
2877 11:05:40.133359 [Byte1]: 70
2878 11:05:40.137718
2879 11:05:40.137798 Set Vref, RX VrefLevel [Byte0]: 71
2880 11:05:40.141089 [Byte1]: 71
2881 11:05:40.145601
2882 11:05:40.145682 Set Vref, RX VrefLevel [Byte0]: 72
2883 11:05:40.149027 [Byte1]: 72
2884 11:05:40.153657
2885 11:05:40.153741 Set Vref, RX VrefLevel [Byte0]: 73
2886 11:05:40.156784 [Byte1]: 73
2887 11:05:40.161715
2888 11:05:40.161791 Final RX Vref Byte 0 = 61 to rank0
2889 11:05:40.164970 Final RX Vref Byte 1 = 54 to rank0
2890 11:05:40.168424 Final RX Vref Byte 0 = 61 to rank1
2891 11:05:40.171542 Final RX Vref Byte 1 = 54 to rank1==
2892 11:05:40.175112 Dram Type= 6, Freq= 0, CH_0, rank 0
2893 11:05:40.181748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2894 11:05:40.181823 ==
2895 11:05:40.181886 DQS Delay:
2896 11:05:40.181951 DQS0 = 0, DQS1 = 0
2897 11:05:40.184767 DQM Delay:
2898 11:05:40.184836 DQM0 = 111, DQM1 = 101
2899 11:05:40.188415 DQ Delay:
2900 11:05:40.191589 DQ0 =112, DQ1 =110, DQ2 =110, DQ3 =108
2901 11:05:40.194941 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2902 11:05:40.197991 DQ8 =92, DQ9 =86, DQ10 =104, DQ11 =94
2903 11:05:40.201419 DQ12 =108, DQ13 =106, DQ14 =116, DQ15 =108
2904 11:05:40.201510
2905 11:05:40.201577
2906 11:05:40.208119 [DQSOSCAuto] RK0, (LSB)MR18= 0xfefe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2907 11:05:40.211721 CH0 RK0: MR19=303, MR18=FEFE
2908 11:05:40.217976 CH0_RK0: MR19=0x303, MR18=0xFEFE, DQSOSC=410, MR23=63, INC=39, DEC=26
2909 11:05:40.218059
2910 11:05:40.221464 ----->DramcWriteLeveling(PI) begin...
2911 11:05:40.221611 ==
2912 11:05:40.224964 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 11:05:40.228169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 11:05:40.231431 ==
2915 11:05:40.231514 Write leveling (Byte 0): 33 => 33
2916 11:05:40.234932 Write leveling (Byte 1): 30 => 30
2917 11:05:40.238453 DramcWriteLeveling(PI) end<-----
2918 11:05:40.238535
2919 11:05:40.238600 ==
2920 11:05:40.241877 Dram Type= 6, Freq= 0, CH_0, rank 1
2921 11:05:40.248301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2922 11:05:40.248383 ==
2923 11:05:40.248449 [Gating] SW mode calibration
2924 11:05:40.258000 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2925 11:05:40.261489 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2926 11:05:40.264788 0 15 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2927 11:05:40.271923 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 11:05:40.274837 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 11:05:40.278332 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2930 11:05:40.284923 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2931 11:05:40.288517 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2932 11:05:40.291617 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2933 11:05:40.298370 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
2934 11:05:40.301497 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
2935 11:05:40.304708 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 11:05:40.311630 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 11:05:40.314704 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2938 11:05:40.318054 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2939 11:05:40.324777 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2940 11:05:40.328295 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
2941 11:05:40.331353 1 0 28 | B1->B0 | 2424 4343 | 0 0 | (0 0) (0 0)
2942 11:05:40.338042 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2943 11:05:40.341435 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 11:05:40.344837 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 11:05:40.351462 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 11:05:40.354656 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 11:05:40.358118 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 11:05:40.361607 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2949 11:05:40.367984 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2950 11:05:40.371406 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 11:05:40.374842 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 11:05:40.381382 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 11:05:40.384624 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 11:05:40.387746 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 11:05:40.394566 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 11:05:40.397774 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 11:05:40.401323 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 11:05:40.407962 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 11:05:40.411030 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 11:05:40.414443 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 11:05:40.421072 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 11:05:40.424362 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 11:05:40.427840 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 11:05:40.434461 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2965 11:05:40.437703 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2966 11:05:40.440742 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 11:05:40.444383 Total UI for P1: 0, mck2ui 16
2968 11:05:40.447481 best dqsien dly found for B0: ( 1, 3, 26)
2969 11:05:40.451096 Total UI for P1: 0, mck2ui 16
2970 11:05:40.454301 best dqsien dly found for B1: ( 1, 3, 30)
2971 11:05:40.457752 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2972 11:05:40.460841 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2973 11:05:40.460923
2974 11:05:40.467429 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2975 11:05:40.471035 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2976 11:05:40.471113 [Gating] SW calibration Done
2977 11:05:40.474178 ==
2978 11:05:40.477687 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 11:05:40.480757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 11:05:40.480831 ==
2981 11:05:40.480896 RX Vref Scan: 0
2982 11:05:40.480960
2983 11:05:40.484466 RX Vref 0 -> 0, step: 1
2984 11:05:40.484540
2985 11:05:40.487679 RX Delay -40 -> 252, step: 8
2986 11:05:40.490747 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2987 11:05:40.494279 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2988 11:05:40.497421 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2989 11:05:40.504066 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2990 11:05:40.507573 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2991 11:05:40.510705 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2992 11:05:40.513879 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2993 11:05:40.517417 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2994 11:05:40.524036 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2995 11:05:40.527307 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2996 11:05:40.530666 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2997 11:05:40.534083 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2998 11:05:40.537288 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2999 11:05:40.544408 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3000 11:05:40.547401 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3001 11:05:40.550863 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3002 11:05:40.550939 ==
3003 11:05:40.554362 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 11:05:40.557608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 11:05:40.557683 ==
3006 11:05:40.560772 DQS Delay:
3007 11:05:40.560838 DQS0 = 0, DQS1 = 0
3008 11:05:40.564385 DQM Delay:
3009 11:05:40.564456 DQM0 = 111, DQM1 = 102
3010 11:05:40.564517 DQ Delay:
3011 11:05:40.567456 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
3012 11:05:40.570983 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
3013 11:05:40.574424 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3014 11:05:40.580880 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3015 11:05:40.580949
3016 11:05:40.581008
3017 11:05:40.581072 ==
3018 11:05:40.584212 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 11:05:40.587435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 11:05:40.587504 ==
3021 11:05:40.587569
3022 11:05:40.587628
3023 11:05:40.591143 TX Vref Scan disable
3024 11:05:40.591219 == TX Byte 0 ==
3025 11:05:40.597783 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3026 11:05:40.600945 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3027 11:05:40.601020 == TX Byte 1 ==
3028 11:05:40.607477 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3029 11:05:40.610843 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3030 11:05:40.610917 ==
3031 11:05:40.614151 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 11:05:40.617385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 11:05:40.617463 ==
3034 11:05:40.630469 TX Vref=22, minBit 2, minWin=26, winSum=430
3035 11:05:40.633726 TX Vref=24, minBit 2, minWin=26, winSum=434
3036 11:05:40.637216 TX Vref=26, minBit 8, minWin=26, winSum=434
3037 11:05:40.640265 TX Vref=28, minBit 0, minWin=27, winSum=440
3038 11:05:40.643742 TX Vref=30, minBit 10, minWin=26, winSum=441
3039 11:05:40.650592 TX Vref=32, minBit 8, minWin=26, winSum=440
3040 11:05:40.653762 [TxChooseVref] Worse bit 0, Min win 27, Win sum 440, Final Vref 28
3041 11:05:40.653841
3042 11:05:40.657287 Final TX Range 1 Vref 28
3043 11:05:40.657364
3044 11:05:40.657461 ==
3045 11:05:40.660425 Dram Type= 6, Freq= 0, CH_0, rank 1
3046 11:05:40.663651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 11:05:40.663740 ==
3048 11:05:40.667107
3049 11:05:40.667189
3050 11:05:40.667253 TX Vref Scan disable
3051 11:05:40.670714 == TX Byte 0 ==
3052 11:05:40.673524 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3053 11:05:40.677150 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3054 11:05:40.680458 == TX Byte 1 ==
3055 11:05:40.683669 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3056 11:05:40.687153 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3057 11:05:40.690275
3058 11:05:40.690357 [DATLAT]
3059 11:05:40.690422 Freq=1200, CH0 RK1
3060 11:05:40.690482
3061 11:05:40.693844 DATLAT Default: 0xd
3062 11:05:40.693926 0, 0xFFFF, sum = 0
3063 11:05:40.697177 1, 0xFFFF, sum = 0
3064 11:05:40.697261 2, 0xFFFF, sum = 0
3065 11:05:40.700306 3, 0xFFFF, sum = 0
3066 11:05:40.700390 4, 0xFFFF, sum = 0
3067 11:05:40.703744 5, 0xFFFF, sum = 0
3068 11:05:40.706887 6, 0xFFFF, sum = 0
3069 11:05:40.706972 7, 0xFFFF, sum = 0
3070 11:05:40.710366 8, 0xFFFF, sum = 0
3071 11:05:40.710449 9, 0xFFFF, sum = 0
3072 11:05:40.713790 10, 0xFFFF, sum = 0
3073 11:05:40.713887 11, 0xFFFF, sum = 0
3074 11:05:40.716844 12, 0x0, sum = 1
3075 11:05:40.716927 13, 0x0, sum = 2
3076 11:05:40.720257 14, 0x0, sum = 3
3077 11:05:40.720341 15, 0x0, sum = 4
3078 11:05:40.720408 best_step = 13
3079 11:05:40.720469
3080 11:05:40.723514 ==
3081 11:05:40.726882 Dram Type= 6, Freq= 0, CH_0, rank 1
3082 11:05:40.730305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 11:05:40.730387 ==
3084 11:05:40.730451 RX Vref Scan: 0
3085 11:05:40.730512
3086 11:05:40.733772 RX Vref 0 -> 0, step: 1
3087 11:05:40.733853
3088 11:05:40.736901 RX Delay -37 -> 252, step: 4
3089 11:05:40.740347 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3090 11:05:40.747040 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3091 11:05:40.750414 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3092 11:05:40.753782 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3093 11:05:40.756993 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3094 11:05:40.760308 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3095 11:05:40.766863 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3096 11:05:40.770072 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3097 11:05:40.773395 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3098 11:05:40.777052 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3099 11:05:40.780049 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3100 11:05:40.783751 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3101 11:05:40.790353 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3102 11:05:40.793781 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3103 11:05:40.796902 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3104 11:05:40.800301 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3105 11:05:40.800385 ==
3106 11:05:40.803704 Dram Type= 6, Freq= 0, CH_0, rank 1
3107 11:05:40.810249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 11:05:40.810333 ==
3109 11:05:40.810398 DQS Delay:
3110 11:05:40.810458 DQS0 = 0, DQS1 = 0
3111 11:05:40.813806 DQM Delay:
3112 11:05:40.813888 DQM0 = 111, DQM1 = 101
3113 11:05:40.817123 DQ Delay:
3114 11:05:40.820257 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3115 11:05:40.823642 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3116 11:05:40.827137 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3117 11:05:40.830568 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3118 11:05:40.830650
3119 11:05:40.830715
3120 11:05:40.837102 [DQSOSCAuto] RK1, (LSB)MR18= 0x15fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 401 ps
3121 11:05:40.840356 CH0 RK1: MR19=403, MR18=15FC
3122 11:05:40.847182 CH0_RK1: MR19=0x403, MR18=0x15FC, DQSOSC=401, MR23=63, INC=40, DEC=27
3123 11:05:40.850490 [RxdqsGatingPostProcess] freq 1200
3124 11:05:40.856907 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3125 11:05:40.860507 best DQS0 dly(2T, 0.5T) = (0, 11)
3126 11:05:40.860589 best DQS1 dly(2T, 0.5T) = (0, 12)
3127 11:05:40.863554 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3128 11:05:40.867238 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3129 11:05:40.870519 best DQS0 dly(2T, 0.5T) = (0, 11)
3130 11:05:40.873624 best DQS1 dly(2T, 0.5T) = (0, 11)
3131 11:05:40.877004 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3132 11:05:40.880353 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3133 11:05:40.883722 Pre-setting of DQS Precalculation
3134 11:05:40.890378 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3135 11:05:40.890461 ==
3136 11:05:40.893531 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 11:05:40.897005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 11:05:40.897089 ==
3139 11:05:40.903704 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3140 11:05:40.906994 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3141 11:05:40.916391 [CA 0] Center 37 (7~67) winsize 61
3142 11:05:40.919844 [CA 1] Center 37 (7~68) winsize 62
3143 11:05:40.923045 [CA 2] Center 34 (4~64) winsize 61
3144 11:05:40.926478 [CA 3] Center 34 (4~64) winsize 61
3145 11:05:40.929907 [CA 4] Center 34 (4~64) winsize 61
3146 11:05:40.932967 [CA 5] Center 33 (3~63) winsize 61
3147 11:05:40.933048
3148 11:05:40.936326 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3149 11:05:40.936401
3150 11:05:40.939830 [CATrainingPosCal] consider 1 rank data
3151 11:05:40.943416 u2DelayCellTimex100 = 270/100 ps
3152 11:05:40.946449 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3153 11:05:40.949876 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3154 11:05:40.956466 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3155 11:05:40.959911 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3156 11:05:40.962972 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3157 11:05:40.966358 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3158 11:05:40.966440
3159 11:05:40.969891 CA PerBit enable=1, Macro0, CA PI delay=33
3160 11:05:40.969973
3161 11:05:40.972940 [CBTSetCACLKResult] CA Dly = 33
3162 11:05:40.973023 CS Dly: 5 (0~36)
3163 11:05:40.973088 ==
3164 11:05:40.976532 Dram Type= 6, Freq= 0, CH_1, rank 1
3165 11:05:40.983206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3166 11:05:40.983289 ==
3167 11:05:40.986295 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3168 11:05:40.992847 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3169 11:05:41.001852 [CA 0] Center 37 (8~67) winsize 60
3170 11:05:41.005310 [CA 1] Center 37 (7~68) winsize 62
3171 11:05:41.008522 [CA 2] Center 34 (4~65) winsize 62
3172 11:05:41.011912 [CA 3] Center 33 (3~64) winsize 62
3173 11:05:41.015095 [CA 4] Center 34 (4~65) winsize 62
3174 11:05:41.018537 [CA 5] Center 32 (2~63) winsize 62
3175 11:05:41.018620
3176 11:05:41.021979 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3177 11:05:41.022062
3178 11:05:41.025425 [CATrainingPosCal] consider 2 rank data
3179 11:05:41.028460 u2DelayCellTimex100 = 270/100 ps
3180 11:05:41.032048 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3181 11:05:41.035300 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3182 11:05:41.041859 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3183 11:05:41.045313 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3184 11:05:41.048429 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3185 11:05:41.051951 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3186 11:05:41.052033
3187 11:05:41.055417 CA PerBit enable=1, Macro0, CA PI delay=33
3188 11:05:41.055499
3189 11:05:41.058481 [CBTSetCACLKResult] CA Dly = 33
3190 11:05:41.058563 CS Dly: 6 (0~39)
3191 11:05:41.058628
3192 11:05:41.061805 ----->DramcWriteLeveling(PI) begin...
3193 11:05:41.065431 ==
3194 11:05:41.068509 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 11:05:41.071803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 11:05:41.071886 ==
3197 11:05:41.075296 Write leveling (Byte 0): 26 => 26
3198 11:05:41.078748 Write leveling (Byte 1): 26 => 26
3199 11:05:41.081881 DramcWriteLeveling(PI) end<-----
3200 11:05:41.081964
3201 11:05:41.082029 ==
3202 11:05:41.085020 Dram Type= 6, Freq= 0, CH_1, rank 0
3203 11:05:41.088561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 11:05:41.088645 ==
3205 11:05:41.091838 [Gating] SW mode calibration
3206 11:05:41.098407 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3207 11:05:41.101844 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3208 11:05:41.108418 0 15 0 | B1->B0 | 3131 2928 | 1 1 | (1 1) (0 0)
3209 11:05:41.111762 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 11:05:41.115203 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 11:05:41.121804 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 11:05:41.125227 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3213 11:05:41.128368 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3214 11:05:41.135005 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3215 11:05:41.138321 0 15 28 | B1->B0 | 2f2f 2e2e | 0 0 | (1 0) (0 1)
3216 11:05:41.141936 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3217 11:05:41.148520 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 11:05:41.151810 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 11:05:41.154939 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 11:05:41.161689 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 11:05:41.165265 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3222 11:05:41.168353 1 0 24 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
3223 11:05:41.175189 1 0 28 | B1->B0 | 3838 3636 | 0 0 | (0 0) (0 0)
3224 11:05:41.178642 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 11:05:41.181614 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 11:05:41.188215 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 11:05:41.191657 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 11:05:41.195063 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 11:05:41.201792 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 11:05:41.204862 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 11:05:41.208331 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3232 11:05:41.215031 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3233 11:05:41.218061 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 11:05:41.221706 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 11:05:41.228061 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 11:05:41.231685 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 11:05:41.234705 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 11:05:41.238364 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 11:05:41.245002 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 11:05:41.248401 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 11:05:41.251327 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 11:05:41.258249 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 11:05:41.261484 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 11:05:41.264794 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 11:05:41.271244 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 11:05:41.274813 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 11:05:41.277888 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3248 11:05:41.284670 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3249 11:05:41.284778 Total UI for P1: 0, mck2ui 16
3250 11:05:41.291509 best dqsien dly found for B1: ( 1, 3, 28)
3251 11:05:41.294697 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3252 11:05:41.298298 Total UI for P1: 0, mck2ui 16
3253 11:05:41.301628 best dqsien dly found for B0: ( 1, 3, 30)
3254 11:05:41.304690 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3255 11:05:41.308034 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3256 11:05:41.308115
3257 11:05:41.311767 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3258 11:05:41.314650 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3259 11:05:41.318028 [Gating] SW calibration Done
3260 11:05:41.318135 ==
3261 11:05:41.321501 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 11:05:41.324936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 11:05:41.325044 ==
3264 11:05:41.328040 RX Vref Scan: 0
3265 11:05:41.328122
3266 11:05:41.331483 RX Vref 0 -> 0, step: 1
3267 11:05:41.331580
3268 11:05:41.331643 RX Delay -40 -> 252, step: 8
3269 11:05:41.337952 iDelay=200, Bit 0, Center 119 (40 ~ 199) 160
3270 11:05:41.341353 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3271 11:05:41.344670 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3272 11:05:41.348194 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3273 11:05:41.351322 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3274 11:05:41.358115 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3275 11:05:41.361320 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3276 11:05:41.364726 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3277 11:05:41.367968 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3278 11:05:41.371295 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3279 11:05:41.378319 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3280 11:05:41.381469 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3281 11:05:41.384886 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3282 11:05:41.388352 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3283 11:05:41.391377 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3284 11:05:41.398218 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3285 11:05:41.398300 ==
3286 11:05:41.401457 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 11:05:41.404940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 11:05:41.405022 ==
3289 11:05:41.405087 DQS Delay:
3290 11:05:41.408309 DQS0 = 0, DQS1 = 0
3291 11:05:41.408390 DQM Delay:
3292 11:05:41.411750 DQM0 = 113, DQM1 = 105
3293 11:05:41.411831 DQ Delay:
3294 11:05:41.414795 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =111
3295 11:05:41.418199 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3296 11:05:41.421784 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
3297 11:05:41.424734 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3298 11:05:41.424815
3299 11:05:41.424879
3300 11:05:41.428155 ==
3301 11:05:41.428237 Dram Type= 6, Freq= 0, CH_1, rank 0
3302 11:05:41.434783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3303 11:05:41.434865 ==
3304 11:05:41.434929
3305 11:05:41.434989
3306 11:05:41.435046 TX Vref Scan disable
3307 11:05:41.438665 == TX Byte 0 ==
3308 11:05:41.442124 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3309 11:05:41.448765 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3310 11:05:41.448847 == TX Byte 1 ==
3311 11:05:41.451838 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3312 11:05:41.458861 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3313 11:05:41.458943 ==
3314 11:05:41.461773 Dram Type= 6, Freq= 0, CH_1, rank 0
3315 11:05:41.465396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3316 11:05:41.465556 ==
3317 11:05:41.476432 TX Vref=22, minBit 10, minWin=24, winSum=407
3318 11:05:41.479760 TX Vref=24, minBit 10, minWin=24, winSum=408
3319 11:05:41.483247 TX Vref=26, minBit 10, minWin=24, winSum=418
3320 11:05:41.486621 TX Vref=28, minBit 9, minWin=25, winSum=418
3321 11:05:41.489638 TX Vref=30, minBit 9, minWin=25, winSum=421
3322 11:05:41.496608 TX Vref=32, minBit 9, minWin=25, winSum=417
3323 11:05:41.499790 [TxChooseVref] Worse bit 9, Min win 25, Win sum 421, Final Vref 30
3324 11:05:41.499873
3325 11:05:41.503199 Final TX Range 1 Vref 30
3326 11:05:41.503282
3327 11:05:41.503346 ==
3328 11:05:41.506727 Dram Type= 6, Freq= 0, CH_1, rank 0
3329 11:05:41.509870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3330 11:05:41.509952 ==
3331 11:05:41.513331
3332 11:05:41.513436
3333 11:05:41.513570 TX Vref Scan disable
3334 11:05:41.516400 == TX Byte 0 ==
3335 11:05:41.519848 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3336 11:05:41.523197 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3337 11:05:41.526533 == TX Byte 1 ==
3338 11:05:41.530034 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3339 11:05:41.533001 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3340 11:05:41.536543
3341 11:05:41.536625 [DATLAT]
3342 11:05:41.536690 Freq=1200, CH1 RK0
3343 11:05:41.536751
3344 11:05:41.540032 DATLAT Default: 0xd
3345 11:05:41.540114 0, 0xFFFF, sum = 0
3346 11:05:41.543109 1, 0xFFFF, sum = 0
3347 11:05:41.543197 2, 0xFFFF, sum = 0
3348 11:05:41.546286 3, 0xFFFF, sum = 0
3349 11:05:41.549842 4, 0xFFFF, sum = 0
3350 11:05:41.549926 5, 0xFFFF, sum = 0
3351 11:05:41.553071 6, 0xFFFF, sum = 0
3352 11:05:41.553154 7, 0xFFFF, sum = 0
3353 11:05:41.556611 8, 0xFFFF, sum = 0
3354 11:05:41.556695 9, 0xFFFF, sum = 0
3355 11:05:41.559739 10, 0xFFFF, sum = 0
3356 11:05:41.559822 11, 0xFFFF, sum = 0
3357 11:05:41.562884 12, 0x0, sum = 1
3358 11:05:41.562967 13, 0x0, sum = 2
3359 11:05:41.566350 14, 0x0, sum = 3
3360 11:05:41.566433 15, 0x0, sum = 4
3361 11:05:41.566499 best_step = 13
3362 11:05:41.569775
3363 11:05:41.569856 ==
3364 11:05:41.573055 Dram Type= 6, Freq= 0, CH_1, rank 0
3365 11:05:41.576479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3366 11:05:41.576561 ==
3367 11:05:41.576626 RX Vref Scan: 1
3368 11:05:41.576686
3369 11:05:41.579770 Set Vref Range= 32 -> 127
3370 11:05:41.579852
3371 11:05:41.583131 RX Vref 32 -> 127, step: 1
3372 11:05:41.583212
3373 11:05:41.586562 RX Delay -21 -> 252, step: 4
3374 11:05:41.586643
3375 11:05:41.589522 Set Vref, RX VrefLevel [Byte0]: 32
3376 11:05:41.593121 [Byte1]: 32
3377 11:05:41.593202
3378 11:05:41.596500 Set Vref, RX VrefLevel [Byte0]: 33
3379 11:05:41.599748 [Byte1]: 33
3380 11:05:41.599831
3381 11:05:41.603337 Set Vref, RX VrefLevel [Byte0]: 34
3382 11:05:41.606257 [Byte1]: 34
3383 11:05:41.611029
3384 11:05:41.611111 Set Vref, RX VrefLevel [Byte0]: 35
3385 11:05:41.614062 [Byte1]: 35
3386 11:05:41.619047
3387 11:05:41.619128 Set Vref, RX VrefLevel [Byte0]: 36
3388 11:05:41.621954 [Byte1]: 36
3389 11:05:41.626619
3390 11:05:41.626701 Set Vref, RX VrefLevel [Byte0]: 37
3391 11:05:41.629854 [Byte1]: 37
3392 11:05:41.634813
3393 11:05:41.634894 Set Vref, RX VrefLevel [Byte0]: 38
3394 11:05:41.637820 [Byte1]: 38
3395 11:05:41.642595
3396 11:05:41.642677 Set Vref, RX VrefLevel [Byte0]: 39
3397 11:05:41.645806 [Byte1]: 39
3398 11:05:41.650397
3399 11:05:41.650478 Set Vref, RX VrefLevel [Byte0]: 40
3400 11:05:41.653804 [Byte1]: 40
3401 11:05:41.658438
3402 11:05:41.658519 Set Vref, RX VrefLevel [Byte0]: 41
3403 11:05:41.661435 [Byte1]: 41
3404 11:05:41.666114
3405 11:05:41.666195 Set Vref, RX VrefLevel [Byte0]: 42
3406 11:05:41.669750 [Byte1]: 42
3407 11:05:41.674061
3408 11:05:41.674142 Set Vref, RX VrefLevel [Byte0]: 43
3409 11:05:41.677383 [Byte1]: 43
3410 11:05:41.681997
3411 11:05:41.682077 Set Vref, RX VrefLevel [Byte0]: 44
3412 11:05:41.685438 [Byte1]: 44
3413 11:05:41.689833
3414 11:05:41.689914 Set Vref, RX VrefLevel [Byte0]: 45
3415 11:05:41.693317 [Byte1]: 45
3416 11:05:41.698094
3417 11:05:41.698175 Set Vref, RX VrefLevel [Byte0]: 46
3418 11:05:41.701117 [Byte1]: 46
3419 11:05:41.705985
3420 11:05:41.706066 Set Vref, RX VrefLevel [Byte0]: 47
3421 11:05:41.709216 [Byte1]: 47
3422 11:05:41.713847
3423 11:05:41.713926 Set Vref, RX VrefLevel [Byte0]: 48
3424 11:05:41.717177 [Byte1]: 48
3425 11:05:41.721642
3426 11:05:41.721714 Set Vref, RX VrefLevel [Byte0]: 49
3427 11:05:41.725041 [Byte1]: 49
3428 11:05:41.729467
3429 11:05:41.729585 Set Vref, RX VrefLevel [Byte0]: 50
3430 11:05:41.732863 [Byte1]: 50
3431 11:05:41.737659
3432 11:05:41.737741 Set Vref, RX VrefLevel [Byte0]: 51
3433 11:05:41.740981 [Byte1]: 51
3434 11:05:41.745387
3435 11:05:41.745469 Set Vref, RX VrefLevel [Byte0]: 52
3436 11:05:41.748963 [Byte1]: 52
3437 11:05:41.753418
3438 11:05:41.753505 Set Vref, RX VrefLevel [Byte0]: 53
3439 11:05:41.756745 [Byte1]: 53
3440 11:05:41.761456
3441 11:05:41.761576 Set Vref, RX VrefLevel [Byte0]: 54
3442 11:05:41.764642 [Byte1]: 54
3443 11:05:41.769390
3444 11:05:41.769495 Set Vref, RX VrefLevel [Byte0]: 55
3445 11:05:41.772569 [Byte1]: 55
3446 11:05:41.777417
3447 11:05:41.777520 Set Vref, RX VrefLevel [Byte0]: 56
3448 11:05:41.780350 [Byte1]: 56
3449 11:05:41.785250
3450 11:05:41.785331 Set Vref, RX VrefLevel [Byte0]: 57
3451 11:05:41.788410 [Byte1]: 57
3452 11:05:41.793016
3453 11:05:41.793098 Set Vref, RX VrefLevel [Byte0]: 58
3454 11:05:41.796174 [Byte1]: 58
3455 11:05:41.800997
3456 11:05:41.801080 Set Vref, RX VrefLevel [Byte0]: 59
3457 11:05:41.804081 [Byte1]: 59
3458 11:05:41.808898
3459 11:05:41.809010 Set Vref, RX VrefLevel [Byte0]: 60
3460 11:05:41.812134 [Byte1]: 60
3461 11:05:41.816550
3462 11:05:41.816632 Set Vref, RX VrefLevel [Byte0]: 61
3463 11:05:41.820282 [Byte1]: 61
3464 11:05:41.824699
3465 11:05:41.824781 Set Vref, RX VrefLevel [Byte0]: 62
3466 11:05:41.828071 [Byte1]: 62
3467 11:05:41.832446
3468 11:05:41.832528 Set Vref, RX VrefLevel [Byte0]: 63
3469 11:05:41.835674 [Byte1]: 63
3470 11:05:41.840316
3471 11:05:41.840414 Set Vref, RX VrefLevel [Byte0]: 64
3472 11:05:41.843715 [Byte1]: 64
3473 11:05:41.848331
3474 11:05:41.848413 Set Vref, RX VrefLevel [Byte0]: 65
3475 11:05:41.851553 [Byte1]: 65
3476 11:05:41.856508
3477 11:05:41.856590 Final RX Vref Byte 0 = 59 to rank0
3478 11:05:41.859667 Final RX Vref Byte 1 = 51 to rank0
3479 11:05:41.863144 Final RX Vref Byte 0 = 59 to rank1
3480 11:05:41.866406 Final RX Vref Byte 1 = 51 to rank1==
3481 11:05:41.869554 Dram Type= 6, Freq= 0, CH_1, rank 0
3482 11:05:41.876154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3483 11:05:41.876236 ==
3484 11:05:41.876302 DQS Delay:
3485 11:05:41.876362 DQS0 = 0, DQS1 = 0
3486 11:05:41.879667 DQM Delay:
3487 11:05:41.879774 DQM0 = 114, DQM1 = 106
3488 11:05:41.882877 DQ Delay:
3489 11:05:41.886322 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =112
3490 11:05:41.889818 DQ4 =110, DQ5 =124, DQ6 =124, DQ7 =110
3491 11:05:41.892894 DQ8 =92, DQ9 =100, DQ10 =106, DQ11 =100
3492 11:05:41.896422 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =114
3493 11:05:41.896504
3494 11:05:41.896602
3495 11:05:41.903029 [DQSOSCAuto] RK0, (LSB)MR18= 0xecf3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3496 11:05:41.906165 CH1 RK0: MR19=303, MR18=ECF3
3497 11:05:41.913001 CH1_RK0: MR19=0x303, MR18=0xECF3, DQSOSC=415, MR23=63, INC=38, DEC=25
3498 11:05:41.913083
3499 11:05:41.916286 ----->DramcWriteLeveling(PI) begin...
3500 11:05:41.916369 ==
3501 11:05:41.919614 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 11:05:41.923155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 11:05:41.926121 ==
3504 11:05:41.926203 Write leveling (Byte 0): 23 => 23
3505 11:05:41.929759 Write leveling (Byte 1): 27 => 27
3506 11:05:41.933175 DramcWriteLeveling(PI) end<-----
3507 11:05:41.933257
3508 11:05:41.933322 ==
3509 11:05:41.936393 Dram Type= 6, Freq= 0, CH_1, rank 1
3510 11:05:41.942850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3511 11:05:41.942933 ==
3512 11:05:41.946392 [Gating] SW mode calibration
3513 11:05:41.952942 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3514 11:05:41.956001 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3515 11:05:41.962799 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3516 11:05:41.965934 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 11:05:41.969534 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 11:05:41.976190 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 11:05:41.979380 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 11:05:41.982814 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 11:05:41.986296 0 15 24 | B1->B0 | 3434 2424 | 1 0 | (0 1) (1 0)
3522 11:05:41.992879 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3523 11:05:41.996062 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 11:05:41.999512 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 11:05:42.005824 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 11:05:42.009427 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 11:05:42.012650 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 11:05:42.019463 1 0 20 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
3529 11:05:42.022776 1 0 24 | B1->B0 | 2929 4545 | 0 0 | (0 0) (0 0)
3530 11:05:42.025927 1 0 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3531 11:05:42.032500 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 11:05:42.036232 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 11:05:42.039439 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 11:05:42.046121 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 11:05:42.049388 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 11:05:42.052404 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3537 11:05:42.059152 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3538 11:05:42.062392 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3539 11:05:42.065861 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 11:05:42.072360 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 11:05:42.075718 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 11:05:42.078941 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 11:05:42.085784 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 11:05:42.088889 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 11:05:42.092385 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 11:05:42.098981 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 11:05:42.102213 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 11:05:42.105686 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 11:05:42.112062 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 11:05:42.115564 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 11:05:42.118896 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 11:05:42.125509 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 11:05:42.128789 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3554 11:05:42.132138 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3555 11:05:42.135483 Total UI for P1: 0, mck2ui 16
3556 11:05:42.138762 best dqsien dly found for B0: ( 1, 3, 24)
3557 11:05:42.141912 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 11:05:42.145070 Total UI for P1: 0, mck2ui 16
3559 11:05:42.148406 best dqsien dly found for B1: ( 1, 3, 26)
3560 11:05:42.155292 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3561 11:05:42.158538 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3562 11:05:42.158620
3563 11:05:42.161851 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3564 11:05:42.165272 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3565 11:05:42.168334 [Gating] SW calibration Done
3566 11:05:42.168417 ==
3567 11:05:42.171794 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 11:05:42.174972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 11:05:42.175054 ==
3570 11:05:42.178604 RX Vref Scan: 0
3571 11:05:42.178687
3572 11:05:42.178751 RX Vref 0 -> 0, step: 1
3573 11:05:42.178811
3574 11:05:42.181875 RX Delay -40 -> 252, step: 8
3575 11:05:42.184885 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
3576 11:05:42.191614 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3577 11:05:42.195088 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3578 11:05:42.198213 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3579 11:05:42.201694 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3580 11:05:42.204837 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3581 11:05:42.208147 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3582 11:05:42.214949 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3583 11:05:42.218321 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3584 11:05:42.221635 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3585 11:05:42.224909 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3586 11:05:42.227947 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3587 11:05:42.235001 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3588 11:05:42.237862 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3589 11:05:42.241230 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3590 11:05:42.244602 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3591 11:05:42.244706 ==
3592 11:05:42.248102 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 11:05:42.254764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 11:05:42.254847 ==
3595 11:05:42.254913 DQS Delay:
3596 11:05:42.258036 DQS0 = 0, DQS1 = 0
3597 11:05:42.258118 DQM Delay:
3598 11:05:42.261398 DQM0 = 110, DQM1 = 108
3599 11:05:42.261501 DQ Delay:
3600 11:05:42.264593 DQ0 =111, DQ1 =107, DQ2 =99, DQ3 =107
3601 11:05:42.267825 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3602 11:05:42.271260 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3603 11:05:42.274516 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =111
3604 11:05:42.274599
3605 11:05:42.274663
3606 11:05:42.274723 ==
3607 11:05:42.277699 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 11:05:42.280978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 11:05:42.284481 ==
3610 11:05:42.284563
3611 11:05:42.284628
3612 11:05:42.284688 TX Vref Scan disable
3613 11:05:42.287714 == TX Byte 0 ==
3614 11:05:42.291185 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3615 11:05:42.294363 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3616 11:05:42.297716 == TX Byte 1 ==
3617 11:05:42.301052 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3618 11:05:42.304152 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3619 11:05:42.307311 ==
3620 11:05:42.310730 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 11:05:42.313947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 11:05:42.314029 ==
3623 11:05:42.325371 TX Vref=22, minBit 0, minWin=25, winSum=420
3624 11:05:42.328893 TX Vref=24, minBit 0, minWin=25, winSum=423
3625 11:05:42.331932 TX Vref=26, minBit 3, minWin=25, winSum=431
3626 11:05:42.335358 TX Vref=28, minBit 0, minWin=26, winSum=429
3627 11:05:42.338865 TX Vref=30, minBit 1, minWin=26, winSum=431
3628 11:05:42.345101 TX Vref=32, minBit 4, minWin=26, winSum=430
3629 11:05:42.348648 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3630 11:05:42.348730
3631 11:05:42.352254 Final TX Range 1 Vref 30
3632 11:05:42.352341
3633 11:05:42.352405 ==
3634 11:05:42.355063 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 11:05:42.358242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 11:05:42.361609 ==
3637 11:05:42.361691
3638 11:05:42.361756
3639 11:05:42.361816 TX Vref Scan disable
3640 11:05:42.365081 == TX Byte 0 ==
3641 11:05:42.368659 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3642 11:05:42.375310 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3643 11:05:42.375391 == TX Byte 1 ==
3644 11:05:42.378457 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3645 11:05:42.385026 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3646 11:05:42.385134
3647 11:05:42.385216 [DATLAT]
3648 11:05:42.385278 Freq=1200, CH1 RK1
3649 11:05:42.385336
3650 11:05:42.388394 DATLAT Default: 0xd
3651 11:05:42.388476 0, 0xFFFF, sum = 0
3652 11:05:42.391678 1, 0xFFFF, sum = 0
3653 11:05:42.394925 2, 0xFFFF, sum = 0
3654 11:05:42.395008 3, 0xFFFF, sum = 0
3655 11:05:42.398369 4, 0xFFFF, sum = 0
3656 11:05:42.398451 5, 0xFFFF, sum = 0
3657 11:05:42.401371 6, 0xFFFF, sum = 0
3658 11:05:42.401455 7, 0xFFFF, sum = 0
3659 11:05:42.404886 8, 0xFFFF, sum = 0
3660 11:05:42.404970 9, 0xFFFF, sum = 0
3661 11:05:42.408076 10, 0xFFFF, sum = 0
3662 11:05:42.408160 11, 0xFFFF, sum = 0
3663 11:05:42.411536 12, 0x0, sum = 1
3664 11:05:42.411620 13, 0x0, sum = 2
3665 11:05:42.414855 14, 0x0, sum = 3
3666 11:05:42.414939 15, 0x0, sum = 4
3667 11:05:42.417964 best_step = 13
3668 11:05:42.418072
3669 11:05:42.418165 ==
3670 11:05:42.421332 Dram Type= 6, Freq= 0, CH_1, rank 1
3671 11:05:42.424743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3672 11:05:42.424827 ==
3673 11:05:42.424892 RX Vref Scan: 0
3674 11:05:42.428037
3675 11:05:42.428119 RX Vref 0 -> 0, step: 1
3676 11:05:42.428184
3677 11:05:42.431541 RX Delay -21 -> 252, step: 4
3678 11:05:42.438231 iDelay=195, Bit 0, Center 116 (43 ~ 190) 148
3679 11:05:42.441232 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3680 11:05:42.444441 iDelay=195, Bit 2, Center 102 (31 ~ 174) 144
3681 11:05:42.447804 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3682 11:05:42.451067 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3683 11:05:42.457723 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3684 11:05:42.461051 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3685 11:05:42.464356 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3686 11:05:42.467928 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3687 11:05:42.470856 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3688 11:05:42.477626 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3689 11:05:42.481041 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3690 11:05:42.484400 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3691 11:05:42.487465 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3692 11:05:42.490990 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3693 11:05:42.497298 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3694 11:05:42.497380 ==
3695 11:05:42.500777 Dram Type= 6, Freq= 0, CH_1, rank 1
3696 11:05:42.503904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3697 11:05:42.503991 ==
3698 11:05:42.504057 DQS Delay:
3699 11:05:42.507455 DQS0 = 0, DQS1 = 0
3700 11:05:42.507538 DQM Delay:
3701 11:05:42.510423 DQM0 = 111, DQM1 = 109
3702 11:05:42.510505 DQ Delay:
3703 11:05:42.513901 DQ0 =116, DQ1 =110, DQ2 =102, DQ3 =108
3704 11:05:42.517447 DQ4 =108, DQ5 =120, DQ6 =120, DQ7 =110
3705 11:05:42.520539 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =102
3706 11:05:42.523861 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3707 11:05:42.527062
3708 11:05:42.527144
3709 11:05:42.533821 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa0a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3710 11:05:42.536927 CH1 RK1: MR19=304, MR18=FA0A
3711 11:05:42.543446 CH1_RK1: MR19=0x304, MR18=0xFA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3712 11:05:42.547036 [RxdqsGatingPostProcess] freq 1200
3713 11:05:42.550293 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3714 11:05:42.553513 best DQS0 dly(2T, 0.5T) = (0, 11)
3715 11:05:42.557210 best DQS1 dly(2T, 0.5T) = (0, 11)
3716 11:05:42.560132 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3717 11:05:42.563655 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3718 11:05:42.566712 best DQS0 dly(2T, 0.5T) = (0, 11)
3719 11:05:42.570356 best DQS1 dly(2T, 0.5T) = (0, 11)
3720 11:05:42.573774 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3721 11:05:42.576929 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3722 11:05:42.580013 Pre-setting of DQS Precalculation
3723 11:05:42.583501 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3724 11:05:42.590132 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3725 11:05:42.599985 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3726 11:05:42.600068
3727 11:05:42.600133
3728 11:05:42.603348 [Calibration Summary] 2400 Mbps
3729 11:05:42.603431 CH 0, Rank 0
3730 11:05:42.606561 SW Impedance : PASS
3731 11:05:42.606644 DUTY Scan : NO K
3732 11:05:42.609833 ZQ Calibration : PASS
3733 11:05:42.613327 Jitter Meter : NO K
3734 11:05:42.613437 CBT Training : PASS
3735 11:05:42.616651 Write leveling : PASS
3736 11:05:42.619711 RX DQS gating : PASS
3737 11:05:42.619819 RX DQ/DQS(RDDQC) : PASS
3738 11:05:42.623208 TX DQ/DQS : PASS
3739 11:05:42.623292 RX DATLAT : PASS
3740 11:05:42.626451 RX DQ/DQS(Engine): PASS
3741 11:05:42.629826 TX OE : NO K
3742 11:05:42.629935 All Pass.
3743 11:05:42.630027
3744 11:05:42.630116 CH 0, Rank 1
3745 11:05:42.633198 SW Impedance : PASS
3746 11:05:42.636369 DUTY Scan : NO K
3747 11:05:42.636451 ZQ Calibration : PASS
3748 11:05:42.639663 Jitter Meter : NO K
3749 11:05:42.643216 CBT Training : PASS
3750 11:05:42.643324 Write leveling : PASS
3751 11:05:42.646230 RX DQS gating : PASS
3752 11:05:42.649594 RX DQ/DQS(RDDQC) : PASS
3753 11:05:42.649717 TX DQ/DQS : PASS
3754 11:05:42.652740 RX DATLAT : PASS
3755 11:05:42.656270 RX DQ/DQS(Engine): PASS
3756 11:05:42.656352 TX OE : NO K
3757 11:05:42.659695 All Pass.
3758 11:05:42.659777
3759 11:05:42.659843 CH 1, Rank 0
3760 11:05:42.662742 SW Impedance : PASS
3761 11:05:42.662825 DUTY Scan : NO K
3762 11:05:42.665986 ZQ Calibration : PASS
3763 11:05:42.669425 Jitter Meter : NO K
3764 11:05:42.669546 CBT Training : PASS
3765 11:05:42.672763 Write leveling : PASS
3766 11:05:42.676473 RX DQS gating : PASS
3767 11:05:42.676556 RX DQ/DQS(RDDQC) : PASS
3768 11:05:42.679558 TX DQ/DQS : PASS
3769 11:05:42.679642 RX DATLAT : PASS
3770 11:05:42.682789 RX DQ/DQS(Engine): PASS
3771 11:05:42.686256 TX OE : NO K
3772 11:05:42.686338 All Pass.
3773 11:05:42.686403
3774 11:05:42.686463 CH 1, Rank 1
3775 11:05:42.689361 SW Impedance : PASS
3776 11:05:42.692877 DUTY Scan : NO K
3777 11:05:42.692959 ZQ Calibration : PASS
3778 11:05:42.696006 Jitter Meter : NO K
3779 11:05:42.699508 CBT Training : PASS
3780 11:05:42.699591 Write leveling : PASS
3781 11:05:42.702763 RX DQS gating : PASS
3782 11:05:42.706283 RX DQ/DQS(RDDQC) : PASS
3783 11:05:42.706366 TX DQ/DQS : PASS
3784 11:05:42.709466 RX DATLAT : PASS
3785 11:05:42.712794 RX DQ/DQS(Engine): PASS
3786 11:05:42.712876 TX OE : NO K
3787 11:05:42.715781 All Pass.
3788 11:05:42.715863
3789 11:05:42.715929 DramC Write-DBI off
3790 11:05:42.719217 PER_BANK_REFRESH: Hybrid Mode
3791 11:05:42.719302 TX_TRACKING: ON
3792 11:05:42.729241 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3793 11:05:42.732629 [FAST_K] Save calibration result to emmc
3794 11:05:42.735950 dramc_set_vcore_voltage set vcore to 650000
3795 11:05:42.739108 Read voltage for 600, 5
3796 11:05:42.739190 Vio18 = 0
3797 11:05:42.742447 Vcore = 650000
3798 11:05:42.742528 Vdram = 0
3799 11:05:42.742593 Vddq = 0
3800 11:05:42.745837 Vmddr = 0
3801 11:05:42.749148 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3802 11:05:42.755675 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3803 11:05:42.755757 MEM_TYPE=3, freq_sel=19
3804 11:05:42.759243 sv_algorithm_assistance_LP4_1600
3805 11:05:42.765729 ============ PULL DRAM RESETB DOWN ============
3806 11:05:42.769069 ========== PULL DRAM RESETB DOWN end =========
3807 11:05:42.772319 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3808 11:05:42.775307 ===================================
3809 11:05:42.778663 LPDDR4 DRAM CONFIGURATION
3810 11:05:42.781903 ===================================
3811 11:05:42.785423 EX_ROW_EN[0] = 0x0
3812 11:05:42.785543 EX_ROW_EN[1] = 0x0
3813 11:05:42.788683 LP4Y_EN = 0x0
3814 11:05:42.788764 WORK_FSP = 0x0
3815 11:05:42.792027 WL = 0x2
3816 11:05:42.792142 RL = 0x2
3817 11:05:42.795347 BL = 0x2
3818 11:05:42.795429 RPST = 0x0
3819 11:05:42.798596 RD_PRE = 0x0
3820 11:05:42.798680 WR_PRE = 0x1
3821 11:05:42.801648 WR_PST = 0x0
3822 11:05:42.801768 DBI_WR = 0x0
3823 11:05:42.805255 DBI_RD = 0x0
3824 11:05:42.805362 OTF = 0x1
3825 11:05:42.808369 ===================================
3826 11:05:42.811733 ===================================
3827 11:05:42.814932 ANA top config
3828 11:05:42.818322 ===================================
3829 11:05:42.821605 DLL_ASYNC_EN = 0
3830 11:05:42.821679 ALL_SLAVE_EN = 1
3831 11:05:42.825147 NEW_RANK_MODE = 1
3832 11:05:42.828356 DLL_IDLE_MODE = 1
3833 11:05:42.831418 LP45_APHY_COMB_EN = 1
3834 11:05:42.831526 TX_ODT_DIS = 1
3835 11:05:42.834815 NEW_8X_MODE = 1
3836 11:05:42.838339 ===================================
3837 11:05:42.841405 ===================================
3838 11:05:42.844818 data_rate = 1200
3839 11:05:42.848489 CKR = 1
3840 11:05:42.851693 DQ_P2S_RATIO = 8
3841 11:05:42.855019 ===================================
3842 11:05:42.858033 CA_P2S_RATIO = 8
3843 11:05:42.858118 DQ_CA_OPEN = 0
3844 11:05:42.861503 DQ_SEMI_OPEN = 0
3845 11:05:42.864662 CA_SEMI_OPEN = 0
3846 11:05:42.868134 CA_FULL_RATE = 0
3847 11:05:42.871115 DQ_CKDIV4_EN = 1
3848 11:05:42.874565 CA_CKDIV4_EN = 1
3849 11:05:42.874650 CA_PREDIV_EN = 0
3850 11:05:42.877960 PH8_DLY = 0
3851 11:05:42.881353 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3852 11:05:42.884511 DQ_AAMCK_DIV = 4
3853 11:05:42.888017 CA_AAMCK_DIV = 4
3854 11:05:42.891208 CA_ADMCK_DIV = 4
3855 11:05:42.891290 DQ_TRACK_CA_EN = 0
3856 11:05:42.894339 CA_PICK = 600
3857 11:05:42.897744 CA_MCKIO = 600
3858 11:05:42.900997 MCKIO_SEMI = 0
3859 11:05:42.904094 PLL_FREQ = 2288
3860 11:05:42.907542 DQ_UI_PI_RATIO = 32
3861 11:05:42.910929 CA_UI_PI_RATIO = 0
3862 11:05:42.914115 ===================================
3863 11:05:42.917360 ===================================
3864 11:05:42.917467 memory_type:LPDDR4
3865 11:05:42.920814 GP_NUM : 10
3866 11:05:42.923901 SRAM_EN : 1
3867 11:05:42.923984 MD32_EN : 0
3868 11:05:42.927294 ===================================
3869 11:05:42.930606 [ANA_INIT] >>>>>>>>>>>>>>
3870 11:05:42.933805 <<<<<< [CONFIGURE PHASE]: ANA_TX
3871 11:05:42.937120 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3872 11:05:42.940704 ===================================
3873 11:05:42.944055 data_rate = 1200,PCW = 0X5800
3874 11:05:42.947223 ===================================
3875 11:05:42.950819 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3876 11:05:42.953872 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3877 11:05:42.960433 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3878 11:05:42.963850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3879 11:05:42.967359 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3880 11:05:42.973808 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3881 11:05:42.973890 [ANA_INIT] flow start
3882 11:05:42.977203 [ANA_INIT] PLL >>>>>>>>
3883 11:05:42.977286 [ANA_INIT] PLL <<<<<<<<
3884 11:05:42.980423 [ANA_INIT] MIDPI >>>>>>>>
3885 11:05:42.983715 [ANA_INIT] MIDPI <<<<<<<<
3886 11:05:42.986861 [ANA_INIT] DLL >>>>>>>>
3887 11:05:42.986943 [ANA_INIT] flow end
3888 11:05:42.990425 ============ LP4 DIFF to SE enter ============
3889 11:05:42.996783 ============ LP4 DIFF to SE exit ============
3890 11:05:42.996869 [ANA_INIT] <<<<<<<<<<<<<
3891 11:05:43.000496 [Flow] Enable top DCM control >>>>>
3892 11:05:43.003751 [Flow] Enable top DCM control <<<<<
3893 11:05:43.006854 Enable DLL master slave shuffle
3894 11:05:43.013406 ==============================================================
3895 11:05:43.013528 Gating Mode config
3896 11:05:43.020165 ==============================================================
3897 11:05:43.023321 Config description:
3898 11:05:43.033243 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3899 11:05:43.039848 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3900 11:05:43.043129 SELPH_MODE 0: By rank 1: By Phase
3901 11:05:43.049754 ==============================================================
3902 11:05:43.052962 GAT_TRACK_EN = 1
3903 11:05:43.056572 RX_GATING_MODE = 2
3904 11:05:43.059552 RX_GATING_TRACK_MODE = 2
3905 11:05:43.059635 SELPH_MODE = 1
3906 11:05:43.062966 PICG_EARLY_EN = 1
3907 11:05:43.066298 VALID_LAT_VALUE = 1
3908 11:05:43.073089 ==============================================================
3909 11:05:43.076140 Enter into Gating configuration >>>>
3910 11:05:43.079553 Exit from Gating configuration <<<<
3911 11:05:43.082874 Enter into DVFS_PRE_config >>>>>
3912 11:05:43.093071 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3913 11:05:43.096223 Exit from DVFS_PRE_config <<<<<
3914 11:05:43.099685 Enter into PICG configuration >>>>
3915 11:05:43.102849 Exit from PICG configuration <<<<
3916 11:05:43.106247 [RX_INPUT] configuration >>>>>
3917 11:05:43.109612 [RX_INPUT] configuration <<<<<
3918 11:05:43.112805 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3919 11:05:43.119218 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3920 11:05:43.125883 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3921 11:05:43.132517 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3922 11:05:43.139337 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3923 11:05:43.142537 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3924 11:05:43.149112 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3925 11:05:43.155106 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3926 11:05:43.155685 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3927 11:05:43.159102 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3928 11:05:43.162712 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3929 11:05:43.169247 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3930 11:05:43.172492 ===================================
3931 11:05:43.175752 LPDDR4 DRAM CONFIGURATION
3932 11:05:43.179226 ===================================
3933 11:05:43.179309 EX_ROW_EN[0] = 0x0
3934 11:05:43.182300 EX_ROW_EN[1] = 0x0
3935 11:05:43.182382 LP4Y_EN = 0x0
3936 11:05:43.185966 WORK_FSP = 0x0
3937 11:05:43.186049 WL = 0x2
3938 11:05:43.189410 RL = 0x2
3939 11:05:43.189515 BL = 0x2
3940 11:05:43.192334 RPST = 0x0
3941 11:05:43.192449 RD_PRE = 0x0
3942 11:05:43.195562 WR_PRE = 0x1
3943 11:05:43.195643 WR_PST = 0x0
3944 11:05:43.199030 DBI_WR = 0x0
3945 11:05:43.199112 DBI_RD = 0x0
3946 11:05:43.202522 OTF = 0x1
3947 11:05:43.205501 ===================================
3948 11:05:43.209059 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3949 11:05:43.212110 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3950 11:05:43.218906 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3951 11:05:43.222172 ===================================
3952 11:05:43.225463 LPDDR4 DRAM CONFIGURATION
3953 11:05:43.225567 ===================================
3954 11:05:43.228995 EX_ROW_EN[0] = 0x10
3955 11:05:43.232012 EX_ROW_EN[1] = 0x0
3956 11:05:43.232107 LP4Y_EN = 0x0
3957 11:05:43.235307 WORK_FSP = 0x0
3958 11:05:43.235389 WL = 0x2
3959 11:05:43.238742 RL = 0x2
3960 11:05:43.238824 BL = 0x2
3961 11:05:43.242206 RPST = 0x0
3962 11:05:43.242288 RD_PRE = 0x0
3963 11:05:43.245387 WR_PRE = 0x1
3964 11:05:43.245468 WR_PST = 0x0
3965 11:05:43.248760 DBI_WR = 0x0
3966 11:05:43.248868 DBI_RD = 0x0
3967 11:05:43.252082 OTF = 0x1
3968 11:05:43.255347 ===================================
3969 11:05:43.261910 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3970 11:05:43.265281 nWR fixed to 30
3971 11:05:43.268388 [ModeRegInit_LP4] CH0 RK0
3972 11:05:43.268469 [ModeRegInit_LP4] CH0 RK1
3973 11:05:43.271798 [ModeRegInit_LP4] CH1 RK0
3974 11:05:43.275063 [ModeRegInit_LP4] CH1 RK1
3975 11:05:43.275145 match AC timing 17
3976 11:05:43.281749 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3977 11:05:43.285100 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3978 11:05:43.288436 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3979 11:05:43.295138 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3980 11:05:43.298532 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3981 11:05:43.298614 ==
3982 11:05:43.301666 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 11:05:43.305118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 11:05:43.305201 ==
3985 11:05:43.311645 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3986 11:05:43.318339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3987 11:05:43.321450 [CA 0] Center 37 (7~67) winsize 61
3988 11:05:43.325058 [CA 1] Center 36 (6~67) winsize 62
3989 11:05:43.328367 [CA 2] Center 35 (5~65) winsize 61
3990 11:05:43.331333 [CA 3] Center 35 (5~65) winsize 61
3991 11:05:43.334735 [CA 4] Center 34 (4~65) winsize 62
3992 11:05:43.338399 [CA 5] Center 34 (4~64) winsize 61
3993 11:05:43.338479
3994 11:05:43.341427 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3995 11:05:43.341517
3996 11:05:43.344606 [CATrainingPosCal] consider 1 rank data
3997 11:05:43.348119 u2DelayCellTimex100 = 270/100 ps
3998 11:05:43.351293 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3999 11:05:43.354681 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4000 11:05:43.358290 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4001 11:05:43.361417 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4002 11:05:43.364718 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4003 11:05:43.371196 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4004 11:05:43.371283
4005 11:05:43.374357 CA PerBit enable=1, Macro0, CA PI delay=34
4006 11:05:43.374445
4007 11:05:43.377940 [CBTSetCACLKResult] CA Dly = 34
4008 11:05:43.378021 CS Dly: 6 (0~37)
4009 11:05:43.378086 ==
4010 11:05:43.381051 Dram Type= 6, Freq= 0, CH_0, rank 1
4011 11:05:43.384724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4012 11:05:43.387604 ==
4013 11:05:43.391288 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4014 11:05:43.397804 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4015 11:05:43.401103 [CA 0] Center 37 (7~67) winsize 61
4016 11:05:43.404513 [CA 1] Center 37 (7~67) winsize 61
4017 11:05:43.408038 [CA 2] Center 35 (5~65) winsize 61
4018 11:05:43.410970 [CA 3] Center 34 (4~65) winsize 62
4019 11:05:43.414152 [CA 4] Center 34 (4~65) winsize 62
4020 11:05:43.417424 [CA 5] Center 33 (3~64) winsize 62
4021 11:05:43.417544
4022 11:05:43.420668 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4023 11:05:43.420749
4024 11:05:43.424161 [CATrainingPosCal] consider 2 rank data
4025 11:05:43.427269 u2DelayCellTimex100 = 270/100 ps
4026 11:05:43.430702 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4027 11:05:43.434254 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4028 11:05:43.440734 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4029 11:05:43.443881 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4030 11:05:43.447072 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4031 11:05:43.450427 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4032 11:05:43.450508
4033 11:05:43.453982 CA PerBit enable=1, Macro0, CA PI delay=34
4034 11:05:43.454074
4035 11:05:43.457143 [CBTSetCACLKResult] CA Dly = 34
4036 11:05:43.457224 CS Dly: 6 (0~37)
4037 11:05:43.457289
4038 11:05:43.460348 ----->DramcWriteLeveling(PI) begin...
4039 11:05:43.463934 ==
4040 11:05:43.466982 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 11:05:43.470342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 11:05:43.470425 ==
4043 11:05:43.473832 Write leveling (Byte 0): 32 => 32
4044 11:05:43.476862 Write leveling (Byte 1): 32 => 32
4045 11:05:43.480170 DramcWriteLeveling(PI) end<-----
4046 11:05:43.480251
4047 11:05:43.480316 ==
4048 11:05:43.483617 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 11:05:43.486992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 11:05:43.487074 ==
4051 11:05:43.490305 [Gating] SW mode calibration
4052 11:05:43.496685 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4053 11:05:43.503375 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4054 11:05:43.506661 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4055 11:05:43.510207 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4056 11:05:43.516685 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4057 11:05:43.519911 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4058 11:05:43.523299 0 9 16 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (0 0)
4059 11:05:43.529969 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4060 11:05:43.533168 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 11:05:43.536667 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 11:05:43.543065 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 11:05:43.546541 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 11:05:43.549817 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 11:05:43.553156 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 11:05:43.559689 0 10 16 | B1->B0 | 3333 3c3c | 0 1 | (1 1) (0 0)
4067 11:05:43.562794 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4068 11:05:43.566309 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 11:05:43.572744 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 11:05:43.576379 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 11:05:43.579538 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 11:05:43.586281 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 11:05:43.589232 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4074 11:05:43.592734 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 11:05:43.599395 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 11:05:43.602508 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 11:05:43.606111 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 11:05:43.612778 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 11:05:43.615914 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 11:05:43.619289 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 11:05:43.625883 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 11:05:43.629045 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 11:05:43.632422 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 11:05:43.639215 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 11:05:43.642091 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 11:05:43.645455 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 11:05:43.652169 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 11:05:43.655575 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 11:05:43.659028 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4090 11:05:43.665578 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4091 11:05:43.668631 Total UI for P1: 0, mck2ui 16
4092 11:05:43.672155 best dqsien dly found for B0: ( 0, 13, 12)
4093 11:05:43.675691 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 11:05:43.678624 Total UI for P1: 0, mck2ui 16
4095 11:05:43.681972 best dqsien dly found for B1: ( 0, 13, 16)
4096 11:05:43.685505 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4097 11:05:43.688636 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4098 11:05:43.688719
4099 11:05:43.692012 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4100 11:05:43.695524 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4101 11:05:43.698597 [Gating] SW calibration Done
4102 11:05:43.698679 ==
4103 11:05:43.701774 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 11:05:43.708379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 11:05:43.708462 ==
4106 11:05:43.708528 RX Vref Scan: 0
4107 11:05:43.708589
4108 11:05:43.711896 RX Vref 0 -> 0, step: 1
4109 11:05:43.711978
4110 11:05:43.715321 RX Delay -230 -> 252, step: 16
4111 11:05:43.718537 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4112 11:05:43.721950 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4113 11:05:43.725019 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4114 11:05:43.731816 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4115 11:05:43.734907 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4116 11:05:43.738363 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4117 11:05:43.741859 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4118 11:05:43.748350 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4119 11:05:43.751893 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4120 11:05:43.754871 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4121 11:05:43.758334 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4122 11:05:43.761743 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4123 11:05:43.768173 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4124 11:05:43.771802 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4125 11:05:43.775104 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4126 11:05:43.778279 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4127 11:05:43.781704 ==
4128 11:05:43.781806 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 11:05:43.788314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 11:05:43.788397 ==
4131 11:05:43.788461 DQS Delay:
4132 11:05:43.791367 DQS0 = 0, DQS1 = 0
4133 11:05:43.791448 DQM Delay:
4134 11:05:43.794701 DQM0 = 38, DQM1 = 30
4135 11:05:43.794783 DQ Delay:
4136 11:05:43.798218 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4137 11:05:43.801455 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4138 11:05:43.804720 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4139 11:05:43.807990 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4140 11:05:43.808070
4141 11:05:43.808135
4142 11:05:43.808194 ==
4143 11:05:43.811339 Dram Type= 6, Freq= 0, CH_0, rank 0
4144 11:05:43.814352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 11:05:43.814434 ==
4146 11:05:43.814499
4147 11:05:43.814558
4148 11:05:43.817937 TX Vref Scan disable
4149 11:05:43.821240 == TX Byte 0 ==
4150 11:05:43.824466 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4151 11:05:43.827545 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4152 11:05:43.831068 == TX Byte 1 ==
4153 11:05:43.834534 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4154 11:05:43.837862 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4155 11:05:43.837948 ==
4156 11:05:43.840920 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 11:05:43.847628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 11:05:43.847711 ==
4159 11:05:43.847776
4160 11:05:43.847835
4161 11:05:43.847892 TX Vref Scan disable
4162 11:05:43.851728 == TX Byte 0 ==
4163 11:05:43.855301 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4164 11:05:43.858495 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4165 11:05:43.861877 == TX Byte 1 ==
4166 11:05:43.865080 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4167 11:05:43.871864 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4168 11:05:43.871947
4169 11:05:43.872011 [DATLAT]
4170 11:05:43.872070 Freq=600, CH0 RK0
4171 11:05:43.872128
4172 11:05:43.875302 DATLAT Default: 0x9
4173 11:05:43.875384 0, 0xFFFF, sum = 0
4174 11:05:43.878635 1, 0xFFFF, sum = 0
4175 11:05:43.878717 2, 0xFFFF, sum = 0
4176 11:05:43.881920 3, 0xFFFF, sum = 0
4177 11:05:43.882003 4, 0xFFFF, sum = 0
4178 11:05:43.885112 5, 0xFFFF, sum = 0
4179 11:05:43.888495 6, 0xFFFF, sum = 0
4180 11:05:43.888578 7, 0xFFFF, sum = 0
4181 11:05:43.888644 8, 0x0, sum = 1
4182 11:05:43.891824 9, 0x0, sum = 2
4183 11:05:43.891907 10, 0x0, sum = 3
4184 11:05:43.895008 11, 0x0, sum = 4
4185 11:05:43.895091 best_step = 9
4186 11:05:43.895155
4187 11:05:43.895215 ==
4188 11:05:43.898571 Dram Type= 6, Freq= 0, CH_0, rank 0
4189 11:05:43.904855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 11:05:43.904937 ==
4191 11:05:43.905002 RX Vref Scan: 1
4192 11:05:43.905062
4193 11:05:43.908461 RX Vref 0 -> 0, step: 1
4194 11:05:43.908542
4195 11:05:43.911497 RX Delay -195 -> 252, step: 8
4196 11:05:43.911601
4197 11:05:43.914889 Set Vref, RX VrefLevel [Byte0]: 61
4198 11:05:43.918300 [Byte1]: 54
4199 11:05:43.918382
4200 11:05:43.921679 Final RX Vref Byte 0 = 61 to rank0
4201 11:05:43.924715 Final RX Vref Byte 1 = 54 to rank0
4202 11:05:43.928283 Final RX Vref Byte 0 = 61 to rank1
4203 11:05:43.931498 Final RX Vref Byte 1 = 54 to rank1==
4204 11:05:43.934523 Dram Type= 6, Freq= 0, CH_0, rank 0
4205 11:05:43.937962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 11:05:43.938044 ==
4207 11:05:43.941416 DQS Delay:
4208 11:05:43.941612 DQS0 = 0, DQS1 = 0
4209 11:05:43.944439 DQM Delay:
4210 11:05:43.944540 DQM0 = 34, DQM1 = 29
4211 11:05:43.944631 DQ Delay:
4212 11:05:43.947831 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =32
4213 11:05:43.951019 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =48
4214 11:05:43.954523 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4215 11:05:43.957649 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =36
4216 11:05:43.957731
4217 11:05:43.957795
4218 11:05:43.967763 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4219 11:05:43.970838 CH0 RK0: MR19=808, MR18=3D3C
4220 11:05:43.977439 CH0_RK0: MR19=0x808, MR18=0x3D3C, DQSOSC=398, MR23=63, INC=165, DEC=110
4221 11:05:43.977563
4222 11:05:43.980868 ----->DramcWriteLeveling(PI) begin...
4223 11:05:43.980951 ==
4224 11:05:43.983911 Dram Type= 6, Freq= 0, CH_0, rank 1
4225 11:05:43.987417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 11:05:43.987502 ==
4227 11:05:43.990498 Write leveling (Byte 0): 31 => 31
4228 11:05:43.993637 Write leveling (Byte 1): 32 => 32
4229 11:05:43.997123 DramcWriteLeveling(PI) end<-----
4230 11:05:43.997264
4231 11:05:43.997373 ==
4232 11:05:44.000583 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 11:05:44.003643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 11:05:44.003740 ==
4235 11:05:44.007000 [Gating] SW mode calibration
4236 11:05:44.013760 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4237 11:05:44.020431 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4238 11:05:44.023643 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4239 11:05:44.030244 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4240 11:05:44.033421 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4241 11:05:44.037040 0 9 12 | B1->B0 | 3434 2f2f | 0 0 | (1 0) (1 1)
4242 11:05:44.040262 0 9 16 | B1->B0 | 3030 2525 | 0 0 | (0 1) (0 0)
4243 11:05:44.047099 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 11:05:44.050478 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 11:05:44.053670 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 11:05:44.060402 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 11:05:44.063550 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 11:05:44.066629 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 11:05:44.073431 0 10 12 | B1->B0 | 2525 3636 | 0 1 | (0 0) (1 1)
4250 11:05:44.076706 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4251 11:05:44.080224 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 11:05:44.086624 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 11:05:44.090132 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 11:05:44.093179 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 11:05:44.100185 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 11:05:44.103099 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 11:05:44.106670 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4258 11:05:44.113333 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4259 11:05:44.116594 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 11:05:44.119745 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 11:05:44.126614 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 11:05:44.129837 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 11:05:44.133060 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 11:05:44.139722 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 11:05:44.143055 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 11:05:44.146392 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 11:05:44.152884 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 11:05:44.156420 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 11:05:44.159543 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 11:05:44.166158 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 11:05:44.169526 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 11:05:44.172936 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 11:05:44.179294 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4274 11:05:44.182662 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 11:05:44.185953 Total UI for P1: 0, mck2ui 16
4276 11:05:44.189344 best dqsien dly found for B0: ( 0, 13, 12)
4277 11:05:44.192747 Total UI for P1: 0, mck2ui 16
4278 11:05:44.195780 best dqsien dly found for B1: ( 0, 13, 14)
4279 11:05:44.199270 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4280 11:05:44.202381 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4281 11:05:44.202464
4282 11:05:44.205878 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4283 11:05:44.208988 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4284 11:05:44.212599 [Gating] SW calibration Done
4285 11:05:44.212697 ==
4286 11:05:44.215560 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 11:05:44.218799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 11:05:44.222286 ==
4289 11:05:44.222368 RX Vref Scan: 0
4290 11:05:44.222433
4291 11:05:44.225688 RX Vref 0 -> 0, step: 1
4292 11:05:44.225770
4293 11:05:44.228928 RX Delay -230 -> 252, step: 16
4294 11:05:44.232204 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4295 11:05:44.235374 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4296 11:05:44.238734 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4297 11:05:44.245534 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4298 11:05:44.248441 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4299 11:05:44.251935 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4300 11:05:44.255249 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4301 11:05:44.258742 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4302 11:05:44.265108 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4303 11:05:44.268478 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4304 11:05:44.271837 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4305 11:05:44.275305 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4306 11:05:44.281764 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4307 11:05:44.284745 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4308 11:05:44.288411 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4309 11:05:44.291386 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4310 11:05:44.294746 ==
4311 11:05:44.297995 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 11:05:44.301356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 11:05:44.301491 ==
4314 11:05:44.301573 DQS Delay:
4315 11:05:44.304733 DQS0 = 0, DQS1 = 0
4316 11:05:44.304813 DQM Delay:
4317 11:05:44.308132 DQM0 = 36, DQM1 = 29
4318 11:05:44.308214 DQ Delay:
4319 11:05:44.311478 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4320 11:05:44.314852 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4321 11:05:44.318270 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =17
4322 11:05:44.321364 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4323 11:05:44.321446
4324 11:05:44.321552
4325 11:05:44.321613 ==
4326 11:05:44.324979 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 11:05:44.327833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 11:05:44.327915 ==
4329 11:05:44.327980
4330 11:05:44.328039
4331 11:05:44.331549 TX Vref Scan disable
4332 11:05:44.334384 == TX Byte 0 ==
4333 11:05:44.337823 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4334 11:05:44.341096 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4335 11:05:44.344518 == TX Byte 1 ==
4336 11:05:44.347488 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4337 11:05:44.351035 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4338 11:05:44.351117 ==
4339 11:05:44.354058 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 11:05:44.360588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 11:05:44.360698 ==
4342 11:05:44.360796
4343 11:05:44.360882
4344 11:05:44.360970 TX Vref Scan disable
4345 11:05:44.365193 == TX Byte 0 ==
4346 11:05:44.368379 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4347 11:05:44.374983 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4348 11:05:44.375065 == TX Byte 1 ==
4349 11:05:44.378388 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4350 11:05:44.384913 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4351 11:05:44.384995
4352 11:05:44.385059 [DATLAT]
4353 11:05:44.385118 Freq=600, CH0 RK1
4354 11:05:44.385176
4355 11:05:44.388316 DATLAT Default: 0x9
4356 11:05:44.391434 0, 0xFFFF, sum = 0
4357 11:05:44.391517 1, 0xFFFF, sum = 0
4358 11:05:44.394877 2, 0xFFFF, sum = 0
4359 11:05:44.394959 3, 0xFFFF, sum = 0
4360 11:05:44.397999 4, 0xFFFF, sum = 0
4361 11:05:44.398082 5, 0xFFFF, sum = 0
4362 11:05:44.401403 6, 0xFFFF, sum = 0
4363 11:05:44.401507 7, 0xFFFF, sum = 0
4364 11:05:44.404727 8, 0x0, sum = 1
4365 11:05:44.404810 9, 0x0, sum = 2
4366 11:05:44.407989 10, 0x0, sum = 3
4367 11:05:44.408071 11, 0x0, sum = 4
4368 11:05:44.408136 best_step = 9
4369 11:05:44.408196
4370 11:05:44.411377 ==
4371 11:05:44.411462 Dram Type= 6, Freq= 0, CH_0, rank 1
4372 11:05:44.417979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 11:05:44.418060 ==
4374 11:05:44.418124 RX Vref Scan: 0
4375 11:05:44.418184
4376 11:05:44.421573 RX Vref 0 -> 0, step: 1
4377 11:05:44.421670
4378 11:05:44.424682 RX Delay -195 -> 252, step: 8
4379 11:05:44.431211 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4380 11:05:44.434748 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4381 11:05:44.437774 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4382 11:05:44.441433 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4383 11:05:44.444597 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4384 11:05:44.450866 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4385 11:05:44.454345 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4386 11:05:44.457649 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4387 11:05:44.461391 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4388 11:05:44.467688 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4389 11:05:44.471055 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4390 11:05:44.474132 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4391 11:05:44.477672 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4392 11:05:44.484067 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4393 11:05:44.487287 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4394 11:05:44.490579 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4395 11:05:44.490687 ==
4396 11:05:44.494219 Dram Type= 6, Freq= 0, CH_0, rank 1
4397 11:05:44.497256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 11:05:44.500746 ==
4399 11:05:44.500827 DQS Delay:
4400 11:05:44.500890 DQS0 = 0, DQS1 = 0
4401 11:05:44.503749 DQM Delay:
4402 11:05:44.503829 DQM0 = 33, DQM1 = 27
4403 11:05:44.507213 DQ Delay:
4404 11:05:44.507298 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4405 11:05:44.510300 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4406 11:05:44.513740 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4407 11:05:44.517222 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4408 11:05:44.520457
4409 11:05:44.520537
4410 11:05:44.527071 [DQSOSCAuto] RK1, (LSB)MR18= 0x6836, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4411 11:05:44.530080 CH0 RK1: MR19=808, MR18=6836
4412 11:05:44.536825 CH0_RK1: MR19=0x808, MR18=0x6836, DQSOSC=390, MR23=63, INC=172, DEC=114
4413 11:05:44.539955 [RxdqsGatingPostProcess] freq 600
4414 11:05:44.543302 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4415 11:05:44.546694 Pre-setting of DQS Precalculation
4416 11:05:44.553468 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4417 11:05:44.553557 ==
4418 11:05:44.556723 Dram Type= 6, Freq= 0, CH_1, rank 0
4419 11:05:44.559932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 11:05:44.560014 ==
4421 11:05:44.566698 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4422 11:05:44.569783 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4423 11:05:44.574366 [CA 0] Center 35 (5~66) winsize 62
4424 11:05:44.577494 [CA 1] Center 35 (5~66) winsize 62
4425 11:05:44.581011 [CA 2] Center 34 (4~65) winsize 62
4426 11:05:44.584185 [CA 3] Center 34 (4~65) winsize 62
4427 11:05:44.587361 [CA 4] Center 34 (4~65) winsize 62
4428 11:05:44.590647 [CA 5] Center 34 (4~64) winsize 61
4429 11:05:44.590729
4430 11:05:44.594011 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4431 11:05:44.594093
4432 11:05:44.597397 [CATrainingPosCal] consider 1 rank data
4433 11:05:44.600912 u2DelayCellTimex100 = 270/100 ps
4434 11:05:44.604111 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4435 11:05:44.607253 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4436 11:05:44.614124 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4437 11:05:44.617309 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4438 11:05:44.620720 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4439 11:05:44.624114 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4440 11:05:44.624196
4441 11:05:44.627375 CA PerBit enable=1, Macro0, CA PI delay=34
4442 11:05:44.627457
4443 11:05:44.630579 [CBTSetCACLKResult] CA Dly = 34
4444 11:05:44.630661 CS Dly: 4 (0~35)
4445 11:05:44.633987 ==
4446 11:05:44.634074 Dram Type= 6, Freq= 0, CH_1, rank 1
4447 11:05:44.640618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4448 11:05:44.640700 ==
4449 11:05:44.643751 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4450 11:05:44.650291 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4451 11:05:44.654009 [CA 0] Center 36 (6~66) winsize 61
4452 11:05:44.657453 [CA 1] Center 36 (5~67) winsize 63
4453 11:05:44.660607 [CA 2] Center 34 (4~65) winsize 62
4454 11:05:44.664017 [CA 3] Center 34 (3~65) winsize 63
4455 11:05:44.667295 [CA 4] Center 34 (4~65) winsize 62
4456 11:05:44.670980 [CA 5] Center 33 (3~64) winsize 62
4457 11:05:44.671062
4458 11:05:44.673989 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4459 11:05:44.674071
4460 11:05:44.677340 [CATrainingPosCal] consider 2 rank data
4461 11:05:44.680375 u2DelayCellTimex100 = 270/100 ps
4462 11:05:44.684019 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4463 11:05:44.690423 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4464 11:05:44.693767 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4465 11:05:44.697070 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4466 11:05:44.700362 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4467 11:05:44.703595 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4468 11:05:44.703676
4469 11:05:44.707175 CA PerBit enable=1, Macro0, CA PI delay=34
4470 11:05:44.707257
4471 11:05:44.710509 [CBTSetCACLKResult] CA Dly = 34
4472 11:05:44.713700 CS Dly: 5 (0~37)
4473 11:05:44.713781
4474 11:05:44.716812 ----->DramcWriteLeveling(PI) begin...
4475 11:05:44.716894 ==
4476 11:05:44.720302 Dram Type= 6, Freq= 0, CH_1, rank 0
4477 11:05:44.723684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4478 11:05:44.723767 ==
4479 11:05:44.726805 Write leveling (Byte 0): 28 => 28
4480 11:05:44.730142 Write leveling (Byte 1): 29 => 29
4481 11:05:44.733459 DramcWriteLeveling(PI) end<-----
4482 11:05:44.733578
4483 11:05:44.733642 ==
4484 11:05:44.736860 Dram Type= 6, Freq= 0, CH_1, rank 0
4485 11:05:44.739918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4486 11:05:44.740000 ==
4487 11:05:44.743282 [Gating] SW mode calibration
4488 11:05:44.749941 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4489 11:05:44.756668 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4490 11:05:44.760010 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4491 11:05:44.763202 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4492 11:05:44.769533 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4493 11:05:44.772908 0 9 12 | B1->B0 | 3232 3232 | 0 0 | (0 1) (0 1)
4494 11:05:44.776200 0 9 16 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
4495 11:05:44.783045 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 11:05:44.786251 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 11:05:44.789597 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 11:05:44.795947 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 11:05:44.799397 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 11:05:44.802554 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 11:05:44.809295 0 10 12 | B1->B0 | 2727 2e2e | 0 0 | (0 0) (0 0)
4502 11:05:44.812423 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4503 11:05:44.815742 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 11:05:44.822458 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 11:05:44.825705 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 11:05:44.828792 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 11:05:44.835713 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 11:05:44.838639 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 11:05:44.841998 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 11:05:44.848678 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4511 11:05:44.852200 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 11:05:44.855203 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 11:05:44.861758 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 11:05:44.865255 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 11:05:44.868474 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 11:05:44.875089 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 11:05:44.878424 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 11:05:44.881860 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 11:05:44.888559 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 11:05:44.891703 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 11:05:44.895240 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 11:05:44.901818 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 11:05:44.905274 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 11:05:44.908407 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 11:05:44.915155 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4526 11:05:44.918644 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4527 11:05:44.922084 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 11:05:44.925250 Total UI for P1: 0, mck2ui 16
4529 11:05:44.928484 best dqsien dly found for B0: ( 0, 13, 14)
4530 11:05:44.931711 Total UI for P1: 0, mck2ui 16
4531 11:05:44.935049 best dqsien dly found for B1: ( 0, 13, 16)
4532 11:05:44.938305 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4533 11:05:44.941795 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4534 11:05:44.941877
4535 11:05:44.944852 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4536 11:05:44.951497 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4537 11:05:44.951580 [Gating] SW calibration Done
4538 11:05:44.954940 ==
4539 11:05:44.955043 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 11:05:44.961659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 11:05:44.961742 ==
4542 11:05:44.961807 RX Vref Scan: 0
4543 11:05:44.961868
4544 11:05:44.964972 RX Vref 0 -> 0, step: 1
4545 11:05:44.965055
4546 11:05:44.968119 RX Delay -230 -> 252, step: 16
4547 11:05:44.971443 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4548 11:05:44.974888 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4549 11:05:44.981295 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4550 11:05:44.984866 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4551 11:05:44.987846 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4552 11:05:44.991387 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4553 11:05:44.997761 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4554 11:05:45.001190 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4555 11:05:45.004305 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4556 11:05:45.007858 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4557 11:05:45.010988 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4558 11:05:45.017784 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4559 11:05:45.020937 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4560 11:05:45.024474 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4561 11:05:45.027675 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4562 11:05:45.034254 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4563 11:05:45.034337 ==
4564 11:05:45.037760 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 11:05:45.040814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 11:05:45.040922 ==
4567 11:05:45.041016 DQS Delay:
4568 11:05:45.043994 DQS0 = 0, DQS1 = 0
4569 11:05:45.044076 DQM Delay:
4570 11:05:45.047380 DQM0 = 38, DQM1 = 28
4571 11:05:45.047469 DQ Delay:
4572 11:05:45.050898 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4573 11:05:45.054163 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4574 11:05:45.057288 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4575 11:05:45.060642 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4576 11:05:45.060741
4577 11:05:45.060808
4578 11:05:45.060898 ==
4579 11:05:45.064021 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 11:05:45.067333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 11:05:45.070594 ==
4582 11:05:45.070677
4583 11:05:45.070743
4584 11:05:45.070803 TX Vref Scan disable
4585 11:05:45.074020 == TX Byte 0 ==
4586 11:05:45.077304 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4587 11:05:45.080740 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4588 11:05:45.083966 == TX Byte 1 ==
4589 11:05:45.087251 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4590 11:05:45.090379 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4591 11:05:45.093812 ==
4592 11:05:45.097371 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 11:05:45.100382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 11:05:45.100563 ==
4595 11:05:45.100669
4596 11:05:45.100757
4597 11:05:45.103557 TX Vref Scan disable
4598 11:05:45.103680 == TX Byte 0 ==
4599 11:05:45.110349 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4600 11:05:45.113799 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4601 11:05:45.113882 == TX Byte 1 ==
4602 11:05:45.120379 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4603 11:05:45.123504 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4604 11:05:45.123601
4605 11:05:45.123725 [DATLAT]
4606 11:05:45.126823 Freq=600, CH1 RK0
4607 11:05:45.126905
4608 11:05:45.126970 DATLAT Default: 0x9
4609 11:05:45.130068 0, 0xFFFF, sum = 0
4610 11:05:45.130151 1, 0xFFFF, sum = 0
4611 11:05:45.133540 2, 0xFFFF, sum = 0
4612 11:05:45.136755 3, 0xFFFF, sum = 0
4613 11:05:45.136837 4, 0xFFFF, sum = 0
4614 11:05:45.140378 5, 0xFFFF, sum = 0
4615 11:05:45.140461 6, 0xFFFF, sum = 0
4616 11:05:45.143481 7, 0xFFFF, sum = 0
4617 11:05:45.143565 8, 0x0, sum = 1
4618 11:05:45.146693 9, 0x0, sum = 2
4619 11:05:45.146778 10, 0x0, sum = 3
4620 11:05:45.146844 11, 0x0, sum = 4
4621 11:05:45.150218 best_step = 9
4622 11:05:45.150300
4623 11:05:45.150365 ==
4624 11:05:45.153730 Dram Type= 6, Freq= 0, CH_1, rank 0
4625 11:05:45.156833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 11:05:45.156916 ==
4627 11:05:45.160356 RX Vref Scan: 1
4628 11:05:45.160439
4629 11:05:45.160505 RX Vref 0 -> 0, step: 1
4630 11:05:45.160566
4631 11:05:45.163581 RX Delay -195 -> 252, step: 8
4632 11:05:45.163663
4633 11:05:45.166643 Set Vref, RX VrefLevel [Byte0]: 59
4634 11:05:45.170121 [Byte1]: 51
4635 11:05:45.174273
4636 11:05:45.174354 Final RX Vref Byte 0 = 59 to rank0
4637 11:05:45.177526 Final RX Vref Byte 1 = 51 to rank0
4638 11:05:45.180824 Final RX Vref Byte 0 = 59 to rank1
4639 11:05:45.184486 Final RX Vref Byte 1 = 51 to rank1==
4640 11:05:45.187294 Dram Type= 6, Freq= 0, CH_1, rank 0
4641 11:05:45.194079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 11:05:45.194161 ==
4643 11:05:45.194227 DQS Delay:
4644 11:05:45.197366 DQS0 = 0, DQS1 = 0
4645 11:05:45.197448 DQM Delay:
4646 11:05:45.197554 DQM0 = 38, DQM1 = 28
4647 11:05:45.200693 DQ Delay:
4648 11:05:45.203894 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4649 11:05:45.207440 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4650 11:05:45.210687 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4651 11:05:45.213878 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4652 11:05:45.213981
4653 11:05:45.214062
4654 11:05:45.220645 [DQSOSCAuto] RK0, (LSB)MR18= 0x202d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
4655 11:05:45.224004 CH1 RK0: MR19=808, MR18=202D
4656 11:05:45.230607 CH1_RK0: MR19=0x808, MR18=0x202D, DQSOSC=401, MR23=63, INC=163, DEC=108
4657 11:05:45.230689
4658 11:05:45.233721 ----->DramcWriteLeveling(PI) begin...
4659 11:05:45.233804 ==
4660 11:05:45.237126 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 11:05:45.240400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 11:05:45.240482 ==
4663 11:05:45.243828 Write leveling (Byte 0): 30 => 30
4664 11:05:45.247084 Write leveling (Byte 1): 30 => 30
4665 11:05:45.250492 DramcWriteLeveling(PI) end<-----
4666 11:05:45.250573
4667 11:05:45.250638 ==
4668 11:05:45.253648 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 11:05:45.257077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 11:05:45.257159 ==
4671 11:05:45.260416 [Gating] SW mode calibration
4672 11:05:45.266820 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4673 11:05:45.273498 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4674 11:05:45.276679 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4675 11:05:45.283397 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4676 11:05:45.286755 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4677 11:05:45.289852 0 9 12 | B1->B0 | 3131 2e2e | 0 0 | (1 1) (1 1)
4678 11:05:45.296637 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4679 11:05:45.299991 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 11:05:45.303165 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 11:05:45.309974 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 11:05:45.312878 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 11:05:45.316329 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 11:05:45.322850 0 10 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4685 11:05:45.326322 0 10 12 | B1->B0 | 2f2f 4040 | 0 0 | (0 0) (0 0)
4686 11:05:45.329690 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4687 11:05:45.336265 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 11:05:45.339552 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 11:05:45.342820 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 11:05:45.349347 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 11:05:45.352481 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 11:05:45.355978 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 11:05:45.362760 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4694 11:05:45.365793 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 11:05:45.369411 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 11:05:45.375950 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 11:05:45.379110 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 11:05:45.382409 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 11:05:45.389412 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 11:05:45.392418 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 11:05:45.395847 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 11:05:45.399305 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 11:05:45.405813 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 11:05:45.409102 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 11:05:45.412244 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 11:05:45.418900 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 11:05:45.422050 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 11:05:45.425723 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 11:05:45.432064 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4710 11:05:45.435409 Total UI for P1: 0, mck2ui 16
4711 11:05:45.438920 best dqsien dly found for B1: ( 0, 13, 10)
4712 11:05:45.442093 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 11:05:45.445328 Total UI for P1: 0, mck2ui 16
4714 11:05:45.448694 best dqsien dly found for B0: ( 0, 13, 12)
4715 11:05:45.451962 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4716 11:05:45.455428 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4717 11:05:45.455555
4718 11:05:45.458794 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4719 11:05:45.465472 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4720 11:05:45.465589 [Gating] SW calibration Done
4721 11:05:45.465654 ==
4722 11:05:45.468494 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 11:05:45.475060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 11:05:45.475142 ==
4725 11:05:45.475207 RX Vref Scan: 0
4726 11:05:45.475267
4727 11:05:45.478487 RX Vref 0 -> 0, step: 1
4728 11:05:45.478568
4729 11:05:45.481772 RX Delay -230 -> 252, step: 16
4730 11:05:45.485101 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4731 11:05:45.488259 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4732 11:05:45.495145 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4733 11:05:45.498021 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4734 11:05:45.501534 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4735 11:05:45.504947 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4736 11:05:45.508146 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4737 11:05:45.515006 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4738 11:05:45.518283 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4739 11:05:45.521512 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4740 11:05:45.524714 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4741 11:05:45.531302 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4742 11:05:45.534720 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4743 11:05:45.538216 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4744 11:05:45.541354 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4745 11:05:45.548021 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4746 11:05:45.548104 ==
4747 11:05:45.551377 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 11:05:45.554553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 11:05:45.554636 ==
4750 11:05:45.554701 DQS Delay:
4751 11:05:45.558005 DQS0 = 0, DQS1 = 0
4752 11:05:45.558086 DQM Delay:
4753 11:05:45.561051 DQM0 = 36, DQM1 = 29
4754 11:05:45.561132 DQ Delay:
4755 11:05:45.564601 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4756 11:05:45.567743 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4757 11:05:45.571338 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4758 11:05:45.574138 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4759 11:05:45.574219
4760 11:05:45.574283
4761 11:05:45.574343 ==
4762 11:05:45.577591 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 11:05:45.580792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 11:05:45.584149 ==
4765 11:05:45.584230
4766 11:05:45.584295
4767 11:05:45.584354 TX Vref Scan disable
4768 11:05:45.587354 == TX Byte 0 ==
4769 11:05:45.590820 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4770 11:05:45.594136 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4771 11:05:45.597358 == TX Byte 1 ==
4772 11:05:45.600633 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4773 11:05:45.603854 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4774 11:05:45.607380 ==
4775 11:05:45.610428 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 11:05:45.614079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 11:05:45.614161 ==
4778 11:05:45.614225
4779 11:05:45.614285
4780 11:05:45.617123 TX Vref Scan disable
4781 11:05:45.617204 == TX Byte 0 ==
4782 11:05:45.623642 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4783 11:05:45.627263 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4784 11:05:45.630485 == TX Byte 1 ==
4785 11:05:45.633839 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4786 11:05:45.636855 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4787 11:05:45.636936
4788 11:05:45.637000 [DATLAT]
4789 11:05:45.640390 Freq=600, CH1 RK1
4790 11:05:45.640471
4791 11:05:45.640536 DATLAT Default: 0x9
4792 11:05:45.643439 0, 0xFFFF, sum = 0
4793 11:05:45.646701 1, 0xFFFF, sum = 0
4794 11:05:45.646783 2, 0xFFFF, sum = 0
4795 11:05:45.650246 3, 0xFFFF, sum = 0
4796 11:05:45.650329 4, 0xFFFF, sum = 0
4797 11:05:45.653404 5, 0xFFFF, sum = 0
4798 11:05:45.653511 6, 0xFFFF, sum = 0
4799 11:05:45.657012 7, 0xFFFF, sum = 0
4800 11:05:45.657094 8, 0x0, sum = 1
4801 11:05:45.659982 9, 0x0, sum = 2
4802 11:05:45.660065 10, 0x0, sum = 3
4803 11:05:45.660130 11, 0x0, sum = 4
4804 11:05:45.663597 best_step = 9
4805 11:05:45.663684
4806 11:05:45.663750 ==
4807 11:05:45.666715 Dram Type= 6, Freq= 0, CH_1, rank 1
4808 11:05:45.669811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4809 11:05:45.669894 ==
4810 11:05:45.673408 RX Vref Scan: 0
4811 11:05:45.673524
4812 11:05:45.673589 RX Vref 0 -> 0, step: 1
4813 11:05:45.676505
4814 11:05:45.676586 RX Delay -195 -> 252, step: 8
4815 11:05:45.684326 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4816 11:05:45.687476 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4817 11:05:45.690660 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4818 11:05:45.694081 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4819 11:05:45.700782 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4820 11:05:45.704156 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4821 11:05:45.707529 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4822 11:05:45.710726 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4823 11:05:45.717377 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4824 11:05:45.720446 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4825 11:05:45.724106 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4826 11:05:45.727130 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4827 11:05:45.733737 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4828 11:05:45.737241 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4829 11:05:45.740383 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4830 11:05:45.743909 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4831 11:05:45.743991 ==
4832 11:05:45.747016 Dram Type= 6, Freq= 0, CH_1, rank 1
4833 11:05:45.753510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4834 11:05:45.753593 ==
4835 11:05:45.753658 DQS Delay:
4836 11:05:45.756763 DQS0 = 0, DQS1 = 0
4837 11:05:45.756844 DQM Delay:
4838 11:05:45.756908 DQM0 = 36, DQM1 = 29
4839 11:05:45.760438 DQ Delay:
4840 11:05:45.763509 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4841 11:05:45.766921 DQ4 =32, DQ5 =44, DQ6 =48, DQ7 =36
4842 11:05:45.770087 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4843 11:05:45.773524 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4844 11:05:45.773606
4845 11:05:45.773670
4846 11:05:45.780133 [DQSOSCAuto] RK1, (LSB)MR18= 0x3556, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4847 11:05:45.783615 CH1 RK1: MR19=808, MR18=3556
4848 11:05:45.789980 CH1_RK1: MR19=0x808, MR18=0x3556, DQSOSC=393, MR23=63, INC=169, DEC=113
4849 11:05:45.793403 [RxdqsGatingPostProcess] freq 600
4850 11:05:45.797011 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4851 11:05:45.799935 Pre-setting of DQS Precalculation
4852 11:05:45.806464 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4853 11:05:45.813289 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4854 11:05:45.820131 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4855 11:05:45.820223
4856 11:05:45.820291
4857 11:05:45.822992 [Calibration Summary] 1200 Mbps
4858 11:05:45.823073 CH 0, Rank 0
4859 11:05:45.826390 SW Impedance : PASS
4860 11:05:45.829700 DUTY Scan : NO K
4861 11:05:45.829783 ZQ Calibration : PASS
4862 11:05:45.833035 Jitter Meter : NO K
4863 11:05:45.836361 CBT Training : PASS
4864 11:05:45.836445 Write leveling : PASS
4865 11:05:45.839754 RX DQS gating : PASS
4866 11:05:45.842856 RX DQ/DQS(RDDQC) : PASS
4867 11:05:45.842939 TX DQ/DQS : PASS
4868 11:05:45.846376 RX DATLAT : PASS
4869 11:05:45.849876 RX DQ/DQS(Engine): PASS
4870 11:05:45.849959 TX OE : NO K
4871 11:05:45.850054 All Pass.
4872 11:05:45.852948
4873 11:05:45.853029 CH 0, Rank 1
4874 11:05:45.856342 SW Impedance : PASS
4875 11:05:45.856424 DUTY Scan : NO K
4876 11:05:45.859629 ZQ Calibration : PASS
4877 11:05:45.863042 Jitter Meter : NO K
4878 11:05:45.863124 CBT Training : PASS
4879 11:05:45.866364 Write leveling : PASS
4880 11:05:45.866445 RX DQS gating : PASS
4881 11:05:45.869627 RX DQ/DQS(RDDQC) : PASS
4882 11:05:45.873012 TX DQ/DQS : PASS
4883 11:05:45.873094 RX DATLAT : PASS
4884 11:05:45.876120 RX DQ/DQS(Engine): PASS
4885 11:05:45.879443 TX OE : NO K
4886 11:05:45.879525 All Pass.
4887 11:05:45.879588
4888 11:05:45.879649 CH 1, Rank 0
4889 11:05:45.882735 SW Impedance : PASS
4890 11:05:45.886062 DUTY Scan : NO K
4891 11:05:45.886143 ZQ Calibration : PASS
4892 11:05:45.889403 Jitter Meter : NO K
4893 11:05:45.892724 CBT Training : PASS
4894 11:05:45.892805 Write leveling : PASS
4895 11:05:45.896133 RX DQS gating : PASS
4896 11:05:45.899253 RX DQ/DQS(RDDQC) : PASS
4897 11:05:45.899335 TX DQ/DQS : PASS
4898 11:05:45.902417 RX DATLAT : PASS
4899 11:05:45.905783 RX DQ/DQS(Engine): PASS
4900 11:05:45.905865 TX OE : NO K
4901 11:05:45.909313 All Pass.
4902 11:05:45.909419
4903 11:05:45.909542 CH 1, Rank 1
4904 11:05:45.912380 SW Impedance : PASS
4905 11:05:45.912461 DUTY Scan : NO K
4906 11:05:45.916123 ZQ Calibration : PASS
4907 11:05:45.918999 Jitter Meter : NO K
4908 11:05:45.919081 CBT Training : PASS
4909 11:05:45.922513 Write leveling : PASS
4910 11:05:45.925953 RX DQS gating : PASS
4911 11:05:45.926059 RX DQ/DQS(RDDQC) : PASS
4912 11:05:45.928988 TX DQ/DQS : PASS
4913 11:05:45.929069 RX DATLAT : PASS
4914 11:05:45.932312 RX DQ/DQS(Engine): PASS
4915 11:05:45.935715 TX OE : NO K
4916 11:05:45.935797 All Pass.
4917 11:05:45.935862
4918 11:05:45.939064 DramC Write-DBI off
4919 11:05:45.939145 PER_BANK_REFRESH: Hybrid Mode
4920 11:05:45.942439 TX_TRACKING: ON
4921 11:05:45.952077 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4922 11:05:45.955522 [FAST_K] Save calibration result to emmc
4923 11:05:45.959112 dramc_set_vcore_voltage set vcore to 662500
4924 11:05:45.959200 Read voltage for 933, 3
4925 11:05:45.962072 Vio18 = 0
4926 11:05:45.962156 Vcore = 662500
4927 11:05:45.962243 Vdram = 0
4928 11:05:45.965554 Vddq = 0
4929 11:05:45.965640 Vmddr = 0
4930 11:05:45.972300 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4931 11:05:45.975392 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4932 11:05:45.978832 MEM_TYPE=3, freq_sel=17
4933 11:05:45.981921 sv_algorithm_assistance_LP4_1600
4934 11:05:45.985385 ============ PULL DRAM RESETB DOWN ============
4935 11:05:45.988441 ========== PULL DRAM RESETB DOWN end =========
4936 11:05:45.995263 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4937 11:05:45.998508 ===================================
4938 11:05:45.998593 LPDDR4 DRAM CONFIGURATION
4939 11:05:46.001696 ===================================
4940 11:05:46.005084 EX_ROW_EN[0] = 0x0
4941 11:05:46.008557 EX_ROW_EN[1] = 0x0
4942 11:05:46.008643 LP4Y_EN = 0x0
4943 11:05:46.011823 WORK_FSP = 0x0
4944 11:05:46.011908 WL = 0x3
4945 11:05:46.015054 RL = 0x3
4946 11:05:46.015139 BL = 0x2
4947 11:05:46.018252 RPST = 0x0
4948 11:05:46.018361 RD_PRE = 0x0
4949 11:05:46.021738 WR_PRE = 0x1
4950 11:05:46.021819 WR_PST = 0x0
4951 11:05:46.024961 DBI_WR = 0x0
4952 11:05:46.025042 DBI_RD = 0x0
4953 11:05:46.028084 OTF = 0x1
4954 11:05:46.031676 ===================================
4955 11:05:46.034753 ===================================
4956 11:05:46.034835 ANA top config
4957 11:05:46.038122 ===================================
4958 11:05:46.041772 DLL_ASYNC_EN = 0
4959 11:05:46.044765 ALL_SLAVE_EN = 1
4960 11:05:46.048078 NEW_RANK_MODE = 1
4961 11:05:46.048220 DLL_IDLE_MODE = 1
4962 11:05:46.051246 LP45_APHY_COMB_EN = 1
4963 11:05:46.054789 TX_ODT_DIS = 1
4964 11:05:46.057983 NEW_8X_MODE = 1
4965 11:05:46.061440 ===================================
4966 11:05:46.064540 ===================================
4967 11:05:46.067842 data_rate = 1866
4968 11:05:46.067924 CKR = 1
4969 11:05:46.071230 DQ_P2S_RATIO = 8
4970 11:05:46.074618 ===================================
4971 11:05:46.077982 CA_P2S_RATIO = 8
4972 11:05:46.081146 DQ_CA_OPEN = 0
4973 11:05:46.084358 DQ_SEMI_OPEN = 0
4974 11:05:46.087770 CA_SEMI_OPEN = 0
4975 11:05:46.087852 CA_FULL_RATE = 0
4976 11:05:46.091271 DQ_CKDIV4_EN = 1
4977 11:05:46.094501 CA_CKDIV4_EN = 1
4978 11:05:46.097789 CA_PREDIV_EN = 0
4979 11:05:46.100845 PH8_DLY = 0
4980 11:05:46.104308 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4981 11:05:46.104390 DQ_AAMCK_DIV = 4
4982 11:05:46.107618 CA_AAMCK_DIV = 4
4983 11:05:46.110945 CA_ADMCK_DIV = 4
4984 11:05:46.114109 DQ_TRACK_CA_EN = 0
4985 11:05:46.117737 CA_PICK = 933
4986 11:05:46.120979 CA_MCKIO = 933
4987 11:05:46.121060 MCKIO_SEMI = 0
4988 11:05:46.124352 PLL_FREQ = 3732
4989 11:05:46.127343 DQ_UI_PI_RATIO = 32
4990 11:05:46.130927 CA_UI_PI_RATIO = 0
4991 11:05:46.134471 ===================================
4992 11:05:46.137371 ===================================
4993 11:05:46.140859 memory_type:LPDDR4
4994 11:05:46.140941 GP_NUM : 10
4995 11:05:46.144060 SRAM_EN : 1
4996 11:05:46.147504 MD32_EN : 0
4997 11:05:46.150658 ===================================
4998 11:05:46.150740 [ANA_INIT] >>>>>>>>>>>>>>
4999 11:05:46.154079 <<<<<< [CONFIGURE PHASE]: ANA_TX
5000 11:05:46.157617 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5001 11:05:46.160662 ===================================
5002 11:05:46.164264 data_rate = 1866,PCW = 0X8f00
5003 11:05:46.167301 ===================================
5004 11:05:46.170552 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5005 11:05:46.177297 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5006 11:05:46.180802 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5007 11:05:46.187340 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5008 11:05:46.190591 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5009 11:05:46.193956 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5010 11:05:46.194038 [ANA_INIT] flow start
5011 11:05:46.197207 [ANA_INIT] PLL >>>>>>>>
5012 11:05:46.200740 [ANA_INIT] PLL <<<<<<<<
5013 11:05:46.203880 [ANA_INIT] MIDPI >>>>>>>>
5014 11:05:46.203962 [ANA_INIT] MIDPI <<<<<<<<
5015 11:05:46.207382 [ANA_INIT] DLL >>>>>>>>
5016 11:05:46.210390 [ANA_INIT] flow end
5017 11:05:46.214118 ============ LP4 DIFF to SE enter ============
5018 11:05:46.217186 ============ LP4 DIFF to SE exit ============
5019 11:05:46.220606 [ANA_INIT] <<<<<<<<<<<<<
5020 11:05:46.223645 [Flow] Enable top DCM control >>>>>
5021 11:05:46.227020 [Flow] Enable top DCM control <<<<<
5022 11:05:46.230587 Enable DLL master slave shuffle
5023 11:05:46.233903 ==============================================================
5024 11:05:46.237188 Gating Mode config
5025 11:05:46.240480 ==============================================================
5026 11:05:46.243888 Config description:
5027 11:05:46.253643 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5028 11:05:46.260433 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5029 11:05:46.263595 SELPH_MODE 0: By rank 1: By Phase
5030 11:05:46.270411 ==============================================================
5031 11:05:46.273645 GAT_TRACK_EN = 1
5032 11:05:46.276653 RX_GATING_MODE = 2
5033 11:05:46.280109 RX_GATING_TRACK_MODE = 2
5034 11:05:46.283274 SELPH_MODE = 1
5035 11:05:46.286723 PICG_EARLY_EN = 1
5036 11:05:46.286805 VALID_LAT_VALUE = 1
5037 11:05:46.293419 ==============================================================
5038 11:05:46.296738 Enter into Gating configuration >>>>
5039 11:05:46.300110 Exit from Gating configuration <<<<
5040 11:05:46.303173 Enter into DVFS_PRE_config >>>>>
5041 11:05:46.313281 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5042 11:05:46.316493 Exit from DVFS_PRE_config <<<<<
5043 11:05:46.319544 Enter into PICG configuration >>>>
5044 11:05:46.322929 Exit from PICG configuration <<<<
5045 11:05:46.326438 [RX_INPUT] configuration >>>>>
5046 11:05:46.329539 [RX_INPUT] configuration <<<<<
5047 11:05:46.336292 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5048 11:05:46.339675 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5049 11:05:46.346016 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5050 11:05:46.352913 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5051 11:05:46.359535 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5052 11:05:46.366169 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5053 11:05:46.369308 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5054 11:05:46.372776 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5055 11:05:46.376110 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5056 11:05:46.382967 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5057 11:05:46.386126 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5058 11:05:46.389438 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5059 11:05:46.392529 ===================================
5060 11:05:46.395888 LPDDR4 DRAM CONFIGURATION
5061 11:05:46.399259 ===================================
5062 11:05:46.399341 EX_ROW_EN[0] = 0x0
5063 11:05:46.402823 EX_ROW_EN[1] = 0x0
5064 11:05:46.406097 LP4Y_EN = 0x0
5065 11:05:46.406180 WORK_FSP = 0x0
5066 11:05:46.409368 WL = 0x3
5067 11:05:46.409485 RL = 0x3
5068 11:05:46.412622 BL = 0x2
5069 11:05:46.412704 RPST = 0x0
5070 11:05:46.415866 RD_PRE = 0x0
5071 11:05:46.415948 WR_PRE = 0x1
5072 11:05:46.419037 WR_PST = 0x0
5073 11:05:46.419119 DBI_WR = 0x0
5074 11:05:46.422314 DBI_RD = 0x0
5075 11:05:46.422396 OTF = 0x1
5076 11:05:46.425821 ===================================
5077 11:05:46.429053 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5078 11:05:46.435842 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5079 11:05:46.438887 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5080 11:05:46.442278 ===================================
5081 11:05:46.445671 LPDDR4 DRAM CONFIGURATION
5082 11:05:46.448678 ===================================
5083 11:05:46.448761 EX_ROW_EN[0] = 0x10
5084 11:05:46.452105 EX_ROW_EN[1] = 0x0
5085 11:05:46.455407 LP4Y_EN = 0x0
5086 11:05:46.455489 WORK_FSP = 0x0
5087 11:05:46.458758 WL = 0x3
5088 11:05:46.458840 RL = 0x3
5089 11:05:46.461935 BL = 0x2
5090 11:05:46.462017 RPST = 0x0
5091 11:05:46.465425 RD_PRE = 0x0
5092 11:05:46.465544 WR_PRE = 0x1
5093 11:05:46.468556 WR_PST = 0x0
5094 11:05:46.468637 DBI_WR = 0x0
5095 11:05:46.472018 DBI_RD = 0x0
5096 11:05:46.472099 OTF = 0x1
5097 11:05:46.475088 ===================================
5098 11:05:46.481642 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5099 11:05:46.486328 nWR fixed to 30
5100 11:05:46.489643 [ModeRegInit_LP4] CH0 RK0
5101 11:05:46.489725 [ModeRegInit_LP4] CH0 RK1
5102 11:05:46.492836 [ModeRegInit_LP4] CH1 RK0
5103 11:05:46.496054 [ModeRegInit_LP4] CH1 RK1
5104 11:05:46.496162 match AC timing 9
5105 11:05:46.502801 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5106 11:05:46.506207 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5107 11:05:46.509594 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5108 11:05:46.515939 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5109 11:05:46.519485 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5110 11:05:46.519571 ==
5111 11:05:46.522570 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 11:05:46.526347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 11:05:46.526431 ==
5114 11:05:46.532811 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5115 11:05:46.539291 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5116 11:05:46.542459 [CA 0] Center 38 (7~69) winsize 63
5117 11:05:46.545657 [CA 1] Center 38 (8~69) winsize 62
5118 11:05:46.549281 [CA 2] Center 35 (5~65) winsize 61
5119 11:05:46.552240 [CA 3] Center 35 (5~65) winsize 61
5120 11:05:46.555746 [CA 4] Center 34 (4~64) winsize 61
5121 11:05:46.559229 [CA 5] Center 33 (3~64) winsize 62
5122 11:05:46.559312
5123 11:05:46.562301 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5124 11:05:46.562384
5125 11:05:46.565711 [CATrainingPosCal] consider 1 rank data
5126 11:05:46.568852 u2DelayCellTimex100 = 270/100 ps
5127 11:05:46.572353 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5128 11:05:46.575570 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5129 11:05:46.578907 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5130 11:05:46.582369 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5131 11:05:46.588986 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5132 11:05:46.592412 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5133 11:05:46.592495
5134 11:05:46.595380 CA PerBit enable=1, Macro0, CA PI delay=33
5135 11:05:46.595462
5136 11:05:46.598850 [CBTSetCACLKResult] CA Dly = 33
5137 11:05:46.598933 CS Dly: 7 (0~38)
5138 11:05:46.598998 ==
5139 11:05:46.601931 Dram Type= 6, Freq= 0, CH_0, rank 1
5140 11:05:46.608675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5141 11:05:46.608758 ==
5142 11:05:46.612272 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5143 11:05:46.618412 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5144 11:05:46.621924 [CA 0] Center 38 (8~69) winsize 62
5145 11:05:46.625024 [CA 1] Center 38 (8~69) winsize 62
5146 11:05:46.628319 [CA 2] Center 35 (5~66) winsize 62
5147 11:05:46.631785 [CA 3] Center 35 (5~65) winsize 61
5148 11:05:46.635355 [CA 4] Center 34 (3~65) winsize 63
5149 11:05:46.638500 [CA 5] Center 33 (3~64) winsize 62
5150 11:05:46.638582
5151 11:05:46.641858 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5152 11:05:46.641940
5153 11:05:46.645245 [CATrainingPosCal] consider 2 rank data
5154 11:05:46.648209 u2DelayCellTimex100 = 270/100 ps
5155 11:05:46.651899 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5156 11:05:46.655026 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5157 11:05:46.661684 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5158 11:05:46.664794 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5159 11:05:46.668389 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5160 11:05:46.671490 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5161 11:05:46.671573
5162 11:05:46.674941 CA PerBit enable=1, Macro0, CA PI delay=33
5163 11:05:46.675024
5164 11:05:46.678159 [CBTSetCACLKResult] CA Dly = 33
5165 11:05:46.678242 CS Dly: 7 (0~39)
5166 11:05:46.678336
5167 11:05:46.684854 ----->DramcWriteLeveling(PI) begin...
5168 11:05:46.684937 ==
5169 11:05:46.688116 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 11:05:46.691285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 11:05:46.691368 ==
5172 11:05:46.694603 Write leveling (Byte 0): 35 => 35
5173 11:05:46.698128 Write leveling (Byte 1): 30 => 30
5174 11:05:46.701329 DramcWriteLeveling(PI) end<-----
5175 11:05:46.701411
5176 11:05:46.701500 ==
5177 11:05:46.704540 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 11:05:46.707863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 11:05:46.707945 ==
5180 11:05:46.711366 [Gating] SW mode calibration
5181 11:05:46.717858 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5182 11:05:46.724738 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5183 11:05:46.727785 0 14 0 | B1->B0 | 2323 2e2e | 0 0 | (1 1) (0 0)
5184 11:05:46.731052 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
5185 11:05:46.737695 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5186 11:05:46.741233 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 11:05:46.744471 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 11:05:46.750862 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 11:05:46.754464 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 11:05:46.757573 0 14 28 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5191 11:05:46.764407 0 15 0 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (1 1)
5192 11:05:46.767606 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5193 11:05:46.771042 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 11:05:46.777271 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 11:05:46.780665 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 11:05:46.784125 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 11:05:46.790765 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 11:05:46.794037 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5199 11:05:46.797154 1 0 0 | B1->B0 | 2626 3e3e | 1 0 | (0 0) (1 1)
5200 11:05:46.803937 1 0 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5201 11:05:46.807012 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 11:05:46.810536 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 11:05:46.817303 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 11:05:46.820236 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 11:05:46.823718 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 11:05:46.826973 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 11:05:46.833605 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5208 11:05:46.836670 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5209 11:05:46.843477 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 11:05:46.846668 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 11:05:46.850176 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 11:05:46.853303 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 11:05:46.859918 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 11:05:46.863363 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 11:05:46.866518 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 11:05:46.873238 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 11:05:46.876775 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 11:05:46.880008 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 11:05:46.886343 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 11:05:46.889676 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 11:05:46.893180 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 11:05:46.899611 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5223 11:05:46.902893 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5224 11:05:46.906395 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 11:05:46.909387 Total UI for P1: 0, mck2ui 16
5226 11:05:46.912882 best dqsien dly found for B0: ( 1, 2, 30)
5227 11:05:46.916163 Total UI for P1: 0, mck2ui 16
5228 11:05:46.919858 best dqsien dly found for B1: ( 1, 3, 2)
5229 11:05:46.922771 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5230 11:05:46.925989 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5231 11:05:46.926070
5232 11:05:46.932758 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5233 11:05:46.936276 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5234 11:05:46.939290 [Gating] SW calibration Done
5235 11:05:46.939371 ==
5236 11:05:46.942783 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 11:05:46.945929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 11:05:46.946011 ==
5239 11:05:46.946076 RX Vref Scan: 0
5240 11:05:46.946136
5241 11:05:46.949415 RX Vref 0 -> 0, step: 1
5242 11:05:46.949526
5243 11:05:46.952610 RX Delay -80 -> 252, step: 8
5244 11:05:46.955998 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5245 11:05:46.959102 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5246 11:05:46.965779 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5247 11:05:46.968930 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5248 11:05:46.972375 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5249 11:05:46.975590 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5250 11:05:46.979052 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5251 11:05:46.982198 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5252 11:05:46.988949 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5253 11:05:46.992152 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5254 11:05:46.995581 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5255 11:05:46.998758 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5256 11:05:47.002312 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5257 11:05:47.008629 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5258 11:05:47.012245 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5259 11:05:47.015229 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5260 11:05:47.015311 ==
5261 11:05:47.018661 Dram Type= 6, Freq= 0, CH_0, rank 0
5262 11:05:47.021706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5263 11:05:47.025261 ==
5264 11:05:47.025343 DQS Delay:
5265 11:05:47.025408 DQS0 = 0, DQS1 = 0
5266 11:05:47.028242 DQM Delay:
5267 11:05:47.028323 DQM0 = 94, DQM1 = 82
5268 11:05:47.031689 DQ Delay:
5269 11:05:47.031771 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5270 11:05:47.035108 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107
5271 11:05:47.038637 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5272 11:05:47.044836 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5273 11:05:47.044918
5274 11:05:47.044982
5275 11:05:47.045042 ==
5276 11:05:47.048294 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 11:05:47.051479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 11:05:47.051583 ==
5279 11:05:47.051649
5280 11:05:47.051709
5281 11:05:47.055015 TX Vref Scan disable
5282 11:05:47.055097 == TX Byte 0 ==
5283 11:05:47.061445 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5284 11:05:47.064789 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5285 11:05:47.064871 == TX Byte 1 ==
5286 11:05:47.071204 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5287 11:05:47.074504 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5288 11:05:47.074586 ==
5289 11:05:47.078027 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 11:05:47.081489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 11:05:47.081571 ==
5292 11:05:47.081636
5293 11:05:47.081695
5294 11:05:47.084695 TX Vref Scan disable
5295 11:05:47.088024 == TX Byte 0 ==
5296 11:05:47.091216 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5297 11:05:47.094662 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5298 11:05:47.098010 == TX Byte 1 ==
5299 11:05:47.101287 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5300 11:05:47.107430 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5301 11:05:47.107511
5302 11:05:47.107575 [DATLAT]
5303 11:05:47.107635 Freq=933, CH0 RK0
5304 11:05:47.107692
5305 11:05:47.110963 DATLAT Default: 0xd
5306 11:05:47.111045 0, 0xFFFF, sum = 0
5307 11:05:47.114314 1, 0xFFFF, sum = 0
5308 11:05:47.114397 2, 0xFFFF, sum = 0
5309 11:05:47.117435 3, 0xFFFF, sum = 0
5310 11:05:47.120837 4, 0xFFFF, sum = 0
5311 11:05:47.120920 5, 0xFFFF, sum = 0
5312 11:05:47.124384 6, 0xFFFF, sum = 0
5313 11:05:47.124467 7, 0xFFFF, sum = 0
5314 11:05:47.127418 8, 0xFFFF, sum = 0
5315 11:05:47.127501 9, 0xFFFF, sum = 0
5316 11:05:47.130842 10, 0x0, sum = 1
5317 11:05:47.130924 11, 0x0, sum = 2
5318 11:05:47.134141 12, 0x0, sum = 3
5319 11:05:47.134224 13, 0x0, sum = 4
5320 11:05:47.134289 best_step = 11
5321 11:05:47.137300
5322 11:05:47.137380 ==
5323 11:05:47.140716 Dram Type= 6, Freq= 0, CH_0, rank 0
5324 11:05:47.143658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 11:05:47.143766 ==
5326 11:05:47.143857 RX Vref Scan: 1
5327 11:05:47.143927
5328 11:05:47.147022 RX Vref 0 -> 0, step: 1
5329 11:05:47.147104
5330 11:05:47.150806 RX Delay -77 -> 252, step: 4
5331 11:05:47.150887
5332 11:05:47.153856 Set Vref, RX VrefLevel [Byte0]: 61
5333 11:05:47.157112 [Byte1]: 54
5334 11:05:47.160379
5335 11:05:47.160486 Final RX Vref Byte 0 = 61 to rank0
5336 11:05:47.163986 Final RX Vref Byte 1 = 54 to rank0
5337 11:05:47.167186 Final RX Vref Byte 0 = 61 to rank1
5338 11:05:47.170375 Final RX Vref Byte 1 = 54 to rank1==
5339 11:05:47.173879 Dram Type= 6, Freq= 0, CH_0, rank 0
5340 11:05:47.180218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 11:05:47.180301 ==
5342 11:05:47.180365 DQS Delay:
5343 11:05:47.180424 DQS0 = 0, DQS1 = 0
5344 11:05:47.183597 DQM Delay:
5345 11:05:47.183679 DQM0 = 96, DQM1 = 83
5346 11:05:47.186716 DQ Delay:
5347 11:05:47.190161 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5348 11:05:47.193265 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =106
5349 11:05:47.196854 DQ8 =78, DQ9 =70, DQ10 =84, DQ11 =78
5350 11:05:47.199904 DQ12 =86, DQ13 =86, DQ14 =96, DQ15 =90
5351 11:05:47.199986
5352 11:05:47.200050
5353 11:05:47.206627 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 417 ps
5354 11:05:47.210058 CH0 RK0: MR19=505, MR18=F0E
5355 11:05:47.216558 CH0_RK0: MR19=0x505, MR18=0xF0E, DQSOSC=417, MR23=63, INC=62, DEC=41
5356 11:05:47.216644
5357 11:05:47.219838 ----->DramcWriteLeveling(PI) begin...
5358 11:05:47.219924 ==
5359 11:05:47.223224 Dram Type= 6, Freq= 0, CH_0, rank 1
5360 11:05:47.226522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 11:05:47.226605 ==
5362 11:05:47.229988 Write leveling (Byte 0): 33 => 33
5363 11:05:47.233019 Write leveling (Byte 1): 32 => 32
5364 11:05:47.236407 DramcWriteLeveling(PI) end<-----
5365 11:05:47.236489
5366 11:05:47.236554 ==
5367 11:05:47.239850 Dram Type= 6, Freq= 0, CH_0, rank 1
5368 11:05:47.242928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5369 11:05:47.243010 ==
5370 11:05:47.246340 [Gating] SW mode calibration
5371 11:05:47.253206 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5372 11:05:47.259522 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5373 11:05:47.263001 0 14 0 | B1->B0 | 2423 3434 | 1 1 | (0 0) (1 1)
5374 11:05:47.269535 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5375 11:05:47.273255 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 11:05:47.276394 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 11:05:47.282948 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 11:05:47.285931 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 11:05:47.289623 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 11:05:47.292600 0 14 28 | B1->B0 | 3434 2828 | 0 0 | (0 1) (1 1)
5381 11:05:47.299626 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5382 11:05:47.302739 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 11:05:47.305922 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 11:05:47.312790 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 11:05:47.315935 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 11:05:47.319285 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 11:05:47.325993 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 11:05:47.329172 0 15 28 | B1->B0 | 2323 3535 | 0 1 | (0 0) (1 1)
5389 11:05:47.332559 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5390 11:05:47.339219 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 11:05:47.342341 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 11:05:47.345743 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 11:05:47.352455 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 11:05:47.355905 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 11:05:47.358934 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 11:05:47.365971 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5397 11:05:47.369097 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 11:05:47.372205 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 11:05:47.378780 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 11:05:47.382290 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 11:05:47.385460 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 11:05:47.392087 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 11:05:47.395253 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 11:05:47.398837 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 11:05:47.405456 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 11:05:47.408799 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 11:05:47.412025 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 11:05:47.418707 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 11:05:47.422003 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 11:05:47.425438 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 11:05:47.432201 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 11:05:47.435355 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5413 11:05:47.438829 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5414 11:05:47.442157 Total UI for P1: 0, mck2ui 16
5415 11:05:47.445421 best dqsien dly found for B0: ( 1, 2, 28)
5416 11:05:47.451820 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5417 11:05:47.451903 Total UI for P1: 0, mck2ui 16
5418 11:05:47.455417 best dqsien dly found for B1: ( 1, 3, 0)
5419 11:05:47.461965 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5420 11:05:47.465236 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5421 11:05:47.465318
5422 11:05:47.468686 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5423 11:05:47.471810 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5424 11:05:47.475344 [Gating] SW calibration Done
5425 11:05:47.475426 ==
5426 11:05:47.478572 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 11:05:47.481643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 11:05:47.481726 ==
5429 11:05:47.485255 RX Vref Scan: 0
5430 11:05:47.485339
5431 11:05:47.485442 RX Vref 0 -> 0, step: 1
5432 11:05:47.485567
5433 11:05:47.488268 RX Delay -80 -> 252, step: 8
5434 11:05:47.491803 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5435 11:05:47.494810 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5436 11:05:47.501528 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5437 11:05:47.505082 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5438 11:05:47.508090 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5439 11:05:47.511385 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5440 11:05:47.515020 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5441 11:05:47.521412 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5442 11:05:47.524826 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5443 11:05:47.528189 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5444 11:05:47.531562 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5445 11:05:47.534636 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5446 11:05:47.541253 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5447 11:05:47.544607 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5448 11:05:47.548067 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5449 11:05:47.551306 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5450 11:05:47.551391 ==
5451 11:05:47.554655 Dram Type= 6, Freq= 0, CH_0, rank 1
5452 11:05:47.557842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5453 11:05:47.561306 ==
5454 11:05:47.561391 DQS Delay:
5455 11:05:47.561484 DQS0 = 0, DQS1 = 0
5456 11:05:47.564380 DQM Delay:
5457 11:05:47.564465 DQM0 = 90, DQM1 = 83
5458 11:05:47.567790 DQ Delay:
5459 11:05:47.571309 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5460 11:05:47.571394 DQ4 =91, DQ5 =75, DQ6 =99, DQ7 =103
5461 11:05:47.574638 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =75
5462 11:05:47.577656 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5463 11:05:47.581046
5464 11:05:47.581131
5465 11:05:47.581217 ==
5466 11:05:47.584270 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 11:05:47.587734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 11:05:47.587820 ==
5469 11:05:47.587907
5470 11:05:47.587988
5471 11:05:47.590835 TX Vref Scan disable
5472 11:05:47.590920 == TX Byte 0 ==
5473 11:05:47.597791 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5474 11:05:47.601058 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5475 11:05:47.601143 == TX Byte 1 ==
5476 11:05:47.607732 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5477 11:05:47.610956 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5478 11:05:47.611042 ==
5479 11:05:47.614366 Dram Type= 6, Freq= 0, CH_0, rank 1
5480 11:05:47.617318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 11:05:47.617403 ==
5482 11:05:47.617540
5483 11:05:47.617623
5484 11:05:47.620684 TX Vref Scan disable
5485 11:05:47.624163 == TX Byte 0 ==
5486 11:05:47.627409 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5487 11:05:47.630386 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5488 11:05:47.633728 == TX Byte 1 ==
5489 11:05:47.637189 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5490 11:05:47.640470 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5491 11:05:47.640553
5492 11:05:47.643731 [DATLAT]
5493 11:05:47.643813 Freq=933, CH0 RK1
5494 11:05:47.643879
5495 11:05:47.647322 DATLAT Default: 0xb
5496 11:05:47.647405 0, 0xFFFF, sum = 0
5497 11:05:47.650333 1, 0xFFFF, sum = 0
5498 11:05:47.650421 2, 0xFFFF, sum = 0
5499 11:05:47.653853 3, 0xFFFF, sum = 0
5500 11:05:47.653937 4, 0xFFFF, sum = 0
5501 11:05:47.657230 5, 0xFFFF, sum = 0
5502 11:05:47.657314 6, 0xFFFF, sum = 0
5503 11:05:47.660402 7, 0xFFFF, sum = 0
5504 11:05:47.663679 8, 0xFFFF, sum = 0
5505 11:05:47.663764 9, 0xFFFF, sum = 0
5506 11:05:47.663830 10, 0x0, sum = 1
5507 11:05:47.667034 11, 0x0, sum = 2
5508 11:05:47.667117 12, 0x0, sum = 3
5509 11:05:47.670337 13, 0x0, sum = 4
5510 11:05:47.670421 best_step = 11
5511 11:05:47.670487
5512 11:05:47.670548 ==
5513 11:05:47.673671 Dram Type= 6, Freq= 0, CH_0, rank 1
5514 11:05:47.680389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 11:05:47.680471 ==
5516 11:05:47.680537 RX Vref Scan: 0
5517 11:05:47.680597
5518 11:05:47.683737 RX Vref 0 -> 0, step: 1
5519 11:05:47.683819
5520 11:05:47.687060 RX Delay -77 -> 252, step: 4
5521 11:05:47.690023 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5522 11:05:47.697007 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5523 11:05:47.700161 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5524 11:05:47.703308 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5525 11:05:47.706783 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5526 11:05:47.710046 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5527 11:05:47.713255 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5528 11:05:47.720173 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5529 11:05:47.723451 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5530 11:05:47.726555 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5531 11:05:47.729867 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5532 11:05:47.733316 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5533 11:05:47.740038 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5534 11:05:47.743034 iDelay=199, Bit 13, Center 88 (-5 ~ 182) 188
5535 11:05:47.746478 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5536 11:05:47.749678 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5537 11:05:47.749760 ==
5538 11:05:47.753314 Dram Type= 6, Freq= 0, CH_0, rank 1
5539 11:05:47.759698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5540 11:05:47.759781 ==
5541 11:05:47.759847 DQS Delay:
5542 11:05:47.759908 DQS0 = 0, DQS1 = 0
5543 11:05:47.763277 DQM Delay:
5544 11:05:47.763359 DQM0 = 92, DQM1 = 84
5545 11:05:47.766488 DQ Delay:
5546 11:05:47.769821 DQ0 =92, DQ1 =94, DQ2 =88, DQ3 =88
5547 11:05:47.773066 DQ4 =90, DQ5 =80, DQ6 =106, DQ7 =104
5548 11:05:47.776616 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =78
5549 11:05:47.779719 DQ12 =90, DQ13 =88, DQ14 =94, DQ15 =92
5550 11:05:47.779801
5551 11:05:47.779866
5552 11:05:47.786543 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5553 11:05:47.789833 CH0 RK1: MR19=505, MR18=2C0E
5554 11:05:47.796488 CH0_RK1: MR19=0x505, MR18=0x2C0E, DQSOSC=408, MR23=63, INC=65, DEC=43
5555 11:05:47.799938 [RxdqsGatingPostProcess] freq 933
5556 11:05:47.803273 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5557 11:05:47.806216 best DQS0 dly(2T, 0.5T) = (0, 10)
5558 11:05:47.809745 best DQS1 dly(2T, 0.5T) = (0, 11)
5559 11:05:47.812831 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5560 11:05:47.816380 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5561 11:05:47.819494 best DQS0 dly(2T, 0.5T) = (0, 10)
5562 11:05:47.822994 best DQS1 dly(2T, 0.5T) = (0, 11)
5563 11:05:47.826534 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5564 11:05:47.829366 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5565 11:05:47.832820 Pre-setting of DQS Precalculation
5566 11:05:47.836340 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5567 11:05:47.836423 ==
5568 11:05:47.839532 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 11:05:47.846090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 11:05:47.846188 ==
5571 11:05:47.849402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5572 11:05:47.856075 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5573 11:05:47.859204 [CA 0] Center 36 (7~66) winsize 60
5574 11:05:47.862786 [CA 1] Center 37 (7~67) winsize 61
5575 11:05:47.865854 [CA 2] Center 34 (5~64) winsize 60
5576 11:05:47.869178 [CA 3] Center 34 (4~64) winsize 61
5577 11:05:47.872767 [CA 4] Center 34 (5~64) winsize 60
5578 11:05:47.875841 [CA 5] Center 33 (4~63) winsize 60
5579 11:05:47.875922
5580 11:05:47.879122 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5581 11:05:47.879204
5582 11:05:47.882667 [CATrainingPosCal] consider 1 rank data
5583 11:05:47.885835 u2DelayCellTimex100 = 270/100 ps
5584 11:05:47.888862 CA0 delay=36 (7~66),Diff = 3 PI (18 cell)
5585 11:05:47.895642 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5586 11:05:47.899090 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5587 11:05:47.902388 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5588 11:05:47.905707 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5589 11:05:47.909103 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5590 11:05:47.909185
5591 11:05:47.912360 CA PerBit enable=1, Macro0, CA PI delay=33
5592 11:05:47.912443
5593 11:05:47.915757 [CBTSetCACLKResult] CA Dly = 33
5594 11:05:47.915839 CS Dly: 6 (0~37)
5595 11:05:47.919040 ==
5596 11:05:47.922198 Dram Type= 6, Freq= 0, CH_1, rank 1
5597 11:05:47.925352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5598 11:05:47.925461 ==
5599 11:05:47.928793 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5600 11:05:47.935228 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5601 11:05:47.939025 [CA 0] Center 37 (8~67) winsize 60
5602 11:05:47.942604 [CA 1] Center 37 (7~68) winsize 62
5603 11:05:47.945564 [CA 2] Center 35 (5~65) winsize 61
5604 11:05:47.948918 [CA 3] Center 33 (3~64) winsize 62
5605 11:05:47.952252 [CA 4] Center 34 (4~65) winsize 62
5606 11:05:47.955859 [CA 5] Center 33 (3~64) winsize 62
5607 11:05:47.955940
5608 11:05:47.959218 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5609 11:05:47.959300
5610 11:05:47.962361 [CATrainingPosCal] consider 2 rank data
5611 11:05:47.965788 u2DelayCellTimex100 = 270/100 ps
5612 11:05:47.968852 CA0 delay=37 (8~66),Diff = 4 PI (24 cell)
5613 11:05:47.975742 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5614 11:05:47.979045 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5615 11:05:47.982443 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5616 11:05:47.985625 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5617 11:05:47.988919 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5618 11:05:47.989004
5619 11:05:47.991907 CA PerBit enable=1, Macro0, CA PI delay=33
5620 11:05:47.991988
5621 11:05:47.995192 [CBTSetCACLKResult] CA Dly = 33
5622 11:05:47.998427 CS Dly: 7 (0~39)
5623 11:05:47.998531
5624 11:05:48.002172 ----->DramcWriteLeveling(PI) begin...
5625 11:05:48.002256 ==
5626 11:05:48.005147 Dram Type= 6, Freq= 0, CH_1, rank 0
5627 11:05:48.008632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5628 11:05:48.008705 ==
5629 11:05:48.011736 Write leveling (Byte 0): 27 => 27
5630 11:05:48.015384 Write leveling (Byte 1): 27 => 27
5631 11:05:48.018526 DramcWriteLeveling(PI) end<-----
5632 11:05:48.018609
5633 11:05:48.018674 ==
5634 11:05:48.022037 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 11:05:48.025298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 11:05:48.025379 ==
5637 11:05:48.028363 [Gating] SW mode calibration
5638 11:05:48.034786 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5639 11:05:48.041788 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5640 11:05:48.045029 0 14 0 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 1)
5641 11:05:48.048026 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 11:05:48.054780 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 11:05:48.057974 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5644 11:05:48.061495 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 11:05:48.067873 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 11:05:48.071106 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 11:05:48.074601 0 14 28 | B1->B0 | 2e2e 2f2f | 0 1 | (1 0) (1 0)
5648 11:05:48.081191 0 15 0 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
5649 11:05:48.084685 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 11:05:48.087830 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 11:05:48.094457 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 11:05:48.097633 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 11:05:48.100705 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 11:05:48.107296 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 11:05:48.110693 0 15 28 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
5656 11:05:48.114219 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5657 11:05:48.120714 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 11:05:48.124055 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 11:05:48.127451 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 11:05:48.134074 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 11:05:48.137175 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 11:05:48.140680 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 11:05:48.147382 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5664 11:05:48.153876 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 11:05:48.153958 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 11:05:48.160463 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 11:05:48.164054 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 11:05:48.167080 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 11:05:48.173591 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 11:05:48.176897 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 11:05:48.180212 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 11:05:48.186885 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 11:05:48.190334 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 11:05:48.193345 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 11:05:48.199832 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 11:05:48.203225 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 11:05:48.206681 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 11:05:48.213030 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 11:05:48.216374 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5680 11:05:48.219646 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 11:05:48.223084 Total UI for P1: 0, mck2ui 16
5682 11:05:48.226327 best dqsien dly found for B0: ( 1, 2, 28)
5683 11:05:48.229789 Total UI for P1: 0, mck2ui 16
5684 11:05:48.232946 best dqsien dly found for B1: ( 1, 2, 28)
5685 11:05:48.236416 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5686 11:05:48.239975 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5687 11:05:48.240057
5688 11:05:48.246091 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5689 11:05:48.249715 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5690 11:05:48.249824 [Gating] SW calibration Done
5691 11:05:48.252840 ==
5692 11:05:48.256354 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 11:05:48.259260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 11:05:48.259342 ==
5695 11:05:48.259408 RX Vref Scan: 0
5696 11:05:48.259468
5697 11:05:48.262615 RX Vref 0 -> 0, step: 1
5698 11:05:48.262697
5699 11:05:48.265839 RX Delay -80 -> 252, step: 8
5700 11:05:48.269322 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5701 11:05:48.272625 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5702 11:05:48.276105 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5703 11:05:48.282635 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5704 11:05:48.286035 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5705 11:05:48.289418 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5706 11:05:48.292506 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5707 11:05:48.295868 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5708 11:05:48.299311 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5709 11:05:48.305595 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5710 11:05:48.309217 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5711 11:05:48.312216 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5712 11:05:48.315858 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5713 11:05:48.318896 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5714 11:05:48.325720 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5715 11:05:48.329047 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5716 11:05:48.329156 ==
5717 11:05:48.332332 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 11:05:48.335823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 11:05:48.335906 ==
5720 11:05:48.338941 DQS Delay:
5721 11:05:48.339022 DQS0 = 0, DQS1 = 0
5722 11:05:48.339088 DQM Delay:
5723 11:05:48.342085 DQM0 = 96, DQM1 = 89
5724 11:05:48.342167 DQ Delay:
5725 11:05:48.345465 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =91
5726 11:05:48.348698 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =95
5727 11:05:48.352223 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5728 11:05:48.355390 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5729 11:05:48.355566
5730 11:05:48.355699
5731 11:05:48.355773 ==
5732 11:05:48.358531 Dram Type= 6, Freq= 0, CH_1, rank 0
5733 11:05:48.365397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 11:05:48.365537 ==
5735 11:05:48.365605
5736 11:05:48.365665
5737 11:05:48.365722 TX Vref Scan disable
5738 11:05:48.368847 == TX Byte 0 ==
5739 11:05:48.372313 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5740 11:05:48.378817 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5741 11:05:48.378899 == TX Byte 1 ==
5742 11:05:48.382086 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5743 11:05:48.388705 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5744 11:05:48.388787 ==
5745 11:05:48.392033 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 11:05:48.395253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 11:05:48.395335 ==
5748 11:05:48.395400
5749 11:05:48.395459
5750 11:05:48.398795 TX Vref Scan disable
5751 11:05:48.398879 == TX Byte 0 ==
5752 11:05:48.405220 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5753 11:05:48.408600 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5754 11:05:48.408682 == TX Byte 1 ==
5755 11:05:48.415177 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5756 11:05:48.418546 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5757 11:05:48.418628
5758 11:05:48.418693 [DATLAT]
5759 11:05:48.421749 Freq=933, CH1 RK0
5760 11:05:48.421831
5761 11:05:48.421895 DATLAT Default: 0xd
5762 11:05:48.425070 0, 0xFFFF, sum = 0
5763 11:05:48.425153 1, 0xFFFF, sum = 0
5764 11:05:48.428537 2, 0xFFFF, sum = 0
5765 11:05:48.431788 3, 0xFFFF, sum = 0
5766 11:05:48.431871 4, 0xFFFF, sum = 0
5767 11:05:48.435157 5, 0xFFFF, sum = 0
5768 11:05:48.435240 6, 0xFFFF, sum = 0
5769 11:05:48.438472 7, 0xFFFF, sum = 0
5770 11:05:48.438556 8, 0xFFFF, sum = 0
5771 11:05:48.441653 9, 0xFFFF, sum = 0
5772 11:05:48.441736 10, 0x0, sum = 1
5773 11:05:48.445190 11, 0x0, sum = 2
5774 11:05:48.445273 12, 0x0, sum = 3
5775 11:05:48.448272 13, 0x0, sum = 4
5776 11:05:48.448355 best_step = 11
5777 11:05:48.448419
5778 11:05:48.448479 ==
5779 11:05:48.451659 Dram Type= 6, Freq= 0, CH_1, rank 0
5780 11:05:48.454848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 11:05:48.454930 ==
5782 11:05:48.458364 RX Vref Scan: 1
5783 11:05:48.458446
5784 11:05:48.461514 RX Vref 0 -> 0, step: 1
5785 11:05:48.461595
5786 11:05:48.461660 RX Delay -61 -> 252, step: 4
5787 11:05:48.461720
5788 11:05:48.465027 Set Vref, RX VrefLevel [Byte0]: 59
5789 11:05:48.468264 [Byte1]: 51
5790 11:05:48.472927
5791 11:05:48.473008 Final RX Vref Byte 0 = 59 to rank0
5792 11:05:48.475981 Final RX Vref Byte 1 = 51 to rank0
5793 11:05:48.479363 Final RX Vref Byte 0 = 59 to rank1
5794 11:05:48.482580 Final RX Vref Byte 1 = 51 to rank1==
5795 11:05:48.485976 Dram Type= 6, Freq= 0, CH_1, rank 0
5796 11:05:48.492857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5797 11:05:48.492940 ==
5798 11:05:48.493006 DQS Delay:
5799 11:05:48.493065 DQS0 = 0, DQS1 = 0
5800 11:05:48.495927 DQM Delay:
5801 11:05:48.496010 DQM0 = 94, DQM1 = 88
5802 11:05:48.499482 DQ Delay:
5803 11:05:48.502555 DQ0 =98, DQ1 =90, DQ2 =84, DQ3 =92
5804 11:05:48.506030 DQ4 =92, DQ5 =104, DQ6 =106, DQ7 =92
5805 11:05:48.509423 DQ8 =78, DQ9 =80, DQ10 =88, DQ11 =80
5806 11:05:48.512748 DQ12 =98, DQ13 =92, DQ14 =94, DQ15 =94
5807 11:05:48.512835
5808 11:05:48.512921
5809 11:05:48.519343 [DQSOSCAuto] RK0, (LSB)MR18= 0x20b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5810 11:05:48.522651 CH1 RK0: MR19=505, MR18=20B
5811 11:05:48.529116 CH1_RK0: MR19=0x505, MR18=0x20B, DQSOSC=418, MR23=63, INC=62, DEC=41
5812 11:05:48.529203
5813 11:05:48.532597 ----->DramcWriteLeveling(PI) begin...
5814 11:05:48.532683 ==
5815 11:05:48.535606 Dram Type= 6, Freq= 0, CH_1, rank 1
5816 11:05:48.539233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 11:05:48.539319 ==
5818 11:05:48.542239 Write leveling (Byte 0): 26 => 26
5819 11:05:48.545752 Write leveling (Byte 1): 27 => 27
5820 11:05:48.548782 DramcWriteLeveling(PI) end<-----
5821 11:05:48.548869
5822 11:05:48.548955 ==
5823 11:05:48.552032 Dram Type= 6, Freq= 0, CH_1, rank 1
5824 11:05:48.555438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 11:05:48.555524 ==
5826 11:05:48.558795 [Gating] SW mode calibration
5827 11:05:48.565395 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5828 11:05:48.571878 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5829 11:05:48.575374 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5830 11:05:48.582014 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 11:05:48.585259 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5832 11:05:48.588516 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 11:05:48.595127 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 11:05:48.598168 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 11:05:48.601655 0 14 24 | B1->B0 | 3232 2f2f | 1 0 | (1 1) (0 0)
5836 11:05:48.608324 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
5837 11:05:48.611715 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 11:05:48.614867 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 11:05:48.621735 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 11:05:48.624749 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 11:05:48.628037 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 11:05:48.634811 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 11:05:48.637953 0 15 24 | B1->B0 | 2b2b 3838 | 0 0 | (0 0) (0 0)
5844 11:05:48.641457 0 15 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5845 11:05:48.647927 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 11:05:48.651322 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 11:05:48.654523 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 11:05:48.661293 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 11:05:48.664581 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 11:05:48.667957 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 11:05:48.671194 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5852 11:05:48.677880 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5853 11:05:48.681389 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 11:05:48.684595 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 11:05:48.691316 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 11:05:48.694793 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 11:05:48.698095 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 11:05:48.704841 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 11:05:48.707919 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 11:05:48.711338 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 11:05:48.717947 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 11:05:48.721258 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 11:05:48.724612 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 11:05:48.731260 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 11:05:48.734259 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 11:05:48.737606 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 11:05:48.744122 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 11:05:48.747479 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5869 11:05:48.750923 Total UI for P1: 0, mck2ui 16
5870 11:05:48.754017 best dqsien dly found for B0: ( 1, 2, 26)
5871 11:05:48.757452 Total UI for P1: 0, mck2ui 16
5872 11:05:48.760574 best dqsien dly found for B1: ( 1, 2, 26)
5873 11:05:48.764156 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5874 11:05:48.767224 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5875 11:05:48.767309
5876 11:05:48.770441 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5877 11:05:48.773933 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5878 11:05:48.776929 [Gating] SW calibration Done
5879 11:05:48.777014 ==
5880 11:05:48.780237 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 11:05:48.786928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 11:05:48.787014 ==
5883 11:05:48.787101 RX Vref Scan: 0
5884 11:05:48.787183
5885 11:05:48.790264 RX Vref 0 -> 0, step: 1
5886 11:05:48.790349
5887 11:05:48.793600 RX Delay -80 -> 252, step: 8
5888 11:05:48.797065 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5889 11:05:48.800336 iDelay=208, Bit 1, Center 83 (-16 ~ 183) 200
5890 11:05:48.803417 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5891 11:05:48.807073 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5892 11:05:48.813552 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5893 11:05:48.816656 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5894 11:05:48.820153 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5895 11:05:48.823420 iDelay=208, Bit 7, Center 87 (-16 ~ 191) 208
5896 11:05:48.826692 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5897 11:05:48.833521 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5898 11:05:48.836814 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5899 11:05:48.839965 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5900 11:05:48.843440 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5901 11:05:48.846556 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5902 11:05:48.853226 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5903 11:05:48.856545 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5904 11:05:48.856630 ==
5905 11:05:48.859661 Dram Type= 6, Freq= 0, CH_1, rank 1
5906 11:05:48.863058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5907 11:05:48.863144 ==
5908 11:05:48.863232 DQS Delay:
5909 11:05:48.866526 DQS0 = 0, DQS1 = 0
5910 11:05:48.866612 DQM Delay:
5911 11:05:48.869583 DQM0 = 92, DQM1 = 87
5912 11:05:48.869669 DQ Delay:
5913 11:05:48.873065 DQ0 =99, DQ1 =83, DQ2 =83, DQ3 =87
5914 11:05:48.876701 DQ4 =91, DQ5 =103, DQ6 =107, DQ7 =87
5915 11:05:48.879666 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5916 11:05:48.883087 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5917 11:05:48.883173
5918 11:05:48.883259
5919 11:05:48.883341 ==
5920 11:05:48.886064 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 11:05:48.892935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 11:05:48.893020 ==
5923 11:05:48.893107
5924 11:05:48.893189
5925 11:05:48.893268 TX Vref Scan disable
5926 11:05:48.896381 == TX Byte 0 ==
5927 11:05:48.899414 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5928 11:05:48.906145 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5929 11:05:48.906231 == TX Byte 1 ==
5930 11:05:48.909514 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5931 11:05:48.916193 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5932 11:05:48.916280 ==
5933 11:05:48.919202 Dram Type= 6, Freq= 0, CH_1, rank 1
5934 11:05:48.922632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5935 11:05:48.922718 ==
5936 11:05:48.922804
5937 11:05:48.922886
5938 11:05:48.926021 TX Vref Scan disable
5939 11:05:48.926113 == TX Byte 0 ==
5940 11:05:48.932549 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5941 11:05:48.935951 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5942 11:05:48.936037 == TX Byte 1 ==
5943 11:05:48.942547 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5944 11:05:48.945994 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5945 11:05:48.946080
5946 11:05:48.946165 [DATLAT]
5947 11:05:48.949107 Freq=933, CH1 RK1
5948 11:05:48.949192
5949 11:05:48.949279 DATLAT Default: 0xb
5950 11:05:48.952444 0, 0xFFFF, sum = 0
5951 11:05:48.952530 1, 0xFFFF, sum = 0
5952 11:05:48.955943 2, 0xFFFF, sum = 0
5953 11:05:48.956029 3, 0xFFFF, sum = 0
5954 11:05:48.959039 4, 0xFFFF, sum = 0
5955 11:05:48.962399 5, 0xFFFF, sum = 0
5956 11:05:48.962486 6, 0xFFFF, sum = 0
5957 11:05:48.965995 7, 0xFFFF, sum = 0
5958 11:05:48.966082 8, 0xFFFF, sum = 0
5959 11:05:48.969029 9, 0xFFFF, sum = 0
5960 11:05:48.969116 10, 0x0, sum = 1
5961 11:05:48.972237 11, 0x0, sum = 2
5962 11:05:48.972323 12, 0x0, sum = 3
5963 11:05:48.972411 13, 0x0, sum = 4
5964 11:05:48.975611 best_step = 11
5965 11:05:48.975697
5966 11:05:48.975783 ==
5967 11:05:48.979259 Dram Type= 6, Freq= 0, CH_1, rank 1
5968 11:05:48.982316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5969 11:05:48.982401 ==
5970 11:05:48.985681 RX Vref Scan: 0
5971 11:05:48.985765
5972 11:05:48.985852 RX Vref 0 -> 0, step: 1
5973 11:05:48.989046
5974 11:05:48.989131 RX Delay -69 -> 252, step: 4
5975 11:05:48.996475 iDelay=199, Bit 0, Center 96 (-1 ~ 194) 196
5976 11:05:49.000023 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5977 11:05:49.003193 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5978 11:05:49.006752 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5979 11:05:49.009788 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5980 11:05:49.016310 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5981 11:05:49.019793 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5982 11:05:49.023130 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5983 11:05:49.026448 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5984 11:05:49.029719 iDelay=199, Bit 9, Center 80 (-13 ~ 174) 188
5985 11:05:49.036327 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5986 11:05:49.039409 iDelay=199, Bit 11, Center 84 (-9 ~ 178) 188
5987 11:05:49.042817 iDelay=199, Bit 12, Center 98 (7 ~ 190) 184
5988 11:05:49.046268 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5989 11:05:49.049458 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5990 11:05:49.053072 iDelay=199, Bit 15, Center 96 (3 ~ 190) 188
5991 11:05:49.056224 ==
5992 11:05:49.056303 Dram Type= 6, Freq= 0, CH_1, rank 1
5993 11:05:49.062780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5994 11:05:49.062870 ==
5995 11:05:49.062958 DQS Delay:
5996 11:05:49.066038 DQS0 = 0, DQS1 = 0
5997 11:05:49.066123 DQM Delay:
5998 11:05:49.069300 DQM0 = 94, DQM1 = 90
5999 11:05:49.069384 DQ Delay:
6000 11:05:49.072880 DQ0 =96, DQ1 =90, DQ2 =84, DQ3 =92
6001 11:05:49.076132 DQ4 =90, DQ5 =104, DQ6 =104, DQ7 =92
6002 11:05:49.079562 DQ8 =78, DQ9 =80, DQ10 =92, DQ11 =84
6003 11:05:49.082595 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =96
6004 11:05:49.082680
6005 11:05:49.082767
6006 11:05:49.089398 [DQSOSCAuto] RK1, (LSB)MR18= 0x1025, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
6007 11:05:49.092725 CH1 RK1: MR19=505, MR18=1025
6008 11:05:49.099352 CH1_RK1: MR19=0x505, MR18=0x1025, DQSOSC=410, MR23=63, INC=64, DEC=42
6009 11:05:49.102397 [RxdqsGatingPostProcess] freq 933
6010 11:05:49.109317 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6011 11:05:49.109403 best DQS0 dly(2T, 0.5T) = (0, 10)
6012 11:05:49.112391 best DQS1 dly(2T, 0.5T) = (0, 10)
6013 11:05:49.115742 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6014 11:05:49.119025 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6015 11:05:49.122347 best DQS0 dly(2T, 0.5T) = (0, 10)
6016 11:05:49.125757 best DQS1 dly(2T, 0.5T) = (0, 10)
6017 11:05:49.128915 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6018 11:05:49.132318 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6019 11:05:49.135541 Pre-setting of DQS Precalculation
6020 11:05:49.142341 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6021 11:05:49.148685 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6022 11:05:49.155250 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6023 11:05:49.155332
6024 11:05:49.155397
6025 11:05:49.158759 [Calibration Summary] 1866 Mbps
6026 11:05:49.158840 CH 0, Rank 0
6027 11:05:49.162100 SW Impedance : PASS
6028 11:05:49.165286 DUTY Scan : NO K
6029 11:05:49.165367 ZQ Calibration : PASS
6030 11:05:49.168657 Jitter Meter : NO K
6031 11:05:49.168739 CBT Training : PASS
6032 11:05:49.172269 Write leveling : PASS
6033 11:05:49.175485 RX DQS gating : PASS
6034 11:05:49.175570 RX DQ/DQS(RDDQC) : PASS
6035 11:05:49.178670 TX DQ/DQS : PASS
6036 11:05:49.181681 RX DATLAT : PASS
6037 11:05:49.181762 RX DQ/DQS(Engine): PASS
6038 11:05:49.185037 TX OE : NO K
6039 11:05:49.185145 All Pass.
6040 11:05:49.185238
6041 11:05:49.188483 CH 0, Rank 1
6042 11:05:49.188564 SW Impedance : PASS
6043 11:05:49.191928 DUTY Scan : NO K
6044 11:05:49.195053 ZQ Calibration : PASS
6045 11:05:49.195134 Jitter Meter : NO K
6046 11:05:49.198554 CBT Training : PASS
6047 11:05:49.201586 Write leveling : PASS
6048 11:05:49.201668 RX DQS gating : PASS
6049 11:05:49.205084 RX DQ/DQS(RDDQC) : PASS
6050 11:05:49.208433 TX DQ/DQS : PASS
6051 11:05:49.208515 RX DATLAT : PASS
6052 11:05:49.211856 RX DQ/DQS(Engine): PASS
6053 11:05:49.214946 TX OE : NO K
6054 11:05:49.215027 All Pass.
6055 11:05:49.215093
6056 11:05:49.215152 CH 1, Rank 0
6057 11:05:49.218425 SW Impedance : PASS
6058 11:05:49.221669 DUTY Scan : NO K
6059 11:05:49.221751 ZQ Calibration : PASS
6060 11:05:49.224972 Jitter Meter : NO K
6061 11:05:49.228442 CBT Training : PASS
6062 11:05:49.228523 Write leveling : PASS
6063 11:05:49.231689 RX DQS gating : PASS
6064 11:05:49.231771 RX DQ/DQS(RDDQC) : PASS
6065 11:05:49.234862 TX DQ/DQS : PASS
6066 11:05:49.238584 RX DATLAT : PASS
6067 11:05:49.238666 RX DQ/DQS(Engine): PASS
6068 11:05:49.241607 TX OE : NO K
6069 11:05:49.241690 All Pass.
6070 11:05:49.241755
6071 11:05:49.244707 CH 1, Rank 1
6072 11:05:49.244788 SW Impedance : PASS
6073 11:05:49.248096 DUTY Scan : NO K
6074 11:05:49.251483 ZQ Calibration : PASS
6075 11:05:49.251564 Jitter Meter : NO K
6076 11:05:49.254557 CBT Training : PASS
6077 11:05:49.257994 Write leveling : PASS
6078 11:05:49.258076 RX DQS gating : PASS
6079 11:05:49.261352 RX DQ/DQS(RDDQC) : PASS
6080 11:05:49.264765 TX DQ/DQS : PASS
6081 11:05:49.264847 RX DATLAT : PASS
6082 11:05:49.267830 RX DQ/DQS(Engine): PASS
6083 11:05:49.271206 TX OE : NO K
6084 11:05:49.271288 All Pass.
6085 11:05:49.271353
6086 11:05:49.274599 DramC Write-DBI off
6087 11:05:49.274681 PER_BANK_REFRESH: Hybrid Mode
6088 11:05:49.278086 TX_TRACKING: ON
6089 11:05:49.284537 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6090 11:05:49.291051 [FAST_K] Save calibration result to emmc
6091 11:05:49.294465 dramc_set_vcore_voltage set vcore to 650000
6092 11:05:49.294547 Read voltage for 400, 6
6093 11:05:49.297627 Vio18 = 0
6094 11:05:49.297709 Vcore = 650000
6095 11:05:49.297774 Vdram = 0
6096 11:05:49.301099 Vddq = 0
6097 11:05:49.301181 Vmddr = 0
6098 11:05:49.304201 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6099 11:05:49.310800 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6100 11:05:49.314203 MEM_TYPE=3, freq_sel=20
6101 11:05:49.317541 sv_algorithm_assistance_LP4_800
6102 11:05:49.321192 ============ PULL DRAM RESETB DOWN ============
6103 11:05:49.324209 ========== PULL DRAM RESETB DOWN end =========
6104 11:05:49.327624 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6105 11:05:49.330841 ===================================
6106 11:05:49.334007 LPDDR4 DRAM CONFIGURATION
6107 11:05:49.337461 ===================================
6108 11:05:49.341148 EX_ROW_EN[0] = 0x0
6109 11:05:49.341230 EX_ROW_EN[1] = 0x0
6110 11:05:49.344218 LP4Y_EN = 0x0
6111 11:05:49.344303 WORK_FSP = 0x0
6112 11:05:49.347338 WL = 0x2
6113 11:05:49.347420 RL = 0x2
6114 11:05:49.350829 BL = 0x2
6115 11:05:49.350910 RPST = 0x0
6116 11:05:49.354029 RD_PRE = 0x0
6117 11:05:49.354110 WR_PRE = 0x1
6118 11:05:49.357432 WR_PST = 0x0
6119 11:05:49.360747 DBI_WR = 0x0
6120 11:05:49.360829 DBI_RD = 0x0
6121 11:05:49.364092 OTF = 0x1
6122 11:05:49.367496 ===================================
6123 11:05:49.370552 ===================================
6124 11:05:49.370635 ANA top config
6125 11:05:49.374032 ===================================
6126 11:05:49.377340 DLL_ASYNC_EN = 0
6127 11:05:49.380580 ALL_SLAVE_EN = 1
6128 11:05:49.380662 NEW_RANK_MODE = 1
6129 11:05:49.383795 DLL_IDLE_MODE = 1
6130 11:05:49.387439 LP45_APHY_COMB_EN = 1
6131 11:05:49.390579 TX_ODT_DIS = 1
6132 11:05:49.390662 NEW_8X_MODE = 1
6133 11:05:49.393828 ===================================
6134 11:05:49.397057 ===================================
6135 11:05:49.400510 data_rate = 800
6136 11:05:49.404041 CKR = 1
6137 11:05:49.407204 DQ_P2S_RATIO = 4
6138 11:05:49.410739 ===================================
6139 11:05:49.413785 CA_P2S_RATIO = 4
6140 11:05:49.416971 DQ_CA_OPEN = 0
6141 11:05:49.417056 DQ_SEMI_OPEN = 1
6142 11:05:49.420531 CA_SEMI_OPEN = 1
6143 11:05:49.423598 CA_FULL_RATE = 0
6144 11:05:49.426868 DQ_CKDIV4_EN = 0
6145 11:05:49.430465 CA_CKDIV4_EN = 1
6146 11:05:49.433433 CA_PREDIV_EN = 0
6147 11:05:49.433559 PH8_DLY = 0
6148 11:05:49.436908 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6149 11:05:49.440204 DQ_AAMCK_DIV = 0
6150 11:05:49.443579 CA_AAMCK_DIV = 0
6151 11:05:49.446849 CA_ADMCK_DIV = 4
6152 11:05:49.450054 DQ_TRACK_CA_EN = 0
6153 11:05:49.453372 CA_PICK = 800
6154 11:05:49.453457 CA_MCKIO = 400
6155 11:05:49.456807 MCKIO_SEMI = 400
6156 11:05:49.460289 PLL_FREQ = 3016
6157 11:05:49.463315 DQ_UI_PI_RATIO = 32
6158 11:05:49.466670 CA_UI_PI_RATIO = 32
6159 11:05:49.469964 ===================================
6160 11:05:49.473293 ===================================
6161 11:05:49.476757 memory_type:LPDDR4
6162 11:05:49.476842 GP_NUM : 10
6163 11:05:49.479828 SRAM_EN : 1
6164 11:05:49.482999 MD32_EN : 0
6165 11:05:49.486294 ===================================
6166 11:05:49.486380 [ANA_INIT] >>>>>>>>>>>>>>
6167 11:05:49.489735 <<<<<< [CONFIGURE PHASE]: ANA_TX
6168 11:05:49.492964 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6169 11:05:49.496350 ===================================
6170 11:05:49.499774 data_rate = 800,PCW = 0X7400
6171 11:05:49.502773 ===================================
6172 11:05:49.506240 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6173 11:05:49.512839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6174 11:05:49.522517 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6175 11:05:49.529623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6176 11:05:49.532439 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6177 11:05:49.535930 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6178 11:05:49.536016 [ANA_INIT] flow start
6179 11:05:49.539089 [ANA_INIT] PLL >>>>>>>>
6180 11:05:49.542704 [ANA_INIT] PLL <<<<<<<<
6181 11:05:49.542788 [ANA_INIT] MIDPI >>>>>>>>
6182 11:05:49.545664 [ANA_INIT] MIDPI <<<<<<<<
6183 11:05:49.549186 [ANA_INIT] DLL >>>>>>>>
6184 11:05:49.549271 [ANA_INIT] flow end
6185 11:05:49.555860 ============ LP4 DIFF to SE enter ============
6186 11:05:49.559022 ============ LP4 DIFF to SE exit ============
6187 11:05:49.559108 [ANA_INIT] <<<<<<<<<<<<<
6188 11:05:49.562618 [Flow] Enable top DCM control >>>>>
6189 11:05:49.565784 [Flow] Enable top DCM control <<<<<
6190 11:05:49.569290 Enable DLL master slave shuffle
6191 11:05:49.575800 ==============================================================
6192 11:05:49.578956 Gating Mode config
6193 11:05:49.582211 ==============================================================
6194 11:05:49.585768 Config description:
6195 11:05:49.595508 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6196 11:05:49.602304 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6197 11:05:49.605395 SELPH_MODE 0: By rank 1: By Phase
6198 11:05:49.611835 ==============================================================
6199 11:05:49.615239 GAT_TRACK_EN = 0
6200 11:05:49.618715 RX_GATING_MODE = 2
6201 11:05:49.621836 RX_GATING_TRACK_MODE = 2
6202 11:05:49.621918 SELPH_MODE = 1
6203 11:05:49.625188 PICG_EARLY_EN = 1
6204 11:05:49.628596 VALID_LAT_VALUE = 1
6205 11:05:49.635429 ==============================================================
6206 11:05:49.638564 Enter into Gating configuration >>>>
6207 11:05:49.641908 Exit from Gating configuration <<<<
6208 11:05:49.645209 Enter into DVFS_PRE_config >>>>>
6209 11:05:49.655052 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6210 11:05:49.658560 Exit from DVFS_PRE_config <<<<<
6211 11:05:49.661827 Enter into PICG configuration >>>>
6212 11:05:49.664819 Exit from PICG configuration <<<<
6213 11:05:49.668077 [RX_INPUT] configuration >>>>>
6214 11:05:49.671504 [RX_INPUT] configuration <<<<<
6215 11:05:49.674628 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6216 11:05:49.681349 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6217 11:05:49.688148 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6218 11:05:49.694752 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6219 11:05:49.701087 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6220 11:05:49.708033 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6221 11:05:49.711233 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6222 11:05:49.714483 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6223 11:05:49.718063 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6224 11:05:49.721092 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6225 11:05:49.727726 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6226 11:05:49.731167 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6227 11:05:49.734619 ===================================
6228 11:05:49.737787 LPDDR4 DRAM CONFIGURATION
6229 11:05:49.741356 ===================================
6230 11:05:49.741442 EX_ROW_EN[0] = 0x0
6231 11:05:49.744564 EX_ROW_EN[1] = 0x0
6232 11:05:49.744649 LP4Y_EN = 0x0
6233 11:05:49.747847 WORK_FSP = 0x0
6234 11:05:49.747933 WL = 0x2
6235 11:05:49.751243 RL = 0x2
6236 11:05:49.751353 BL = 0x2
6237 11:05:49.754475 RPST = 0x0
6238 11:05:49.754557 RD_PRE = 0x0
6239 11:05:49.757689 WR_PRE = 0x1
6240 11:05:49.761067 WR_PST = 0x0
6241 11:05:49.761152 DBI_WR = 0x0
6242 11:05:49.764240 DBI_RD = 0x0
6243 11:05:49.764327 OTF = 0x1
6244 11:05:49.767848 ===================================
6245 11:05:49.770745 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6246 11:05:49.777437 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6247 11:05:49.780957 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6248 11:05:49.784064 ===================================
6249 11:05:49.787540 LPDDR4 DRAM CONFIGURATION
6250 11:05:49.790840 ===================================
6251 11:05:49.790922 EX_ROW_EN[0] = 0x10
6252 11:05:49.794094 EX_ROW_EN[1] = 0x0
6253 11:05:49.794176 LP4Y_EN = 0x0
6254 11:05:49.797546 WORK_FSP = 0x0
6255 11:05:49.797627 WL = 0x2
6256 11:05:49.800769 RL = 0x2
6257 11:05:49.800864 BL = 0x2
6258 11:05:49.804335 RPST = 0x0
6259 11:05:49.804417 RD_PRE = 0x0
6260 11:05:49.807419 WR_PRE = 0x1
6261 11:05:49.810830 WR_PST = 0x0
6262 11:05:49.810911 DBI_WR = 0x0
6263 11:05:49.813894 DBI_RD = 0x0
6264 11:05:49.813976 OTF = 0x1
6265 11:05:49.817351 ===================================
6266 11:05:49.824093 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6267 11:05:49.827566 nWR fixed to 30
6268 11:05:49.830700 [ModeRegInit_LP4] CH0 RK0
6269 11:05:49.830782 [ModeRegInit_LP4] CH0 RK1
6270 11:05:49.834117 [ModeRegInit_LP4] CH1 RK0
6271 11:05:49.837316 [ModeRegInit_LP4] CH1 RK1
6272 11:05:49.837397 match AC timing 19
6273 11:05:49.844153 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6274 11:05:49.847272 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6275 11:05:49.850755 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6276 11:05:49.857400 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6277 11:05:49.860524 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6278 11:05:49.860606 ==
6279 11:05:49.863972 Dram Type= 6, Freq= 0, CH_0, rank 0
6280 11:05:49.867251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6281 11:05:49.867333 ==
6282 11:05:49.874212 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6283 11:05:49.880361 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6284 11:05:49.883651 [CA 0] Center 36 (8~64) winsize 57
6285 11:05:49.887090 [CA 1] Center 36 (8~64) winsize 57
6286 11:05:49.890380 [CA 2] Center 36 (8~64) winsize 57
6287 11:05:49.893856 [CA 3] Center 36 (8~64) winsize 57
6288 11:05:49.893937 [CA 4] Center 36 (8~64) winsize 57
6289 11:05:49.897006 [CA 5] Center 36 (8~64) winsize 57
6290 11:05:49.897088
6291 11:05:49.903657 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6292 11:05:49.903738
6293 11:05:49.906969 [CATrainingPosCal] consider 1 rank data
6294 11:05:49.910534 u2DelayCellTimex100 = 270/100 ps
6295 11:05:49.913520 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 11:05:49.916983 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 11:05:49.920117 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 11:05:49.923554 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 11:05:49.926873 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 11:05:49.930273 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 11:05:49.930355
6302 11:05:49.933515 CA PerBit enable=1, Macro0, CA PI delay=36
6303 11:05:49.933597
6304 11:05:49.936707 [CBTSetCACLKResult] CA Dly = 36
6305 11:05:49.940178 CS Dly: 1 (0~32)
6306 11:05:49.940259 ==
6307 11:05:49.943223 Dram Type= 6, Freq= 0, CH_0, rank 1
6308 11:05:49.946648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 11:05:49.946731 ==
6310 11:05:49.953327 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6311 11:05:49.960154 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6312 11:05:49.963048 [CA 0] Center 36 (8~64) winsize 57
6313 11:05:49.963130 [CA 1] Center 36 (8~64) winsize 57
6314 11:05:49.966323 [CA 2] Center 36 (8~64) winsize 57
6315 11:05:49.969767 [CA 3] Center 36 (8~64) winsize 57
6316 11:05:49.972976 [CA 4] Center 36 (8~64) winsize 57
6317 11:05:49.976454 [CA 5] Center 36 (8~64) winsize 57
6318 11:05:49.976535
6319 11:05:49.979596 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6320 11:05:49.979678
6321 11:05:49.986491 [CATrainingPosCal] consider 2 rank data
6322 11:05:49.986573 u2DelayCellTimex100 = 270/100 ps
6323 11:05:49.989721 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 11:05:49.996369 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 11:05:49.999859 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 11:05:50.003088 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 11:05:50.006403 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 11:05:50.009788 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 11:05:50.009875
6330 11:05:50.012864 CA PerBit enable=1, Macro0, CA PI delay=36
6331 11:05:50.012963
6332 11:05:50.016038 [CBTSetCACLKResult] CA Dly = 36
6333 11:05:50.019613 CS Dly: 1 (0~32)
6334 11:05:50.019702
6335 11:05:50.022900 ----->DramcWriteLeveling(PI) begin...
6336 11:05:50.022983 ==
6337 11:05:50.026323 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 11:05:50.029411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 11:05:50.029531 ==
6340 11:05:50.032796 Write leveling (Byte 0): 40 => 8
6341 11:05:50.036205 Write leveling (Byte 1): 40 => 8
6342 11:05:50.039352 DramcWriteLeveling(PI) end<-----
6343 11:05:50.039439
6344 11:05:50.039505 ==
6345 11:05:50.042882 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 11:05:50.045941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 11:05:50.046023 ==
6348 11:05:50.049440 [Gating] SW mode calibration
6349 11:05:50.055985 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6350 11:05:50.062749 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6351 11:05:50.065884 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6352 11:05:50.069397 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6353 11:05:50.075733 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6354 11:05:50.079375 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6355 11:05:50.082319 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6356 11:05:50.089028 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6357 11:05:50.092358 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6358 11:05:50.095719 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6359 11:05:50.102444 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6360 11:05:50.102527 Total UI for P1: 0, mck2ui 16
6361 11:05:50.105773 best dqsien dly found for B0: ( 0, 14, 24)
6362 11:05:50.109362 Total UI for P1: 0, mck2ui 16
6363 11:05:50.112240 best dqsien dly found for B1: ( 0, 14, 24)
6364 11:05:50.118851 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6365 11:05:50.122207 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6366 11:05:50.122288
6367 11:05:50.125549 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6368 11:05:50.128966 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6369 11:05:50.132184 [Gating] SW calibration Done
6370 11:05:50.132266 ==
6371 11:05:50.135498 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 11:05:50.138792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 11:05:50.138873 ==
6374 11:05:50.142435 RX Vref Scan: 0
6375 11:05:50.142516
6376 11:05:50.142580 RX Vref 0 -> 0, step: 1
6377 11:05:50.142640
6378 11:05:50.145709 RX Delay -410 -> 252, step: 16
6379 11:05:50.152237 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6380 11:05:50.155385 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6381 11:05:50.158638 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6382 11:05:50.161972 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6383 11:05:50.168685 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6384 11:05:50.171838 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6385 11:05:50.175374 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6386 11:05:50.178617 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6387 11:05:50.185217 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6388 11:05:50.188782 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6389 11:05:50.191814 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6390 11:05:50.195360 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6391 11:05:50.201942 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6392 11:05:50.205328 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6393 11:05:50.208483 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6394 11:05:50.211688 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6395 11:05:50.215035 ==
6396 11:05:50.215147 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 11:05:50.221518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 11:05:50.221602 ==
6399 11:05:50.221667 DQS Delay:
6400 11:05:50.224966 DQS0 = 51, DQS1 = 59
6401 11:05:50.225047 DQM Delay:
6402 11:05:50.228132 DQM0 = 10, DQM1 = 9
6403 11:05:50.228212 DQ Delay:
6404 11:05:50.231690 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6405 11:05:50.235287 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6406 11:05:50.235368 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6407 11:05:50.238357 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6408 11:05:50.241814
6409 11:05:50.241895
6410 11:05:50.241959 ==
6411 11:05:50.244798 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 11:05:50.248245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 11:05:50.248327 ==
6414 11:05:50.248391
6415 11:05:50.248450
6416 11:05:50.251415 TX Vref Scan disable
6417 11:05:50.251497 == TX Byte 0 ==
6418 11:05:50.254682 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 11:05:50.261445 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 11:05:50.261561 == TX Byte 1 ==
6421 11:05:50.264666 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6422 11:05:50.271427 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6423 11:05:50.271508 ==
6424 11:05:50.274919 Dram Type= 6, Freq= 0, CH_0, rank 0
6425 11:05:50.278083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 11:05:50.278164 ==
6427 11:05:50.278229
6428 11:05:50.278288
6429 11:05:50.281362 TX Vref Scan disable
6430 11:05:50.281445 == TX Byte 0 ==
6431 11:05:50.288005 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6432 11:05:50.291329 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6433 11:05:50.291412 == TX Byte 1 ==
6434 11:05:50.294783 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6435 11:05:50.301358 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6436 11:05:50.301440
6437 11:05:50.301535 [DATLAT]
6438 11:05:50.304681 Freq=400, CH0 RK0
6439 11:05:50.304764
6440 11:05:50.304828 DATLAT Default: 0xf
6441 11:05:50.307718 0, 0xFFFF, sum = 0
6442 11:05:50.307801 1, 0xFFFF, sum = 0
6443 11:05:50.311119 2, 0xFFFF, sum = 0
6444 11:05:50.311202 3, 0xFFFF, sum = 0
6445 11:05:50.314324 4, 0xFFFF, sum = 0
6446 11:05:50.314406 5, 0xFFFF, sum = 0
6447 11:05:50.317630 6, 0xFFFF, sum = 0
6448 11:05:50.317716 7, 0xFFFF, sum = 0
6449 11:05:50.321183 8, 0xFFFF, sum = 0
6450 11:05:50.321266 9, 0xFFFF, sum = 0
6451 11:05:50.324516 10, 0xFFFF, sum = 0
6452 11:05:50.324599 11, 0xFFFF, sum = 0
6453 11:05:50.327611 12, 0xFFFF, sum = 0
6454 11:05:50.327695 13, 0x0, sum = 1
6455 11:05:50.331081 14, 0x0, sum = 2
6456 11:05:50.331164 15, 0x0, sum = 3
6457 11:05:50.334547 16, 0x0, sum = 4
6458 11:05:50.334630 best_step = 14
6459 11:05:50.334695
6460 11:05:50.334755 ==
6461 11:05:50.337683 Dram Type= 6, Freq= 0, CH_0, rank 0
6462 11:05:50.344118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 11:05:50.344200 ==
6464 11:05:50.344265 RX Vref Scan: 1
6465 11:05:50.344325
6466 11:05:50.347654 RX Vref 0 -> 0, step: 1
6467 11:05:50.347735
6468 11:05:50.350806 RX Delay -359 -> 252, step: 8
6469 11:05:50.350888
6470 11:05:50.354277 Set Vref, RX VrefLevel [Byte0]: 61
6471 11:05:50.357384 [Byte1]: 54
6472 11:05:50.360947
6473 11:05:50.361031 Final RX Vref Byte 0 = 61 to rank0
6474 11:05:50.363897 Final RX Vref Byte 1 = 54 to rank0
6475 11:05:50.367396 Final RX Vref Byte 0 = 61 to rank1
6476 11:05:50.370540 Final RX Vref Byte 1 = 54 to rank1==
6477 11:05:50.373935 Dram Type= 6, Freq= 0, CH_0, rank 0
6478 11:05:50.380238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 11:05:50.380324 ==
6480 11:05:50.380412 DQS Delay:
6481 11:05:50.383665 DQS0 = 60, DQS1 = 68
6482 11:05:50.383741 DQM Delay:
6483 11:05:50.387344 DQM0 = 14, DQM1 = 14
6484 11:05:50.387429 DQ Delay:
6485 11:05:50.390229 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6486 11:05:50.393796 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6487 11:05:50.396986 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6488 11:05:50.400301 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6489 11:05:50.400387
6490 11:05:50.400474
6491 11:05:50.406628 [DQSOSCAuto] RK0, (LSB)MR18= 0x8584, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6492 11:05:50.409892 CH0 RK0: MR19=C0C, MR18=8584
6493 11:05:50.416907 CH0_RK0: MR19=0xC0C, MR18=0x8584, DQSOSC=393, MR23=63, INC=382, DEC=254
6494 11:05:50.416994 ==
6495 11:05:50.419830 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 11:05:50.423257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 11:05:50.423343 ==
6498 11:05:50.426589 [Gating] SW mode calibration
6499 11:05:50.433283 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6500 11:05:50.439842 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6501 11:05:50.442968 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6502 11:05:50.446556 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6503 11:05:50.453224 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6504 11:05:50.456307 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6505 11:05:50.459704 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 11:05:50.466364 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 11:05:50.469669 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6508 11:05:50.472710 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6509 11:05:50.479604 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6510 11:05:50.482894 Total UI for P1: 0, mck2ui 16
6511 11:05:50.486256 best dqsien dly found for B0: ( 0, 14, 24)
6512 11:05:50.486359 Total UI for P1: 0, mck2ui 16
6513 11:05:50.492866 best dqsien dly found for B1: ( 0, 14, 24)
6514 11:05:50.495987 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6515 11:05:50.499443 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6516 11:05:50.499564
6517 11:05:50.502405 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6518 11:05:50.506032 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6519 11:05:50.509167 [Gating] SW calibration Done
6520 11:05:50.509318 ==
6521 11:05:50.512605 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 11:05:50.515774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 11:05:50.515977 ==
6524 11:05:50.519200 RX Vref Scan: 0
6525 11:05:50.519406
6526 11:05:50.522452 RX Vref 0 -> 0, step: 1
6527 11:05:50.522690
6528 11:05:50.522878 RX Delay -410 -> 252, step: 16
6529 11:05:50.529390 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6530 11:05:50.532829 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6531 11:05:50.536078 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6532 11:05:50.542625 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6533 11:05:50.545862 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6534 11:05:50.549436 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6535 11:05:50.552550 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6536 11:05:50.559379 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6537 11:05:50.562914 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6538 11:05:50.566057 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6539 11:05:50.569196 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6540 11:05:50.575799 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6541 11:05:50.578995 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6542 11:05:50.582366 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6543 11:05:50.585678 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6544 11:05:50.592363 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6545 11:05:50.592806 ==
6546 11:05:50.595733 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 11:05:50.598749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 11:05:50.599205 ==
6549 11:05:50.599657 DQS Delay:
6550 11:05:50.601962 DQS0 = 59, DQS1 = 59
6551 11:05:50.602402 DQM Delay:
6552 11:05:50.605444 DQM0 = 16, DQM1 = 10
6553 11:05:50.605925 DQ Delay:
6554 11:05:50.608599 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6555 11:05:50.611983 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6556 11:05:50.615269 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6557 11:05:50.618444 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6558 11:05:50.618870
6559 11:05:50.619198
6560 11:05:50.619504 ==
6561 11:05:50.621928 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 11:05:50.624995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 11:05:50.628668 ==
6564 11:05:50.629112
6565 11:05:50.629660
6566 11:05:50.630088 TX Vref Scan disable
6567 11:05:50.631799 == TX Byte 0 ==
6568 11:05:50.634507 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6569 11:05:50.638046 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6570 11:05:50.641399 == TX Byte 1 ==
6571 11:05:50.644696 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6572 11:05:50.648012 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6573 11:05:50.648098 ==
6574 11:05:50.651397 Dram Type= 6, Freq= 0, CH_0, rank 1
6575 11:05:50.657757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6576 11:05:50.657890 ==
6577 11:05:50.657976
6578 11:05:50.658058
6579 11:05:50.658138 TX Vref Scan disable
6580 11:05:50.661264 == TX Byte 0 ==
6581 11:05:50.664435 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6582 11:05:50.667529 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6583 11:05:50.671042 == TX Byte 1 ==
6584 11:05:50.674299 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6585 11:05:50.677393 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6586 11:05:50.677484
6587 11:05:50.680884 [DATLAT]
6588 11:05:50.680969 Freq=400, CH0 RK1
6589 11:05:50.681056
6590 11:05:50.684004 DATLAT Default: 0xe
6591 11:05:50.684090 0, 0xFFFF, sum = 0
6592 11:05:50.687522 1, 0xFFFF, sum = 0
6593 11:05:50.687609 2, 0xFFFF, sum = 0
6594 11:05:50.690539 3, 0xFFFF, sum = 0
6595 11:05:50.690626 4, 0xFFFF, sum = 0
6596 11:05:50.693905 5, 0xFFFF, sum = 0
6597 11:05:50.693991 6, 0xFFFF, sum = 0
6598 11:05:50.697266 7, 0xFFFF, sum = 0
6599 11:05:50.697353 8, 0xFFFF, sum = 0
6600 11:05:50.700369 9, 0xFFFF, sum = 0
6601 11:05:50.704019 10, 0xFFFF, sum = 0
6602 11:05:50.704106 11, 0xFFFF, sum = 0
6603 11:05:50.707547 12, 0xFFFF, sum = 0
6604 11:05:50.707634 13, 0x0, sum = 1
6605 11:05:50.710552 14, 0x0, sum = 2
6606 11:05:50.710638 15, 0x0, sum = 3
6607 11:05:50.710726 16, 0x0, sum = 4
6608 11:05:50.713708 best_step = 14
6609 11:05:50.713793
6610 11:05:50.713880 ==
6611 11:05:50.717157 Dram Type= 6, Freq= 0, CH_0, rank 1
6612 11:05:50.720428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 11:05:50.720514 ==
6614 11:05:50.723947 RX Vref Scan: 0
6615 11:05:50.724032
6616 11:05:50.724118 RX Vref 0 -> 0, step: 1
6617 11:05:50.727337
6618 11:05:50.727421 RX Delay -359 -> 252, step: 8
6619 11:05:50.735737 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6620 11:05:50.738904 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6621 11:05:50.742037 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6622 11:05:50.748960 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6623 11:05:50.752074 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6624 11:05:50.755635 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6625 11:05:50.758683 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6626 11:05:50.765105 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6627 11:05:50.768484 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6628 11:05:50.772024 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6629 11:05:50.775354 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6630 11:05:50.781746 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6631 11:05:50.785085 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6632 11:05:50.788301 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6633 11:05:50.791886 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6634 11:05:50.798624 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6635 11:05:50.798711 ==
6636 11:05:50.801586 Dram Type= 6, Freq= 0, CH_0, rank 1
6637 11:05:50.804815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 11:05:50.804902 ==
6639 11:05:50.804989 DQS Delay:
6640 11:05:50.808434 DQS0 = 60, DQS1 = 72
6641 11:05:50.808519 DQM Delay:
6642 11:05:50.811913 DQM0 = 11, DQM1 = 18
6643 11:05:50.811999 DQ Delay:
6644 11:05:50.815232 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6645 11:05:50.818545 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6646 11:05:50.821771 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =12
6647 11:05:50.825103 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6648 11:05:50.825188
6649 11:05:50.825291
6650 11:05:50.831554 [DQSOSCAuto] RK1, (LSB)MR18= 0xcb80, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6651 11:05:50.834987 CH0 RK1: MR19=C0C, MR18=CB80
6652 11:05:50.841752 CH0_RK1: MR19=0xC0C, MR18=0xCB80, DQSOSC=384, MR23=63, INC=400, DEC=267
6653 11:05:50.844752 [RxdqsGatingPostProcess] freq 400
6654 11:05:50.851379 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6655 11:05:50.854771 best DQS0 dly(2T, 0.5T) = (0, 10)
6656 11:05:50.858246 best DQS1 dly(2T, 0.5T) = (0, 10)
6657 11:05:50.861327 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6658 11:05:50.861413 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6659 11:05:50.864712 best DQS0 dly(2T, 0.5T) = (0, 10)
6660 11:05:50.868103 best DQS1 dly(2T, 0.5T) = (0, 10)
6661 11:05:50.871343 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6662 11:05:50.874429 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6663 11:05:50.877745 Pre-setting of DQS Precalculation
6664 11:05:50.884787 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6665 11:05:50.884873 ==
6666 11:05:50.887800 Dram Type= 6, Freq= 0, CH_1, rank 0
6667 11:05:50.891238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 11:05:50.891331 ==
6669 11:05:50.897777 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6670 11:05:50.904358 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6671 11:05:50.904461 [CA 0] Center 36 (8~64) winsize 57
6672 11:05:50.907763 [CA 1] Center 36 (8~64) winsize 57
6673 11:05:50.911291 [CA 2] Center 36 (8~64) winsize 57
6674 11:05:50.914623 [CA 3] Center 36 (8~64) winsize 57
6675 11:05:50.917809 [CA 4] Center 36 (8~64) winsize 57
6676 11:05:50.921008 [CA 5] Center 36 (8~64) winsize 57
6677 11:05:50.921085
6678 11:05:50.924367 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6679 11:05:50.924474
6680 11:05:50.927483 [CATrainingPosCal] consider 1 rank data
6681 11:05:50.930932 u2DelayCellTimex100 = 270/100 ps
6682 11:05:50.934335 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 11:05:50.940932 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 11:05:50.944130 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 11:05:50.947530 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 11:05:50.950947 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 11:05:50.954365 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 11:05:50.954445
6689 11:05:50.957747 CA PerBit enable=1, Macro0, CA PI delay=36
6690 11:05:50.957829
6691 11:05:50.960832 [CBTSetCACLKResult] CA Dly = 36
6692 11:05:50.960912 CS Dly: 1 (0~32)
6693 11:05:50.960977 ==
6694 11:05:50.964229 Dram Type= 6, Freq= 0, CH_1, rank 1
6695 11:05:50.970834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 11:05:50.970915 ==
6697 11:05:50.974348 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6698 11:05:50.981089 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6699 11:05:50.984205 [CA 0] Center 36 (8~64) winsize 57
6700 11:05:50.987639 [CA 1] Center 36 (8~64) winsize 57
6701 11:05:50.990738 [CA 2] Center 36 (8~64) winsize 57
6702 11:05:50.994172 [CA 3] Center 36 (8~64) winsize 57
6703 11:05:50.997646 [CA 4] Center 36 (8~64) winsize 57
6704 11:05:51.000709 [CA 5] Center 36 (8~64) winsize 57
6705 11:05:51.000799
6706 11:05:51.003961 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6707 11:05:51.004042
6708 11:05:51.007322 [CATrainingPosCal] consider 2 rank data
6709 11:05:51.010852 u2DelayCellTimex100 = 270/100 ps
6710 11:05:51.013866 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 11:05:51.017607 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 11:05:51.020460 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 11:05:51.023822 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 11:05:51.027431 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 11:05:51.034101 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 11:05:51.034182
6717 11:05:51.037126 CA PerBit enable=1, Macro0, CA PI delay=36
6718 11:05:51.037208
6719 11:05:51.040661 [CBTSetCACLKResult] CA Dly = 36
6720 11:05:51.040742 CS Dly: 1 (0~32)
6721 11:05:51.040807
6722 11:05:51.043892 ----->DramcWriteLeveling(PI) begin...
6723 11:05:51.043975 ==
6724 11:05:51.047024 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 11:05:51.053508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 11:05:51.053630 ==
6727 11:05:51.057031 Write leveling (Byte 0): 40 => 8
6728 11:05:51.057112 Write leveling (Byte 1): 40 => 8
6729 11:05:51.060116 DramcWriteLeveling(PI) end<-----
6730 11:05:51.060205
6731 11:05:51.060269 ==
6732 11:05:51.063495 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 11:05:51.069982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 11:05:51.070063 ==
6735 11:05:51.073421 [Gating] SW mode calibration
6736 11:05:51.080061 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6737 11:05:51.083435 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6738 11:05:51.090139 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6739 11:05:51.093109 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6740 11:05:51.096753 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6741 11:05:51.103332 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6742 11:05:51.106420 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6743 11:05:51.109837 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6744 11:05:51.116243 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6745 11:05:51.119720 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6746 11:05:51.122882 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6747 11:05:51.126222 Total UI for P1: 0, mck2ui 16
6748 11:05:51.129634 best dqsien dly found for B0: ( 0, 14, 24)
6749 11:05:51.132767 Total UI for P1: 0, mck2ui 16
6750 11:05:51.136078 best dqsien dly found for B1: ( 0, 14, 24)
6751 11:05:51.139350 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6752 11:05:51.142786 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6753 11:05:51.142872
6754 11:05:51.149258 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6755 11:05:51.152592 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6756 11:05:51.156073 [Gating] SW calibration Done
6757 11:05:51.156158 ==
6758 11:05:51.159229 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 11:05:51.162636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 11:05:51.162722 ==
6761 11:05:51.162809 RX Vref Scan: 0
6762 11:05:51.162892
6763 11:05:51.166054 RX Vref 0 -> 0, step: 1
6764 11:05:51.166139
6765 11:05:51.169425 RX Delay -410 -> 252, step: 16
6766 11:05:51.172693 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6767 11:05:51.179338 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6768 11:05:51.182363 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6769 11:05:51.186172 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6770 11:05:51.189111 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6771 11:05:51.195588 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6772 11:05:51.199196 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6773 11:05:51.202467 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6774 11:05:51.205679 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6775 11:05:51.212347 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6776 11:05:51.215381 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6777 11:05:51.218681 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6778 11:05:51.222025 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6779 11:05:51.228734 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6780 11:05:51.231949 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6781 11:05:51.235360 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6782 11:05:51.235459 ==
6783 11:05:51.238548 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 11:05:51.245127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 11:05:51.245281 ==
6786 11:05:51.245346 DQS Delay:
6787 11:05:51.248304 DQS0 = 51, DQS1 = 67
6788 11:05:51.248387 DQM Delay:
6789 11:05:51.248490 DQM0 = 13, DQM1 = 17
6790 11:05:51.251701 DQ Delay:
6791 11:05:51.255064 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6792 11:05:51.258412 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6793 11:05:51.258537 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6794 11:05:51.264833 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6795 11:05:51.264916
6796 11:05:51.264981
6797 11:05:51.265041 ==
6798 11:05:51.268037 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 11:05:51.271691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 11:05:51.271774 ==
6801 11:05:51.271840
6802 11:05:51.271900
6803 11:05:51.274592 TX Vref Scan disable
6804 11:05:51.274675 == TX Byte 0 ==
6805 11:05:51.281254 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 11:05:51.284538 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 11:05:51.284622 == TX Byte 1 ==
6808 11:05:51.291085 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6809 11:05:51.294457 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6810 11:05:51.294540 ==
6811 11:05:51.297632 Dram Type= 6, Freq= 0, CH_1, rank 0
6812 11:05:51.301444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 11:05:51.301540 ==
6814 11:05:51.301606
6815 11:05:51.301667
6816 11:05:51.304362 TX Vref Scan disable
6817 11:05:51.304445 == TX Byte 0 ==
6818 11:05:51.310747 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6819 11:05:51.314261 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6820 11:05:51.314344 == TX Byte 1 ==
6821 11:05:51.320897 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6822 11:05:51.324020 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6823 11:05:51.324102
6824 11:05:51.324168 [DATLAT]
6825 11:05:51.327476 Freq=400, CH1 RK0
6826 11:05:51.327559
6827 11:05:51.327624 DATLAT Default: 0xf
6828 11:05:51.331153 0, 0xFFFF, sum = 0
6829 11:05:51.331238 1, 0xFFFF, sum = 0
6830 11:05:51.334096 2, 0xFFFF, sum = 0
6831 11:05:51.334180 3, 0xFFFF, sum = 0
6832 11:05:51.337380 4, 0xFFFF, sum = 0
6833 11:05:51.337489 5, 0xFFFF, sum = 0
6834 11:05:51.340627 6, 0xFFFF, sum = 0
6835 11:05:51.340712 7, 0xFFFF, sum = 0
6836 11:05:51.344109 8, 0xFFFF, sum = 0
6837 11:05:51.344194 9, 0xFFFF, sum = 0
6838 11:05:51.347447 10, 0xFFFF, sum = 0
6839 11:05:51.350765 11, 0xFFFF, sum = 0
6840 11:05:51.350850 12, 0xFFFF, sum = 0
6841 11:05:51.353867 13, 0x0, sum = 1
6842 11:05:51.353951 14, 0x0, sum = 2
6843 11:05:51.357397 15, 0x0, sum = 3
6844 11:05:51.357486 16, 0x0, sum = 4
6845 11:05:51.357553 best_step = 14
6846 11:05:51.357614
6847 11:05:51.360521 ==
6848 11:05:51.364174 Dram Type= 6, Freq= 0, CH_1, rank 0
6849 11:05:51.367338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 11:05:51.367422 ==
6851 11:05:51.367488 RX Vref Scan: 1
6852 11:05:51.367549
6853 11:05:51.370585 RX Vref 0 -> 0, step: 1
6854 11:05:51.370668
6855 11:05:51.373791 RX Delay -375 -> 252, step: 8
6856 11:05:51.373873
6857 11:05:51.377301 Set Vref, RX VrefLevel [Byte0]: 59
6858 11:05:51.380371 [Byte1]: 51
6859 11:05:51.384262
6860 11:05:51.384344 Final RX Vref Byte 0 = 59 to rank0
6861 11:05:51.387714 Final RX Vref Byte 1 = 51 to rank0
6862 11:05:51.390740 Final RX Vref Byte 0 = 59 to rank1
6863 11:05:51.394098 Final RX Vref Byte 1 = 51 to rank1==
6864 11:05:51.397393 Dram Type= 6, Freq= 0, CH_1, rank 0
6865 11:05:51.404243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 11:05:51.404327 ==
6867 11:05:51.404393 DQS Delay:
6868 11:05:51.407393 DQS0 = 56, DQS1 = 64
6869 11:05:51.407476 DQM Delay:
6870 11:05:51.407542 DQM0 = 13, DQM1 = 10
6871 11:05:51.410852 DQ Delay:
6872 11:05:51.414037 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6873 11:05:51.414120 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6874 11:05:51.417324 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6875 11:05:51.420749 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6876 11:05:51.420832
6877 11:05:51.424268
6878 11:05:51.431076 [DQSOSCAuto] RK0, (LSB)MR18= 0x5367, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6879 11:05:51.434108 CH1 RK0: MR19=C0C, MR18=5367
6880 11:05:51.440787 CH1_RK0: MR19=0xC0C, MR18=0x5367, DQSOSC=396, MR23=63, INC=376, DEC=251
6881 11:05:51.440874 ==
6882 11:05:51.444259 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 11:05:51.447421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 11:05:51.447505 ==
6885 11:05:51.450514 [Gating] SW mode calibration
6886 11:05:51.457410 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6887 11:05:51.464059 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6888 11:05:51.467316 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6889 11:05:51.470752 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6890 11:05:51.477171 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6891 11:05:51.480473 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6892 11:05:51.484081 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6893 11:05:51.487392 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6894 11:05:51.493895 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6895 11:05:51.497033 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6896 11:05:51.500327 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6897 11:05:51.503634 Total UI for P1: 0, mck2ui 16
6898 11:05:51.507177 best dqsien dly found for B0: ( 0, 14, 24)
6899 11:05:51.510528 Total UI for P1: 0, mck2ui 16
6900 11:05:51.513651 best dqsien dly found for B1: ( 0, 14, 24)
6901 11:05:51.516933 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6902 11:05:51.523638 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6903 11:05:51.523750
6904 11:05:51.526692 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6905 11:05:51.530172 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6906 11:05:51.533565 [Gating] SW calibration Done
6907 11:05:51.533680 ==
6908 11:05:51.536743 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 11:05:51.540012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 11:05:51.540124 ==
6911 11:05:51.543566 RX Vref Scan: 0
6912 11:05:51.543668
6913 11:05:51.543755 RX Vref 0 -> 0, step: 1
6914 11:05:51.543861
6915 11:05:51.546676 RX Delay -410 -> 252, step: 16
6916 11:05:51.550283 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6917 11:05:51.556776 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6918 11:05:51.560015 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6919 11:05:51.563241 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6920 11:05:51.566787 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6921 11:05:51.573392 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6922 11:05:51.576656 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6923 11:05:51.580157 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6924 11:05:51.583451 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6925 11:05:51.589882 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6926 11:05:51.593243 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6927 11:05:51.596386 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6928 11:05:51.599638 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6929 11:05:51.606575 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6930 11:05:51.609731 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6931 11:05:51.613039 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6932 11:05:51.613153 ==
6933 11:05:51.616310 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 11:05:51.622988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 11:05:51.623098 ==
6936 11:05:51.623196 DQS Delay:
6937 11:05:51.626425 DQS0 = 59, DQS1 = 59
6938 11:05:51.626538 DQM Delay:
6939 11:05:51.626635 DQM0 = 19, DQM1 = 14
6940 11:05:51.629679 DQ Delay:
6941 11:05:51.633144 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6942 11:05:51.636260 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6943 11:05:51.639799 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6944 11:05:51.642822 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6945 11:05:51.642931
6946 11:05:51.643034
6947 11:05:51.643137 ==
6948 11:05:51.646205 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 11:05:51.649319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 11:05:51.649427 ==
6951 11:05:51.649565
6952 11:05:51.649651
6953 11:05:51.652686 TX Vref Scan disable
6954 11:05:51.652793 == TX Byte 0 ==
6955 11:05:51.659294 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6956 11:05:51.662610 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6957 11:05:51.662694 == TX Byte 1 ==
6958 11:05:51.669603 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6959 11:05:51.672610 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6960 11:05:51.672718 ==
6961 11:05:51.676030 Dram Type= 6, Freq= 0, CH_1, rank 1
6962 11:05:51.679055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6963 11:05:51.679164 ==
6964 11:05:51.679265
6965 11:05:51.679367
6966 11:05:51.682690 TX Vref Scan disable
6967 11:05:51.682792 == TX Byte 0 ==
6968 11:05:51.689245 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6969 11:05:51.692429 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6970 11:05:51.692516 == TX Byte 1 ==
6971 11:05:51.699135 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6972 11:05:51.702615 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6973 11:05:51.702721
6974 11:05:51.702814 [DATLAT]
6975 11:05:51.705586 Freq=400, CH1 RK1
6976 11:05:51.705684
6977 11:05:51.705815 DATLAT Default: 0xe
6978 11:05:51.708977 0, 0xFFFF, sum = 0
6979 11:05:51.709088 1, 0xFFFF, sum = 0
6980 11:05:51.712473 2, 0xFFFF, sum = 0
6981 11:05:51.712673 3, 0xFFFF, sum = 0
6982 11:05:51.715668 4, 0xFFFF, sum = 0
6983 11:05:51.715786 5, 0xFFFF, sum = 0
6984 11:05:51.719044 6, 0xFFFF, sum = 0
6985 11:05:51.719168 7, 0xFFFF, sum = 0
6986 11:05:51.722457 8, 0xFFFF, sum = 0
6987 11:05:51.722551 9, 0xFFFF, sum = 0
6988 11:05:51.725823 10, 0xFFFF, sum = 0
6989 11:05:51.729359 11, 0xFFFF, sum = 0
6990 11:05:51.729470 12, 0xFFFF, sum = 0
6991 11:05:51.732238 13, 0x0, sum = 1
6992 11:05:51.732322 14, 0x0, sum = 2
6993 11:05:51.732425 15, 0x0, sum = 3
6994 11:05:51.735563 16, 0x0, sum = 4
6995 11:05:51.735648 best_step = 14
6996 11:05:51.735732
6997 11:05:51.738759 ==
6998 11:05:51.742371 Dram Type= 6, Freq= 0, CH_1, rank 1
6999 11:05:51.745322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7000 11:05:51.745430 ==
7001 11:05:51.745559 RX Vref Scan: 0
7002 11:05:51.745640
7003 11:05:51.748809 RX Vref 0 -> 0, step: 1
7004 11:05:51.748923
7005 11:05:51.751993 RX Delay -359 -> 252, step: 8
7006 11:05:51.758825 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7007 11:05:51.762363 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7008 11:05:51.765531 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7009 11:05:51.769039 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7010 11:05:51.775829 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7011 11:05:51.778759 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7012 11:05:51.782088 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7013 11:05:51.785352 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
7014 11:05:51.792047 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7015 11:05:51.795396 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7016 11:05:51.798549 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7017 11:05:51.805463 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7018 11:05:51.808705 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7019 11:05:51.811701 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7020 11:05:51.815570 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7021 11:05:51.822018 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7022 11:05:51.822103 ==
7023 11:05:51.825446 Dram Type= 6, Freq= 0, CH_1, rank 1
7024 11:05:51.828548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7025 11:05:51.828663 ==
7026 11:05:51.828761 DQS Delay:
7027 11:05:51.831899 DQS0 = 60, DQS1 = 64
7028 11:05:51.831978 DQM Delay:
7029 11:05:51.835104 DQM0 = 13, DQM1 = 10
7030 11:05:51.835179 DQ Delay:
7031 11:05:51.838488 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7032 11:05:51.841661 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
7033 11:05:51.845080 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7034 11:05:51.848288 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7035 11:05:51.848363
7036 11:05:51.848426
7037 11:05:51.854846 [DQSOSCAuto] RK1, (LSB)MR18= 0x7dac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7038 11:05:51.858240 CH1 RK1: MR19=C0C, MR18=7DAC
7039 11:05:51.864544 CH1_RK1: MR19=0xC0C, MR18=0x7DAC, DQSOSC=388, MR23=63, INC=392, DEC=261
7040 11:05:51.867835 [RxdqsGatingPostProcess] freq 400
7041 11:05:51.874677 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7042 11:05:51.877871 best DQS0 dly(2T, 0.5T) = (0, 10)
7043 11:05:51.881413 best DQS1 dly(2T, 0.5T) = (0, 10)
7044 11:05:51.884642 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7045 11:05:51.888133 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7046 11:05:51.888229 best DQS0 dly(2T, 0.5T) = (0, 10)
7047 11:05:51.891491 best DQS1 dly(2T, 0.5T) = (0, 10)
7048 11:05:51.894681 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7049 11:05:51.897788 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7050 11:05:51.901268 Pre-setting of DQS Precalculation
7051 11:05:51.908033 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7052 11:05:51.914442 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7053 11:05:51.921314 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7054 11:05:51.921403
7055 11:05:51.921468
7056 11:05:51.924571 [Calibration Summary] 800 Mbps
7057 11:05:51.924685 CH 0, Rank 0
7058 11:05:51.928030 SW Impedance : PASS
7059 11:05:51.931239 DUTY Scan : NO K
7060 11:05:51.931321 ZQ Calibration : PASS
7061 11:05:51.934238 Jitter Meter : NO K
7062 11:05:51.937736 CBT Training : PASS
7063 11:05:51.937813 Write leveling : PASS
7064 11:05:51.940902 RX DQS gating : PASS
7065 11:05:51.944419 RX DQ/DQS(RDDQC) : PASS
7066 11:05:51.944496 TX DQ/DQS : PASS
7067 11:05:51.947513 RX DATLAT : PASS
7068 11:05:51.947598 RX DQ/DQS(Engine): PASS
7069 11:05:51.950935 TX OE : NO K
7070 11:05:51.951011 All Pass.
7071 11:05:51.951075
7072 11:05:51.954103 CH 0, Rank 1
7073 11:05:51.957356 SW Impedance : PASS
7074 11:05:51.957435 DUTY Scan : NO K
7075 11:05:51.960663 ZQ Calibration : PASS
7076 11:05:51.964053 Jitter Meter : NO K
7077 11:05:51.964137 CBT Training : PASS
7078 11:05:51.967327 Write leveling : NO K
7079 11:05:51.967401 RX DQS gating : PASS
7080 11:05:51.970552 RX DQ/DQS(RDDQC) : PASS
7081 11:05:51.974060 TX DQ/DQS : PASS
7082 11:05:51.974136 RX DATLAT : PASS
7083 11:05:51.977385 RX DQ/DQS(Engine): PASS
7084 11:05:51.980429 TX OE : NO K
7085 11:05:51.980512 All Pass.
7086 11:05:51.980578
7087 11:05:51.980637 CH 1, Rank 0
7088 11:05:51.983818 SW Impedance : PASS
7089 11:05:51.987423 DUTY Scan : NO K
7090 11:05:51.987502 ZQ Calibration : PASS
7091 11:05:51.990463 Jitter Meter : NO K
7092 11:05:51.993841 CBT Training : PASS
7093 11:05:51.993919 Write leveling : PASS
7094 11:05:51.997091 RX DQS gating : PASS
7095 11:05:52.000734 RX DQ/DQS(RDDQC) : PASS
7096 11:05:52.000805 TX DQ/DQS : PASS
7097 11:05:52.003929 RX DATLAT : PASS
7098 11:05:52.007073 RX DQ/DQS(Engine): PASS
7099 11:05:52.007147 TX OE : NO K
7100 11:05:52.007212 All Pass.
7101 11:05:52.010670
7102 11:05:52.010745 CH 1, Rank 1
7103 11:05:52.013698 SW Impedance : PASS
7104 11:05:52.013772 DUTY Scan : NO K
7105 11:05:52.016958 ZQ Calibration : PASS
7106 11:05:52.020411 Jitter Meter : NO K
7107 11:05:52.020525 CBT Training : PASS
7108 11:05:52.023617 Write leveling : NO K
7109 11:05:52.023725 RX DQS gating : PASS
7110 11:05:52.027218 RX DQ/DQS(RDDQC) : PASS
7111 11:05:52.030322 TX DQ/DQS : PASS
7112 11:05:52.030434 RX DATLAT : PASS
7113 11:05:52.033414 RX DQ/DQS(Engine): PASS
7114 11:05:52.036866 TX OE : NO K
7115 11:05:52.036975 All Pass.
7116 11:05:52.037076
7117 11:05:52.039910 DramC Write-DBI off
7118 11:05:52.040010 PER_BANK_REFRESH: Hybrid Mode
7119 11:05:52.043471 TX_TRACKING: ON
7120 11:05:52.053207 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7121 11:05:52.056629 [FAST_K] Save calibration result to emmc
7122 11:05:52.059857 dramc_set_vcore_voltage set vcore to 725000
7123 11:05:52.063037 Read voltage for 1600, 0
7124 11:05:52.063145 Vio18 = 0
7125 11:05:52.063231 Vcore = 725000
7126 11:05:52.066558 Vdram = 0
7127 11:05:52.066641 Vddq = 0
7128 11:05:52.066725 Vmddr = 0
7129 11:05:52.073155 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7130 11:05:52.076417 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7131 11:05:52.079693 MEM_TYPE=3, freq_sel=13
7132 11:05:52.082970 sv_algorithm_assistance_LP4_3733
7133 11:05:52.086256 ============ PULL DRAM RESETB DOWN ============
7134 11:05:52.089362 ========== PULL DRAM RESETB DOWN end =========
7135 11:05:52.096081 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7136 11:05:52.099506 ===================================
7137 11:05:52.099596 LPDDR4 DRAM CONFIGURATION
7138 11:05:52.102878 ===================================
7139 11:05:52.106105 EX_ROW_EN[0] = 0x0
7140 11:05:52.109620 EX_ROW_EN[1] = 0x0
7141 11:05:52.109703 LP4Y_EN = 0x0
7142 11:05:52.112804 WORK_FSP = 0x1
7143 11:05:52.112887 WL = 0x5
7144 11:05:52.116359 RL = 0x5
7145 11:05:52.116443 BL = 0x2
7146 11:05:52.119433 RPST = 0x0
7147 11:05:52.119519 RD_PRE = 0x0
7148 11:05:52.122550 WR_PRE = 0x1
7149 11:05:52.122633 WR_PST = 0x1
7150 11:05:52.126007 DBI_WR = 0x0
7151 11:05:52.126091 DBI_RD = 0x0
7152 11:05:52.129409 OTF = 0x1
7153 11:05:52.132757 ===================================
7154 11:05:52.135807 ===================================
7155 11:05:52.135894 ANA top config
7156 11:05:52.139250 ===================================
7157 11:05:52.142640 DLL_ASYNC_EN = 0
7158 11:05:52.145706 ALL_SLAVE_EN = 0
7159 11:05:52.149135 NEW_RANK_MODE = 1
7160 11:05:52.149223 DLL_IDLE_MODE = 1
7161 11:05:52.152536 LP45_APHY_COMB_EN = 1
7162 11:05:52.155581 TX_ODT_DIS = 0
7163 11:05:52.159384 NEW_8X_MODE = 1
7164 11:05:52.162293 ===================================
7165 11:05:52.165774 ===================================
7166 11:05:52.168940 data_rate = 3200
7167 11:05:52.169023 CKR = 1
7168 11:05:52.172362 DQ_P2S_RATIO = 8
7169 11:05:52.175537 ===================================
7170 11:05:52.178963 CA_P2S_RATIO = 8
7171 11:05:52.182367 DQ_CA_OPEN = 0
7172 11:05:52.185326 DQ_SEMI_OPEN = 0
7173 11:05:52.188876 CA_SEMI_OPEN = 0
7174 11:05:52.188959 CA_FULL_RATE = 0
7175 11:05:52.192224 DQ_CKDIV4_EN = 0
7176 11:05:52.195471 CA_CKDIV4_EN = 0
7177 11:05:52.198701 CA_PREDIV_EN = 0
7178 11:05:52.202007 PH8_DLY = 12
7179 11:05:52.205267 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7180 11:05:52.205375 DQ_AAMCK_DIV = 4
7181 11:05:52.208775 CA_AAMCK_DIV = 4
7182 11:05:52.212231 CA_ADMCK_DIV = 4
7183 11:05:52.215303 DQ_TRACK_CA_EN = 0
7184 11:05:52.218492 CA_PICK = 1600
7185 11:05:52.221789 CA_MCKIO = 1600
7186 11:05:52.225243 MCKIO_SEMI = 0
7187 11:05:52.228675 PLL_FREQ = 3068
7188 11:05:52.228759 DQ_UI_PI_RATIO = 32
7189 11:05:52.231826 CA_UI_PI_RATIO = 0
7190 11:05:52.235325 ===================================
7191 11:05:52.238473 ===================================
7192 11:05:52.241595 memory_type:LPDDR4
7193 11:05:52.245236 GP_NUM : 10
7194 11:05:52.245320 SRAM_EN : 1
7195 11:05:52.248534 MD32_EN : 0
7196 11:05:52.251985 ===================================
7197 11:05:52.252074 [ANA_INIT] >>>>>>>>>>>>>>
7198 11:05:52.254983 <<<<<< [CONFIGURE PHASE]: ANA_TX
7199 11:05:52.258510 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7200 11:05:52.261580 ===================================
7201 11:05:52.265104 data_rate = 3200,PCW = 0X7600
7202 11:05:52.268193 ===================================
7203 11:05:52.271687 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7204 11:05:52.278253 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7205 11:05:52.285049 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7206 11:05:52.288298 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7207 11:05:52.291435 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7208 11:05:52.294903 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7209 11:05:52.298028 [ANA_INIT] flow start
7210 11:05:52.298112 [ANA_INIT] PLL >>>>>>>>
7211 11:05:52.301582 [ANA_INIT] PLL <<<<<<<<
7212 11:05:52.304661 [ANA_INIT] MIDPI >>>>>>>>
7213 11:05:52.304773 [ANA_INIT] MIDPI <<<<<<<<
7214 11:05:52.308012 [ANA_INIT] DLL >>>>>>>>
7215 11:05:52.311348 [ANA_INIT] DLL <<<<<<<<
7216 11:05:52.311432 [ANA_INIT] flow end
7217 11:05:52.317882 ============ LP4 DIFF to SE enter ============
7218 11:05:52.321431 ============ LP4 DIFF to SE exit ============
7219 11:05:52.324784 [ANA_INIT] <<<<<<<<<<<<<
7220 11:05:52.327952 [Flow] Enable top DCM control >>>>>
7221 11:05:52.331106 [Flow] Enable top DCM control <<<<<
7222 11:05:52.331215 Enable DLL master slave shuffle
7223 11:05:52.338129 ==============================================================
7224 11:05:52.341246 Gating Mode config
7225 11:05:52.344677 ==============================================================
7226 11:05:52.347720 Config description:
7227 11:05:52.358136 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7228 11:05:52.364496 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7229 11:05:52.367882 SELPH_MODE 0: By rank 1: By Phase
7230 11:05:52.374504 ==============================================================
7231 11:05:52.377338 GAT_TRACK_EN = 1
7232 11:05:52.380929 RX_GATING_MODE = 2
7233 11:05:52.384049 RX_GATING_TRACK_MODE = 2
7234 11:05:52.387552 SELPH_MODE = 1
7235 11:05:52.387636 PICG_EARLY_EN = 1
7236 11:05:52.390850 VALID_LAT_VALUE = 1
7237 11:05:52.397702 ==============================================================
7238 11:05:52.400791 Enter into Gating configuration >>>>
7239 11:05:52.404412 Exit from Gating configuration <<<<
7240 11:05:52.407453 Enter into DVFS_PRE_config >>>>>
7241 11:05:52.417304 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7242 11:05:52.420838 Exit from DVFS_PRE_config <<<<<
7243 11:05:52.424020 Enter into PICG configuration >>>>
7244 11:05:52.427458 Exit from PICG configuration <<<<
7245 11:05:52.430503 [RX_INPUT] configuration >>>>>
7246 11:05:52.433959 [RX_INPUT] configuration <<<<<
7247 11:05:52.437208 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7248 11:05:52.444043 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7249 11:05:52.450655 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7250 11:05:52.457082 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7251 11:05:52.463747 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7252 11:05:52.470383 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7253 11:05:52.473708 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7254 11:05:52.477048 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7255 11:05:52.480377 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7256 11:05:52.486831 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7257 11:05:52.490396 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7258 11:05:52.493603 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7259 11:05:52.496671 ===================================
7260 11:05:52.500032 LPDDR4 DRAM CONFIGURATION
7261 11:05:52.503518 ===================================
7262 11:05:52.503603 EX_ROW_EN[0] = 0x0
7263 11:05:52.506780 EX_ROW_EN[1] = 0x0
7264 11:05:52.506865 LP4Y_EN = 0x0
7265 11:05:52.509924 WORK_FSP = 0x1
7266 11:05:52.513186 WL = 0x5
7267 11:05:52.513270 RL = 0x5
7268 11:05:52.516639 BL = 0x2
7269 11:05:52.516722 RPST = 0x0
7270 11:05:52.520058 RD_PRE = 0x0
7271 11:05:52.520173 WR_PRE = 0x1
7272 11:05:52.523175 WR_PST = 0x1
7273 11:05:52.523259 DBI_WR = 0x0
7274 11:05:52.526532 DBI_RD = 0x0
7275 11:05:52.526615 OTF = 0x1
7276 11:05:52.529787 ===================================
7277 11:05:52.533329 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7278 11:05:52.539972 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7279 11:05:52.543277 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7280 11:05:52.546499 ===================================
7281 11:05:52.549963 LPDDR4 DRAM CONFIGURATION
7282 11:05:52.553388 ===================================
7283 11:05:52.553523 EX_ROW_EN[0] = 0x10
7284 11:05:52.556616 EX_ROW_EN[1] = 0x0
7285 11:05:52.556700 LP4Y_EN = 0x0
7286 11:05:52.560047 WORK_FSP = 0x1
7287 11:05:52.560131 WL = 0x5
7288 11:05:52.563063 RL = 0x5
7289 11:05:52.563147 BL = 0x2
7290 11:05:52.566483 RPST = 0x0
7291 11:05:52.569689 RD_PRE = 0x0
7292 11:05:52.569773 WR_PRE = 0x1
7293 11:05:52.573243 WR_PST = 0x1
7294 11:05:52.573327 DBI_WR = 0x0
7295 11:05:52.576394 DBI_RD = 0x0
7296 11:05:52.576478 OTF = 0x1
7297 11:05:52.579788 ===================================
7298 11:05:52.586424 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7299 11:05:52.586509 ==
7300 11:05:52.589487 Dram Type= 6, Freq= 0, CH_0, rank 0
7301 11:05:52.592647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7302 11:05:52.592732 ==
7303 11:05:52.596077 [Duty_Offset_Calibration]
7304 11:05:52.599548 B0:2 B1:0 CA:3
7305 11:05:52.599632
7306 11:05:52.602595 [DutyScan_Calibration_Flow] k_type=0
7307 11:05:52.611015
7308 11:05:52.611098 ==CLK 0==
7309 11:05:52.614550 Final CLK duty delay cell = 0
7310 11:05:52.617791 [0] MAX Duty = 5031%(X100), DQS PI = 12
7311 11:05:52.621067 [0] MIN Duty = 4907%(X100), DQS PI = 6
7312 11:05:52.624563 [0] AVG Duty = 4969%(X100)
7313 11:05:52.624647
7314 11:05:52.627836 CH0 CLK Duty spec in!! Max-Min= 124%
7315 11:05:52.630952 [DutyScan_Calibration_Flow] ====Done====
7316 11:05:52.631038
7317 11:05:52.634278 [DutyScan_Calibration_Flow] k_type=1
7318 11:05:52.651038
7319 11:05:52.651131 ==DQS 0 ==
7320 11:05:52.654387 Final DQS duty delay cell = 0
7321 11:05:52.657665 [0] MAX Duty = 5125%(X100), DQS PI = 30
7322 11:05:52.661049 [0] MIN Duty = 4875%(X100), DQS PI = 48
7323 11:05:52.664264 [0] AVG Duty = 5000%(X100)
7324 11:05:52.664348
7325 11:05:52.664435 ==DQS 1 ==
7326 11:05:52.667688 Final DQS duty delay cell = 0
7327 11:05:52.671081 [0] MAX Duty = 5156%(X100), DQS PI = 32
7328 11:05:52.674522 [0] MIN Duty = 5031%(X100), DQS PI = 14
7329 11:05:52.677472 [0] AVG Duty = 5093%(X100)
7330 11:05:52.677563
7331 11:05:52.680996 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7332 11:05:52.681080
7333 11:05:52.684511 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7334 11:05:52.687547 [DutyScan_Calibration_Flow] ====Done====
7335 11:05:52.687631
7336 11:05:52.690959 [DutyScan_Calibration_Flow] k_type=3
7337 11:05:52.709194
7338 11:05:52.709277 ==DQM 0 ==
7339 11:05:52.712846 Final DQM duty delay cell = 0
7340 11:05:52.715871 [0] MAX Duty = 5156%(X100), DQS PI = 14
7341 11:05:52.719193 [0] MIN Duty = 4875%(X100), DQS PI = 0
7342 11:05:52.719278 [0] AVG Duty = 5015%(X100)
7343 11:05:52.722525
7344 11:05:52.722609 ==DQM 1 ==
7345 11:05:52.725711 Final DQM duty delay cell = 4
7346 11:05:52.728997 [4] MAX Duty = 5187%(X100), DQS PI = 60
7347 11:05:52.732436 [4] MIN Duty = 5031%(X100), DQS PI = 14
7348 11:05:52.735786 [4] AVG Duty = 5109%(X100)
7349 11:05:52.735867
7350 11:05:52.739125 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7351 11:05:52.739210
7352 11:05:52.742512 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7353 11:05:52.745782 [DutyScan_Calibration_Flow] ====Done====
7354 11:05:52.745863
7355 11:05:52.748856 [DutyScan_Calibration_Flow] k_type=2
7356 11:05:52.764581
7357 11:05:52.764680 ==DQ 0 ==
7358 11:05:52.767878 Final DQ duty delay cell = -4
7359 11:05:52.771224 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7360 11:05:52.774465 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7361 11:05:52.777765 [-4] AVG Duty = 4938%(X100)
7362 11:05:52.777846
7363 11:05:52.777910 ==DQ 1 ==
7364 11:05:52.781029 Final DQ duty delay cell = -4
7365 11:05:52.784445 [-4] MAX Duty = 5000%(X100), DQS PI = 60
7366 11:05:52.787910 [-4] MIN Duty = 4844%(X100), DQS PI = 18
7367 11:05:52.791359 [-4] AVG Duty = 4922%(X100)
7368 11:05:52.791441
7369 11:05:52.794499 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7370 11:05:52.794581
7371 11:05:52.797774 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7372 11:05:52.800968 [DutyScan_Calibration_Flow] ====Done====
7373 11:05:52.801052 ==
7374 11:05:52.804162 Dram Type= 6, Freq= 0, CH_1, rank 0
7375 11:05:52.807682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7376 11:05:52.807764 ==
7377 11:05:52.811323 [Duty_Offset_Calibration]
7378 11:05:52.811404 B0:1 B1:-2 CA:1
7379 11:05:52.811469
7380 11:05:52.814333 [DutyScan_Calibration_Flow] k_type=0
7381 11:05:52.825727
7382 11:05:52.825808 ==CLK 0==
7383 11:05:52.828869 Final CLK duty delay cell = 0
7384 11:05:52.832189 [0] MAX Duty = 5031%(X100), DQS PI = 0
7385 11:05:52.835559 [0] MIN Duty = 4875%(X100), DQS PI = 28
7386 11:05:52.835640 [0] AVG Duty = 4953%(X100)
7387 11:05:52.838720
7388 11:05:52.838800 CH1 CLK Duty spec in!! Max-Min= 156%
7389 11:05:52.845433 [DutyScan_Calibration_Flow] ====Done====
7390 11:05:52.845564
7391 11:05:52.848844 [DutyScan_Calibration_Flow] k_type=1
7392 11:05:52.865259
7393 11:05:52.865365 ==DQS 0 ==
7394 11:05:52.868368 Final DQS duty delay cell = 0
7395 11:05:52.871851 [0] MAX Duty = 5156%(X100), DQS PI = 0
7396 11:05:52.874997 [0] MIN Duty = 5062%(X100), DQS PI = 14
7397 11:05:52.878574 [0] AVG Duty = 5109%(X100)
7398 11:05:52.878672
7399 11:05:52.878766 ==DQS 1 ==
7400 11:05:52.881904 Final DQS duty delay cell = 0
7401 11:05:52.885189 [0] MAX Duty = 5125%(X100), DQS PI = 28
7402 11:05:52.888254 [0] MIN Duty = 4813%(X100), DQS PI = 58
7403 11:05:52.891727 [0] AVG Duty = 4969%(X100)
7404 11:05:52.891801
7405 11:05:52.895035 CH1 DQS 0 Duty spec in!! Max-Min= 94%
7406 11:05:52.895141
7407 11:05:52.898498 CH1 DQS 1 Duty spec in!! Max-Min= 312%
7408 11:05:52.901511 [DutyScan_Calibration_Flow] ====Done====
7409 11:05:52.901609
7410 11:05:52.904916 [DutyScan_Calibration_Flow] k_type=3
7411 11:05:52.922030
7412 11:05:52.922115 ==DQM 0 ==
7413 11:05:52.925472 Final DQM duty delay cell = 0
7414 11:05:52.928612 [0] MAX Duty = 5000%(X100), DQS PI = 60
7415 11:05:52.932136 [0] MIN Duty = 4844%(X100), DQS PI = 22
7416 11:05:52.935251 [0] AVG Duty = 4922%(X100)
7417 11:05:52.935334
7418 11:05:52.935419 ==DQM 1 ==
7419 11:05:52.938503 Final DQM duty delay cell = 0
7420 11:05:52.942028 [0] MAX Duty = 5062%(X100), DQS PI = 2
7421 11:05:52.945207 [0] MIN Duty = 4875%(X100), DQS PI = 56
7422 11:05:52.948642 [0] AVG Duty = 4968%(X100)
7423 11:05:52.948727
7424 11:05:52.951699 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7425 11:05:52.951784
7426 11:05:52.954923 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7427 11:05:52.958398 [DutyScan_Calibration_Flow] ====Done====
7428 11:05:52.958482
7429 11:05:52.961644 [DutyScan_Calibration_Flow] k_type=2
7430 11:05:52.978914
7431 11:05:52.978997 ==DQ 0 ==
7432 11:05:52.982234 Final DQ duty delay cell = 0
7433 11:05:52.985783 [0] MAX Duty = 5093%(X100), DQS PI = 62
7434 11:05:52.988866 [0] MIN Duty = 4938%(X100), DQS PI = 14
7435 11:05:52.988950 [0] AVG Duty = 5015%(X100)
7436 11:05:52.992141
7437 11:05:52.992224 ==DQ 1 ==
7438 11:05:52.995601 Final DQ duty delay cell = 0
7439 11:05:52.998659 [0] MAX Duty = 5156%(X100), DQS PI = 26
7440 11:05:53.002111 [0] MIN Duty = 4938%(X100), DQS PI = 56
7441 11:05:53.002195 [0] AVG Duty = 5047%(X100)
7442 11:05:53.002279
7443 11:05:53.008805 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7444 11:05:53.008898
7445 11:05:53.012074 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7446 11:05:53.015408 [DutyScan_Calibration_Flow] ====Done====
7447 11:05:53.018818 nWR fixed to 30
7448 11:05:53.018905 [ModeRegInit_LP4] CH0 RK0
7449 11:05:53.022004 [ModeRegInit_LP4] CH0 RK1
7450 11:05:53.025439 [ModeRegInit_LP4] CH1 RK0
7451 11:05:53.028455 [ModeRegInit_LP4] CH1 RK1
7452 11:05:53.028563 match AC timing 5
7453 11:05:53.035241 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7454 11:05:53.038625 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7455 11:05:53.041769 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7456 11:05:53.048479 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7457 11:05:53.051688 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7458 11:05:53.051772 [MiockJmeterHQA]
7459 11:05:53.051857
7460 11:05:53.055129 [DramcMiockJmeter] u1RxGatingPI = 0
7461 11:05:53.058475 0 : 4363, 4138
7462 11:05:53.058561 4 : 4255, 4029
7463 11:05:53.061713 8 : 4363, 4138
7464 11:05:53.061823 12 : 4363, 4137
7465 11:05:53.061927 16 : 4363, 4137
7466 11:05:53.064817 20 : 4252, 4027
7467 11:05:53.064902 24 : 4253, 4027
7468 11:05:53.068149 28 : 4253, 4026
7469 11:05:53.068232 32 : 4252, 4027
7470 11:05:53.071406 36 : 4254, 4029
7471 11:05:53.071481 40 : 4363, 4137
7472 11:05:53.074902 44 : 4252, 4027
7473 11:05:53.075003 48 : 4252, 4027
7474 11:05:53.075094 52 : 4253, 4027
7475 11:05:53.078326 56 : 4255, 4029
7476 11:05:53.078409 60 : 4252, 4027
7477 11:05:53.081452 64 : 4363, 4137
7478 11:05:53.081547 68 : 4363, 4137
7479 11:05:53.084777 72 : 4250, 4027
7480 11:05:53.084860 76 : 4250, 4027
7481 11:05:53.088019 80 : 4250, 4027
7482 11:05:53.088102 84 : 4250, 4027
7483 11:05:53.088168 88 : 4253, 4029
7484 11:05:53.091707 92 : 4360, 4138
7485 11:05:53.091793 96 : 4250, 4027
7486 11:05:53.094818 100 : 4250, 4027
7487 11:05:53.094901 104 : 4360, 3804
7488 11:05:53.097988 108 : 4250, 0
7489 11:05:53.098071 112 : 4250, 0
7490 11:05:53.098138 116 : 4249, 0
7491 11:05:53.101393 120 : 4250, 0
7492 11:05:53.101538 124 : 4250, 0
7493 11:05:53.104818 128 : 4363, 0
7494 11:05:53.104901 132 : 4361, 0
7495 11:05:53.104967 136 : 4360, 0
7496 11:05:53.108222 140 : 4363, 0
7497 11:05:53.108332 144 : 4250, 0
7498 11:05:53.108436 148 : 4250, 0
7499 11:05:53.111333 152 : 4250, 0
7500 11:05:53.111418 156 : 4250, 0
7501 11:05:53.114805 160 : 4250, 0
7502 11:05:53.114890 164 : 4250, 0
7503 11:05:53.114978 168 : 4252, 0
7504 11:05:53.118059 172 : 4360, 0
7505 11:05:53.118169 176 : 4250, 0
7506 11:05:53.121412 180 : 4250, 0
7507 11:05:53.121538 184 : 4361, 0
7508 11:05:53.121624 188 : 4250, 0
7509 11:05:53.124891 192 : 4250, 0
7510 11:05:53.124977 196 : 4250, 0
7511 11:05:53.128049 200 : 4250, 0
7512 11:05:53.128135 204 : 4250, 0
7513 11:05:53.128220 208 : 4252, 0
7514 11:05:53.131505 212 : 4250, 0
7515 11:05:53.131591 216 : 4250, 0
7516 11:05:53.131678 220 : 4252, 0
7517 11:05:53.134649 224 : 4360, 0
7518 11:05:53.134734 228 : 4361, 0
7519 11:05:53.138129 232 : 4361, 0
7520 11:05:53.138241 236 : 4250, 937
7521 11:05:53.141289 240 : 4250, 4025
7522 11:05:53.141374 244 : 4361, 4137
7523 11:05:53.144430 248 : 4250, 4027
7524 11:05:53.144515 252 : 4250, 4027
7525 11:05:53.144601 256 : 4363, 4140
7526 11:05:53.148012 260 : 4250, 4026
7527 11:05:53.148097 264 : 4250, 4027
7528 11:05:53.151400 268 : 4250, 4027
7529 11:05:53.151486 272 : 4252, 4029
7530 11:05:53.154330 276 : 4250, 4026
7531 11:05:53.154445 280 : 4250, 4027
7532 11:05:53.157820 284 : 4360, 4138
7533 11:05:53.157905 288 : 4249, 4027
7534 11:05:53.161038 292 : 4250, 4026
7535 11:05:53.161122 296 : 4361, 4137
7536 11:05:53.164475 300 : 4250, 4027
7537 11:05:53.164560 304 : 4249, 4027
7538 11:05:53.167878 308 : 4363, 4140
7539 11:05:53.167963 312 : 4250, 4026
7540 11:05:53.168050 316 : 4250, 4027
7541 11:05:53.171263 320 : 4249, 4027
7542 11:05:53.171348 324 : 4252, 4029
7543 11:05:53.174487 328 : 4250, 4026
7544 11:05:53.174572 332 : 4250, 4027
7545 11:05:53.177761 336 : 4360, 4138
7546 11:05:53.177845 340 : 4250, 4027
7547 11:05:53.180986 344 : 4250, 4026
7548 11:05:53.181085 348 : 4361, 4137
7549 11:05:53.184317 352 : 4250, 4015
7550 11:05:53.184402 356 : 4250, 2859
7551 11:05:53.187591 360 : 4363, 2
7552 11:05:53.187675
7553 11:05:53.187759 MIOCK jitter meter ch=0
7554 11:05:53.187839
7555 11:05:53.190754 1T = (360-108) = 252 dly cells
7556 11:05:53.197367 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7557 11:05:53.197451 ==
7558 11:05:53.200747 Dram Type= 6, Freq= 0, CH_0, rank 0
7559 11:05:53.204092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7560 11:05:53.204201 ==
7561 11:05:53.210393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7562 11:05:53.214107 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7563 11:05:53.217217 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7564 11:05:53.223930 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7565 11:05:53.233893 [CA 0] Center 43 (13~74) winsize 62
7566 11:05:53.236974 [CA 1] Center 43 (13~74) winsize 62
7567 11:05:53.240252 [CA 2] Center 39 (10~68) winsize 59
7568 11:05:53.243694 [CA 3] Center 38 (9~68) winsize 60
7569 11:05:53.246776 [CA 4] Center 36 (7~66) winsize 60
7570 11:05:53.250332 [CA 5] Center 36 (7~66) winsize 60
7571 11:05:53.250416
7572 11:05:53.253823 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7573 11:05:53.253907
7574 11:05:53.256997 [CATrainingPosCal] consider 1 rank data
7575 11:05:53.260326 u2DelayCellTimex100 = 258/100 ps
7576 11:05:53.266826 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7577 11:05:53.270294 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7578 11:05:53.273443 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7579 11:05:53.276822 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7580 11:05:53.280218 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7581 11:05:53.283227 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7582 11:05:53.283311
7583 11:05:53.286790 CA PerBit enable=1, Macro0, CA PI delay=36
7584 11:05:53.286874
7585 11:05:53.289929 [CBTSetCACLKResult] CA Dly = 36
7586 11:05:53.293291 CS Dly: 11 (0~42)
7587 11:05:53.296416 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7588 11:05:53.299640 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7589 11:05:53.299724 ==
7590 11:05:53.303039 Dram Type= 6, Freq= 0, CH_0, rank 1
7591 11:05:53.309833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7592 11:05:53.309947 ==
7593 11:05:53.313075 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7594 11:05:53.319935 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7595 11:05:53.322991 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7596 11:05:53.329336 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7597 11:05:53.337418 [CA 0] Center 44 (13~75) winsize 63
7598 11:05:53.340852 [CA 1] Center 43 (13~74) winsize 62
7599 11:05:53.344043 [CA 2] Center 39 (10~69) winsize 60
7600 11:05:53.347499 [CA 3] Center 39 (10~68) winsize 59
7601 11:05:53.350829 [CA 4] Center 37 (8~67) winsize 60
7602 11:05:53.353873 [CA 5] Center 36 (7~66) winsize 60
7603 11:05:53.353979
7604 11:05:53.357452 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7605 11:05:53.357543
7606 11:05:53.363756 [CATrainingPosCal] consider 2 rank data
7607 11:05:53.363838 u2DelayCellTimex100 = 258/100 ps
7608 11:05:53.370680 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7609 11:05:53.373898 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7610 11:05:53.377004 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7611 11:05:53.380547 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7612 11:05:53.383754 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7613 11:05:53.386865 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7614 11:05:53.386981
7615 11:05:53.390524 CA PerBit enable=1, Macro0, CA PI delay=36
7616 11:05:53.390610
7617 11:05:53.393362 [CBTSetCACLKResult] CA Dly = 36
7618 11:05:53.396955 CS Dly: 11 (0~43)
7619 11:05:53.400103 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7620 11:05:53.403545 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7621 11:05:53.403652
7622 11:05:53.406704 ----->DramcWriteLeveling(PI) begin...
7623 11:05:53.410059 ==
7624 11:05:53.413382 Dram Type= 6, Freq= 0, CH_0, rank 0
7625 11:05:53.416725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7626 11:05:53.416808 ==
7627 11:05:53.420016 Write leveling (Byte 0): 34 => 34
7628 11:05:53.423357 Write leveling (Byte 1): 29 => 29
7629 11:05:53.426525 DramcWriteLeveling(PI) end<-----
7630 11:05:53.426609
7631 11:05:53.426694 ==
7632 11:05:53.430046 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 11:05:53.433345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 11:05:53.433461 ==
7635 11:05:53.436753 [Gating] SW mode calibration
7636 11:05:53.442929 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7637 11:05:53.449729 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7638 11:05:53.452830 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 11:05:53.456343 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7640 11:05:53.462938 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 11:05:53.466438 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 11:05:53.469565 1 4 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7643 11:05:53.476205 1 4 20 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
7644 11:05:53.479548 1 4 24 | B1->B0 | 302f 3434 | 1 1 | (1 1) (1 1)
7645 11:05:53.483117 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7646 11:05:53.486316 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7647 11:05:53.493007 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7648 11:05:53.496416 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7649 11:05:53.499434 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7650 11:05:53.506256 1 5 16 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (0 0)
7651 11:05:53.509438 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7652 11:05:53.512946 1 5 24 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
7653 11:05:53.519515 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 11:05:53.522726 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 11:05:53.525970 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 11:05:53.532650 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 11:05:53.536319 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7658 11:05:53.539331 1 6 16 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (1 1)
7659 11:05:53.546084 1 6 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7660 11:05:53.549421 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7661 11:05:53.552748 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 11:05:53.559049 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 11:05:53.562668 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 11:05:53.565802 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7665 11:05:53.572452 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7666 11:05:53.575964 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7667 11:05:53.579077 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7668 11:05:53.585726 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7669 11:05:53.589220 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 11:05:53.592280 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 11:05:53.598824 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 11:05:53.602257 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 11:05:53.605710 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 11:05:53.612269 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 11:05:53.615489 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 11:05:53.618856 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 11:05:53.625811 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 11:05:53.628688 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 11:05:53.632011 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 11:05:53.638723 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 11:05:53.641841 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7682 11:05:53.645138 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7683 11:05:53.651834 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7684 11:05:53.651916 Total UI for P1: 0, mck2ui 16
7685 11:05:53.658489 best dqsien dly found for B0: ( 1, 9, 14)
7686 11:05:53.661857 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7687 11:05:53.665002 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7688 11:05:53.671788 1 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7689 11:05:53.671869 Total UI for P1: 0, mck2ui 16
7690 11:05:53.674896 best dqsien dly found for B1: ( 1, 9, 26)
7691 11:05:53.681337 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7692 11:05:53.684789 best DQS1 dly(MCK, UI, PI) = (1, 9, 26)
7693 11:05:53.684871
7694 11:05:53.688082 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7695 11:05:53.691636 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 26)
7696 11:05:53.694911 [Gating] SW calibration Done
7697 11:05:53.694992 ==
7698 11:05:53.698198 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 11:05:53.701514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 11:05:53.701611 ==
7701 11:05:53.704621 RX Vref Scan: 0
7702 11:05:53.704702
7703 11:05:53.704766 RX Vref 0 -> 0, step: 1
7704 11:05:53.704826
7705 11:05:53.708020 RX Delay 0 -> 252, step: 8
7706 11:05:53.711439 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7707 11:05:53.717959 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7708 11:05:53.721230 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7709 11:05:53.724727 iDelay=200, Bit 3, Center 119 (64 ~ 175) 112
7710 11:05:53.728268 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7711 11:05:53.731454 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7712 11:05:53.738213 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7713 11:05:53.741562 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7714 11:05:53.744612 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7715 11:05:53.748296 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7716 11:05:53.751330 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7717 11:05:53.758043 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7718 11:05:53.761273 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7719 11:05:53.764647 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7720 11:05:53.767693 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7721 11:05:53.771159 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7722 11:05:53.774610 ==
7723 11:05:53.774692 Dram Type= 6, Freq= 0, CH_0, rank 0
7724 11:05:53.781107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7725 11:05:53.781188 ==
7726 11:05:53.781253 DQS Delay:
7727 11:05:53.784241 DQS0 = 0, DQS1 = 0
7728 11:05:53.784323 DQM Delay:
7729 11:05:53.787777 DQM0 = 128, DQM1 = 123
7730 11:05:53.787857 DQ Delay:
7731 11:05:53.790906 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7732 11:05:53.794347 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =143
7733 11:05:53.797460 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7734 11:05:53.800800 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7735 11:05:53.800881
7736 11:05:53.800945
7737 11:05:53.801003 ==
7738 11:05:53.804209 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 11:05:53.810693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 11:05:53.810775 ==
7741 11:05:53.810840
7742 11:05:53.810898
7743 11:05:53.810954 TX Vref Scan disable
7744 11:05:53.814430 == TX Byte 0 ==
7745 11:05:53.817962 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7746 11:05:53.824202 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7747 11:05:53.824310 == TX Byte 1 ==
7748 11:05:53.827695 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7749 11:05:53.834368 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7750 11:05:53.834449 ==
7751 11:05:53.837561 Dram Type= 6, Freq= 0, CH_0, rank 0
7752 11:05:53.840655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7753 11:05:53.840736 ==
7754 11:05:53.853852
7755 11:05:53.856907 TX Vref early break, caculate TX vref
7756 11:05:53.860545 TX Vref=16, minBit 8, minWin=20, winSum=351
7757 11:05:53.863773 TX Vref=18, minBit 4, minWin=22, winSum=363
7758 11:05:53.867033 TX Vref=20, minBit 7, minWin=22, winSum=372
7759 11:05:53.870308 TX Vref=22, minBit 0, minWin=23, winSum=378
7760 11:05:53.873411 TX Vref=24, minBit 8, minWin=22, winSum=389
7761 11:05:53.880456 TX Vref=26, minBit 8, minWin=24, winSum=403
7762 11:05:53.883596 TX Vref=28, minBit 0, minWin=25, winSum=405
7763 11:05:53.886992 TX Vref=30, minBit 0, minWin=24, winSum=398
7764 11:05:53.890415 TX Vref=32, minBit 8, minWin=22, winSum=389
7765 11:05:53.893576 TX Vref=34, minBit 8, minWin=21, winSum=381
7766 11:05:53.900249 [TxChooseVref] Worse bit 0, Min win 25, Win sum 405, Final Vref 28
7767 11:05:53.900331
7768 11:05:53.903368 Final TX Range 0 Vref 28
7769 11:05:53.903450
7770 11:05:53.903519 ==
7771 11:05:53.906483 Dram Type= 6, Freq= 0, CH_0, rank 0
7772 11:05:53.909801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7773 11:05:53.909883 ==
7774 11:05:53.909947
7775 11:05:53.910013
7776 11:05:53.913325 TX Vref Scan disable
7777 11:05:53.920049 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7778 11:05:53.920156 == TX Byte 0 ==
7779 11:05:53.923335 u2DelayCellOfst[0]=15 cells (4 PI)
7780 11:05:53.926729 u2DelayCellOfst[1]=18 cells (5 PI)
7781 11:05:53.929944 u2DelayCellOfst[2]=15 cells (4 PI)
7782 11:05:53.933277 u2DelayCellOfst[3]=11 cells (3 PI)
7783 11:05:53.936345 u2DelayCellOfst[4]=11 cells (3 PI)
7784 11:05:53.939734 u2DelayCellOfst[5]=0 cells (0 PI)
7785 11:05:53.943148 u2DelayCellOfst[6]=22 cells (6 PI)
7786 11:05:53.946423 u2DelayCellOfst[7]=18 cells (5 PI)
7787 11:05:53.949733 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7788 11:05:53.953240 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7789 11:05:53.956283 == TX Byte 1 ==
7790 11:05:53.959772 u2DelayCellOfst[8]=0 cells (0 PI)
7791 11:05:53.959884 u2DelayCellOfst[9]=0 cells (0 PI)
7792 11:05:53.962864 u2DelayCellOfst[10]=7 cells (2 PI)
7793 11:05:53.965966 u2DelayCellOfst[11]=3 cells (1 PI)
7794 11:05:53.969541 u2DelayCellOfst[12]=11 cells (3 PI)
7795 11:05:53.972818 u2DelayCellOfst[13]=11 cells (3 PI)
7796 11:05:53.976235 u2DelayCellOfst[14]=15 cells (4 PI)
7797 11:05:53.979398 u2DelayCellOfst[15]=7 cells (2 PI)
7798 11:05:53.982643 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7799 11:05:53.989214 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7800 11:05:53.989295 DramC Write-DBI on
7801 11:05:53.989359 ==
7802 11:05:53.992613 Dram Type= 6, Freq= 0, CH_0, rank 0
7803 11:05:53.999127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7804 11:05:53.999208 ==
7805 11:05:53.999273
7806 11:05:53.999331
7807 11:05:53.999388 TX Vref Scan disable
7808 11:05:54.003332 == TX Byte 0 ==
7809 11:05:54.006823 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7810 11:05:54.009972 == TX Byte 1 ==
7811 11:05:54.013066 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7812 11:05:54.016480 DramC Write-DBI off
7813 11:05:54.016560
7814 11:05:54.016625 [DATLAT]
7815 11:05:54.016684 Freq=1600, CH0 RK0
7816 11:05:54.016742
7817 11:05:54.019697 DATLAT Default: 0xf
7818 11:05:54.019811 0, 0xFFFF, sum = 0
7819 11:05:54.023095 1, 0xFFFF, sum = 0
7820 11:05:54.026431 2, 0xFFFF, sum = 0
7821 11:05:54.026513 3, 0xFFFF, sum = 0
7822 11:05:54.029637 4, 0xFFFF, sum = 0
7823 11:05:54.029719 5, 0xFFFF, sum = 0
7824 11:05:54.033078 6, 0xFFFF, sum = 0
7825 11:05:54.033188 7, 0xFFFF, sum = 0
7826 11:05:54.036262 8, 0xFFFF, sum = 0
7827 11:05:54.036344 9, 0xFFFF, sum = 0
7828 11:05:54.039837 10, 0xFFFF, sum = 0
7829 11:05:54.039920 11, 0xFFFF, sum = 0
7830 11:05:54.042807 12, 0xFFFF, sum = 0
7831 11:05:54.042890 13, 0xFFFF, sum = 0
7832 11:05:54.046142 14, 0x0, sum = 1
7833 11:05:54.046227 15, 0x0, sum = 2
7834 11:05:54.049513 16, 0x0, sum = 3
7835 11:05:54.049598 17, 0x0, sum = 4
7836 11:05:54.052991 best_step = 15
7837 11:05:54.053072
7838 11:05:54.053137 ==
7839 11:05:54.056234 Dram Type= 6, Freq= 0, CH_0, rank 0
7840 11:05:54.059600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7841 11:05:54.059683 ==
7842 11:05:54.062769 RX Vref Scan: 1
7843 11:05:54.062850
7844 11:05:54.062914 Set Vref Range= 24 -> 127
7845 11:05:54.062975
7846 11:05:54.066225 RX Vref 24 -> 127, step: 1
7847 11:05:54.066307
7848 11:05:54.069568 RX Delay 11 -> 252, step: 4
7849 11:05:54.069650
7850 11:05:54.072679 Set Vref, RX VrefLevel [Byte0]: 24
7851 11:05:54.076174 [Byte1]: 24
7852 11:05:54.076256
7853 11:05:54.079546 Set Vref, RX VrefLevel [Byte0]: 25
7854 11:05:54.082818 [Byte1]: 25
7855 11:05:54.086180
7856 11:05:54.086261 Set Vref, RX VrefLevel [Byte0]: 26
7857 11:05:54.089364 [Byte1]: 26
7858 11:05:54.093660
7859 11:05:54.093741 Set Vref, RX VrefLevel [Byte0]: 27
7860 11:05:54.096980 [Byte1]: 27
7861 11:05:54.101152
7862 11:05:54.101233 Set Vref, RX VrefLevel [Byte0]: 28
7863 11:05:54.104411 [Byte1]: 28
7864 11:05:54.108962
7865 11:05:54.109043 Set Vref, RX VrefLevel [Byte0]: 29
7866 11:05:54.111989 [Byte1]: 29
7867 11:05:54.116390
7868 11:05:54.116471 Set Vref, RX VrefLevel [Byte0]: 30
7869 11:05:54.119718 [Byte1]: 30
7870 11:05:54.123999
7871 11:05:54.124081 Set Vref, RX VrefLevel [Byte0]: 31
7872 11:05:54.127325 [Byte1]: 31
7873 11:05:54.131704
7874 11:05:54.131785 Set Vref, RX VrefLevel [Byte0]: 32
7875 11:05:54.135011 [Byte1]: 32
7876 11:05:54.139220
7877 11:05:54.139301 Set Vref, RX VrefLevel [Byte0]: 33
7878 11:05:54.142730 [Byte1]: 33
7879 11:05:54.146967
7880 11:05:54.147049 Set Vref, RX VrefLevel [Byte0]: 34
7881 11:05:54.150475 [Byte1]: 34
7882 11:05:54.154502
7883 11:05:54.154586 Set Vref, RX VrefLevel [Byte0]: 35
7884 11:05:54.157981 [Byte1]: 35
7885 11:05:54.162166
7886 11:05:54.162248 Set Vref, RX VrefLevel [Byte0]: 36
7887 11:05:54.165267 [Byte1]: 36
7888 11:05:54.169774
7889 11:05:54.169856 Set Vref, RX VrefLevel [Byte0]: 37
7890 11:05:54.172929 [Byte1]: 37
7891 11:05:54.177420
7892 11:05:54.177536 Set Vref, RX VrefLevel [Byte0]: 38
7893 11:05:54.180861 [Byte1]: 38
7894 11:05:54.185028
7895 11:05:54.185110 Set Vref, RX VrefLevel [Byte0]: 39
7896 11:05:54.188347 [Byte1]: 39
7897 11:05:54.192740
7898 11:05:54.192822 Set Vref, RX VrefLevel [Byte0]: 40
7899 11:05:54.195823 [Byte1]: 40
7900 11:05:54.200425
7901 11:05:54.200507 Set Vref, RX VrefLevel [Byte0]: 41
7902 11:05:54.203469 [Byte1]: 41
7903 11:05:54.207700
7904 11:05:54.207781 Set Vref, RX VrefLevel [Byte0]: 42
7905 11:05:54.211235 [Byte1]: 42
7906 11:05:54.215561
7907 11:05:54.215642 Set Vref, RX VrefLevel [Byte0]: 43
7908 11:05:54.218704 [Byte1]: 43
7909 11:05:54.223217
7910 11:05:54.223303 Set Vref, RX VrefLevel [Byte0]: 44
7911 11:05:54.226282 [Byte1]: 44
7912 11:05:54.230763
7913 11:05:54.230848 Set Vref, RX VrefLevel [Byte0]: 45
7914 11:05:54.233887 [Byte1]: 45
7915 11:05:54.238400
7916 11:05:54.238485 Set Vref, RX VrefLevel [Byte0]: 46
7917 11:05:54.241688 [Byte1]: 46
7918 11:05:54.246119
7919 11:05:54.246205 Set Vref, RX VrefLevel [Byte0]: 47
7920 11:05:54.249238 [Byte1]: 47
7921 11:05:54.253499
7922 11:05:54.253585 Set Vref, RX VrefLevel [Byte0]: 48
7923 11:05:54.256864 [Byte1]: 48
7924 11:05:54.261049
7925 11:05:54.261129 Set Vref, RX VrefLevel [Byte0]: 49
7926 11:05:54.264563 [Byte1]: 49
7927 11:05:54.268873
7928 11:05:54.268959 Set Vref, RX VrefLevel [Byte0]: 50
7929 11:05:54.272046 [Byte1]: 50
7930 11:05:54.276453
7931 11:05:54.276533 Set Vref, RX VrefLevel [Byte0]: 51
7932 11:05:54.279863 [Byte1]: 51
7933 11:05:54.283983
7934 11:05:54.284064 Set Vref, RX VrefLevel [Byte0]: 52
7935 11:05:54.287319 [Byte1]: 52
7936 11:05:54.291558
7937 11:05:54.291639 Set Vref, RX VrefLevel [Byte0]: 53
7938 11:05:54.294747 [Byte1]: 53
7939 11:05:54.299060
7940 11:05:54.299141 Set Vref, RX VrefLevel [Byte0]: 54
7941 11:05:54.302421 [Byte1]: 54
7942 11:05:54.306934
7943 11:05:54.307015 Set Vref, RX VrefLevel [Byte0]: 55
7944 11:05:54.310018 [Byte1]: 55
7945 11:05:54.314591
7946 11:05:54.314671 Set Vref, RX VrefLevel [Byte0]: 56
7947 11:05:54.317710 [Byte1]: 56
7948 11:05:54.322040
7949 11:05:54.322150 Set Vref, RX VrefLevel [Byte0]: 57
7950 11:05:54.325269 [Byte1]: 57
7951 11:05:54.329462
7952 11:05:54.329580 Set Vref, RX VrefLevel [Byte0]: 58
7953 11:05:54.333122 [Byte1]: 58
7954 11:05:54.337416
7955 11:05:54.337551 Set Vref, RX VrefLevel [Byte0]: 59
7956 11:05:54.340591 [Byte1]: 59
7957 11:05:54.344909
7958 11:05:54.344989 Set Vref, RX VrefLevel [Byte0]: 60
7959 11:05:54.348208 [Byte1]: 60
7960 11:05:54.352754
7961 11:05:54.352842 Set Vref, RX VrefLevel [Byte0]: 61
7962 11:05:54.355773 [Byte1]: 61
7963 11:05:54.360316
7964 11:05:54.360396 Set Vref, RX VrefLevel [Byte0]: 62
7965 11:05:54.363326 [Byte1]: 62
7966 11:05:54.367783
7967 11:05:54.367864 Set Vref, RX VrefLevel [Byte0]: 63
7968 11:05:54.370976 [Byte1]: 63
7969 11:05:54.375320
7970 11:05:54.375401 Set Vref, RX VrefLevel [Byte0]: 64
7971 11:05:54.378481 [Byte1]: 64
7972 11:05:54.382765
7973 11:05:54.382846 Set Vref, RX VrefLevel [Byte0]: 65
7974 11:05:54.386421 [Byte1]: 65
7975 11:05:54.390382
7976 11:05:54.390463 Set Vref, RX VrefLevel [Byte0]: 66
7977 11:05:54.394165 [Byte1]: 66
7978 11:05:54.398046
7979 11:05:54.398127 Set Vref, RX VrefLevel [Byte0]: 67
7980 11:05:54.401258 [Byte1]: 67
7981 11:05:54.405680
7982 11:05:54.405787 Set Vref, RX VrefLevel [Byte0]: 68
7983 11:05:54.409025 [Byte1]: 68
7984 11:05:54.413293
7985 11:05:54.413399 Set Vref, RX VrefLevel [Byte0]: 69
7986 11:05:54.416862 [Byte1]: 69
7987 11:05:54.421032
7988 11:05:54.421141 Set Vref, RX VrefLevel [Byte0]: 70
7989 11:05:54.424440 [Byte1]: 70
7990 11:05:54.428601
7991 11:05:54.428682 Set Vref, RX VrefLevel [Byte0]: 71
7992 11:05:54.431744 [Byte1]: 71
7993 11:05:54.436291
7994 11:05:54.436382 Set Vref, RX VrefLevel [Byte0]: 72
7995 11:05:54.439582 [Byte1]: 72
7996 11:05:54.443670
7997 11:05:54.443776 Set Vref, RX VrefLevel [Byte0]: 73
7998 11:05:54.447424 [Byte1]: 73
7999 11:05:54.451516
8000 11:05:54.451597 Set Vref, RX VrefLevel [Byte0]: 74
8001 11:05:54.454615 [Byte1]: 74
8002 11:05:54.459012
8003 11:05:54.459093 Set Vref, RX VrefLevel [Byte0]: 75
8004 11:05:54.462410 [Byte1]: 75
8005 11:05:54.466787
8006 11:05:54.466880 Set Vref, RX VrefLevel [Byte0]: 76
8007 11:05:54.469846 [Byte1]: 76
8008 11:05:54.474486
8009 11:05:54.474567 Set Vref, RX VrefLevel [Byte0]: 77
8010 11:05:54.477598 [Byte1]: 77
8011 11:05:54.481947
8012 11:05:54.482027 Set Vref, RX VrefLevel [Byte0]: 78
8013 11:05:54.485046 [Byte1]: 78
8014 11:05:54.489368
8015 11:05:54.489481 Final RX Vref Byte 0 = 61 to rank0
8016 11:05:54.492770 Final RX Vref Byte 1 = 60 to rank0
8017 11:05:54.496187 Final RX Vref Byte 0 = 61 to rank1
8018 11:05:54.499380 Final RX Vref Byte 1 = 60 to rank1==
8019 11:05:54.502768 Dram Type= 6, Freq= 0, CH_0, rank 0
8020 11:05:54.509410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8021 11:05:54.509519 ==
8022 11:05:54.509585 DQS Delay:
8023 11:05:54.512361 DQS0 = 0, DQS1 = 0
8024 11:05:54.512441 DQM Delay:
8025 11:05:54.512525 DQM0 = 125, DQM1 = 119
8026 11:05:54.515962 DQ Delay:
8027 11:05:54.519395 DQ0 =124, DQ1 =128, DQ2 =124, DQ3 =122
8028 11:05:54.522445 DQ4 =124, DQ5 =112, DQ6 =132, DQ7 =136
8029 11:05:54.525971 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8030 11:05:54.529404 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
8031 11:05:54.529512
8032 11:05:54.529578
8033 11:05:54.529638
8034 11:05:54.532504 [DramC_TX_OE_Calibration] TA2
8035 11:05:54.535897 Original DQ_B0 (3 6) =30, OEN = 27
8036 11:05:54.539051 Original DQ_B1 (3 6) =30, OEN = 27
8037 11:05:54.542443 24, 0x0, End_B0=24 End_B1=24
8038 11:05:54.542525 25, 0x0, End_B0=25 End_B1=25
8039 11:05:54.545621 26, 0x0, End_B0=26 End_B1=26
8040 11:05:54.549002 27, 0x0, End_B0=27 End_B1=27
8041 11:05:54.552338 28, 0x0, End_B0=28 End_B1=28
8042 11:05:54.555819 29, 0x0, End_B0=29 End_B1=29
8043 11:05:54.555901 30, 0x0, End_B0=30 End_B1=30
8044 11:05:54.559047 31, 0x4141, End_B0=30 End_B1=30
8045 11:05:54.562808 Byte0 end_step=30 best_step=27
8046 11:05:54.565823 Byte1 end_step=30 best_step=27
8047 11:05:54.569157 Byte0 TX OE(2T, 0.5T) = (3, 3)
8048 11:05:54.572616 Byte1 TX OE(2T, 0.5T) = (3, 3)
8049 11:05:54.572697
8050 11:05:54.572761
8051 11:05:54.579030 [DQSOSCAuto] RK0, (LSB)MR18= 0x1211, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8052 11:05:54.582615 CH0 RK0: MR19=303, MR18=1211
8053 11:05:54.588883 CH0_RK0: MR19=0x303, MR18=0x1211, DQSOSC=400, MR23=63, INC=23, DEC=15
8054 11:05:54.588965
8055 11:05:54.592458 ----->DramcWriteLeveling(PI) begin...
8056 11:05:54.592540 ==
8057 11:05:54.595650 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 11:05:54.598949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 11:05:54.599030 ==
8060 11:05:54.602344 Write leveling (Byte 0): 35 => 35
8061 11:05:54.605757 Write leveling (Byte 1): 29 => 29
8062 11:05:54.608748 DramcWriteLeveling(PI) end<-----
8063 11:05:54.608837
8064 11:05:54.608902 ==
8065 11:05:54.612283 Dram Type= 6, Freq= 0, CH_0, rank 1
8066 11:05:54.615313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8067 11:05:54.615394 ==
8068 11:05:54.618827 [Gating] SW mode calibration
8069 11:05:54.625614 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8070 11:05:54.632112 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8071 11:05:54.635244 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 11:05:54.641879 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 11:05:54.645558 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 11:05:54.648570 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8075 11:05:54.655275 1 4 16 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
8076 11:05:54.658300 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8077 11:05:54.661792 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8078 11:05:54.668060 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8079 11:05:54.671587 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8080 11:05:54.674875 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8081 11:05:54.681661 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8082 11:05:54.684710 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
8083 11:05:54.687894 1 5 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
8084 11:05:54.694489 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8085 11:05:54.697753 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8086 11:05:54.701087 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8087 11:05:54.707642 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8088 11:05:54.711115 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8089 11:05:54.714444 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8090 11:05:54.720875 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (1 1)
8091 11:05:54.724016 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8092 11:05:54.727451 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8093 11:05:54.734027 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8094 11:05:54.737510 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8095 11:05:54.740814 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8096 11:05:54.747306 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 11:05:54.750375 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8098 11:05:54.753876 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8099 11:05:54.760457 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8100 11:05:54.763967 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8101 11:05:54.766985 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 11:05:54.773879 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 11:05:54.777015 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 11:05:54.780245 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 11:05:54.787028 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 11:05:54.790395 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 11:05:54.793721 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 11:05:54.800242 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 11:05:54.803601 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 11:05:54.807149 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 11:05:54.810232 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 11:05:54.816661 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 11:05:54.820335 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8114 11:05:54.823252 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8115 11:05:54.829962 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8116 11:05:54.833343 Total UI for P1: 0, mck2ui 16
8117 11:05:54.836670 best dqsien dly found for B0: ( 1, 9, 10)
8118 11:05:54.840003 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8119 11:05:54.843292 Total UI for P1: 0, mck2ui 16
8120 11:05:54.846590 best dqsien dly found for B1: ( 1, 9, 16)
8121 11:05:54.849894 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8122 11:05:54.853404 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8123 11:05:54.853547
8124 11:05:54.856497 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8125 11:05:54.862793 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8126 11:05:54.862875 [Gating] SW calibration Done
8127 11:05:54.862940 ==
8128 11:05:54.866367 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 11:05:54.872969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 11:05:54.873050 ==
8131 11:05:54.873124 RX Vref Scan: 0
8132 11:05:54.873186
8133 11:05:54.876063 RX Vref 0 -> 0, step: 1
8134 11:05:54.876144
8135 11:05:54.879581 RX Delay 0 -> 252, step: 8
8136 11:05:54.882784 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8137 11:05:54.886314 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8138 11:05:54.889405 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8139 11:05:54.896036 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8140 11:05:54.899148 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8141 11:05:54.902532 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8142 11:05:54.905869 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8143 11:05:54.909163 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8144 11:05:54.915894 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8145 11:05:54.919113 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8146 11:05:54.922408 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8147 11:05:54.925702 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8148 11:05:54.929305 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8149 11:05:54.935688 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8150 11:05:54.939042 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8151 11:05:54.942205 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8152 11:05:54.942285 ==
8153 11:05:54.945750 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 11:05:54.948879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 11:05:54.952315 ==
8156 11:05:54.952396 DQS Delay:
8157 11:05:54.952460 DQS0 = 0, DQS1 = 0
8158 11:05:54.955378 DQM Delay:
8159 11:05:54.955459 DQM0 = 128, DQM1 = 122
8160 11:05:54.958727 DQ Delay:
8161 11:05:54.961907 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8162 11:05:54.965365 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8163 11:05:54.968657 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8164 11:05:54.972189 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8165 11:05:54.972270
8166 11:05:54.972334
8167 11:05:54.972392 ==
8168 11:05:54.975327 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 11:05:54.978395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 11:05:54.978477 ==
8171 11:05:54.981806
8172 11:05:54.981886
8173 11:05:54.981949 TX Vref Scan disable
8174 11:05:54.985033 == TX Byte 0 ==
8175 11:05:54.988473 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8176 11:05:54.991542 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8177 11:05:54.994914 == TX Byte 1 ==
8178 11:05:54.998432 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8179 11:05:55.001611 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8180 11:05:55.001692 ==
8181 11:05:55.005012 Dram Type= 6, Freq= 0, CH_0, rank 1
8182 11:05:55.011726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8183 11:05:55.011808 ==
8184 11:05:55.025411
8185 11:05:55.028536 TX Vref early break, caculate TX vref
8186 11:05:55.031887 TX Vref=16, minBit 8, minWin=21, winSum=363
8187 11:05:55.035415 TX Vref=18, minBit 8, minWin=21, winSum=370
8188 11:05:55.038812 TX Vref=20, minBit 8, minWin=22, winSum=382
8189 11:05:55.041850 TX Vref=22, minBit 9, minWin=22, winSum=391
8190 11:05:55.045353 TX Vref=24, minBit 8, minWin=23, winSum=395
8191 11:05:55.051939 TX Vref=26, minBit 8, minWin=24, winSum=407
8192 11:05:55.055182 TX Vref=28, minBit 8, minWin=24, winSum=410
8193 11:05:55.058393 TX Vref=30, minBit 8, minWin=22, winSum=405
8194 11:05:55.062007 TX Vref=32, minBit 8, minWin=22, winSum=401
8195 11:05:55.065329 TX Vref=34, minBit 8, minWin=22, winSum=390
8196 11:05:55.068632 TX Vref=36, minBit 8, minWin=22, winSum=384
8197 11:05:55.075490 [TxChooseVref] Worse bit 8, Min win 24, Win sum 410, Final Vref 28
8198 11:05:55.075572
8199 11:05:55.078370 Final TX Range 0 Vref 28
8200 11:05:55.078452
8201 11:05:55.078516 ==
8202 11:05:55.081863 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 11:05:55.085426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 11:05:55.085545 ==
8205 11:05:55.085610
8206 11:05:55.085669
8207 11:05:55.088432 TX Vref Scan disable
8208 11:05:55.095024 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8209 11:05:55.095105 == TX Byte 0 ==
8210 11:05:55.098366 u2DelayCellOfst[0]=11 cells (3 PI)
8211 11:05:55.101756 u2DelayCellOfst[1]=18 cells (5 PI)
8212 11:05:55.104880 u2DelayCellOfst[2]=11 cells (3 PI)
8213 11:05:55.108320 u2DelayCellOfst[3]=11 cells (3 PI)
8214 11:05:55.111592 u2DelayCellOfst[4]=7 cells (2 PI)
8215 11:05:55.115128 u2DelayCellOfst[5]=0 cells (0 PI)
8216 11:05:55.118215 u2DelayCellOfst[6]=18 cells (5 PI)
8217 11:05:55.121449 u2DelayCellOfst[7]=18 cells (5 PI)
8218 11:05:55.124956 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8219 11:05:55.128318 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8220 11:05:55.131524 == TX Byte 1 ==
8221 11:05:55.134646 u2DelayCellOfst[8]=0 cells (0 PI)
8222 11:05:55.138071 u2DelayCellOfst[9]=0 cells (0 PI)
8223 11:05:55.138153 u2DelayCellOfst[10]=7 cells (2 PI)
8224 11:05:55.141581 u2DelayCellOfst[11]=7 cells (2 PI)
8225 11:05:55.144706 u2DelayCellOfst[12]=11 cells (3 PI)
8226 11:05:55.148113 u2DelayCellOfst[13]=11 cells (3 PI)
8227 11:05:55.151328 u2DelayCellOfst[14]=15 cells (4 PI)
8228 11:05:55.154784 u2DelayCellOfst[15]=11 cells (3 PI)
8229 11:05:55.161340 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8230 11:05:55.164379 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8231 11:05:55.164460 DramC Write-DBI on
8232 11:05:55.164525 ==
8233 11:05:55.167851 Dram Type= 6, Freq= 0, CH_0, rank 1
8234 11:05:55.174520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8235 11:05:55.174620 ==
8236 11:05:55.174698
8237 11:05:55.174757
8238 11:05:55.174813 TX Vref Scan disable
8239 11:05:55.178988 == TX Byte 0 ==
8240 11:05:55.181903 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8241 11:05:55.185501 == TX Byte 1 ==
8242 11:05:55.188732 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8243 11:05:55.191846 DramC Write-DBI off
8244 11:05:55.191927
8245 11:05:55.191991 [DATLAT]
8246 11:05:55.192050 Freq=1600, CH0 RK1
8247 11:05:55.192116
8248 11:05:55.195094 DATLAT Default: 0xf
8249 11:05:55.195175 0, 0xFFFF, sum = 0
8250 11:05:55.198568 1, 0xFFFF, sum = 0
8251 11:05:55.201735 2, 0xFFFF, sum = 0
8252 11:05:55.201820 3, 0xFFFF, sum = 0
8253 11:05:55.205221 4, 0xFFFF, sum = 0
8254 11:05:55.205304 5, 0xFFFF, sum = 0
8255 11:05:55.208409 6, 0xFFFF, sum = 0
8256 11:05:55.208517 7, 0xFFFF, sum = 0
8257 11:05:55.211975 8, 0xFFFF, sum = 0
8258 11:05:55.212057 9, 0xFFFF, sum = 0
8259 11:05:55.214859 10, 0xFFFF, sum = 0
8260 11:05:55.214941 11, 0xFFFF, sum = 0
8261 11:05:55.218301 12, 0xFFFF, sum = 0
8262 11:05:55.218383 13, 0xCFFF, sum = 0
8263 11:05:55.221734 14, 0x0, sum = 1
8264 11:05:55.221843 15, 0x0, sum = 2
8265 11:05:55.225074 16, 0x0, sum = 3
8266 11:05:55.225156 17, 0x0, sum = 4
8267 11:05:55.228263 best_step = 15
8268 11:05:55.228344
8269 11:05:55.228408 ==
8270 11:05:55.231732 Dram Type= 6, Freq= 0, CH_0, rank 1
8271 11:05:55.234810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8272 11:05:55.234892 ==
8273 11:05:55.238201 RX Vref Scan: 0
8274 11:05:55.238290
8275 11:05:55.238356 RX Vref 0 -> 0, step: 1
8276 11:05:55.238416
8277 11:05:55.241708 RX Delay 3 -> 252, step: 4
8278 11:05:55.244776 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8279 11:05:55.251561 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8280 11:05:55.254642 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8281 11:05:55.258015 iDelay=191, Bit 3, Center 120 (63 ~ 178) 116
8282 11:05:55.261509 iDelay=191, Bit 4, Center 122 (67 ~ 178) 112
8283 11:05:55.264815 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8284 11:05:55.271347 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8285 11:05:55.274697 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8286 11:05:55.278077 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8287 11:05:55.281262 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8288 11:05:55.284826 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8289 11:05:55.291464 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8290 11:05:55.294750 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8291 11:05:55.298329 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8292 11:05:55.301381 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8293 11:05:55.304938 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8294 11:05:55.308126 ==
8295 11:05:55.311624 Dram Type= 6, Freq= 0, CH_0, rank 1
8296 11:05:55.314903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8297 11:05:55.314985 ==
8298 11:05:55.315050 DQS Delay:
8299 11:05:55.317953 DQS0 = 0, DQS1 = 0
8300 11:05:55.318033 DQM Delay:
8301 11:05:55.321276 DQM0 = 124, DQM1 = 118
8302 11:05:55.321383 DQ Delay:
8303 11:05:55.324825 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =120
8304 11:05:55.328339 DQ4 =122, DQ5 =112, DQ6 =134, DQ7 =134
8305 11:05:55.331341 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8306 11:05:55.334793 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8307 11:05:55.334874
8308 11:05:55.334937
8309 11:05:55.334996
8310 11:05:55.338043 [DramC_TX_OE_Calibration] TA2
8311 11:05:55.341482 Original DQ_B0 (3 6) =30, OEN = 27
8312 11:05:55.344838 Original DQ_B1 (3 6) =30, OEN = 27
8313 11:05:55.348087 24, 0x0, End_B0=24 End_B1=24
8314 11:05:55.351321 25, 0x0, End_B0=25 End_B1=25
8315 11:05:55.351403 26, 0x0, End_B0=26 End_B1=26
8316 11:05:55.354446 27, 0x0, End_B0=27 End_B1=27
8317 11:05:55.357812 28, 0x0, End_B0=28 End_B1=28
8318 11:05:55.361147 29, 0x0, End_B0=29 End_B1=29
8319 11:05:55.364436 30, 0x0, End_B0=30 End_B1=30
8320 11:05:55.364518 31, 0x4141, End_B0=30 End_B1=30
8321 11:05:55.368118 Byte0 end_step=30 best_step=27
8322 11:05:55.371261 Byte1 end_step=30 best_step=27
8323 11:05:55.374314 Byte0 TX OE(2T, 0.5T) = (3, 3)
8324 11:05:55.377726 Byte1 TX OE(2T, 0.5T) = (3, 3)
8325 11:05:55.377807
8326 11:05:55.377871
8327 11:05:55.384337 [DQSOSCAuto] RK1, (LSB)MR18= 0x220f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8328 11:05:55.387479 CH0 RK1: MR19=303, MR18=220F
8329 11:05:55.394140 CH0_RK1: MR19=0x303, MR18=0x220F, DQSOSC=392, MR23=63, INC=24, DEC=16
8330 11:05:55.397656 [RxdqsGatingPostProcess] freq 1600
8331 11:05:55.404071 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8332 11:05:55.407602 best DQS0 dly(2T, 0.5T) = (1, 1)
8333 11:05:55.407683 best DQS1 dly(2T, 0.5T) = (1, 1)
8334 11:05:55.410720 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8335 11:05:55.414206 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8336 11:05:55.417337 best DQS0 dly(2T, 0.5T) = (1, 1)
8337 11:05:55.420838 best DQS1 dly(2T, 0.5T) = (1, 1)
8338 11:05:55.424108 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8339 11:05:55.427437 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8340 11:05:55.430611 Pre-setting of DQS Precalculation
8341 11:05:55.434085 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8342 11:05:55.434166 ==
8343 11:05:55.437402 Dram Type= 6, Freq= 0, CH_1, rank 0
8344 11:05:55.443917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8345 11:05:55.443999 ==
8346 11:05:55.447391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8347 11:05:55.453829 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8348 11:05:55.457001 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8349 11:05:55.463556 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8350 11:05:55.471645 [CA 0] Center 41 (12~70) winsize 59
8351 11:05:55.475175 [CA 1] Center 42 (12~72) winsize 61
8352 11:05:55.478158 [CA 2] Center 37 (8~66) winsize 59
8353 11:05:55.481452 [CA 3] Center 37 (8~66) winsize 59
8354 11:05:55.485244 [CA 4] Center 37 (8~67) winsize 60
8355 11:05:55.488386 [CA 5] Center 36 (7~66) winsize 60
8356 11:05:55.488468
8357 11:05:55.491538 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8358 11:05:55.491619
8359 11:05:55.495010 [CATrainingPosCal] consider 1 rank data
8360 11:05:55.498552 u2DelayCellTimex100 = 258/100 ps
8361 11:05:55.501732 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8362 11:05:55.508252 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8363 11:05:55.511516 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8364 11:05:55.514938 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8365 11:05:55.518079 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8366 11:05:55.521485 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8367 11:05:55.521620
8368 11:05:55.524798 CA PerBit enable=1, Macro0, CA PI delay=36
8369 11:05:55.524937
8370 11:05:55.528268 [CBTSetCACLKResult] CA Dly = 36
8371 11:05:55.531319 CS Dly: 9 (0~40)
8372 11:05:55.534627 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8373 11:05:55.538078 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8374 11:05:55.538276 ==
8375 11:05:55.541537 Dram Type= 6, Freq= 0, CH_1, rank 1
8376 11:05:55.544966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 11:05:55.548095 ==
8378 11:05:55.551733 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8379 11:05:55.554884 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8380 11:05:55.561651 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8381 11:05:55.567816 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8382 11:05:55.575456 [CA 0] Center 41 (12~71) winsize 60
8383 11:05:55.578646 [CA 1] Center 42 (12~72) winsize 61
8384 11:05:55.582132 [CA 2] Center 38 (8~68) winsize 61
8385 11:05:55.585254 [CA 3] Center 37 (8~66) winsize 59
8386 11:05:55.588279 [CA 4] Center 38 (9~68) winsize 60
8387 11:05:55.591697 [CA 5] Center 37 (7~67) winsize 61
8388 11:05:55.591777
8389 11:05:55.594670 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8390 11:05:55.594750
8391 11:05:55.598224 [CATrainingPosCal] consider 2 rank data
8392 11:05:55.601343 u2DelayCellTimex100 = 258/100 ps
8393 11:05:55.604645 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8394 11:05:55.611508 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8395 11:05:55.614759 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8396 11:05:55.618066 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8397 11:05:55.621338 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8398 11:05:55.624483 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8399 11:05:55.624564
8400 11:05:55.627693 CA PerBit enable=1, Macro0, CA PI delay=36
8401 11:05:55.627773
8402 11:05:55.631240 [CBTSetCACLKResult] CA Dly = 36
8403 11:05:55.634670 CS Dly: 11 (0~44)
8404 11:05:55.637659 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8405 11:05:55.641102 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8406 11:05:55.641182
8407 11:05:55.644721 ----->DramcWriteLeveling(PI) begin...
8408 11:05:55.644804 ==
8409 11:05:55.647598 Dram Type= 6, Freq= 0, CH_1, rank 0
8410 11:05:55.654376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8411 11:05:55.654458 ==
8412 11:05:55.657613 Write leveling (Byte 0): 24 => 24
8413 11:05:55.657693 Write leveling (Byte 1): 27 => 27
8414 11:05:55.661018 DramcWriteLeveling(PI) end<-----
8415 11:05:55.661104
8416 11:05:55.664280 ==
8417 11:05:55.664361 Dram Type= 6, Freq= 0, CH_1, rank 0
8418 11:05:55.670877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8419 11:05:55.670958 ==
8420 11:05:55.674097 [Gating] SW mode calibration
8421 11:05:55.680535 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8422 11:05:55.684078 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8423 11:05:55.690508 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 11:05:55.693999 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 11:05:55.697147 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 11:05:55.703746 1 4 12 | B1->B0 | 2525 2323 | 1 1 | (1 1) (1 1)
8427 11:05:55.707070 1 4 16 | B1->B0 | 3434 3333 | 1 1 | (0 0) (1 1)
8428 11:05:55.710584 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8429 11:05:55.717047 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8430 11:05:55.720082 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8431 11:05:55.723585 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8432 11:05:55.730042 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8433 11:05:55.733458 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8434 11:05:55.736986 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8435 11:05:55.743530 1 5 16 | B1->B0 | 2626 2424 | 0 0 | (0 0) (1 0)
8436 11:05:55.746711 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 11:05:55.750110 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 11:05:55.756920 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 11:05:55.760311 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8440 11:05:55.763477 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8441 11:05:55.769787 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8442 11:05:55.773343 1 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8443 11:05:55.776344 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 11:05:55.783229 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8445 11:05:55.786445 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8446 11:05:55.789463 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8447 11:05:55.796298 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 11:05:55.799614 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8449 11:05:55.802871 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8450 11:05:55.809433 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8451 11:05:55.812752 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8452 11:05:55.815878 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8453 11:05:55.822737 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 11:05:55.825905 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 11:05:55.829294 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 11:05:55.836012 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 11:05:55.838927 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 11:05:55.842240 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 11:05:55.848771 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 11:05:55.852360 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 11:05:55.855332 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 11:05:55.862142 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 11:05:55.865322 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 11:05:55.869052 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 11:05:55.875213 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 11:05:55.878569 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8467 11:05:55.882154 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8468 11:05:55.885210 Total UI for P1: 0, mck2ui 16
8469 11:05:55.888678 best dqsien dly found for B1: ( 1, 9, 12)
8470 11:05:55.895150 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8471 11:05:55.895234 Total UI for P1: 0, mck2ui 16
8472 11:05:55.901831 best dqsien dly found for B0: ( 1, 9, 16)
8473 11:05:55.904908 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8474 11:05:55.908206 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8475 11:05:55.908289
8476 11:05:55.911837 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8477 11:05:55.914865 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8478 11:05:55.918187 [Gating] SW calibration Done
8479 11:05:55.918270 ==
8480 11:05:55.921585 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 11:05:55.924879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 11:05:55.924962 ==
8483 11:05:55.928230 RX Vref Scan: 0
8484 11:05:55.928312
8485 11:05:55.928377 RX Vref 0 -> 0, step: 1
8486 11:05:55.931283
8487 11:05:55.931366 RX Delay 0 -> 252, step: 8
8488 11:05:55.934711 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8489 11:05:55.941299 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8490 11:05:55.944578 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8491 11:05:55.948097 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8492 11:05:55.951354 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8493 11:05:55.954392 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8494 11:05:55.961386 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8495 11:05:55.964405 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8496 11:05:55.967976 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8497 11:05:55.971364 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8498 11:05:55.977498 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8499 11:05:55.981047 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8500 11:05:55.984524 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8501 11:05:55.987505 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8502 11:05:55.991063 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8503 11:05:55.997746 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8504 11:05:55.997832 ==
8505 11:05:56.000902 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 11:05:56.004016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8507 11:05:56.004099 ==
8508 11:05:56.004165 DQS Delay:
8509 11:05:56.007403 DQS0 = 0, DQS1 = 0
8510 11:05:56.007500 DQM Delay:
8511 11:05:56.011012 DQM0 = 131, DQM1 = 126
8512 11:05:56.011097 DQ Delay:
8513 11:05:56.014033 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8514 11:05:56.017226 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8515 11:05:56.020576 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8516 11:05:56.024507 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8517 11:05:56.024593
8518 11:05:56.027383
8519 11:05:56.027468 ==
8520 11:05:56.030575 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 11:05:56.033822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 11:05:56.033907 ==
8523 11:05:56.033994
8524 11:05:56.034075
8525 11:05:56.037215 TX Vref Scan disable
8526 11:05:56.037301 == TX Byte 0 ==
8527 11:05:56.043835 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8528 11:05:56.046805 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8529 11:05:56.046891 == TX Byte 1 ==
8530 11:05:56.053845 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8531 11:05:56.056874 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8532 11:05:56.056960 ==
8533 11:05:56.060073 Dram Type= 6, Freq= 0, CH_1, rank 0
8534 11:05:56.063397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8535 11:05:56.063484 ==
8536 11:05:56.078117
8537 11:05:56.081481 TX Vref early break, caculate TX vref
8538 11:05:56.084665 TX Vref=16, minBit 1, minWin=22, winSum=364
8539 11:05:56.088047 TX Vref=18, minBit 11, minWin=22, winSum=378
8540 11:05:56.091080 TX Vref=20, minBit 5, minWin=23, winSum=387
8541 11:05:56.094645 TX Vref=22, minBit 5, minWin=23, winSum=393
8542 11:05:56.098103 TX Vref=24, minBit 1, minWin=25, winSum=410
8543 11:05:56.104354 TX Vref=26, minBit 1, minWin=25, winSum=413
8544 11:05:56.107809 TX Vref=28, minBit 1, minWin=25, winSum=421
8545 11:05:56.111230 TX Vref=30, minBit 0, minWin=25, winSum=415
8546 11:05:56.114590 TX Vref=32, minBit 5, minWin=24, winSum=411
8547 11:05:56.117662 TX Vref=34, minBit 1, minWin=23, winSum=399
8548 11:05:56.121291 TX Vref=36, minBit 1, minWin=23, winSum=387
8549 11:05:56.127867 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 28
8550 11:05:56.127954
8551 11:05:56.131012 Final TX Range 0 Vref 28
8552 11:05:56.131098
8553 11:05:56.131184 ==
8554 11:05:56.134501 Dram Type= 6, Freq= 0, CH_1, rank 0
8555 11:05:56.137633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8556 11:05:56.137719 ==
8557 11:05:56.137806
8558 11:05:56.140909
8559 11:05:56.140994 TX Vref Scan disable
8560 11:05:56.147499 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8561 11:05:56.147585 == TX Byte 0 ==
8562 11:05:56.150767 u2DelayCellOfst[0]=18 cells (5 PI)
8563 11:05:56.154343 u2DelayCellOfst[1]=15 cells (4 PI)
8564 11:05:56.157527 u2DelayCellOfst[2]=0 cells (0 PI)
8565 11:05:56.160885 u2DelayCellOfst[3]=3 cells (1 PI)
8566 11:05:56.164022 u2DelayCellOfst[4]=7 cells (2 PI)
8567 11:05:56.167577 u2DelayCellOfst[5]=22 cells (6 PI)
8568 11:05:56.171034 u2DelayCellOfst[6]=18 cells (5 PI)
8569 11:05:56.174182 u2DelayCellOfst[7]=3 cells (1 PI)
8570 11:05:56.177309 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8571 11:05:56.180733 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8572 11:05:56.184068 == TX Byte 1 ==
8573 11:05:56.187571 u2DelayCellOfst[8]=0 cells (0 PI)
8574 11:05:56.190667 u2DelayCellOfst[9]=7 cells (2 PI)
8575 11:05:56.190753 u2DelayCellOfst[10]=15 cells (4 PI)
8576 11:05:56.194173 u2DelayCellOfst[11]=7 cells (2 PI)
8577 11:05:56.197220 u2DelayCellOfst[12]=18 cells (5 PI)
8578 11:05:56.200563 u2DelayCellOfst[13]=22 cells (6 PI)
8579 11:05:56.203959 u2DelayCellOfst[14]=22 cells (6 PI)
8580 11:05:56.207154 u2DelayCellOfst[15]=22 cells (6 PI)
8581 11:05:56.213935 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8582 11:05:56.217210 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8583 11:05:56.217291 DramC Write-DBI on
8584 11:05:56.217355 ==
8585 11:05:56.220309 Dram Type= 6, Freq= 0, CH_1, rank 0
8586 11:05:56.227325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8587 11:05:56.227411 ==
8588 11:05:56.227497
8589 11:05:56.227579
8590 11:05:56.230421 TX Vref Scan disable
8591 11:05:56.230506 == TX Byte 0 ==
8592 11:05:56.237076 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8593 11:05:56.237161 == TX Byte 1 ==
8594 11:05:56.240159 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8595 11:05:56.243738 DramC Write-DBI off
8596 11:05:56.243823
8597 11:05:56.243908 [DATLAT]
8598 11:05:56.246951 Freq=1600, CH1 RK0
8599 11:05:56.247037
8600 11:05:56.247124 DATLAT Default: 0xf
8601 11:05:56.250085 0, 0xFFFF, sum = 0
8602 11:05:56.250172 1, 0xFFFF, sum = 0
8603 11:05:56.253620 2, 0xFFFF, sum = 0
8604 11:05:56.253706 3, 0xFFFF, sum = 0
8605 11:05:56.256585 4, 0xFFFF, sum = 0
8606 11:05:56.256671 5, 0xFFFF, sum = 0
8607 11:05:56.259867 6, 0xFFFF, sum = 0
8608 11:05:56.259954 7, 0xFFFF, sum = 0
8609 11:05:56.263349 8, 0xFFFF, sum = 0
8610 11:05:56.263431 9, 0xFFFF, sum = 0
8611 11:05:56.266761 10, 0xFFFF, sum = 0
8612 11:05:56.270085 11, 0xFFFF, sum = 0
8613 11:05:56.270167 12, 0xFFFF, sum = 0
8614 11:05:56.273412 13, 0x8FFF, sum = 0
8615 11:05:56.273525 14, 0x0, sum = 1
8616 11:05:56.276577 15, 0x0, sum = 2
8617 11:05:56.276659 16, 0x0, sum = 3
8618 11:05:56.280039 17, 0x0, sum = 4
8619 11:05:56.280121 best_step = 15
8620 11:05:56.280184
8621 11:05:56.280243 ==
8622 11:05:56.283089 Dram Type= 6, Freq= 0, CH_1, rank 0
8623 11:05:56.286311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8624 11:05:56.286392 ==
8625 11:05:56.289876 RX Vref Scan: 1
8626 11:05:56.289982
8627 11:05:56.293031 Set Vref Range= 24 -> 127
8628 11:05:56.293112
8629 11:05:56.293176 RX Vref 24 -> 127, step: 1
8630 11:05:56.293235
8631 11:05:56.296218 RX Delay 11 -> 252, step: 4
8632 11:05:56.296298
8633 11:05:56.299641 Set Vref, RX VrefLevel [Byte0]: 24
8634 11:05:56.303015 [Byte1]: 24
8635 11:05:56.306406
8636 11:05:56.306493 Set Vref, RX VrefLevel [Byte0]: 25
8637 11:05:56.309957 [Byte1]: 25
8638 11:05:56.314208
8639 11:05:56.314289 Set Vref, RX VrefLevel [Byte0]: 26
8640 11:05:56.317272 [Byte1]: 26
8641 11:05:56.321713
8642 11:05:56.321794 Set Vref, RX VrefLevel [Byte0]: 27
8643 11:05:56.324929 [Byte1]: 27
8644 11:05:56.329200
8645 11:05:56.329307 Set Vref, RX VrefLevel [Byte0]: 28
8646 11:05:56.332573 [Byte1]: 28
8647 11:05:56.337126
8648 11:05:56.337233 Set Vref, RX VrefLevel [Byte0]: 29
8649 11:05:56.340211 [Byte1]: 29
8650 11:05:56.344444
8651 11:05:56.344525 Set Vref, RX VrefLevel [Byte0]: 30
8652 11:05:56.347945 [Byte1]: 30
8653 11:05:56.352211
8654 11:05:56.352291 Set Vref, RX VrefLevel [Byte0]: 31
8655 11:05:56.355261 [Byte1]: 31
8656 11:05:56.359842
8657 11:05:56.359948 Set Vref, RX VrefLevel [Byte0]: 32
8658 11:05:56.362941 [Byte1]: 32
8659 11:05:56.367411
8660 11:05:56.367491 Set Vref, RX VrefLevel [Byte0]: 33
8661 11:05:56.370771 [Byte1]: 33
8662 11:05:56.374945
8663 11:05:56.375026 Set Vref, RX VrefLevel [Byte0]: 34
8664 11:05:56.378361 [Byte1]: 34
8665 11:05:56.382574
8666 11:05:56.382654 Set Vref, RX VrefLevel [Byte0]: 35
8667 11:05:56.385750 [Byte1]: 35
8668 11:05:56.390233
8669 11:05:56.390321 Set Vref, RX VrefLevel [Byte0]: 36
8670 11:05:56.393642 [Byte1]: 36
8671 11:05:56.397981
8672 11:05:56.398080 Set Vref, RX VrefLevel [Byte0]: 37
8673 11:05:56.401303 [Byte1]: 37
8674 11:05:56.405598
8675 11:05:56.405706 Set Vref, RX VrefLevel [Byte0]: 38
8676 11:05:56.408824 [Byte1]: 38
8677 11:05:56.413060
8678 11:05:56.413162 Set Vref, RX VrefLevel [Byte0]: 39
8679 11:05:56.416221 [Byte1]: 39
8680 11:05:56.420506
8681 11:05:56.420602 Set Vref, RX VrefLevel [Byte0]: 40
8682 11:05:56.423947 [Byte1]: 40
8683 11:05:56.428257
8684 11:05:56.428369 Set Vref, RX VrefLevel [Byte0]: 41
8685 11:05:56.431585 [Byte1]: 41
8686 11:05:56.435884
8687 11:05:56.435988 Set Vref, RX VrefLevel [Byte0]: 42
8688 11:05:56.438933 [Byte1]: 42
8689 11:05:56.443488
8690 11:05:56.443586 Set Vref, RX VrefLevel [Byte0]: 43
8691 11:05:56.446711 [Byte1]: 43
8692 11:05:56.451303
8693 11:05:56.451405 Set Vref, RX VrefLevel [Byte0]: 44
8694 11:05:56.454346 [Byte1]: 44
8695 11:05:56.458918
8696 11:05:56.459016 Set Vref, RX VrefLevel [Byte0]: 45
8697 11:05:56.462047 [Byte1]: 45
8698 11:05:56.466305
8699 11:05:56.466387 Set Vref, RX VrefLevel [Byte0]: 46
8700 11:05:56.469758 [Byte1]: 46
8701 11:05:56.473910
8702 11:05:56.473980 Set Vref, RX VrefLevel [Byte0]: 47
8703 11:05:56.477330 [Byte1]: 47
8704 11:05:56.481568
8705 11:05:56.481664 Set Vref, RX VrefLevel [Byte0]: 48
8706 11:05:56.484686 [Byte1]: 48
8707 11:05:56.489083
8708 11:05:56.489177 Set Vref, RX VrefLevel [Byte0]: 49
8709 11:05:56.492527 [Byte1]: 49
8710 11:05:56.496777
8711 11:05:56.496879 Set Vref, RX VrefLevel [Byte0]: 50
8712 11:05:56.500201 [Byte1]: 50
8713 11:05:56.504285
8714 11:05:56.504384 Set Vref, RX VrefLevel [Byte0]: 51
8715 11:05:56.507694 [Byte1]: 51
8716 11:05:56.512063
8717 11:05:56.512172 Set Vref, RX VrefLevel [Byte0]: 52
8718 11:05:56.515479 [Byte1]: 52
8719 11:05:56.519596
8720 11:05:56.519705 Set Vref, RX VrefLevel [Byte0]: 53
8721 11:05:56.522801 [Byte1]: 53
8722 11:05:56.527346
8723 11:05:56.527448 Set Vref, RX VrefLevel [Byte0]: 54
8724 11:05:56.530466 [Byte1]: 54
8725 11:05:56.534994
8726 11:05:56.535096 Set Vref, RX VrefLevel [Byte0]: 55
8727 11:05:56.541371 [Byte1]: 55
8728 11:05:56.541470
8729 11:05:56.544706 Set Vref, RX VrefLevel [Byte0]: 56
8730 11:05:56.547718 [Byte1]: 56
8731 11:05:56.547816
8732 11:05:56.551062 Set Vref, RX VrefLevel [Byte0]: 57
8733 11:05:56.554257 [Byte1]: 57
8734 11:05:56.557704
8735 11:05:56.557804 Set Vref, RX VrefLevel [Byte0]: 58
8736 11:05:56.560839 [Byte1]: 58
8737 11:05:56.565325
8738 11:05:56.565431 Set Vref, RX VrefLevel [Byte0]: 59
8739 11:05:56.568745 [Byte1]: 59
8740 11:05:56.573075
8741 11:05:56.573180 Set Vref, RX VrefLevel [Byte0]: 60
8742 11:05:56.576225 [Byte1]: 60
8743 11:05:56.580404
8744 11:05:56.580478 Set Vref, RX VrefLevel [Byte0]: 61
8745 11:05:56.583935 [Byte1]: 61
8746 11:05:56.588122
8747 11:05:56.588212 Set Vref, RX VrefLevel [Byte0]: 62
8748 11:05:56.591741 [Byte1]: 62
8749 11:05:56.595873
8750 11:05:56.595958 Set Vref, RX VrefLevel [Byte0]: 63
8751 11:05:56.598904 [Byte1]: 63
8752 11:05:56.603239
8753 11:05:56.603324 Set Vref, RX VrefLevel [Byte0]: 64
8754 11:05:56.606702 [Byte1]: 64
8755 11:05:56.610952
8756 11:05:56.611064 Set Vref, RX VrefLevel [Byte0]: 65
8757 11:05:56.614572 [Byte1]: 65
8758 11:05:56.618687
8759 11:05:56.618772 Set Vref, RX VrefLevel [Byte0]: 66
8760 11:05:56.621631 [Byte1]: 66
8761 11:05:56.626362
8762 11:05:56.626447 Set Vref, RX VrefLevel [Byte0]: 67
8763 11:05:56.629426 [Byte1]: 67
8764 11:05:56.633916
8765 11:05:56.634005 Set Vref, RX VrefLevel [Byte0]: 68
8766 11:05:56.637284 [Byte1]: 68
8767 11:05:56.641361
8768 11:05:56.641468 Set Vref, RX VrefLevel [Byte0]: 69
8769 11:05:56.644883 [Byte1]: 69
8770 11:05:56.649066
8771 11:05:56.649148 Set Vref, RX VrefLevel [Byte0]: 70
8772 11:05:56.652503 [Byte1]: 70
8773 11:05:56.656759
8774 11:05:56.656841 Set Vref, RX VrefLevel [Byte0]: 71
8775 11:05:56.660094 [Byte1]: 71
8776 11:05:56.664367
8777 11:05:56.664450 Final RX Vref Byte 0 = 60 to rank0
8778 11:05:56.667498 Final RX Vref Byte 1 = 55 to rank0
8779 11:05:56.670996 Final RX Vref Byte 0 = 60 to rank1
8780 11:05:56.674098 Final RX Vref Byte 1 = 55 to rank1==
8781 11:05:56.677553 Dram Type= 6, Freq= 0, CH_1, rank 0
8782 11:05:56.684110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 11:05:56.684196 ==
8784 11:05:56.684283 DQS Delay:
8785 11:05:56.684364 DQS0 = 0, DQS1 = 0
8786 11:05:56.687626 DQM Delay:
8787 11:05:56.687711 DQM0 = 131, DQM1 = 123
8788 11:05:56.690789 DQ Delay:
8789 11:05:56.694147 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =128
8790 11:05:56.697411 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8791 11:05:56.700858 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8792 11:05:56.704257 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8793 11:05:56.704341
8794 11:05:56.704427
8795 11:05:56.704507
8796 11:05:56.707503 [DramC_TX_OE_Calibration] TA2
8797 11:05:56.710836 Original DQ_B0 (3 6) =30, OEN = 27
8798 11:05:56.714258 Original DQ_B1 (3 6) =30, OEN = 27
8799 11:05:56.717690 24, 0x0, End_B0=24 End_B1=24
8800 11:05:56.717777 25, 0x0, End_B0=25 End_B1=25
8801 11:05:56.720650 26, 0x0, End_B0=26 End_B1=26
8802 11:05:56.724130 27, 0x0, End_B0=27 End_B1=27
8803 11:05:56.727158 28, 0x0, End_B0=28 End_B1=28
8804 11:05:56.730561 29, 0x0, End_B0=29 End_B1=29
8805 11:05:56.730647 30, 0x0, End_B0=30 End_B1=30
8806 11:05:56.733927 31, 0x4141, End_B0=30 End_B1=30
8807 11:05:56.737211 Byte0 end_step=30 best_step=27
8808 11:05:56.740766 Byte1 end_step=30 best_step=27
8809 11:05:56.743712 Byte0 TX OE(2T, 0.5T) = (3, 3)
8810 11:05:56.746955 Byte1 TX OE(2T, 0.5T) = (3, 3)
8811 11:05:56.747041
8812 11:05:56.747127
8813 11:05:56.753861 [DQSOSCAuto] RK0, (LSB)MR18= 0x80d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8814 11:05:56.757018 CH1 RK0: MR19=303, MR18=80D
8815 11:05:56.763985 CH1_RK0: MR19=0x303, MR18=0x80D, DQSOSC=403, MR23=63, INC=22, DEC=15
8816 11:05:56.764071
8817 11:05:56.766778 ----->DramcWriteLeveling(PI) begin...
8818 11:05:56.766864 ==
8819 11:05:56.770074 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 11:05:56.773257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 11:05:56.773343 ==
8822 11:05:56.776761 Write leveling (Byte 0): 24 => 24
8823 11:05:56.779921 Write leveling (Byte 1): 29 => 29
8824 11:05:56.783477 DramcWriteLeveling(PI) end<-----
8825 11:05:56.783562
8826 11:05:56.783649 ==
8827 11:05:56.786630 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 11:05:56.790207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 11:05:56.790293 ==
8830 11:05:56.793271 [Gating] SW mode calibration
8831 11:05:56.799777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8832 11:05:56.806412 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8833 11:05:56.809890 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 11:05:56.816579 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 11:05:56.819604 1 4 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8836 11:05:56.823059 1 4 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
8837 11:05:56.829805 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 11:05:56.833054 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 11:05:56.836231 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 11:05:56.842749 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8841 11:05:56.846156 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8842 11:05:56.849438 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8843 11:05:56.856117 1 5 8 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
8844 11:05:56.859455 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8845 11:05:56.862593 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 11:05:56.866403 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 11:05:56.872688 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 11:05:56.875802 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 11:05:56.879244 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8850 11:05:56.885705 1 6 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
8851 11:05:56.889209 1 6 8 | B1->B0 | 2727 4545 | 1 0 | (0 0) (0 0)
8852 11:05:56.892286 1 6 12 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
8853 11:05:56.899057 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 11:05:56.902143 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 11:05:56.905510 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 11:05:56.912112 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 11:05:56.915466 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 11:05:56.918699 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8859 11:05:56.925317 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8860 11:05:56.928967 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8861 11:05:56.931903 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 11:05:56.938786 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 11:05:56.941947 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 11:05:56.945388 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 11:05:56.951945 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 11:05:56.955392 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 11:05:56.958572 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 11:05:56.965391 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 11:05:56.968654 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 11:05:56.971800 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 11:05:56.978390 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 11:05:56.981879 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 11:05:56.985074 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 11:05:56.991759 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 11:05:56.995352 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8876 11:05:56.998454 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8877 11:05:57.001422 Total UI for P1: 0, mck2ui 16
8878 11:05:57.004927 best dqsien dly found for B0: ( 1, 9, 8)
8879 11:05:57.011484 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8880 11:05:57.011594 Total UI for P1: 0, mck2ui 16
8881 11:05:57.018248 best dqsien dly found for B1: ( 1, 9, 12)
8882 11:05:57.021472 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8883 11:05:57.024762 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8884 11:05:57.024848
8885 11:05:57.028141 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8886 11:05:57.031433 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8887 11:05:57.034580 [Gating] SW calibration Done
8888 11:05:57.034665 ==
8889 11:05:57.037973 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 11:05:57.041393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 11:05:57.041544 ==
8892 11:05:57.044529 RX Vref Scan: 0
8893 11:05:57.044611
8894 11:05:57.044676 RX Vref 0 -> 0, step: 1
8895 11:05:57.044738
8896 11:05:57.048095 RX Delay 0 -> 252, step: 8
8897 11:05:57.051276 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8898 11:05:57.057901 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8899 11:05:57.061081 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8900 11:05:57.064437 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8901 11:05:57.067755 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8902 11:05:57.071254 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8903 11:05:57.077651 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8904 11:05:57.081211 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8905 11:05:57.084364 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8906 11:05:57.087762 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8907 11:05:57.090922 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8908 11:05:57.097759 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8909 11:05:57.101032 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8910 11:05:57.104271 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8911 11:05:57.107679 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8912 11:05:57.114269 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8913 11:05:57.114351 ==
8914 11:05:57.117666 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 11:05:57.120774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 11:05:57.120857 ==
8917 11:05:57.120922 DQS Delay:
8918 11:05:57.124204 DQS0 = 0, DQS1 = 0
8919 11:05:57.124286 DQM Delay:
8920 11:05:57.127400 DQM0 = 133, DQM1 = 128
8921 11:05:57.127484 DQ Delay:
8922 11:05:57.130881 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8923 11:05:57.134016 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8924 11:05:57.137462 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8925 11:05:57.140827 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8926 11:05:57.140912
8927 11:05:57.140998
8928 11:05:57.143907 ==
8929 11:05:57.143992 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 11:05:57.150846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 11:05:57.150932 ==
8932 11:05:57.151019
8933 11:05:57.151101
8934 11:05:57.153806 TX Vref Scan disable
8935 11:05:57.153916 == TX Byte 0 ==
8936 11:05:57.157254 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8937 11:05:57.163932 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8938 11:05:57.164018 == TX Byte 1 ==
8939 11:05:57.167110 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8940 11:05:57.173645 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8941 11:05:57.173731 ==
8942 11:05:57.177048 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 11:05:57.180502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 11:05:57.180587 ==
8945 11:05:57.194886
8946 11:05:57.198444 TX Vref early break, caculate TX vref
8947 11:05:57.201375 TX Vref=16, minBit 8, minWin=22, winSum=378
8948 11:05:57.204913 TX Vref=18, minBit 0, minWin=23, winSum=384
8949 11:05:57.208107 TX Vref=20, minBit 8, minWin=23, winSum=395
8950 11:05:57.211211 TX Vref=22, minBit 8, minWin=24, winSum=401
8951 11:05:57.214696 TX Vref=24, minBit 8, minWin=24, winSum=414
8952 11:05:57.221316 TX Vref=26, minBit 5, minWin=25, winSum=418
8953 11:05:57.224735 TX Vref=28, minBit 5, minWin=25, winSum=419
8954 11:05:57.228117 TX Vref=30, minBit 1, minWin=25, winSum=417
8955 11:05:57.231394 TX Vref=32, minBit 5, minWin=23, winSum=409
8956 11:05:57.234717 TX Vref=34, minBit 5, minWin=23, winSum=398
8957 11:05:57.237904 TX Vref=36, minBit 1, minWin=23, winSum=390
8958 11:05:57.244676 [TxChooseVref] Worse bit 5, Min win 25, Win sum 419, Final Vref 28
8959 11:05:57.244786
8960 11:05:57.247699 Final TX Range 0 Vref 28
8961 11:05:57.247786
8962 11:05:57.247871 ==
8963 11:05:57.251111 Dram Type= 6, Freq= 0, CH_1, rank 1
8964 11:05:57.254517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8965 11:05:57.254603 ==
8966 11:05:57.254690
8967 11:05:57.257761
8968 11:05:57.257846 TX Vref Scan disable
8969 11:05:57.264444 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8970 11:05:57.264530 == TX Byte 0 ==
8971 11:05:57.267862 u2DelayCellOfst[0]=18 cells (5 PI)
8972 11:05:57.270947 u2DelayCellOfst[1]=11 cells (3 PI)
8973 11:05:57.274490 u2DelayCellOfst[2]=0 cells (0 PI)
8974 11:05:57.277843 u2DelayCellOfst[3]=7 cells (2 PI)
8975 11:05:57.281086 u2DelayCellOfst[4]=7 cells (2 PI)
8976 11:05:57.284072 u2DelayCellOfst[5]=22 cells (6 PI)
8977 11:05:57.287563 u2DelayCellOfst[6]=18 cells (5 PI)
8978 11:05:57.291137 u2DelayCellOfst[7]=7 cells (2 PI)
8979 11:05:57.294357 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8980 11:05:57.297437 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8981 11:05:57.300868 == TX Byte 1 ==
8982 11:05:57.304269 u2DelayCellOfst[8]=0 cells (0 PI)
8983 11:05:57.307599 u2DelayCellOfst[9]=3 cells (1 PI)
8984 11:05:57.310619 u2DelayCellOfst[10]=11 cells (3 PI)
8985 11:05:57.310704 u2DelayCellOfst[11]=3 cells (1 PI)
8986 11:05:57.314007 u2DelayCellOfst[12]=15 cells (4 PI)
8987 11:05:57.317395 u2DelayCellOfst[13]=15 cells (4 PI)
8988 11:05:57.320665 u2DelayCellOfst[14]=18 cells (5 PI)
8989 11:05:57.324021 u2DelayCellOfst[15]=15 cells (4 PI)
8990 11:05:57.330626 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8991 11:05:57.333759 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8992 11:05:57.333837 DramC Write-DBI on
8993 11:05:57.337010 ==
8994 11:05:57.337101 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 11:05:57.343969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 11:05:57.344059 ==
8997 11:05:57.344146
8998 11:05:57.344227
8999 11:05:57.346932 TX Vref Scan disable
9000 11:05:57.347052 == TX Byte 0 ==
9001 11:05:57.353581 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9002 11:05:57.353658 == TX Byte 1 ==
9003 11:05:57.356796 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
9004 11:05:57.360260 DramC Write-DBI off
9005 11:05:57.360363
9006 11:05:57.360453 [DATLAT]
9007 11:05:57.363730 Freq=1600, CH1 RK1
9008 11:05:57.363807
9009 11:05:57.363871 DATLAT Default: 0xf
9010 11:05:57.366751 0, 0xFFFF, sum = 0
9011 11:05:57.366852 1, 0xFFFF, sum = 0
9012 11:05:57.370022 2, 0xFFFF, sum = 0
9013 11:05:57.370096 3, 0xFFFF, sum = 0
9014 11:05:57.373341 4, 0xFFFF, sum = 0
9015 11:05:57.373440 5, 0xFFFF, sum = 0
9016 11:05:57.376693 6, 0xFFFF, sum = 0
9017 11:05:57.376765 7, 0xFFFF, sum = 0
9018 11:05:57.379838 8, 0xFFFF, sum = 0
9019 11:05:57.383235 9, 0xFFFF, sum = 0
9020 11:05:57.383313 10, 0xFFFF, sum = 0
9021 11:05:57.386729 11, 0xFFFF, sum = 0
9022 11:05:57.386804 12, 0xFFFF, sum = 0
9023 11:05:57.390003 13, 0x8FFF, sum = 0
9024 11:05:57.390075 14, 0x0, sum = 1
9025 11:05:57.393347 15, 0x0, sum = 2
9026 11:05:57.393448 16, 0x0, sum = 3
9027 11:05:57.396733 17, 0x0, sum = 4
9028 11:05:57.396834 best_step = 15
9029 11:05:57.396922
9030 11:05:57.397007 ==
9031 11:05:57.399911 Dram Type= 6, Freq= 0, CH_1, rank 1
9032 11:05:57.403353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9033 11:05:57.403439 ==
9034 11:05:57.406704 RX Vref Scan: 0
9035 11:05:57.406789
9036 11:05:57.409767 RX Vref 0 -> 0, step: 1
9037 11:05:57.409849
9038 11:05:57.409915 RX Delay 11 -> 252, step: 4
9039 11:05:57.416928 iDelay=195, Bit 0, Center 136 (83 ~ 190) 108
9040 11:05:57.420053 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9041 11:05:57.423658 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9042 11:05:57.426843 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
9043 11:05:57.430219 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9044 11:05:57.437068 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9045 11:05:57.440203 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9046 11:05:57.443418 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
9047 11:05:57.446743 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9048 11:05:57.450376 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
9049 11:05:57.456610 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9050 11:05:57.460020 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9051 11:05:57.463475 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9052 11:05:57.466608 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9053 11:05:57.473374 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9054 11:05:57.476610 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9055 11:05:57.476695 ==
9056 11:05:57.479960 Dram Type= 6, Freq= 0, CH_1, rank 1
9057 11:05:57.483056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9058 11:05:57.483141 ==
9059 11:05:57.486340 DQS Delay:
9060 11:05:57.486425 DQS0 = 0, DQS1 = 0
9061 11:05:57.486511 DQM Delay:
9062 11:05:57.489640 DQM0 = 130, DQM1 = 125
9063 11:05:57.489728 DQ Delay:
9064 11:05:57.492916 DQ0 =136, DQ1 =128, DQ2 =118, DQ3 =128
9065 11:05:57.496302 DQ4 =126, DQ5 =140, DQ6 =142, DQ7 =126
9066 11:05:57.499779 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =120
9067 11:05:57.506320 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =136
9068 11:05:57.506405
9069 11:05:57.506492
9070 11:05:57.506573
9071 11:05:57.509709 [DramC_TX_OE_Calibration] TA2
9072 11:05:57.512764 Original DQ_B0 (3 6) =30, OEN = 27
9073 11:05:57.512850 Original DQ_B1 (3 6) =30, OEN = 27
9074 11:05:57.516027 24, 0x0, End_B0=24 End_B1=24
9075 11:05:57.519603 25, 0x0, End_B0=25 End_B1=25
9076 11:05:57.522959 26, 0x0, End_B0=26 End_B1=26
9077 11:05:57.526082 27, 0x0, End_B0=27 End_B1=27
9078 11:05:57.526168 28, 0x0, End_B0=28 End_B1=28
9079 11:05:57.529232 29, 0x0, End_B0=29 End_B1=29
9080 11:05:57.532821 30, 0x0, End_B0=30 End_B1=30
9081 11:05:57.536013 31, 0x4141, End_B0=30 End_B1=30
9082 11:05:57.539406 Byte0 end_step=30 best_step=27
9083 11:05:57.542834 Byte1 end_step=30 best_step=27
9084 11:05:57.542919 Byte0 TX OE(2T, 0.5T) = (3, 3)
9085 11:05:57.546030 Byte1 TX OE(2T, 0.5T) = (3, 3)
9086 11:05:57.546115
9087 11:05:57.546200
9088 11:05:57.555945 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
9089 11:05:57.556031 CH1 RK1: MR19=303, MR18=D1A
9090 11:05:57.562709 CH1_RK1: MR19=0x303, MR18=0xD1A, DQSOSC=396, MR23=63, INC=23, DEC=15
9091 11:05:57.565728 [RxdqsGatingPostProcess] freq 1600
9092 11:05:57.572552 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9093 11:05:57.575895 best DQS0 dly(2T, 0.5T) = (1, 1)
9094 11:05:57.578922 best DQS1 dly(2T, 0.5T) = (1, 1)
9095 11:05:57.582429 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9096 11:05:57.585949 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9097 11:05:57.586034 best DQS0 dly(2T, 0.5T) = (1, 1)
9098 11:05:57.588956 best DQS1 dly(2T, 0.5T) = (1, 1)
9099 11:05:57.592448 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9100 11:05:57.595718 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9101 11:05:57.598952 Pre-setting of DQS Precalculation
9102 11:05:57.605502 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9103 11:05:57.612195 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9104 11:05:57.618687 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9105 11:05:57.618773
9106 11:05:57.618858
9107 11:05:57.621779 [Calibration Summary] 3200 Mbps
9108 11:05:57.621864 CH 0, Rank 0
9109 11:05:57.625534 SW Impedance : PASS
9110 11:05:57.628652 DUTY Scan : NO K
9111 11:05:57.628756 ZQ Calibration : PASS
9112 11:05:57.631750 Jitter Meter : NO K
9113 11:05:57.635368 CBT Training : PASS
9114 11:05:57.635469 Write leveling : PASS
9115 11:05:57.638432 RX DQS gating : PASS
9116 11:05:57.641924 RX DQ/DQS(RDDQC) : PASS
9117 11:05:57.642001 TX DQ/DQS : PASS
9118 11:05:57.645243 RX DATLAT : PASS
9119 11:05:57.648335 RX DQ/DQS(Engine): PASS
9120 11:05:57.648437 TX OE : PASS
9121 11:05:57.651572 All Pass.
9122 11:05:57.651670
9123 11:05:57.651762 CH 0, Rank 1
9124 11:05:57.655320 SW Impedance : PASS
9125 11:05:57.655418 DUTY Scan : NO K
9126 11:05:57.658519 ZQ Calibration : PASS
9127 11:05:57.661594 Jitter Meter : NO K
9128 11:05:57.661697 CBT Training : PASS
9129 11:05:57.665037 Write leveling : PASS
9130 11:05:57.668469 RX DQS gating : PASS
9131 11:05:57.668573 RX DQ/DQS(RDDQC) : PASS
9132 11:05:57.671675 TX DQ/DQS : PASS
9133 11:05:57.671773 RX DATLAT : PASS
9134 11:05:57.675059 RX DQ/DQS(Engine): PASS
9135 11:05:57.678171 TX OE : PASS
9136 11:05:57.678247 All Pass.
9137 11:05:57.678311
9138 11:05:57.678369 CH 1, Rank 0
9139 11:05:57.681650 SW Impedance : PASS
9140 11:05:57.684641 DUTY Scan : NO K
9141 11:05:57.684716 ZQ Calibration : PASS
9142 11:05:57.688136 Jitter Meter : NO K
9143 11:05:57.691694 CBT Training : PASS
9144 11:05:57.691772 Write leveling : PASS
9145 11:05:57.694842 RX DQS gating : PASS
9146 11:05:57.698329 RX DQ/DQS(RDDQC) : PASS
9147 11:05:57.698414 TX DQ/DQS : PASS
9148 11:05:57.701436 RX DATLAT : PASS
9149 11:05:57.704624 RX DQ/DQS(Engine): PASS
9150 11:05:57.704709 TX OE : PASS
9151 11:05:57.708119 All Pass.
9152 11:05:57.708203
9153 11:05:57.708289 CH 1, Rank 1
9154 11:05:57.711221 SW Impedance : PASS
9155 11:05:57.711320 DUTY Scan : NO K
9156 11:05:57.714648 ZQ Calibration : PASS
9157 11:05:57.718039 Jitter Meter : NO K
9158 11:05:57.718124 CBT Training : PASS
9159 11:05:57.721435 Write leveling : PASS
9160 11:05:57.724546 RX DQS gating : PASS
9161 11:05:57.724631 RX DQ/DQS(RDDQC) : PASS
9162 11:05:57.727945 TX DQ/DQS : PASS
9163 11:05:57.731294 RX DATLAT : PASS
9164 11:05:57.731379 RX DQ/DQS(Engine): PASS
9165 11:05:57.734404 TX OE : PASS
9166 11:05:57.734489 All Pass.
9167 11:05:57.734575
9168 11:05:57.737655 DramC Write-DBI on
9169 11:05:57.740924 PER_BANK_REFRESH: Hybrid Mode
9170 11:05:57.741006 TX_TRACKING: ON
9171 11:05:57.750937 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9172 11:05:57.757817 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9173 11:05:57.764103 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9174 11:05:57.767400 [FAST_K] Save calibration result to emmc
9175 11:05:57.771002 sync common calibartion params.
9176 11:05:57.774230 sync cbt_mode0:1, 1:1
9177 11:05:57.777384 dram_init: ddr_geometry: 2
9178 11:05:57.777467 dram_init: ddr_geometry: 2
9179 11:05:57.780665 dram_init: ddr_geometry: 2
9180 11:05:57.784108 0:dram_rank_size:100000000
9181 11:05:57.784192 1:dram_rank_size:100000000
9182 11:05:57.790859 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9183 11:05:57.794045 DFS_SHUFFLE_HW_MODE: ON
9184 11:05:57.797246 dramc_set_vcore_voltage set vcore to 725000
9185 11:05:57.800821 Read voltage for 1600, 0
9186 11:05:57.800903 Vio18 = 0
9187 11:05:57.800968 Vcore = 725000
9188 11:05:57.803964 Vdram = 0
9189 11:05:57.804047 Vddq = 0
9190 11:05:57.804112 Vmddr = 0
9191 11:05:57.807383 switch to 3200 Mbps bootup
9192 11:05:57.807465 [DramcRunTimeConfig]
9193 11:05:57.810820 PHYPLL
9194 11:05:57.810903 DPM_CONTROL_AFTERK: ON
9195 11:05:57.813842 PER_BANK_REFRESH: ON
9196 11:05:57.817399 REFRESH_OVERHEAD_REDUCTION: ON
9197 11:05:57.817553 CMD_PICG_NEW_MODE: OFF
9198 11:05:57.820478 XRTWTW_NEW_MODE: ON
9199 11:05:57.820550 XRTRTR_NEW_MODE: ON
9200 11:05:57.824138 TX_TRACKING: ON
9201 11:05:57.824226 RDSEL_TRACKING: OFF
9202 11:05:57.827178 DQS Precalculation for DVFS: ON
9203 11:05:57.830392 RX_TRACKING: OFF
9204 11:05:57.830474 HW_GATING DBG: ON
9205 11:05:57.833777 ZQCS_ENABLE_LP4: ON
9206 11:05:57.833859 RX_PICG_NEW_MODE: ON
9207 11:05:57.837277 TX_PICG_NEW_MODE: ON
9208 11:05:57.840726 ENABLE_RX_DCM_DPHY: ON
9209 11:05:57.840808 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9210 11:05:57.843670 DUMMY_READ_FOR_TRACKING: OFF
9211 11:05:57.847300 !!! SPM_CONTROL_AFTERK: OFF
9212 11:05:57.850481 !!! SPM could not control APHY
9213 11:05:57.850565 IMPEDANCE_TRACKING: ON
9214 11:05:57.853914 TEMP_SENSOR: ON
9215 11:05:57.853997 HW_SAVE_FOR_SR: OFF
9216 11:05:57.857328 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9217 11:05:57.860744 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9218 11:05:57.863907 Read ODT Tracking: ON
9219 11:05:57.867000 Refresh Rate DeBounce: ON
9220 11:05:57.867083 DFS_NO_QUEUE_FLUSH: ON
9221 11:05:57.870626 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9222 11:05:57.873685 ENABLE_DFS_RUNTIME_MRW: OFF
9223 11:05:57.877304 DDR_RESERVE_NEW_MODE: ON
9224 11:05:57.877386 MR_CBT_SWITCH_FREQ: ON
9225 11:05:57.880295 =========================
9226 11:05:57.899530 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9227 11:05:57.902454 dram_init: ddr_geometry: 2
9228 11:05:57.920934 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9229 11:05:57.924080 dram_init: dram init end (result: 0)
9230 11:05:57.930586 DRAM-K: Full calibration passed in 24573 msecs
9231 11:05:57.934230 MRC: failed to locate region type 0.
9232 11:05:57.934313 DRAM rank0 size:0x100000000,
9233 11:05:57.937282 DRAM rank1 size=0x100000000
9234 11:05:57.947351 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9235 11:05:57.953678 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9236 11:05:57.960300 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9237 11:05:57.970234 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9238 11:05:57.970321 DRAM rank0 size:0x100000000,
9239 11:05:57.973610 DRAM rank1 size=0x100000000
9240 11:05:57.973693 CBMEM:
9241 11:05:57.976793 IMD: root @ 0xfffff000 254 entries.
9242 11:05:57.980072 IMD: root @ 0xffffec00 62 entries.
9243 11:05:57.983447 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9244 11:05:57.989961 WARNING: RO_VPD is uninitialized or empty.
9245 11:05:57.993279 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9246 11:05:58.001010 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9247 11:05:58.013489 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9248 11:05:58.024896 BS: romstage times (exec / console): total (unknown) / 24037 ms
9249 11:05:58.024982
9250 11:05:58.025065
9251 11:05:58.034928 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9252 11:05:58.038260 ARM64: Exception handlers installed.
9253 11:05:58.041617 ARM64: Testing exception
9254 11:05:58.045074 ARM64: Done test exception
9255 11:05:58.045155 Enumerating buses...
9256 11:05:58.048224 Show all devs... Before device enumeration.
9257 11:05:58.051539 Root Device: enabled 1
9258 11:05:58.054907 CPU_CLUSTER: 0: enabled 1
9259 11:05:58.054988 CPU: 00: enabled 1
9260 11:05:58.058472 Compare with tree...
9261 11:05:58.058553 Root Device: enabled 1
9262 11:05:58.061620 CPU_CLUSTER: 0: enabled 1
9263 11:05:58.065041 CPU: 00: enabled 1
9264 11:05:58.065123 Root Device scanning...
9265 11:05:58.068254 scan_static_bus for Root Device
9266 11:05:58.071437 CPU_CLUSTER: 0 enabled
9267 11:05:58.074716 scan_static_bus for Root Device done
9268 11:05:58.078020 scan_bus: bus Root Device finished in 8 msecs
9269 11:05:58.078132 done
9270 11:05:58.084744 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9271 11:05:58.088050 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9272 11:05:58.094866 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9273 11:05:58.098007 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9274 11:05:58.101398 Allocating resources...
9275 11:05:58.104601 Reading resources...
9276 11:05:58.108058 Root Device read_resources bus 0 link: 0
9277 11:05:58.108137 DRAM rank0 size:0x100000000,
9278 11:05:58.111299 DRAM rank1 size=0x100000000
9279 11:05:58.114829 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9280 11:05:58.117912 CPU: 00 missing read_resources
9281 11:05:58.121308 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9282 11:05:58.127718 Root Device read_resources bus 0 link: 0 done
9283 11:05:58.127795 Done reading resources.
9284 11:05:58.134390 Show resources in subtree (Root Device)...After reading.
9285 11:05:58.137768 Root Device child on link 0 CPU_CLUSTER: 0
9286 11:05:58.141043 CPU_CLUSTER: 0 child on link 0 CPU: 00
9287 11:05:58.151065 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9288 11:05:58.151151 CPU: 00
9289 11:05:58.154463 Root Device assign_resources, bus 0 link: 0
9290 11:05:58.157677 CPU_CLUSTER: 0 missing set_resources
9291 11:05:58.164244 Root Device assign_resources, bus 0 link: 0 done
9292 11:05:58.164329 Done setting resources.
9293 11:05:58.171101 Show resources in subtree (Root Device)...After assigning values.
9294 11:05:58.174311 Root Device child on link 0 CPU_CLUSTER: 0
9295 11:05:58.177611 CPU_CLUSTER: 0 child on link 0 CPU: 00
9296 11:05:58.187471 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9297 11:05:58.187557 CPU: 00
9298 11:05:58.190586 Done allocating resources.
9299 11:05:58.197288 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9300 11:05:58.197374 Enabling resources...
9301 11:05:58.197461 done.
9302 11:05:58.203799 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9303 11:05:58.203884 Initializing devices...
9304 11:05:58.207337 Root Device init
9305 11:05:58.207423 init hardware done!
9306 11:05:58.210422 0x00000018: ctrlr->caps
9307 11:05:58.213765 52.000 MHz: ctrlr->f_max
9308 11:05:58.213852 0.400 MHz: ctrlr->f_min
9309 11:05:58.217105 0x40ff8080: ctrlr->voltages
9310 11:05:58.220461 sclk: 390625
9311 11:05:58.220546 Bus Width = 1
9312 11:05:58.220633 sclk: 390625
9313 11:05:58.223928 Bus Width = 1
9314 11:05:58.224012 Early init status = 3
9315 11:05:58.230424 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9316 11:05:58.233633 in-header: 03 fc 00 00 01 00 00 00
9317 11:05:58.236971 in-data: 00
9318 11:05:58.240206 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9319 11:05:58.244012 in-header: 03 fd 00 00 00 00 00 00
9320 11:05:58.247272 in-data:
9321 11:05:58.250399 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9322 11:05:58.254769 in-header: 03 fc 00 00 01 00 00 00
9323 11:05:58.257957 in-data: 00
9324 11:05:58.261298 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9325 11:05:58.266799 in-header: 03 fd 00 00 00 00 00 00
9326 11:05:58.269927 in-data:
9327 11:05:58.273054 [SSUSB] Setting up USB HOST controller...
9328 11:05:58.276645 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9329 11:05:58.280025 [SSUSB] phy power-on done.
9330 11:05:58.283083 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9331 11:05:58.289681 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9332 11:05:58.292878 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9333 11:05:58.299519 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9334 11:05:58.306242 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9335 11:05:58.313034 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9336 11:05:58.319174 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9337 11:05:58.325889 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9338 11:05:58.329627 SPM: binary array size = 0x9dc
9339 11:05:58.332753 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9340 11:05:58.339345 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9341 11:05:58.346019 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9342 11:05:58.352366 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9343 11:05:58.355710 configure_display: Starting display init
9344 11:05:58.390087 anx7625_power_on_init: Init interface.
9345 11:05:58.393223 anx7625_disable_pd_protocol: Disabled PD feature.
9346 11:05:58.396396 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9347 11:05:58.424235 anx7625_start_dp_work: Secure OCM version=00
9348 11:05:58.427578 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9349 11:05:58.442362 sp_tx_get_edid_block: EDID Block = 1
9350 11:05:58.544784 Extracted contents:
9351 11:05:58.548645 header: 00 ff ff ff ff ff ff 00
9352 11:05:58.551659 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9353 11:05:58.555161 version: 01 04
9354 11:05:58.558222 basic params: 95 1f 11 78 0a
9355 11:05:58.561404 chroma info: 76 90 94 55 54 90 27 21 50 54
9356 11:05:58.564821 established: 00 00 00
9357 11:05:58.571129 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9358 11:05:58.574544 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9359 11:05:58.581204 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9360 11:05:58.587799 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9361 11:05:58.594473 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9362 11:05:58.597748 extensions: 00
9363 11:05:58.597830 checksum: fb
9364 11:05:58.597904
9365 11:05:58.600998 Manufacturer: IVO Model 57d Serial Number 0
9366 11:05:58.604277 Made week 0 of 2020
9367 11:05:58.607587 EDID version: 1.4
9368 11:05:58.607658 Digital display
9369 11:05:58.611214 6 bits per primary color channel
9370 11:05:58.611297 DisplayPort interface
9371 11:05:58.614242 Maximum image size: 31 cm x 17 cm
9372 11:05:58.617667 Gamma: 220%
9373 11:05:58.617745 Check DPMS levels
9374 11:05:58.620727 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9375 11:05:58.627680 First detailed timing is preferred timing
9376 11:05:58.627808 Established timings supported:
9377 11:05:58.631072 Standard timings supported:
9378 11:05:58.634178 Detailed timings
9379 11:05:58.637253 Hex of detail: 383680a07038204018303c0035ae10000019
9380 11:05:58.644267 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9381 11:05:58.647257 0780 0798 07c8 0820 hborder 0
9382 11:05:58.650821 0438 043b 0447 0458 vborder 0
9383 11:05:58.654156 -hsync -vsync
9384 11:05:58.654238 Did detailed timing
9385 11:05:58.660457 Hex of detail: 000000000000000000000000000000000000
9386 11:05:58.663941 Manufacturer-specified data, tag 0
9387 11:05:58.667171 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9388 11:05:58.670614 ASCII string: InfoVision
9389 11:05:58.673634 Hex of detail: 000000fe00523134304e574635205248200a
9390 11:05:58.677261 ASCII string: R140NWF5 RH
9391 11:05:58.677337 Checksum
9392 11:05:58.680398 Checksum: 0xfb (valid)
9393 11:05:58.683762 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9394 11:05:58.687136 DSI data_rate: 832800000 bps
9395 11:05:58.693834 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9396 11:05:58.697115 anx7625_parse_edid: pixelclock(138800).
9397 11:05:58.700407 hactive(1920), hsync(48), hfp(24), hbp(88)
9398 11:05:58.703798 vactive(1080), vsync(12), vfp(3), vbp(17)
9399 11:05:58.707151 anx7625_dsi_config: config dsi.
9400 11:05:58.713595 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9401 11:05:58.727049 anx7625_dsi_config: success to config DSI
9402 11:05:58.730351 anx7625_dp_start: MIPI phy setup OK.
9403 11:05:58.733439 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9404 11:05:58.736838 mtk_ddp_mode_set invalid vrefresh 60
9405 11:05:58.740409 main_disp_path_setup
9406 11:05:58.740507 ovl_layer_smi_id_en
9407 11:05:58.743460 ovl_layer_smi_id_en
9408 11:05:58.743542 ccorr_config
9409 11:05:58.743607 aal_config
9410 11:05:58.747031 gamma_config
9411 11:05:58.747113 postmask_config
9412 11:05:58.750159 dither_config
9413 11:05:58.753358 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9414 11:05:58.760147 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9415 11:05:58.763234 Root Device init finished in 553 msecs
9416 11:05:58.766463 CPU_CLUSTER: 0 init
9417 11:05:58.773145 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9418 11:05:58.779774 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9419 11:05:58.779859 APU_MBOX 0x190000b0 = 0x10001
9420 11:05:58.783357 APU_MBOX 0x190001b0 = 0x10001
9421 11:05:58.786363 APU_MBOX 0x190005b0 = 0x10001
9422 11:05:58.789714 APU_MBOX 0x190006b0 = 0x10001
9423 11:05:58.793205 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9424 11:05:58.805949 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9425 11:05:58.818352 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9426 11:05:58.824969 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9427 11:05:58.836706 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9428 11:05:58.845616 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9429 11:05:58.849044 CPU_CLUSTER: 0 init finished in 81 msecs
9430 11:05:58.852277 Devices initialized
9431 11:05:58.855744 Show all devs... After init.
9432 11:05:58.855846 Root Device: enabled 1
9433 11:05:58.858986 CPU_CLUSTER: 0: enabled 1
9434 11:05:58.862590 CPU: 00: enabled 1
9435 11:05:58.865751 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9436 11:05:58.869055 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9437 11:05:58.872429 ELOG: NV offset 0x57f000 size 0x1000
9438 11:05:58.879248 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9439 11:05:58.885548 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9440 11:05:58.889059 ELOG: Event(17) added with size 13 at 2024-03-03 11:05:59 UTC
9441 11:05:58.895299 ELOG: Event(16) added with size 11 at 2024-03-03 11:05:59 UTC
9442 11:05:58.978968 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9443 11:05:58.982305 out: cmd=0x121: 03 db 21 01 00 00 00 00
9444 11:05:58.985630 in-header: 03 01 00 00 2c 00 00 00
9445 11:05:58.998812 in-data: 5d 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9446 11:05:59.005399 ELOG: Event(A1) added with size 10 at 2024-03-03 11:05:59 UTC
9447 11:05:59.011770 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9448 11:05:59.015289 ELOG: Event(A0) added with size 9 at 2024-03-03 11:05:59 UTC
9449 11:05:59.021780 elog_add_boot_reason: Logged dev mode boot
9450 11:05:59.024984 BS: BS_POST_DEVICE entry times (exec / console): 80 / 74 ms
9451 11:05:59.028175 Finalize devices...
9452 11:05:59.028251 Devices finalized
9453 11:05:59.035212 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9454 11:05:59.038182 Writing coreboot table at 0xffe64000
9455 11:05:59.041754 0. 000000000010a000-0000000000113fff: RAMSTAGE
9456 11:05:59.044770 1. 0000000040000000-00000000400fffff: RAM
9457 11:05:59.048053 2. 0000000040100000-000000004032afff: RAMSTAGE
9458 11:05:59.054836 3. 000000004032b000-00000000545fffff: RAM
9459 11:05:59.058130 4. 0000000054600000-000000005465ffff: BL31
9460 11:05:59.061509 5. 0000000054660000-00000000ffe63fff: RAM
9461 11:05:59.064621 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9462 11:05:59.071310 7. 0000000100000000-000000023fffffff: RAM
9463 11:05:59.071392 Passing 5 GPIOs to payload:
9464 11:05:59.077874 NAME | PORT | POLARITY | VALUE
9465 11:05:59.081196 EC in RW | 0x000000aa | low | undefined
9466 11:05:59.087935 EC interrupt | 0x00000005 | low | undefined
9467 11:05:59.091044 TPM interrupt | 0x000000ab | high | undefined
9468 11:05:59.094626 SD card detect | 0x00000011 | high | undefined
9469 11:05:59.101188 speaker enable | 0x00000093 | high | undefined
9470 11:05:59.104269 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9471 11:05:59.107549 in-header: 03 f9 00 00 02 00 00 00
9472 11:05:59.110888 in-data: 02 00
9473 11:05:59.110970 ADC[4]: Raw value=894081 ID=7
9474 11:05:59.114291 ADC[3]: Raw value=212700 ID=1
9475 11:05:59.117512 RAM Code: 0x71
9476 11:05:59.117607 ADC[6]: Raw value=74722 ID=0
9477 11:05:59.120825 ADC[5]: Raw value=211960 ID=1
9478 11:05:59.124166 SKU Code: 0x1
9479 11:05:59.127312 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 18ab
9480 11:05:59.130630 coreboot table: 964 bytes.
9481 11:05:59.134242 IMD ROOT 0. 0xfffff000 0x00001000
9482 11:05:59.137309 IMD SMALL 1. 0xffffe000 0x00001000
9483 11:05:59.140839 RO MCACHE 2. 0xffffc000 0x00001104
9484 11:05:59.144148 CONSOLE 3. 0xfff7c000 0x00080000
9485 11:05:59.147473 FMAP 4. 0xfff7b000 0x00000452
9486 11:05:59.150705 TIME STAMP 5. 0xfff7a000 0x00000910
9487 11:05:59.154199 VBOOT WORK 6. 0xfff66000 0x00014000
9488 11:05:59.157320 RAMOOPS 7. 0xffe66000 0x00100000
9489 11:05:59.160727 COREBOOT 8. 0xffe64000 0x00002000
9490 11:05:59.160831 IMD small region:
9491 11:05:59.167254 IMD ROOT 0. 0xffffec00 0x00000400
9492 11:05:59.170644 VPD 1. 0xffffeb80 0x0000006c
9493 11:05:59.173845 MMC STATUS 2. 0xffffeb60 0x00000004
9494 11:05:59.177213 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9495 11:05:59.180373 Probing TPM: done!
9496 11:05:59.183768 Connected to device vid:did:rid of 1ae0:0028:00
9497 11:05:59.194045 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9498 11:05:59.197273 Initialized TPM device CR50 revision 0
9499 11:05:59.200770 Checking cr50 for pending updates
9500 11:05:59.205027 Reading cr50 TPM mode
9501 11:05:59.213581 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9502 11:05:59.220251 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9503 11:05:59.260336 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9504 11:05:59.263715 Checking segment from ROM address 0x40100000
9505 11:05:59.266753 Checking segment from ROM address 0x4010001c
9506 11:05:59.273598 Loading segment from ROM address 0x40100000
9507 11:05:59.273680 code (compression=0)
9508 11:05:59.283585 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9509 11:05:59.290353 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9510 11:05:59.290436 it's not compressed!
9511 11:05:59.296982 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9512 11:05:59.300387 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9513 11:05:59.320445 Loading segment from ROM address 0x4010001c
9514 11:05:59.320528 Entry Point 0x80000000
9515 11:05:59.324035 Loaded segments
9516 11:05:59.327358 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9517 11:05:59.333980 Jumping to boot code at 0x80000000(0xffe64000)
9518 11:05:59.340675 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9519 11:05:59.347277 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9520 11:05:59.355208 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9521 11:05:59.358442 Checking segment from ROM address 0x40100000
9522 11:05:59.361708 Checking segment from ROM address 0x4010001c
9523 11:05:59.368572 Loading segment from ROM address 0x40100000
9524 11:05:59.368661 code (compression=1)
9525 11:05:59.375042 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9526 11:05:59.385073 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9527 11:05:59.385156 using LZMA
9528 11:05:59.393389 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9529 11:05:59.400003 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9530 11:05:59.403756 Loading segment from ROM address 0x4010001c
9531 11:05:59.403839 Entry Point 0x54601000
9532 11:05:59.406658 Loaded segments
9533 11:05:59.410123 NOTICE: MT8192 bl31_setup
9534 11:05:59.417046 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9535 11:05:59.420348 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9536 11:05:59.423839 WARNING: region 0:
9537 11:05:59.427287 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9538 11:05:59.427369 WARNING: region 1:
9539 11:05:59.433661 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9540 11:05:59.436932 WARNING: region 2:
9541 11:05:59.440303 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9542 11:05:59.443742 WARNING: region 3:
9543 11:05:59.446903 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9544 11:05:59.450430 WARNING: region 4:
9545 11:05:59.457254 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9546 11:05:59.457336 WARNING: region 5:
9547 11:05:59.460195 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9548 11:05:59.463531 WARNING: region 6:
9549 11:05:59.467271 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9550 11:05:59.470207 WARNING: region 7:
9551 11:05:59.473663 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9552 11:05:59.480372 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9553 11:05:59.483831 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9554 11:05:59.486968 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9555 11:05:59.493487 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9556 11:05:59.496843 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9557 11:05:59.500360 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9558 11:05:59.507049 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9559 11:05:59.510430 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9560 11:05:59.517012 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9561 11:05:59.520092 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9562 11:05:59.523449 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9563 11:05:59.530277 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9564 11:05:59.533663 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9565 11:05:59.536745 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9566 11:05:59.543627 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9567 11:05:59.546620 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9568 11:05:59.553295 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9569 11:05:59.556850 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9570 11:05:59.560263 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9571 11:05:59.566978 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9572 11:05:59.570013 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9573 11:05:59.573569 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9574 11:05:59.580255 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9575 11:05:59.583748 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9576 11:05:59.590357 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9577 11:05:59.593800 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9578 11:05:59.596874 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9579 11:05:59.603677 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9580 11:05:59.606816 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9581 11:05:59.613597 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9582 11:05:59.617070 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9583 11:05:59.620305 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9584 11:05:59.626919 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9585 11:05:59.630156 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9586 11:05:59.633759 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9587 11:05:59.637008 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9588 11:05:59.643666 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9589 11:05:59.646938 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9590 11:05:59.650362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9591 11:05:59.653621 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9592 11:05:59.660343 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9593 11:05:59.663409 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9594 11:05:59.666776 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9595 11:05:59.670275 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9596 11:05:59.676726 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9597 11:05:59.680291 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9598 11:05:59.683486 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9599 11:05:59.686845 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9600 11:05:59.693607 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9601 11:05:59.696681 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9602 11:05:59.703379 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9603 11:05:59.706948 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9604 11:05:59.710456 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9605 11:05:59.716790 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9606 11:05:59.720255 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9607 11:05:59.726971 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9608 11:05:59.730103 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9609 11:05:59.736758 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9610 11:05:59.740144 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9611 11:05:59.746781 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9612 11:05:59.750317 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9613 11:05:59.753344 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9614 11:05:59.760321 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9615 11:05:59.763656 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9616 11:05:59.770083 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9617 11:05:59.773760 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9618 11:05:59.780074 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9619 11:05:59.783592 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9620 11:05:59.786625 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9621 11:05:59.793584 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9622 11:05:59.796731 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9623 11:05:59.803331 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9624 11:05:59.806594 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9625 11:05:59.813128 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9626 11:05:59.816701 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9627 11:05:59.820273 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9628 11:05:59.826723 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9629 11:05:59.830030 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9630 11:05:59.837005 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9631 11:05:59.840235 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9632 11:05:59.846673 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9633 11:05:59.850260 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9634 11:05:59.853375 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9635 11:05:59.860166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9636 11:05:59.863538 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9637 11:05:59.870143 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9638 11:05:59.873527 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9639 11:05:59.880040 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9640 11:05:59.883449 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9641 11:05:59.886927 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9642 11:05:59.893425 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9643 11:05:59.896935 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9644 11:05:59.903368 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9645 11:05:59.906931 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9646 11:05:59.913447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9647 11:05:59.916788 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9648 11:05:59.920123 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9649 11:05:59.926785 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9650 11:05:59.930039 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9651 11:05:59.933513 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9652 11:05:59.936705 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9653 11:05:59.943415 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9654 11:05:59.946885 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9655 11:05:59.953594 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9656 11:05:59.957001 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9657 11:05:59.960027 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9658 11:05:59.966702 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9659 11:05:59.970292 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9660 11:05:59.976640 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9661 11:05:59.979937 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9662 11:05:59.983432 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9663 11:05:59.990053 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9664 11:05:59.993459 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9665 11:06:00.000160 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9666 11:06:00.003276 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9667 11:06:00.006767 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9668 11:06:00.010415 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9669 11:06:00.016717 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9670 11:06:00.020222 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9671 11:06:00.023325 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9672 11:06:00.030026 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9673 11:06:00.033277 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9674 11:06:00.036714 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9675 11:06:00.039766 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9676 11:06:00.046686 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9677 11:06:00.050076 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9678 11:06:00.056744 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9679 11:06:00.059804 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9680 11:06:00.063322 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9681 11:06:00.069969 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9682 11:06:00.073351 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9683 11:06:00.080065 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9684 11:06:00.083237 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9685 11:06:00.086379 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9686 11:06:00.093006 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9687 11:06:00.096731 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9688 11:06:00.099741 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9689 11:06:00.106523 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9690 11:06:00.109766 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9691 11:06:00.116329 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9692 11:06:00.119912 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9693 11:06:00.123281 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9694 11:06:00.129632 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9695 11:06:00.132951 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9696 11:06:00.139629 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9697 11:06:00.142898 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9698 11:06:00.146309 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9699 11:06:00.152997 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9700 11:06:00.156113 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9701 11:06:00.163048 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9702 11:06:00.166310 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9703 11:06:00.169616 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9704 11:06:00.176390 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9705 11:06:00.179574 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9706 11:06:00.183230 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9707 11:06:00.189615 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9708 11:06:00.192903 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9709 11:06:00.199618 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9710 11:06:00.203138 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9711 11:06:00.206383 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9712 11:06:00.213092 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9713 11:06:00.216185 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9714 11:06:00.222787 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9715 11:06:00.226013 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9716 11:06:00.229445 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9717 11:06:00.236227 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9718 11:06:00.239255 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9719 11:06:00.246011 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9720 11:06:00.249100 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9721 11:06:00.252486 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9722 11:06:00.259079 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9723 11:06:00.262382 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9724 11:06:00.265888 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9725 11:06:00.272433 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9726 11:06:00.275985 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9727 11:06:00.282454 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9728 11:06:00.285763 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9729 11:06:00.292197 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9730 11:06:00.295694 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9731 11:06:00.298879 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9732 11:06:00.305400 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9733 11:06:00.308828 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9734 11:06:00.312232 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9735 11:06:00.318597 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9736 11:06:00.322336 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9737 11:06:00.328520 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9738 11:06:00.331998 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9739 11:06:00.335172 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9740 11:06:00.341843 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9741 11:06:00.344960 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9742 11:06:00.351730 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9743 11:06:00.355190 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9744 11:06:00.361941 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9745 11:06:00.365089 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9746 11:06:00.368319 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9747 11:06:00.374950 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9748 11:06:00.378394 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9749 11:06:00.384992 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9750 11:06:00.388387 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9751 11:06:00.394829 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9752 11:06:00.398378 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9753 11:06:00.401621 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9754 11:06:00.408054 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9755 11:06:00.411308 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9756 11:06:00.418000 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9757 11:06:00.421347 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9758 11:06:00.424639 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9759 11:06:00.431260 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9760 11:06:00.434607 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9761 11:06:00.441258 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9762 11:06:00.444352 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9763 11:06:00.451016 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9764 11:06:00.454403 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9765 11:06:00.457913 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9766 11:06:00.464301 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9767 11:06:00.467764 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9768 11:06:00.474200 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9769 11:06:00.477659 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9770 11:06:00.481230 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9771 11:06:00.487747 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9772 11:06:00.491170 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9773 11:06:00.497562 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9774 11:06:00.500901 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9775 11:06:00.504421 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9776 11:06:00.511236 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9777 11:06:00.514261 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9778 11:06:00.521010 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9779 11:06:00.524225 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9780 11:06:00.530880 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9781 11:06:00.534031 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9782 11:06:00.537466 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9783 11:06:00.541034 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9784 11:06:00.544304 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9785 11:06:00.550751 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9786 11:06:00.554072 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9787 11:06:00.557703 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9788 11:06:00.564285 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9789 11:06:00.567566 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9790 11:06:00.574058 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9791 11:06:00.577297 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9792 11:06:00.580869 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9793 11:06:00.587371 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9794 11:06:00.590457 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9795 11:06:00.593956 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9796 11:06:00.600469 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9797 11:06:00.603840 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9798 11:06:00.610514 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9799 11:06:00.613727 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9800 11:06:00.617273 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9801 11:06:00.623757 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9802 11:06:00.627316 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9803 11:06:00.630321 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9804 11:06:00.636947 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9805 11:06:00.640336 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9806 11:06:00.643582 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9807 11:06:00.650380 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9808 11:06:00.653533 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9809 11:06:00.660166 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9810 11:06:00.663356 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9811 11:06:00.666608 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9812 11:06:00.673307 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9813 11:06:00.676709 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9814 11:06:00.683371 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9815 11:06:00.686467 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9816 11:06:00.689913 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9817 11:06:00.696416 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9818 11:06:00.699786 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9819 11:06:00.703319 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9820 11:06:00.709601 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9821 11:06:00.712982 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9822 11:06:00.716319 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9823 11:06:00.719766 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9824 11:06:00.722967 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9825 11:06:00.729935 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9826 11:06:00.732876 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9827 11:06:00.736232 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9828 11:06:00.739710 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9829 11:06:00.746290 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9830 11:06:00.749603 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9831 11:06:00.752777 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9832 11:06:00.759478 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9833 11:06:00.762659 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9834 11:06:00.766159 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9835 11:06:00.772748 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9836 11:06:00.775978 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9837 11:06:00.782606 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9838 11:06:00.786094 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9839 11:06:00.789265 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9840 11:06:00.795797 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9841 11:06:00.799096 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9842 11:06:00.805834 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9843 11:06:00.809055 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9844 11:06:00.812484 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9845 11:06:00.819098 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9846 11:06:00.822305 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9847 11:06:00.828970 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9848 11:06:00.832347 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9849 11:06:00.835453 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9850 11:06:00.842339 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9851 11:06:00.845441 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9852 11:06:00.852215 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9853 11:06:00.855231 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9854 11:06:00.862004 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9855 11:06:00.865183 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9856 11:06:00.868632 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9857 11:06:00.875117 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9858 11:06:00.878481 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9859 11:06:00.885017 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9860 11:06:00.888338 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9861 11:06:00.894944 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9862 11:06:00.898517 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9863 11:06:00.901464 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9864 11:06:00.908327 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9865 11:06:00.911685 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9866 11:06:00.915056 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9867 11:06:00.921737 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9868 11:06:00.925095 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9869 11:06:00.931488 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9870 11:06:00.935018 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9871 11:06:00.941626 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9872 11:06:00.945025 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9873 11:06:00.948226 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9874 11:06:00.954856 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9875 11:06:00.957948 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9876 11:06:00.964844 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9877 11:06:00.968158 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9878 11:06:00.971570 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9879 11:06:00.978002 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9880 11:06:00.981265 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9881 11:06:00.988012 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9882 11:06:00.991394 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9883 11:06:00.994552 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9884 11:06:01.001372 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9885 11:06:01.004412 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9886 11:06:01.011294 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9887 11:06:01.014505 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9888 11:06:01.021030 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9889 11:06:01.024287 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9890 11:06:01.027768 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9891 11:06:01.034392 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9892 11:06:01.037757 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9893 11:06:01.044298 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9894 11:06:01.047741 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9895 11:06:01.050732 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9896 11:06:01.057421 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9897 11:06:01.060998 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9898 11:06:01.067218 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9899 11:06:01.070602 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9900 11:06:01.074089 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9901 11:06:01.080550 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9902 11:06:01.084198 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9903 11:06:01.090586 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9904 11:06:01.093867 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9905 11:06:01.097433 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9906 11:06:01.103971 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9907 11:06:01.107216 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9908 11:06:01.113535 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9909 11:06:01.116933 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9910 11:06:01.123610 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9911 11:06:01.126805 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9912 11:06:01.133517 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9913 11:06:01.136634 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9914 11:06:01.140019 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9915 11:06:01.146764 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9916 11:06:01.150249 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9917 11:06:01.156631 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9918 11:06:01.160283 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9919 11:06:01.166566 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9920 11:06:01.169794 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9921 11:06:01.176598 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9922 11:06:01.179836 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9923 11:06:01.183267 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9924 11:06:01.189684 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9925 11:06:01.193311 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9926 11:06:01.199729 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9927 11:06:01.203012 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9928 11:06:01.209627 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9929 11:06:01.213067 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9930 11:06:01.216012 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9931 11:06:01.222755 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9932 11:06:01.226357 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9933 11:06:01.232864 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9934 11:06:01.236110 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9935 11:06:01.242732 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9936 11:06:01.245865 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9937 11:06:01.252734 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9938 11:06:01.255870 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9939 11:06:01.259364 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9940 11:06:01.265991 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9941 11:06:01.269198 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9942 11:06:01.275714 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9943 11:06:01.279046 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9944 11:06:01.285605 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9945 11:06:01.288982 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9946 11:06:01.295749 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9947 11:06:01.298770 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9948 11:06:01.302252 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9949 11:06:01.308638 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9950 11:06:01.312337 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9951 11:06:01.318770 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9952 11:06:01.322049 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9953 11:06:01.328672 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9954 11:06:01.331851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9955 11:06:01.335381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9956 11:06:01.341784 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9957 11:06:01.345370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9958 11:06:01.351942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9959 11:06:01.355031 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9960 11:06:01.362079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9961 11:06:01.365415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9962 11:06:01.371937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9963 11:06:01.375245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9964 11:06:01.381840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9965 11:06:01.385355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9966 11:06:01.391866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9967 11:06:01.394982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9968 11:06:01.401511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9969 11:06:01.405115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9970 11:06:01.411745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9971 11:06:01.414741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9972 11:06:01.421399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9973 11:06:01.424680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9974 11:06:01.431407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9975 11:06:01.434978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9976 11:06:01.441352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9977 11:06:01.444821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9978 11:06:01.451501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9979 11:06:01.454621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9980 11:06:01.461462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9981 11:06:01.464590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9982 11:06:01.471236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9983 11:06:01.474374 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9984 11:06:01.481015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9985 11:06:01.484426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9986 11:06:01.487858 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9987 11:06:01.491082 INFO: [APUAPC] vio 0
9988 11:06:01.497606 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9989 11:06:01.500735 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9990 11:06:01.504333 INFO: [APUAPC] D0_APC_0: 0x400510
9991 11:06:01.507412 INFO: [APUAPC] D0_APC_1: 0x0
9992 11:06:01.510984 INFO: [APUAPC] D0_APC_2: 0x1540
9993 11:06:01.514070 INFO: [APUAPC] D0_APC_3: 0x0
9994 11:06:01.517461 INFO: [APUAPC] D1_APC_0: 0xffffffff
9995 11:06:01.521022 INFO: [APUAPC] D1_APC_1: 0xffffffff
9996 11:06:01.523987 INFO: [APUAPC] D1_APC_2: 0x3fffff
9997 11:06:01.524070 INFO: [APUAPC] D1_APC_3: 0x0
9998 11:06:01.530844 INFO: [APUAPC] D2_APC_0: 0xffffffff
9999 11:06:01.533989 INFO: [APUAPC] D2_APC_1: 0xffffffff
10000 11:06:01.537462 INFO: [APUAPC] D2_APC_2: 0x3fffff
10001 11:06:01.537583 INFO: [APUAPC] D2_APC_3: 0x0
10002 11:06:01.540519 INFO: [APUAPC] D3_APC_0: 0xffffffff
10003 11:06:01.547545 INFO: [APUAPC] D3_APC_1: 0xffffffff
10004 11:06:01.547628 INFO: [APUAPC] D3_APC_2: 0x3fffff
10005 11:06:01.550871 INFO: [APUAPC] D3_APC_3: 0x0
10006 11:06:01.554014 INFO: [APUAPC] D4_APC_0: 0xffffffff
10007 11:06:01.557185 INFO: [APUAPC] D4_APC_1: 0xffffffff
10008 11:06:01.560565 INFO: [APUAPC] D4_APC_2: 0x3fffff
10009 11:06:01.563775 INFO: [APUAPC] D4_APC_3: 0x0
10010 11:06:01.567057 INFO: [APUAPC] D5_APC_0: 0xffffffff
10011 11:06:01.570690 INFO: [APUAPC] D5_APC_1: 0xffffffff
10012 11:06:01.573806 INFO: [APUAPC] D5_APC_2: 0x3fffff
10013 11:06:01.577403 INFO: [APUAPC] D5_APC_3: 0x0
10014 11:06:01.580611 INFO: [APUAPC] D6_APC_0: 0xffffffff
10015 11:06:01.583667 INFO: [APUAPC] D6_APC_1: 0xffffffff
10016 11:06:01.587104 INFO: [APUAPC] D6_APC_2: 0x3fffff
10017 11:06:01.590200 INFO: [APUAPC] D6_APC_3: 0x0
10018 11:06:01.593667 INFO: [APUAPC] D7_APC_0: 0xffffffff
10019 11:06:01.596786 INFO: [APUAPC] D7_APC_1: 0xffffffff
10020 11:06:01.600329 INFO: [APUAPC] D7_APC_2: 0x3fffff
10021 11:06:01.603600 INFO: [APUAPC] D7_APC_3: 0x0
10022 11:06:01.606906 INFO: [APUAPC] D8_APC_0: 0xffffffff
10023 11:06:01.610330 INFO: [APUAPC] D8_APC_1: 0xffffffff
10024 11:06:01.613395 INFO: [APUAPC] D8_APC_2: 0x3fffff
10025 11:06:01.616807 INFO: [APUAPC] D8_APC_3: 0x0
10026 11:06:01.620321 INFO: [APUAPC] D9_APC_0: 0xffffffff
10027 11:06:01.623414 INFO: [APUAPC] D9_APC_1: 0xffffffff
10028 11:06:01.626600 INFO: [APUAPC] D9_APC_2: 0x3fffff
10029 11:06:01.630152 INFO: [APUAPC] D9_APC_3: 0x0
10030 11:06:01.633313 INFO: [APUAPC] D10_APC_0: 0xffffffff
10031 11:06:01.636673 INFO: [APUAPC] D10_APC_1: 0xffffffff
10032 11:06:01.639827 INFO: [APUAPC] D10_APC_2: 0x3fffff
10033 11:06:01.643225 INFO: [APUAPC] D10_APC_3: 0x0
10034 11:06:01.646494 INFO: [APUAPC] D11_APC_0: 0xffffffff
10035 11:06:01.649607 INFO: [APUAPC] D11_APC_1: 0xffffffff
10036 11:06:01.653068 INFO: [APUAPC] D11_APC_2: 0x3fffff
10037 11:06:01.656307 INFO: [APUAPC] D11_APC_3: 0x0
10038 11:06:01.659601 INFO: [APUAPC] D12_APC_0: 0xffffffff
10039 11:06:01.663122 INFO: [APUAPC] D12_APC_1: 0xffffffff
10040 11:06:01.666216 INFO: [APUAPC] D12_APC_2: 0x3fffff
10041 11:06:01.669492 INFO: [APUAPC] D12_APC_3: 0x0
10042 11:06:01.673014 INFO: [APUAPC] D13_APC_0: 0xffffffff
10043 11:06:01.676003 INFO: [APUAPC] D13_APC_1: 0xffffffff
10044 11:06:01.679637 INFO: [APUAPC] D13_APC_2: 0x3fffff
10045 11:06:01.682705 INFO: [APUAPC] D13_APC_3: 0x0
10046 11:06:01.686241 INFO: [APUAPC] D14_APC_0: 0xffffffff
10047 11:06:01.689355 INFO: [APUAPC] D14_APC_1: 0xffffffff
10048 11:06:01.692588 INFO: [APUAPC] D14_APC_2: 0x3fffff
10049 11:06:01.696272 INFO: [APUAPC] D14_APC_3: 0x0
10050 11:06:01.699229 INFO: [APUAPC] D15_APC_0: 0xffffffff
10051 11:06:01.702929 INFO: [APUAPC] D15_APC_1: 0xffffffff
10052 11:06:01.706118 INFO: [APUAPC] D15_APC_2: 0x3fffff
10053 11:06:01.709290 INFO: [APUAPC] D15_APC_3: 0x0
10054 11:06:01.712681 INFO: [APUAPC] APC_CON: 0x4
10055 11:06:01.716284 INFO: [NOCDAPC] D0_APC_0: 0x0
10056 11:06:01.719229 INFO: [NOCDAPC] D0_APC_1: 0x0
10057 11:06:01.722709 INFO: [NOCDAPC] D1_APC_0: 0x0
10058 11:06:01.726163 INFO: [NOCDAPC] D1_APC_1: 0xfff
10059 11:06:01.726250 INFO: [NOCDAPC] D2_APC_0: 0x0
10060 11:06:01.729254 INFO: [NOCDAPC] D2_APC_1: 0xfff
10061 11:06:01.732527 INFO: [NOCDAPC] D3_APC_0: 0x0
10062 11:06:01.735818 INFO: [NOCDAPC] D3_APC_1: 0xfff
10063 11:06:01.739303 INFO: [NOCDAPC] D4_APC_0: 0x0
10064 11:06:01.742621 INFO: [NOCDAPC] D4_APC_1: 0xfff
10065 11:06:01.745659 INFO: [NOCDAPC] D5_APC_0: 0x0
10066 11:06:01.748968 INFO: [NOCDAPC] D5_APC_1: 0xfff
10067 11:06:01.752513 INFO: [NOCDAPC] D6_APC_0: 0x0
10068 11:06:01.755739 INFO: [NOCDAPC] D6_APC_1: 0xfff
10069 11:06:01.758832 INFO: [NOCDAPC] D7_APC_0: 0x0
10070 11:06:01.762312 INFO: [NOCDAPC] D7_APC_1: 0xfff
10071 11:06:01.762400 INFO: [NOCDAPC] D8_APC_0: 0x0
10072 11:06:01.765708 INFO: [NOCDAPC] D8_APC_1: 0xfff
10073 11:06:01.769188 INFO: [NOCDAPC] D9_APC_0: 0x0
10074 11:06:01.772536 INFO: [NOCDAPC] D9_APC_1: 0xfff
10075 11:06:01.776402 INFO: [NOCDAPC] D10_APC_0: 0x0
10076 11:06:01.779635 INFO: [NOCDAPC] D10_APC_1: 0xfff
10077 11:06:01.783020 INFO: [NOCDAPC] D11_APC_0: 0x0
10078 11:06:01.786461 INFO: [NOCDAPC] D11_APC_1: 0xfff
10079 11:06:01.789310 INFO: [NOCDAPC] D12_APC_0: 0x0
10080 11:06:01.792745 INFO: [NOCDAPC] D12_APC_1: 0xfff
10081 11:06:01.796349 INFO: [NOCDAPC] D13_APC_0: 0x0
10082 11:06:01.799403 INFO: [NOCDAPC] D13_APC_1: 0xfff
10083 11:06:01.802635 INFO: [NOCDAPC] D14_APC_0: 0x0
10084 11:06:01.803105 INFO: [NOCDAPC] D14_APC_1: 0xfff
10085 11:06:01.806162 INFO: [NOCDAPC] D15_APC_0: 0x0
10086 11:06:01.809817 INFO: [NOCDAPC] D15_APC_1: 0xfff
10087 11:06:01.812909 INFO: [NOCDAPC] APC_CON: 0x4
10088 11:06:01.815832 INFO: [APUAPC] set_apusys_apc done
10089 11:06:01.819426 INFO: [DEVAPC] devapc_init done
10090 11:06:01.822802 INFO: GICv3 without legacy support detected.
10091 11:06:01.829327 INFO: ARM GICv3 driver initialized in EL3
10092 11:06:01.832641 INFO: Maximum SPI INTID supported: 639
10093 11:06:01.835734 INFO: BL31: Initializing runtime services
10094 11:06:01.842523 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10095 11:06:01.845794 INFO: SPM: enable CPC mode
10096 11:06:01.849158 INFO: mcdi ready for mcusys-off-idle and system suspend
10097 11:06:01.856178 INFO: BL31: Preparing for EL3 exit to normal world
10098 11:06:01.858880 INFO: Entry point address = 0x80000000
10099 11:06:01.859349 INFO: SPSR = 0x8
10100 11:06:01.865665
10101 11:06:01.866227
10102 11:06:01.866594
10103 11:06:01.868794 Starting depthcharge on Spherion...
10104 11:06:01.869260
10105 11:06:01.869681 Wipe memory regions:
10106 11:06:01.870080
10107 11:06:01.872995 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10108 11:06:01.873584 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10109 11:06:01.874066 Setting prompt string to ['asurada:']
10110 11:06:01.874528 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10111 11:06:01.875239 [0x00000040000000, 0x00000054600000)
10112 11:06:01.994491
10113 11:06:01.995140 [0x00000054660000, 0x00000080000000)
10114 11:06:02.255241
10115 11:06:02.255809 [0x000000821a7280, 0x000000ffe64000)
10116 11:06:02.998629
10117 11:06:02.999188 [0x00000100000000, 0x00000240000000)
10118 11:06:04.888682
10119 11:06:04.892130 Initializing XHCI USB controller at 0x11200000.
10120 11:06:05.929774
10121 11:06:05.932793 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10122 11:06:05.932872
10123 11:06:05.932935
10124 11:06:05.933033
10125 11:06:05.933349 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10127 11:06:06.033775 asurada: tftpboot 192.168.201.1 12925624/tftp-deploy-7i8qwhg8/kernel/image.itb 12925624/tftp-deploy-7i8qwhg8/kernel/cmdline
10128 11:06:06.033929 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10129 11:06:06.034011 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10130 11:06:06.038162 tftpboot 192.168.201.1 12925624/tftp-deploy-7i8qwhg8/kernel/image.ittp-deploy-7i8qwhg8/kernel/cmdline
10131 11:06:06.038247
10132 11:06:06.038312 Waiting for link
10133 11:06:06.198274
10134 11:06:06.198416 R8152: Initializing
10135 11:06:06.198487
10136 11:06:06.201646 Version 6 (ocp_data = 5c30)
10137 11:06:06.201768
10138 11:06:06.204877 R8152: Done initializing
10139 11:06:06.204989
10140 11:06:06.205083 Adding net device
10141 11:06:08.109341
10142 11:06:08.109904 done.
10143 11:06:08.110244
10144 11:06:08.110557 MAC: 00:24:32:30:78:ff
10145 11:06:08.110858
10146 11:06:08.112500 Sending DHCP discover... done.
10147 11:06:08.112964
10148 11:06:13.927197 Waiting for reply... done.
10149 11:06:13.927865
10150 11:06:13.928220 Sending DHCP request... done.
10151 11:06:13.930386
10152 11:06:13.930808 Waiting for reply... done.
10153 11:06:13.931148
10154 11:06:13.933865 My ip is 192.168.201.21
10155 11:06:13.934288
10156 11:06:13.937079 The DHCP server ip is 192.168.201.1
10157 11:06:13.937528
10158 11:06:13.940300 TFTP server IP predefined by user: 192.168.201.1
10159 11:06:13.940722
10160 11:06:13.947133 Bootfile predefined by user: 12925624/tftp-deploy-7i8qwhg8/kernel/image.itb
10161 11:06:13.947559
10162 11:06:13.950597 Sending tftp read request... done.
10163 11:06:13.951023
10164 11:06:13.958912 Waiting for the transfer...
10165 11:06:13.959473
10166 11:06:14.699548 00000000 ################################################################
10167 11:06:14.700090
10168 11:06:15.446039 00080000 ################################################################
10169 11:06:15.446580
10170 11:06:16.185254 00100000 ################################################################
10171 11:06:16.185910
10172 11:06:16.923907 00180000 ################################################################
10173 11:06:16.924453
10174 11:06:17.666880 00200000 ################################################################
10175 11:06:17.667436
10176 11:06:18.402767 00280000 ################################################################
10177 11:06:18.403318
10178 11:06:19.147762 00300000 ################################################################
10179 11:06:19.148295
10180 11:06:19.885309 00380000 ################################################################
10181 11:06:19.885855
10182 11:06:20.615618 00400000 ################################################################
10183 11:06:20.616144
10184 11:06:21.313861 00480000 ################################################################
10185 11:06:21.314405
10186 11:06:21.959577 00500000 ################################################################
10187 11:06:21.959717
10188 11:06:22.552566 00580000 ################################################################
10189 11:06:22.552729
10190 11:06:23.182515 00600000 ################################################################
10191 11:06:23.183026
10192 11:06:23.912073 00680000 ################################################################
10193 11:06:23.912601
10194 11:06:24.551933 00700000 ################################################################
10195 11:06:24.552067
10196 11:06:25.219226 00780000 ################################################################
10197 11:06:25.219387
10198 11:06:25.808182 00800000 ################################################################
10199 11:06:25.808436
10200 11:06:26.527705 00880000 ################################################################
10201 11:06:26.528253
10202 11:06:27.233193 00900000 ################################################################
10203 11:06:27.233351
10204 11:06:27.916663 00980000 ################################################################
10205 11:06:27.917315
10206 11:06:28.622670 00a00000 ################################################################
10207 11:06:28.623172
10208 11:06:29.330054 00a80000 ################################################################
10209 11:06:29.330597
10210 11:06:30.067049 00b00000 ################################################################
10211 11:06:30.067625
10212 11:06:30.773808 00b80000 ################################################################
10213 11:06:30.773954
10214 11:06:31.475734 00c00000 ################################################################
10215 11:06:31.476240
10216 11:06:32.197622 00c80000 ################################################################
10217 11:06:32.198134
10218 11:06:32.934027 00d00000 ################################################################
10219 11:06:32.934545
10220 11:06:33.682333 00d80000 ################################################################
10221 11:06:33.682851
10222 11:06:34.421992 00e00000 ################################################################
10223 11:06:34.422527
10224 11:06:35.162648 00e80000 ################################################################
10225 11:06:35.163177
10226 11:06:35.874592 00f00000 ################################################################
10227 11:06:35.875141
10228 11:06:36.623888 00f80000 ################################################################
10229 11:06:36.624441
10230 11:06:37.366624 01000000 ################################################################
10231 11:06:37.367141
10232 11:06:38.116855 01080000 ################################################################
10233 11:06:38.117399
10234 11:06:38.863137 01100000 ################################################################
10235 11:06:38.863676
10236 11:06:39.614558 01180000 ################################################################
10237 11:06:39.615129
10238 11:06:40.373223 01200000 ################################################################
10239 11:06:40.373878
10240 11:06:41.136047 01280000 ################################################################
10241 11:06:41.136751
10242 11:06:41.884220 01300000 ################################################################
10243 11:06:41.884753
10244 11:06:42.616464 01380000 ################################################################
10245 11:06:42.616995
10246 11:06:43.361049 01400000 ################################################################
10247 11:06:43.361670
10248 11:06:44.116131 01480000 ################################################################
10249 11:06:44.116684
10250 11:06:44.869670 01500000 ################################################################
10251 11:06:44.870201
10252 11:06:45.607075 01580000 ################################################################
10253 11:06:45.607614
10254 11:06:46.361686 01600000 ################################################################
10255 11:06:46.362226
10256 11:06:47.105547 01680000 ################################################################
10257 11:06:47.106078
10258 11:06:47.811121 01700000 ################################################################
10259 11:06:47.811282
10260 11:06:48.487549 01780000 ################################################################
10261 11:06:48.488074
10262 11:06:49.231847 01800000 ################################################################
10263 11:06:49.232397
10264 11:06:49.797781 01880000 ################################################################
10265 11:06:49.797933
10266 11:06:50.377820 01900000 ################################################################
10267 11:06:50.377973
10268 11:06:50.958807 01980000 ################################################################
10269 11:06:50.958958
10270 11:06:51.535679 01a00000 ################################################################
10271 11:06:51.535839
10272 11:06:52.094064 01a80000 ################################################################
10273 11:06:52.094211
10274 11:06:52.660948 01b00000 ################################################################
10275 11:06:52.661096
10276 11:06:53.232609 01b80000 ################################################################
10277 11:06:53.232761
10278 11:06:53.818006 01c00000 ################################################################
10279 11:06:53.818157
10280 11:06:53.850302 01c80000 #### done.
10281 11:06:53.850415
10282 11:06:53.853602 The bootfile was 29912950 bytes long.
10283 11:06:53.853689
10284 11:06:53.856773 Sending tftp read request... done.
10285 11:06:53.856855
10286 11:06:53.856920 Waiting for the transfer...
10287 11:06:53.856980
10288 11:06:53.859966 00000000 # done.
10289 11:06:53.860050
10290 11:06:53.866971 Command line loaded dynamically from TFTP file: 12925624/tftp-deploy-7i8qwhg8/kernel/cmdline
10291 11:06:53.867061
10292 11:06:53.889800 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12925624/extract-nfsrootfs-beawcsqf,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10293 11:06:53.889901
10294 11:06:53.889967 Loading FIT.
10295 11:06:53.890028
10296 11:06:53.893276 Image ramdisk-1 has 17805938 bytes.
10297 11:06:53.893358
10298 11:06:53.896627 Image fdt-1 has 47278 bytes.
10299 11:06:53.896708
10300 11:06:53.899600 Image kernel-1 has 12057697 bytes.
10301 11:06:53.899680
10302 11:06:53.909636 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10303 11:06:53.909718
10304 11:06:53.926127 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10305 11:06:53.926216
10306 11:06:53.932783 Choosing best match conf-1 for compat google,spherion-rev2.
10307 11:06:53.932865
10308 11:06:53.940398 Connected to device vid:did:rid of 1ae0:0028:00
10309 11:06:53.948573
10310 11:06:53.952002 tpm_get_response: command 0x17b, return code 0x0
10311 11:06:53.952085
10312 11:06:53.955198 ec_init: CrosEC protocol v3 supported (256, 248)
10313 11:06:53.959337
10314 11:06:53.962704 tpm_cleanup: add release locality here.
10315 11:06:53.962785
10316 11:06:53.962851 Shutting down all USB controllers.
10317 11:06:53.965743
10318 11:06:53.965824 Removing current net device
10319 11:06:53.965888
10320 11:06:53.972397 Exiting depthcharge with code 4 at timestamp: 81506517
10321 11:06:53.972480
10322 11:06:53.975792 LZMA decompressing kernel-1 to 0x821a6718
10323 11:06:53.975874
10324 11:06:53.979071 LZMA decompressing kernel-1 to 0x40000000
10325 11:06:55.478933
10326 11:06:55.479083 jumping to kernel
10327 11:06:55.479544 end: 2.2.4 bootloader-commands (duration 00:00:54) [common]
10328 11:06:55.479643 start: 2.2.5 auto-login-action (timeout 00:03:32) [common]
10329 11:06:55.479733 Setting prompt string to ['Linux version [0-9]']
10330 11:06:55.479798 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10331 11:06:55.479864 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10332 11:06:55.560926
10333 11:06:55.564154 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10334 11:06:55.567655 start: 2.2.5.1 login-action (timeout 00:03:31) [common]
10335 11:06:55.567750 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10336 11:06:55.567821 Setting prompt string to []
10337 11:06:55.567910 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10338 11:06:55.568015 Using line separator: #'\n'#
10339 11:06:55.568104 No login prompt set.
10340 11:06:55.568178 Parsing kernel messages
10341 11:06:55.568231 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10342 11:06:55.568331 [login-action] Waiting for messages, (timeout 00:03:31)
10343 11:06:55.568407 Waiting using forced prompt support (timeout 00:01:46)
10344 11:06:55.587186 [ 0.000000] Linux version 6.1.80-cip16 (KernelCI@build-j128891-arm64-gcc-10-defconfig-arm64-chromebook-nrg4h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024
10345 11:06:55.590511 [ 0.000000] random: crng init done
10346 11:06:55.597423 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10347 11:06:55.600658 [ 0.000000] efi: UEFI not found.
10348 11:06:55.607161 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10349 11:06:55.613854 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10350 11:06:55.623790 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10351 11:06:55.633487 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10352 11:06:55.640167 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10353 11:06:55.646718 [ 0.000000] printk: bootconsole [mtk8250] enabled
10354 11:06:55.653401 [ 0.000000] NUMA: No NUMA configuration found
10355 11:06:55.659948 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10356 11:06:55.663196 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10357 11:06:55.666543 [ 0.000000] Zone ranges:
10358 11:06:55.672980 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10359 11:06:55.676522 [ 0.000000] DMA32 empty
10360 11:06:55.683049 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10361 11:06:55.686224 [ 0.000000] Movable zone start for each node
10362 11:06:55.689587 [ 0.000000] Early memory node ranges
10363 11:06:55.696388 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10364 11:06:55.702755 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10365 11:06:55.709599 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10366 11:06:55.716041 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10367 11:06:55.722596 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10368 11:06:55.729082 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10369 11:06:55.785527 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10370 11:06:55.792313 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10371 11:06:55.798933 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10372 11:06:55.801985 [ 0.000000] psci: probing for conduit method from DT.
10373 11:06:55.808981 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10374 11:06:55.811866 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10375 11:06:55.818662 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10376 11:06:55.822154 [ 0.000000] psci: SMC Calling Convention v1.2
10377 11:06:55.828491 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10378 11:06:55.831871 [ 0.000000] Detected VIPT I-cache on CPU0
10379 11:06:55.838592 [ 0.000000] CPU features: detected: GIC system register CPU interface
10380 11:06:55.845214 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10381 11:06:55.851696 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10382 11:06:55.858407 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10383 11:06:55.865145 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10384 11:06:55.874928 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10385 11:06:55.878139 [ 0.000000] alternatives: applying boot alternatives
10386 11:06:55.884912 [ 0.000000] Fallback order for Node 0: 0
10387 11:06:55.891270 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10388 11:06:55.894848 [ 0.000000] Policy zone: Normal
10389 11:06:55.917644 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12925624/extract-nfsrootfs-beawcsqf,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10390 11:06:55.927548 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10391 11:06:55.937382 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10392 11:06:55.947699 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10393 11:06:55.954188 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10394 11:06:55.957291 <6>[ 0.000000] software IO TLB: area num 8.
10395 11:06:56.013808 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10396 11:06:56.163047 <6>[ 0.000000] Memory: 7949804K/8385536K available (18048K kernel code, 4118K rwdata, 19616K rodata, 8448K init, 616K bss, 402964K reserved, 32768K cma-reserved)
10397 11:06:56.169488 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10398 11:06:56.176321 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10399 11:06:56.179536 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10400 11:06:56.186121 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10401 11:06:56.192909 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10402 11:06:56.196418 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10403 11:06:56.206184 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10404 11:06:56.212704 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10405 11:06:56.219270 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10406 11:06:56.226318 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10407 11:06:56.229067 <6>[ 0.000000] GICv3: 608 SPIs implemented
10408 11:06:56.232535 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10409 11:06:56.239145 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10410 11:06:56.242476 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10411 11:06:56.248868 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10412 11:06:56.262131 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10413 11:06:56.275170 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10414 11:06:56.281758 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10415 11:06:56.289736 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10416 11:06:56.302780 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10417 11:06:56.309434 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10418 11:06:56.316179 <6>[ 0.009183] Console: colour dummy device 80x25
10419 11:06:56.326242 <6>[ 0.013940] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10420 11:06:56.332653 <6>[ 0.024383] pid_max: default: 32768 minimum: 301
10421 11:06:56.335932 <6>[ 0.029248] LSM: Security Framework initializing
10422 11:06:56.342568 <6>[ 0.034218] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10423 11:06:56.352604 <6>[ 0.042080] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10424 11:06:56.362572 <6>[ 0.051496] cblist_init_generic: Setting adjustable number of callback queues.
10425 11:06:56.365932 <6>[ 0.058939] cblist_init_generic: Setting shift to 3 and lim to 1.
10426 11:06:56.375721 <6>[ 0.065279] cblist_init_generic: Setting adjustable number of callback queues.
10427 11:06:56.382209 <6>[ 0.072706] cblist_init_generic: Setting shift to 3 and lim to 1.
10428 11:06:56.385422 <6>[ 0.079145] rcu: Hierarchical SRCU implementation.
10429 11:06:56.392436 <6>[ 0.084161] rcu: Max phase no-delay instances is 1000.
10430 11:06:56.398979 <6>[ 0.091186] EFI services will not be available.
10431 11:06:56.402238 <6>[ 0.096127] smp: Bringing up secondary CPUs ...
10432 11:06:56.410417 <6>[ 0.101182] Detected VIPT I-cache on CPU1
10433 11:06:56.417254 <6>[ 0.101250] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10434 11:06:56.424008 <6>[ 0.101283] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10435 11:06:56.427289 <6>[ 0.101617] Detected VIPT I-cache on CPU2
10436 11:06:56.433585 <6>[ 0.101666] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10437 11:06:56.440509 <6>[ 0.101682] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10438 11:06:56.447184 <6>[ 0.101940] Detected VIPT I-cache on CPU3
10439 11:06:56.453900 <6>[ 0.101985] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10440 11:06:56.460475 <6>[ 0.101998] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10441 11:06:56.463683 <6>[ 0.102306] CPU features: detected: Spectre-v4
10442 11:06:56.470163 <6>[ 0.102312] CPU features: detected: Spectre-BHB
10443 11:06:56.473441 <6>[ 0.102317] Detected PIPT I-cache on CPU4
10444 11:06:56.480099 <6>[ 0.102374] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10445 11:06:56.486588 <6>[ 0.102391] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10446 11:06:56.493342 <6>[ 0.102685] Detected PIPT I-cache on CPU5
10447 11:06:56.500082 <6>[ 0.102748] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10448 11:06:56.506586 <6>[ 0.102764] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10449 11:06:56.509796 <6>[ 0.103048] Detected PIPT I-cache on CPU6
10450 11:06:56.516356 <6>[ 0.103115] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10451 11:06:56.523095 <6>[ 0.103131] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10452 11:06:56.529740 <6>[ 0.103432] Detected PIPT I-cache on CPU7
10453 11:06:56.536461 <6>[ 0.103497] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10454 11:06:56.542879 <6>[ 0.103513] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10455 11:06:56.546273 <6>[ 0.103561] smp: Brought up 1 node, 8 CPUs
10456 11:06:56.552894 <6>[ 0.244871] SMP: Total of 8 processors activated.
10457 11:06:56.556378 <6>[ 0.249792] CPU features: detected: 32-bit EL0 Support
10458 11:06:56.565967 <6>[ 0.255155] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10459 11:06:56.572603 <6>[ 0.263955] CPU features: detected: Common not Private translations
10460 11:06:56.579348 <6>[ 0.270431] CPU features: detected: CRC32 instructions
10461 11:06:56.582554 <6>[ 0.275782] CPU features: detected: RCpc load-acquire (LDAPR)
10462 11:06:56.589116 <6>[ 0.281743] CPU features: detected: LSE atomic instructions
10463 11:06:56.595804 <6>[ 0.287560] CPU features: detected: Privileged Access Never
10464 11:06:56.602479 <6>[ 0.293339] CPU features: detected: RAS Extension Support
10465 11:06:56.609049 <6>[ 0.298982] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10466 11:06:56.612116 <6>[ 0.306245] CPU: All CPU(s) started at EL2
10467 11:06:56.618548 <6>[ 0.310589] alternatives: applying system-wide alternatives
10468 11:06:56.628012 <6>[ 0.321391] devtmpfs: initialized
10469 11:06:56.644113 <6>[ 0.330491] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10470 11:06:56.650590 <6>[ 0.340456] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10471 11:06:56.657331 <6>[ 0.348214] pinctrl core: initialized pinctrl subsystem
10472 11:06:56.660330 <6>[ 0.354894] DMI not present or invalid.
10473 11:06:56.666981 <6>[ 0.359312] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10474 11:06:56.676760 <6>[ 0.366179] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10475 11:06:56.683358 <6>[ 0.373774] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10476 11:06:56.693188 <6>[ 0.381994] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10477 11:06:56.696578 <6>[ 0.390236] audit: initializing netlink subsys (disabled)
10478 11:06:56.706429 <5>[ 0.395929] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10479 11:06:56.713223 <6>[ 0.396652] thermal_sys: Registered thermal governor 'step_wise'
10480 11:06:56.719813 <6>[ 0.403897] thermal_sys: Registered thermal governor 'power_allocator'
10481 11:06:56.723093 <6>[ 0.410156] cpuidle: using governor menu
10482 11:06:56.729722 <6>[ 0.421116] NET: Registered PF_QIPCRTR protocol family
10483 11:06:56.736468 <6>[ 0.426599] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10484 11:06:56.739745 <6>[ 0.433706] ASID allocator initialised with 32768 entries
10485 11:06:56.747121 <6>[ 0.440288] Serial: AMBA PL011 UART driver
10486 11:06:56.755786 <4>[ 0.449071] Trying to register duplicate clock ID: 134
10487 11:06:56.810384 <6>[ 0.506811] KASLR enabled
10488 11:06:56.824925 <6>[ 0.514581] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10489 11:06:56.831536 <6>[ 0.521598] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10490 11:06:56.837896 <6>[ 0.528089] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10491 11:06:56.844902 <6>[ 0.535093] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10492 11:06:56.851342 <6>[ 0.541578] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10493 11:06:56.857957 <6>[ 0.548582] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10494 11:06:56.864405 <6>[ 0.555069] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10495 11:06:56.871120 <6>[ 0.562074] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10496 11:06:56.874404 <6>[ 0.569604] ACPI: Interpreter disabled.
10497 11:06:56.882779 <6>[ 0.576023] iommu: Default domain type: Translated
10498 11:06:56.889358 <6>[ 0.581138] iommu: DMA domain TLB invalidation policy: strict mode
10499 11:06:56.892742 <5>[ 0.587799] SCSI subsystem initialized
10500 11:06:56.899201 <6>[ 0.591967] usbcore: registered new interface driver usbfs
10501 11:06:56.906087 <6>[ 0.597697] usbcore: registered new interface driver hub
10502 11:06:56.909507 <6>[ 0.603250] usbcore: registered new device driver usb
10503 11:06:56.916100 <6>[ 0.609347] pps_core: LinuxPPS API ver. 1 registered
10504 11:06:56.925970 <6>[ 0.614539] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10505 11:06:56.929705 <6>[ 0.623887] PTP clock support registered
10506 11:06:56.932589 <6>[ 0.628128] EDAC MC: Ver: 3.0.0
10507 11:06:56.940160 <6>[ 0.633254] FPGA manager framework
10508 11:06:56.946683 <6>[ 0.636934] Advanced Linux Sound Architecture Driver Initialized.
10509 11:06:56.950034 <6>[ 0.643709] vgaarb: loaded
10510 11:06:56.953467 <6>[ 0.646875] clocksource: Switched to clocksource arch_sys_counter
10511 11:06:56.960311 <5>[ 0.653311] VFS: Disk quotas dquot_6.6.0
10512 11:06:56.966781 <6>[ 0.657496] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10513 11:06:56.970234 <6>[ 0.664686] pnp: PnP ACPI: disabled
10514 11:06:56.978013 <6>[ 0.671354] NET: Registered PF_INET protocol family
10515 11:06:56.988157 <6>[ 0.676945] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10516 11:06:56.999294 <6>[ 0.689254] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10517 11:06:57.009262 <6>[ 0.698071] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10518 11:06:57.015993 <6>[ 0.706040] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10519 11:06:57.026010 <6>[ 0.714740] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10520 11:06:57.032556 <6>[ 0.724484] TCP: Hash tables configured (established 65536 bind 65536)
10521 11:06:57.039066 <6>[ 0.731351] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10522 11:06:57.048881 <6>[ 0.738549] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10523 11:06:57.055390 <6>[ 0.746248] NET: Registered PF_UNIX/PF_LOCAL protocol family
10524 11:06:57.058867 <6>[ 0.752421] RPC: Registered named UNIX socket transport module.
10525 11:06:57.065501 <6>[ 0.758574] RPC: Registered udp transport module.
10526 11:06:57.068813 <6>[ 0.763506] RPC: Registered tcp transport module.
10527 11:06:57.075209 <6>[ 0.768439] RPC: Registered tcp NFSv4.1 backchannel transport module.
10528 11:06:57.081908 <6>[ 0.775106] PCI: CLS 0 bytes, default 64
10529 11:06:57.085166 <6>[ 0.779513] Unpacking initramfs...
10530 11:06:57.109123 <6>[ 0.798982] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10531 11:06:57.119224 <6>[ 0.807663] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10532 11:06:57.122284 <6>[ 0.816526] kvm [1]: IPA Size Limit: 40 bits
10533 11:06:57.128959 <6>[ 0.821056] kvm [1]: GICv3: no GICV resource entry
10534 11:06:57.132369 <6>[ 0.826075] kvm [1]: disabling GICv2 emulation
10535 11:06:57.139310 <6>[ 0.830763] kvm [1]: GIC system register CPU interface enabled
10536 11:06:57.142201 <6>[ 0.836922] kvm [1]: vgic interrupt IRQ18
10537 11:06:57.148734 <6>[ 0.841277] kvm [1]: VHE mode initialized successfully
10538 11:06:57.155436 <5>[ 0.847797] Initialise system trusted keyrings
10539 11:06:57.162161 <6>[ 0.852658] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10540 11:06:57.169871 <6>[ 0.862808] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10541 11:06:57.176163 <5>[ 0.869230] NFS: Registering the id_resolver key type
10542 11:06:57.179558 <5>[ 0.874537] Key type id_resolver registered
10543 11:06:57.186230 <5>[ 0.878951] Key type id_legacy registered
10544 11:06:57.192788 <6>[ 0.883235] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10545 11:06:57.199554 <6>[ 0.890157] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10546 11:06:57.206102 <6>[ 0.897888] 9p: Installing v9fs 9p2000 file system support
10547 11:06:57.242631 <5>[ 0.935757] Key type asymmetric registered
10548 11:06:57.245994 <5>[ 0.940092] Asymmetric key parser 'x509' registered
10549 11:06:57.255850 <6>[ 0.945238] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10550 11:06:57.259036 <6>[ 0.952855] io scheduler mq-deadline registered
10551 11:06:57.262639 <6>[ 0.957635] io scheduler kyber registered
10552 11:06:57.281394 <6>[ 0.974652] EINJ: ACPI disabled.
10553 11:06:57.313732 <4>[ 1.000331] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10554 11:06:57.323640 <4>[ 1.010958] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10555 11:06:57.338440 <6>[ 1.031783] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10556 11:06:57.346439 <6>[ 1.039872] printk: console [ttyS0] disabled
10557 11:06:57.374435 <6>[ 1.064500] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10558 11:06:57.381198 <6>[ 1.073974] printk: console [ttyS0] enabled
10559 11:06:57.384754 <6>[ 1.073974] printk: console [ttyS0] enabled
10560 11:06:57.391103 <6>[ 1.082867] printk: bootconsole [mtk8250] disabled
10561 11:06:57.394307 <6>[ 1.082867] printk: bootconsole [mtk8250] disabled
10562 11:06:57.400971 <6>[ 1.094172] SuperH (H)SCI(F) driver initialized
10563 11:06:57.404197 <6>[ 1.099466] msm_serial: driver initialized
10564 11:06:57.418633 <6>[ 1.108495] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10565 11:06:57.428441 <6>[ 1.117045] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10566 11:06:57.435302 <6>[ 1.125587] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10567 11:06:57.445403 <6>[ 1.134217] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10568 11:06:57.451988 <6>[ 1.142924] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10569 11:06:57.462051 <6>[ 1.151646] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10570 11:06:57.471759 <6>[ 1.160188] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10571 11:06:57.478277 <6>[ 1.168979] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10572 11:06:57.488314 <6>[ 1.177523] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10573 11:06:57.500348 <6>[ 1.193476] loop: module loaded
10574 11:06:57.506732 <6>[ 1.199481] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10575 11:06:57.529826 <4>[ 1.222906] mtk-pmic-keys: Failed to locate of_node [id: -1]
10576 11:06:57.536583 <6>[ 1.229902] megasas: 07.719.03.00-rc1
10577 11:06:57.546365 <6>[ 1.239457] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10578 11:06:57.553105 <6>[ 1.246260] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10579 11:06:57.569603 <6>[ 1.262888] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10580 11:06:57.626449 <6>[ 1.312896] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10581 11:06:57.825794 <6>[ 1.518984] Freeing initrd memory: 17384K
10582 11:06:57.836090 <6>[ 1.529234] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10583 11:06:57.846893 <6>[ 1.540161] tun: Universal TUN/TAP device driver, 1.6
10584 11:06:57.850208 <6>[ 1.546223] thunder_xcv, ver 1.0
10585 11:06:57.853472 <6>[ 1.549729] thunder_bgx, ver 1.0
10586 11:06:57.856729 <6>[ 1.553225] nicpf, ver 1.0
10587 11:06:57.867194 <6>[ 1.557233] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10588 11:06:57.870788 <6>[ 1.564708] hns3: Copyright (c) 2017 Huawei Corporation.
10589 11:06:57.877290 <6>[ 1.570295] hclge is initializing
10590 11:06:57.880695 <6>[ 1.573875] e1000: Intel(R) PRO/1000 Network Driver
10591 11:06:57.887410 <6>[ 1.579004] e1000: Copyright (c) 1999-2006 Intel Corporation.
10592 11:06:57.890602 <6>[ 1.585016] e1000e: Intel(R) PRO/1000 Network Driver
10593 11:06:57.897246 <6>[ 1.590232] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10594 11:06:57.903842 <6>[ 1.596419] igb: Intel(R) Gigabit Ethernet Network Driver
10595 11:06:57.910319 <6>[ 1.602069] igb: Copyright (c) 2007-2014 Intel Corporation.
10596 11:06:57.917285 <6>[ 1.607905] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10597 11:06:57.923764 <6>[ 1.614423] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10598 11:06:57.927089 <6>[ 1.620884] sky2: driver version 1.30
10599 11:06:57.933674 <6>[ 1.625873] VFIO - User Level meta-driver version: 0.3
10600 11:06:57.940792 <6>[ 1.634106] usbcore: registered new interface driver usb-storage
10601 11:06:57.947816 <6>[ 1.640551] usbcore: registered new device driver onboard-usb-hub
10602 11:06:57.956575 <6>[ 1.649709] mt6397-rtc mt6359-rtc: registered as rtc0
10603 11:06:57.966418 <6>[ 1.655172] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T11:06:58 UTC (1709464018)
10604 11:06:57.969711 <6>[ 1.664730] i2c_dev: i2c /dev entries driver
10605 11:06:57.986549 <6>[ 1.676467] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10606 11:06:58.006369 <6>[ 1.699448] cpu cpu0: EM: created perf domain
10607 11:06:58.009801 <6>[ 1.704389] cpu cpu4: EM: created perf domain
10608 11:06:58.016859 <6>[ 1.709952] sdhci: Secure Digital Host Controller Interface driver
10609 11:06:58.023336 <6>[ 1.716385] sdhci: Copyright(c) Pierre Ossman
10610 11:06:58.030102 <6>[ 1.721341] Synopsys Designware Multimedia Card Interface Driver
10611 11:06:58.036550 <6>[ 1.727978] sdhci-pltfm: SDHCI platform and OF driver helper
10612 11:06:58.040178 <6>[ 1.728026] mmc0: CQHCI version 5.10
10613 11:06:58.046752 <6>[ 1.738264] ledtrig-cpu: registered to indicate activity on CPUs
10614 11:06:58.053371 <6>[ 1.745329] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10615 11:06:58.059906 <6>[ 1.752386] usbcore: registered new interface driver usbhid
10616 11:06:58.063451 <6>[ 1.758210] usbhid: USB HID core driver
10617 11:06:58.069794 <6>[ 1.762405] spi_master spi0: will run message pump with realtime priority
10618 11:06:58.113769 <6>[ 1.800554] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10619 11:06:58.133361 <6>[ 1.816599] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10620 11:06:58.136722 <6>[ 1.830399] mmc0: Command Queue Engine enabled
10621 11:06:58.143606 <6>[ 1.835201] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10622 11:06:58.150255 <6>[ 1.842540] mmcblk0: mmc0:0001 DA4128 116 GiB
10623 11:06:58.153371 <6>[ 1.847366] cros-ec-spi spi0.0: Chrome EC device registered
10624 11:06:58.160142 <6>[ 1.851184] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10625 11:06:58.167144 <6>[ 1.860270] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10626 11:06:58.173486 <6>[ 1.866245] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10627 11:06:58.180328 <6>[ 1.872358] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10628 11:06:58.197958 <6>[ 1.887870] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10629 11:06:58.205328 <6>[ 1.898538] NET: Registered PF_PACKET protocol family
10630 11:06:58.212100 <6>[ 1.903961] 9pnet: Installing 9P2000 support
10631 11:06:58.215143 <5>[ 1.908530] Key type dns_resolver registered
10632 11:06:58.218660 <6>[ 1.913559] registered taskstats version 1
10633 11:06:58.225096 <5>[ 1.917946] Loading compiled-in X.509 certificates
10634 11:06:58.256627 <4>[ 1.943208] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10635 11:06:58.266648 <4>[ 1.953888] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10636 11:06:58.273361 <3>[ 1.964417] debugfs: File 'uA_load' in directory '/' already present!
10637 11:06:58.279990 <3>[ 1.971117] debugfs: File 'min_uV' in directory '/' already present!
10638 11:06:58.286377 <3>[ 1.977724] debugfs: File 'max_uV' in directory '/' already present!
10639 11:06:58.293116 <3>[ 1.984330] debugfs: File 'constraint_flags' in directory '/' already present!
10640 11:06:58.304055 <3>[ 1.993876] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10641 11:06:58.313617 <6>[ 2.006889] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10642 11:06:58.320482 <6>[ 2.013562] xhci-mtk 11200000.usb: xHCI Host Controller
10643 11:06:58.327062 <6>[ 2.019053] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10644 11:06:58.337130 <6>[ 2.026889] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10645 11:06:58.343477 <6>[ 2.036297] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10646 11:06:58.350334 <6>[ 2.042352] xhci-mtk 11200000.usb: xHCI Host Controller
10647 11:06:58.357000 <6>[ 2.047826] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10648 11:06:58.363552 <6>[ 2.055471] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10649 11:06:58.369971 <6>[ 2.063207] hub 1-0:1.0: USB hub found
10650 11:06:58.373308 <6>[ 2.067215] hub 1-0:1.0: 1 port detected
10651 11:06:58.383033 <6>[ 2.071480] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10652 11:06:58.386487 <6>[ 2.080018] hub 2-0:1.0: USB hub found
10653 11:06:58.389489 <6>[ 2.084023] hub 2-0:1.0: 1 port detected
10654 11:06:58.398315 <6>[ 2.091768] mtk-msdc 11f70000.mmc: Got CD GPIO
10655 11:06:58.410409 <6>[ 2.100174] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10656 11:06:58.416698 <6>[ 2.108202] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10657 11:06:58.426784 <4>[ 2.116101] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10658 11:06:58.436754 <6>[ 2.125629] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10659 11:06:58.443362 <6>[ 2.133705] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10660 11:06:58.450057 <6>[ 2.141724] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10661 11:06:58.460256 <6>[ 2.149644] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10662 11:06:58.466819 <6>[ 2.157461] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10663 11:06:58.476723 <6>[ 2.165277] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10664 11:06:58.486701 <6>[ 2.175572] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10665 11:06:58.493102 <6>[ 2.183956] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10666 11:06:58.503303 <6>[ 2.192300] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10667 11:06:58.509636 <6>[ 2.200638] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10668 11:06:58.519506 <6>[ 2.208975] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10669 11:06:58.526285 <6>[ 2.217313] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10670 11:06:58.536052 <6>[ 2.225651] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10671 11:06:58.542729 <6>[ 2.233988] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10672 11:06:58.552672 <6>[ 2.242324] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10673 11:06:58.559355 <6>[ 2.250662] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10674 11:06:58.569183 <6>[ 2.259002] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10675 11:06:58.575876 <6>[ 2.267340] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10676 11:06:58.586063 <6>[ 2.275677] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10677 11:06:58.592521 <6>[ 2.284014] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10678 11:06:58.602546 <6>[ 2.292351] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10679 11:06:58.609068 <6>[ 2.301090] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10680 11:06:58.615598 <6>[ 2.308218] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10681 11:06:58.622103 <6>[ 2.314971] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10682 11:06:58.629130 <6>[ 2.321727] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10683 11:06:58.635410 <6>[ 2.328663] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10684 11:06:58.645491 <6>[ 2.335517] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10685 11:06:58.655422 <6>[ 2.344646] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10686 11:06:58.665366 <6>[ 2.353766] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10687 11:06:58.675374 <6>[ 2.363059] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10688 11:06:58.685023 <6>[ 2.372526] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10689 11:06:58.691895 <6>[ 2.381992] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10690 11:06:58.701714 <6>[ 2.391111] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10691 11:06:58.711380 <6>[ 2.400577] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10692 11:06:58.721461 <6>[ 2.409696] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10693 11:06:58.731492 <6>[ 2.418990] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10694 11:06:58.741439 <6>[ 2.429150] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10695 11:06:58.751179 <6>[ 2.440459] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10696 11:06:58.757795 <6>[ 2.450071] Trying to probe devices needed for running init ...
10697 11:06:58.805163 <6>[ 2.495148] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10698 11:06:58.959824 <6>[ 2.652974] hub 1-1:1.0: USB hub found
10699 11:06:58.962908 <6>[ 2.657506] hub 1-1:1.0: 4 ports detected
10700 11:06:58.972755 <6>[ 2.666157] hub 1-1:1.0: USB hub found
10701 11:06:58.976038 <6>[ 2.670496] hub 1-1:1.0: 4 ports detected
10702 11:06:59.085183 <6>[ 2.775503] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10703 11:06:59.111384 <6>[ 2.804718] hub 2-1:1.0: USB hub found
10704 11:06:59.114414 <6>[ 2.809205] hub 2-1:1.0: 3 ports detected
10705 11:06:59.123776 <6>[ 2.817206] hub 2-1:1.0: USB hub found
10706 11:06:59.127267 <6>[ 2.821717] hub 2-1:1.0: 3 ports detected
10707 11:06:59.301056 <6>[ 2.991157] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10708 11:06:59.433183 <6>[ 3.126706] hub 1-1.4:1.0: USB hub found
10709 11:06:59.436720 <6>[ 3.131345] hub 1-1.4:1.0: 2 ports detected
10710 11:06:59.445794 <6>[ 3.138985] hub 1-1.4:1.0: USB hub found
10711 11:06:59.448873 <6>[ 3.143570] hub 1-1.4:1.0: 2 ports detected
10712 11:06:59.513099 <6>[ 3.203381] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10713 11:06:59.745203 <6>[ 3.435188] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10714 11:06:59.937035 <6>[ 3.627190] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10715 11:07:11.038141 <6>[ 14.736201] ALSA device list:
10716 11:07:11.044814 <6>[ 14.739487] No soundcards found.
10717 11:07:11.052692 <6>[ 14.747449] Freeing unused kernel memory: 8448K
10718 11:07:11.056072 <6>[ 14.753008] Run /init as init process
10719 11:07:11.067010 Loading, please wait...
10720 11:07:11.086845 Starting version 247.3-7+deb11u4
10721 11:07:11.277143 <6>[ 14.968526] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10722 11:07:11.288954 <6>[ 14.983558] remoteproc remoteproc0: scp is available
10723 11:07:11.295479 <6>[ 14.989608] remoteproc remoteproc0: powering up scp
10724 11:07:11.302368 <6>[ 14.994854] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10725 11:07:11.308770 <6>[ 15.003373] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10726 11:07:11.315450 <6>[ 15.004949] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10727 11:07:11.325420 <3>[ 15.006768] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 11:07:11.331997 <3>[ 15.006799] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 11:07:11.341730 <3>[ 15.006813] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 11:07:11.348302 <3>[ 15.011160] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 11:07:11.358099 <6>[ 15.017262] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10732 11:07:11.364952 <3>[ 15.036116] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 11:07:11.374908 <6>[ 15.043435] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10734 11:07:11.381460 <6>[ 15.047140] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10735 11:07:11.391278 <3>[ 15.049031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 11:07:11.398727 <3>[ 15.049054] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10737 11:07:11.405387 <3>[ 15.049072] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10738 11:07:11.415241 <3>[ 15.049557] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 11:07:11.421821 <6>[ 15.058367] usbcore: registered new device driver r8152-cfgselector
10740 11:07:11.424914 <6>[ 15.060240] mc: Linux media interface: v0.10
10741 11:07:11.435018 <3>[ 15.066240] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 11:07:11.441712 <4>[ 15.075372] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10743 11:07:11.451302 <4>[ 15.081960] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10744 11:07:11.454672 <4>[ 15.081960] Fallback method does not support PEC.
10745 11:07:11.464989 <3>[ 15.082386] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 11:07:11.471118 <4>[ 15.095777] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10747 11:07:11.478115 <3>[ 15.098502] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 11:07:11.487927 <3>[ 15.098601] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 11:07:11.494460 <3>[ 15.109167] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10750 11:07:11.504512 <3>[ 15.114675] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 11:07:11.510833 <3>[ 15.114679] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10752 11:07:11.520760 <3>[ 15.114686] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10753 11:07:11.527715 <3>[ 15.114691] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 11:07:11.537354 <3>[ 15.114729] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 11:07:11.543997 <6>[ 15.134444] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10756 11:07:11.550892 <6>[ 15.134475] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10757 11:07:11.557469 <6>[ 15.134483] remoteproc remoteproc0: remote processor scp is now up
10758 11:07:11.564241 <6>[ 15.168318] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10759 11:07:11.574359 <6>[ 15.171344] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10760 11:07:11.577385 <6>[ 15.178371] pci_bus 0000:00: root bus resource [bus 00-ff]
10761 11:07:11.588042 <6>[ 15.188119] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10762 11:07:11.594408 <6>[ 15.195226] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10763 11:07:11.604275 <6>[ 15.195425] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10764 11:07:11.614654 <6>[ 15.195929] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10765 11:07:11.620940 <6>[ 15.206223] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10766 11:07:11.630960 <4>[ 15.206641] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10767 11:07:11.637225 <4>[ 15.206658] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10768 11:07:11.647459 <6>[ 15.211386] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10769 11:07:11.657180 <6>[ 15.217246] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10770 11:07:11.664053 <6>[ 15.241393] videodev: Linux video capture interface: v2.00
10771 11:07:11.670402 <6>[ 15.242973] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10772 11:07:11.673752 <6>[ 15.243636] Bluetooth: Core ver 2.22
10773 11:07:11.680299 <6>[ 15.243717] NET: Registered PF_BLUETOOTH protocol family
10774 11:07:11.686923 <6>[ 15.243720] Bluetooth: HCI device and connection manager initialized
10775 11:07:11.690201 <6>[ 15.243737] Bluetooth: HCI socket layer initialized
10776 11:07:11.696805 <6>[ 15.243743] Bluetooth: L2CAP socket layer initialized
10777 11:07:11.700343 <6>[ 15.243752] Bluetooth: SCO socket layer initialized
10778 11:07:11.707098 <6>[ 15.280816] usbcore: registered new interface driver btusb
10779 11:07:11.713216 <6>[ 15.287436] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10780 11:07:11.726699 <4>[ 15.287903] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10781 11:07:11.730204 <3>[ 15.287949] Bluetooth: hci0: Failed to load firmware file (-2)
10782 11:07:11.736767 <3>[ 15.287954] Bluetooth: hci0: Failed to set up firmware (-2)
10783 11:07:11.746477 <4>[ 15.287958] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10784 11:07:11.756389 <6>[ 15.288343] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10785 11:07:11.766103 <6>[ 15.289454] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10786 11:07:11.772941 <6>[ 15.289546] usbcore: registered new interface driver uvcvideo
10787 11:07:11.782655 <3>[ 15.291997] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10788 11:07:11.785962 <6>[ 15.303115] r8152 2-1.3:1.0 eth0: v1.12.13
10789 11:07:11.789302 <6>[ 15.304523] pci 0000:00:00.0: supports D1 D2
10790 11:07:11.795796 <6>[ 15.313593] usbcore: registered new interface driver r8152
10791 11:07:11.802521 <6>[ 15.321724] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10792 11:07:11.812306 <6>[ 15.322801] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10793 11:07:11.819051 <6>[ 15.323017] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10794 11:07:11.825741 <6>[ 15.364158] usbcore: registered new interface driver cdc_ether
10795 11:07:11.832349 <6>[ 15.370188] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10796 11:07:11.835354 <6>[ 15.386236] usbcore: registered new interface driver r8153_ecm
10797 11:07:11.845629 <6>[ 15.391233] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10798 11:07:11.848898 <6>[ 15.411752] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10799 11:07:11.858741 <6>[ 15.414870] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10800 11:07:11.865456 <6>[ 15.557535] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10801 11:07:11.868607 <6>[ 15.565129] pci 0000:01:00.0: supports D1 D2
10802 11:07:11.875156 <6>[ 15.569652] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10803 11:07:11.895766 <6>[ 15.587208] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10804 11:07:11.902408 <6>[ 15.594113] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10805 11:07:11.908981 <6>[ 15.602207] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10806 11:07:11.918673 <6>[ 15.610204] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10807 11:07:11.925276 <6>[ 15.618205] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10808 11:07:11.935300 <6>[ 15.626206] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10809 11:07:11.938674 <6>[ 15.634205] pci 0000:00:00.0: PCI bridge to [bus 01]
10810 11:07:11.948755 <6>[ 15.639422] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10811 11:07:11.955123 <6>[ 15.647555] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10812 11:07:11.961901 <6>[ 15.654449] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10813 11:07:11.968332 <6>[ 15.661285] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10814 11:07:11.983585 <5>[ 15.675270] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10815 11:07:12.002195 <5>[ 15.693644] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10816 11:07:12.008899 <5>[ 15.700997] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10817 11:07:12.018940 <4>[ 15.709453] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10818 11:07:12.021899 <6>[ 15.718338] cfg80211: failed to load regulatory.db
10819 11:07:12.071425 <6>[ 15.762968] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10820 11:07:12.077972 <6>[ 15.770481] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10821 11:07:12.102273 <6>[ 15.797126] mt7921e 0000:01:00.0: ASIC revision: 79610010
10822 11:07:12.203272 <6>[ 15.894809] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10823 11:07:12.206575 <6>[ 15.894809]
10824 11:07:12.210069 Begin: Loading essential drivers ... done.
10825 11:07:12.213085 Begin: Running /scripts/init-premount ... done.
10826 11:07:12.219809 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10827 11:07:12.229678 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10828 11:07:12.232994 Device /sys/class/net/enx0024323078ff found
10829 11:07:12.233077 done.
10830 11:07:12.283557 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10831 11:07:12.471308 <6>[ 16.162817] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10832 11:07:13.155400 <6>[ 16.850320] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10833 11:07:13.317867 <6>[ 17.013082] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10834 11:07:13.460386 IP-Config: no response after 2 secs - giving up
10835 11:07:13.495304 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10836 11:07:13.527883 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:07 mtu 1500 DHCP
10837 11:07:14.235367 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10838 11:07:14.241699 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10839 11:07:14.248365 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10840 11:07:14.254880 host : mt8192-asurada-spherion-r0-cbg-8
10841 11:07:14.261526 domain : lava-rack
10842 11:07:14.268065 rootserver: 192.168.201.1 rootpath:
10843 11:07:14.268147 filename :
10844 11:07:14.391755 done.
10845 11:07:14.400250 Begin: Running /scripts/nfs-bottom ... done.
10846 11:07:14.421058 Begin: Running /scripts/init-bottom ... done.
10847 11:07:15.673383 <6>[ 19.368349] NET: Registered PF_INET6 protocol family
10848 11:07:15.680921 <6>[ 19.375786] Segment Routing with IPv6
10849 11:07:15.683954 <6>[ 19.379792] In-situ OAM (IOAM) with IPv6
10850 11:07:15.831415 <30>[ 19.506316] systemd[1]: systemd 247.3-7+deb11u4 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10851 11:07:15.834665 <30>[ 19.530765] systemd[1]: Detected architecture arm64.
10852 11:07:15.858783
10853 11:07:15.862172 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10854 11:07:15.862633
10855 11:07:15.879562 <30>[ 19.574421] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10856 11:07:16.892884 <30>[ 20.584712] systemd[1]: Queued start job for default target Graphical Interface.
10857 11:07:16.922935 <30>[ 20.617674] systemd[1]: Created slice system-getty.slice.
10858 11:07:16.929314 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10859 11:07:16.945691 <30>[ 20.640578] systemd[1]: Created slice system-modprobe.slice.
10860 11:07:16.952527 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10861 11:07:16.970230 <30>[ 20.665262] systemd[1]: Created slice system-serial\x2dgetty.slice.
10862 11:07:16.980908 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10863 11:07:16.993774 <30>[ 20.688272] systemd[1]: Created slice User and Session Slice.
10864 11:07:17.000279 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10865 11:07:17.020508 <30>[ 20.712000] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10866 11:07:17.030532 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10867 11:07:17.048722 <30>[ 20.739925] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10868 11:07:17.055311 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10869 11:07:17.079005 <30>[ 20.767357] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10870 11:07:17.085367 <30>[ 20.779497] systemd[1]: Reached target Local Encrypted Volumes.
10871 11:07:17.092324 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10872 11:07:17.109127 <30>[ 20.803707] systemd[1]: Reached target Paths.
10873 11:07:17.115388 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10874 11:07:17.128313 <30>[ 20.823159] systemd[1]: Reached target Remote File Systems.
10875 11:07:17.134776 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10876 11:07:17.152386 <30>[ 20.847535] systemd[1]: Reached target Slices.
10877 11:07:17.158849 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10878 11:07:17.171844 <30>[ 20.867163] systemd[1]: Reached target Swap.
10879 11:07:17.175148 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10880 11:07:17.195811 <30>[ 20.887641] systemd[1]: Listening on initctl Compatibility Named Pipe.
10881 11:07:17.202447 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10882 11:07:17.208941 <30>[ 20.904088] systemd[1]: Listening on Journal Audit Socket.
10883 11:07:17.215897 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10884 11:07:17.233670 <30>[ 20.928707] systemd[1]: Listening on Journal Socket (/dev/log).
10885 11:07:17.240626 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10886 11:07:17.257172 <30>[ 20.951733] systemd[1]: Listening on Journal Socket.
10887 11:07:17.263327 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10888 11:07:17.280933 <30>[ 20.972953] systemd[1]: Listening on Network Service Netlink Socket.
10889 11:07:17.287775 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10890 11:07:17.303549 <30>[ 20.998728] systemd[1]: Listening on udev Control Socket.
10891 11:07:17.310187 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10892 11:07:17.324254 <30>[ 21.019595] systemd[1]: Listening on udev Kernel Socket.
10893 11:07:17.331155 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10894 11:07:17.372336 <30>[ 21.067227] systemd[1]: Mounting Huge Pages File System...
10895 11:07:17.378814 Mounting [0;1;39mHuge Pages File System[0m...
10896 11:07:17.396380 <30>[ 21.091364] systemd[1]: Mounting POSIX Message Queue File System...
10897 11:07:17.403357 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10898 11:07:17.424708 <30>[ 21.119754] systemd[1]: Mounting Kernel Debug File System...
10899 11:07:17.431282 Mounting [0;1;39mKernel Debug File System[0m...
10900 11:07:17.447819 <30>[ 21.139688] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10901 11:07:17.462866 <30>[ 21.154772] systemd[1]: Starting Create list of static device nodes for the current kernel...
10902 11:07:17.469343 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10903 11:07:17.493108 <30>[ 21.188413] systemd[1]: Starting Load Kernel Module configfs...
10904 11:07:17.499845 Starting [0;1;39mLoad Kernel Module configfs[0m...
10905 11:07:17.520456 <30>[ 21.215406] systemd[1]: Starting Load Kernel Module drm...
10906 11:07:17.526923 Starting [0;1;39mLoad Kernel Module drm[0m...
10907 11:07:17.545345 <30>[ 21.240335] systemd[1]: Starting Load Kernel Module fuse...
10908 11:07:17.552020 Starting [0;1;39mLoad Kernel Module fuse[0m...
10909 11:07:17.578406 <30>[ 21.270003] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10910 11:07:17.590170 <6>[ 21.284956] fuse: init (API version 7.37)
10911 11:07:17.616662 <30>[ 21.311662] systemd[1]: Starting Journal Service...
10912 11:07:17.619736 Starting [0;1;39mJournal Service[0m...
10913 11:07:17.645536 <30>[ 21.340487] systemd[1]: Starting Load Kernel Modules...
10914 11:07:17.652079 Starting [0;1;39mLoad Kernel Modules[0m...
10915 11:07:17.669612 <30>[ 21.361755] systemd[1]: Starting Remount Root and Kernel File Systems...
10916 11:07:17.675972 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10917 11:07:17.692345 <30>[ 21.387632] systemd[1]: Starting Coldplug All udev Devices...
10918 11:07:17.698733 Starting [0;1;39mColdplug All udev Devices[0m...
10919 11:07:17.717686 <30>[ 21.413118] systemd[1]: Mounted Huge Pages File System.
10920 11:07:17.724452 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10921 11:07:17.740208 <30>[ 21.435742] systemd[1]: Mounted POSIX Message Queue File System.
10922 11:07:17.746803 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10923 11:07:17.764470 <30>[ 21.459864] systemd[1]: Mounted Kernel Debug File System.
10924 11:07:17.771276 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10925 11:07:17.781226 <3>[ 21.472152] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 11:07:17.791870 <30>[ 21.484164] systemd[1]: Finished Create list of static device nodes for the current kernel.
10927 11:07:17.801876 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10928 11:07:17.817298 <3>[ 21.509317] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 11:07:17.824444 <30>[ 21.519516] systemd[1]: modprobe@configfs.service: Succeeded.
10930 11:07:17.831270 <30>[ 21.526454] systemd[1]: Finished Load Kernel Module configfs.
10931 11:07:17.838050 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10932 11:07:17.853213 <30>[ 21.548034] systemd[1]: modprobe@drm.service: Succeeded.
10933 11:07:17.860243 <30>[ 21.554794] systemd[1]: Finished Load Kernel Module drm.
10934 11:07:17.870045 <3>[ 21.556336] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 11:07:17.876586 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10936 11:07:17.898728 <3>[ 21.590485] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 11:07:17.905850 <30>[ 21.600695] systemd[1]: modprobe@fuse.service: Succeeded.
10938 11:07:17.912537 <30>[ 21.607667] systemd[1]: Finished Load Kernel Module fuse.
10939 11:07:17.919384 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10940 11:07:17.937575 <30>[ 21.632827] systemd[1]: Finished Load Kernel Modules.
10941 11:07:17.948114 <3>[ 21.633627] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 11:07:17.954054 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10943 11:07:17.973677 <30>[ 21.665233] systemd[1]: Finished Remount Root and Kernel File Systems.
10944 11:07:17.980306 <3>[ 21.668029] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 11:07:17.986945 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10946 11:07:18.010343 <3>[ 21.702364] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 11:07:18.041907 <3>[ 21.733856] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 11:07:18.054269 <30>[ 21.749344] systemd[1]: Mounting FUSE Control File System...
10949 11:07:18.060927 Mounting [0;1;39mFUSE Control File System[0m...
10950 11:07:18.072128 <3>[ 21.763647] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 11:07:18.084538 <30>[ 21.776381] systemd[1]: Mounting Kernel Configuration File System...
10952 11:07:18.088009 Mounting [0;1;39mKernel Configuration File System[0m...
10953 11:07:18.103339 <3>[ 21.795445] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 11:07:18.118711 <30>[ 21.810701] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10955 11:07:18.129066 <30>[ 21.819960] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10956 11:07:18.165635 <30>[ 21.860237] systemd[1]: Starting Load/Save Random Seed...
10957 11:07:18.172349 Starting [0;1;39mLoad/Save Random Seed[0m...
10958 11:07:18.186735 <30>[ 21.881855] systemd[1]: Starting Apply Kernel Variables...
10959 11:07:18.193253 Starting [0;1;39mApply Kernel Variables[0m...
10960 11:07:18.213267 <30>[ 21.907891] systemd[1]: Starting Create System Users...
10961 11:07:18.230024 <4>[ 21.913047] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10962 11:07:18.236834 <3>[ 21.929234] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10963 11:07:18.243137 Starting [0;1;39mCreate System Users[0m...
10964 11:07:18.259362 <30>[ 21.954213] systemd[1]: Started Journal Service.
10965 11:07:18.265914 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10966 11:07:18.289814 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10967 11:07:18.304027 See 'systemctl status systemd-udev-trigger.service' for details.
10968 11:07:18.320784 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10969 11:07:18.335927 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10970 11:07:18.352927 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10971 11:07:18.370124 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10972 11:07:18.386016 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10973 11:07:18.441345 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10974 11:07:18.457738 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10975 11:07:18.507512 <46>[ 22.199497] systemd-journald[295]: Received client request to flush runtime journal.
10976 11:07:19.105850 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10977 11:07:19.124272 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10978 11:07:19.139652 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10979 11:07:19.195403 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10980 11:07:19.916716 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10981 11:07:19.960476 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10982 11:07:20.017117 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10983 11:07:20.087034 Starting [0;1;39mNetwork Service[0m...
10984 11:07:20.382779 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10985 11:07:20.428308 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10986 11:07:20.447120 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10987 11:07:20.817528 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10988 11:07:20.835285 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10989 11:07:20.855857 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10990 11:07:20.871670 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10991 11:07:20.920664 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10992 11:07:20.941233 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10993 11:07:21.008421 Starting [0;1;39mNetwork Name Resolution[0m...
10994 11:07:21.039169 Starting [0;1;39mNetwork Time Synchronization[0m...
10995 11:07:21.091915 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10996 11:07:21.107920 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10997 11:07:21.186829 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10998 11:07:21.599109 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10999 11:07:21.616258 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11000 11:07:21.639065 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11001 11:07:21.651614 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11002 11:07:21.667323 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11003 11:07:21.697814 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11004 11:07:21.898117 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11005 11:07:22.431823 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11006 11:07:22.769173 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11007 11:07:22.783098 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11008 11:07:22.804938 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11009 11:07:22.819452 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11010 11:07:22.835394 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11011 11:07:22.888520 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11012 11:07:22.971863 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11013 11:07:23.076383 Starting [0;1;39mUser Login Management[0m...
11014 11:07:23.093072 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11015 11:07:23.110261 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11016 11:07:23.126660 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11017 11:07:23.143028 Starting [0;1;39mPermit User Sessions[0m...
11018 11:07:23.267376 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11019 11:07:23.289843 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11020 11:07:23.360040 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11021 11:07:23.378347 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11022 11:07:23.399539 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11023 11:07:23.418255 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11024 11:07:23.438013 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11025 11:07:23.456763 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11026 11:07:23.517065 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11027 11:07:23.577382 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11028 11:07:23.657679
11029 11:07:23.658206
11030 11:07:23.660798 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11031 11:07:23.661248
11032 11:07:23.674991 debian-bullseye-arm64 login: root (automatic login)
11033 11:07:23.675441
11034 11:07:23.675784
11035 11:07:24.089838 Linux debian-bullseye-arm64 6.1.80-cip16 #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024 aarch64
11036 11:07:24.089972
11037 11:07:24.096571 The programs included with the Debian GNU/Linux system are free software;
11038 11:07:24.103437 the exact distribution terms for each program are described in the
11039 11:07:24.106429 individual files in /usr/share/doc/*/copyright.
11040 11:07:24.106513
11041 11:07:24.113071 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11042 11:07:24.116192 permitted by applicable law.
11043 11:07:25.055463 Matched prompt #10: / #
11045 11:07:25.055743 Setting prompt string to ['/ #']
11046 11:07:25.055838 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11048 11:07:25.056078 end: 2.2.5 auto-login-action (duration 00:00:30) [common]
11049 11:07:25.056170 start: 2.2.6 expect-shell-connection (timeout 00:03:02) [common]
11050 11:07:25.056242 Setting prompt string to ['/ #']
11051 11:07:25.056303 Forcing a shell prompt, looking for ['/ #']
11053 11:07:25.106493 / #
11054 11:07:25.106618 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11055 11:07:25.106726 Waiting using forced prompt support (timeout 00:02:30)
11056 11:07:25.110749
11057 11:07:25.111016 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11058 11:07:25.111111 start: 2.2.7 export-device-env (timeout 00:03:02) [common]
11060 11:07:25.211506 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12925624/extract-nfsrootfs-beawcsqf'
11061 11:07:25.216626 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12925624/extract-nfsrootfs-beawcsqf'
11063 11:07:25.317151 / # export NFS_SERVER_IP='192.168.201.1'
11064 11:07:25.322282 export NFS_SERVER_IP='192.168.201.1'
11065 11:07:25.322567 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11066 11:07:25.322669 end: 2.2 depthcharge-retry (duration 00:01:58) [common]
11067 11:07:25.322763 end: 2 depthcharge-action (duration 00:01:58) [common]
11068 11:07:25.322856 start: 3 lava-test-retry (timeout 00:07:18) [common]
11069 11:07:25.322947 start: 3.1 lava-test-shell (timeout 00:07:18) [common]
11070 11:07:25.323024 Using namespace: common
11072 11:07:25.423356 / # #
11073 11:07:25.423480 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11074 11:07:25.428492 #
11075 11:07:25.428790 Using /lava-12925624
11077 11:07:25.529171 / # export SHELL=/bin/bash
11078 11:07:25.534579 export SHELL=/bin/bash
11080 11:07:25.635104 / # . /lava-12925624/environment
11081 11:07:25.640261 . /lava-12925624/environment
11083 11:07:25.746463 / # /lava-12925624/bin/lava-test-runner /lava-12925624/0
11084 11:07:25.746575 Test shell timeout: 10s (minimum of the action and connection timeout)
11085 11:07:25.751474 /lava-12925624/bin/lava-test-runner /lava-12925624/0
11086 11:07:26.052343 + export TESTRUN_ID=0_timesync-off
11087 11:07:26.055662 + TESTRUN_ID=0_timesync-off
11088 11:07:26.058967 + cd /lava-12925624/0/tests/0_timesync-off
11089 11:07:26.062417 ++ cat uuid
11090 11:07:26.067062 + UUID=12925624_1.6.2.3.1
11091 11:07:26.067147 + set +x
11092 11:07:26.073404 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12925624_1.6.2.3.1>
11093 11:07:26.073691 Received signal: <STARTRUN> 0_timesync-off 12925624_1.6.2.3.1
11094 11:07:26.073765 Starting test lava.0_timesync-off (12925624_1.6.2.3.1)
11095 11:07:26.073853 Skipping test definition patterns.
11096 11:07:26.076894 + systemctl stop systemd-timesyncd
11097 11:07:26.140685 + set +x
11098 11:07:26.143878 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12925624_1.6.2.3.1>
11099 11:07:26.144135 Received signal: <ENDRUN> 0_timesync-off 12925624_1.6.2.3.1
11100 11:07:26.144220 Ending use of test pattern.
11101 11:07:26.144284 Ending test lava.0_timesync-off (12925624_1.6.2.3.1), duration 0.07
11103 11:07:26.223517 + export TESTRUN_ID=1_kselftest-rtc
11104 11:07:26.226567 + TESTRUN_ID=1_kselftest-rtc
11105 11:07:26.230048 + cd /lava-12925624/0/tests/1_kselftest-rtc
11106 11:07:26.233377 ++ cat uuid
11107 11:07:26.239328 + UUID=12925624_1.6.2.3.5
11108 11:07:26.239413 + set +x
11109 11:07:26.245960 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 12925624_1.6.2.3.5>
11110 11:07:26.246217 Received signal: <STARTRUN> 1_kselftest-rtc 12925624_1.6.2.3.5
11111 11:07:26.246289 Starting test lava.1_kselftest-rtc (12925624_1.6.2.3.5)
11112 11:07:26.246371 Skipping test definition patterns.
11113 11:07:26.249379 + cd ./automated/linux/kselftest/
11114 11:07:26.275724 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11115 11:07:26.322248 INFO: install_deps skipped
11116 11:07:26.452600 --2024-03-03 11:07:26-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11117 11:07:26.463681 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11118 11:07:26.597069 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11119 11:07:26.730753 HTTP request sent, awaiting response... 200 OK
11120 11:07:26.733823 Length: 1746012 (1.7M) [application/octet-stream]
11121 11:07:26.737275 Saving to: 'kselftest.tar.xz'
11122 11:07:26.737378
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11130 11:07:27.851034
11131 11:07:27.998294 2024-03-03 11:07:27 (1.50 MB/s) - 'kselftest.tar.xz' saved [1746012/1746012]
11132 11:07:27.998455
11133 11:07:32.871857 skiplist:
11134 11:07:32.874921 ========================================
11135 11:07:32.878208 ========================================
11136 11:07:32.929659 rtc:rtctest
11137 11:07:32.950931 ============== Tests to run ===============
11138 11:07:32.951049 rtc:rtctest
11139 11:07:32.957639 ===========End Tests to run ===============
11140 11:07:32.961138 shardfile-rtc pass
11141 11:07:33.065308 <12>[ 36.762603] kselftest: Running tests in rtc
11142 11:07:33.075491 TAP version 13
11143 11:07:33.089254 1..1
11144 11:07:33.127252 # selftests: rtc: rtctest
11145 11:07:33.578443 # TAP version 13
11146 11:07:33.578608 # 1..8
11147 11:07:33.581635 # # Starting 8 tests from 2 test cases.
11148 11:07:33.584976 # # RUN rtc.date_read ...
11149 11:07:33.591469 # # rtctest.c:49:date_read:Current RTC date/time is 03/03/2024 11:07:33.
11150 11:07:33.595027 # # OK rtc.date_read
11151 11:07:33.598292 # ok 1 rtc.date_read
11152 11:07:33.601689 # # RUN rtc.date_read_loop ...
11153 11:07:33.611365 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11154 11:07:42.457508 <6>[ 46.159041] vpu: disabling
11155 11:07:42.460950 <6>[ 46.162144] vproc2: disabling
11156 11:07:42.464006 <6>[ 46.165466] vproc1: disabling
11157 11:07:42.467547 <6>[ 46.168773] vaud18: disabling
11158 11:07:42.474135 <6>[ 46.172651] vsram_others: disabling
11159 11:07:42.477357 <6>[ 46.176619] va09: disabling
11160 11:07:42.480650 <6>[ 46.179785] vsram_md: disabling
11161 11:07:42.484052 <6>[ 46.183348] Vgpu: disabling
11162 11:08:04.015199 # # rtctest.c:115:date_read_loop:Performed 2688 RTC time reads.
11163 11:08:04.018564 # # OK rtc.date_read_loop
11164 11:08:04.021751 # ok 2 rtc.date_read_loop
11165 11:08:04.025571 # # RUN rtc.uie_read ...
11166 11:08:06.996187 # # OK rtc.uie_read
11167 11:08:06.999070 # ok 3 rtc.uie_read
11168 11:08:07.002290 # # RUN rtc.uie_select ...
11169 11:08:09.996454 # # OK rtc.uie_select
11170 11:08:09.999764 # ok 4 rtc.uie_select
11171 11:08:10.002952 # # RUN rtc.alarm_alm_set ...
11172 11:08:10.009692 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 11:08:13.
11173 11:08:10.012849 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11174 11:08:10.019528 # # alarm_alm_set: Test terminated by assertion
11175 11:08:10.023105 # # FAIL rtc.alarm_alm_set
11176 11:08:10.023567 # not ok 5 rtc.alarm_alm_set
11177 11:08:10.029958 # # RUN rtc.alarm_wkalm_set ...
11178 11:08:10.036191 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 03/03/2024 11:08:13.
11179 11:08:12.998861 # # OK rtc.alarm_wkalm_set
11180 11:08:12.999383 # ok 6 rtc.alarm_wkalm_set
11181 11:08:13.005545 # # RUN rtc.alarm_alm_set_minute ...
11182 11:08:13.009126 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 11:09:00.
11183 11:08:13.015696 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11184 11:08:13.022279 # # alarm_alm_set_minute: Test terminated by assertion
11185 11:08:13.025418 # # FAIL rtc.alarm_alm_set_minute
11186 11:08:13.028556 # not ok 7 rtc.alarm_alm_set_minute
11187 11:08:13.031962 # # RUN rtc.alarm_wkalm_set_minute ...
11188 11:08:13.038647 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 03/03/2024 11:09:00.
11189 11:08:59.993560 # # OK rtc.alarm_wkalm_set_minute
11190 11:08:59.996993 # ok 8 rtc.alarm_wkalm_set_minute
11191 11:09:00.000502 # # FAILED: 6 / 8 tests passed.
11192 11:09:00.003443 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11193 11:09:00.006799 not ok 1 selftests: rtc: rtctest # exit=1
11194 11:09:00.663170 Traceback (most recent call last):
11195 11:09:00.673143 File "/lava-12925624/0/tests/1_kselftest-rtc/automated/linux/kselftest/./parse-output.py", line 4, in <module>
11196 11:09:00.676475 from tap import parser
11197 11:09:00.679944 ModuleNotFoundError: No module named 'tap'
11198 11:09:00.700617 + ../../utils/send-to-lava.sh ./output/result.txt
11199 11:09:00.807066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11200 11:09:00.807603 + set +x
11201 11:09:00.808381 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11203 11:09:00.813620 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 12925624_1.6.2.3.5>
11204 11:09:00.814356 Received signal: <ENDRUN> 1_kselftest-rtc 12925624_1.6.2.3.5
11205 11:09:00.814739 Ending use of test pattern.
11206 11:09:00.815065 Ending test lava.1_kselftest-rtc (12925624_1.6.2.3.5), duration 94.57
11208 11:09:00.816936 <LAVA_TEST_RUNNER EXIT>
11209 11:09:00.817591 ok: lava_test_shell seems to have completed
11210 11:09:00.818268 shardfile-rtc: pass
11211 11:09:00.818710 end: 3.1 lava-test-shell (duration 00:01:35) [common]
11212 11:09:00.819155 end: 3 lava-test-retry (duration 00:01:35) [common]
11213 11:09:00.819612 start: 4 finalize (timeout 00:05:43) [common]
11214 11:09:00.820077 start: 4.1 power-off (timeout 00:00:30) [common]
11215 11:09:00.820837 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11216 11:09:00.957379 >> Command sent successfully.
11217 11:09:00.961800 Returned 0 in 0 seconds
11218 11:09:01.062804 end: 4.1 power-off (duration 00:00:00) [common]
11220 11:09:01.064214 start: 4.2 read-feedback (timeout 00:05:42) [common]
11221 11:09:01.065403 Listened to connection for namespace 'common' for up to 1s
11222 11:09:02.065823 Finalising connection for namespace 'common'
11223 11:09:02.066506 Disconnecting from shell: Finalise
11224 11:09:02.066961 / #
11225 11:09:02.167936 end: 4.2 read-feedback (duration 00:00:01) [common]
11226 11:09:02.168745 end: 4 finalize (duration 00:00:01) [common]
11227 11:09:02.169467 Cleaning after the job
11228 11:09:02.170136 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925624/tftp-deploy-7i8qwhg8/ramdisk
11229 11:09:02.183435 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925624/tftp-deploy-7i8qwhg8/kernel
11230 11:09:02.220236 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925624/tftp-deploy-7i8qwhg8/dtb
11231 11:09:02.220529 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925624/tftp-deploy-7i8qwhg8/nfsrootfs
11232 11:09:02.314065 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925624/tftp-deploy-7i8qwhg8/modules
11233 11:09:02.321442 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12925624
11234 11:09:02.969545 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12925624
11235 11:09:02.969726 Job finished correctly