Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 37
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 17
1 11:08:05.529567 lava-dispatcher, installed at version: 2024.01
2 11:08:05.529776 start: 0 validate
3 11:08:05.529947 Start time: 2024-03-03 11:08:05.529937+00:00 (UTC)
4 11:08:05.530074 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:08:05.530204 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20240129.0%2Farm64%2Finitrd.cpio.gz exists
6 11:08:05.798269 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:08:05.798448 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:08:06.064842 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:08:06.065064 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:08:06.331562 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:08:06.331782 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20240129.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:08:06.598083 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:08:06.598264 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:08:06.866520 validate duration: 1.34
16 11:08:06.866820 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:08:06.866918 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:08:06.867038 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:08:06.867161 Not decompressing ramdisk as can be used compressed.
20 11:08:06.867269 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20240129.0/arm64/initrd.cpio.gz
21 11:08:06.867350 saving as /var/lib/lava/dispatcher/tmp/12925670/tftp-deploy-5ljo28bt/ramdisk/initrd.cpio.gz
22 11:08:06.867415 total size: 4663085 (4 MB)
23 11:08:06.870903 progress 0 % (0 MB)
24 11:08:06.872580 progress 5 % (0 MB)
25 11:08:06.873840 progress 10 % (0 MB)
26 11:08:06.875079 progress 15 % (0 MB)
27 11:08:06.877687 progress 20 % (0 MB)
28 11:08:06.879709 progress 25 % (1 MB)
29 11:08:06.881568 progress 30 % (1 MB)
30 11:08:06.882815 progress 35 % (1 MB)
31 11:08:06.885033 progress 40 % (1 MB)
32 11:08:06.887378 progress 45 % (2 MB)
33 11:08:06.889922 progress 50 % (2 MB)
34 11:08:06.891499 progress 55 % (2 MB)
35 11:08:06.892842 progress 60 % (2 MB)
36 11:08:06.895306 progress 65 % (2 MB)
37 11:08:06.897287 progress 70 % (3 MB)
38 11:08:06.899949 progress 75 % (3 MB)
39 11:08:06.901194 progress 80 % (3 MB)
40 11:08:06.902453 progress 85 % (3 MB)
41 11:08:06.903937 progress 90 % (4 MB)
42 11:08:06.905243 progress 95 % (4 MB)
43 11:08:06.907327 progress 100 % (4 MB)
44 11:08:06.907479 4 MB downloaded in 0.04 s (111.00 MB/s)
45 11:08:06.907636 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:08:06.907959 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:08:06.908047 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:08:06.908132 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:08:06.908267 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:08:06.908336 saving as /var/lib/lava/dispatcher/tmp/12925670/tftp-deploy-5ljo28bt/kernel/Image
52 11:08:06.908398 total size: 51599872 (49 MB)
53 11:08:06.908459 No compression specified
54 11:08:06.909515 progress 0 % (0 MB)
55 11:08:06.922993 progress 5 % (2 MB)
56 11:08:06.936608 progress 10 % (4 MB)
57 11:08:06.950141 progress 15 % (7 MB)
58 11:08:06.963488 progress 20 % (9 MB)
59 11:08:06.977141 progress 25 % (12 MB)
60 11:08:06.990580 progress 30 % (14 MB)
61 11:08:07.004010 progress 35 % (17 MB)
62 11:08:07.017252 progress 40 % (19 MB)
63 11:08:07.030615 progress 45 % (22 MB)
64 11:08:07.044302 progress 50 % (24 MB)
65 11:08:07.057884 progress 55 % (27 MB)
66 11:08:07.071241 progress 60 % (29 MB)
67 11:08:07.084803 progress 65 % (32 MB)
68 11:08:07.098121 progress 70 % (34 MB)
69 11:08:07.111368 progress 75 % (36 MB)
70 11:08:07.124603 progress 80 % (39 MB)
71 11:08:07.137950 progress 85 % (41 MB)
72 11:08:07.151450 progress 90 % (44 MB)
73 11:08:07.164656 progress 95 % (46 MB)
74 11:08:07.177975 progress 100 % (49 MB)
75 11:08:07.178204 49 MB downloaded in 0.27 s (182.39 MB/s)
76 11:08:07.178366 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:08:07.178608 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:08:07.178697 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:08:07.178787 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:08:07.178929 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:08:07.178999 saving as /var/lib/lava/dispatcher/tmp/12925670/tftp-deploy-5ljo28bt/dtb/mt8192-asurada-spherion-r0.dtb
83 11:08:07.179062 total size: 47278 (0 MB)
84 11:08:07.179125 No compression specified
85 11:08:07.180253 progress 69 % (0 MB)
86 11:08:07.180528 progress 100 % (0 MB)
87 11:08:07.180687 0 MB downloaded in 0.00 s (27.79 MB/s)
88 11:08:07.180811 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:08:07.181034 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:08:07.181123 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:08:07.181208 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:08:07.181375 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20240129.0/arm64/full.rootfs.tar.xz
94 11:08:07.181445 saving as /var/lib/lava/dispatcher/tmp/12925670/tftp-deploy-5ljo28bt/nfsrootfs/full.rootfs.tar
95 11:08:07.181507 total size: 89509512 (85 MB)
96 11:08:07.181568 Using unxz to decompress xz
97 11:08:07.187426 progress 0 % (0 MB)
98 11:08:07.397726 progress 5 % (4 MB)
99 11:08:07.613842 progress 10 % (8 MB)
100 11:08:07.865354 progress 15 % (12 MB)
101 11:08:08.063461 progress 20 % (17 MB)
102 11:08:08.175030 progress 25 % (21 MB)
103 11:08:08.422218 progress 30 % (25 MB)
104 11:08:08.710182 progress 35 % (29 MB)
105 11:08:08.972049 progress 40 % (34 MB)
106 11:08:09.239255 progress 45 % (38 MB)
107 11:08:09.486808 progress 50 % (42 MB)
108 11:08:09.752576 progress 55 % (46 MB)
109 11:08:10.006115 progress 60 % (51 MB)
110 11:08:10.273551 progress 65 % (55 MB)
111 11:08:10.573390 progress 70 % (59 MB)
112 11:08:10.871487 progress 75 % (64 MB)
113 11:08:11.165297 progress 80 % (68 MB)
114 11:08:11.421611 progress 85 % (72 MB)
115 11:08:11.652531 progress 90 % (76 MB)
116 11:08:11.911894 progress 95 % (81 MB)
117 11:08:12.200279 progress 100 % (85 MB)
118 11:08:12.206274 85 MB downloaded in 5.02 s (16.99 MB/s)
119 11:08:12.206605 end: 1.4.1 http-download (duration 00:00:05) [common]
121 11:08:12.207059 end: 1.4 download-retry (duration 00:00:05) [common]
122 11:08:12.207176 start: 1.5 download-retry (timeout 00:09:55) [common]
123 11:08:12.207272 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 11:08:12.207430 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:08:12.207501 saving as /var/lib/lava/dispatcher/tmp/12925670/tftp-deploy-5ljo28bt/modules/modules.tar
126 11:08:12.207567 total size: 8628476 (8 MB)
127 11:08:12.207693 Using unxz to decompress xz
128 11:08:12.212249 progress 0 % (0 MB)
129 11:08:12.232948 progress 5 % (0 MB)
130 11:08:12.258382 progress 10 % (0 MB)
131 11:08:12.284886 progress 15 % (1 MB)
132 11:08:12.308992 progress 20 % (1 MB)
133 11:08:12.333936 progress 25 % (2 MB)
134 11:08:12.358846 progress 30 % (2 MB)
135 11:08:12.389592 progress 35 % (2 MB)
136 11:08:12.417187 progress 40 % (3 MB)
137 11:08:12.444060 progress 45 % (3 MB)
138 11:08:12.469630 progress 50 % (4 MB)
139 11:08:12.495913 progress 55 % (4 MB)
140 11:08:12.520271 progress 60 % (4 MB)
141 11:08:12.547286 progress 65 % (5 MB)
142 11:08:12.574509 progress 70 % (5 MB)
143 11:08:12.601688 progress 75 % (6 MB)
144 11:08:12.628892 progress 80 % (6 MB)
145 11:08:12.654245 progress 85 % (7 MB)
146 11:08:12.679282 progress 90 % (7 MB)
147 11:08:12.709974 progress 95 % (7 MB)
148 11:08:12.739385 progress 100 % (8 MB)
149 11:08:12.744600 8 MB downloaded in 0.54 s (15.32 MB/s)
150 11:08:12.744861 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:08:12.745139 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:08:12.745234 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 11:08:12.745337 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 11:08:14.506576 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12925670/extract-nfsrootfs-f0qwj3q5
156 11:08:14.506759 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 11:08:14.506858 start: 1.6.2 lava-overlay (timeout 00:09:52) [common]
158 11:08:14.507024 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8
159 11:08:14.507155 makedir: /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin
160 11:08:14.507256 makedir: /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/tests
161 11:08:14.507356 makedir: /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/results
162 11:08:14.507456 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-add-keys
163 11:08:14.507608 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-add-sources
164 11:08:14.507746 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-background-process-start
165 11:08:14.507874 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-background-process-stop
166 11:08:14.508000 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-common-functions
167 11:08:14.508124 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-echo-ipv4
168 11:08:14.508251 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-install-packages
169 11:08:14.508376 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-installed-packages
170 11:08:14.508517 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-os-build
171 11:08:14.508656 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-probe-channel
172 11:08:14.508782 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-probe-ip
173 11:08:14.508909 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-target-ip
174 11:08:14.509034 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-target-mac
175 11:08:14.509159 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-target-storage
176 11:08:14.509286 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-test-case
177 11:08:14.509413 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-test-event
178 11:08:14.509537 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-test-feedback
179 11:08:14.509661 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-test-raise
180 11:08:14.509785 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-test-reference
181 11:08:14.509909 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-test-runner
182 11:08:14.510033 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-test-set
183 11:08:14.510156 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-test-shell
184 11:08:14.510284 Updating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-install-packages (oe)
185 11:08:14.510437 Updating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/bin/lava-installed-packages (oe)
186 11:08:14.510559 Creating /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/environment
187 11:08:14.510653 LAVA metadata
188 11:08:14.510723 - LAVA_JOB_ID=12925670
189 11:08:14.510785 - LAVA_DISPATCHER_IP=192.168.201.1
190 11:08:14.510885 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:52) [common]
191 11:08:14.510951 skipped lava-vland-overlay
192 11:08:14.511023 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 11:08:14.511100 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:52) [common]
194 11:08:14.511160 skipped lava-multinode-overlay
195 11:08:14.511230 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 11:08:14.511305 start: 1.6.2.3 test-definition (timeout 00:09:52) [common]
197 11:08:14.511375 Loading test definitions
198 11:08:14.511467 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:52) [common]
199 11:08:14.511536 Using /lava-12925670 at stage 0
200 11:08:14.511876 uuid=12925670_1.6.2.3.1 testdef=None
201 11:08:14.511964 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 11:08:14.512048 start: 1.6.2.3.2 test-overlay (timeout 00:09:52) [common]
203 11:08:14.512582 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 11:08:14.512800 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:52) [common]
206 11:08:14.513394 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 11:08:14.513620 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
209 11:08:14.514198 runner path: /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/0/tests/0_lc-compliance test_uuid 12925670_1.6.2.3.1
210 11:08:14.514365 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 11:08:14.514607 Creating lava-test-runner.conf files
213 11:08:14.514670 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12925670/lava-overlay-hsv4eck8/lava-12925670/0 for stage 0
214 11:08:14.514759 - 0_lc-compliance
215 11:08:14.514855 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 11:08:14.514937 start: 1.6.2.4 compress-overlay (timeout 00:09:52) [common]
217 11:08:14.520929 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 11:08:14.521030 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
219 11:08:14.521115 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 11:08:14.521199 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 11:08:14.521284 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
222 11:08:14.644502 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 11:08:14.644896 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 11:08:14.645047 extracting modules file /var/lib/lava/dispatcher/tmp/12925670/tftp-deploy-5ljo28bt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925670/extract-nfsrootfs-f0qwj3q5
225 11:08:14.915122 extracting modules file /var/lib/lava/dispatcher/tmp/12925670/tftp-deploy-5ljo28bt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925670/extract-overlay-ramdisk-vr24_d4c/ramdisk
226 11:08:15.144783 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 11:08:15.144953 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 11:08:15.145048 [common] Applying overlay to NFS
229 11:08:15.145118 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925670/compress-overlay-bgt4ihfh/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12925670/extract-nfsrootfs-f0qwj3q5
230 11:08:15.151599 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 11:08:15.151755 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 11:08:15.151847 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 11:08:15.151933 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 11:08:15.152010 Building ramdisk /var/lib/lava/dispatcher/tmp/12925670/extract-overlay-ramdisk-vr24_d4c/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12925670/extract-overlay-ramdisk-vr24_d4c/ramdisk
235 11:08:15.485454 >> 119441 blocks
236 11:08:17.393538 rename /var/lib/lava/dispatcher/tmp/12925670/extract-overlay-ramdisk-vr24_d4c/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12925670/tftp-deploy-5ljo28bt/ramdisk/ramdisk.cpio.gz
237 11:08:17.393983 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 11:08:17.394102 start: 1.6.8 prepare-kernel (timeout 00:09:49) [common]
239 11:08:17.394206 start: 1.6.8.1 prepare-fit (timeout 00:09:49) [common]
240 11:08:17.394316 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12925670/tftp-deploy-5ljo28bt/kernel/Image'
241 11:08:30.062077 Returned 0 in 12 seconds
242 11:08:30.162688 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12925670/tftp-deploy-5ljo28bt/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12925670/tftp-deploy-5ljo28bt/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12925670/tftp-deploy-5ljo28bt/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12925670/tftp-deploy-5ljo28bt/kernel/image.itb
243 11:08:30.521703 output: FIT description: Kernel Image image with one or more FDT blobs
244 11:08:30.522061 output: Created: Sun Mar 3 11:08:30 2024
245 11:08:30.522136 output: Image 0 (kernel-1)
246 11:08:30.522202 output: Description:
247 11:08:30.522263 output: Created: Sun Mar 3 11:08:30 2024
248 11:08:30.522321 output: Type: Kernel Image
249 11:08:30.522380 output: Compression: lzma compressed
250 11:08:30.522439 output: Data Size: 12057697 Bytes = 11775.09 KiB = 11.50 MiB
251 11:08:30.522496 output: Architecture: AArch64
252 11:08:30.522553 output: OS: Linux
253 11:08:30.522609 output: Load Address: 0x00000000
254 11:08:30.522664 output: Entry Point: 0x00000000
255 11:08:30.522720 output: Hash algo: crc32
256 11:08:30.522777 output: Hash value: cf43f4f3
257 11:08:30.522843 output: Image 1 (fdt-1)
258 11:08:30.522900 output: Description: mt8192-asurada-spherion-r0
259 11:08:30.522954 output: Created: Sun Mar 3 11:08:30 2024
260 11:08:30.523006 output: Type: Flat Device Tree
261 11:08:30.523065 output: Compression: uncompressed
262 11:08:30.523117 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
263 11:08:30.523170 output: Architecture: AArch64
264 11:08:30.523222 output: Hash algo: crc32
265 11:08:30.523273 output: Hash value: cc4352de
266 11:08:30.523331 output: Image 2 (ramdisk-1)
267 11:08:30.523383 output: Description: unavailable
268 11:08:30.523435 output: Created: Sun Mar 3 11:08:30 2024
269 11:08:30.523488 output: Type: RAMDisk Image
270 11:08:30.523544 output: Compression: Unknown Compression
271 11:08:30.523597 output: Data Size: 17806600 Bytes = 17389.26 KiB = 16.98 MiB
272 11:08:30.523650 output: Architecture: AArch64
273 11:08:30.523747 output: OS: Linux
274 11:08:30.523805 output: Load Address: unavailable
275 11:08:30.523858 output: Entry Point: unavailable
276 11:08:30.523910 output: Hash algo: crc32
277 11:08:30.523962 output: Hash value: 9328d386
278 11:08:30.524013 output: Default Configuration: 'conf-1'
279 11:08:30.524071 output: Configuration 0 (conf-1)
280 11:08:30.524123 output: Description: mt8192-asurada-spherion-r0
281 11:08:30.524175 output: Kernel: kernel-1
282 11:08:30.524227 output: Init Ramdisk: ramdisk-1
283 11:08:30.524279 output: FDT: fdt-1
284 11:08:30.524336 output: Loadables: kernel-1
285 11:08:30.524388 output:
286 11:08:30.524594 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 11:08:30.524699 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 11:08:30.524810 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 11:08:30.524904 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:36) [common]
290 11:08:30.524993 No LXC device requested
291 11:08:30.525081 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 11:08:30.525167 start: 1.8 deploy-device-env (timeout 00:09:36) [common]
293 11:08:30.525246 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 11:08:30.525319 Checking files for TFTP limit of 4294967296 bytes.
295 11:08:30.525912 end: 1 tftp-deploy (duration 00:00:24) [common]
296 11:08:30.526017 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 11:08:30.526121 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 11:08:30.526247 substitutions:
299 11:08:30.526320 - {DTB}: 12925670/tftp-deploy-5ljo28bt/dtb/mt8192-asurada-spherion-r0.dtb
300 11:08:30.526390 - {INITRD}: 12925670/tftp-deploy-5ljo28bt/ramdisk/ramdisk.cpio.gz
301 11:08:30.526450 - {KERNEL}: 12925670/tftp-deploy-5ljo28bt/kernel/Image
302 11:08:30.526508 - {LAVA_MAC}: None
303 11:08:30.526572 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12925670/extract-nfsrootfs-f0qwj3q5
304 11:08:30.526630 - {NFS_SERVER_IP}: 192.168.201.1
305 11:08:30.526685 - {PRESEED_CONFIG}: None
306 11:08:30.526741 - {PRESEED_LOCAL}: None
307 11:08:30.526794 - {RAMDISK}: 12925670/tftp-deploy-5ljo28bt/ramdisk/ramdisk.cpio.gz
308 11:08:30.526854 - {ROOT_PART}: None
309 11:08:30.526908 - {ROOT}: None
310 11:08:30.526962 - {SERVER_IP}: 192.168.201.1
311 11:08:30.527015 - {TEE}: None
312 11:08:30.527074 Parsed boot commands:
313 11:08:30.527129 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 11:08:30.527319 Parsed boot commands: tftpboot 192.168.201.1 12925670/tftp-deploy-5ljo28bt/kernel/image.itb 12925670/tftp-deploy-5ljo28bt/kernel/cmdline
315 11:08:30.527408 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 11:08:30.527493 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 11:08:30.527593 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 11:08:30.527721 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 11:08:30.527799 Not connected, no need to disconnect.
320 11:08:30.527876 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 11:08:30.527958 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 11:08:30.528028 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
323 11:08:30.532022 Setting prompt string to ['lava-test: # ']
324 11:08:30.532407 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 11:08:30.532528 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 11:08:30.532634 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 11:08:30.532757 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 11:08:30.532987 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
329 11:08:35.661581 >> Command sent successfully.
330 11:08:35.664077 Returned 0 in 5 seconds
331 11:08:35.764441 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 11:08:35.764769 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 11:08:35.764868 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 11:08:35.764962 Setting prompt string to 'Starting depthcharge on Spherion...'
336 11:08:35.765032 Changing prompt to 'Starting depthcharge on Spherion...'
337 11:08:35.765100 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 11:08:35.765373 [Enter `^Ec?' for help]
339 11:08:35.937832
340 11:08:35.937967
341 11:08:35.938038 F0: 102B 0000
342 11:08:35.938105
343 11:08:35.941669 F3: 1001 0000 [0200]
344 11:08:35.941748
345 11:08:35.941814 F3: 1001 0000
346 11:08:35.941876
347 11:08:35.941941 F7: 102D 0000
348 11:08:35.941999
349 11:08:35.944716 F1: 0000 0000
350 11:08:35.944788
351 11:08:35.944849 V0: 0000 0000 [0001]
352 11:08:35.944915
353 11:08:35.948510 00: 0007 8000
354 11:08:35.948585
355 11:08:35.948652 01: 0000 0000
356 11:08:35.948713
357 11:08:35.951342 BP: 0C00 0209 [0000]
358 11:08:35.951418
359 11:08:35.951479 G0: 1182 0000
360 11:08:35.951536
361 11:08:35.955478 EC: 0000 0021 [4000]
362 11:08:35.955550
363 11:08:35.955611 S7: 0000 0000 [0000]
364 11:08:35.955684
365 11:08:35.958588 CC: 0000 0000 [0001]
366 11:08:35.958670
367 11:08:35.958734 T0: 0000 0040 [010F]
368 11:08:35.958794
369 11:08:35.958851 Jump to BL
370 11:08:35.958913
371 11:08:35.985042
372 11:08:35.985124
373 11:08:35.985197
374 11:08:35.992264 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 11:08:35.996692 ARM64: Exception handlers installed.
376 11:08:35.999965 ARM64: Testing exception
377 11:08:36.003316 ARM64: Done test exception
378 11:08:36.009915 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 11:08:36.020144 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 11:08:36.026734 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 11:08:36.036822 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 11:08:36.043379 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 11:08:36.050386 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 11:08:36.062043 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 11:08:36.069336 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 11:08:36.087956 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 11:08:36.091386 WDT: Last reset was cold boot
388 11:08:36.094905 SPI1(PAD0) initialized at 2873684 Hz
389 11:08:36.098314 SPI5(PAD0) initialized at 992727 Hz
390 11:08:36.101269 VBOOT: Loading verstage.
391 11:08:36.108089 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 11:08:36.111326 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 11:08:36.114834 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 11:08:36.117583 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 11:08:36.125573 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 11:08:36.132924 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 11:08:36.142919 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
398 11:08:36.142998
399 11:08:36.143067
400 11:08:36.152937 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 11:08:36.156066 ARM64: Exception handlers installed.
402 11:08:36.159637 ARM64: Testing exception
403 11:08:36.159722 ARM64: Done test exception
404 11:08:36.166082 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 11:08:36.170133 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 11:08:36.184440 Probing TPM: . done!
407 11:08:36.184521 TPM ready after 0 ms
408 11:08:36.191384 Connected to device vid:did:rid of 1ae0:0028:00
409 11:08:36.253664 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
410 11:08:36.253763 Initialized TPM device CR50 revision 0
411 11:08:36.265853 tlcl_send_startup: Startup return code is 0
412 11:08:36.265938 TPM: setup succeeded
413 11:08:36.277115 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 11:08:36.285431 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 11:08:36.292154 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 11:08:36.307454 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 11:08:36.310949 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 11:08:36.318227 in-header: 03 07 00 00 08 00 00 00
419 11:08:36.321716 in-data: aa e4 47 04 13 02 00 00
420 11:08:36.325209 Chrome EC: UHEPI supported
421 11:08:36.332568 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 11:08:36.336230 in-header: 03 ad 00 00 08 00 00 00
423 11:08:36.339908 in-data: 00 20 20 08 00 00 00 00
424 11:08:36.340019 Phase 1
425 11:08:36.343414 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 11:08:36.350295 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 11:08:36.353991 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 11:08:36.357699 Recovery requested (1009000e)
429 11:08:36.367062 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 11:08:36.372810 tlcl_extend: response is 0
431 11:08:36.384151 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 11:08:36.387797 tlcl_extend: response is 0
433 11:08:36.394857 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 11:08:36.414411 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
435 11:08:36.421014 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 11:08:36.421091
437 11:08:36.421156
438 11:08:36.431559 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 11:08:36.435228 ARM64: Exception handlers installed.
440 11:08:36.435307 ARM64: Testing exception
441 11:08:36.438642 ARM64: Done test exception
442 11:08:36.459970 pmic_efuse_setting: Set efuses in 11 msecs
443 11:08:36.463698 pmwrap_interface_init: Select PMIF_VLD_RDY
444 11:08:36.470639 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 11:08:36.473390 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 11:08:36.477072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 11:08:36.484820 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 11:08:36.488319 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 11:08:36.495125 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 11:08:36.499065 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 11:08:36.503377 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 11:08:36.506370 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 11:08:36.513412 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 11:08:36.517203 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 11:08:36.520649 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 11:08:36.524151 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 11:08:36.531636 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 11:08:36.539095 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 11:08:36.542737 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 11:08:36.550805 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 11:08:36.553631 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 11:08:36.561025 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 11:08:36.568416 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 11:08:36.572156 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 11:08:36.575647 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 11:08:36.583176 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 11:08:36.586488 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 11:08:36.594016 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 11:08:36.601512 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 11:08:36.604918 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 11:08:36.608200 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 11:08:36.615928 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 11:08:36.619557 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 11:08:36.623142 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 11:08:36.630412 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 11:08:36.634104 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 11:08:36.637421 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 11:08:36.644492 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 11:08:36.648091 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 11:08:36.655775 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 11:08:36.659258 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 11:08:36.663053 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 11:08:36.667141 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 11:08:36.670307 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 11:08:36.678254 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 11:08:36.681210 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 11:08:36.685274 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 11:08:36.688576 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 11:08:36.692673 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 11:08:36.700072 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 11:08:36.703253 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 11:08:36.707332 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 11:08:36.710589 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 11:08:36.714005 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 11:08:36.721931 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 11:08:36.732646 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 11:08:36.736218 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 11:08:36.743273 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 11:08:36.750543 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 11:08:36.757964 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 11:08:36.761614 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 11:08:36.765397 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 11:08:36.773602 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x1
504 11:08:36.776685 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 11:08:36.784824 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
506 11:08:36.788577 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 11:08:36.797556 [RTC]rtc_get_frequency_meter,154: input=15, output=834
508 11:08:36.806964 [RTC]rtc_get_frequency_meter,154: input=7, output=707
509 11:08:36.815921 [RTC]rtc_get_frequency_meter,154: input=11, output=771
510 11:08:36.825879 [RTC]rtc_get_frequency_meter,154: input=13, output=803
511 11:08:36.835755 [RTC]rtc_get_frequency_meter,154: input=12, output=787
512 11:08:36.844898 [RTC]rtc_get_frequency_meter,154: input=12, output=787
513 11:08:36.854433 [RTC]rtc_get_frequency_meter,154: input=13, output=803
514 11:08:36.857470 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
515 11:08:36.865202 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
516 11:08:36.868948 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 11:08:36.872120 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
518 11:08:36.875800 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 11:08:36.879341 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
520 11:08:36.883139 ADC[4]: Raw value=902661 ID=7
521 11:08:36.887482 ADC[3]: Raw value=213282 ID=1
522 11:08:36.887598 RAM Code: 0x71
523 11:08:36.890712 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 11:08:36.898335 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 11:08:36.905282 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 11:08:36.912340 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 11:08:36.916523 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 11:08:36.919869 in-header: 03 07 00 00 08 00 00 00
529 11:08:36.923388 in-data: aa e4 47 04 13 02 00 00
530 11:08:36.923472 Chrome EC: UHEPI supported
531 11:08:36.930987 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 11:08:36.934304 in-header: 03 ed 00 00 08 00 00 00
533 11:08:36.938183 in-data: 80 20 60 08 00 00 00 00
534 11:08:36.941533 MRC: failed to locate region type 0.
535 11:08:36.948745 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 11:08:36.948830 DRAM-K: Running full calibration
537 11:08:36.956262 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 11:08:36.960181 header.status = 0x0
539 11:08:36.964179 header.version = 0x6 (expected: 0x6)
540 11:08:36.964262 header.size = 0xd00 (expected: 0xd00)
541 11:08:36.968035 header.flags = 0x0
542 11:08:36.974683 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 11:08:36.991452 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
544 11:08:36.998508 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 11:08:37.001865 dram_init: ddr_geometry: 2
546 11:08:37.001953 [EMI] MDL number = 2
547 11:08:37.006051 [EMI] Get MDL freq = 0
548 11:08:37.006136 dram_init: ddr_type: 0
549 11:08:37.009357 is_discrete_lpddr4: 1
550 11:08:37.013017 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 11:08:37.013101
552 11:08:37.013168
553 11:08:37.016391 [Bian_co] ETT version 0.0.0.1
554 11:08:37.020333 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 11:08:37.020417
556 11:08:37.023707 dramc_set_vcore_voltage set vcore to 650000
557 11:08:37.027190 Read voltage for 800, 4
558 11:08:37.027275 Vio18 = 0
559 11:08:37.027342 Vcore = 650000
560 11:08:37.027405 Vdram = 0
561 11:08:37.031271 Vddq = 0
562 11:08:37.031354 Vmddr = 0
563 11:08:37.034487 dram_init: config_dvfs: 1
564 11:08:37.038186 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 11:08:37.041986 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 11:08:37.045955 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
567 11:08:37.052700 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
568 11:08:37.056404 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
569 11:08:37.059996 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
570 11:08:37.060081 MEM_TYPE=3, freq_sel=18
571 11:08:37.064040 sv_algorithm_assistance_LP4_1600
572 11:08:37.067429 ============ PULL DRAM RESETB DOWN ============
573 11:08:37.070992 ========== PULL DRAM RESETB DOWN end =========
574 11:08:37.077679 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 11:08:37.081397 ===================================
576 11:08:37.081481 LPDDR4 DRAM CONFIGURATION
577 11:08:37.084587 ===================================
578 11:08:37.087600 EX_ROW_EN[0] = 0x0
579 11:08:37.091099 EX_ROW_EN[1] = 0x0
580 11:08:37.091185 LP4Y_EN = 0x0
581 11:08:37.094339 WORK_FSP = 0x0
582 11:08:37.094423 WL = 0x2
583 11:08:37.097599 RL = 0x2
584 11:08:37.097683 BL = 0x2
585 11:08:37.100860 RPST = 0x0
586 11:08:37.100976 RD_PRE = 0x0
587 11:08:37.104129 WR_PRE = 0x1
588 11:08:37.104213 WR_PST = 0x0
589 11:08:37.107525 DBI_WR = 0x0
590 11:08:37.107609 DBI_RD = 0x0
591 11:08:37.111103 OTF = 0x1
592 11:08:37.114015 ===================================
593 11:08:37.117618 ===================================
594 11:08:37.117705 ANA top config
595 11:08:37.120697 ===================================
596 11:08:37.124013 DLL_ASYNC_EN = 0
597 11:08:37.127549 ALL_SLAVE_EN = 1
598 11:08:37.130925 NEW_RANK_MODE = 1
599 11:08:37.131010 DLL_IDLE_MODE = 1
600 11:08:37.134501 LP45_APHY_COMB_EN = 1
601 11:08:37.137188 TX_ODT_DIS = 1
602 11:08:37.140682 NEW_8X_MODE = 1
603 11:08:37.144202 ===================================
604 11:08:37.147596 ===================================
605 11:08:37.150669 data_rate = 1600
606 11:08:37.150753 CKR = 1
607 11:08:37.153762 DQ_P2S_RATIO = 8
608 11:08:37.156962 ===================================
609 11:08:37.160402 CA_P2S_RATIO = 8
610 11:08:37.163701 DQ_CA_OPEN = 0
611 11:08:37.167376 DQ_SEMI_OPEN = 0
612 11:08:37.170790 CA_SEMI_OPEN = 0
613 11:08:37.170874 CA_FULL_RATE = 0
614 11:08:37.174128 DQ_CKDIV4_EN = 1
615 11:08:37.177579 CA_CKDIV4_EN = 1
616 11:08:37.180413 CA_PREDIV_EN = 0
617 11:08:37.183793 PH8_DLY = 0
618 11:08:37.186665 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 11:08:37.186749 DQ_AAMCK_DIV = 4
620 11:08:37.189926 CA_AAMCK_DIV = 4
621 11:08:37.193681 CA_ADMCK_DIV = 4
622 11:08:37.196561 DQ_TRACK_CA_EN = 0
623 11:08:37.200362 CA_PICK = 800
624 11:08:37.203279 CA_MCKIO = 800
625 11:08:37.206607 MCKIO_SEMI = 0
626 11:08:37.210070 PLL_FREQ = 3068
627 11:08:37.210150 DQ_UI_PI_RATIO = 32
628 11:08:37.214012 CA_UI_PI_RATIO = 0
629 11:08:37.217373 ===================================
630 11:08:37.220832 ===================================
631 11:08:37.224591 memory_type:LPDDR4
632 11:08:37.224684 GP_NUM : 10
633 11:08:37.228438 SRAM_EN : 1
634 11:08:37.228510 MD32_EN : 0
635 11:08:37.232081 ===================================
636 11:08:37.236000 [ANA_INIT] >>>>>>>>>>>>>>
637 11:08:37.239427 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 11:08:37.243391 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 11:08:37.243491 ===================================
640 11:08:37.246690 data_rate = 1600,PCW = 0X7600
641 11:08:37.249962 ===================================
642 11:08:37.253348 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 11:08:37.260071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 11:08:37.263706 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 11:08:37.270157 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 11:08:37.273473 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 11:08:37.276515 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 11:08:37.276626 [ANA_INIT] flow start
649 11:08:37.279907 [ANA_INIT] PLL >>>>>>>>
650 11:08:37.283279 [ANA_INIT] PLL <<<<<<<<
651 11:08:37.286417 [ANA_INIT] MIDPI >>>>>>>>
652 11:08:37.286501 [ANA_INIT] MIDPI <<<<<<<<
653 11:08:37.290078 [ANA_INIT] DLL >>>>>>>>
654 11:08:37.293483 [ANA_INIT] flow end
655 11:08:37.297056 ============ LP4 DIFF to SE enter ============
656 11:08:37.299884 ============ LP4 DIFF to SE exit ============
657 11:08:37.303164 [ANA_INIT] <<<<<<<<<<<<<
658 11:08:37.306282 [Flow] Enable top DCM control >>>>>
659 11:08:37.309717 [Flow] Enable top DCM control <<<<<
660 11:08:37.312965 Enable DLL master slave shuffle
661 11:08:37.316331 ==============================================================
662 11:08:37.320045 Gating Mode config
663 11:08:37.323570 ==============================================================
664 11:08:37.327035 Config description:
665 11:08:37.336609 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 11:08:37.342890 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 11:08:37.346358 SELPH_MODE 0: By rank 1: By Phase
668 11:08:37.353149 ==============================================================
669 11:08:37.356081 GAT_TRACK_EN = 1
670 11:08:37.359387 RX_GATING_MODE = 2
671 11:08:37.362893 RX_GATING_TRACK_MODE = 2
672 11:08:37.365880 SELPH_MODE = 1
673 11:08:37.369446 PICG_EARLY_EN = 1
674 11:08:37.373017 VALID_LAT_VALUE = 1
675 11:08:37.376141 ==============================================================
676 11:08:37.379890 Enter into Gating configuration >>>>
677 11:08:37.382752 Exit from Gating configuration <<<<
678 11:08:37.385791 Enter into DVFS_PRE_config >>>>>
679 11:08:37.399260 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 11:08:37.399350 Exit from DVFS_PRE_config <<<<<
681 11:08:37.402535 Enter into PICG configuration >>>>
682 11:08:37.405611 Exit from PICG configuration <<<<
683 11:08:37.409094 [RX_INPUT] configuration >>>>>
684 11:08:37.412147 [RX_INPUT] configuration <<<<<
685 11:08:37.418685 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 11:08:37.422219 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 11:08:37.429096 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 11:08:37.436121 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 11:08:37.442742 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 11:08:37.449413 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 11:08:37.453029 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 11:08:37.455867 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 11:08:37.459137 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 11:08:37.466150 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 11:08:37.469018 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 11:08:37.472384 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 11:08:37.476034 ===================================
698 11:08:37.479299 LPDDR4 DRAM CONFIGURATION
699 11:08:37.482152 ===================================
700 11:08:37.482236 EX_ROW_EN[0] = 0x0
701 11:08:37.485465 EX_ROW_EN[1] = 0x0
702 11:08:37.485548 LP4Y_EN = 0x0
703 11:08:37.488846 WORK_FSP = 0x0
704 11:08:37.492612 WL = 0x2
705 11:08:37.492691 RL = 0x2
706 11:08:37.495432 BL = 0x2
707 11:08:37.495533 RPST = 0x0
708 11:08:37.499072 RD_PRE = 0x0
709 11:08:37.499144 WR_PRE = 0x1
710 11:08:37.502184 WR_PST = 0x0
711 11:08:37.502258 DBI_WR = 0x0
712 11:08:37.505228 DBI_RD = 0x0
713 11:08:37.505307 OTF = 0x1
714 11:08:37.509355 ===================================
715 11:08:37.512143 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 11:08:37.518696 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 11:08:37.522248 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 11:08:37.525458 ===================================
719 11:08:37.528933 LPDDR4 DRAM CONFIGURATION
720 11:08:37.532396 ===================================
721 11:08:37.532471 EX_ROW_EN[0] = 0x10
722 11:08:37.535478 EX_ROW_EN[1] = 0x0
723 11:08:37.535546 LP4Y_EN = 0x0
724 11:08:37.538729 WORK_FSP = 0x0
725 11:08:37.541924 WL = 0x2
726 11:08:37.542001 RL = 0x2
727 11:08:37.545430 BL = 0x2
728 11:08:37.545505 RPST = 0x0
729 11:08:37.548710 RD_PRE = 0x0
730 11:08:37.548788 WR_PRE = 0x1
731 11:08:37.551932 WR_PST = 0x0
732 11:08:37.552009 DBI_WR = 0x0
733 11:08:37.555173 DBI_RD = 0x0
734 11:08:37.555247 OTF = 0x1
735 11:08:37.558498 ===================================
736 11:08:37.565026 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 11:08:37.569528 nWR fixed to 40
738 11:08:37.572949 [ModeRegInit_LP4] CH0 RK0
739 11:08:37.573027 [ModeRegInit_LP4] CH0 RK1
740 11:08:37.575507 [ModeRegInit_LP4] CH1 RK0
741 11:08:37.579549 [ModeRegInit_LP4] CH1 RK1
742 11:08:37.579658 match AC timing 13
743 11:08:37.585644 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 11:08:37.589169 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 11:08:37.592123 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 11:08:37.599077 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 11:08:37.602053 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 11:08:37.605537 [EMI DOE] emi_dcm 0
749 11:08:37.609634 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 11:08:37.609713 ==
751 11:08:37.612230 Dram Type= 6, Freq= 0, CH_0, rank 0
752 11:08:37.615537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 11:08:37.615640 ==
754 11:08:37.622115 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 11:08:37.628738 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 11:08:37.636877 [CA 0] Center 37 (7~68) winsize 62
757 11:08:37.640608 [CA 1] Center 37 (7~68) winsize 62
758 11:08:37.643257 [CA 2] Center 34 (4~65) winsize 62
759 11:08:37.646308 [CA 3] Center 34 (4~65) winsize 62
760 11:08:37.649681 [CA 4] Center 33 (3~64) winsize 62
761 11:08:37.653589 [CA 5] Center 33 (3~64) winsize 62
762 11:08:37.653665
763 11:08:37.656407 [CmdBusTrainingLP45] Vref(ca) range 1: 32
764 11:08:37.656478
765 11:08:37.659893 [CATrainingPosCal] consider 1 rank data
766 11:08:37.663528 u2DelayCellTimex100 = 270/100 ps
767 11:08:37.667022 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
768 11:08:37.673594 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
769 11:08:37.676187 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
770 11:08:37.679736 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
771 11:08:37.682859 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
772 11:08:37.686356 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
773 11:08:37.686431
774 11:08:37.689968 CA PerBit enable=1, Macro0, CA PI delay=33
775 11:08:37.690039
776 11:08:37.692782 [CBTSetCACLKResult] CA Dly = 33
777 11:08:37.692859 CS Dly: 6 (0~37)
778 11:08:37.696074 ==
779 11:08:37.699821 Dram Type= 6, Freq= 0, CH_0, rank 1
780 11:08:37.702681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 11:08:37.702757 ==
782 11:08:37.706249 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 11:08:37.713119 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 11:08:37.723226 [CA 0] Center 37 (6~68) winsize 63
785 11:08:37.725936 [CA 1] Center 37 (7~68) winsize 62
786 11:08:37.729104 [CA 2] Center 34 (4~65) winsize 62
787 11:08:37.732962 [CA 3] Center 34 (4~65) winsize 62
788 11:08:37.735944 [CA 4] Center 33 (3~64) winsize 62
789 11:08:37.739063 [CA 5] Center 33 (2~64) winsize 63
790 11:08:37.739135
791 11:08:37.742509 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 11:08:37.742583
793 11:08:37.745744 [CATrainingPosCal] consider 2 rank data
794 11:08:37.749177 u2DelayCellTimex100 = 270/100 ps
795 11:08:37.752792 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
796 11:08:37.759352 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
797 11:08:37.762708 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
798 11:08:37.765937 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
799 11:08:37.769060 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
800 11:08:37.772429 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 11:08:37.772502
802 11:08:37.775905 CA PerBit enable=1, Macro0, CA PI delay=33
803 11:08:37.776007
804 11:08:37.779338 [CBTSetCACLKResult] CA Dly = 33
805 11:08:37.779411 CS Dly: 6 (0~38)
806 11:08:37.782760
807 11:08:37.786136 ----->DramcWriteLeveling(PI) begin...
808 11:08:37.786212 ==
809 11:08:37.788859 Dram Type= 6, Freq= 0, CH_0, rank 0
810 11:08:37.792673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:08:37.792759 ==
812 11:08:37.796731 Write leveling (Byte 0): 34 => 34
813 11:08:37.799963 Write leveling (Byte 1): 31 => 31
814 11:08:37.800047 DramcWriteLeveling(PI) end<-----
815 11:08:37.800114
816 11:08:37.803426 ==
817 11:08:37.803510 Dram Type= 6, Freq= 0, CH_0, rank 0
818 11:08:37.807699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 11:08:37.810428 ==
820 11:08:37.810512 [Gating] SW mode calibration
821 11:08:37.820328 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 11:08:37.825136 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 11:08:37.828034 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 11:08:37.834346 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
825 11:08:37.837764 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 11:08:37.840641 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
827 11:08:37.847391 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:08:37.850790 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 11:08:37.854191 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 11:08:37.860586 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 11:08:37.864152 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 11:08:37.867108 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 11:08:37.873924 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 11:08:37.877213 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 11:08:37.880192 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 11:08:37.887005 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 11:08:37.890876 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 11:08:37.893787 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 11:08:37.900581 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 11:08:37.903976 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
841 11:08:37.907630 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
842 11:08:37.913646 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 11:08:37.917135 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 11:08:37.920458 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 11:08:37.927391 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 11:08:37.930497 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 11:08:37.933436 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 11:08:37.939989 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 11:08:37.943234 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
850 11:08:37.946685 0 9 12 | B1->B0 | 2b2a 3434 | 1 1 | (0 0) (1 1)
851 11:08:37.950002 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 11:08:37.956875 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 11:08:37.960139 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 11:08:37.963392 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 11:08:37.969682 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 11:08:37.973223 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
857 11:08:37.976844 0 10 8 | B1->B0 | 3232 2b2b | 0 0 | (0 1) (1 0)
858 11:08:37.983127 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
859 11:08:37.986607 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:08:37.990296 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:08:37.996283 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:08:37.999915 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:08:38.003248 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:08:38.009346 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:08:38.012712 0 11 8 | B1->B0 | 2424 3939 | 0 0 | (0 0) (0 0)
866 11:08:38.016293 0 11 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
867 11:08:38.023027 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 11:08:38.026605 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 11:08:38.029514 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 11:08:38.036168 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 11:08:38.039286 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 11:08:38.042711 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
873 11:08:38.049517 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
874 11:08:38.052345 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
875 11:08:38.055569 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 11:08:38.062346 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 11:08:38.066452 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 11:08:38.068831 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 11:08:38.075777 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 11:08:38.078923 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 11:08:38.082606 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 11:08:38.088791 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 11:08:38.092075 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 11:08:38.095606 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 11:08:38.102463 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 11:08:38.105294 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 11:08:38.108686 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 11:08:38.115352 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 11:08:38.118923 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
890 11:08:38.122195 Total UI for P1: 0, mck2ui 16
891 11:08:38.125725 best dqsien dly found for B0: ( 0, 14, 6)
892 11:08:38.128836 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 11:08:38.132385 Total UI for P1: 0, mck2ui 16
894 11:08:38.135460 best dqsien dly found for B1: ( 0, 14, 10)
895 11:08:38.138556 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
896 11:08:38.142674 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
897 11:08:38.142749
898 11:08:38.145180 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
899 11:08:38.151739 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
900 11:08:38.151824 [Gating] SW calibration Done
901 11:08:38.151891 ==
902 11:08:38.155147 Dram Type= 6, Freq= 0, CH_0, rank 0
903 11:08:38.162285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 11:08:38.162369 ==
905 11:08:38.162434 RX Vref Scan: 0
906 11:08:38.162495
907 11:08:38.165660 RX Vref 0 -> 0, step: 1
908 11:08:38.165747
909 11:08:38.168525 RX Delay -130 -> 252, step: 16
910 11:08:38.171934 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
911 11:08:38.175445 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
912 11:08:38.178637 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
913 11:08:38.184954 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
914 11:08:38.188317 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
915 11:08:38.191610 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
916 11:08:38.195628 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
917 11:08:38.198165 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
918 11:08:38.205039 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
919 11:08:38.208223 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
920 11:08:38.211644 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
921 11:08:38.215389 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
922 11:08:38.218809 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
923 11:08:38.224692 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
924 11:08:38.228139 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
925 11:08:38.231378 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
926 11:08:38.231462 ==
927 11:08:38.234608 Dram Type= 6, Freq= 0, CH_0, rank 0
928 11:08:38.238270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 11:08:38.242062 ==
930 11:08:38.242145 DQS Delay:
931 11:08:38.242213 DQS0 = 0, DQS1 = 0
932 11:08:38.244849 DQM Delay:
933 11:08:38.244933 DQM0 = 84, DQM1 = 71
934 11:08:38.248137 DQ Delay:
935 11:08:38.248221 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
936 11:08:38.251443 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
937 11:08:38.254473 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
938 11:08:38.258485 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
939 11:08:38.261295
940 11:08:38.261405
941 11:08:38.261505 ==
942 11:08:38.264797 Dram Type= 6, Freq= 0, CH_0, rank 0
943 11:08:38.268179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 11:08:38.268263 ==
945 11:08:38.268330
946 11:08:38.268390
947 11:08:38.271586 TX Vref Scan disable
948 11:08:38.271676 == TX Byte 0 ==
949 11:08:38.277845 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
950 11:08:38.281119 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
951 11:08:38.281230 == TX Byte 1 ==
952 11:08:38.287623 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
953 11:08:38.291364 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
954 11:08:38.291467 ==
955 11:08:38.294726 Dram Type= 6, Freq= 0, CH_0, rank 0
956 11:08:38.297670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 11:08:38.297755 ==
958 11:08:38.312274 TX Vref=22, minBit 13, minWin=26, winSum=435
959 11:08:38.314881 TX Vref=24, minBit 3, minWin=27, winSum=445
960 11:08:38.318391 TX Vref=26, minBit 3, minWin=27, winSum=446
961 11:08:38.321701 TX Vref=28, minBit 7, minWin=27, winSum=450
962 11:08:38.325055 TX Vref=30, minBit 10, minWin=27, winSum=450
963 11:08:38.331584 TX Vref=32, minBit 9, minWin=27, winSum=447
964 11:08:38.335132 [TxChooseVref] Worse bit 7, Min win 27, Win sum 450, Final Vref 28
965 11:08:38.335210
966 11:08:38.338527 Final TX Range 1 Vref 28
967 11:08:38.338604
968 11:08:38.338668 ==
969 11:08:38.341640 Dram Type= 6, Freq= 0, CH_0, rank 0
970 11:08:38.344640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 11:08:38.348581 ==
972 11:08:38.348657
973 11:08:38.348720
974 11:08:38.348779 TX Vref Scan disable
975 11:08:38.351791 == TX Byte 0 ==
976 11:08:38.355475 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
977 11:08:38.361927 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
978 11:08:38.362006 == TX Byte 1 ==
979 11:08:38.364987 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 11:08:38.371661 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 11:08:38.371770
982 11:08:38.371834 [DATLAT]
983 11:08:38.371897 Freq=800, CH0 RK0
984 11:08:38.371956
985 11:08:38.374668 DATLAT Default: 0xa
986 11:08:38.374736 0, 0xFFFF, sum = 0
987 11:08:38.378271 1, 0xFFFF, sum = 0
988 11:08:38.381220 2, 0xFFFF, sum = 0
989 11:08:38.381292 3, 0xFFFF, sum = 0
990 11:08:38.384646 4, 0xFFFF, sum = 0
991 11:08:38.384720 5, 0xFFFF, sum = 0
992 11:08:38.388297 6, 0xFFFF, sum = 0
993 11:08:38.388381 7, 0xFFFF, sum = 0
994 11:08:38.391261 8, 0xFFFF, sum = 0
995 11:08:38.391336 9, 0x0, sum = 1
996 11:08:38.394697 10, 0x0, sum = 2
997 11:08:38.394824 11, 0x0, sum = 3
998 11:08:38.398045 12, 0x0, sum = 4
999 11:08:38.398154 best_step = 10
1000 11:08:38.398250
1001 11:08:38.398343 ==
1002 11:08:38.401432 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 11:08:38.404374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 11:08:38.404453 ==
1005 11:08:38.408035 RX Vref Scan: 1
1006 11:08:38.408110
1007 11:08:38.410905 Set Vref Range= 32 -> 127
1008 11:08:38.410985
1009 11:08:38.411049 RX Vref 32 -> 127, step: 1
1010 11:08:38.411134
1011 11:08:38.414849 RX Delay -111 -> 252, step: 8
1012 11:08:38.414936
1013 11:08:38.417589 Set Vref, RX VrefLevel [Byte0]: 32
1014 11:08:38.420956 [Byte1]: 32
1015 11:08:38.424616
1016 11:08:38.424698 Set Vref, RX VrefLevel [Byte0]: 33
1017 11:08:38.428220 [Byte1]: 33
1018 11:08:38.432760
1019 11:08:38.432832 Set Vref, RX VrefLevel [Byte0]: 34
1020 11:08:38.435648 [Byte1]: 34
1021 11:08:38.440110
1022 11:08:38.440183 Set Vref, RX VrefLevel [Byte0]: 35
1023 11:08:38.443300 [Byte1]: 35
1024 11:08:38.447548
1025 11:08:38.447654 Set Vref, RX VrefLevel [Byte0]: 36
1026 11:08:38.451196 [Byte1]: 36
1027 11:08:38.455133
1028 11:08:38.455210 Set Vref, RX VrefLevel [Byte0]: 37
1029 11:08:38.458566 [Byte1]: 37
1030 11:08:38.463283
1031 11:08:38.463358 Set Vref, RX VrefLevel [Byte0]: 38
1032 11:08:38.466464 [Byte1]: 38
1033 11:08:38.470691
1034 11:08:38.470764 Set Vref, RX VrefLevel [Byte0]: 39
1035 11:08:38.474096 [Byte1]: 39
1036 11:08:38.478303
1037 11:08:38.478378 Set Vref, RX VrefLevel [Byte0]: 40
1038 11:08:38.481982 [Byte1]: 40
1039 11:08:38.485494
1040 11:08:38.489217 Set Vref, RX VrefLevel [Byte0]: 41
1041 11:08:38.489288 [Byte1]: 41
1042 11:08:38.493773
1043 11:08:38.493849 Set Vref, RX VrefLevel [Byte0]: 42
1044 11:08:38.497017 [Byte1]: 42
1045 11:08:38.500850
1046 11:08:38.500975 Set Vref, RX VrefLevel [Byte0]: 43
1047 11:08:38.504443 [Byte1]: 43
1048 11:08:38.509424
1049 11:08:38.509529 Set Vref, RX VrefLevel [Byte0]: 44
1050 11:08:38.512212 [Byte1]: 44
1051 11:08:38.516550
1052 11:08:38.516667 Set Vref, RX VrefLevel [Byte0]: 45
1053 11:08:38.519708 [Byte1]: 45
1054 11:08:38.524457
1055 11:08:38.524584 Set Vref, RX VrefLevel [Byte0]: 46
1056 11:08:38.527757 [Byte1]: 46
1057 11:08:38.531804
1058 11:08:38.531880 Set Vref, RX VrefLevel [Byte0]: 47
1059 11:08:38.535098 [Byte1]: 47
1060 11:08:38.539981
1061 11:08:38.540065 Set Vref, RX VrefLevel [Byte0]: 48
1062 11:08:38.543256 [Byte1]: 48
1063 11:08:38.547530
1064 11:08:38.547616 Set Vref, RX VrefLevel [Byte0]: 49
1065 11:08:38.550239 [Byte1]: 49
1066 11:08:38.554524
1067 11:08:38.554601 Set Vref, RX VrefLevel [Byte0]: 50
1068 11:08:38.557631 [Byte1]: 50
1069 11:08:38.562144
1070 11:08:38.562216 Set Vref, RX VrefLevel [Byte0]: 51
1071 11:08:38.565589 [Byte1]: 51
1072 11:08:38.570452
1073 11:08:38.570521 Set Vref, RX VrefLevel [Byte0]: 52
1074 11:08:38.572879 [Byte1]: 52
1075 11:08:38.577356
1076 11:08:38.577428 Set Vref, RX VrefLevel [Byte0]: 53
1077 11:08:38.580693 [Byte1]: 53
1078 11:08:38.585444
1079 11:08:38.585519 Set Vref, RX VrefLevel [Byte0]: 54
1080 11:08:38.588377 [Byte1]: 54
1081 11:08:38.592831
1082 11:08:38.592903 Set Vref, RX VrefLevel [Byte0]: 55
1083 11:08:38.596411 [Byte1]: 55
1084 11:08:38.600210
1085 11:08:38.600283 Set Vref, RX VrefLevel [Byte0]: 56
1086 11:08:38.603448 [Byte1]: 56
1087 11:08:38.608573
1088 11:08:38.608677 Set Vref, RX VrefLevel [Byte0]: 57
1089 11:08:38.611364 [Byte1]: 57
1090 11:08:38.615700
1091 11:08:38.615786 Set Vref, RX VrefLevel [Byte0]: 58
1092 11:08:38.619114 [Byte1]: 58
1093 11:08:38.623511
1094 11:08:38.623617 Set Vref, RX VrefLevel [Byte0]: 59
1095 11:08:38.626740 [Byte1]: 59
1096 11:08:38.630945
1097 11:08:38.631016 Set Vref, RX VrefLevel [Byte0]: 60
1098 11:08:38.635187 [Byte1]: 60
1099 11:08:38.638897
1100 11:08:38.638967 Set Vref, RX VrefLevel [Byte0]: 61
1101 11:08:38.642018 [Byte1]: 61
1102 11:08:38.646161
1103 11:08:38.646232 Set Vref, RX VrefLevel [Byte0]: 62
1104 11:08:38.649812 [Byte1]: 62
1105 11:08:38.654014
1106 11:08:38.654088 Set Vref, RX VrefLevel [Byte0]: 63
1107 11:08:38.657731 [Byte1]: 63
1108 11:08:38.661686
1109 11:08:38.661758 Set Vref, RX VrefLevel [Byte0]: 64
1110 11:08:38.664907 [Byte1]: 64
1111 11:08:38.669560
1112 11:08:38.669630 Set Vref, RX VrefLevel [Byte0]: 65
1113 11:08:38.672273 [Byte1]: 65
1114 11:08:38.676995
1115 11:08:38.677069 Set Vref, RX VrefLevel [Byte0]: 66
1116 11:08:38.680661 [Byte1]: 66
1117 11:08:38.684633
1118 11:08:38.684737 Set Vref, RX VrefLevel [Byte0]: 67
1119 11:08:38.687539 [Byte1]: 67
1120 11:08:38.692445
1121 11:08:38.692516 Set Vref, RX VrefLevel [Byte0]: 68
1122 11:08:38.695600 [Byte1]: 68
1123 11:08:38.699762
1124 11:08:38.699835 Set Vref, RX VrefLevel [Byte0]: 69
1125 11:08:38.702926 [Byte1]: 69
1126 11:08:38.707203
1127 11:08:38.707274 Set Vref, RX VrefLevel [Byte0]: 70
1128 11:08:38.711037 [Byte1]: 70
1129 11:08:38.715287
1130 11:08:38.715360 Set Vref, RX VrefLevel [Byte0]: 71
1131 11:08:38.718634 [Byte1]: 71
1132 11:08:38.722844
1133 11:08:38.722945 Set Vref, RX VrefLevel [Byte0]: 72
1134 11:08:38.725758 [Byte1]: 72
1135 11:08:38.730919
1136 11:08:38.731053 Set Vref, RX VrefLevel [Byte0]: 73
1137 11:08:38.733912 [Byte1]: 73
1138 11:08:38.738269
1139 11:08:38.738350 Set Vref, RX VrefLevel [Byte0]: 74
1140 11:08:38.741634 [Byte1]: 74
1141 11:08:38.745817
1142 11:08:38.745898 Set Vref, RX VrefLevel [Byte0]: 75
1143 11:08:38.748856 [Byte1]: 75
1144 11:08:38.753237
1145 11:08:38.753319 Set Vref, RX VrefLevel [Byte0]: 76
1146 11:08:38.756610 [Byte1]: 76
1147 11:08:38.760683
1148 11:08:38.760764 Set Vref, RX VrefLevel [Byte0]: 77
1149 11:08:38.764288 [Byte1]: 77
1150 11:08:38.768519
1151 11:08:38.768600 Set Vref, RX VrefLevel [Byte0]: 78
1152 11:08:38.772226 [Byte1]: 78
1153 11:08:38.776502
1154 11:08:38.776583 Set Vref, RX VrefLevel [Byte0]: 79
1155 11:08:38.779399 [Byte1]: 79
1156 11:08:38.783942
1157 11:08:38.784023 Set Vref, RX VrefLevel [Byte0]: 80
1158 11:08:38.787485 [Byte1]: 80
1159 11:08:38.791376
1160 11:08:38.791457 Set Vref, RX VrefLevel [Byte0]: 81
1161 11:08:38.795106 [Byte1]: 81
1162 11:08:38.799226
1163 11:08:38.799308 Set Vref, RX VrefLevel [Byte0]: 82
1164 11:08:38.802485 [Byte1]: 82
1165 11:08:38.806539
1166 11:08:38.806620 Set Vref, RX VrefLevel [Byte0]: 83
1167 11:08:38.810450 [Byte1]: 83
1168 11:08:38.814833
1169 11:08:38.814914 Final RX Vref Byte 0 = 65 to rank0
1170 11:08:38.818221 Final RX Vref Byte 1 = 61 to rank0
1171 11:08:38.821449 Final RX Vref Byte 0 = 65 to rank1
1172 11:08:38.824657 Final RX Vref Byte 1 = 61 to rank1==
1173 11:08:38.827859 Dram Type= 6, Freq= 0, CH_0, rank 0
1174 11:08:38.834090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1175 11:08:38.834173 ==
1176 11:08:38.834238 DQS Delay:
1177 11:08:38.837945 DQS0 = 0, DQS1 = 0
1178 11:08:38.838027 DQM Delay:
1179 11:08:38.838093 DQM0 = 87, DQM1 = 75
1180 11:08:38.840839 DQ Delay:
1181 11:08:38.844438 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1182 11:08:38.847800 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1183 11:08:38.850810 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1184 11:08:38.854206 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1185 11:08:38.854288
1186 11:08:38.854352
1187 11:08:38.898019 [DQSOSCAuto] RK0, (LSB)MR18= 0x4122, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1188 11:08:38.898844 CH0 RK0: MR19=606, MR18=4122
1189 11:08:38.899111 CH0_RK0: MR19=0x606, MR18=0x4122, DQSOSC=393, MR23=63, INC=95, DEC=63
1190 11:08:38.899182
1191 11:08:38.899591 ----->DramcWriteLeveling(PI) begin...
1192 11:08:38.899682 ==
1193 11:08:38.899816 Dram Type= 6, Freq= 0, CH_0, rank 1
1194 11:08:38.900082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1195 11:08:38.900182 ==
1196 11:08:38.900256 Write leveling (Byte 0): 35 => 35
1197 11:08:38.900318 Write leveling (Byte 1): 30 => 30
1198 11:08:38.900578 DramcWriteLeveling(PI) end<-----
1199 11:08:38.900684
1200 11:08:38.900748 ==
1201 11:08:38.900803 Dram Type= 6, Freq= 0, CH_0, rank 1
1202 11:08:38.900871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1203 11:08:38.900929 ==
1204 11:08:38.926825 [Gating] SW mode calibration
1205 11:08:38.927134 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1206 11:08:38.927220 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1207 11:08:38.927829 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1208 11:08:38.928477 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1209 11:08:38.928559 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1210 11:08:38.931035 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1211 11:08:38.934322 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 11:08:38.941177 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 11:08:38.943708 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 11:08:38.947109 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 11:08:38.953957 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 11:08:38.957417 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 11:08:38.960690 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 11:08:38.967230 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 11:08:38.970294 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:08:38.973465 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:08:38.980044 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:08:38.983359 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:08:38.986917 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:08:38.993209 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:08:38.996556 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1226 11:08:39.000035 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1227 11:08:39.006489 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:08:39.010091 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:08:39.013040 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:08:39.020017 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:08:39.023240 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:08:39.026409 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:08:39.032647 0 9 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1234 11:08:39.036265 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1235 11:08:39.039514 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 11:08:39.047012 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 11:08:39.050928 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 11:08:39.054143 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 11:08:39.057965 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 11:08:39.064646 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1241 11:08:39.068199 0 10 8 | B1->B0 | 3131 2929 | 0 0 | (0 1) (1 1)
1242 11:08:39.071844 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:08:39.075479 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:08:39.081882 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:08:39.085575 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 11:08:39.088443 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 11:08:39.095532 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 11:08:39.098471 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 11:08:39.102207 0 11 8 | B1->B0 | 2d2d 3a3a | 0 0 | (0 0) (1 1)
1250 11:08:39.108573 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1251 11:08:39.111611 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 11:08:39.115158 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 11:08:39.121737 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 11:08:39.124685 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 11:08:39.128142 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 11:08:39.134655 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1257 11:08:39.138217 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1258 11:08:39.141075 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1259 11:08:39.147857 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 11:08:39.151257 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 11:08:39.154716 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 11:08:39.158093 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 11:08:39.164607 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 11:08:39.167856 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 11:08:39.171380 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 11:08:39.177622 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 11:08:39.181347 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 11:08:39.184406 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 11:08:39.191356 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 11:08:39.194535 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:08:39.197863 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:08:39.204108 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1273 11:08:39.207885 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1274 11:08:39.210910 Total UI for P1: 0, mck2ui 16
1275 11:08:39.214061 best dqsien dly found for B0: ( 0, 14, 4)
1276 11:08:39.217524 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 11:08:39.220936 Total UI for P1: 0, mck2ui 16
1278 11:08:39.224309 best dqsien dly found for B1: ( 0, 14, 8)
1279 11:08:39.228186 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1280 11:08:39.230661 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1281 11:08:39.230743
1282 11:08:39.237669 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1283 11:08:39.240871 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1284 11:08:39.244252 [Gating] SW calibration Done
1285 11:08:39.244334 ==
1286 11:08:39.247259 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 11:08:39.250415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 11:08:39.250498 ==
1289 11:08:39.250563 RX Vref Scan: 0
1290 11:08:39.250623
1291 11:08:39.253685 RX Vref 0 -> 0, step: 1
1292 11:08:39.253766
1293 11:08:39.257177 RX Delay -130 -> 252, step: 16
1294 11:08:39.260628 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1295 11:08:39.263561 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1296 11:08:39.270202 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1297 11:08:39.273412 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1298 11:08:39.276783 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1299 11:08:39.280193 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1300 11:08:39.283588 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1301 11:08:39.290471 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1302 11:08:39.293389 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1303 11:08:39.296887 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1304 11:08:39.299981 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1305 11:08:39.307802 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1306 11:08:39.310147 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1307 11:08:39.313476 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1308 11:08:39.316827 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1309 11:08:39.320212 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1310 11:08:39.320294 ==
1311 11:08:39.323460 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 11:08:39.330124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 11:08:39.330207 ==
1314 11:08:39.330273 DQS Delay:
1315 11:08:39.333383 DQS0 = 0, DQS1 = 0
1316 11:08:39.333465 DQM Delay:
1317 11:08:39.336647 DQM0 = 87, DQM1 = 77
1318 11:08:39.336729 DQ Delay:
1319 11:08:39.339744 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1320 11:08:39.343173 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1321 11:08:39.346294 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1322 11:08:39.349736 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1323 11:08:39.349817
1324 11:08:39.349881
1325 11:08:39.349941 ==
1326 11:08:39.352969 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 11:08:39.356384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 11:08:39.356492 ==
1329 11:08:39.356569
1330 11:08:39.356631
1331 11:08:39.359655 TX Vref Scan disable
1332 11:08:39.363665 == TX Byte 0 ==
1333 11:08:39.366396 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1334 11:08:39.369557 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1335 11:08:39.372730 == TX Byte 1 ==
1336 11:08:39.376203 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1337 11:08:39.379815 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1338 11:08:39.379897 ==
1339 11:08:39.382531 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 11:08:39.389905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 11:08:39.389987 ==
1342 11:08:39.401683 TX Vref=22, minBit 2, minWin=27, winSum=439
1343 11:08:39.404839 TX Vref=24, minBit 1, minWin=27, winSum=442
1344 11:08:39.408989 TX Vref=26, minBit 3, minWin=27, winSum=447
1345 11:08:39.411695 TX Vref=28, minBit 5, minWin=27, winSum=447
1346 11:08:39.415503 TX Vref=30, minBit 0, minWin=27, winSum=444
1347 11:08:39.421585 TX Vref=32, minBit 9, minWin=27, winSum=447
1348 11:08:39.424759 [TxChooseVref] Worse bit 3, Min win 27, Win sum 447, Final Vref 26
1349 11:08:39.424842
1350 11:08:39.428375 Final TX Range 1 Vref 26
1351 11:08:39.428456
1352 11:08:39.428521 ==
1353 11:08:39.431859 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 11:08:39.435175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 11:08:39.435257 ==
1356 11:08:39.438734
1357 11:08:39.438814
1358 11:08:39.438878 TX Vref Scan disable
1359 11:08:39.441978 == TX Byte 0 ==
1360 11:08:39.445049 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1361 11:08:39.451490 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1362 11:08:39.451573 == TX Byte 1 ==
1363 11:08:39.455007 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1364 11:08:39.461957 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1365 11:08:39.462041
1366 11:08:39.462105 [DATLAT]
1367 11:08:39.462165 Freq=800, CH0 RK1
1368 11:08:39.462223
1369 11:08:39.465138 DATLAT Default: 0xa
1370 11:08:39.465218 0, 0xFFFF, sum = 0
1371 11:08:39.468559 1, 0xFFFF, sum = 0
1372 11:08:39.468643 2, 0xFFFF, sum = 0
1373 11:08:39.471333 3, 0xFFFF, sum = 0
1374 11:08:39.475138 4, 0xFFFF, sum = 0
1375 11:08:39.475221 5, 0xFFFF, sum = 0
1376 11:08:39.478371 6, 0xFFFF, sum = 0
1377 11:08:39.478453 7, 0xFFFF, sum = 0
1378 11:08:39.482166 8, 0xFFFF, sum = 0
1379 11:08:39.482248 9, 0x0, sum = 1
1380 11:08:39.482313 10, 0x0, sum = 2
1381 11:08:39.484691 11, 0x0, sum = 3
1382 11:08:39.484773 12, 0x0, sum = 4
1383 11:08:39.488251 best_step = 10
1384 11:08:39.488332
1385 11:08:39.488396 ==
1386 11:08:39.491579 Dram Type= 6, Freq= 0, CH_0, rank 1
1387 11:08:39.494603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1388 11:08:39.494684 ==
1389 11:08:39.498351 RX Vref Scan: 0
1390 11:08:39.498432
1391 11:08:39.498501 RX Vref 0 -> 0, step: 1
1392 11:08:39.501252
1393 11:08:39.501351 RX Delay -111 -> 252, step: 8
1394 11:08:39.508874 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1395 11:08:39.511549 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1396 11:08:39.515272 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1397 11:08:39.518122 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1398 11:08:39.525114 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1399 11:08:39.528366 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1400 11:08:39.531500 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1401 11:08:39.534831 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1402 11:08:39.538038 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1403 11:08:39.544796 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1404 11:08:39.548437 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
1405 11:08:39.551537 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1406 11:08:39.554434 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1407 11:08:39.557669 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1408 11:08:39.564393 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1409 11:08:39.567959 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1410 11:08:39.568039 ==
1411 11:08:39.571264 Dram Type= 6, Freq= 0, CH_0, rank 1
1412 11:08:39.574935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1413 11:08:39.575012 ==
1414 11:08:39.577428 DQS Delay:
1415 11:08:39.577504 DQS0 = 0, DQS1 = 0
1416 11:08:39.577565 DQM Delay:
1417 11:08:39.581064 DQM0 = 85, DQM1 = 77
1418 11:08:39.581166 DQ Delay:
1419 11:08:39.584346 DQ0 =84, DQ1 =92, DQ2 =76, DQ3 =84
1420 11:08:39.587418 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1421 11:08:39.591140 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1422 11:08:39.593979 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1423 11:08:39.594055
1424 11:08:39.594117
1425 11:08:39.604556 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a01, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 395 ps
1426 11:08:39.607276 CH0 RK1: MR19=606, MR18=3A01
1427 11:08:39.611499 CH0_RK1: MR19=0x606, MR18=0x3A01, DQSOSC=395, MR23=63, INC=94, DEC=63
1428 11:08:39.614061 [RxdqsGatingPostProcess] freq 800
1429 11:08:39.620323 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1430 11:08:39.623941 Pre-setting of DQS Precalculation
1431 11:08:39.627222 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1432 11:08:39.630778 ==
1433 11:08:39.633602 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 11:08:39.637040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 11:08:39.637142 ==
1436 11:08:39.640218 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1437 11:08:39.647017 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1438 11:08:39.656792 [CA 0] Center 36 (6~67) winsize 62
1439 11:08:39.660261 [CA 1] Center 36 (6~67) winsize 62
1440 11:08:39.663491 [CA 2] Center 34 (4~65) winsize 62
1441 11:08:39.666891 [CA 3] Center 34 (4~65) winsize 62
1442 11:08:39.670058 [CA 4] Center 34 (4~65) winsize 62
1443 11:08:39.673778 [CA 5] Center 34 (3~65) winsize 63
1444 11:08:39.673859
1445 11:08:39.677114 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1446 11:08:39.677182
1447 11:08:39.680042 [CATrainingPosCal] consider 1 rank data
1448 11:08:39.683802 u2DelayCellTimex100 = 270/100 ps
1449 11:08:39.686773 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1450 11:08:39.693113 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1451 11:08:39.696391 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1452 11:08:39.699756 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1453 11:08:39.703120 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1454 11:08:39.706913 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1455 11:08:39.706989
1456 11:08:39.710665 CA PerBit enable=1, Macro0, CA PI delay=34
1457 11:08:39.710740
1458 11:08:39.713181 [CBTSetCACLKResult] CA Dly = 34
1459 11:08:39.713280 CS Dly: 4 (0~35)
1460 11:08:39.713377 ==
1461 11:08:39.717286 Dram Type= 6, Freq= 0, CH_1, rank 1
1462 11:08:39.723726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1463 11:08:39.723803 ==
1464 11:08:39.727394 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1465 11:08:39.734009 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1466 11:08:39.743394 [CA 0] Center 36 (6~67) winsize 62
1467 11:08:39.746854 [CA 1] Center 37 (6~68) winsize 63
1468 11:08:39.750450 [CA 2] Center 34 (4~65) winsize 62
1469 11:08:39.753501 [CA 3] Center 34 (4~65) winsize 62
1470 11:08:39.756801 [CA 4] Center 34 (4~65) winsize 62
1471 11:08:39.760465 [CA 5] Center 34 (4~64) winsize 61
1472 11:08:39.760929
1473 11:08:39.763433 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1474 11:08:39.763894
1475 11:08:39.767203 [CATrainingPosCal] consider 2 rank data
1476 11:08:39.770928 u2DelayCellTimex100 = 270/100 ps
1477 11:08:39.773796 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1478 11:08:39.777240 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1479 11:08:39.780183 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1480 11:08:39.786948 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1481 11:08:39.790463 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1482 11:08:39.793707 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1483 11:08:39.794130
1484 11:08:39.796647 CA PerBit enable=1, Macro0, CA PI delay=34
1485 11:08:39.797087
1486 11:08:39.800298 [CBTSetCACLKResult] CA Dly = 34
1487 11:08:39.800744 CS Dly: 5 (0~38)
1488 11:08:39.801195
1489 11:08:39.803807 ----->DramcWriteLeveling(PI) begin...
1490 11:08:39.804254 ==
1491 11:08:39.806830 Dram Type= 6, Freq= 0, CH_1, rank 0
1492 11:08:39.813694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1493 11:08:39.814137 ==
1494 11:08:39.816834 Write leveling (Byte 0): 27 => 27
1495 11:08:39.820106 Write leveling (Byte 1): 28 => 28
1496 11:08:39.823138 DramcWriteLeveling(PI) end<-----
1497 11:08:39.823577
1498 11:08:39.824062 ==
1499 11:08:39.827094 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 11:08:39.830232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1501 11:08:39.830725 ==
1502 11:08:39.833929 [Gating] SW mode calibration
1503 11:08:39.840175 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1504 11:08:39.843763 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1505 11:08:39.850551 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1506 11:08:39.853402 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1507 11:08:39.856822 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 11:08:39.863853 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 11:08:39.866881 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 11:08:39.869947 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 11:08:39.876763 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 11:08:39.880178 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 11:08:39.883384 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 11:08:39.890168 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 11:08:39.893478 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 11:08:39.896751 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 11:08:39.903222 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:08:39.906688 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:08:39.909982 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:08:39.917062 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:08:39.919770 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1522 11:08:39.923158 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1523 11:08:39.930140 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1524 11:08:39.933190 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:08:39.936331 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:08:39.943185 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:08:39.946515 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:08:39.949594 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:08:39.956197 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:08:39.959244 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:08:39.962465 0 9 8 | B1->B0 | 2d2d 3232 | 1 1 | (0 0) (1 1)
1532 11:08:39.969764 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 11:08:39.972875 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 11:08:39.976371 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 11:08:39.983241 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 11:08:39.985985 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 11:08:39.989840 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 11:08:39.995847 0 10 4 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
1539 11:08:39.999232 0 10 8 | B1->B0 | 2d2d 2525 | 1 0 | (1 0) (0 0)
1540 11:08:40.002449 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:08:40.009259 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:08:40.012755 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 11:08:40.015981 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 11:08:40.019180 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 11:08:40.025750 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 11:08:40.029377 0 11 4 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
1547 11:08:40.032189 0 11 8 | B1->B0 | 3c3c 3f3f | 0 0 | (0 0) (1 1)
1548 11:08:40.039241 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 11:08:40.042302 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 11:08:40.045791 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 11:08:40.052238 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 11:08:40.055470 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 11:08:40.059159 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 11:08:40.065852 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1555 11:08:40.068572 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1556 11:08:40.071938 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 11:08:40.078456 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 11:08:40.082015 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 11:08:40.085105 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 11:08:40.091872 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 11:08:40.095316 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 11:08:40.098435 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 11:08:40.104963 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 11:08:40.108441 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 11:08:40.111709 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 11:08:40.118327 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 11:08:40.121624 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:08:40.125148 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:08:40.131757 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:08:40.135332 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1571 11:08:40.138156 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1572 11:08:40.141768 Total UI for P1: 0, mck2ui 16
1573 11:08:40.144591 best dqsien dly found for B0: ( 0, 14, 4)
1574 11:08:40.151712 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 11:08:40.152277 Total UI for P1: 0, mck2ui 16
1576 11:08:40.157757 best dqsien dly found for B1: ( 0, 14, 8)
1577 11:08:40.161456 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1578 11:08:40.164535 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1579 11:08:40.165194
1580 11:08:40.168131 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1581 11:08:40.171239 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1582 11:08:40.174461 [Gating] SW calibration Done
1583 11:08:40.175027 ==
1584 11:08:40.178260 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 11:08:40.181101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 11:08:40.181609 ==
1587 11:08:40.184606 RX Vref Scan: 0
1588 11:08:40.185169
1589 11:08:40.185539 RX Vref 0 -> 0, step: 1
1590 11:08:40.185878
1591 11:08:40.187762 RX Delay -130 -> 252, step: 16
1592 11:08:40.195226 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1593 11:08:40.198080 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1594 11:08:40.200803 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1595 11:08:40.204472 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1596 11:08:40.207626 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1597 11:08:40.213801 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1598 11:08:40.217379 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1599 11:08:40.220535 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1600 11:08:40.224073 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1601 11:08:40.227658 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1602 11:08:40.234133 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1603 11:08:40.237297 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1604 11:08:40.240499 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1605 11:08:40.244177 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1606 11:08:40.247349 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1607 11:08:40.254320 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1608 11:08:40.254888 ==
1609 11:08:40.257662 Dram Type= 6, Freq= 0, CH_1, rank 0
1610 11:08:40.260056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1611 11:08:40.260532 ==
1612 11:08:40.260906 DQS Delay:
1613 11:08:40.263431 DQS0 = 0, DQS1 = 0
1614 11:08:40.263957 DQM Delay:
1615 11:08:40.267391 DQM0 = 89, DQM1 = 80
1616 11:08:40.268009 DQ Delay:
1617 11:08:40.270264 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1618 11:08:40.273832 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1619 11:08:40.277224 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1620 11:08:40.280248 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1621 11:08:40.280824
1622 11:08:40.281197
1623 11:08:40.281539 ==
1624 11:08:40.283796 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 11:08:40.290489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 11:08:40.291066 ==
1627 11:08:40.291442
1628 11:08:40.291828
1629 11:08:40.292163 TX Vref Scan disable
1630 11:08:40.294162 == TX Byte 0 ==
1631 11:08:40.298113 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1632 11:08:40.300669 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1633 11:08:40.304087 == TX Byte 1 ==
1634 11:08:40.308137 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1635 11:08:40.310668 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1636 11:08:40.311262 ==
1637 11:08:40.313889 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 11:08:40.320573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 11:08:40.321142 ==
1640 11:08:40.332429 TX Vref=22, minBit 10, minWin=26, winSum=443
1641 11:08:40.336156 TX Vref=24, minBit 9, minWin=27, winSum=447
1642 11:08:40.339245 TX Vref=26, minBit 9, minWin=27, winSum=448
1643 11:08:40.342401 TX Vref=28, minBit 8, minWin=27, winSum=450
1644 11:08:40.345844 TX Vref=30, minBit 10, minWin=27, winSum=449
1645 11:08:40.352812 TX Vref=32, minBit 8, minWin=27, winSum=447
1646 11:08:40.355312 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 28
1647 11:08:40.355833
1648 11:08:40.358799 Final TX Range 1 Vref 28
1649 11:08:40.359278
1650 11:08:40.359648 ==
1651 11:08:40.362553 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 11:08:40.366057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 11:08:40.368940 ==
1654 11:08:40.369411
1655 11:08:40.369782
1656 11:08:40.370128 TX Vref Scan disable
1657 11:08:40.372295 == TX Byte 0 ==
1658 11:08:40.376138 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1659 11:08:40.382834 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1660 11:08:40.383403 == TX Byte 1 ==
1661 11:08:40.385705 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1662 11:08:40.392682 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1663 11:08:40.393243
1664 11:08:40.393610 [DATLAT]
1665 11:08:40.393952 Freq=800, CH1 RK0
1666 11:08:40.394283
1667 11:08:40.395464 DATLAT Default: 0xa
1668 11:08:40.395950 0, 0xFFFF, sum = 0
1669 11:08:40.399020 1, 0xFFFF, sum = 0
1670 11:08:40.399488 2, 0xFFFF, sum = 0
1671 11:08:40.402904 3, 0xFFFF, sum = 0
1672 11:08:40.403373 4, 0xFFFF, sum = 0
1673 11:08:40.406338 5, 0xFFFF, sum = 0
1674 11:08:40.410046 6, 0xFFFF, sum = 0
1675 11:08:40.410618 7, 0xFFFF, sum = 0
1676 11:08:40.412649 8, 0xFFFF, sum = 0
1677 11:08:40.413115 9, 0x0, sum = 1
1678 11:08:40.413484 10, 0x0, sum = 2
1679 11:08:40.416211 11, 0x0, sum = 3
1680 11:08:40.416685 12, 0x0, sum = 4
1681 11:08:40.419150 best_step = 10
1682 11:08:40.419615
1683 11:08:40.420050 ==
1684 11:08:40.422546 Dram Type= 6, Freq= 0, CH_1, rank 0
1685 11:08:40.425761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1686 11:08:40.426336 ==
1687 11:08:40.429616 RX Vref Scan: 1
1688 11:08:40.430081
1689 11:08:40.430451 Set Vref Range= 32 -> 127
1690 11:08:40.432385
1691 11:08:40.432850 RX Vref 32 -> 127, step: 1
1692 11:08:40.433224
1693 11:08:40.436131 RX Delay -95 -> 252, step: 8
1694 11:08:40.436693
1695 11:08:40.438761 Set Vref, RX VrefLevel [Byte0]: 32
1696 11:08:40.442823 [Byte1]: 32
1697 11:08:40.443384
1698 11:08:40.445920 Set Vref, RX VrefLevel [Byte0]: 33
1699 11:08:40.449156 [Byte1]: 33
1700 11:08:40.452536
1701 11:08:40.453009 Set Vref, RX VrefLevel [Byte0]: 34
1702 11:08:40.456324 [Byte1]: 34
1703 11:08:40.460702
1704 11:08:40.461259 Set Vref, RX VrefLevel [Byte0]: 35
1705 11:08:40.463829 [Byte1]: 35
1706 11:08:40.468579
1707 11:08:40.469139 Set Vref, RX VrefLevel [Byte0]: 36
1708 11:08:40.471293 [Byte1]: 36
1709 11:08:40.475845
1710 11:08:40.476397 Set Vref, RX VrefLevel [Byte0]: 37
1711 11:08:40.479126 [Byte1]: 37
1712 11:08:40.483798
1713 11:08:40.484374 Set Vref, RX VrefLevel [Byte0]: 38
1714 11:08:40.486809 [Byte1]: 38
1715 11:08:40.490751
1716 11:08:40.491309 Set Vref, RX VrefLevel [Byte0]: 39
1717 11:08:40.494144 [Byte1]: 39
1718 11:08:40.498171
1719 11:08:40.498636 Set Vref, RX VrefLevel [Byte0]: 40
1720 11:08:40.501452 [Byte1]: 40
1721 11:08:40.506356
1722 11:08:40.506919 Set Vref, RX VrefLevel [Byte0]: 41
1723 11:08:40.509501 [Byte1]: 41
1724 11:08:40.513400
1725 11:08:40.513931 Set Vref, RX VrefLevel [Byte0]: 42
1726 11:08:40.516729 [Byte1]: 42
1727 11:08:40.520920
1728 11:08:40.521387 Set Vref, RX VrefLevel [Byte0]: 43
1729 11:08:40.524255 [Byte1]: 43
1730 11:08:40.529056
1731 11:08:40.529643 Set Vref, RX VrefLevel [Byte0]: 44
1732 11:08:40.531909 [Byte1]: 44
1733 11:08:40.536629
1734 11:08:40.537210 Set Vref, RX VrefLevel [Byte0]: 45
1735 11:08:40.539790 [Byte1]: 45
1736 11:08:40.544601
1737 11:08:40.545158 Set Vref, RX VrefLevel [Byte0]: 46
1738 11:08:40.547841 [Byte1]: 46
1739 11:08:40.551662
1740 11:08:40.552293 Set Vref, RX VrefLevel [Byte0]: 47
1741 11:08:40.555814 [Byte1]: 47
1742 11:08:40.559488
1743 11:08:40.560109 Set Vref, RX VrefLevel [Byte0]: 48
1744 11:08:40.562312 [Byte1]: 48
1745 11:08:40.567230
1746 11:08:40.567870 Set Vref, RX VrefLevel [Byte0]: 49
1747 11:08:40.570892 [Byte1]: 49
1748 11:08:40.574646
1749 11:08:40.575205 Set Vref, RX VrefLevel [Byte0]: 50
1750 11:08:40.578551 [Byte1]: 50
1751 11:08:40.582206
1752 11:08:40.582771 Set Vref, RX VrefLevel [Byte0]: 51
1753 11:08:40.585535 [Byte1]: 51
1754 11:08:40.590035
1755 11:08:40.590593 Set Vref, RX VrefLevel [Byte0]: 52
1756 11:08:40.593151 [Byte1]: 52
1757 11:08:40.597160
1758 11:08:40.597719 Set Vref, RX VrefLevel [Byte0]: 53
1759 11:08:40.600675 [Byte1]: 53
1760 11:08:40.604937
1761 11:08:40.605404 Set Vref, RX VrefLevel [Byte0]: 54
1762 11:08:40.608423 [Byte1]: 54
1763 11:08:40.612554
1764 11:08:40.613140 Set Vref, RX VrefLevel [Byte0]: 55
1765 11:08:40.615845 [Byte1]: 55
1766 11:08:40.620083
1767 11:08:40.620660 Set Vref, RX VrefLevel [Byte0]: 56
1768 11:08:40.623267 [Byte1]: 56
1769 11:08:40.628150
1770 11:08:40.628718 Set Vref, RX VrefLevel [Byte0]: 57
1771 11:08:40.631211 [Byte1]: 57
1772 11:08:40.635321
1773 11:08:40.635820 Set Vref, RX VrefLevel [Byte0]: 58
1774 11:08:40.638952 [Byte1]: 58
1775 11:08:40.642576
1776 11:08:40.643144 Set Vref, RX VrefLevel [Byte0]: 59
1777 11:08:40.646352 [Byte1]: 59
1778 11:08:40.650963
1779 11:08:40.651538 Set Vref, RX VrefLevel [Byte0]: 60
1780 11:08:40.653990 [Byte1]: 60
1781 11:08:40.657975
1782 11:08:40.658544 Set Vref, RX VrefLevel [Byte0]: 61
1783 11:08:40.661339 [Byte1]: 61
1784 11:08:40.666304
1785 11:08:40.666877 Set Vref, RX VrefLevel [Byte0]: 62
1786 11:08:40.668651 [Byte1]: 62
1787 11:08:40.673150
1788 11:08:40.673718 Set Vref, RX VrefLevel [Byte0]: 63
1789 11:08:40.676566 [Byte1]: 63
1790 11:08:40.680773
1791 11:08:40.681341 Set Vref, RX VrefLevel [Byte0]: 64
1792 11:08:40.684195 [Byte1]: 64
1793 11:08:40.688600
1794 11:08:40.689157 Set Vref, RX VrefLevel [Byte0]: 65
1795 11:08:40.691833 [Byte1]: 65
1796 11:08:40.695837
1797 11:08:40.696303 Set Vref, RX VrefLevel [Byte0]: 66
1798 11:08:40.699343 [Byte1]: 66
1799 11:08:40.703811
1800 11:08:40.704534 Set Vref, RX VrefLevel [Byte0]: 67
1801 11:08:40.706879 [Byte1]: 67
1802 11:08:40.711375
1803 11:08:40.712055 Set Vref, RX VrefLevel [Byte0]: 68
1804 11:08:40.714778 [Byte1]: 68
1805 11:08:40.719633
1806 11:08:40.720220 Set Vref, RX VrefLevel [Byte0]: 69
1807 11:08:40.722242 [Byte1]: 69
1808 11:08:40.726878
1809 11:08:40.727397 Set Vref, RX VrefLevel [Byte0]: 70
1810 11:08:40.729908 [Byte1]: 70
1811 11:08:40.734842
1812 11:08:40.735365 Set Vref, RX VrefLevel [Byte0]: 71
1813 11:08:40.737575 [Byte1]: 71
1814 11:08:40.741738
1815 11:08:40.742250 Set Vref, RX VrefLevel [Byte0]: 72
1816 11:08:40.744756 [Byte1]: 72
1817 11:08:40.749460
1818 11:08:40.749979 Set Vref, RX VrefLevel [Byte0]: 73
1819 11:08:40.752649 [Byte1]: 73
1820 11:08:40.756761
1821 11:08:40.757283 Set Vref, RX VrefLevel [Byte0]: 74
1822 11:08:40.760327 [Byte1]: 74
1823 11:08:40.764327
1824 11:08:40.764848 Set Vref, RX VrefLevel [Byte0]: 75
1825 11:08:40.767885 [Byte1]: 75
1826 11:08:40.772071
1827 11:08:40.772592 Set Vref, RX VrefLevel [Byte0]: 76
1828 11:08:40.774899 [Byte1]: 76
1829 11:08:40.779618
1830 11:08:40.780174 Set Vref, RX VrefLevel [Byte0]: 77
1831 11:08:40.783021 [Byte1]: 77
1832 11:08:40.787286
1833 11:08:40.787840 Final RX Vref Byte 0 = 56 to rank0
1834 11:08:40.791000 Final RX Vref Byte 1 = 62 to rank0
1835 11:08:40.793951 Final RX Vref Byte 0 = 56 to rank1
1836 11:08:40.797327 Final RX Vref Byte 1 = 62 to rank1==
1837 11:08:40.800393 Dram Type= 6, Freq= 0, CH_1, rank 0
1838 11:08:40.807199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 11:08:40.807631 ==
1840 11:08:40.808019 DQS Delay:
1841 11:08:40.808340 DQS0 = 0, DQS1 = 0
1842 11:08:40.810187 DQM Delay:
1843 11:08:40.810609 DQM0 = 86, DQM1 = 78
1844 11:08:40.813297 DQ Delay:
1845 11:08:40.817191 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1846 11:08:40.820661 DQ4 =84, DQ5 =100, DQ6 =96, DQ7 =80
1847 11:08:40.823460 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1848 11:08:40.826892 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
1849 11:08:40.827592
1850 11:08:40.828029
1851 11:08:40.833665 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
1852 11:08:40.837071 CH1 RK0: MR19=606, MR18=2A16
1853 11:08:40.843258 CH1_RK0: MR19=0x606, MR18=0x2A16, DQSOSC=399, MR23=63, INC=92, DEC=61
1854 11:08:40.843730
1855 11:08:40.846827 ----->DramcWriteLeveling(PI) begin...
1856 11:08:40.847258 ==
1857 11:08:40.850036 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 11:08:40.853089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 11:08:40.853634 ==
1860 11:08:40.856541 Write leveling (Byte 0): 27 => 27
1861 11:08:40.859487 Write leveling (Byte 1): 29 => 29
1862 11:08:40.862978 DramcWriteLeveling(PI) end<-----
1863 11:08:40.863402
1864 11:08:40.863789 ==
1865 11:08:40.866585 Dram Type= 6, Freq= 0, CH_1, rank 1
1866 11:08:40.870065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 11:08:40.870602 ==
1868 11:08:40.872923 [Gating] SW mode calibration
1869 11:08:40.879975 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1870 11:08:40.886289 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1871 11:08:40.889572 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1872 11:08:40.896060 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1873 11:08:40.899324 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 11:08:40.902647 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 11:08:40.909685 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:08:40.912772 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:08:40.916478 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 11:08:40.922484 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:08:40.926329 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:08:40.929384 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:08:40.935830 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:08:40.939495 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:08:40.942864 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:08:40.946084 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:08:40.953427 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 11:08:40.956192 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:08:40.959355 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:08:40.966155 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:08:40.969649 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:08:40.972665 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:08:40.979504 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:08:40.982842 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:08:40.986078 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:08:40.992597 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:08:40.995893 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:08:40.998641 0 9 4 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1897 11:08:41.006171 0 9 8 | B1->B0 | 3333 2b2b | 1 0 | (1 1) (0 0)
1898 11:08:41.008543 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 11:08:41.012200 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 11:08:41.018844 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 11:08:41.022233 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 11:08:41.025809 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 11:08:41.032689 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 11:08:41.035777 0 10 4 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 1)
1905 11:08:41.039631 0 10 8 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (1 1)
1906 11:08:41.046304 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:08:41.048905 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:08:41.051947 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 11:08:41.059016 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 11:08:41.062266 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 11:08:41.065881 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 11:08:41.072355 0 11 4 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
1913 11:08:41.075747 0 11 8 | B1->B0 | 3d3d 3434 | 1 1 | (0 0) (0 0)
1914 11:08:41.078912 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 11:08:41.086115 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 11:08:41.089511 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 11:08:41.092298 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 11:08:41.098401 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 11:08:41.101919 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 11:08:41.104939 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1921 11:08:41.108475 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1922 11:08:41.115040 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 11:08:41.118389 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 11:08:41.122186 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 11:08:41.128832 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 11:08:41.131373 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 11:08:41.135042 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 11:08:41.141817 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 11:08:41.144679 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 11:08:41.148234 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 11:08:41.154857 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 11:08:41.158069 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 11:08:41.161657 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 11:08:41.168179 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 11:08:41.171793 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 11:08:41.175024 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 11:08:41.180940 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 11:08:41.184509 Total UI for P1: 0, mck2ui 16
1939 11:08:41.187988 best dqsien dly found for B0: ( 0, 14, 6)
1940 11:08:41.191360 Total UI for P1: 0, mck2ui 16
1941 11:08:41.194729 best dqsien dly found for B1: ( 0, 14, 6)
1942 11:08:41.198105 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1943 11:08:41.201495 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1944 11:08:41.202079
1945 11:08:41.204385 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1946 11:08:41.207625 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1947 11:08:41.210984 [Gating] SW calibration Done
1948 11:08:41.211554 ==
1949 11:08:41.214255 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 11:08:41.217565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 11:08:41.218042 ==
1952 11:08:41.221038 RX Vref Scan: 0
1953 11:08:41.221494
1954 11:08:41.221830 RX Vref 0 -> 0, step: 1
1955 11:08:41.224211
1956 11:08:41.224682 RX Delay -130 -> 252, step: 16
1957 11:08:41.230807 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1958 11:08:41.234465 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1959 11:08:41.238454 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1960 11:08:41.240886 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1961 11:08:41.244048 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1962 11:08:41.250751 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1963 11:08:41.253916 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1964 11:08:41.257238 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1965 11:08:41.260685 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1966 11:08:41.264092 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1967 11:08:41.270856 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1968 11:08:41.273681 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1969 11:08:41.277610 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1970 11:08:41.280575 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1971 11:08:41.287450 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1972 11:08:41.290470 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1973 11:08:41.291001 ==
1974 11:08:41.294186 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 11:08:41.297347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 11:08:41.297882 ==
1977 11:08:41.298223 DQS Delay:
1978 11:08:41.301056 DQS0 = 0, DQS1 = 0
1979 11:08:41.301591 DQM Delay:
1980 11:08:41.304002 DQM0 = 87, DQM1 = 78
1981 11:08:41.304638 DQ Delay:
1982 11:08:41.306872 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1983 11:08:41.310436 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1984 11:08:41.313698 DQ8 =61, DQ9 =69, DQ10 =85, DQ11 =69
1985 11:08:41.316878 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1986 11:08:41.317298
1987 11:08:41.317631
1988 11:08:41.317937 ==
1989 11:08:41.320095 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 11:08:41.326996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 11:08:41.327524 ==
1992 11:08:41.327932
1993 11:08:41.328248
1994 11:08:41.328544 TX Vref Scan disable
1995 11:08:41.330087 == TX Byte 0 ==
1996 11:08:41.333726 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1997 11:08:41.340376 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1998 11:08:41.340899 == TX Byte 1 ==
1999 11:08:41.343871 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2000 11:08:41.350585 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2001 11:08:41.351107 ==
2002 11:08:41.353867 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 11:08:41.356840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 11:08:41.357404 ==
2005 11:08:41.369596 TX Vref=22, minBit 9, minWin=26, winSum=444
2006 11:08:41.372817 TX Vref=24, minBit 1, minWin=27, winSum=444
2007 11:08:41.376270 TX Vref=26, minBit 8, minWin=27, winSum=448
2008 11:08:41.379288 TX Vref=28, minBit 8, minWin=27, winSum=451
2009 11:08:41.382620 TX Vref=30, minBit 8, minWin=27, winSum=452
2010 11:08:41.389240 TX Vref=32, minBit 8, minWin=27, winSum=448
2011 11:08:41.392614 [TxChooseVref] Worse bit 8, Min win 27, Win sum 452, Final Vref 30
2012 11:08:41.393180
2013 11:08:41.395663 Final TX Range 1 Vref 30
2014 11:08:41.396272
2015 11:08:41.396642 ==
2016 11:08:41.399286 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 11:08:41.402415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 11:08:41.405496 ==
2019 11:08:41.405964
2020 11:08:41.406327
2021 11:08:41.406669 TX Vref Scan disable
2022 11:08:41.409596 == TX Byte 0 ==
2023 11:08:41.412367 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2024 11:08:41.419081 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2025 11:08:41.419605 == TX Byte 1 ==
2026 11:08:41.423001 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2027 11:08:41.429313 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2028 11:08:41.429844
2029 11:08:41.430184 [DATLAT]
2030 11:08:41.430496 Freq=800, CH1 RK1
2031 11:08:41.430798
2032 11:08:41.432000 DATLAT Default: 0xa
2033 11:08:41.432419 0, 0xFFFF, sum = 0
2034 11:08:41.435358 1, 0xFFFF, sum = 0
2035 11:08:41.438806 2, 0xFFFF, sum = 0
2036 11:08:41.439229 3, 0xFFFF, sum = 0
2037 11:08:41.442588 4, 0xFFFF, sum = 0
2038 11:08:41.443114 5, 0xFFFF, sum = 0
2039 11:08:41.445612 6, 0xFFFF, sum = 0
2040 11:08:41.446137 7, 0xFFFF, sum = 0
2041 11:08:41.448801 8, 0xFFFF, sum = 0
2042 11:08:41.449327 9, 0x0, sum = 1
2043 11:08:41.452070 10, 0x0, sum = 2
2044 11:08:41.452598 11, 0x0, sum = 3
2045 11:08:41.455735 12, 0x0, sum = 4
2046 11:08:41.456259 best_step = 10
2047 11:08:41.456596
2048 11:08:41.456906 ==
2049 11:08:41.459015 Dram Type= 6, Freq= 0, CH_1, rank 1
2050 11:08:41.462159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2051 11:08:41.462688 ==
2052 11:08:41.465469 RX Vref Scan: 0
2053 11:08:41.465893
2054 11:08:41.468635 RX Vref 0 -> 0, step: 1
2055 11:08:41.469157
2056 11:08:41.469498 RX Delay -111 -> 252, step: 8
2057 11:08:41.476162 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2058 11:08:41.479412 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2059 11:08:41.482754 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2060 11:08:41.486064 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2061 11:08:41.489540 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2062 11:08:41.496414 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2063 11:08:41.499092 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2064 11:08:41.503114 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2065 11:08:41.505897 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2066 11:08:41.512740 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2067 11:08:41.515657 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2068 11:08:41.519449 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2069 11:08:41.522766 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2070 11:08:41.526485 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2071 11:08:41.532597 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2072 11:08:41.535810 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2073 11:08:41.536370 ==
2074 11:08:41.539186 Dram Type= 6, Freq= 0, CH_1, rank 1
2075 11:08:41.542373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2076 11:08:41.542937 ==
2077 11:08:41.546040 DQS Delay:
2078 11:08:41.546599 DQS0 = 0, DQS1 = 0
2079 11:08:41.546972 DQM Delay:
2080 11:08:41.548802 DQM0 = 87, DQM1 = 78
2081 11:08:41.549362 DQ Delay:
2082 11:08:41.552228 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2083 11:08:41.555585 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2084 11:08:41.559332 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
2085 11:08:41.561873 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2086 11:08:41.562305
2087 11:08:41.562636
2088 11:08:41.572395 [DQSOSCAuto] RK1, (LSB)MR18= 0x140b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 404 ps
2089 11:08:41.575764 CH1 RK1: MR19=606, MR18=140B
2090 11:08:41.578628 CH1_RK1: MR19=0x606, MR18=0x140B, DQSOSC=404, MR23=63, INC=90, DEC=60
2091 11:08:41.581809 [RxdqsGatingPostProcess] freq 800
2092 11:08:41.588717 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2093 11:08:41.591750 Pre-setting of DQS Precalculation
2094 11:08:41.595480 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2095 11:08:41.605431 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2096 11:08:41.612806 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2097 11:08:41.613388
2098 11:08:41.613734
2099 11:08:41.615194 [Calibration Summary] 1600 Mbps
2100 11:08:41.615655 CH 0, Rank 0
2101 11:08:41.618195 SW Impedance : PASS
2102 11:08:41.618622 DUTY Scan : NO K
2103 11:08:41.621916 ZQ Calibration : PASS
2104 11:08:41.625078 Jitter Meter : NO K
2105 11:08:41.625503 CBT Training : PASS
2106 11:08:41.628719 Write leveling : PASS
2107 11:08:41.631717 RX DQS gating : PASS
2108 11:08:41.632147 RX DQ/DQS(RDDQC) : PASS
2109 11:08:41.635288 TX DQ/DQS : PASS
2110 11:08:41.638728 RX DATLAT : PASS
2111 11:08:41.639253 RX DQ/DQS(Engine): PASS
2112 11:08:41.641915 TX OE : NO K
2113 11:08:41.642438 All Pass.
2114 11:08:41.642779
2115 11:08:41.644553 CH 0, Rank 1
2116 11:08:41.644976 SW Impedance : PASS
2117 11:08:41.648214 DUTY Scan : NO K
2118 11:08:41.651846 ZQ Calibration : PASS
2119 11:08:41.652366 Jitter Meter : NO K
2120 11:08:41.655047 CBT Training : PASS
2121 11:08:41.655569 Write leveling : PASS
2122 11:08:41.658519 RX DQS gating : PASS
2123 11:08:41.661458 RX DQ/DQS(RDDQC) : PASS
2124 11:08:41.661919 TX DQ/DQS : PASS
2125 11:08:41.664824 RX DATLAT : PASS
2126 11:08:41.668454 RX DQ/DQS(Engine): PASS
2127 11:08:41.668968 TX OE : NO K
2128 11:08:41.671299 All Pass.
2129 11:08:41.671780
2130 11:08:41.672139 CH 1, Rank 0
2131 11:08:41.674776 SW Impedance : PASS
2132 11:08:41.675204 DUTY Scan : NO K
2133 11:08:41.677809 ZQ Calibration : PASS
2134 11:08:41.681415 Jitter Meter : NO K
2135 11:08:41.681934 CBT Training : PASS
2136 11:08:41.685021 Write leveling : PASS
2137 11:08:41.688627 RX DQS gating : PASS
2138 11:08:41.689149 RX DQ/DQS(RDDQC) : PASS
2139 11:08:41.692238 TX DQ/DQS : PASS
2140 11:08:41.694627 RX DATLAT : PASS
2141 11:08:41.695052 RX DQ/DQS(Engine): PASS
2142 11:08:41.697841 TX OE : NO K
2143 11:08:41.698267 All Pass.
2144 11:08:41.698602
2145 11:08:41.701355 CH 1, Rank 1
2146 11:08:41.701795 SW Impedance : PASS
2147 11:08:41.704699 DUTY Scan : NO K
2148 11:08:41.705124 ZQ Calibration : PASS
2149 11:08:41.707891 Jitter Meter : NO K
2150 11:08:41.711448 CBT Training : PASS
2151 11:08:41.711938 Write leveling : PASS
2152 11:08:41.714857 RX DQS gating : PASS
2153 11:08:41.718223 RX DQ/DQS(RDDQC) : PASS
2154 11:08:41.718744 TX DQ/DQS : PASS
2155 11:08:41.721652 RX DATLAT : PASS
2156 11:08:41.724624 RX DQ/DQS(Engine): PASS
2157 11:08:41.725057 TX OE : NO K
2158 11:08:41.727934 All Pass.
2159 11:08:41.728350
2160 11:08:41.728679 DramC Write-DBI off
2161 11:08:41.731107 PER_BANK_REFRESH: Hybrid Mode
2162 11:08:41.731526 TX_TRACKING: ON
2163 11:08:41.734598 [GetDramInforAfterCalByMRR] Vendor 6.
2164 11:08:41.741280 [GetDramInforAfterCalByMRR] Revision 606.
2165 11:08:41.744697 [GetDramInforAfterCalByMRR] Revision 2 0.
2166 11:08:41.745217 MR0 0x3b3b
2167 11:08:41.745552 MR8 0x5151
2168 11:08:41.747916 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2169 11:08:41.748436
2170 11:08:41.751396 MR0 0x3b3b
2171 11:08:41.751945 MR8 0x5151
2172 11:08:41.755115 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2173 11:08:41.755636
2174 11:08:41.764734 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2175 11:08:41.767710 [FAST_K] Save calibration result to emmc
2176 11:08:41.771330 [FAST_K] Save calibration result to emmc
2177 11:08:41.774584 dram_init: config_dvfs: 1
2178 11:08:41.777651 dramc_set_vcore_voltage set vcore to 662500
2179 11:08:41.781335 Read voltage for 1200, 2
2180 11:08:41.781851 Vio18 = 0
2181 11:08:41.782233 Vcore = 662500
2182 11:08:41.784219 Vdram = 0
2183 11:08:41.784631 Vddq = 0
2184 11:08:41.784959 Vmddr = 0
2185 11:08:41.791265 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2186 11:08:41.794454 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2187 11:08:41.798166 MEM_TYPE=3, freq_sel=15
2188 11:08:41.801487 sv_algorithm_assistance_LP4_1600
2189 11:08:41.804502 ============ PULL DRAM RESETB DOWN ============
2190 11:08:41.807664 ========== PULL DRAM RESETB DOWN end =========
2191 11:08:41.814505 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2192 11:08:41.817596 ===================================
2193 11:08:41.818014 LPDDR4 DRAM CONFIGURATION
2194 11:08:41.820986 ===================================
2195 11:08:41.824311 EX_ROW_EN[0] = 0x0
2196 11:08:41.827453 EX_ROW_EN[1] = 0x0
2197 11:08:41.827918 LP4Y_EN = 0x0
2198 11:08:41.831321 WORK_FSP = 0x0
2199 11:08:41.831893 WL = 0x4
2200 11:08:41.834243 RL = 0x4
2201 11:08:41.834934 BL = 0x2
2202 11:08:41.837285 RPST = 0x0
2203 11:08:41.837802 RD_PRE = 0x0
2204 11:08:41.840847 WR_PRE = 0x1
2205 11:08:41.841370 WR_PST = 0x0
2206 11:08:41.844105 DBI_WR = 0x0
2207 11:08:41.844627 DBI_RD = 0x0
2208 11:08:41.847376 OTF = 0x1
2209 11:08:41.850631 ===================================
2210 11:08:41.854230 ===================================
2211 11:08:41.854797 ANA top config
2212 11:08:41.857694 ===================================
2213 11:08:41.860478 DLL_ASYNC_EN = 0
2214 11:08:41.863577 ALL_SLAVE_EN = 0
2215 11:08:41.867183 NEW_RANK_MODE = 1
2216 11:08:41.867748 DLL_IDLE_MODE = 1
2217 11:08:41.870719 LP45_APHY_COMB_EN = 1
2218 11:08:41.873349 TX_ODT_DIS = 1
2219 11:08:41.877389 NEW_8X_MODE = 1
2220 11:08:41.880728 ===================================
2221 11:08:41.883636 ===================================
2222 11:08:41.887421 data_rate = 2400
2223 11:08:41.890696 CKR = 1
2224 11:08:41.891258 DQ_P2S_RATIO = 8
2225 11:08:41.893427 ===================================
2226 11:08:41.897079 CA_P2S_RATIO = 8
2227 11:08:41.900292 DQ_CA_OPEN = 0
2228 11:08:41.903355 DQ_SEMI_OPEN = 0
2229 11:08:41.906853 CA_SEMI_OPEN = 0
2230 11:08:41.910218 CA_FULL_RATE = 0
2231 11:08:41.910832 DQ_CKDIV4_EN = 0
2232 11:08:41.913145 CA_CKDIV4_EN = 0
2233 11:08:41.916522 CA_PREDIV_EN = 0
2234 11:08:41.919872 PH8_DLY = 17
2235 11:08:41.923500 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2236 11:08:41.926356 DQ_AAMCK_DIV = 4
2237 11:08:41.926775 CA_AAMCK_DIV = 4
2238 11:08:41.929573 CA_ADMCK_DIV = 4
2239 11:08:41.933077 DQ_TRACK_CA_EN = 0
2240 11:08:41.936321 CA_PICK = 1200
2241 11:08:41.939699 CA_MCKIO = 1200
2242 11:08:41.943039 MCKIO_SEMI = 0
2243 11:08:41.946308 PLL_FREQ = 2366
2244 11:08:41.949711 DQ_UI_PI_RATIO = 32
2245 11:08:41.950248 CA_UI_PI_RATIO = 0
2246 11:08:41.952528 ===================================
2247 11:08:41.955962 ===================================
2248 11:08:41.959440 memory_type:LPDDR4
2249 11:08:41.962891 GP_NUM : 10
2250 11:08:41.963497 SRAM_EN : 1
2251 11:08:41.966433 MD32_EN : 0
2252 11:08:41.969127 ===================================
2253 11:08:41.973019 [ANA_INIT] >>>>>>>>>>>>>>
2254 11:08:41.976179 <<<<<< [CONFIGURE PHASE]: ANA_TX
2255 11:08:41.979074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2256 11:08:41.982665 ===================================
2257 11:08:41.983085 data_rate = 2400,PCW = 0X5b00
2258 11:08:41.985696 ===================================
2259 11:08:41.989623 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2260 11:08:41.996259 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2261 11:08:42.002746 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 11:08:42.006104 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2263 11:08:42.009609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2264 11:08:42.012589 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2265 11:08:42.015771 [ANA_INIT] flow start
2266 11:08:42.016192 [ANA_INIT] PLL >>>>>>>>
2267 11:08:42.019201 [ANA_INIT] PLL <<<<<<<<
2268 11:08:42.022594 [ANA_INIT] MIDPI >>>>>>>>
2269 11:08:42.025979 [ANA_INIT] MIDPI <<<<<<<<
2270 11:08:42.026404 [ANA_INIT] DLL >>>>>>>>
2271 11:08:42.028988 [ANA_INIT] DLL <<<<<<<<
2272 11:08:42.032407 [ANA_INIT] flow end
2273 11:08:42.035329 ============ LP4 DIFF to SE enter ============
2274 11:08:42.038567 ============ LP4 DIFF to SE exit ============
2275 11:08:42.042016 [ANA_INIT] <<<<<<<<<<<<<
2276 11:08:42.045470 [Flow] Enable top DCM control >>>>>
2277 11:08:42.048676 [Flow] Enable top DCM control <<<<<
2278 11:08:42.052072 Enable DLL master slave shuffle
2279 11:08:42.056040 ==============================================================
2280 11:08:42.059123 Gating Mode config
2281 11:08:42.065353 ==============================================================
2282 11:08:42.065779 Config description:
2283 11:08:42.074860 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2284 11:08:42.081622 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2285 11:08:42.085245 SELPH_MODE 0: By rank 1: By Phase
2286 11:08:42.091739 ==============================================================
2287 11:08:42.095625 GAT_TRACK_EN = 1
2288 11:08:42.098642 RX_GATING_MODE = 2
2289 11:08:42.102136 RX_GATING_TRACK_MODE = 2
2290 11:08:42.105112 SELPH_MODE = 1
2291 11:08:42.108628 PICG_EARLY_EN = 1
2292 11:08:42.111579 VALID_LAT_VALUE = 1
2293 11:08:42.114967 ==============================================================
2294 11:08:42.118147 Enter into Gating configuration >>>>
2295 11:08:42.121582 Exit from Gating configuration <<<<
2296 11:08:42.125427 Enter into DVFS_PRE_config >>>>>
2297 11:08:42.138184 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2298 11:08:42.138777 Exit from DVFS_PRE_config <<<<<
2299 11:08:42.142130 Enter into PICG configuration >>>>
2300 11:08:42.144876 Exit from PICG configuration <<<<
2301 11:08:42.147926 [RX_INPUT] configuration >>>>>
2302 11:08:42.151633 [RX_INPUT] configuration <<<<<
2303 11:08:42.158275 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2304 11:08:42.161751 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2305 11:08:42.167815 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2306 11:08:42.174379 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2307 11:08:42.180682 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2308 11:08:42.187805 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2309 11:08:42.191207 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2310 11:08:42.194154 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2311 11:08:42.197542 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2312 11:08:42.204302 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2313 11:08:42.207396 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2314 11:08:42.210942 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2315 11:08:42.214275 ===================================
2316 11:08:42.217185 LPDDR4 DRAM CONFIGURATION
2317 11:08:42.220993 ===================================
2318 11:08:42.223799 EX_ROW_EN[0] = 0x0
2319 11:08:42.224222 EX_ROW_EN[1] = 0x0
2320 11:08:42.227250 LP4Y_EN = 0x0
2321 11:08:42.227703 WORK_FSP = 0x0
2322 11:08:42.231273 WL = 0x4
2323 11:08:42.231726 RL = 0x4
2324 11:08:42.233691 BL = 0x2
2325 11:08:42.234108 RPST = 0x0
2326 11:08:42.237740 RD_PRE = 0x0
2327 11:08:42.238237 WR_PRE = 0x1
2328 11:08:42.240569 WR_PST = 0x0
2329 11:08:42.240990 DBI_WR = 0x0
2330 11:08:42.243788 DBI_RD = 0x0
2331 11:08:42.244205 OTF = 0x1
2332 11:08:42.247030 ===================================
2333 11:08:42.253770 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2334 11:08:42.256960 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2335 11:08:42.260135 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2336 11:08:42.263660 ===================================
2337 11:08:42.267448 LPDDR4 DRAM CONFIGURATION
2338 11:08:42.270610 ===================================
2339 11:08:42.273846 EX_ROW_EN[0] = 0x10
2340 11:08:42.274263 EX_ROW_EN[1] = 0x0
2341 11:08:42.277007 LP4Y_EN = 0x0
2342 11:08:42.277427 WORK_FSP = 0x0
2343 11:08:42.280040 WL = 0x4
2344 11:08:42.280492 RL = 0x4
2345 11:08:42.283554 BL = 0x2
2346 11:08:42.284007 RPST = 0x0
2347 11:08:42.286830 RD_PRE = 0x0
2348 11:08:42.287245 WR_PRE = 0x1
2349 11:08:42.290478 WR_PST = 0x0
2350 11:08:42.290893 DBI_WR = 0x0
2351 11:08:42.293376 DBI_RD = 0x0
2352 11:08:42.293870 OTF = 0x1
2353 11:08:42.296693 ===================================
2354 11:08:42.303780 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2355 11:08:42.304298 ==
2356 11:08:42.307029 Dram Type= 6, Freq= 0, CH_0, rank 0
2357 11:08:42.313135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 11:08:42.313554 ==
2359 11:08:42.313882 [Duty_Offset_Calibration]
2360 11:08:42.317108 B0:1 B1:-1 CA:0
2361 11:08:42.317526
2362 11:08:42.319591 [DutyScan_Calibration_Flow] k_type=0
2363 11:08:42.329254
2364 11:08:42.329773 ==CLK 0==
2365 11:08:42.332343 Final CLK duty delay cell = 0
2366 11:08:42.335838 [0] MAX Duty = 5125%(X100), DQS PI = 24
2367 11:08:42.339216 [0] MIN Duty = 4907%(X100), DQS PI = 8
2368 11:08:42.339633 [0] AVG Duty = 5016%(X100)
2369 11:08:42.342624
2370 11:08:42.345653 CH0 CLK Duty spec in!! Max-Min= 218%
2371 11:08:42.348975 [DutyScan_Calibration_Flow] ====Done====
2372 11:08:42.349445
2373 11:08:42.352011 [DutyScan_Calibration_Flow] k_type=1
2374 11:08:42.367615
2375 11:08:42.368135 ==DQS 0 ==
2376 11:08:42.370806 Final DQS duty delay cell = -4
2377 11:08:42.373992 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2378 11:08:42.377748 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2379 11:08:42.381173 [-4] AVG Duty = 4968%(X100)
2380 11:08:42.381592
2381 11:08:42.381928 ==DQS 1 ==
2382 11:08:42.384178 Final DQS duty delay cell = 0
2383 11:08:42.387505 [0] MAX Duty = 5124%(X100), DQS PI = 4
2384 11:08:42.391191 [0] MIN Duty = 5000%(X100), DQS PI = 22
2385 11:08:42.394409 [0] AVG Duty = 5062%(X100)
2386 11:08:42.394901
2387 11:08:42.397501 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2388 11:08:42.398064
2389 11:08:42.400658 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2390 11:08:42.404250 [DutyScan_Calibration_Flow] ====Done====
2391 11:08:42.404670
2392 11:08:42.407344 [DutyScan_Calibration_Flow] k_type=3
2393 11:08:42.425286
2394 11:08:42.425771 ==DQM 0 ==
2395 11:08:42.428450 Final DQM duty delay cell = 0
2396 11:08:42.431776 [0] MAX Duty = 5062%(X100), DQS PI = 20
2397 11:08:42.435759 [0] MIN Duty = 4875%(X100), DQS PI = 8
2398 11:08:42.438144 [0] AVG Duty = 4968%(X100)
2399 11:08:42.438560
2400 11:08:42.438888 ==DQM 1 ==
2401 11:08:42.441754 Final DQM duty delay cell = 4
2402 11:08:42.445242 [4] MAX Duty = 5187%(X100), DQS PI = 14
2403 11:08:42.448446 [4] MIN Duty = 5000%(X100), DQS PI = 24
2404 11:08:42.451395 [4] AVG Duty = 5093%(X100)
2405 11:08:42.451848
2406 11:08:42.454950 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2407 11:08:42.455372
2408 11:08:42.458261 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2409 11:08:42.461439 [DutyScan_Calibration_Flow] ====Done====
2410 11:08:42.461858
2411 11:08:42.464365 [DutyScan_Calibration_Flow] k_type=2
2412 11:08:42.479822
2413 11:08:42.480323 ==DQ 0 ==
2414 11:08:42.483082 Final DQ duty delay cell = -4
2415 11:08:42.486455 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2416 11:08:42.490110 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2417 11:08:42.493393 [-4] AVG Duty = 4969%(X100)
2418 11:08:42.493914
2419 11:08:42.494255 ==DQ 1 ==
2420 11:08:42.496829 Final DQ duty delay cell = -4
2421 11:08:42.500142 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2422 11:08:42.503185 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2423 11:08:42.506574 [-4] AVG Duty = 4922%(X100)
2424 11:08:42.507000
2425 11:08:42.509749 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2426 11:08:42.510292
2427 11:08:42.513343 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2428 11:08:42.516704 [DutyScan_Calibration_Flow] ====Done====
2429 11:08:42.517124 ==
2430 11:08:42.519910 Dram Type= 6, Freq= 0, CH_1, rank 0
2431 11:08:42.522951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2432 11:08:42.523375 ==
2433 11:08:42.526895 [Duty_Offset_Calibration]
2434 11:08:42.527424 B0:-1 B1:1 CA:1
2435 11:08:42.527820
2436 11:08:42.529887 [DutyScan_Calibration_Flow] k_type=0
2437 11:08:42.540911
2438 11:08:42.541430 ==CLK 0==
2439 11:08:42.544428 Final CLK duty delay cell = 0
2440 11:08:42.547496 [0] MAX Duty = 5156%(X100), DQS PI = 22
2441 11:08:42.550450 [0] MIN Duty = 4969%(X100), DQS PI = 60
2442 11:08:42.551018 [0] AVG Duty = 5062%(X100)
2443 11:08:42.554055
2444 11:08:42.557422 CH1 CLK Duty spec in!! Max-Min= 187%
2445 11:08:42.560484 [DutyScan_Calibration_Flow] ====Done====
2446 11:08:42.560905
2447 11:08:42.563487 [DutyScan_Calibration_Flow] k_type=1
2448 11:08:42.580016
2449 11:08:42.580572 ==DQS 0 ==
2450 11:08:42.583309 Final DQS duty delay cell = 0
2451 11:08:42.586336 [0] MAX Duty = 5125%(X100), DQS PI = 48
2452 11:08:42.589834 [0] MIN Duty = 4907%(X100), DQS PI = 6
2453 11:08:42.593204 [0] AVG Duty = 5016%(X100)
2454 11:08:42.593670
2455 11:08:42.594040 ==DQS 1 ==
2456 11:08:42.596528 Final DQS duty delay cell = 0
2457 11:08:42.600270 [0] MAX Duty = 5094%(X100), DQS PI = 12
2458 11:08:42.603120 [0] MIN Duty = 4969%(X100), DQS PI = 58
2459 11:08:42.606683 [0] AVG Duty = 5031%(X100)
2460 11:08:42.607146
2461 11:08:42.609685 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2462 11:08:42.610153
2463 11:08:42.612983 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2464 11:08:42.616626 [DutyScan_Calibration_Flow] ====Done====
2465 11:08:42.617046
2466 11:08:42.620168 [DutyScan_Calibration_Flow] k_type=3
2467 11:08:42.635794
2468 11:08:42.636303 ==DQM 0 ==
2469 11:08:42.638712 Final DQM duty delay cell = -4
2470 11:08:42.642390 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2471 11:08:42.645800 [-4] MIN Duty = 4844%(X100), DQS PI = 6
2472 11:08:42.648904 [-4] AVG Duty = 4937%(X100)
2473 11:08:42.649325
2474 11:08:42.649659 ==DQM 1 ==
2475 11:08:42.652690 Final DQM duty delay cell = 0
2476 11:08:42.656347 [0] MAX Duty = 5187%(X100), DQS PI = 6
2477 11:08:42.658796 [0] MIN Duty = 5000%(X100), DQS PI = 28
2478 11:08:42.662230 [0] AVG Duty = 5093%(X100)
2479 11:08:42.662764
2480 11:08:42.665712 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2481 11:08:42.666133
2482 11:08:42.668530 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2483 11:08:42.672570 [DutyScan_Calibration_Flow] ====Done====
2484 11:08:42.673095
2485 11:08:42.675141 [DutyScan_Calibration_Flow] k_type=2
2486 11:08:42.692791
2487 11:08:42.693355 ==DQ 0 ==
2488 11:08:42.695777 Final DQ duty delay cell = 0
2489 11:08:42.698612 [0] MAX Duty = 5156%(X100), DQS PI = 28
2490 11:08:42.701891 [0] MIN Duty = 4907%(X100), DQS PI = 6
2491 11:08:42.702424 [0] AVG Duty = 5031%(X100)
2492 11:08:42.705121
2493 11:08:42.705582 ==DQ 1 ==
2494 11:08:42.708678 Final DQ duty delay cell = 0
2495 11:08:42.711770 [0] MAX Duty = 5124%(X100), DQS PI = 10
2496 11:08:42.715423 [0] MIN Duty = 4969%(X100), DQS PI = 0
2497 11:08:42.715886 [0] AVG Duty = 5046%(X100)
2498 11:08:42.718581
2499 11:08:42.722039 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2500 11:08:42.722463
2501 11:08:42.724960 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2502 11:08:42.728212 [DutyScan_Calibration_Flow] ====Done====
2503 11:08:42.731753 nWR fixed to 30
2504 11:08:42.732179 [ModeRegInit_LP4] CH0 RK0
2505 11:08:42.735508 [ModeRegInit_LP4] CH0 RK1
2506 11:08:42.738685 [ModeRegInit_LP4] CH1 RK0
2507 11:08:42.741501 [ModeRegInit_LP4] CH1 RK1
2508 11:08:42.741921 match AC timing 7
2509 11:08:42.744967 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2510 11:08:42.751476 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2511 11:08:42.755250 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2512 11:08:42.761572 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2513 11:08:42.764788 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2514 11:08:42.765265 ==
2515 11:08:42.768164 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 11:08:42.771482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 11:08:42.771946 ==
2518 11:08:42.778467 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 11:08:42.784336 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2520 11:08:42.792054 [CA 0] Center 39 (9~70) winsize 62
2521 11:08:42.795341 [CA 1] Center 39 (9~70) winsize 62
2522 11:08:42.798803 [CA 2] Center 35 (5~66) winsize 62
2523 11:08:42.802501 [CA 3] Center 35 (5~66) winsize 62
2524 11:08:42.805415 [CA 4] Center 34 (4~64) winsize 61
2525 11:08:42.808867 [CA 5] Center 33 (4~63) winsize 60
2526 11:08:42.809335
2527 11:08:42.811964 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2528 11:08:42.812583
2529 11:08:42.815043 [CATrainingPosCal] consider 1 rank data
2530 11:08:42.818645 u2DelayCellTimex100 = 270/100 ps
2531 11:08:42.822072 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2532 11:08:42.825286 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2533 11:08:42.832272 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2534 11:08:42.835330 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2535 11:08:42.839213 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2536 11:08:42.842025 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2537 11:08:42.842455
2538 11:08:42.846064 CA PerBit enable=1, Macro0, CA PI delay=33
2539 11:08:42.846487
2540 11:08:42.848538 [CBTSetCACLKResult] CA Dly = 33
2541 11:08:42.848961 CS Dly: 8 (0~39)
2542 11:08:42.851356 ==
2543 11:08:42.854984 Dram Type= 6, Freq= 0, CH_0, rank 1
2544 11:08:42.858368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2545 11:08:42.858790 ==
2546 11:08:42.861860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2547 11:08:42.868182 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2548 11:08:42.878177 [CA 0] Center 39 (9~70) winsize 62
2549 11:08:42.881062 [CA 1] Center 39 (9~70) winsize 62
2550 11:08:42.884470 [CA 2] Center 35 (5~66) winsize 62
2551 11:08:42.887734 [CA 3] Center 34 (4~65) winsize 62
2552 11:08:42.890768 [CA 4] Center 33 (3~64) winsize 62
2553 11:08:42.893965 [CA 5] Center 33 (3~63) winsize 61
2554 11:08:42.894460
2555 11:08:42.897329 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2556 11:08:42.897751
2557 11:08:42.900902 [CATrainingPosCal] consider 2 rank data
2558 11:08:42.903652 u2DelayCellTimex100 = 270/100 ps
2559 11:08:42.907429 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2560 11:08:42.913664 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2561 11:08:42.917437 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2562 11:08:42.920296 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2563 11:08:42.923881 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2564 11:08:42.927050 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2565 11:08:42.927475
2566 11:08:42.930422 CA PerBit enable=1, Macro0, CA PI delay=33
2567 11:08:42.930941
2568 11:08:42.934065 [CBTSetCACLKResult] CA Dly = 33
2569 11:08:42.937186 CS Dly: 9 (0~41)
2570 11:08:42.937604
2571 11:08:42.940564 ----->DramcWriteLeveling(PI) begin...
2572 11:08:42.940992 ==
2573 11:08:42.944028 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 11:08:42.946921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 11:08:42.947452 ==
2576 11:08:42.950599 Write leveling (Byte 0): 32 => 32
2577 11:08:42.953602 Write leveling (Byte 1): 29 => 29
2578 11:08:42.957017 DramcWriteLeveling(PI) end<-----
2579 11:08:42.957534
2580 11:08:42.957868 ==
2581 11:08:42.959939 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 11:08:42.963262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 11:08:42.963790 ==
2584 11:08:42.966862 [Gating] SW mode calibration
2585 11:08:42.973272 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2586 11:08:42.980285 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2587 11:08:42.983345 0 15 0 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
2588 11:08:42.986474 0 15 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2589 11:08:42.993119 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2590 11:08:42.996729 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 11:08:43.000801 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 11:08:43.006783 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 11:08:43.010168 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 11:08:43.013568 0 15 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
2595 11:08:43.020177 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
2596 11:08:43.023038 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 11:08:43.026526 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 11:08:43.032728 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 11:08:43.036341 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 11:08:43.039531 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 11:08:43.046607 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 11:08:43.049487 1 0 28 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
2603 11:08:43.052659 1 1 0 | B1->B0 | 2323 4040 | 0 0 | (0 0) (1 1)
2604 11:08:43.059111 1 1 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2605 11:08:43.063177 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 11:08:43.066385 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 11:08:43.072998 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 11:08:43.076286 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 11:08:43.079473 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 11:08:43.085610 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2611 11:08:43.089210 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2612 11:08:43.093037 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 11:08:43.098916 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 11:08:43.102701 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 11:08:43.105528 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 11:08:43.112169 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 11:08:43.115380 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 11:08:43.118537 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 11:08:43.125126 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 11:08:43.128870 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 11:08:43.131929 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 11:08:43.138650 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 11:08:43.142178 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 11:08:43.144995 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 11:08:43.151921 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 11:08:43.155272 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2627 11:08:43.158835 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2628 11:08:43.161761 Total UI for P1: 0, mck2ui 16
2629 11:08:43.164998 best dqsien dly found for B0: ( 1, 3, 28)
2630 11:08:43.171617 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2631 11:08:43.172080 Total UI for P1: 0, mck2ui 16
2632 11:08:43.177999 best dqsien dly found for B1: ( 1, 4, 0)
2633 11:08:43.181915 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2634 11:08:43.184700 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2635 11:08:43.185130
2636 11:08:43.188600 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2637 11:08:43.191763 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2638 11:08:43.194617 [Gating] SW calibration Done
2639 11:08:43.195039 ==
2640 11:08:43.198280 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 11:08:43.201788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 11:08:43.202214 ==
2643 11:08:43.204859 RX Vref Scan: 0
2644 11:08:43.205280
2645 11:08:43.205618 RX Vref 0 -> 0, step: 1
2646 11:08:43.205934
2647 11:08:43.208556 RX Delay -40 -> 252, step: 8
2648 11:08:43.211533 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2649 11:08:43.217885 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2650 11:08:43.222208 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2651 11:08:43.224769 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2652 11:08:43.228267 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2653 11:08:43.231782 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2654 11:08:43.238168 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2655 11:08:43.241694 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2656 11:08:43.245112 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2657 11:08:43.247809 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2658 11:08:43.251580 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2659 11:08:43.254620 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2660 11:08:43.261289 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2661 11:08:43.265150 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2662 11:08:43.267958 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2663 11:08:43.271503 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2664 11:08:43.272117 ==
2665 11:08:43.274588 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 11:08:43.281494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 11:08:43.282028 ==
2668 11:08:43.282401 DQS Delay:
2669 11:08:43.284205 DQS0 = 0, DQS1 = 0
2670 11:08:43.284691 DQM Delay:
2671 11:08:43.287830 DQM0 = 119, DQM1 = 106
2672 11:08:43.288299 DQ Delay:
2673 11:08:43.290968 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2674 11:08:43.294696 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2675 11:08:43.297769 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2676 11:08:43.300875 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2677 11:08:43.301299
2678 11:08:43.301632
2679 11:08:43.301944 ==
2680 11:08:43.304732 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 11:08:43.311523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 11:08:43.312149 ==
2683 11:08:43.312496
2684 11:08:43.312808
2685 11:08:43.313105 TX Vref Scan disable
2686 11:08:43.314552 == TX Byte 0 ==
2687 11:08:43.318020 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2688 11:08:43.324126 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2689 11:08:43.324549 == TX Byte 1 ==
2690 11:08:43.327875 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2691 11:08:43.334274 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2692 11:08:43.334793 ==
2693 11:08:43.337176 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 11:08:43.340473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 11:08:43.340900 ==
2696 11:08:43.352295 TX Vref=22, minBit 5, minWin=24, winSum=412
2697 11:08:43.356033 TX Vref=24, minBit 13, minWin=25, winSum=423
2698 11:08:43.359072 TX Vref=26, minBit 1, minWin=26, winSum=427
2699 11:08:43.362055 TX Vref=28, minBit 0, minWin=27, winSum=433
2700 11:08:43.365412 TX Vref=30, minBit 5, minWin=26, winSum=432
2701 11:08:43.371958 TX Vref=32, minBit 1, minWin=26, winSum=432
2702 11:08:43.375495 [TxChooseVref] Worse bit 0, Min win 27, Win sum 433, Final Vref 28
2703 11:08:43.376068
2704 11:08:43.378553 Final TX Range 1 Vref 28
2705 11:08:43.378978
2706 11:08:43.379315 ==
2707 11:08:43.381771 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 11:08:43.385188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 11:08:43.388414 ==
2710 11:08:43.388838
2711 11:08:43.389177
2712 11:08:43.389491 TX Vref Scan disable
2713 11:08:43.391754 == TX Byte 0 ==
2714 11:08:43.395204 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2715 11:08:43.401770 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2716 11:08:43.402293 == TX Byte 1 ==
2717 11:08:43.405258 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2718 11:08:43.411713 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2719 11:08:43.412142
2720 11:08:43.412538 [DATLAT]
2721 11:08:43.413026 Freq=1200, CH0 RK0
2722 11:08:43.413358
2723 11:08:43.415082 DATLAT Default: 0xd
2724 11:08:43.418523 0, 0xFFFF, sum = 0
2725 11:08:43.419100 1, 0xFFFF, sum = 0
2726 11:08:43.421264 2, 0xFFFF, sum = 0
2727 11:08:43.421700 3, 0xFFFF, sum = 0
2728 11:08:43.425200 4, 0xFFFF, sum = 0
2729 11:08:43.425631 5, 0xFFFF, sum = 0
2730 11:08:43.428118 6, 0xFFFF, sum = 0
2731 11:08:43.428594 7, 0xFFFF, sum = 0
2732 11:08:43.431482 8, 0xFFFF, sum = 0
2733 11:08:43.432062 9, 0xFFFF, sum = 0
2734 11:08:43.435004 10, 0xFFFF, sum = 0
2735 11:08:43.435436 11, 0xFFFF, sum = 0
2736 11:08:43.438227 12, 0x0, sum = 1
2737 11:08:43.438755 13, 0x0, sum = 2
2738 11:08:43.441658 14, 0x0, sum = 3
2739 11:08:43.442093 15, 0x0, sum = 4
2740 11:08:43.445177 best_step = 13
2741 11:08:43.445702
2742 11:08:43.446046 ==
2743 11:08:43.448002 Dram Type= 6, Freq= 0, CH_0, rank 0
2744 11:08:43.451268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2745 11:08:43.451739 ==
2746 11:08:43.454957 RX Vref Scan: 1
2747 11:08:43.455474
2748 11:08:43.455852 Set Vref Range= 32 -> 127
2749 11:08:43.456177
2750 11:08:43.458491 RX Vref 32 -> 127, step: 1
2751 11:08:43.459013
2752 11:08:43.461904 RX Delay -21 -> 252, step: 4
2753 11:08:43.462427
2754 11:08:43.464727 Set Vref, RX VrefLevel [Byte0]: 32
2755 11:08:43.468177 [Byte1]: 32
2756 11:08:43.468602
2757 11:08:43.471129 Set Vref, RX VrefLevel [Byte0]: 33
2758 11:08:43.474203 [Byte1]: 33
2759 11:08:43.478326
2760 11:08:43.478746 Set Vref, RX VrefLevel [Byte0]: 34
2761 11:08:43.481743 [Byte1]: 34
2762 11:08:43.486866
2763 11:08:43.487287 Set Vref, RX VrefLevel [Byte0]: 35
2764 11:08:43.489454 [Byte1]: 35
2765 11:08:43.494469
2766 11:08:43.494952 Set Vref, RX VrefLevel [Byte0]: 36
2767 11:08:43.497419 [Byte1]: 36
2768 11:08:43.502604
2769 11:08:43.503036 Set Vref, RX VrefLevel [Byte0]: 37
2770 11:08:43.505424 [Byte1]: 37
2771 11:08:43.510454
2772 11:08:43.511013 Set Vref, RX VrefLevel [Byte0]: 38
2773 11:08:43.513489 [Byte1]: 38
2774 11:08:43.519515
2775 11:08:43.520013 Set Vref, RX VrefLevel [Byte0]: 39
2776 11:08:43.521961 [Byte1]: 39
2777 11:08:43.526365
2778 11:08:43.526782 Set Vref, RX VrefLevel [Byte0]: 40
2779 11:08:43.529905 [Byte1]: 40
2780 11:08:43.533857
2781 11:08:43.534378 Set Vref, RX VrefLevel [Byte0]: 41
2782 11:08:43.537185 [Byte1]: 41
2783 11:08:43.542526
2784 11:08:43.543069 Set Vref, RX VrefLevel [Byte0]: 42
2785 11:08:43.545312 [Byte1]: 42
2786 11:08:43.549695
2787 11:08:43.550118 Set Vref, RX VrefLevel [Byte0]: 43
2788 11:08:43.552960 [Byte1]: 43
2789 11:08:43.557764
2790 11:08:43.558190 Set Vref, RX VrefLevel [Byte0]: 44
2791 11:08:43.561301 [Byte1]: 44
2792 11:08:43.565653
2793 11:08:43.566074 Set Vref, RX VrefLevel [Byte0]: 45
2794 11:08:43.569185 [Byte1]: 45
2795 11:08:43.573338
2796 11:08:43.573757 Set Vref, RX VrefLevel [Byte0]: 46
2797 11:08:43.576941 [Byte1]: 46
2798 11:08:43.581505
2799 11:08:43.581941 Set Vref, RX VrefLevel [Byte0]: 47
2800 11:08:43.584849 [Byte1]: 47
2801 11:08:43.589645
2802 11:08:43.590196 Set Vref, RX VrefLevel [Byte0]: 48
2803 11:08:43.592918 [Byte1]: 48
2804 11:08:43.597615
2805 11:08:43.598106 Set Vref, RX VrefLevel [Byte0]: 49
2806 11:08:43.600644 [Byte1]: 49
2807 11:08:43.605130
2808 11:08:43.605637 Set Vref, RX VrefLevel [Byte0]: 50
2809 11:08:43.608644 [Byte1]: 50
2810 11:08:43.613484
2811 11:08:43.613997 Set Vref, RX VrefLevel [Byte0]: 51
2812 11:08:43.616550 [Byte1]: 51
2813 11:08:43.621568
2814 11:08:43.622002 Set Vref, RX VrefLevel [Byte0]: 52
2815 11:08:43.624561 [Byte1]: 52
2816 11:08:43.629281
2817 11:08:43.629702 Set Vref, RX VrefLevel [Byte0]: 53
2818 11:08:43.632322 [Byte1]: 53
2819 11:08:43.637419
2820 11:08:43.637938 Set Vref, RX VrefLevel [Byte0]: 54
2821 11:08:43.640612 [Byte1]: 54
2822 11:08:43.645682
2823 11:08:43.646208 Set Vref, RX VrefLevel [Byte0]: 55
2824 11:08:43.648200 [Byte1]: 55
2825 11:08:43.653046
2826 11:08:43.653584 Set Vref, RX VrefLevel [Byte0]: 56
2827 11:08:43.655992 [Byte1]: 56
2828 11:08:43.660797
2829 11:08:43.661217 Set Vref, RX VrefLevel [Byte0]: 57
2830 11:08:43.664370 [Byte1]: 57
2831 11:08:43.668616
2832 11:08:43.669311 Set Vref, RX VrefLevel [Byte0]: 58
2833 11:08:43.672140 [Byte1]: 58
2834 11:08:43.676590
2835 11:08:43.677010 Set Vref, RX VrefLevel [Byte0]: 59
2836 11:08:43.679711 [Byte1]: 59
2837 11:08:43.684525
2838 11:08:43.684823 Set Vref, RX VrefLevel [Byte0]: 60
2839 11:08:43.687384 [Byte1]: 60
2840 11:08:43.692514
2841 11:08:43.692789 Set Vref, RX VrefLevel [Byte0]: 61
2842 11:08:43.695641 [Byte1]: 61
2843 11:08:43.700664
2844 11:08:43.700834 Set Vref, RX VrefLevel [Byte0]: 62
2845 11:08:43.703218 [Byte1]: 62
2846 11:08:43.708384
2847 11:08:43.708544 Set Vref, RX VrefLevel [Byte0]: 63
2848 11:08:43.711243 [Byte1]: 63
2849 11:08:43.715798
2850 11:08:43.715938 Set Vref, RX VrefLevel [Byte0]: 64
2851 11:08:43.718901 [Byte1]: 64
2852 11:08:43.724043
2853 11:08:43.724367 Set Vref, RX VrefLevel [Byte0]: 65
2854 11:08:43.727781 [Byte1]: 65
2855 11:08:43.732090
2856 11:08:43.732421 Set Vref, RX VrefLevel [Byte0]: 66
2857 11:08:43.735345 [Byte1]: 66
2858 11:08:43.739948
2859 11:08:43.740372 Set Vref, RX VrefLevel [Byte0]: 67
2860 11:08:43.743516 [Byte1]: 67
2861 11:08:43.747839
2862 11:08:43.748340 Set Vref, RX VrefLevel [Byte0]: 68
2863 11:08:43.751120 [Byte1]: 68
2864 11:08:43.755526
2865 11:08:43.755885 Set Vref, RX VrefLevel [Byte0]: 69
2866 11:08:43.759107 [Byte1]: 69
2867 11:08:43.763731
2868 11:08:43.764221 Set Vref, RX VrefLevel [Byte0]: 70
2869 11:08:43.767149 [Byte1]: 70
2870 11:08:43.771799
2871 11:08:43.772378 Set Vref, RX VrefLevel [Byte0]: 71
2872 11:08:43.775387 [Byte1]: 71
2873 11:08:43.779665
2874 11:08:43.780192 Set Vref, RX VrefLevel [Byte0]: 72
2875 11:08:43.782807 [Byte1]: 72
2876 11:08:43.787945
2877 11:08:43.788473 Set Vref, RX VrefLevel [Byte0]: 73
2878 11:08:43.791344 [Byte1]: 73
2879 11:08:43.795565
2880 11:08:43.796042 Set Vref, RX VrefLevel [Byte0]: 74
2881 11:08:43.799056 [Byte1]: 74
2882 11:08:43.803544
2883 11:08:43.804076 Set Vref, RX VrefLevel [Byte0]: 75
2884 11:08:43.806678 [Byte1]: 75
2885 11:08:43.811104
2886 11:08:43.815165 Set Vref, RX VrefLevel [Byte0]: 76
2887 11:08:43.817582 [Byte1]: 76
2888 11:08:43.818035
2889 11:08:43.821376 Set Vref, RX VrefLevel [Byte0]: 77
2890 11:08:43.824365 [Byte1]: 77
2891 11:08:43.824790
2892 11:08:43.827544 Final RX Vref Byte 0 = 60 to rank0
2893 11:08:43.831361 Final RX Vref Byte 1 = 48 to rank0
2894 11:08:43.834318 Final RX Vref Byte 0 = 60 to rank1
2895 11:08:43.838065 Final RX Vref Byte 1 = 48 to rank1==
2896 11:08:43.841105 Dram Type= 6, Freq= 0, CH_0, rank 0
2897 11:08:43.844605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 11:08:43.847783 ==
2899 11:08:43.848295 DQS Delay:
2900 11:08:43.848631 DQS0 = 0, DQS1 = 0
2901 11:08:43.851249 DQM Delay:
2902 11:08:43.851796 DQM0 = 119, DQM1 = 106
2903 11:08:43.854467 DQ Delay:
2904 11:08:43.857916 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2905 11:08:43.861110 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
2906 11:08:43.864391 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =100
2907 11:08:43.867718 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2908 11:08:43.868175
2909 11:08:43.868526
2910 11:08:43.874343 [DQSOSCAuto] RK0, (LSB)MR18= 0xefa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 404 ps
2911 11:08:43.877338 CH0 RK0: MR19=403, MR18=EFA
2912 11:08:43.883725 CH0_RK0: MR19=0x403, MR18=0xEFA, DQSOSC=404, MR23=63, INC=40, DEC=26
2913 11:08:43.884271
2914 11:08:43.887005 ----->DramcWriteLeveling(PI) begin...
2915 11:08:43.887435 ==
2916 11:08:43.890417 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 11:08:43.893817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 11:08:43.894318 ==
2919 11:08:43.897404 Write leveling (Byte 0): 33 => 33
2920 11:08:43.900207 Write leveling (Byte 1): 31 => 31
2921 11:08:43.903749 DramcWriteLeveling(PI) end<-----
2922 11:08:43.904178
2923 11:08:43.904517 ==
2924 11:08:43.907136 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 11:08:43.913623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2926 11:08:43.914130 ==
2927 11:08:43.914480 [Gating] SW mode calibration
2928 11:08:43.923197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2929 11:08:43.926505 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2930 11:08:43.933691 0 15 0 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
2931 11:08:43.936611 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2932 11:08:43.939948 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2933 11:08:43.946510 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2934 11:08:43.949820 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2935 11:08:43.954161 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2936 11:08:43.959979 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2937 11:08:43.962984 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
2938 11:08:43.966380 1 0 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
2939 11:08:43.972802 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2940 11:08:43.976338 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2941 11:08:43.979880 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2942 11:08:43.986340 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2943 11:08:43.989275 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2944 11:08:43.993549 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2945 11:08:43.999654 1 0 28 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
2946 11:08:44.002785 1 1 0 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
2947 11:08:44.006188 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 11:08:44.012713 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 11:08:44.015324 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 11:08:44.018950 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2951 11:08:44.025679 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2952 11:08:44.029056 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2953 11:08:44.032589 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2954 11:08:44.038815 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 11:08:44.041810 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 11:08:44.045148 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 11:08:44.051912 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 11:08:44.055296 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 11:08:44.058789 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 11:08:44.065693 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 11:08:44.068190 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 11:08:44.072187 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 11:08:44.078577 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 11:08:44.081468 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 11:08:44.084896 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 11:08:44.091624 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 11:08:44.094885 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 11:08:44.098691 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 11:08:44.104865 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2970 11:08:44.107964 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 11:08:44.111159 Total UI for P1: 0, mck2ui 16
2972 11:08:44.114322 best dqsien dly found for B0: ( 1, 3, 28)
2973 11:08:44.117865 Total UI for P1: 0, mck2ui 16
2974 11:08:44.121239 best dqsien dly found for B1: ( 1, 3, 30)
2975 11:08:44.124748 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2976 11:08:44.128007 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2977 11:08:44.128547
2978 11:08:44.131056 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2979 11:08:44.134808 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2980 11:08:44.138306 [Gating] SW calibration Done
2981 11:08:44.138863 ==
2982 11:08:44.141208 Dram Type= 6, Freq= 0, CH_0, rank 1
2983 11:08:44.144695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2984 11:08:44.145336 ==
2985 11:08:44.147349 RX Vref Scan: 0
2986 11:08:44.147980
2987 11:08:44.150942 RX Vref 0 -> 0, step: 1
2988 11:08:44.151635
2989 11:08:44.152051 RX Delay -40 -> 252, step: 8
2990 11:08:44.157701 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2991 11:08:44.161014 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2992 11:08:44.164101 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2993 11:08:44.167412 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2994 11:08:44.170517 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2995 11:08:44.177086 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2996 11:08:44.181004 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2997 11:08:44.184331 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2998 11:08:44.187304 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2999 11:08:44.194396 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3000 11:08:44.197846 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3001 11:08:44.200951 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3002 11:08:44.203743 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3003 11:08:44.206861 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3004 11:08:44.213308 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3005 11:08:44.216644 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3006 11:08:44.217279 ==
3007 11:08:44.220560 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 11:08:44.223163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 11:08:44.223786 ==
3010 11:08:44.226893 DQS Delay:
3011 11:08:44.227489 DQS0 = 0, DQS1 = 0
3012 11:08:44.229753 DQM Delay:
3013 11:08:44.230299 DQM0 = 116, DQM1 = 108
3014 11:08:44.230773 DQ Delay:
3015 11:08:44.233139 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
3016 11:08:44.239649 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3017 11:08:44.243369 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3018 11:08:44.246532 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3019 11:08:44.246951
3020 11:08:44.247281
3021 11:08:44.247594 ==
3022 11:08:44.249296 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 11:08:44.253019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 11:08:44.253442 ==
3025 11:08:44.253775
3026 11:08:44.254082
3027 11:08:44.256322 TX Vref Scan disable
3028 11:08:44.259424 == TX Byte 0 ==
3029 11:08:44.262902 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3030 11:08:44.266314 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3031 11:08:44.269552 == TX Byte 1 ==
3032 11:08:44.272836 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3033 11:08:44.276456 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3034 11:08:44.276879 ==
3035 11:08:44.279746 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 11:08:44.283015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 11:08:44.286222 ==
3038 11:08:44.295862 TX Vref=22, minBit 3, minWin=25, winSum=418
3039 11:08:44.299119 TX Vref=24, minBit 1, minWin=25, winSum=425
3040 11:08:44.303517 TX Vref=26, minBit 1, minWin=26, winSum=431
3041 11:08:44.306104 TX Vref=28, minBit 1, minWin=26, winSum=431
3042 11:08:44.309455 TX Vref=30, minBit 10, minWin=26, winSum=433
3043 11:08:44.316241 TX Vref=32, minBit 12, minWin=26, winSum=434
3044 11:08:44.318998 [TxChooseVref] Worse bit 12, Min win 26, Win sum 434, Final Vref 32
3045 11:08:44.319658
3046 11:08:44.322792 Final TX Range 1 Vref 32
3047 11:08:44.323219
3048 11:08:44.323554 ==
3049 11:08:44.325920 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 11:08:44.333159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 11:08:44.333699 ==
3052 11:08:44.334044
3053 11:08:44.334358
3054 11:08:44.334659 TX Vref Scan disable
3055 11:08:44.336830 == TX Byte 0 ==
3056 11:08:44.339452 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3057 11:08:44.346788 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3058 11:08:44.347333 == TX Byte 1 ==
3059 11:08:44.349403 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3060 11:08:44.355624 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3061 11:08:44.356108
3062 11:08:44.356443 [DATLAT]
3063 11:08:44.356752 Freq=1200, CH0 RK1
3064 11:08:44.357056
3065 11:08:44.359219 DATLAT Default: 0xd
3066 11:08:44.362917 0, 0xFFFF, sum = 0
3067 11:08:44.363449 1, 0xFFFF, sum = 0
3068 11:08:44.365833 2, 0xFFFF, sum = 0
3069 11:08:44.366274 3, 0xFFFF, sum = 0
3070 11:08:44.369277 4, 0xFFFF, sum = 0
3071 11:08:44.369707 5, 0xFFFF, sum = 0
3072 11:08:44.372949 6, 0xFFFF, sum = 0
3073 11:08:44.373479 7, 0xFFFF, sum = 0
3074 11:08:44.376406 8, 0xFFFF, sum = 0
3075 11:08:44.376942 9, 0xFFFF, sum = 0
3076 11:08:44.379448 10, 0xFFFF, sum = 0
3077 11:08:44.380036 11, 0xFFFF, sum = 0
3078 11:08:44.382458 12, 0x0, sum = 1
3079 11:08:44.382990 13, 0x0, sum = 2
3080 11:08:44.385685 14, 0x0, sum = 3
3081 11:08:44.386112 15, 0x0, sum = 4
3082 11:08:44.389399 best_step = 13
3083 11:08:44.389937
3084 11:08:44.390305 ==
3085 11:08:44.392214 Dram Type= 6, Freq= 0, CH_0, rank 1
3086 11:08:44.395570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3087 11:08:44.396128 ==
3088 11:08:44.398930 RX Vref Scan: 0
3089 11:08:44.399453
3090 11:08:44.399833 RX Vref 0 -> 0, step: 1
3091 11:08:44.400151
3092 11:08:44.402490 RX Delay -21 -> 252, step: 4
3093 11:08:44.408506 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3094 11:08:44.412002 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3095 11:08:44.415259 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3096 11:08:44.419216 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3097 11:08:44.422595 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3098 11:08:44.428926 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3099 11:08:44.431475 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3100 11:08:44.435101 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3101 11:08:44.437930 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3102 11:08:44.441510 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3103 11:08:44.448404 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3104 11:08:44.451728 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3105 11:08:44.455062 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3106 11:08:44.458891 iDelay=199, Bit 13, Center 116 (51 ~ 182) 132
3107 11:08:44.461265 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3108 11:08:44.468264 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3109 11:08:44.468707 ==
3110 11:08:44.471338 Dram Type= 6, Freq= 0, CH_0, rank 1
3111 11:08:44.474626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 11:08:44.475058 ==
3113 11:08:44.475395 DQS Delay:
3114 11:08:44.477811 DQS0 = 0, DQS1 = 0
3115 11:08:44.478234 DQM Delay:
3116 11:08:44.481472 DQM0 = 116, DQM1 = 107
3117 11:08:44.481897 DQ Delay:
3118 11:08:44.484343 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3119 11:08:44.487423 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3120 11:08:44.491202 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3121 11:08:44.497606 DQ12 =112, DQ13 =116, DQ14 =118, DQ15 =116
3122 11:08:44.498048
3123 11:08:44.498491
3124 11:08:44.504086 [DQSOSCAuto] RK1, (LSB)MR18= 0x9e5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
3125 11:08:44.507509 CH0 RK1: MR19=403, MR18=9E5
3126 11:08:44.514095 CH0_RK1: MR19=0x403, MR18=0x9E5, DQSOSC=406, MR23=63, INC=39, DEC=26
3127 11:08:44.517393 [RxdqsGatingPostProcess] freq 1200
3128 11:08:44.520851 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3129 11:08:44.524537 best DQS0 dly(2T, 0.5T) = (0, 11)
3130 11:08:44.527789 best DQS1 dly(2T, 0.5T) = (0, 12)
3131 11:08:44.530431 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3132 11:08:44.533837 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3133 11:08:44.537284 best DQS0 dly(2T, 0.5T) = (0, 11)
3134 11:08:44.541003 best DQS1 dly(2T, 0.5T) = (0, 11)
3135 11:08:44.543786 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3136 11:08:44.547402 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3137 11:08:44.550741 Pre-setting of DQS Precalculation
3138 11:08:44.553851 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3139 11:08:44.554281 ==
3140 11:08:44.557473 Dram Type= 6, Freq= 0, CH_1, rank 0
3141 11:08:44.563783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3142 11:08:44.564217 ==
3143 11:08:44.566751 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3144 11:08:44.573700 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3145 11:08:44.582118 [CA 0] Center 38 (8~68) winsize 61
3146 11:08:44.585516 [CA 1] Center 37 (7~68) winsize 62
3147 11:08:44.589378 [CA 2] Center 34 (4~64) winsize 61
3148 11:08:44.592196 [CA 3] Center 33 (3~64) winsize 62
3149 11:08:44.595533 [CA 4] Center 34 (4~64) winsize 61
3150 11:08:44.599062 [CA 5] Center 33 (3~64) winsize 62
3151 11:08:44.599489
3152 11:08:44.602884 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3153 11:08:44.603329
3154 11:08:44.605360 [CATrainingPosCal] consider 1 rank data
3155 11:08:44.609016 u2DelayCellTimex100 = 270/100 ps
3156 11:08:44.612353 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3157 11:08:44.619106 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3158 11:08:44.622030 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3159 11:08:44.625464 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3160 11:08:44.628444 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3161 11:08:44.632372 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3162 11:08:44.632801
3163 11:08:44.635355 CA PerBit enable=1, Macro0, CA PI delay=33
3164 11:08:44.635827
3165 11:08:44.639362 [CBTSetCACLKResult] CA Dly = 33
3166 11:08:44.639980 CS Dly: 6 (0~37)
3167 11:08:44.641961 ==
3168 11:08:44.645100 Dram Type= 6, Freq= 0, CH_1, rank 1
3169 11:08:44.648832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 11:08:44.649263 ==
3171 11:08:44.651856 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3172 11:08:44.658690 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3173 11:08:44.667944 [CA 0] Center 37 (7~68) winsize 62
3174 11:08:44.671141 [CA 1] Center 38 (8~68) winsize 61
3175 11:08:44.674444 [CA 2] Center 34 (4~65) winsize 62
3176 11:08:44.678055 [CA 3] Center 33 (3~64) winsize 62
3177 11:08:44.680735 [CA 4] Center 34 (4~65) winsize 62
3178 11:08:44.684450 [CA 5] Center 33 (3~64) winsize 62
3179 11:08:44.684881
3180 11:08:44.687808 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3181 11:08:44.688239
3182 11:08:44.690893 [CATrainingPosCal] consider 2 rank data
3183 11:08:44.694621 u2DelayCellTimex100 = 270/100 ps
3184 11:08:44.698282 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3185 11:08:44.704589 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3186 11:08:44.708043 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3187 11:08:44.710759 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3188 11:08:44.714250 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3189 11:08:44.717578 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3190 11:08:44.718005
3191 11:08:44.720604 CA PerBit enable=1, Macro0, CA PI delay=33
3192 11:08:44.721037
3193 11:08:44.723990 [CBTSetCACLKResult] CA Dly = 33
3194 11:08:44.724418 CS Dly: 7 (0~40)
3195 11:08:44.727246
3196 11:08:44.730897 ----->DramcWriteLeveling(PI) begin...
3197 11:08:44.731437 ==
3198 11:08:44.734186 Dram Type= 6, Freq= 0, CH_1, rank 0
3199 11:08:44.737442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 11:08:44.737966 ==
3201 11:08:44.740680 Write leveling (Byte 0): 25 => 25
3202 11:08:44.744879 Write leveling (Byte 1): 27 => 27
3203 11:08:44.747515 DramcWriteLeveling(PI) end<-----
3204 11:08:44.748019
3205 11:08:44.748365 ==
3206 11:08:44.750736 Dram Type= 6, Freq= 0, CH_1, rank 0
3207 11:08:44.754084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3208 11:08:44.754517 ==
3209 11:08:44.757284 [Gating] SW mode calibration
3210 11:08:44.763453 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3211 11:08:44.770246 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3212 11:08:44.773616 0 15 0 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
3213 11:08:44.776898 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3214 11:08:44.783957 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3215 11:08:44.786839 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3216 11:08:44.790190 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3217 11:08:44.796621 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3218 11:08:44.800114 0 15 24 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
3219 11:08:44.803173 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3220 11:08:44.810437 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 11:08:44.813117 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3222 11:08:44.816645 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3223 11:08:44.822905 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3224 11:08:44.826558 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3225 11:08:44.829625 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3226 11:08:44.836308 1 0 24 | B1->B0 | 2828 3939 | 0 0 | (0 0) (0 0)
3227 11:08:44.839454 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 11:08:44.843107 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 11:08:44.850008 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 11:08:44.853327 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 11:08:44.856168 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3232 11:08:44.863518 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3233 11:08:44.867186 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3234 11:08:44.869722 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3235 11:08:44.876024 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3236 11:08:44.879444 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 11:08:44.882736 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 11:08:44.889517 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 11:08:44.892492 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 11:08:44.896323 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 11:08:44.902917 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 11:08:44.906757 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 11:08:44.909082 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 11:08:44.912459 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 11:08:44.919739 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 11:08:44.922459 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 11:08:44.929627 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 11:08:44.932499 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 11:08:44.935899 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 11:08:44.942902 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3251 11:08:44.945700 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3252 11:08:44.948813 Total UI for P1: 0, mck2ui 16
3253 11:08:44.952176 best dqsien dly found for B0: ( 1, 3, 24)
3254 11:08:44.956210 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3255 11:08:44.959287 Total UI for P1: 0, mck2ui 16
3256 11:08:44.962196 best dqsien dly found for B1: ( 1, 3, 28)
3257 11:08:44.965526 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3258 11:08:44.969157 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3259 11:08:44.969877
3260 11:08:44.972609 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3261 11:08:44.979238 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3262 11:08:44.979960 [Gating] SW calibration Done
3263 11:08:44.980502 ==
3264 11:08:44.982303 Dram Type= 6, Freq= 0, CH_1, rank 0
3265 11:08:44.988598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3266 11:08:44.989169 ==
3267 11:08:44.989688 RX Vref Scan: 0
3268 11:08:44.990181
3269 11:08:44.991795 RX Vref 0 -> 0, step: 1
3270 11:08:44.992222
3271 11:08:44.995347 RX Delay -40 -> 252, step: 8
3272 11:08:44.998743 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3273 11:08:45.002630 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3274 11:08:45.005773 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3275 11:08:45.012003 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3276 11:08:45.015469 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3277 11:08:45.018961 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3278 11:08:45.021634 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3279 11:08:45.025310 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3280 11:08:45.031824 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3281 11:08:45.035028 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3282 11:08:45.038545 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3283 11:08:45.042323 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3284 11:08:45.045196 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3285 11:08:45.051857 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3286 11:08:45.055122 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3287 11:08:45.058742 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3288 11:08:45.059305 ==
3289 11:08:45.061905 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 11:08:45.064916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 11:08:45.065487 ==
3292 11:08:45.068328 DQS Delay:
3293 11:08:45.068893 DQS0 = 0, DQS1 = 0
3294 11:08:45.071635 DQM Delay:
3295 11:08:45.072241 DQM0 = 117, DQM1 = 110
3296 11:08:45.072613 DQ Delay:
3297 11:08:45.078492 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3298 11:08:45.082118 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3299 11:08:45.084758 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3300 11:08:45.088343 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3301 11:08:45.088915
3302 11:08:45.089285
3303 11:08:45.089624 ==
3304 11:08:45.091433 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 11:08:45.094872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 11:08:45.095435 ==
3307 11:08:45.095852
3308 11:08:45.096197
3309 11:08:45.097924 TX Vref Scan disable
3310 11:08:45.101152 == TX Byte 0 ==
3311 11:08:45.104859 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3312 11:08:45.107990 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3313 11:08:45.111656 == TX Byte 1 ==
3314 11:08:45.114391 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3315 11:08:45.118109 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3316 11:08:45.118682 ==
3317 11:08:45.121315 Dram Type= 6, Freq= 0, CH_1, rank 0
3318 11:08:45.124097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3319 11:08:45.127521 ==
3320 11:08:45.138165 TX Vref=22, minBit 8, minWin=25, winSum=415
3321 11:08:45.141384 TX Vref=24, minBit 8, minWin=25, winSum=422
3322 11:08:45.144590 TX Vref=26, minBit 9, minWin=25, winSum=427
3323 11:08:45.147458 TX Vref=28, minBit 9, minWin=26, winSum=432
3324 11:08:45.151784 TX Vref=30, minBit 9, minWin=26, winSum=431
3325 11:08:45.157659 TX Vref=32, minBit 11, minWin=25, winSum=425
3326 11:08:45.161688 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 28
3327 11:08:45.162270
3328 11:08:45.164402 Final TX Range 1 Vref 28
3329 11:08:45.165007
3330 11:08:45.165384 ==
3331 11:08:45.167398 Dram Type= 6, Freq= 0, CH_1, rank 0
3332 11:08:45.170950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3333 11:08:45.174460 ==
3334 11:08:45.174945
3335 11:08:45.175318
3336 11:08:45.175662 TX Vref Scan disable
3337 11:08:45.177788 == TX Byte 0 ==
3338 11:08:45.181467 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3339 11:08:45.187366 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3340 11:08:45.187823 == TX Byte 1 ==
3341 11:08:45.191234 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3342 11:08:45.197259 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3343 11:08:45.197793
3344 11:08:45.198135 [DATLAT]
3345 11:08:45.198451 Freq=1200, CH1 RK0
3346 11:08:45.198750
3347 11:08:45.200350 DATLAT Default: 0xd
3348 11:08:45.203857 0, 0xFFFF, sum = 0
3349 11:08:45.204392 1, 0xFFFF, sum = 0
3350 11:08:45.207206 2, 0xFFFF, sum = 0
3351 11:08:45.207780 3, 0xFFFF, sum = 0
3352 11:08:45.210090 4, 0xFFFF, sum = 0
3353 11:08:45.210518 5, 0xFFFF, sum = 0
3354 11:08:45.214436 6, 0xFFFF, sum = 0
3355 11:08:45.214957 7, 0xFFFF, sum = 0
3356 11:08:45.216895 8, 0xFFFF, sum = 0
3357 11:08:45.217360 9, 0xFFFF, sum = 0
3358 11:08:45.220439 10, 0xFFFF, sum = 0
3359 11:08:45.220906 11, 0xFFFF, sum = 0
3360 11:08:45.223778 12, 0x0, sum = 1
3361 11:08:45.224338 13, 0x0, sum = 2
3362 11:08:45.227281 14, 0x0, sum = 3
3363 11:08:45.227796 15, 0x0, sum = 4
3364 11:08:45.230794 best_step = 13
3365 11:08:45.231254
3366 11:08:45.231578 ==
3367 11:08:45.234030 Dram Type= 6, Freq= 0, CH_1, rank 0
3368 11:08:45.237144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3369 11:08:45.237569 ==
3370 11:08:45.237904 RX Vref Scan: 1
3371 11:08:45.240921
3372 11:08:45.241343 Set Vref Range= 32 -> 127
3373 11:08:45.241675
3374 11:08:45.244186 RX Vref 32 -> 127, step: 1
3375 11:08:45.244616
3376 11:08:45.247193 RX Delay -21 -> 252, step: 4
3377 11:08:45.247776
3378 11:08:45.250705 Set Vref, RX VrefLevel [Byte0]: 32
3379 11:08:45.253979 [Byte1]: 32
3380 11:08:45.254505
3381 11:08:45.257054 Set Vref, RX VrefLevel [Byte0]: 33
3382 11:08:45.260339 [Byte1]: 33
3383 11:08:45.264323
3384 11:08:45.264884 Set Vref, RX VrefLevel [Byte0]: 34
3385 11:08:45.267771 [Byte1]: 34
3386 11:08:45.271755
3387 11:08:45.272220 Set Vref, RX VrefLevel [Byte0]: 35
3388 11:08:45.275322 [Byte1]: 35
3389 11:08:45.280010
3390 11:08:45.280472 Set Vref, RX VrefLevel [Byte0]: 36
3391 11:08:45.282888 [Byte1]: 36
3392 11:08:45.287659
3393 11:08:45.288464 Set Vref, RX VrefLevel [Byte0]: 37
3394 11:08:45.291032 [Byte1]: 37
3395 11:08:45.295653
3396 11:08:45.296109 Set Vref, RX VrefLevel [Byte0]: 38
3397 11:08:45.298302 [Byte1]: 38
3398 11:08:45.303499
3399 11:08:45.303617 Set Vref, RX VrefLevel [Byte0]: 39
3400 11:08:45.307185 [Byte1]: 39
3401 11:08:45.311126
3402 11:08:45.311221 Set Vref, RX VrefLevel [Byte0]: 40
3403 11:08:45.314342 [Byte1]: 40
3404 11:08:45.319230
3405 11:08:45.319332 Set Vref, RX VrefLevel [Byte0]: 41
3406 11:08:45.322456 [Byte1]: 41
3407 11:08:45.326743
3408 11:08:45.326937 Set Vref, RX VrefLevel [Byte0]: 42
3409 11:08:45.330330 [Byte1]: 42
3410 11:08:45.334697
3411 11:08:45.334843 Set Vref, RX VrefLevel [Byte0]: 43
3412 11:08:45.339114 [Byte1]: 43
3413 11:08:45.343209
3414 11:08:45.343620 Set Vref, RX VrefLevel [Byte0]: 44
3415 11:08:45.346575 [Byte1]: 44
3416 11:08:45.350873
3417 11:08:45.351282 Set Vref, RX VrefLevel [Byte0]: 45
3418 11:08:45.354426 [Byte1]: 45
3419 11:08:45.359141
3420 11:08:45.359553 Set Vref, RX VrefLevel [Byte0]: 46
3421 11:08:45.365366 [Byte1]: 46
3422 11:08:45.365787
3423 11:08:45.368952 Set Vref, RX VrefLevel [Byte0]: 47
3424 11:08:45.371704 [Byte1]: 47
3425 11:08:45.372130
3426 11:08:45.375968 Set Vref, RX VrefLevel [Byte0]: 48
3427 11:08:45.378389 [Byte1]: 48
3428 11:08:45.382531
3429 11:08:45.383060 Set Vref, RX VrefLevel [Byte0]: 49
3430 11:08:45.385927 [Byte1]: 49
3431 11:08:45.390455
3432 11:08:45.390962 Set Vref, RX VrefLevel [Byte0]: 50
3433 11:08:45.393678 [Byte1]: 50
3434 11:08:45.398846
3435 11:08:45.399361 Set Vref, RX VrefLevel [Byte0]: 51
3436 11:08:45.401755 [Byte1]: 51
3437 11:08:45.406749
3438 11:08:45.407315 Set Vref, RX VrefLevel [Byte0]: 52
3439 11:08:45.409781 [Byte1]: 52
3440 11:08:45.414628
3441 11:08:45.415048 Set Vref, RX VrefLevel [Byte0]: 53
3442 11:08:45.418082 [Byte1]: 53
3443 11:08:45.422252
3444 11:08:45.422662 Set Vref, RX VrefLevel [Byte0]: 54
3445 11:08:45.425647 [Byte1]: 54
3446 11:08:45.430039
3447 11:08:45.430455 Set Vref, RX VrefLevel [Byte0]: 55
3448 11:08:45.434138 [Byte1]: 55
3449 11:08:45.438456
3450 11:08:45.438971 Set Vref, RX VrefLevel [Byte0]: 56
3451 11:08:45.441206 [Byte1]: 56
3452 11:08:45.446520
3453 11:08:45.447041 Set Vref, RX VrefLevel [Byte0]: 57
3454 11:08:45.450281 [Byte1]: 57
3455 11:08:45.454058
3456 11:08:45.454551 Set Vref, RX VrefLevel [Byte0]: 58
3457 11:08:45.457162 [Byte1]: 58
3458 11:08:45.461766
3459 11:08:45.462209 Set Vref, RX VrefLevel [Byte0]: 59
3460 11:08:45.465492 [Byte1]: 59
3461 11:08:45.469939
3462 11:08:45.470409 Set Vref, RX VrefLevel [Byte0]: 60
3463 11:08:45.472838 [Byte1]: 60
3464 11:08:45.478185
3465 11:08:45.478714 Set Vref, RX VrefLevel [Byte0]: 61
3466 11:08:45.480604 [Byte1]: 61
3467 11:08:45.485559
3468 11:08:45.486110 Set Vref, RX VrefLevel [Byte0]: 62
3469 11:08:45.489361 [Byte1]: 62
3470 11:08:45.495104
3471 11:08:45.496770 Set Vref, RX VrefLevel [Byte0]: 63
3472 11:08:45.497243 [Byte1]: 63
3473 11:08:45.502174
3474 11:08:45.502751 Set Vref, RX VrefLevel [Byte0]: 64
3475 11:08:45.505057 [Byte1]: 64
3476 11:08:45.509492
3477 11:08:45.510070 Set Vref, RX VrefLevel [Byte0]: 65
3478 11:08:45.513046 [Byte1]: 65
3479 11:08:45.517706
3480 11:08:45.518278 Set Vref, RX VrefLevel [Byte0]: 66
3481 11:08:45.520860 [Byte1]: 66
3482 11:08:45.525241
3483 11:08:45.525706 Final RX Vref Byte 0 = 53 to rank0
3484 11:08:45.528281 Final RX Vref Byte 1 = 59 to rank0
3485 11:08:45.531750 Final RX Vref Byte 0 = 53 to rank1
3486 11:08:45.535251 Final RX Vref Byte 1 = 59 to rank1==
3487 11:08:45.539282 Dram Type= 6, Freq= 0, CH_1, rank 0
3488 11:08:45.544934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 11:08:45.545519 ==
3490 11:08:45.545899 DQS Delay:
3491 11:08:45.548523 DQS0 = 0, DQS1 = 0
3492 11:08:45.548994 DQM Delay:
3493 11:08:45.549369 DQM0 = 116, DQM1 = 112
3494 11:08:45.551522 DQ Delay:
3495 11:08:45.555555 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =112
3496 11:08:45.558654 DQ4 =112, DQ5 =128, DQ6 =124, DQ7 =112
3497 11:08:45.561641 DQ8 =100, DQ9 =100, DQ10 =116, DQ11 =102
3498 11:08:45.565133 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =120
3499 11:08:45.565706
3500 11:08:45.566078
3501 11:08:45.575167 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdf0, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 411 ps
3502 11:08:45.575807 CH1 RK0: MR19=303, MR18=FDF0
3503 11:08:45.581360 CH1_RK0: MR19=0x303, MR18=0xFDF0, DQSOSC=411, MR23=63, INC=38, DEC=25
3504 11:08:45.581917
3505 11:08:45.584511 ----->DramcWriteLeveling(PI) begin...
3506 11:08:45.584992 ==
3507 11:08:45.588113 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 11:08:45.595013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 11:08:45.595622 ==
3510 11:08:45.597821 Write leveling (Byte 0): 24 => 24
3511 11:08:45.601999 Write leveling (Byte 1): 29 => 29
3512 11:08:45.602576 DramcWriteLeveling(PI) end<-----
3513 11:08:45.604591
3514 11:08:45.605065 ==
3515 11:08:45.608333 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 11:08:45.610919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 11:08:45.611390 ==
3518 11:08:45.614767 [Gating] SW mode calibration
3519 11:08:45.621086 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3520 11:08:45.627456 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3521 11:08:45.630838 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3522 11:08:45.634135 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 11:08:45.637978 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 11:08:45.643786 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3525 11:08:45.647421 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3526 11:08:45.654407 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3527 11:08:45.657891 0 15 24 | B1->B0 | 3232 3434 | 0 1 | (0 1) (1 0)
3528 11:08:45.660644 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (1 0) (0 1)
3529 11:08:45.667035 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 11:08:45.670628 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 11:08:45.673557 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 11:08:45.679753 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 11:08:45.683830 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3534 11:08:45.687044 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3535 11:08:45.692862 1 0 24 | B1->B0 | 3838 2828 | 1 0 | (0 0) (0 0)
3536 11:08:45.696589 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 11:08:45.699873 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 11:08:45.705948 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 11:08:45.709645 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 11:08:45.713266 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 11:08:45.719275 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 11:08:45.722609 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 11:08:45.725977 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3544 11:08:45.732462 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3545 11:08:45.735787 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 11:08:45.739458 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 11:08:45.745948 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 11:08:45.749442 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 11:08:45.752351 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 11:08:45.758962 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 11:08:45.762425 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 11:08:45.765619 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 11:08:45.772018 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 11:08:45.775252 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 11:08:45.778487 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 11:08:45.785187 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 11:08:45.788795 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 11:08:45.791661 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 11:08:45.798064 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3560 11:08:45.802226 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3561 11:08:45.804575 Total UI for P1: 0, mck2ui 16
3562 11:08:45.808038 best dqsien dly found for B1: ( 1, 3, 24)
3563 11:08:45.811336 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3564 11:08:45.815109 Total UI for P1: 0, mck2ui 16
3565 11:08:45.818116 best dqsien dly found for B0: ( 1, 3, 26)
3566 11:08:45.821246 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3567 11:08:45.824452 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3568 11:08:45.825061
3569 11:08:45.831470 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3570 11:08:45.834664 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3571 11:08:45.837568 [Gating] SW calibration Done
3572 11:08:45.838130 ==
3573 11:08:45.841028 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 11:08:45.844507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 11:08:45.844976 ==
3576 11:08:45.845345 RX Vref Scan: 0
3577 11:08:45.847720
3578 11:08:45.848184 RX Vref 0 -> 0, step: 1
3579 11:08:45.848669
3580 11:08:45.851295 RX Delay -40 -> 252, step: 8
3581 11:08:45.854438 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3582 11:08:45.857865 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3583 11:08:45.865062 iDelay=208, Bit 2, Center 107 (40 ~ 175) 136
3584 11:08:45.867347 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3585 11:08:45.870687 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3586 11:08:45.873865 iDelay=208, Bit 5, Center 123 (48 ~ 199) 152
3587 11:08:45.876998 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3588 11:08:45.883660 iDelay=208, Bit 7, Center 119 (48 ~ 191) 144
3589 11:08:45.887086 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3590 11:08:45.891043 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3591 11:08:45.893543 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3592 11:08:45.900335 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3593 11:08:45.903444 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3594 11:08:45.906677 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3595 11:08:45.910191 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3596 11:08:45.913613 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3597 11:08:45.916238 ==
3598 11:08:45.920376 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 11:08:45.922855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 11:08:45.923354 ==
3601 11:08:45.923961 DQS Delay:
3602 11:08:45.926321 DQS0 = 0, DQS1 = 0
3603 11:08:45.926858 DQM Delay:
3604 11:08:45.929600 DQM0 = 117, DQM1 = 110
3605 11:08:45.930128 DQ Delay:
3606 11:08:45.933026 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3607 11:08:45.936801 DQ4 =115, DQ5 =123, DQ6 =131, DQ7 =119
3608 11:08:45.939758 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3609 11:08:45.943278 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3610 11:08:45.943882
3611 11:08:45.944257
3612 11:08:45.944598 ==
3613 11:08:45.946003 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 11:08:45.953115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 11:08:45.953685 ==
3616 11:08:45.954055
3617 11:08:45.954391
3618 11:08:45.956045 TX Vref Scan disable
3619 11:08:45.956511 == TX Byte 0 ==
3620 11:08:45.959234 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3621 11:08:45.966245 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3622 11:08:45.966776 == TX Byte 1 ==
3623 11:08:45.969331 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3624 11:08:45.975388 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3625 11:08:45.975835 ==
3626 11:08:45.979123 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 11:08:45.982687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 11:08:45.983214 ==
3629 11:08:45.995176 TX Vref=22, minBit 9, minWin=25, winSum=424
3630 11:08:45.998159 TX Vref=24, minBit 8, minWin=25, winSum=429
3631 11:08:46.001255 TX Vref=26, minBit 8, minWin=26, winSum=434
3632 11:08:46.004664 TX Vref=28, minBit 8, minWin=26, winSum=437
3633 11:08:46.007923 TX Vref=30, minBit 8, minWin=26, winSum=435
3634 11:08:46.014792 TX Vref=32, minBit 8, minWin=26, winSum=434
3635 11:08:46.017656 [TxChooseVref] Worse bit 8, Min win 26, Win sum 437, Final Vref 28
3636 11:08:46.018178
3637 11:08:46.020948 Final TX Range 1 Vref 28
3638 11:08:46.021364
3639 11:08:46.021749 ==
3640 11:08:46.023749 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 11:08:46.031172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 11:08:46.031745 ==
3643 11:08:46.032085
3644 11:08:46.032392
3645 11:08:46.032690 TX Vref Scan disable
3646 11:08:46.034641 == TX Byte 0 ==
3647 11:08:46.037337 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3648 11:08:46.043940 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3649 11:08:46.044446 == TX Byte 1 ==
3650 11:08:46.047320 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3651 11:08:46.054001 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3652 11:08:46.054528
3653 11:08:46.054865 [DATLAT]
3654 11:08:46.055173 Freq=1200, CH1 RK1
3655 11:08:46.056944
3656 11:08:46.057361 DATLAT Default: 0xd
3657 11:08:46.060124 0, 0xFFFF, sum = 0
3658 11:08:46.060549 1, 0xFFFF, sum = 0
3659 11:08:46.064516 2, 0xFFFF, sum = 0
3660 11:08:46.065041 3, 0xFFFF, sum = 0
3661 11:08:46.067656 4, 0xFFFF, sum = 0
3662 11:08:46.068280 5, 0xFFFF, sum = 0
3663 11:08:46.070167 6, 0xFFFF, sum = 0
3664 11:08:46.070592 7, 0xFFFF, sum = 0
3665 11:08:46.073888 8, 0xFFFF, sum = 0
3666 11:08:46.074435 9, 0xFFFF, sum = 0
3667 11:08:46.076646 10, 0xFFFF, sum = 0
3668 11:08:46.077066 11, 0xFFFF, sum = 0
3669 11:08:46.080635 12, 0x0, sum = 1
3670 11:08:46.081164 13, 0x0, sum = 2
3671 11:08:46.083539 14, 0x0, sum = 3
3672 11:08:46.084117 15, 0x0, sum = 4
3673 11:08:46.087363 best_step = 13
3674 11:08:46.087926
3675 11:08:46.088265 ==
3676 11:08:46.090406 Dram Type= 6, Freq= 0, CH_1, rank 1
3677 11:08:46.093589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3678 11:08:46.094011 ==
3679 11:08:46.096811 RX Vref Scan: 0
3680 11:08:46.097329
3681 11:08:46.097665 RX Vref 0 -> 0, step: 1
3682 11:08:46.097978
3683 11:08:46.100205 RX Delay -21 -> 252, step: 4
3684 11:08:46.107263 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3685 11:08:46.110258 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3686 11:08:46.112943 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3687 11:08:46.116372 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3688 11:08:46.122794 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3689 11:08:46.126290 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3690 11:08:46.129227 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3691 11:08:46.132808 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3692 11:08:46.135882 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3693 11:08:46.142687 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3694 11:08:46.146882 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3695 11:08:46.149821 iDelay=199, Bit 11, Center 104 (39 ~ 170) 132
3696 11:08:46.152627 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3697 11:08:46.156179 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3698 11:08:46.162827 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3699 11:08:46.166314 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3700 11:08:46.166836 ==
3701 11:08:46.169166 Dram Type= 6, Freq= 0, CH_1, rank 1
3702 11:08:46.172778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3703 11:08:46.173199 ==
3704 11:08:46.175611 DQS Delay:
3705 11:08:46.176071 DQS0 = 0, DQS1 = 0
3706 11:08:46.176500 DQM Delay:
3707 11:08:46.179071 DQM0 = 117, DQM1 = 111
3708 11:08:46.179589 DQ Delay:
3709 11:08:46.182566 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3710 11:08:46.185853 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =116
3711 11:08:46.192022 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =104
3712 11:08:46.195953 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120
3713 11:08:46.196473
3714 11:08:46.196807
3715 11:08:46.202217 [DQSOSCAuto] RK1, (LSB)MR18= 0xeee8, (MSB)MR19= 0x303, tDQSOscB0 = 420 ps tDQSOscB1 = 417 ps
3716 11:08:46.205621 CH1 RK1: MR19=303, MR18=EEE8
3717 11:08:46.212052 CH1_RK1: MR19=0x303, MR18=0xEEE8, DQSOSC=417, MR23=63, INC=37, DEC=25
3718 11:08:46.215642 [RxdqsGatingPostProcess] freq 1200
3719 11:08:46.222062 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3720 11:08:46.222485 best DQS0 dly(2T, 0.5T) = (0, 11)
3721 11:08:46.225472 best DQS1 dly(2T, 0.5T) = (0, 11)
3722 11:08:46.228533 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3723 11:08:46.231934 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3724 11:08:46.234975 best DQS0 dly(2T, 0.5T) = (0, 11)
3725 11:08:46.238068 best DQS1 dly(2T, 0.5T) = (0, 11)
3726 11:08:46.241661 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3727 11:08:46.244975 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3728 11:08:46.248801 Pre-setting of DQS Precalculation
3729 11:08:46.254963 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3730 11:08:46.261663 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3731 11:08:46.268277 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3732 11:08:46.268803
3733 11:08:46.269137
3734 11:08:46.271023 [Calibration Summary] 2400 Mbps
3735 11:08:46.271439 CH 0, Rank 0
3736 11:08:46.274350 SW Impedance : PASS
3737 11:08:46.277604 DUTY Scan : NO K
3738 11:08:46.278018 ZQ Calibration : PASS
3739 11:08:46.281330 Jitter Meter : NO K
3740 11:08:46.284258 CBT Training : PASS
3741 11:08:46.284782 Write leveling : PASS
3742 11:08:46.287656 RX DQS gating : PASS
3743 11:08:46.291308 RX DQ/DQS(RDDQC) : PASS
3744 11:08:46.291864 TX DQ/DQS : PASS
3745 11:08:46.294067 RX DATLAT : PASS
3746 11:08:46.297734 RX DQ/DQS(Engine): PASS
3747 11:08:46.298256 TX OE : NO K
3748 11:08:46.300399 All Pass.
3749 11:08:46.300814
3750 11:08:46.301140 CH 0, Rank 1
3751 11:08:46.304131 SW Impedance : PASS
3752 11:08:46.304657 DUTY Scan : NO K
3753 11:08:46.307592 ZQ Calibration : PASS
3754 11:08:46.310686 Jitter Meter : NO K
3755 11:08:46.311219 CBT Training : PASS
3756 11:08:46.313874 Write leveling : PASS
3757 11:08:46.317054 RX DQS gating : PASS
3758 11:08:46.317470 RX DQ/DQS(RDDQC) : PASS
3759 11:08:46.320885 TX DQ/DQS : PASS
3760 11:08:46.324163 RX DATLAT : PASS
3761 11:08:46.324586 RX DQ/DQS(Engine): PASS
3762 11:08:46.327345 TX OE : NO K
3763 11:08:46.327804 All Pass.
3764 11:08:46.328142
3765 11:08:46.330330 CH 1, Rank 0
3766 11:08:46.330883 SW Impedance : PASS
3767 11:08:46.333364 DUTY Scan : NO K
3768 11:08:46.333784 ZQ Calibration : PASS
3769 11:08:46.336887 Jitter Meter : NO K
3770 11:08:46.340321 CBT Training : PASS
3771 11:08:46.340742 Write leveling : PASS
3772 11:08:46.343489 RX DQS gating : PASS
3773 11:08:46.347033 RX DQ/DQS(RDDQC) : PASS
3774 11:08:46.347605 TX DQ/DQS : PASS
3775 11:08:46.350020 RX DATLAT : PASS
3776 11:08:46.353738 RX DQ/DQS(Engine): PASS
3777 11:08:46.354307 TX OE : NO K
3778 11:08:46.356381 All Pass.
3779 11:08:46.356858
3780 11:08:46.357340 CH 1, Rank 1
3781 11:08:46.359960 SW Impedance : PASS
3782 11:08:46.360421 DUTY Scan : NO K
3783 11:08:46.362941 ZQ Calibration : PASS
3784 11:08:46.366407 Jitter Meter : NO K
3785 11:08:46.366940 CBT Training : PASS
3786 11:08:46.369996 Write leveling : PASS
3787 11:08:46.373321 RX DQS gating : PASS
3788 11:08:46.373755 RX DQ/DQS(RDDQC) : PASS
3789 11:08:46.376487 TX DQ/DQS : PASS
3790 11:08:46.379355 RX DATLAT : PASS
3791 11:08:46.379837 RX DQ/DQS(Engine): PASS
3792 11:08:46.382719 TX OE : NO K
3793 11:08:46.383169 All Pass.
3794 11:08:46.383611
3795 11:08:46.386347 DramC Write-DBI off
3796 11:08:46.389694 PER_BANK_REFRESH: Hybrid Mode
3797 11:08:46.390133 TX_TRACKING: ON
3798 11:08:46.399621 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3799 11:08:46.403247 [FAST_K] Save calibration result to emmc
3800 11:08:46.406163 dramc_set_vcore_voltage set vcore to 650000
3801 11:08:46.409314 Read voltage for 600, 5
3802 11:08:46.409738 Vio18 = 0
3803 11:08:46.410074 Vcore = 650000
3804 11:08:46.412633 Vdram = 0
3805 11:08:46.413054 Vddq = 0
3806 11:08:46.413495 Vmddr = 0
3807 11:08:46.419264 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3808 11:08:46.422521 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3809 11:08:46.426676 MEM_TYPE=3, freq_sel=19
3810 11:08:46.429015 sv_algorithm_assistance_LP4_1600
3811 11:08:46.432384 ============ PULL DRAM RESETB DOWN ============
3812 11:08:46.435701 ========== PULL DRAM RESETB DOWN end =========
3813 11:08:46.442612 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3814 11:08:46.445919 ===================================
3815 11:08:46.449339 LPDDR4 DRAM CONFIGURATION
3816 11:08:46.452376 ===================================
3817 11:08:46.452804 EX_ROW_EN[0] = 0x0
3818 11:08:46.455423 EX_ROW_EN[1] = 0x0
3819 11:08:46.456023 LP4Y_EN = 0x0
3820 11:08:46.459404 WORK_FSP = 0x0
3821 11:08:46.459911 WL = 0x2
3822 11:08:46.462257 RL = 0x2
3823 11:08:46.462673 BL = 0x2
3824 11:08:46.465503 RPST = 0x0
3825 11:08:46.465921 RD_PRE = 0x0
3826 11:08:46.468889 WR_PRE = 0x1
3827 11:08:46.469304 WR_PST = 0x0
3828 11:08:46.472798 DBI_WR = 0x0
3829 11:08:46.475585 DBI_RD = 0x0
3830 11:08:46.476045 OTF = 0x1
3831 11:08:46.478993 ===================================
3832 11:08:46.482534 ===================================
3833 11:08:46.483060 ANA top config
3834 11:08:46.485307 ===================================
3835 11:08:46.488380 DLL_ASYNC_EN = 0
3836 11:08:46.491882 ALL_SLAVE_EN = 1
3837 11:08:46.495629 NEW_RANK_MODE = 1
3838 11:08:46.498842 DLL_IDLE_MODE = 1
3839 11:08:46.499364 LP45_APHY_COMB_EN = 1
3840 11:08:46.501427 TX_ODT_DIS = 1
3841 11:08:46.504627 NEW_8X_MODE = 1
3842 11:08:46.508245 ===================================
3843 11:08:46.511752 ===================================
3844 11:08:46.515299 data_rate = 1200
3845 11:08:46.518630 CKR = 1
3846 11:08:46.521210 DQ_P2S_RATIO = 8
3847 11:08:46.525067 ===================================
3848 11:08:46.525485 CA_P2S_RATIO = 8
3849 11:08:46.528161 DQ_CA_OPEN = 0
3850 11:08:46.531309 DQ_SEMI_OPEN = 0
3851 11:08:46.534747 CA_SEMI_OPEN = 0
3852 11:08:46.537974 CA_FULL_RATE = 0
3853 11:08:46.542465 DQ_CKDIV4_EN = 1
3854 11:08:46.542988 CA_CKDIV4_EN = 1
3855 11:08:46.544933 CA_PREDIV_EN = 0
3856 11:08:46.548175 PH8_DLY = 0
3857 11:08:46.550808 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3858 11:08:46.554163 DQ_AAMCK_DIV = 4
3859 11:08:46.557565 CA_AAMCK_DIV = 4
3860 11:08:46.557983 CA_ADMCK_DIV = 4
3861 11:08:46.560830 DQ_TRACK_CA_EN = 0
3862 11:08:46.564216 CA_PICK = 600
3863 11:08:46.567621 CA_MCKIO = 600
3864 11:08:46.570953 MCKIO_SEMI = 0
3865 11:08:46.573813 PLL_FREQ = 2288
3866 11:08:46.578133 DQ_UI_PI_RATIO = 32
3867 11:08:46.580897 CA_UI_PI_RATIO = 0
3868 11:08:46.581319 ===================================
3869 11:08:46.583972 ===================================
3870 11:08:46.587502 memory_type:LPDDR4
3871 11:08:46.590426 GP_NUM : 10
3872 11:08:46.590844 SRAM_EN : 1
3873 11:08:46.593845 MD32_EN : 0
3874 11:08:46.597151 ===================================
3875 11:08:46.600766 [ANA_INIT] >>>>>>>>>>>>>>
3876 11:08:46.604241 <<<<<< [CONFIGURE PHASE]: ANA_TX
3877 11:08:46.607214 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3878 11:08:46.610455 ===================================
3879 11:08:46.613480 data_rate = 1200,PCW = 0X5800
3880 11:08:46.617383 ===================================
3881 11:08:46.620145 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3882 11:08:46.623377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3883 11:08:46.630123 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3884 11:08:46.633188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3885 11:08:46.636595 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3886 11:08:46.640001 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3887 11:08:46.643252 [ANA_INIT] flow start
3888 11:08:46.646485 [ANA_INIT] PLL >>>>>>>>
3889 11:08:46.646950 [ANA_INIT] PLL <<<<<<<<
3890 11:08:46.650814 [ANA_INIT] MIDPI >>>>>>>>
3891 11:08:46.653263 [ANA_INIT] MIDPI <<<<<<<<
3892 11:08:46.656828 [ANA_INIT] DLL >>>>>>>>
3893 11:08:46.657375 [ANA_INIT] flow end
3894 11:08:46.659824 ============ LP4 DIFF to SE enter ============
3895 11:08:46.666059 ============ LP4 DIFF to SE exit ============
3896 11:08:46.666588 [ANA_INIT] <<<<<<<<<<<<<
3897 11:08:46.669638 [Flow] Enable top DCM control >>>>>
3898 11:08:46.672626 [Flow] Enable top DCM control <<<<<
3899 11:08:46.676499 Enable DLL master slave shuffle
3900 11:08:46.682879 ==============================================================
3901 11:08:46.683300 Gating Mode config
3902 11:08:46.689386 ==============================================================
3903 11:08:46.692416 Config description:
3904 11:08:46.702877 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3905 11:08:46.709282 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3906 11:08:46.712341 SELPH_MODE 0: By rank 1: By Phase
3907 11:08:46.718923 ==============================================================
3908 11:08:46.722400 GAT_TRACK_EN = 1
3909 11:08:46.725708 RX_GATING_MODE = 2
3910 11:08:46.729011 RX_GATING_TRACK_MODE = 2
3911 11:08:46.729492 SELPH_MODE = 1
3912 11:08:46.732535 PICG_EARLY_EN = 1
3913 11:08:46.735902 VALID_LAT_VALUE = 1
3914 11:08:46.742335 ==============================================================
3915 11:08:46.745547 Enter into Gating configuration >>>>
3916 11:08:46.748501 Exit from Gating configuration <<<<
3917 11:08:46.751786 Enter into DVFS_PRE_config >>>>>
3918 11:08:46.762070 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3919 11:08:46.765241 Exit from DVFS_PRE_config <<<<<
3920 11:08:46.768722 Enter into PICG configuration >>>>
3921 11:08:46.771890 Exit from PICG configuration <<<<
3922 11:08:46.775372 [RX_INPUT] configuration >>>>>
3923 11:08:46.778794 [RX_INPUT] configuration <<<<<
3924 11:08:46.781366 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3925 11:08:46.787915 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3926 11:08:46.794482 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3927 11:08:46.801288 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3928 11:08:46.808053 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3929 11:08:46.814582 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3930 11:08:46.817391 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3931 11:08:46.820903 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3932 11:08:46.824229 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3933 11:08:46.830465 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3934 11:08:46.833975 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3935 11:08:46.837202 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3936 11:08:46.841032 ===================================
3937 11:08:46.844634 LPDDR4 DRAM CONFIGURATION
3938 11:08:46.847809 ===================================
3939 11:08:46.848302 EX_ROW_EN[0] = 0x0
3940 11:08:46.850394 EX_ROW_EN[1] = 0x0
3941 11:08:46.854103 LP4Y_EN = 0x0
3942 11:08:46.854613 WORK_FSP = 0x0
3943 11:08:46.857699 WL = 0x2
3944 11:08:46.858275 RL = 0x2
3945 11:08:46.860902 BL = 0x2
3946 11:08:46.861474 RPST = 0x0
3947 11:08:46.863554 RD_PRE = 0x0
3948 11:08:46.864156 WR_PRE = 0x1
3949 11:08:46.867390 WR_PST = 0x0
3950 11:08:46.868017 DBI_WR = 0x0
3951 11:08:46.870635 DBI_RD = 0x0
3952 11:08:46.871218 OTF = 0x1
3953 11:08:46.873757 ===================================
3954 11:08:46.880296 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3955 11:08:46.884137 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3956 11:08:46.887126 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3957 11:08:46.890070 ===================================
3958 11:08:46.893667 LPDDR4 DRAM CONFIGURATION
3959 11:08:46.896614 ===================================
3960 11:08:46.899851 EX_ROW_EN[0] = 0x10
3961 11:08:46.900339 EX_ROW_EN[1] = 0x0
3962 11:08:46.903219 LP4Y_EN = 0x0
3963 11:08:46.903732 WORK_FSP = 0x0
3964 11:08:46.906996 WL = 0x2
3965 11:08:46.907462 RL = 0x2
3966 11:08:46.909942 BL = 0x2
3967 11:08:46.910534 RPST = 0x0
3968 11:08:46.912871 RD_PRE = 0x0
3969 11:08:46.913410 WR_PRE = 0x1
3970 11:08:46.916589 WR_PST = 0x0
3971 11:08:46.917115 DBI_WR = 0x0
3972 11:08:46.919793 DBI_RD = 0x0
3973 11:08:46.920260 OTF = 0x1
3974 11:08:46.923051 ===================================
3975 11:08:46.929650 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3976 11:08:46.934417 nWR fixed to 30
3977 11:08:46.938035 [ModeRegInit_LP4] CH0 RK0
3978 11:08:46.938530 [ModeRegInit_LP4] CH0 RK1
3979 11:08:46.940926 [ModeRegInit_LP4] CH1 RK0
3980 11:08:46.944275 [ModeRegInit_LP4] CH1 RK1
3981 11:08:46.944729 match AC timing 17
3982 11:08:46.951402 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3983 11:08:46.953965 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3984 11:08:46.957831 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3985 11:08:46.964284 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3986 11:08:46.967089 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3987 11:08:46.967648 ==
3988 11:08:46.970496 Dram Type= 6, Freq= 0, CH_0, rank 0
3989 11:08:46.973729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3990 11:08:46.974174 ==
3991 11:08:46.980297 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3992 11:08:46.987564 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3993 11:08:46.991204 [CA 0] Center 36 (6~66) winsize 61
3994 11:08:46.993621 [CA 1] Center 36 (6~66) winsize 61
3995 11:08:46.996619 [CA 2] Center 34 (3~65) winsize 63
3996 11:08:46.999963 [CA 3] Center 33 (3~64) winsize 62
3997 11:08:47.003003 [CA 4] Center 33 (3~64) winsize 62
3998 11:08:47.006875 [CA 5] Center 33 (3~64) winsize 62
3999 11:08:47.007292
4000 11:08:47.010212 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4001 11:08:47.010733
4002 11:08:47.013265 [CATrainingPosCal] consider 1 rank data
4003 11:08:47.016028 u2DelayCellTimex100 = 270/100 ps
4004 11:08:47.019392 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4005 11:08:47.022913 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4006 11:08:47.026233 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4007 11:08:47.032898 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4008 11:08:47.035958 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4009 11:08:47.039417 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4010 11:08:47.039973
4011 11:08:47.042895 CA PerBit enable=1, Macro0, CA PI delay=33
4012 11:08:47.043434
4013 11:08:47.046232 [CBTSetCACLKResult] CA Dly = 33
4014 11:08:47.046882 CS Dly: 5 (0~36)
4015 11:08:47.049380 ==
4016 11:08:47.049833 Dram Type= 6, Freq= 0, CH_0, rank 1
4017 11:08:47.056094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 11:08:47.056516 ==
4019 11:08:47.059728 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4020 11:08:47.065713 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4021 11:08:47.069557 [CA 0] Center 35 (5~66) winsize 62
4022 11:08:47.072658 [CA 1] Center 36 (6~66) winsize 61
4023 11:08:47.076444 [CA 2] Center 34 (4~64) winsize 61
4024 11:08:47.079450 [CA 3] Center 33 (3~64) winsize 62
4025 11:08:47.082926 [CA 4] Center 33 (2~64) winsize 63
4026 11:08:47.086357 [CA 5] Center 33 (2~64) winsize 63
4027 11:08:47.086885
4028 11:08:47.089582 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4029 11:08:47.090112
4030 11:08:47.092893 [CATrainingPosCal] consider 2 rank data
4031 11:08:47.096126 u2DelayCellTimex100 = 270/100 ps
4032 11:08:47.099409 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4033 11:08:47.105489 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4034 11:08:47.109479 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4035 11:08:47.112266 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4036 11:08:47.115590 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4037 11:08:47.119177 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4038 11:08:47.119613
4039 11:08:47.122535 CA PerBit enable=1, Macro0, CA PI delay=33
4040 11:08:47.122955
4041 11:08:47.125350 [CBTSetCACLKResult] CA Dly = 33
4042 11:08:47.128987 CS Dly: 5 (0~37)
4043 11:08:47.129555
4044 11:08:47.131908 ----->DramcWriteLeveling(PI) begin...
4045 11:08:47.132341 ==
4046 11:08:47.135346 Dram Type= 6, Freq= 0, CH_0, rank 0
4047 11:08:47.138685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 11:08:47.139103 ==
4049 11:08:47.142182 Write leveling (Byte 0): 34 => 34
4050 11:08:47.145081 Write leveling (Byte 1): 30 => 30
4051 11:08:47.148884 DramcWriteLeveling(PI) end<-----
4052 11:08:47.149306
4053 11:08:47.149829 ==
4054 11:08:47.152062 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 11:08:47.155349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 11:08:47.156011 ==
4057 11:08:47.158303 [Gating] SW mode calibration
4058 11:08:47.165584 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4059 11:08:47.171790 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4060 11:08:47.174636 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4061 11:08:47.181519 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4062 11:08:47.184637 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4063 11:08:47.187845 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4064 11:08:47.194784 0 9 16 | B1->B0 | 3030 2525 | 0 0 | (1 1) (1 1)
4065 11:08:47.197576 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 11:08:47.201187 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 11:08:47.207508 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 11:08:47.210424 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 11:08:47.214043 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4070 11:08:47.220267 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 11:08:47.223793 0 10 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4072 11:08:47.227433 0 10 16 | B1->B0 | 3232 4141 | 0 0 | (0 0) (0 0)
4073 11:08:47.233850 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 11:08:47.237114 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 11:08:47.240056 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 11:08:47.246965 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 11:08:47.250062 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 11:08:47.253175 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 11:08:47.259729 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4080 11:08:47.263582 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4081 11:08:47.266800 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 11:08:47.273172 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 11:08:47.277040 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 11:08:47.280062 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 11:08:47.286281 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 11:08:47.289946 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 11:08:47.293286 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 11:08:47.299465 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 11:08:47.303346 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 11:08:47.305947 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 11:08:47.312329 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 11:08:47.316131 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 11:08:47.319290 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 11:08:47.326155 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 11:08:47.329266 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4096 11:08:47.332643 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4097 11:08:47.336149 Total UI for P1: 0, mck2ui 16
4098 11:08:47.339227 best dqsien dly found for B0: ( 0, 13, 12)
4099 11:08:47.342557 Total UI for P1: 0, mck2ui 16
4100 11:08:47.345465 best dqsien dly found for B1: ( 0, 13, 12)
4101 11:08:47.349235 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4102 11:08:47.352276 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4103 11:08:47.355630
4104 11:08:47.358781 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4105 11:08:47.361985 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4106 11:08:47.365372 [Gating] SW calibration Done
4107 11:08:47.365789 ==
4108 11:08:47.369009 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 11:08:47.372222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 11:08:47.372687 ==
4111 11:08:47.373128 RX Vref Scan: 0
4112 11:08:47.374915
4113 11:08:47.375351 RX Vref 0 -> 0, step: 1
4114 11:08:47.375741
4115 11:08:47.378666 RX Delay -230 -> 252, step: 16
4116 11:08:47.382119 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4117 11:08:47.388694 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4118 11:08:47.391563 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4119 11:08:47.394908 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4120 11:08:47.398346 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4121 11:08:47.404921 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4122 11:08:47.407879 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4123 11:08:47.411491 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4124 11:08:47.414799 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4125 11:08:47.417828 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4126 11:08:47.424725 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4127 11:08:47.427733 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4128 11:08:47.430851 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4129 11:08:47.437738 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4130 11:08:47.441202 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4131 11:08:47.444031 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4132 11:08:47.444457 ==
4133 11:08:47.447170 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 11:08:47.450584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 11:08:47.451006 ==
4136 11:08:47.454022 DQS Delay:
4137 11:08:47.454439 DQS0 = 0, DQS1 = 0
4138 11:08:47.457440 DQM Delay:
4139 11:08:47.457994 DQM0 = 43, DQM1 = 32
4140 11:08:47.460553 DQ Delay:
4141 11:08:47.460971 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4142 11:08:47.464104 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4143 11:08:47.467654 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4144 11:08:47.470604 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4145 11:08:47.471019
4146 11:08:47.473800
4147 11:08:47.474222 ==
4148 11:08:47.476829 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 11:08:47.480217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 11:08:47.480638 ==
4151 11:08:47.481243
4152 11:08:47.481582
4153 11:08:47.484150 TX Vref Scan disable
4154 11:08:47.484568 == TX Byte 0 ==
4155 11:08:47.490537 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4156 11:08:47.493690 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4157 11:08:47.494389 == TX Byte 1 ==
4158 11:08:47.499897 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4159 11:08:47.503186 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4160 11:08:47.503921 ==
4161 11:08:47.506928 Dram Type= 6, Freq= 0, CH_0, rank 0
4162 11:08:47.510007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4163 11:08:47.510444 ==
4164 11:08:47.510785
4165 11:08:47.511155
4166 11:08:47.513205 TX Vref Scan disable
4167 11:08:47.516841 == TX Byte 0 ==
4168 11:08:47.520147 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4169 11:08:47.526593 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4170 11:08:47.527014 == TX Byte 1 ==
4171 11:08:47.530240 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4172 11:08:47.536348 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4173 11:08:47.536771
4174 11:08:47.537241 [DATLAT]
4175 11:08:47.537588 Freq=600, CH0 RK0
4176 11:08:47.537888
4177 11:08:47.539749 DATLAT Default: 0x9
4178 11:08:47.540116 0, 0xFFFF, sum = 0
4179 11:08:47.543407 1, 0xFFFF, sum = 0
4180 11:08:47.546375 2, 0xFFFF, sum = 0
4181 11:08:47.546800 3, 0xFFFF, sum = 0
4182 11:08:47.549825 4, 0xFFFF, sum = 0
4183 11:08:47.550259 5, 0xFFFF, sum = 0
4184 11:08:47.553617 6, 0xFFFF, sum = 0
4185 11:08:47.554201 7, 0xFFFF, sum = 0
4186 11:08:47.556484 8, 0x0, sum = 1
4187 11:08:47.556908 9, 0x0, sum = 2
4188 11:08:47.559861 10, 0x0, sum = 3
4189 11:08:47.560287 11, 0x0, sum = 4
4190 11:08:47.560627 best_step = 9
4191 11:08:47.560933
4192 11:08:47.562962 ==
4193 11:08:47.563373 Dram Type= 6, Freq= 0, CH_0, rank 0
4194 11:08:47.569674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 11:08:47.570258 ==
4196 11:08:47.570658 RX Vref Scan: 1
4197 11:08:47.570990
4198 11:08:47.572691 RX Vref 0 -> 0, step: 1
4199 11:08:47.573206
4200 11:08:47.576139 RX Delay -195 -> 252, step: 8
4201 11:08:47.576567
4202 11:08:47.579248 Set Vref, RX VrefLevel [Byte0]: 60
4203 11:08:47.583112 [Byte1]: 48
4204 11:08:47.583543
4205 11:08:47.586324 Final RX Vref Byte 0 = 60 to rank0
4206 11:08:47.589181 Final RX Vref Byte 1 = 48 to rank0
4207 11:08:47.592367 Final RX Vref Byte 0 = 60 to rank1
4208 11:08:47.595532 Final RX Vref Byte 1 = 48 to rank1==
4209 11:08:47.599005 Dram Type= 6, Freq= 0, CH_0, rank 0
4210 11:08:47.602505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 11:08:47.605679 ==
4212 11:08:47.606208 DQS Delay:
4213 11:08:47.606544 DQS0 = 0, DQS1 = 0
4214 11:08:47.609016 DQM Delay:
4215 11:08:47.609432 DQM0 = 44, DQM1 = 33
4216 11:08:47.612381 DQ Delay:
4217 11:08:47.612797 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4218 11:08:47.615893 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4219 11:08:47.619074 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4220 11:08:47.622650 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4221 11:08:47.625508
4222 11:08:47.625941
4223 11:08:47.632684 [DQSOSCAuto] RK0, (LSB)MR18= 0x6139, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
4224 11:08:47.635592 CH0 RK0: MR19=808, MR18=6139
4225 11:08:47.641836 CH0_RK0: MR19=0x808, MR18=0x6139, DQSOSC=391, MR23=63, INC=171, DEC=114
4226 11:08:47.642264
4227 11:08:47.645695 ----->DramcWriteLeveling(PI) begin...
4228 11:08:47.646225 ==
4229 11:08:47.648793 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 11:08:47.652586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 11:08:47.653014 ==
4232 11:08:47.655449 Write leveling (Byte 0): 32 => 32
4233 11:08:47.658253 Write leveling (Byte 1): 32 => 32
4234 11:08:47.662657 DramcWriteLeveling(PI) end<-----
4235 11:08:47.663182
4236 11:08:47.663528 ==
4237 11:08:47.665684 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 11:08:47.668592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 11:08:47.669259 ==
4240 11:08:47.671884 [Gating] SW mode calibration
4241 11:08:47.678356 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4242 11:08:47.684624 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4243 11:08:47.688391 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4244 11:08:47.695016 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4245 11:08:47.698345 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4246 11:08:47.701363 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
4247 11:08:47.708106 0 9 16 | B1->B0 | 2f2f 2c2c | 0 1 | (1 1) (0 0)
4248 11:08:47.711477 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 11:08:47.714422 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 11:08:47.721057 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 11:08:47.724703 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 11:08:47.728044 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 11:08:47.734496 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4254 11:08:47.737402 0 10 12 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
4255 11:08:47.740881 0 10 16 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
4256 11:08:47.747844 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 11:08:47.751034 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 11:08:47.754533 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 11:08:47.761087 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 11:08:47.764675 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 11:08:47.767106 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 11:08:47.773599 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4263 11:08:47.777461 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 11:08:47.780414 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 11:08:47.787577 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 11:08:47.790406 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 11:08:47.793540 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 11:08:47.800192 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 11:08:47.803296 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 11:08:47.806657 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 11:08:47.813487 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 11:08:47.817229 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 11:08:47.820649 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 11:08:47.826750 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 11:08:47.829743 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 11:08:47.833190 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 11:08:47.839753 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 11:08:47.843356 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 11:08:47.846289 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4280 11:08:47.849625 Total UI for P1: 0, mck2ui 16
4281 11:08:47.852661 best dqsien dly found for B0: ( 0, 13, 14)
4282 11:08:47.859429 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4283 11:08:47.860017 Total UI for P1: 0, mck2ui 16
4284 11:08:47.865677 best dqsien dly found for B1: ( 0, 13, 16)
4285 11:08:47.869609 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4286 11:08:47.872704 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4287 11:08:47.873228
4288 11:08:47.876158 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4289 11:08:47.879111 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4290 11:08:47.882475 [Gating] SW calibration Done
4291 11:08:47.883040 ==
4292 11:08:47.885928 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 11:08:47.888844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 11:08:47.889268 ==
4295 11:08:47.892697 RX Vref Scan: 0
4296 11:08:47.893116
4297 11:08:47.893453 RX Vref 0 -> 0, step: 1
4298 11:08:47.895567
4299 11:08:47.896028 RX Delay -230 -> 252, step: 16
4300 11:08:47.902194 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4301 11:08:47.905826 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4302 11:08:47.908778 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4303 11:08:47.912293 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4304 11:08:47.918574 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4305 11:08:47.922149 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4306 11:08:47.925010 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4307 11:08:47.928509 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4308 11:08:47.931923 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4309 11:08:47.938371 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4310 11:08:47.941723 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4311 11:08:47.945101 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4312 11:08:47.948539 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4313 11:08:47.955407 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4314 11:08:47.958567 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4315 11:08:47.961870 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4316 11:08:47.962509 ==
4317 11:08:47.964660 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 11:08:47.971780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 11:08:47.972212 ==
4320 11:08:47.972551 DQS Delay:
4321 11:08:47.972864 DQS0 = 0, DQS1 = 0
4322 11:08:47.974593 DQM Delay:
4323 11:08:47.975049 DQM0 = 43, DQM1 = 36
4324 11:08:47.977920 DQ Delay:
4325 11:08:47.981269 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4326 11:08:47.984513 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4327 11:08:47.988224 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4328 11:08:47.991266 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4329 11:08:47.991735
4330 11:08:47.992082
4331 11:08:47.992395 ==
4332 11:08:47.994358 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 11:08:47.998184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 11:08:47.998661 ==
4335 11:08:47.999149
4336 11:08:47.999601
4337 11:08:48.000918 TX Vref Scan disable
4338 11:08:48.001404 == TX Byte 0 ==
4339 11:08:48.007619 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4340 11:08:48.010986 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4341 11:08:48.013768 == TX Byte 1 ==
4342 11:08:48.017878 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4343 11:08:48.021498 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4344 11:08:48.021886 ==
4345 11:08:48.024057 Dram Type= 6, Freq= 0, CH_0, rank 1
4346 11:08:48.027472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 11:08:48.030930 ==
4348 11:08:48.031229
4349 11:08:48.031466
4350 11:08:48.031718 TX Vref Scan disable
4351 11:08:48.034411 == TX Byte 0 ==
4352 11:08:48.037766 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4353 11:08:48.044183 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4354 11:08:48.044620 == TX Byte 1 ==
4355 11:08:48.047378 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4356 11:08:48.054565 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4357 11:08:48.055087
4358 11:08:48.055422 [DATLAT]
4359 11:08:48.055793 Freq=600, CH0 RK1
4360 11:08:48.056104
4361 11:08:48.057236 DATLAT Default: 0x9
4362 11:08:48.061036 0, 0xFFFF, sum = 0
4363 11:08:48.061456 1, 0xFFFF, sum = 0
4364 11:08:48.064732 2, 0xFFFF, sum = 0
4365 11:08:48.065153 3, 0xFFFF, sum = 0
4366 11:08:48.067463 4, 0xFFFF, sum = 0
4367 11:08:48.068040 5, 0xFFFF, sum = 0
4368 11:08:48.070872 6, 0xFFFF, sum = 0
4369 11:08:48.071393 7, 0xFFFF, sum = 0
4370 11:08:48.074230 8, 0x0, sum = 1
4371 11:08:48.074654 9, 0x0, sum = 2
4372 11:08:48.077415 10, 0x0, sum = 3
4373 11:08:48.077833 11, 0x0, sum = 4
4374 11:08:48.078220 best_step = 9
4375 11:08:48.078533
4376 11:08:48.081066 ==
4377 11:08:48.083704 Dram Type= 6, Freq= 0, CH_0, rank 1
4378 11:08:48.086973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 11:08:48.087422 ==
4380 11:08:48.087988 RX Vref Scan: 0
4381 11:08:48.088465
4382 11:08:48.090627 RX Vref 0 -> 0, step: 1
4383 11:08:48.091049
4384 11:08:48.093728 RX Delay -179 -> 252, step: 8
4385 11:08:48.100485 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4386 11:08:48.103890 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4387 11:08:48.106934 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4388 11:08:48.109636 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4389 11:08:48.116565 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4390 11:08:48.120226 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4391 11:08:48.122921 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4392 11:08:48.126113 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4393 11:08:48.129708 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4394 11:08:48.136112 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4395 11:08:48.139831 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4396 11:08:48.142634 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4397 11:08:48.146260 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4398 11:08:48.152574 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4399 11:08:48.155733 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4400 11:08:48.159187 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4401 11:08:48.159772 ==
4402 11:08:48.162428 Dram Type= 6, Freq= 0, CH_0, rank 1
4403 11:08:48.169062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 11:08:48.169586 ==
4405 11:08:48.169920 DQS Delay:
4406 11:08:48.172465 DQS0 = 0, DQS1 = 0
4407 11:08:48.172985 DQM Delay:
4408 11:08:48.173362 DQM0 = 41, DQM1 = 37
4409 11:08:48.175276 DQ Delay:
4410 11:08:48.178698 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4411 11:08:48.182580 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4412 11:08:48.185585 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4413 11:08:48.188637 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4414 11:08:48.189108
4415 11:08:48.189473
4416 11:08:48.195314 [DQSOSCAuto] RK1, (LSB)MR18= 0x5509, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
4417 11:08:48.198755 CH0 RK1: MR19=808, MR18=5509
4418 11:08:48.204966 CH0_RK1: MR19=0x808, MR18=0x5509, DQSOSC=393, MR23=63, INC=169, DEC=113
4419 11:08:48.208652 [RxdqsGatingPostProcess] freq 600
4420 11:08:48.215205 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4421 11:08:48.215642 Pre-setting of DQS Precalculation
4422 11:08:48.221690 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4423 11:08:48.222222 ==
4424 11:08:48.224804 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 11:08:48.228787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 11:08:48.229206 ==
4427 11:08:48.235313 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4428 11:08:48.241298 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4429 11:08:48.245177 [CA 0] Center 35 (5~66) winsize 62
4430 11:08:48.247793 [CA 1] Center 35 (5~66) winsize 62
4431 11:08:48.251335 [CA 2] Center 34 (4~65) winsize 62
4432 11:08:48.254864 [CA 3] Center 33 (3~64) winsize 62
4433 11:08:48.257905 [CA 4] Center 34 (4~65) winsize 62
4434 11:08:48.261546 [CA 5] Center 33 (3~64) winsize 62
4435 11:08:48.262183
4436 11:08:48.264952 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4437 11:08:48.265520
4438 11:08:48.267506 [CATrainingPosCal] consider 1 rank data
4439 11:08:48.270835 u2DelayCellTimex100 = 270/100 ps
4440 11:08:48.274299 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4441 11:08:48.277187 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4442 11:08:48.280879 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4443 11:08:48.284108 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4444 11:08:48.290486 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4445 11:08:48.294062 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4446 11:08:48.294491
4447 11:08:48.297122 CA PerBit enable=1, Macro0, CA PI delay=33
4448 11:08:48.297545
4449 11:08:48.300763 [CBTSetCACLKResult] CA Dly = 33
4450 11:08:48.301186 CS Dly: 4 (0~35)
4451 11:08:48.301525 ==
4452 11:08:48.303491 Dram Type= 6, Freq= 0, CH_1, rank 1
4453 11:08:48.310315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 11:08:48.310746 ==
4455 11:08:48.313409 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4456 11:08:48.320407 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4457 11:08:48.324397 [CA 0] Center 35 (5~66) winsize 62
4458 11:08:48.327109 [CA 1] Center 36 (6~66) winsize 61
4459 11:08:48.330069 [CA 2] Center 34 (4~65) winsize 62
4460 11:08:48.333026 [CA 3] Center 34 (3~65) winsize 63
4461 11:08:48.336483 [CA 4] Center 34 (4~65) winsize 62
4462 11:08:48.339924 [CA 5] Center 34 (3~65) winsize 63
4463 11:08:48.340472
4464 11:08:48.343278 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4465 11:08:48.343943
4466 11:08:48.346659 [CATrainingPosCal] consider 2 rank data
4467 11:08:48.349348 u2DelayCellTimex100 = 270/100 ps
4468 11:08:48.353287 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4469 11:08:48.359513 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4470 11:08:48.362595 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4471 11:08:48.366223 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4472 11:08:48.369416 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4473 11:08:48.372527 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4474 11:08:48.373163
4475 11:08:48.376215 CA PerBit enable=1, Macro0, CA PI delay=33
4476 11:08:48.376676
4477 11:08:48.379343 [CBTSetCACLKResult] CA Dly = 33
4478 11:08:48.382063 CS Dly: 5 (0~37)
4479 11:08:48.382135
4480 11:08:48.385472 ----->DramcWriteLeveling(PI) begin...
4481 11:08:48.385556 ==
4482 11:08:48.389096 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 11:08:48.391901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 11:08:48.391984 ==
4485 11:08:48.395285 Write leveling (Byte 0): 29 => 29
4486 11:08:48.398830 Write leveling (Byte 1): 31 => 31
4487 11:08:48.401934 DramcWriteLeveling(PI) end<-----
4488 11:08:48.402016
4489 11:08:48.402081 ==
4490 11:08:48.405109 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 11:08:48.408165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 11:08:48.408249 ==
4493 11:08:48.411815 [Gating] SW mode calibration
4494 11:08:48.418752 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4495 11:08:48.425426 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4496 11:08:48.429291 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4497 11:08:48.431999 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4498 11:08:48.438521 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4499 11:08:48.442353 0 9 12 | B1->B0 | 3333 2e2e | 1 1 | (1 1) (1 0)
4500 11:08:48.445694 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4501 11:08:48.451942 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 11:08:48.455825 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 11:08:48.458463 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 11:08:48.464806 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4505 11:08:48.468334 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4506 11:08:48.474877 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4507 11:08:48.477924 0 10 12 | B1->B0 | 2d2d 3d3d | 0 1 | (1 1) (0 0)
4508 11:08:48.482203 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 11:08:48.484769 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 11:08:48.491883 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 11:08:48.494978 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 11:08:48.497943 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 11:08:48.504516 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 11:08:48.507781 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 11:08:48.511117 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4516 11:08:48.517407 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 11:08:48.521062 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 11:08:48.524449 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 11:08:48.530859 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 11:08:48.534576 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 11:08:48.537121 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 11:08:48.544013 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 11:08:48.547594 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 11:08:48.554191 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 11:08:48.557165 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 11:08:48.560617 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 11:08:48.564051 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 11:08:48.570741 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 11:08:48.573642 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 11:08:48.577298 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 11:08:48.583791 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4532 11:08:48.587189 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4533 11:08:48.589979 Total UI for P1: 0, mck2ui 16
4534 11:08:48.593307 best dqsien dly found for B0: ( 0, 13, 12)
4535 11:08:48.596493 Total UI for P1: 0, mck2ui 16
4536 11:08:48.600098 best dqsien dly found for B1: ( 0, 13, 12)
4537 11:08:48.603261 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4538 11:08:48.607254 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4539 11:08:48.608098
4540 11:08:48.609952 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4541 11:08:48.616489 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4542 11:08:48.616917 [Gating] SW calibration Done
4543 11:08:48.619487 ==
4544 11:08:48.620137 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 11:08:48.626549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 11:08:48.626976 ==
4547 11:08:48.627314 RX Vref Scan: 0
4548 11:08:48.627707
4549 11:08:48.629873 RX Vref 0 -> 0, step: 1
4550 11:08:48.630297
4551 11:08:48.633001 RX Delay -230 -> 252, step: 16
4552 11:08:48.636550 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4553 11:08:48.639340 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4554 11:08:48.646458 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4555 11:08:48.649891 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4556 11:08:48.652927 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4557 11:08:48.656064 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4558 11:08:48.662818 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4559 11:08:48.666207 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4560 11:08:48.669433 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4561 11:08:48.672974 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4562 11:08:48.676365 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4563 11:08:48.682423 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4564 11:08:48.685476 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4565 11:08:48.689398 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4566 11:08:48.695297 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4567 11:08:48.698670 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4568 11:08:48.699229 ==
4569 11:08:48.702548 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 11:08:48.705476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 11:08:48.705949 ==
4572 11:08:48.709506 DQS Delay:
4573 11:08:48.710064 DQS0 = 0, DQS1 = 0
4574 11:08:48.710435 DQM Delay:
4575 11:08:48.711782 DQM0 = 47, DQM1 = 38
4576 11:08:48.712248 DQ Delay:
4577 11:08:48.715211 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4578 11:08:48.718821 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4579 11:08:48.721515 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4580 11:08:48.724796 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4581 11:08:48.725264
4582 11:08:48.725652
4583 11:08:48.725995 ==
4584 11:08:48.728212 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 11:08:48.735100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 11:08:48.735569 ==
4587 11:08:48.735983
4588 11:08:48.736328
4589 11:08:48.736657 TX Vref Scan disable
4590 11:08:48.738437 == TX Byte 0 ==
4591 11:08:48.741801 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4592 11:08:48.749268 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4593 11:08:48.749908 == TX Byte 1 ==
4594 11:08:48.752278 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4595 11:08:48.758992 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4596 11:08:48.759435 ==
4597 11:08:48.761623 Dram Type= 6, Freq= 0, CH_1, rank 0
4598 11:08:48.765238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 11:08:48.765761 ==
4600 11:08:48.766101
4601 11:08:48.766417
4602 11:08:48.768421 TX Vref Scan disable
4603 11:08:48.771650 == TX Byte 0 ==
4604 11:08:48.775293 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4605 11:08:48.778456 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4606 11:08:48.781577 == TX Byte 1 ==
4607 11:08:48.785312 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4608 11:08:48.788319 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4609 11:08:48.788749
4610 11:08:48.789085 [DATLAT]
4611 11:08:48.791299 Freq=600, CH1 RK0
4612 11:08:48.791768
4613 11:08:48.794700 DATLAT Default: 0x9
4614 11:08:48.795124 0, 0xFFFF, sum = 0
4615 11:08:48.797746 1, 0xFFFF, sum = 0
4616 11:08:48.798147 2, 0xFFFF, sum = 0
4617 11:08:48.801508 3, 0xFFFF, sum = 0
4618 11:08:48.801740 4, 0xFFFF, sum = 0
4619 11:08:48.804303 5, 0xFFFF, sum = 0
4620 11:08:48.804535 6, 0xFFFF, sum = 0
4621 11:08:48.807415 7, 0xFFFF, sum = 0
4622 11:08:48.807600 8, 0x0, sum = 1
4623 11:08:48.810548 9, 0x0, sum = 2
4624 11:08:48.810759 10, 0x0, sum = 3
4625 11:08:48.813924 11, 0x0, sum = 4
4626 11:08:48.814087 best_step = 9
4627 11:08:48.814210
4628 11:08:48.814323 ==
4629 11:08:48.817055 Dram Type= 6, Freq= 0, CH_1, rank 0
4630 11:08:48.820661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 11:08:48.823656 ==
4632 11:08:48.823827 RX Vref Scan: 1
4633 11:08:48.823919
4634 11:08:48.826799 RX Vref 0 -> 0, step: 1
4635 11:08:48.826929
4636 11:08:48.830125 RX Delay -195 -> 252, step: 8
4637 11:08:48.830228
4638 11:08:48.834091 Set Vref, RX VrefLevel [Byte0]: 53
4639 11:08:48.834186 [Byte1]: 59
4640 11:08:48.838380
4641 11:08:48.838466 Final RX Vref Byte 0 = 53 to rank0
4642 11:08:48.842228 Final RX Vref Byte 1 = 59 to rank0
4643 11:08:48.845139 Final RX Vref Byte 0 = 53 to rank1
4644 11:08:48.848679 Final RX Vref Byte 1 = 59 to rank1==
4645 11:08:48.852129 Dram Type= 6, Freq= 0, CH_1, rank 0
4646 11:08:48.858572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 11:08:48.858998 ==
4648 11:08:48.859332 DQS Delay:
4649 11:08:48.862102 DQS0 = 0, DQS1 = 0
4650 11:08:48.862524 DQM Delay:
4651 11:08:48.862861 DQM0 = 46, DQM1 = 37
4652 11:08:48.865649 DQ Delay:
4653 11:08:48.868368 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =40
4654 11:08:48.871539 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =40
4655 11:08:48.875061 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4656 11:08:48.878032 DQ12 =44, DQ13 =48, DQ14 =44, DQ15 =48
4657 11:08:48.878460
4658 11:08:48.878800
4659 11:08:48.884752 [DQSOSCAuto] RK0, (LSB)MR18= 0x462b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4660 11:08:48.888204 CH1 RK0: MR19=808, MR18=462B
4661 11:08:48.894900 CH1_RK0: MR19=0x808, MR18=0x462B, DQSOSC=396, MR23=63, INC=167, DEC=111
4662 11:08:48.895330
4663 11:08:48.897860 ----->DramcWriteLeveling(PI) begin...
4664 11:08:48.898292 ==
4665 11:08:48.901468 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 11:08:48.904651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 11:08:48.907165 ==
4668 11:08:48.907393 Write leveling (Byte 0): 29 => 29
4669 11:08:48.910992 Write leveling (Byte 1): 28 => 28
4670 11:08:48.914082 DramcWriteLeveling(PI) end<-----
4671 11:08:48.914268
4672 11:08:48.914412 ==
4673 11:08:48.917341 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 11:08:48.923726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 11:08:48.923866 ==
4676 11:08:48.927334 [Gating] SW mode calibration
4677 11:08:48.933471 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4678 11:08:48.936825 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4679 11:08:48.943577 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4680 11:08:48.947246 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4681 11:08:48.950282 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4682 11:08:48.956710 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 0) (1 1)
4683 11:08:48.960246 0 9 16 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
4684 11:08:48.963721 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 11:08:48.969799 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 11:08:48.973482 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4687 11:08:48.976434 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4688 11:08:48.983803 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4689 11:08:48.986637 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4690 11:08:48.989401 0 10 12 | B1->B0 | 3535 2929 | 1 0 | (0 0) (0 0)
4691 11:08:48.996171 0 10 16 | B1->B0 | 4646 3d3d | 0 0 | (0 0) (0 0)
4692 11:08:48.999643 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 11:08:49.003160 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 11:08:49.009037 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 11:08:49.012395 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 11:08:49.015799 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 11:08:49.022820 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 11:08:49.025701 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4699 11:08:49.029485 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 11:08:49.035830 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 11:08:49.038959 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 11:08:49.042324 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 11:08:49.048918 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 11:08:49.052529 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 11:08:49.056103 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 11:08:49.062189 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 11:08:49.065316 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 11:08:49.069059 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 11:08:49.075194 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 11:08:49.078671 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 11:08:49.081778 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 11:08:49.089095 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 11:08:49.091788 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 11:08:49.094937 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 11:08:49.101794 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4716 11:08:49.102282 Total UI for P1: 0, mck2ui 16
4717 11:08:49.108827 best dqsien dly found for B0: ( 0, 13, 14)
4718 11:08:49.109252 Total UI for P1: 0, mck2ui 16
4719 11:08:49.115070 best dqsien dly found for B1: ( 0, 13, 14)
4720 11:08:49.118078 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4721 11:08:49.121439 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4722 11:08:49.121667
4723 11:08:49.125034 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4724 11:08:49.128404 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4725 11:08:49.131310 [Gating] SW calibration Done
4726 11:08:49.131464 ==
4727 11:08:49.134564 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 11:08:49.137738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 11:08:49.137871 ==
4730 11:08:49.168113 RX Vref Scan: 0
4731 11:08:49.168575
4732 11:08:49.168948 RX Vref 0 -> 0, step: 1
4733 11:08:49.169340
4734 11:08:49.169745 RX Delay -230 -> 252, step: 16
4735 11:08:49.170081 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4736 11:08:49.170390 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4737 11:08:49.170632 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4738 11:08:49.170862 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4739 11:08:49.171087 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4740 11:08:49.171598 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4741 11:08:49.174353 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4742 11:08:49.177806 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4743 11:08:49.181145 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4744 11:08:49.187169 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4745 11:08:49.191069 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4746 11:08:49.194796 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4747 11:08:49.197379 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4748 11:08:49.204088 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4749 11:08:49.207002 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4750 11:08:49.210267 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4751 11:08:49.210387 ==
4752 11:08:49.214194 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 11:08:49.220234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 11:08:49.220330 ==
4755 11:08:49.220406 DQS Delay:
4756 11:08:49.220476 DQS0 = 0, DQS1 = 0
4757 11:08:49.223390 DQM Delay:
4758 11:08:49.223475 DQM0 = 43, DQM1 = 38
4759 11:08:49.226742 DQ Delay:
4760 11:08:49.229928 DQ0 =57, DQ1 =41, DQ2 =25, DQ3 =41
4761 11:08:49.233390 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =33
4762 11:08:49.236951 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4763 11:08:49.240283 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4764 11:08:49.240368
4765 11:08:49.240435
4766 11:08:49.240497 ==
4767 11:08:49.243498 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 11:08:49.246928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 11:08:49.247039 ==
4770 11:08:49.247150
4771 11:08:49.247264
4772 11:08:49.250333 TX Vref Scan disable
4773 11:08:49.250435 == TX Byte 0 ==
4774 11:08:49.256618 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4775 11:08:49.259912 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4776 11:08:49.264272 == TX Byte 1 ==
4777 11:08:49.267076 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4778 11:08:49.270425 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4779 11:08:49.270624 ==
4780 11:08:49.273417 Dram Type= 6, Freq= 0, CH_1, rank 1
4781 11:08:49.276413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4782 11:08:49.276656 ==
4783 11:08:49.279530
4784 11:08:49.279755
4785 11:08:49.279910 TX Vref Scan disable
4786 11:08:49.283384 == TX Byte 0 ==
4787 11:08:49.286525 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4788 11:08:49.293596 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4789 11:08:49.293908 == TX Byte 1 ==
4790 11:08:49.296557 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4791 11:08:49.303593 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4792 11:08:49.304124
4793 11:08:49.304417 [DATLAT]
4794 11:08:49.304683 Freq=600, CH1 RK1
4795 11:08:49.306609
4796 11:08:49.307166 DATLAT Default: 0x9
4797 11:08:49.310376 0, 0xFFFF, sum = 0
4798 11:08:49.311081 1, 0xFFFF, sum = 0
4799 11:08:49.313218 2, 0xFFFF, sum = 0
4800 11:08:49.313937 3, 0xFFFF, sum = 0
4801 11:08:49.316837 4, 0xFFFF, sum = 0
4802 11:08:49.317311 5, 0xFFFF, sum = 0
4803 11:08:49.319622 6, 0xFFFF, sum = 0
4804 11:08:49.320137 7, 0xFFFF, sum = 0
4805 11:08:49.323240 8, 0x0, sum = 1
4806 11:08:49.323787 9, 0x0, sum = 2
4807 11:08:49.326243 10, 0x0, sum = 3
4808 11:08:49.326926 11, 0x0, sum = 4
4809 11:08:49.327506 best_step = 9
4810 11:08:49.329383
4811 11:08:49.330011 ==
4812 11:08:49.332700 Dram Type= 6, Freq= 0, CH_1, rank 1
4813 11:08:49.336166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4814 11:08:49.336586 ==
4815 11:08:49.336919 RX Vref Scan: 0
4816 11:08:49.337227
4817 11:08:49.339488 RX Vref 0 -> 0, step: 1
4818 11:08:49.340001
4819 11:08:49.342650 RX Delay -195 -> 252, step: 8
4820 11:08:49.349124 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4821 11:08:49.352524 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4822 11:08:49.355948 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4823 11:08:49.359058 iDelay=213, Bit 3, Center 44 (-99 ~ 188) 288
4824 11:08:49.365955 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4825 11:08:49.369130 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4826 11:08:49.372761 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4827 11:08:49.375656 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4828 11:08:49.379016 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4829 11:08:49.385471 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4830 11:08:49.389407 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4831 11:08:49.391972 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4832 11:08:49.394993 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4833 11:08:49.401390 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4834 11:08:49.405406 iDelay=213, Bit 14, Center 40 (-115 ~ 196) 312
4835 11:08:49.409008 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4836 11:08:49.409432 ==
4837 11:08:49.411532 Dram Type= 6, Freq= 0, CH_1, rank 1
4838 11:08:49.419087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4839 11:08:49.419564 ==
4840 11:08:49.420004 DQS Delay:
4841 11:08:49.421515 DQS0 = 0, DQS1 = 0
4842 11:08:49.422029 DQM Delay:
4843 11:08:49.422410 DQM0 = 45, DQM1 = 36
4844 11:08:49.424790 DQ Delay:
4845 11:08:49.428093 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4846 11:08:49.431358 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =40
4847 11:08:49.434744 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4848 11:08:49.437373 DQ12 =48, DQ13 =44, DQ14 =40, DQ15 =48
4849 11:08:49.437609
4850 11:08:49.437808
4851 11:08:49.444394 [DQSOSCAuto] RK1, (LSB)MR18= 0x281d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
4852 11:08:49.447450 CH1 RK1: MR19=808, MR18=281D
4853 11:08:49.454136 CH1_RK1: MR19=0x808, MR18=0x281D, DQSOSC=402, MR23=63, INC=162, DEC=108
4854 11:08:49.457180 [RxdqsGatingPostProcess] freq 600
4855 11:08:49.464008 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4856 11:08:49.464172 Pre-setting of DQS Precalculation
4857 11:08:49.470558 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4858 11:08:49.477515 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4859 11:08:49.484641 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4860 11:08:49.485090
4861 11:08:49.485476
4862 11:08:49.487175 [Calibration Summary] 1200 Mbps
4863 11:08:49.490704 CH 0, Rank 0
4864 11:08:49.491240 SW Impedance : PASS
4865 11:08:49.494261 DUTY Scan : NO K
4866 11:08:49.494680 ZQ Calibration : PASS
4867 11:08:49.497690 Jitter Meter : NO K
4868 11:08:49.500466 CBT Training : PASS
4869 11:08:49.500917 Write leveling : PASS
4870 11:08:49.504317 RX DQS gating : PASS
4871 11:08:49.507979 RX DQ/DQS(RDDQC) : PASS
4872 11:08:49.508399 TX DQ/DQS : PASS
4873 11:08:49.510432 RX DATLAT : PASS
4874 11:08:49.513906 RX DQ/DQS(Engine): PASS
4875 11:08:49.514323 TX OE : NO K
4876 11:08:49.517486 All Pass.
4877 11:08:49.518046
4878 11:08:49.518533 CH 0, Rank 1
4879 11:08:49.520142 SW Impedance : PASS
4880 11:08:49.520642 DUTY Scan : NO K
4881 11:08:49.523721 ZQ Calibration : PASS
4882 11:08:49.526980 Jitter Meter : NO K
4883 11:08:49.527206 CBT Training : PASS
4884 11:08:49.530325 Write leveling : PASS
4885 11:08:49.533470 RX DQS gating : PASS
4886 11:08:49.533652 RX DQ/DQS(RDDQC) : PASS
4887 11:08:49.536789 TX DQ/DQS : PASS
4888 11:08:49.540200 RX DATLAT : PASS
4889 11:08:49.540351 RX DQ/DQS(Engine): PASS
4890 11:08:49.543771 TX OE : NO K
4891 11:08:49.544201 All Pass.
4892 11:08:49.544539
4893 11:08:49.547122 CH 1, Rank 0
4894 11:08:49.547543 SW Impedance : PASS
4895 11:08:49.550498 DUTY Scan : NO K
4896 11:08:49.553712 ZQ Calibration : PASS
4897 11:08:49.554156 Jitter Meter : NO K
4898 11:08:49.556662 CBT Training : PASS
4899 11:08:49.559946 Write leveling : PASS
4900 11:08:49.560367 RX DQS gating : PASS
4901 11:08:49.563843 RX DQ/DQS(RDDQC) : PASS
4902 11:08:49.564360 TX DQ/DQS : PASS
4903 11:08:49.567143 RX DATLAT : PASS
4904 11:08:49.570570 RX DQ/DQS(Engine): PASS
4905 11:08:49.571109 TX OE : NO K
4906 11:08:49.573184 All Pass.
4907 11:08:49.573703
4908 11:08:49.574037 CH 1, Rank 1
4909 11:08:49.576344 SW Impedance : PASS
4910 11:08:49.576766 DUTY Scan : NO K
4911 11:08:49.579560 ZQ Calibration : PASS
4912 11:08:49.582885 Jitter Meter : NO K
4913 11:08:49.583402 CBT Training : PASS
4914 11:08:49.586129 Write leveling : PASS
4915 11:08:49.589715 RX DQS gating : PASS
4916 11:08:49.590134 RX DQ/DQS(RDDQC) : PASS
4917 11:08:49.592434 TX DQ/DQS : PASS
4918 11:08:49.596138 RX DATLAT : PASS
4919 11:08:49.596562 RX DQ/DQS(Engine): PASS
4920 11:08:49.599231 TX OE : NO K
4921 11:08:49.599655 All Pass.
4922 11:08:49.600045
4923 11:08:49.602511 DramC Write-DBI off
4924 11:08:49.605893 PER_BANK_REFRESH: Hybrid Mode
4925 11:08:49.606315 TX_TRACKING: ON
4926 11:08:49.616614 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4927 11:08:49.619410 [FAST_K] Save calibration result to emmc
4928 11:08:49.622117 dramc_set_vcore_voltage set vcore to 662500
4929 11:08:49.625423 Read voltage for 933, 3
4930 11:08:49.625725 Vio18 = 0
4931 11:08:49.626037 Vcore = 662500
4932 11:08:49.628849 Vdram = 0
4933 11:08:49.629203 Vddq = 0
4934 11:08:49.629457 Vmddr = 0
4935 11:08:49.635356 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4936 11:08:49.641900 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4937 11:08:49.642326 MEM_TYPE=3, freq_sel=17
4938 11:08:49.645210 sv_algorithm_assistance_LP4_1600
4939 11:08:49.648741 ============ PULL DRAM RESETB DOWN ============
4940 11:08:49.655122 ========== PULL DRAM RESETB DOWN end =========
4941 11:08:49.658520 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4942 11:08:49.661665 ===================================
4943 11:08:49.665083 LPDDR4 DRAM CONFIGURATION
4944 11:08:49.668422 ===================================
4945 11:08:49.668838 EX_ROW_EN[0] = 0x0
4946 11:08:49.671636 EX_ROW_EN[1] = 0x0
4947 11:08:49.672094 LP4Y_EN = 0x0
4948 11:08:49.675560 WORK_FSP = 0x0
4949 11:08:49.678384 WL = 0x3
4950 11:08:49.678805 RL = 0x3
4951 11:08:49.681825 BL = 0x2
4952 11:08:49.682242 RPST = 0x0
4953 11:08:49.685015 RD_PRE = 0x0
4954 11:08:49.685434 WR_PRE = 0x1
4955 11:08:49.688077 WR_PST = 0x0
4956 11:08:49.688493 DBI_WR = 0x0
4957 11:08:49.691903 DBI_RD = 0x0
4958 11:08:49.692318 OTF = 0x1
4959 11:08:49.694770 ===================================
4960 11:08:49.698313 ===================================
4961 11:08:49.701295 ANA top config
4962 11:08:49.704740 ===================================
4963 11:08:49.705162 DLL_ASYNC_EN = 0
4964 11:08:49.708163 ALL_SLAVE_EN = 1
4965 11:08:49.710987 NEW_RANK_MODE = 1
4966 11:08:49.714464 DLL_IDLE_MODE = 1
4967 11:08:49.717743 LP45_APHY_COMB_EN = 1
4968 11:08:49.718164 TX_ODT_DIS = 1
4969 11:08:49.721603 NEW_8X_MODE = 1
4970 11:08:49.724573 ===================================
4971 11:08:49.727969 ===================================
4972 11:08:49.731201 data_rate = 1866
4973 11:08:49.734571 CKR = 1
4974 11:08:49.737494 DQ_P2S_RATIO = 8
4975 11:08:49.740956 ===================================
4976 11:08:49.744010 CA_P2S_RATIO = 8
4977 11:08:49.744611 DQ_CA_OPEN = 0
4978 11:08:49.747227 DQ_SEMI_OPEN = 0
4979 11:08:49.750627 CA_SEMI_OPEN = 0
4980 11:08:49.754039 CA_FULL_RATE = 0
4981 11:08:49.757337 DQ_CKDIV4_EN = 1
4982 11:08:49.760155 CA_CKDIV4_EN = 1
4983 11:08:49.760395 CA_PREDIV_EN = 0
4984 11:08:49.763849 PH8_DLY = 0
4985 11:08:49.766664 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4986 11:08:49.770085 DQ_AAMCK_DIV = 4
4987 11:08:49.773566 CA_AAMCK_DIV = 4
4988 11:08:49.776312 CA_ADMCK_DIV = 4
4989 11:08:49.776545 DQ_TRACK_CA_EN = 0
4990 11:08:49.779985 CA_PICK = 933
4991 11:08:49.783370 CA_MCKIO = 933
4992 11:08:49.786539 MCKIO_SEMI = 0
4993 11:08:49.790005 PLL_FREQ = 3732
4994 11:08:49.793460 DQ_UI_PI_RATIO = 32
4995 11:08:49.796332 CA_UI_PI_RATIO = 0
4996 11:08:49.799562 ===================================
4997 11:08:49.803129 ===================================
4998 11:08:49.803347 memory_type:LPDDR4
4999 11:08:49.806282 GP_NUM : 10
5000 11:08:49.809809 SRAM_EN : 1
5001 11:08:49.810022 MD32_EN : 0
5002 11:08:49.812760 ===================================
5003 11:08:49.816826 [ANA_INIT] >>>>>>>>>>>>>>
5004 11:08:49.819505 <<<<<< [CONFIGURE PHASE]: ANA_TX
5005 11:08:49.822604 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5006 11:08:49.825783 ===================================
5007 11:08:49.829092 data_rate = 1866,PCW = 0X8f00
5008 11:08:49.832477 ===================================
5009 11:08:49.836107 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5010 11:08:49.839288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5011 11:08:49.845614 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5012 11:08:49.849470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5013 11:08:49.855320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5014 11:08:49.859498 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5015 11:08:49.859607 [ANA_INIT] flow start
5016 11:08:49.862919 [ANA_INIT] PLL >>>>>>>>
5017 11:08:49.865378 [ANA_INIT] PLL <<<<<<<<
5018 11:08:49.865460 [ANA_INIT] MIDPI >>>>>>>>
5019 11:08:49.868773 [ANA_INIT] MIDPI <<<<<<<<
5020 11:08:49.872349 [ANA_INIT] DLL >>>>>>>>
5021 11:08:49.872431 [ANA_INIT] flow end
5022 11:08:49.878737 ============ LP4 DIFF to SE enter ============
5023 11:08:49.881758 ============ LP4 DIFF to SE exit ============
5024 11:08:49.885322 [ANA_INIT] <<<<<<<<<<<<<
5025 11:08:49.889144 [Flow] Enable top DCM control >>>>>
5026 11:08:49.891967 [Flow] Enable top DCM control <<<<<
5027 11:08:49.892048 Enable DLL master slave shuffle
5028 11:08:49.898601 ==============================================================
5029 11:08:49.901902 Gating Mode config
5030 11:08:49.905205 ==============================================================
5031 11:08:49.908570 Config description:
5032 11:08:49.918010 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5033 11:08:49.924568 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5034 11:08:49.928019 SELPH_MODE 0: By rank 1: By Phase
5035 11:08:49.935780 ==============================================================
5036 11:08:49.939118 GAT_TRACK_EN = 1
5037 11:08:49.940995 RX_GATING_MODE = 2
5038 11:08:49.944564 RX_GATING_TRACK_MODE = 2
5039 11:08:49.947949 SELPH_MODE = 1
5040 11:08:49.951709 PICG_EARLY_EN = 1
5041 11:08:49.952306 VALID_LAT_VALUE = 1
5042 11:08:49.958312 ==============================================================
5043 11:08:49.961659 Enter into Gating configuration >>>>
5044 11:08:49.965050 Exit from Gating configuration <<<<
5045 11:08:49.968056 Enter into DVFS_PRE_config >>>>>
5046 11:08:49.978223 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5047 11:08:49.981514 Exit from DVFS_PRE_config <<<<<
5048 11:08:49.984383 Enter into PICG configuration >>>>
5049 11:08:49.988084 Exit from PICG configuration <<<<
5050 11:08:49.990823 [RX_INPUT] configuration >>>>>
5051 11:08:49.994494 [RX_INPUT] configuration <<<<<
5052 11:08:50.001615 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5053 11:08:50.005295 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5054 11:08:50.011117 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5055 11:08:50.017480 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5056 11:08:50.024580 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5057 11:08:50.030736 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5058 11:08:50.034048 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5059 11:08:50.037764 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5060 11:08:50.040847 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5061 11:08:50.047293 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5062 11:08:50.050786 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5063 11:08:50.054143 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5064 11:08:50.057843 ===================================
5065 11:08:50.060326 LPDDR4 DRAM CONFIGURATION
5066 11:08:50.063973 ===================================
5067 11:08:50.066857 EX_ROW_EN[0] = 0x0
5068 11:08:50.067342 EX_ROW_EN[1] = 0x0
5069 11:08:50.070615 LP4Y_EN = 0x0
5070 11:08:50.071082 WORK_FSP = 0x0
5071 11:08:50.073190 WL = 0x3
5072 11:08:50.073609 RL = 0x3
5073 11:08:50.076812 BL = 0x2
5074 11:08:50.077286 RPST = 0x0
5075 11:08:50.080268 RD_PRE = 0x0
5076 11:08:50.080731 WR_PRE = 0x1
5077 11:08:50.083436 WR_PST = 0x0
5078 11:08:50.084060 DBI_WR = 0x0
5079 11:08:50.086511 DBI_RD = 0x0
5080 11:08:50.086805 OTF = 0x1
5081 11:08:50.090269 ===================================
5082 11:08:50.095884 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5083 11:08:50.099926 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5084 11:08:50.102929 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5085 11:08:50.106648 ===================================
5086 11:08:50.109739 LPDDR4 DRAM CONFIGURATION
5087 11:08:50.112902 ===================================
5088 11:08:50.116453 EX_ROW_EN[0] = 0x10
5089 11:08:50.116867 EX_ROW_EN[1] = 0x0
5090 11:08:50.119757 LP4Y_EN = 0x0
5091 11:08:50.120175 WORK_FSP = 0x0
5092 11:08:50.122817 WL = 0x3
5093 11:08:50.123257 RL = 0x3
5094 11:08:50.125946 BL = 0x2
5095 11:08:50.126593 RPST = 0x0
5096 11:08:50.129526 RD_PRE = 0x0
5097 11:08:50.129942 WR_PRE = 0x1
5098 11:08:50.132682 WR_PST = 0x0
5099 11:08:50.133098 DBI_WR = 0x0
5100 11:08:50.135966 DBI_RD = 0x0
5101 11:08:50.136396 OTF = 0x1
5102 11:08:50.139822 ===================================
5103 11:08:50.146285 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5104 11:08:50.151328 nWR fixed to 30
5105 11:08:50.154806 [ModeRegInit_LP4] CH0 RK0
5106 11:08:50.155364 [ModeRegInit_LP4] CH0 RK1
5107 11:08:50.157642 [ModeRegInit_LP4] CH1 RK0
5108 11:08:50.161277 [ModeRegInit_LP4] CH1 RK1
5109 11:08:50.161695 match AC timing 9
5110 11:08:50.167235 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5111 11:08:50.170876 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5112 11:08:50.174137 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5113 11:08:50.181636 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5114 11:08:50.184113 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5115 11:08:50.184593 ==
5116 11:08:50.187816 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 11:08:50.190547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 11:08:50.190962 ==
5119 11:08:50.197499 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5120 11:08:50.203787 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5121 11:08:50.206714 [CA 0] Center 37 (7~68) winsize 62
5122 11:08:50.210234 [CA 1] Center 37 (7~68) winsize 62
5123 11:08:50.213397 [CA 2] Center 34 (4~65) winsize 62
5124 11:08:50.216922 [CA 3] Center 35 (5~65) winsize 61
5125 11:08:50.220534 [CA 4] Center 33 (3~64) winsize 62
5126 11:08:50.223647 [CA 5] Center 33 (3~63) winsize 61
5127 11:08:50.224376
5128 11:08:50.226769 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5129 11:08:50.227440
5130 11:08:50.229826 [CATrainingPosCal] consider 1 rank data
5131 11:08:50.233457 u2DelayCellTimex100 = 270/100 ps
5132 11:08:50.237282 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5133 11:08:50.239630 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5134 11:08:50.242780 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5135 11:08:50.249690 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5136 11:08:50.252770 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5137 11:08:50.256375 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5138 11:08:50.256790
5139 11:08:50.260186 CA PerBit enable=1, Macro0, CA PI delay=33
5140 11:08:50.260714
5141 11:08:50.262723 [CBTSetCACLKResult] CA Dly = 33
5142 11:08:50.263142 CS Dly: 7 (0~38)
5143 11:08:50.263470 ==
5144 11:08:50.266216 Dram Type= 6, Freq= 0, CH_0, rank 1
5145 11:08:50.272666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 11:08:50.273175 ==
5147 11:08:50.276045 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5148 11:08:50.282650 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5149 11:08:50.286162 [CA 0] Center 37 (7~68) winsize 62
5150 11:08:50.289437 [CA 1] Center 37 (7~68) winsize 62
5151 11:08:50.293172 [CA 2] Center 34 (4~65) winsize 62
5152 11:08:50.296818 [CA 3] Center 34 (4~65) winsize 62
5153 11:08:50.299401 [CA 4] Center 33 (3~64) winsize 62
5154 11:08:50.302659 [CA 5] Center 33 (3~63) winsize 61
5155 11:08:50.303080
5156 11:08:50.306238 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5157 11:08:50.306759
5158 11:08:50.309221 [CATrainingPosCal] consider 2 rank data
5159 11:08:50.312594 u2DelayCellTimex100 = 270/100 ps
5160 11:08:50.316162 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5161 11:08:50.322041 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5162 11:08:50.325708 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5163 11:08:50.329076 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5164 11:08:50.332430 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5165 11:08:50.335659 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5166 11:08:50.336109
5167 11:08:50.339089 CA PerBit enable=1, Macro0, CA PI delay=33
5168 11:08:50.339611
5169 11:08:50.342253 [CBTSetCACLKResult] CA Dly = 33
5170 11:08:50.345102 CS Dly: 7 (0~39)
5171 11:08:50.345521
5172 11:08:50.348674 ----->DramcWriteLeveling(PI) begin...
5173 11:08:50.349100 ==
5174 11:08:50.352080 Dram Type= 6, Freq= 0, CH_0, rank 0
5175 11:08:50.355807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5176 11:08:50.356363 ==
5177 11:08:50.358902 Write leveling (Byte 0): 34 => 34
5178 11:08:50.361632 Write leveling (Byte 1): 30 => 30
5179 11:08:50.365140 DramcWriteLeveling(PI) end<-----
5180 11:08:50.365755
5181 11:08:50.366169 ==
5182 11:08:50.368384 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 11:08:50.371383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 11:08:50.371845 ==
5185 11:08:50.374997 [Gating] SW mode calibration
5186 11:08:50.382134 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5187 11:08:50.388447 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5188 11:08:50.392118 0 14 0 | B1->B0 | 2323 3333 | 1 1 | (1 1) (1 1)
5189 11:08:50.398193 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5190 11:08:50.401164 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 11:08:50.404844 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 11:08:50.408000 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5193 11:08:50.414238 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5194 11:08:50.418035 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5195 11:08:50.421829 0 14 28 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)
5196 11:08:50.427761 0 15 0 | B1->B0 | 3333 2828 | 1 0 | (1 0) (1 0)
5197 11:08:50.431454 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5198 11:08:50.434248 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 11:08:50.440760 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 11:08:50.444106 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5201 11:08:50.447464 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5202 11:08:50.453954 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5203 11:08:50.457622 0 15 28 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
5204 11:08:50.460679 1 0 0 | B1->B0 | 2e2e 4141 | 0 0 | (0 0) (0 0)
5205 11:08:50.467550 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 11:08:50.470714 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 11:08:50.477872 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 11:08:50.480342 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 11:08:50.483955 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 11:08:50.489890 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 11:08:50.493431 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 11:08:50.496694 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5213 11:08:50.503530 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 11:08:50.506546 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 11:08:50.510473 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 11:08:50.513567 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 11:08:50.519838 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 11:08:50.523615 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 11:08:50.526489 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 11:08:50.533814 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 11:08:50.536499 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 11:08:50.539801 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 11:08:50.546455 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 11:08:50.549607 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 11:08:50.556447 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 11:08:50.559770 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 11:08:50.562941 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5228 11:08:50.569337 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5229 11:08:50.569885 Total UI for P1: 0, mck2ui 16
5230 11:08:50.572411 best dqsien dly found for B0: ( 1, 2, 28)
5231 11:08:50.579387 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5232 11:08:50.582519 Total UI for P1: 0, mck2ui 16
5233 11:08:50.585698 best dqsien dly found for B1: ( 1, 3, 2)
5234 11:08:50.589360 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5235 11:08:50.592636 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5236 11:08:50.593079
5237 11:08:50.595447 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5238 11:08:50.598919 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5239 11:08:50.601842 [Gating] SW calibration Done
5240 11:08:50.602264 ==
5241 11:08:50.605148 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 11:08:50.608709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 11:08:50.611718 ==
5244 11:08:50.612142 RX Vref Scan: 0
5245 11:08:50.612477
5246 11:08:50.615384 RX Vref 0 -> 0, step: 1
5247 11:08:50.615847
5248 11:08:50.616188 RX Delay -80 -> 252, step: 8
5249 11:08:50.622257 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5250 11:08:50.625400 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5251 11:08:50.628683 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5252 11:08:50.632130 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5253 11:08:50.635190 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5254 11:08:50.641520 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5255 11:08:50.645477 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5256 11:08:50.648312 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5257 11:08:50.651454 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5258 11:08:50.655374 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5259 11:08:50.658904 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5260 11:08:50.664937 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5261 11:08:50.668486 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5262 11:08:50.672113 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5263 11:08:50.674915 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5264 11:08:50.678328 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5265 11:08:50.681277 ==
5266 11:08:50.684934 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 11:08:50.688071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 11:08:50.688497 ==
5269 11:08:50.688836 DQS Delay:
5270 11:08:50.691074 DQS0 = 0, DQS1 = 0
5271 11:08:50.691495 DQM Delay:
5272 11:08:50.694368 DQM0 = 97, DQM1 = 85
5273 11:08:50.694811 DQ Delay:
5274 11:08:50.698622 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5275 11:08:50.700953 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5276 11:08:50.704384 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =79
5277 11:08:50.708022 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5278 11:08:50.708558
5279 11:08:50.708898
5280 11:08:50.709206 ==
5281 11:08:50.711065 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 11:08:50.714154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 11:08:50.714578 ==
5284 11:08:50.717363
5285 11:08:50.717782
5286 11:08:50.718110 TX Vref Scan disable
5287 11:08:50.720777 == TX Byte 0 ==
5288 11:08:50.723641 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5289 11:08:50.727729 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5290 11:08:50.730729 == TX Byte 1 ==
5291 11:08:50.734102 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5292 11:08:50.736951 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5293 11:08:50.740709 ==
5294 11:08:50.741133 Dram Type= 6, Freq= 0, CH_0, rank 0
5295 11:08:50.746947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 11:08:50.747383 ==
5297 11:08:50.747763
5298 11:08:50.748090
5299 11:08:50.750394 TX Vref Scan disable
5300 11:08:50.750813 == TX Byte 0 ==
5301 11:08:50.756915 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5302 11:08:50.760524 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5303 11:08:50.760945 == TX Byte 1 ==
5304 11:08:50.767044 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5305 11:08:50.770496 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5306 11:08:50.770917
5307 11:08:50.771505 [DATLAT]
5308 11:08:50.773360 Freq=933, CH0 RK0
5309 11:08:50.773776
5310 11:08:50.774102 DATLAT Default: 0xd
5311 11:08:50.776569 0, 0xFFFF, sum = 0
5312 11:08:50.776994 1, 0xFFFF, sum = 0
5313 11:08:50.779849 2, 0xFFFF, sum = 0
5314 11:08:50.780273 3, 0xFFFF, sum = 0
5315 11:08:50.783511 4, 0xFFFF, sum = 0
5316 11:08:50.783971 5, 0xFFFF, sum = 0
5317 11:08:50.787010 6, 0xFFFF, sum = 0
5318 11:08:50.790031 7, 0xFFFF, sum = 0
5319 11:08:50.790473 8, 0xFFFF, sum = 0
5320 11:08:50.793751 9, 0xFFFF, sum = 0
5321 11:08:50.794180 10, 0x0, sum = 1
5322 11:08:50.796076 11, 0x0, sum = 2
5323 11:08:50.796503 12, 0x0, sum = 3
5324 11:08:50.796843 13, 0x0, sum = 4
5325 11:08:50.800396 best_step = 11
5326 11:08:50.800817
5327 11:08:50.801150 ==
5328 11:08:50.803629 Dram Type= 6, Freq= 0, CH_0, rank 0
5329 11:08:50.806396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 11:08:50.806817 ==
5331 11:08:50.809417 RX Vref Scan: 1
5332 11:08:50.809834
5333 11:08:50.813080 RX Vref 0 -> 0, step: 1
5334 11:08:50.813502
5335 11:08:50.813836 RX Delay -61 -> 252, step: 4
5336 11:08:50.814151
5337 11:08:50.816073 Set Vref, RX VrefLevel [Byte0]: 60
5338 11:08:50.819494 [Byte1]: 48
5339 11:08:50.824168
5340 11:08:50.824583 Final RX Vref Byte 0 = 60 to rank0
5341 11:08:50.827561 Final RX Vref Byte 1 = 48 to rank0
5342 11:08:50.830961 Final RX Vref Byte 0 = 60 to rank1
5343 11:08:50.834548 Final RX Vref Byte 1 = 48 to rank1==
5344 11:08:50.837838 Dram Type= 6, Freq= 0, CH_0, rank 0
5345 11:08:50.844364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 11:08:50.844786 ==
5347 11:08:50.845178 DQS Delay:
5348 11:08:50.845619 DQS0 = 0, DQS1 = 0
5349 11:08:50.847263 DQM Delay:
5350 11:08:50.847719 DQM0 = 97, DQM1 = 85
5351 11:08:50.850576 DQ Delay:
5352 11:08:50.854244 DQ0 =94, DQ1 =100, DQ2 =94, DQ3 =94
5353 11:08:50.857501 DQ4 =96, DQ5 =88, DQ6 =104, DQ7 =106
5354 11:08:50.860477 DQ8 =74, DQ9 =72, DQ10 =84, DQ11 =80
5355 11:08:50.863966 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =94
5356 11:08:50.864485
5357 11:08:50.864814
5358 11:08:50.870609 [DQSOSCAuto] RK0, (LSB)MR18= 0x250b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 410 ps
5359 11:08:50.873908 CH0 RK0: MR19=505, MR18=250B
5360 11:08:50.880197 CH0_RK0: MR19=0x505, MR18=0x250B, DQSOSC=410, MR23=63, INC=64, DEC=42
5361 11:08:50.880625
5362 11:08:50.883405 ----->DramcWriteLeveling(PI) begin...
5363 11:08:50.884033 ==
5364 11:08:50.886818 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 11:08:50.890217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 11:08:50.890950 ==
5367 11:08:50.893788 Write leveling (Byte 0): 33 => 33
5368 11:08:50.896809 Write leveling (Byte 1): 30 => 30
5369 11:08:50.900074 DramcWriteLeveling(PI) end<-----
5370 11:08:50.900589
5371 11:08:50.901056 ==
5372 11:08:50.903045 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 11:08:50.910335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 11:08:50.910895 ==
5375 11:08:50.911263 [Gating] SW mode calibration
5376 11:08:50.919857 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5377 11:08:50.923226 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5378 11:08:50.929643 0 14 0 | B1->B0 | 2929 3232 | 1 0 | (1 1) (1 1)
5379 11:08:50.933482 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5380 11:08:50.935825 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 11:08:50.942517 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5382 11:08:50.946007 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5383 11:08:50.949493 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5384 11:08:50.955642 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5385 11:08:50.959188 0 14 28 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5386 11:08:50.962171 0 15 0 | B1->B0 | 2d2d 2929 | 1 0 | (1 0) (0 0)
5387 11:08:50.968807 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5388 11:08:50.972674 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 11:08:50.976089 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5390 11:08:50.982109 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5391 11:08:50.986018 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5392 11:08:50.988742 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5393 11:08:50.995563 0 15 28 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
5394 11:08:50.998685 1 0 0 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
5395 11:08:51.002371 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 11:08:51.008556 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 11:08:51.012134 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 11:08:51.015041 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 11:08:51.021842 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 11:08:51.025249 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 11:08:51.028632 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5402 11:08:51.034846 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5403 11:08:51.038077 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 11:08:51.041543 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 11:08:51.048251 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 11:08:51.051599 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 11:08:51.054759 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 11:08:51.061451 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 11:08:51.064743 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 11:08:51.067716 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 11:08:51.074669 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 11:08:51.077605 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 11:08:51.080986 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 11:08:51.087504 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 11:08:51.090873 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 11:08:51.094267 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 11:08:51.097817 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5418 11:08:51.104083 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5419 11:08:51.107366 Total UI for P1: 0, mck2ui 16
5420 11:08:51.110857 best dqsien dly found for B0: ( 1, 2, 28)
5421 11:08:51.114161 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5422 11:08:51.117579 Total UI for P1: 0, mck2ui 16
5423 11:08:51.120523 best dqsien dly found for B1: ( 1, 2, 30)
5424 11:08:51.124211 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5425 11:08:51.126961 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5426 11:08:51.127493
5427 11:08:51.131063 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5428 11:08:51.137681 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5429 11:08:51.138104 [Gating] SW calibration Done
5430 11:08:51.140279 ==
5431 11:08:51.140696 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 11:08:51.146745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 11:08:51.147207 ==
5434 11:08:51.147555 RX Vref Scan: 0
5435 11:08:51.147976
5436 11:08:51.150274 RX Vref 0 -> 0, step: 1
5437 11:08:51.150765
5438 11:08:51.153715 RX Delay -80 -> 252, step: 8
5439 11:08:51.156767 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5440 11:08:51.160405 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5441 11:08:51.163488 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5442 11:08:51.169772 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5443 11:08:51.173128 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5444 11:08:51.176603 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5445 11:08:51.179497 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5446 11:08:51.183395 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5447 11:08:51.186509 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5448 11:08:51.193502 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5449 11:08:51.196862 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5450 11:08:51.199774 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5451 11:08:51.202851 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5452 11:08:51.209861 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5453 11:08:51.212634 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5454 11:08:51.216034 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5455 11:08:51.216561 ==
5456 11:08:51.220330 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 11:08:51.222815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 11:08:51.223336 ==
5459 11:08:51.226172 DQS Delay:
5460 11:08:51.226826 DQS0 = 0, DQS1 = 0
5461 11:08:51.227174 DQM Delay:
5462 11:08:51.229138 DQM0 = 97, DQM1 = 87
5463 11:08:51.229653 DQ Delay:
5464 11:08:51.232259 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5465 11:08:51.235399 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5466 11:08:51.238754 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5467 11:08:51.242293 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5468 11:08:51.242801
5469 11:08:51.243139
5470 11:08:51.246128 ==
5471 11:08:51.249062 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 11:08:51.252280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 11:08:51.252705 ==
5474 11:08:51.253042
5475 11:08:51.253354
5476 11:08:51.255990 TX Vref Scan disable
5477 11:08:51.256410 == TX Byte 0 ==
5478 11:08:51.259052 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5479 11:08:51.265703 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5480 11:08:51.266221 == TX Byte 1 ==
5481 11:08:51.268919 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5482 11:08:51.275896 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5483 11:08:51.276415 ==
5484 11:08:51.278891 Dram Type= 6, Freq= 0, CH_0, rank 1
5485 11:08:51.281983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 11:08:51.282512 ==
5487 11:08:51.282852
5488 11:08:51.283177
5489 11:08:51.285428 TX Vref Scan disable
5490 11:08:51.288741 == TX Byte 0 ==
5491 11:08:51.292059 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5492 11:08:51.295408 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5493 11:08:51.298120 == TX Byte 1 ==
5494 11:08:51.301816 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5495 11:08:51.305189 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5496 11:08:51.305711
5497 11:08:51.308562 [DATLAT]
5498 11:08:51.309074 Freq=933, CH0 RK1
5499 11:08:51.309411
5500 11:08:51.312059 DATLAT Default: 0xb
5501 11:08:51.312579 0, 0xFFFF, sum = 0
5502 11:08:51.315711 1, 0xFFFF, sum = 0
5503 11:08:51.316234 2, 0xFFFF, sum = 0
5504 11:08:51.318473 3, 0xFFFF, sum = 0
5505 11:08:51.318997 4, 0xFFFF, sum = 0
5506 11:08:51.321855 5, 0xFFFF, sum = 0
5507 11:08:51.322277 6, 0xFFFF, sum = 0
5508 11:08:51.325200 7, 0xFFFF, sum = 0
5509 11:08:51.325624 8, 0xFFFF, sum = 0
5510 11:08:51.328369 9, 0xFFFF, sum = 0
5511 11:08:51.328905 10, 0x0, sum = 1
5512 11:08:51.331576 11, 0x0, sum = 2
5513 11:08:51.332142 12, 0x0, sum = 3
5514 11:08:51.334488 13, 0x0, sum = 4
5515 11:08:51.334925 best_step = 11
5516 11:08:51.335259
5517 11:08:51.335568 ==
5518 11:08:51.337812 Dram Type= 6, Freq= 0, CH_0, rank 1
5519 11:08:51.344692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 11:08:51.345113 ==
5521 11:08:51.345448 RX Vref Scan: 0
5522 11:08:51.345759
5523 11:08:51.348336 RX Vref 0 -> 0, step: 1
5524 11:08:51.348952
5525 11:08:51.351114 RX Delay -61 -> 252, step: 4
5526 11:08:51.354157 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5527 11:08:51.357794 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5528 11:08:51.364441 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5529 11:08:51.367870 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5530 11:08:51.370772 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5531 11:08:51.374160 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5532 11:08:51.377701 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5533 11:08:51.384201 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5534 11:08:51.387466 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5535 11:08:51.391012 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5536 11:08:51.394174 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5537 11:08:51.397818 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5538 11:08:51.403995 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5539 11:08:51.407131 iDelay=203, Bit 13, Center 90 (-5 ~ 186) 192
5540 11:08:51.410768 iDelay=203, Bit 14, Center 98 (11 ~ 186) 176
5541 11:08:51.413510 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5542 11:08:51.414020 ==
5543 11:08:51.417078 Dram Type= 6, Freq= 0, CH_0, rank 1
5544 11:08:51.423930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 11:08:51.424445 ==
5546 11:08:51.424785 DQS Delay:
5547 11:08:51.425094 DQS0 = 0, DQS1 = 0
5548 11:08:51.427220 DQM Delay:
5549 11:08:51.427945 DQM0 = 95, DQM1 = 85
5550 11:08:51.430236 DQ Delay:
5551 11:08:51.433278 DQ0 =92, DQ1 =98, DQ2 =90, DQ3 =94
5552 11:08:51.436781 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5553 11:08:51.439917 DQ8 =76, DQ9 =74, DQ10 =86, DQ11 =78
5554 11:08:51.443068 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =92
5555 11:08:51.443484
5556 11:08:51.443864
5557 11:08:51.450047 [DQSOSCAuto] RK1, (LSB)MR18= 0x20f1, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 411 ps
5558 11:08:51.453312 CH0 RK1: MR19=504, MR18=20F1
5559 11:08:51.460142 CH0_RK1: MR19=0x504, MR18=0x20F1, DQSOSC=411, MR23=63, INC=64, DEC=42
5560 11:08:51.463174 [RxdqsGatingPostProcess] freq 933
5561 11:08:51.467350 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5562 11:08:51.469728 best DQS0 dly(2T, 0.5T) = (0, 10)
5563 11:08:51.473505 best DQS1 dly(2T, 0.5T) = (0, 11)
5564 11:08:51.476535 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5565 11:08:51.479428 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5566 11:08:51.482966 best DQS0 dly(2T, 0.5T) = (0, 10)
5567 11:08:51.487100 best DQS1 dly(2T, 0.5T) = (0, 10)
5568 11:08:51.489519 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5569 11:08:51.493453 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5570 11:08:51.496509 Pre-setting of DQS Precalculation
5571 11:08:51.503120 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5572 11:08:51.503642 ==
5573 11:08:51.506449 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 11:08:51.510028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 11:08:51.510551 ==
5576 11:08:51.516309 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5577 11:08:51.519206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5578 11:08:51.523185 [CA 0] Center 36 (6~67) winsize 62
5579 11:08:51.526150 [CA 1] Center 37 (6~68) winsize 63
5580 11:08:51.529453 [CA 2] Center 34 (4~65) winsize 62
5581 11:08:51.532816 [CA 3] Center 33 (3~64) winsize 62
5582 11:08:51.536315 [CA 4] Center 34 (4~64) winsize 61
5583 11:08:51.539589 [CA 5] Center 33 (3~64) winsize 62
5584 11:08:51.540066
5585 11:08:51.543023 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5586 11:08:51.543444
5587 11:08:51.546198 [CATrainingPosCal] consider 1 rank data
5588 11:08:51.550171 u2DelayCellTimex100 = 270/100 ps
5589 11:08:51.552722 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5590 11:08:51.559278 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5591 11:08:51.562857 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5592 11:08:51.566603 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5593 11:08:51.569538 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5594 11:08:51.572569 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5595 11:08:51.573084
5596 11:08:51.576058 CA PerBit enable=1, Macro0, CA PI delay=33
5597 11:08:51.576625
5598 11:08:51.578923 [CBTSetCACLKResult] CA Dly = 33
5599 11:08:51.582231 CS Dly: 6 (0~37)
5600 11:08:51.582746 ==
5601 11:08:51.585749 Dram Type= 6, Freq= 0, CH_1, rank 1
5602 11:08:51.588900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 11:08:51.589418 ==
5604 11:08:51.595472 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5605 11:08:51.598528 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5606 11:08:51.603550 [CA 0] Center 36 (6~67) winsize 62
5607 11:08:51.606375 [CA 1] Center 37 (7~67) winsize 61
5608 11:08:51.609912 [CA 2] Center 34 (4~65) winsize 62
5609 11:08:51.612774 [CA 3] Center 33 (3~64) winsize 62
5610 11:08:51.616300 [CA 4] Center 34 (3~65) winsize 63
5611 11:08:51.619817 [CA 5] Center 33 (3~64) winsize 62
5612 11:08:51.620415
5613 11:08:51.623942 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5614 11:08:51.624523
5615 11:08:51.626448 [CATrainingPosCal] consider 2 rank data
5616 11:08:51.629423 u2DelayCellTimex100 = 270/100 ps
5617 11:08:51.633155 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5618 11:08:51.639333 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5619 11:08:51.642505 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5620 11:08:51.646210 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5621 11:08:51.649900 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5622 11:08:51.652833 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5623 11:08:51.653356
5624 11:08:51.655997 CA PerBit enable=1, Macro0, CA PI delay=33
5625 11:08:51.656419
5626 11:08:51.659402 [CBTSetCACLKResult] CA Dly = 33
5627 11:08:51.662845 CS Dly: 7 (0~39)
5628 11:08:51.663362
5629 11:08:51.666100 ----->DramcWriteLeveling(PI) begin...
5630 11:08:51.666653 ==
5631 11:08:51.669158 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 11:08:51.672387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 11:08:51.672968 ==
5634 11:08:51.675642 Write leveling (Byte 0): 25 => 25
5635 11:08:51.679411 Write leveling (Byte 1): 27 => 27
5636 11:08:51.682372 DramcWriteLeveling(PI) end<-----
5637 11:08:51.682912
5638 11:08:51.683243 ==
5639 11:08:51.685613 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 11:08:51.689822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 11:08:51.690342 ==
5642 11:08:51.692134 [Gating] SW mode calibration
5643 11:08:51.699021 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5644 11:08:51.705959 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5645 11:08:51.708726 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5646 11:08:51.712037 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 11:08:51.719196 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 11:08:51.722074 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5649 11:08:51.724838 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5650 11:08:51.732209 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5651 11:08:51.735304 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
5652 11:08:51.738400 0 14 28 | B1->B0 | 2f2f 2525 | 1 0 | (0 0) (0 0)
5653 11:08:51.744787 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5654 11:08:51.748464 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 11:08:51.752198 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 11:08:51.758426 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 11:08:51.761440 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5658 11:08:51.765036 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5659 11:08:51.771193 0 15 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5660 11:08:51.774862 0 15 28 | B1->B0 | 3636 3a3a | 0 0 | (0 0) (0 0)
5661 11:08:51.778272 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 11:08:51.784325 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 11:08:51.787859 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 11:08:51.791093 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 11:08:51.797391 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 11:08:51.800810 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 11:08:51.804246 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5668 11:08:51.810953 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5669 11:08:51.814177 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 11:08:51.817403 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 11:08:51.823877 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 11:08:51.827122 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 11:08:51.830644 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 11:08:51.837362 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 11:08:51.840563 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 11:08:51.844061 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 11:08:51.850656 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 11:08:51.853844 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 11:08:51.856890 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 11:08:51.863474 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 11:08:51.866613 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 11:08:51.870121 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 11:08:51.876584 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 11:08:51.880211 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5685 11:08:51.883775 Total UI for P1: 0, mck2ui 16
5686 11:08:51.886426 best dqsien dly found for B0: ( 1, 2, 26)
5687 11:08:51.890010 Total UI for P1: 0, mck2ui 16
5688 11:08:51.893141 best dqsien dly found for B1: ( 1, 2, 26)
5689 11:08:51.896355 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5690 11:08:51.899912 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5691 11:08:51.900429
5692 11:08:51.903151 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5693 11:08:51.909800 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5694 11:08:51.910333 [Gating] SW calibration Done
5695 11:08:51.910673 ==
5696 11:08:51.912645 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 11:08:51.919209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 11:08:51.919771 ==
5699 11:08:51.920119 RX Vref Scan: 0
5700 11:08:51.920430
5701 11:08:51.922655 RX Vref 0 -> 0, step: 1
5702 11:08:51.923175
5703 11:08:51.926144 RX Delay -80 -> 252, step: 8
5704 11:08:51.928826 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5705 11:08:51.932633 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5706 11:08:51.935523 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5707 11:08:51.942362 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5708 11:08:51.945975 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5709 11:08:51.948720 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5710 11:08:51.952081 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5711 11:08:51.955077 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5712 11:08:51.958445 iDelay=208, Bit 8, Center 79 (-24 ~ 183) 208
5713 11:08:51.965393 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5714 11:08:51.968240 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5715 11:08:51.971942 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5716 11:08:51.974785 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5717 11:08:51.981589 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5718 11:08:51.985284 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5719 11:08:51.988422 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5720 11:08:51.988933 ==
5721 11:08:51.991603 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 11:08:51.995000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 11:08:51.995518 ==
5724 11:08:51.998645 DQS Delay:
5725 11:08:51.999203 DQS0 = 0, DQS1 = 0
5726 11:08:51.999550 DQM Delay:
5727 11:08:52.001877 DQM0 = 99, DQM1 = 90
5728 11:08:52.002396 DQ Delay:
5729 11:08:52.004470 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =95
5730 11:08:52.008592 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5731 11:08:52.011477 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5732 11:08:52.015354 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5733 11:08:52.015913
5734 11:08:52.016254
5735 11:08:52.017815 ==
5736 11:08:52.021068 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 11:08:52.024634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 11:08:52.025179 ==
5739 11:08:52.025519
5740 11:08:52.025825
5741 11:08:52.027513 TX Vref Scan disable
5742 11:08:52.028110 == TX Byte 0 ==
5743 11:08:52.030876 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5744 11:08:52.037681 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5745 11:08:52.038210 == TX Byte 1 ==
5746 11:08:52.044333 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5747 11:08:52.047384 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5748 11:08:52.047847 ==
5749 11:08:52.051206 Dram Type= 6, Freq= 0, CH_1, rank 0
5750 11:08:52.054629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 11:08:52.055063 ==
5752 11:08:52.055404
5753 11:08:52.055765
5754 11:08:52.057100 TX Vref Scan disable
5755 11:08:52.060369 == TX Byte 0 ==
5756 11:08:52.063948 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5757 11:08:52.067108 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5758 11:08:52.070993 == TX Byte 1 ==
5759 11:08:52.073673 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5760 11:08:52.076857 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5761 11:08:52.077326
5762 11:08:52.080644 [DATLAT]
5763 11:08:52.081107 Freq=933, CH1 RK0
5764 11:08:52.081475
5765 11:08:52.083899 DATLAT Default: 0xd
5766 11:08:52.084402 0, 0xFFFF, sum = 0
5767 11:08:52.086613 1, 0xFFFF, sum = 0
5768 11:08:52.087083 2, 0xFFFF, sum = 0
5769 11:08:52.090036 3, 0xFFFF, sum = 0
5770 11:08:52.090507 4, 0xFFFF, sum = 0
5771 11:08:52.093656 5, 0xFFFF, sum = 0
5772 11:08:52.094132 6, 0xFFFF, sum = 0
5773 11:08:52.097109 7, 0xFFFF, sum = 0
5774 11:08:52.097536 8, 0xFFFF, sum = 0
5775 11:08:52.100096 9, 0xFFFF, sum = 0
5776 11:08:52.100525 10, 0x0, sum = 1
5777 11:08:52.103430 11, 0x0, sum = 2
5778 11:08:52.104024 12, 0x0, sum = 3
5779 11:08:52.107707 13, 0x0, sum = 4
5780 11:08:52.108274 best_step = 11
5781 11:08:52.108616
5782 11:08:52.108927 ==
5783 11:08:52.109600 Dram Type= 6, Freq= 0, CH_1, rank 0
5784 11:08:52.117372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 11:08:52.117893 ==
5786 11:08:52.118234 RX Vref Scan: 1
5787 11:08:52.118549
5788 11:08:52.119849 RX Vref 0 -> 0, step: 1
5789 11:08:52.120266
5790 11:08:52.123419 RX Delay -69 -> 252, step: 4
5791 11:08:52.123996
5792 11:08:52.126300 Set Vref, RX VrefLevel [Byte0]: 53
5793 11:08:52.130006 [Byte1]: 59
5794 11:08:52.130532
5795 11:08:52.132714 Final RX Vref Byte 0 = 53 to rank0
5796 11:08:52.136583 Final RX Vref Byte 1 = 59 to rank0
5797 11:08:52.139463 Final RX Vref Byte 0 = 53 to rank1
5798 11:08:52.142934 Final RX Vref Byte 1 = 59 to rank1==
5799 11:08:52.145849 Dram Type= 6, Freq= 0, CH_1, rank 0
5800 11:08:52.149617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 11:08:52.153072 ==
5802 11:08:52.153600 DQS Delay:
5803 11:08:52.153937 DQS0 = 0, DQS1 = 0
5804 11:08:52.155666 DQM Delay:
5805 11:08:52.156117 DQM0 = 100, DQM1 = 94
5806 11:08:52.159430 DQ Delay:
5807 11:08:52.162442 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =96
5808 11:08:52.165757 DQ4 =96, DQ5 =112, DQ6 =112, DQ7 =96
5809 11:08:52.169203 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =86
5810 11:08:52.172540 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =102
5811 11:08:52.172964
5812 11:08:52.173303
5813 11:08:52.179007 [DQSOSCAuto] RK0, (LSB)MR18= 0x1303, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 415 ps
5814 11:08:52.182086 CH1 RK0: MR19=505, MR18=1303
5815 11:08:52.189093 CH1_RK0: MR19=0x505, MR18=0x1303, DQSOSC=415, MR23=63, INC=62, DEC=41
5816 11:08:52.189611
5817 11:08:52.191817 ----->DramcWriteLeveling(PI) begin...
5818 11:08:52.192319 ==
5819 11:08:52.195827 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 11:08:52.198611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 11:08:52.199037 ==
5822 11:08:52.202516 Write leveling (Byte 0): 27 => 27
5823 11:08:52.205307 Write leveling (Byte 1): 29 => 29
5824 11:08:52.208665 DramcWriteLeveling(PI) end<-----
5825 11:08:52.209091
5826 11:08:52.209427 ==
5827 11:08:52.212100 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 11:08:52.218803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 11:08:52.219335 ==
5830 11:08:52.219714 [Gating] SW mode calibration
5831 11:08:52.228767 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5832 11:08:52.231858 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5833 11:08:52.234861 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 11:08:52.241310 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 11:08:52.244994 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 11:08:52.251629 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5837 11:08:52.254495 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5838 11:08:52.257609 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5839 11:08:52.265157 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5840 11:08:52.269054 0 14 28 | B1->B0 | 2b2b 3232 | 0 0 | (0 0) (0 1)
5841 11:08:52.271321 0 15 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
5842 11:08:52.277475 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 11:08:52.280671 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 11:08:52.284476 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5845 11:08:52.290834 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 11:08:52.294582 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5847 11:08:52.297511 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5848 11:08:52.304232 0 15 28 | B1->B0 | 4242 3434 | 0 0 | (0 0) (0 0)
5849 11:08:52.307473 1 0 0 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5850 11:08:52.310621 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 11:08:52.317283 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 11:08:52.320511 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 11:08:52.323543 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 11:08:52.330507 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 11:08:52.333325 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5856 11:08:52.336736 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5857 11:08:52.343625 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 11:08:52.346677 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 11:08:52.350122 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 11:08:52.356560 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 11:08:52.360191 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 11:08:52.363215 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 11:08:52.370337 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 11:08:52.373365 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 11:08:52.376932 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 11:08:52.383386 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 11:08:52.386364 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 11:08:52.389549 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 11:08:52.396665 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 11:08:52.399912 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 11:08:52.403102 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5872 11:08:52.410036 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5873 11:08:52.413263 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5874 11:08:52.416189 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5875 11:08:52.419770 Total UI for P1: 0, mck2ui 16
5876 11:08:52.422374 best dqsien dly found for B0: ( 1, 2, 28)
5877 11:08:52.425683 Total UI for P1: 0, mck2ui 16
5878 11:08:52.429022 best dqsien dly found for B1: ( 1, 2, 28)
5879 11:08:52.432249 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5880 11:08:52.436208 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5881 11:08:52.436676
5882 11:08:52.439388 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5883 11:08:52.445368 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5884 11:08:52.445832 [Gating] SW calibration Done
5885 11:08:52.449044 ==
5886 11:08:52.449584 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 11:08:52.455641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 11:08:52.456262 ==
5889 11:08:52.456637 RX Vref Scan: 0
5890 11:08:52.456984
5891 11:08:52.458918 RX Vref 0 -> 0, step: 1
5892 11:08:52.459382
5893 11:08:52.462513 RX Delay -80 -> 252, step: 8
5894 11:08:52.465424 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5895 11:08:52.469096 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5896 11:08:52.472584 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5897 11:08:52.478920 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5898 11:08:52.482816 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5899 11:08:52.485573 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5900 11:08:52.488384 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5901 11:08:52.491902 iDelay=208, Bit 7, Center 99 (0 ~ 199) 200
5902 11:08:52.495138 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5903 11:08:52.501624 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5904 11:08:52.505648 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5905 11:08:52.508405 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5906 11:08:52.511735 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5907 11:08:52.515212 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5908 11:08:52.521367 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5909 11:08:52.525049 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5910 11:08:52.525516 ==
5911 11:08:52.528165 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 11:08:52.531771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 11:08:52.532239 ==
5914 11:08:52.534919 DQS Delay:
5915 11:08:52.535479 DQS0 = 0, DQS1 = 0
5916 11:08:52.535907 DQM Delay:
5917 11:08:52.538449 DQM0 = 101, DQM1 = 92
5918 11:08:52.539018 DQ Delay:
5919 11:08:52.541268 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5920 11:08:52.544727 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5921 11:08:52.547792 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5922 11:08:52.551180 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5923 11:08:52.551646
5924 11:08:52.552072
5925 11:08:52.554876 ==
5926 11:08:52.555447 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 11:08:52.561190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 11:08:52.561662 ==
5929 11:08:52.562032
5930 11:08:52.562372
5931 11:08:52.564196 TX Vref Scan disable
5932 11:08:52.564664 == TX Byte 0 ==
5933 11:08:52.567572 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5934 11:08:52.574244 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5935 11:08:52.574817 == TX Byte 1 ==
5936 11:08:52.580755 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5937 11:08:52.584114 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5938 11:08:52.584601 ==
5939 11:08:52.587707 Dram Type= 6, Freq= 0, CH_1, rank 1
5940 11:08:52.591275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5941 11:08:52.591908 ==
5942 11:08:52.592288
5943 11:08:52.592628
5944 11:08:52.593646 TX Vref Scan disable
5945 11:08:52.597266 == TX Byte 0 ==
5946 11:08:52.600649 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5947 11:08:52.603978 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5948 11:08:52.607503 == TX Byte 1 ==
5949 11:08:52.611101 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5950 11:08:52.613881 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5951 11:08:52.614454
5952 11:08:52.617525 [DATLAT]
5953 11:08:52.618096 Freq=933, CH1 RK1
5954 11:08:52.618467
5955 11:08:52.620178 DATLAT Default: 0xb
5956 11:08:52.620644 0, 0xFFFF, sum = 0
5957 11:08:52.623857 1, 0xFFFF, sum = 0
5958 11:08:52.624436 2, 0xFFFF, sum = 0
5959 11:08:52.627008 3, 0xFFFF, sum = 0
5960 11:08:52.627584 4, 0xFFFF, sum = 0
5961 11:08:52.630186 5, 0xFFFF, sum = 0
5962 11:08:52.630761 6, 0xFFFF, sum = 0
5963 11:08:52.633492 7, 0xFFFF, sum = 0
5964 11:08:52.633964 8, 0xFFFF, sum = 0
5965 11:08:52.637250 9, 0xFFFF, sum = 0
5966 11:08:52.637720 10, 0x0, sum = 1
5967 11:08:52.639957 11, 0x0, sum = 2
5968 11:08:52.640429 12, 0x0, sum = 3
5969 11:08:52.643637 13, 0x0, sum = 4
5970 11:08:52.644145 best_step = 11
5971 11:08:52.644514
5972 11:08:52.644856 ==
5973 11:08:52.647050 Dram Type= 6, Freq= 0, CH_1, rank 1
5974 11:08:52.653547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5975 11:08:52.654124 ==
5976 11:08:52.654502 RX Vref Scan: 0
5977 11:08:52.654881
5978 11:08:52.656805 RX Vref 0 -> 0, step: 1
5979 11:08:52.657271
5980 11:08:52.659766 RX Delay -61 -> 252, step: 4
5981 11:08:52.664271 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5982 11:08:52.670222 iDelay=207, Bit 1, Center 96 (7 ~ 186) 180
5983 11:08:52.673093 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
5984 11:08:52.676264 iDelay=207, Bit 3, Center 100 (15 ~ 186) 172
5985 11:08:52.679828 iDelay=207, Bit 4, Center 100 (7 ~ 194) 188
5986 11:08:52.683083 iDelay=207, Bit 5, Center 110 (19 ~ 202) 184
5987 11:08:52.689992 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5988 11:08:52.692919 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5989 11:08:52.696226 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
5990 11:08:52.699960 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5991 11:08:52.702971 iDelay=207, Bit 10, Center 96 (7 ~ 186) 180
5992 11:08:52.706506 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5993 11:08:52.712784 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5994 11:08:52.716020 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
5995 11:08:52.719110 iDelay=207, Bit 14, Center 102 (11 ~ 194) 184
5996 11:08:52.722425 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5997 11:08:52.722989 ==
5998 11:08:52.725582 Dram Type= 6, Freq= 0, CH_1, rank 1
5999 11:08:52.732544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6000 11:08:52.733113 ==
6001 11:08:52.733485 DQS Delay:
6002 11:08:52.735515 DQS0 = 0, DQS1 = 0
6003 11:08:52.736017 DQM Delay:
6004 11:08:52.736387 DQM0 = 101, DQM1 = 94
6005 11:08:52.739104 DQ Delay:
6006 11:08:52.742674 DQ0 =104, DQ1 =96, DQ2 =88, DQ3 =100
6007 11:08:52.745303 DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =98
6008 11:08:52.749081 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =84
6009 11:08:52.752564 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102
6010 11:08:52.753127
6011 11:08:52.753496
6012 11:08:52.758820 [DQSOSCAuto] RK1, (LSB)MR18= 0x3fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 421 ps
6013 11:08:52.762154 CH1 RK1: MR19=504, MR18=3FD
6014 11:08:52.768969 CH1_RK1: MR19=0x504, MR18=0x3FD, DQSOSC=421, MR23=63, INC=61, DEC=40
6015 11:08:52.772555 [RxdqsGatingPostProcess] freq 933
6016 11:08:52.778841 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6017 11:08:52.782102 best DQS0 dly(2T, 0.5T) = (0, 10)
6018 11:08:52.782673 best DQS1 dly(2T, 0.5T) = (0, 10)
6019 11:08:52.785407 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6020 11:08:52.788359 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6021 11:08:52.792111 best DQS0 dly(2T, 0.5T) = (0, 10)
6022 11:08:52.794926 best DQS1 dly(2T, 0.5T) = (0, 10)
6023 11:08:52.798701 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6024 11:08:52.801692 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6025 11:08:52.805283 Pre-setting of DQS Precalculation
6026 11:08:52.811844 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6027 11:08:52.818006 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6028 11:08:52.825304 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6029 11:08:52.825919
6030 11:08:52.826307
6031 11:08:52.828175 [Calibration Summary] 1866 Mbps
6032 11:08:52.828639 CH 0, Rank 0
6033 11:08:52.831409 SW Impedance : PASS
6034 11:08:52.835168 DUTY Scan : NO K
6035 11:08:52.835789 ZQ Calibration : PASS
6036 11:08:52.837958 Jitter Meter : NO K
6037 11:08:52.841888 CBT Training : PASS
6038 11:08:52.842361 Write leveling : PASS
6039 11:08:52.844579 RX DQS gating : PASS
6040 11:08:52.847745 RX DQ/DQS(RDDQC) : PASS
6041 11:08:52.848311 TX DQ/DQS : PASS
6042 11:08:52.851747 RX DATLAT : PASS
6043 11:08:52.855294 RX DQ/DQS(Engine): PASS
6044 11:08:52.855910 TX OE : NO K
6045 11:08:52.857496 All Pass.
6046 11:08:52.857960
6047 11:08:52.858367 CH 0, Rank 1
6048 11:08:52.861157 SW Impedance : PASS
6049 11:08:52.861621 DUTY Scan : NO K
6050 11:08:52.864177 ZQ Calibration : PASS
6051 11:08:52.867767 Jitter Meter : NO K
6052 11:08:52.868377 CBT Training : PASS
6053 11:08:52.870820 Write leveling : PASS
6054 11:08:52.874774 RX DQS gating : PASS
6055 11:08:52.875354 RX DQ/DQS(RDDQC) : PASS
6056 11:08:52.877473 TX DQ/DQS : PASS
6057 11:08:52.878047 RX DATLAT : PASS
6058 11:08:52.880786 RX DQ/DQS(Engine): PASS
6059 11:08:52.883990 TX OE : NO K
6060 11:08:52.884456 All Pass.
6061 11:08:52.884830
6062 11:08:52.887017 CH 1, Rank 0
6063 11:08:52.887475 SW Impedance : PASS
6064 11:08:52.890744 DUTY Scan : NO K
6065 11:08:52.891240 ZQ Calibration : PASS
6066 11:08:52.893953 Jitter Meter : NO K
6067 11:08:52.897001 CBT Training : PASS
6068 11:08:52.897468 Write leveling : PASS
6069 11:08:52.900517 RX DQS gating : PASS
6070 11:08:52.903970 RX DQ/DQS(RDDQC) : PASS
6071 11:08:52.904450 TX DQ/DQS : PASS
6072 11:08:52.906859 RX DATLAT : PASS
6073 11:08:52.910331 RX DQ/DQS(Engine): PASS
6074 11:08:52.910750 TX OE : NO K
6075 11:08:52.913425 All Pass.
6076 11:08:52.913846
6077 11:08:52.914177 CH 1, Rank 1
6078 11:08:52.917064 SW Impedance : PASS
6079 11:08:52.917594 DUTY Scan : NO K
6080 11:08:52.920073 ZQ Calibration : PASS
6081 11:08:52.923819 Jitter Meter : NO K
6082 11:08:52.924388 CBT Training : PASS
6083 11:08:52.927341 Write leveling : PASS
6084 11:08:52.930585 RX DQS gating : PASS
6085 11:08:52.931126 RX DQ/DQS(RDDQC) : PASS
6086 11:08:52.933138 TX DQ/DQS : PASS
6087 11:08:52.936803 RX DATLAT : PASS
6088 11:08:52.937265 RX DQ/DQS(Engine): PASS
6089 11:08:52.940009 TX OE : NO K
6090 11:08:52.940481 All Pass.
6091 11:08:52.940816
6092 11:08:52.943300 DramC Write-DBI off
6093 11:08:52.947379 PER_BANK_REFRESH: Hybrid Mode
6094 11:08:52.947846 TX_TRACKING: ON
6095 11:08:52.956586 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6096 11:08:52.960012 [FAST_K] Save calibration result to emmc
6097 11:08:52.964485 dramc_set_vcore_voltage set vcore to 650000
6098 11:08:52.966707 Read voltage for 400, 6
6099 11:08:52.967129 Vio18 = 0
6100 11:08:52.967462 Vcore = 650000
6101 11:08:52.970198 Vdram = 0
6102 11:08:52.970750 Vddq = 0
6103 11:08:52.971296 Vmddr = 0
6104 11:08:52.976507 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6105 11:08:52.979407 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6106 11:08:52.982807 MEM_TYPE=3, freq_sel=20
6107 11:08:52.986168 sv_algorithm_assistance_LP4_800
6108 11:08:52.989267 ============ PULL DRAM RESETB DOWN ============
6109 11:08:52.993138 ========== PULL DRAM RESETB DOWN end =========
6110 11:08:52.999433 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6111 11:08:53.002467 ===================================
6112 11:08:53.005910 LPDDR4 DRAM CONFIGURATION
6113 11:08:53.009698 ===================================
6114 11:08:53.010232 EX_ROW_EN[0] = 0x0
6115 11:08:53.012318 EX_ROW_EN[1] = 0x0
6116 11:08:53.012740 LP4Y_EN = 0x0
6117 11:08:53.016063 WORK_FSP = 0x0
6118 11:08:53.016587 WL = 0x2
6119 11:08:53.019541 RL = 0x2
6120 11:08:53.020111 BL = 0x2
6121 11:08:53.022490 RPST = 0x0
6122 11:08:53.023018 RD_PRE = 0x0
6123 11:08:53.025914 WR_PRE = 0x1
6124 11:08:53.026442 WR_PST = 0x0
6125 11:08:53.029409 DBI_WR = 0x0
6126 11:08:53.032709 DBI_RD = 0x0
6127 11:08:53.033241 OTF = 0x1
6128 11:08:53.035384 ===================================
6129 11:08:53.038840 ===================================
6130 11:08:53.039374 ANA top config
6131 11:08:53.042321 ===================================
6132 11:08:53.045681 DLL_ASYNC_EN = 0
6133 11:08:53.049060 ALL_SLAVE_EN = 1
6134 11:08:53.051895 NEW_RANK_MODE = 1
6135 11:08:53.055751 DLL_IDLE_MODE = 1
6136 11:08:53.056273 LP45_APHY_COMB_EN = 1
6137 11:08:53.058524 TX_ODT_DIS = 1
6138 11:08:53.061927 NEW_8X_MODE = 1
6139 11:08:53.065359 ===================================
6140 11:08:53.068362 ===================================
6141 11:08:53.071868 data_rate = 800
6142 11:08:53.075765 CKR = 1
6143 11:08:53.078458 DQ_P2S_RATIO = 4
6144 11:08:53.082259 ===================================
6145 11:08:53.082792 CA_P2S_RATIO = 4
6146 11:08:53.085021 DQ_CA_OPEN = 0
6147 11:08:53.088361 DQ_SEMI_OPEN = 1
6148 11:08:53.092085 CA_SEMI_OPEN = 1
6149 11:08:53.094745 CA_FULL_RATE = 0
6150 11:08:53.098028 DQ_CKDIV4_EN = 0
6151 11:08:53.098566 CA_CKDIV4_EN = 1
6152 11:08:53.101633 CA_PREDIV_EN = 0
6153 11:08:53.104567 PH8_DLY = 0
6154 11:08:53.108188 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6155 11:08:53.111131 DQ_AAMCK_DIV = 0
6156 11:08:53.114377 CA_AAMCK_DIV = 0
6157 11:08:53.114801 CA_ADMCK_DIV = 4
6158 11:08:53.118301 DQ_TRACK_CA_EN = 0
6159 11:08:53.120999 CA_PICK = 800
6160 11:08:53.124802 CA_MCKIO = 400
6161 11:08:53.127949 MCKIO_SEMI = 400
6162 11:08:53.131666 PLL_FREQ = 3016
6163 11:08:53.134688 DQ_UI_PI_RATIO = 32
6164 11:08:53.137517 CA_UI_PI_RATIO = 32
6165 11:08:53.140810 ===================================
6166 11:08:53.144220 ===================================
6167 11:08:53.144642 memory_type:LPDDR4
6168 11:08:53.147926 GP_NUM : 10
6169 11:08:53.148455 SRAM_EN : 1
6170 11:08:53.151695 MD32_EN : 0
6171 11:08:53.154173 ===================================
6172 11:08:53.157824 [ANA_INIT] >>>>>>>>>>>>>>
6173 11:08:53.160776 <<<<<< [CONFIGURE PHASE]: ANA_TX
6174 11:08:53.164297 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6175 11:08:53.167568 ===================================
6176 11:08:53.171040 data_rate = 800,PCW = 0X7400
6177 11:08:53.174076 ===================================
6178 11:08:53.177379 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6179 11:08:53.180953 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6180 11:08:53.194444 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6181 11:08:53.197887 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6182 11:08:53.200683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6183 11:08:53.204122 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6184 11:08:53.207486 [ANA_INIT] flow start
6185 11:08:53.208150 [ANA_INIT] PLL >>>>>>>>
6186 11:08:53.210472 [ANA_INIT] PLL <<<<<<<<
6187 11:08:53.213939 [ANA_INIT] MIDPI >>>>>>>>
6188 11:08:53.217533 [ANA_INIT] MIDPI <<<<<<<<
6189 11:08:53.218094 [ANA_INIT] DLL >>>>>>>>
6190 11:08:53.220314 [ANA_INIT] flow end
6191 11:08:53.224156 ============ LP4 DIFF to SE enter ============
6192 11:08:53.227398 ============ LP4 DIFF to SE exit ============
6193 11:08:53.230311 [ANA_INIT] <<<<<<<<<<<<<
6194 11:08:53.233926 [Flow] Enable top DCM control >>>>>
6195 11:08:53.236499 [Flow] Enable top DCM control <<<<<
6196 11:08:53.240687 Enable DLL master slave shuffle
6197 11:08:53.246975 ==============================================================
6198 11:08:53.247516 Gating Mode config
6199 11:08:53.253290 ==============================================================
6200 11:08:53.253806 Config description:
6201 11:08:53.263178 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6202 11:08:53.269723 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6203 11:08:53.277160 SELPH_MODE 0: By rank 1: By Phase
6204 11:08:53.279762 ==============================================================
6205 11:08:53.283076 GAT_TRACK_EN = 0
6206 11:08:53.286703 RX_GATING_MODE = 2
6207 11:08:53.290113 RX_GATING_TRACK_MODE = 2
6208 11:08:53.293094 SELPH_MODE = 1
6209 11:08:53.296227 PICG_EARLY_EN = 1
6210 11:08:53.299448 VALID_LAT_VALUE = 1
6211 11:08:53.306154 ==============================================================
6212 11:08:53.309806 Enter into Gating configuration >>>>
6213 11:08:53.313232 Exit from Gating configuration <<<<
6214 11:08:53.316111 Enter into DVFS_PRE_config >>>>>
6215 11:08:53.326297 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6216 11:08:53.330152 Exit from DVFS_PRE_config <<<<<
6217 11:08:53.332714 Enter into PICG configuration >>>>
6218 11:08:53.335764 Exit from PICG configuration <<<<
6219 11:08:53.339484 [RX_INPUT] configuration >>>>>
6220 11:08:53.339951 [RX_INPUT] configuration <<<<<
6221 11:08:53.345976 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6222 11:08:53.352168 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6223 11:08:53.359229 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6224 11:08:53.362069 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6225 11:08:53.368932 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6226 11:08:53.375608 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6227 11:08:53.378868 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6228 11:08:53.385025 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6229 11:08:53.388831 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6230 11:08:53.392240 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6231 11:08:53.395443 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6232 11:08:53.401345 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6233 11:08:53.405156 ===================================
6234 11:08:53.405581 LPDDR4 DRAM CONFIGURATION
6235 11:08:53.408339 ===================================
6236 11:08:53.411521 EX_ROW_EN[0] = 0x0
6237 11:08:53.415338 EX_ROW_EN[1] = 0x0
6238 11:08:53.415897 LP4Y_EN = 0x0
6239 11:08:53.418249 WORK_FSP = 0x0
6240 11:08:53.418776 WL = 0x2
6241 11:08:53.421730 RL = 0x2
6242 11:08:53.422192 BL = 0x2
6243 11:08:53.424590 RPST = 0x0
6244 11:08:53.425012 RD_PRE = 0x0
6245 11:08:53.428182 WR_PRE = 0x1
6246 11:08:53.428602 WR_PST = 0x0
6247 11:08:53.431732 DBI_WR = 0x0
6248 11:08:53.432189 DBI_RD = 0x0
6249 11:08:53.434431 OTF = 0x1
6250 11:08:53.437961 ===================================
6251 11:08:53.441320 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6252 11:08:53.444571 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6253 11:08:53.451705 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6254 11:08:53.454346 ===================================
6255 11:08:53.454776 LPDDR4 DRAM CONFIGURATION
6256 11:08:53.458035 ===================================
6257 11:08:53.460669 EX_ROW_EN[0] = 0x10
6258 11:08:53.464103 EX_ROW_EN[1] = 0x0
6259 11:08:53.464584 LP4Y_EN = 0x0
6260 11:08:53.467359 WORK_FSP = 0x0
6261 11:08:53.467867 WL = 0x2
6262 11:08:53.470957 RL = 0x2
6263 11:08:53.471518 BL = 0x2
6264 11:08:53.474004 RPST = 0x0
6265 11:08:53.474466 RD_PRE = 0x0
6266 11:08:53.478241 WR_PRE = 0x1
6267 11:08:53.478803 WR_PST = 0x0
6268 11:08:53.480614 DBI_WR = 0x0
6269 11:08:53.481078 DBI_RD = 0x0
6270 11:08:53.483997 OTF = 0x1
6271 11:08:53.487324 ===================================
6272 11:08:53.494542 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6273 11:08:53.496968 nWR fixed to 30
6274 11:08:53.500633 [ModeRegInit_LP4] CH0 RK0
6275 11:08:53.501152 [ModeRegInit_LP4] CH0 RK1
6276 11:08:53.503929 [ModeRegInit_LP4] CH1 RK0
6277 11:08:53.507218 [ModeRegInit_LP4] CH1 RK1
6278 11:08:53.507781 match AC timing 19
6279 11:08:53.513430 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6280 11:08:53.517194 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6281 11:08:53.520646 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6282 11:08:53.526634 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6283 11:08:53.530240 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6284 11:08:53.530767 ==
6285 11:08:53.533465 Dram Type= 6, Freq= 0, CH_0, rank 0
6286 11:08:53.537086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 11:08:53.537515 ==
6288 11:08:53.543066 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6289 11:08:53.549734 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6290 11:08:53.553459 [CA 0] Center 36 (8~64) winsize 57
6291 11:08:53.556489 [CA 1] Center 36 (8~64) winsize 57
6292 11:08:53.559903 [CA 2] Center 36 (8~64) winsize 57
6293 11:08:53.563482 [CA 3] Center 36 (8~64) winsize 57
6294 11:08:53.566326 [CA 4] Center 36 (8~64) winsize 57
6295 11:08:53.569503 [CA 5] Center 36 (8~64) winsize 57
6296 11:08:53.569924
6297 11:08:53.572905 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6298 11:08:53.573433
6299 11:08:53.576319 [CATrainingPosCal] consider 1 rank data
6300 11:08:53.580345 u2DelayCellTimex100 = 270/100 ps
6301 11:08:53.582931 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 11:08:53.586517 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 11:08:53.589286 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 11:08:53.593715 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 11:08:53.596347 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 11:08:53.600104 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 11:08:53.600626
6308 11:08:53.602816 CA PerBit enable=1, Macro0, CA PI delay=36
6309 11:08:53.606178
6310 11:08:53.606697 [CBTSetCACLKResult] CA Dly = 36
6311 11:08:53.609766 CS Dly: 1 (0~32)
6312 11:08:53.610286 ==
6313 11:08:53.612359 Dram Type= 6, Freq= 0, CH_0, rank 1
6314 11:08:53.616023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 11:08:53.616547 ==
6316 11:08:53.622803 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6317 11:08:53.629117 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6318 11:08:53.632472 [CA 0] Center 36 (8~64) winsize 57
6319 11:08:53.635622 [CA 1] Center 36 (8~64) winsize 57
6320 11:08:53.638644 [CA 2] Center 36 (8~64) winsize 57
6321 11:08:53.642285 [CA 3] Center 36 (8~64) winsize 57
6322 11:08:53.645074 [CA 4] Center 36 (8~64) winsize 57
6323 11:08:53.645495 [CA 5] Center 36 (8~64) winsize 57
6324 11:08:53.648829
6325 11:08:53.652544 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6326 11:08:53.653065
6327 11:08:53.655416 [CATrainingPosCal] consider 2 rank data
6328 11:08:53.658820 u2DelayCellTimex100 = 270/100 ps
6329 11:08:53.662109 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 11:08:53.664900 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 11:08:53.668383 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 11:08:53.671381 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 11:08:53.674822 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 11:08:53.677995 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 11:08:53.678416
6336 11:08:53.684549 CA PerBit enable=1, Macro0, CA PI delay=36
6337 11:08:53.684970
6338 11:08:53.685301 [CBTSetCACLKResult] CA Dly = 36
6339 11:08:53.688202 CS Dly: 1 (0~32)
6340 11:08:53.688615
6341 11:08:53.691607 ----->DramcWriteLeveling(PI) begin...
6342 11:08:53.692190 ==
6343 11:08:53.694794 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 11:08:53.697801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 11:08:53.698222 ==
6346 11:08:53.701533 Write leveling (Byte 0): 40 => 8
6347 11:08:53.704778 Write leveling (Byte 1): 32 => 0
6348 11:08:53.708369 DramcWriteLeveling(PI) end<-----
6349 11:08:53.708788
6350 11:08:53.709115 ==
6351 11:08:53.710875 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 11:08:53.714498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 11:08:53.717820 ==
6354 11:08:53.718241 [Gating] SW mode calibration
6355 11:08:53.727708 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6356 11:08:53.731094 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6357 11:08:53.734280 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6358 11:08:53.741239 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6359 11:08:53.743758 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6360 11:08:53.746970 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6361 11:08:53.753724 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6362 11:08:53.757717 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6363 11:08:53.760542 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6364 11:08:53.767062 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6365 11:08:53.770192 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6366 11:08:53.773581 Total UI for P1: 0, mck2ui 16
6367 11:08:53.777290 best dqsien dly found for B0: ( 0, 14, 24)
6368 11:08:53.780194 Total UI for P1: 0, mck2ui 16
6369 11:08:53.783402 best dqsien dly found for B1: ( 0, 14, 24)
6370 11:08:53.786604 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6371 11:08:53.790393 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6372 11:08:53.790925
6373 11:08:53.793609 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6374 11:08:53.799816 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6375 11:08:53.800338 [Gating] SW calibration Done
6376 11:08:53.802924 ==
6377 11:08:53.803342 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 11:08:53.809683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 11:08:53.810227 ==
6380 11:08:53.810563 RX Vref Scan: 0
6381 11:08:53.810876
6382 11:08:53.813054 RX Vref 0 -> 0, step: 1
6383 11:08:53.813566
6384 11:08:53.816657 RX Delay -410 -> 252, step: 16
6385 11:08:53.819834 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6386 11:08:53.823846 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6387 11:08:53.829886 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6388 11:08:53.832781 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6389 11:08:53.836676 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6390 11:08:53.839753 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6391 11:08:53.846186 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6392 11:08:53.848984 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6393 11:08:53.852133 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6394 11:08:53.859357 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6395 11:08:53.862418 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6396 11:08:53.865629 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6397 11:08:53.868534 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6398 11:08:53.875379 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6399 11:08:53.879075 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6400 11:08:53.882111 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6401 11:08:53.882688 ==
6402 11:08:53.885312 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 11:08:53.892151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 11:08:53.892750 ==
6405 11:08:53.893134 DQS Delay:
6406 11:08:53.895892 DQS0 = 43, DQS1 = 59
6407 11:08:53.896361 DQM Delay:
6408 11:08:53.896735 DQM0 = 10, DQM1 = 11
6409 11:08:53.898576 DQ Delay:
6410 11:08:53.901915 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6411 11:08:53.902388 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6412 11:08:53.905365 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6413 11:08:53.908665 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6414 11:08:53.909241
6415 11:08:53.911906
6416 11:08:53.912375 ==
6417 11:08:53.915436 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 11:08:53.919273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 11:08:53.919905 ==
6420 11:08:53.920292
6421 11:08:53.920640
6422 11:08:53.921650 TX Vref Scan disable
6423 11:08:53.922118 == TX Byte 0 ==
6424 11:08:53.924732 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6425 11:08:53.931417 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6426 11:08:53.932039 == TX Byte 1 ==
6427 11:08:53.935049 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6428 11:08:53.941647 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6429 11:08:53.942228 ==
6430 11:08:53.944921 Dram Type= 6, Freq= 0, CH_0, rank 0
6431 11:08:53.948144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 11:08:53.948723 ==
6433 11:08:53.949099
6434 11:08:53.949443
6435 11:08:53.951973 TX Vref Scan disable
6436 11:08:53.952542 == TX Byte 0 ==
6437 11:08:53.958101 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6438 11:08:53.961635 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6439 11:08:53.962111 == TX Byte 1 ==
6440 11:08:53.968138 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6441 11:08:53.971563 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6442 11:08:53.972066
6443 11:08:53.972436 [DATLAT]
6444 11:08:53.974365 Freq=400, CH0 RK0
6445 11:08:53.974828
6446 11:08:53.975194 DATLAT Default: 0xf
6447 11:08:53.977851 0, 0xFFFF, sum = 0
6448 11:08:53.978313 1, 0xFFFF, sum = 0
6449 11:08:53.981616 2, 0xFFFF, sum = 0
6450 11:08:53.982148 3, 0xFFFF, sum = 0
6451 11:08:53.984393 4, 0xFFFF, sum = 0
6452 11:08:53.984826 5, 0xFFFF, sum = 0
6453 11:08:53.987616 6, 0xFFFF, sum = 0
6454 11:08:53.988069 7, 0xFFFF, sum = 0
6455 11:08:53.991430 8, 0xFFFF, sum = 0
6456 11:08:53.992011 9, 0xFFFF, sum = 0
6457 11:08:53.994749 10, 0xFFFF, sum = 0
6458 11:08:53.997575 11, 0xFFFF, sum = 0
6459 11:08:53.998113 12, 0xFFFF, sum = 0
6460 11:08:54.001062 13, 0x0, sum = 1
6461 11:08:54.001490 14, 0x0, sum = 2
6462 11:08:54.004521 15, 0x0, sum = 3
6463 11:08:54.004946 16, 0x0, sum = 4
6464 11:08:54.005286 best_step = 14
6465 11:08:54.005599
6466 11:08:54.007623 ==
6467 11:08:54.011289 Dram Type= 6, Freq= 0, CH_0, rank 0
6468 11:08:54.013930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 11:08:54.014359 ==
6470 11:08:54.014697 RX Vref Scan: 1
6471 11:08:54.015013
6472 11:08:54.017776 RX Vref 0 -> 0, step: 1
6473 11:08:54.018301
6474 11:08:54.021250 RX Delay -359 -> 252, step: 8
6475 11:08:54.021770
6476 11:08:54.024562 Set Vref, RX VrefLevel [Byte0]: 60
6477 11:08:54.027593 [Byte1]: 48
6478 11:08:54.031413
6479 11:08:54.031883 Final RX Vref Byte 0 = 60 to rank0
6480 11:08:54.034374 Final RX Vref Byte 1 = 48 to rank0
6481 11:08:54.038268 Final RX Vref Byte 0 = 60 to rank1
6482 11:08:54.040890 Final RX Vref Byte 1 = 48 to rank1==
6483 11:08:54.044320 Dram Type= 6, Freq= 0, CH_0, rank 0
6484 11:08:54.050968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 11:08:54.051393 ==
6486 11:08:54.051775 DQS Delay:
6487 11:08:54.054689 DQS0 = 48, DQS1 = 60
6488 11:08:54.055107 DQM Delay:
6489 11:08:54.055440 DQM0 = 11, DQM1 = 12
6490 11:08:54.057992 DQ Delay:
6491 11:08:54.060911 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6492 11:08:54.064284 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6493 11:08:54.064737 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6494 11:08:54.067522 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6495 11:08:54.070944
6496 11:08:54.071392
6497 11:08:54.077503 [DQSOSCAuto] RK0, (LSB)MR18= 0xb375, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 387 ps
6498 11:08:54.080712 CH0 RK0: MR19=C0C, MR18=B375
6499 11:08:54.087270 CH0_RK0: MR19=0xC0C, MR18=0xB375, DQSOSC=387, MR23=63, INC=394, DEC=262
6500 11:08:54.087742 ==
6501 11:08:54.090740 Dram Type= 6, Freq= 0, CH_0, rank 1
6502 11:08:54.093735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 11:08:54.094270 ==
6504 11:08:54.097267 [Gating] SW mode calibration
6505 11:08:54.104193 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6506 11:08:54.110237 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6507 11:08:54.113650 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6508 11:08:54.116673 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6509 11:08:54.123619 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6510 11:08:54.126622 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6511 11:08:54.130490 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6512 11:08:54.136388 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6513 11:08:54.140148 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6514 11:08:54.143173 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6515 11:08:54.149977 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6516 11:08:54.153305 Total UI for P1: 0, mck2ui 16
6517 11:08:54.156032 best dqsien dly found for B0: ( 0, 14, 24)
6518 11:08:54.160338 Total UI for P1: 0, mck2ui 16
6519 11:08:54.162629 best dqsien dly found for B1: ( 0, 14, 24)
6520 11:08:54.166036 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6521 11:08:54.169249 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6522 11:08:54.169670
6523 11:08:54.172452 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6524 11:08:54.176075 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6525 11:08:54.179208 [Gating] SW calibration Done
6526 11:08:54.179627 ==
6527 11:08:54.182588 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 11:08:54.185786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 11:08:54.186381 ==
6530 11:08:54.189962 RX Vref Scan: 0
6531 11:08:54.190493
6532 11:08:54.192424 RX Vref 0 -> 0, step: 1
6533 11:08:54.192850
6534 11:08:54.195776 RX Delay -410 -> 252, step: 16
6535 11:08:54.199124 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6536 11:08:54.202227 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6537 11:08:54.205470 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6538 11:08:54.212389 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6539 11:08:54.215440 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6540 11:08:54.219432 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6541 11:08:54.222267 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6542 11:08:54.228439 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6543 11:08:54.232141 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6544 11:08:54.234971 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6545 11:08:54.241613 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6546 11:08:54.244923 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6547 11:08:54.248120 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6548 11:08:54.251384 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6549 11:08:54.257909 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6550 11:08:54.261193 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6551 11:08:54.261633 ==
6552 11:08:54.265291 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 11:08:54.268338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 11:08:54.268776 ==
6555 11:08:54.271082 DQS Delay:
6556 11:08:54.271509 DQS0 = 35, DQS1 = 59
6557 11:08:54.274687 DQM Delay:
6558 11:08:54.275111 DQM0 = 3, DQM1 = 17
6559 11:08:54.275447 DQ Delay:
6560 11:08:54.277948 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6561 11:08:54.280994 DQ4 =0, DQ5 =0, DQ6 =8, DQ7 =8
6562 11:08:54.284619 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6563 11:08:54.287648 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6564 11:08:54.288166
6565 11:08:54.288606
6566 11:08:54.288960 ==
6567 11:08:54.290958 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 11:08:54.294166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 11:08:54.297219 ==
6570 11:08:54.297642
6571 11:08:54.297980
6572 11:08:54.298293 TX Vref Scan disable
6573 11:08:54.300645 == TX Byte 0 ==
6574 11:08:54.304305 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6575 11:08:54.307508 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6576 11:08:54.311173 == TX Byte 1 ==
6577 11:08:54.314628 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6578 11:08:54.317538 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6579 11:08:54.318074 ==
6580 11:08:54.320848 Dram Type= 6, Freq= 0, CH_0, rank 1
6581 11:08:54.327709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 11:08:54.328249 ==
6583 11:08:54.328595
6584 11:08:54.328908
6585 11:08:54.329208 TX Vref Scan disable
6586 11:08:54.330412 == TX Byte 0 ==
6587 11:08:54.333571 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6588 11:08:54.337963 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6589 11:08:54.340152 == TX Byte 1 ==
6590 11:08:54.343262 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6591 11:08:54.347104 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6592 11:08:54.347532
6593 11:08:54.350161 [DATLAT]
6594 11:08:54.350586 Freq=400, CH0 RK1
6595 11:08:54.350925
6596 11:08:54.353669 DATLAT Default: 0xe
6597 11:08:54.354201 0, 0xFFFF, sum = 0
6598 11:08:54.356880 1, 0xFFFF, sum = 0
6599 11:08:54.357312 2, 0xFFFF, sum = 0
6600 11:08:54.360042 3, 0xFFFF, sum = 0
6601 11:08:54.360476 4, 0xFFFF, sum = 0
6602 11:08:54.363780 5, 0xFFFF, sum = 0
6603 11:08:54.364319 6, 0xFFFF, sum = 0
6604 11:08:54.366633 7, 0xFFFF, sum = 0
6605 11:08:54.369618 8, 0xFFFF, sum = 0
6606 11:08:54.370051 9, 0xFFFF, sum = 0
6607 11:08:54.373027 10, 0xFFFF, sum = 0
6608 11:08:54.373459 11, 0xFFFF, sum = 0
6609 11:08:54.376552 12, 0xFFFF, sum = 0
6610 11:08:54.376987 13, 0x0, sum = 1
6611 11:08:54.379843 14, 0x0, sum = 2
6612 11:08:54.380278 15, 0x0, sum = 3
6613 11:08:54.383193 16, 0x0, sum = 4
6614 11:08:54.383626 best_step = 14
6615 11:08:54.384003
6616 11:08:54.384318 ==
6617 11:08:54.386019 Dram Type= 6, Freq= 0, CH_0, rank 1
6618 11:08:54.389621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 11:08:54.392925 ==
6620 11:08:54.393351 RX Vref Scan: 0
6621 11:08:54.393687
6622 11:08:54.396058 RX Vref 0 -> 0, step: 1
6623 11:08:54.396480
6624 11:08:54.399072 RX Delay -359 -> 252, step: 8
6625 11:08:54.406231 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6626 11:08:54.409450 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6627 11:08:54.412631 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6628 11:08:54.415815 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6629 11:08:54.422443 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6630 11:08:54.426025 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6631 11:08:54.429379 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6632 11:08:54.432967 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6633 11:08:54.438913 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6634 11:08:54.442612 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6635 11:08:54.445502 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6636 11:08:54.449410 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6637 11:08:54.455354 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6638 11:08:54.458723 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6639 11:08:54.462224 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6640 11:08:54.468246 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6641 11:08:54.468808 ==
6642 11:08:54.471492 Dram Type= 6, Freq= 0, CH_0, rank 1
6643 11:08:54.475460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 11:08:54.476155 ==
6645 11:08:54.476535 DQS Delay:
6646 11:08:54.478141 DQS0 = 44, DQS1 = 60
6647 11:08:54.478602 DQM Delay:
6648 11:08:54.482330 DQM0 = 7, DQM1 = 15
6649 11:08:54.482933 DQ Delay:
6650 11:08:54.484789 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6651 11:08:54.488080 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6652 11:08:54.491356 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6653 11:08:54.494928 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6654 11:08:54.495525
6655 11:08:54.495963
6656 11:08:54.501188 [DQSOSCAuto] RK1, (LSB)MR18= 0xae3c, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps
6657 11:08:54.504602 CH0 RK1: MR19=C0C, MR18=AE3C
6658 11:08:54.511432 CH0_RK1: MR19=0xC0C, MR18=0xAE3C, DQSOSC=388, MR23=63, INC=392, DEC=261
6659 11:08:54.514507 [RxdqsGatingPostProcess] freq 400
6660 11:08:54.521561 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6661 11:08:54.522132 best DQS0 dly(2T, 0.5T) = (0, 10)
6662 11:08:54.524265 best DQS1 dly(2T, 0.5T) = (0, 10)
6663 11:08:54.527870 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6664 11:08:54.531301 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6665 11:08:54.534293 best DQS0 dly(2T, 0.5T) = (0, 10)
6666 11:08:54.537664 best DQS1 dly(2T, 0.5T) = (0, 10)
6667 11:08:54.541044 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6668 11:08:54.544504 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6669 11:08:54.547555 Pre-setting of DQS Precalculation
6670 11:08:54.554478 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6671 11:08:54.555052 ==
6672 11:08:54.557467 Dram Type= 6, Freq= 0, CH_1, rank 0
6673 11:08:54.560523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 11:08:54.561001 ==
6675 11:08:54.567552 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6676 11:08:54.573550 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6677 11:08:54.576624 [CA 0] Center 36 (8~64) winsize 57
6678 11:08:54.577095 [CA 1] Center 36 (8~64) winsize 57
6679 11:08:54.580266 [CA 2] Center 36 (8~64) winsize 57
6680 11:08:54.583712 [CA 3] Center 36 (8~64) winsize 57
6681 11:08:54.586554 [CA 4] Center 36 (8~64) winsize 57
6682 11:08:54.590727 [CA 5] Center 36 (8~64) winsize 57
6683 11:08:54.591353
6684 11:08:54.593564 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6685 11:08:54.594034
6686 11:08:54.600098 [CATrainingPosCal] consider 1 rank data
6687 11:08:54.600659 u2DelayCellTimex100 = 270/100 ps
6688 11:08:54.606831 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 11:08:54.610094 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 11:08:54.613285 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 11:08:54.616792 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 11:08:54.619805 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 11:08:54.623139 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 11:08:54.623644
6695 11:08:54.627041 CA PerBit enable=1, Macro0, CA PI delay=36
6696 11:08:54.627614
6697 11:08:54.629393 [CBTSetCACLKResult] CA Dly = 36
6698 11:08:54.633081 CS Dly: 1 (0~32)
6699 11:08:54.633547 ==
6700 11:08:54.636412 Dram Type= 6, Freq= 0, CH_1, rank 1
6701 11:08:54.639925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 11:08:54.640496 ==
6703 11:08:54.646166 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6704 11:08:54.649078 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6705 11:08:54.652634 [CA 0] Center 36 (8~64) winsize 57
6706 11:08:54.655963 [CA 1] Center 36 (8~64) winsize 57
6707 11:08:54.659462 [CA 2] Center 36 (8~64) winsize 57
6708 11:08:54.663428 [CA 3] Center 36 (8~64) winsize 57
6709 11:08:54.666413 [CA 4] Center 36 (8~64) winsize 57
6710 11:08:54.669311 [CA 5] Center 36 (8~64) winsize 57
6711 11:08:54.669778
6712 11:08:54.672580 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6713 11:08:54.673044
6714 11:08:54.675515 [CATrainingPosCal] consider 2 rank data
6715 11:08:54.678963 u2DelayCellTimex100 = 270/100 ps
6716 11:08:54.682022 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 11:08:54.689265 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 11:08:54.692516 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 11:08:54.695633 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 11:08:54.698772 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 11:08:54.702145 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 11:08:54.702705
6723 11:08:54.705519 CA PerBit enable=1, Macro0, CA PI delay=36
6724 11:08:54.705987
6725 11:08:54.708654 [CBTSetCACLKResult] CA Dly = 36
6726 11:08:54.711548 CS Dly: 1 (0~32)
6727 11:08:54.712059
6728 11:08:54.715717 ----->DramcWriteLeveling(PI) begin...
6729 11:08:54.716299 ==
6730 11:08:54.718478 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 11:08:54.722073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 11:08:54.722642 ==
6733 11:08:54.725200 Write leveling (Byte 0): 40 => 8
6734 11:08:54.728708 Write leveling (Byte 1): 32 => 0
6735 11:08:54.732123 DramcWriteLeveling(PI) end<-----
6736 11:08:54.732686
6737 11:08:54.733057 ==
6738 11:08:54.735180 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 11:08:54.738378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 11:08:54.738855 ==
6741 11:08:54.741596 [Gating] SW mode calibration
6742 11:08:54.748498 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6743 11:08:54.755018 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6744 11:08:54.758430 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6745 11:08:54.761346 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6746 11:08:54.767961 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6747 11:08:54.771903 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6748 11:08:54.774562 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6749 11:08:54.781450 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6750 11:08:54.784751 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6751 11:08:54.787993 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6752 11:08:54.794696 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6753 11:08:54.797890 Total UI for P1: 0, mck2ui 16
6754 11:08:54.801133 best dqsien dly found for B0: ( 0, 14, 24)
6755 11:08:54.804159 Total UI for P1: 0, mck2ui 16
6756 11:08:54.807488 best dqsien dly found for B1: ( 0, 14, 24)
6757 11:08:54.810928 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6758 11:08:54.814241 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6759 11:08:54.814977
6760 11:08:54.817959 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6761 11:08:54.820619 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6762 11:08:54.824030 [Gating] SW calibration Done
6763 11:08:54.824605 ==
6764 11:08:54.827781 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 11:08:54.830357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 11:08:54.830837 ==
6767 11:08:54.834537 RX Vref Scan: 0
6768 11:08:54.835112
6769 11:08:54.836884 RX Vref 0 -> 0, step: 1
6770 11:08:54.837355
6771 11:08:54.837729 RX Delay -410 -> 252, step: 16
6772 11:08:54.843419 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6773 11:08:54.847012 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6774 11:08:54.850254 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6775 11:08:54.856850 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6776 11:08:54.860604 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6777 11:08:54.863573 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6778 11:08:54.867485 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6779 11:08:54.873368 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6780 11:08:54.877129 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6781 11:08:54.880369 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6782 11:08:54.883727 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6783 11:08:54.890144 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6784 11:08:54.893114 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6785 11:08:54.897003 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6786 11:08:54.900086 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6787 11:08:54.907511 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6788 11:08:54.908135 ==
6789 11:08:54.910446 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 11:08:54.913267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 11:08:54.913846 ==
6792 11:08:54.914224 DQS Delay:
6793 11:08:54.916863 DQS0 = 43, DQS1 = 51
6794 11:08:54.917434 DQM Delay:
6795 11:08:54.920284 DQM0 = 12, DQM1 = 14
6796 11:08:54.920752 DQ Delay:
6797 11:08:54.923536 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6798 11:08:54.926619 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6799 11:08:54.929556 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6800 11:08:54.933211 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6801 11:08:54.933787
6802 11:08:54.934158
6803 11:08:54.934502 ==
6804 11:08:54.936129 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 11:08:54.939474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 11:08:54.940000 ==
6807 11:08:54.940397
6808 11:08:54.942879
6809 11:08:54.943344 TX Vref Scan disable
6810 11:08:54.946568 == TX Byte 0 ==
6811 11:08:54.949044 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6812 11:08:54.952654 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6813 11:08:54.956416 == TX Byte 1 ==
6814 11:08:54.959296 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6815 11:08:54.963019 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6816 11:08:54.963485 ==
6817 11:08:54.966162 Dram Type= 6, Freq= 0, CH_1, rank 0
6818 11:08:54.969713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 11:08:54.972871 ==
6820 11:08:54.973347
6821 11:08:54.973722
6822 11:08:54.974067 TX Vref Scan disable
6823 11:08:54.975756 == TX Byte 0 ==
6824 11:08:54.979088 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6825 11:08:54.982543 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6826 11:08:54.985593 == TX Byte 1 ==
6827 11:08:54.989207 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6828 11:08:54.992296 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6829 11:08:54.992768
6830 11:08:54.995967 [DATLAT]
6831 11:08:54.996435 Freq=400, CH1 RK0
6832 11:08:54.996809
6833 11:08:54.998953 DATLAT Default: 0xf
6834 11:08:54.999423 0, 0xFFFF, sum = 0
6835 11:08:55.002539 1, 0xFFFF, sum = 0
6836 11:08:55.003119 2, 0xFFFF, sum = 0
6837 11:08:55.005233 3, 0xFFFF, sum = 0
6838 11:08:55.005709 4, 0xFFFF, sum = 0
6839 11:08:55.009194 5, 0xFFFF, sum = 0
6840 11:08:55.009668 6, 0xFFFF, sum = 0
6841 11:08:55.012242 7, 0xFFFF, sum = 0
6842 11:08:55.012720 8, 0xFFFF, sum = 0
6843 11:08:55.016058 9, 0xFFFF, sum = 0
6844 11:08:55.018638 10, 0xFFFF, sum = 0
6845 11:08:55.019220 11, 0xFFFF, sum = 0
6846 11:08:55.021999 12, 0xFFFF, sum = 0
6847 11:08:55.022580 13, 0x0, sum = 1
6848 11:08:55.025841 14, 0x0, sum = 2
6849 11:08:55.026421 15, 0x0, sum = 3
6850 11:08:55.028601 16, 0x0, sum = 4
6851 11:08:55.029079 best_step = 14
6852 11:08:55.029457
6853 11:08:55.029800 ==
6854 11:08:55.031741 Dram Type= 6, Freq= 0, CH_1, rank 0
6855 11:08:55.035059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 11:08:55.035632 ==
6857 11:08:55.038567 RX Vref Scan: 1
6858 11:08:55.039040
6859 11:08:55.042273 RX Vref 0 -> 0, step: 1
6860 11:08:55.042850
6861 11:08:55.043230 RX Delay -343 -> 252, step: 8
6862 11:08:55.043584
6863 11:08:55.044995 Set Vref, RX VrefLevel [Byte0]: 53
6864 11:08:55.048196 [Byte1]: 59
6865 11:08:55.053596
6866 11:08:55.054170 Final RX Vref Byte 0 = 53 to rank0
6867 11:08:55.056969 Final RX Vref Byte 1 = 59 to rank0
6868 11:08:55.060234 Final RX Vref Byte 0 = 53 to rank1
6869 11:08:55.063257 Final RX Vref Byte 1 = 59 to rank1==
6870 11:08:55.066909 Dram Type= 6, Freq= 0, CH_1, rank 0
6871 11:08:55.073735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 11:08:55.074228 ==
6873 11:08:55.074602 DQS Delay:
6874 11:08:55.076548 DQS0 = 44, DQS1 = 56
6875 11:08:55.077016 DQM Delay:
6876 11:08:55.077391 DQM0 = 8, DQM1 = 12
6877 11:08:55.079856 DQ Delay:
6878 11:08:55.083906 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6879 11:08:55.086559 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =0
6880 11:08:55.087022 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6881 11:08:55.090028 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24
6882 11:08:55.093843
6883 11:08:55.094412
6884 11:08:55.100094 [DQSOSCAuto] RK0, (LSB)MR18= 0x8f67, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6885 11:08:55.103418 CH1 RK0: MR19=C0C, MR18=8F67
6886 11:08:55.110032 CH1_RK0: MR19=0xC0C, MR18=0x8F67, DQSOSC=391, MR23=63, INC=386, DEC=257
6887 11:08:55.110595 ==
6888 11:08:55.113288 Dram Type= 6, Freq= 0, CH_1, rank 1
6889 11:08:55.116261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 11:08:55.116822 ==
6891 11:08:55.119826 [Gating] SW mode calibration
6892 11:08:55.126804 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6893 11:08:55.132866 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6894 11:08:55.135824 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6895 11:08:55.139529 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6896 11:08:55.145780 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6897 11:08:55.149351 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6898 11:08:55.152569 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6899 11:08:55.158943 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6900 11:08:55.162362 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6901 11:08:55.165474 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6902 11:08:55.172165 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6903 11:08:55.172595 Total UI for P1: 0, mck2ui 16
6904 11:08:55.178461 best dqsien dly found for B0: ( 0, 14, 24)
6905 11:08:55.178890 Total UI for P1: 0, mck2ui 16
6906 11:08:55.185517 best dqsien dly found for B1: ( 0, 14, 24)
6907 11:08:55.188722 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6908 11:08:55.191777 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6909 11:08:55.192279
6910 11:08:55.195969 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6911 11:08:55.198467 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6912 11:08:55.202267 [Gating] SW calibration Done
6913 11:08:55.202693 ==
6914 11:08:55.204902 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 11:08:55.208422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 11:08:55.208854 ==
6917 11:08:55.212676 RX Vref Scan: 0
6918 11:08:55.213223
6919 11:08:55.215323 RX Vref 0 -> 0, step: 1
6920 11:08:55.215938
6921 11:08:55.216294 RX Delay -410 -> 252, step: 16
6922 11:08:55.221778 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6923 11:08:55.225512 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6924 11:08:55.228657 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6925 11:08:55.231563 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6926 11:08:55.238199 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6927 11:08:55.241348 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6928 11:08:55.244709 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6929 11:08:55.251645 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6930 11:08:55.255452 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6931 11:08:55.258614 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6932 11:08:55.261360 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6933 11:08:55.267622 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6934 11:08:55.271122 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6935 11:08:55.274465 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6936 11:08:55.278181 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6937 11:08:55.284441 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6938 11:08:55.285060 ==
6939 11:08:55.287425 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 11:08:55.290905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 11:08:55.291378 ==
6942 11:08:55.294386 DQS Delay:
6943 11:08:55.294965 DQS0 = 43, DQS1 = 59
6944 11:08:55.295340 DQM Delay:
6945 11:08:55.297532 DQM0 = 12, DQM1 = 22
6946 11:08:55.298118 DQ Delay:
6947 11:08:55.300706 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6948 11:08:55.304302 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6949 11:08:55.307442 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6950 11:08:55.310643 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6951 11:08:55.311211
6952 11:08:55.311581
6953 11:08:55.311969 ==
6954 11:08:55.313821 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 11:08:55.318677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 11:08:55.320391 ==
6957 11:08:55.320861
6958 11:08:55.321237
6959 11:08:55.321583 TX Vref Scan disable
6960 11:08:55.324051 == TX Byte 0 ==
6961 11:08:55.327796 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6962 11:08:55.330844 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6963 11:08:55.333696 == TX Byte 1 ==
6964 11:08:55.336939 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6965 11:08:55.340510 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6966 11:08:55.341095 ==
6967 11:08:55.343526 Dram Type= 6, Freq= 0, CH_1, rank 1
6968 11:08:55.349846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6969 11:08:55.350413 ==
6970 11:08:55.350788
6971 11:08:55.351132
6972 11:08:55.351459 TX Vref Scan disable
6973 11:08:55.353801 == TX Byte 0 ==
6974 11:08:55.356923 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6975 11:08:55.360068 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6976 11:08:55.363600 == TX Byte 1 ==
6977 11:08:55.366223 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6978 11:08:55.369586 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6979 11:08:55.370187
6980 11:08:55.373587 [DATLAT]
6981 11:08:55.374286 Freq=400, CH1 RK1
6982 11:08:55.374692
6983 11:08:55.376277 DATLAT Default: 0xe
6984 11:08:55.376750 0, 0xFFFF, sum = 0
6985 11:08:55.379847 1, 0xFFFF, sum = 0
6986 11:08:55.380324 2, 0xFFFF, sum = 0
6987 11:08:55.382805 3, 0xFFFF, sum = 0
6988 11:08:55.383278 4, 0xFFFF, sum = 0
6989 11:08:55.386917 5, 0xFFFF, sum = 0
6990 11:08:55.387499 6, 0xFFFF, sum = 0
6991 11:08:55.389373 7, 0xFFFF, sum = 0
6992 11:08:55.392875 8, 0xFFFF, sum = 0
6993 11:08:55.393420 9, 0xFFFF, sum = 0
6994 11:08:55.396213 10, 0xFFFF, sum = 0
6995 11:08:55.396691 11, 0xFFFF, sum = 0
6996 11:08:55.399335 12, 0xFFFF, sum = 0
6997 11:08:55.399898 13, 0x0, sum = 1
6998 11:08:55.402881 14, 0x0, sum = 2
6999 11:08:55.403542 15, 0x0, sum = 3
7000 11:08:55.405824 16, 0x0, sum = 4
7001 11:08:55.406331 best_step = 14
7002 11:08:55.406708
7003 11:08:55.407057 ==
7004 11:08:55.409026 Dram Type= 6, Freq= 0, CH_1, rank 1
7005 11:08:55.412089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7006 11:08:55.415654 ==
7007 11:08:55.416258 RX Vref Scan: 0
7008 11:08:55.416634
7009 11:08:55.419143 RX Vref 0 -> 0, step: 1
7010 11:08:55.419925
7011 11:08:55.422192 RX Delay -359 -> 252, step: 8
7012 11:08:55.428610 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7013 11:08:55.432347 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7014 11:08:55.435371 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7015 11:08:55.438571 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7016 11:08:55.445231 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7017 11:08:55.449238 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7018 11:08:55.451720 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7019 11:08:55.454890 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7020 11:08:55.462691 iDelay=225, Bit 8, Center -60 (-311 ~ 192) 504
7021 11:08:55.465307 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7022 11:08:55.468196 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7023 11:08:55.471736 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
7024 11:08:55.478700 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7025 11:08:55.481562 iDelay=225, Bit 13, Center -36 (-287 ~ 216) 504
7026 11:08:55.485424 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7027 11:08:55.487982 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7028 11:08:55.491289 ==
7029 11:08:55.495090 Dram Type= 6, Freq= 0, CH_1, rank 1
7030 11:08:55.498232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7031 11:08:55.498821 ==
7032 11:08:55.499195 DQS Delay:
7033 11:08:55.501440 DQS0 = 44, DQS1 = 60
7034 11:08:55.501904 DQM Delay:
7035 11:08:55.505174 DQM0 = 9, DQM1 = 14
7036 11:08:55.505639 DQ Delay:
7037 11:08:55.508471 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
7038 11:08:55.511474 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
7039 11:08:55.514848 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
7040 11:08:55.518127 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =24
7041 11:08:55.518696
7042 11:08:55.519066
7043 11:08:55.524607 [DQSOSCAuto] RK1, (LSB)MR18= 0x5948, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
7044 11:08:55.527545 CH1 RK1: MR19=C0C, MR18=5948
7045 11:08:55.535163 CH1_RK1: MR19=0xC0C, MR18=0x5948, DQSOSC=398, MR23=63, INC=372, DEC=248
7046 11:08:55.537505 [RxdqsGatingPostProcess] freq 400
7047 11:08:55.544683 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7048 11:08:55.545255 best DQS0 dly(2T, 0.5T) = (0, 10)
7049 11:08:55.547359 best DQS1 dly(2T, 0.5T) = (0, 10)
7050 11:08:55.550993 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7051 11:08:55.554696 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7052 11:08:55.557517 best DQS0 dly(2T, 0.5T) = (0, 10)
7053 11:08:55.560949 best DQS1 dly(2T, 0.5T) = (0, 10)
7054 11:08:55.564471 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7055 11:08:55.567820 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7056 11:08:55.570888 Pre-setting of DQS Precalculation
7057 11:08:55.577378 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7058 11:08:55.583798 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7059 11:08:55.590657 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7060 11:08:55.591242
7061 11:08:55.591618
7062 11:08:55.593363 [Calibration Summary] 800 Mbps
7063 11:08:55.593825 CH 0, Rank 0
7064 11:08:55.596772 SW Impedance : PASS
7065 11:08:55.600085 DUTY Scan : NO K
7066 11:08:55.600551 ZQ Calibration : PASS
7067 11:08:55.603511 Jitter Meter : NO K
7068 11:08:55.607175 CBT Training : PASS
7069 11:08:55.607804 Write leveling : PASS
7070 11:08:55.610299 RX DQS gating : PASS
7071 11:08:55.610866 RX DQ/DQS(RDDQC) : PASS
7072 11:08:55.614129 TX DQ/DQS : PASS
7073 11:08:55.616504 RX DATLAT : PASS
7074 11:08:55.616971 RX DQ/DQS(Engine): PASS
7075 11:08:55.620409 TX OE : NO K
7076 11:08:55.620990 All Pass.
7077 11:08:55.621361
7078 11:08:55.624021 CH 0, Rank 1
7079 11:08:55.624590 SW Impedance : PASS
7080 11:08:55.626927 DUTY Scan : NO K
7081 11:08:55.630306 ZQ Calibration : PASS
7082 11:08:55.630905 Jitter Meter : NO K
7083 11:08:55.633322 CBT Training : PASS
7084 11:08:55.636902 Write leveling : NO K
7085 11:08:55.637476 RX DQS gating : PASS
7086 11:08:55.639557 RX DQ/DQS(RDDQC) : PASS
7087 11:08:55.643112 TX DQ/DQS : PASS
7088 11:08:55.643577 RX DATLAT : PASS
7089 11:08:55.646576 RX DQ/DQS(Engine): PASS
7090 11:08:55.649495 TX OE : NO K
7091 11:08:55.649996 All Pass.
7092 11:08:55.650377
7093 11:08:55.650718 CH 1, Rank 0
7094 11:08:55.653130 SW Impedance : PASS
7095 11:08:55.656214 DUTY Scan : NO K
7096 11:08:55.656682 ZQ Calibration : PASS
7097 11:08:55.659298 Jitter Meter : NO K
7098 11:08:55.662800 CBT Training : PASS
7099 11:08:55.663265 Write leveling : PASS
7100 11:08:55.666069 RX DQS gating : PASS
7101 11:08:55.669242 RX DQ/DQS(RDDQC) : PASS
7102 11:08:55.669710 TX DQ/DQS : PASS
7103 11:08:55.673563 RX DATLAT : PASS
7104 11:08:55.675744 RX DQ/DQS(Engine): PASS
7105 11:08:55.676225 TX OE : NO K
7106 11:08:55.679340 All Pass.
7107 11:08:55.679959
7108 11:08:55.680334 CH 1, Rank 1
7109 11:08:55.682878 SW Impedance : PASS
7110 11:08:55.683341 DUTY Scan : NO K
7111 11:08:55.686124 ZQ Calibration : PASS
7112 11:08:55.689120 Jitter Meter : NO K
7113 11:08:55.689583 CBT Training : PASS
7114 11:08:55.692528 Write leveling : NO K
7115 11:08:55.695423 RX DQS gating : PASS
7116 11:08:55.695936 RX DQ/DQS(RDDQC) : PASS
7117 11:08:55.699181 TX DQ/DQS : PASS
7118 11:08:55.699801 RX DATLAT : PASS
7119 11:08:55.702315 RX DQ/DQS(Engine): PASS
7120 11:08:55.705689 TX OE : NO K
7121 11:08:55.706158 All Pass.
7122 11:08:55.706526
7123 11:08:55.709255 DramC Write-DBI off
7124 11:08:55.709831 PER_BANK_REFRESH: Hybrid Mode
7125 11:08:55.712578 TX_TRACKING: ON
7126 11:08:55.722638 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7127 11:08:55.725634 [FAST_K] Save calibration result to emmc
7128 11:08:55.729619 dramc_set_vcore_voltage set vcore to 725000
7129 11:08:55.732333 Read voltage for 1600, 0
7130 11:08:55.732903 Vio18 = 0
7131 11:08:55.733275 Vcore = 725000
7132 11:08:55.735731 Vdram = 0
7133 11:08:55.736301 Vddq = 0
7134 11:08:55.736675 Vmddr = 0
7135 11:08:55.741906 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7136 11:08:55.745735 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7137 11:08:55.748455 MEM_TYPE=3, freq_sel=13
7138 11:08:55.752084 sv_algorithm_assistance_LP4_3733
7139 11:08:55.755509 ============ PULL DRAM RESETB DOWN ============
7140 11:08:55.758467 ========== PULL DRAM RESETB DOWN end =========
7141 11:08:55.765136 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7142 11:08:55.768179 ===================================
7143 11:08:55.771907 LPDDR4 DRAM CONFIGURATION
7144 11:08:55.772612 ===================================
7145 11:08:55.774794 EX_ROW_EN[0] = 0x0
7146 11:08:55.777746 EX_ROW_EN[1] = 0x0
7147 11:08:55.778210 LP4Y_EN = 0x0
7148 11:08:55.781174 WORK_FSP = 0x1
7149 11:08:55.781640 WL = 0x5
7150 11:08:55.784732 RL = 0x5
7151 11:08:55.785196 BL = 0x2
7152 11:08:55.788330 RPST = 0x0
7153 11:08:55.788845 RD_PRE = 0x0
7154 11:08:55.791431 WR_PRE = 0x1
7155 11:08:55.791933 WR_PST = 0x1
7156 11:08:55.794795 DBI_WR = 0x0
7157 11:08:55.795361 DBI_RD = 0x0
7158 11:08:55.798273 OTF = 0x1
7159 11:08:55.801190 ===================================
7160 11:08:55.804057 ===================================
7161 11:08:55.804529 ANA top config
7162 11:08:55.808037 ===================================
7163 11:08:55.810996 DLL_ASYNC_EN = 0
7164 11:08:55.814598 ALL_SLAVE_EN = 0
7165 11:08:55.817816 NEW_RANK_MODE = 1
7166 11:08:55.820492 DLL_IDLE_MODE = 1
7167 11:08:55.820960 LP45_APHY_COMB_EN = 1
7168 11:08:55.824017 TX_ODT_DIS = 0
7169 11:08:55.827611 NEW_8X_MODE = 1
7170 11:08:55.830979 ===================================
7171 11:08:55.833938 ===================================
7172 11:08:55.837660 data_rate = 3200
7173 11:08:55.840757 CKR = 1
7174 11:08:55.841223 DQ_P2S_RATIO = 8
7175 11:08:55.844350 ===================================
7176 11:08:55.847712 CA_P2S_RATIO = 8
7177 11:08:55.850699 DQ_CA_OPEN = 0
7178 11:08:55.854316 DQ_SEMI_OPEN = 0
7179 11:08:55.857330 CA_SEMI_OPEN = 0
7180 11:08:55.860349 CA_FULL_RATE = 0
7181 11:08:55.863801 DQ_CKDIV4_EN = 0
7182 11:08:55.864366 CA_CKDIV4_EN = 0
7183 11:08:55.866962 CA_PREDIV_EN = 0
7184 11:08:55.870084 PH8_DLY = 12
7185 11:08:55.873640 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7186 11:08:55.876774 DQ_AAMCK_DIV = 4
7187 11:08:55.880293 CA_AAMCK_DIV = 4
7188 11:08:55.880898 CA_ADMCK_DIV = 4
7189 11:08:55.883394 DQ_TRACK_CA_EN = 0
7190 11:08:55.886729 CA_PICK = 1600
7191 11:08:55.889852 CA_MCKIO = 1600
7192 11:08:55.893186 MCKIO_SEMI = 0
7193 11:08:55.896692 PLL_FREQ = 3068
7194 11:08:55.899775 DQ_UI_PI_RATIO = 32
7195 11:08:55.903208 CA_UI_PI_RATIO = 0
7196 11:08:55.906474 ===================================
7197 11:08:55.909624 ===================================
7198 11:08:55.910198 memory_type:LPDDR4
7199 11:08:55.912838 GP_NUM : 10
7200 11:08:55.916168 SRAM_EN : 1
7201 11:08:55.916639 MD32_EN : 0
7202 11:08:55.919519 ===================================
7203 11:08:55.922587 [ANA_INIT] >>>>>>>>>>>>>>
7204 11:08:55.925834 <<<<<< [CONFIGURE PHASE]: ANA_TX
7205 11:08:55.929796 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7206 11:08:55.932487 ===================================
7207 11:08:55.935976 data_rate = 3200,PCW = 0X7600
7208 11:08:55.939834 ===================================
7209 11:08:55.942086 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7210 11:08:55.945661 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7211 11:08:55.952557 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7212 11:08:55.955232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7213 11:08:55.962462 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7214 11:08:55.965654 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7215 11:08:55.966225 [ANA_INIT] flow start
7216 11:08:55.969171 [ANA_INIT] PLL >>>>>>>>
7217 11:08:55.971716 [ANA_INIT] PLL <<<<<<<<
7218 11:08:55.972216 [ANA_INIT] MIDPI >>>>>>>>
7219 11:08:55.975559 [ANA_INIT] MIDPI <<<<<<<<
7220 11:08:55.978526 [ANA_INIT] DLL >>>>>>>>
7221 11:08:55.979071 [ANA_INIT] DLL <<<<<<<<
7222 11:08:55.981617 [ANA_INIT] flow end
7223 11:08:55.985091 ============ LP4 DIFF to SE enter ============
7224 11:08:55.991402 ============ LP4 DIFF to SE exit ============
7225 11:08:55.992031 [ANA_INIT] <<<<<<<<<<<<<
7226 11:08:55.994876 [Flow] Enable top DCM control >>>>>
7227 11:08:55.998091 [Flow] Enable top DCM control <<<<<
7228 11:08:56.001961 Enable DLL master slave shuffle
7229 11:08:56.008007 ==============================================================
7230 11:08:56.008587 Gating Mode config
7231 11:08:56.014626 ==============================================================
7232 11:08:56.017569 Config description:
7233 11:08:56.027467 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7234 11:08:56.034062 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7235 11:08:56.037333 SELPH_MODE 0: By rank 1: By Phase
7236 11:08:56.044077 ==============================================================
7237 11:08:56.047305 GAT_TRACK_EN = 1
7238 11:08:56.050474 RX_GATING_MODE = 2
7239 11:08:56.054020 RX_GATING_TRACK_MODE = 2
7240 11:08:56.054592 SELPH_MODE = 1
7241 11:08:56.056738 PICG_EARLY_EN = 1
7242 11:08:56.060876 VALID_LAT_VALUE = 1
7243 11:08:56.066947 ==============================================================
7244 11:08:56.070730 Enter into Gating configuration >>>>
7245 11:08:56.073132 Exit from Gating configuration <<<<
7246 11:08:56.076843 Enter into DVFS_PRE_config >>>>>
7247 11:08:56.086497 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7248 11:08:56.089666 Exit from DVFS_PRE_config <<<<<
7249 11:08:56.093050 Enter into PICG configuration >>>>
7250 11:08:56.096399 Exit from PICG configuration <<<<
7251 11:08:56.099537 [RX_INPUT] configuration >>>>>
7252 11:08:56.103192 [RX_INPUT] configuration <<<<<
7253 11:08:56.105998 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7254 11:08:56.112721 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7255 11:08:56.119736 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7256 11:08:56.126493 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7257 11:08:56.132785 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7258 11:08:56.139712 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7259 11:08:56.142544 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7260 11:08:56.145716 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7261 11:08:56.149311 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7262 11:08:56.156253 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7263 11:08:56.159816 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7264 11:08:56.162722 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7265 11:08:56.165642 ===================================
7266 11:08:56.169285 LPDDR4 DRAM CONFIGURATION
7267 11:08:56.172441 ===================================
7268 11:08:56.172913 EX_ROW_EN[0] = 0x0
7269 11:08:56.175518 EX_ROW_EN[1] = 0x0
7270 11:08:56.176020 LP4Y_EN = 0x0
7271 11:08:56.178823 WORK_FSP = 0x1
7272 11:08:56.181985 WL = 0x5
7273 11:08:56.182450 RL = 0x5
7274 11:08:56.185676 BL = 0x2
7275 11:08:56.186241 RPST = 0x0
7276 11:08:56.188886 RD_PRE = 0x0
7277 11:08:56.189352 WR_PRE = 0x1
7278 11:08:56.192003 WR_PST = 0x1
7279 11:08:56.192503 DBI_WR = 0x0
7280 11:08:56.195389 DBI_RD = 0x0
7281 11:08:56.195992 OTF = 0x1
7282 11:08:56.198547 ===================================
7283 11:08:56.202430 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7284 11:08:56.208535 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7285 11:08:56.211916 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7286 11:08:56.215561 ===================================
7287 11:08:56.218290 LPDDR4 DRAM CONFIGURATION
7288 11:08:56.221431 ===================================
7289 11:08:56.222196 EX_ROW_EN[0] = 0x10
7290 11:08:56.224836 EX_ROW_EN[1] = 0x0
7291 11:08:56.228023 LP4Y_EN = 0x0
7292 11:08:56.228790 WORK_FSP = 0x1
7293 11:08:56.231457 WL = 0x5
7294 11:08:56.232159 RL = 0x5
7295 11:08:56.234759 BL = 0x2
7296 11:08:56.235273 RPST = 0x0
7297 11:08:56.237977 RD_PRE = 0x0
7298 11:08:56.238402 WR_PRE = 0x1
7299 11:08:56.241091 WR_PST = 0x1
7300 11:08:56.241772 DBI_WR = 0x0
7301 11:08:56.244253 DBI_RD = 0x0
7302 11:08:56.244640 OTF = 0x1
7303 11:08:56.247904 ===================================
7304 11:08:56.254718 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7305 11:08:56.255258 ==
7306 11:08:56.257653 Dram Type= 6, Freq= 0, CH_0, rank 0
7307 11:08:56.264160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7308 11:08:56.264588 ==
7309 11:08:56.264925 [Duty_Offset_Calibration]
7310 11:08:56.267573 B0:1 B1:-1 CA:0
7311 11:08:56.268048
7312 11:08:56.271012 [DutyScan_Calibration_Flow] k_type=0
7313 11:08:56.280377
7314 11:08:56.280911 ==CLK 0==
7315 11:08:56.283411 Final CLK duty delay cell = 0
7316 11:08:56.286499 [0] MAX Duty = 5124%(X100), DQS PI = 22
7317 11:08:56.289736 [0] MIN Duty = 4907%(X100), DQS PI = 6
7318 11:08:56.290164 [0] AVG Duty = 5015%(X100)
7319 11:08:56.293354
7320 11:08:56.296602 CH0 CLK Duty spec in!! Max-Min= 217%
7321 11:08:56.299927 [DutyScan_Calibration_Flow] ====Done====
7322 11:08:56.300354
7323 11:08:56.303749 [DutyScan_Calibration_Flow] k_type=1
7324 11:08:56.319740
7325 11:08:56.320318 ==DQS 0 ==
7326 11:08:56.322485 Final DQS duty delay cell = -4
7327 11:08:56.325980 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7328 11:08:56.329351 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7329 11:08:56.332291 [-4] AVG Duty = 4906%(X100)
7330 11:08:56.332758
7331 11:08:56.333127 ==DQS 1 ==
7332 11:08:56.335790 Final DQS duty delay cell = 0
7333 11:08:56.338575 [0] MAX Duty = 5156%(X100), DQS PI = 0
7334 11:08:56.342428 [0] MIN Duty = 5031%(X100), DQS PI = 18
7335 11:08:56.345303 [0] AVG Duty = 5093%(X100)
7336 11:08:56.345768
7337 11:08:56.348528 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7338 11:08:56.348992
7339 11:08:56.351966 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7340 11:08:56.355330 [DutyScan_Calibration_Flow] ====Done====
7341 11:08:56.355844
7342 11:08:56.358692 [DutyScan_Calibration_Flow] k_type=3
7343 11:08:56.376500
7344 11:08:56.376919 ==DQM 0 ==
7345 11:08:56.379893 Final DQM duty delay cell = 0
7346 11:08:56.383534 [0] MAX Duty = 5124%(X100), DQS PI = 20
7347 11:08:56.386672 [0] MIN Duty = 4907%(X100), DQS PI = 10
7348 11:08:56.389643 [0] AVG Duty = 5015%(X100)
7349 11:08:56.390106
7350 11:08:56.390539 ==DQM 1 ==
7351 11:08:56.393663 Final DQM duty delay cell = 0
7352 11:08:56.396368 [0] MAX Duty = 5000%(X100), DQS PI = 4
7353 11:08:56.400126 [0] MIN Duty = 4813%(X100), DQS PI = 20
7354 11:08:56.403383 [0] AVG Duty = 4906%(X100)
7355 11:08:56.403896
7356 11:08:56.406658 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7357 11:08:56.407124
7358 11:08:56.410077 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7359 11:08:56.412984 [DutyScan_Calibration_Flow] ====Done====
7360 11:08:56.413549
7361 11:08:56.416453 [DutyScan_Calibration_Flow] k_type=2
7362 11:08:56.433005
7363 11:08:56.433574 ==DQ 0 ==
7364 11:08:56.436401 Final DQ duty delay cell = -4
7365 11:08:56.439844 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7366 11:08:56.443646 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7367 11:08:56.446091 [-4] AVG Duty = 4953%(X100)
7368 11:08:56.446560
7369 11:08:56.446926 ==DQ 1 ==
7370 11:08:56.449379 Final DQ duty delay cell = 0
7371 11:08:56.452846 [0] MAX Duty = 5125%(X100), DQS PI = 2
7372 11:08:56.456241 [0] MIN Duty = 5000%(X100), DQS PI = 36
7373 11:08:56.459769 [0] AVG Duty = 5062%(X100)
7374 11:08:56.460342
7375 11:08:56.462658 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7376 11:08:56.463122
7377 11:08:56.465960 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7378 11:08:56.469741 [DutyScan_Calibration_Flow] ====Done====
7379 11:08:56.470343 ==
7380 11:08:56.472261 Dram Type= 6, Freq= 0, CH_1, rank 0
7381 11:08:56.475829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7382 11:08:56.476439 ==
7383 11:08:56.479120 [Duty_Offset_Calibration]
7384 11:08:56.479745 B0:-1 B1:1 CA:2
7385 11:08:56.482631
7386 11:08:56.485425 [DutyScan_Calibration_Flow] k_type=0
7387 11:08:56.493848
7388 11:08:56.494406 ==CLK 0==
7389 11:08:56.497257 Final CLK duty delay cell = 0
7390 11:08:56.500610 [0] MAX Duty = 5187%(X100), DQS PI = 22
7391 11:08:56.503369 [0] MIN Duty = 4969%(X100), DQS PI = 62
7392 11:08:56.503874 [0] AVG Duty = 5078%(X100)
7393 11:08:56.507221
7394 11:08:56.510366 CH1 CLK Duty spec in!! Max-Min= 218%
7395 11:08:56.513574 [DutyScan_Calibration_Flow] ====Done====
7396 11:08:56.514131
7397 11:08:56.516878 [DutyScan_Calibration_Flow] k_type=1
7398 11:08:56.533661
7399 11:08:56.534217 ==DQS 0 ==
7400 11:08:56.536856 Final DQS duty delay cell = 0
7401 11:08:56.539706 [0] MAX Duty = 5124%(X100), DQS PI = 18
7402 11:08:56.543047 [0] MIN Duty = 4907%(X100), DQS PI = 10
7403 11:08:56.546399 [0] AVG Duty = 5015%(X100)
7404 11:08:56.546860
7405 11:08:56.547224 ==DQS 1 ==
7406 11:08:56.549700 Final DQS duty delay cell = 0
7407 11:08:56.553309 [0] MAX Duty = 5093%(X100), DQS PI = 22
7408 11:08:56.556652 [0] MIN Duty = 4969%(X100), DQS PI = 56
7409 11:08:56.560287 [0] AVG Duty = 5031%(X100)
7410 11:08:56.560848
7411 11:08:56.563529 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7412 11:08:56.564141
7413 11:08:56.567001 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7414 11:08:56.569483 [DutyScan_Calibration_Flow] ====Done====
7415 11:08:56.569949
7416 11:08:56.572998 [DutyScan_Calibration_Flow] k_type=3
7417 11:08:56.590521
7418 11:08:56.591083 ==DQM 0 ==
7419 11:08:56.593525 Final DQM duty delay cell = 0
7420 11:08:56.596909 [0] MAX Duty = 5218%(X100), DQS PI = 34
7421 11:08:56.600179 [0] MIN Duty = 5031%(X100), DQS PI = 6
7422 11:08:56.603810 [0] AVG Duty = 5124%(X100)
7423 11:08:56.604363
7424 11:08:56.604730 ==DQM 1 ==
7425 11:08:56.606617 Final DQM duty delay cell = 0
7426 11:08:56.610255 [0] MAX Duty = 5125%(X100), DQS PI = 0
7427 11:08:56.613165 [0] MIN Duty = 4969%(X100), DQS PI = 32
7428 11:08:56.616658 [0] AVG Duty = 5047%(X100)
7429 11:08:56.617120
7430 11:08:56.619770 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7431 11:08:56.620237
7432 11:08:56.623230 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7433 11:08:56.626521 [DutyScan_Calibration_Flow] ====Done====
7434 11:08:56.626981
7435 11:08:56.629594 [DutyScan_Calibration_Flow] k_type=2
7436 11:08:56.647654
7437 11:08:56.648260 ==DQ 0 ==
7438 11:08:56.650941 Final DQ duty delay cell = 0
7439 11:08:56.653644 [0] MAX Duty = 5156%(X100), DQS PI = 30
7440 11:08:56.657284 [0] MIN Duty = 4906%(X100), DQS PI = 8
7441 11:08:56.657855 [0] AVG Duty = 5031%(X100)
7442 11:08:56.660484
7443 11:08:56.661041 ==DQ 1 ==
7444 11:08:56.664025 Final DQ duty delay cell = 0
7445 11:08:56.667023 [0] MAX Duty = 5156%(X100), DQS PI = 8
7446 11:08:56.670502 [0] MIN Duty = 4969%(X100), DQS PI = 56
7447 11:08:56.670968 [0] AVG Duty = 5062%(X100)
7448 11:08:56.671334
7449 11:08:56.676688 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7450 11:08:56.677257
7451 11:08:56.679887 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7452 11:08:56.683084 [DutyScan_Calibration_Flow] ====Done====
7453 11:08:56.686934 nWR fixed to 30
7454 11:08:56.687498 [ModeRegInit_LP4] CH0 RK0
7455 11:08:56.690472 [ModeRegInit_LP4] CH0 RK1
7456 11:08:56.693638 [ModeRegInit_LP4] CH1 RK0
7457 11:08:56.696607 [ModeRegInit_LP4] CH1 RK1
7458 11:08:56.697070 match AC timing 5
7459 11:08:56.703295 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7460 11:08:56.706505 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7461 11:08:56.709361 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7462 11:08:56.716068 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7463 11:08:56.719218 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7464 11:08:56.719721 [MiockJmeterHQA]
7465 11:08:56.720099
7466 11:08:56.722950 [DramcMiockJmeter] u1RxGatingPI = 0
7467 11:08:56.726684 0 : 4255, 4027
7468 11:08:56.727252 4 : 4363, 4138
7469 11:08:56.729239 8 : 4253, 4027
7470 11:08:56.729710 12 : 4252, 4027
7471 11:08:56.732494 16 : 4252, 4027
7472 11:08:56.732966 20 : 4252, 4027
7473 11:08:56.733336 24 : 4254, 4029
7474 11:08:56.735741 28 : 4253, 4026
7475 11:08:56.736233 32 : 4252, 4027
7476 11:08:56.739559 36 : 4365, 4140
7477 11:08:56.740080 40 : 4252, 4027
7478 11:08:56.742420 44 : 4255, 4029
7479 11:08:56.742892 48 : 4253, 4026
7480 11:08:56.745822 52 : 4363, 4138
7481 11:08:56.746346 56 : 4253, 4026
7482 11:08:56.746911 60 : 4360, 4138
7483 11:08:56.749442 64 : 4249, 4027
7484 11:08:56.749912 68 : 4250, 4027
7485 11:08:56.752172 72 : 4250, 4027
7486 11:08:56.752596 76 : 4252, 4029
7487 11:08:56.755756 80 : 4360, 4138
7488 11:08:56.756282 84 : 4250, 4027
7489 11:08:56.759135 88 : 4361, 4136
7490 11:08:56.759659 92 : 4250, 423
7491 11:08:56.760050 96 : 4250, 0
7492 11:08:56.762142 100 : 4250, 0
7493 11:08:56.762661 104 : 4250, 0
7494 11:08:56.765494 108 : 4250, 0
7495 11:08:56.766020 112 : 4252, 0
7496 11:08:56.766364 116 : 4250, 0
7497 11:08:56.769011 120 : 4250, 0
7498 11:08:56.769541 124 : 4253, 0
7499 11:08:56.772191 128 : 4361, 0
7500 11:08:56.772714 132 : 4361, 0
7501 11:08:56.773060 136 : 4363, 0
7502 11:08:56.775661 140 : 4250, 0
7503 11:08:56.776249 144 : 4250, 0
7504 11:08:56.778342 148 : 4363, 0
7505 11:08:56.778767 152 : 4250, 0
7506 11:08:56.779106 156 : 4250, 0
7507 11:08:56.782067 160 : 4250, 0
7508 11:08:56.782716 164 : 4252, 0
7509 11:08:56.783153 168 : 4361, 0
7510 11:08:56.785716 172 : 4250, 0
7511 11:08:56.786148 176 : 4250, 0
7512 11:08:56.788637 180 : 4250, 0
7513 11:08:56.789065 184 : 4360, 0
7514 11:08:56.789407 188 : 4250, 0
7515 11:08:56.791525 192 : 4249, 0
7516 11:08:56.792017 196 : 4250, 0
7517 11:08:56.795150 200 : 4250, 0
7518 11:08:56.795725 204 : 4250, 0
7519 11:08:56.796085 208 : 4250, 0
7520 11:08:56.798616 212 : 4250, 0
7521 11:08:56.799141 216 : 4252, 0
7522 11:08:56.801381 220 : 4249, 0
7523 11:08:56.801810 224 : 4250, 622
7524 11:08:56.804735 228 : 4249, 3617
7525 11:08:56.805162 232 : 4250, 4027
7526 11:08:56.805500 236 : 4250, 4026
7527 11:08:56.808403 240 : 4361, 4137
7528 11:08:56.808835 244 : 4361, 4138
7529 11:08:56.811347 248 : 4250, 4027
7530 11:08:56.811909 252 : 4360, 4137
7531 11:08:56.814921 256 : 4250, 4026
7532 11:08:56.815446 260 : 4250, 4027
7533 11:08:56.817897 264 : 4249, 4027
7534 11:08:56.818326 268 : 4252, 4029
7535 11:08:56.821515 272 : 4250, 4026
7536 11:08:56.822041 276 : 4250, 4027
7537 11:08:56.824638 280 : 4250, 4027
7538 11:08:56.825163 284 : 4250, 4027
7539 11:08:56.828124 288 : 4250, 4027
7540 11:08:56.828646 292 : 4361, 4137
7541 11:08:56.831067 296 : 4361, 4138
7542 11:08:56.831594 300 : 4250, 4027
7543 11:08:56.834107 304 : 4363, 4140
7544 11:08:56.834539 308 : 4250, 4027
7545 11:08:56.834879 312 : 4250, 4027
7546 11:08:56.837834 316 : 4249, 4027
7547 11:08:56.838363 320 : 4252, 4029
7548 11:08:56.840955 324 : 4250, 4026
7549 11:08:56.841391 328 : 4250, 4027
7550 11:08:56.844404 332 : 4250, 4027
7551 11:08:56.844940 336 : 4250, 3767
7552 11:08:56.847424 340 : 4250, 1646
7553 11:08:56.847900
7554 11:08:56.848255 MIOCK jitter meter ch=0
7555 11:08:56.851037
7556 11:08:56.851457 1T = (340-92) = 248 dly cells
7557 11:08:56.857576 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7558 11:08:56.858094 ==
7559 11:08:56.861125 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 11:08:56.864172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 11:08:56.864692 ==
7562 11:08:56.871107 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7563 11:08:56.873809 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7564 11:08:56.880063 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7565 11:08:56.883506 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7566 11:08:56.894076 [CA 0] Center 43 (13~74) winsize 62
7567 11:08:56.897897 [CA 1] Center 43 (13~73) winsize 61
7568 11:08:56.900503 [CA 2] Center 38 (9~68) winsize 60
7569 11:08:56.904082 [CA 3] Center 38 (9~68) winsize 60
7570 11:08:56.907740 [CA 4] Center 36 (7~66) winsize 60
7571 11:08:56.910743 [CA 5] Center 35 (6~65) winsize 60
7572 11:08:56.911306
7573 11:08:56.913916 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7574 11:08:56.914480
7575 11:08:56.920817 [CATrainingPosCal] consider 1 rank data
7576 11:08:56.921443 u2DelayCellTimex100 = 262/100 ps
7577 11:08:56.927331 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7578 11:08:56.930964 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7579 11:08:56.933622 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7580 11:08:56.937079 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7581 11:08:56.940846 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7582 11:08:56.944047 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7583 11:08:56.944515
7584 11:08:56.947079 CA PerBit enable=1, Macro0, CA PI delay=35
7585 11:08:56.947641
7586 11:08:56.950539 [CBTSetCACLKResult] CA Dly = 35
7587 11:08:56.953789 CS Dly: 11 (0~42)
7588 11:08:56.956989 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7589 11:08:56.959861 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7590 11:08:56.963298 ==
7591 11:08:56.966367 Dram Type= 6, Freq= 0, CH_0, rank 1
7592 11:08:56.970216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 11:08:56.970780 ==
7594 11:08:56.972725 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7595 11:08:56.979919 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7596 11:08:56.982779 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7597 11:08:56.989133 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7598 11:08:56.998012 [CA 0] Center 42 (12~73) winsize 62
7599 11:08:57.001226 [CA 1] Center 43 (13~73) winsize 61
7600 11:08:57.004197 [CA 2] Center 37 (8~67) winsize 60
7601 11:08:57.008247 [CA 3] Center 37 (7~67) winsize 61
7602 11:08:57.010840 [CA 4] Center 35 (6~65) winsize 60
7603 11:08:57.014650 [CA 5] Center 35 (5~65) winsize 61
7604 11:08:57.015215
7605 11:08:57.017518 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7606 11:08:57.017985
7607 11:08:57.021240 [CATrainingPosCal] consider 2 rank data
7608 11:08:57.024130 u2DelayCellTimex100 = 262/100 ps
7609 11:08:57.028019 CA0 delay=43 (13~73),Diff = 8 PI (29 cell)
7610 11:08:57.034070 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7611 11:08:57.037727 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7612 11:08:57.041118 CA3 delay=38 (9~67),Diff = 3 PI (11 cell)
7613 11:08:57.044137 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7614 11:08:57.047887 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7615 11:08:57.048441
7616 11:08:57.050741 CA PerBit enable=1, Macro0, CA PI delay=35
7617 11:08:57.051207
7618 11:08:57.054359 [CBTSetCACLKResult] CA Dly = 35
7619 11:08:57.057506 CS Dly: 11 (0~43)
7620 11:08:57.060497 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7621 11:08:57.063873 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7622 11:08:57.064433
7623 11:08:57.067020 ----->DramcWriteLeveling(PI) begin...
7624 11:08:57.067592 ==
7625 11:08:57.070222 Dram Type= 6, Freq= 0, CH_0, rank 0
7626 11:08:57.076865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7627 11:08:57.077371 ==
7628 11:08:57.080279 Write leveling (Byte 0): 35 => 35
7629 11:08:57.083374 Write leveling (Byte 1): 26 => 26
7630 11:08:57.086951 DramcWriteLeveling(PI) end<-----
7631 11:08:57.087516
7632 11:08:57.087957 ==
7633 11:08:57.090037 Dram Type= 6, Freq= 0, CH_0, rank 0
7634 11:08:57.093095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7635 11:08:57.093565 ==
7636 11:08:57.096416 [Gating] SW mode calibration
7637 11:08:57.103250 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7638 11:08:57.110176 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7639 11:08:57.112920 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7640 11:08:57.116345 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 11:08:57.122849 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 11:08:57.126213 1 4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7643 11:08:57.129809 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7644 11:08:57.136321 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7645 11:08:57.139408 1 4 24 | B1->B0 | 2d2c 3434 | 1 1 | (0 0) (1 1)
7646 11:08:57.142588 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7647 11:08:57.149422 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7648 11:08:57.152738 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7649 11:08:57.156481 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7650 11:08:57.159354 1 5 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7651 11:08:57.166251 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7652 11:08:57.169476 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7653 11:08:57.175771 1 5 24 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
7654 11:08:57.179079 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 11:08:57.182045 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 11:08:57.189087 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 11:08:57.192357 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7658 11:08:57.195933 1 6 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7659 11:08:57.201951 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7660 11:08:57.205432 1 6 20 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7661 11:08:57.208542 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7662 11:08:57.215667 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 11:08:57.218560 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 11:08:57.221397 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7665 11:08:57.228374 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7666 11:08:57.231756 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7667 11:08:57.234855 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7668 11:08:57.241224 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7669 11:08:57.244739 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 11:08:57.248002 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 11:08:57.254377 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 11:08:57.258266 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 11:08:57.261025 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 11:08:57.267919 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 11:08:57.271343 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 11:08:57.274629 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 11:08:57.280637 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 11:08:57.284079 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 11:08:57.287554 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 11:08:57.294541 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 11:08:57.297619 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7682 11:08:57.300719 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7683 11:08:57.304520 Total UI for P1: 0, mck2ui 16
7684 11:08:57.307463 best dqsien dly found for B0: ( 1, 9, 8)
7685 11:08:57.313930 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7686 11:08:57.317640 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7687 11:08:57.320401 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7688 11:08:57.324481 Total UI for P1: 0, mck2ui 16
7689 11:08:57.326883 best dqsien dly found for B1: ( 1, 9, 20)
7690 11:08:57.330431 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7691 11:08:57.333937 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7692 11:08:57.334404
7693 11:08:57.340476 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7694 11:08:57.343599 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7695 11:08:57.344207 [Gating] SW calibration Done
7696 11:08:57.346526 ==
7697 11:08:57.350554 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 11:08:57.353621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 11:08:57.354088 ==
7700 11:08:57.354454 RX Vref Scan: 0
7701 11:08:57.354800
7702 11:08:57.356866 RX Vref 0 -> 0, step: 1
7703 11:08:57.357332
7704 11:08:57.359920 RX Delay 0 -> 252, step: 8
7705 11:08:57.363331 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7706 11:08:57.366817 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7707 11:08:57.369726 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7708 11:08:57.376288 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7709 11:08:57.379459 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7710 11:08:57.383349 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7711 11:08:57.386007 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7712 11:08:57.390282 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7713 11:08:57.396320 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7714 11:08:57.399753 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7715 11:08:57.402741 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7716 11:08:57.406495 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7717 11:08:57.409378 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7718 11:08:57.416078 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7719 11:08:57.419516 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7720 11:08:57.422915 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7721 11:08:57.423476 ==
7722 11:08:57.426296 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 11:08:57.432499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 11:08:57.433061 ==
7725 11:08:57.433430 DQS Delay:
7726 11:08:57.433770 DQS0 = 0, DQS1 = 0
7727 11:08:57.435864 DQM Delay:
7728 11:08:57.436323 DQM0 = 134, DQM1 = 126
7729 11:08:57.439457 DQ Delay:
7730 11:08:57.442476 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7731 11:08:57.445605 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =147
7732 11:08:57.449622 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7733 11:08:57.452353 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7734 11:08:57.452819
7735 11:08:57.453184
7736 11:08:57.453528 ==
7737 11:08:57.456320 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 11:08:57.459641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 11:08:57.462481 ==
7740 11:08:57.463052
7741 11:08:57.463421
7742 11:08:57.463796 TX Vref Scan disable
7743 11:08:57.465286 == TX Byte 0 ==
7744 11:08:57.468683 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7745 11:08:57.472253 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7746 11:08:57.475746 == TX Byte 1 ==
7747 11:08:57.478806 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7748 11:08:57.485134 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7749 11:08:57.485759 ==
7750 11:08:57.488892 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 11:08:57.491452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 11:08:57.491974 ==
7753 11:08:57.505253
7754 11:08:57.508472 TX Vref early break, caculate TX vref
7755 11:08:57.511730 TX Vref=16, minBit 14, minWin=22, winSum=371
7756 11:08:57.515110 TX Vref=18, minBit 1, minWin=23, winSum=374
7757 11:08:57.518545 TX Vref=20, minBit 6, minWin=23, winSum=389
7758 11:08:57.521468 TX Vref=22, minBit 4, minWin=23, winSum=397
7759 11:08:57.528100 TX Vref=24, minBit 0, minWin=25, winSum=408
7760 11:08:57.531339 TX Vref=26, minBit 3, minWin=25, winSum=413
7761 11:08:57.534818 TX Vref=28, minBit 0, minWin=25, winSum=414
7762 11:08:57.538524 TX Vref=30, minBit 4, minWin=25, winSum=412
7763 11:08:57.541246 TX Vref=32, minBit 7, minWin=23, winSum=396
7764 11:08:57.545221 TX Vref=34, minBit 7, minWin=23, winSum=388
7765 11:08:57.551243 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 28
7766 11:08:57.551878
7767 11:08:57.554200 Final TX Range 0 Vref 28
7768 11:08:57.554660
7769 11:08:57.555025 ==
7770 11:08:57.557899 Dram Type= 6, Freq= 0, CH_0, rank 0
7771 11:08:57.561018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7772 11:08:57.561584 ==
7773 11:08:57.561958
7774 11:08:57.564240
7775 11:08:57.564796 TX Vref Scan disable
7776 11:08:57.570539 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7777 11:08:57.571096 == TX Byte 0 ==
7778 11:08:57.574007 u2DelayCellOfst[0]=14 cells (4 PI)
7779 11:08:57.577815 u2DelayCellOfst[1]=18 cells (5 PI)
7780 11:08:57.580790 u2DelayCellOfst[2]=14 cells (4 PI)
7781 11:08:57.583657 u2DelayCellOfst[3]=14 cells (4 PI)
7782 11:08:57.587532 u2DelayCellOfst[4]=11 cells (3 PI)
7783 11:08:57.590665 u2DelayCellOfst[5]=0 cells (0 PI)
7784 11:08:57.593760 u2DelayCellOfst[6]=18 cells (5 PI)
7785 11:08:57.597074 u2DelayCellOfst[7]=22 cells (6 PI)
7786 11:08:57.600878 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7787 11:08:57.603771 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7788 11:08:57.606720 == TX Byte 1 ==
7789 11:08:57.609977 u2DelayCellOfst[8]=0 cells (0 PI)
7790 11:08:57.613804 u2DelayCellOfst[9]=0 cells (0 PI)
7791 11:08:57.616892 u2DelayCellOfst[10]=3 cells (1 PI)
7792 11:08:57.620573 u2DelayCellOfst[11]=0 cells (0 PI)
7793 11:08:57.622937 u2DelayCellOfst[12]=11 cells (3 PI)
7794 11:08:57.626065 u2DelayCellOfst[13]=11 cells (3 PI)
7795 11:08:57.630264 u2DelayCellOfst[14]=14 cells (4 PI)
7796 11:08:57.633023 u2DelayCellOfst[15]=11 cells (3 PI)
7797 11:08:57.636448 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7798 11:08:57.639427 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7799 11:08:57.643008 DramC Write-DBI on
7800 11:08:57.643470 ==
7801 11:08:57.646644 Dram Type= 6, Freq= 0, CH_0, rank 0
7802 11:08:57.649103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7803 11:08:57.649566 ==
7804 11:08:57.649934
7805 11:08:57.650271
7806 11:08:57.652198 TX Vref Scan disable
7807 11:08:57.656868 == TX Byte 0 ==
7808 11:08:57.658792 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7809 11:08:57.659254 == TX Byte 1 ==
7810 11:08:57.665587 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7811 11:08:57.666152 DramC Write-DBI off
7812 11:08:57.666522
7813 11:08:57.668934 [DATLAT]
7814 11:08:57.669495 Freq=1600, CH0 RK0
7815 11:08:57.669866
7816 11:08:57.672343 DATLAT Default: 0xf
7817 11:08:57.672901 0, 0xFFFF, sum = 0
7818 11:08:57.675484 1, 0xFFFF, sum = 0
7819 11:08:57.675985 2, 0xFFFF, sum = 0
7820 11:08:57.679294 3, 0xFFFF, sum = 0
7821 11:08:57.679911 4, 0xFFFF, sum = 0
7822 11:08:57.682757 5, 0xFFFF, sum = 0
7823 11:08:57.683325 6, 0xFFFF, sum = 0
7824 11:08:57.685472 7, 0xFFFF, sum = 0
7825 11:08:57.685987 8, 0xFFFF, sum = 0
7826 11:08:57.689284 9, 0xFFFF, sum = 0
7827 11:08:57.689750 10, 0xFFFF, sum = 0
7828 11:08:57.691774 11, 0xFFFF, sum = 0
7829 11:08:57.695249 12, 0xFFFF, sum = 0
7830 11:08:57.695766 13, 0xFFFF, sum = 0
7831 11:08:57.698584 14, 0x0, sum = 1
7832 11:08:57.699157 15, 0x0, sum = 2
7833 11:08:57.702126 16, 0x0, sum = 3
7834 11:08:57.702749 17, 0x0, sum = 4
7835 11:08:57.703140 best_step = 15
7836 11:08:57.703482
7837 11:08:57.704887 ==
7838 11:08:57.708614 Dram Type= 6, Freq= 0, CH_0, rank 0
7839 11:08:57.711605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7840 11:08:57.712121 ==
7841 11:08:57.712578 RX Vref Scan: 1
7842 11:08:57.712934
7843 11:08:57.715318 Set Vref Range= 24 -> 127
7844 11:08:57.715827
7845 11:08:57.718268 RX Vref 24 -> 127, step: 1
7846 11:08:57.718830
7847 11:08:57.721446 RX Delay 11 -> 252, step: 4
7848 11:08:57.722005
7849 11:08:57.725129 Set Vref, RX VrefLevel [Byte0]: 24
7850 11:08:57.728553 [Byte1]: 24
7851 11:08:57.729115
7852 11:08:57.731706 Set Vref, RX VrefLevel [Byte0]: 25
7853 11:08:57.734677 [Byte1]: 25
7854 11:08:57.735237
7855 11:08:57.738026 Set Vref, RX VrefLevel [Byte0]: 26
7856 11:08:57.741548 [Byte1]: 26
7857 11:08:57.744835
7858 11:08:57.745484 Set Vref, RX VrefLevel [Byte0]: 27
7859 11:08:57.748266 [Byte1]: 27
7860 11:08:57.752435
7861 11:08:57.752901 Set Vref, RX VrefLevel [Byte0]: 28
7862 11:08:57.755994 [Byte1]: 28
7863 11:08:57.760480
7864 11:08:57.760941 Set Vref, RX VrefLevel [Byte0]: 29
7865 11:08:57.763955 [Byte1]: 29
7866 11:08:57.768081
7867 11:08:57.768635 Set Vref, RX VrefLevel [Byte0]: 30
7868 11:08:57.771398 [Byte1]: 30
7869 11:08:57.776095
7870 11:08:57.776743 Set Vref, RX VrefLevel [Byte0]: 31
7871 11:08:57.779331 [Byte1]: 31
7872 11:08:57.783204
7873 11:08:57.783814 Set Vref, RX VrefLevel [Byte0]: 32
7874 11:08:57.786312 [Byte1]: 32
7875 11:08:57.791892
7876 11:08:57.792445 Set Vref, RX VrefLevel [Byte0]: 33
7877 11:08:57.793911 [Byte1]: 33
7878 11:08:57.798749
7879 11:08:57.799306 Set Vref, RX VrefLevel [Byte0]: 34
7880 11:08:57.801580 [Byte1]: 34
7881 11:08:57.806329
7882 11:08:57.806815 Set Vref, RX VrefLevel [Byte0]: 35
7883 11:08:57.809062 [Byte1]: 35
7884 11:08:57.813364
7885 11:08:57.813825 Set Vref, RX VrefLevel [Byte0]: 36
7886 11:08:57.816569 [Byte1]: 36
7887 11:08:57.821467
7888 11:08:57.822017 Set Vref, RX VrefLevel [Byte0]: 37
7889 11:08:57.825146 [Byte1]: 37
7890 11:08:57.828518
7891 11:08:57.829220 Set Vref, RX VrefLevel [Byte0]: 38
7892 11:08:57.832221 [Byte1]: 38
7893 11:08:57.836698
7894 11:08:57.837258 Set Vref, RX VrefLevel [Byte0]: 39
7895 11:08:57.840054 [Byte1]: 39
7896 11:08:57.844225
7897 11:08:57.844684 Set Vref, RX VrefLevel [Byte0]: 40
7898 11:08:57.847286 [Byte1]: 40
7899 11:08:57.851531
7900 11:08:57.852141 Set Vref, RX VrefLevel [Byte0]: 41
7901 11:08:57.855044 [Byte1]: 41
7902 11:08:57.859287
7903 11:08:57.859847 Set Vref, RX VrefLevel [Byte0]: 42
7904 11:08:57.862515 [Byte1]: 42
7905 11:08:57.866970
7906 11:08:57.867587 Set Vref, RX VrefLevel [Byte0]: 43
7907 11:08:57.870174 [Byte1]: 43
7908 11:08:57.874263
7909 11:08:57.874722 Set Vref, RX VrefLevel [Byte0]: 44
7910 11:08:57.877843 [Byte1]: 44
7911 11:08:57.882180
7912 11:08:57.882738 Set Vref, RX VrefLevel [Byte0]: 45
7913 11:08:57.885453 [Byte1]: 45
7914 11:08:57.889721
7915 11:08:57.890182 Set Vref, RX VrefLevel [Byte0]: 46
7916 11:08:57.892962 [Byte1]: 46
7917 11:08:57.897332
7918 11:08:57.897893 Set Vref, RX VrefLevel [Byte0]: 47
7919 11:08:57.900796 [Byte1]: 47
7920 11:08:57.905254
7921 11:08:57.905710 Set Vref, RX VrefLevel [Byte0]: 48
7922 11:08:57.907993 [Byte1]: 48
7923 11:08:57.912611
7924 11:08:57.913067 Set Vref, RX VrefLevel [Byte0]: 49
7925 11:08:57.919030 [Byte1]: 49
7926 11:08:57.919588
7927 11:08:57.922415 Set Vref, RX VrefLevel [Byte0]: 50
7928 11:08:57.925717 [Byte1]: 50
7929 11:08:57.926275
7930 11:08:57.928875 Set Vref, RX VrefLevel [Byte0]: 51
7931 11:08:57.932169 [Byte1]: 51
7932 11:08:57.935727
7933 11:08:57.936287 Set Vref, RX VrefLevel [Byte0]: 52
7934 11:08:57.938855 [Byte1]: 52
7935 11:08:57.943116
7936 11:08:57.943818 Set Vref, RX VrefLevel [Byte0]: 53
7937 11:08:57.946138 [Byte1]: 53
7938 11:08:57.950838
7939 11:08:57.951427 Set Vref, RX VrefLevel [Byte0]: 54
7940 11:08:57.953614 [Byte1]: 54
7941 11:08:57.958169
7942 11:08:57.958629 Set Vref, RX VrefLevel [Byte0]: 55
7943 11:08:57.961470 [Byte1]: 55
7944 11:08:57.966137
7945 11:08:57.966701 Set Vref, RX VrefLevel [Byte0]: 56
7946 11:08:57.969362 [Byte1]: 56
7947 11:08:57.974256
7948 11:08:57.974810 Set Vref, RX VrefLevel [Byte0]: 57
7949 11:08:57.976562 [Byte1]: 57
7950 11:08:57.981023
7951 11:08:57.981583 Set Vref, RX VrefLevel [Byte0]: 58
7952 11:08:57.984622 [Byte1]: 58
7953 11:08:57.988387
7954 11:08:57.988890 Set Vref, RX VrefLevel [Byte0]: 59
7955 11:08:57.991717 [Byte1]: 59
7956 11:08:57.996588
7957 11:08:57.997149 Set Vref, RX VrefLevel [Byte0]: 60
7958 11:08:57.999342 [Byte1]: 60
7959 11:08:58.003896
7960 11:08:58.004358 Set Vref, RX VrefLevel [Byte0]: 61
7961 11:08:58.007246 [Byte1]: 61
7962 11:08:58.011631
7963 11:08:58.012249 Set Vref, RX VrefLevel [Byte0]: 62
7964 11:08:58.014913 [Byte1]: 62
7965 11:08:58.019489
7966 11:08:58.020129 Set Vref, RX VrefLevel [Byte0]: 63
7967 11:08:58.022584 [Byte1]: 63
7968 11:08:58.027553
7969 11:08:58.028163 Set Vref, RX VrefLevel [Byte0]: 64
7970 11:08:58.029692 [Byte1]: 64
7971 11:08:58.034276
7972 11:08:58.034827 Set Vref, RX VrefLevel [Byte0]: 65
7973 11:08:58.037720 [Byte1]: 65
7974 11:08:58.041869
7975 11:08:58.042335 Set Vref, RX VrefLevel [Byte0]: 66
7976 11:08:58.045329 [Byte1]: 66
7977 11:08:58.049428
7978 11:08:58.049897 Set Vref, RX VrefLevel [Byte0]: 67
7979 11:08:58.053124 [Byte1]: 67
7980 11:08:58.056964
7981 11:08:58.057429 Set Vref, RX VrefLevel [Byte0]: 68
7982 11:08:58.060598 [Byte1]: 68
7983 11:08:58.064577
7984 11:08:58.065158 Set Vref, RX VrefLevel [Byte0]: 69
7985 11:08:58.067996 [Byte1]: 69
7986 11:08:58.072645
7987 11:08:58.073236 Set Vref, RX VrefLevel [Byte0]: 70
7988 11:08:58.075705 [Byte1]: 70
7989 11:08:58.080008
7990 11:08:58.080571 Set Vref, RX VrefLevel [Byte0]: 71
7991 11:08:58.083449 [Byte1]: 71
7992 11:08:58.087620
7993 11:08:58.088135 Set Vref, RX VrefLevel [Byte0]: 72
7994 11:08:58.090762 [Byte1]: 72
7995 11:08:58.095427
7996 11:08:58.095956 Set Vref, RX VrefLevel [Byte0]: 73
7997 11:08:58.098352 [Byte1]: 73
7998 11:08:58.102765
7999 11:08:58.103252 Set Vref, RX VrefLevel [Byte0]: 74
8000 11:08:58.106346 [Byte1]: 74
8001 11:08:58.110486
8002 11:08:58.113255 Set Vref, RX VrefLevel [Byte0]: 75
8003 11:08:58.116852 [Byte1]: 75
8004 11:08:58.117277
8005 11:08:58.120326 Set Vref, RX VrefLevel [Byte0]: 76
8006 11:08:58.123449 [Byte1]: 76
8007 11:08:58.124026
8008 11:08:58.126985 Set Vref, RX VrefLevel [Byte0]: 77
8009 11:08:58.129949 [Byte1]: 77
8010 11:08:58.133141
8011 11:08:58.133672 Set Vref, RX VrefLevel [Byte0]: 78
8012 11:08:58.136458 [Byte1]: 78
8013 11:08:58.140887
8014 11:08:58.141314 Set Vref, RX VrefLevel [Byte0]: 79
8015 11:08:58.144657 [Byte1]: 79
8016 11:08:58.148336
8017 11:08:58.148759 Final RX Vref Byte 0 = 68 to rank0
8018 11:08:58.151845 Final RX Vref Byte 1 = 58 to rank0
8019 11:08:58.155142 Final RX Vref Byte 0 = 68 to rank1
8020 11:08:58.158634 Final RX Vref Byte 1 = 58 to rank1==
8021 11:08:58.162076 Dram Type= 6, Freq= 0, CH_0, rank 0
8022 11:08:58.168368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8023 11:08:58.168907 ==
8024 11:08:58.169251 DQS Delay:
8025 11:08:58.169616 DQS0 = 0, DQS1 = 0
8026 11:08:58.171741 DQM Delay:
8027 11:08:58.172210 DQM0 = 133, DQM1 = 123
8028 11:08:58.174703 DQ Delay:
8029 11:08:58.178728 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =132
8030 11:08:58.181880 DQ4 =134, DQ5 =122, DQ6 =142, DQ7 =140
8031 11:08:58.184791 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8032 11:08:58.188187 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128
8033 11:08:58.188613
8034 11:08:58.188947
8035 11:08:58.189307
8036 11:08:58.191367 [DramC_TX_OE_Calibration] TA2
8037 11:08:58.194920 Original DQ_B0 (3 6) =30, OEN = 27
8038 11:08:58.198568 Original DQ_B1 (3 6) =30, OEN = 27
8039 11:08:58.201221 24, 0x0, End_B0=24 End_B1=24
8040 11:08:58.201660 25, 0x0, End_B0=25 End_B1=25
8041 11:08:58.204584 26, 0x0, End_B0=26 End_B1=26
8042 11:08:58.207842 27, 0x0, End_B0=27 End_B1=27
8043 11:08:58.211763 28, 0x0, End_B0=28 End_B1=28
8044 11:08:58.215108 29, 0x0, End_B0=29 End_B1=29
8045 11:08:58.215741 30, 0x0, End_B0=30 End_B1=30
8046 11:08:58.217477 31, 0x4141, End_B0=30 End_B1=30
8047 11:08:58.221471 Byte0 end_step=30 best_step=27
8048 11:08:58.224424 Byte1 end_step=30 best_step=27
8049 11:08:58.227869 Byte0 TX OE(2T, 0.5T) = (3, 3)
8050 11:08:58.231793 Byte1 TX OE(2T, 0.5T) = (3, 3)
8051 11:08:58.232307
8052 11:08:58.232650
8053 11:08:58.237161 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c0d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 395 ps
8054 11:08:58.241179 CH0 RK0: MR19=303, MR18=1C0D
8055 11:08:58.247777 CH0_RK0: MR19=0x303, MR18=0x1C0D, DQSOSC=395, MR23=63, INC=23, DEC=15
8056 11:08:58.248203
8057 11:08:58.250617 ----->DramcWriteLeveling(PI) begin...
8058 11:08:58.251135 ==
8059 11:08:58.253828 Dram Type= 6, Freq= 0, CH_0, rank 1
8060 11:08:58.257280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8061 11:08:58.257747 ==
8062 11:08:58.260570 Write leveling (Byte 0): 33 => 33
8063 11:08:58.263568 Write leveling (Byte 1): 30 => 30
8064 11:08:58.266935 DramcWriteLeveling(PI) end<-----
8065 11:08:58.267364
8066 11:08:58.267900 ==
8067 11:08:58.270467 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 11:08:58.276552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 11:08:58.276985 ==
8070 11:08:58.277424 [Gating] SW mode calibration
8071 11:08:58.286864 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8072 11:08:58.289991 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8073 11:08:58.293490 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 11:08:58.299937 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 11:08:58.303270 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 11:08:58.309815 1 4 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8077 11:08:58.313026 1 4 16 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8078 11:08:58.316167 1 4 20 | B1->B0 | 2b2a 3434 | 1 1 | (0 0) (1 1)
8079 11:08:58.322867 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8080 11:08:58.326001 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8081 11:08:58.329693 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8082 11:08:58.332977 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8083 11:08:58.339328 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8084 11:08:58.343885 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8085 11:08:58.349650 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
8086 11:08:58.352307 1 5 20 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
8087 11:08:58.356093 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8088 11:08:58.362374 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8089 11:08:58.365831 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8090 11:08:58.369113 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8091 11:08:58.375395 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8092 11:08:58.378789 1 6 12 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
8093 11:08:58.382421 1 6 16 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
8094 11:08:58.388389 1 6 20 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8095 11:08:58.391861 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8096 11:08:58.395001 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 11:08:58.402024 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8098 11:08:58.405007 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8099 11:08:58.408358 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8100 11:08:58.415202 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8101 11:08:58.418294 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8102 11:08:58.421532 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8103 11:08:58.428469 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 11:08:58.431268 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 11:08:58.435029 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 11:08:58.441410 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 11:08:58.444852 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 11:08:58.447915 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 11:08:58.454891 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 11:08:58.458033 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 11:08:58.461201 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 11:08:58.468049 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 11:08:58.470943 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 11:08:58.474213 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 11:08:58.481423 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 11:08:58.484624 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8117 11:08:58.487393 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8118 11:08:58.490540 Total UI for P1: 0, mck2ui 16
8119 11:08:58.494129 best dqsien dly found for B0: ( 1, 9, 12)
8120 11:08:58.500438 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8121 11:08:58.504037 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8122 11:08:58.507311 Total UI for P1: 0, mck2ui 16
8123 11:08:58.510590 best dqsien dly found for B1: ( 1, 9, 18)
8124 11:08:58.513518 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8125 11:08:58.516895 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8126 11:08:58.517379
8127 11:08:58.520198 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8128 11:08:58.523537 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8129 11:08:58.526883 [Gating] SW calibration Done
8130 11:08:58.527419 ==
8131 11:08:58.530019 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 11:08:58.533796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 11:08:58.537042 ==
8134 11:08:58.537521 RX Vref Scan: 0
8135 11:08:58.537959
8136 11:08:58.540903 RX Vref 0 -> 0, step: 1
8137 11:08:58.541467
8138 11:08:58.543769 RX Delay 0 -> 252, step: 8
8139 11:08:58.546472 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8140 11:08:58.550059 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8141 11:08:58.553659 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8142 11:08:58.556864 iDelay=208, Bit 3, Center 127 (72 ~ 183) 112
8143 11:08:58.563063 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8144 11:08:58.566217 iDelay=208, Bit 5, Center 123 (64 ~ 183) 120
8145 11:08:58.570028 iDelay=208, Bit 6, Center 139 (80 ~ 199) 120
8146 11:08:58.573136 iDelay=208, Bit 7, Center 147 (88 ~ 207) 120
8147 11:08:58.575596 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8148 11:08:58.582742 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8149 11:08:58.585484 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8150 11:08:58.589267 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8151 11:08:58.592719 iDelay=208, Bit 12, Center 131 (72 ~ 191) 120
8152 11:08:58.599066 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8153 11:08:58.602280 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8154 11:08:58.605645 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8155 11:08:58.605722 ==
8156 11:08:58.609005 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 11:08:58.612337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 11:08:58.612415 ==
8159 11:08:58.615820 DQS Delay:
8160 11:08:58.615894 DQS0 = 0, DQS1 = 0
8161 11:08:58.618541 DQM Delay:
8162 11:08:58.618621 DQM0 = 133, DQM1 = 127
8163 11:08:58.618683 DQ Delay:
8164 11:08:58.625319 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8165 11:08:58.628464 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =147
8166 11:08:58.632031 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8167 11:08:58.634981 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8168 11:08:58.635053
8169 11:08:58.635114
8170 11:08:58.635181 ==
8171 11:08:58.638211 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 11:08:58.641780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 11:08:58.641893 ==
8174 11:08:58.641991
8175 11:08:58.642099
8176 11:08:58.644810 TX Vref Scan disable
8177 11:08:58.648209 == TX Byte 0 ==
8178 11:08:58.651807 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8179 11:08:58.654930 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8180 11:08:58.658653 == TX Byte 1 ==
8181 11:08:58.661771 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8182 11:08:58.665147 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8183 11:08:58.665224 ==
8184 11:08:58.668385 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 11:08:58.674291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 11:08:58.674369 ==
8187 11:08:58.687090
8188 11:08:58.689655 TX Vref early break, caculate TX vref
8189 11:08:58.693345 TX Vref=16, minBit 0, minWin=22, winSum=380
8190 11:08:58.696228 TX Vref=18, minBit 1, minWin=23, winSum=390
8191 11:08:58.699538 TX Vref=20, minBit 3, minWin=23, winSum=398
8192 11:08:58.702980 TX Vref=22, minBit 5, minWin=23, winSum=400
8193 11:08:58.706070 TX Vref=24, minBit 1, minWin=24, winSum=413
8194 11:08:58.712718 TX Vref=26, minBit 2, minWin=24, winSum=414
8195 11:08:58.716131 TX Vref=28, minBit 0, minWin=24, winSum=413
8196 11:08:58.719243 TX Vref=30, minBit 1, minWin=24, winSum=407
8197 11:08:58.722755 TX Vref=32, minBit 1, minWin=23, winSum=397
8198 11:08:58.725811 TX Vref=34, minBit 1, minWin=22, winSum=386
8199 11:08:58.732287 [TxChooseVref] Worse bit 2, Min win 24, Win sum 414, Final Vref 26
8200 11:08:58.732367
8201 11:08:58.735848 Final TX Range 0 Vref 26
8202 11:08:58.735923
8203 11:08:58.735985 ==
8204 11:08:58.738820 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 11:08:58.742364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 11:08:58.742439 ==
8207 11:08:58.742504
8208 11:08:58.742592
8209 11:08:58.745528 TX Vref Scan disable
8210 11:08:58.752341 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8211 11:08:58.752426 == TX Byte 0 ==
8212 11:08:58.755661 u2DelayCellOfst[0]=11 cells (3 PI)
8213 11:08:58.758772 u2DelayCellOfst[1]=18 cells (5 PI)
8214 11:08:58.762040 u2DelayCellOfst[2]=11 cells (3 PI)
8215 11:08:58.765228 u2DelayCellOfst[3]=14 cells (4 PI)
8216 11:08:58.768755 u2DelayCellOfst[4]=11 cells (3 PI)
8217 11:08:58.771543 u2DelayCellOfst[5]=0 cells (0 PI)
8218 11:08:58.775088 u2DelayCellOfst[6]=18 cells (5 PI)
8219 11:08:58.778209 u2DelayCellOfst[7]=18 cells (5 PI)
8220 11:08:58.781633 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8221 11:08:58.784862 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8222 11:08:58.787952 == TX Byte 1 ==
8223 11:08:58.791682 u2DelayCellOfst[8]=0 cells (0 PI)
8224 11:08:58.794805 u2DelayCellOfst[9]=3 cells (1 PI)
8225 11:08:58.798170 u2DelayCellOfst[10]=7 cells (2 PI)
8226 11:08:58.802440 u2DelayCellOfst[11]=3 cells (1 PI)
8227 11:08:58.804643 u2DelayCellOfst[12]=14 cells (4 PI)
8228 11:08:58.808180 u2DelayCellOfst[13]=14 cells (4 PI)
8229 11:08:58.810964 u2DelayCellOfst[14]=18 cells (5 PI)
8230 11:08:58.814268 u2DelayCellOfst[15]=14 cells (4 PI)
8231 11:08:58.817761 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8232 11:08:58.820783 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8233 11:08:58.824154 DramC Write-DBI on
8234 11:08:58.824230 ==
8235 11:08:58.828232 Dram Type= 6, Freq= 0, CH_0, rank 1
8236 11:08:58.831047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8237 11:08:58.831123 ==
8238 11:08:58.831184
8239 11:08:58.831261
8240 11:08:58.834279 TX Vref Scan disable
8241 11:08:58.834367 == TX Byte 0 ==
8242 11:08:58.840715 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8243 11:08:58.840792 == TX Byte 1 ==
8244 11:08:58.847450 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8245 11:08:58.847568 DramC Write-DBI off
8246 11:08:58.847662
8247 11:08:58.847779 [DATLAT]
8248 11:08:58.850417 Freq=1600, CH0 RK1
8249 11:08:58.850511
8250 11:08:58.853905 DATLAT Default: 0xf
8251 11:08:58.853979 0, 0xFFFF, sum = 0
8252 11:08:58.857391 1, 0xFFFF, sum = 0
8253 11:08:58.857479 2, 0xFFFF, sum = 0
8254 11:08:58.860571 3, 0xFFFF, sum = 0
8255 11:08:58.860648 4, 0xFFFF, sum = 0
8256 11:08:58.863983 5, 0xFFFF, sum = 0
8257 11:08:58.864105 6, 0xFFFF, sum = 0
8258 11:08:58.866929 7, 0xFFFF, sum = 0
8259 11:08:58.867006 8, 0xFFFF, sum = 0
8260 11:08:58.870290 9, 0xFFFF, sum = 0
8261 11:08:58.870372 10, 0xFFFF, sum = 0
8262 11:08:58.873384 11, 0xFFFF, sum = 0
8263 11:08:58.873470 12, 0xFFFF, sum = 0
8264 11:08:58.877369 13, 0xFFFF, sum = 0
8265 11:08:58.877455 14, 0x0, sum = 1
8266 11:08:58.880879 15, 0x0, sum = 2
8267 11:08:58.880954 16, 0x0, sum = 3
8268 11:08:58.883594 17, 0x0, sum = 4
8269 11:08:58.883667 best_step = 15
8270 11:08:58.883778
8271 11:08:58.883845 ==
8272 11:08:58.888022 Dram Type= 6, Freq= 0, CH_0, rank 1
8273 11:08:58.894119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 11:08:58.894537 ==
8275 11:08:58.894865 RX Vref Scan: 0
8276 11:08:58.895169
8277 11:08:58.897482 RX Vref 0 -> 0, step: 1
8278 11:08:58.897951
8279 11:08:58.900681 RX Delay 11 -> 252, step: 4
8280 11:08:58.904123 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8281 11:08:58.907071 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8282 11:08:58.910696 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8283 11:08:58.917166 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8284 11:08:58.920504 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8285 11:08:58.924107 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8286 11:08:58.927748 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8287 11:08:58.930564 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8288 11:08:58.937076 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8289 11:08:58.940553 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8290 11:08:58.943578 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8291 11:08:58.947332 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8292 11:08:58.953896 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8293 11:08:58.957302 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8294 11:08:58.960572 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8295 11:08:58.963828 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8296 11:08:58.964344 ==
8297 11:08:58.967204 Dram Type= 6, Freq= 0, CH_0, rank 1
8298 11:08:58.973349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8299 11:08:58.973876 ==
8300 11:08:58.974241 DQS Delay:
8301 11:08:58.976383 DQS0 = 0, DQS1 = 0
8302 11:08:58.976849 DQM Delay:
8303 11:08:58.977202 DQM0 = 130, DQM1 = 125
8304 11:08:58.980216 DQ Delay:
8305 11:08:58.984031 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =126
8306 11:08:58.986813 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8307 11:08:58.989809 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8308 11:08:58.992794 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8309 11:08:58.993248
8310 11:08:58.993574
8311 11:08:58.993878
8312 11:08:58.995973 [DramC_TX_OE_Calibration] TA2
8313 11:08:58.999772 Original DQ_B0 (3 6) =30, OEN = 27
8314 11:08:59.003501 Original DQ_B1 (3 6) =30, OEN = 27
8315 11:08:59.006583 24, 0x0, End_B0=24 End_B1=24
8316 11:08:59.009599 25, 0x0, End_B0=25 End_B1=25
8317 11:08:59.010023 26, 0x0, End_B0=26 End_B1=26
8318 11:08:59.012824 27, 0x0, End_B0=27 End_B1=27
8319 11:08:59.016011 28, 0x0, End_B0=28 End_B1=28
8320 11:08:59.019604 29, 0x0, End_B0=29 End_B1=29
8321 11:08:59.020119 30, 0x0, End_B0=30 End_B1=30
8322 11:08:59.023157 31, 0x4141, End_B0=30 End_B1=30
8323 11:08:59.026004 Byte0 end_step=30 best_step=27
8324 11:08:59.029155 Byte1 end_step=30 best_step=27
8325 11:08:59.032965 Byte0 TX OE(2T, 0.5T) = (3, 3)
8326 11:08:59.036284 Byte1 TX OE(2T, 0.5T) = (3, 3)
8327 11:08:59.036800
8328 11:08:59.037133
8329 11:08:59.042314 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8330 11:08:59.046041 CH0 RK1: MR19=303, MR18=1E01
8331 11:08:59.052755 CH0_RK1: MR19=0x303, MR18=0x1E01, DQSOSC=394, MR23=63, INC=23, DEC=15
8332 11:08:59.055789 [RxdqsGatingPostProcess] freq 1600
8333 11:08:59.062605 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8334 11:08:59.063074 best DQS0 dly(2T, 0.5T) = (1, 1)
8335 11:08:59.065518 best DQS1 dly(2T, 0.5T) = (1, 1)
8336 11:08:59.069179 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8337 11:08:59.072135 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8338 11:08:59.075714 best DQS0 dly(2T, 0.5T) = (1, 1)
8339 11:08:59.079132 best DQS1 dly(2T, 0.5T) = (1, 1)
8340 11:08:59.082430 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8341 11:08:59.085996 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8342 11:08:59.088878 Pre-setting of DQS Precalculation
8343 11:08:59.092080 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8344 11:08:59.092512 ==
8345 11:08:59.095380 Dram Type= 6, Freq= 0, CH_1, rank 0
8346 11:08:59.101799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8347 11:08:59.102215 ==
8348 11:08:59.105449 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8349 11:08:59.112358 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8350 11:08:59.115230 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8351 11:08:59.122040 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8352 11:08:59.130115 [CA 0] Center 43 (14~72) winsize 59
8353 11:08:59.133393 [CA 1] Center 42 (13~72) winsize 60
8354 11:08:59.135888 [CA 2] Center 37 (9~66) winsize 58
8355 11:08:59.139638 [CA 3] Center 37 (8~67) winsize 60
8356 11:08:59.142774 [CA 4] Center 38 (8~68) winsize 61
8357 11:08:59.146140 [CA 5] Center 37 (8~67) winsize 60
8358 11:08:59.146623
8359 11:08:59.149467 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8360 11:08:59.150026
8361 11:08:59.152681 [CATrainingPosCal] consider 1 rank data
8362 11:08:59.155749 u2DelayCellTimex100 = 262/100 ps
8363 11:08:59.162844 CA0 delay=43 (14~72),Diff = 6 PI (22 cell)
8364 11:08:59.166367 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8365 11:08:59.169663 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8366 11:08:59.172550 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8367 11:08:59.175999 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8368 11:08:59.178963 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8369 11:08:59.179420
8370 11:08:59.182122 CA PerBit enable=1, Macro0, CA PI delay=37
8371 11:08:59.182579
8372 11:08:59.185484 [CBTSetCACLKResult] CA Dly = 37
8373 11:08:59.189238 CS Dly: 10 (0~41)
8374 11:08:59.192060 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8375 11:08:59.195351 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8376 11:08:59.195814 ==
8377 11:08:59.198959 Dram Type= 6, Freq= 0, CH_1, rank 1
8378 11:08:59.205876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8379 11:08:59.206457 ==
8380 11:08:59.208707 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8381 11:08:59.215596 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8382 11:08:59.218421 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8383 11:08:59.224924 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8384 11:08:59.232980 [CA 0] Center 42 (13~72) winsize 60
8385 11:08:59.236571 [CA 1] Center 42 (13~72) winsize 60
8386 11:08:59.239484 [CA 2] Center 37 (8~67) winsize 60
8387 11:08:59.243154 [CA 3] Center 37 (8~66) winsize 59
8388 11:08:59.245972 [CA 4] Center 37 (8~67) winsize 60
8389 11:08:59.249794 [CA 5] Center 37 (8~67) winsize 60
8390 11:08:59.250350
8391 11:08:59.252742 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8392 11:08:59.253199
8393 11:08:59.256027 [CATrainingPosCal] consider 2 rank data
8394 11:08:59.259187 u2DelayCellTimex100 = 262/100 ps
8395 11:08:59.266483 CA0 delay=43 (14~72),Diff = 6 PI (22 cell)
8396 11:08:59.269423 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8397 11:08:59.272436 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8398 11:08:59.276059 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8399 11:08:59.279652 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8400 11:08:59.282237 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8401 11:08:59.282791
8402 11:08:59.285708 CA PerBit enable=1, Macro0, CA PI delay=37
8403 11:08:59.286266
8404 11:08:59.288962 [CBTSetCACLKResult] CA Dly = 37
8405 11:08:59.292830 CS Dly: 11 (0~43)
8406 11:08:59.295488 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8407 11:08:59.298727 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8408 11:08:59.299181
8409 11:08:59.302564 ----->DramcWriteLeveling(PI) begin...
8410 11:08:59.303123 ==
8411 11:08:59.306015 Dram Type= 6, Freq= 0, CH_1, rank 0
8412 11:08:59.311759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 11:08:59.312219 ==
8414 11:08:59.315748 Write leveling (Byte 0): 24 => 24
8415 11:08:59.318944 Write leveling (Byte 1): 25 => 25
8416 11:08:59.319504 DramcWriteLeveling(PI) end<-----
8417 11:08:59.322082
8418 11:08:59.322574 ==
8419 11:08:59.325363 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 11:08:59.328883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 11:08:59.329514 ==
8422 11:08:59.331488 [Gating] SW mode calibration
8423 11:08:59.338473 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8424 11:08:59.345526 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8425 11:08:59.347997 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 11:08:59.352134 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 11:08:59.357972 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 11:08:59.361853 1 4 12 | B1->B0 | 2727 3333 | 1 0 | (0 0) (1 1)
8429 11:08:59.364594 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8430 11:08:59.371342 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8431 11:08:59.374312 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8432 11:08:59.377767 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8433 11:08:59.384532 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8434 11:08:59.388128 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8435 11:08:59.390928 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8436 11:08:59.397368 1 5 12 | B1->B0 | 3131 2929 | 0 0 | (0 1) (0 1)
8437 11:08:59.400694 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 11:08:59.404281 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 11:08:59.411083 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8440 11:08:59.414073 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8441 11:08:59.416974 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8442 11:08:59.424166 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8443 11:08:59.427760 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8444 11:08:59.430068 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8445 11:08:59.436914 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8446 11:08:59.440141 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8447 11:08:59.443354 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 11:08:59.450164 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8449 11:08:59.453425 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8450 11:08:59.457030 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8451 11:08:59.463321 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8452 11:08:59.466311 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8453 11:08:59.469796 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8454 11:08:59.476320 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 11:08:59.479324 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 11:08:59.482881 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 11:08:59.489364 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 11:08:59.492579 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 11:08:59.496783 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 11:08:59.502793 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 11:08:59.505758 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 11:08:59.509504 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 11:08:59.515820 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 11:08:59.519381 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 11:08:59.522054 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 11:08:59.529031 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 11:08:59.532146 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8468 11:08:59.535568 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8469 11:08:59.542656 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8470 11:08:59.543107 Total UI for P1: 0, mck2ui 16
8471 11:08:59.549351 best dqsien dly found for B0: ( 1, 9, 12)
8472 11:08:59.549774 Total UI for P1: 0, mck2ui 16
8473 11:08:59.555417 best dqsien dly found for B1: ( 1, 9, 10)
8474 11:08:59.558482 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8475 11:08:59.562199 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8476 11:08:59.562762
8477 11:08:59.565166 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8478 11:08:59.568932 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8479 11:08:59.572094 [Gating] SW calibration Done
8480 11:08:59.572673 ==
8481 11:08:59.575402 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 11:08:59.578323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 11:08:59.578810 ==
8484 11:08:59.581576 RX Vref Scan: 0
8485 11:08:59.582040
8486 11:08:59.582410 RX Vref 0 -> 0, step: 1
8487 11:08:59.585523
8488 11:08:59.585985 RX Delay 0 -> 252, step: 8
8489 11:08:59.588849 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8490 11:08:59.594865 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8491 11:08:59.598564 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8492 11:08:59.601604 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8493 11:08:59.604928 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8494 11:08:59.608587 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8495 11:08:59.615237 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8496 11:08:59.617970 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8497 11:08:59.621717 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8498 11:08:59.624558 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8499 11:08:59.631318 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8500 11:08:59.635130 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8501 11:08:59.637701 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8502 11:08:59.641109 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8503 11:08:59.644384 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8504 11:08:59.650998 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8505 11:08:59.651561 ==
8506 11:08:59.654374 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 11:08:59.657208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 11:08:59.657692 ==
8509 11:08:59.658065 DQS Delay:
8510 11:08:59.660459 DQS0 = 0, DQS1 = 0
8511 11:08:59.660925 DQM Delay:
8512 11:08:59.664448 DQM0 = 137, DQM1 = 128
8513 11:08:59.664952 DQ Delay:
8514 11:08:59.667727 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =131
8515 11:08:59.670634 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8516 11:08:59.673918 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8517 11:08:59.680885 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8518 11:08:59.681442
8519 11:08:59.681810
8520 11:08:59.682150 ==
8521 11:08:59.683714 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 11:08:59.687314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 11:08:59.687931 ==
8524 11:08:59.688308
8525 11:08:59.688648
8526 11:08:59.691231 TX Vref Scan disable
8527 11:08:59.691840 == TX Byte 0 ==
8528 11:08:59.696763 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8529 11:08:59.700456 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8530 11:08:59.700915 == TX Byte 1 ==
8531 11:08:59.706635 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8532 11:08:59.709995 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8533 11:08:59.710495 ==
8534 11:08:59.713491 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 11:08:59.716757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 11:08:59.717193 ==
8537 11:08:59.730431
8538 11:08:59.733957 TX Vref early break, caculate TX vref
8539 11:08:59.737384 TX Vref=16, minBit 0, minWin=22, winSum=376
8540 11:08:59.740411 TX Vref=18, minBit 0, minWin=22, winSum=388
8541 11:08:59.743346 TX Vref=20, minBit 0, minWin=23, winSum=398
8542 11:08:59.747291 TX Vref=22, minBit 0, minWin=24, winSum=404
8543 11:08:59.750230 TX Vref=24, minBit 0, minWin=24, winSum=416
8544 11:08:59.756776 TX Vref=26, minBit 0, minWin=25, winSum=422
8545 11:08:59.759657 TX Vref=28, minBit 0, minWin=25, winSum=422
8546 11:08:59.763446 TX Vref=30, minBit 5, minWin=24, winSum=415
8547 11:08:59.767108 TX Vref=32, minBit 1, minWin=24, winSum=406
8548 11:08:59.770602 TX Vref=34, minBit 5, minWin=23, winSum=396
8549 11:08:59.777065 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 26
8550 11:08:59.777530
8551 11:08:59.779721 Final TX Range 0 Vref 26
8552 11:08:59.780388
8553 11:08:59.780798 ==
8554 11:08:59.782746 Dram Type= 6, Freq= 0, CH_1, rank 0
8555 11:08:59.786447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8556 11:08:59.786908 ==
8557 11:08:59.787275
8558 11:08:59.787611
8559 11:08:59.789673 TX Vref Scan disable
8560 11:08:59.796265 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8561 11:08:59.796681 == TX Byte 0 ==
8562 11:08:59.799356 u2DelayCellOfst[0]=18 cells (5 PI)
8563 11:08:59.803043 u2DelayCellOfst[1]=11 cells (3 PI)
8564 11:08:59.806037 u2DelayCellOfst[2]=0 cells (0 PI)
8565 11:08:59.809611 u2DelayCellOfst[3]=3 cells (1 PI)
8566 11:08:59.813158 u2DelayCellOfst[4]=7 cells (2 PI)
8567 11:08:59.816609 u2DelayCellOfst[5]=22 cells (6 PI)
8568 11:08:59.819649 u2DelayCellOfst[6]=18 cells (5 PI)
8569 11:08:59.823331 u2DelayCellOfst[7]=7 cells (2 PI)
8570 11:08:59.826278 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8571 11:08:59.829130 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8572 11:08:59.833041 == TX Byte 1 ==
8573 11:08:59.836615 u2DelayCellOfst[8]=0 cells (0 PI)
8574 11:08:59.837138 u2DelayCellOfst[9]=3 cells (1 PI)
8575 11:08:59.839297 u2DelayCellOfst[10]=11 cells (3 PI)
8576 11:08:59.842558 u2DelayCellOfst[11]=7 cells (2 PI)
8577 11:08:59.846078 u2DelayCellOfst[12]=18 cells (5 PI)
8578 11:08:59.849361 u2DelayCellOfst[13]=18 cells (5 PI)
8579 11:08:59.852305 u2DelayCellOfst[14]=18 cells (5 PI)
8580 11:08:59.855396 u2DelayCellOfst[15]=18 cells (5 PI)
8581 11:08:59.862251 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8582 11:08:59.865920 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8583 11:08:59.866434 DramC Write-DBI on
8584 11:08:59.866764 ==
8585 11:08:59.868772 Dram Type= 6, Freq= 0, CH_1, rank 0
8586 11:08:59.875265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8587 11:08:59.875826 ==
8588 11:08:59.876167
8589 11:08:59.876472
8590 11:08:59.878996 TX Vref Scan disable
8591 11:08:59.879409 == TX Byte 0 ==
8592 11:08:59.884848 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8593 11:08:59.885479 == TX Byte 1 ==
8594 11:08:59.888865 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8595 11:08:59.891489 DramC Write-DBI off
8596 11:08:59.892116
8597 11:08:59.892473 [DATLAT]
8598 11:08:59.895058 Freq=1600, CH1 RK0
8599 11:08:59.895487
8600 11:08:59.895886 DATLAT Default: 0xf
8601 11:08:59.898265 0, 0xFFFF, sum = 0
8602 11:08:59.898722 1, 0xFFFF, sum = 0
8603 11:08:59.901734 2, 0xFFFF, sum = 0
8604 11:08:59.902273 3, 0xFFFF, sum = 0
8605 11:08:59.904969 4, 0xFFFF, sum = 0
8606 11:08:59.905391 5, 0xFFFF, sum = 0
8607 11:08:59.908383 6, 0xFFFF, sum = 0
8608 11:08:59.908921 7, 0xFFFF, sum = 0
8609 11:08:59.912255 8, 0xFFFF, sum = 0
8610 11:08:59.912677 9, 0xFFFF, sum = 0
8611 11:08:59.915007 10, 0xFFFF, sum = 0
8612 11:08:59.918145 11, 0xFFFF, sum = 0
8613 11:08:59.918564 12, 0xFFFF, sum = 0
8614 11:08:59.921818 13, 0xFFFF, sum = 0
8615 11:08:59.922238 14, 0x0, sum = 1
8616 11:08:59.924618 15, 0x0, sum = 2
8617 11:08:59.925039 16, 0x0, sum = 3
8618 11:08:59.928057 17, 0x0, sum = 4
8619 11:08:59.928484 best_step = 15
8620 11:08:59.928814
8621 11:08:59.929121 ==
8622 11:08:59.931448 Dram Type= 6, Freq= 0, CH_1, rank 0
8623 11:08:59.934734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8624 11:08:59.935149 ==
8625 11:08:59.938293 RX Vref Scan: 1
8626 11:08:59.938788
8627 11:08:59.941270 Set Vref Range= 24 -> 127
8628 11:08:59.941788
8629 11:08:59.942122 RX Vref 24 -> 127, step: 1
8630 11:08:59.944633
8631 11:08:59.945185 RX Delay 11 -> 252, step: 4
8632 11:08:59.945521
8633 11:08:59.947851 Set Vref, RX VrefLevel [Byte0]: 24
8634 11:08:59.951374 [Byte1]: 24
8635 11:08:59.955149
8636 11:08:59.955665 Set Vref, RX VrefLevel [Byte0]: 25
8637 11:08:59.958164 [Byte1]: 25
8638 11:08:59.962567
8639 11:08:59.962981 Set Vref, RX VrefLevel [Byte0]: 26
8640 11:08:59.965927 [Byte1]: 26
8641 11:08:59.970304
8642 11:08:59.970716 Set Vref, RX VrefLevel [Byte0]: 27
8643 11:08:59.973102 [Byte1]: 27
8644 11:08:59.978220
8645 11:08:59.978734 Set Vref, RX VrefLevel [Byte0]: 28
8646 11:08:59.981135 [Byte1]: 28
8647 11:08:59.985229
8648 11:08:59.985743 Set Vref, RX VrefLevel [Byte0]: 29
8649 11:08:59.988677 [Byte1]: 29
8650 11:08:59.993189
8651 11:08:59.996323 Set Vref, RX VrefLevel [Byte0]: 30
8652 11:08:59.998953 [Byte1]: 30
8653 11:08:59.999374
8654 11:09:00.002234 Set Vref, RX VrefLevel [Byte0]: 31
8655 11:09:00.005497 [Byte1]: 31
8656 11:09:00.005914
8657 11:09:00.008859 Set Vref, RX VrefLevel [Byte0]: 32
8658 11:09:00.012344 [Byte1]: 32
8659 11:09:00.015767
8660 11:09:00.016180 Set Vref, RX VrefLevel [Byte0]: 33
8661 11:09:00.018943 [Byte1]: 33
8662 11:09:00.023614
8663 11:09:00.024068 Set Vref, RX VrefLevel [Byte0]: 34
8664 11:09:00.026848 [Byte1]: 34
8665 11:09:00.030638
8666 11:09:00.031052 Set Vref, RX VrefLevel [Byte0]: 35
8667 11:09:00.034010 [Byte1]: 35
8668 11:09:00.038410
8669 11:09:00.038822 Set Vref, RX VrefLevel [Byte0]: 36
8670 11:09:00.042168 [Byte1]: 36
8671 11:09:00.046024
8672 11:09:00.046439 Set Vref, RX VrefLevel [Byte0]: 37
8673 11:09:00.049346 [Byte1]: 37
8674 11:09:00.053719
8675 11:09:00.054131 Set Vref, RX VrefLevel [Byte0]: 38
8676 11:09:00.056789 [Byte1]: 38
8677 11:09:00.061351
8678 11:09:00.061776 Set Vref, RX VrefLevel [Byte0]: 39
8679 11:09:00.064979 [Byte1]: 39
8680 11:09:00.069292
8681 11:09:00.069858 Set Vref, RX VrefLevel [Byte0]: 40
8682 11:09:00.072497 [Byte1]: 40
8683 11:09:00.076850
8684 11:09:00.077410 Set Vref, RX VrefLevel [Byte0]: 41
8685 11:09:00.080229 [Byte1]: 41
8686 11:09:00.084013
8687 11:09:00.084497 Set Vref, RX VrefLevel [Byte0]: 42
8688 11:09:00.087781 [Byte1]: 42
8689 11:09:00.092014
8690 11:09:00.095625 Set Vref, RX VrefLevel [Byte0]: 43
8691 11:09:00.097981 [Byte1]: 43
8692 11:09:00.098443
8693 11:09:00.101514 Set Vref, RX VrefLevel [Byte0]: 44
8694 11:09:00.104990 [Byte1]: 44
8695 11:09:00.105550
8696 11:09:00.107821 Set Vref, RX VrefLevel [Byte0]: 45
8697 11:09:00.111169 [Byte1]: 45
8698 11:09:00.114377
8699 11:09:00.114835 Set Vref, RX VrefLevel [Byte0]: 46
8700 11:09:00.117988 [Byte1]: 46
8701 11:09:00.122215
8702 11:09:00.122721 Set Vref, RX VrefLevel [Byte0]: 47
8703 11:09:00.126102 [Byte1]: 47
8704 11:09:00.130555
8705 11:09:00.131129 Set Vref, RX VrefLevel [Byte0]: 48
8706 11:09:00.133236 [Byte1]: 48
8707 11:09:00.137622
8708 11:09:00.138180 Set Vref, RX VrefLevel [Byte0]: 49
8709 11:09:00.140669 [Byte1]: 49
8710 11:09:00.145030
8711 11:09:00.145592 Set Vref, RX VrefLevel [Byte0]: 50
8712 11:09:00.148251 [Byte1]: 50
8713 11:09:00.152729
8714 11:09:00.153190 Set Vref, RX VrefLevel [Byte0]: 51
8715 11:09:00.155725 [Byte1]: 51
8716 11:09:00.160640
8717 11:09:00.161221 Set Vref, RX VrefLevel [Byte0]: 52
8718 11:09:00.163827 [Byte1]: 52
8719 11:09:00.167870
8720 11:09:00.168426 Set Vref, RX VrefLevel [Byte0]: 53
8721 11:09:00.171250 [Byte1]: 53
8722 11:09:00.176134
8723 11:09:00.176691 Set Vref, RX VrefLevel [Byte0]: 54
8724 11:09:00.179472 [Byte1]: 54
8725 11:09:00.183141
8726 11:09:00.183753 Set Vref, RX VrefLevel [Byte0]: 55
8727 11:09:00.186587 [Byte1]: 55
8728 11:09:00.190532
8729 11:09:00.190996 Set Vref, RX VrefLevel [Byte0]: 56
8730 11:09:00.194278 [Byte1]: 56
8731 11:09:00.198817
8732 11:09:00.199317 Set Vref, RX VrefLevel [Byte0]: 57
8733 11:09:00.201389 [Byte1]: 57
8734 11:09:00.206267
8735 11:09:00.206830 Set Vref, RX VrefLevel [Byte0]: 58
8736 11:09:00.209182 [Byte1]: 58
8737 11:09:00.213501
8738 11:09:00.214057 Set Vref, RX VrefLevel [Byte0]: 59
8739 11:09:00.217447 [Byte1]: 59
8740 11:09:00.221168
8741 11:09:00.221632 Set Vref, RX VrefLevel [Byte0]: 60
8742 11:09:00.224774 [Byte1]: 60
8743 11:09:00.228579
8744 11:09:00.229039 Set Vref, RX VrefLevel [Byte0]: 61
8745 11:09:00.232137 [Byte1]: 61
8746 11:09:00.236228
8747 11:09:00.236641 Set Vref, RX VrefLevel [Byte0]: 62
8748 11:09:00.239556 [Byte1]: 62
8749 11:09:00.244264
8750 11:09:00.244783 Set Vref, RX VrefLevel [Byte0]: 63
8751 11:09:00.247514 [Byte1]: 63
8752 11:09:00.251483
8753 11:09:00.251989 Set Vref, RX VrefLevel [Byte0]: 64
8754 11:09:00.255476 [Byte1]: 64
8755 11:09:00.259093
8756 11:09:00.259515 Set Vref, RX VrefLevel [Byte0]: 65
8757 11:09:00.262458 [Byte1]: 65
8758 11:09:00.266885
8759 11:09:00.267304 Set Vref, RX VrefLevel [Byte0]: 66
8760 11:09:00.270499 [Byte1]: 66
8761 11:09:00.275187
8762 11:09:00.275734 Set Vref, RX VrefLevel [Byte0]: 67
8763 11:09:00.277825 [Byte1]: 67
8764 11:09:00.282083
8765 11:09:00.282601 Set Vref, RX VrefLevel [Byte0]: 68
8766 11:09:00.285971 [Byte1]: 68
8767 11:09:00.289846
8768 11:09:00.290382 Set Vref, RX VrefLevel [Byte0]: 69
8769 11:09:00.292855 [Byte1]: 69
8770 11:09:00.297618
8771 11:09:00.298185 Set Vref, RX VrefLevel [Byte0]: 70
8772 11:09:00.300325 [Byte1]: 70
8773 11:09:00.305075
8774 11:09:00.305493 Set Vref, RX VrefLevel [Byte0]: 71
8775 11:09:00.308005 [Byte1]: 71
8776 11:09:00.312448
8777 11:09:00.312864 Set Vref, RX VrefLevel [Byte0]: 72
8778 11:09:00.316192 [Byte1]: 72
8779 11:09:00.320382
8780 11:09:00.320795 Set Vref, RX VrefLevel [Byte0]: 73
8781 11:09:00.323194 [Byte1]: 73
8782 11:09:00.328102
8783 11:09:00.328514 Final RX Vref Byte 0 = 53 to rank0
8784 11:09:00.330926 Final RX Vref Byte 1 = 59 to rank0
8785 11:09:00.334587 Final RX Vref Byte 0 = 53 to rank1
8786 11:09:00.338140 Final RX Vref Byte 1 = 59 to rank1==
8787 11:09:00.340973 Dram Type= 6, Freq= 0, CH_1, rank 0
8788 11:09:00.347854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8789 11:09:00.348405 ==
8790 11:09:00.348777 DQS Delay:
8791 11:09:00.351114 DQS0 = 0, DQS1 = 0
8792 11:09:00.351570 DQM Delay:
8793 11:09:00.351994 DQM0 = 133, DQM1 = 127
8794 11:09:00.354133 DQ Delay:
8795 11:09:00.357259 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =128
8796 11:09:00.360937 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8797 11:09:00.363713 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8798 11:09:00.367309 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8799 11:09:00.367750
8800 11:09:00.368080
8801 11:09:00.368383
8802 11:09:00.370901 [DramC_TX_OE_Calibration] TA2
8803 11:09:00.374206 Original DQ_B0 (3 6) =30, OEN = 27
8804 11:09:00.377269 Original DQ_B1 (3 6) =30, OEN = 27
8805 11:09:00.381027 24, 0x0, End_B0=24 End_B1=24
8806 11:09:00.383588 25, 0x0, End_B0=25 End_B1=25
8807 11:09:00.384116 26, 0x0, End_B0=26 End_B1=26
8808 11:09:00.387167 27, 0x0, End_B0=27 End_B1=27
8809 11:09:00.390396 28, 0x0, End_B0=28 End_B1=28
8810 11:09:00.394178 29, 0x0, End_B0=29 End_B1=29
8811 11:09:00.394601 30, 0x0, End_B0=30 End_B1=30
8812 11:09:00.397029 31, 0x4141, End_B0=30 End_B1=30
8813 11:09:00.400091 Byte0 end_step=30 best_step=27
8814 11:09:00.403456 Byte1 end_step=30 best_step=27
8815 11:09:00.407280 Byte0 TX OE(2T, 0.5T) = (3, 3)
8816 11:09:00.410292 Byte1 TX OE(2T, 0.5T) = (3, 3)
8817 11:09:00.410708
8818 11:09:00.411035
8819 11:09:00.416939 [DQSOSCAuto] RK0, (LSB)MR18= 0x150a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
8820 11:09:00.419763 CH1 RK0: MR19=303, MR18=150A
8821 11:09:00.426912 CH1_RK0: MR19=0x303, MR18=0x150A, DQSOSC=399, MR23=63, INC=23, DEC=15
8822 11:09:00.427443
8823 11:09:00.430475 ----->DramcWriteLeveling(PI) begin...
8824 11:09:00.431007 ==
8825 11:09:00.433057 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 11:09:00.436280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 11:09:00.436698 ==
8828 11:09:00.439868 Write leveling (Byte 0): 23 => 23
8829 11:09:00.443410 Write leveling (Byte 1): 27 => 27
8830 11:09:00.446151 DramcWriteLeveling(PI) end<-----
8831 11:09:00.446567
8832 11:09:00.446892 ==
8833 11:09:00.449619 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 11:09:00.453314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 11:09:00.456603 ==
8836 11:09:00.457125 [Gating] SW mode calibration
8837 11:09:00.466552 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8838 11:09:00.470169 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8839 11:09:00.472725 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 11:09:00.479021 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 11:09:00.482146 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8842 11:09:00.485875 1 4 12 | B1->B0 | 3231 2323 | 1 0 | (0 0) (0 0)
8843 11:09:00.492431 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8844 11:09:00.495899 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8845 11:09:00.498959 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8846 11:09:00.505277 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8847 11:09:00.508771 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8848 11:09:00.511838 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8849 11:09:00.519522 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8850 11:09:00.522275 1 5 12 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8851 11:09:00.525501 1 5 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
8852 11:09:00.532095 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8853 11:09:00.535920 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8854 11:09:00.538907 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8855 11:09:00.545544 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8856 11:09:00.549429 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8857 11:09:00.551542 1 6 8 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
8858 11:09:00.558014 1 6 12 | B1->B0 | 4646 2424 | 0 0 | (0 0) (0 0)
8859 11:09:00.561888 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8860 11:09:00.565401 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8861 11:09:00.571718 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8862 11:09:00.574762 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8863 11:09:00.578174 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8864 11:09:00.584578 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8865 11:09:00.587881 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 11:09:00.591098 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8867 11:09:00.597562 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8868 11:09:00.601449 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 11:09:00.604068 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 11:09:00.610911 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 11:09:00.614186 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 11:09:00.617395 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 11:09:00.624341 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 11:09:00.627465 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 11:09:00.634584 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 11:09:00.637311 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 11:09:00.640630 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 11:09:00.647075 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 11:09:00.650250 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 11:09:00.653781 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 11:09:00.660242 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8882 11:09:00.663354 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8883 11:09:00.666881 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8884 11:09:00.670192 Total UI for P1: 0, mck2ui 16
8885 11:09:00.673520 best dqsien dly found for B0: ( 1, 9, 12)
8886 11:09:00.677091 Total UI for P1: 0, mck2ui 16
8887 11:09:00.679838 best dqsien dly found for B1: ( 1, 9, 10)
8888 11:09:00.683495 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8889 11:09:00.686959 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8890 11:09:00.687418
8891 11:09:00.693615 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8892 11:09:00.696633 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8893 11:09:00.699969 [Gating] SW calibration Done
8894 11:09:00.700429 ==
8895 11:09:00.703307 Dram Type= 6, Freq= 0, CH_1, rank 1
8896 11:09:00.706715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8897 11:09:00.707273 ==
8898 11:09:00.707642 RX Vref Scan: 0
8899 11:09:00.708052
8900 11:09:00.709985 RX Vref 0 -> 0, step: 1
8901 11:09:00.710561
8902 11:09:00.713183 RX Delay 0 -> 252, step: 8
8903 11:09:00.715961 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8904 11:09:00.719447 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8905 11:09:00.726281 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8906 11:09:00.729722 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8907 11:09:00.732592 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8908 11:09:00.735871 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8909 11:09:00.739002 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8910 11:09:00.745983 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8911 11:09:00.749038 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8912 11:09:00.752376 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8913 11:09:00.755876 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8914 11:09:00.759403 iDelay=208, Bit 11, Center 119 (56 ~ 183) 128
8915 11:09:00.766171 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8916 11:09:00.768935 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8917 11:09:00.771918 iDelay=208, Bit 14, Center 131 (72 ~ 191) 120
8918 11:09:00.775780 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8919 11:09:00.776208 ==
8920 11:09:00.778677 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 11:09:00.785385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 11:09:00.785885 ==
8923 11:09:00.786216 DQS Delay:
8924 11:09:00.788544 DQS0 = 0, DQS1 = 0
8925 11:09:00.789059 DQM Delay:
8926 11:09:00.792178 DQM0 = 137, DQM1 = 128
8927 11:09:00.792694 DQ Delay:
8928 11:09:00.795291 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8929 11:09:00.798508 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8930 11:09:00.801914 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8931 11:09:00.805210 DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =139
8932 11:09:00.805727
8933 11:09:00.806243
8934 11:09:00.806574 ==
8935 11:09:00.808185 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 11:09:00.814971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 11:09:00.815427 ==
8938 11:09:00.815810
8939 11:09:00.816128
8940 11:09:00.816443 TX Vref Scan disable
8941 11:09:00.818381 == TX Byte 0 ==
8942 11:09:00.821552 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8943 11:09:00.828389 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8944 11:09:00.828906 == TX Byte 1 ==
8945 11:09:00.831972 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8946 11:09:00.838175 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8947 11:09:00.838698 ==
8948 11:09:00.841648 Dram Type= 6, Freq= 0, CH_1, rank 1
8949 11:09:00.844889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8950 11:09:00.845618 ==
8951 11:09:00.858088
8952 11:09:00.861343 TX Vref early break, caculate TX vref
8953 11:09:00.864338 TX Vref=16, minBit 0, minWin=22, winSum=376
8954 11:09:00.868082 TX Vref=18, minBit 0, minWin=23, winSum=389
8955 11:09:00.870860 TX Vref=20, minBit 0, minWin=23, winSum=396
8956 11:09:00.874082 TX Vref=22, minBit 1, minWin=23, winSum=404
8957 11:09:00.877656 TX Vref=24, minBit 5, minWin=23, winSum=409
8958 11:09:00.883768 TX Vref=26, minBit 0, minWin=24, winSum=415
8959 11:09:00.887448 TX Vref=28, minBit 0, minWin=24, winSum=418
8960 11:09:00.890787 TX Vref=30, minBit 0, minWin=24, winSum=411
8961 11:09:00.894059 TX Vref=32, minBit 0, minWin=24, winSum=408
8962 11:09:00.896987 TX Vref=34, minBit 0, minWin=22, winSum=395
8963 11:09:00.903606 [TxChooseVref] Worse bit 0, Min win 24, Win sum 418, Final Vref 28
8964 11:09:00.904121
8965 11:09:00.906713 Final TX Range 0 Vref 28
8966 11:09:00.907191
8967 11:09:00.907645 ==
8968 11:09:00.910072 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 11:09:00.913321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 11:09:00.913796 ==
8971 11:09:00.914223
8972 11:09:00.914593
8973 11:09:00.916946 TX Vref Scan disable
8974 11:09:00.923152 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8975 11:09:00.923620 == TX Byte 0 ==
8976 11:09:00.926717 u2DelayCellOfst[0]=22 cells (6 PI)
8977 11:09:00.930011 u2DelayCellOfst[1]=14 cells (4 PI)
8978 11:09:00.933306 u2DelayCellOfst[2]=0 cells (0 PI)
8979 11:09:00.937039 u2DelayCellOfst[3]=11 cells (3 PI)
8980 11:09:00.939637 u2DelayCellOfst[4]=11 cells (3 PI)
8981 11:09:00.943372 u2DelayCellOfst[5]=26 cells (7 PI)
8982 11:09:00.946273 u2DelayCellOfst[6]=22 cells (6 PI)
8983 11:09:00.950008 u2DelayCellOfst[7]=7 cells (2 PI)
8984 11:09:00.953051 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8985 11:09:00.956426 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8986 11:09:00.959406 == TX Byte 1 ==
8987 11:09:00.962821 u2DelayCellOfst[8]=0 cells (0 PI)
8988 11:09:00.966464 u2DelayCellOfst[9]=3 cells (1 PI)
8989 11:09:00.969536 u2DelayCellOfst[10]=11 cells (3 PI)
8990 11:09:00.970038 u2DelayCellOfst[11]=3 cells (1 PI)
8991 11:09:00.972723 u2DelayCellOfst[12]=14 cells (4 PI)
8992 11:09:00.975923 u2DelayCellOfst[13]=14 cells (4 PI)
8993 11:09:00.979327 u2DelayCellOfst[14]=14 cells (4 PI)
8994 11:09:00.982908 u2DelayCellOfst[15]=14 cells (4 PI)
8995 11:09:00.989726 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8996 11:09:00.992813 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8997 11:09:00.993369 DramC Write-DBI on
8998 11:09:00.995999 ==
8999 11:09:00.998995 Dram Type= 6, Freq= 0, CH_1, rank 1
9000 11:09:01.002456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9001 11:09:01.002922 ==
9002 11:09:01.003306
9003 11:09:01.003642
9004 11:09:01.005899 TX Vref Scan disable
9005 11:09:01.006404 == TX Byte 0 ==
9006 11:09:01.012698 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9007 11:09:01.013155 == TX Byte 1 ==
9008 11:09:01.015640 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9009 11:09:01.019034 DramC Write-DBI off
9010 11:09:01.019450
9011 11:09:01.019827 [DATLAT]
9012 11:09:01.022254 Freq=1600, CH1 RK1
9013 11:09:01.022776
9014 11:09:01.023107 DATLAT Default: 0xf
9015 11:09:01.025604 0, 0xFFFF, sum = 0
9016 11:09:01.026029 1, 0xFFFF, sum = 0
9017 11:09:01.028891 2, 0xFFFF, sum = 0
9018 11:09:01.029311 3, 0xFFFF, sum = 0
9019 11:09:01.032187 4, 0xFFFF, sum = 0
9020 11:09:01.032610 5, 0xFFFF, sum = 0
9021 11:09:01.035630 6, 0xFFFF, sum = 0
9022 11:09:01.036173 7, 0xFFFF, sum = 0
9023 11:09:01.038847 8, 0xFFFF, sum = 0
9024 11:09:01.041908 9, 0xFFFF, sum = 0
9025 11:09:01.042333 10, 0xFFFF, sum = 0
9026 11:09:01.045300 11, 0xFFFF, sum = 0
9027 11:09:01.045720 12, 0xFFFF, sum = 0
9028 11:09:01.048884 13, 0xFFFF, sum = 0
9029 11:09:01.049363 14, 0x0, sum = 1
9030 11:09:01.051755 15, 0x0, sum = 2
9031 11:09:01.052184 16, 0x0, sum = 3
9032 11:09:01.055039 17, 0x0, sum = 4
9033 11:09:01.055569 best_step = 15
9034 11:09:01.055973
9035 11:09:01.056284 ==
9036 11:09:01.058547 Dram Type= 6, Freq= 0, CH_1, rank 1
9037 11:09:01.061804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9038 11:09:01.065704 ==
9039 11:09:01.066220 RX Vref Scan: 0
9040 11:09:01.066553
9041 11:09:01.068520 RX Vref 0 -> 0, step: 1
9042 11:09:01.068935
9043 11:09:01.069263 RX Delay 11 -> 252, step: 4
9044 11:09:01.076215 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9045 11:09:01.079613 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9046 11:09:01.083111 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9047 11:09:01.085805 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9048 11:09:01.092105 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9049 11:09:01.095759 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9050 11:09:01.098522 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9051 11:09:01.102868 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9052 11:09:01.106561 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9053 11:09:01.113029 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9054 11:09:01.114684 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9055 11:09:01.118601 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9056 11:09:01.121732 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9057 11:09:01.127857 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9058 11:09:01.132022 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9059 11:09:01.135035 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9060 11:09:01.135564 ==
9061 11:09:01.138193 Dram Type= 6, Freq= 0, CH_1, rank 1
9062 11:09:01.141559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9063 11:09:01.142083 ==
9064 11:09:01.144784 DQS Delay:
9065 11:09:01.145349 DQS0 = 0, DQS1 = 0
9066 11:09:01.147984 DQM Delay:
9067 11:09:01.148569 DQM0 = 134, DQM1 = 126
9068 11:09:01.150971 DQ Delay:
9069 11:09:01.154392 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9070 11:09:01.157894 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9071 11:09:01.161073 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9072 11:09:01.164846 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =138
9073 11:09:01.165413
9074 11:09:01.165779
9075 11:09:01.166118
9076 11:09:01.167636 [DramC_TX_OE_Calibration] TA2
9077 11:09:01.171110 Original DQ_B0 (3 6) =30, OEN = 27
9078 11:09:01.174594 Original DQ_B1 (3 6) =30, OEN = 27
9079 11:09:01.178161 24, 0x0, End_B0=24 End_B1=24
9080 11:09:01.178734 25, 0x0, End_B0=25 End_B1=25
9081 11:09:01.180803 26, 0x0, End_B0=26 End_B1=26
9082 11:09:01.184244 27, 0x0, End_B0=27 End_B1=27
9083 11:09:01.187182 28, 0x0, End_B0=28 End_B1=28
9084 11:09:01.187652 29, 0x0, End_B0=29 End_B1=29
9085 11:09:01.190534 30, 0x0, End_B0=30 End_B1=30
9086 11:09:01.193960 31, 0x4545, End_B0=30 End_B1=30
9087 11:09:01.197076 Byte0 end_step=30 best_step=27
9088 11:09:01.200147 Byte1 end_step=30 best_step=27
9089 11:09:01.203873 Byte0 TX OE(2T, 0.5T) = (3, 3)
9090 11:09:01.207180 Byte1 TX OE(2T, 0.5T) = (3, 3)
9091 11:09:01.207600
9092 11:09:01.207990
9093 11:09:01.213242 [DQSOSCAuto] RK1, (LSB)MR18= 0xa08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 404 ps
9094 11:09:01.217045 CH1 RK1: MR19=303, MR18=A08
9095 11:09:01.223551 CH1_RK1: MR19=0x303, MR18=0xA08, DQSOSC=404, MR23=63, INC=22, DEC=15
9096 11:09:01.227379 [RxdqsGatingPostProcess] freq 1600
9097 11:09:01.230291 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9098 11:09:01.233070 best DQS0 dly(2T, 0.5T) = (1, 1)
9099 11:09:01.237402 best DQS1 dly(2T, 0.5T) = (1, 1)
9100 11:09:01.240027 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9101 11:09:01.243368 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9102 11:09:01.246058 best DQS0 dly(2T, 0.5T) = (1, 1)
9103 11:09:01.249259 best DQS1 dly(2T, 0.5T) = (1, 1)
9104 11:09:01.252874 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9105 11:09:01.256542 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9106 11:09:01.259264 Pre-setting of DQS Precalculation
9107 11:09:01.263061 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9108 11:09:01.269553 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9109 11:09:01.279883 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9110 11:09:01.280644
9111 11:09:01.281048
9112 11:09:01.282879 [Calibration Summary] 3200 Mbps
9113 11:09:01.283447 CH 0, Rank 0
9114 11:09:01.285666 SW Impedance : PASS
9115 11:09:01.286131 DUTY Scan : NO K
9116 11:09:01.289131 ZQ Calibration : PASS
9117 11:09:01.292654 Jitter Meter : NO K
9118 11:09:01.293222 CBT Training : PASS
9119 11:09:01.295477 Write leveling : PASS
9120 11:09:01.298829 RX DQS gating : PASS
9121 11:09:01.299320 RX DQ/DQS(RDDQC) : PASS
9122 11:09:01.301883 TX DQ/DQS : PASS
9123 11:09:01.305397 RX DATLAT : PASS
9124 11:09:01.305973 RX DQ/DQS(Engine): PASS
9125 11:09:01.308531 TX OE : PASS
9126 11:09:01.309003 All Pass.
9127 11:09:01.309372
9128 11:09:01.312105 CH 0, Rank 1
9129 11:09:01.312577 SW Impedance : PASS
9130 11:09:01.315644 DUTY Scan : NO K
9131 11:09:01.316213 ZQ Calibration : PASS
9132 11:09:01.318395 Jitter Meter : NO K
9133 11:09:01.322082 CBT Training : PASS
9134 11:09:01.322502 Write leveling : PASS
9135 11:09:01.325248 RX DQS gating : PASS
9136 11:09:01.328382 RX DQ/DQS(RDDQC) : PASS
9137 11:09:01.328809 TX DQ/DQS : PASS
9138 11:09:01.331974 RX DATLAT : PASS
9139 11:09:01.335782 RX DQ/DQS(Engine): PASS
9140 11:09:01.336307 TX OE : PASS
9141 11:09:01.338562 All Pass.
9142 11:09:01.339082
9143 11:09:01.339419 CH 1, Rank 0
9144 11:09:01.342080 SW Impedance : PASS
9145 11:09:01.342602 DUTY Scan : NO K
9146 11:09:01.345070 ZQ Calibration : PASS
9147 11:09:01.348386 Jitter Meter : NO K
9148 11:09:01.348851 CBT Training : PASS
9149 11:09:01.351715 Write leveling : PASS
9150 11:09:01.355144 RX DQS gating : PASS
9151 11:09:01.355813 RX DQ/DQS(RDDQC) : PASS
9152 11:09:01.358334 TX DQ/DQS : PASS
9153 11:09:01.361289 RX DATLAT : PASS
9154 11:09:01.361805 RX DQ/DQS(Engine): PASS
9155 11:09:01.365349 TX OE : PASS
9156 11:09:01.365816 All Pass.
9157 11:09:01.366184
9158 11:09:01.368220 CH 1, Rank 1
9159 11:09:01.368646 SW Impedance : PASS
9160 11:09:01.371770 DUTY Scan : NO K
9161 11:09:01.374915 ZQ Calibration : PASS
9162 11:09:01.375349 Jitter Meter : NO K
9163 11:09:01.378181 CBT Training : PASS
9164 11:09:01.381042 Write leveling : PASS
9165 11:09:01.381469 RX DQS gating : PASS
9166 11:09:01.384567 RX DQ/DQS(RDDQC) : PASS
9167 11:09:01.384991 TX DQ/DQS : PASS
9168 11:09:01.388151 RX DATLAT : PASS
9169 11:09:01.391192 RX DQ/DQS(Engine): PASS
9170 11:09:01.391613 TX OE : PASS
9171 11:09:01.394566 All Pass.
9172 11:09:01.395095
9173 11:09:01.395432 DramC Write-DBI on
9174 11:09:01.398318 PER_BANK_REFRESH: Hybrid Mode
9175 11:09:01.401284 TX_TRACKING: ON
9176 11:09:01.407647 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9177 11:09:01.417600 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9178 11:09:01.424424 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9179 11:09:01.427324 [FAST_K] Save calibration result to emmc
9180 11:09:01.431013 sync common calibartion params.
9181 11:09:01.434347 sync cbt_mode0:1, 1:1
9182 11:09:01.434919 dram_init: ddr_geometry: 2
9183 11:09:01.437227 dram_init: ddr_geometry: 2
9184 11:09:01.440543 dram_init: ddr_geometry: 2
9185 11:09:01.441110 0:dram_rank_size:100000000
9186 11:09:01.444085 1:dram_rank_size:100000000
9187 11:09:01.450393 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9188 11:09:01.454202 DFS_SHUFFLE_HW_MODE: ON
9189 11:09:01.456982 dramc_set_vcore_voltage set vcore to 725000
9190 11:09:01.457547 Read voltage for 1600, 0
9191 11:09:01.460355 Vio18 = 0
9192 11:09:01.460821 Vcore = 725000
9193 11:09:01.461190 Vdram = 0
9194 11:09:01.463862 Vddq = 0
9195 11:09:01.464328 Vmddr = 0
9196 11:09:01.466720 switch to 3200 Mbps bootup
9197 11:09:01.467186 [DramcRunTimeConfig]
9198 11:09:01.467553 PHYPLL
9199 11:09:01.470570 DPM_CONTROL_AFTERK: ON
9200 11:09:01.473589 PER_BANK_REFRESH: ON
9201 11:09:01.476760 REFRESH_OVERHEAD_REDUCTION: ON
9202 11:09:01.477331 CMD_PICG_NEW_MODE: OFF
9203 11:09:01.480387 XRTWTW_NEW_MODE: ON
9204 11:09:01.480856 XRTRTR_NEW_MODE: ON
9205 11:09:01.483559 TX_TRACKING: ON
9206 11:09:01.484171 RDSEL_TRACKING: OFF
9207 11:09:01.486741 DQS Precalculation for DVFS: ON
9208 11:09:01.489716 RX_TRACKING: OFF
9209 11:09:01.490183 HW_GATING DBG: ON
9210 11:09:01.493169 ZQCS_ENABLE_LP4: ON
9211 11:09:01.493741 RX_PICG_NEW_MODE: ON
9212 11:09:01.496871 TX_PICG_NEW_MODE: ON
9213 11:09:01.497442 ENABLE_RX_DCM_DPHY: ON
9214 11:09:01.499796 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9215 11:09:01.503081 DUMMY_READ_FOR_TRACKING: OFF
9216 11:09:01.506777 !!! SPM_CONTROL_AFTERK: OFF
9217 11:09:01.509501 !!! SPM could not control APHY
9218 11:09:01.509966 IMPEDANCE_TRACKING: ON
9219 11:09:01.513524 TEMP_SENSOR: ON
9220 11:09:01.514093 HW_SAVE_FOR_SR: OFF
9221 11:09:01.516572 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9222 11:09:01.519860 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9223 11:09:01.522830 Read ODT Tracking: ON
9224 11:09:01.526451 Refresh Rate DeBounce: ON
9225 11:09:01.527010 DFS_NO_QUEUE_FLUSH: ON
9226 11:09:01.529452 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9227 11:09:01.533225 ENABLE_DFS_RUNTIME_MRW: OFF
9228 11:09:01.536325 DDR_RESERVE_NEW_MODE: ON
9229 11:09:01.536788 MR_CBT_SWITCH_FREQ: ON
9230 11:09:01.539204 =========================
9231 11:09:01.558618 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9232 11:09:01.561302 dram_init: ddr_geometry: 2
9233 11:09:01.579916 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9234 11:09:01.583370 dram_init: dram init end (result: 0)
9235 11:09:01.589811 DRAM-K: Full calibration passed in 24626 msecs
9236 11:09:01.593662 MRC: failed to locate region type 0.
9237 11:09:01.594223 DRAM rank0 size:0x100000000,
9238 11:09:01.596327 DRAM rank1 size=0x100000000
9239 11:09:01.606066 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9240 11:09:01.612719 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9241 11:09:01.622379 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9242 11:09:01.628851 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9243 11:09:01.629507 DRAM rank0 size:0x100000000,
9244 11:09:01.631943 DRAM rank1 size=0x100000000
9245 11:09:01.632406 CBMEM:
9246 11:09:01.635666 IMD: root @ 0xfffff000 254 entries.
9247 11:09:01.638415 IMD: root @ 0xffffec00 62 entries.
9248 11:09:01.645832 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9249 11:09:01.648431 WARNING: RO_VPD is uninitialized or empty.
9250 11:09:01.651861 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9251 11:09:01.660026 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9252 11:09:01.673014 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9253 11:09:01.684093 BS: romstage times (exec / console): total (unknown) / 24115 ms
9254 11:09:01.684708
9255 11:09:01.685303
9256 11:09:01.694012 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9257 11:09:01.697752 ARM64: Exception handlers installed.
9258 11:09:01.700332 ARM64: Testing exception
9259 11:09:01.704024 ARM64: Done test exception
9260 11:09:01.704675 Enumerating buses...
9261 11:09:01.706914 Show all devs... Before device enumeration.
9262 11:09:01.710186 Root Device: enabled 1
9263 11:09:01.713491 CPU_CLUSTER: 0: enabled 1
9264 11:09:01.713922 CPU: 00: enabled 1
9265 11:09:01.716736 Compare with tree...
9266 11:09:01.717150 Root Device: enabled 1
9267 11:09:01.719777 CPU_CLUSTER: 0: enabled 1
9268 11:09:01.723882 CPU: 00: enabled 1
9269 11:09:01.724393 Root Device scanning...
9270 11:09:01.726466 scan_static_bus for Root Device
9271 11:09:01.729724 CPU_CLUSTER: 0 enabled
9272 11:09:01.733188 scan_static_bus for Root Device done
9273 11:09:01.736951 scan_bus: bus Root Device finished in 8 msecs
9274 11:09:01.737463 done
9275 11:09:01.743254 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9276 11:09:01.746983 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9277 11:09:01.752787 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9278 11:09:01.759430 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9279 11:09:01.760174 Allocating resources...
9280 11:09:01.762899 Reading resources...
9281 11:09:01.766258 Root Device read_resources bus 0 link: 0
9282 11:09:01.770172 DRAM rank0 size:0x100000000,
9283 11:09:01.770764 DRAM rank1 size=0x100000000
9284 11:09:01.776357 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9285 11:09:01.776862 CPU: 00 missing read_resources
9286 11:09:01.782824 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9287 11:09:01.785699 Root Device read_resources bus 0 link: 0 done
9288 11:09:01.789696 Done reading resources.
9289 11:09:01.792150 Show resources in subtree (Root Device)...After reading.
9290 11:09:01.795950 Root Device child on link 0 CPU_CLUSTER: 0
9291 11:09:01.799927 CPU_CLUSTER: 0 child on link 0 CPU: 00
9292 11:09:01.808709 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9293 11:09:01.809234 CPU: 00
9294 11:09:01.815847 Root Device assign_resources, bus 0 link: 0
9295 11:09:01.818565 CPU_CLUSTER: 0 missing set_resources
9296 11:09:01.822216 Root Device assign_resources, bus 0 link: 0 done
9297 11:09:01.825607 Done setting resources.
9298 11:09:01.829267 Show resources in subtree (Root Device)...After assigning values.
9299 11:09:01.832066 Root Device child on link 0 CPU_CLUSTER: 0
9300 11:09:01.839220 CPU_CLUSTER: 0 child on link 0 CPU: 00
9301 11:09:01.845242 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9302 11:09:01.848988 CPU: 00
9303 11:09:01.849540 Done allocating resources.
9304 11:09:01.855793 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9305 11:09:01.856347 Enabling resources...
9306 11:09:01.858826 done.
9307 11:09:01.861771 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9308 11:09:01.865392 Initializing devices...
9309 11:09:01.865854 Root Device init
9310 11:09:01.868435 init hardware done!
9311 11:09:01.868896 0x00000018: ctrlr->caps
9312 11:09:01.871877 52.000 MHz: ctrlr->f_max
9313 11:09:01.875244 0.400 MHz: ctrlr->f_min
9314 11:09:01.878465 0x40ff8080: ctrlr->voltages
9315 11:09:01.879027 sclk: 390625
9316 11:09:01.879396 Bus Width = 1
9317 11:09:01.881555 sclk: 390625
9318 11:09:01.882011 Bus Width = 1
9319 11:09:01.884961 Early init status = 3
9320 11:09:01.887866 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9321 11:09:01.891173 in-header: 03 fc 00 00 01 00 00 00
9322 11:09:01.894443 in-data: 00
9323 11:09:01.898276 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9324 11:09:01.903019 in-header: 03 fd 00 00 00 00 00 00
9325 11:09:01.905817 in-data:
9326 11:09:01.909366 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9327 11:09:01.913023 in-header: 03 fc 00 00 01 00 00 00
9328 11:09:01.915977 in-data: 00
9329 11:09:01.919011 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9330 11:09:01.924434 in-header: 03 fd 00 00 00 00 00 00
9331 11:09:01.927387 in-data:
9332 11:09:01.931213 [SSUSB] Setting up USB HOST controller...
9333 11:09:01.934111 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9334 11:09:01.937304 [SSUSB] phy power-on done.
9335 11:09:01.940980 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9336 11:09:01.947875 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9337 11:09:01.950500 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9338 11:09:01.957103 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9339 11:09:01.963817 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9340 11:09:01.970043 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9341 11:09:01.977327 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9342 11:09:01.983403 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9343 11:09:01.986727 SPM: binary array size = 0x9dc
9344 11:09:01.990245 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9345 11:09:01.996818 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9346 11:09:02.003368 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9347 11:09:02.009735 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9348 11:09:02.012929 configure_display: Starting display init
9349 11:09:02.047468 anx7625_power_on_init: Init interface.
9350 11:09:02.050535 anx7625_disable_pd_protocol: Disabled PD feature.
9351 11:09:02.054016 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9352 11:09:02.081322 anx7625_start_dp_work: Secure OCM version=00
9353 11:09:02.084687 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9354 11:09:02.099477 sp_tx_get_edid_block: EDID Block = 1
9355 11:09:02.202206 Extracted contents:
9356 11:09:02.205099 header: 00 ff ff ff ff ff ff 00
9357 11:09:02.208329 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9358 11:09:02.211992 version: 01 04
9359 11:09:02.215136 basic params: 95 1f 11 78 0a
9360 11:09:02.218731 chroma info: 76 90 94 55 54 90 27 21 50 54
9361 11:09:02.221913 established: 00 00 00
9362 11:09:02.228279 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9363 11:09:02.231806 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9364 11:09:02.238877 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9365 11:09:02.246187 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9366 11:09:02.251425 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9367 11:09:02.255842 extensions: 00
9368 11:09:02.255923 checksum: fb
9369 11:09:02.255987
9370 11:09:02.261067 Manufacturer: IVO Model 57d Serial Number 0
9371 11:09:02.261149 Made week 0 of 2020
9372 11:09:02.264510 EDID version: 1.4
9373 11:09:02.264591 Digital display
9374 11:09:02.267621 6 bits per primary color channel
9375 11:09:02.267727 DisplayPort interface
9376 11:09:02.271124 Maximum image size: 31 cm x 17 cm
9377 11:09:02.274537 Gamma: 220%
9378 11:09:02.274617 Check DPMS levels
9379 11:09:02.281495 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9380 11:09:02.284010 First detailed timing is preferred timing
9381 11:09:02.287552 Established timings supported:
9382 11:09:02.287713 Standard timings supported:
9383 11:09:02.290858 Detailed timings
9384 11:09:02.294115 Hex of detail: 383680a07038204018303c0035ae10000019
9385 11:09:02.300423 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9386 11:09:02.304107 0780 0798 07c8 0820 hborder 0
9387 11:09:02.307080 0438 043b 0447 0458 vborder 0
9388 11:09:02.310936 -hsync -vsync
9389 11:09:02.311016 Did detailed timing
9390 11:09:02.317118 Hex of detail: 000000000000000000000000000000000000
9391 11:09:02.320294 Manufacturer-specified data, tag 0
9392 11:09:02.323460 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9393 11:09:02.327138 ASCII string: InfoVision
9394 11:09:02.330512 Hex of detail: 000000fe00523134304e574635205248200a
9395 11:09:02.333412 ASCII string: R140NWF5 RH
9396 11:09:02.333494 Checksum
9397 11:09:02.336997 Checksum: 0xfb (valid)
9398 11:09:02.340229 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9399 11:09:02.344337 DSI data_rate: 832800000 bps
9400 11:09:02.349714 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9401 11:09:02.353359 anx7625_parse_edid: pixelclock(138800).
9402 11:09:02.357420 hactive(1920), hsync(48), hfp(24), hbp(88)
9403 11:09:02.359589 vactive(1080), vsync(12), vfp(3), vbp(17)
9404 11:09:02.364516 anx7625_dsi_config: config dsi.
9405 11:09:02.369926 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9406 11:09:02.383688 anx7625_dsi_config: success to config DSI
9407 11:09:02.387028 anx7625_dp_start: MIPI phy setup OK.
9408 11:09:02.390404 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9409 11:09:02.393988 mtk_ddp_mode_set invalid vrefresh 60
9410 11:09:02.397062 main_disp_path_setup
9411 11:09:02.397142 ovl_layer_smi_id_en
9412 11:09:02.400491 ovl_layer_smi_id_en
9413 11:09:02.400571 ccorr_config
9414 11:09:02.400635 aal_config
9415 11:09:02.403801 gamma_config
9416 11:09:02.403908 postmask_config
9417 11:09:02.406886 dither_config
9418 11:09:02.410327 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9419 11:09:02.417284 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9420 11:09:02.420123 Root Device init finished in 551 msecs
9421 11:09:02.423591 CPU_CLUSTER: 0 init
9422 11:09:02.430816 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9423 11:09:02.436694 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9424 11:09:02.436775 APU_MBOX 0x190000b0 = 0x10001
9425 11:09:02.439949 APU_MBOX 0x190001b0 = 0x10001
9426 11:09:02.443121 APU_MBOX 0x190005b0 = 0x10001
9427 11:09:02.446565 APU_MBOX 0x190006b0 = 0x10001
9428 11:09:02.453071 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9429 11:09:02.462784 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9430 11:09:02.475608 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9431 11:09:02.482240 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9432 11:09:02.493929 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9433 11:09:02.502753 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9434 11:09:02.506333 CPU_CLUSTER: 0 init finished in 81 msecs
9435 11:09:02.509265 Devices initialized
9436 11:09:02.513109 Show all devs... After init.
9437 11:09:02.513188 Root Device: enabled 1
9438 11:09:02.516007 CPU_CLUSTER: 0: enabled 1
9439 11:09:02.519557 CPU: 00: enabled 1
9440 11:09:02.522793 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9441 11:09:02.525604 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9442 11:09:02.529112 ELOG: NV offset 0x57f000 size 0x1000
9443 11:09:02.535955 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9444 11:09:02.542992 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9445 11:09:02.546075 ELOG: Event(17) added with size 13 at 2024-03-03 11:09:03 UTC
9446 11:09:02.552161 out: cmd=0x121: 03 db 21 01 00 00 00 00
9447 11:09:02.555542 in-header: 03 9e 00 00 2c 00 00 00
9448 11:09:02.565770 in-data: c1 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9449 11:09:02.571890 ELOG: Event(A1) added with size 10 at 2024-03-03 11:09:03 UTC
9450 11:09:02.578984 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9451 11:09:02.585519 ELOG: Event(A0) added with size 9 at 2024-03-03 11:09:03 UTC
9452 11:09:02.589122 elog_add_boot_reason: Logged dev mode boot
9453 11:09:02.594854 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9454 11:09:02.594935 Finalize devices...
9455 11:09:02.598342 Devices finalized
9456 11:09:02.601680 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9457 11:09:02.605514 Writing coreboot table at 0xffe64000
9458 11:09:02.608289 0. 000000000010a000-0000000000113fff: RAMSTAGE
9459 11:09:02.615099 1. 0000000040000000-00000000400fffff: RAM
9460 11:09:02.618215 2. 0000000040100000-000000004032afff: RAMSTAGE
9461 11:09:02.621193 3. 000000004032b000-00000000545fffff: RAM
9462 11:09:02.624512 4. 0000000054600000-000000005465ffff: BL31
9463 11:09:02.627943 5. 0000000054660000-00000000ffe63fff: RAM
9464 11:09:02.634571 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9465 11:09:02.638062 7. 0000000100000000-000000023fffffff: RAM
9466 11:09:02.640854 Passing 5 GPIOs to payload:
9467 11:09:02.644649 NAME | PORT | POLARITY | VALUE
9468 11:09:02.651484 EC in RW | 0x000000aa | low | undefined
9469 11:09:02.654205 EC interrupt | 0x00000005 | low | undefined
9470 11:09:02.661102 TPM interrupt | 0x000000ab | high | undefined
9471 11:09:02.664437 SD card detect | 0x00000011 | high | undefined
9472 11:09:02.667972 speaker enable | 0x00000093 | high | undefined
9473 11:09:02.670945 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9474 11:09:02.674048 in-header: 03 f9 00 00 02 00 00 00
9475 11:09:02.677722 in-data: 02 00
9476 11:09:02.680566 ADC[4]: Raw value=903031 ID=7
9477 11:09:02.684129 ADC[3]: Raw value=212912 ID=1
9478 11:09:02.684209 RAM Code: 0x71
9479 11:09:02.687305 ADC[6]: Raw value=75036 ID=0
9480 11:09:02.690697 ADC[5]: Raw value=212912 ID=1
9481 11:09:02.690778 SKU Code: 0x1
9482 11:09:02.697971 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5d13
9483 11:09:02.698052 coreboot table: 964 bytes.
9484 11:09:02.700491 IMD ROOT 0. 0xfffff000 0x00001000
9485 11:09:02.704345 IMD SMALL 1. 0xffffe000 0x00001000
9486 11:09:02.707385 RO MCACHE 2. 0xffffc000 0x00001104
9487 11:09:02.711388 CONSOLE 3. 0xfff7c000 0x00080000
9488 11:09:02.713918 FMAP 4. 0xfff7b000 0x00000452
9489 11:09:02.717171 TIME STAMP 5. 0xfff7a000 0x00000910
9490 11:09:02.720583 VBOOT WORK 6. 0xfff66000 0x00014000
9491 11:09:02.723643 RAMOOPS 7. 0xffe66000 0x00100000
9492 11:09:02.727285 COREBOOT 8. 0xffe64000 0x00002000
9493 11:09:02.730038 IMD small region:
9494 11:09:02.733435 IMD ROOT 0. 0xffffec00 0x00000400
9495 11:09:02.736815 VPD 1. 0xffffeb80 0x0000006c
9496 11:09:02.740164 MMC STATUS 2. 0xffffeb60 0x00000004
9497 11:09:02.746904 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9498 11:09:02.746985 Probing TPM: done!
9499 11:09:02.753576 Connected to device vid:did:rid of 1ae0:0028:00
9500 11:09:02.760211 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9501 11:09:02.763389 Initialized TPM device CR50 revision 0
9502 11:09:02.767168 Checking cr50 for pending updates
9503 11:09:02.772676 Reading cr50 TPM mode
9504 11:09:02.781346 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9505 11:09:02.787625 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9506 11:09:02.827600 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9507 11:09:02.830969 Checking segment from ROM address 0x40100000
9508 11:09:02.834532 Checking segment from ROM address 0x4010001c
9509 11:09:02.841459 Loading segment from ROM address 0x40100000
9510 11:09:02.841540 code (compression=0)
9511 11:09:02.851314 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9512 11:09:02.857510 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9513 11:09:02.857592 it's not compressed!
9514 11:09:02.864330 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9515 11:09:02.870888 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9516 11:09:02.888333 Loading segment from ROM address 0x4010001c
9517 11:09:02.888415 Entry Point 0x80000000
9518 11:09:02.892138 Loaded segments
9519 11:09:02.894964 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9520 11:09:02.901889 Jumping to boot code at 0x80000000(0xffe64000)
9521 11:09:02.908281 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9522 11:09:02.914969 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9523 11:09:02.922451 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9524 11:09:02.925935 Checking segment from ROM address 0x40100000
9525 11:09:02.929727 Checking segment from ROM address 0x4010001c
9526 11:09:02.936476 Loading segment from ROM address 0x40100000
9527 11:09:02.936650 code (compression=1)
9528 11:09:02.942734 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9529 11:09:02.952477 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9530 11:09:02.952672 using LZMA
9531 11:09:02.961478 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9532 11:09:02.968244 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9533 11:09:02.971427 Loading segment from ROM address 0x4010001c
9534 11:09:02.971730 Entry Point 0x54601000
9535 11:09:02.974706 Loaded segments
9536 11:09:02.977869 NOTICE: MT8192 bl31_setup
9537 11:09:02.985096 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9538 11:09:02.988065 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9539 11:09:02.991761 WARNING: region 0:
9540 11:09:02.994831 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 11:09:02.995247 WARNING: region 1:
9542 11:09:03.001840 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9543 11:09:03.005138 WARNING: region 2:
9544 11:09:03.008434 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9545 11:09:03.012265 WARNING: region 3:
9546 11:09:03.015127 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9547 11:09:03.018622 WARNING: region 4:
9548 11:09:03.024867 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9549 11:09:03.025283 WARNING: region 5:
9550 11:09:03.028251 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9551 11:09:03.031244 WARNING: region 6:
9552 11:09:03.034683 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9553 11:09:03.037894 WARNING: region 7:
9554 11:09:03.041818 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9555 11:09:03.047830 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9556 11:09:03.051742 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9557 11:09:03.054496 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9558 11:09:03.061770 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9559 11:09:03.064531 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9560 11:09:03.071356 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9561 11:09:03.075270 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9562 11:09:03.077677 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9563 11:09:03.084653 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9564 11:09:03.087663 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9565 11:09:03.091285 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9566 11:09:03.097713 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9567 11:09:03.100564 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9568 11:09:03.107315 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9569 11:09:03.110489 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9570 11:09:03.113709 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9571 11:09:03.120367 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9572 11:09:03.124108 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9573 11:09:03.130422 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9574 11:09:03.133748 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9575 11:09:03.137141 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9576 11:09:03.143348 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9577 11:09:03.147388 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9578 11:09:03.154177 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9579 11:09:03.156986 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9580 11:09:03.160149 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9581 11:09:03.166755 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9582 11:09:03.170087 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9583 11:09:03.176776 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9584 11:09:03.179960 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9585 11:09:03.183274 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9586 11:09:03.189777 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9587 11:09:03.193298 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9588 11:09:03.196826 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9589 11:09:03.203193 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9590 11:09:03.206783 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9591 11:09:03.209942 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9592 11:09:03.213088 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9593 11:09:03.219311 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9594 11:09:03.222604 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9595 11:09:03.226214 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9596 11:09:03.229377 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9597 11:09:03.236360 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9598 11:09:03.239592 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9599 11:09:03.242678 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9600 11:09:03.246199 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9601 11:09:03.252394 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9602 11:09:03.256006 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9603 11:09:03.259166 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9604 11:09:03.265867 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9605 11:09:03.269572 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9606 11:09:03.275952 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9607 11:09:03.279297 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9608 11:09:03.285642 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9609 11:09:03.289090 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9610 11:09:03.295507 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9611 11:09:03.298594 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9612 11:09:03.302433 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9613 11:09:03.308970 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9614 11:09:03.312315 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9615 11:09:03.318414 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9616 11:09:03.322351 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9617 11:09:03.329610 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9618 11:09:03.331752 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9619 11:09:03.338272 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9620 11:09:03.341673 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9621 11:09:03.345020 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9622 11:09:03.351969 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9623 11:09:03.355033 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9624 11:09:03.361514 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9625 11:09:03.364927 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9626 11:09:03.372326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9627 11:09:03.375098 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9628 11:09:03.378081 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9629 11:09:03.384758 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9630 11:09:03.388210 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9631 11:09:03.394498 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9632 11:09:03.398478 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9633 11:09:03.404680 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9634 11:09:03.407646 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9635 11:09:03.414714 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9636 11:09:03.417682 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9637 11:09:03.424537 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9638 11:09:03.427598 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9639 11:09:03.430978 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9640 11:09:03.437337 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9641 11:09:03.440560 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9642 11:09:03.447125 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9643 11:09:03.450955 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9644 11:09:03.457148 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9645 11:09:03.460958 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9646 11:09:03.463936 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9647 11:09:03.470320 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9648 11:09:03.473629 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9649 11:09:03.480888 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9650 11:09:03.484127 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9651 11:09:03.490097 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9652 11:09:03.493499 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9653 11:09:03.497248 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9654 11:09:03.499970 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9655 11:09:03.506984 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9656 11:09:03.509936 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9657 11:09:03.513071 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9658 11:09:03.519930 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9659 11:09:03.523534 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9660 11:09:03.530069 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9661 11:09:03.533229 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9662 11:09:03.536466 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9663 11:09:03.543155 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9664 11:09:03.546684 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9665 11:09:03.553281 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9666 11:09:03.556792 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9667 11:09:03.559754 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9668 11:09:03.566338 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9669 11:09:03.569880 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9670 11:09:03.576283 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9671 11:09:03.579381 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9672 11:09:03.582901 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9673 11:09:03.589561 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9674 11:09:03.592728 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9675 11:09:03.596111 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9676 11:09:03.599449 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9677 11:09:03.606333 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9678 11:09:03.609619 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9679 11:09:03.612691 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9680 11:09:03.619214 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9681 11:09:03.623467 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9682 11:09:03.626463 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9683 11:09:03.632389 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9684 11:09:03.636063 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9685 11:09:03.642585 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9686 11:09:03.646173 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9687 11:09:03.648943 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9688 11:09:03.655364 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9689 11:09:03.658533 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9690 11:09:03.665266 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9691 11:09:03.669500 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9692 11:09:03.671799 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9693 11:09:03.678721 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9694 11:09:03.681722 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9695 11:09:03.688512 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9696 11:09:03.691832 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9697 11:09:03.695530 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9698 11:09:03.702402 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9699 11:09:03.705390 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9700 11:09:03.711960 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9701 11:09:03.715149 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9702 11:09:03.718462 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9703 11:09:03.725513 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9704 11:09:03.728711 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9705 11:09:03.735122 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9706 11:09:03.738778 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9707 11:09:03.741607 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9708 11:09:03.748681 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9709 11:09:03.751994 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9710 11:09:03.758672 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9711 11:09:03.761985 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9712 11:09:03.764941 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9713 11:09:03.771733 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9714 11:09:03.774936 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9715 11:09:03.782259 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9716 11:09:03.784666 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9717 11:09:03.787769 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9718 11:09:03.794562 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9719 11:09:03.797439 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9720 11:09:03.804082 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9721 11:09:03.807708 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9722 11:09:03.810740 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9723 11:09:03.817770 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9724 11:09:03.820484 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9725 11:09:03.827190 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9726 11:09:03.830383 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9727 11:09:03.833504 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9728 11:09:03.840579 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9729 11:09:03.843750 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9730 11:09:03.850447 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9731 11:09:03.853815 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9732 11:09:03.859954 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9733 11:09:03.863376 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9734 11:09:03.866663 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9735 11:09:03.873466 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9736 11:09:03.876924 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9737 11:09:03.883526 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9738 11:09:03.886747 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9739 11:09:03.890509 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9740 11:09:03.896180 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9741 11:09:03.899732 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9742 11:09:03.906204 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9743 11:09:03.909615 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9744 11:09:03.912705 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9745 11:09:03.919343 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9746 11:09:03.922776 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9747 11:09:03.929041 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9748 11:09:03.932635 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9749 11:09:03.939371 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9750 11:09:03.942808 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9751 11:09:03.945742 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9752 11:09:03.952828 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9753 11:09:03.956131 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9754 11:09:03.963187 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9755 11:09:03.965400 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9756 11:09:03.971786 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9757 11:09:03.975161 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9758 11:09:03.978560 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9759 11:09:03.985134 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9760 11:09:03.988462 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9761 11:09:03.995251 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9762 11:09:03.998536 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9763 11:09:04.005095 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9764 11:09:04.008305 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9765 11:09:04.012068 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9766 11:09:04.018120 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9767 11:09:04.021871 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9768 11:09:04.028021 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9769 11:09:04.031500 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9770 11:09:04.038694 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9771 11:09:04.041003 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9772 11:09:04.044249 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9773 11:09:04.051290 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9774 11:09:04.054791 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9775 11:09:04.061097 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9776 11:09:04.064274 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9777 11:09:04.071065 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9778 11:09:04.074239 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9779 11:09:04.077594 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9780 11:09:04.084478 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9781 11:09:04.087595 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9782 11:09:04.093836 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9783 11:09:04.097809 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9784 11:09:04.100505 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9785 11:09:04.107061 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9786 11:09:04.110306 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9787 11:09:04.113611 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9788 11:09:04.116643 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9789 11:09:04.123564 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9790 11:09:04.126806 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9791 11:09:04.130447 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9792 11:09:04.136705 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9793 11:09:04.139802 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9794 11:09:04.146384 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9795 11:09:04.149513 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9796 11:09:04.153316 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9797 11:09:04.160171 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9798 11:09:04.162705 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9799 11:09:04.166364 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9800 11:09:04.172640 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9801 11:09:04.176185 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9802 11:09:04.182766 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9803 11:09:04.186579 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9804 11:09:04.189243 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9805 11:09:04.196584 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9806 11:09:04.199908 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9807 11:09:04.205854 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9808 11:09:04.208915 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9809 11:09:04.213055 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9810 11:09:04.218921 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9811 11:09:04.222373 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9812 11:09:04.225308 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9813 11:09:04.231959 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9814 11:09:04.235959 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9815 11:09:04.238669 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9816 11:09:04.245987 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9817 11:09:04.248605 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9818 11:09:04.255284 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9819 11:09:04.258340 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9820 11:09:04.261697 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9821 11:09:04.268041 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9822 11:09:04.271648 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9823 11:09:04.275075 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9824 11:09:04.282032 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9825 11:09:04.284274 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9826 11:09:04.288101 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9827 11:09:04.291572 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9828 11:09:04.297826 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9829 11:09:04.301235 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9830 11:09:04.304530 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9831 11:09:04.307740 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9832 11:09:04.314525 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9833 11:09:04.317360 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9834 11:09:04.321428 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9835 11:09:04.327624 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9836 11:09:04.330425 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9837 11:09:04.333912 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9838 11:09:04.340423 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9839 11:09:04.344018 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9840 11:09:04.351137 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9841 11:09:04.353557 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9842 11:09:04.357130 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9843 11:09:04.364235 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9844 11:09:04.366629 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9845 11:09:04.373816 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9846 11:09:04.377566 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9847 11:09:04.383110 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9848 11:09:04.386401 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9849 11:09:04.390365 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9850 11:09:04.396434 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9851 11:09:04.399774 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9852 11:09:04.406574 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9853 11:09:04.409714 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9854 11:09:04.413368 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9855 11:09:04.419617 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9856 11:09:04.422875 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9857 11:09:04.429228 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9858 11:09:04.432583 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9859 11:09:04.438878 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9860 11:09:04.443288 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9861 11:09:04.445804 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9862 11:09:04.452675 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9863 11:09:04.456194 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9864 11:09:04.462072 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9865 11:09:04.465453 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9866 11:09:04.471879 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9867 11:09:04.475776 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9868 11:09:04.478759 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9869 11:09:04.485308 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9870 11:09:04.488602 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9871 11:09:04.495293 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9872 11:09:04.498515 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9873 11:09:04.501731 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9874 11:09:04.508442 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9875 11:09:04.512306 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9876 11:09:04.518826 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9877 11:09:04.521636 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9878 11:09:04.524816 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9879 11:09:04.531932 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9880 11:09:04.535360 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9881 11:09:04.541493 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9882 11:09:04.544718 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9883 11:09:04.551052 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9884 11:09:04.554406 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9885 11:09:04.558171 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9886 11:09:04.564391 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9887 11:09:04.568142 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9888 11:09:04.574439 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9889 11:09:04.577712 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9890 11:09:04.584403 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9891 11:09:04.587963 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9892 11:09:04.590661 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9893 11:09:04.597245 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9894 11:09:04.600560 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9895 11:09:04.607582 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9896 11:09:04.610850 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9897 11:09:04.614503 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9898 11:09:04.620413 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9899 11:09:04.623915 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9900 11:09:04.630521 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9901 11:09:04.633914 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9902 11:09:04.640942 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9903 11:09:04.644418 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9904 11:09:04.647055 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9905 11:09:04.653657 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9906 11:09:04.656996 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9907 11:09:04.663509 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9908 11:09:04.666241 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9909 11:09:04.670044 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9910 11:09:04.676318 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9911 11:09:04.680004 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9912 11:09:04.686377 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9913 11:09:04.689963 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9914 11:09:04.695932 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9915 11:09:04.700257 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9916 11:09:04.706523 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9917 11:09:04.709702 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9918 11:09:04.715783 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9919 11:09:04.719598 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9920 11:09:04.722540 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9921 11:09:04.729399 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9922 11:09:04.732424 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9923 11:09:04.739188 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9924 11:09:04.742138 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9925 11:09:04.749025 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9926 11:09:04.752279 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9927 11:09:04.758848 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9928 11:09:04.762047 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9929 11:09:04.768504 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9930 11:09:04.772218 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9931 11:09:04.776174 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9932 11:09:04.781760 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9933 11:09:04.785799 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9934 11:09:04.791771 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9935 11:09:04.795241 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9936 11:09:04.801741 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9937 11:09:04.805337 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9938 11:09:04.811971 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9939 11:09:04.815371 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9940 11:09:04.818240 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9941 11:09:04.825363 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9942 11:09:04.828120 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9943 11:09:04.834914 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9944 11:09:04.837426 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9945 11:09:04.844556 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9946 11:09:04.847358 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9947 11:09:04.854334 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9948 11:09:04.857568 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9949 11:09:04.861081 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9950 11:09:04.867094 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9951 11:09:04.870414 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9952 11:09:04.877724 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9953 11:09:04.880469 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9954 11:09:04.887396 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9955 11:09:04.891199 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9956 11:09:04.893432 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9957 11:09:04.901115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9958 11:09:04.903455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9959 11:09:04.909834 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9960 11:09:04.913465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9961 11:09:04.920121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9962 11:09:04.923075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9963 11:09:04.929750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9964 11:09:04.933003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9965 11:09:04.939496 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9966 11:09:04.943372 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9967 11:09:04.949627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9968 11:09:04.953285 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9969 11:09:04.959305 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9970 11:09:04.963174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9971 11:09:04.969103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9972 11:09:04.973693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9973 11:09:04.979422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9974 11:09:04.982484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9975 11:09:04.989365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9976 11:09:04.993657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9977 11:09:04.999126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9978 11:09:05.002219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9979 11:09:05.008923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9980 11:09:05.012353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9981 11:09:05.018410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9982 11:09:05.021676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9983 11:09:05.028578 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9984 11:09:05.031495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9985 11:09:05.038456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9986 11:09:05.042066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9987 11:09:05.048371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9988 11:09:05.051853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9989 11:09:05.057976 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9990 11:09:05.058504 INFO: [APUAPC] vio 0
9991 11:09:05.064896 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9992 11:09:05.068247 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9993 11:09:05.071105 INFO: [APUAPC] D0_APC_0: 0x400510
9994 11:09:05.075063 INFO: [APUAPC] D0_APC_1: 0x0
9995 11:09:05.078086 INFO: [APUAPC] D0_APC_2: 0x1540
9996 11:09:05.081175 INFO: [APUAPC] D0_APC_3: 0x0
9997 11:09:05.084546 INFO: [APUAPC] D1_APC_0: 0xffffffff
9998 11:09:05.088437 INFO: [APUAPC] D1_APC_1: 0xffffffff
9999 11:09:05.091557 INFO: [APUAPC] D1_APC_2: 0x3fffff
10000 11:09:05.094697 INFO: [APUAPC] D1_APC_3: 0x0
10001 11:09:05.098247 INFO: [APUAPC] D2_APC_0: 0xffffffff
10002 11:09:05.101579 INFO: [APUAPC] D2_APC_1: 0xffffffff
10003 11:09:05.104282 INFO: [APUAPC] D2_APC_2: 0x3fffff
10004 11:09:05.108227 INFO: [APUAPC] D2_APC_3: 0x0
10005 11:09:05.111338 INFO: [APUAPC] D3_APC_0: 0xffffffff
10006 11:09:05.114282 INFO: [APUAPC] D3_APC_1: 0xffffffff
10007 11:09:05.117864 INFO: [APUAPC] D3_APC_2: 0x3fffff
10008 11:09:05.120644 INFO: [APUAPC] D3_APC_3: 0x0
10009 11:09:05.124094 INFO: [APUAPC] D4_APC_0: 0xffffffff
10010 11:09:05.127243 INFO: [APUAPC] D4_APC_1: 0xffffffff
10011 11:09:05.130494 INFO: [APUAPC] D4_APC_2: 0x3fffff
10012 11:09:05.134833 INFO: [APUAPC] D4_APC_3: 0x0
10013 11:09:05.137081 INFO: [APUAPC] D5_APC_0: 0xffffffff
10014 11:09:05.141267 INFO: [APUAPC] D5_APC_1: 0xffffffff
10015 11:09:05.143763 INFO: [APUAPC] D5_APC_2: 0x3fffff
10016 11:09:05.147377 INFO: [APUAPC] D5_APC_3: 0x0
10017 11:09:05.150087 INFO: [APUAPC] D6_APC_0: 0xffffffff
10018 11:09:05.153711 INFO: [APUAPC] D6_APC_1: 0xffffffff
10019 11:09:05.157373 INFO: [APUAPC] D6_APC_2: 0x3fffff
10020 11:09:05.160611 INFO: [APUAPC] D6_APC_3: 0x0
10021 11:09:05.163392 INFO: [APUAPC] D7_APC_0: 0xffffffff
10022 11:09:05.166900 INFO: [APUAPC] D7_APC_1: 0xffffffff
10023 11:09:05.170149 INFO: [APUAPC] D7_APC_2: 0x3fffff
10024 11:09:05.174071 INFO: [APUAPC] D7_APC_3: 0x0
10025 11:09:05.176543 INFO: [APUAPC] D8_APC_0: 0xffffffff
10026 11:09:05.179839 INFO: [APUAPC] D8_APC_1: 0xffffffff
10027 11:09:05.183147 INFO: [APUAPC] D8_APC_2: 0x3fffff
10028 11:09:05.183618 INFO: [APUAPC] D8_APC_3: 0x0
10029 11:09:05.190111 INFO: [APUAPC] D9_APC_0: 0xffffffff
10030 11:09:05.193043 INFO: [APUAPC] D9_APC_1: 0xffffffff
10031 11:09:05.196408 INFO: [APUAPC] D9_APC_2: 0x3fffff
10032 11:09:05.196877 INFO: [APUAPC] D9_APC_3: 0x0
10033 11:09:05.202753 INFO: [APUAPC] D10_APC_0: 0xffffffff
10034 11:09:05.206040 INFO: [APUAPC] D10_APC_1: 0xffffffff
10035 11:09:05.210325 INFO: [APUAPC] D10_APC_2: 0x3fffff
10036 11:09:05.213129 INFO: [APUAPC] D10_APC_3: 0x0
10037 11:09:05.216186 INFO: [APUAPC] D11_APC_0: 0xffffffff
10038 11:09:05.219236 INFO: [APUAPC] D11_APC_1: 0xffffffff
10039 11:09:05.223014 INFO: [APUAPC] D11_APC_2: 0x3fffff
10040 11:09:05.225915 INFO: [APUAPC] D11_APC_3: 0x0
10041 11:09:05.229232 INFO: [APUAPC] D12_APC_0: 0xffffffff
10042 11:09:05.232176 INFO: [APUAPC] D12_APC_1: 0xffffffff
10043 11:09:05.236283 INFO: [APUAPC] D12_APC_2: 0x3fffff
10044 11:09:05.238956 INFO: [APUAPC] D12_APC_3: 0x0
10045 11:09:05.242542 INFO: [APUAPC] D13_APC_0: 0xffffffff
10046 11:09:05.245559 INFO: [APUAPC] D13_APC_1: 0xffffffff
10047 11:09:05.248859 INFO: [APUAPC] D13_APC_2: 0x3fffff
10048 11:09:05.251832 INFO: [APUAPC] D13_APC_3: 0x0
10049 11:09:05.255430 INFO: [APUAPC] D14_APC_0: 0xffffffff
10050 11:09:05.258548 INFO: [APUAPC] D14_APC_1: 0xffffffff
10051 11:09:05.262210 INFO: [APUAPC] D14_APC_2: 0x3fffff
10052 11:09:05.265037 INFO: [APUAPC] D14_APC_3: 0x0
10053 11:09:05.268492 INFO: [APUAPC] D15_APC_0: 0xffffffff
10054 11:09:05.271906 INFO: [APUAPC] D15_APC_1: 0xffffffff
10055 11:09:05.275245 INFO: [APUAPC] D15_APC_2: 0x3fffff
10056 11:09:05.278648 INFO: [APUAPC] D15_APC_3: 0x0
10057 11:09:05.281755 INFO: [APUAPC] APC_CON: 0x4
10058 11:09:05.284980 INFO: [NOCDAPC] D0_APC_0: 0x0
10059 11:09:05.285557 INFO: [NOCDAPC] D0_APC_1: 0x0
10060 11:09:05.288141 INFO: [NOCDAPC] D1_APC_0: 0x0
10061 11:09:05.291973 INFO: [NOCDAPC] D1_APC_1: 0xfff
10062 11:09:05.294947 INFO: [NOCDAPC] D2_APC_0: 0x0
10063 11:09:05.298366 INFO: [NOCDAPC] D2_APC_1: 0xfff
10064 11:09:05.301552 INFO: [NOCDAPC] D3_APC_0: 0x0
10065 11:09:05.305534 INFO: [NOCDAPC] D3_APC_1: 0xfff
10066 11:09:05.307794 INFO: [NOCDAPC] D4_APC_0: 0x0
10067 11:09:05.311433 INFO: [NOCDAPC] D4_APC_1: 0xfff
10068 11:09:05.314058 INFO: [NOCDAPC] D5_APC_0: 0x0
10069 11:09:05.317235 INFO: [NOCDAPC] D5_APC_1: 0xfff
10070 11:09:05.321020 INFO: [NOCDAPC] D6_APC_0: 0x0
10071 11:09:05.323820 INFO: [NOCDAPC] D6_APC_1: 0xfff
10072 11:09:05.324237 INFO: [NOCDAPC] D7_APC_0: 0x0
10073 11:09:05.327367 INFO: [NOCDAPC] D7_APC_1: 0xfff
10074 11:09:05.330311 INFO: [NOCDAPC] D8_APC_0: 0x0
10075 11:09:05.333625 INFO: [NOCDAPC] D8_APC_1: 0xfff
10076 11:09:05.337470 INFO: [NOCDAPC] D9_APC_0: 0x0
10077 11:09:05.340651 INFO: [NOCDAPC] D9_APC_1: 0xfff
10078 11:09:05.343941 INFO: [NOCDAPC] D10_APC_0: 0x0
10079 11:09:05.347255 INFO: [NOCDAPC] D10_APC_1: 0xfff
10080 11:09:05.350372 INFO: [NOCDAPC] D11_APC_0: 0x0
10081 11:09:05.354140 INFO: [NOCDAPC] D11_APC_1: 0xfff
10082 11:09:05.356605 INFO: [NOCDAPC] D12_APC_0: 0x0
10083 11:09:05.360133 INFO: [NOCDAPC] D12_APC_1: 0xfff
10084 11:09:05.363256 INFO: [NOCDAPC] D13_APC_0: 0x0
10085 11:09:05.366546 INFO: [NOCDAPC] D13_APC_1: 0xfff
10086 11:09:05.370277 INFO: [NOCDAPC] D14_APC_0: 0x0
10087 11:09:05.373096 INFO: [NOCDAPC] D14_APC_1: 0xfff
10088 11:09:05.373511 INFO: [NOCDAPC] D15_APC_0: 0x0
10089 11:09:05.377086 INFO: [NOCDAPC] D15_APC_1: 0xfff
10090 11:09:05.379714 INFO: [NOCDAPC] APC_CON: 0x4
10091 11:09:05.383451 INFO: [APUAPC] set_apusys_apc done
10092 11:09:05.386877 INFO: [DEVAPC] devapc_init done
10093 11:09:05.393043 INFO: GICv3 without legacy support detected.
10094 11:09:05.396329 INFO: ARM GICv3 driver initialized in EL3
10095 11:09:05.399444 INFO: Maximum SPI INTID supported: 639
10096 11:09:05.402873 INFO: BL31: Initializing runtime services
10097 11:09:05.409411 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10098 11:09:05.412584 INFO: SPM: enable CPC mode
10099 11:09:05.415967 INFO: mcdi ready for mcusys-off-idle and system suspend
10100 11:09:05.422592 INFO: BL31: Preparing for EL3 exit to normal world
10101 11:09:05.425939 INFO: Entry point address = 0x80000000
10102 11:09:05.426470 INFO: SPSR = 0x8
10103 11:09:05.434053
10104 11:09:05.434545
10105 11:09:05.434882
10106 11:09:05.437176 Starting depthcharge on Spherion...
10107 11:09:05.437600
10108 11:09:05.437936 Wipe memory regions:
10109 11:09:05.438285
10110 11:09:05.440834 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10111 11:09:05.441346 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10112 11:09:05.441751 Setting prompt string to ['asurada:']
10113 11:09:05.442147 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10114 11:09:05.442808 [0x00000040000000, 0x00000054600000)
10115 11:09:05.562128
10116 11:09:05.562665 [0x00000054660000, 0x00000080000000)
10117 11:09:05.822758
10118 11:09:05.823365 [0x000000821a7280, 0x000000ffe64000)
10119 11:09:06.567017
10120 11:09:06.567178 [0x00000100000000, 0x00000240000000)
10121 11:09:08.458010
10122 11:09:08.460830 Initializing XHCI USB controller at 0x11200000.
10123 11:09:09.499139
10124 11:09:09.502148 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10125 11:09:09.502577
10126 11:09:09.502913
10127 11:09:09.503227
10128 11:09:09.504005 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10130 11:09:09.605141 asurada: tftpboot 192.168.201.1 12925670/tftp-deploy-5ljo28bt/kernel/image.itb 12925670/tftp-deploy-5ljo28bt/kernel/cmdline
10131 11:09:09.605708 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10132 11:09:09.606131 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10133 11:09:09.610153 tftpboot 192.168.201.1 12925670/tftp-deploy-5ljo28bt/kernel/image.itp-deploy-5ljo28bt/kernel/cmdline
10134 11:09:09.610564
10135 11:09:09.610902 Waiting for link
10136 11:09:09.771613
10137 11:09:09.772173 R8152: Initializing
10138 11:09:09.772521
10139 11:09:09.774141 Version 6 (ocp_data = 5c30)
10140 11:09:09.774569
10141 11:09:09.777198 R8152: Done initializing
10142 11:09:09.777620
10143 11:09:09.777956 Adding net device
10144 11:09:11.741367
10145 11:09:11.741952 done.
10146 11:09:11.742320
10147 11:09:11.742642 MAC: 00:e0:4c:68:02:81
10148 11:09:11.742947
10149 11:09:11.745076 Sending DHCP discover... done.
10150 11:09:11.745502
10151 11:09:11.747643 Waiting for reply... done.
10152 11:09:11.748110
10153 11:09:11.750967 Sending DHCP request... done.
10154 11:09:11.751391
10155 11:09:11.755885 Waiting for reply... done.
10156 11:09:11.756419
10157 11:09:11.756763 My ip is 192.168.201.14
10158 11:09:11.757077
10159 11:09:11.759393 The DHCP server ip is 192.168.201.1
10160 11:09:11.759860
10161 11:09:11.766158 TFTP server IP predefined by user: 192.168.201.1
10162 11:09:11.766586
10163 11:09:11.773498 Bootfile predefined by user: 12925670/tftp-deploy-5ljo28bt/kernel/image.itb
10164 11:09:11.773923
10165 11:09:11.775601 Sending tftp read request... done.
10166 11:09:11.776058
10167 11:09:11.782380 Waiting for the transfer...
10168 11:09:11.782802
10169 11:09:12.432717 00000000 ################################################################
10170 11:09:12.433218
10171 11:09:13.094681 00080000 ################################################################
10172 11:09:13.095194
10173 11:09:13.764058 00100000 ################################################################
10174 11:09:13.764562
10175 11:09:14.424655 00180000 ################################################################
10176 11:09:14.424797
10177 11:09:15.055606 00200000 ################################################################
10178 11:09:15.056145
10179 11:09:15.716690 00280000 ################################################################
10180 11:09:15.717287
10181 11:09:16.321961 00300000 ################################################################
10182 11:09:16.322113
10183 11:09:16.957152 00380000 ################################################################
10184 11:09:16.957716
10185 11:09:17.567190 00400000 ################################################################
10186 11:09:17.567348
10187 11:09:18.161227 00480000 ################################################################
10188 11:09:18.161373
10189 11:09:18.742924 00500000 ################################################################
10190 11:09:18.743075
10191 11:09:19.356669 00580000 ################################################################
10192 11:09:19.356819
10193 11:09:19.942969 00600000 ################################################################
10194 11:09:19.943117
10195 11:09:20.530251 00680000 ################################################################
10196 11:09:20.530398
10197 11:09:21.152545 00700000 ################################################################
10198 11:09:21.153042
10199 11:09:21.813992 00780000 ################################################################
10200 11:09:21.814498
10201 11:09:22.496069 00800000 ################################################################
10202 11:09:22.496578
10203 11:09:23.095844 00880000 ################################################################
10204 11:09:23.095996
10205 11:09:23.660743 00900000 ################################################################
10206 11:09:23.660906
10207 11:09:24.353283 00980000 ################################################################
10208 11:09:24.353839
10209 11:09:25.028716 00a00000 ################################################################
10210 11:09:25.029239
10211 11:09:25.654865 00a80000 ################################################################
10212 11:09:25.655012
10213 11:09:26.306130 00b00000 ################################################################
10214 11:09:26.306626
10215 11:09:26.941021 00b80000 ################################################################
10216 11:09:26.941163
10217 11:09:27.471120 00c00000 ################################################################
10218 11:09:27.471258
10219 11:09:28.055104 00c80000 ################################################################
10220 11:09:28.055326
10221 11:09:28.678328 00d00000 ################################################################
10222 11:09:28.678474
10223 11:09:29.223878 00d80000 ################################################################
10224 11:09:29.224030
10225 11:09:29.773001 00e00000 ################################################################
10226 11:09:29.773157
10227 11:09:30.329065 00e80000 ################################################################
10228 11:09:30.329246
10229 11:09:30.902305 00f00000 ################################################################
10230 11:09:30.902463
10231 11:09:31.480121 00f80000 ################################################################
10232 11:09:31.480267
10233 11:09:32.043110 01000000 ################################################################
10234 11:09:32.043266
10235 11:09:32.616591 01080000 ################################################################
10236 11:09:32.616748
10237 11:09:33.186518 01100000 ################################################################
10238 11:09:33.186675
10239 11:09:33.752691 01180000 ################################################################
10240 11:09:33.752836
10241 11:09:34.331399 01200000 ################################################################
10242 11:09:34.331544
10243 11:09:34.895174 01280000 ################################################################
10244 11:09:34.895331
10245 11:09:35.453149 01300000 ################################################################
10246 11:09:35.453303
10247 11:09:36.004256 01380000 ################################################################
10248 11:09:36.004411
10249 11:09:36.543194 01400000 ################################################################
10250 11:09:36.543346
10251 11:09:37.096486 01480000 ################################################################
10252 11:09:37.096640
10253 11:09:37.628837 01500000 ################################################################
10254 11:09:37.628990
10255 11:09:38.184044 01580000 ################################################################
10256 11:09:38.184196
10257 11:09:38.774784 01600000 ################################################################
10258 11:09:38.774927
10259 11:09:39.344598 01680000 ################################################################
10260 11:09:39.344749
10261 11:09:39.900213 01700000 ################################################################
10262 11:09:39.900374
10263 11:09:40.439191 01780000 ################################################################
10264 11:09:40.439341
10265 11:09:40.976832 01800000 ################################################################
10266 11:09:40.976982
10267 11:09:41.542779 01880000 ################################################################
10268 11:09:41.542928
10269 11:09:42.119270 01900000 ################################################################
10270 11:09:42.119419
10271 11:09:42.650183 01980000 ################################################################
10272 11:09:42.650336
10273 11:09:43.185624 01a00000 ################################################################
10274 11:09:43.185778
10275 11:09:43.754428 01a80000 ################################################################
10276 11:09:43.754586
10277 11:09:44.314385 01b00000 ################################################################
10278 11:09:44.314542
10279 11:09:44.894499 01b80000 ################################################################
10280 11:09:44.894654
10281 11:09:45.459725 01c00000 ################################################################
10282 11:09:45.459882
10283 11:09:45.492973 01c80000 #### done.
10284 11:09:45.493135
10285 11:09:45.496410 The bootfile was 29913610 bytes long.
10286 11:09:45.496512
10287 11:09:45.499092 Sending tftp read request... done.
10288 11:09:45.499182
10289 11:09:45.499268 Waiting for the transfer...
10290 11:09:45.502472
10291 11:09:45.502565 00000000 # done.
10292 11:09:45.502655
10293 11:09:45.509313 Command line loaded dynamically from TFTP file: 12925670/tftp-deploy-5ljo28bt/kernel/cmdline
10294 11:09:45.509421
10295 11:09:45.532176 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12925670/extract-nfsrootfs-f0qwj3q5,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10296 11:09:45.532351
10297 11:09:45.532452 Loading FIT.
10298 11:09:45.532535
10299 11:09:45.535372 Image ramdisk-1 has 17806600 bytes.
10300 11:09:45.535492
10301 11:09:45.538427 Image fdt-1 has 47278 bytes.
10302 11:09:45.538516
10303 11:09:45.542246 Image kernel-1 has 12057697 bytes.
10304 11:09:45.542341
10305 11:09:45.551819 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10306 11:09:45.551943
10307 11:09:45.568391 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10308 11:09:45.568542
10309 11:09:45.574429 Choosing best match conf-1 for compat google,spherion-rev2.
10310 11:09:45.579217
10311 11:09:45.582727 Connected to device vid:did:rid of 1ae0:0028:00
10312 11:09:45.589868
10313 11:09:45.593095 tpm_get_response: command 0x17b, return code 0x0
10314 11:09:45.593194
10315 11:09:45.596652 ec_init: CrosEC protocol v3 supported (256, 248)
10316 11:09:45.600948
10317 11:09:45.604406 tpm_cleanup: add release locality here.
10318 11:09:45.604504
10319 11:09:45.604591 Shutting down all USB controllers.
10320 11:09:45.607290
10321 11:09:45.607377 Removing current net device
10322 11:09:45.607464
10323 11:09:45.613497 Exiting depthcharge with code 4 at timestamp: 69624730
10324 11:09:45.613597
10325 11:09:45.617221 LZMA decompressing kernel-1 to 0x821a6718
10326 11:09:45.617311
10327 11:09:45.620291 LZMA decompressing kernel-1 to 0x40000000
10328 11:09:47.120321
10329 11:09:47.120480 jumping to kernel
10330 11:09:47.121109 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10331 11:09:47.121249 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10332 11:09:47.121364 Setting prompt string to ['Linux version [0-9]']
10333 11:09:47.121474 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10334 11:09:47.121584 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10335 11:09:47.203271
10336 11:09:47.206850 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10337 11:09:47.210057 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10338 11:09:47.210167 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10339 11:09:47.210253 Setting prompt string to []
10340 11:09:47.210354 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10341 11:09:47.210445 Using line separator: #'\n'#
10342 11:09:47.210518 No login prompt set.
10343 11:09:47.210603 Parsing kernel messages
10344 11:09:47.210696 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10345 11:09:47.210877 [login-action] Waiting for messages, (timeout 00:03:43)
10346 11:09:47.210979 Waiting using forced prompt support (timeout 00:01:52)
10347 11:09:47.229677 [ 0.000000] Linux version 6.1.80-cip16 (KernelCI@build-j128891-arm64-gcc-10-defconfig-arm64-chromebook-nrg4h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024
10348 11:09:47.233308 [ 0.000000] random: crng init done
10349 11:09:47.239141 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10350 11:09:47.242231 [ 0.000000] efi: UEFI not found.
10351 11:09:47.249139 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10352 11:09:47.258744 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10353 11:09:47.269516 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10354 11:09:47.275145 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10355 11:09:47.281847 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10356 11:09:47.288640 [ 0.000000] printk: bootconsole [mtk8250] enabled
10357 11:09:47.294885 [ 0.000000] NUMA: No NUMA configuration found
10358 11:09:47.302031 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10359 11:09:47.308146 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10360 11:09:47.308262 [ 0.000000] Zone ranges:
10361 11:09:47.315175 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10362 11:09:47.318328 [ 0.000000] DMA32 empty
10363 11:09:47.324521 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10364 11:09:47.327571 [ 0.000000] Movable zone start for each node
10365 11:09:47.331102 [ 0.000000] Early memory node ranges
10366 11:09:47.337619 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10367 11:09:47.344400 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10368 11:09:47.350916 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10369 11:09:47.357607 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10370 11:09:47.363680 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10371 11:09:47.370883 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10372 11:09:47.427550 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10373 11:09:47.433986 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10374 11:09:47.440984 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10375 11:09:47.444179 [ 0.000000] psci: probing for conduit method from DT.
10376 11:09:47.450602 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10377 11:09:47.454780 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10378 11:09:47.460782 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10379 11:09:47.463609 [ 0.000000] psci: SMC Calling Convention v1.2
10380 11:09:47.470715 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10381 11:09:47.473616 [ 0.000000] Detected VIPT I-cache on CPU0
10382 11:09:47.480539 [ 0.000000] CPU features: detected: GIC system register CPU interface
10383 11:09:47.486720 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10384 11:09:47.493537 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10385 11:09:47.500136 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10386 11:09:47.509865 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10387 11:09:47.516610 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10388 11:09:47.519236 [ 0.000000] alternatives: applying boot alternatives
10389 11:09:47.526798 [ 0.000000] Fallback order for Node 0: 0
10390 11:09:47.533549 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10391 11:09:47.536330 [ 0.000000] Policy zone: Normal
10392 11:09:47.560135 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12925670/extract-nfsrootfs-f0qwj3q5,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10393 11:09:47.569185 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10394 11:09:47.579822 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10395 11:09:47.589629 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10396 11:09:47.596112 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10397 11:09:47.600005 <6>[ 0.000000] software IO TLB: area num 8.
10398 11:09:47.656440 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10399 11:09:47.805531 <6>[ 0.000000] Memory: 7949804K/8385536K available (18048K kernel code, 4118K rwdata, 19616K rodata, 8448K init, 616K bss, 402964K reserved, 32768K cma-reserved)
10400 11:09:47.811936 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10401 11:09:47.818438 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10402 11:09:47.821574 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10403 11:09:47.828350 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10404 11:09:47.834920 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10405 11:09:47.838383 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10406 11:09:47.848737 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10407 11:09:47.854981 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10408 11:09:47.861305 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10409 11:09:47.868215 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10410 11:09:47.871224 <6>[ 0.000000] GICv3: 608 SPIs implemented
10411 11:09:47.874334 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10412 11:09:47.881517 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10413 11:09:47.884354 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10414 11:09:47.890775 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10415 11:09:47.903863 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10416 11:09:47.916887 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10417 11:09:47.923969 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10418 11:09:47.931945 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10419 11:09:47.945500 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10420 11:09:47.951901 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10421 11:09:47.958442 <6>[ 0.009232] Console: colour dummy device 80x25
10422 11:09:47.968444 <6>[ 0.013962] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10423 11:09:47.974963 <6>[ 0.024469] pid_max: default: 32768 minimum: 301
10424 11:09:47.978473 <6>[ 0.029334] LSM: Security Framework initializing
10425 11:09:47.984781 <6>[ 0.034304] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10426 11:09:47.994988 <6>[ 0.042166] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10427 11:09:48.004581 <6>[ 0.051596] cblist_init_generic: Setting adjustable number of callback queues.
10428 11:09:48.011464 <6>[ 0.059083] cblist_init_generic: Setting shift to 3 and lim to 1.
10429 11:09:48.017720 <6>[ 0.065423] cblist_init_generic: Setting adjustable number of callback queues.
10430 11:09:48.024537 <6>[ 0.072850] cblist_init_generic: Setting shift to 3 and lim to 1.
10431 11:09:48.027448 <6>[ 0.079252] rcu: Hierarchical SRCU implementation.
10432 11:09:48.034960 <6>[ 0.084299] rcu: Max phase no-delay instances is 1000.
10433 11:09:48.041232 <6>[ 0.091325] EFI services will not be available.
10434 11:09:48.044078 <6>[ 0.096271] smp: Bringing up secondary CPUs ...
10435 11:09:48.053131 <6>[ 0.101325] Detected VIPT I-cache on CPU1
10436 11:09:48.060038 <6>[ 0.101394] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10437 11:09:48.066526 <6>[ 0.101428] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10438 11:09:48.069263 <6>[ 0.101767] Detected VIPT I-cache on CPU2
10439 11:09:48.079646 <6>[ 0.101816] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10440 11:09:48.085794 <6>[ 0.101834] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10441 11:09:48.089272 <6>[ 0.102092] Detected VIPT I-cache on CPU3
10442 11:09:48.095767 <6>[ 0.102138] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10443 11:09:48.102126 <6>[ 0.102152] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10444 11:09:48.108421 <6>[ 0.102457] CPU features: detected: Spectre-v4
10445 11:09:48.111722 <6>[ 0.102463] CPU features: detected: Spectre-BHB
10446 11:09:48.115338 <6>[ 0.102468] Detected PIPT I-cache on CPU4
10447 11:09:48.125282 <6>[ 0.102525] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10448 11:09:48.132919 <6>[ 0.102541] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10449 11:09:48.135129 <6>[ 0.102837] Detected PIPT I-cache on CPU5
10450 11:09:48.141698 <6>[ 0.102900] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10451 11:09:48.148760 <6>[ 0.102917] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10452 11:09:48.152601 <6>[ 0.103202] Detected PIPT I-cache on CPU6
10453 11:09:48.161344 <6>[ 0.103267] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10454 11:09:48.168044 <6>[ 0.103282] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10455 11:09:48.171819 <6>[ 0.103580] Detected PIPT I-cache on CPU7
10456 11:09:48.178506 <6>[ 0.103644] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10457 11:09:48.184400 <6>[ 0.103660] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10458 11:09:48.190945 <6>[ 0.103706] smp: Brought up 1 node, 8 CPUs
10459 11:09:48.194392 <6>[ 0.245096] SMP: Total of 8 processors activated.
10460 11:09:48.200774 <6>[ 0.250017] CPU features: detected: 32-bit EL0 Support
10461 11:09:48.207355 <6>[ 0.255413] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10462 11:09:48.213716 <6>[ 0.264213] CPU features: detected: Common not Private translations
10463 11:09:48.220555 <6>[ 0.270689] CPU features: detected: CRC32 instructions
10464 11:09:48.227358 <6>[ 0.276040] CPU features: detected: RCpc load-acquire (LDAPR)
10465 11:09:48.230784 <6>[ 0.282037] CPU features: detected: LSE atomic instructions
10466 11:09:48.237019 <6>[ 0.287854] CPU features: detected: Privileged Access Never
10467 11:09:48.243804 <6>[ 0.293633] CPU features: detected: RAS Extension Support
10468 11:09:48.250335 <6>[ 0.299242] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10469 11:09:48.253909 <6>[ 0.306462] CPU: All CPU(s) started at EL2
10470 11:09:48.260350 <6>[ 0.310778] alternatives: applying system-wide alternatives
10471 11:09:48.271160 <6>[ 0.321638] devtmpfs: initialized
10472 11:09:48.286276 <6>[ 0.330524] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10473 11:09:48.292880 <6>[ 0.340484] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10474 11:09:48.300147 <6>[ 0.348190] pinctrl core: initialized pinctrl subsystem
10475 11:09:48.302640 <6>[ 0.354869] DMI not present or invalid.
10476 11:09:48.309312 <6>[ 0.359280] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10477 11:09:48.319397 <6>[ 0.366138] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10478 11:09:48.325425 <6>[ 0.373725] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10479 11:09:48.335859 <6>[ 0.381943] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10480 11:09:48.338757 <6>[ 0.390184] audit: initializing netlink subsys (disabled)
10481 11:09:48.348790 <5>[ 0.395875] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10482 11:09:48.355667 <6>[ 0.396585] thermal_sys: Registered thermal governor 'step_wise'
10483 11:09:48.362093 <6>[ 0.403843] thermal_sys: Registered thermal governor 'power_allocator'
10484 11:09:48.365201 <6>[ 0.410099] cpuidle: using governor menu
10485 11:09:48.372284 <6>[ 0.421057] NET: Registered PF_QIPCRTR protocol family
10486 11:09:48.378914 <6>[ 0.426542] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10487 11:09:48.385739 <6>[ 0.433646] ASID allocator initialised with 32768 entries
10488 11:09:48.388269 <6>[ 0.440216] Serial: AMBA PL011 UART driver
10489 11:09:48.398258 <4>[ 0.448972] Trying to register duplicate clock ID: 134
10490 11:09:48.452321 <6>[ 0.506578] KASLR enabled
10491 11:09:48.466939 <6>[ 0.514268] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10492 11:09:48.473602 <6>[ 0.521284] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10493 11:09:48.479878 <6>[ 0.527774] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10494 11:09:48.486703 <6>[ 0.534780] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10495 11:09:48.493485 <6>[ 0.541266] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10496 11:09:48.500608 <6>[ 0.548267] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10497 11:09:48.506140 <6>[ 0.554756] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10498 11:09:48.513696 <6>[ 0.561760] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10499 11:09:48.516339 <6>[ 0.569286] ACPI: Interpreter disabled.
10500 11:09:48.525318 <6>[ 0.575691] iommu: Default domain type: Translated
10501 11:09:48.531146 <6>[ 0.580803] iommu: DMA domain TLB invalidation policy: strict mode
10502 11:09:48.534492 <5>[ 0.587465] SCSI subsystem initialized
10503 11:09:48.541474 <6>[ 0.591637] usbcore: registered new interface driver usbfs
10504 11:09:48.547812 <6>[ 0.597370] usbcore: registered new interface driver hub
10505 11:09:48.551575 <6>[ 0.602921] usbcore: registered new device driver usb
10506 11:09:48.558538 <6>[ 0.609020] pps_core: LinuxPPS API ver. 1 registered
10507 11:09:48.568439 <6>[ 0.614214] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10508 11:09:48.571557 <6>[ 0.623560] PTP clock support registered
10509 11:09:48.574870 <6>[ 0.627803] EDAC MC: Ver: 3.0.0
10510 11:09:48.582095 <6>[ 0.632947] FPGA manager framework
10511 11:09:48.589013 <6>[ 0.636625] Advanced Linux Sound Architecture Driver Initialized.
10512 11:09:48.591837 <6>[ 0.643408] vgaarb: loaded
10513 11:09:48.598509 <6>[ 0.646578] clocksource: Switched to clocksource arch_sys_counter
10514 11:09:48.601706 <5>[ 0.653017] VFS: Disk quotas dquot_6.6.0
10515 11:09:48.608418 <6>[ 0.657200] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10516 11:09:48.611699 <6>[ 0.664385] pnp: PnP ACPI: disabled
10517 11:09:48.620468 <6>[ 0.671059] NET: Registered PF_INET protocol family
10518 11:09:48.629957 <6>[ 0.676661] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10519 11:09:48.641498 <6>[ 0.688961] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10520 11:09:48.651470 <6>[ 0.697775] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10521 11:09:48.657856 <6>[ 0.705744] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10522 11:09:48.667655 <6>[ 0.714443] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10523 11:09:48.674894 <6>[ 0.724188] TCP: Hash tables configured (established 65536 bind 65536)
10524 11:09:48.680897 <6>[ 0.731051] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10525 11:09:48.691221 <6>[ 0.738250] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10526 11:09:48.698004 <6>[ 0.745953] NET: Registered PF_UNIX/PF_LOCAL protocol family
10527 11:09:48.700911 <6>[ 0.752041] RPC: Registered named UNIX socket transport module.
10528 11:09:48.707634 <6>[ 0.758190] RPC: Registered udp transport module.
10529 11:09:48.710630 <6>[ 0.763121] RPC: Registered tcp transport module.
10530 11:09:48.717121 <6>[ 0.768051] RPC: Registered tcp NFSv4.1 backchannel transport module.
10531 11:09:48.724033 <6>[ 0.774716] PCI: CLS 0 bytes, default 64
10532 11:09:48.727235 <6>[ 0.779117] Unpacking initramfs...
10533 11:09:48.751344 <6>[ 0.798707] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10534 11:09:48.760990 <6>[ 0.807374] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10535 11:09:48.765059 <6>[ 0.816241] kvm [1]: IPA Size Limit: 40 bits
10536 11:09:48.770936 <6>[ 0.820766] kvm [1]: GICv3: no GICV resource entry
10537 11:09:48.774591 <6>[ 0.825788] kvm [1]: disabling GICv2 emulation
10538 11:09:48.780761 <6>[ 0.830478] kvm [1]: GIC system register CPU interface enabled
10539 11:09:48.784587 <6>[ 0.836639] kvm [1]: vgic interrupt IRQ18
10540 11:09:48.791013 <6>[ 0.840988] kvm [1]: VHE mode initialized successfully
10541 11:09:48.797187 <5>[ 0.847467] Initialise system trusted keyrings
10542 11:09:48.803980 <6>[ 0.852304] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10543 11:09:48.811484 <6>[ 0.862344] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10544 11:09:48.817947 <5>[ 0.868743] NFS: Registering the id_resolver key type
10545 11:09:48.821738 <5>[ 0.874044] Key type id_resolver registered
10546 11:09:48.828130 <5>[ 0.878458] Key type id_legacy registered
10547 11:09:48.834710 <6>[ 0.882752] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10548 11:09:48.841442 <6>[ 0.889677] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10549 11:09:48.848127 <6>[ 0.897405] 9p: Installing v9fs 9p2000 file system support
10550 11:09:48.884870 <5>[ 0.935915] Key type asymmetric registered
10551 11:09:48.888529 <5>[ 0.940248] Asymmetric key parser 'x509' registered
10552 11:09:48.898111 <6>[ 0.945392] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10553 11:09:48.901803 <6>[ 0.953012] io scheduler mq-deadline registered
10554 11:09:48.905233 <6>[ 0.957770] io scheduler kyber registered
10555 11:09:48.923842 <6>[ 0.974930] EINJ: ACPI disabled.
10556 11:09:48.956207 <4>[ 1.000392] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10557 11:09:48.965763 <4>[ 1.011032] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10558 11:09:48.981564 <6>[ 1.032037] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10559 11:09:48.989362 <6>[ 1.040039] printk: console [ttyS0] disabled
10560 11:09:49.017030 <6>[ 1.064662] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10561 11:09:49.023361 <6>[ 1.074138] printk: console [ttyS0] enabled
10562 11:09:49.026688 <6>[ 1.074138] printk: console [ttyS0] enabled
10563 11:09:49.033520 <6>[ 1.083035] printk: bootconsole [mtk8250] disabled
10564 11:09:49.036826 <6>[ 1.083035] printk: bootconsole [mtk8250] disabled
10565 11:09:49.043635 <6>[ 1.094254] SuperH (H)SCI(F) driver initialized
10566 11:09:49.046885 <6>[ 1.099542] msm_serial: driver initialized
10567 11:09:49.061390 <6>[ 1.108554] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10568 11:09:49.070980 <6>[ 1.117106] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10569 11:09:49.077235 <6>[ 1.125649] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10570 11:09:49.087031 <6>[ 1.134276] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10571 11:09:49.096926 <6>[ 1.142982] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10572 11:09:49.104257 <6>[ 1.151695] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10573 11:09:49.113488 <6>[ 1.160242] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10574 11:09:49.120006 <6>[ 1.169036] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10575 11:09:49.130006 <6>[ 1.177580] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10576 11:09:49.142242 <6>[ 1.193203] loop: module loaded
10577 11:09:49.148995 <6>[ 1.199277] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10578 11:09:49.171761 <4>[ 1.222672] mtk-pmic-keys: Failed to locate of_node [id: -1]
10579 11:09:49.178845 <6>[ 1.229630] megasas: 07.719.03.00-rc1
10580 11:09:49.188408 <6>[ 1.239347] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10581 11:09:49.197108 <6>[ 1.247884] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10582 11:09:49.213880 <6>[ 1.264253] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10583 11:09:49.272491 <6>[ 1.317100] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10584 11:09:49.474205 <6>[ 1.524874] Freeing initrd memory: 17384K
10585 11:09:49.484008 <6>[ 1.535225] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10586 11:09:49.495448 <6>[ 1.546051] tun: Universal TUN/TAP device driver, 1.6
10587 11:09:49.498386 <6>[ 1.552106] thunder_xcv, ver 1.0
10588 11:09:49.502660 <6>[ 1.555612] thunder_bgx, ver 1.0
10589 11:09:49.505475 <6>[ 1.559106] nicpf, ver 1.0
10590 11:09:49.515295 <6>[ 1.563117] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10591 11:09:49.519200 <6>[ 1.570594] hns3: Copyright (c) 2017 Huawei Corporation.
10592 11:09:49.525386 <6>[ 1.576180] hclge is initializing
10593 11:09:49.528748 <6>[ 1.579754] e1000: Intel(R) PRO/1000 Network Driver
10594 11:09:49.535633 <6>[ 1.584884] e1000: Copyright (c) 1999-2006 Intel Corporation.
10595 11:09:49.538730 <6>[ 1.590895] e1000e: Intel(R) PRO/1000 Network Driver
10596 11:09:49.545286 <6>[ 1.596111] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10597 11:09:49.551977 <6>[ 1.602297] igb: Intel(R) Gigabit Ethernet Network Driver
10598 11:09:49.559071 <6>[ 1.607947] igb: Copyright (c) 2007-2014 Intel Corporation.
10599 11:09:49.566109 <6>[ 1.613785] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10600 11:09:49.572166 <6>[ 1.620304] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10601 11:09:49.575980 <6>[ 1.626767] sky2: driver version 1.30
10602 11:09:49.582003 <6>[ 1.631750] VFIO - User Level meta-driver version: 0.3
10603 11:09:49.588902 <6>[ 1.639986] usbcore: registered new interface driver usb-storage
10604 11:09:49.595438 <6>[ 1.646430] usbcore: registered new device driver onboard-usb-hub
10605 11:09:49.605120 <6>[ 1.655586] mt6397-rtc mt6359-rtc: registered as rtc0
10606 11:09:49.614852 <6>[ 1.661061] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T11:09:50 UTC (1709464190)
10607 11:09:49.617849 <6>[ 1.670654] i2c_dev: i2c /dev entries driver
10608 11:09:49.634599 <6>[ 1.682367] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10609 11:09:49.654566 <6>[ 1.705300] cpu cpu0: EM: created perf domain
10610 11:09:49.657556 <6>[ 1.710252] cpu cpu4: EM: created perf domain
10611 11:09:49.665136 <6>[ 1.715797] sdhci: Secure Digital Host Controller Interface driver
10612 11:09:49.671823 <6>[ 1.722228] sdhci: Copyright(c) Pierre Ossman
10613 11:09:49.678193 <6>[ 1.727189] Synopsys Designware Multimedia Card Interface Driver
10614 11:09:49.685046 <6>[ 1.733814] sdhci-pltfm: SDHCI platform and OF driver helper
10615 11:09:49.688324 <6>[ 1.733847] mmc0: CQHCI version 5.10
10616 11:09:49.694867 <6>[ 1.744124] ledtrig-cpu: registered to indicate activity on CPUs
10617 11:09:49.701807 <6>[ 1.751139] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10618 11:09:49.707783 <6>[ 1.758197] usbcore: registered new interface driver usbhid
10619 11:09:49.711176 <6>[ 1.764019] usbhid: USB HID core driver
10620 11:09:49.718260 <6>[ 1.768223] spi_master spi0: will run message pump with realtime priority
10621 11:09:49.766834 <6>[ 1.810937] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10622 11:09:49.785807 <6>[ 1.826472] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10623 11:09:49.789103 <6>[ 1.840022] mmc0: Command Queue Engine enabled
10624 11:09:49.796256 <6>[ 1.841656] cros-ec-spi spi0.0: Chrome EC device registered
10625 11:09:49.800185 <6>[ 1.844764] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10626 11:09:49.806765 <6>[ 1.858267] mmcblk0: mmc0:0001 DA4128 116 GiB
10627 11:09:49.817768 <6>[ 1.865535] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10628 11:09:49.824633 <6>[ 1.871020] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10629 11:09:49.830943 <6>[ 1.875924] NET: Registered PF_PACKET protocol family
10630 11:09:49.834454 <6>[ 1.882205] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10631 11:09:49.841163 <6>[ 1.886164] 9pnet: Installing 9P2000 support
10632 11:09:49.844246 <6>[ 1.891998] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10633 11:09:49.851294 <5>[ 1.895856] Key type dns_resolver registered
10634 11:09:49.858148 <6>[ 1.901710] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10635 11:09:49.861474 <6>[ 1.906044] registered taskstats version 1
10636 11:09:49.864321 <5>[ 1.916475] Loading compiled-in X.509 certificates
10637 11:09:49.898610 <4>[ 1.942486] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10638 11:09:49.908123 <4>[ 1.953196] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10639 11:09:49.914475 <3>[ 1.963744] debugfs: File 'uA_load' in directory '/' already present!
10640 11:09:49.921184 <3>[ 1.970450] debugfs: File 'min_uV' in directory '/' already present!
10641 11:09:49.927903 <3>[ 1.977107] debugfs: File 'max_uV' in directory '/' already present!
10642 11:09:49.934421 <3>[ 1.983719] debugfs: File 'constraint_flags' in directory '/' already present!
10643 11:09:49.945272 <3>[ 1.993014] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10644 11:09:49.955389 <6>[ 2.006223] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10645 11:09:49.961944 <6>[ 2.013134] xhci-mtk 11200000.usb: xHCI Host Controller
10646 11:09:49.968814 <6>[ 2.018661] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10647 11:09:49.979101 <6>[ 2.026514] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10648 11:09:49.986117 <6>[ 2.035935] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10649 11:09:49.992494 <6>[ 2.041993] xhci-mtk 11200000.usb: xHCI Host Controller
10650 11:09:49.998846 <6>[ 2.047468] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10651 11:09:50.005737 <6>[ 2.055114] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10652 11:09:50.011987 <6>[ 2.062780] hub 1-0:1.0: USB hub found
10653 11:09:50.015968 <6>[ 2.066788] hub 1-0:1.0: 1 port detected
10654 11:09:50.021736 <6>[ 2.071050] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10655 11:09:50.029177 <6>[ 2.079775] hub 2-0:1.0: USB hub found
10656 11:09:50.032671 <6>[ 2.083796] hub 2-0:1.0: 1 port detected
10657 11:09:50.039981 <6>[ 2.090503] mtk-msdc 11f70000.mmc: Got CD GPIO
10658 11:09:50.057340 <6>[ 2.104443] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10659 11:09:50.063602 <6>[ 2.112472] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10660 11:09:50.073382 <4>[ 2.120362] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10661 11:09:50.083092 <6>[ 2.129888] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10662 11:09:50.090067 <6>[ 2.137964] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10663 11:09:50.097343 <6>[ 2.146044] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10664 11:09:50.106421 <6>[ 2.153972] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10665 11:09:50.113240 <6>[ 2.161788] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10666 11:09:50.123199 <6>[ 2.169607] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10667 11:09:50.133242 <6>[ 2.180117] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10668 11:09:50.139633 <6>[ 2.188477] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10669 11:09:50.149965 <6>[ 2.196817] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10670 11:09:50.156229 <6>[ 2.205155] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10671 11:09:50.165777 <6>[ 2.213495] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10672 11:09:50.172903 <6>[ 2.221832] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10673 11:09:50.183242 <6>[ 2.230170] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10674 11:09:50.192361 <6>[ 2.238508] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10675 11:09:50.199290 <6>[ 2.246846] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10676 11:09:50.209226 <6>[ 2.255192] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10677 11:09:50.215733 <6>[ 2.263529] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10678 11:09:50.225908 <6>[ 2.271867] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10679 11:09:50.232150 <6>[ 2.280204] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10680 11:09:50.242732 <6>[ 2.288540] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10681 11:09:50.249448 <6>[ 2.296877] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10682 11:09:50.255629 <6>[ 2.305649] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10683 11:09:50.262251 <6>[ 2.312798] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10684 11:09:50.268723 <6>[ 2.319540] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10685 11:09:50.279032 <6>[ 2.326300] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10686 11:09:50.286310 <6>[ 2.333233] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10687 11:09:50.291658 <6>[ 2.340083] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10688 11:09:50.301893 <6>[ 2.349215] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10689 11:09:50.311586 <6>[ 2.358334] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10690 11:09:50.321327 <6>[ 2.367628] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10691 11:09:50.331371 <6>[ 2.377096] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10692 11:09:50.341237 <6>[ 2.386562] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10693 11:09:50.347626 <6>[ 2.395682] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10694 11:09:50.358143 <6>[ 2.405149] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10695 11:09:50.367603 <6>[ 2.414267] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10696 11:09:50.377344 <6>[ 2.423561] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10697 11:09:50.387075 <6>[ 2.433721] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10698 11:09:50.397868 <6>[ 2.445597] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10699 11:09:50.404397 <6>[ 2.455267] Trying to probe devices needed for running init ...
10700 11:09:50.423218 <6>[ 2.470927] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10701 11:09:50.451609 <6>[ 2.502440] hub 2-1:1.0: USB hub found
10702 11:09:50.454573 <6>[ 2.506925] hub 2-1:1.0: 3 ports detected
10703 11:09:50.463360 <6>[ 2.514114] hub 2-1:1.0: USB hub found
10704 11:09:50.466692 <6>[ 2.518432] hub 2-1:1.0: 3 ports detected
10705 11:09:50.575196 <6>[ 2.622849] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10706 11:09:50.729605 <6>[ 2.780829] hub 1-1:1.0: USB hub found
10707 11:09:50.732663 <6>[ 2.785317] hub 1-1:1.0: 4 ports detected
10708 11:09:50.742370 <6>[ 2.793576] hub 1-1:1.0: USB hub found
10709 11:09:50.746293 <6>[ 2.798060] hub 1-1:1.0: 4 ports detected
10710 11:09:50.815221 <6>[ 2.863103] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10711 11:09:51.067395 <6>[ 3.114894] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10712 11:09:51.199659 <6>[ 3.250841] hub 1-1.4:1.0: USB hub found
10713 11:09:51.203055 <6>[ 3.255513] hub 1-1.4:1.0: 2 ports detected
10714 11:09:51.213260 <6>[ 3.264072] hub 1-1.4:1.0: USB hub found
10715 11:09:51.217336 <6>[ 3.268677] hub 1-1.4:1.0: 2 ports detected
10716 11:09:51.515398 <6>[ 3.562863] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10717 11:09:51.707263 <6>[ 3.754864] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10718 11:10:02.680325 <6>[ 14.735904] ALSA device list:
10719 11:10:02.687217 <6>[ 14.739191] No soundcards found.
10720 11:10:02.695871 <6>[ 14.747641] Freeing unused kernel memory: 8448K
10721 11:10:02.699010 <6>[ 14.752578] Run /init as init process
10722 11:10:02.707979 Loading, please wait...
10723 11:10:02.726139 Starting version 247.3-7+deb11u4
10724 11:10:02.923337 <6>[ 14.972295] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10725 11:10:02.938244 <6>[ 14.990217] remoteproc remoteproc0: scp is available
10726 11:10:02.946731 <6>[ 14.998825] remoteproc remoteproc0: powering up scp
10727 11:10:02.956679 <6>[ 15.004161] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10728 11:10:02.959834 <6>[ 15.012674] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10729 11:10:02.971928 <3>[ 15.020220] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 11:10:02.974697 <6>[ 15.022940] mc: Linux media interface: v0.10
10731 11:10:02.981135 <6>[ 15.024025] usbcore: registered new device driver r8152-cfgselector
10732 11:10:02.990902 <3>[ 15.028751] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 11:10:02.997855 <6>[ 15.035232] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10734 11:10:03.007637 <3>[ 15.039616] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 11:10:03.014463 <6>[ 15.049209] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10736 11:10:03.024667 <6>[ 15.072241] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10737 11:10:03.030583 <6>[ 15.074513] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10738 11:10:03.042796 <6>[ 15.094752] Bluetooth: Core ver 2.22
10739 11:10:03.049588 <3>[ 15.098190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10740 11:10:03.056363 <6>[ 15.102909] NET: Registered PF_BLUETOOTH protocol family
10741 11:10:03.062769 <3>[ 15.106786] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10742 11:10:03.069244 <6>[ 15.112407] Bluetooth: HCI device and connection manager initialized
10743 11:10:03.078972 <3>[ 15.120406] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 11:10:03.082392 <6>[ 15.121412] videodev: Linux video capture interface: v2.00
10745 11:10:03.089199 <6>[ 15.127042] Bluetooth: HCI socket layer initialized
10746 11:10:03.095635 <4>[ 15.128097] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10747 11:10:03.102390 <4>[ 15.129094] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10748 11:10:03.112201 <3>[ 15.135064] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 11:10:03.115736 <6>[ 15.140858] Bluetooth: L2CAP socket layer initialized
10750 11:10:03.125342 <6>[ 15.144221] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10751 11:10:03.131909 <6>[ 15.144221] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10752 11:10:03.138791 <6>[ 15.144241] remoteproc remoteproc0: remote processor scp is now up
10753 11:10:03.148850 <3>[ 15.145920] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10754 11:10:03.152565 <6>[ 15.153277] Bluetooth: SCO socket layer initialized
10755 11:10:03.158610 <3>[ 15.160567] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10756 11:10:03.169749 <4>[ 15.177451] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10757 11:10:03.172769 <4>[ 15.177451] Fallback method does not support PEC.
10758 11:10:03.182621 <3>[ 15.182444] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 11:10:03.189221 <6>[ 15.183789] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10760 11:10:03.199767 <6>[ 15.185526] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10761 11:10:03.206287 <6>[ 15.199929] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10762 11:10:03.212410 <3>[ 15.203953] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10763 11:10:03.223255 <3>[ 15.203956] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 11:10:03.229064 <3>[ 15.206235] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10765 11:10:03.235576 <6>[ 15.209088] pci_bus 0000:00: root bus resource [bus 00-ff]
10766 11:10:03.245914 <6>[ 15.209404] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10767 11:10:03.252093 <3>[ 15.217191] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 11:10:03.262039 <3>[ 15.227093] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10769 11:10:03.268172 <6>[ 15.230796] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10770 11:10:03.278802 <4>[ 15.234711] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10771 11:10:03.285255 <4>[ 15.234722] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10772 11:10:03.294652 <6>[ 15.235048] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10773 11:10:03.302118 <3>[ 15.238871] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 11:10:03.311666 <6>[ 15.239208] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10775 11:10:03.321273 <6>[ 15.239447] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10776 11:10:03.331097 <6>[ 15.247124] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10777 11:10:03.337967 <6>[ 15.247168] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10778 11:10:03.344451 <3>[ 15.255441] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 11:10:03.354150 <6>[ 15.262261] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10780 11:10:03.361787 <3>[ 15.270328] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10781 11:10:03.367701 <6>[ 15.278472] pci 0000:00:00.0: supports D1 D2
10782 11:10:03.371438 <6>[ 15.282822] r8152 2-1.3:1.0 eth0: v1.12.13
10783 11:10:03.377384 <6>[ 15.282907] usbcore: registered new interface driver r8152
10784 11:10:03.384267 <3>[ 15.287175] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 11:10:03.391058 <6>[ 15.292909] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10786 11:10:03.397666 <6>[ 15.294475] usbcore: registered new interface driver btusb
10787 11:10:03.407667 <4>[ 15.294914] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10788 11:10:03.413771 <3>[ 15.294927] Bluetooth: hci0: Failed to load firmware file (-2)
10789 11:10:03.420581 <3>[ 15.294932] Bluetooth: hci0: Failed to set up firmware (-2)
10790 11:10:03.430626 <4>[ 15.294937] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10791 11:10:03.436717 <3>[ 15.301279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 11:10:03.444516 <6>[ 15.302039] usbcore: registered new interface driver cdc_ether
10793 11:10:03.454191 <6>[ 15.310229] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10794 11:10:03.457425 <6>[ 15.318639] usbcore: registered new interface driver r8153_ecm
10795 11:10:03.466506 <6>[ 15.319185] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10796 11:10:03.476620 <6>[ 15.320334] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10797 11:10:03.483271 <6>[ 15.320418] usbcore: registered new interface driver uvcvideo
10798 11:10:03.490307 <6>[ 15.325346] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10799 11:10:03.496582 <6>[ 15.350774] r8152 2-1.3:1.0 enx00e04c680281: renamed from eth0
10800 11:10:03.503084 <6>[ 15.351673] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10801 11:10:03.509674 <6>[ 15.370516] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10802 11:10:03.516170 <6>[ 15.378840] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10803 11:10:03.526189 <6>[ 15.574433] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10804 11:10:03.529601 <6>[ 15.582012] pci 0000:01:00.0: supports D1 D2
10805 11:10:03.536059 <6>[ 15.586861] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10806 11:10:03.558834 <6>[ 15.606853] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10807 11:10:03.564724 <6>[ 15.613759] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10808 11:10:03.571093 <6>[ 15.621842] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10809 11:10:03.581487 <6>[ 15.629842] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10810 11:10:03.587703 <6>[ 15.637844] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10811 11:10:03.597454 <6>[ 15.645844] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10812 11:10:03.601541 <6>[ 15.653844] pci 0000:00:00.0: PCI bridge to [bus 01]
10813 11:10:03.611336 <6>[ 15.659060] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10814 11:10:03.617633 <6>[ 15.667198] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10815 11:10:03.624311 <6>[ 15.674051] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10816 11:10:03.631188 <6>[ 15.680805] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10817 11:10:03.645211 <5>[ 15.694138] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10818 11:10:03.665981 <5>[ 15.714833] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10819 11:10:03.672836 <5>[ 15.722229] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10820 11:10:03.682749 <4>[ 15.730674] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10821 11:10:03.689255 <6>[ 15.739562] cfg80211: failed to load regulatory.db
10822 11:10:03.732159 <6>[ 15.780835] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10823 11:10:03.738521 <6>[ 15.788333] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10824 11:10:03.762167 <6>[ 15.814963] mt7921e 0000:01:00.0: ASIC revision: 79610010
10825 11:10:03.864600 <6>[ 15.914010] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10826 11:10:03.868522 <6>[ 15.914010]
10827 11:10:03.871841 Begin: Loading essential drivers ... done.
10828 11:10:03.874684 Begin: Running /scripts/init-premount ... done.
10829 11:10:03.881226 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10830 11:10:03.891143 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10831 11:10:03.894501 Device /sys/class/net/enx00e04c680281 found
10832 11:10:03.894738 done.
10833 11:10:03.946019 IP-Config: enx00e04c680281 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10834 11:10:04.131801 <6>[ 16.180572] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10835 11:10:04.909583 <6>[ 16.961784] r8152 2-1.3:1.0 enx00e04c680281: carrier on
10836 11:10:04.974012 <6>[ 17.026479] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10837 11:10:05.108066 IP-Config: no response after 2 secs - giving up
10838 11:10:05.138055 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:47 mtu 1500 DHCP
10839 11:10:05.882579 IP-Config: enx00e04c680281 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10840 11:10:05.885297 IP-Config: enx00e04c680281 complete (dhcp from 192.168.201.1):
10841 11:10:05.895044 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10842 11:10:05.902367 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10843 11:10:05.907955 host : mt8192-asurada-spherion-r0-cbg-9
10844 11:10:05.915144 domain : lava-rack
10845 11:10:05.918046 rootserver: 192.168.201.1 rootpath:
10846 11:10:05.918512 filename :
10847 11:10:06.000449 done.
10848 11:10:06.009494 Begin: Running /scripts/nfs-bottom ... done.
10849 11:10:06.034696 Begin: Running /scripts/init-bottom ... done.
10850 11:10:07.277622 <6>[ 19.330411] NET: Registered PF_INET6 protocol family
10851 11:10:07.285065 <6>[ 19.338259] Segment Routing with IPv6
10852 11:10:07.288432 <6>[ 19.342226] In-situ OAM (IOAM) with IPv6
10853 11:10:07.421632 <30>[ 19.455139] systemd[1]: systemd 247.3-7+deb11u4 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10854 11:10:07.428764 <30>[ 19.479599] systemd[1]: Detected architecture arm64.
10855 11:10:07.447839
10856 11:10:07.451324 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10857 11:10:07.451406
10858 11:10:07.468586 <30>[ 19.521438] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10859 11:10:08.314907 <30>[ 20.364286] systemd[1]: Queued start job for default target Graphical Interface.
10860 11:10:08.347880 <30>[ 20.401252] systemd[1]: Created slice system-getty.slice.
10861 11:10:08.354716 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10862 11:10:08.370915 <30>[ 20.424161] systemd[1]: Created slice system-modprobe.slice.
10863 11:10:08.377670 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10864 11:10:08.394925 <30>[ 20.448069] systemd[1]: Created slice system-serial\x2dgetty.slice.
10865 11:10:08.404988 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10866 11:10:08.418573 <30>[ 20.471899] systemd[1]: Created slice User and Session Slice.
10867 11:10:08.425193 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10868 11:10:08.446253 <30>[ 20.495747] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10869 11:10:08.455807 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10870 11:10:08.473944 <30>[ 20.523639] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10871 11:10:08.480323 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10872 11:10:08.504446 <30>[ 20.551020] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10873 11:10:08.511320 <30>[ 20.563187] systemd[1]: Reached target Local Encrypted Volumes.
10874 11:10:08.517936 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10875 11:10:08.534523 <30>[ 20.587469] systemd[1]: Reached target Paths.
10876 11:10:08.540896 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10877 11:10:08.553831 <30>[ 20.606863] systemd[1]: Reached target Remote File Systems.
10878 11:10:08.560227 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10879 11:10:08.578113 <30>[ 20.631238] systemd[1]: Reached target Slices.
10880 11:10:08.584676 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10881 11:10:08.597500 <30>[ 20.650885] systemd[1]: Reached target Swap.
10882 11:10:08.601044 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10883 11:10:08.621665 <30>[ 20.671395] systemd[1]: Listening on initctl Compatibility Named Pipe.
10884 11:10:08.628183 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10885 11:10:08.634874 <30>[ 20.687672] systemd[1]: Listening on Journal Audit Socket.
10886 11:10:08.640885 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10887 11:10:08.659272 <30>[ 20.712099] systemd[1]: Listening on Journal Socket (/dev/log).
10888 11:10:08.665226 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10889 11:10:08.682191 <30>[ 20.735451] systemd[1]: Listening on Journal Socket.
10890 11:10:08.689097 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10891 11:10:08.706709 <30>[ 20.756332] systemd[1]: Listening on Network Service Netlink Socket.
10892 11:10:08.712775 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10893 11:10:08.728338 <30>[ 20.781607] systemd[1]: Listening on udev Control Socket.
10894 11:10:08.734916 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10895 11:10:08.750463 <30>[ 20.803301] systemd[1]: Listening on udev Kernel Socket.
10896 11:10:08.756617 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10897 11:10:08.806120 <30>[ 20.859358] systemd[1]: Mounting Huge Pages File System...
10898 11:10:08.812607 Mounting [0;1;39mHuge Pages File System[0m...
10899 11:10:08.827979 <30>[ 20.881291] systemd[1]: Mounting POSIX Message Queue File System...
10900 11:10:08.834853 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10901 11:10:08.852977 <30>[ 20.906062] systemd[1]: Mounting Kernel Debug File System...
10902 11:10:08.859821 Mounting [0;1;39mKernel Debug File System[0m...
10903 11:10:08.877163 <30>[ 20.927337] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10904 11:10:08.900563 <30>[ 20.950536] systemd[1]: Starting Create list of static device nodes for the current kernel...
10905 11:10:08.907068 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10906 11:10:08.950314 <30>[ 21.003535] systemd[1]: Starting Load Kernel Module configfs...
10907 11:10:08.956995 Starting [0;1;39mLoad Kernel Module configfs[0m...
10908 11:10:08.975286 <30>[ 21.028276] systemd[1]: Starting Load Kernel Module drm...
10909 11:10:08.981443 Starting [0;1;39mLoad Kernel Module drm[0m...
10910 11:10:09.002935 <30>[ 21.055918] systemd[1]: Starting Load Kernel Module fuse...
10911 11:10:09.009042 Starting [0;1;39mLoad Kernel Module fuse[0m...
10912 11:10:09.030582 <30>[ 21.080307] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10913 11:10:09.058357 <6>[ 21.111402] fuse: init (API version 7.37)
10914 11:10:09.071392 <30>[ 21.123733] systemd[1]: Starting Journal Service...
10915 11:10:09.077323 Starting [0;1;39mJournal Service[0m...
10916 11:10:09.100228 <30>[ 21.153375] systemd[1]: Starting Load Kernel Modules...
10917 11:10:09.106757 Starting [0;1;39mLoad Kernel Modules[0m...
10918 11:10:09.161865 <30>[ 21.211872] systemd[1]: Starting Remount Root and Kernel File Systems...
10919 11:10:09.168658 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10920 11:10:09.188013 <30>[ 21.241483] systemd[1]: Starting Coldplug All udev Devices...
10921 11:10:09.194489 Starting [0;1;39mColdplug All udev Devices[0m...
10922 11:10:09.214583 <30>[ 21.267606] systemd[1]: Mounted Huge Pages File System.
10923 11:10:09.220950 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10924 11:10:09.239099 <30>[ 21.292136] systemd[1]: Mounted POSIX Message Queue File System.
10925 11:10:09.248838 <3>[ 21.292628] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 11:10:09.255097 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10927 11:10:09.274447 <30>[ 21.327281] systemd[1]: Mounted Kernel Debug File System.
10928 11:10:09.284016 <3>[ 21.329856] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 11:10:09.290523 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10930 11:10:09.309702 <30>[ 21.359779] systemd[1]: Finished Create list of static device nodes for the current kernel.
10931 11:10:09.319895 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10932 11:10:09.333729 <3>[ 21.383321] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 11:10:09.340243 <30>[ 21.393646] systemd[1]: modprobe@configfs.service: Succeeded.
10934 11:10:09.347896 <30>[ 21.400829] systemd[1]: Finished Load Kernel Module configfs.
10935 11:10:09.355107 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10936 11:10:09.364765 <3>[ 21.412847] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 11:10:09.374889 <30>[ 21.428121] systemd[1]: modprobe@drm.service: Succeeded.
10938 11:10:09.381650 <30>[ 21.434524] systemd[1]: Finished Load Kernel Module drm.
10939 11:10:09.395644 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m<3>[ 21.445193] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 11:10:09.398474 .
10941 11:10:09.419744 <30>[ 21.472545] systemd[1]: modprobe@fuse.service: Succeeded.
10942 11:10:09.429795 <3>[ 21.477123] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 11:10:09.432972 <30>[ 21.479530] systemd[1]: Finished Load Kernel Module fuse.
10944 11:10:09.439643 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10945 11:10:09.459900 <3>[ 21.509742] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 11:10:09.468507 <30>[ 21.521468] systemd[1]: Finished Load Kernel Modules.
10947 11:10:09.475136 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10948 11:10:09.493285 <3>[ 21.543356] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 11:10:09.500109 <30>[ 21.544677] systemd[1]: Finished Remount Root and Kernel File Systems.
10950 11:10:09.509410 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10951 11:10:09.524541 <3>[ 21.574186] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 11:10:09.552320 <30>[ 21.605616] systemd[1]: Mounting FUSE Control File System...
10953 11:10:09.563001 <3>[ 21.606042] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 11:10:09.568705 Mounting [0;1;39mFUSE Control File System[0m...
10955 11:10:09.585837 <30>[ 21.637765] systemd[1]: Mounting Kernel Configuration File System...
10956 11:10:09.591795 Mounting [0;1;39mKernel Configuration File System[0m...
10957 11:10:09.614511 <30>[ 21.664265] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10958 11:10:09.624468 <30>[ 21.673603] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10959 11:10:09.651257 <30>[ 21.704297] systemd[1]: Starting Load/Save Random Seed...
10960 11:10:09.658151 Starting [0;1;39mLoad/Save Random Seed[0m...
10961 11:10:09.674922 <30>[ 21.727883] systemd[1]: Starting Apply Kernel Variables...
10962 11:10:09.681876 Starting [0;1;39mApply Kernel Variables[0m...
10963 11:10:09.700189 <30>[ 21.752631] systemd[1]: Starting Create System Users...
10964 11:10:09.715826 <4>[ 21.757129] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10965 11:10:09.722979 <3>[ 21.773918] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10966 11:10:09.729292 Starting [0;1;39mCreate System Users[0m...
10967 11:10:09.748170 <30>[ 21.801400] systemd[1]: Started Journal Service.
10968 11:10:09.754836 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10969 11:10:09.783098 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10970 11:10:09.793319 See 'systemctl status systemd-udev-trigger.service' for details.
10971 11:10:09.809867 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10972 11:10:09.826046 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10973 11:10:09.844537 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10974 11:10:09.859465 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10975 11:10:09.875090 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10976 11:10:09.918384 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10977 11:10:09.937442 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10978 11:10:09.990082 <46>[ 22.039895] systemd-journald[298]: Received client request to flush runtime journal.
10979 11:10:10.035409 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10980 11:10:10.054900 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10981 11:10:10.069506 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10982 11:10:10.118458 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10983 11:10:11.402849 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10984 11:10:11.442083 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10985 11:10:11.484169 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10986 11:10:11.544543 Starting [0;1;39mNetwork Service[0m...
10987 11:10:11.847959 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10988 11:10:11.871196 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10989 11:10:11.922180 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10990 11:10:12.247113 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10991 11:10:12.265429 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10992 11:10:12.290292 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10993 11:10:12.310351 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10994 11:10:12.366871 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10995 11:10:12.386343 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10996 11:10:12.411432 Starting [0;1;39mNetwork Name Resolution[0m...
10997 11:10:12.433680 Starting [0;1;39mNetwork Time Synchronization[0m...
10998 11:10:12.452183 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10999 11:10:12.470369 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11000 11:10:12.540503 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11001 11:10:12.669337 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11002 11:10:12.686090 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11003 11:10:12.705777 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11004 11:10:12.717774 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11005 11:10:12.733660 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11006 11:10:12.879361 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11007 11:10:12.916844 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11008 11:10:12.943929 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11009 11:10:12.976067 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11010 11:10:12.989911 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11011 11:10:13.247211 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11012 11:10:13.262136 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11013 11:10:13.281165 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11014 11:10:13.334561 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11015 11:10:13.738332 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11016 11:10:14.118170 Starting [0;1;39mUser Login Management[0m...
11017 11:10:14.135285 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11018 11:10:14.152579 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11019 11:10:14.168409 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11020 11:10:14.202010 Starting [0;1;39mPermit User Sessions[0m...
11021 11:10:14.332961 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11022 11:10:14.373991 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11023 11:10:14.418244 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11024 11:10:14.433201 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11025 11:10:14.446630 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11026 11:10:14.464546 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11027 11:10:14.487996 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11028 11:10:14.506321 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11029 11:10:14.551427 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11030 11:10:14.603017 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11031 11:10:14.723308
11032 11:10:14.723482
11033 11:10:14.726488 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11034 11:10:14.726594
11035 11:10:14.729476 debian-bullseye-arm64 login: root (automatic login)
11036 11:10:14.729579
11037 11:10:14.729682
11038 11:10:15.045058 Linux debian-bullseye-arm64 6.1.80-cip16 #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024 aarch64
11039 11:10:15.045214
11040 11:10:15.051235 The programs included with the Debian GNU/Linux system are free software;
11041 11:10:15.058172 the exact distribution terms for each program are described in the
11042 11:10:15.061671 individual files in /usr/share/doc/*/copyright.
11043 11:10:15.061777
11044 11:10:15.068251 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11045 11:10:15.071557 permitted by applicable law.
11046 11:10:15.148569 Matched prompt #10: / #
11048 11:10:15.148918 Setting prompt string to ['/ #']
11049 11:10:15.149052 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11051 11:10:15.149360 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11052 11:10:15.149481 start: 2.2.6 expect-shell-connection (timeout 00:03:15) [common]
11053 11:10:15.149580 Setting prompt string to ['/ #']
11054 11:10:15.149669 Forcing a shell prompt, looking for ['/ #']
11056 11:10:15.199920 / #
11057 11:10:15.200044 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11058 11:10:15.200145 Waiting using forced prompt support (timeout 00:02:30)
11059 11:10:15.204667
11060 11:10:15.204957 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11061 11:10:15.205076 start: 2.2.7 export-device-env (timeout 00:03:15) [common]
11063 11:10:15.305416 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12925670/extract-nfsrootfs-f0qwj3q5'
11064 11:10:15.310506 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12925670/extract-nfsrootfs-f0qwj3q5'
11066 11:10:15.411139 / # export NFS_SERVER_IP='192.168.201.1'
11067 11:10:15.416358 export NFS_SERVER_IP='192.168.201.1'
11068 11:10:15.416675 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11069 11:10:15.416797 end: 2.2 depthcharge-retry (duration 00:01:45) [common]
11070 11:10:15.416919 end: 2 depthcharge-action (duration 00:01:45) [common]
11071 11:10:15.417057 start: 3 lava-test-retry (timeout 00:30:00) [common]
11072 11:10:15.417190 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11073 11:10:15.417296 Using namespace: common
11075 11:10:15.517699 / # #
11076 11:10:15.517868 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11077 11:10:15.523083 #
11078 11:10:15.523380 Using /lava-12925670
11080 11:10:15.623721 / # export SHELL=/bin/sh
11081 11:10:15.629355 export SHELL=/bin/sh
11083 11:10:15.729864 / # . /lava-12925670/environment
11084 11:10:15.735540 . /lava-12925670/environment
11086 11:10:15.841922 / # /lava-12925670/bin/lava-test-runner /lava-12925670/0
11087 11:10:15.842099 Test shell timeout: 10s (minimum of the action and connection timeout)
11088 11:10:15.847850 /lava-12925670/bin/lava-test-runner /lava-12925670/0
11089 11:10:16.094780 + export TESTRUN_ID=0_lc-compliance
11090 11:10:16.100926 + cd /lava-12925670/0/tests/0_lc-compliance
11091 11:10:16.101047 + cat uuid
11092 11:10:16.108699 + UUID=12925670_1.6.2.3.1
11093 11:10:16.108808 + set +x
11094 11:10:16.115464 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 12925670_1.6.2.3.1>
11095 11:10:16.115763 Received signal: <STARTRUN> 0_lc-compliance 12925670_1.6.2.3.1
11096 11:10:16.115846 Starting test lava.0_lc-compliance (12925670_1.6.2.3.1)
11097 11:10:16.115933 Skipping test definition patterns.
11098 11:10:16.117779 + /usr/bin/lc-compliance-parser.sh
11099 11:10:17.315548 [0:00:29.248303385] [410] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-6f1bd9cf
11100 11:10:17.319383 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11101 11:10:17.333914 [0:00:29.267000154] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11102 11:10:17.393748 [0:00:29.326553308] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11103 11:10:17.401216 [==========] Running 120 tests from 1 test suite.
11104 11:10:17.447428 [0:00:29.380734308] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11105 11:10:17.489755 [----------] Global test environment set-up.
11106 11:10:17.502275 [0:00:29.435483385] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11107 11:10:17.574014 [----------] 120 tests from CaptureTests/SingleStream
11108 11:10:17.659903 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11109 11:10:17.728283 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11110 11:10:17.728598 Received signal: <TESTSET> START CaptureTests/SingleStream
11111 11:10:17.728710 Starting test_set CaptureTests/SingleStream
11112 11:10:17.731916 Camera needs 4 requests, can't test only 1
11113 11:10:17.808820 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11114 11:10:17.880224
11115 11:10:17.932080 [0:00:29.864990308] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11116 11:10:17.967999 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (60 ms)
11117 11:10:18.077532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11118 11:10:18.077824 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11120 11:10:18.095116 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11121 11:10:18.147904 Camera needs 4 requests, can't test only 2
11122 11:10:18.228164 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11123 11:10:18.298555
11124 11:10:18.380771 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (54 ms)
11125 11:10:18.471041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11126 11:10:18.471370 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11128 11:10:18.487511 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11129 11:10:18.543326 Camera needs 4 requests, can't test only 3
11130 11:10:18.626551 [0:00:30.559670770] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11131 11:10:18.630193 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11132 11:10:18.706747
11133 11:10:18.788795 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (55 ms)
11134 11:10:18.886668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11135 11:10:18.886989 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11137 11:10:18.903440 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11138 11:10:18.958933 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (429 ms)
11139 11:10:19.053518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11140 11:10:19.053843 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11142 11:10:19.070594 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11143 11:10:19.123756 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (695 ms)
11144 11:10:19.215890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11145 11:10:19.216180 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11147 11:10:19.232703 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11148 11:10:19.874077 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1256 ms)
11149 11:10:19.884073 [0:00:31.816933770] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11150 11:10:19.971617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11151 11:10:19.971969 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11153 11:10:19.989045 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11154 11:10:21.690883 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1817 ms)
11155 11:10:21.700634 [0:00:33.634206077] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11156 11:10:21.798638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11157 11:10:21.798957 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11159 11:10:21.815989 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11160 11:10:24.419011 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2727 ms)
11161 11:10:24.429249 [0:00:36.362172308] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11162 11:10:24.542725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11163 11:10:24.543032 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11165 11:10:24.560062 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11166 11:10:28.616774 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4198 ms)
11167 11:10:28.626569 [0:00:40.560242693] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11168 11:10:28.737969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11169 11:10:28.738805 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11171 11:10:28.757135 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11172 11:10:34.100162 <6>[ 46.158849] vpu: disabling
11173 11:10:34.102629 <6>[ 46.162178] vproc2: disabling
11174 11:10:34.106155 <6>[ 46.165678] vproc1: disabling
11175 11:10:34.110266 <6>[ 46.169344] vaud18: disabling
11176 11:10:34.116664 <6>[ 46.173031] vsram_others: disabling
11177 11:10:34.120642 <6>[ 46.177180] va09: disabling
11178 11:10:34.123638 <6>[ 46.180527] vsram_md: disabling
11179 11:10:34.126576 <6>[ 46.184268] Vgpu: disabling
11180 11:10:35.193987 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6578 ms)
11181 11:10:35.203768 [0:00:47.138917924] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11182 11:10:35.260465 [0:00:47.195199463] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11183 11:10:35.300856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11184 11:10:35.301132 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11186 11:10:35.314506 [0:00:47.249255540] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11187 11:10:35.320484 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11188 11:10:35.368558 [0:00:47.302966232] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11189 11:10:35.377022 Camera needs 4 requests, can't test only 1
11190 11:10:35.461189 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11191 11:10:35.540584
11192 11:10:35.627841 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (57 ms)
11193 11:10:35.727545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11194 11:10:35.727844 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11196 11:10:35.745215 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11197 11:10:35.798663 Camera needs 4 requests, can't test only 2
11198 11:10:35.885991 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11199 11:10:35.962676
11200 11:10:36.053125 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (55 ms)
11201 11:10:36.066529 [0:00:47.996563386] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11202 11:10:36.162536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11203 11:10:36.162827 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11205 11:10:36.179245 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11206 11:10:36.237011 Camera needs 4 requests, can't test only 3
11207 11:10:36.320603 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11208 11:10:36.397549
11209 11:10:36.484373 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (54 ms)
11210 11:10:36.585662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11211 11:10:36.585974 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11213 11:10:36.602766 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11214 11:10:36.658675 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (693 ms)
11215 11:10:36.752368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11216 11:10:36.752664 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11218 11:10:36.768620 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11219 11:10:36.960936 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (908 ms)
11220 11:10:36.974094 [0:00:48.904511155] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11221 11:10:37.062263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11222 11:10:37.062551 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11224 11:10:37.078501 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11225 11:10:38.218168 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1256 ms)
11226 11:10:38.230542 [0:00:50.161547386] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11227 11:10:38.324779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11228 11:10:38.325070 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11230 11:10:38.341208 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11231 11:10:40.035996 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1819 ms)
11232 11:10:40.049333 [0:00:51.980485694] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11233 11:10:40.142005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11234 11:10:40.142307 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11236 11:10:40.158197 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11237 11:10:42.765261 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2730 ms)
11238 11:10:42.779025 [0:00:54.709918002] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11239 11:10:42.864214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11240 11:10:42.864501 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11242 11:10:42.880542 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11243 11:10:46.963517 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4197 ms)
11244 11:10:46.975653 [0:00:58.907562315] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11245 11:10:47.074717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11246 11:10:47.075008 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11248 11:10:47.091911 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11249 11:10:53.542356 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6578 ms)
11250 11:10:53.555017 [0:01:05.485552749] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11251 11:10:53.604257 [0:01:05.539355165] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11252 11:10:53.657826 [0:01:05.593130507] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11253 11:10:53.669495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11254 11:10:53.670474 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11256 11:10:53.688529 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11257 11:10:53.712393 [0:01:05.647544533] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11258 11:10:53.756643 Camera needs 4 requests, can't test only 1
11259 11:10:53.857223 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11260 11:10:53.952114
11261 11:10:54.055524 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (56 ms)
11262 11:10:54.170392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11263 11:10:54.171259 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11265 11:10:54.189381 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11266 11:10:54.254149 Camera needs 4 requests, can't test only 2
11267 11:10:54.335936 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11268 11:10:54.408019 [0:01:06.343146178] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11269 11:10:54.419651
11270 11:10:54.506968 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (52 ms)
11271 11:10:54.601355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11272 11:10:54.601645 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11274 11:10:54.617578 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11275 11:10:54.671009 Camera needs 4 requests, can't test only 3
11276 11:10:54.755334 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11277 11:10:54.836890
11278 11:10:54.925126 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (54 ms)
11279 11:10:55.015888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11280 11:10:55.016178 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11282 11:10:55.032692 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11283 11:10:55.092423 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (695 ms)
11284 11:10:55.190491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11285 11:10:55.190776 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11287 11:10:55.205603 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11288 11:10:55.306524 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (908 ms)
11289 11:10:55.319965 [0:01:07.251471724] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11290 11:10:55.406861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11291 11:10:55.407151 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11293 11:10:55.422331 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11294 11:10:56.567677 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1257 ms)
11295 11:10:56.577123 [0:01:08.508745942] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11296 11:10:56.671391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11297 11:10:56.671695 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11299 11:10:56.688441 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11300 11:10:58.382791 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1818 ms)
11301 11:10:58.395961 [0:01:10.326723494] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11302 11:10:58.486715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11303 11:10:58.487022 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11305 11:10:58.503938 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11306 11:11:01.110833 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2728 ms)
11307 11:11:01.124431 [0:01:13.055453707] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11308 11:11:01.219022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11309 11:11:01.219313 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11311 11:11:01.235218 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11312 11:11:05.312432 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4198 ms)
11313 11:11:05.322137 [0:01:17.253213446] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11314 11:11:05.426198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11315 11:11:05.426503 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11317 11:11:05.442980 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11318 11:11:11.886664 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6578 ms)
11319 11:11:11.899231 [0:01:23.830781662] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11320 11:11:11.950626 [0:01:23.886641476] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11321 11:11:12.005201 [0:01:23.940946741] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11322 11:11:12.014489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11323 11:11:12.015194 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11325 11:11:12.036880 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11326 11:11:12.059772 [0:01:23.995755417] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11327 11:11:12.109536 Camera needs 4 requests, can't test only 1
11328 11:11:12.217322 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11329 11:11:12.315894
11330 11:11:12.425831 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (55 ms)
11331 11:11:12.549831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11332 11:11:12.550599 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11334 11:11:12.571966 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11335 11:11:12.642652 Camera needs 4 requests, can't test only 2
11336 11:11:12.749648 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11337 11:11:12.758746 [0:01:24.692620366] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11338 11:11:12.850935
11339 11:11:12.959807 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (54 ms)
11340 11:11:13.083995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11341 11:11:13.084741 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11343 11:11:13.103782 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11344 11:11:13.176135 Camera needs 4 requests, can't test only 3
11345 11:11:13.279252 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11346 11:11:13.378756
11347 11:11:13.484973 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (55 ms)
11348 11:11:13.597464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11349 11:11:13.598030 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11351 11:11:13.617073 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11352 11:11:13.663128 [0:01:25.599091222] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11353 11:11:13.686957 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (696 ms)
11354 11:11:13.797361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11355 11:11:13.798173 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11357 11:11:13.816671 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11358 11:11:13.875745 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (907 ms)
11359 11:11:13.985609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11360 11:11:13.985968 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11362 11:11:14.002825 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11363 11:11:14.911355 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1256 ms)
11364 11:11:14.924339 [0:01:26.856400344] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11365 11:11:15.037887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11366 11:11:15.038673 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11368 11:11:15.058270 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11369 11:11:16.728505 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1817 ms)
11370 11:11:16.741341 [0:01:28.673575985] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11371 11:11:16.847570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11372 11:11:16.848077 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11374 11:11:16.868800 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11375 11:11:19.456421 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2728 ms)
11376 11:11:19.469277 [0:01:31.401723544] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11377 11:11:19.586291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11378 11:11:19.587075 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11380 11:11:19.607288 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11381 11:11:23.654134 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4197 ms)
11382 11:11:23.666801 [0:01:35.599548561] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11383 11:11:23.785661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11384 11:11:23.786380 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11386 11:11:23.806718 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11387 11:11:30.231662 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6579 ms)
11388 11:11:30.244563 [0:01:42.177879433] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11389 11:11:30.297091 [0:01:42.234517199] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11390 11:11:30.352493 [0:01:42.290137823] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11391 11:11:30.362588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11392 11:11:30.363274 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11394 11:11:30.382679 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11395 11:11:30.405953 [0:01:42.343525783] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11396 11:11:30.449871 Camera needs 4 requests, can't test only 1
11397 11:11:30.543535 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11398 11:11:30.643971
11399 11:11:30.749497 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (57 ms)
11400 11:11:30.875079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11401 11:11:30.875787 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11403 11:11:30.894857 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11404 11:11:30.962648 Camera needs 4 requests, can't test only 2
11405 11:11:31.067987 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11406 11:11:31.164918
11407 11:11:31.274185 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (55 ms)
11408 11:11:31.397079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11409 11:11:31.397850 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11411 11:11:31.417783 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11412 11:11:31.488714 Camera needs 4 requests, can't test only 3
11413 11:11:31.594496 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11414 11:11:31.696237
11415 11:11:31.805801 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (55 ms)
11416 11:11:31.926394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11417 11:11:31.927111 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11419 11:11:31.945889 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11420 11:11:32.474171 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2075 ms)
11421 11:11:32.486684 [0:01:44.419625899] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11422 11:11:32.600874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11423 11:11:32.601587 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11425 11:11:32.621121 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11426 11:11:35.190206 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2717 ms)
11427 11:11:35.203321 [0:01:47.139267647] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11428 11:11:35.312748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11429 11:11:35.313544 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11431 11:11:35.334647 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11432 11:11:38.953177 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3763 ms)
11433 11:11:38.966480 [0:01:50.902737518] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11434 11:11:39.077890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11435 11:11:39.078618 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11437 11:11:39.099614 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11438 11:11:44.394917 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5443 ms)
11439 11:11:44.407979 [0:01:56.345435799] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11440 11:11:44.523090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11441 11:11:44.523849 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11443 11:11:44.543388 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11444 11:11:52.572189 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8176 ms)
11445 11:11:52.585101 [0:02:04.521690238] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11446 11:11:52.691518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11447 11:11:52.692341 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11449 11:11:52.710019 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11450 11:12:05.155126 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12581 ms)
11451 11:12:05.168261 [0:02:17.103338219] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11452 11:12:05.285314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11453 11:12:05.286044 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11455 11:12:05.305475 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11456 11:12:24.877598 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19722 ms)
11457 11:12:24.890836 [0:02:36.826679492] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11458 11:12:24.944877 [0:02:36.882304581] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11459 11:12:25.000832 [0:02:36.937441185] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11460 11:12:25.008829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11461 11:12:25.009574 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11463 11:12:25.028758 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11464 11:12:25.054691 [0:02:36.992086093] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11465 11:12:25.098754 Camera needs 4 requests, can't test only 1
11466 11:12:25.201237 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11467 11:12:25.300267
11468 11:12:25.410166 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (57 ms)
11469 11:12:25.531920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11470 11:12:25.532231 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11472 11:12:25.548932 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11473 11:12:25.620379 Camera needs 4 requests, can't test only 2
11474 11:12:25.722977 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11475 11:12:25.827100
11476 11:12:25.938789 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (54 ms)
11477 11:12:26.058316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11478 11:12:26.059087 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11480 11:12:26.075444 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11481 11:12:26.145519 Camera needs 4 requests, can't test only 3
11482 11:12:26.250087 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11483 11:12:26.353246
11484 11:12:26.464866 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (55 ms)
11485 11:12:26.587443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11486 11:12:26.588213 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11488 11:12:26.603812 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11489 11:12:27.129612 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2079 ms)
11490 11:12:27.138986 [0:02:39.072537215] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11491 11:12:27.253486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11492 11:12:27.253822 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11494 11:12:27.269664 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11495 11:12:29.840840 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2712 ms)
11496 11:12:29.851203 [0:02:41.786009584] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11497 11:12:29.968329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11498 11:12:29.969108 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11500 11:12:29.985738 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11501 11:12:33.602442 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3762 ms)
11502 11:12:33.612221 [0:02:45.547950907] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11503 11:12:33.700241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11504 11:12:33.700554 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11506 11:12:33.712874 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11507 11:12:39.045723 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5443 ms)
11508 11:12:39.055907 [0:02:50.991311018] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11509 11:12:39.169820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11510 11:12:39.170834 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11512 11:12:39.186070 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11513 11:12:47.220940 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8176 ms)
11514 11:12:47.230764 [0:02:59.166969869] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11515 11:12:47.356597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11516 11:12:47.356933 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11518 11:12:47.373130 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11519 11:12:59.803719 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12583 ms)
11520 11:12:59.814019 [0:03:11.750877578] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11521 11:12:59.932319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11522 11:12:59.933093 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11524 11:12:59.948397 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11525 11:13:19.527943 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19723 ms)
11526 11:13:19.537740 [0:03:31.475765315] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11527 11:13:19.592173 [0:03:31.532205829] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11528 11:13:19.648845 [0:03:31.587844301] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11529 11:13:19.663572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11530 11:13:19.664328 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11532 11:13:19.680807 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11533 11:13:19.702656 [0:03:31.642447279] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11534 11:13:19.753548 Camera needs 4 requests, can't test only 1
11535 11:13:19.855576 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11536 11:13:19.955440
11537 11:13:20.070058 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (56 ms)
11538 11:13:20.190717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11539 11:13:20.191499 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11541 11:13:20.208580 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11542 11:13:20.273838 Camera needs 4 requests, can't test only 2
11543 11:13:20.381614 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11544 11:13:20.483274
11545 11:13:20.595511 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (56 ms)
11546 11:13:20.713817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11547 11:13:20.714556 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11549 11:13:20.730923 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11550 11:13:20.799723 Camera needs 4 requests, can't test only 3
11551 11:13:20.908069 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11552 11:13:21.005793
11553 11:13:21.119151 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (55 ms)
11554 11:13:21.243432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11555 11:13:21.244277 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11557 11:13:21.259628 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11558 11:13:21.776408 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2079 ms)
11559 11:13:21.785799 [0:03:33.721893466] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11560 11:13:21.904049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11561 11:13:21.904880 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11563 11:13:21.922103 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11564 11:13:24.487882 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2712 ms)
11565 11:13:24.497338 [0:03:36.435684097] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11566 11:13:24.611051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11567 11:13:24.611896 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11569 11:13:24.628135 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11570 11:13:28.250632 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3762 ms)
11571 11:13:28.259612 [0:03:40.198413219] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11572 11:13:28.375358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11573 11:13:28.376123 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11575 11:13:28.392431 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11576 11:13:33.693196 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5443 ms)
11577 11:13:33.702708 [0:03:45.641346303] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11578 11:13:33.821294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11579 11:13:33.822008 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11581 11:13:33.839421 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11582 11:13:41.868031 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8177 ms)
11583 11:13:41.877922 [0:03:53.817766762] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11584 11:13:41.996315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11585 11:13:41.997058 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11587 11:13:42.013962 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11588 11:13:54.450265 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12582 ms)
11589 11:13:54.460149 [0:04:06.400556000] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11590 11:13:54.580645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11591 11:13:54.581374 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11593 11:13:54.597792 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11594 11:14:14.174335 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19723 ms)
11595 11:14:14.183540 [0:04:26.123082926] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11596 11:14:14.238059 [0:04:26.178961791] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11597 11:14:14.292140 [0:04:26.233138812] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11598 11:14:14.307823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11599 11:14:14.308516 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11601 11:14:14.325517 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11602 11:14:14.346818 [0:04:26.288272352] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11603 11:14:14.392032 Camera needs 4 requests, can't test only 1
11604 11:14:14.494324 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11605 11:14:14.597505
11606 11:14:14.710071 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (58 ms)
11607 11:14:14.835579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11608 11:14:14.836402 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11610 11:14:14.853242 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11611 11:14:14.919180 Camera needs 4 requests, can't test only 2
11612 11:14:15.021221 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11613 11:14:15.123500
11614 11:14:15.235640 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (55 ms)
11615 11:14:15.354297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11616 11:14:15.355032 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11618 11:14:15.371897 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11619 11:14:15.441914 Camera needs 4 requests, can't test only 3
11620 11:14:15.547385 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11621 11:14:15.644971
11622 11:14:15.756575 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (55 ms)
11623 11:14:15.880812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11624 11:14:15.881630 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11626 11:14:15.898480 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11627 11:14:16.421928 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2080 ms)
11628 11:14:16.431614 [0:04:28.368554876] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11629 11:14:16.553248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11630 11:14:16.554021 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11632 11:14:16.569631 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11633 11:14:19.132007 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2709 ms)
11634 11:14:19.141378 [0:04:31.078978046] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11635 11:14:19.257643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11636 11:14:19.258408 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11638 11:14:19.274698 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11639 11:14:22.891528 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3760 ms)
11640 11:14:22.901557 [0:04:34.840103474] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11641 11:14:23.023239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11642 11:14:23.023986 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11644 11:14:23.042050 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11645 11:14:28.332353 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5440 ms)
11646 11:14:28.342010 [0:04:40.280618472] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11647 11:14:28.461792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11648 11:14:28.462551 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11650 11:14:28.479751 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11651 11:14:36.507655 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8174 ms)
11652 11:14:36.517324 [0:04:48.455484428] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11653 11:14:36.633793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11654 11:14:36.634560 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11656 11:14:36.651259 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11657 11:14:49.091176 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12583 ms)
11658 11:14:49.100830 [0:05:01.038760022] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11659 11:14:49.218139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11660 11:14:49.218891 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11662 11:14:49.234335 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11663 11:15:08.814257 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19723 ms)
11664 11:15:08.823971 [0:05:20.761974065] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11665 11:15:08.945196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11666 11:15:08.945915 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11668 11:15:08.962832 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11669 11:15:09.230650 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (419 ms)
11670 11:15:09.244224 [0:05:21.179552029] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11671 11:15:09.351613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11672 11:15:09.352384 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11674 11:15:09.371935 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11675 11:15:09.719918 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (490 ms)
11676 11:15:09.732911 [0:05:21.668916169] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11677 11:15:09.848557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11678 11:15:09.849327 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11680 11:15:09.867296 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11681 11:15:10.277660 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (557 ms)
11682 11:15:10.287366 [0:05:22.226340797] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11683 11:15:10.405342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11684 11:15:10.406196 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11686 11:15:10.425334 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11687 11:15:10.974450 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (697 ms)
11688 11:15:10.987663 [0:05:22.923574977] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11689 11:15:11.097667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11690 11:15:11.098407 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11692 11:15:11.118312 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11693 11:15:11.882801 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (908 ms)
11694 11:15:11.896156 [0:05:23.831824656] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11695 11:15:12.015523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11696 11:15:12.016326 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11698 11:15:12.037256 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11699 11:15:13.139972 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1257 ms)
11700 11:15:13.153582 [0:05:25.089110507] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11701 11:15:13.265074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11702 11:15:13.265869 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11704 11:15:13.286007 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11705 11:15:14.958274 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1818 ms)
11706 11:15:14.971156 [0:05:26.907020593] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11707 11:15:15.099072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11708 11:15:15.099800 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11710 11:15:15.118789 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11711 11:15:17.685273 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2727 ms)
11712 11:15:17.698221 [0:05:29.634062818] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11713 11:15:17.810849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11714 11:15:17.811567 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11716 11:15:17.830594 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11717 11:15:21.882926 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4198 ms)
11718 11:15:21.896325 [0:05:33.832114364] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11719 11:15:22.000751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11720 11:15:22.001486 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11722 11:15:22.021978 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11723 11:15:28.461615 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6578 ms)
11724 11:15:28.473519 [0:05:40.409931220] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11725 11:15:28.591614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11726 11:15:28.592444 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11728 11:15:28.612919 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11729 11:15:28.882286 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (417 ms)
11730 11:15:28.892196 [0:05:40.827575287] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11731 11:15:29.006432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11732 11:15:29.006771 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11734 11:15:29.022158 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11735 11:15:29.370141 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (488 ms)
11736 11:15:29.379092 [0:05:41.315367168] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11737 11:15:29.493877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11738 11:15:29.494653 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11740 11:15:29.512463 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11741 11:15:29.926532 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (557 ms)
11742 11:15:29.936551 [0:05:41.872673498] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11743 11:15:30.052085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11744 11:15:30.052926 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11746 11:15:30.067598 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11747 11:15:30.624349 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (698 ms)
11748 11:15:30.634219 [0:05:42.570173017] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11749 11:15:30.754502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11750 11:15:30.755283 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11752 11:15:30.772162 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11753 11:15:31.533960 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (909 ms)
11754 11:15:31.543205 [0:05:43.479346880] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11755 11:15:31.665906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11756 11:15:31.666721 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11758 11:15:31.684198 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11759 11:15:32.790682 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1257 ms)
11760 11:15:32.800025 [0:05:44.736634257] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11761 11:15:32.892535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11762 11:15:32.892853 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11764 11:15:32.905186 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11765 11:15:34.608792 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1818 ms)
11766 11:15:34.618756 [0:05:46.554761319] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11767 11:15:34.737256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11768 11:15:34.738175 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11770 11:15:34.754463 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11771 11:15:37.337794 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2730 ms)
11772 11:15:37.348090 [0:05:49.283989460] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11773 11:15:37.463928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11774 11:15:37.464696 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11776 11:15:37.481869 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11777 11:15:41.536482 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4198 ms)
11778 11:15:41.545647 [0:05:53.482212854] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11779 11:15:41.665349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11780 11:15:41.666092 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11782 11:15:41.684758 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11783 11:15:48.114029 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6578 ms)
11784 11:15:48.123479 [0:06:00.059017109] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11785 11:15:48.224708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11786 11:15:48.225018 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11788 11:15:48.238028 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11789 11:15:48.529892 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (415 ms)
11790 11:15:48.539234 [0:06:00.475675609] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11791 11:15:48.656536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11792 11:15:48.657245 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11794 11:15:48.671433 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11795 11:15:49.018260 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (489 ms)
11796 11:15:49.027415 [0:06:00.964165954] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11797 11:15:49.140920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11798 11:15:49.141630 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11800 11:15:49.155324 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11801 11:15:49.575341 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (557 ms)
11802 11:15:49.585391 [0:06:01.521761539] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11803 11:15:49.703362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11804 11:15:49.704138 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11806 11:15:49.719456 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11807 11:15:50.272195 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (696 ms)
11808 11:15:50.282096 [0:06:02.218746952] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11809 11:15:50.397748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11810 11:15:50.398525 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11812 11:15:50.414855 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11813 11:15:51.180866 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (910 ms)
11814 11:15:51.190679 [0:06:03.128408206] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11815 11:15:51.301260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11816 11:15:51.301996 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11818 11:15:51.317861 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11819 11:15:52.438508 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1257 ms)
11820 11:15:52.447880 [0:06:04.386128644] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11821 11:15:52.563006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11822 11:15:52.563794 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11824 11:15:52.579281 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11825 11:15:54.255961 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1818 ms)
11826 11:15:54.266113 [0:06:06.203656368] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11827 11:15:54.375652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11828 11:15:54.376468 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11830 11:15:54.392045 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11831 11:15:56.984616 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2728 ms)
11832 11:15:56.994556 [0:06:08.931071678] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11833 11:15:57.113608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11834 11:15:57.114401 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11836 11:15:57.129842 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11837 11:16:01.181583 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4197 ms)
11838 11:16:01.191958 [0:06:13.128413399] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11839 11:16:01.302120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11840 11:16:01.303102 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11842 11:16:01.319965 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11843 11:16:07.759583 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6579 ms)
11844 11:16:07.769841 [0:06:19.706931204] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11845 11:16:07.887730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11846 11:16:07.888441 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11848 11:16:07.906348 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11849 11:16:08.176906 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (417 ms)
11850 11:16:08.187035 [0:06:20.123850225] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11851 11:16:08.290207 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11853 11:16:08.293348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11854 11:16:08.308965 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11855 11:16:08.663319 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (487 ms)
11856 11:16:08.673699 [0:06:20.611220779] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11857 11:16:08.764379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11858 11:16:08.764682 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11860 11:16:08.778131 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11861 11:16:09.221158 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (558 ms)
11862 11:16:09.231175 [0:06:21.168891176] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11863 11:16:09.352655 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11865 11:16:09.355121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11866 11:16:09.371703 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11867 11:16:09.916205 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (697 ms)
11868 11:16:09.928980 [0:06:21.866310331] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11869 11:16:10.047184 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11871 11:16:10.049493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11872 11:16:10.068321 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11873 11:16:10.826845 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (908 ms)
11874 11:16:10.836423 [0:06:22.773963031] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11875 11:16:10.949759 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11877 11:16:10.952871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11878 11:16:10.968983 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11879 11:16:12.084309 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1257 ms)
11880 11:16:12.094179 [0:06:24.031651248] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11881 11:16:12.211372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11882 11:16:12.212138 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11884 11:16:12.228707 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11885 11:16:13.901940 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1818 ms)
11886 11:16:13.911872 [0:06:25.849431943] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11887 11:16:14.025364 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11889 11:16:14.028444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11890 11:16:14.045925 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11891 11:16:16.629837 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2728 ms)
11892 11:16:16.639251 [0:06:28.577079861] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11893 11:16:16.764995 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11895 11:16:16.768050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11896 11:16:16.783774 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11897 11:16:20.827897 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4198 ms)
11898 11:16:20.837837 [0:06:32.775418989] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11899 11:16:20.946071 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11901 11:16:20.948731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11902 11:16:20.964765 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11903 11:16:27.406192 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6579 ms)
11904 11:16:27.525024 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11906 11:16:27.527100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11907 11:16:27.544976 [----------] 120 tests from CaptureTests/SingleStream (370087 ms total)
11908 11:16:27.647668
11909 11:16:27.757625 [----------] Global test environment tear-down
11910 11:16:27.858344 [==========] 120 tests from 1 test suite ran. (370087 ms total)
11911 11:16:27.960150 <LAVA_SIGNAL_TESTSET STOP>
11912 11:16:27.960923 Received signal: <TESTSET> STOP
11913 11:16:27.961322 Closing test_set CaptureTests/SingleStream
11914 11:16:27.974933 + set +x
11915 11:16:27.978294 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 12925670_1.6.2.3.1>
11916 11:16:27.979112 Received signal: <ENDRUN> 0_lc-compliance 12925670_1.6.2.3.1
11917 11:16:27.979525 Ending use of test pattern.
11918 11:16:27.979902 Ending test lava.0_lc-compliance (12925670_1.6.2.3.1), duration 371.86
11920 11:16:27.981431 <LAVA_TEST_RUNNER EXIT>
11921 11:16:27.982086 ok: lava_test_shell seems to have completed
11922 11:16:27.991156 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11923 11:16:27.992050 end: 3.1 lava-test-shell (duration 00:06:13) [common]
11924 11:16:27.992519 end: 3 lava-test-retry (duration 00:06:13) [common]
11925 11:16:27.993167 start: 4 finalize (timeout 00:10:00) [common]
11926 11:16:27.993655 start: 4.1 power-off (timeout 00:00:30) [common]
11927 11:16:27.994399 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11928 11:16:28.078358 >> Command sent successfully.
11929 11:16:28.090148 Returned 0 in 0 seconds
11930 11:16:28.191665 end: 4.1 power-off (duration 00:00:00) [common]
11932 11:16:28.193248 start: 4.2 read-feedback (timeout 00:10:00) [common]
11933 11:16:28.194610 Listened to connection for namespace 'common' for up to 1s
11934 11:16:29.195261 Finalising connection for namespace 'common'
11935 11:16:29.196231 Disconnecting from shell: Finalise
11936 11:16:29.196679 / #
11937 11:16:29.297759 end: 4.2 read-feedback (duration 00:00:01) [common]
11938 11:16:29.298767 end: 4 finalize (duration 00:00:01) [common]
11939 11:16:29.299575 Cleaning after the job
11940 11:16:29.300221 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925670/tftp-deploy-5ljo28bt/ramdisk
11941 11:16:29.314320 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925670/tftp-deploy-5ljo28bt/kernel
11942 11:16:29.346755 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925670/tftp-deploy-5ljo28bt/dtb
11943 11:16:29.347077 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925670/tftp-deploy-5ljo28bt/nfsrootfs
11944 11:16:29.407036 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925670/tftp-deploy-5ljo28bt/modules
11945 11:16:29.414166 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12925670
11946 11:16:29.732627 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12925670
11947 11:16:29.732813 Job finished correctly