Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 33
- Boot result: PASS
- Errors: 1
- Warnings: 1
- Kernel Warnings: 14
1 11:07:58.011849 lava-dispatcher, installed at version: 2024.01
2 11:07:58.012080 start: 0 validate
3 11:07:58.012223 Start time: 2024-03-03 11:07:58.012214+00:00 (UTC)
4 11:07:58.012361 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:07:58.012503 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 11:07:58.281174 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:07:58.281351 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:07:58.547425 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:07:58.547604 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:07:58.814328 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:07:58.814544 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:07:59.081760 validate duration: 1.07
14 11:07:59.082065 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:07:59.082178 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:07:59.082271 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:07:59.082416 Not decompressing ramdisk as can be used compressed.
18 11:07:59.082528 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 11:07:59.082596 saving as /var/lib/lava/dispatcher/tmp/12925658/tftp-deploy-8e9hyeki/ramdisk/rootfs.cpio.gz
20 11:07:59.082662 total size: 26246609 (25 MB)
21 11:07:59.083729 progress 0 % (0 MB)
22 11:07:59.091364 progress 5 % (1 MB)
23 11:07:59.098671 progress 10 % (2 MB)
24 11:07:59.105900 progress 15 % (3 MB)
25 11:07:59.113105 progress 20 % (5 MB)
26 11:07:59.120266 progress 25 % (6 MB)
27 11:07:59.127612 progress 30 % (7 MB)
28 11:07:59.134797 progress 35 % (8 MB)
29 11:07:59.141911 progress 40 % (10 MB)
30 11:07:59.149000 progress 45 % (11 MB)
31 11:07:59.156212 progress 50 % (12 MB)
32 11:07:59.163150 progress 55 % (13 MB)
33 11:07:59.170015 progress 60 % (15 MB)
34 11:07:59.176941 progress 65 % (16 MB)
35 11:07:59.183863 progress 70 % (17 MB)
36 11:07:59.190805 progress 75 % (18 MB)
37 11:07:59.197739 progress 80 % (20 MB)
38 11:07:59.204694 progress 85 % (21 MB)
39 11:07:59.211548 progress 90 % (22 MB)
40 11:07:59.218444 progress 95 % (23 MB)
41 11:07:59.225300 progress 100 % (25 MB)
42 11:07:59.225556 25 MB downloaded in 0.14 s (175.17 MB/s)
43 11:07:59.225721 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:07:59.225974 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:07:59.226064 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:07:59.226152 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:07:59.226293 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:07:59.226365 saving as /var/lib/lava/dispatcher/tmp/12925658/tftp-deploy-8e9hyeki/kernel/Image
50 11:07:59.226439 total size: 51599872 (49 MB)
51 11:07:59.226503 No compression specified
52 11:07:59.227616 progress 0 % (0 MB)
53 11:07:59.241120 progress 5 % (2 MB)
54 11:07:59.254867 progress 10 % (4 MB)
55 11:07:59.268644 progress 15 % (7 MB)
56 11:07:59.282689 progress 20 % (9 MB)
57 11:07:59.296608 progress 25 % (12 MB)
58 11:07:59.310341 progress 30 % (14 MB)
59 11:07:59.324031 progress 35 % (17 MB)
60 11:07:59.338460 progress 40 % (19 MB)
61 11:07:59.352723 progress 45 % (22 MB)
62 11:07:59.366584 progress 50 % (24 MB)
63 11:07:59.380356 progress 55 % (27 MB)
64 11:07:59.393850 progress 60 % (29 MB)
65 11:07:59.407463 progress 65 % (32 MB)
66 11:07:59.421118 progress 70 % (34 MB)
67 11:07:59.434715 progress 75 % (36 MB)
68 11:07:59.448254 progress 80 % (39 MB)
69 11:07:59.462090 progress 85 % (41 MB)
70 11:07:59.476050 progress 90 % (44 MB)
71 11:07:59.489676 progress 95 % (46 MB)
72 11:07:59.503182 progress 100 % (49 MB)
73 11:07:59.503432 49 MB downloaded in 0.28 s (177.66 MB/s)
74 11:07:59.503598 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:07:59.503846 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:07:59.503941 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:07:59.504036 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:07:59.504181 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:07:59.504253 saving as /var/lib/lava/dispatcher/tmp/12925658/tftp-deploy-8e9hyeki/dtb/mt8192-asurada-spherion-r0.dtb
81 11:07:59.504324 total size: 47278 (0 MB)
82 11:07:59.504390 No compression specified
83 11:07:59.505571 progress 69 % (0 MB)
84 11:07:59.505866 progress 100 % (0 MB)
85 11:07:59.506060 0 MB downloaded in 0.00 s (26.02 MB/s)
86 11:07:59.506236 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:07:59.506532 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:07:59.506621 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:07:59.506713 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:07:59.506832 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:07:59.506909 saving as /var/lib/lava/dispatcher/tmp/12925658/tftp-deploy-8e9hyeki/modules/modules.tar
93 11:07:59.506973 total size: 8628476 (8 MB)
94 11:07:59.507036 Using unxz to decompress xz
95 11:07:59.511339 progress 0 % (0 MB)
96 11:07:59.532582 progress 5 % (0 MB)
97 11:07:59.567242 progress 10 % (0 MB)
98 11:07:59.601819 progress 15 % (1 MB)
99 11:07:59.635750 progress 20 % (1 MB)
100 11:07:59.661660 progress 25 % (2 MB)
101 11:07:59.686388 progress 30 % (2 MB)
102 11:07:59.716081 progress 35 % (2 MB)
103 11:07:59.743078 progress 40 % (3 MB)
104 11:07:59.768862 progress 45 % (3 MB)
105 11:07:59.794482 progress 50 % (4 MB)
106 11:07:59.820205 progress 55 % (4 MB)
107 11:07:59.844948 progress 60 % (4 MB)
108 11:07:59.871991 progress 65 % (5 MB)
109 11:07:59.898307 progress 70 % (5 MB)
110 11:07:59.924617 progress 75 % (6 MB)
111 11:07:59.952419 progress 80 % (6 MB)
112 11:07:59.978436 progress 85 % (7 MB)
113 11:08:00.004242 progress 90 % (7 MB)
114 11:08:00.035908 progress 95 % (7 MB)
115 11:08:00.066102 progress 100 % (8 MB)
116 11:08:00.071487 8 MB downloaded in 0.56 s (14.58 MB/s)
117 11:08:00.071789 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:08:00.072195 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:08:00.072323 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:08:00.072458 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:08:00.072575 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:08:00.072700 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:08:00.072974 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p
125 11:08:00.073153 makedir: /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin
126 11:08:00.073297 makedir: /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/tests
127 11:08:00.073430 makedir: /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/results
128 11:08:00.073580 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-add-keys
129 11:08:00.073738 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-add-sources
130 11:08:00.073882 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-background-process-start
131 11:08:00.074051 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-background-process-stop
132 11:08:00.074218 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-common-functions
133 11:08:00.074401 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-echo-ipv4
134 11:08:00.074568 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-install-packages
135 11:08:00.074734 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-installed-packages
136 11:08:00.074896 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-os-build
137 11:08:00.075056 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-probe-channel
138 11:08:00.075222 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-probe-ip
139 11:08:00.075382 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-target-ip
140 11:08:00.075522 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-target-mac
141 11:08:00.075649 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-target-storage
142 11:08:00.075793 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-test-case
143 11:08:00.075956 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-test-event
144 11:08:00.076115 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-test-feedback
145 11:08:00.076279 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-test-raise
146 11:08:00.076447 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-test-reference
147 11:08:00.076609 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-test-runner
148 11:08:00.076772 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-test-set
149 11:08:00.076933 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-test-shell
150 11:08:00.077101 Updating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-install-packages (oe)
151 11:08:00.077289 Updating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/bin/lava-installed-packages (oe)
152 11:08:00.077422 Creating /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/environment
153 11:08:00.077562 LAVA metadata
154 11:08:00.077667 - LAVA_JOB_ID=12925658
155 11:08:00.077762 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:08:00.077908 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:08:00.078004 skipped lava-vland-overlay
158 11:08:00.078125 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:08:00.078250 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:08:00.078348 skipped lava-multinode-overlay
161 11:08:00.078461 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:08:00.078580 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:08:00.078664 Loading test definitions
164 11:08:00.078758 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:08:00.078836 Using /lava-12925658 at stage 0
166 11:08:00.079164 uuid=12925658_1.5.2.3.1 testdef=None
167 11:08:00.079254 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:08:00.079340 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:08:00.080086 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:08:00.080446 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:08:00.081365 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:08:00.081688 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:08:00.082519 runner path: /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/0/tests/0_v4l2-compliance-uvc test_uuid 12925658_1.5.2.3.1
176 11:08:00.082721 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:08:00.083065 Creating lava-test-runner.conf files
179 11:08:00.083160 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12925658/lava-overlay-18t8j11p/lava-12925658/0 for stage 0
180 11:08:00.083281 - 0_v4l2-compliance-uvc
181 11:08:00.083405 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:08:00.083521 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:08:00.092583 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:08:00.092738 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:08:00.092858 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:08:00.092980 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:08:00.093106 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:08:00.829959 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:08:00.830505 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:08:00.830689 extracting modules file /var/lib/lava/dispatcher/tmp/12925658/tftp-deploy-8e9hyeki/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925658/extract-overlay-ramdisk-_cl0he0_/ramdisk
191 11:08:01.166604 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:08:01.166784 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:08:01.166880 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925658/compress-overlay-f491aqfo/overlay-1.5.2.4.tar.gz to ramdisk
194 11:08:01.166957 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925658/compress-overlay-f491aqfo/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12925658/extract-overlay-ramdisk-_cl0he0_/ramdisk
195 11:08:01.173733 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:08:01.173852 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:08:01.173947 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:08:01.174038 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:08:01.174121 Building ramdisk /var/lib/lava/dispatcher/tmp/12925658/extract-overlay-ramdisk-_cl0he0_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12925658/extract-overlay-ramdisk-_cl0he0_/ramdisk
200 11:08:01.831741 >> 228478 blocks
201 11:08:06.042050 rename /var/lib/lava/dispatcher/tmp/12925658/extract-overlay-ramdisk-_cl0he0_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12925658/tftp-deploy-8e9hyeki/ramdisk/ramdisk.cpio.gz
202 11:08:06.042554 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 11:08:06.042703 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 11:08:06.042806 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 11:08:06.042935 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12925658/tftp-deploy-8e9hyeki/kernel/Image'
206 11:08:19.858219 Returned 0 in 13 seconds
207 11:08:19.959016 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12925658/tftp-deploy-8e9hyeki/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12925658/tftp-deploy-8e9hyeki/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12925658/tftp-deploy-8e9hyeki/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12925658/tftp-deploy-8e9hyeki/kernel/image.itb
208 11:08:20.632528 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:08:20.632949 output: Created: Sun Mar 3 11:08:20 2024
210 11:08:20.633058 output: Image 0 (kernel-1)
211 11:08:20.633164 output: Description:
212 11:08:20.633265 output: Created: Sun Mar 3 11:08:20 2024
213 11:08:20.633377 output: Type: Kernel Image
214 11:08:20.633525 output: Compression: lzma compressed
215 11:08:20.633649 output: Data Size: 12057697 Bytes = 11775.09 KiB = 11.50 MiB
216 11:08:20.633740 output: Architecture: AArch64
217 11:08:20.633840 output: OS: Linux
218 11:08:20.633944 output: Load Address: 0x00000000
219 11:08:20.634037 output: Entry Point: 0x00000000
220 11:08:20.634156 output: Hash algo: crc32
221 11:08:20.634246 output: Hash value: cf43f4f3
222 11:08:20.634332 output: Image 1 (fdt-1)
223 11:08:20.634466 output: Description: mt8192-asurada-spherion-r0
224 11:08:20.634553 output: Created: Sun Mar 3 11:08:20 2024
225 11:08:20.634636 output: Type: Flat Device Tree
226 11:08:20.634736 output: Compression: uncompressed
227 11:08:20.634812 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 11:08:20.634867 output: Architecture: AArch64
229 11:08:20.634921 output: Hash algo: crc32
230 11:08:20.634974 output: Hash value: cc4352de
231 11:08:20.635059 output: Image 2 (ramdisk-1)
232 11:08:20.635116 output: Description: unavailable
233 11:08:20.635174 output: Created: Sun Mar 3 11:08:20 2024
234 11:08:20.635228 output: Type: RAMDisk Image
235 11:08:20.635281 output: Compression: Unknown Compression
236 11:08:20.635358 output: Data Size: 39380225 Bytes = 38457.25 KiB = 37.56 MiB
237 11:08:20.635443 output: Architecture: AArch64
238 11:08:20.635527 output: OS: Linux
239 11:08:20.635612 output: Load Address: unavailable
240 11:08:20.635700 output: Entry Point: unavailable
241 11:08:20.635784 output: Hash algo: crc32
242 11:08:20.635898 output: Hash value: b97010f3
243 11:08:20.636010 output: Default Configuration: 'conf-1'
244 11:08:20.636094 output: Configuration 0 (conf-1)
245 11:08:20.636181 output: Description: mt8192-asurada-spherion-r0
246 11:08:20.636265 output: Kernel: kernel-1
247 11:08:20.636348 output: Init Ramdisk: ramdisk-1
248 11:08:20.636434 output: FDT: fdt-1
249 11:08:20.636517 output: Loadables: kernel-1
250 11:08:20.636603 output:
251 11:08:20.636851 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 11:08:20.636982 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 11:08:20.637128 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 11:08:20.637259 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 11:08:20.637379 No LXC device requested
256 11:08:20.637569 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:08:20.637722 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 11:08:20.637872 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:08:20.637978 Checking files for TFTP limit of 4294967296 bytes.
260 11:08:20.638709 end: 1 tftp-deploy (duration 00:00:22) [common]
261 11:08:20.638843 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:08:20.638970 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:08:20.639155 substitutions:
264 11:08:20.639265 - {DTB}: 12925658/tftp-deploy-8e9hyeki/dtb/mt8192-asurada-spherion-r0.dtb
265 11:08:20.639358 - {INITRD}: 12925658/tftp-deploy-8e9hyeki/ramdisk/ramdisk.cpio.gz
266 11:08:20.639449 - {KERNEL}: 12925658/tftp-deploy-8e9hyeki/kernel/Image
267 11:08:20.639566 - {LAVA_MAC}: None
268 11:08:20.639654 - {PRESEED_CONFIG}: None
269 11:08:20.639743 - {PRESEED_LOCAL}: None
270 11:08:20.639828 - {RAMDISK}: 12925658/tftp-deploy-8e9hyeki/ramdisk/ramdisk.cpio.gz
271 11:08:20.639913 - {ROOT_PART}: None
272 11:08:20.639999 - {ROOT}: None
273 11:08:20.640083 - {SERVER_IP}: 192.168.201.1
274 11:08:20.640166 - {TEE}: None
275 11:08:20.640252 Parsed boot commands:
276 11:08:20.640335 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:08:20.640560 Parsed boot commands: tftpboot 192.168.201.1 12925658/tftp-deploy-8e9hyeki/kernel/image.itb 12925658/tftp-deploy-8e9hyeki/kernel/cmdline
278 11:08:20.640680 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:08:20.640799 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:08:20.640919 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:08:20.641041 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:08:20.641141 Not connected, no need to disconnect.
283 11:08:20.641248 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:08:20.641361 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:08:20.641456 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 11:08:20.646088 Setting prompt string to ['lava-test: # ']
287 11:08:20.646601 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:08:20.646738 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:08:20.646867 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:08:20.646963 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:08:20.647236 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 11:08:25.785591 >> Command sent successfully.
293 11:08:25.788901 Returned 0 in 5 seconds
294 11:08:25.889290 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:08:25.889607 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:08:25.889706 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:08:25.889793 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:08:25.889865 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:08:25.889934 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:08:25.890199 [Enter `^Ec?' for help]
302 11:08:26.062453
303 11:08:26.062594
304 11:08:26.062669 F0: 102B 0000
305 11:08:26.062738
306 11:08:26.062799 F3: 1001 0000 [0200]
307 11:08:26.062858
308 11:08:26.066012 F3: 1001 0000
309 11:08:26.066095
310 11:08:26.066160 F7: 102D 0000
311 11:08:26.066221
312 11:08:26.069378 F1: 0000 0000
313 11:08:26.069461
314 11:08:26.069529 V0: 0000 0000 [0001]
315 11:08:26.069593
316 11:08:26.072339 00: 0007 8000
317 11:08:26.072426
318 11:08:26.072493 01: 0000 0000
319 11:08:26.072556
320 11:08:26.076281 BP: 0C00 0209 [0000]
321 11:08:26.076363
322 11:08:26.076428 G0: 1182 0000
323 11:08:26.076502
324 11:08:26.076616 EC: 0000 0021 [4000]
325 11:08:26.079296
326 11:08:26.079378 S7: 0000 0000 [0000]
327 11:08:26.079445
328 11:08:26.082465 CC: 0000 0000 [0001]
329 11:08:26.082561
330 11:08:26.082627 T0: 0000 0040 [010F]
331 11:08:26.082689
332 11:08:26.082747 Jump to BL
333 11:08:26.082804
334 11:08:26.109140
335 11:08:26.109231
336 11:08:26.109303
337 11:08:26.116719 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:08:26.120394 ARM64: Exception handlers installed.
339 11:08:26.124645 ARM64: Testing exception
340 11:08:26.124724 ARM64: Done test exception
341 11:08:26.134383 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:08:26.145187 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:08:26.151726 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:08:26.162278 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:08:26.168819 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:08:26.175712 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:08:26.186247 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:08:26.193254 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:08:26.211964 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:08:26.215349 WDT: Last reset was cold boot
351 11:08:26.218384 SPI1(PAD0) initialized at 2873684 Hz
352 11:08:26.221931 SPI5(PAD0) initialized at 992727 Hz
353 11:08:26.225151 VBOOT: Loading verstage.
354 11:08:26.231991 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:08:26.235417 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:08:26.239031 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:08:26.241977 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:08:26.249815 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:08:26.255814 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:08:26.266645 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
361 11:08:26.266729
362 11:08:26.266827
363 11:08:26.277270 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:08:26.280272 ARM64: Exception handlers installed.
365 11:08:26.283496 ARM64: Testing exception
366 11:08:26.283579 ARM64: Done test exception
367 11:08:26.290330 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:08:26.294125 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:08:26.308290 Probing TPM: . done!
370 11:08:26.308375 TPM ready after 0 ms
371 11:08:26.315220 Connected to device vid:did:rid of 1ae0:0028:00
372 11:08:26.322158 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 11:08:26.378868 Initialized TPM device CR50 revision 0
374 11:08:26.390948 tlcl_send_startup: Startup return code is 0
375 11:08:26.391042 TPM: setup succeeded
376 11:08:26.402187 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:08:26.411152 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:08:26.421871 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:08:26.432634 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:08:26.435332 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:08:26.444093 in-header: 03 07 00 00 08 00 00 00
382 11:08:26.447986 in-data: aa e4 47 04 13 02 00 00
383 11:08:26.451818 Chrome EC: UHEPI supported
384 11:08:26.459436 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:08:26.462646 in-header: 03 ad 00 00 08 00 00 00
386 11:08:26.466549 in-data: 00 20 20 08 00 00 00 00
387 11:08:26.466633 Phase 1
388 11:08:26.469777 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:08:26.477326 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:08:26.481163 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:08:26.485010 Recovery requested (1009000e)
392 11:08:26.492988 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:08:26.498633 tlcl_extend: response is 0
394 11:08:26.508367 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:08:26.513738 tlcl_extend: response is 0
396 11:08:26.520456 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:08:26.540989 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
398 11:08:26.547228 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:08:26.547313
400 11:08:26.547380
401 11:08:26.557731 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:08:26.561583 ARM64: Exception handlers installed.
403 11:08:26.561673 ARM64: Testing exception
404 11:08:26.565207 ARM64: Done test exception
405 11:08:26.585915 pmic_efuse_setting: Set efuses in 11 msecs
406 11:08:26.589233 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:08:26.596729 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:08:26.600749 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:08:26.603764 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:08:26.610567 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:08:26.614575 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:08:26.618067 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:08:26.625829 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:08:26.628864 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:08:26.633126 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:08:26.640384 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:08:26.644201 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:08:26.648051 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:08:26.651223 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:08:26.658703 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:08:26.665891 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:08:26.669538 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:08:26.676525 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:08:26.680240 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:08:26.687841 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:08:26.691413 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:08:26.698847 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:08:26.703181 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:08:26.709753 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:08:26.712976 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:08:26.720388 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:08:26.724780 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:08:26.731772 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:08:26.735414 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:08:26.739276 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:08:26.746195 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:08:26.749800 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:08:26.753613 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:08:26.761069 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:08:26.764893 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:08:26.768364 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:08:26.775724 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:08:26.779332 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:08:26.786694 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:08:26.790955 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:08:26.794508 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:08:26.798306 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:08:26.801438 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:08:26.805389 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:08:26.813308 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:08:26.817053 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:08:26.820599 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:08:26.824082 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:08:26.827634 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:08:26.831953 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:08:26.838884 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:08:26.842792 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:08:26.849837 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:08:26.857373 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:08:26.861133 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:08:26.871716 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:08:26.879826 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:08:26.883198 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:08:26.886590 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:08:26.890194 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:08:26.899981 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x26
467 11:08:26.903377 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:08:26.911226 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 11:08:26.914883 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:08:26.923251 [RTC]rtc_get_frequency_meter,154: input=15, output=790
471 11:08:26.932735 [RTC]rtc_get_frequency_meter,154: input=23, output=978
472 11:08:26.943169 [RTC]rtc_get_frequency_meter,154: input=19, output=884
473 11:08:26.952751 [RTC]rtc_get_frequency_meter,154: input=17, output=837
474 11:08:26.961933 [RTC]rtc_get_frequency_meter,154: input=16, output=814
475 11:08:26.971106 [RTC]rtc_get_frequency_meter,154: input=15, output=790
476 11:08:26.980959 [RTC]rtc_get_frequency_meter,154: input=16, output=813
477 11:08:26.985020 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 11:08:26.988752 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 11:08:26.992397 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:08:26.999712 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 11:08:27.003528 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:08:27.007407 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 11:08:27.010774 ADC[4]: Raw value=902066 ID=7
484 11:08:27.010877 ADC[3]: Raw value=213336 ID=1
485 11:08:27.014718 RAM Code: 0x71
486 11:08:27.018000 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:08:27.021589 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:08:27.033214 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 11:08:27.037505 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 11:08:27.040326 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:08:27.045271 in-header: 03 07 00 00 08 00 00 00
492 11:08:27.049008 in-data: aa e4 47 04 13 02 00 00
493 11:08:27.053330 Chrome EC: UHEPI supported
494 11:08:27.060229 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:08:27.063990 in-header: 03 ed 00 00 08 00 00 00
496 11:08:27.067608 in-data: 80 20 60 08 00 00 00 00
497 11:08:27.067691 MRC: failed to locate region type 0.
498 11:08:27.074677 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:08:27.078468 DRAM-K: Running full calibration
500 11:08:27.085435 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 11:08:27.085518 header.status = 0x0
502 11:08:27.089052 header.version = 0x6 (expected: 0x6)
503 11:08:27.093034 header.size = 0xd00 (expected: 0xd00)
504 11:08:27.097181 header.flags = 0x0
505 11:08:27.100261 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:08:27.119282 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
507 11:08:27.127310 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:08:27.127395 dram_init: ddr_geometry: 2
509 11:08:27.130706 [EMI] MDL number = 2
510 11:08:27.134090 [EMI] Get MDL freq = 0
511 11:08:27.134172 dram_init: ddr_type: 0
512 11:08:27.138434 is_discrete_lpddr4: 1
513 11:08:27.141571 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:08:27.141653
515 11:08:27.141718
516 11:08:27.141780 [Bian_co] ETT version 0.0.0.1
517 11:08:27.149376 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 11:08:27.149459
519 11:08:27.152939 dramc_set_vcore_voltage set vcore to 650000
520 11:08:27.153022 Read voltage for 800, 4
521 11:08:27.153089 Vio18 = 0
522 11:08:27.156752 Vcore = 650000
523 11:08:27.156862 Vdram = 0
524 11:08:27.156961 Vddq = 0
525 11:08:27.160136 Vmddr = 0
526 11:08:27.160247 dram_init: config_dvfs: 1
527 11:08:27.166848 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:08:27.170345 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:08:27.173578 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 11:08:27.180062 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 11:08:27.184033 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 11:08:27.187178 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 11:08:27.189992 MEM_TYPE=3, freq_sel=18
534 11:08:27.190074 sv_algorithm_assistance_LP4_1600
535 11:08:27.196782 ============ PULL DRAM RESETB DOWN ============
536 11:08:27.200422 ========== PULL DRAM RESETB DOWN end =========
537 11:08:27.203524 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:08:27.207233 ===================================
539 11:08:27.211210 LPDDR4 DRAM CONFIGURATION
540 11:08:27.213841 ===================================
541 11:08:27.217277 EX_ROW_EN[0] = 0x0
542 11:08:27.217377 EX_ROW_EN[1] = 0x0
543 11:08:27.220831 LP4Y_EN = 0x0
544 11:08:27.220927 WORK_FSP = 0x0
545 11:08:27.224021 WL = 0x2
546 11:08:27.224105 RL = 0x2
547 11:08:27.227152 BL = 0x2
548 11:08:27.227259 RPST = 0x0
549 11:08:27.230670 RD_PRE = 0x0
550 11:08:27.230752 WR_PRE = 0x1
551 11:08:27.233943 WR_PST = 0x0
552 11:08:27.234051 DBI_WR = 0x0
553 11:08:27.237244 DBI_RD = 0x0
554 11:08:27.237369 OTF = 0x1
555 11:08:27.240714 ===================================
556 11:08:27.244089 ===================================
557 11:08:27.247288 ANA top config
558 11:08:27.250303 ===================================
559 11:08:27.250384 DLL_ASYNC_EN = 0
560 11:08:27.253930 ALL_SLAVE_EN = 1
561 11:08:27.257604 NEW_RANK_MODE = 1
562 11:08:27.261006 DLL_IDLE_MODE = 1
563 11:08:27.264116 LP45_APHY_COMB_EN = 1
564 11:08:27.264197 TX_ODT_DIS = 1
565 11:08:27.267602 NEW_8X_MODE = 1
566 11:08:27.270679 ===================================
567 11:08:27.274252 ===================================
568 11:08:27.277275 data_rate = 1600
569 11:08:27.280749 CKR = 1
570 11:08:27.284367 DQ_P2S_RATIO = 8
571 11:08:27.287571 ===================================
572 11:08:27.287654 CA_P2S_RATIO = 8
573 11:08:27.290686 DQ_CA_OPEN = 0
574 11:08:27.293952 DQ_SEMI_OPEN = 0
575 11:08:27.297922 CA_SEMI_OPEN = 0
576 11:08:27.301045 CA_FULL_RATE = 0
577 11:08:27.303798 DQ_CKDIV4_EN = 1
578 11:08:27.303880 CA_CKDIV4_EN = 1
579 11:08:27.307789 CA_PREDIV_EN = 0
580 11:08:27.311106 PH8_DLY = 0
581 11:08:27.314613 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:08:27.317458 DQ_AAMCK_DIV = 4
583 11:08:27.317558 CA_AAMCK_DIV = 4
584 11:08:27.320981 CA_ADMCK_DIV = 4
585 11:08:27.324399 DQ_TRACK_CA_EN = 0
586 11:08:27.327959 CA_PICK = 800
587 11:08:27.331834 CA_MCKIO = 800
588 11:08:27.334649 MCKIO_SEMI = 0
589 11:08:27.338822 PLL_FREQ = 3068
590 11:08:27.338904 DQ_UI_PI_RATIO = 32
591 11:08:27.342033 CA_UI_PI_RATIO = 0
592 11:08:27.345588 ===================================
593 11:08:27.349881 ===================================
594 11:08:27.349964 memory_type:LPDDR4
595 11:08:27.353293 GP_NUM : 10
596 11:08:27.356423 SRAM_EN : 1
597 11:08:27.356504 MD32_EN : 0
598 11:08:27.360538 ===================================
599 11:08:27.364468 [ANA_INIT] >>>>>>>>>>>>>>
600 11:08:27.364550 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:08:27.367987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:08:27.371538 ===================================
603 11:08:27.374544 data_rate = 1600,PCW = 0X7600
604 11:08:27.378808 ===================================
605 11:08:27.381463 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:08:27.388507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:08:27.391508 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:08:27.398109 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:08:27.401662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:08:27.405021 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:08:27.405097 [ANA_INIT] flow start
612 11:08:27.408331 [ANA_INIT] PLL >>>>>>>>
613 11:08:27.411366 [ANA_INIT] PLL <<<<<<<<
614 11:08:27.411462 [ANA_INIT] MIDPI >>>>>>>>
615 11:08:27.415020 [ANA_INIT] MIDPI <<<<<<<<
616 11:08:27.418755 [ANA_INIT] DLL >>>>>>>>
617 11:08:27.418837 [ANA_INIT] flow end
618 11:08:27.425219 ============ LP4 DIFF to SE enter ============
619 11:08:27.428123 ============ LP4 DIFF to SE exit ============
620 11:08:27.432277 [ANA_INIT] <<<<<<<<<<<<<
621 11:08:27.435416 [Flow] Enable top DCM control >>>>>
622 11:08:27.438713 [Flow] Enable top DCM control <<<<<
623 11:08:27.438797 Enable DLL master slave shuffle
624 11:08:27.445222 ==============================================================
625 11:08:27.448659 Gating Mode config
626 11:08:27.451721 ==============================================================
627 11:08:27.455076 Config description:
628 11:08:27.465101 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:08:27.471970 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:08:27.475470 SELPH_MODE 0: By rank 1: By Phase
631 11:08:27.482226 ==============================================================
632 11:08:27.485601 GAT_TRACK_EN = 1
633 11:08:27.488903 RX_GATING_MODE = 2
634 11:08:27.488986 RX_GATING_TRACK_MODE = 2
635 11:08:27.492370 SELPH_MODE = 1
636 11:08:27.495578 PICG_EARLY_EN = 1
637 11:08:27.498977 VALID_LAT_VALUE = 1
638 11:08:27.505531 ==============================================================
639 11:08:27.508770 Enter into Gating configuration >>>>
640 11:08:27.512221 Exit from Gating configuration <<<<
641 11:08:27.515401 Enter into DVFS_PRE_config >>>>>
642 11:08:27.525826 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:08:27.529200 Exit from DVFS_PRE_config <<<<<
644 11:08:27.532207 Enter into PICG configuration >>>>
645 11:08:27.535481 Exit from PICG configuration <<<<
646 11:08:27.538831 [RX_INPUT] configuration >>>>>
647 11:08:27.538913 [RX_INPUT] configuration <<<<<
648 11:08:27.545822 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:08:27.552405 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:08:27.556058 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:08:27.563678 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:08:27.570129 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:08:27.576656 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:08:27.579803 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:08:27.583003 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:08:27.587123 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:08:27.593681 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:08:27.597191 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:08:27.600543 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:08:27.603702 ===================================
661 11:08:27.606767 LPDDR4 DRAM CONFIGURATION
662 11:08:27.610433 ===================================
663 11:08:27.610515 EX_ROW_EN[0] = 0x0
664 11:08:27.613709 EX_ROW_EN[1] = 0x0
665 11:08:27.616872 LP4Y_EN = 0x0
666 11:08:27.616976 WORK_FSP = 0x0
667 11:08:27.620006 WL = 0x2
668 11:08:27.620087 RL = 0x2
669 11:08:27.623649 BL = 0x2
670 11:08:27.623757 RPST = 0x0
671 11:08:27.627136 RD_PRE = 0x0
672 11:08:27.627218 WR_PRE = 0x1
673 11:08:27.630475 WR_PST = 0x0
674 11:08:27.630558 DBI_WR = 0x0
675 11:08:27.634038 DBI_RD = 0x0
676 11:08:27.634121 OTF = 0x1
677 11:08:27.636895 ===================================
678 11:08:27.640432 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:08:27.647228 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:08:27.650887 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:08:27.653714 ===================================
682 11:08:27.657820 LPDDR4 DRAM CONFIGURATION
683 11:08:27.660414 ===================================
684 11:08:27.660575 EX_ROW_EN[0] = 0x10
685 11:08:27.664417 EX_ROW_EN[1] = 0x0
686 11:08:27.664582 LP4Y_EN = 0x0
687 11:08:27.667986 WORK_FSP = 0x0
688 11:08:27.668094 WL = 0x2
689 11:08:27.670547 RL = 0x2
690 11:08:27.670649 BL = 0x2
691 11:08:27.673888 RPST = 0x0
692 11:08:27.674001 RD_PRE = 0x0
693 11:08:27.677246 WR_PRE = 0x1
694 11:08:27.677365 WR_PST = 0x0
695 11:08:27.680785 DBI_WR = 0x0
696 11:08:27.680895 DBI_RD = 0x0
697 11:08:27.683901 OTF = 0x1
698 11:08:27.687430 ===================================
699 11:08:27.694139 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:08:27.697493 nWR fixed to 40
701 11:08:27.700642 [ModeRegInit_LP4] CH0 RK0
702 11:08:27.700745 [ModeRegInit_LP4] CH0 RK1
703 11:08:27.704730 [ModeRegInit_LP4] CH1 RK0
704 11:08:27.707530 [ModeRegInit_LP4] CH1 RK1
705 11:08:27.707612 match AC timing 13
706 11:08:27.714255 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 11:08:27.717653 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:08:27.720623 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:08:27.727747 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:08:27.730797 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:08:27.730879 [EMI DOE] emi_dcm 0
712 11:08:27.737672 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:08:27.737755 ==
714 11:08:27.741454 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:08:27.744358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 11:08:27.744442 ==
717 11:08:27.751270 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:08:27.754234 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:08:27.764465 [CA 0] Center 37 (7~68) winsize 62
720 11:08:27.767661 [CA 1] Center 37 (6~68) winsize 63
721 11:08:27.771286 [CA 2] Center 35 (5~66) winsize 62
722 11:08:27.775198 [CA 3] Center 34 (4~65) winsize 62
723 11:08:27.778205 [CA 4] Center 34 (3~65) winsize 63
724 11:08:27.781197 [CA 5] Center 33 (3~64) winsize 62
725 11:08:27.781280
726 11:08:27.784887 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 11:08:27.784970
728 11:08:27.787780 [CATrainingPosCal] consider 1 rank data
729 11:08:27.791750 u2DelayCellTimex100 = 270/100 ps
730 11:08:27.794479 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 11:08:27.797726 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 11:08:27.804718 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 11:08:27.808443 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 11:08:27.811448 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 11:08:27.814593 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 11:08:27.814710
737 11:08:27.818126 CA PerBit enable=1, Macro0, CA PI delay=33
738 11:08:27.818227
739 11:08:27.821497 [CBTSetCACLKResult] CA Dly = 33
740 11:08:27.821579 CS Dly: 5 (0~36)
741 11:08:27.821643 ==
742 11:08:27.825054 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:08:27.831439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 11:08:27.831522 ==
745 11:08:27.834900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:08:27.841704 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:08:27.851114 [CA 0] Center 37 (6~68) winsize 63
748 11:08:27.854068 [CA 1] Center 37 (7~68) winsize 62
749 11:08:27.857322 [CA 2] Center 35 (4~66) winsize 63
750 11:08:27.860746 [CA 3] Center 35 (4~66) winsize 63
751 11:08:27.864542 [CA 4] Center 34 (3~65) winsize 63
752 11:08:27.867739 [CA 5] Center 33 (3~64) winsize 62
753 11:08:27.867820
754 11:08:27.871049 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:08:27.871157
756 11:08:27.874218 [CATrainingPosCal] consider 2 rank data
757 11:08:27.877741 u2DelayCellTimex100 = 270/100 ps
758 11:08:27.880923 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 11:08:27.884528 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 11:08:27.891277 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 11:08:27.894694 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 11:08:27.897582 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
763 11:08:27.901356 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 11:08:27.901434
765 11:08:27.905369 CA PerBit enable=1, Macro0, CA PI delay=33
766 11:08:27.905443
767 11:08:27.907510 [CBTSetCACLKResult] CA Dly = 33
768 11:08:27.907580 CS Dly: 5 (0~37)
769 11:08:27.907641
770 11:08:27.910839 ----->DramcWriteLeveling(PI) begin...
771 11:08:27.910910 ==
772 11:08:27.914378 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:08:27.921706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:08:27.921814 ==
775 11:08:27.921908 Write leveling (Byte 0): 30 => 30
776 11:08:27.925971 Write leveling (Byte 1): 30 => 30
777 11:08:27.929398 DramcWriteLeveling(PI) end<-----
778 11:08:27.929479
779 11:08:27.929545 ==
780 11:08:27.933050 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:08:27.937124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:08:27.937207 ==
783 11:08:27.939873 [Gating] SW mode calibration
784 11:08:27.947416 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:08:27.950686 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:08:27.957539 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 11:08:27.960747 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 11:08:27.964499 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 11:08:27.970830 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
790 11:08:27.974374 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:08:27.977653 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:08:27.984172 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:08:27.988156 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:08:27.990845 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:08:27.997584 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:08:28.001223 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:08:28.004584 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:08:28.008065 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:08:28.014333 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:08:28.018215 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:08:28.021105 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:08:28.027944 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:08:28.031271 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:08:28.034624 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
805 11:08:28.041286 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
806 11:08:28.044467 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:08:28.048653 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:08:28.055096 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:08:28.058052 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:08:28.061615 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:08:28.068149 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:08:28.071264 0 9 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
813 11:08:28.074820 0 9 12 | B1->B0 | 2626 2f2f | 0 1 | (0 0) (1 1)
814 11:08:28.078912 0 9 16 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
815 11:08:28.084881 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:08:28.088555 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 11:08:28.092228 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:08:28.098315 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:08:28.102340 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 11:08:28.105338 0 10 8 | B1->B0 | 3434 3030 | 0 1 | (0 1) (1 0)
821 11:08:28.111752 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
822 11:08:28.114965 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:08:28.118362 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:08:28.125120 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:08:28.128114 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:08:28.132085 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:08:28.139258 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:08:28.142077 0 11 8 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
829 11:08:28.145035 0 11 12 | B1->B0 | 3838 4242 | 0 0 | (0 0) (0 0)
830 11:08:28.148227 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:08:28.155261 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:08:28.158859 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 11:08:28.162191 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:08:28.168549 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:08:28.171918 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 11:08:28.174956 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 11:08:28.181787 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
838 11:08:28.185001 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:08:28.188721 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:08:28.195688 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:08:28.198347 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:08:28.201716 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:08:28.208667 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:08:28.212183 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:08:28.215500 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:08:28.218640 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:08:28.225527 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:08:28.228718 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:08:28.232434 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:08:28.238911 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:08:28.242336 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 11:08:28.245776 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 11:08:28.252360 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 11:08:28.252469 Total UI for P1: 0, mck2ui 16
855 11:08:28.259110 best dqsien dly found for B0: ( 0, 14, 8)
856 11:08:28.262297 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 11:08:28.265911 Total UI for P1: 0, mck2ui 16
858 11:08:28.269051 best dqsien dly found for B1: ( 0, 14, 10)
859 11:08:28.272270 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
860 11:08:28.275976 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 11:08:28.276058
862 11:08:28.279027 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 11:08:28.282322 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 11:08:28.285554 [Gating] SW calibration Done
865 11:08:28.285640 ==
866 11:08:28.289088 Dram Type= 6, Freq= 0, CH_0, rank 0
867 11:08:28.292629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 11:08:28.292716 ==
869 11:08:28.296305 RX Vref Scan: 0
870 11:08:28.296392
871 11:08:28.299195 RX Vref 0 -> 0, step: 1
872 11:08:28.299281
873 11:08:28.299370 RX Delay -130 -> 252, step: 16
874 11:08:28.305825 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 11:08:28.308769 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 11:08:28.312985 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
877 11:08:28.316156 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 11:08:28.318854 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 11:08:28.325708 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
880 11:08:28.329448 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
881 11:08:28.332482 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
882 11:08:28.335825 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
883 11:08:28.339076 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
884 11:08:28.346077 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
885 11:08:28.349202 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 11:08:28.352468 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
887 11:08:28.355807 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
888 11:08:28.359295 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 11:08:28.366153 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
890 11:08:28.366236 ==
891 11:08:28.369488 Dram Type= 6, Freq= 0, CH_0, rank 0
892 11:08:28.372492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 11:08:28.372578 ==
894 11:08:28.372643 DQS Delay:
895 11:08:28.376463 DQS0 = 0, DQS1 = 0
896 11:08:28.376550 DQM Delay:
897 11:08:28.379367 DQM0 = 85, DQM1 = 77
898 11:08:28.379453 DQ Delay:
899 11:08:28.382990 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
900 11:08:28.386271 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
901 11:08:28.389345 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
902 11:08:28.392581 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
903 11:08:28.392667
904 11:08:28.392754
905 11:08:28.392837 ==
906 11:08:28.395877 Dram Type= 6, Freq= 0, CH_0, rank 0
907 11:08:28.399420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 11:08:28.399506 ==
909 11:08:28.399595
910 11:08:28.399677
911 11:08:28.402644 TX Vref Scan disable
912 11:08:28.406334 == TX Byte 0 ==
913 11:08:28.409440 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
914 11:08:28.412657 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
915 11:08:28.416543 == TX Byte 1 ==
916 11:08:28.419665 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
917 11:08:28.423003 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
918 11:08:28.423085 ==
919 11:08:28.426121 Dram Type= 6, Freq= 0, CH_0, rank 0
920 11:08:28.429741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 11:08:28.433215 ==
922 11:08:28.444442 TX Vref=22, minBit 0, minWin=27, winSum=439
923 11:08:28.447857 TX Vref=24, minBit 5, minWin=27, winSum=443
924 11:08:28.451216 TX Vref=26, minBit 5, minWin=27, winSum=446
925 11:08:28.454358 TX Vref=28, minBit 3, minWin=27, winSum=451
926 11:08:28.457570 TX Vref=30, minBit 2, minWin=28, winSum=452
927 11:08:28.461355 TX Vref=32, minBit 2, minWin=28, winSum=453
928 11:08:28.467951 [TxChooseVref] Worse bit 2, Min win 28, Win sum 453, Final Vref 32
929 11:08:28.468033
930 11:08:28.471193 Final TX Range 1 Vref 32
931 11:08:28.471275
932 11:08:28.471341 ==
933 11:08:28.474564 Dram Type= 6, Freq= 0, CH_0, rank 0
934 11:08:28.477976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 11:08:28.478059 ==
936 11:08:28.478125
937 11:08:28.478186
938 11:08:28.481155 TX Vref Scan disable
939 11:08:28.485103 == TX Byte 0 ==
940 11:08:28.487867 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
941 11:08:28.491418 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
942 11:08:28.494689 == TX Byte 1 ==
943 11:08:28.497875 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
944 11:08:28.501617 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
945 11:08:28.501699
946 11:08:28.505047 [DATLAT]
947 11:08:28.505129 Freq=800, CH0 RK0
948 11:08:28.505194
949 11:08:28.508337 DATLAT Default: 0xa
950 11:08:28.508418 0, 0xFFFF, sum = 0
951 11:08:28.512226 1, 0xFFFF, sum = 0
952 11:08:28.512311 2, 0xFFFF, sum = 0
953 11:08:28.514615 3, 0xFFFF, sum = 0
954 11:08:28.514698 4, 0xFFFF, sum = 0
955 11:08:28.518633 5, 0xFFFF, sum = 0
956 11:08:28.518716 6, 0xFFFF, sum = 0
957 11:08:28.521757 7, 0xFFFF, sum = 0
958 11:08:28.521840 8, 0xFFFF, sum = 0
959 11:08:28.525527 9, 0x0, sum = 1
960 11:08:28.525610 10, 0x0, sum = 2
961 11:08:28.527962 11, 0x0, sum = 3
962 11:08:28.528045 12, 0x0, sum = 4
963 11:08:28.531924 best_step = 10
964 11:08:28.532006
965 11:08:28.532071 ==
966 11:08:28.534948 Dram Type= 6, Freq= 0, CH_0, rank 0
967 11:08:28.538283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 11:08:28.538391 ==
969 11:08:28.538502 RX Vref Scan: 1
970 11:08:28.541425
971 11:08:28.541506 Set Vref Range= 32 -> 127
972 11:08:28.541572
973 11:08:28.544724 RX Vref 32 -> 127, step: 1
974 11:08:28.544806
975 11:08:28.548651 RX Delay -95 -> 252, step: 8
976 11:08:28.548732
977 11:08:28.551666 Set Vref, RX VrefLevel [Byte0]: 32
978 11:08:28.555285 [Byte1]: 32
979 11:08:28.555367
980 11:08:28.558661 Set Vref, RX VrefLevel [Byte0]: 33
981 11:08:28.562363 [Byte1]: 33
982 11:08:28.562493
983 11:08:28.565629 Set Vref, RX VrefLevel [Byte0]: 34
984 11:08:28.568782 [Byte1]: 34
985 11:08:28.568889
986 11:08:28.572816 Set Vref, RX VrefLevel [Byte0]: 35
987 11:08:28.575665 [Byte1]: 35
988 11:08:28.580204
989 11:08:28.580289 Set Vref, RX VrefLevel [Byte0]: 36
990 11:08:28.583127 [Byte1]: 36
991 11:08:28.587576
992 11:08:28.587661 Set Vref, RX VrefLevel [Byte0]: 37
993 11:08:28.590697 [Byte1]: 37
994 11:08:28.595837
995 11:08:28.595923 Set Vref, RX VrefLevel [Byte0]: 38
996 11:08:28.598746 [Byte1]: 38
997 11:08:28.602915
998 11:08:28.603001 Set Vref, RX VrefLevel [Byte0]: 39
999 11:08:28.606537 [Byte1]: 39
1000 11:08:28.610248
1001 11:08:28.610334 Set Vref, RX VrefLevel [Byte0]: 40
1002 11:08:28.613760 [Byte1]: 40
1003 11:08:28.617754
1004 11:08:28.621366 Set Vref, RX VrefLevel [Byte0]: 41
1005 11:08:28.621469 [Byte1]: 41
1006 11:08:28.625047
1007 11:08:28.625119 Set Vref, RX VrefLevel [Byte0]: 42
1008 11:08:28.628292 [Byte1]: 42
1009 11:08:28.632955
1010 11:08:28.633044 Set Vref, RX VrefLevel [Byte0]: 43
1011 11:08:28.635986 [Byte1]: 43
1012 11:08:28.640221
1013 11:08:28.640329 Set Vref, RX VrefLevel [Byte0]: 44
1014 11:08:28.643987 [Byte1]: 44
1015 11:08:28.647870
1016 11:08:28.647977 Set Vref, RX VrefLevel [Byte0]: 45
1017 11:08:28.651357 [Byte1]: 45
1018 11:08:28.655707
1019 11:08:28.655780 Set Vref, RX VrefLevel [Byte0]: 46
1020 11:08:28.659188 [Byte1]: 46
1021 11:08:28.663602
1022 11:08:28.663684 Set Vref, RX VrefLevel [Byte0]: 47
1023 11:08:28.666582 [Byte1]: 47
1024 11:08:28.670764
1025 11:08:28.670849 Set Vref, RX VrefLevel [Byte0]: 48
1026 11:08:28.674536 [Byte1]: 48
1027 11:08:28.678627
1028 11:08:28.678707 Set Vref, RX VrefLevel [Byte0]: 49
1029 11:08:28.681817 [Byte1]: 49
1030 11:08:28.686187
1031 11:08:28.686268 Set Vref, RX VrefLevel [Byte0]: 50
1032 11:08:28.689162 [Byte1]: 50
1033 11:08:28.693904
1034 11:08:28.693984 Set Vref, RX VrefLevel [Byte0]: 51
1035 11:08:28.696909 [Byte1]: 51
1036 11:08:28.701195
1037 11:08:28.701278 Set Vref, RX VrefLevel [Byte0]: 52
1038 11:08:28.704261 [Byte1]: 52
1039 11:08:28.708868
1040 11:08:28.708948 Set Vref, RX VrefLevel [Byte0]: 53
1041 11:08:28.711988 [Byte1]: 53
1042 11:08:28.716683
1043 11:08:28.716762 Set Vref, RX VrefLevel [Byte0]: 54
1044 11:08:28.719618 [Byte1]: 54
1045 11:08:28.724066
1046 11:08:28.724148 Set Vref, RX VrefLevel [Byte0]: 55
1047 11:08:28.727530 [Byte1]: 55
1048 11:08:28.731756
1049 11:08:28.731837 Set Vref, RX VrefLevel [Byte0]: 56
1050 11:08:28.734777 [Byte1]: 56
1051 11:08:28.739154
1052 11:08:28.739261 Set Vref, RX VrefLevel [Byte0]: 57
1053 11:08:28.742746 [Byte1]: 57
1054 11:08:28.746538
1055 11:08:28.746618 Set Vref, RX VrefLevel [Byte0]: 58
1056 11:08:28.750283 [Byte1]: 58
1057 11:08:28.754474
1058 11:08:28.754555 Set Vref, RX VrefLevel [Byte0]: 59
1059 11:08:28.757716 [Byte1]: 59
1060 11:08:28.762209
1061 11:08:28.762316 Set Vref, RX VrefLevel [Byte0]: 60
1062 11:08:28.765333 [Byte1]: 60
1063 11:08:28.769343
1064 11:08:28.769444 Set Vref, RX VrefLevel [Byte0]: 61
1065 11:08:28.773051 [Byte1]: 61
1066 11:08:28.777517
1067 11:08:28.777593 Set Vref, RX VrefLevel [Byte0]: 62
1068 11:08:28.780919 [Byte1]: 62
1069 11:08:28.784786
1070 11:08:28.784885 Set Vref, RX VrefLevel [Byte0]: 63
1071 11:08:28.788294 [Byte1]: 63
1072 11:08:28.792223
1073 11:08:28.792296 Set Vref, RX VrefLevel [Byte0]: 64
1074 11:08:28.795952 [Byte1]: 64
1075 11:08:28.800124
1076 11:08:28.800192 Set Vref, RX VrefLevel [Byte0]: 65
1077 11:08:28.803539 [Byte1]: 65
1078 11:08:28.807211
1079 11:08:28.807305 Set Vref, RX VrefLevel [Byte0]: 66
1080 11:08:28.810893 [Byte1]: 66
1081 11:08:28.814876
1082 11:08:28.814957 Set Vref, RX VrefLevel [Byte0]: 67
1083 11:08:28.818675 [Byte1]: 67
1084 11:08:28.822617
1085 11:08:28.822697 Set Vref, RX VrefLevel [Byte0]: 68
1086 11:08:28.826169 [Byte1]: 68
1087 11:08:28.830101
1088 11:08:28.830207 Set Vref, RX VrefLevel [Byte0]: 69
1089 11:08:28.836934 [Byte1]: 69
1090 11:08:28.837014
1091 11:08:28.840178 Set Vref, RX VrefLevel [Byte0]: 70
1092 11:08:28.843666 [Byte1]: 70
1093 11:08:28.843746
1094 11:08:28.846855 Set Vref, RX VrefLevel [Byte0]: 71
1095 11:08:28.849999 [Byte1]: 71
1096 11:08:28.850081
1097 11:08:28.853686 Set Vref, RX VrefLevel [Byte0]: 72
1098 11:08:28.857161 [Byte1]: 72
1099 11:08:28.861083
1100 11:08:28.861164 Set Vref, RX VrefLevel [Byte0]: 73
1101 11:08:28.863844 [Byte1]: 73
1102 11:08:28.868270
1103 11:08:28.868350 Set Vref, RX VrefLevel [Byte0]: 74
1104 11:08:28.871953 [Byte1]: 74
1105 11:08:28.875697
1106 11:08:28.875778 Set Vref, RX VrefLevel [Byte0]: 75
1107 11:08:28.879592 [Byte1]: 75
1108 11:08:28.883894
1109 11:08:28.883975 Set Vref, RX VrefLevel [Byte0]: 76
1110 11:08:28.886928 [Byte1]: 76
1111 11:08:28.891398
1112 11:08:28.891492 Set Vref, RX VrefLevel [Byte0]: 77
1113 11:08:28.894781 [Byte1]: 77
1114 11:08:28.898919
1115 11:08:28.898999 Final RX Vref Byte 0 = 62 to rank0
1116 11:08:28.902614 Final RX Vref Byte 1 = 58 to rank0
1117 11:08:28.905142 Final RX Vref Byte 0 = 62 to rank1
1118 11:08:28.908415 Final RX Vref Byte 1 = 58 to rank1==
1119 11:08:28.912031 Dram Type= 6, Freq= 0, CH_0, rank 0
1120 11:08:28.915629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1121 11:08:28.918773 ==
1122 11:08:28.918854 DQS Delay:
1123 11:08:28.918919 DQS0 = 0, DQS1 = 0
1124 11:08:28.922113 DQM Delay:
1125 11:08:28.922193 DQM0 = 88, DQM1 = 79
1126 11:08:28.925321 DQ Delay:
1127 11:08:28.925401 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1128 11:08:28.928802 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1129 11:08:28.932526 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1130 11:08:28.936132 DQ12 =88, DQ13 =80, DQ14 =88, DQ15 =88
1131 11:08:28.936212
1132 11:08:28.936280
1133 11:08:28.945730 [DQSOSCAuto] RK0, (LSB)MR18= 0x280f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 399 ps
1134 11:08:28.948901 CH0 RK0: MR19=606, MR18=280F
1135 11:08:28.952488 CH0_RK0: MR19=0x606, MR18=0x280F, DQSOSC=399, MR23=63, INC=92, DEC=61
1136 11:08:28.955713
1137 11:08:28.959225 ----->DramcWriteLeveling(PI) begin...
1138 11:08:28.959325 ==
1139 11:08:28.962745 Dram Type= 6, Freq= 0, CH_0, rank 1
1140 11:08:28.965524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1141 11:08:28.965666 ==
1142 11:08:28.969162 Write leveling (Byte 0): 27 => 27
1143 11:08:28.972414 Write leveling (Byte 1): 26 => 26
1144 11:08:28.975840 DramcWriteLeveling(PI) end<-----
1145 11:08:28.975927
1146 11:08:28.975991 ==
1147 11:08:28.979281 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 11:08:28.982703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 11:08:28.982785 ==
1150 11:08:28.985803 [Gating] SW mode calibration
1151 11:08:28.992989 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1152 11:08:29.037157 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1153 11:08:29.037748 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 11:08:29.038202 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1155 11:08:29.038615 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1156 11:08:29.038697 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:08:29.038762 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 11:08:29.039550 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:08:29.039942 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:08:29.040016 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:08:29.040090 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:08:29.078761 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:08:29.079031 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:08:29.079285 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:08:29.079352 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:08:29.080081 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:08:29.080462 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:08:29.080866 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:08:29.081723 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1170 11:08:29.081788 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1171 11:08:29.082658 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1172 11:08:29.085229 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:08:29.091393 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 11:08:29.094705 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:08:29.097726 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:08:29.104399 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:08:29.107815 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:08:29.111079 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:08:29.114434 0 9 8 | B1->B0 | 2323 3030 | 1 1 | (1 1) (1 1)
1180 11:08:29.121561 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1181 11:08:29.124576 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 11:08:29.127957 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 11:08:29.134704 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 11:08:29.137809 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 11:08:29.141653 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 11:08:29.148446 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
1187 11:08:29.151818 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
1188 11:08:29.154954 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
1189 11:08:29.161832 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 11:08:29.164802 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:08:29.169041 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:08:29.172253 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 11:08:29.175922 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 11:08:29.183714 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1195 11:08:29.187031 0 11 8 | B1->B0 | 2727 3d3d | 0 1 | (0 0) (0 0)
1196 11:08:29.190456 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1197 11:08:29.193536 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 11:08:29.201549 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 11:08:29.204441 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 11:08:29.207756 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 11:08:29.214302 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 11:08:29.217957 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1203 11:08:29.220921 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1204 11:08:29.227707 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1205 11:08:29.231114 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 11:08:29.234390 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:08:29.237860 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:08:29.244625 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:08:29.247685 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:08:29.251554 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:08:29.257936 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:08:29.261555 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:08:29.264462 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:08:29.271663 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:08:29.275046 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:08:29.277943 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:08:29.284571 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 11:08:29.288117 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 11:08:29.291306 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1220 11:08:29.294794 Total UI for P1: 0, mck2ui 16
1221 11:08:29.298086 best dqsien dly found for B0: ( 0, 14, 6)
1222 11:08:29.301577 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 11:08:29.305085 Total UI for P1: 0, mck2ui 16
1224 11:08:29.307946 best dqsien dly found for B1: ( 0, 14, 8)
1225 11:08:29.311829 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1226 11:08:29.314815 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1227 11:08:29.314896
1228 11:08:29.321644 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1229 11:08:29.325008 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1230 11:08:29.325090 [Gating] SW calibration Done
1231 11:08:29.328624 ==
1232 11:08:29.332103 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 11:08:29.334930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 11:08:29.335012 ==
1235 11:08:29.335077 RX Vref Scan: 0
1236 11:08:29.335137
1237 11:08:29.338342 RX Vref 0 -> 0, step: 1
1238 11:08:29.338460
1239 11:08:29.341807 RX Delay -130 -> 252, step: 16
1240 11:08:29.345717 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1241 11:08:29.349514 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1242 11:08:29.351706 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1243 11:08:29.358839 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1244 11:08:29.362323 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1245 11:08:29.365457 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1246 11:08:29.369009 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1247 11:08:29.371936 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1248 11:08:29.379063 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1249 11:08:29.382282 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1250 11:08:29.385752 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1251 11:08:29.388688 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1252 11:08:29.392646 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1253 11:08:29.398688 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1254 11:08:29.402657 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1255 11:08:29.405760 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1256 11:08:29.405831 ==
1257 11:08:29.408866 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 11:08:29.411920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 11:08:29.412002 ==
1260 11:08:29.415441 DQS Delay:
1261 11:08:29.415522 DQS0 = 0, DQS1 = 0
1262 11:08:29.415586 DQM Delay:
1263 11:08:29.418990 DQM0 = 83, DQM1 = 73
1264 11:08:29.419070 DQ Delay:
1265 11:08:29.422054 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1266 11:08:29.425519 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
1267 11:08:29.428901 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1268 11:08:29.432246 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
1269 11:08:29.432327
1270 11:08:29.432392
1271 11:08:29.432456 ==
1272 11:08:29.435880 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 11:08:29.442215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 11:08:29.442326 ==
1275 11:08:29.442457
1276 11:08:29.442556
1277 11:08:29.442644 TX Vref Scan disable
1278 11:08:29.445873 == TX Byte 0 ==
1279 11:08:29.449060 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1280 11:08:29.452284 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1281 11:08:29.456349 == TX Byte 1 ==
1282 11:08:29.458899 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1283 11:08:29.462376 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1284 11:08:29.466106 ==
1285 11:08:29.469124 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 11:08:29.472578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 11:08:29.472652 ==
1288 11:08:29.485421 TX Vref=22, minBit 9, minWin=26, winSum=436
1289 11:08:29.488378 TX Vref=24, minBit 9, minWin=26, winSum=435
1290 11:08:29.491792 TX Vref=26, minBit 9, minWin=26, winSum=439
1291 11:08:29.495347 TX Vref=28, minBit 9, minWin=27, winSum=447
1292 11:08:29.498355 TX Vref=30, minBit 8, minWin=27, winSum=445
1293 11:08:29.501548 TX Vref=32, minBit 8, minWin=27, winSum=443
1294 11:08:29.508692 [TxChooseVref] Worse bit 9, Min win 27, Win sum 447, Final Vref 28
1295 11:08:29.508773
1296 11:08:29.511897 Final TX Range 1 Vref 28
1297 11:08:29.511978
1298 11:08:29.512042 ==
1299 11:08:29.515337 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 11:08:29.518327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 11:08:29.518438 ==
1302 11:08:29.518504
1303 11:08:29.518564
1304 11:08:29.521594 TX Vref Scan disable
1305 11:08:29.525161 == TX Byte 0 ==
1306 11:08:29.528330 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1307 11:08:29.531627 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1308 11:08:29.534973 == TX Byte 1 ==
1309 11:08:29.538202 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1310 11:08:29.541654 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1311 11:08:29.545045
1312 11:08:29.545126 [DATLAT]
1313 11:08:29.545190 Freq=800, CH0 RK1
1314 11:08:29.545252
1315 11:08:29.548577 DATLAT Default: 0xa
1316 11:08:29.548657 0, 0xFFFF, sum = 0
1317 11:08:29.551663 1, 0xFFFF, sum = 0
1318 11:08:29.551745 2, 0xFFFF, sum = 0
1319 11:08:29.555004 3, 0xFFFF, sum = 0
1320 11:08:29.555076 4, 0xFFFF, sum = 0
1321 11:08:29.558752 5, 0xFFFF, sum = 0
1322 11:08:29.558834 6, 0xFFFF, sum = 0
1323 11:08:29.561751 7, 0xFFFF, sum = 0
1324 11:08:29.561862 8, 0xFFFF, sum = 0
1325 11:08:29.565011 9, 0x0, sum = 1
1326 11:08:29.565093 10, 0x0, sum = 2
1327 11:08:29.568897 11, 0x0, sum = 3
1328 11:08:29.568978 12, 0x0, sum = 4
1329 11:08:29.572029 best_step = 10
1330 11:08:29.572113
1331 11:08:29.572179 ==
1332 11:08:29.575506 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 11:08:29.578760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 11:08:29.578841 ==
1335 11:08:29.581984 RX Vref Scan: 0
1336 11:08:29.582064
1337 11:08:29.582133 RX Vref 0 -> 0, step: 1
1338 11:08:29.582196
1339 11:08:29.585376 RX Delay -95 -> 252, step: 8
1340 11:08:29.591906 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1341 11:08:29.595602 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1342 11:08:29.599124 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1343 11:08:29.601878 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1344 11:08:29.605171 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1345 11:08:29.608902 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1346 11:08:29.615629 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1347 11:08:29.618732 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1348 11:08:29.622009 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1349 11:08:29.625953 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1350 11:08:29.628806 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1351 11:08:29.635383 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1352 11:08:29.639088 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1353 11:08:29.642148 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1354 11:08:29.645734 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1355 11:08:29.649174 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1356 11:08:29.652448 ==
1357 11:08:29.655585 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 11:08:29.658949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 11:08:29.659034 ==
1360 11:08:29.659103 DQS Delay:
1361 11:08:29.662567 DQS0 = 0, DQS1 = 0
1362 11:08:29.662643 DQM Delay:
1363 11:08:29.665802 DQM0 = 87, DQM1 = 78
1364 11:08:29.665922 DQ Delay:
1365 11:08:29.669131 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1366 11:08:29.672470 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1367 11:08:29.675711 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1368 11:08:29.678871 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1369 11:08:29.678989
1370 11:08:29.679099
1371 11:08:29.685559 [DQSOSCAuto] RK1, (LSB)MR18= 0x321b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1372 11:08:29.689187 CH0 RK1: MR19=606, MR18=321B
1373 11:08:29.695505 CH0_RK1: MR19=0x606, MR18=0x321B, DQSOSC=397, MR23=63, INC=93, DEC=62
1374 11:08:29.699242 [RxdqsGatingPostProcess] freq 800
1375 11:08:29.702739 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1376 11:08:29.706017 Pre-setting of DQS Precalculation
1377 11:08:29.712378 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1378 11:08:29.712459 ==
1379 11:08:29.716268 Dram Type= 6, Freq= 0, CH_1, rank 0
1380 11:08:29.720064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 11:08:29.720189 ==
1382 11:08:29.725978 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1383 11:08:29.729396 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1384 11:08:29.740209 [CA 0] Center 36 (6~66) winsize 61
1385 11:08:29.743082 [CA 1] Center 36 (6~66) winsize 61
1386 11:08:29.746270 [CA 2] Center 34 (4~65) winsize 62
1387 11:08:29.749894 [CA 3] Center 34 (3~65) winsize 63
1388 11:08:29.753805 [CA 4] Center 34 (4~65) winsize 62
1389 11:08:29.756385 [CA 5] Center 33 (3~64) winsize 62
1390 11:08:29.756465
1391 11:08:29.759820 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1392 11:08:29.759898
1393 11:08:29.763029 [CATrainingPosCal] consider 1 rank data
1394 11:08:29.766270 u2DelayCellTimex100 = 270/100 ps
1395 11:08:29.769736 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1396 11:08:29.772817 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1397 11:08:29.779856 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1398 11:08:29.783102 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1399 11:08:29.786194 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1400 11:08:29.789490 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1401 11:08:29.789570
1402 11:08:29.793172 CA PerBit enable=1, Macro0, CA PI delay=33
1403 11:08:29.793253
1404 11:08:29.796590 [CBTSetCACLKResult] CA Dly = 33
1405 11:08:29.796672 CS Dly: 4 (0~35)
1406 11:08:29.796737 ==
1407 11:08:29.799783 Dram Type= 6, Freq= 0, CH_1, rank 1
1408 11:08:29.806773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 11:08:29.806855 ==
1410 11:08:29.809857 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1411 11:08:29.816769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1412 11:08:29.825757 [CA 0] Center 36 (6~67) winsize 62
1413 11:08:29.829852 [CA 1] Center 36 (6~67) winsize 62
1414 11:08:29.832943 [CA 2] Center 34 (4~65) winsize 62
1415 11:08:29.836969 [CA 3] Center 33 (3~64) winsize 62
1416 11:08:29.840256 [CA 4] Center 34 (4~65) winsize 62
1417 11:08:29.843770 [CA 5] Center 33 (3~64) winsize 62
1418 11:08:29.843851
1419 11:08:29.847650 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1420 11:08:29.847732
1421 11:08:29.851348 [CATrainingPosCal] consider 2 rank data
1422 11:08:29.855419 u2DelayCellTimex100 = 270/100 ps
1423 11:08:29.858975 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1424 11:08:29.862849 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1425 11:08:29.862932 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1426 11:08:29.869640 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1427 11:08:29.873788 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1428 11:08:29.876062 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1429 11:08:29.876143
1430 11:08:29.879342 CA PerBit enable=1, Macro0, CA PI delay=33
1431 11:08:29.879427
1432 11:08:29.882904 [CBTSetCACLKResult] CA Dly = 33
1433 11:08:29.882984 CS Dly: 5 (0~37)
1434 11:08:29.883049
1435 11:08:29.886752 ----->DramcWriteLeveling(PI) begin...
1436 11:08:29.886836 ==
1437 11:08:29.889401 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 11:08:29.896531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 11:08:29.896614 ==
1440 11:08:29.899953 Write leveling (Byte 0): 28 => 28
1441 11:08:29.900034 Write leveling (Byte 1): 31 => 31
1442 11:08:29.903125 DramcWriteLeveling(PI) end<-----
1443 11:08:29.903206
1444 11:08:29.903271 ==
1445 11:08:29.906293 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 11:08:29.913082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 11:08:29.913165 ==
1448 11:08:29.916329 [Gating] SW mode calibration
1449 11:08:29.923355 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1450 11:08:29.926236 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1451 11:08:29.933477 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 11:08:29.936476 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 11:08:29.939744 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:08:29.943440 0 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1455 11:08:29.949846 0 6 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1456 11:08:29.953390 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:08:29.956340 0 6 24 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1458 11:08:29.963535 0 6 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1459 11:08:29.966812 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:08:29.969967 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:08:29.976480 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1462 11:08:29.979819 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1463 11:08:29.983052 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1464 11:08:29.990665 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1465 11:08:29.993535 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:08:29.996769 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1467 11:08:30.003530 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1468 11:08:30.006599 0 8 4 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 1)
1469 11:08:30.010564 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1470 11:08:30.016493 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 11:08:30.020366 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:08:30.023564 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:08:30.026978 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:08:30.033495 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:08:30.036596 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:08:30.039985 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:08:30.046978 0 9 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
1478 11:08:30.050078 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1479 11:08:30.053552 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 11:08:30.060090 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 11:08:30.063898 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1482 11:08:30.066936 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 11:08:30.073810 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 11:08:30.077315 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 11:08:30.080050 0 10 8 | B1->B0 | 2d2d 2f2f | 1 0 | (1 0) (0 1)
1486 11:08:30.087634 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 11:08:30.090740 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 11:08:30.093494 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 11:08:30.096826 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 11:08:30.103734 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 11:08:30.107930 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 11:08:30.111131 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 11:08:30.117846 0 11 8 | B1->B0 | 3030 3131 | 1 0 | (0 0) (1 1)
1494 11:08:30.120531 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 11:08:30.124487 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 11:08:30.130762 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 11:08:30.134197 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 11:08:30.137217 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 11:08:30.144098 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 11:08:30.147962 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 11:08:30.150913 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1502 11:08:30.154593 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:08:30.160727 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:08:30.164095 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:08:30.167410 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:08:30.174213 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:08:30.177280 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:08:30.181627 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:08:30.187736 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:08:30.190847 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:08:30.194210 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:08:30.201095 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:08:30.204471 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:08:30.207542 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:08:30.214149 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 11:08:30.217560 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 11:08:30.221072 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 11:08:30.225129 Total UI for P1: 0, mck2ui 16
1519 11:08:30.227502 best dqsien dly found for B0: ( 0, 14, 6)
1520 11:08:30.231282 Total UI for P1: 0, mck2ui 16
1521 11:08:30.234321 best dqsien dly found for B1: ( 0, 14, 6)
1522 11:08:30.238177 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1523 11:08:30.241278 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1524 11:08:30.241363
1525 11:08:30.244447 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1526 11:08:30.247807 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1527 11:08:30.251154 [Gating] SW calibration Done
1528 11:08:30.251239 ==
1529 11:08:30.254724 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 11:08:30.257731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 11:08:30.261442 ==
1532 11:08:30.261526 RX Vref Scan: 0
1533 11:08:30.261613
1534 11:08:30.264669 RX Vref 0 -> 0, step: 1
1535 11:08:30.264753
1536 11:08:30.267831 RX Delay -130 -> 252, step: 16
1537 11:08:30.271465 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1538 11:08:30.274873 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1539 11:08:30.278084 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1540 11:08:30.281426 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1541 11:08:30.284771 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1542 11:08:30.291978 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1543 11:08:30.295044 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1544 11:08:30.298640 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1545 11:08:30.301834 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1546 11:08:30.305327 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1547 11:08:30.311818 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1548 11:08:30.315144 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1549 11:08:30.318908 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1550 11:08:30.321623 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1551 11:08:30.325705 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1552 11:08:30.331869 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1553 11:08:30.331954 ==
1554 11:08:30.335510 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 11:08:30.338786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 11:08:30.338871 ==
1557 11:08:30.338957 DQS Delay:
1558 11:08:30.342625 DQS0 = 0, DQS1 = 0
1559 11:08:30.342709 DQM Delay:
1560 11:08:30.345609 DQM0 = 84, DQM1 = 77
1561 11:08:30.345693 DQ Delay:
1562 11:08:30.348617 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1563 11:08:30.352319 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1564 11:08:30.355594 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1565 11:08:30.358835 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1566 11:08:30.358919
1567 11:08:30.359018
1568 11:08:30.359100 ==
1569 11:08:30.362305 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 11:08:30.365651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 11:08:30.365736 ==
1572 11:08:30.365822
1573 11:08:30.365902
1574 11:08:30.368652 TX Vref Scan disable
1575 11:08:30.372167 == TX Byte 0 ==
1576 11:08:30.375640 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1577 11:08:30.378933 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1578 11:08:30.382271 == TX Byte 1 ==
1579 11:08:30.385734 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1580 11:08:30.389120 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1581 11:08:30.389203 ==
1582 11:08:30.392505 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 11:08:30.396186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 11:08:30.396267 ==
1585 11:08:30.410160 TX Vref=22, minBit 5, minWin=27, winSum=442
1586 11:08:30.413247 TX Vref=24, minBit 0, minWin=27, winSum=444
1587 11:08:30.417202 TX Vref=26, minBit 8, minWin=27, winSum=448
1588 11:08:30.421166 TX Vref=28, minBit 0, minWin=27, winSum=452
1589 11:08:30.424061 TX Vref=30, minBit 0, minWin=28, winSum=455
1590 11:08:30.427595 TX Vref=32, minBit 1, minWin=28, winSum=457
1591 11:08:30.434179 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 32
1592 11:08:30.434275
1593 11:08:30.437787 Final TX Range 1 Vref 32
1594 11:08:30.437869
1595 11:08:30.437934 ==
1596 11:08:30.441093 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 11:08:30.445003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 11:08:30.445086 ==
1599 11:08:30.445151
1600 11:08:30.445211
1601 11:08:30.448058 TX Vref Scan disable
1602 11:08:30.451281 == TX Byte 0 ==
1603 11:08:30.454382 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1604 11:08:30.458260 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1605 11:08:30.461452 == TX Byte 1 ==
1606 11:08:30.464657 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1607 11:08:30.467957 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1608 11:08:30.468040
1609 11:08:30.468142 [DATLAT]
1610 11:08:30.471376 Freq=800, CH1 RK0
1611 11:08:30.471458
1612 11:08:30.474160 DATLAT Default: 0xa
1613 11:08:30.474243 0, 0xFFFF, sum = 0
1614 11:08:30.478074 1, 0xFFFF, sum = 0
1615 11:08:30.478157 2, 0xFFFF, sum = 0
1616 11:08:30.480982 3, 0xFFFF, sum = 0
1617 11:08:30.481065 4, 0xFFFF, sum = 0
1618 11:08:30.484395 5, 0xFFFF, sum = 0
1619 11:08:30.484477 6, 0xFFFF, sum = 0
1620 11:08:30.487993 7, 0xFFFF, sum = 0
1621 11:08:30.488075 8, 0xFFFF, sum = 0
1622 11:08:30.491211 9, 0x0, sum = 1
1623 11:08:30.491294 10, 0x0, sum = 2
1624 11:08:30.494515 11, 0x0, sum = 3
1625 11:08:30.494598 12, 0x0, sum = 4
1626 11:08:30.494664 best_step = 10
1627 11:08:30.494724
1628 11:08:30.498183 ==
1629 11:08:30.501346 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 11:08:30.504331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 11:08:30.504414 ==
1632 11:08:30.504479 RX Vref Scan: 1
1633 11:08:30.504540
1634 11:08:30.508145 Set Vref Range= 32 -> 127
1635 11:08:30.508227
1636 11:08:30.511044 RX Vref 32 -> 127, step: 1
1637 11:08:30.511126
1638 11:08:30.514640 RX Delay -95 -> 252, step: 8
1639 11:08:30.514722
1640 11:08:30.517970 Set Vref, RX VrefLevel [Byte0]: 32
1641 11:08:30.521177 [Byte1]: 32
1642 11:08:30.521258
1643 11:08:30.524640 Set Vref, RX VrefLevel [Byte0]: 33
1644 11:08:30.527886 [Byte1]: 33
1645 11:08:30.527968
1646 11:08:30.531259 Set Vref, RX VrefLevel [Byte0]: 34
1647 11:08:30.534500 [Byte1]: 34
1648 11:08:30.537757
1649 11:08:30.537838 Set Vref, RX VrefLevel [Byte0]: 35
1650 11:08:30.541103 [Byte1]: 35
1651 11:08:30.545875
1652 11:08:30.545956 Set Vref, RX VrefLevel [Byte0]: 36
1653 11:08:30.548961 [Byte1]: 36
1654 11:08:30.553193
1655 11:08:30.553275 Set Vref, RX VrefLevel [Byte0]: 37
1656 11:08:30.556836 [Byte1]: 37
1657 11:08:30.560977
1658 11:08:30.561059 Set Vref, RX VrefLevel [Byte0]: 38
1659 11:08:30.563898 [Byte1]: 38
1660 11:08:30.568712
1661 11:08:30.568793 Set Vref, RX VrefLevel [Byte0]: 39
1662 11:08:30.571922 [Byte1]: 39
1663 11:08:30.575848
1664 11:08:30.575930 Set Vref, RX VrefLevel [Byte0]: 40
1665 11:08:30.579158 [Byte1]: 40
1666 11:08:30.583548
1667 11:08:30.583630 Set Vref, RX VrefLevel [Byte0]: 41
1668 11:08:30.587332 [Byte1]: 41
1669 11:08:30.591279
1670 11:08:30.591360 Set Vref, RX VrefLevel [Byte0]: 42
1671 11:08:30.594294 [Byte1]: 42
1672 11:08:30.598657
1673 11:08:30.598738 Set Vref, RX VrefLevel [Byte0]: 43
1674 11:08:30.602041 [Byte1]: 43
1675 11:08:30.606477
1676 11:08:30.606578 Set Vref, RX VrefLevel [Byte0]: 44
1677 11:08:30.609916 [Byte1]: 44
1678 11:08:30.613759
1679 11:08:30.613841 Set Vref, RX VrefLevel [Byte0]: 45
1680 11:08:30.617283 [Byte1]: 45
1681 11:08:30.621532
1682 11:08:30.621614 Set Vref, RX VrefLevel [Byte0]: 46
1683 11:08:30.624892 [Byte1]: 46
1684 11:08:30.629547
1685 11:08:30.629628 Set Vref, RX VrefLevel [Byte0]: 47
1686 11:08:30.632636 [Byte1]: 47
1687 11:08:30.636796
1688 11:08:30.636878 Set Vref, RX VrefLevel [Byte0]: 48
1689 11:08:30.640566 [Byte1]: 48
1690 11:08:30.645143
1691 11:08:30.645225 Set Vref, RX VrefLevel [Byte0]: 49
1692 11:08:30.648177 [Byte1]: 49
1693 11:08:30.652275
1694 11:08:30.652356 Set Vref, RX VrefLevel [Byte0]: 50
1695 11:08:30.655475 [Byte1]: 50
1696 11:08:30.659767
1697 11:08:30.659848 Set Vref, RX VrefLevel [Byte0]: 51
1698 11:08:30.662999 [Byte1]: 51
1699 11:08:30.667375
1700 11:08:30.667522 Set Vref, RX VrefLevel [Byte0]: 52
1701 11:08:30.670177 [Byte1]: 52
1702 11:08:30.674433
1703 11:08:30.674528 Set Vref, RX VrefLevel [Byte0]: 53
1704 11:08:30.677826 [Byte1]: 53
1705 11:08:30.682393
1706 11:08:30.682496 Set Vref, RX VrefLevel [Byte0]: 54
1707 11:08:30.685521 [Byte1]: 54
1708 11:08:30.690033
1709 11:08:30.690114 Set Vref, RX VrefLevel [Byte0]: 55
1710 11:08:30.693154 [Byte1]: 55
1711 11:08:30.697245
1712 11:08:30.697326 Set Vref, RX VrefLevel [Byte0]: 56
1713 11:08:30.700988 [Byte1]: 56
1714 11:08:30.705420
1715 11:08:30.705502 Set Vref, RX VrefLevel [Byte0]: 57
1716 11:08:30.708437 [Byte1]: 57
1717 11:08:30.712876
1718 11:08:30.712957 Set Vref, RX VrefLevel [Byte0]: 58
1719 11:08:30.715863 [Byte1]: 58
1720 11:08:30.720428
1721 11:08:30.720510 Set Vref, RX VrefLevel [Byte0]: 59
1722 11:08:30.723944 [Byte1]: 59
1723 11:08:30.727548
1724 11:08:30.727629 Set Vref, RX VrefLevel [Byte0]: 60
1725 11:08:30.731384 [Byte1]: 60
1726 11:08:30.735495
1727 11:08:30.735577 Set Vref, RX VrefLevel [Byte0]: 61
1728 11:08:30.739012 [Byte1]: 61
1729 11:08:30.743369
1730 11:08:30.743450 Set Vref, RX VrefLevel [Byte0]: 62
1731 11:08:30.746928 [Byte1]: 62
1732 11:08:30.750952
1733 11:08:30.751033 Set Vref, RX VrefLevel [Byte0]: 63
1734 11:08:30.753719 [Byte1]: 63
1735 11:08:30.758180
1736 11:08:30.758261 Set Vref, RX VrefLevel [Byte0]: 64
1737 11:08:30.761672 [Byte1]: 64
1738 11:08:30.766632
1739 11:08:30.766713 Set Vref, RX VrefLevel [Byte0]: 65
1740 11:08:30.769156 [Byte1]: 65
1741 11:08:30.773211
1742 11:08:30.773292 Set Vref, RX VrefLevel [Byte0]: 66
1743 11:08:30.776750 [Byte1]: 66
1744 11:08:30.781075
1745 11:08:30.781156 Set Vref, RX VrefLevel [Byte0]: 67
1746 11:08:30.784284 [Byte1]: 67
1747 11:08:30.788500
1748 11:08:30.788582 Set Vref, RX VrefLevel [Byte0]: 68
1749 11:08:30.791738 [Byte1]: 68
1750 11:08:30.796312
1751 11:08:30.796393 Set Vref, RX VrefLevel [Byte0]: 69
1752 11:08:30.799513 [Byte1]: 69
1753 11:08:30.803671
1754 11:08:30.803751 Set Vref, RX VrefLevel [Byte0]: 70
1755 11:08:30.807089 [Byte1]: 70
1756 11:08:30.812042
1757 11:08:30.812122 Set Vref, RX VrefLevel [Byte0]: 71
1758 11:08:30.814776 [Byte1]: 71
1759 11:08:30.818835
1760 11:08:30.818916 Set Vref, RX VrefLevel [Byte0]: 72
1761 11:08:30.822346 [Byte1]: 72
1762 11:08:30.826623
1763 11:08:30.826703 Set Vref, RX VrefLevel [Byte0]: 73
1764 11:08:30.830020 [Byte1]: 73
1765 11:08:30.834646
1766 11:08:30.834727 Set Vref, RX VrefLevel [Byte0]: 74
1767 11:08:30.838024 [Byte1]: 74
1768 11:08:30.841809
1769 11:08:30.841891 Set Vref, RX VrefLevel [Byte0]: 75
1770 11:08:30.844988 [Byte1]: 75
1771 11:08:30.849086
1772 11:08:30.849167 Set Vref, RX VrefLevel [Byte0]: 76
1773 11:08:30.852632 [Byte1]: 76
1774 11:08:30.857126
1775 11:08:30.857207 Set Vref, RX VrefLevel [Byte0]: 77
1776 11:08:30.860282 [Byte1]: 77
1777 11:08:30.864733
1778 11:08:30.864815 Set Vref, RX VrefLevel [Byte0]: 78
1779 11:08:30.868243 [Byte1]: 78
1780 11:08:30.872755
1781 11:08:30.872955 Final RX Vref Byte 0 = 62 to rank0
1782 11:08:30.875485 Final RX Vref Byte 1 = 58 to rank0
1783 11:08:30.879189 Final RX Vref Byte 0 = 62 to rank1
1784 11:08:30.882278 Final RX Vref Byte 1 = 58 to rank1==
1785 11:08:30.885547 Dram Type= 6, Freq= 0, CH_1, rank 0
1786 11:08:30.892251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1787 11:08:30.892375 ==
1788 11:08:30.892491 DQS Delay:
1789 11:08:30.892600 DQS0 = 0, DQS1 = 0
1790 11:08:30.895476 DQM Delay:
1791 11:08:30.895597 DQM0 = 84, DQM1 = 74
1792 11:08:30.898949 DQ Delay:
1793 11:08:30.899070 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =84
1794 11:08:30.902275 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1795 11:08:30.905502 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1796 11:08:30.908885 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =80
1797 11:08:30.909007
1798 11:08:30.912128
1799 11:08:30.918890 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c01, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1800 11:08:30.922328 CH1 RK0: MR19=606, MR18=2C01
1801 11:08:30.928836 CH1_RK0: MR19=0x606, MR18=0x2C01, DQSOSC=398, MR23=63, INC=93, DEC=62
1802 11:08:30.928962
1803 11:08:30.932372 ----->DramcWriteLeveling(PI) begin...
1804 11:08:30.932495 ==
1805 11:08:30.935873 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 11:08:30.938972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 11:08:30.939096 ==
1808 11:08:30.942279 Write leveling (Byte 0): 26 => 26
1809 11:08:30.945589 Write leveling (Byte 1): 26 => 26
1810 11:08:30.949015 DramcWriteLeveling(PI) end<-----
1811 11:08:30.949136
1812 11:08:30.949248 ==
1813 11:08:30.952417 Dram Type= 6, Freq= 0, CH_1, rank 1
1814 11:08:30.956745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1815 11:08:30.956865 ==
1816 11:08:30.959062 [Gating] SW mode calibration
1817 11:08:30.966077 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1818 11:08:30.972647 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1819 11:08:30.976692 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1820 11:08:30.979267 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1821 11:08:30.982702 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1822 11:08:30.989055 0 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1823 11:08:30.992620 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:08:30.996554 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:08:31.002490 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:08:31.006359 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:08:31.009353 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:08:31.016007 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 11:08:31.019783 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1830 11:08:31.022733 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 11:08:31.029559 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:08:31.032808 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:08:31.035906 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1834 11:08:31.043026 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 11:08:31.046317 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1836 11:08:31.049687 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1837 11:08:31.056389 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 11:08:31.060358 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 11:08:31.063015 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 11:08:31.066119 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 11:08:31.073187 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 11:08:31.076263 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 11:08:31.079688 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 11:08:31.087025 0 9 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1845 11:08:31.090033 0 9 8 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
1846 11:08:31.093776 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1847 11:08:31.099906 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1848 11:08:31.103500 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 11:08:31.106499 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 11:08:31.113192 0 9 28 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1851 11:08:31.116692 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 11:08:31.120231 0 10 4 | B1->B0 | 2f2f 2d2d | 1 0 | (1 0) (1 0)
1853 11:08:31.123172 0 10 8 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
1854 11:08:31.129989 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 11:08:31.133012 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 11:08:31.136626 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1857 11:08:31.143141 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 11:08:31.146771 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 11:08:31.150018 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1860 11:08:31.156760 0 11 4 | B1->B0 | 2929 3b3b | 0 0 | (0 0) (0 0)
1861 11:08:31.160090 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1862 11:08:31.163461 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 11:08:31.170410 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 11:08:31.173283 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 11:08:31.177057 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 11:08:31.183668 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 11:08:31.187310 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 11:08:31.190294 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1869 11:08:31.197256 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 11:08:31.200350 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 11:08:31.203622 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 11:08:31.207071 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 11:08:31.213985 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 11:08:31.216999 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 11:08:31.220123 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 11:08:31.227360 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 11:08:31.230508 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 11:08:31.234199 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 11:08:31.240649 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 11:08:31.244149 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 11:08:31.247015 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 11:08:31.254061 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 11:08:31.257382 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 11:08:31.260892 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1885 11:08:31.263993 Total UI for P1: 0, mck2ui 16
1886 11:08:31.267335 best dqsien dly found for B0: ( 0, 14, 2)
1887 11:08:31.270749 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 11:08:31.274156 Total UI for P1: 0, mck2ui 16
1889 11:08:31.277313 best dqsien dly found for B1: ( 0, 14, 4)
1890 11:08:31.280419 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1891 11:08:31.284193 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1892 11:08:31.287429
1893 11:08:31.290837 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1894 11:08:31.294228 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1895 11:08:31.294310 [Gating] SW calibration Done
1896 11:08:31.298102 ==
1897 11:08:31.301217 Dram Type= 6, Freq= 0, CH_1, rank 1
1898 11:08:31.304226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1899 11:08:31.304309 ==
1900 11:08:31.304374 RX Vref Scan: 0
1901 11:08:31.304435
1902 11:08:31.308011 RX Vref 0 -> 0, step: 1
1903 11:08:31.308092
1904 11:08:31.311136 RX Delay -130 -> 252, step: 16
1905 11:08:31.314033 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1906 11:08:31.317415 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1907 11:08:31.321110 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1908 11:08:31.328000 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1909 11:08:31.331156 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1910 11:08:31.334874 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1911 11:08:31.338082 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1912 11:08:31.341127 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1913 11:08:31.347909 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1914 11:08:31.351147 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1915 11:08:31.354288 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1916 11:08:31.357626 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1917 11:08:31.361164 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1918 11:08:31.367928 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1919 11:08:31.371157 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1920 11:08:31.374617 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1921 11:08:31.374698 ==
1922 11:08:31.377774 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 11:08:31.381490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 11:08:31.381575 ==
1925 11:08:31.384445 DQS Delay:
1926 11:08:31.384526 DQS0 = 0, DQS1 = 0
1927 11:08:31.384591 DQM Delay:
1928 11:08:31.388263 DQM0 = 83, DQM1 = 78
1929 11:08:31.388345 DQ Delay:
1930 11:08:31.391470 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1931 11:08:31.394669 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1932 11:08:31.397822 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1933 11:08:31.401236 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1934 11:08:31.401317
1935 11:08:31.401381
1936 11:08:31.401441 ==
1937 11:08:31.404662 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 11:08:31.411170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 11:08:31.411252 ==
1940 11:08:31.411317
1941 11:08:31.411377
1942 11:08:31.411435 TX Vref Scan disable
1943 11:08:31.415158 == TX Byte 0 ==
1944 11:08:31.418805 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1945 11:08:31.425066 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1946 11:08:31.425147 == TX Byte 1 ==
1947 11:08:31.428851 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1948 11:08:31.431567 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1949 11:08:31.434711 ==
1950 11:08:31.438210 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 11:08:31.441630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 11:08:31.441712 ==
1953 11:08:31.454071 TX Vref=22, minBit 8, minWin=27, winSum=442
1954 11:08:31.457373 TX Vref=24, minBit 5, minWin=27, winSum=443
1955 11:08:31.460588 TX Vref=26, minBit 9, minWin=27, winSum=443
1956 11:08:31.463620 TX Vref=28, minBit 9, minWin=27, winSum=447
1957 11:08:31.467163 TX Vref=30, minBit 0, minWin=28, winSum=450
1958 11:08:31.473575 TX Vref=32, minBit 0, minWin=28, winSum=451
1959 11:08:31.477657 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
1960 11:08:31.477738
1961 11:08:31.480608 Final TX Range 1 Vref 32
1962 11:08:31.480688
1963 11:08:31.480752 ==
1964 11:08:31.483964 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 11:08:31.487427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 11:08:31.487508 ==
1967 11:08:31.487572
1968 11:08:31.490276
1969 11:08:31.490358 TX Vref Scan disable
1970 11:08:31.493563 == TX Byte 0 ==
1971 11:08:31.496975 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1972 11:08:31.500508 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1973 11:08:31.503913 == TX Byte 1 ==
1974 11:08:31.507521 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1975 11:08:31.513991 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1976 11:08:31.514076
1977 11:08:31.514176 [DATLAT]
1978 11:08:31.514237 Freq=800, CH1 RK1
1979 11:08:31.514295
1980 11:08:31.517420 DATLAT Default: 0xa
1981 11:08:31.517502 0, 0xFFFF, sum = 0
1982 11:08:31.520321 1, 0xFFFF, sum = 0
1983 11:08:31.520404 2, 0xFFFF, sum = 0
1984 11:08:31.524102 3, 0xFFFF, sum = 0
1985 11:08:31.524186 4, 0xFFFF, sum = 0
1986 11:08:31.527296 5, 0xFFFF, sum = 0
1987 11:08:31.527386 6, 0xFFFF, sum = 0
1988 11:08:31.531201 7, 0xFFFF, sum = 0
1989 11:08:31.531283 8, 0xFFFF, sum = 0
1990 11:08:31.534165 9, 0x0, sum = 1
1991 11:08:31.534247 10, 0x0, sum = 2
1992 11:08:31.537918 11, 0x0, sum = 3
1993 11:08:31.538000 12, 0x0, sum = 4
1994 11:08:31.540738 best_step = 10
1995 11:08:31.540819
1996 11:08:31.540883 ==
1997 11:08:31.544604 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 11:08:31.547726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 11:08:31.547807 ==
2000 11:08:31.550709 RX Vref Scan: 0
2001 11:08:31.550790
2002 11:08:31.550853 RX Vref 0 -> 0, step: 1
2003 11:08:31.550913
2004 11:08:31.554258 RX Delay -95 -> 252, step: 8
2005 11:08:31.561182 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2006 11:08:31.564530 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2007 11:08:31.567792 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2008 11:08:31.571501 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2009 11:08:31.574362 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2010 11:08:31.577737 iDelay=209, Bit 5, Center 92 (-15 ~ 200) 216
2011 11:08:31.584494 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2012 11:08:31.587756 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2013 11:08:31.591225 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2014 11:08:31.594857 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2015 11:08:31.597942 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2016 11:08:31.605008 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2017 11:08:31.607610 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2018 11:08:31.611466 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2019 11:08:31.614358 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2020 11:08:31.617931 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2021 11:08:31.621073 ==
2022 11:08:31.621155 Dram Type= 6, Freq= 0, CH_1, rank 1
2023 11:08:31.628326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2024 11:08:31.628408 ==
2025 11:08:31.628474 DQS Delay:
2026 11:08:31.631674 DQS0 = 0, DQS1 = 0
2027 11:08:31.631755 DQM Delay:
2028 11:08:31.634466 DQM0 = 80, DQM1 = 75
2029 11:08:31.634548 DQ Delay:
2030 11:08:31.638268 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2031 11:08:31.641261 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2032 11:08:31.644847 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2033 11:08:31.648371 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2034 11:08:31.648451
2035 11:08:31.648516
2036 11:08:31.655261 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
2037 11:08:31.658595 CH1 RK1: MR19=606, MR18=1B26
2038 11:08:31.665097 CH1_RK1: MR19=0x606, MR18=0x1B26, DQSOSC=400, MR23=63, INC=92, DEC=61
2039 11:08:31.667879 [RxdqsGatingPostProcess] freq 800
2040 11:08:31.672050 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2041 11:08:31.674652 Pre-setting of DQS Precalculation
2042 11:08:31.681387 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2043 11:08:31.688125 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2044 11:08:31.695387 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2045 11:08:31.695468
2046 11:08:31.695533
2047 11:08:31.698639 [Calibration Summary] 1600 Mbps
2048 11:08:31.698720 CH 0, Rank 0
2049 11:08:31.701589 SW Impedance : PASS
2050 11:08:31.705196 DUTY Scan : NO K
2051 11:08:31.705277 ZQ Calibration : PASS
2052 11:08:31.708038 Jitter Meter : NO K
2053 11:08:31.711429 CBT Training : PASS
2054 11:08:31.711510 Write leveling : PASS
2055 11:08:31.715561 RX DQS gating : PASS
2056 11:08:31.715641 RX DQ/DQS(RDDQC) : PASS
2057 11:08:31.718272 TX DQ/DQS : PASS
2058 11:08:31.721783 RX DATLAT : PASS
2059 11:08:31.721863 RX DQ/DQS(Engine): PASS
2060 11:08:31.725606 TX OE : NO K
2061 11:08:31.725686 All Pass.
2062 11:08:31.725750
2063 11:08:31.728559 CH 0, Rank 1
2064 11:08:31.728639 SW Impedance : PASS
2065 11:08:31.732215 DUTY Scan : NO K
2066 11:08:31.734823 ZQ Calibration : PASS
2067 11:08:31.734904 Jitter Meter : NO K
2068 11:08:31.738083 CBT Training : PASS
2069 11:08:31.742070 Write leveling : PASS
2070 11:08:31.742176 RX DQS gating : PASS
2071 11:08:31.745154 RX DQ/DQS(RDDQC) : PASS
2072 11:08:31.748358 TX DQ/DQS : PASS
2073 11:08:31.748465 RX DATLAT : PASS
2074 11:08:31.751725 RX DQ/DQS(Engine): PASS
2075 11:08:31.751805 TX OE : NO K
2076 11:08:31.754967 All Pass.
2077 11:08:31.755046
2078 11:08:31.755110 CH 1, Rank 0
2079 11:08:31.758370 SW Impedance : PASS
2080 11:08:31.761887 DUTY Scan : NO K
2081 11:08:31.761993 ZQ Calibration : PASS
2082 11:08:31.765078 Jitter Meter : NO K
2083 11:08:31.765183 CBT Training : PASS
2084 11:08:31.768451 Write leveling : PASS
2085 11:08:31.772165 RX DQS gating : PASS
2086 11:08:31.772245 RX DQ/DQS(RDDQC) : PASS
2087 11:08:31.775437 TX DQ/DQS : PASS
2088 11:08:31.778751 RX DATLAT : PASS
2089 11:08:31.778833 RX DQ/DQS(Engine): PASS
2090 11:08:31.781663 TX OE : NO K
2091 11:08:31.781743 All Pass.
2092 11:08:31.781807
2093 11:08:31.785149 CH 1, Rank 1
2094 11:08:31.785231 SW Impedance : PASS
2095 11:08:31.788618 DUTY Scan : NO K
2096 11:08:31.791690 ZQ Calibration : PASS
2097 11:08:31.791770 Jitter Meter : NO K
2098 11:08:31.795607 CBT Training : PASS
2099 11:08:31.795686 Write leveling : PASS
2100 11:08:31.798905 RX DQS gating : PASS
2101 11:08:31.801661 RX DQ/DQS(RDDQC) : PASS
2102 11:08:31.801734 TX DQ/DQS : PASS
2103 11:08:31.805271 RX DATLAT : PASS
2104 11:08:31.808623 RX DQ/DQS(Engine): PASS
2105 11:08:31.808720 TX OE : NO K
2106 11:08:31.812152 All Pass.
2107 11:08:31.812232
2108 11:08:31.812296 DramC Write-DBI off
2109 11:08:31.815218 PER_BANK_REFRESH: Hybrid Mode
2110 11:08:31.815295 TX_TRACKING: ON
2111 11:08:31.818713 [GetDramInforAfterCalByMRR] Vendor 6.
2112 11:08:31.825265 [GetDramInforAfterCalByMRR] Revision 606.
2113 11:08:31.828808 [GetDramInforAfterCalByMRR] Revision 2 0.
2114 11:08:31.828880 MR0 0x3b3b
2115 11:08:31.828941 MR8 0x5151
2116 11:08:31.831926 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2117 11:08:31.832022
2118 11:08:31.835235 MR0 0x3b3b
2119 11:08:31.835315 MR8 0x5151
2120 11:08:31.840428 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2121 11:08:31.840500
2122 11:08:31.849054 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2123 11:08:31.851985 [FAST_K] Save calibration result to emmc
2124 11:08:31.855581 [FAST_K] Save calibration result to emmc
2125 11:08:31.858927 dram_init: config_dvfs: 1
2126 11:08:31.862323 dramc_set_vcore_voltage set vcore to 662500
2127 11:08:31.865665 Read voltage for 1200, 2
2128 11:08:31.865767 Vio18 = 0
2129 11:08:31.865863 Vcore = 662500
2130 11:08:31.865950 Vdram = 0
2131 11:08:31.868968 Vddq = 0
2132 11:08:31.869048 Vmddr = 0
2133 11:08:31.875751 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2134 11:08:31.878964 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2135 11:08:31.882364 MEM_TYPE=3, freq_sel=15
2136 11:08:31.885741 sv_algorithm_assistance_LP4_1600
2137 11:08:31.889257 ============ PULL DRAM RESETB DOWN ============
2138 11:08:31.892106 ========== PULL DRAM RESETB DOWN end =========
2139 11:08:31.899254 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2140 11:08:31.902227 ===================================
2141 11:08:31.902307 LPDDR4 DRAM CONFIGURATION
2142 11:08:31.905898 ===================================
2143 11:08:31.909103 EX_ROW_EN[0] = 0x0
2144 11:08:31.909188 EX_ROW_EN[1] = 0x0
2145 11:08:31.912762 LP4Y_EN = 0x0
2146 11:08:31.912842 WORK_FSP = 0x0
2147 11:08:31.915940 WL = 0x4
2148 11:08:31.916038 RL = 0x4
2149 11:08:31.919264 BL = 0x2
2150 11:08:31.922360 RPST = 0x0
2151 11:08:31.922479 RD_PRE = 0x0
2152 11:08:31.926104 WR_PRE = 0x1
2153 11:08:31.926185 WR_PST = 0x0
2154 11:08:31.929001 DBI_WR = 0x0
2155 11:08:31.929081 DBI_RD = 0x0
2156 11:08:31.932611 OTF = 0x1
2157 11:08:31.935774 ===================================
2158 11:08:31.938996 ===================================
2159 11:08:31.939077 ANA top config
2160 11:08:31.942682 ===================================
2161 11:08:31.946084 DLL_ASYNC_EN = 0
2162 11:08:31.946165 ALL_SLAVE_EN = 0
2163 11:08:31.949124 NEW_RANK_MODE = 1
2164 11:08:31.952670 DLL_IDLE_MODE = 1
2165 11:08:31.956183 LP45_APHY_COMB_EN = 1
2166 11:08:31.959477 TX_ODT_DIS = 1
2167 11:08:31.959559 NEW_8X_MODE = 1
2168 11:08:31.962903 ===================================
2169 11:08:31.966343 ===================================
2170 11:08:31.969551 data_rate = 2400
2171 11:08:31.972727 CKR = 1
2172 11:08:31.976285 DQ_P2S_RATIO = 8
2173 11:08:31.979270 ===================================
2174 11:08:31.983175 CA_P2S_RATIO = 8
2175 11:08:31.983260 DQ_CA_OPEN = 0
2176 11:08:31.985970 DQ_SEMI_OPEN = 0
2177 11:08:31.989830 CA_SEMI_OPEN = 0
2178 11:08:31.993092 CA_FULL_RATE = 0
2179 11:08:31.996641 DQ_CKDIV4_EN = 0
2180 11:08:31.999542 CA_CKDIV4_EN = 0
2181 11:08:31.999623 CA_PREDIV_EN = 0
2182 11:08:32.002765 PH8_DLY = 17
2183 11:08:32.007117 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2184 11:08:32.009662 DQ_AAMCK_DIV = 4
2185 11:08:32.012837 CA_AAMCK_DIV = 4
2186 11:08:32.016316 CA_ADMCK_DIV = 4
2187 11:08:32.016397 DQ_TRACK_CA_EN = 0
2188 11:08:32.019906 CA_PICK = 1200
2189 11:08:32.023238 CA_MCKIO = 1200
2190 11:08:32.026293 MCKIO_SEMI = 0
2191 11:08:32.029441 PLL_FREQ = 2366
2192 11:08:32.032859 DQ_UI_PI_RATIO = 32
2193 11:08:32.036563 CA_UI_PI_RATIO = 0
2194 11:08:32.040068 ===================================
2195 11:08:32.043340 ===================================
2196 11:08:32.043423 memory_type:LPDDR4
2197 11:08:32.046362 GP_NUM : 10
2198 11:08:32.046470 SRAM_EN : 1
2199 11:08:32.049686 MD32_EN : 0
2200 11:08:32.053168 ===================================
2201 11:08:32.056444 [ANA_INIT] >>>>>>>>>>>>>>
2202 11:08:32.059683 <<<<<< [CONFIGURE PHASE]: ANA_TX
2203 11:08:32.063144 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2204 11:08:32.066251 ===================================
2205 11:08:32.066361 data_rate = 2400,PCW = 0X5b00
2206 11:08:32.069689 ===================================
2207 11:08:32.077011 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2208 11:08:32.079807 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2209 11:08:32.086856 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2210 11:08:32.089550 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2211 11:08:32.093286 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2212 11:08:32.096336 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2213 11:08:32.099519 [ANA_INIT] flow start
2214 11:08:32.103137 [ANA_INIT] PLL >>>>>>>>
2215 11:08:32.103218 [ANA_INIT] PLL <<<<<<<<
2216 11:08:32.106602 [ANA_INIT] MIDPI >>>>>>>>
2217 11:08:32.110175 [ANA_INIT] MIDPI <<<<<<<<
2218 11:08:32.110256 [ANA_INIT] DLL >>>>>>>>
2219 11:08:32.113422 [ANA_INIT] DLL <<<<<<<<
2220 11:08:32.116549 [ANA_INIT] flow end
2221 11:08:32.119893 ============ LP4 DIFF to SE enter ============
2222 11:08:32.123085 ============ LP4 DIFF to SE exit ============
2223 11:08:32.126656 [ANA_INIT] <<<<<<<<<<<<<
2224 11:08:32.129738 [Flow] Enable top DCM control >>>>>
2225 11:08:32.133786 [Flow] Enable top DCM control <<<<<
2226 11:08:32.136719 Enable DLL master slave shuffle
2227 11:08:32.140151 ==============================================================
2228 11:08:32.143456 Gating Mode config
2229 11:08:32.146595 ==============================================================
2230 11:08:32.149975 Config description:
2231 11:08:32.160249 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2232 11:08:32.166669 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2233 11:08:32.170080 SELPH_MODE 0: By rank 1: By Phase
2234 11:08:32.176982 ==============================================================
2235 11:08:32.180183 GAT_TRACK_EN = 1
2236 11:08:32.184665 RX_GATING_MODE = 2
2237 11:08:32.187624 RX_GATING_TRACK_MODE = 2
2238 11:08:32.187711 SELPH_MODE = 1
2239 11:08:32.190379 PICG_EARLY_EN = 1
2240 11:08:32.193425 VALID_LAT_VALUE = 1
2241 11:08:32.200274 ==============================================================
2242 11:08:32.203842 Enter into Gating configuration >>>>
2243 11:08:32.207324 Exit from Gating configuration <<<<
2244 11:08:32.210317 Enter into DVFS_PRE_config >>>>>
2245 11:08:32.220753 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2246 11:08:32.223883 Exit from DVFS_PRE_config <<<<<
2247 11:08:32.227390 Enter into PICG configuration >>>>
2248 11:08:32.230793 Exit from PICG configuration <<<<
2249 11:08:32.234053 [RX_INPUT] configuration >>>>>
2250 11:08:32.237071 [RX_INPUT] configuration <<<<<
2251 11:08:32.240429 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2252 11:08:32.247716 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2253 11:08:32.254275 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2254 11:08:32.257188 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2255 11:08:32.263960 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 11:08:32.270965 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 11:08:32.274293 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2258 11:08:32.277566 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2259 11:08:32.284118 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2260 11:08:32.287653 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2261 11:08:32.291296 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2262 11:08:32.297517 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2263 11:08:32.300787 ===================================
2264 11:08:32.300868 LPDDR4 DRAM CONFIGURATION
2265 11:08:32.304032 ===================================
2266 11:08:32.307796 EX_ROW_EN[0] = 0x0
2267 11:08:32.307881 EX_ROW_EN[1] = 0x0
2268 11:08:32.310858 LP4Y_EN = 0x0
2269 11:08:32.310937 WORK_FSP = 0x0
2270 11:08:32.314677 WL = 0x4
2271 11:08:32.314757 RL = 0x4
2272 11:08:32.317717 BL = 0x2
2273 11:08:32.317796 RPST = 0x0
2274 11:08:32.321101 RD_PRE = 0x0
2275 11:08:32.324218 WR_PRE = 0x1
2276 11:08:32.324298 WR_PST = 0x0
2277 11:08:32.328149 DBI_WR = 0x0
2278 11:08:32.328233 DBI_RD = 0x0
2279 11:08:32.331420 OTF = 0x1
2280 11:08:32.334347 ===================================
2281 11:08:32.337884 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2282 11:08:32.341155 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2283 11:08:32.344196 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2284 11:08:32.347628 ===================================
2285 11:08:32.351202 LPDDR4 DRAM CONFIGURATION
2286 11:08:32.354624 ===================================
2287 11:08:32.357586 EX_ROW_EN[0] = 0x10
2288 11:08:32.357667 EX_ROW_EN[1] = 0x0
2289 11:08:32.361722 LP4Y_EN = 0x0
2290 11:08:32.361803 WORK_FSP = 0x0
2291 11:08:32.364729 WL = 0x4
2292 11:08:32.364810 RL = 0x4
2293 11:08:32.367977 BL = 0x2
2294 11:08:32.368059 RPST = 0x0
2295 11:08:32.371205 RD_PRE = 0x0
2296 11:08:32.371315 WR_PRE = 0x1
2297 11:08:32.374783 WR_PST = 0x0
2298 11:08:32.374865 DBI_WR = 0x0
2299 11:08:32.377835 DBI_RD = 0x0
2300 11:08:32.377963 OTF = 0x1
2301 11:08:32.380997 ===================================
2302 11:08:32.387740 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2303 11:08:32.387846 ==
2304 11:08:32.391624 Dram Type= 6, Freq= 0, CH_0, rank 0
2305 11:08:32.394415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2306 11:08:32.398006 ==
2307 11:08:32.398086 [Duty_Offset_Calibration]
2308 11:08:32.401357 B0:2 B1:-1 CA:1
2309 11:08:32.401438
2310 11:08:32.404399 [DutyScan_Calibration_Flow] k_type=0
2311 11:08:32.412791
2312 11:08:32.412872 ==CLK 0==
2313 11:08:32.416316 Final CLK duty delay cell = -4
2314 11:08:32.419268 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2315 11:08:32.422467 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2316 11:08:32.425576 [-4] AVG Duty = 4953%(X100)
2317 11:08:32.425656
2318 11:08:32.429239 CH0 CLK Duty spec in!! Max-Min= 156%
2319 11:08:32.432566 [DutyScan_Calibration_Flow] ====Done====
2320 11:08:32.432645
2321 11:08:32.436106 [DutyScan_Calibration_Flow] k_type=1
2322 11:08:32.451292
2323 11:08:32.451371 ==DQS 0 ==
2324 11:08:32.454196 Final DQS duty delay cell = 0
2325 11:08:32.457817 [0] MAX Duty = 5125%(X100), DQS PI = 46
2326 11:08:32.461223 [0] MIN Duty = 5000%(X100), DQS PI = 12
2327 11:08:32.461303 [0] AVG Duty = 5062%(X100)
2328 11:08:32.464991
2329 11:08:32.465101 ==DQS 1 ==
2330 11:08:32.467655 Final DQS duty delay cell = -4
2331 11:08:32.471422 [-4] MAX Duty = 5124%(X100), DQS PI = 18
2332 11:08:32.474737 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2333 11:08:32.477839 [-4] AVG Duty = 5062%(X100)
2334 11:08:32.477915
2335 11:08:32.481430 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2336 11:08:32.481537
2337 11:08:32.484632 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2338 11:08:32.487794 [DutyScan_Calibration_Flow] ====Done====
2339 11:08:32.487873
2340 11:08:32.491249 [DutyScan_Calibration_Flow] k_type=3
2341 11:08:32.508087
2342 11:08:32.508170 ==DQM 0 ==
2343 11:08:32.511154 Final DQM duty delay cell = 0
2344 11:08:32.514867 [0] MAX Duty = 5031%(X100), DQS PI = 54
2345 11:08:32.518005 [0] MIN Duty = 4907%(X100), DQS PI = 2
2346 11:08:32.518079 [0] AVG Duty = 4969%(X100)
2347 11:08:32.521360
2348 11:08:32.521439 ==DQM 1 ==
2349 11:08:32.524812 Final DQM duty delay cell = 0
2350 11:08:32.528138 [0] MAX Duty = 5156%(X100), DQS PI = 62
2351 11:08:32.531745 [0] MIN Duty = 5000%(X100), DQS PI = 8
2352 11:08:32.531825 [0] AVG Duty = 5078%(X100)
2353 11:08:32.531888
2354 11:08:32.534654 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2355 11:08:32.538230
2356 11:08:32.541603 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2357 11:08:32.544894 [DutyScan_Calibration_Flow] ====Done====
2358 11:08:32.544973
2359 11:08:32.548096 [DutyScan_Calibration_Flow] k_type=2
2360 11:08:32.563617
2361 11:08:32.563697 ==DQ 0 ==
2362 11:08:32.566830 Final DQ duty delay cell = -4
2363 11:08:32.570107 [-4] MAX Duty = 5093%(X100), DQS PI = 54
2364 11:08:32.573587 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2365 11:08:32.576964 [-4] AVG Duty = 4984%(X100)
2366 11:08:32.577044
2367 11:08:32.577107 ==DQ 1 ==
2368 11:08:32.580604 Final DQ duty delay cell = 0
2369 11:08:32.584320 [0] MAX Duty = 5031%(X100), DQS PI = 18
2370 11:08:32.587168 [0] MIN Duty = 4907%(X100), DQS PI = 46
2371 11:08:32.587289 [0] AVG Duty = 4969%(X100)
2372 11:08:32.590559
2373 11:08:32.593590 CH0 DQ 0 Duty spec in!! Max-Min= 217%
2374 11:08:32.593709
2375 11:08:32.597270 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2376 11:08:32.600667 [DutyScan_Calibration_Flow] ====Done====
2377 11:08:32.600791 ==
2378 11:08:32.603855 Dram Type= 6, Freq= 0, CH_1, rank 0
2379 11:08:32.607081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2380 11:08:32.607200 ==
2381 11:08:32.611043 [Duty_Offset_Calibration]
2382 11:08:32.611162 B0:1 B1:1 CA:2
2383 11:08:32.611269
2384 11:08:32.613997 [DutyScan_Calibration_Flow] k_type=0
2385 11:08:32.623923
2386 11:08:32.624005 ==CLK 0==
2387 11:08:32.628072 Final CLK duty delay cell = 0
2388 11:08:32.630622 [0] MAX Duty = 5125%(X100), DQS PI = 24
2389 11:08:32.634445 [0] MIN Duty = 4938%(X100), DQS PI = 42
2390 11:08:32.634549 [0] AVG Duty = 5031%(X100)
2391 11:08:32.637247
2392 11:08:32.641024 CH1 CLK Duty spec in!! Max-Min= 187%
2393 11:08:32.644001 [DutyScan_Calibration_Flow] ====Done====
2394 11:08:32.644081
2395 11:08:32.647437 [DutyScan_Calibration_Flow] k_type=1
2396 11:08:32.663592
2397 11:08:32.663673 ==DQS 0 ==
2398 11:08:32.667010 Final DQS duty delay cell = 0
2399 11:08:32.670051 [0] MAX Duty = 5062%(X100), DQS PI = 18
2400 11:08:32.673394 [0] MIN Duty = 4844%(X100), DQS PI = 50
2401 11:08:32.673474 [0] AVG Duty = 4953%(X100)
2402 11:08:32.676877
2403 11:08:32.676957 ==DQS 1 ==
2404 11:08:32.679949 Final DQS duty delay cell = 0
2405 11:08:32.683138 [0] MAX Duty = 5062%(X100), DQS PI = 36
2406 11:08:32.686961 [0] MIN Duty = 4907%(X100), DQS PI = 2
2407 11:08:32.687041 [0] AVG Duty = 4984%(X100)
2408 11:08:32.689853
2409 11:08:32.693433 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2410 11:08:32.693512
2411 11:08:32.696798 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2412 11:08:32.700776 [DutyScan_Calibration_Flow] ====Done====
2413 11:08:32.700856
2414 11:08:32.703654 [DutyScan_Calibration_Flow] k_type=3
2415 11:08:32.720066
2416 11:08:32.720145 ==DQM 0 ==
2417 11:08:32.723655 Final DQM duty delay cell = 0
2418 11:08:32.726621 [0] MAX Duty = 5093%(X100), DQS PI = 16
2419 11:08:32.730295 [0] MIN Duty = 4907%(X100), DQS PI = 48
2420 11:08:32.733243 [0] AVG Duty = 5000%(X100)
2421 11:08:32.733348
2422 11:08:32.733440 ==DQM 1 ==
2423 11:08:32.736782 Final DQM duty delay cell = 0
2424 11:08:32.739968 [0] MAX Duty = 5156%(X100), DQS PI = 60
2425 11:08:32.743684 [0] MIN Duty = 4938%(X100), DQS PI = 24
2426 11:08:32.746343 [0] AVG Duty = 5047%(X100)
2427 11:08:32.746475
2428 11:08:32.750246 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2429 11:08:32.750355
2430 11:08:32.753494 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2431 11:08:32.756701 [DutyScan_Calibration_Flow] ====Done====
2432 11:08:32.756786
2433 11:08:32.760788 [DutyScan_Calibration_Flow] k_type=2
2434 11:08:32.776357
2435 11:08:32.776443 ==DQ 0 ==
2436 11:08:32.779554 Final DQ duty delay cell = 0
2437 11:08:32.783929 [0] MAX Duty = 5124%(X100), DQS PI = 18
2438 11:08:32.786806 [0] MIN Duty = 4907%(X100), DQS PI = 50
2439 11:08:32.786886 [0] AVG Duty = 5015%(X100)
2440 11:08:32.786950
2441 11:08:32.790461 ==DQ 1 ==
2442 11:08:32.790590 Final DQ duty delay cell = 0
2443 11:08:32.797221 [0] MAX Duty = 5093%(X100), DQS PI = 10
2444 11:08:32.799981 [0] MIN Duty = 5031%(X100), DQS PI = 2
2445 11:08:32.800108 [0] AVG Duty = 5062%(X100)
2446 11:08:32.800223
2447 11:08:32.803201 CH1 DQ 0 Duty spec in!! Max-Min= 217%
2448 11:08:32.803299
2449 11:08:32.807000 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2450 11:08:32.810259 [DutyScan_Calibration_Flow] ====Done====
2451 11:08:32.815272 nWR fixed to 30
2452 11:08:32.819076 [ModeRegInit_LP4] CH0 RK0
2453 11:08:32.819176 [ModeRegInit_LP4] CH0 RK1
2454 11:08:32.822252 [ModeRegInit_LP4] CH1 RK0
2455 11:08:32.825584 [ModeRegInit_LP4] CH1 RK1
2456 11:08:32.825743 match AC timing 7
2457 11:08:32.832157 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2458 11:08:32.835462 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2459 11:08:32.839301 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2460 11:08:32.845299 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2461 11:08:32.848924 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2462 11:08:32.849024 ==
2463 11:08:32.852192 Dram Type= 6, Freq= 0, CH_0, rank 0
2464 11:08:32.855473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2465 11:08:32.855602 ==
2466 11:08:32.862310 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2467 11:08:32.869191 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2468 11:08:32.876451 [CA 0] Center 40 (10~71) winsize 62
2469 11:08:32.879560 [CA 1] Center 39 (9~70) winsize 62
2470 11:08:32.882933 [CA 2] Center 36 (6~67) winsize 62
2471 11:08:32.886084 [CA 3] Center 36 (5~67) winsize 63
2472 11:08:32.889745 [CA 4] Center 35 (5~65) winsize 61
2473 11:08:32.893017 [CA 5] Center 34 (4~65) winsize 62
2474 11:08:32.893101
2475 11:08:32.897019 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2476 11:08:32.897102
2477 11:08:32.899549 [CATrainingPosCal] consider 1 rank data
2478 11:08:32.903362 u2DelayCellTimex100 = 270/100 ps
2479 11:08:32.906979 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2480 11:08:32.913219 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2481 11:08:32.916348 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2482 11:08:32.919593 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2483 11:08:32.922619 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2484 11:08:32.926280 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2485 11:08:32.926436
2486 11:08:32.929602 CA PerBit enable=1, Macro0, CA PI delay=34
2487 11:08:32.929709
2488 11:08:32.933553 [CBTSetCACLKResult] CA Dly = 34
2489 11:08:32.933651 CS Dly: 7 (0~38)
2490 11:08:32.936747 ==
2491 11:08:32.936923 Dram Type= 6, Freq= 0, CH_0, rank 1
2492 11:08:32.942800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2493 11:08:32.942893 ==
2494 11:08:32.946412 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2495 11:08:32.953050 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2496 11:08:32.962301 [CA 0] Center 40 (10~70) winsize 61
2497 11:08:32.965358 [CA 1] Center 39 (9~70) winsize 62
2498 11:08:32.969131 [CA 2] Center 36 (6~67) winsize 62
2499 11:08:32.972178 [CA 3] Center 35 (5~66) winsize 62
2500 11:08:32.975549 [CA 4] Center 34 (4~65) winsize 62
2501 11:08:32.979027 [CA 5] Center 34 (4~64) winsize 61
2502 11:08:32.979111
2503 11:08:32.982207 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2504 11:08:32.982357
2505 11:08:32.985860 [CATrainingPosCal] consider 2 rank data
2506 11:08:32.988673 u2DelayCellTimex100 = 270/100 ps
2507 11:08:32.992495 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2508 11:08:32.996428 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2509 11:08:33.005351 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2510 11:08:33.005779 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2511 11:08:33.009005 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2512 11:08:33.012400 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2513 11:08:33.012527
2514 11:08:33.015708 CA PerBit enable=1, Macro0, CA PI delay=34
2515 11:08:33.015831
2516 11:08:33.019032 [CBTSetCACLKResult] CA Dly = 34
2517 11:08:33.019152 CS Dly: 8 (0~41)
2518 11:08:33.019264
2519 11:08:33.022010 ----->DramcWriteLeveling(PI) begin...
2520 11:08:33.025788 ==
2521 11:08:33.029171 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 11:08:33.032658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 11:08:33.032801 ==
2524 11:08:33.035493 Write leveling (Byte 0): 32 => 32
2525 11:08:33.039008 Write leveling (Byte 1): 30 => 30
2526 11:08:33.042989 DramcWriteLeveling(PI) end<-----
2527 11:08:33.043110
2528 11:08:33.043222 ==
2529 11:08:33.046040 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 11:08:33.049292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2531 11:08:33.049415 ==
2532 11:08:33.052770 [Gating] SW mode calibration
2533 11:08:33.059417 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2534 11:08:33.062509 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2535 11:08:33.068913 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 11:08:33.072475 0 15 4 | B1->B0 | 2322 3333 | 1 1 | (0 0) (0 0)
2537 11:08:33.075682 0 15 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2538 11:08:33.082713 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 11:08:33.086256 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 11:08:33.088974 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 11:08:33.096071 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 11:08:33.099788 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 11:08:33.102758 1 0 0 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
2544 11:08:33.109961 1 0 4 | B1->B0 | 2929 2424 | 0 0 | (0 0) (1 0)
2545 11:08:33.112532 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 11:08:33.116026 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 11:08:33.119246 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 11:08:33.126080 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 11:08:33.129941 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 11:08:33.132987 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 11:08:33.139685 1 1 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2552 11:08:33.142939 1 1 4 | B1->B0 | 3636 4343 | 0 0 | (0 0) (0 0)
2553 11:08:33.146036 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 11:08:33.153059 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 11:08:33.156309 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 11:08:33.159821 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 11:08:33.166342 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 11:08:33.169693 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 11:08:33.173502 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2560 11:08:33.179934 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2561 11:08:33.183036 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 11:08:33.186734 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 11:08:33.190036 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 11:08:33.196856 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 11:08:33.200049 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 11:08:33.203409 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 11:08:33.209986 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 11:08:33.212954 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 11:08:33.216645 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 11:08:33.223194 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 11:08:33.226752 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 11:08:33.230544 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 11:08:33.236527 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 11:08:33.240160 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 11:08:33.243441 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2576 11:08:33.246868 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2577 11:08:33.250180 Total UI for P1: 0, mck2ui 16
2578 11:08:33.253533 best dqsien dly found for B0: ( 1, 4, 0)
2579 11:08:33.260367 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 11:08:33.264009 Total UI for P1: 0, mck2ui 16
2581 11:08:33.266947 best dqsien dly found for B1: ( 1, 4, 2)
2582 11:08:33.270130 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2583 11:08:33.273890 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2584 11:08:33.273973
2585 11:08:33.276952 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2586 11:08:33.280407 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2587 11:08:33.283741 [Gating] SW calibration Done
2588 11:08:33.283823 ==
2589 11:08:33.287390 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 11:08:33.290151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 11:08:33.290233 ==
2592 11:08:33.293441 RX Vref Scan: 0
2593 11:08:33.293523
2594 11:08:33.293588 RX Vref 0 -> 0, step: 1
2595 11:08:33.293648
2596 11:08:33.296899 RX Delay -40 -> 252, step: 8
2597 11:08:33.300369 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2598 11:08:33.307530 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2599 11:08:33.310194 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2600 11:08:33.313907 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2601 11:08:33.317130 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2602 11:08:33.320321 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2603 11:08:33.324292 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2604 11:08:33.330573 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2605 11:08:33.333771 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2606 11:08:33.337373 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2607 11:08:33.340335 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2608 11:08:33.343729 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2609 11:08:33.350761 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2610 11:08:33.354219 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2611 11:08:33.357641 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2612 11:08:33.360645 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2613 11:08:33.360726 ==
2614 11:08:33.364454 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 11:08:33.367402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 11:08:33.371021 ==
2617 11:08:33.371134 DQS Delay:
2618 11:08:33.371200 DQS0 = 0, DQS1 = 0
2619 11:08:33.374557 DQM Delay:
2620 11:08:33.374639 DQM0 = 116, DQM1 = 107
2621 11:08:33.377507 DQ Delay:
2622 11:08:33.381041 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2623 11:08:33.384138 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2624 11:08:33.387998 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2625 11:08:33.391023 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2626 11:08:33.391104
2627 11:08:33.391186
2628 11:08:33.391262 ==
2629 11:08:33.394175 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 11:08:33.397930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 11:08:33.398013 ==
2632 11:08:33.398078
2633 11:08:33.398138
2634 11:08:33.400867 TX Vref Scan disable
2635 11:08:33.404287 == TX Byte 0 ==
2636 11:08:33.407448 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2637 11:08:33.411131 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2638 11:08:33.414198 == TX Byte 1 ==
2639 11:08:33.417605 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2640 11:08:33.420921 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2641 11:08:33.421002 ==
2642 11:08:33.424177 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 11:08:33.427510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 11:08:33.427623 ==
2645 11:08:33.440847 TX Vref=22, minBit 7, minWin=24, winSum=413
2646 11:08:33.444823 TX Vref=24, minBit 7, minWin=25, winSum=421
2647 11:08:33.447431 TX Vref=26, minBit 1, minWin=26, winSum=430
2648 11:08:33.451690 TX Vref=28, minBit 1, minWin=26, winSum=434
2649 11:08:33.454459 TX Vref=30, minBit 4, minWin=26, winSum=439
2650 11:08:33.457388 TX Vref=32, minBit 0, minWin=26, winSum=429
2651 11:08:33.464452 [TxChooseVref] Worse bit 4, Min win 26, Win sum 439, Final Vref 30
2652 11:08:33.464536
2653 11:08:33.468042 Final TX Range 1 Vref 30
2654 11:08:33.468124
2655 11:08:33.468189 ==
2656 11:08:33.470963 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 11:08:33.474391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 11:08:33.474498 ==
2659 11:08:33.474563
2660 11:08:33.474624
2661 11:08:33.478072 TX Vref Scan disable
2662 11:08:33.481387 == TX Byte 0 ==
2663 11:08:33.484519 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2664 11:08:33.488041 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2665 11:08:33.491301 == TX Byte 1 ==
2666 11:08:33.494517 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2667 11:08:33.497842 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2668 11:08:33.497923
2669 11:08:33.501352 [DATLAT]
2670 11:08:33.501434 Freq=1200, CH0 RK0
2671 11:08:33.501500
2672 11:08:33.504346 DATLAT Default: 0xd
2673 11:08:33.504427 0, 0xFFFF, sum = 0
2674 11:08:33.508252 1, 0xFFFF, sum = 0
2675 11:08:33.508335 2, 0xFFFF, sum = 0
2676 11:08:33.511048 3, 0xFFFF, sum = 0
2677 11:08:33.511157 4, 0xFFFF, sum = 0
2678 11:08:33.514738 5, 0xFFFF, sum = 0
2679 11:08:33.514824 6, 0xFFFF, sum = 0
2680 11:08:33.517959 7, 0xFFFF, sum = 0
2681 11:08:33.518043 8, 0xFFFF, sum = 0
2682 11:08:33.521771 9, 0xFFFF, sum = 0
2683 11:08:33.521855 10, 0xFFFF, sum = 0
2684 11:08:33.524576 11, 0xFFFF, sum = 0
2685 11:08:33.524660 12, 0x0, sum = 1
2686 11:08:33.528194 13, 0x0, sum = 2
2687 11:08:33.528303 14, 0x0, sum = 3
2688 11:08:33.531204 15, 0x0, sum = 4
2689 11:08:33.531288 best_step = 13
2690 11:08:33.531371
2691 11:08:33.531450 ==
2692 11:08:33.534819 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 11:08:33.541315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 11:08:33.541439 ==
2695 11:08:33.541550 RX Vref Scan: 1
2696 11:08:33.541662
2697 11:08:33.544986 Set Vref Range= 32 -> 127
2698 11:08:33.545109
2699 11:08:33.548070 RX Vref 32 -> 127, step: 1
2700 11:08:33.548192
2701 11:08:33.548304 RX Delay -21 -> 252, step: 4
2702 11:08:33.548415
2703 11:08:33.551730 Set Vref, RX VrefLevel [Byte0]: 32
2704 11:08:33.554691 [Byte1]: 32
2705 11:08:33.559046
2706 11:08:33.559169 Set Vref, RX VrefLevel [Byte0]: 33
2707 11:08:33.562856 [Byte1]: 33
2708 11:08:33.566947
2709 11:08:33.567034 Set Vref, RX VrefLevel [Byte0]: 34
2710 11:08:33.570355 [Byte1]: 34
2711 11:08:33.574964
2712 11:08:33.575046 Set Vref, RX VrefLevel [Byte0]: 35
2713 11:08:33.578145 [Byte1]: 35
2714 11:08:33.583346
2715 11:08:33.583430 Set Vref, RX VrefLevel [Byte0]: 36
2716 11:08:33.586338 [Byte1]: 36
2717 11:08:33.590681
2718 11:08:33.590766 Set Vref, RX VrefLevel [Byte0]: 37
2719 11:08:33.594477 [Byte1]: 37
2720 11:08:33.599062
2721 11:08:33.599185 Set Vref, RX VrefLevel [Byte0]: 38
2722 11:08:33.602116 [Byte1]: 38
2723 11:08:33.607052
2724 11:08:33.607175 Set Vref, RX VrefLevel [Byte0]: 39
2725 11:08:33.610877 [Byte1]: 39
2726 11:08:33.614713
2727 11:08:33.614832 Set Vref, RX VrefLevel [Byte0]: 40
2728 11:08:33.617895 [Byte1]: 40
2729 11:08:33.623007
2730 11:08:33.623126 Set Vref, RX VrefLevel [Byte0]: 41
2731 11:08:33.625773 [Byte1]: 41
2732 11:08:33.630271
2733 11:08:33.630387 Set Vref, RX VrefLevel [Byte0]: 42
2734 11:08:33.633786 [Byte1]: 42
2735 11:08:33.638277
2736 11:08:33.638360 Set Vref, RX VrefLevel [Byte0]: 43
2737 11:08:33.641620 [Byte1]: 43
2738 11:08:33.646117
2739 11:08:33.646195 Set Vref, RX VrefLevel [Byte0]: 44
2740 11:08:33.649899 [Byte1]: 44
2741 11:08:33.654607
2742 11:08:33.654682 Set Vref, RX VrefLevel [Byte0]: 45
2743 11:08:33.657700 [Byte1]: 45
2744 11:08:33.661930
2745 11:08:33.662003 Set Vref, RX VrefLevel [Byte0]: 46
2746 11:08:33.665276 [Byte1]: 46
2747 11:08:33.670441
2748 11:08:33.670524 Set Vref, RX VrefLevel [Byte0]: 47
2749 11:08:33.673327 [Byte1]: 47
2750 11:08:33.678283
2751 11:08:33.678365 Set Vref, RX VrefLevel [Byte0]: 48
2752 11:08:33.681686 [Byte1]: 48
2753 11:08:33.686191
2754 11:08:33.686274 Set Vref, RX VrefLevel [Byte0]: 49
2755 11:08:33.689064 [Byte1]: 49
2756 11:08:33.694062
2757 11:08:33.694145 Set Vref, RX VrefLevel [Byte0]: 50
2758 11:08:33.697227 [Byte1]: 50
2759 11:08:33.702041
2760 11:08:33.702124 Set Vref, RX VrefLevel [Byte0]: 51
2761 11:08:33.705263 [Byte1]: 51
2762 11:08:33.709519
2763 11:08:33.709602 Set Vref, RX VrefLevel [Byte0]: 52
2764 11:08:33.713128 [Byte1]: 52
2765 11:08:33.717540
2766 11:08:33.717622 Set Vref, RX VrefLevel [Byte0]: 53
2767 11:08:33.720936 [Byte1]: 53
2768 11:08:33.725441
2769 11:08:33.725535 Set Vref, RX VrefLevel [Byte0]: 54
2770 11:08:33.729055 [Byte1]: 54
2771 11:08:33.734148
2772 11:08:33.734234 Set Vref, RX VrefLevel [Byte0]: 55
2773 11:08:33.737064 [Byte1]: 55
2774 11:08:33.741585
2775 11:08:33.741667 Set Vref, RX VrefLevel [Byte0]: 56
2776 11:08:33.745245 [Byte1]: 56
2777 11:08:33.749495
2778 11:08:33.749578 Set Vref, RX VrefLevel [Byte0]: 57
2779 11:08:33.752492 [Byte1]: 57
2780 11:08:33.757216
2781 11:08:33.757298 Set Vref, RX VrefLevel [Byte0]: 58
2782 11:08:33.760541 [Byte1]: 58
2783 11:08:33.765675
2784 11:08:33.765757 Set Vref, RX VrefLevel [Byte0]: 59
2785 11:08:33.768557 [Byte1]: 59
2786 11:08:33.773271
2787 11:08:33.773354 Set Vref, RX VrefLevel [Byte0]: 60
2788 11:08:33.776720 [Byte1]: 60
2789 11:08:33.781030
2790 11:08:33.781113 Set Vref, RX VrefLevel [Byte0]: 61
2791 11:08:33.784132 [Byte1]: 61
2792 11:08:33.789607
2793 11:08:33.789690 Set Vref, RX VrefLevel [Byte0]: 62
2794 11:08:33.792078 [Byte1]: 62
2795 11:08:33.796957
2796 11:08:33.797039 Set Vref, RX VrefLevel [Byte0]: 63
2797 11:08:33.800202 [Byte1]: 63
2798 11:08:33.804617
2799 11:08:33.804705 Set Vref, RX VrefLevel [Byte0]: 64
2800 11:08:33.808241 [Byte1]: 64
2801 11:08:33.812622
2802 11:08:33.812705 Set Vref, RX VrefLevel [Byte0]: 65
2803 11:08:33.816380 [Byte1]: 65
2804 11:08:33.820412
2805 11:08:33.820496 Set Vref, RX VrefLevel [Byte0]: 66
2806 11:08:33.823780 [Byte1]: 66
2807 11:08:33.828507
2808 11:08:33.828590 Set Vref, RX VrefLevel [Byte0]: 67
2809 11:08:33.832166 [Byte1]: 67
2810 11:08:33.836367
2811 11:08:33.836450 Set Vref, RX VrefLevel [Byte0]: 68
2812 11:08:33.839593 [Byte1]: 68
2813 11:08:33.844316
2814 11:08:33.844399 Final RX Vref Byte 0 = 55 to rank0
2815 11:08:33.847692 Final RX Vref Byte 1 = 51 to rank0
2816 11:08:33.851326 Final RX Vref Byte 0 = 55 to rank1
2817 11:08:33.854753 Final RX Vref Byte 1 = 51 to rank1==
2818 11:08:33.858096 Dram Type= 6, Freq= 0, CH_0, rank 0
2819 11:08:33.861325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 11:08:33.864786 ==
2821 11:08:33.864869 DQS Delay:
2822 11:08:33.864954 DQS0 = 0, DQS1 = 0
2823 11:08:33.868460 DQM Delay:
2824 11:08:33.868542 DQM0 = 115, DQM1 = 104
2825 11:08:33.871218 DQ Delay:
2826 11:08:33.874626 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2827 11:08:33.877809 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2828 11:08:33.881451 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2829 11:08:33.884458 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2830 11:08:33.884584
2831 11:08:33.884696
2832 11:08:33.891616 [DQSOSCAuto] RK0, (LSB)MR18= 0xffee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2833 11:08:33.894670 CH0 RK0: MR19=303, MR18=FFEE
2834 11:08:33.901933 CH0_RK0: MR19=0x303, MR18=0xFFEE, DQSOSC=410, MR23=63, INC=39, DEC=26
2835 11:08:33.902055
2836 11:08:33.904605 ----->DramcWriteLeveling(PI) begin...
2837 11:08:33.904728 ==
2838 11:08:33.908240 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 11:08:33.911566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2840 11:08:33.911688 ==
2841 11:08:33.915166 Write leveling (Byte 0): 34 => 34
2842 11:08:33.918217 Write leveling (Byte 1): 28 => 28
2843 11:08:33.922336 DramcWriteLeveling(PI) end<-----
2844 11:08:33.922497
2845 11:08:33.922610 ==
2846 11:08:33.925249 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 11:08:33.928226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 11:08:33.928348 ==
2849 11:08:33.931687 [Gating] SW mode calibration
2850 11:08:33.938117 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2851 11:08:33.945517 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2852 11:08:33.948664 0 15 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2853 11:08:33.955349 0 15 4 | B1->B0 | 2828 3434 | 1 0 | (0 0) (0 0)
2854 11:08:33.958883 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 11:08:33.962085 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 11:08:33.965592 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 11:08:33.971638 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 11:08:33.975096 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2859 11:08:33.978647 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2860 11:08:33.984965 1 0 0 | B1->B0 | 2f2f 2626 | 0 0 | (0 1) (0 0)
2861 11:08:33.988315 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 11:08:33.991970 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 11:08:33.999095 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 11:08:34.002216 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 11:08:34.005028 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 11:08:34.011959 1 0 24 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
2867 11:08:34.015551 1 0 28 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
2868 11:08:34.019204 1 1 0 | B1->B0 | 2a2a 3c3c | 0 1 | (0 0) (0 0)
2869 11:08:34.025596 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 11:08:34.029136 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 11:08:34.032557 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 11:08:34.035182 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 11:08:34.042031 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 11:08:34.045321 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2875 11:08:34.048734 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2876 11:08:34.055724 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2877 11:08:34.058983 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 11:08:34.062584 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 11:08:34.069324 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 11:08:34.072612 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 11:08:34.076187 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 11:08:34.082904 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 11:08:34.085759 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 11:08:34.089153 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 11:08:34.092984 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 11:08:34.099642 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 11:08:34.102936 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 11:08:34.106372 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 11:08:34.113126 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 11:08:34.116190 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 11:08:34.119457 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2892 11:08:34.126715 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2893 11:08:34.126837 Total UI for P1: 0, mck2ui 16
2894 11:08:34.132706 best dqsien dly found for B0: ( 1, 3, 28)
2895 11:08:34.136237 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 11:08:34.139439 Total UI for P1: 0, mck2ui 16
2897 11:08:34.143312 best dqsien dly found for B1: ( 1, 4, 0)
2898 11:08:34.146250 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2899 11:08:34.149791 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2900 11:08:34.149913
2901 11:08:34.152814 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2902 11:08:34.156557 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2903 11:08:34.159730 [Gating] SW calibration Done
2904 11:08:34.159852 ==
2905 11:08:34.162996 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 11:08:34.166235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 11:08:34.166357 ==
2908 11:08:34.169342 RX Vref Scan: 0
2909 11:08:34.169463
2910 11:08:34.169576 RX Vref 0 -> 0, step: 1
2911 11:08:34.173293
2912 11:08:34.173414 RX Delay -40 -> 252, step: 8
2913 11:08:34.179817 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2914 11:08:34.183222 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2915 11:08:34.186328 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2916 11:08:34.190447 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2917 11:08:34.193328 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2918 11:08:34.196882 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2919 11:08:34.203480 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2920 11:08:34.206810 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2921 11:08:34.209643 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2922 11:08:34.213675 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2923 11:08:34.216600 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2924 11:08:34.223335 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2925 11:08:34.226574 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2926 11:08:34.230392 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2927 11:08:34.233500 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2928 11:08:34.236545 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2929 11:08:34.236671 ==
2930 11:08:34.240786 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 11:08:34.246496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 11:08:34.246620 ==
2933 11:08:34.246733 DQS Delay:
2934 11:08:34.250773 DQS0 = 0, DQS1 = 0
2935 11:08:34.250893 DQM Delay:
2936 11:08:34.251005 DQM0 = 115, DQM1 = 106
2937 11:08:34.253521 DQ Delay:
2938 11:08:34.257043 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2939 11:08:34.260275 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2940 11:08:34.263497 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2941 11:08:34.266782 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2942 11:08:34.266903
2943 11:08:34.267014
2944 11:08:34.267120 ==
2945 11:08:34.270226 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 11:08:34.273426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 11:08:34.273543 ==
2948 11:08:34.276705
2949 11:08:34.276824
2950 11:08:34.276936 TX Vref Scan disable
2951 11:08:34.280325 == TX Byte 0 ==
2952 11:08:34.284058 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2953 11:08:34.287685 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2954 11:08:34.290819 == TX Byte 1 ==
2955 11:08:34.294082 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2956 11:08:34.297045 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2957 11:08:34.297165 ==
2958 11:08:34.300280 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 11:08:34.307107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 11:08:34.307231 ==
2961 11:08:34.318313 TX Vref=22, minBit 1, minWin=25, winSum=422
2962 11:08:34.321339 TX Vref=24, minBit 1, minWin=25, winSum=427
2963 11:08:34.324448 TX Vref=26, minBit 1, minWin=26, winSum=432
2964 11:08:34.327910 TX Vref=28, minBit 2, minWin=26, winSum=433
2965 11:08:34.331451 TX Vref=30, minBit 4, minWin=26, winSum=438
2966 11:08:34.334958 TX Vref=32, minBit 0, minWin=26, winSum=433
2967 11:08:34.341341 [TxChooseVref] Worse bit 4, Min win 26, Win sum 438, Final Vref 30
2968 11:08:34.341477
2969 11:08:34.344548 Final TX Range 1 Vref 30
2970 11:08:34.344669
2971 11:08:34.344799 ==
2972 11:08:34.348159 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 11:08:34.352076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 11:08:34.352196 ==
2975 11:08:34.352329
2976 11:08:34.352452
2977 11:08:34.355302 TX Vref Scan disable
2978 11:08:34.358534 == TX Byte 0 ==
2979 11:08:34.361457 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2980 11:08:34.365049 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2981 11:08:34.368485 == TX Byte 1 ==
2982 11:08:34.372127 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2983 11:08:34.375160 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2984 11:08:34.375241
2985 11:08:34.378654 [DATLAT]
2986 11:08:34.378736 Freq=1200, CH0 RK1
2987 11:08:34.378800
2988 11:08:34.381522 DATLAT Default: 0xd
2989 11:08:34.381602 0, 0xFFFF, sum = 0
2990 11:08:34.384980 1, 0xFFFF, sum = 0
2991 11:08:34.385061 2, 0xFFFF, sum = 0
2992 11:08:34.389161 3, 0xFFFF, sum = 0
2993 11:08:34.389244 4, 0xFFFF, sum = 0
2994 11:08:34.391681 5, 0xFFFF, sum = 0
2995 11:08:34.391763 6, 0xFFFF, sum = 0
2996 11:08:34.395051 7, 0xFFFF, sum = 0
2997 11:08:34.395133 8, 0xFFFF, sum = 0
2998 11:08:34.398367 9, 0xFFFF, sum = 0
2999 11:08:34.398470 10, 0xFFFF, sum = 0
3000 11:08:34.402215 11, 0xFFFF, sum = 0
3001 11:08:34.402296 12, 0x0, sum = 1
3002 11:08:34.405566 13, 0x0, sum = 2
3003 11:08:34.405647 14, 0x0, sum = 3
3004 11:08:34.408588 15, 0x0, sum = 4
3005 11:08:34.408669 best_step = 13
3006 11:08:34.408734
3007 11:08:34.408792 ==
3008 11:08:34.411805 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 11:08:34.418385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 11:08:34.418473 ==
3011 11:08:34.418537 RX Vref Scan: 0
3012 11:08:34.418597
3013 11:08:34.421668 RX Vref 0 -> 0, step: 1
3014 11:08:34.421747
3015 11:08:34.425103 RX Delay -21 -> 252, step: 4
3016 11:08:34.428301 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3017 11:08:34.431995 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3018 11:08:34.435217 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3019 11:08:34.442198 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3020 11:08:34.445806 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3021 11:08:34.449076 iDelay=195, Bit 5, Center 106 (35 ~ 178) 144
3022 11:08:34.451880 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3023 11:08:34.455180 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3024 11:08:34.462728 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3025 11:08:34.465201 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3026 11:08:34.469151 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3027 11:08:34.472031 iDelay=195, Bit 11, Center 92 (27 ~ 158) 132
3028 11:08:34.475253 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3029 11:08:34.482457 iDelay=195, Bit 13, Center 108 (43 ~ 174) 132
3030 11:08:34.485500 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3031 11:08:34.489131 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3032 11:08:34.489231 ==
3033 11:08:34.491945 Dram Type= 6, Freq= 0, CH_0, rank 1
3034 11:08:34.495578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3035 11:08:34.495660 ==
3036 11:08:34.498751 DQS Delay:
3037 11:08:34.498832 DQS0 = 0, DQS1 = 0
3038 11:08:34.501895 DQM Delay:
3039 11:08:34.501976 DQM0 = 114, DQM1 = 104
3040 11:08:34.502041 DQ Delay:
3041 11:08:34.505881 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3042 11:08:34.509351 DQ4 =112, DQ5 =106, DQ6 =120, DQ7 =122
3043 11:08:34.512111 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =92
3044 11:08:34.518736 DQ12 =110, DQ13 =108, DQ14 =118, DQ15 =112
3045 11:08:34.518817
3046 11:08:34.518882
3047 11:08:34.525806 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 410 ps
3048 11:08:34.528792 CH0 RK1: MR19=403, MR18=F1
3049 11:08:34.535954 CH0_RK1: MR19=0x403, MR18=0xF1, DQSOSC=410, MR23=63, INC=39, DEC=26
3050 11:08:34.539008 [RxdqsGatingPostProcess] freq 1200
3051 11:08:34.542180 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3052 11:08:34.545671 best DQS0 dly(2T, 0.5T) = (0, 12)
3053 11:08:34.549053 best DQS1 dly(2T, 0.5T) = (0, 12)
3054 11:08:34.552346 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3055 11:08:34.556109 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3056 11:08:34.558892 best DQS0 dly(2T, 0.5T) = (0, 11)
3057 11:08:34.562352 best DQS1 dly(2T, 0.5T) = (0, 12)
3058 11:08:34.565791 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3059 11:08:34.569328 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3060 11:08:34.569410 Pre-setting of DQS Precalculation
3061 11:08:34.575749 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3062 11:08:34.575832 ==
3063 11:08:34.579221 Dram Type= 6, Freq= 0, CH_1, rank 0
3064 11:08:34.582805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 11:08:34.582888 ==
3066 11:08:34.589797 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3067 11:08:34.596345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3068 11:08:34.603489 [CA 0] Center 38 (9~67) winsize 59
3069 11:08:34.606425 [CA 1] Center 38 (8~68) winsize 61
3070 11:08:34.610117 [CA 2] Center 35 (5~65) winsize 61
3071 11:08:34.613207 [CA 3] Center 34 (4~65) winsize 62
3072 11:08:34.617005 [CA 4] Center 34 (4~65) winsize 62
3073 11:08:34.620646 [CA 5] Center 34 (4~64) winsize 61
3074 11:08:34.620728
3075 11:08:34.623912 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3076 11:08:34.623993
3077 11:08:34.626680 [CATrainingPosCal] consider 1 rank data
3078 11:08:34.629943 u2DelayCellTimex100 = 270/100 ps
3079 11:08:34.633654 CA0 delay=38 (9~67),Diff = 4 PI (19 cell)
3080 11:08:34.636512 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3081 11:08:34.643435 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3082 11:08:34.646754 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3083 11:08:34.650121 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3084 11:08:34.653585 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3085 11:08:34.653666
3086 11:08:34.657038 CA PerBit enable=1, Macro0, CA PI delay=34
3087 11:08:34.657119
3088 11:08:34.660180 [CBTSetCACLKResult] CA Dly = 34
3089 11:08:34.660262 CS Dly: 6 (0~37)
3090 11:08:34.660327 ==
3091 11:08:34.663647 Dram Type= 6, Freq= 0, CH_1, rank 1
3092 11:08:34.670389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 11:08:34.670509 ==
3094 11:08:34.673519 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3095 11:08:34.680549 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3096 11:08:34.688694 [CA 0] Center 38 (8~68) winsize 61
3097 11:08:34.692486 [CA 1] Center 37 (8~67) winsize 60
3098 11:08:34.695970 [CA 2] Center 34 (4~65) winsize 62
3099 11:08:34.699401 [CA 3] Center 34 (4~65) winsize 62
3100 11:08:34.703098 [CA 4] Center 34 (4~65) winsize 62
3101 11:08:34.706167 [CA 5] Center 33 (3~63) winsize 61
3102 11:08:34.706249
3103 11:08:34.708887 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3104 11:08:34.708969
3105 11:08:34.712853 [CATrainingPosCal] consider 2 rank data
3106 11:08:34.716257 u2DelayCellTimex100 = 270/100 ps
3107 11:08:34.719237 CA0 delay=38 (9~67),Diff = 5 PI (24 cell)
3108 11:08:34.722886 CA1 delay=37 (8~67),Diff = 4 PI (19 cell)
3109 11:08:34.726348 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3110 11:08:34.732830 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3111 11:08:34.736292 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3112 11:08:34.739337 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3113 11:08:34.739419
3114 11:08:34.742904 CA PerBit enable=1, Macro0, CA PI delay=33
3115 11:08:34.742985
3116 11:08:34.746063 [CBTSetCACLKResult] CA Dly = 33
3117 11:08:34.746145 CS Dly: 7 (0~40)
3118 11:08:34.746210
3119 11:08:34.749343 ----->DramcWriteLeveling(PI) begin...
3120 11:08:34.749426 ==
3121 11:08:34.752713 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 11:08:34.759240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 11:08:34.759322 ==
3124 11:08:34.762816 Write leveling (Byte 0): 28 => 28
3125 11:08:34.762902 Write leveling (Byte 1): 29 => 29
3126 11:08:34.765858 DramcWriteLeveling(PI) end<-----
3127 11:08:34.765939
3128 11:08:34.766004 ==
3129 11:08:34.769110 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 11:08:34.776288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 11:08:34.776371 ==
3132 11:08:34.779414 [Gating] SW mode calibration
3133 11:08:34.786131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3134 11:08:34.789969 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3135 11:08:34.796667 0 15 0 | B1->B0 | 2424 2323 | 0 1 | (0 0) (1 1)
3136 11:08:34.800807 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 11:08:34.802731 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 11:08:34.807127 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 11:08:34.812984 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3140 11:08:34.816435 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 11:08:34.819889 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 11:08:34.826580 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3143 11:08:34.830184 1 0 0 | B1->B0 | 2424 2929 | 0 0 | (1 0) (1 0)
3144 11:08:34.833134 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 11:08:34.840151 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 11:08:34.843352 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 11:08:34.847056 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 11:08:34.853145 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 11:08:34.856308 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 11:08:34.859772 1 0 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3151 11:08:34.866662 1 1 0 | B1->B0 | 4040 2d2d | 0 0 | (0 0) (1 1)
3152 11:08:34.869678 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 11:08:34.873368 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 11:08:34.876846 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 11:08:34.883536 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 11:08:34.887121 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 11:08:34.890355 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 11:08:34.896919 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 11:08:34.901401 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3160 11:08:34.903835 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 11:08:34.910366 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 11:08:34.913606 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 11:08:34.917081 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 11:08:34.923765 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 11:08:34.927031 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 11:08:34.930682 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 11:08:34.933880 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 11:08:34.940732 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 11:08:34.944497 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 11:08:34.948248 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 11:08:34.954438 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 11:08:34.957611 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 11:08:34.960919 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 11:08:34.967462 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 11:08:34.970960 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3176 11:08:34.974650 Total UI for P1: 0, mck2ui 16
3177 11:08:34.977493 best dqsien dly found for B0: ( 1, 3, 30)
3178 11:08:34.981408 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 11:08:34.984284 Total UI for P1: 0, mck2ui 16
3180 11:08:34.987774 best dqsien dly found for B1: ( 1, 4, 0)
3181 11:08:34.991134 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3182 11:08:34.994640 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3183 11:08:34.994759
3184 11:08:34.998146 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3185 11:08:35.001431 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3186 11:08:35.004451 [Gating] SW calibration Done
3187 11:08:35.004573 ==
3188 11:08:35.007734 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 11:08:35.011018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 11:08:35.014756 ==
3191 11:08:35.014879 RX Vref Scan: 0
3192 11:08:35.014991
3193 11:08:35.017786 RX Vref 0 -> 0, step: 1
3194 11:08:35.017903
3195 11:08:35.021049 RX Delay -40 -> 252, step: 8
3196 11:08:35.024969 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3197 11:08:35.027782 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3198 11:08:35.031389 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3199 11:08:35.034357 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3200 11:08:35.041711 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3201 11:08:35.044981 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3202 11:08:35.048044 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3203 11:08:35.051502 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3204 11:08:35.054577 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3205 11:08:35.057875 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3206 11:08:35.065201 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3207 11:08:35.068125 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3208 11:08:35.071343 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3209 11:08:35.074873 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3210 11:08:35.077954 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3211 11:08:35.085043 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3212 11:08:35.085124 ==
3213 11:08:35.088395 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 11:08:35.091265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 11:08:35.091346 ==
3216 11:08:35.091409 DQS Delay:
3217 11:08:35.094973 DQS0 = 0, DQS1 = 0
3218 11:08:35.095053 DQM Delay:
3219 11:08:35.097871 DQM0 = 116, DQM1 = 108
3220 11:08:35.097951 DQ Delay:
3221 11:08:35.101622 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =119
3222 11:08:35.104965 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3223 11:08:35.108592 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3224 11:08:35.112134 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3225 11:08:35.112214
3226 11:08:35.112277
3227 11:08:35.115674 ==
3228 11:08:35.115754 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 11:08:35.121284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 11:08:35.121364 ==
3231 11:08:35.121428
3232 11:08:35.121487
3233 11:08:35.121544 TX Vref Scan disable
3234 11:08:35.125589 == TX Byte 0 ==
3235 11:08:35.128577 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3236 11:08:35.132063 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3237 11:08:35.135209 == TX Byte 1 ==
3238 11:08:35.138604 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3239 11:08:35.142132 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3240 11:08:35.145419 ==
3241 11:08:35.148613 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 11:08:35.152073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 11:08:35.152153 ==
3244 11:08:35.163042 TX Vref=22, minBit 2, minWin=25, winSum=417
3245 11:08:35.166289 TX Vref=24, minBit 2, minWin=25, winSum=419
3246 11:08:35.170021 TX Vref=26, minBit 1, minWin=26, winSum=424
3247 11:08:35.173143 TX Vref=28, minBit 3, minWin=26, winSum=432
3248 11:08:35.176953 TX Vref=30, minBit 2, minWin=26, winSum=429
3249 11:08:35.179862 TX Vref=32, minBit 2, minWin=26, winSum=428
3250 11:08:35.186989 [TxChooseVref] Worse bit 3, Min win 26, Win sum 432, Final Vref 28
3251 11:08:35.187070
3252 11:08:35.190277 Final TX Range 1 Vref 28
3253 11:08:35.190383
3254 11:08:35.190495 ==
3255 11:08:35.193334 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 11:08:35.196854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 11:08:35.196938 ==
3258 11:08:35.197002
3259 11:08:35.197061
3260 11:08:35.200151 TX Vref Scan disable
3261 11:08:35.203258 == TX Byte 0 ==
3262 11:08:35.206902 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3263 11:08:35.210291 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3264 11:08:35.214086 == TX Byte 1 ==
3265 11:08:35.217332 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3266 11:08:35.220096 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3267 11:08:35.220177
3268 11:08:35.223423 [DATLAT]
3269 11:08:35.223502 Freq=1200, CH1 RK0
3270 11:08:35.223566
3271 11:08:35.226757 DATLAT Default: 0xd
3272 11:08:35.226836 0, 0xFFFF, sum = 0
3273 11:08:35.229953 1, 0xFFFF, sum = 0
3274 11:08:35.230061 2, 0xFFFF, sum = 0
3275 11:08:35.233525 3, 0xFFFF, sum = 0
3276 11:08:35.233606 4, 0xFFFF, sum = 0
3277 11:08:35.236846 5, 0xFFFF, sum = 0
3278 11:08:35.236974 6, 0xFFFF, sum = 0
3279 11:08:35.239936 7, 0xFFFF, sum = 0
3280 11:08:35.240062 8, 0xFFFF, sum = 0
3281 11:08:35.243561 9, 0xFFFF, sum = 0
3282 11:08:35.243684 10, 0xFFFF, sum = 0
3283 11:08:35.246991 11, 0xFFFF, sum = 0
3284 11:08:35.247113 12, 0x0, sum = 1
3285 11:08:35.250496 13, 0x0, sum = 2
3286 11:08:35.250620 14, 0x0, sum = 3
3287 11:08:35.254054 15, 0x0, sum = 4
3288 11:08:35.254177 best_step = 13
3289 11:08:35.254288
3290 11:08:35.254402 ==
3291 11:08:35.256993 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 11:08:35.263611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 11:08:35.263735 ==
3294 11:08:35.263847 RX Vref Scan: 1
3295 11:08:35.263954
3296 11:08:35.267421 Set Vref Range= 32 -> 127
3297 11:08:35.267540
3298 11:08:35.270301 RX Vref 32 -> 127, step: 1
3299 11:08:35.270445
3300 11:08:35.270556 RX Delay -21 -> 252, step: 4
3301 11:08:35.270664
3302 11:08:35.273600 Set Vref, RX VrefLevel [Byte0]: 32
3303 11:08:35.277296 [Byte1]: 32
3304 11:08:35.281408
3305 11:08:35.281529 Set Vref, RX VrefLevel [Byte0]: 33
3306 11:08:35.285314 [Byte1]: 33
3307 11:08:35.289645
3308 11:08:35.289803 Set Vref, RX VrefLevel [Byte0]: 34
3309 11:08:35.292431 [Byte1]: 34
3310 11:08:35.297264
3311 11:08:35.297385 Set Vref, RX VrefLevel [Byte0]: 35
3312 11:08:35.300621 [Byte1]: 35
3313 11:08:35.304881
3314 11:08:35.305000 Set Vref, RX VrefLevel [Byte0]: 36
3315 11:08:35.308543 [Byte1]: 36
3316 11:08:35.313419
3317 11:08:35.313540 Set Vref, RX VrefLevel [Byte0]: 37
3318 11:08:35.316644 [Byte1]: 37
3319 11:08:35.320945
3320 11:08:35.321066 Set Vref, RX VrefLevel [Byte0]: 38
3321 11:08:35.324328 [Byte1]: 38
3322 11:08:35.328596
3323 11:08:35.328716 Set Vref, RX VrefLevel [Byte0]: 39
3324 11:08:35.332094 [Byte1]: 39
3325 11:08:35.336493
3326 11:08:35.336611 Set Vref, RX VrefLevel [Byte0]: 40
3327 11:08:35.340016 [Byte1]: 40
3328 11:08:35.344563
3329 11:08:35.344682 Set Vref, RX VrefLevel [Byte0]: 41
3330 11:08:35.347721 [Byte1]: 41
3331 11:08:35.352765
3332 11:08:35.352890 Set Vref, RX VrefLevel [Byte0]: 42
3333 11:08:35.356286 [Byte1]: 42
3334 11:08:35.360599
3335 11:08:35.360719 Set Vref, RX VrefLevel [Byte0]: 43
3336 11:08:35.363956 [Byte1]: 43
3337 11:08:35.368428
3338 11:08:35.368548 Set Vref, RX VrefLevel [Byte0]: 44
3339 11:08:35.371606 [Byte1]: 44
3340 11:08:35.376404
3341 11:08:35.376524 Set Vref, RX VrefLevel [Byte0]: 45
3342 11:08:35.379904 [Byte1]: 45
3343 11:08:35.384754
3344 11:08:35.384875 Set Vref, RX VrefLevel [Byte0]: 46
3345 11:08:35.387481 [Byte1]: 46
3346 11:08:35.392415
3347 11:08:35.392537 Set Vref, RX VrefLevel [Byte0]: 47
3348 11:08:35.395366 [Byte1]: 47
3349 11:08:35.400249
3350 11:08:35.400370 Set Vref, RX VrefLevel [Byte0]: 48
3351 11:08:35.403506 [Byte1]: 48
3352 11:08:35.407821
3353 11:08:35.407942 Set Vref, RX VrefLevel [Byte0]: 49
3354 11:08:35.411198 [Byte1]: 49
3355 11:08:35.415729
3356 11:08:35.415850 Set Vref, RX VrefLevel [Byte0]: 50
3357 11:08:35.419611 [Byte1]: 50
3358 11:08:35.424001
3359 11:08:35.424120 Set Vref, RX VrefLevel [Byte0]: 51
3360 11:08:35.427378 [Byte1]: 51
3361 11:08:35.431836
3362 11:08:35.431959 Set Vref, RX VrefLevel [Byte0]: 52
3363 11:08:35.435175 [Byte1]: 52
3364 11:08:35.439696
3365 11:08:35.439820 Set Vref, RX VrefLevel [Byte0]: 53
3366 11:08:35.442856 [Byte1]: 53
3367 11:08:35.447807
3368 11:08:35.447928 Set Vref, RX VrefLevel [Byte0]: 54
3369 11:08:35.451337 [Byte1]: 54
3370 11:08:35.455612
3371 11:08:35.455732 Set Vref, RX VrefLevel [Byte0]: 55
3372 11:08:35.459057 [Byte1]: 55
3373 11:08:35.463439
3374 11:08:35.463561 Set Vref, RX VrefLevel [Byte0]: 56
3375 11:08:35.466655 [Byte1]: 56
3376 11:08:35.471073
3377 11:08:35.471195 Set Vref, RX VrefLevel [Byte0]: 57
3378 11:08:35.474886 [Byte1]: 57
3379 11:08:35.479655
3380 11:08:35.479776 Set Vref, RX VrefLevel [Byte0]: 58
3381 11:08:35.482302 [Byte1]: 58
3382 11:08:35.487395
3383 11:08:35.487516 Set Vref, RX VrefLevel [Byte0]: 59
3384 11:08:35.491030 [Byte1]: 59
3385 11:08:35.495381
3386 11:08:35.495503 Set Vref, RX VrefLevel [Byte0]: 60
3387 11:08:35.498824 [Byte1]: 60
3388 11:08:35.503013
3389 11:08:35.503132 Set Vref, RX VrefLevel [Byte0]: 61
3390 11:08:35.506365 [Byte1]: 61
3391 11:08:35.511083
3392 11:08:35.511204 Set Vref, RX VrefLevel [Byte0]: 62
3393 11:08:35.514753 [Byte1]: 62
3394 11:08:35.518875
3395 11:08:35.519000 Set Vref, RX VrefLevel [Byte0]: 63
3396 11:08:35.522083 [Byte1]: 63
3397 11:08:35.526981
3398 11:08:35.527100 Set Vref, RX VrefLevel [Byte0]: 64
3399 11:08:35.529958 [Byte1]: 64
3400 11:08:35.534575
3401 11:08:35.534697 Set Vref, RX VrefLevel [Byte0]: 65
3402 11:08:35.538082 [Byte1]: 65
3403 11:08:35.542345
3404 11:08:35.542505 Set Vref, RX VrefLevel [Byte0]: 66
3405 11:08:35.546318 [Byte1]: 66
3406 11:08:35.550651
3407 11:08:35.550770 Set Vref, RX VrefLevel [Byte0]: 67
3408 11:08:35.553620 [Byte1]: 67
3409 11:08:35.558639
3410 11:08:35.558761 Set Vref, RX VrefLevel [Byte0]: 68
3411 11:08:35.562014 [Byte1]: 68
3412 11:08:35.566595
3413 11:08:35.566713 Set Vref, RX VrefLevel [Byte0]: 69
3414 11:08:35.569476 [Byte1]: 69
3415 11:08:35.574551
3416 11:08:35.574671 Set Vref, RX VrefLevel [Byte0]: 70
3417 11:08:35.578098 [Byte1]: 70
3418 11:08:35.582047
3419 11:08:35.582168 Set Vref, RX VrefLevel [Byte0]: 71
3420 11:08:35.585747 [Byte1]: 71
3421 11:08:35.589933
3422 11:08:35.590053 Final RX Vref Byte 0 = 59 to rank0
3423 11:08:35.593601 Final RX Vref Byte 1 = 52 to rank0
3424 11:08:35.596607 Final RX Vref Byte 0 = 59 to rank1
3425 11:08:35.600029 Final RX Vref Byte 1 = 52 to rank1==
3426 11:08:35.603323 Dram Type= 6, Freq= 0, CH_1, rank 0
3427 11:08:35.611209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3428 11:08:35.611333 ==
3429 11:08:35.611446 DQS Delay:
3430 11:08:35.611554 DQS0 = 0, DQS1 = 0
3431 11:08:35.613390 DQM Delay:
3432 11:08:35.613506 DQM0 = 116, DQM1 = 109
3433 11:08:35.617437 DQ Delay:
3434 11:08:35.620939 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =114
3435 11:08:35.624116 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3436 11:08:35.627243 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =104
3437 11:08:35.630830 DQ12 =116, DQ13 =118, DQ14 =116, DQ15 =114
3438 11:08:35.630953
3439 11:08:35.631063
3440 11:08:35.637597 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbe0, (MSB)MR19= 0x303, tDQSOscB0 = 423 ps tDQSOscB1 = 412 ps
3441 11:08:35.640651 CH1 RK0: MR19=303, MR18=FBE0
3442 11:08:35.647573 CH1_RK0: MR19=0x303, MR18=0xFBE0, DQSOSC=412, MR23=63, INC=38, DEC=25
3443 11:08:35.647698
3444 11:08:35.650630 ----->DramcWriteLeveling(PI) begin...
3445 11:08:35.650754 ==
3446 11:08:35.653952 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 11:08:35.657784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 11:08:35.657905 ==
3449 11:08:35.660812 Write leveling (Byte 0): 25 => 25
3450 11:08:35.664423 Write leveling (Byte 1): 30 => 30
3451 11:08:35.667383 DramcWriteLeveling(PI) end<-----
3452 11:08:35.667504
3453 11:08:35.667614 ==
3454 11:08:35.671068 Dram Type= 6, Freq= 0, CH_1, rank 1
3455 11:08:35.674288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3456 11:08:35.674430 ==
3457 11:08:35.677633 [Gating] SW mode calibration
3458 11:08:35.684055 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3459 11:08:35.691174 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3460 11:08:35.694325 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3461 11:08:35.697725 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 11:08:35.704206 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3463 11:08:35.707675 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 11:08:35.710951 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 11:08:35.718164 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3466 11:08:35.720979 0 15 24 | B1->B0 | 3434 2c2c | 0 0 | (0 0) (0 1)
3467 11:08:35.724529 0 15 28 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
3468 11:08:35.730842 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 11:08:35.734704 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 11:08:35.738169 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 11:08:35.745022 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 11:08:35.747714 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 11:08:35.751168 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3474 11:08:35.757799 1 0 24 | B1->B0 | 2424 4343 | 0 0 | (0 0) (0 0)
3475 11:08:35.760956 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3476 11:08:35.764197 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 11:08:35.771008 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 11:08:35.774028 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 11:08:35.777915 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 11:08:35.784192 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 11:08:35.787356 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3482 11:08:35.790820 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3483 11:08:35.797902 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3484 11:08:35.801033 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 11:08:35.804890 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 11:08:35.807770 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 11:08:35.814775 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 11:08:35.817642 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 11:08:35.820811 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 11:08:35.827855 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 11:08:35.831241 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 11:08:35.834626 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 11:08:35.841601 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 11:08:35.844364 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 11:08:35.847535 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 11:08:35.854542 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 11:08:35.857591 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 11:08:35.861116 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3499 11:08:35.867693 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3500 11:08:35.867773 Total UI for P1: 0, mck2ui 16
3501 11:08:35.874007 best dqsien dly found for B0: ( 1, 3, 24)
3502 11:08:35.877694 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 11:08:35.881092 Total UI for P1: 0, mck2ui 16
3504 11:08:35.884448 best dqsien dly found for B1: ( 1, 3, 26)
3505 11:08:35.887650 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3506 11:08:35.891762 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3507 11:08:35.891885
3508 11:08:35.894863 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3509 11:08:35.897433 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3510 11:08:35.901366 [Gating] SW calibration Done
3511 11:08:35.901486 ==
3512 11:08:35.904469 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 11:08:35.907730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 11:08:35.907850 ==
3515 11:08:35.911425 RX Vref Scan: 0
3516 11:08:35.911546
3517 11:08:35.914175 RX Vref 0 -> 0, step: 1
3518 11:08:35.914295
3519 11:08:35.914429 RX Delay -40 -> 252, step: 8
3520 11:08:35.921244 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3521 11:08:35.924336 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3522 11:08:35.927635 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3523 11:08:35.931466 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
3524 11:08:35.934307 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3525 11:08:35.941332 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3526 11:08:35.944576 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3527 11:08:35.948233 iDelay=192, Bit 7, Center 111 (48 ~ 175) 128
3528 11:08:35.952028 iDelay=192, Bit 8, Center 99 (24 ~ 175) 152
3529 11:08:35.954633 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3530 11:08:35.958199 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3531 11:08:35.964674 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3532 11:08:35.967980 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3533 11:08:35.971240 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3534 11:08:35.974568 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3535 11:08:35.977823 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3536 11:08:35.981203 ==
3537 11:08:35.984541 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 11:08:35.988148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 11:08:35.988268 ==
3540 11:08:35.988381 DQS Delay:
3541 11:08:35.991395 DQS0 = 0, DQS1 = 0
3542 11:08:35.991513 DQM Delay:
3543 11:08:35.994258 DQM0 = 113, DQM1 = 110
3544 11:08:35.994376 DQ Delay:
3545 11:08:35.997828 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =115
3546 11:08:36.000995 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =111
3547 11:08:36.004902 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3548 11:08:36.007652 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3549 11:08:36.007773
3550 11:08:36.007882
3551 11:08:36.007991 ==
3552 11:08:36.010881 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 11:08:36.017982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 11:08:36.018103 ==
3555 11:08:36.018215
3556 11:08:36.018325
3557 11:08:36.018439 TX Vref Scan disable
3558 11:08:36.021367 == TX Byte 0 ==
3559 11:08:36.024821 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3560 11:08:36.027837 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3561 11:08:36.031399 == TX Byte 1 ==
3562 11:08:36.034461 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3563 11:08:36.038581 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3564 11:08:36.041502 ==
3565 11:08:36.044986 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 11:08:36.048182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 11:08:36.048304 ==
3568 11:08:36.059225 TX Vref=22, minBit 0, minWin=25, winSum=415
3569 11:08:36.063319 TX Vref=24, minBit 3, minWin=25, winSum=424
3570 11:08:36.065806 TX Vref=26, minBit 3, minWin=25, winSum=426
3571 11:08:36.069550 TX Vref=28, minBit 13, minWin=26, winSum=434
3572 11:08:36.072806 TX Vref=30, minBit 1, minWin=26, winSum=431
3573 11:08:36.076481 TX Vref=32, minBit 4, minWin=26, winSum=434
3574 11:08:36.083092 [TxChooseVref] Worse bit 13, Min win 26, Win sum 434, Final Vref 28
3575 11:08:36.083216
3576 11:08:36.086084 Final TX Range 1 Vref 28
3577 11:08:36.086206
3578 11:08:36.086318 ==
3579 11:08:36.089688 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 11:08:36.092690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 11:08:36.092812 ==
3582 11:08:36.092923
3583 11:08:36.096154
3584 11:08:36.096271 TX Vref Scan disable
3585 11:08:36.099269 == TX Byte 0 ==
3586 11:08:36.103149 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3587 11:08:36.106735 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3588 11:08:36.109604 == TX Byte 1 ==
3589 11:08:36.112828 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3590 11:08:36.116200 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3591 11:08:36.116319
3592 11:08:36.119392 [DATLAT]
3593 11:08:36.119512 Freq=1200, CH1 RK1
3594 11:08:36.119621
3595 11:08:36.123172 DATLAT Default: 0xd
3596 11:08:36.123291 0, 0xFFFF, sum = 0
3597 11:08:36.127093 1, 0xFFFF, sum = 0
3598 11:08:36.127216 2, 0xFFFF, sum = 0
3599 11:08:36.129589 3, 0xFFFF, sum = 0
3600 11:08:36.129711 4, 0xFFFF, sum = 0
3601 11:08:36.133048 5, 0xFFFF, sum = 0
3602 11:08:36.133173 6, 0xFFFF, sum = 0
3603 11:08:36.135912 7, 0xFFFF, sum = 0
3604 11:08:36.139389 8, 0xFFFF, sum = 0
3605 11:08:36.139512 9, 0xFFFF, sum = 0
3606 11:08:36.142817 10, 0xFFFF, sum = 0
3607 11:08:36.142938 11, 0xFFFF, sum = 0
3608 11:08:36.146624 12, 0x0, sum = 1
3609 11:08:36.146779 13, 0x0, sum = 2
3610 11:08:36.146894 14, 0x0, sum = 3
3611 11:08:36.149833 15, 0x0, sum = 4
3612 11:08:36.149957 best_step = 13
3613 11:08:36.150067
3614 11:08:36.152992 ==
3615 11:08:36.153109 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 11:08:36.159362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 11:08:36.159487 ==
3618 11:08:36.159598 RX Vref Scan: 0
3619 11:08:36.159703
3620 11:08:36.163089 RX Vref 0 -> 0, step: 1
3621 11:08:36.163211
3622 11:08:36.165796 RX Delay -21 -> 252, step: 4
3623 11:08:36.169469 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3624 11:08:36.176275 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3625 11:08:36.179509 iDelay=191, Bit 2, Center 106 (43 ~ 170) 128
3626 11:08:36.182585 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3627 11:08:36.186056 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3628 11:08:36.189034 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3629 11:08:36.192998 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3630 11:08:36.199583 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3631 11:08:36.202382 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3632 11:08:36.206025 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3633 11:08:36.209664 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3634 11:08:36.213184 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3635 11:08:36.219361 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3636 11:08:36.222830 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3637 11:08:36.226173 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3638 11:08:36.229135 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3639 11:08:36.229255 ==
3640 11:08:36.232894 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 11:08:36.239282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 11:08:36.239407 ==
3643 11:08:36.239522 DQS Delay:
3644 11:08:36.239632 DQS0 = 0, DQS1 = 0
3645 11:08:36.242534 DQM Delay:
3646 11:08:36.242653 DQM0 = 114, DQM1 = 109
3647 11:08:36.246059 DQ Delay:
3648 11:08:36.249145 DQ0 =114, DQ1 =110, DQ2 =106, DQ3 =112
3649 11:08:36.252802 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3650 11:08:36.256108 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3651 11:08:36.260251 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =116
3652 11:08:36.260374
3653 11:08:36.260485
3654 11:08:36.266075 [DQSOSCAuto] RK1, (LSB)MR18= 0xf4fc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 415 ps
3655 11:08:36.269022 CH1 RK1: MR19=303, MR18=F4FC
3656 11:08:36.275781 CH1_RK1: MR19=0x303, MR18=0xF4FC, DQSOSC=411, MR23=63, INC=38, DEC=25
3657 11:08:36.279461 [RxdqsGatingPostProcess] freq 1200
3658 11:08:36.286098 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3659 11:08:36.289594 best DQS0 dly(2T, 0.5T) = (0, 11)
3660 11:08:36.292979 best DQS1 dly(2T, 0.5T) = (0, 12)
3661 11:08:36.295727 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3662 11:08:36.295810 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3663 11:08:36.299676 best DQS0 dly(2T, 0.5T) = (0, 11)
3664 11:08:36.302942 best DQS1 dly(2T, 0.5T) = (0, 11)
3665 11:08:36.305832 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3666 11:08:36.309399 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3667 11:08:36.312495 Pre-setting of DQS Precalculation
3668 11:08:36.319544 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3669 11:08:36.326220 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3670 11:08:36.332417 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3671 11:08:36.332525
3672 11:08:36.332609
3673 11:08:36.336255 [Calibration Summary] 2400 Mbps
3674 11:08:36.336338 CH 0, Rank 0
3675 11:08:36.339226 SW Impedance : PASS
3676 11:08:36.343098 DUTY Scan : NO K
3677 11:08:36.343181 ZQ Calibration : PASS
3678 11:08:36.346272 Jitter Meter : NO K
3679 11:08:36.349410 CBT Training : PASS
3680 11:08:36.349492 Write leveling : PASS
3681 11:08:36.352453 RX DQS gating : PASS
3682 11:08:36.355804 RX DQ/DQS(RDDQC) : PASS
3683 11:08:36.355887 TX DQ/DQS : PASS
3684 11:08:36.359448 RX DATLAT : PASS
3685 11:08:36.359530 RX DQ/DQS(Engine): PASS
3686 11:08:36.362294 TX OE : NO K
3687 11:08:36.362400 All Pass.
3688 11:08:36.362482
3689 11:08:36.365745 CH 0, Rank 1
3690 11:08:36.365842 SW Impedance : PASS
3691 11:08:36.369235 DUTY Scan : NO K
3692 11:08:36.373191 ZQ Calibration : PASS
3693 11:08:36.373274 Jitter Meter : NO K
3694 11:08:36.376386 CBT Training : PASS
3695 11:08:36.379695 Write leveling : PASS
3696 11:08:36.379782 RX DQS gating : PASS
3697 11:08:36.382594 RX DQ/DQS(RDDQC) : PASS
3698 11:08:36.385769 TX DQ/DQS : PASS
3699 11:08:36.385852 RX DATLAT : PASS
3700 11:08:36.389104 RX DQ/DQS(Engine): PASS
3701 11:08:36.392651 TX OE : NO K
3702 11:08:36.392734 All Pass.
3703 11:08:36.392817
3704 11:08:36.392896 CH 1, Rank 0
3705 11:08:36.395745 SW Impedance : PASS
3706 11:08:36.399012 DUTY Scan : NO K
3707 11:08:36.399131 ZQ Calibration : PASS
3708 11:08:36.402338 Jitter Meter : NO K
3709 11:08:36.402453 CBT Training : PASS
3710 11:08:36.405897 Write leveling : PASS
3711 11:08:36.409439 RX DQS gating : PASS
3712 11:08:36.409522 RX DQ/DQS(RDDQC) : PASS
3713 11:08:36.412682 TX DQ/DQS : PASS
3714 11:08:36.416026 RX DATLAT : PASS
3715 11:08:36.416109 RX DQ/DQS(Engine): PASS
3716 11:08:36.419708 TX OE : NO K
3717 11:08:36.419791 All Pass.
3718 11:08:36.419875
3719 11:08:36.422618 CH 1, Rank 1
3720 11:08:36.422725 SW Impedance : PASS
3721 11:08:36.426098 DUTY Scan : NO K
3722 11:08:36.428891 ZQ Calibration : PASS
3723 11:08:36.428974 Jitter Meter : NO K
3724 11:08:36.432481 CBT Training : PASS
3725 11:08:36.435888 Write leveling : PASS
3726 11:08:36.435971 RX DQS gating : PASS
3727 11:08:36.439283 RX DQ/DQS(RDDQC) : PASS
3728 11:08:36.442635 TX DQ/DQS : PASS
3729 11:08:36.442718 RX DATLAT : PASS
3730 11:08:36.445898 RX DQ/DQS(Engine): PASS
3731 11:08:36.445998 TX OE : NO K
3732 11:08:36.449097 All Pass.
3733 11:08:36.449179
3734 11:08:36.449279 DramC Write-DBI off
3735 11:08:36.452853 PER_BANK_REFRESH: Hybrid Mode
3736 11:08:36.455487 TX_TRACKING: ON
3737 11:08:36.462669 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3738 11:08:36.465973 [FAST_K] Save calibration result to emmc
3739 11:08:36.472321 dramc_set_vcore_voltage set vcore to 650000
3740 11:08:36.472404 Read voltage for 600, 5
3741 11:08:36.472488 Vio18 = 0
3742 11:08:36.475450 Vcore = 650000
3743 11:08:36.475533 Vdram = 0
3744 11:08:36.475617 Vddq = 0
3745 11:08:36.479283 Vmddr = 0
3746 11:08:36.482523 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3747 11:08:36.489151 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3748 11:08:36.492102 MEM_TYPE=3, freq_sel=19
3749 11:08:36.492224 sv_algorithm_assistance_LP4_1600
3750 11:08:36.499082 ============ PULL DRAM RESETB DOWN ============
3751 11:08:36.502121 ========== PULL DRAM RESETB DOWN end =========
3752 11:08:36.505551 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3753 11:08:36.508889 ===================================
3754 11:08:36.512657 LPDDR4 DRAM CONFIGURATION
3755 11:08:36.515426 ===================================
3756 11:08:36.519006 EX_ROW_EN[0] = 0x0
3757 11:08:36.519130 EX_ROW_EN[1] = 0x0
3758 11:08:36.522468 LP4Y_EN = 0x0
3759 11:08:36.522587 WORK_FSP = 0x0
3760 11:08:36.525863 WL = 0x2
3761 11:08:36.525984 RL = 0x2
3762 11:08:36.528399 BL = 0x2
3763 11:08:36.528519 RPST = 0x0
3764 11:08:36.532101 RD_PRE = 0x0
3765 11:08:36.532223 WR_PRE = 0x1
3766 11:08:36.535166 WR_PST = 0x0
3767 11:08:36.535288 DBI_WR = 0x0
3768 11:08:36.538641 DBI_RD = 0x0
3769 11:08:36.538764 OTF = 0x1
3770 11:08:36.541922 ===================================
3771 11:08:36.545364 ===================================
3772 11:08:36.548616 ANA top config
3773 11:08:36.552036 ===================================
3774 11:08:36.555402 DLL_ASYNC_EN = 0
3775 11:08:36.555527 ALL_SLAVE_EN = 1
3776 11:08:36.558947 NEW_RANK_MODE = 1
3777 11:08:36.562587 DLL_IDLE_MODE = 1
3778 11:08:36.565595 LP45_APHY_COMB_EN = 1
3779 11:08:36.565716 TX_ODT_DIS = 1
3780 11:08:36.568820 NEW_8X_MODE = 1
3781 11:08:36.572308 ===================================
3782 11:08:36.575743 ===================================
3783 11:08:36.578664 data_rate = 1200
3784 11:08:36.581911 CKR = 1
3785 11:08:36.585583 DQ_P2S_RATIO = 8
3786 11:08:36.588906 ===================================
3787 11:08:36.592934 CA_P2S_RATIO = 8
3788 11:08:36.593057 DQ_CA_OPEN = 0
3789 11:08:36.595724 DQ_SEMI_OPEN = 0
3790 11:08:36.599065 CA_SEMI_OPEN = 0
3791 11:08:36.602363 CA_FULL_RATE = 0
3792 11:08:36.605498 DQ_CKDIV4_EN = 1
3793 11:08:36.605620 CA_CKDIV4_EN = 1
3794 11:08:36.608768 CA_PREDIV_EN = 0
3795 11:08:36.612092 PH8_DLY = 0
3796 11:08:36.616205 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3797 11:08:36.618975 DQ_AAMCK_DIV = 4
3798 11:08:36.622092 CA_AAMCK_DIV = 4
3799 11:08:36.622212 CA_ADMCK_DIV = 4
3800 11:08:36.625701 DQ_TRACK_CA_EN = 0
3801 11:08:36.629345 CA_PICK = 600
3802 11:08:36.632286 CA_MCKIO = 600
3803 11:08:36.635273 MCKIO_SEMI = 0
3804 11:08:36.639199 PLL_FREQ = 2288
3805 11:08:36.642614 DQ_UI_PI_RATIO = 32
3806 11:08:36.642696 CA_UI_PI_RATIO = 0
3807 11:08:36.645838 ===================================
3808 11:08:36.649166 ===================================
3809 11:08:36.652262 memory_type:LPDDR4
3810 11:08:36.655391 GP_NUM : 10
3811 11:08:36.655473 SRAM_EN : 1
3812 11:08:36.658741 MD32_EN : 0
3813 11:08:36.662581 ===================================
3814 11:08:36.665598 [ANA_INIT] >>>>>>>>>>>>>>
3815 11:08:36.668741 <<<<<< [CONFIGURE PHASE]: ANA_TX
3816 11:08:36.672302 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3817 11:08:36.675448 ===================================
3818 11:08:36.675530 data_rate = 1200,PCW = 0X5800
3819 11:08:36.678899 ===================================
3820 11:08:36.682006 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3821 11:08:36.688661 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3822 11:08:36.696116 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3823 11:08:36.699072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3824 11:08:36.702577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3825 11:08:36.705489 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3826 11:08:36.708850 [ANA_INIT] flow start
3827 11:08:36.708931 [ANA_INIT] PLL >>>>>>>>
3828 11:08:36.712253 [ANA_INIT] PLL <<<<<<<<
3829 11:08:36.715666 [ANA_INIT] MIDPI >>>>>>>>
3830 11:08:36.719213 [ANA_INIT] MIDPI <<<<<<<<
3831 11:08:36.719335 [ANA_INIT] DLL >>>>>>>>
3832 11:08:36.722178 [ANA_INIT] flow end
3833 11:08:36.725637 ============ LP4 DIFF to SE enter ============
3834 11:08:36.728544 ============ LP4 DIFF to SE exit ============
3835 11:08:36.732471 [ANA_INIT] <<<<<<<<<<<<<
3836 11:08:36.735515 [Flow] Enable top DCM control >>>>>
3837 11:08:36.739517 [Flow] Enable top DCM control <<<<<
3838 11:08:36.742379 Enable DLL master slave shuffle
3839 11:08:36.745623 ==============================================================
3840 11:08:36.748741 Gating Mode config
3841 11:08:36.755622 ==============================================================
3842 11:08:36.755702 Config description:
3843 11:08:36.765797 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3844 11:08:36.772122 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3845 11:08:36.775592 SELPH_MODE 0: By rank 1: By Phase
3846 11:08:36.782013 ==============================================================
3847 11:08:36.785963 GAT_TRACK_EN = 1
3848 11:08:36.789213 RX_GATING_MODE = 2
3849 11:08:36.792721 RX_GATING_TRACK_MODE = 2
3850 11:08:36.795742 SELPH_MODE = 1
3851 11:08:36.798811 PICG_EARLY_EN = 1
3852 11:08:36.802143 VALID_LAT_VALUE = 1
3853 11:08:36.805480 ==============================================================
3854 11:08:36.809035 Enter into Gating configuration >>>>
3855 11:08:36.812076 Exit from Gating configuration <<<<
3856 11:08:36.815414 Enter into DVFS_PRE_config >>>>>
3857 11:08:36.825868 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3858 11:08:36.829261 Exit from DVFS_PRE_config <<<<<
3859 11:08:36.832694 Enter into PICG configuration >>>>
3860 11:08:36.835818 Exit from PICG configuration <<<<
3861 11:08:36.839095 [RX_INPUT] configuration >>>>>
3862 11:08:36.842241 [RX_INPUT] configuration <<<<<
3863 11:08:36.849246 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3864 11:08:36.852938 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3865 11:08:36.859068 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3866 11:08:36.865830 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3867 11:08:36.872768 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3868 11:08:36.879366 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3869 11:08:36.883120 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3870 11:08:36.885729 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3871 11:08:36.889607 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3872 11:08:36.896156 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3873 11:08:36.899294 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3874 11:08:36.902365 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3875 11:08:36.906124 ===================================
3876 11:08:36.909113 LPDDR4 DRAM CONFIGURATION
3877 11:08:36.912065 ===================================
3878 11:08:36.912147 EX_ROW_EN[0] = 0x0
3879 11:08:36.915603 EX_ROW_EN[1] = 0x0
3880 11:08:36.915708 LP4Y_EN = 0x0
3881 11:08:36.919397 WORK_FSP = 0x0
3882 11:08:36.919477 WL = 0x2
3883 11:08:36.922773 RL = 0x2
3884 11:08:36.922852 BL = 0x2
3885 11:08:36.925946 RPST = 0x0
3886 11:08:36.928987 RD_PRE = 0x0
3887 11:08:36.929059 WR_PRE = 0x1
3888 11:08:36.932280 WR_PST = 0x0
3889 11:08:36.932351 DBI_WR = 0x0
3890 11:08:36.935617 DBI_RD = 0x0
3891 11:08:36.935701 OTF = 0x1
3892 11:08:36.939066 ===================================
3893 11:08:36.942657 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3894 11:08:36.946626 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3895 11:08:36.952750 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3896 11:08:36.956061 ===================================
3897 11:08:36.959220 LPDDR4 DRAM CONFIGURATION
3898 11:08:36.962381 ===================================
3899 11:08:36.962469 EX_ROW_EN[0] = 0x10
3900 11:08:36.965987 EX_ROW_EN[1] = 0x0
3901 11:08:36.966067 LP4Y_EN = 0x0
3902 11:08:36.969391 WORK_FSP = 0x0
3903 11:08:36.969471 WL = 0x2
3904 11:08:36.972345 RL = 0x2
3905 11:08:36.972425 BL = 0x2
3906 11:08:36.975637 RPST = 0x0
3907 11:08:36.975717 RD_PRE = 0x0
3908 11:08:36.978831 WR_PRE = 0x1
3909 11:08:36.978911 WR_PST = 0x0
3910 11:08:36.982630 DBI_WR = 0x0
3911 11:08:36.982736 DBI_RD = 0x0
3912 11:08:36.985841 OTF = 0x1
3913 11:08:36.989372 ===================================
3914 11:08:36.995885 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3915 11:08:36.999275 nWR fixed to 30
3916 11:08:37.002684 [ModeRegInit_LP4] CH0 RK0
3917 11:08:37.002764 [ModeRegInit_LP4] CH0 RK1
3918 11:08:37.005496 [ModeRegInit_LP4] CH1 RK0
3919 11:08:37.009064 [ModeRegInit_LP4] CH1 RK1
3920 11:08:37.009143 match AC timing 17
3921 11:08:37.015792 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3922 11:08:37.019078 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3923 11:08:37.022589 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3924 11:08:37.029038 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3925 11:08:37.032420 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3926 11:08:37.032501 ==
3927 11:08:37.035665 Dram Type= 6, Freq= 0, CH_0, rank 0
3928 11:08:37.039269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3929 11:08:37.039350 ==
3930 11:08:37.045712 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3931 11:08:37.052388 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3932 11:08:37.056081 [CA 0] Center 36 (6~66) winsize 61
3933 11:08:37.059067 [CA 1] Center 36 (6~66) winsize 61
3934 11:08:37.062318 [CA 2] Center 34 (4~65) winsize 62
3935 11:08:37.065842 [CA 3] Center 34 (4~64) winsize 61
3936 11:08:37.069070 [CA 4] Center 33 (3~64) winsize 62
3937 11:08:37.072609 [CA 5] Center 33 (3~64) winsize 62
3938 11:08:37.072689
3939 11:08:37.075801 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3940 11:08:37.075887
3941 11:08:37.079301 [CATrainingPosCal] consider 1 rank data
3942 11:08:37.082840 u2DelayCellTimex100 = 270/100 ps
3943 11:08:37.085943 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3944 11:08:37.088974 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3945 11:08:37.092529 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3946 11:08:37.095895 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3947 11:08:37.098983 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3948 11:08:37.102355 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3949 11:08:37.102481
3950 11:08:37.109344 CA PerBit enable=1, Macro0, CA PI delay=33
3951 11:08:37.109424
3952 11:08:37.109487 [CBTSetCACLKResult] CA Dly = 33
3953 11:08:37.112626 CS Dly: 5 (0~36)
3954 11:08:37.112706 ==
3955 11:08:37.115543 Dram Type= 6, Freq= 0, CH_0, rank 1
3956 11:08:37.119605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3957 11:08:37.119685 ==
3958 11:08:37.125752 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3959 11:08:37.132168 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3960 11:08:37.136145 [CA 0] Center 36 (6~66) winsize 61
3961 11:08:37.138748 [CA 1] Center 36 (6~66) winsize 61
3962 11:08:37.142021 [CA 2] Center 34 (4~65) winsize 62
3963 11:08:37.145685 [CA 3] Center 34 (4~64) winsize 61
3964 11:08:37.148996 [CA 4] Center 33 (3~64) winsize 62
3965 11:08:37.152834 [CA 5] Center 33 (3~64) winsize 62
3966 11:08:37.152914
3967 11:08:37.155520 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3968 11:08:37.155600
3969 11:08:37.159497 [CATrainingPosCal] consider 2 rank data
3970 11:08:37.162261 u2DelayCellTimex100 = 270/100 ps
3971 11:08:37.165494 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3972 11:08:37.169005 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3973 11:08:37.172274 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3974 11:08:37.175261 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3975 11:08:37.179190 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3976 11:08:37.182236 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3977 11:08:37.182341
3978 11:08:37.188707 CA PerBit enable=1, Macro0, CA PI delay=33
3979 11:08:37.188787
3980 11:08:37.192276 [CBTSetCACLKResult] CA Dly = 33
3981 11:08:37.192399 CS Dly: 5 (0~36)
3982 11:08:37.192479
3983 11:08:37.195277 ----->DramcWriteLeveling(PI) begin...
3984 11:08:37.195358 ==
3985 11:08:37.198828 Dram Type= 6, Freq= 0, CH_0, rank 0
3986 11:08:37.202542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 11:08:37.202622 ==
3988 11:08:37.205297 Write leveling (Byte 0): 32 => 32
3989 11:08:37.208956 Write leveling (Byte 1): 28 => 28
3990 11:08:37.212134 DramcWriteLeveling(PI) end<-----
3991 11:08:37.212214
3992 11:08:37.212278 ==
3993 11:08:37.216111 Dram Type= 6, Freq= 0, CH_0, rank 0
3994 11:08:37.222294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 11:08:37.222374 ==
3996 11:08:37.222475 [Gating] SW mode calibration
3997 11:08:37.232313 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3998 11:08:37.235426 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3999 11:08:37.238436 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 11:08:37.246002 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 11:08:37.248617 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4002 11:08:37.252311 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4003 11:08:37.258875 0 9 16 | B1->B0 | 3232 2c2c | 0 0 | (0 0) (0 0)
4004 11:08:37.262129 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 11:08:37.265573 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 11:08:37.272241 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 11:08:37.275112 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 11:08:37.278767 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 11:08:37.285217 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 11:08:37.288753 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4011 11:08:37.291798 0 10 16 | B1->B0 | 2e2e 3d3d | 0 0 | (0 0) (0 0)
4012 11:08:37.298988 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4013 11:08:37.302560 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 11:08:37.305083 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 11:08:37.311750 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 11:08:37.315317 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 11:08:37.318905 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 11:08:37.321982 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 11:08:37.329057 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4020 11:08:37.332255 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4021 11:08:37.335495 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 11:08:37.342184 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 11:08:37.345096 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 11:08:37.348686 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 11:08:37.355078 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 11:08:37.358714 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 11:08:37.361680 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 11:08:37.368785 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 11:08:37.371912 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 11:08:37.374920 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 11:08:37.381489 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 11:08:37.384786 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 11:08:37.388823 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 11:08:37.395617 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 11:08:37.398145 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4036 11:08:37.401990 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 11:08:37.405177 Total UI for P1: 0, mck2ui 16
4038 11:08:37.408291 best dqsien dly found for B0: ( 0, 13, 16)
4039 11:08:37.411918 Total UI for P1: 0, mck2ui 16
4040 11:08:37.415472 best dqsien dly found for B1: ( 0, 13, 16)
4041 11:08:37.419094 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4042 11:08:37.421560 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4043 11:08:37.421640
4044 11:08:37.428291 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4045 11:08:37.431439 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4046 11:08:37.431519 [Gating] SW calibration Done
4047 11:08:37.434848 ==
4048 11:08:37.434922 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 11:08:37.441550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 11:08:37.441631 ==
4051 11:08:37.441695 RX Vref Scan: 0
4052 11:08:37.441754
4053 11:08:37.445010 RX Vref 0 -> 0, step: 1
4054 11:08:37.445091
4055 11:08:37.448363 RX Delay -230 -> 252, step: 16
4056 11:08:37.451495 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4057 11:08:37.455075 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4058 11:08:37.461480 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4059 11:08:37.465012 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4060 11:08:37.468454 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4061 11:08:37.471701 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4062 11:08:37.474909 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4063 11:08:37.481608 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4064 11:08:37.484996 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4065 11:08:37.488203 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4066 11:08:37.491676 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4067 11:08:37.498181 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4068 11:08:37.501481 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4069 11:08:37.504938 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4070 11:08:37.507956 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4071 11:08:37.515029 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4072 11:08:37.515109 ==
4073 11:08:37.517938 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 11:08:37.521372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 11:08:37.521453 ==
4076 11:08:37.521517 DQS Delay:
4077 11:08:37.524502 DQS0 = 0, DQS1 = 0
4078 11:08:37.524608 DQM Delay:
4079 11:08:37.528363 DQM0 = 41, DQM1 = 31
4080 11:08:37.528443 DQ Delay:
4081 11:08:37.531567 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4082 11:08:37.534524 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4083 11:08:37.538148 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4084 11:08:37.541084 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4085 11:08:37.541166
4086 11:08:37.541229
4087 11:08:37.541317 ==
4088 11:08:37.544826 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 11:08:37.548095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 11:08:37.548176 ==
4091 11:08:37.548240
4092 11:08:37.548299
4093 11:08:37.551483 TX Vref Scan disable
4094 11:08:37.554651 == TX Byte 0 ==
4095 11:08:37.557817 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4096 11:08:37.561715 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4097 11:08:37.565215 == TX Byte 1 ==
4098 11:08:37.567831 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4099 11:08:37.571263 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4100 11:08:37.571343 ==
4101 11:08:37.574993 Dram Type= 6, Freq= 0, CH_0, rank 0
4102 11:08:37.581168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4103 11:08:37.581248 ==
4104 11:08:37.581312
4105 11:08:37.581371
4106 11:08:37.581428 TX Vref Scan disable
4107 11:08:37.585753 == TX Byte 0 ==
4108 11:08:37.589011 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4109 11:08:37.592368 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4110 11:08:37.595874 == TX Byte 1 ==
4111 11:08:37.599282 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4112 11:08:37.602667 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4113 11:08:37.605809
4114 11:08:37.605890 [DATLAT]
4115 11:08:37.605955 Freq=600, CH0 RK0
4116 11:08:37.606014
4117 11:08:37.609142 DATLAT Default: 0x9
4118 11:08:37.609222 0, 0xFFFF, sum = 0
4119 11:08:37.612920 1, 0xFFFF, sum = 0
4120 11:08:37.613044 2, 0xFFFF, sum = 0
4121 11:08:37.615940 3, 0xFFFF, sum = 0
4122 11:08:37.616022 4, 0xFFFF, sum = 0
4123 11:08:37.619016 5, 0xFFFF, sum = 0
4124 11:08:37.619097 6, 0xFFFF, sum = 0
4125 11:08:37.622433 7, 0xFFFF, sum = 0
4126 11:08:37.622515 8, 0x0, sum = 1
4127 11:08:37.625830 9, 0x0, sum = 2
4128 11:08:37.625911 10, 0x0, sum = 3
4129 11:08:37.629331 11, 0x0, sum = 4
4130 11:08:37.629417 best_step = 9
4131 11:08:37.629504
4132 11:08:37.629612 ==
4133 11:08:37.632345 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 11:08:37.638957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 11:08:37.639033 ==
4136 11:08:37.639095 RX Vref Scan: 1
4137 11:08:37.639154
4138 11:08:37.642556 RX Vref 0 -> 0, step: 1
4139 11:08:37.642636
4140 11:08:37.645901 RX Delay -195 -> 252, step: 8
4141 11:08:37.645980
4142 11:08:37.649033 Set Vref, RX VrefLevel [Byte0]: 55
4143 11:08:37.652187 [Byte1]: 51
4144 11:08:37.652267
4145 11:08:37.655533 Final RX Vref Byte 0 = 55 to rank0
4146 11:08:37.658967 Final RX Vref Byte 1 = 51 to rank0
4147 11:08:37.662594 Final RX Vref Byte 0 = 55 to rank1
4148 11:08:37.666072 Final RX Vref Byte 1 = 51 to rank1==
4149 11:08:37.668751 Dram Type= 6, Freq= 0, CH_0, rank 0
4150 11:08:37.672338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 11:08:37.672418 ==
4152 11:08:37.675645 DQS Delay:
4153 11:08:37.675726 DQS0 = 0, DQS1 = 0
4154 11:08:37.675789 DQM Delay:
4155 11:08:37.679132 DQM0 = 42, DQM1 = 33
4156 11:08:37.679212 DQ Delay:
4157 11:08:37.682755 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4158 11:08:37.686375 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4159 11:08:37.689292 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4160 11:08:37.692341 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4161 11:08:37.692421
4162 11:08:37.692484
4163 11:08:37.702553 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b1a, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
4164 11:08:37.702634 CH0 RK0: MR19=808, MR18=3B1A
4165 11:08:37.708993 CH0_RK0: MR19=0x808, MR18=0x3B1A, DQSOSC=398, MR23=63, INC=165, DEC=110
4166 11:08:37.709074
4167 11:08:37.712582 ----->DramcWriteLeveling(PI) begin...
4168 11:08:37.712663 ==
4169 11:08:37.715721 Dram Type= 6, Freq= 0, CH_0, rank 1
4170 11:08:37.722508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 11:08:37.722581 ==
4172 11:08:37.726056 Write leveling (Byte 0): 33 => 33
4173 11:08:37.728705 Write leveling (Byte 1): 29 => 29
4174 11:08:37.728775 DramcWriteLeveling(PI) end<-----
4175 11:08:37.732345
4176 11:08:37.732416 ==
4177 11:08:37.735616 Dram Type= 6, Freq= 0, CH_0, rank 1
4178 11:08:37.739497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4179 11:08:37.739580 ==
4180 11:08:37.742019 [Gating] SW mode calibration
4181 11:08:37.749260 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4182 11:08:37.752035 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4183 11:08:37.758821 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 11:08:37.762202 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 11:08:37.765409 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4186 11:08:37.772493 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4187 11:08:37.775787 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4188 11:08:37.778952 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4189 11:08:37.785625 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 11:08:37.788937 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 11:08:37.792199 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 11:08:37.799007 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 11:08:37.802254 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 11:08:37.805476 0 10 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
4195 11:08:37.812296 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4196 11:08:37.815735 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 11:08:37.819022 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 11:08:37.822314 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 11:08:37.829113 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 11:08:37.832376 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 11:08:37.835737 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 11:08:37.842249 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4203 11:08:37.846011 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4204 11:08:37.848979 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4205 11:08:37.855855 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 11:08:37.858885 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 11:08:37.862741 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 11:08:37.868979 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 11:08:37.872554 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 11:08:37.875792 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 11:08:37.882972 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 11:08:37.885710 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 11:08:37.889411 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 11:08:37.895832 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 11:08:37.899284 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 11:08:37.902862 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 11:08:37.906006 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 11:08:37.912447 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 11:08:37.915665 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 11:08:37.919223 Total UI for P1: 0, mck2ui 16
4221 11:08:37.922609 best dqsien dly found for B0: ( 0, 13, 14)
4222 11:08:37.925651 Total UI for P1: 0, mck2ui 16
4223 11:08:37.929196 best dqsien dly found for B1: ( 0, 13, 14)
4224 11:08:37.932439 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4225 11:08:37.935878 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4226 11:08:37.935959
4227 11:08:37.939446 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4228 11:08:37.943117 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4229 11:08:37.946302 [Gating] SW calibration Done
4230 11:08:37.946461 ==
4231 11:08:37.949431 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 11:08:37.955919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 11:08:37.956044 ==
4234 11:08:37.956158 RX Vref Scan: 0
4235 11:08:37.956267
4236 11:08:37.959179 RX Vref 0 -> 0, step: 1
4237 11:08:37.959297
4238 11:08:37.962304 RX Delay -230 -> 252, step: 16
4239 11:08:37.965843 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4240 11:08:37.969202 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4241 11:08:37.972691 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4242 11:08:37.979649 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4243 11:08:37.983169 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4244 11:08:37.986219 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4245 11:08:37.989861 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4246 11:08:37.992952 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4247 11:08:37.999661 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4248 11:08:38.003570 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4249 11:08:38.006555 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4250 11:08:38.009914 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4251 11:08:38.016002 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4252 11:08:38.019721 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4253 11:08:38.023247 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4254 11:08:38.026246 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4255 11:08:38.026367 ==
4256 11:08:38.029481 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 11:08:38.036298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 11:08:38.036419 ==
4259 11:08:38.036531 DQS Delay:
4260 11:08:38.036642 DQS0 = 0, DQS1 = 0
4261 11:08:38.039364 DQM Delay:
4262 11:08:38.039484 DQM0 = 38, DQM1 = 31
4263 11:08:38.042814 DQ Delay:
4264 11:08:38.046297 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4265 11:08:38.046424 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4266 11:08:38.049504 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4267 11:08:38.056629 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4268 11:08:38.056711
4269 11:08:38.056775
4270 11:08:38.056835 ==
4271 11:08:38.059469 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 11:08:38.063466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 11:08:38.063547 ==
4274 11:08:38.063611
4275 11:08:38.063671
4276 11:08:38.065953 TX Vref Scan disable
4277 11:08:38.066034 == TX Byte 0 ==
4278 11:08:38.072563 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4279 11:08:38.076141 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4280 11:08:38.076222 == TX Byte 1 ==
4281 11:08:38.083046 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4282 11:08:38.086474 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4283 11:08:38.086577 ==
4284 11:08:38.089624 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 11:08:38.093190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 11:08:38.093271 ==
4287 11:08:38.093335
4288 11:08:38.093395
4289 11:08:38.096387 TX Vref Scan disable
4290 11:08:38.100046 == TX Byte 0 ==
4291 11:08:38.102898 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4292 11:08:38.106604 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4293 11:08:38.109596 == TX Byte 1 ==
4294 11:08:38.112716 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4295 11:08:38.116478 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4296 11:08:38.116558
4297 11:08:38.119531 [DATLAT]
4298 11:08:38.119611 Freq=600, CH0 RK1
4299 11:08:38.119674
4300 11:08:38.122916 DATLAT Default: 0x9
4301 11:08:38.122996 0, 0xFFFF, sum = 0
4302 11:08:38.126800 1, 0xFFFF, sum = 0
4303 11:08:38.126895 2, 0xFFFF, sum = 0
4304 11:08:38.130162 3, 0xFFFF, sum = 0
4305 11:08:38.130286 4, 0xFFFF, sum = 0
4306 11:08:38.132845 5, 0xFFFF, sum = 0
4307 11:08:38.132967 6, 0xFFFF, sum = 0
4308 11:08:38.136333 7, 0xFFFF, sum = 0
4309 11:08:38.136461 8, 0x0, sum = 1
4310 11:08:38.139726 9, 0x0, sum = 2
4311 11:08:38.139828 10, 0x0, sum = 3
4312 11:08:38.142582 11, 0x0, sum = 4
4313 11:08:38.142701 best_step = 9
4314 11:08:38.142816
4315 11:08:38.142928 ==
4316 11:08:38.146073 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 11:08:38.153831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 11:08:38.153937 ==
4319 11:08:38.154029 RX Vref Scan: 0
4320 11:08:38.154117
4321 11:08:38.156338 RX Vref 0 -> 0, step: 1
4322 11:08:38.156443
4323 11:08:38.159680 RX Delay -195 -> 252, step: 8
4324 11:08:38.162673 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4325 11:08:38.169446 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4326 11:08:38.172493 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4327 11:08:38.176011 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4328 11:08:38.179555 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4329 11:08:38.182760 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4330 11:08:38.189345 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4331 11:08:38.193019 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4332 11:08:38.196360 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4333 11:08:38.199232 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4334 11:08:38.202584 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4335 11:08:38.209665 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4336 11:08:38.212845 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4337 11:08:38.216097 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4338 11:08:38.219748 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4339 11:08:38.226005 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4340 11:08:38.226086 ==
4341 11:08:38.229549 Dram Type= 6, Freq= 0, CH_0, rank 1
4342 11:08:38.232513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 11:08:38.232598 ==
4344 11:08:38.232662 DQS Delay:
4345 11:08:38.236045 DQS0 = 0, DQS1 = 0
4346 11:08:38.236125 DQM Delay:
4347 11:08:38.239725 DQM0 = 40, DQM1 = 32
4348 11:08:38.239805 DQ Delay:
4349 11:08:38.242615 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4350 11:08:38.245907 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4351 11:08:38.249501 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4352 11:08:38.252678 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
4353 11:08:38.252758
4354 11:08:38.252821
4355 11:08:38.262646 [DQSOSCAuto] RK1, (LSB)MR18= 0x4426, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4356 11:08:38.262735 CH0 RK1: MR19=808, MR18=4426
4357 11:08:38.269647 CH0_RK1: MR19=0x808, MR18=0x4426, DQSOSC=396, MR23=63, INC=167, DEC=111
4358 11:08:38.272682 [RxdqsGatingPostProcess] freq 600
4359 11:08:38.279726 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4360 11:08:38.282916 Pre-setting of DQS Precalculation
4361 11:08:38.286534 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4362 11:08:38.286661 ==
4363 11:08:38.289379 Dram Type= 6, Freq= 0, CH_1, rank 0
4364 11:08:38.292850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 11:08:38.292972 ==
4366 11:08:38.300181 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4367 11:08:38.306340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4368 11:08:38.309342 [CA 0] Center 35 (5~66) winsize 62
4369 11:08:38.313176 [CA 1] Center 35 (5~66) winsize 62
4370 11:08:38.315951 [CA 2] Center 34 (3~65) winsize 63
4371 11:08:38.319508 [CA 3] Center 33 (3~64) winsize 62
4372 11:08:38.322689 [CA 4] Center 34 (3~65) winsize 63
4373 11:08:38.326027 [CA 5] Center 33 (3~64) winsize 62
4374 11:08:38.326148
4375 11:08:38.329241 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4376 11:08:38.329363
4377 11:08:38.332482 [CATrainingPosCal] consider 1 rank data
4378 11:08:38.336070 u2DelayCellTimex100 = 270/100 ps
4379 11:08:38.339256 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4380 11:08:38.342712 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4381 11:08:38.346349 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4382 11:08:38.349339 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4383 11:08:38.353259 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4384 11:08:38.356605 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4385 11:08:38.356686
4386 11:08:38.362977 CA PerBit enable=1, Macro0, CA PI delay=33
4387 11:08:38.363058
4388 11:08:38.366078 [CBTSetCACLKResult] CA Dly = 33
4389 11:08:38.366159 CS Dly: 4 (0~35)
4390 11:08:38.366223 ==
4391 11:08:38.369427 Dram Type= 6, Freq= 0, CH_1, rank 1
4392 11:08:38.372911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 11:08:38.373017 ==
4394 11:08:38.379934 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4395 11:08:38.385957 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4396 11:08:38.389557 [CA 0] Center 35 (5~66) winsize 62
4397 11:08:38.392696 [CA 1] Center 35 (5~66) winsize 62
4398 11:08:38.396577 [CA 2] Center 34 (4~65) winsize 62
4399 11:08:38.399868 [CA 3] Center 34 (3~65) winsize 63
4400 11:08:38.404325 [CA 4] Center 34 (3~65) winsize 63
4401 11:08:38.406476 [CA 5] Center 33 (3~64) winsize 62
4402 11:08:38.406557
4403 11:08:38.409733 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4404 11:08:38.409813
4405 11:08:38.412770 [CATrainingPosCal] consider 2 rank data
4406 11:08:38.416688 u2DelayCellTimex100 = 270/100 ps
4407 11:08:38.419299 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4408 11:08:38.423155 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4409 11:08:38.425977 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4410 11:08:38.429602 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4411 11:08:38.433308 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4412 11:08:38.436019 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4413 11:08:38.439143
4414 11:08:38.442941 CA PerBit enable=1, Macro0, CA PI delay=33
4415 11:08:38.443022
4416 11:08:38.446498 [CBTSetCACLKResult] CA Dly = 33
4417 11:08:38.446579 CS Dly: 4 (0~35)
4418 11:08:38.446644
4419 11:08:38.449588 ----->DramcWriteLeveling(PI) begin...
4420 11:08:38.449670 ==
4421 11:08:38.452761 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 11:08:38.456237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 11:08:38.459956 ==
4424 11:08:38.460036 Write leveling (Byte 0): 30 => 30
4425 11:08:38.462820 Write leveling (Byte 1): 30 => 30
4426 11:08:38.466058 DramcWriteLeveling(PI) end<-----
4427 11:08:38.466138
4428 11:08:38.466203 ==
4429 11:08:38.469666 Dram Type= 6, Freq= 0, CH_1, rank 0
4430 11:08:38.476273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 11:08:38.476353 ==
4432 11:08:38.476417 [Gating] SW mode calibration
4433 11:08:38.486098 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4434 11:08:38.489622 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4435 11:08:38.493314 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 11:08:38.499571 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4437 11:08:38.503187 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4438 11:08:38.506024 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 0)
4439 11:08:38.513014 0 9 16 | B1->B0 | 2828 2626 | 1 0 | (1 0) (1 0)
4440 11:08:38.516192 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 11:08:38.519502 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 11:08:38.526055 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 11:08:38.529340 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 11:08:38.532618 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 11:08:38.539435 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 11:08:38.542654 0 10 12 | B1->B0 | 2929 2626 | 0 0 | (0 0) (0 0)
4447 11:08:38.546545 0 10 16 | B1->B0 | 3b3b 4141 | 0 0 | (0 0) (0 0)
4448 11:08:38.553317 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 11:08:38.556105 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 11:08:38.559286 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 11:08:38.566087 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 11:08:38.569571 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 11:08:38.572822 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 11:08:38.579339 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4455 11:08:38.582862 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4456 11:08:38.586154 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 11:08:38.589496 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 11:08:38.595820 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 11:08:38.599382 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 11:08:38.602541 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 11:08:38.609464 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 11:08:38.612410 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 11:08:38.616159 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 11:08:38.622649 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 11:08:38.625791 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 11:08:38.629875 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 11:08:38.636244 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 11:08:38.639064 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 11:08:38.642382 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 11:08:38.649311 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 11:08:38.652362 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 11:08:38.655625 Total UI for P1: 0, mck2ui 16
4473 11:08:38.658879 best dqsien dly found for B0: ( 0, 13, 14)
4474 11:08:38.662414 Total UI for P1: 0, mck2ui 16
4475 11:08:38.665671 best dqsien dly found for B1: ( 0, 13, 14)
4476 11:08:38.668858 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4477 11:08:38.672701 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4478 11:08:38.672782
4479 11:08:38.675861 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4480 11:08:38.678912 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4481 11:08:38.682419 [Gating] SW calibration Done
4482 11:08:38.682514 ==
4483 11:08:38.686067 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 11:08:38.689025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 11:08:38.692531 ==
4486 11:08:38.692612 RX Vref Scan: 0
4487 11:08:38.692677
4488 11:08:38.695665 RX Vref 0 -> 0, step: 1
4489 11:08:38.695746
4490 11:08:38.699253 RX Delay -230 -> 252, step: 16
4491 11:08:38.702727 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4492 11:08:38.705998 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4493 11:08:38.709025 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4494 11:08:38.713124 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4495 11:08:38.719438 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4496 11:08:38.722631 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4497 11:08:38.725723 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4498 11:08:38.729238 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4499 11:08:38.732855 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4500 11:08:38.739610 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4501 11:08:38.742287 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4502 11:08:38.745943 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4503 11:08:38.749066 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4504 11:08:38.756110 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4505 11:08:38.759634 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4506 11:08:38.762744 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4507 11:08:38.762868 ==
4508 11:08:38.765891 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 11:08:38.769573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 11:08:38.772629 ==
4511 11:08:38.772751 DQS Delay:
4512 11:08:38.772862 DQS0 = 0, DQS1 = 0
4513 11:08:38.775787 DQM Delay:
4514 11:08:38.775908 DQM0 = 43, DQM1 = 34
4515 11:08:38.779406 DQ Delay:
4516 11:08:38.779527 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4517 11:08:38.782647 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4518 11:08:38.785873 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4519 11:08:38.789474 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4520 11:08:38.789595
4521 11:08:38.789706
4522 11:08:38.792782 ==
4523 11:08:38.796101 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 11:08:38.799710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 11:08:38.799830 ==
4526 11:08:38.799943
4527 11:08:38.800051
4528 11:08:38.802676 TX Vref Scan disable
4529 11:08:38.802795 == TX Byte 0 ==
4530 11:08:38.805826 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4531 11:08:38.812608 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4532 11:08:38.812731 == TX Byte 1 ==
4533 11:08:38.820016 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4534 11:08:38.822661 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4535 11:08:38.822782 ==
4536 11:08:38.826030 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 11:08:38.829713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 11:08:38.829834 ==
4539 11:08:38.829947
4540 11:08:38.830055
4541 11:08:38.832425 TX Vref Scan disable
4542 11:08:38.835988 == TX Byte 0 ==
4543 11:08:38.839645 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4544 11:08:38.842744 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4545 11:08:38.846043 == TX Byte 1 ==
4546 11:08:38.849919 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4547 11:08:38.852655 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4548 11:08:38.852778
4549 11:08:38.856798 [DATLAT]
4550 11:08:38.856916 Freq=600, CH1 RK0
4551 11:08:38.857029
4552 11:08:38.859532 DATLAT Default: 0x9
4553 11:08:38.859649 0, 0xFFFF, sum = 0
4554 11:08:38.862762 1, 0xFFFF, sum = 0
4555 11:08:38.862885 2, 0xFFFF, sum = 0
4556 11:08:38.866214 3, 0xFFFF, sum = 0
4557 11:08:38.866333 4, 0xFFFF, sum = 0
4558 11:08:38.869313 5, 0xFFFF, sum = 0
4559 11:08:38.869436 6, 0xFFFF, sum = 0
4560 11:08:38.872881 7, 0xFFFF, sum = 0
4561 11:08:38.873003 8, 0x0, sum = 1
4562 11:08:38.875971 9, 0x0, sum = 2
4563 11:08:38.876094 10, 0x0, sum = 3
4564 11:08:38.879458 11, 0x0, sum = 4
4565 11:08:38.879582 best_step = 9
4566 11:08:38.879690
4567 11:08:38.879800 ==
4568 11:08:38.882716 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 11:08:38.886492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 11:08:38.886615 ==
4571 11:08:38.889299 RX Vref Scan: 1
4572 11:08:38.889417
4573 11:08:38.893011 RX Vref 0 -> 0, step: 1
4574 11:08:38.893131
4575 11:08:38.893241 RX Delay -195 -> 252, step: 8
4576 11:08:38.893347
4577 11:08:38.896074 Set Vref, RX VrefLevel [Byte0]: 59
4578 11:08:38.899504 [Byte1]: 52
4579 11:08:38.904288
4580 11:08:38.904368 Final RX Vref Byte 0 = 59 to rank0
4581 11:08:38.907223 Final RX Vref Byte 1 = 52 to rank0
4582 11:08:38.910727 Final RX Vref Byte 0 = 59 to rank1
4583 11:08:38.913943 Final RX Vref Byte 1 = 52 to rank1==
4584 11:08:38.917850 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 11:08:38.924316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 11:08:38.924397 ==
4587 11:08:38.924462 DQS Delay:
4588 11:08:38.924522 DQS0 = 0, DQS1 = 0
4589 11:08:38.927515 DQM Delay:
4590 11:08:38.927595 DQM0 = 40, DQM1 = 33
4591 11:08:38.931261 DQ Delay:
4592 11:08:38.934609 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4593 11:08:38.934691 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4594 11:08:38.937730 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4595 11:08:38.941135 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4596 11:08:38.943936
4597 11:08:38.944016
4598 11:08:38.951118 [DQSOSCAuto] RK0, (LSB)MR18= 0x440a, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 396 ps
4599 11:08:38.954463 CH1 RK0: MR19=808, MR18=440A
4600 11:08:38.961109 CH1_RK0: MR19=0x808, MR18=0x440A, DQSOSC=396, MR23=63, INC=167, DEC=111
4601 11:08:38.961190
4602 11:08:38.964086 ----->DramcWriteLeveling(PI) begin...
4603 11:08:38.964168 ==
4604 11:08:38.967392 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 11:08:38.970861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 11:08:38.970942 ==
4607 11:08:38.974232 Write leveling (Byte 0): 30 => 30
4608 11:08:38.977280 Write leveling (Byte 1): 29 => 29
4609 11:08:38.980725 DramcWriteLeveling(PI) end<-----
4610 11:08:38.980806
4611 11:08:38.980870 ==
4612 11:08:38.984317 Dram Type= 6, Freq= 0, CH_1, rank 1
4613 11:08:38.987733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 11:08:38.987814 ==
4615 11:08:38.990804 [Gating] SW mode calibration
4616 11:08:38.997537 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4617 11:08:39.004225 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4618 11:08:39.007394 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4619 11:08:39.011460 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4620 11:08:39.017361 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4621 11:08:39.021240 0 9 12 | B1->B0 | 3232 2e2e | 0 1 | (0 0) (0 0)
4622 11:08:39.024269 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4623 11:08:39.031216 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 11:08:39.034288 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 11:08:39.038554 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 11:08:39.044227 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 11:08:39.048270 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4628 11:08:39.050961 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 11:08:39.054238 0 10 12 | B1->B0 | 3232 4242 | 0 0 | (0 0) (0 0)
4630 11:08:39.061069 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4631 11:08:39.064682 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 11:08:39.067970 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 11:08:39.074208 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 11:08:39.077655 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 11:08:39.081283 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 11:08:39.088112 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 11:08:39.090920 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4638 11:08:39.094427 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 11:08:39.101193 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 11:08:39.104304 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 11:08:39.107425 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 11:08:39.114488 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 11:08:39.117639 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 11:08:39.121351 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 11:08:39.127806 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 11:08:39.131406 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 11:08:39.134317 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 11:08:39.138216 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 11:08:39.145458 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 11:08:39.148109 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 11:08:39.151292 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 11:08:39.157953 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 11:08:39.161078 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4654 11:08:39.164430 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 11:08:39.168870 Total UI for P1: 0, mck2ui 16
4656 11:08:39.171262 best dqsien dly found for B0: ( 0, 13, 12)
4657 11:08:39.174184 Total UI for P1: 0, mck2ui 16
4658 11:08:39.177799 best dqsien dly found for B1: ( 0, 13, 14)
4659 11:08:39.181190 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4660 11:08:39.184319 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4661 11:08:39.187630
4662 11:08:39.191206 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4663 11:08:39.194441 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4664 11:08:39.197855 [Gating] SW calibration Done
4665 11:08:39.197935 ==
4666 11:08:39.201053 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 11:08:39.204312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 11:08:39.204393 ==
4669 11:08:39.204457 RX Vref Scan: 0
4670 11:08:39.207517
4671 11:08:39.207596 RX Vref 0 -> 0, step: 1
4672 11:08:39.207660
4673 11:08:39.210725 RX Delay -230 -> 252, step: 16
4674 11:08:39.214496 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4675 11:08:39.220994 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4676 11:08:39.224095 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4677 11:08:39.228065 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4678 11:08:39.230715 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4679 11:08:39.234083 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4680 11:08:39.240801 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4681 11:08:39.243947 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4682 11:08:39.247169 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4683 11:08:39.250713 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4684 11:08:39.257603 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4685 11:08:39.260845 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4686 11:08:39.264237 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4687 11:08:39.267415 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4688 11:08:39.270976 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4689 11:08:39.277522 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4690 11:08:39.277603 ==
4691 11:08:39.280854 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 11:08:39.284451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 11:08:39.284579 ==
4694 11:08:39.284663 DQS Delay:
4695 11:08:39.287329 DQS0 = 0, DQS1 = 0
4696 11:08:39.287417 DQM Delay:
4697 11:08:39.291226 DQM0 = 41, DQM1 = 35
4698 11:08:39.291306 DQ Delay:
4699 11:08:39.293911 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4700 11:08:39.297501 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4701 11:08:39.301434 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4702 11:08:39.304108 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4703 11:08:39.304188
4704 11:08:39.304252
4705 11:08:39.304311 ==
4706 11:08:39.307253 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 11:08:39.310971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 11:08:39.311078 ==
4709 11:08:39.314438
4710 11:08:39.314535
4711 11:08:39.314623 TX Vref Scan disable
4712 11:08:39.317545 == TX Byte 0 ==
4713 11:08:39.321104 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4714 11:08:39.324277 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4715 11:08:39.328051 == TX Byte 1 ==
4716 11:08:39.331017 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4717 11:08:39.333842 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4718 11:08:39.337578 ==
4719 11:08:39.337659 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 11:08:39.344602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 11:08:39.344684 ==
4722 11:08:39.344748
4723 11:08:39.344808
4724 11:08:39.344865 TX Vref Scan disable
4725 11:08:39.348852 == TX Byte 0 ==
4726 11:08:39.352509 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4727 11:08:39.356131 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4728 11:08:39.358649 == TX Byte 1 ==
4729 11:08:39.361984 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4730 11:08:39.365738 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4731 11:08:39.369220
4732 11:08:39.369300 [DATLAT]
4733 11:08:39.369365 Freq=600, CH1 RK1
4734 11:08:39.369427
4735 11:08:39.372587 DATLAT Default: 0x9
4736 11:08:39.372668 0, 0xFFFF, sum = 0
4737 11:08:39.375698 1, 0xFFFF, sum = 0
4738 11:08:39.375781 2, 0xFFFF, sum = 0
4739 11:08:39.378868 3, 0xFFFF, sum = 0
4740 11:08:39.378950 4, 0xFFFF, sum = 0
4741 11:08:39.382401 5, 0xFFFF, sum = 0
4742 11:08:39.382519 6, 0xFFFF, sum = 0
4743 11:08:39.385562 7, 0xFFFF, sum = 0
4744 11:08:39.385644 8, 0x0, sum = 1
4745 11:08:39.388983 9, 0x0, sum = 2
4746 11:08:39.389092 10, 0x0, sum = 3
4747 11:08:39.392343 11, 0x0, sum = 4
4748 11:08:39.392444 best_step = 9
4749 11:08:39.392534
4750 11:08:39.392621 ==
4751 11:08:39.395937 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 11:08:39.399899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 11:08:39.402258 ==
4754 11:08:39.402340 RX Vref Scan: 0
4755 11:08:39.402427
4756 11:08:39.406192 RX Vref 0 -> 0, step: 1
4757 11:08:39.406273
4758 11:08:39.409032 RX Delay -195 -> 252, step: 8
4759 11:08:39.412159 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4760 11:08:39.415711 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4761 11:08:39.422543 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4762 11:08:39.425455 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4763 11:08:39.429044 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4764 11:08:39.432445 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4765 11:08:39.438882 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4766 11:08:39.442087 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4767 11:08:39.445579 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4768 11:08:39.448938 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4769 11:08:39.452034 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4770 11:08:39.459063 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4771 11:08:39.462672 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4772 11:08:39.465607 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4773 11:08:39.468829 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4774 11:08:39.475660 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4775 11:08:39.475742 ==
4776 11:08:39.478904 Dram Type= 6, Freq= 0, CH_1, rank 1
4777 11:08:39.482361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4778 11:08:39.482464 ==
4779 11:08:39.482530 DQS Delay:
4780 11:08:39.485729 DQS0 = 0, DQS1 = 0
4781 11:08:39.485810 DQM Delay:
4782 11:08:39.488908 DQM0 = 38, DQM1 = 33
4783 11:08:39.489032 DQ Delay:
4784 11:08:39.492053 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4785 11:08:39.495845 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4786 11:08:39.499105 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4787 11:08:39.501954 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4788 11:08:39.502074
4789 11:08:39.502185
4790 11:08:39.509034 [DQSOSCAuto] RK1, (LSB)MR18= 0x303e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 400 ps
4791 11:08:39.512293 CH1 RK1: MR19=808, MR18=303E
4792 11:08:39.518660 CH1_RK1: MR19=0x808, MR18=0x303E, DQSOSC=398, MR23=63, INC=165, DEC=110
4793 11:08:39.522284 [RxdqsGatingPostProcess] freq 600
4794 11:08:39.528684 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4795 11:08:39.532006 Pre-setting of DQS Precalculation
4796 11:08:39.535667 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4797 11:08:39.542248 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4798 11:08:39.548798 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4799 11:08:39.548882
4800 11:08:39.548946
4801 11:08:39.552117 [Calibration Summary] 1200 Mbps
4802 11:08:39.555605 CH 0, Rank 0
4803 11:08:39.555686 SW Impedance : PASS
4804 11:08:39.559114 DUTY Scan : NO K
4805 11:08:39.561991 ZQ Calibration : PASS
4806 11:08:39.562072 Jitter Meter : NO K
4807 11:08:39.565353 CBT Training : PASS
4808 11:08:39.569169 Write leveling : PASS
4809 11:08:39.569251 RX DQS gating : PASS
4810 11:08:39.572413 RX DQ/DQS(RDDQC) : PASS
4811 11:08:39.572494 TX DQ/DQS : PASS
4812 11:08:39.576035 RX DATLAT : PASS
4813 11:08:39.578710 RX DQ/DQS(Engine): PASS
4814 11:08:39.578791 TX OE : NO K
4815 11:08:39.582370 All Pass.
4816 11:08:39.582473
4817 11:08:39.582538 CH 0, Rank 1
4818 11:08:39.585312 SW Impedance : PASS
4819 11:08:39.585393 DUTY Scan : NO K
4820 11:08:39.588925 ZQ Calibration : PASS
4821 11:08:39.592203 Jitter Meter : NO K
4822 11:08:39.592284 CBT Training : PASS
4823 11:08:39.595866 Write leveling : PASS
4824 11:08:39.598656 RX DQS gating : PASS
4825 11:08:39.598737 RX DQ/DQS(RDDQC) : PASS
4826 11:08:39.602276 TX DQ/DQS : PASS
4827 11:08:39.605495 RX DATLAT : PASS
4828 11:08:39.605576 RX DQ/DQS(Engine): PASS
4829 11:08:39.608700 TX OE : NO K
4830 11:08:39.608781 All Pass.
4831 11:08:39.608847
4832 11:08:39.611857 CH 1, Rank 0
4833 11:08:39.611938 SW Impedance : PASS
4834 11:08:39.616015 DUTY Scan : NO K
4835 11:08:39.618686 ZQ Calibration : PASS
4836 11:08:39.618768 Jitter Meter : NO K
4837 11:08:39.622138 CBT Training : PASS
4838 11:08:39.622219 Write leveling : PASS
4839 11:08:39.625453 RX DQS gating : PASS
4840 11:08:39.628803 RX DQ/DQS(RDDQC) : PASS
4841 11:08:39.628885 TX DQ/DQS : PASS
4842 11:08:39.631955 RX DATLAT : PASS
4843 11:08:39.635271 RX DQ/DQS(Engine): PASS
4844 11:08:39.635353 TX OE : NO K
4845 11:08:39.638664 All Pass.
4846 11:08:39.638770
4847 11:08:39.638863 CH 1, Rank 1
4848 11:08:39.642000 SW Impedance : PASS
4849 11:08:39.642081 DUTY Scan : NO K
4850 11:08:39.645258 ZQ Calibration : PASS
4851 11:08:39.648664 Jitter Meter : NO K
4852 11:08:39.648746 CBT Training : PASS
4853 11:08:39.652073 Write leveling : PASS
4854 11:08:39.655396 RX DQS gating : PASS
4855 11:08:39.655478 RX DQ/DQS(RDDQC) : PASS
4856 11:08:39.658569 TX DQ/DQS : PASS
4857 11:08:39.662170 RX DATLAT : PASS
4858 11:08:39.662251 RX DQ/DQS(Engine): PASS
4859 11:08:39.665196 TX OE : NO K
4860 11:08:39.665278 All Pass.
4861 11:08:39.665343
4862 11:08:39.668699 DramC Write-DBI off
4863 11:08:39.672377 PER_BANK_REFRESH: Hybrid Mode
4864 11:08:39.672458 TX_TRACKING: ON
4865 11:08:39.682449 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4866 11:08:39.685456 [FAST_K] Save calibration result to emmc
4867 11:08:39.688956 dramc_set_vcore_voltage set vcore to 662500
4868 11:08:39.689038 Read voltage for 933, 3
4869 11:08:39.692649 Vio18 = 0
4870 11:08:39.692731 Vcore = 662500
4871 11:08:39.692796 Vdram = 0
4872 11:08:39.695721 Vddq = 0
4873 11:08:39.695802 Vmddr = 0
4874 11:08:39.698747 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4875 11:08:39.705689 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4876 11:08:39.708684 MEM_TYPE=3, freq_sel=17
4877 11:08:39.712389 sv_algorithm_assistance_LP4_1600
4878 11:08:39.715818 ============ PULL DRAM RESETB DOWN ============
4879 11:08:39.718741 ========== PULL DRAM RESETB DOWN end =========
4880 11:08:39.725733 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4881 11:08:39.729151 ===================================
4882 11:08:39.729232 LPDDR4 DRAM CONFIGURATION
4883 11:08:39.732310 ===================================
4884 11:08:39.735842 EX_ROW_EN[0] = 0x0
4885 11:08:39.735923 EX_ROW_EN[1] = 0x0
4886 11:08:39.739012 LP4Y_EN = 0x0
4887 11:08:39.739094 WORK_FSP = 0x0
4888 11:08:39.742240 WL = 0x3
4889 11:08:39.742320 RL = 0x3
4890 11:08:39.746331 BL = 0x2
4891 11:08:39.746475 RPST = 0x0
4892 11:08:39.749150 RD_PRE = 0x0
4893 11:08:39.749234 WR_PRE = 0x1
4894 11:08:39.752334 WR_PST = 0x0
4895 11:08:39.755494 DBI_WR = 0x0
4896 11:08:39.755574 DBI_RD = 0x0
4897 11:08:39.758934 OTF = 0x1
4898 11:08:39.762143 ===================================
4899 11:08:39.765741 ===================================
4900 11:08:39.765822 ANA top config
4901 11:08:39.768838 ===================================
4902 11:08:39.772082 DLL_ASYNC_EN = 0
4903 11:08:39.772162 ALL_SLAVE_EN = 1
4904 11:08:39.776054 NEW_RANK_MODE = 1
4905 11:08:39.778959 DLL_IDLE_MODE = 1
4906 11:08:39.782418 LP45_APHY_COMB_EN = 1
4907 11:08:39.786154 TX_ODT_DIS = 1
4908 11:08:39.786267 NEW_8X_MODE = 1
4909 11:08:39.788794 ===================================
4910 11:08:39.793246 ===================================
4911 11:08:39.796089 data_rate = 1866
4912 11:08:39.798846 CKR = 1
4913 11:08:39.802424 DQ_P2S_RATIO = 8
4914 11:08:39.806198 ===================================
4915 11:08:39.809042 CA_P2S_RATIO = 8
4916 11:08:39.812152 DQ_CA_OPEN = 0
4917 11:08:39.812234 DQ_SEMI_OPEN = 0
4918 11:08:39.815518 CA_SEMI_OPEN = 0
4919 11:08:39.819191 CA_FULL_RATE = 0
4920 11:08:39.822050 DQ_CKDIV4_EN = 1
4921 11:08:39.825795 CA_CKDIV4_EN = 1
4922 11:08:39.825876 CA_PREDIV_EN = 0
4923 11:08:39.828881 PH8_DLY = 0
4924 11:08:39.832800 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4925 11:08:39.835556 DQ_AAMCK_DIV = 4
4926 11:08:39.839235 CA_AAMCK_DIV = 4
4927 11:08:39.842276 CA_ADMCK_DIV = 4
4928 11:08:39.842359 DQ_TRACK_CA_EN = 0
4929 11:08:39.845570 CA_PICK = 933
4930 11:08:39.849228 CA_MCKIO = 933
4931 11:08:39.852653 MCKIO_SEMI = 0
4932 11:08:39.855714 PLL_FREQ = 3732
4933 11:08:39.859155 DQ_UI_PI_RATIO = 32
4934 11:08:39.862572 CA_UI_PI_RATIO = 0
4935 11:08:39.866156 ===================================
4936 11:08:39.869169 ===================================
4937 11:08:39.869251 memory_type:LPDDR4
4938 11:08:39.872504 GP_NUM : 10
4939 11:08:39.872585 SRAM_EN : 1
4940 11:08:39.875690 MD32_EN : 0
4941 11:08:39.878870 ===================================
4942 11:08:39.882469 [ANA_INIT] >>>>>>>>>>>>>>
4943 11:08:39.885817 <<<<<< [CONFIGURE PHASE]: ANA_TX
4944 11:08:39.889399 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4945 11:08:39.892904 ===================================
4946 11:08:39.892988 data_rate = 1866,PCW = 0X8f00
4947 11:08:39.895976 ===================================
4948 11:08:39.899427 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4949 11:08:39.906059 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4950 11:08:39.912569 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4951 11:08:39.915612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4952 11:08:39.919042 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4953 11:08:39.922756 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4954 11:08:39.925710 [ANA_INIT] flow start
4955 11:08:39.929101 [ANA_INIT] PLL >>>>>>>>
4956 11:08:39.929184 [ANA_INIT] PLL <<<<<<<<
4957 11:08:39.932597 [ANA_INIT] MIDPI >>>>>>>>
4958 11:08:39.936149 [ANA_INIT] MIDPI <<<<<<<<
4959 11:08:39.936232 [ANA_INIT] DLL >>>>>>>>
4960 11:08:39.939417 [ANA_INIT] flow end
4961 11:08:39.942574 ============ LP4 DIFF to SE enter ============
4962 11:08:39.946054 ============ LP4 DIFF to SE exit ============
4963 11:08:39.949447 [ANA_INIT] <<<<<<<<<<<<<
4964 11:08:39.952556 [Flow] Enable top DCM control >>>>>
4965 11:08:39.955849 [Flow] Enable top DCM control <<<<<
4966 11:08:39.959560 Enable DLL master slave shuffle
4967 11:08:39.965921 ==============================================================
4968 11:08:39.966005 Gating Mode config
4969 11:08:39.972741 ==============================================================
4970 11:08:39.972825 Config description:
4971 11:08:39.982351 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4972 11:08:39.989450 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4973 11:08:39.995926 SELPH_MODE 0: By rank 1: By Phase
4974 11:08:39.998939 ==============================================================
4975 11:08:40.002710 GAT_TRACK_EN = 1
4976 11:08:40.005854 RX_GATING_MODE = 2
4977 11:08:40.009369 RX_GATING_TRACK_MODE = 2
4978 11:08:40.012818 SELPH_MODE = 1
4979 11:08:40.016797 PICG_EARLY_EN = 1
4980 11:08:40.019237 VALID_LAT_VALUE = 1
4981 11:08:40.022393 ==============================================================
4982 11:08:40.026516 Enter into Gating configuration >>>>
4983 11:08:40.029225 Exit from Gating configuration <<<<
4984 11:08:40.032791 Enter into DVFS_PRE_config >>>>>
4985 11:08:40.045782 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4986 11:08:40.049823 Exit from DVFS_PRE_config <<<<<
4987 11:08:40.049905 Enter into PICG configuration >>>>
4988 11:08:40.052686 Exit from PICG configuration <<<<
4989 11:08:40.056087 [RX_INPUT] configuration >>>>>
4990 11:08:40.059325 [RX_INPUT] configuration <<<<<
4991 11:08:40.065682 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4992 11:08:40.069462 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4993 11:08:40.076149 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4994 11:08:40.082561 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4995 11:08:40.089427 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4996 11:08:40.095633 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4997 11:08:40.099054 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4998 11:08:40.102567 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4999 11:08:40.106240 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5000 11:08:40.112568 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5001 11:08:40.115802 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5002 11:08:40.119062 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5003 11:08:40.122233 ===================================
5004 11:08:40.126312 LPDDR4 DRAM CONFIGURATION
5005 11:08:40.129339 ===================================
5006 11:08:40.129420 EX_ROW_EN[0] = 0x0
5007 11:08:40.132782 EX_ROW_EN[1] = 0x0
5008 11:08:40.135799 LP4Y_EN = 0x0
5009 11:08:40.135881 WORK_FSP = 0x0
5010 11:08:40.139190 WL = 0x3
5011 11:08:40.139272 RL = 0x3
5012 11:08:40.142631 BL = 0x2
5013 11:08:40.142713 RPST = 0x0
5014 11:08:40.146175 RD_PRE = 0x0
5015 11:08:40.146257 WR_PRE = 0x1
5016 11:08:40.149613 WR_PST = 0x0
5017 11:08:40.149694 DBI_WR = 0x0
5018 11:08:40.152894 DBI_RD = 0x0
5019 11:08:40.152974 OTF = 0x1
5020 11:08:40.156828 ===================================
5021 11:08:40.159099 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5022 11:08:40.165811 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5023 11:08:40.169122 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5024 11:08:40.172381 ===================================
5025 11:08:40.175787 LPDDR4 DRAM CONFIGURATION
5026 11:08:40.179162 ===================================
5027 11:08:40.179245 EX_ROW_EN[0] = 0x10
5028 11:08:40.182568 EX_ROW_EN[1] = 0x0
5029 11:08:40.182649 LP4Y_EN = 0x0
5030 11:08:40.185912 WORK_FSP = 0x0
5031 11:08:40.185994 WL = 0x3
5032 11:08:40.189101 RL = 0x3
5033 11:08:40.192842 BL = 0x2
5034 11:08:40.192923 RPST = 0x0
5035 11:08:40.196269 RD_PRE = 0x0
5036 11:08:40.196350 WR_PRE = 0x1
5037 11:08:40.198870 WR_PST = 0x0
5038 11:08:40.198952 DBI_WR = 0x0
5039 11:08:40.202782 DBI_RD = 0x0
5040 11:08:40.202863 OTF = 0x1
5041 11:08:40.205497 ===================================
5042 11:08:40.212469 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5043 11:08:40.216867 nWR fixed to 30
5044 11:08:40.219813 [ModeRegInit_LP4] CH0 RK0
5045 11:08:40.219895 [ModeRegInit_LP4] CH0 RK1
5046 11:08:40.222938 [ModeRegInit_LP4] CH1 RK0
5047 11:08:40.226887 [ModeRegInit_LP4] CH1 RK1
5048 11:08:40.226968 match AC timing 9
5049 11:08:40.233281 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5050 11:08:40.236525 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5051 11:08:40.239599 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5052 11:08:40.246346 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5053 11:08:40.249764 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5054 11:08:40.249846 ==
5055 11:08:40.253715 Dram Type= 6, Freq= 0, CH_0, rank 0
5056 11:08:40.256653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5057 11:08:40.256735 ==
5058 11:08:40.263045 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5059 11:08:40.270095 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5060 11:08:40.273175 [CA 0] Center 38 (8~69) winsize 62
5061 11:08:40.276546 [CA 1] Center 38 (8~69) winsize 62
5062 11:08:40.279898 [CA 2] Center 35 (5~66) winsize 62
5063 11:08:40.283198 [CA 3] Center 35 (4~66) winsize 63
5064 11:08:40.286788 [CA 4] Center 34 (4~64) winsize 61
5065 11:08:40.289856 [CA 5] Center 33 (3~64) winsize 62
5066 11:08:40.289938
5067 11:08:40.293328 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5068 11:08:40.293410
5069 11:08:40.296688 [CATrainingPosCal] consider 1 rank data
5070 11:08:40.299875 u2DelayCellTimex100 = 270/100 ps
5071 11:08:40.303785 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5072 11:08:40.306852 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5073 11:08:40.310389 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5074 11:08:40.313423 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5075 11:08:40.316680 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5076 11:08:40.320307 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5077 11:08:40.320467
5078 11:08:40.323298 CA PerBit enable=1, Macro0, CA PI delay=33
5079 11:08:40.326644
5080 11:08:40.326733 [CBTSetCACLKResult] CA Dly = 33
5081 11:08:40.330303 CS Dly: 6 (0~37)
5082 11:08:40.330405 ==
5083 11:08:40.333689 Dram Type= 6, Freq= 0, CH_0, rank 1
5084 11:08:40.336538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5085 11:08:40.336620 ==
5086 11:08:40.343232 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5087 11:08:40.350288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5088 11:08:40.353392 [CA 0] Center 38 (8~69) winsize 62
5089 11:08:40.356536 [CA 1] Center 38 (8~69) winsize 62
5090 11:08:40.360261 [CA 2] Center 35 (5~66) winsize 62
5091 11:08:40.363262 [CA 3] Center 35 (5~66) winsize 62
5092 11:08:40.366352 [CA 4] Center 34 (4~64) winsize 61
5093 11:08:40.370083 [CA 5] Center 33 (3~64) winsize 62
5094 11:08:40.370163
5095 11:08:40.373565 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5096 11:08:40.373670
5097 11:08:40.376718 [CATrainingPosCal] consider 2 rank data
5098 11:08:40.380443 u2DelayCellTimex100 = 270/100 ps
5099 11:08:40.383355 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5100 11:08:40.386315 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5101 11:08:40.389823 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5102 11:08:40.393821 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5103 11:08:40.396455 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5104 11:08:40.399945 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5105 11:08:40.400063
5106 11:08:40.406657 CA PerBit enable=1, Macro0, CA PI delay=33
5107 11:08:40.406737
5108 11:08:40.406801 [CBTSetCACLKResult] CA Dly = 33
5109 11:08:40.409694 CS Dly: 7 (0~39)
5110 11:08:40.409785
5111 11:08:40.413307 ----->DramcWriteLeveling(PI) begin...
5112 11:08:40.413389 ==
5113 11:08:40.416624 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 11:08:40.419895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 11:08:40.419977 ==
5116 11:08:40.423658 Write leveling (Byte 0): 29 => 29
5117 11:08:40.426687 Write leveling (Byte 1): 27 => 27
5118 11:08:40.430225 DramcWriteLeveling(PI) end<-----
5119 11:08:40.430304
5120 11:08:40.430367 ==
5121 11:08:40.433479 Dram Type= 6, Freq= 0, CH_0, rank 0
5122 11:08:40.436622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 11:08:40.439656 ==
5124 11:08:40.439736 [Gating] SW mode calibration
5125 11:08:40.446791 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5126 11:08:40.453545 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5127 11:08:40.456585 0 14 0 | B1->B0 | 2322 2929 | 1 1 | (0 0) (1 1)
5128 11:08:40.463625 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5129 11:08:40.466501 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 11:08:40.470201 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 11:08:40.476610 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 11:08:40.480095 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 11:08:40.482979 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 11:08:40.490069 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5135 11:08:40.493250 0 15 0 | B1->B0 | 3030 2727 | 0 0 | (0 1) (0 0)
5136 11:08:40.496978 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5137 11:08:40.500182 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 11:08:40.506630 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 11:08:40.510049 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 11:08:40.513056 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 11:08:40.519799 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 11:08:40.523324 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5143 11:08:40.526741 1 0 0 | B1->B0 | 3232 3f3f | 0 0 | (1 1) (0 0)
5144 11:08:40.534014 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5145 11:08:40.536910 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 11:08:40.540129 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 11:08:40.546921 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 11:08:40.550234 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 11:08:40.553213 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 11:08:40.560033 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5151 11:08:40.563763 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5152 11:08:40.567173 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5153 11:08:40.570301 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 11:08:40.576461 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 11:08:40.580339 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 11:08:40.583293 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 11:08:40.589912 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 11:08:40.593391 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 11:08:40.596718 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 11:08:40.603765 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 11:08:40.606834 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 11:08:40.610136 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 11:08:40.616617 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 11:08:40.620156 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 11:08:40.623350 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 11:08:40.630194 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5167 11:08:40.634052 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5168 11:08:40.637382 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 11:08:40.639976 Total UI for P1: 0, mck2ui 16
5170 11:08:40.643949 best dqsien dly found for B0: ( 1, 2, 30)
5171 11:08:40.646552 Total UI for P1: 0, mck2ui 16
5172 11:08:40.650082 best dqsien dly found for B1: ( 1, 2, 30)
5173 11:08:40.653259 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5174 11:08:40.656946 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5175 11:08:40.657051
5176 11:08:40.660425 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5177 11:08:40.667337 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5178 11:08:40.667417 [Gating] SW calibration Done
5179 11:08:40.667481 ==
5180 11:08:40.670347 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 11:08:40.676836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 11:08:40.676917 ==
5183 11:08:40.676982 RX Vref Scan: 0
5184 11:08:40.677042
5185 11:08:40.679931 RX Vref 0 -> 0, step: 1
5186 11:08:40.680010
5187 11:08:40.683683 RX Delay -80 -> 252, step: 8
5188 11:08:40.686735 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5189 11:08:40.689850 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5190 11:08:40.694022 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5191 11:08:40.696579 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5192 11:08:40.703844 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5193 11:08:40.706735 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5194 11:08:40.710232 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5195 11:08:40.713515 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5196 11:08:40.717021 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5197 11:08:40.720678 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5198 11:08:40.726776 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5199 11:08:40.730044 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5200 11:08:40.733763 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5201 11:08:40.736659 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5202 11:08:40.740218 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5203 11:08:40.746952 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5204 11:08:40.747033 ==
5205 11:08:40.749812 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 11:08:40.753321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 11:08:40.753404 ==
5208 11:08:40.753468 DQS Delay:
5209 11:08:40.756717 DQS0 = 0, DQS1 = 0
5210 11:08:40.756822 DQM Delay:
5211 11:08:40.759969 DQM0 = 98, DQM1 = 88
5212 11:08:40.760049 DQ Delay:
5213 11:08:40.763415 DQ0 =99, DQ1 =103, DQ2 =91, DQ3 =91
5214 11:08:40.767176 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5215 11:08:40.770304 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5216 11:08:40.773976 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5217 11:08:40.774049
5218 11:08:40.774111
5219 11:08:40.774170 ==
5220 11:08:40.776850 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 11:08:40.780230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 11:08:40.780319 ==
5223 11:08:40.780383
5224 11:08:40.783501
5225 11:08:40.783581 TX Vref Scan disable
5226 11:08:40.786578 == TX Byte 0 ==
5227 11:08:40.789954 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5228 11:08:40.793697 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5229 11:08:40.796545 == TX Byte 1 ==
5230 11:08:40.799969 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5231 11:08:40.803193 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5232 11:08:40.803273 ==
5233 11:08:40.806432 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 11:08:40.813269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 11:08:40.813350 ==
5236 11:08:40.813415
5237 11:08:40.813479
5238 11:08:40.813538 TX Vref Scan disable
5239 11:08:40.817310 == TX Byte 0 ==
5240 11:08:40.821102 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5241 11:08:40.827701 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5242 11:08:40.827780 == TX Byte 1 ==
5243 11:08:40.830647 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5244 11:08:40.834277 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5245 11:08:40.837222
5246 11:08:40.837290 [DATLAT]
5247 11:08:40.837350 Freq=933, CH0 RK0
5248 11:08:40.837406
5249 11:08:40.840685 DATLAT Default: 0xd
5250 11:08:40.840764 0, 0xFFFF, sum = 0
5251 11:08:40.844745 1, 0xFFFF, sum = 0
5252 11:08:40.844826 2, 0xFFFF, sum = 0
5253 11:08:40.847466 3, 0xFFFF, sum = 0
5254 11:08:40.847548 4, 0xFFFF, sum = 0
5255 11:08:40.850825 5, 0xFFFF, sum = 0
5256 11:08:40.850907 6, 0xFFFF, sum = 0
5257 11:08:40.854208 7, 0xFFFF, sum = 0
5258 11:08:40.854290 8, 0xFFFF, sum = 0
5259 11:08:40.857645 9, 0xFFFF, sum = 0
5260 11:08:40.857726 10, 0x0, sum = 1
5261 11:08:40.860866 11, 0x0, sum = 2
5262 11:08:40.860948 12, 0x0, sum = 3
5263 11:08:40.864114 13, 0x0, sum = 4
5264 11:08:40.864197 best_step = 11
5265 11:08:40.864261
5266 11:08:40.864321 ==
5267 11:08:40.867596 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 11:08:40.874388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 11:08:40.874492 ==
5270 11:08:40.874557 RX Vref Scan: 1
5271 11:08:40.874618
5272 11:08:40.877840 RX Vref 0 -> 0, step: 1
5273 11:08:40.877920
5274 11:08:40.881330 RX Delay -61 -> 252, step: 4
5275 11:08:40.881411
5276 11:08:40.884444 Set Vref, RX VrefLevel [Byte0]: 55
5277 11:08:40.887594 [Byte1]: 51
5278 11:08:40.887675
5279 11:08:40.891284 Final RX Vref Byte 0 = 55 to rank0
5280 11:08:40.894183 Final RX Vref Byte 1 = 51 to rank0
5281 11:08:40.897617 Final RX Vref Byte 0 = 55 to rank1
5282 11:08:40.900759 Final RX Vref Byte 1 = 51 to rank1==
5283 11:08:40.904058 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 11:08:40.908034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 11:08:40.908118 ==
5286 11:08:40.911192 DQS Delay:
5287 11:08:40.911285 DQS0 = 0, DQS1 = 0
5288 11:08:40.911381 DQM Delay:
5289 11:08:40.914673 DQM0 = 96, DQM1 = 88
5290 11:08:40.914757 DQ Delay:
5291 11:08:40.917732 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5292 11:08:40.920560 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =102
5293 11:08:40.924097 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =82
5294 11:08:40.927886 DQ12 =96, DQ13 =90, DQ14 =96, DQ15 =98
5295 11:08:40.927966
5296 11:08:40.928030
5297 11:08:40.937965 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5298 11:08:40.940973 CH0 RK0: MR19=504, MR18=11FD
5299 11:08:40.944577 CH0_RK0: MR19=0x504, MR18=0x11FD, DQSOSC=416, MR23=63, INC=62, DEC=41
5300 11:08:40.944657
5301 11:08:40.948184 ----->DramcWriteLeveling(PI) begin...
5302 11:08:40.951309 ==
5303 11:08:40.951389 Dram Type= 6, Freq= 0, CH_0, rank 1
5304 11:08:40.957576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 11:08:40.957656 ==
5306 11:08:40.960705 Write leveling (Byte 0): 31 => 31
5307 11:08:40.964408 Write leveling (Byte 1): 31 => 31
5308 11:08:40.967735 DramcWriteLeveling(PI) end<-----
5309 11:08:40.967815
5310 11:08:40.967878 ==
5311 11:08:40.971189 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 11:08:40.974546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 11:08:40.974625 ==
5314 11:08:40.977539 [Gating] SW mode calibration
5315 11:08:40.984596 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5316 11:08:40.988026 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5317 11:08:40.994372 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5318 11:08:40.997689 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 11:08:41.001155 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 11:08:41.007842 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 11:08:41.011015 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 11:08:41.014504 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 11:08:41.020998 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 11:08:41.024435 0 14 28 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 1)
5325 11:08:41.027632 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5326 11:08:41.034599 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5327 11:08:41.037875 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 11:08:41.040991 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 11:08:41.047711 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 11:08:41.050945 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 11:08:41.054031 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 11:08:41.060713 0 15 28 | B1->B0 | 2727 3737 | 0 0 | (1 1) (0 0)
5333 11:08:41.064300 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5334 11:08:41.067550 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 11:08:41.074519 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 11:08:41.077405 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 11:08:41.081378 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 11:08:41.087372 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 11:08:41.091068 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5340 11:08:41.094502 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5341 11:08:41.097458 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5342 11:08:41.104209 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 11:08:41.107588 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 11:08:41.111408 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 11:08:41.117865 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 11:08:41.120647 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 11:08:41.124225 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 11:08:41.131084 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 11:08:41.134356 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 11:08:41.137667 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 11:08:41.144101 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 11:08:41.147514 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 11:08:41.150598 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 11:08:41.157494 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 11:08:41.161057 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 11:08:41.164464 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5357 11:08:41.171001 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5358 11:08:41.171081 Total UI for P1: 0, mck2ui 16
5359 11:08:41.178125 best dqsien dly found for B0: ( 1, 2, 28)
5360 11:08:41.180753 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 11:08:41.184708 Total UI for P1: 0, mck2ui 16
5362 11:08:41.187708 best dqsien dly found for B1: ( 1, 3, 0)
5363 11:08:41.190935 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5364 11:08:41.194436 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5365 11:08:41.194541
5366 11:08:41.197673 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5367 11:08:41.201287 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5368 11:08:41.204504 [Gating] SW calibration Done
5369 11:08:41.204609 ==
5370 11:08:41.207696 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 11:08:41.210737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 11:08:41.210822 ==
5373 11:08:41.214554 RX Vref Scan: 0
5374 11:08:41.214635
5375 11:08:41.214703 RX Vref 0 -> 0, step: 1
5376 11:08:41.214771
5377 11:08:41.217561 RX Delay -80 -> 252, step: 8
5378 11:08:41.223923 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5379 11:08:41.227458 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5380 11:08:41.230833 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5381 11:08:41.234043 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5382 11:08:41.237791 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5383 11:08:41.241252 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5384 11:08:41.244217 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5385 11:08:41.250717 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5386 11:08:41.254293 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5387 11:08:41.257339 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5388 11:08:41.260729 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5389 11:08:41.264342 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5390 11:08:41.270640 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5391 11:08:41.274059 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5392 11:08:41.277420 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5393 11:08:41.280812 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5394 11:08:41.280892 ==
5395 11:08:41.284283 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 11:08:41.287531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 11:08:41.287612 ==
5398 11:08:41.290637 DQS Delay:
5399 11:08:41.290718 DQS0 = 0, DQS1 = 0
5400 11:08:41.294426 DQM Delay:
5401 11:08:41.294545 DQM0 = 97, DQM1 = 87
5402 11:08:41.294637 DQ Delay:
5403 11:08:41.297634 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5404 11:08:41.300781 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5405 11:08:41.304205 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =75
5406 11:08:41.307766 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5407 11:08:41.307846
5408 11:08:41.307911
5409 11:08:41.310743 ==
5410 11:08:41.314171 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 11:08:41.317690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 11:08:41.317771 ==
5413 11:08:41.317842
5414 11:08:41.317901
5415 11:08:41.321314 TX Vref Scan disable
5416 11:08:41.321419 == TX Byte 0 ==
5417 11:08:41.324127 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5418 11:08:41.331150 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5419 11:08:41.331231 == TX Byte 1 ==
5420 11:08:41.334199 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5421 11:08:41.340640 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5422 11:08:41.340721 ==
5423 11:08:41.344508 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 11:08:41.347539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 11:08:41.347620 ==
5426 11:08:41.347684
5427 11:08:41.347743
5428 11:08:41.350725 TX Vref Scan disable
5429 11:08:41.354317 == TX Byte 0 ==
5430 11:08:41.357404 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5431 11:08:41.360604 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5432 11:08:41.363841 == TX Byte 1 ==
5433 11:08:41.367610 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5434 11:08:41.370676 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5435 11:08:41.370757
5436 11:08:41.370824 [DATLAT]
5437 11:08:41.374297 Freq=933, CH0 RK1
5438 11:08:41.374415
5439 11:08:41.377375 DATLAT Default: 0xb
5440 11:08:41.377455 0, 0xFFFF, sum = 0
5441 11:08:41.380466 1, 0xFFFF, sum = 0
5442 11:08:41.380575 2, 0xFFFF, sum = 0
5443 11:08:41.383890 3, 0xFFFF, sum = 0
5444 11:08:41.383971 4, 0xFFFF, sum = 0
5445 11:08:41.387177 5, 0xFFFF, sum = 0
5446 11:08:41.387258 6, 0xFFFF, sum = 0
5447 11:08:41.390666 7, 0xFFFF, sum = 0
5448 11:08:41.390747 8, 0xFFFF, sum = 0
5449 11:08:41.394030 9, 0xFFFF, sum = 0
5450 11:08:41.394110 10, 0x0, sum = 1
5451 11:08:41.397090 11, 0x0, sum = 2
5452 11:08:41.397170 12, 0x0, sum = 3
5453 11:08:41.400671 13, 0x0, sum = 4
5454 11:08:41.400753 best_step = 11
5455 11:08:41.400817
5456 11:08:41.400876 ==
5457 11:08:41.403633 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 11:08:41.407149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 11:08:41.407232 ==
5460 11:08:41.410560 RX Vref Scan: 0
5461 11:08:41.410639
5462 11:08:41.414194 RX Vref 0 -> 0, step: 1
5463 11:08:41.414268
5464 11:08:41.414329 RX Delay -61 -> 252, step: 4
5465 11:08:41.421826 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5466 11:08:41.425274 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5467 11:08:41.428337 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5468 11:08:41.431626 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5469 11:08:41.435273 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5470 11:08:41.438595 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5471 11:08:41.445029 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5472 11:08:41.448553 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5473 11:08:41.451700 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5474 11:08:41.455668 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5475 11:08:41.458214 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5476 11:08:41.464911 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5477 11:08:41.468289 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5478 11:08:41.471889 iDelay=199, Bit 13, Center 88 (-1 ~ 178) 180
5479 11:08:41.476089 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5480 11:08:41.478736 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5481 11:08:41.478816 ==
5482 11:08:41.481919 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 11:08:41.488621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 11:08:41.488702 ==
5485 11:08:41.488766 DQS Delay:
5486 11:08:41.488825 DQS0 = 0, DQS1 = 0
5487 11:08:41.491802 DQM Delay:
5488 11:08:41.491881 DQM0 = 95, DQM1 = 87
5489 11:08:41.495214 DQ Delay:
5490 11:08:41.498783 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5491 11:08:41.502046 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =104
5492 11:08:41.505491 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =80
5493 11:08:41.508699 DQ12 =90, DQ13 =88, DQ14 =98, DQ15 =94
5494 11:08:41.508779
5495 11:08:41.508843
5496 11:08:41.514929 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a07, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5497 11:08:41.518234 CH0 RK1: MR19=505, MR18=1A07
5498 11:08:41.525117 CH0_RK1: MR19=0x505, MR18=0x1A07, DQSOSC=413, MR23=63, INC=63, DEC=42
5499 11:08:41.528516 [RxdqsGatingPostProcess] freq 933
5500 11:08:41.531737 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5501 11:08:41.535428 best DQS0 dly(2T, 0.5T) = (0, 10)
5502 11:08:41.538780 best DQS1 dly(2T, 0.5T) = (0, 10)
5503 11:08:41.542500 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5504 11:08:41.545261 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5505 11:08:41.548908 best DQS0 dly(2T, 0.5T) = (0, 10)
5506 11:08:41.551982 best DQS1 dly(2T, 0.5T) = (0, 11)
5507 11:08:41.555510 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5508 11:08:41.558671 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5509 11:08:41.561964 Pre-setting of DQS Precalculation
5510 11:08:41.565142 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5511 11:08:41.565264 ==
5512 11:08:41.568552 Dram Type= 6, Freq= 0, CH_1, rank 0
5513 11:08:41.571787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 11:08:41.575614 ==
5515 11:08:41.579062 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5516 11:08:41.586260 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5517 11:08:41.589457 [CA 0] Center 37 (7~67) winsize 61
5518 11:08:41.593218 [CA 1] Center 36 (6~67) winsize 62
5519 11:08:41.595656 [CA 2] Center 34 (4~65) winsize 62
5520 11:08:41.598814 [CA 3] Center 33 (3~64) winsize 62
5521 11:08:41.602122 [CA 4] Center 34 (3~65) winsize 63
5522 11:08:41.605595 [CA 5] Center 33 (3~64) winsize 62
5523 11:08:41.605677
5524 11:08:41.608864 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5525 11:08:41.608945
5526 11:08:41.612034 [CATrainingPosCal] consider 1 rank data
5527 11:08:41.615543 u2DelayCellTimex100 = 270/100 ps
5528 11:08:41.618722 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5529 11:08:41.621868 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 11:08:41.625177 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5531 11:08:41.628886 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5532 11:08:41.631867 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5533 11:08:41.639047 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5534 11:08:41.639128
5535 11:08:41.642015 CA PerBit enable=1, Macro0, CA PI delay=33
5536 11:08:41.642096
5537 11:08:41.645515 [CBTSetCACLKResult] CA Dly = 33
5538 11:08:41.645595 CS Dly: 4 (0~35)
5539 11:08:41.645659 ==
5540 11:08:41.648716 Dram Type= 6, Freq= 0, CH_1, rank 1
5541 11:08:41.651526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 11:08:41.655412 ==
5543 11:08:41.658811 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5544 11:08:41.665095 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5545 11:08:41.668407 [CA 0] Center 37 (7~67) winsize 61
5546 11:08:41.671830 [CA 1] Center 37 (7~67) winsize 61
5547 11:08:41.675581 [CA 2] Center 34 (3~65) winsize 63
5548 11:08:41.678324 [CA 3] Center 33 (3~64) winsize 62
5549 11:08:41.682073 [CA 4] Center 34 (4~64) winsize 61
5550 11:08:41.684760 [CA 5] Center 32 (2~63) winsize 62
5551 11:08:41.684841
5552 11:08:41.688360 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5553 11:08:41.688441
5554 11:08:41.691495 [CATrainingPosCal] consider 2 rank data
5555 11:08:41.695098 u2DelayCellTimex100 = 270/100 ps
5556 11:08:41.698334 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5557 11:08:41.701711 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5558 11:08:41.705399 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5559 11:08:41.707999 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5560 11:08:41.714744 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5561 11:08:41.718589 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5562 11:08:41.718670
5563 11:08:41.721449 CA PerBit enable=1, Macro0, CA PI delay=33
5564 11:08:41.721529
5565 11:08:41.724946 [CBTSetCACLKResult] CA Dly = 33
5566 11:08:41.725028 CS Dly: 5 (0~38)
5567 11:08:41.725092
5568 11:08:41.728112 ----->DramcWriteLeveling(PI) begin...
5569 11:08:41.728195 ==
5570 11:08:41.731814 Dram Type= 6, Freq= 0, CH_1, rank 0
5571 11:08:41.738797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 11:08:41.738879 ==
5573 11:08:41.741946 Write leveling (Byte 0): 27 => 27
5574 11:08:41.742026 Write leveling (Byte 1): 29 => 29
5575 11:08:41.744974 DramcWriteLeveling(PI) end<-----
5576 11:08:41.745055
5577 11:08:41.745119 ==
5578 11:08:41.748585 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 11:08:41.755510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 11:08:41.755602 ==
5581 11:08:41.758684 [Gating] SW mode calibration
5582 11:08:41.765338 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5583 11:08:41.768530 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5584 11:08:41.774903 0 14 0 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 0)
5585 11:08:41.778423 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 11:08:41.781864 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 11:08:41.785085 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5588 11:08:41.791741 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 11:08:41.795265 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 11:08:41.798501 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5591 11:08:41.805478 0 14 28 | B1->B0 | 3131 3232 | 0 0 | (0 0) (0 1)
5592 11:08:41.808345 0 15 0 | B1->B0 | 2727 2f2f | 0 0 | (1 0) (1 0)
5593 11:08:41.811591 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 11:08:41.818586 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 11:08:41.822096 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 11:08:41.825475 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 11:08:41.832259 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 11:08:41.835366 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 11:08:41.838816 0 15 28 | B1->B0 | 2727 2525 | 1 0 | (0 0) (0 0)
5600 11:08:41.845323 1 0 0 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
5601 11:08:41.848797 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 11:08:41.852013 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 11:08:41.858423 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 11:08:41.861714 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 11:08:41.865878 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 11:08:41.871604 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 11:08:41.875217 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5608 11:08:41.878781 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5609 11:08:41.885315 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 11:08:41.888560 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 11:08:41.891544 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 11:08:41.894973 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 11:08:41.901726 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 11:08:41.905596 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 11:08:41.908263 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 11:08:41.915269 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 11:08:41.918389 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 11:08:41.921795 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 11:08:41.928533 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 11:08:41.931690 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 11:08:41.935119 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 11:08:41.941657 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 11:08:41.945013 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5624 11:08:41.948627 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 11:08:41.951464 Total UI for P1: 0, mck2ui 16
5626 11:08:41.954957 best dqsien dly found for B0: ( 1, 2, 28)
5627 11:08:41.959277 Total UI for P1: 0, mck2ui 16
5628 11:08:41.961569 best dqsien dly found for B1: ( 1, 2, 28)
5629 11:08:41.965245 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5630 11:08:41.969021 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5631 11:08:41.969103
5632 11:08:41.971679 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5633 11:08:41.978357 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5634 11:08:41.978463 [Gating] SW calibration Done
5635 11:08:41.978528 ==
5636 11:08:41.981861 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 11:08:41.988185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 11:08:41.988268 ==
5639 11:08:41.988333 RX Vref Scan: 0
5640 11:08:41.988394
5641 11:08:41.991912 RX Vref 0 -> 0, step: 1
5642 11:08:41.992047
5643 11:08:41.995038 RX Delay -80 -> 252, step: 8
5644 11:08:41.998565 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5645 11:08:42.002036 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5646 11:08:42.005227 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5647 11:08:42.008866 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5648 11:08:42.015123 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5649 11:08:42.018336 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5650 11:08:42.022291 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5651 11:08:42.025112 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5652 11:08:42.028453 iDelay=200, Bit 8, Center 75 (-24 ~ 175) 200
5653 11:08:42.031563 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5654 11:08:42.038845 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5655 11:08:42.042576 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5656 11:08:42.045490 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5657 11:08:42.048701 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5658 11:08:42.051674 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5659 11:08:42.055180 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5660 11:08:42.058829 ==
5661 11:08:42.061895 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 11:08:42.065322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 11:08:42.065402 ==
5664 11:08:42.065466 DQS Delay:
5665 11:08:42.068846 DQS0 = 0, DQS1 = 0
5666 11:08:42.068927 DQM Delay:
5667 11:08:42.071700 DQM0 = 95, DQM1 = 89
5668 11:08:42.071781 DQ Delay:
5669 11:08:42.075581 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =99
5670 11:08:42.078759 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5671 11:08:42.082518 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5672 11:08:42.084996 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5673 11:08:42.085076
5674 11:08:42.085140
5675 11:08:42.085199 ==
5676 11:08:42.088334 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 11:08:42.091616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 11:08:42.091736 ==
5679 11:08:42.091801
5680 11:08:42.091860
5681 11:08:42.095394 TX Vref Scan disable
5682 11:08:42.098253 == TX Byte 0 ==
5683 11:08:42.102106 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5684 11:08:42.105586 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5685 11:08:42.108217 == TX Byte 1 ==
5686 11:08:42.111480 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5687 11:08:42.114740 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5688 11:08:42.114820 ==
5689 11:08:42.118044 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 11:08:42.125056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 11:08:42.125137 ==
5692 11:08:42.125202
5693 11:08:42.125261
5694 11:08:42.125318 TX Vref Scan disable
5695 11:08:42.128939 == TX Byte 0 ==
5696 11:08:42.132047 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5697 11:08:42.135329 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5698 11:08:42.138766 == TX Byte 1 ==
5699 11:08:42.142326 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5700 11:08:42.145314 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5701 11:08:42.149149
5702 11:08:42.149230 [DATLAT]
5703 11:08:42.149295 Freq=933, CH1 RK0
5704 11:08:42.149354
5705 11:08:42.151981 DATLAT Default: 0xd
5706 11:08:42.152062 0, 0xFFFF, sum = 0
5707 11:08:42.156302 1, 0xFFFF, sum = 0
5708 11:08:42.156384 2, 0xFFFF, sum = 0
5709 11:08:42.158775 3, 0xFFFF, sum = 0
5710 11:08:42.158857 4, 0xFFFF, sum = 0
5711 11:08:42.162120 5, 0xFFFF, sum = 0
5712 11:08:42.162202 6, 0xFFFF, sum = 0
5713 11:08:42.165485 7, 0xFFFF, sum = 0
5714 11:08:42.168904 8, 0xFFFF, sum = 0
5715 11:08:42.168986 9, 0xFFFF, sum = 0
5716 11:08:42.172426 10, 0x0, sum = 1
5717 11:08:42.172508 11, 0x0, sum = 2
5718 11:08:42.172574 12, 0x0, sum = 3
5719 11:08:42.175674 13, 0x0, sum = 4
5720 11:08:42.175755 best_step = 11
5721 11:08:42.175819
5722 11:08:42.175878 ==
5723 11:08:42.178787 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 11:08:42.185934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 11:08:42.186015 ==
5726 11:08:42.186081 RX Vref Scan: 1
5727 11:08:42.186141
5728 11:08:42.188872 RX Vref 0 -> 0, step: 1
5729 11:08:42.188953
5730 11:08:42.192639 RX Delay -69 -> 252, step: 4
5731 11:08:42.192720
5732 11:08:42.195692 Set Vref, RX VrefLevel [Byte0]: 59
5733 11:08:42.199009 [Byte1]: 52
5734 11:08:42.199090
5735 11:08:42.202008 Final RX Vref Byte 0 = 59 to rank0
5736 11:08:42.205494 Final RX Vref Byte 1 = 52 to rank0
5737 11:08:42.208730 Final RX Vref Byte 0 = 59 to rank1
5738 11:08:42.211805 Final RX Vref Byte 1 = 52 to rank1==
5739 11:08:42.215270 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 11:08:42.218830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 11:08:42.218911 ==
5742 11:08:42.222320 DQS Delay:
5743 11:08:42.222408 DQS0 = 0, DQS1 = 0
5744 11:08:42.225426 DQM Delay:
5745 11:08:42.225507 DQM0 = 97, DQM1 = 91
5746 11:08:42.225571 DQ Delay:
5747 11:08:42.229456 DQ0 =100, DQ1 =90, DQ2 =86, DQ3 =96
5748 11:08:42.232565 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =94
5749 11:08:42.235739 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5750 11:08:42.238655 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =96
5751 11:08:42.238735
5752 11:08:42.238800
5753 11:08:42.248976 [DQSOSCAuto] RK0, (LSB)MR18= 0x13f0, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5754 11:08:42.251902 CH1 RK0: MR19=504, MR18=13F0
5755 11:08:42.255536 CH1_RK0: MR19=0x504, MR18=0x13F0, DQSOSC=415, MR23=63, INC=62, DEC=41
5756 11:08:42.258714
5757 11:08:42.261874 ----->DramcWriteLeveling(PI) begin...
5758 11:08:42.261956 ==
5759 11:08:42.265852 Dram Type= 6, Freq= 0, CH_1, rank 1
5760 11:08:42.268567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 11:08:42.268649 ==
5762 11:08:42.272198 Write leveling (Byte 0): 27 => 27
5763 11:08:42.275282 Write leveling (Byte 1): 27 => 27
5764 11:08:42.279251 DramcWriteLeveling(PI) end<-----
5765 11:08:42.279332
5766 11:08:42.279396 ==
5767 11:08:42.282164 Dram Type= 6, Freq= 0, CH_1, rank 1
5768 11:08:42.285602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 11:08:42.285683 ==
5770 11:08:42.288822 [Gating] SW mode calibration
5771 11:08:42.295224 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5772 11:08:42.301990 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5773 11:08:42.305298 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 11:08:42.308733 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 11:08:42.315305 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 11:08:42.318883 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 11:08:42.321854 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 11:08:42.325452 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5779 11:08:42.332124 0 14 24 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 0)
5780 11:08:42.335243 0 14 28 | B1->B0 | 2828 2424 | 0 0 | (1 0) (0 0)
5781 11:08:42.338737 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 11:08:42.345197 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5783 11:08:42.348726 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 11:08:42.352084 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 11:08:42.358539 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 11:08:42.362394 0 15 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5787 11:08:42.365273 0 15 24 | B1->B0 | 2828 3636 | 0 0 | (0 0) (0 0)
5788 11:08:42.371979 0 15 28 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
5789 11:08:42.375195 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 11:08:42.378565 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 11:08:42.385243 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 11:08:42.388902 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 11:08:42.392133 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 11:08:42.398697 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 11:08:42.401835 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5796 11:08:42.405480 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5797 11:08:42.411890 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 11:08:42.415101 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 11:08:42.418864 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 11:08:42.425124 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 11:08:42.429180 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 11:08:42.431838 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 11:08:42.434990 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 11:08:42.441657 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 11:08:42.445066 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 11:08:42.448662 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 11:08:42.455378 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 11:08:42.458388 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 11:08:42.462324 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 11:08:42.468478 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 11:08:42.472039 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5812 11:08:42.475300 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 11:08:42.479027 Total UI for P1: 0, mck2ui 16
5814 11:08:42.481763 best dqsien dly found for B0: ( 1, 2, 24)
5815 11:08:42.484850 Total UI for P1: 0, mck2ui 16
5816 11:08:42.488617 best dqsien dly found for B1: ( 1, 2, 26)
5817 11:08:42.491756 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5818 11:08:42.494982 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5819 11:08:42.495063
5820 11:08:42.501926 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5821 11:08:42.505127 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5822 11:08:42.505208 [Gating] SW calibration Done
5823 11:08:42.508010 ==
5824 11:08:42.511326 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 11:08:42.514676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 11:08:42.514791 ==
5827 11:08:42.514901 RX Vref Scan: 0
5828 11:08:42.515008
5829 11:08:42.518260 RX Vref 0 -> 0, step: 1
5830 11:08:42.518375
5831 11:08:42.521682 RX Delay -80 -> 252, step: 8
5832 11:08:42.525441 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5833 11:08:42.528555 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5834 11:08:42.531804 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5835 11:08:42.538828 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5836 11:08:42.541533 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5837 11:08:42.544673 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5838 11:08:42.548197 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5839 11:08:42.551795 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5840 11:08:42.554754 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5841 11:08:42.561419 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5842 11:08:42.564978 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5843 11:08:42.567941 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5844 11:08:42.571788 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5845 11:08:42.575199 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5846 11:08:42.578333 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5847 11:08:42.585209 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5848 11:08:42.585332 ==
5849 11:08:42.588055 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 11:08:42.591976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 11:08:42.592101 ==
5852 11:08:42.592213 DQS Delay:
5853 11:08:42.595434 DQS0 = 0, DQS1 = 0
5854 11:08:42.595554 DQM Delay:
5855 11:08:42.598109 DQM0 = 95, DQM1 = 88
5856 11:08:42.598228 DQ Delay:
5857 11:08:42.601976 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5858 11:08:42.604848 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5859 11:08:42.608782 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5860 11:08:42.611574 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5861 11:08:42.611694
5862 11:08:42.611805
5863 11:08:42.611911 ==
5864 11:08:42.614654 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 11:08:42.617957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 11:08:42.618060 ==
5867 11:08:42.621527
5868 11:08:42.621606
5869 11:08:42.621671 TX Vref Scan disable
5870 11:08:42.624749 == TX Byte 0 ==
5871 11:08:42.628308 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5872 11:08:42.631610 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5873 11:08:42.634979 == TX Byte 1 ==
5874 11:08:42.638268 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5875 11:08:42.641846 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5876 11:08:42.641927 ==
5877 11:08:42.644939 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 11:08:42.651190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 11:08:42.651272 ==
5880 11:08:42.651336
5881 11:08:42.651396
5882 11:08:42.651454 TX Vref Scan disable
5883 11:08:42.655316 == TX Byte 0 ==
5884 11:08:42.659317 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5885 11:08:42.662139 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5886 11:08:42.665628 == TX Byte 1 ==
5887 11:08:42.668789 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5888 11:08:42.672147 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5889 11:08:42.675961
5890 11:08:42.676083 [DATLAT]
5891 11:08:42.676195 Freq=933, CH1 RK1
5892 11:08:42.676305
5893 11:08:42.678982 DATLAT Default: 0xb
5894 11:08:42.679103 0, 0xFFFF, sum = 0
5895 11:08:42.682387 1, 0xFFFF, sum = 0
5896 11:08:42.682526 2, 0xFFFF, sum = 0
5897 11:08:42.685652 3, 0xFFFF, sum = 0
5898 11:08:42.685772 4, 0xFFFF, sum = 0
5899 11:08:42.688781 5, 0xFFFF, sum = 0
5900 11:08:42.688902 6, 0xFFFF, sum = 0
5901 11:08:42.692363 7, 0xFFFF, sum = 0
5902 11:08:42.695660 8, 0xFFFF, sum = 0
5903 11:08:42.695778 9, 0xFFFF, sum = 0
5904 11:08:42.698852 10, 0x0, sum = 1
5905 11:08:42.698974 11, 0x0, sum = 2
5906 11:08:42.699086 12, 0x0, sum = 3
5907 11:08:42.702003 13, 0x0, sum = 4
5908 11:08:42.702119 best_step = 11
5909 11:08:42.702230
5910 11:08:42.702337 ==
5911 11:08:42.705459 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 11:08:42.711934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 11:08:42.712056 ==
5914 11:08:42.712169 RX Vref Scan: 0
5915 11:08:42.712278
5916 11:08:42.715523 RX Vref 0 -> 0, step: 1
5917 11:08:42.715643
5918 11:08:42.718805 RX Delay -61 -> 252, step: 4
5919 11:08:42.722343 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5920 11:08:42.725769 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5921 11:08:42.732015 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5922 11:08:42.735283 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5923 11:08:42.738678 iDelay=195, Bit 4, Center 98 (7 ~ 190) 184
5924 11:08:42.742132 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5925 11:08:42.745355 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5926 11:08:42.748773 iDelay=195, Bit 7, Center 92 (3 ~ 182) 180
5927 11:08:42.755289 iDelay=195, Bit 8, Center 80 (-13 ~ 174) 188
5928 11:08:42.758586 iDelay=195, Bit 9, Center 78 (-13 ~ 170) 184
5929 11:08:42.762031 iDelay=195, Bit 10, Center 92 (-1 ~ 186) 188
5930 11:08:42.765836 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5931 11:08:42.768757 iDelay=195, Bit 12, Center 98 (11 ~ 186) 176
5932 11:08:42.775335 iDelay=195, Bit 13, Center 100 (11 ~ 190) 180
5933 11:08:42.779520 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5934 11:08:42.782247 iDelay=195, Bit 15, Center 100 (11 ~ 190) 180
5935 11:08:42.782370 ==
5936 11:08:42.785255 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 11:08:42.788767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 11:08:42.788889 ==
5939 11:08:42.792257 DQS Delay:
5940 11:08:42.792379 DQS0 = 0, DQS1 = 0
5941 11:08:42.795582 DQM Delay:
5942 11:08:42.795704 DQM0 = 95, DQM1 = 91
5943 11:08:42.795816 DQ Delay:
5944 11:08:42.798852 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5945 11:08:42.801765 DQ4 =98, DQ5 =104, DQ6 =102, DQ7 =92
5946 11:08:42.805307 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =84
5947 11:08:42.808593 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =100
5948 11:08:42.811963
5949 11:08:42.812084
5950 11:08:42.818656 [DQSOSCAuto] RK1, (LSB)MR18= 0x911, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 419 ps
5951 11:08:42.822053 CH1 RK1: MR19=505, MR18=911
5952 11:08:42.828707 CH1_RK1: MR19=0x505, MR18=0x911, DQSOSC=416, MR23=63, INC=62, DEC=41
5953 11:08:42.828812 [RxdqsGatingPostProcess] freq 933
5954 11:08:42.835367 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5955 11:08:42.839382 best DQS0 dly(2T, 0.5T) = (0, 10)
5956 11:08:42.842556 best DQS1 dly(2T, 0.5T) = (0, 10)
5957 11:08:42.845553 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5958 11:08:42.848698 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5959 11:08:42.851962 best DQS0 dly(2T, 0.5T) = (0, 10)
5960 11:08:42.855314 best DQS1 dly(2T, 0.5T) = (0, 10)
5961 11:08:42.858861 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5962 11:08:42.862022 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5963 11:08:42.865428 Pre-setting of DQS Precalculation
5964 11:08:42.868707 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5965 11:08:42.875500 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5966 11:08:42.882313 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5967 11:08:42.882400
5968 11:08:42.885692
5969 11:08:42.885772 [Calibration Summary] 1866 Mbps
5970 11:08:42.888456 CH 0, Rank 0
5971 11:08:42.888536 SW Impedance : PASS
5972 11:08:42.891881 DUTY Scan : NO K
5973 11:08:42.895154 ZQ Calibration : PASS
5974 11:08:42.895234 Jitter Meter : NO K
5975 11:08:42.898385 CBT Training : PASS
5976 11:08:42.902151 Write leveling : PASS
5977 11:08:42.902232 RX DQS gating : PASS
5978 11:08:42.906147 RX DQ/DQS(RDDQC) : PASS
5979 11:08:42.908362 TX DQ/DQS : PASS
5980 11:08:42.908443 RX DATLAT : PASS
5981 11:08:42.911839 RX DQ/DQS(Engine): PASS
5982 11:08:42.915344 TX OE : NO K
5983 11:08:42.915424 All Pass.
5984 11:08:42.915488
5985 11:08:42.915546 CH 0, Rank 1
5986 11:08:42.918593 SW Impedance : PASS
5987 11:08:42.921684 DUTY Scan : NO K
5988 11:08:42.921764 ZQ Calibration : PASS
5989 11:08:42.925958 Jitter Meter : NO K
5990 11:08:42.926041 CBT Training : PASS
5991 11:08:42.928645 Write leveling : PASS
5992 11:08:42.931767 RX DQS gating : PASS
5993 11:08:42.931846 RX DQ/DQS(RDDQC) : PASS
5994 11:08:42.935572 TX DQ/DQS : PASS
5995 11:08:42.938754 RX DATLAT : PASS
5996 11:08:42.938834 RX DQ/DQS(Engine): PASS
5997 11:08:42.941944 TX OE : NO K
5998 11:08:42.942049 All Pass.
5999 11:08:42.942140
6000 11:08:42.945177 CH 1, Rank 0
6001 11:08:42.945283 SW Impedance : PASS
6002 11:08:42.948041 DUTY Scan : NO K
6003 11:08:42.951717 ZQ Calibration : PASS
6004 11:08:42.951798 Jitter Meter : NO K
6005 11:08:42.954938 CBT Training : PASS
6006 11:08:42.958293 Write leveling : PASS
6007 11:08:42.958373 RX DQS gating : PASS
6008 11:08:42.962071 RX DQ/DQS(RDDQC) : PASS
6009 11:08:42.965129 TX DQ/DQS : PASS
6010 11:08:42.965210 RX DATLAT : PASS
6011 11:08:42.968774 RX DQ/DQS(Engine): PASS
6012 11:08:42.968854 TX OE : NO K
6013 11:08:42.971755 All Pass.
6014 11:08:42.971835
6015 11:08:42.971899 CH 1, Rank 1
6016 11:08:42.975021 SW Impedance : PASS
6017 11:08:42.975128 DUTY Scan : NO K
6018 11:08:42.978405 ZQ Calibration : PASS
6019 11:08:42.981533 Jitter Meter : NO K
6020 11:08:42.981613 CBT Training : PASS
6021 11:08:42.985055 Write leveling : PASS
6022 11:08:42.988507 RX DQS gating : PASS
6023 11:08:42.988588 RX DQ/DQS(RDDQC) : PASS
6024 11:08:42.991830 TX DQ/DQS : PASS
6025 11:08:42.994731 RX DATLAT : PASS
6026 11:08:42.994812 RX DQ/DQS(Engine): PASS
6027 11:08:42.998600 TX OE : NO K
6028 11:08:42.998711 All Pass.
6029 11:08:42.998776
6030 11:08:43.001916 DramC Write-DBI off
6031 11:08:43.004784 PER_BANK_REFRESH: Hybrid Mode
6032 11:08:43.004865 TX_TRACKING: ON
6033 11:08:43.014991 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6034 11:08:43.018535 [FAST_K] Save calibration result to emmc
6035 11:08:43.021684 dramc_set_vcore_voltage set vcore to 650000
6036 11:08:43.025082 Read voltage for 400, 6
6037 11:08:43.025162 Vio18 = 0
6038 11:08:43.025227 Vcore = 650000
6039 11:08:43.028094 Vdram = 0
6040 11:08:43.028174 Vddq = 0
6041 11:08:43.028239 Vmddr = 0
6042 11:08:43.035030 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6043 11:08:43.038151 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6044 11:08:43.041503 MEM_TYPE=3, freq_sel=20
6045 11:08:43.045358 sv_algorithm_assistance_LP4_800
6046 11:08:43.048636 ============ PULL DRAM RESETB DOWN ============
6047 11:08:43.051512 ========== PULL DRAM RESETB DOWN end =========
6048 11:08:43.057921 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6049 11:08:43.061686 ===================================
6050 11:08:43.061789 LPDDR4 DRAM CONFIGURATION
6051 11:08:43.064604 ===================================
6052 11:08:43.068183 EX_ROW_EN[0] = 0x0
6053 11:08:43.071650 EX_ROW_EN[1] = 0x0
6054 11:08:43.071731 LP4Y_EN = 0x0
6055 11:08:43.074936 WORK_FSP = 0x0
6056 11:08:43.075016 WL = 0x2
6057 11:08:43.078496 RL = 0x2
6058 11:08:43.078577 BL = 0x2
6059 11:08:43.081500 RPST = 0x0
6060 11:08:43.081606 RD_PRE = 0x0
6061 11:08:43.085042 WR_PRE = 0x1
6062 11:08:43.085123 WR_PST = 0x0
6063 11:08:43.088819 DBI_WR = 0x0
6064 11:08:43.088925 DBI_RD = 0x0
6065 11:08:43.092234 OTF = 0x1
6066 11:08:43.095250 ===================================
6067 11:08:43.098319 ===================================
6068 11:08:43.098460 ANA top config
6069 11:08:43.102093 ===================================
6070 11:08:43.104829 DLL_ASYNC_EN = 0
6071 11:08:43.108396 ALL_SLAVE_EN = 1
6072 11:08:43.108503 NEW_RANK_MODE = 1
6073 11:08:43.111565 DLL_IDLE_MODE = 1
6074 11:08:43.114922 LP45_APHY_COMB_EN = 1
6075 11:08:43.118208 TX_ODT_DIS = 1
6076 11:08:43.122616 NEW_8X_MODE = 1
6077 11:08:43.122745 ===================================
6078 11:08:43.125513 ===================================
6079 11:08:43.128610 data_rate = 800
6080 11:08:43.131977 CKR = 1
6081 11:08:43.135551 DQ_P2S_RATIO = 4
6082 11:08:43.138388 ===================================
6083 11:08:43.142040 CA_P2S_RATIO = 4
6084 11:08:43.145208 DQ_CA_OPEN = 0
6085 11:08:43.145315 DQ_SEMI_OPEN = 1
6086 11:08:43.148634 CA_SEMI_OPEN = 1
6087 11:08:43.151839 CA_FULL_RATE = 0
6088 11:08:43.155076 DQ_CKDIV4_EN = 0
6089 11:08:43.158283 CA_CKDIV4_EN = 1
6090 11:08:43.161532 CA_PREDIV_EN = 0
6091 11:08:43.161644 PH8_DLY = 0
6092 11:08:43.164846 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6093 11:08:43.168697 DQ_AAMCK_DIV = 0
6094 11:08:43.171738 CA_AAMCK_DIV = 0
6095 11:08:43.175091 CA_ADMCK_DIV = 4
6096 11:08:43.178291 DQ_TRACK_CA_EN = 0
6097 11:08:43.178439 CA_PICK = 800
6098 11:08:43.181758 CA_MCKIO = 400
6099 11:08:43.185089 MCKIO_SEMI = 400
6100 11:08:43.188958 PLL_FREQ = 3016
6101 11:08:43.191793 DQ_UI_PI_RATIO = 32
6102 11:08:43.195313 CA_UI_PI_RATIO = 32
6103 11:08:43.198934 ===================================
6104 11:08:43.201940 ===================================
6105 11:08:43.205365 memory_type:LPDDR4
6106 11:08:43.205446 GP_NUM : 10
6107 11:08:43.208888 SRAM_EN : 1
6108 11:08:43.208969 MD32_EN : 0
6109 11:08:43.211847 ===================================
6110 11:08:43.215027 [ANA_INIT] >>>>>>>>>>>>>>
6111 11:08:43.218590 <<<<<< [CONFIGURE PHASE]: ANA_TX
6112 11:08:43.221784 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6113 11:08:43.225261 ===================================
6114 11:08:43.228899 data_rate = 800,PCW = 0X7400
6115 11:08:43.231860 ===================================
6116 11:08:43.235268 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6117 11:08:43.238349 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6118 11:08:43.251648 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6119 11:08:43.254979 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6120 11:08:43.258269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6121 11:08:43.261847 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6122 11:08:43.265334 [ANA_INIT] flow start
6123 11:08:43.268303 [ANA_INIT] PLL >>>>>>>>
6124 11:08:43.268384 [ANA_INIT] PLL <<<<<<<<
6125 11:08:43.272073 [ANA_INIT] MIDPI >>>>>>>>
6126 11:08:43.275139 [ANA_INIT] MIDPI <<<<<<<<
6127 11:08:43.275220 [ANA_INIT] DLL >>>>>>>>
6128 11:08:43.278768 [ANA_INIT] flow end
6129 11:08:43.281751 ============ LP4 DIFF to SE enter ============
6130 11:08:43.285396 ============ LP4 DIFF to SE exit ============
6131 11:08:43.289270 [ANA_INIT] <<<<<<<<<<<<<
6132 11:08:43.292292 [Flow] Enable top DCM control >>>>>
6133 11:08:43.295238 [Flow] Enable top DCM control <<<<<
6134 11:08:43.298796 Enable DLL master slave shuffle
6135 11:08:43.305190 ==============================================================
6136 11:08:43.305272 Gating Mode config
6137 11:08:43.311743 ==============================================================
6138 11:08:43.311825 Config description:
6139 11:08:43.321799 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6140 11:08:43.328754 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6141 11:08:43.335398 SELPH_MODE 0: By rank 1: By Phase
6142 11:08:43.338733 ==============================================================
6143 11:08:43.341964 GAT_TRACK_EN = 0
6144 11:08:43.345264 RX_GATING_MODE = 2
6145 11:08:43.348785 RX_GATING_TRACK_MODE = 2
6146 11:08:43.351636 SELPH_MODE = 1
6147 11:08:43.355607 PICG_EARLY_EN = 1
6148 11:08:43.358765 VALID_LAT_VALUE = 1
6149 11:08:43.361852 ==============================================================
6150 11:08:43.364913 Enter into Gating configuration >>>>
6151 11:08:43.368517 Exit from Gating configuration <<<<
6152 11:08:43.371434 Enter into DVFS_PRE_config >>>>>
6153 11:08:43.385159 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6154 11:08:43.388782 Exit from DVFS_PRE_config <<<<<
6155 11:08:43.391830 Enter into PICG configuration >>>>
6156 11:08:43.391911 Exit from PICG configuration <<<<
6157 11:08:43.395030 [RX_INPUT] configuration >>>>>
6158 11:08:43.398747 [RX_INPUT] configuration <<<<<
6159 11:08:43.405416 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6160 11:08:43.408311 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6161 11:08:43.414827 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6162 11:08:43.421583 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6163 11:08:43.428508 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6164 11:08:43.435182 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6165 11:08:43.438029 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6166 11:08:43.441905 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6167 11:08:43.448296 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6168 11:08:43.451506 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6169 11:08:43.454744 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6170 11:08:43.458163 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6171 11:08:43.461572 ===================================
6172 11:08:43.464772 LPDDR4 DRAM CONFIGURATION
6173 11:08:43.468906 ===================================
6174 11:08:43.471827 EX_ROW_EN[0] = 0x0
6175 11:08:43.471908 EX_ROW_EN[1] = 0x0
6176 11:08:43.474553 LP4Y_EN = 0x0
6177 11:08:43.474633 WORK_FSP = 0x0
6178 11:08:43.477783 WL = 0x2
6179 11:08:43.477863 RL = 0x2
6180 11:08:43.481303 BL = 0x2
6181 11:08:43.481384 RPST = 0x0
6182 11:08:43.484935 RD_PRE = 0x0
6183 11:08:43.485015 WR_PRE = 0x1
6184 11:08:43.488115 WR_PST = 0x0
6185 11:08:43.488196 DBI_WR = 0x0
6186 11:08:43.491373 DBI_RD = 0x0
6187 11:08:43.491454 OTF = 0x1
6188 11:08:43.494664 ===================================
6189 11:08:43.501370 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6190 11:08:43.504573 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6191 11:08:43.507978 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6192 11:08:43.511764 ===================================
6193 11:08:43.514605 LPDDR4 DRAM CONFIGURATION
6194 11:08:43.518077 ===================================
6195 11:08:43.521212 EX_ROW_EN[0] = 0x10
6196 11:08:43.521293 EX_ROW_EN[1] = 0x0
6197 11:08:43.524871 LP4Y_EN = 0x0
6198 11:08:43.524953 WORK_FSP = 0x0
6199 11:08:43.528085 WL = 0x2
6200 11:08:43.528165 RL = 0x2
6201 11:08:43.531159 BL = 0x2
6202 11:08:43.531240 RPST = 0x0
6203 11:08:43.534657 RD_PRE = 0x0
6204 11:08:43.534738 WR_PRE = 0x1
6205 11:08:43.538023 WR_PST = 0x0
6206 11:08:43.538129 DBI_WR = 0x0
6207 11:08:43.541365 DBI_RD = 0x0
6208 11:08:43.541445 OTF = 0x1
6209 11:08:43.545120 ===================================
6210 11:08:43.551459 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6211 11:08:43.555522 nWR fixed to 30
6212 11:08:43.559206 [ModeRegInit_LP4] CH0 RK0
6213 11:08:43.559287 [ModeRegInit_LP4] CH0 RK1
6214 11:08:43.562264 [ModeRegInit_LP4] CH1 RK0
6215 11:08:43.565774 [ModeRegInit_LP4] CH1 RK1
6216 11:08:43.565855 match AC timing 19
6217 11:08:43.572804 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6218 11:08:43.575645 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6219 11:08:43.579323 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6220 11:08:43.585518 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6221 11:08:43.589379 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6222 11:08:43.589460 ==
6223 11:08:43.592365 Dram Type= 6, Freq= 0, CH_0, rank 0
6224 11:08:43.595829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6225 11:08:43.595910 ==
6226 11:08:43.602334 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6227 11:08:43.609365 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6228 11:08:43.612072 [CA 0] Center 36 (8~64) winsize 57
6229 11:08:43.615749 [CA 1] Center 36 (8~64) winsize 57
6230 11:08:43.615852 [CA 2] Center 36 (8~64) winsize 57
6231 11:08:43.619405 [CA 3] Center 36 (8~64) winsize 57
6232 11:08:43.622245 [CA 4] Center 36 (8~64) winsize 57
6233 11:08:43.625502 [CA 5] Center 36 (8~64) winsize 57
6234 11:08:43.625582
6235 11:08:43.629317 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6236 11:08:43.632323
6237 11:08:43.635754 [CATrainingPosCal] consider 1 rank data
6238 11:08:43.635835 u2DelayCellTimex100 = 270/100 ps
6239 11:08:43.642300 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 11:08:43.645548 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 11:08:43.648953 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 11:08:43.652573 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 11:08:43.656033 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 11:08:43.658905 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 11:08:43.658987
6246 11:08:43.662178 CA PerBit enable=1, Macro0, CA PI delay=36
6247 11:08:43.662259
6248 11:08:43.665778 [CBTSetCACLKResult] CA Dly = 36
6249 11:08:43.668761 CS Dly: 1 (0~32)
6250 11:08:43.668841 ==
6251 11:08:43.672270 Dram Type= 6, Freq= 0, CH_0, rank 1
6252 11:08:43.675598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6253 11:08:43.675680 ==
6254 11:08:43.682082 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6255 11:08:43.686443 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6256 11:08:43.689226 [CA 0] Center 36 (8~64) winsize 57
6257 11:08:43.692564 [CA 1] Center 36 (8~64) winsize 57
6258 11:08:43.695935 [CA 2] Center 36 (8~64) winsize 57
6259 11:08:43.699092 [CA 3] Center 36 (8~64) winsize 57
6260 11:08:43.702631 [CA 4] Center 36 (8~64) winsize 57
6261 11:08:43.705846 [CA 5] Center 36 (8~64) winsize 57
6262 11:08:43.705942
6263 11:08:43.709446 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6264 11:08:43.709527
6265 11:08:43.712534 [CATrainingPosCal] consider 2 rank data
6266 11:08:43.716066 u2DelayCellTimex100 = 270/100 ps
6267 11:08:43.719625 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 11:08:43.722891 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 11:08:43.725667 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 11:08:43.728948 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 11:08:43.736216 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 11:08:43.738661 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 11:08:43.738743
6274 11:08:43.742387 CA PerBit enable=1, Macro0, CA PI delay=36
6275 11:08:43.742504
6276 11:08:43.745773 [CBTSetCACLKResult] CA Dly = 36
6277 11:08:43.745853 CS Dly: 1 (0~32)
6278 11:08:43.745918
6279 11:08:43.749186 ----->DramcWriteLeveling(PI) begin...
6280 11:08:43.749268 ==
6281 11:08:43.751986 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 11:08:43.759356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 11:08:43.759437 ==
6284 11:08:43.762278 Write leveling (Byte 0): 40 => 8
6285 11:08:43.762359 Write leveling (Byte 1): 32 => 0
6286 11:08:43.765262 DramcWriteLeveling(PI) end<-----
6287 11:08:43.765342
6288 11:08:43.765407 ==
6289 11:08:43.769030 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 11:08:43.775453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 11:08:43.775535 ==
6292 11:08:43.778887 [Gating] SW mode calibration
6293 11:08:43.785408 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6294 11:08:43.788754 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6295 11:08:43.795102 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6296 11:08:43.798439 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6297 11:08:43.802071 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6298 11:08:43.808525 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6299 11:08:43.811911 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 11:08:43.815198 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 11:08:43.819246 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 11:08:43.825087 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 11:08:43.828635 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6304 11:08:43.831645 Total UI for P1: 0, mck2ui 16
6305 11:08:43.835094 best dqsien dly found for B0: ( 0, 14, 24)
6306 11:08:43.839143 Total UI for P1: 0, mck2ui 16
6307 11:08:43.841954 best dqsien dly found for B1: ( 0, 14, 24)
6308 11:08:43.845499 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6309 11:08:43.848390 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6310 11:08:43.848471
6311 11:08:43.851696 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6312 11:08:43.858491 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6313 11:08:43.858571 [Gating] SW calibration Done
6314 11:08:43.858635 ==
6315 11:08:43.861786 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 11:08:43.868906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 11:08:43.868987 ==
6318 11:08:43.869052 RX Vref Scan: 0
6319 11:08:43.869112
6320 11:08:43.872142 RX Vref 0 -> 0, step: 1
6321 11:08:43.872247
6322 11:08:43.875236 RX Delay -410 -> 252, step: 16
6323 11:08:43.878571 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6324 11:08:43.881793 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6325 11:08:43.888337 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6326 11:08:43.892058 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6327 11:08:43.894997 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6328 11:08:43.899029 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6329 11:08:43.905033 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6330 11:08:43.909088 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6331 11:08:43.911892 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6332 11:08:43.915270 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6333 11:08:43.918419 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6334 11:08:43.925427 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6335 11:08:43.928461 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6336 11:08:43.932447 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6337 11:08:43.938360 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6338 11:08:43.941883 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6339 11:08:43.941964 ==
6340 11:08:43.945093 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 11:08:43.948270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 11:08:43.948352 ==
6343 11:08:43.952133 DQS Delay:
6344 11:08:43.952214 DQS0 = 35, DQS1 = 51
6345 11:08:43.952278 DQM Delay:
6346 11:08:43.955214 DQM0 = 6, DQM1 = 11
6347 11:08:43.955295 DQ Delay:
6348 11:08:43.958487 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6349 11:08:43.961735 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6350 11:08:43.965315 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6351 11:08:43.968620 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6352 11:08:43.968702
6353 11:08:43.968767
6354 11:08:43.968827 ==
6355 11:08:43.971928 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 11:08:43.975879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 11:08:43.975960 ==
6358 11:08:43.976024
6359 11:08:43.976085
6360 11:08:43.978536 TX Vref Scan disable
6361 11:08:43.981829 == TX Byte 0 ==
6362 11:08:43.985197 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6363 11:08:43.988515 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6364 11:08:43.992119 == TX Byte 1 ==
6365 11:08:43.995484 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6366 11:08:43.998654 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6367 11:08:43.998735 ==
6368 11:08:44.001886 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 11:08:44.005115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 11:08:44.005238 ==
6371 11:08:44.008422
6372 11:08:44.008541
6373 11:08:44.008650 TX Vref Scan disable
6374 11:08:44.011980 == TX Byte 0 ==
6375 11:08:44.015456 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 11:08:44.019123 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 11:08:44.022352 == TX Byte 1 ==
6378 11:08:44.025097 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6379 11:08:44.028174 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6380 11:08:44.028255
6381 11:08:44.028320 [DATLAT]
6382 11:08:44.031715 Freq=400, CH0 RK0
6383 11:08:44.031797
6384 11:08:44.035220 DATLAT Default: 0xf
6385 11:08:44.035301 0, 0xFFFF, sum = 0
6386 11:08:44.038172 1, 0xFFFF, sum = 0
6387 11:08:44.038254 2, 0xFFFF, sum = 0
6388 11:08:44.041879 3, 0xFFFF, sum = 0
6389 11:08:44.041961 4, 0xFFFF, sum = 0
6390 11:08:44.045193 5, 0xFFFF, sum = 0
6391 11:08:44.045276 6, 0xFFFF, sum = 0
6392 11:08:44.048291 7, 0xFFFF, sum = 0
6393 11:08:44.048373 8, 0xFFFF, sum = 0
6394 11:08:44.052010 9, 0xFFFF, sum = 0
6395 11:08:44.052091 10, 0xFFFF, sum = 0
6396 11:08:44.055034 11, 0xFFFF, sum = 0
6397 11:08:44.055116 12, 0xFFFF, sum = 0
6398 11:08:44.058264 13, 0x0, sum = 1
6399 11:08:44.058346 14, 0x0, sum = 2
6400 11:08:44.061831 15, 0x0, sum = 3
6401 11:08:44.061913 16, 0x0, sum = 4
6402 11:08:44.065506 best_step = 14
6403 11:08:44.065586
6404 11:08:44.065650 ==
6405 11:08:44.068603 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 11:08:44.072024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 11:08:44.072106 ==
6408 11:08:44.075744 RX Vref Scan: 1
6409 11:08:44.075825
6410 11:08:44.075889 RX Vref 0 -> 0, step: 1
6411 11:08:44.075950
6412 11:08:44.079496 RX Delay -343 -> 252, step: 8
6413 11:08:44.079577
6414 11:08:44.081907 Set Vref, RX VrefLevel [Byte0]: 55
6415 11:08:44.085315 [Byte1]: 51
6416 11:08:44.089195
6417 11:08:44.089275 Final RX Vref Byte 0 = 55 to rank0
6418 11:08:44.092506 Final RX Vref Byte 1 = 51 to rank0
6419 11:08:44.096215 Final RX Vref Byte 0 = 55 to rank1
6420 11:08:44.099171 Final RX Vref Byte 1 = 51 to rank1==
6421 11:08:44.102831 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 11:08:44.106267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 11:08:44.109508 ==
6424 11:08:44.109589 DQS Delay:
6425 11:08:44.109653 DQS0 = 44, DQS1 = 60
6426 11:08:44.112604 DQM Delay:
6427 11:08:44.112684 DQM0 = 11, DQM1 = 15
6428 11:08:44.116145 DQ Delay:
6429 11:08:44.119798 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6430 11:08:44.119879 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6431 11:08:44.122648 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6432 11:08:44.126029 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6433 11:08:44.126109
6434 11:08:44.129109
6435 11:08:44.135862 [DQSOSCAuto] RK0, (LSB)MR18= 0x8857, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6436 11:08:44.139680 CH0 RK0: MR19=C0C, MR18=8857
6437 11:08:44.146156 CH0_RK0: MR19=0xC0C, MR18=0x8857, DQSOSC=392, MR23=63, INC=384, DEC=256
6438 11:08:44.146237 ==
6439 11:08:44.149578 Dram Type= 6, Freq= 0, CH_0, rank 1
6440 11:08:44.152661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 11:08:44.152742 ==
6442 11:08:44.155882 [Gating] SW mode calibration
6443 11:08:44.162706 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6444 11:08:44.169455 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6445 11:08:44.172630 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6446 11:08:44.176453 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6447 11:08:44.178962 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 11:08:44.186163 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6449 11:08:44.189209 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 11:08:44.192980 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 11:08:44.198969 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 11:08:44.202720 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 11:08:44.205788 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6454 11:08:44.210011 Total UI for P1: 0, mck2ui 16
6455 11:08:44.212593 best dqsien dly found for B0: ( 0, 14, 24)
6456 11:08:44.215667 Total UI for P1: 0, mck2ui 16
6457 11:08:44.220104 best dqsien dly found for B1: ( 0, 14, 24)
6458 11:08:44.222765 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6459 11:08:44.225689 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6460 11:08:44.225785
6461 11:08:44.232492 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6462 11:08:44.235645 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6463 11:08:44.239383 [Gating] SW calibration Done
6464 11:08:44.239464 ==
6465 11:08:44.242564 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 11:08:44.245734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 11:08:44.245860 ==
6468 11:08:44.245969 RX Vref Scan: 0
6469 11:08:44.246079
6470 11:08:44.249104 RX Vref 0 -> 0, step: 1
6471 11:08:44.249311
6472 11:08:44.252292 RX Delay -410 -> 252, step: 16
6473 11:08:44.255663 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6474 11:08:44.262340 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6475 11:08:44.265989 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6476 11:08:44.268980 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6477 11:08:44.272136 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6478 11:08:44.279271 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6479 11:08:44.282472 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6480 11:08:44.285792 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6481 11:08:44.289339 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6482 11:08:44.295952 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6483 11:08:44.298762 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6484 11:08:44.302258 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6485 11:08:44.305920 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6486 11:08:44.312267 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6487 11:08:44.315697 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6488 11:08:44.319664 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6489 11:08:44.319745 ==
6490 11:08:44.322582 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 11:08:44.326032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 11:08:44.328896 ==
6493 11:08:44.328979 DQS Delay:
6494 11:08:44.329046 DQS0 = 43, DQS1 = 51
6495 11:08:44.331973 DQM Delay:
6496 11:08:44.332045 DQM0 = 11, DQM1 = 10
6497 11:08:44.335536 DQ Delay:
6498 11:08:44.335617 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6499 11:08:44.339041 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6500 11:08:44.342718 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6501 11:08:44.346002 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6502 11:08:44.346086
6503 11:08:44.346152
6504 11:08:44.346212 ==
6505 11:08:44.349022 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 11:08:44.355491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 11:08:44.355575 ==
6508 11:08:44.355641
6509 11:08:44.355703
6510 11:08:44.355763 TX Vref Scan disable
6511 11:08:44.359090 == TX Byte 0 ==
6512 11:08:44.362211 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6513 11:08:44.365362 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6514 11:08:44.368888 == TX Byte 1 ==
6515 11:08:44.372369 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6516 11:08:44.375612 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6517 11:08:44.375694 ==
6518 11:08:44.378762 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 11:08:44.385526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 11:08:44.385625 ==
6521 11:08:44.385723
6522 11:08:44.385797
6523 11:08:44.385873 TX Vref Scan disable
6524 11:08:44.389329 == TX Byte 0 ==
6525 11:08:44.392487 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6526 11:08:44.396333 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6527 11:08:44.398939 == TX Byte 1 ==
6528 11:08:44.402403 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6529 11:08:44.405399 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6530 11:08:44.405517
6531 11:08:44.408684 [DATLAT]
6532 11:08:44.408782 Freq=400, CH0 RK1
6533 11:08:44.408879
6534 11:08:44.413154 DATLAT Default: 0xe
6535 11:08:44.413252 0, 0xFFFF, sum = 0
6536 11:08:44.415737 1, 0xFFFF, sum = 0
6537 11:08:44.415882 2, 0xFFFF, sum = 0
6538 11:08:44.418858 3, 0xFFFF, sum = 0
6539 11:08:44.418942 4, 0xFFFF, sum = 0
6540 11:08:44.422527 5, 0xFFFF, sum = 0
6541 11:08:44.422625 6, 0xFFFF, sum = 0
6542 11:08:44.425373 7, 0xFFFF, sum = 0
6543 11:08:44.425472 8, 0xFFFF, sum = 0
6544 11:08:44.428863 9, 0xFFFF, sum = 0
6545 11:08:44.428963 10, 0xFFFF, sum = 0
6546 11:08:44.432781 11, 0xFFFF, sum = 0
6547 11:08:44.432880 12, 0xFFFF, sum = 0
6548 11:08:44.435494 13, 0x0, sum = 1
6549 11:08:44.435593 14, 0x0, sum = 2
6550 11:08:44.438781 15, 0x0, sum = 3
6551 11:08:44.438880 16, 0x0, sum = 4
6552 11:08:44.442333 best_step = 14
6553 11:08:44.442440
6554 11:08:44.442537 ==
6555 11:08:44.445814 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 11:08:44.448939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 11:08:44.449022 ==
6558 11:08:44.452282 RX Vref Scan: 0
6559 11:08:44.452363
6560 11:08:44.452447 RX Vref 0 -> 0, step: 1
6561 11:08:44.452509
6562 11:08:44.455911 RX Delay -343 -> 252, step: 8
6563 11:08:44.464092 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6564 11:08:44.467095 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6565 11:08:44.470541 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6566 11:08:44.473864 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6567 11:08:44.479992 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6568 11:08:44.483295 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6569 11:08:44.486982 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6570 11:08:44.489939 iDelay=217, Bit 7, Center -24 (-263 ~ 216) 480
6571 11:08:44.496771 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6572 11:08:44.499877 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6573 11:08:44.503225 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6574 11:08:44.509939 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6575 11:08:44.513332 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6576 11:08:44.516286 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6577 11:08:44.520103 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6578 11:08:44.526086 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6579 11:08:44.526208 ==
6580 11:08:44.529607 Dram Type= 6, Freq= 0, CH_0, rank 1
6581 11:08:44.532892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 11:08:44.533012 ==
6583 11:08:44.533123 DQS Delay:
6584 11:08:44.536501 DQS0 = 48, DQS1 = 56
6585 11:08:44.536620 DQM Delay:
6586 11:08:44.539604 DQM0 = 13, DQM1 = 10
6587 11:08:44.539726 DQ Delay:
6588 11:08:44.543312 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6589 11:08:44.546493 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6590 11:08:44.549782 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6591 11:08:44.553040 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6592 11:08:44.553122
6593 11:08:44.553187
6594 11:08:44.560081 [DQSOSCAuto] RK1, (LSB)MR18= 0x9469, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6595 11:08:44.562980 CH0 RK1: MR19=C0C, MR18=9469
6596 11:08:44.570003 CH0_RK1: MR19=0xC0C, MR18=0x9469, DQSOSC=391, MR23=63, INC=386, DEC=257
6597 11:08:44.573172 [RxdqsGatingPostProcess] freq 400
6598 11:08:44.579544 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6599 11:08:44.583064 best DQS0 dly(2T, 0.5T) = (0, 10)
6600 11:08:44.586252 best DQS1 dly(2T, 0.5T) = (0, 10)
6601 11:08:44.586380 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6602 11:08:44.589883 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6603 11:08:44.592974 best DQS0 dly(2T, 0.5T) = (0, 10)
6604 11:08:44.596773 best DQS1 dly(2T, 0.5T) = (0, 10)
6605 11:08:44.599634 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6606 11:08:44.602644 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6607 11:08:44.606799 Pre-setting of DQS Precalculation
6608 11:08:44.612893 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6609 11:08:44.612976 ==
6610 11:08:44.616112 Dram Type= 6, Freq= 0, CH_1, rank 0
6611 11:08:44.620118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 11:08:44.620201 ==
6613 11:08:44.626265 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6614 11:08:44.629267 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6615 11:08:44.633200 [CA 0] Center 36 (8~64) winsize 57
6616 11:08:44.635959 [CA 1] Center 36 (8~64) winsize 57
6617 11:08:44.639559 [CA 2] Center 36 (8~64) winsize 57
6618 11:08:44.642574 [CA 3] Center 36 (8~64) winsize 57
6619 11:08:44.645975 [CA 4] Center 36 (8~64) winsize 57
6620 11:08:44.649397 [CA 5] Center 36 (8~64) winsize 57
6621 11:08:44.649495
6622 11:08:44.652727 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6623 11:08:44.652818
6624 11:08:44.656206 [CATrainingPosCal] consider 1 rank data
6625 11:08:44.659665 u2DelayCellTimex100 = 270/100 ps
6626 11:08:44.662508 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 11:08:44.666132 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 11:08:44.672854 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 11:08:44.675791 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 11:08:44.678909 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 11:08:44.682558 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 11:08:44.682639
6633 11:08:44.686007 CA PerBit enable=1, Macro0, CA PI delay=36
6634 11:08:44.686119
6635 11:08:44.689074 [CBTSetCACLKResult] CA Dly = 36
6636 11:08:44.689155 CS Dly: 1 (0~32)
6637 11:08:44.689220 ==
6638 11:08:44.692416 Dram Type= 6, Freq= 0, CH_1, rank 1
6639 11:08:44.699526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 11:08:44.699610 ==
6641 11:08:44.702511 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6642 11:08:44.709247 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6643 11:08:44.712688 [CA 0] Center 36 (8~64) winsize 57
6644 11:08:44.715610 [CA 1] Center 36 (8~64) winsize 57
6645 11:08:44.719591 [CA 2] Center 36 (8~64) winsize 57
6646 11:08:44.722591 [CA 3] Center 36 (8~64) winsize 57
6647 11:08:44.725821 [CA 4] Center 36 (8~64) winsize 57
6648 11:08:44.729055 [CA 5] Center 36 (8~64) winsize 57
6649 11:08:44.729137
6650 11:08:44.732510 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6651 11:08:44.732592
6652 11:08:44.735566 [CATrainingPosCal] consider 2 rank data
6653 11:08:44.739040 u2DelayCellTimex100 = 270/100 ps
6654 11:08:44.742445 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 11:08:44.746196 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 11:08:44.748816 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 11:08:44.752209 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 11:08:44.756424 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 11:08:44.759283 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 11:08:44.759383
6661 11:08:44.765717 CA PerBit enable=1, Macro0, CA PI delay=36
6662 11:08:44.765798
6663 11:08:44.769902 [CBTSetCACLKResult] CA Dly = 36
6664 11:08:44.769983 CS Dly: 1 (0~32)
6665 11:08:44.770048
6666 11:08:44.772481 ----->DramcWriteLeveling(PI) begin...
6667 11:08:44.772564 ==
6668 11:08:44.776003 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 11:08:44.779477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 11:08:44.779562 ==
6671 11:08:44.782498 Write leveling (Byte 0): 40 => 8
6672 11:08:44.785805 Write leveling (Byte 1): 40 => 8
6673 11:08:44.789497 DramcWriteLeveling(PI) end<-----
6674 11:08:44.789634
6675 11:08:44.789743 ==
6676 11:08:44.792482 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 11:08:44.795937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 11:08:44.799261 ==
6679 11:08:44.799385 [Gating] SW mode calibration
6680 11:08:44.809093 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6681 11:08:44.812482 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6682 11:08:44.815703 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6683 11:08:44.822344 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6684 11:08:44.825732 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6685 11:08:44.829383 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6686 11:08:44.835634 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 11:08:44.839466 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 11:08:44.842294 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 11:08:44.849337 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 11:08:44.852442 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6691 11:08:44.855543 Total UI for P1: 0, mck2ui 16
6692 11:08:44.859395 best dqsien dly found for B0: ( 0, 14, 24)
6693 11:08:44.862616 Total UI for P1: 0, mck2ui 16
6694 11:08:44.866726 best dqsien dly found for B1: ( 0, 14, 24)
6695 11:08:44.868905 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6696 11:08:44.872371 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6697 11:08:44.872496
6698 11:08:44.875858 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6699 11:08:44.878920 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6700 11:08:44.882261 [Gating] SW calibration Done
6701 11:08:44.882380 ==
6702 11:08:44.885300 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 11:08:44.888585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 11:08:44.892487 ==
6705 11:08:44.892611 RX Vref Scan: 0
6706 11:08:44.892722
6707 11:08:44.895450 RX Vref 0 -> 0, step: 1
6708 11:08:44.895570
6709 11:08:44.898679 RX Delay -410 -> 252, step: 16
6710 11:08:44.902585 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6711 11:08:44.905581 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6712 11:08:44.908769 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6713 11:08:44.915365 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6714 11:08:44.919376 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6715 11:08:44.922331 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6716 11:08:44.925920 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6717 11:08:44.932388 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6718 11:08:44.935600 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6719 11:08:44.939158 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6720 11:08:44.942127 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6721 11:08:44.949096 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6722 11:08:44.952213 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6723 11:08:44.955846 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6724 11:08:44.958826 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6725 11:08:44.965362 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6726 11:08:44.965444 ==
6727 11:08:44.969175 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 11:08:44.972375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 11:08:44.972457 ==
6730 11:08:44.972522 DQS Delay:
6731 11:08:44.975390 DQS0 = 51, DQS1 = 59
6732 11:08:44.975471 DQM Delay:
6733 11:08:44.978959 DQM0 = 20, DQM1 = 17
6734 11:08:44.979055 DQ Delay:
6735 11:08:44.982537 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =24
6736 11:08:44.985421 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6737 11:08:44.988745 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6738 11:08:44.992235 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6739 11:08:44.992316
6740 11:08:44.992380
6741 11:08:44.992441 ==
6742 11:08:44.995325 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 11:08:44.998778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 11:08:44.998860 ==
6745 11:08:44.998925
6746 11:08:45.002429
6747 11:08:45.002524 TX Vref Scan disable
6748 11:08:45.005359 == TX Byte 0 ==
6749 11:08:45.008631 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 11:08:45.012103 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 11:08:45.015797 == TX Byte 1 ==
6752 11:08:45.018892 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 11:08:45.022425 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 11:08:45.022616 ==
6755 11:08:45.026212 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 11:08:45.028748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 11:08:45.028871 ==
6758 11:08:45.028982
6759 11:08:45.029084
6760 11:08:45.032520 TX Vref Scan disable
6761 11:08:45.035515 == TX Byte 0 ==
6762 11:08:45.039438 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 11:08:45.042326 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 11:08:45.045960 == TX Byte 1 ==
6765 11:08:45.049155 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 11:08:45.052300 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 11:08:45.052421
6768 11:08:45.052533 [DATLAT]
6769 11:08:45.055692 Freq=400, CH1 RK0
6770 11:08:45.055813
6771 11:08:45.055929 DATLAT Default: 0xf
6772 11:08:45.059278 0, 0xFFFF, sum = 0
6773 11:08:45.059399 1, 0xFFFF, sum = 0
6774 11:08:45.062584 2, 0xFFFF, sum = 0
6775 11:08:45.062705 3, 0xFFFF, sum = 0
6776 11:08:45.065593 4, 0xFFFF, sum = 0
6777 11:08:45.065713 5, 0xFFFF, sum = 0
6778 11:08:45.069612 6, 0xFFFF, sum = 0
6779 11:08:45.069734 7, 0xFFFF, sum = 0
6780 11:08:45.072745 8, 0xFFFF, sum = 0
6781 11:08:45.075802 9, 0xFFFF, sum = 0
6782 11:08:45.075924 10, 0xFFFF, sum = 0
6783 11:08:45.079199 11, 0xFFFF, sum = 0
6784 11:08:45.079321 12, 0xFFFF, sum = 0
6785 11:08:45.082171 13, 0x0, sum = 1
6786 11:08:45.082293 14, 0x0, sum = 2
6787 11:08:45.085632 15, 0x0, sum = 3
6788 11:08:45.085778 16, 0x0, sum = 4
6789 11:08:45.085943 best_step = 14
6790 11:08:45.086064
6791 11:08:45.089216 ==
6792 11:08:45.092466 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 11:08:45.096442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 11:08:45.096531 ==
6795 11:08:45.096597 RX Vref Scan: 1
6796 11:08:45.096657
6797 11:08:45.099149 RX Vref 0 -> 0, step: 1
6798 11:08:45.099240
6799 11:08:45.102372 RX Delay -359 -> 252, step: 8
6800 11:08:45.102466
6801 11:08:45.106164 Set Vref, RX VrefLevel [Byte0]: 59
6802 11:08:45.108792 [Byte1]: 52
6803 11:08:45.112765
6804 11:08:45.112836 Final RX Vref Byte 0 = 59 to rank0
6805 11:08:45.116375 Final RX Vref Byte 1 = 52 to rank0
6806 11:08:45.119204 Final RX Vref Byte 0 = 59 to rank1
6807 11:08:45.122816 Final RX Vref Byte 1 = 52 to rank1==
6808 11:08:45.126094 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 11:08:45.133064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 11:08:45.133142 ==
6811 11:08:45.133209 DQS Delay:
6812 11:08:45.133272 DQS0 = 48, DQS1 = 60
6813 11:08:45.136304 DQM Delay:
6814 11:08:45.136389 DQM0 = 12, DQM1 = 12
6815 11:08:45.139513 DQ Delay:
6816 11:08:45.142802 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6817 11:08:45.142876 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6818 11:08:45.146095 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6819 11:08:45.149165 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6820 11:08:45.149236
6821 11:08:45.149297
6822 11:08:45.159628 [DQSOSCAuto] RK0, (LSB)MR18= 0x8129, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6823 11:08:45.162824 CH1 RK0: MR19=C0C, MR18=8129
6824 11:08:45.169014 CH1_RK0: MR19=0xC0C, MR18=0x8129, DQSOSC=393, MR23=63, INC=382, DEC=254
6825 11:08:45.169100 ==
6826 11:08:45.172793 Dram Type= 6, Freq= 0, CH_1, rank 1
6827 11:08:45.176145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 11:08:45.176217 ==
6829 11:08:45.179844 [Gating] SW mode calibration
6830 11:08:45.185822 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6831 11:08:45.189214 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6832 11:08:45.196425 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6833 11:08:45.199378 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6834 11:08:45.202661 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6835 11:08:45.209374 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6836 11:08:45.212703 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 11:08:45.216247 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 11:08:45.223300 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 11:08:45.226155 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 11:08:45.229832 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6841 11:08:45.232763 Total UI for P1: 0, mck2ui 16
6842 11:08:45.236015 best dqsien dly found for B0: ( 0, 14, 24)
6843 11:08:45.239250 Total UI for P1: 0, mck2ui 16
6844 11:08:45.242777 best dqsien dly found for B1: ( 0, 14, 24)
6845 11:08:45.246145 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6846 11:08:45.249256 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6847 11:08:45.249379
6848 11:08:45.256137 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6849 11:08:45.259152 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6850 11:08:45.259277 [Gating] SW calibration Done
6851 11:08:45.262807 ==
6852 11:08:45.266067 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 11:08:45.269239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 11:08:45.269362 ==
6855 11:08:45.269477 RX Vref Scan: 0
6856 11:08:45.269584
6857 11:08:45.272837 RX Vref 0 -> 0, step: 1
6858 11:08:45.272961
6859 11:08:45.276094 RX Delay -410 -> 252, step: 16
6860 11:08:45.279780 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6861 11:08:45.282614 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6862 11:08:45.289132 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6863 11:08:45.292796 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6864 11:08:45.295789 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6865 11:08:45.299611 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6866 11:08:45.305992 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6867 11:08:45.309573 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6868 11:08:45.312247 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6869 11:08:45.315894 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6870 11:08:45.322673 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6871 11:08:45.325610 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6872 11:08:45.328889 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6873 11:08:45.332359 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6874 11:08:45.339396 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6875 11:08:45.342538 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6876 11:08:45.342663 ==
6877 11:08:45.346047 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 11:08:45.349089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 11:08:45.349170 ==
6880 11:08:45.352707 DQS Delay:
6881 11:08:45.352786 DQS0 = 43, DQS1 = 51
6882 11:08:45.355799 DQM Delay:
6883 11:08:45.355875 DQM0 = 9, DQM1 = 12
6884 11:08:45.355938 DQ Delay:
6885 11:08:45.359005 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6886 11:08:45.362655 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6887 11:08:45.366162 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6888 11:08:45.369677 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6889 11:08:45.369798
6890 11:08:45.369911
6891 11:08:45.370023 ==
6892 11:08:45.372588 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 11:08:45.375834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 11:08:45.379181 ==
6895 11:08:45.379302
6896 11:08:45.379416
6897 11:08:45.379523 TX Vref Scan disable
6898 11:08:45.382843 == TX Byte 0 ==
6899 11:08:45.385975 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6900 11:08:45.389342 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6901 11:08:45.392281 == TX Byte 1 ==
6902 11:08:45.395813 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6903 11:08:45.399050 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6904 11:08:45.399185 ==
6905 11:08:45.402651 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 11:08:45.406369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 11:08:45.409198 ==
6908 11:08:45.409323
6909 11:08:45.409431
6910 11:08:45.409543 TX Vref Scan disable
6911 11:08:45.412609 == TX Byte 0 ==
6912 11:08:45.415909 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6913 11:08:45.418964 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6914 11:08:45.422329 == TX Byte 1 ==
6915 11:08:45.425658 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6916 11:08:45.429480 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6917 11:08:45.429603
6918 11:08:45.429716 [DATLAT]
6919 11:08:45.432551 Freq=400, CH1 RK1
6920 11:08:45.432673
6921 11:08:45.435609 DATLAT Default: 0xe
6922 11:08:45.435729 0, 0xFFFF, sum = 0
6923 11:08:45.439218 1, 0xFFFF, sum = 0
6924 11:08:45.439354 2, 0xFFFF, sum = 0
6925 11:08:45.442545 3, 0xFFFF, sum = 0
6926 11:08:45.442674 4, 0xFFFF, sum = 0
6927 11:08:45.445498 5, 0xFFFF, sum = 0
6928 11:08:45.445622 6, 0xFFFF, sum = 0
6929 11:08:45.449505 7, 0xFFFF, sum = 0
6930 11:08:45.449632 8, 0xFFFF, sum = 0
6931 11:08:45.452127 9, 0xFFFF, sum = 0
6932 11:08:45.452251 10, 0xFFFF, sum = 0
6933 11:08:45.456070 11, 0xFFFF, sum = 0
6934 11:08:45.456195 12, 0xFFFF, sum = 0
6935 11:08:45.459157 13, 0x0, sum = 1
6936 11:08:45.459278 14, 0x0, sum = 2
6937 11:08:45.462584 15, 0x0, sum = 3
6938 11:08:45.462669 16, 0x0, sum = 4
6939 11:08:45.465619 best_step = 14
6940 11:08:45.465694
6941 11:08:45.465758 ==
6942 11:08:45.468989 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 11:08:45.472104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 11:08:45.472205 ==
6945 11:08:45.475424 RX Vref Scan: 0
6946 11:08:45.475500
6947 11:08:45.475567 RX Vref 0 -> 0, step: 1
6948 11:08:45.475635
6949 11:08:45.479134 RX Delay -343 -> 252, step: 8
6950 11:08:45.486506 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6951 11:08:45.490008 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6952 11:08:45.493270 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6953 11:08:45.496502 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6954 11:08:45.503832 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6955 11:08:45.506768 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6956 11:08:45.509899 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6957 11:08:45.513385 iDelay=217, Bit 7, Center -40 (-279 ~ 200) 480
6958 11:08:45.520204 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6959 11:08:45.523587 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6960 11:08:45.526456 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6961 11:08:45.530194 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6962 11:08:45.536668 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6963 11:08:45.539830 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6964 11:08:45.543330 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6965 11:08:45.549531 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6966 11:08:45.549606 ==
6967 11:08:45.553167 Dram Type= 6, Freq= 0, CH_1, rank 1
6968 11:08:45.556607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6969 11:08:45.556708 ==
6970 11:08:45.556799 DQS Delay:
6971 11:08:45.559918 DQS0 = 52, DQS1 = 56
6972 11:08:45.559988 DQM Delay:
6973 11:08:45.563595 DQM0 = 14, DQM1 = 9
6974 11:08:45.563670 DQ Delay:
6975 11:08:45.566354 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6976 11:08:45.569591 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
6977 11:08:45.573105 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6978 11:08:45.576243 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6979 11:08:45.576342
6980 11:08:45.576435
6981 11:08:45.583013 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 396 ps
6982 11:08:45.586423 CH1 RK1: MR19=C0C, MR18=6C81
6983 11:08:45.593113 CH1_RK1: MR19=0xC0C, MR18=0x6C81, DQSOSC=393, MR23=63, INC=382, DEC=254
6984 11:08:45.596510 [RxdqsGatingPostProcess] freq 400
6985 11:08:45.603267 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6986 11:08:45.603343 best DQS0 dly(2T, 0.5T) = (0, 10)
6987 11:08:45.606382 best DQS1 dly(2T, 0.5T) = (0, 10)
6988 11:08:45.609437 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6989 11:08:45.613099 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6990 11:08:45.616533 best DQS0 dly(2T, 0.5T) = (0, 10)
6991 11:08:45.619974 best DQS1 dly(2T, 0.5T) = (0, 10)
6992 11:08:45.624061 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6993 11:08:45.626420 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6994 11:08:45.629974 Pre-setting of DQS Precalculation
6995 11:08:45.633162 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6996 11:08:45.643091 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6997 11:08:45.650177 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6998 11:08:45.650300
6999 11:08:45.650435
7000 11:08:45.653257 [Calibration Summary] 800 Mbps
7001 11:08:45.653373 CH 0, Rank 0
7002 11:08:45.656156 SW Impedance : PASS
7003 11:08:45.656263 DUTY Scan : NO K
7004 11:08:45.660080 ZQ Calibration : PASS
7005 11:08:45.663196 Jitter Meter : NO K
7006 11:08:45.663318 CBT Training : PASS
7007 11:08:45.666436 Write leveling : PASS
7008 11:08:45.669686 RX DQS gating : PASS
7009 11:08:45.669805 RX DQ/DQS(RDDQC) : PASS
7010 11:08:45.672977 TX DQ/DQS : PASS
7011 11:08:45.676733 RX DATLAT : PASS
7012 11:08:45.676854 RX DQ/DQS(Engine): PASS
7013 11:08:45.679800 TX OE : NO K
7014 11:08:45.679918 All Pass.
7015 11:08:45.680029
7016 11:08:45.682797 CH 0, Rank 1
7017 11:08:45.682915 SW Impedance : PASS
7018 11:08:45.686552 DUTY Scan : NO K
7019 11:08:45.686673 ZQ Calibration : PASS
7020 11:08:45.690251 Jitter Meter : NO K
7021 11:08:45.693147 CBT Training : PASS
7022 11:08:45.693269 Write leveling : NO K
7023 11:08:45.696126 RX DQS gating : PASS
7024 11:08:45.700098 RX DQ/DQS(RDDQC) : PASS
7025 11:08:45.700219 TX DQ/DQS : PASS
7026 11:08:45.703636 RX DATLAT : PASS
7027 11:08:45.706559 RX DQ/DQS(Engine): PASS
7028 11:08:45.706680 TX OE : NO K
7029 11:08:45.709918 All Pass.
7030 11:08:45.710041
7031 11:08:45.710149 CH 1, Rank 0
7032 11:08:45.712874 SW Impedance : PASS
7033 11:08:45.712979 DUTY Scan : NO K
7034 11:08:45.716571 ZQ Calibration : PASS
7035 11:08:45.719751 Jitter Meter : NO K
7036 11:08:45.719858 CBT Training : PASS
7037 11:08:45.723637 Write leveling : PASS
7038 11:08:45.723719 RX DQS gating : PASS
7039 11:08:45.726220 RX DQ/DQS(RDDQC) : PASS
7040 11:08:45.729827 TX DQ/DQS : PASS
7041 11:08:45.729923 RX DATLAT : PASS
7042 11:08:45.733148 RX DQ/DQS(Engine): PASS
7043 11:08:45.736501 TX OE : NO K
7044 11:08:45.736622 All Pass.
7045 11:08:45.736736
7046 11:08:45.736845 CH 1, Rank 1
7047 11:08:45.739611 SW Impedance : PASS
7048 11:08:45.743405 DUTY Scan : NO K
7049 11:08:45.743528 ZQ Calibration : PASS
7050 11:08:45.746590 Jitter Meter : NO K
7051 11:08:45.749928 CBT Training : PASS
7052 11:08:45.750049 Write leveling : NO K
7053 11:08:45.753185 RX DQS gating : PASS
7054 11:08:45.756868 RX DQ/DQS(RDDQC) : PASS
7055 11:08:45.756990 TX DQ/DQS : PASS
7056 11:08:45.760029 RX DATLAT : PASS
7057 11:08:45.760149 RX DQ/DQS(Engine): PASS
7058 11:08:45.763576 TX OE : NO K
7059 11:08:45.763698 All Pass.
7060 11:08:45.763810
7061 11:08:45.767121 DramC Write-DBI off
7062 11:08:45.769898 PER_BANK_REFRESH: Hybrid Mode
7063 11:08:45.770019 TX_TRACKING: ON
7064 11:08:45.780115 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7065 11:08:45.783236 [FAST_K] Save calibration result to emmc
7066 11:08:45.786459 dramc_set_vcore_voltage set vcore to 725000
7067 11:08:45.789756 Read voltage for 1600, 0
7068 11:08:45.789882 Vio18 = 0
7069 11:08:45.793346 Vcore = 725000
7070 11:08:45.793472 Vdram = 0
7071 11:08:45.793584 Vddq = 0
7072 11:08:45.793692 Vmddr = 0
7073 11:08:45.800037 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7074 11:08:45.806584 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7075 11:08:45.806687 MEM_TYPE=3, freq_sel=13
7076 11:08:45.809913 sv_algorithm_assistance_LP4_3733
7077 11:08:45.813033 ============ PULL DRAM RESETB DOWN ============
7078 11:08:45.819715 ========== PULL DRAM RESETB DOWN end =========
7079 11:08:45.823345 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7080 11:08:45.826889 ===================================
7081 11:08:45.830253 LPDDR4 DRAM CONFIGURATION
7082 11:08:45.833260 ===================================
7083 11:08:45.833342 EX_ROW_EN[0] = 0x0
7084 11:08:45.836263 EX_ROW_EN[1] = 0x0
7085 11:08:45.836344 LP4Y_EN = 0x0
7086 11:08:45.839728 WORK_FSP = 0x1
7087 11:08:45.839809 WL = 0x5
7088 11:08:45.843114 RL = 0x5
7089 11:08:45.843195 BL = 0x2
7090 11:08:45.846735 RPST = 0x0
7091 11:08:45.846855 RD_PRE = 0x0
7092 11:08:45.849718 WR_PRE = 0x1
7093 11:08:45.849815 WR_PST = 0x1
7094 11:08:45.853640 DBI_WR = 0x0
7095 11:08:45.856321 DBI_RD = 0x0
7096 11:08:45.856464 OTF = 0x1
7097 11:08:45.859633 ===================================
7098 11:08:45.863083 ===================================
7099 11:08:45.863205 ANA top config
7100 11:08:45.866260 ===================================
7101 11:08:45.869839 DLL_ASYNC_EN = 0
7102 11:08:45.872935 ALL_SLAVE_EN = 0
7103 11:08:45.876257 NEW_RANK_MODE = 1
7104 11:08:45.876379 DLL_IDLE_MODE = 1
7105 11:08:45.879945 LP45_APHY_COMB_EN = 1
7106 11:08:45.882963 TX_ODT_DIS = 0
7107 11:08:45.886603 NEW_8X_MODE = 1
7108 11:08:45.889465 ===================================
7109 11:08:45.893079 ===================================
7110 11:08:45.896071 data_rate = 3200
7111 11:08:45.899587 CKR = 1
7112 11:08:45.899722 DQ_P2S_RATIO = 8
7113 11:08:45.902901 ===================================
7114 11:08:45.905988 CA_P2S_RATIO = 8
7115 11:08:45.909726 DQ_CA_OPEN = 0
7116 11:08:45.913295 DQ_SEMI_OPEN = 0
7117 11:08:45.916494 CA_SEMI_OPEN = 0
7118 11:08:45.916620 CA_FULL_RATE = 0
7119 11:08:45.920068 DQ_CKDIV4_EN = 0
7120 11:08:45.923193 CA_CKDIV4_EN = 0
7121 11:08:45.926632 CA_PREDIV_EN = 0
7122 11:08:45.929562 PH8_DLY = 12
7123 11:08:45.933208 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7124 11:08:45.933332 DQ_AAMCK_DIV = 4
7125 11:08:45.936451 CA_AAMCK_DIV = 4
7126 11:08:45.939753 CA_ADMCK_DIV = 4
7127 11:08:45.942928 DQ_TRACK_CA_EN = 0
7128 11:08:45.947275 CA_PICK = 1600
7129 11:08:45.949546 CA_MCKIO = 1600
7130 11:08:45.952846 MCKIO_SEMI = 0
7131 11:08:45.952966 PLL_FREQ = 3068
7132 11:08:45.956359 DQ_UI_PI_RATIO = 32
7133 11:08:45.959395 CA_UI_PI_RATIO = 0
7134 11:08:45.962814 ===================================
7135 11:08:45.966394 ===================================
7136 11:08:45.970059 memory_type:LPDDR4
7137 11:08:45.973347 GP_NUM : 10
7138 11:08:45.973430 SRAM_EN : 1
7139 11:08:45.976536 MD32_EN : 0
7140 11:08:45.980318 ===================================
7141 11:08:45.980399 [ANA_INIT] >>>>>>>>>>>>>>
7142 11:08:45.983108 <<<<<< [CONFIGURE PHASE]: ANA_TX
7143 11:08:45.986260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7144 11:08:45.989557 ===================================
7145 11:08:45.992924 data_rate = 3200,PCW = 0X7600
7146 11:08:45.996571 ===================================
7147 11:08:45.999606 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7148 11:08:46.006205 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7149 11:08:46.009658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7150 11:08:46.016208 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7151 11:08:46.019380 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7152 11:08:46.023083 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7153 11:08:46.023182 [ANA_INIT] flow start
7154 11:08:46.026458 [ANA_INIT] PLL >>>>>>>>
7155 11:08:46.029462 [ANA_INIT] PLL <<<<<<<<
7156 11:08:46.033014 [ANA_INIT] MIDPI >>>>>>>>
7157 11:08:46.033095 [ANA_INIT] MIDPI <<<<<<<<
7158 11:08:46.036373 [ANA_INIT] DLL >>>>>>>>
7159 11:08:46.039574 [ANA_INIT] DLL <<<<<<<<
7160 11:08:46.039655 [ANA_INIT] flow end
7161 11:08:46.042705 ============ LP4 DIFF to SE enter ============
7162 11:08:46.050272 ============ LP4 DIFF to SE exit ============
7163 11:08:46.050356 [ANA_INIT] <<<<<<<<<<<<<
7164 11:08:46.052857 [Flow] Enable top DCM control >>>>>
7165 11:08:46.056193 [Flow] Enable top DCM control <<<<<
7166 11:08:46.059519 Enable DLL master slave shuffle
7167 11:08:46.065935 ==============================================================
7168 11:08:46.066017 Gating Mode config
7169 11:08:46.072661 ==============================================================
7170 11:08:46.076772 Config description:
7171 11:08:46.086050 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7172 11:08:46.093096 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7173 11:08:46.096090 SELPH_MODE 0: By rank 1: By Phase
7174 11:08:46.102698 ==============================================================
7175 11:08:46.106078 GAT_TRACK_EN = 1
7176 11:08:46.106153 RX_GATING_MODE = 2
7177 11:08:46.109764 RX_GATING_TRACK_MODE = 2
7178 11:08:46.112963 SELPH_MODE = 1
7179 11:08:46.116009 PICG_EARLY_EN = 1
7180 11:08:46.119691 VALID_LAT_VALUE = 1
7181 11:08:46.126262 ==============================================================
7182 11:08:46.129420 Enter into Gating configuration >>>>
7183 11:08:46.132792 Exit from Gating configuration <<<<
7184 11:08:46.136168 Enter into DVFS_PRE_config >>>>>
7185 11:08:46.145997 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7186 11:08:46.149631 Exit from DVFS_PRE_config <<<<<
7187 11:08:46.153423 Enter into PICG configuration >>>>
7188 11:08:46.156204 Exit from PICG configuration <<<<
7189 11:08:46.159824 [RX_INPUT] configuration >>>>>
7190 11:08:46.159909 [RX_INPUT] configuration <<<<<
7191 11:08:46.166635 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7192 11:08:46.172771 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7193 11:08:46.179910 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7194 11:08:46.183563 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7195 11:08:46.190065 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7196 11:08:46.196107 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7197 11:08:46.199992 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7198 11:08:46.203472 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7199 11:08:46.209351 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7200 11:08:46.213037 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7201 11:08:46.216202 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7202 11:08:46.222919 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7203 11:08:46.226083 ===================================
7204 11:08:46.226170 LPDDR4 DRAM CONFIGURATION
7205 11:08:46.229868 ===================================
7206 11:08:46.233041 EX_ROW_EN[0] = 0x0
7207 11:08:46.233126 EX_ROW_EN[1] = 0x0
7208 11:08:46.236165 LP4Y_EN = 0x0
7209 11:08:46.236250 WORK_FSP = 0x1
7210 11:08:46.240209 WL = 0x5
7211 11:08:46.242884 RL = 0x5
7212 11:08:46.242968 BL = 0x2
7213 11:08:46.246209 RPST = 0x0
7214 11:08:46.246292 RD_PRE = 0x0
7215 11:08:46.249322 WR_PRE = 0x1
7216 11:08:46.249406 WR_PST = 0x1
7217 11:08:46.252679 DBI_WR = 0x0
7218 11:08:46.252763 DBI_RD = 0x0
7219 11:08:46.256610 OTF = 0x1
7220 11:08:46.259527 ===================================
7221 11:08:46.262746 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7222 11:08:46.266663 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7223 11:08:46.269236 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7224 11:08:46.272935 ===================================
7225 11:08:46.276538 LPDDR4 DRAM CONFIGURATION
7226 11:08:46.279310 ===================================
7227 11:08:46.282554 EX_ROW_EN[0] = 0x10
7228 11:08:46.282640 EX_ROW_EN[1] = 0x0
7229 11:08:46.285854 LP4Y_EN = 0x0
7230 11:08:46.285938 WORK_FSP = 0x1
7231 11:08:46.289625 WL = 0x5
7232 11:08:46.289709 RL = 0x5
7233 11:08:46.292771 BL = 0x2
7234 11:08:46.292855 RPST = 0x0
7235 11:08:46.296165 RD_PRE = 0x0
7236 11:08:46.296250 WR_PRE = 0x1
7237 11:08:46.299768 WR_PST = 0x1
7238 11:08:46.299853 DBI_WR = 0x0
7239 11:08:46.302950 DBI_RD = 0x0
7240 11:08:46.305850 OTF = 0x1
7241 11:08:46.305935 ===================================
7242 11:08:46.312632 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7243 11:08:46.312717 ==
7244 11:08:46.315841 Dram Type= 6, Freq= 0, CH_0, rank 0
7245 11:08:46.323062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7246 11:08:46.323147 ==
7247 11:08:46.323234 [Duty_Offset_Calibration]
7248 11:08:46.326019 B0:2 B1:-1 CA:1
7249 11:08:46.326104
7250 11:08:46.329377 [DutyScan_Calibration_Flow] k_type=0
7251 11:08:46.337970
7252 11:08:46.338054 ==CLK 0==
7253 11:08:46.341748 Final CLK duty delay cell = -4
7254 11:08:46.344857 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7255 11:08:46.348056 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7256 11:08:46.351254 [-4] AVG Duty = 4937%(X100)
7257 11:08:46.351341
7258 11:08:46.354331 CH0 CLK Duty spec in!! Max-Min= 187%
7259 11:08:46.358059 [DutyScan_Calibration_Flow] ====Done====
7260 11:08:46.358143
7261 11:08:46.361224 [DutyScan_Calibration_Flow] k_type=1
7262 11:08:46.377618
7263 11:08:46.377702 ==DQS 0 ==
7264 11:08:46.380907 Final DQS duty delay cell = 0
7265 11:08:46.383962 [0] MAX Duty = 5125%(X100), DQS PI = 56
7266 11:08:46.387337 [0] MIN Duty = 5000%(X100), DQS PI = 14
7267 11:08:46.390799 [0] AVG Duty = 5062%(X100)
7268 11:08:46.390909
7269 11:08:46.390997 ==DQS 1 ==
7270 11:08:46.393923 Final DQS duty delay cell = -4
7271 11:08:46.397576 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7272 11:08:46.400751 [-4] MIN Duty = 5031%(X100), DQS PI = 20
7273 11:08:46.404506 [-4] AVG Duty = 5062%(X100)
7274 11:08:46.404591
7275 11:08:46.407672 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7276 11:08:46.407757
7277 11:08:46.411193 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7278 11:08:46.414074 [DutyScan_Calibration_Flow] ====Done====
7279 11:08:46.414159
7280 11:08:46.417495 [DutyScan_Calibration_Flow] k_type=3
7281 11:08:46.434723
7282 11:08:46.434835 ==DQM 0 ==
7283 11:08:46.438306 Final DQM duty delay cell = 0
7284 11:08:46.441493 [0] MAX Duty = 5000%(X100), DQS PI = 18
7285 11:08:46.445105 [0] MIN Duty = 4875%(X100), DQS PI = 4
7286 11:08:46.445190 [0] AVG Duty = 4937%(X100)
7287 11:08:46.448091
7288 11:08:46.448177 ==DQM 1 ==
7289 11:08:46.451789 Final DQM duty delay cell = 0
7290 11:08:46.454958 [0] MAX Duty = 5187%(X100), DQS PI = 58
7291 11:08:46.458593 [0] MIN Duty = 4969%(X100), DQS PI = 18
7292 11:08:46.461329 [0] AVG Duty = 5078%(X100)
7293 11:08:46.461407
7294 11:08:46.464514 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7295 11:08:46.464591
7296 11:08:46.468090 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7297 11:08:46.471742 [DutyScan_Calibration_Flow] ====Done====
7298 11:08:46.471820
7299 11:08:46.474629 [DutyScan_Calibration_Flow] k_type=2
7300 11:08:46.492157
7301 11:08:46.492242 ==DQ 0 ==
7302 11:08:46.495217 Final DQ duty delay cell = 0
7303 11:08:46.498957 [0] MAX Duty = 5156%(X100), DQS PI = 0
7304 11:08:46.502145 [0] MIN Duty = 5031%(X100), DQS PI = 12
7305 11:08:46.502259 [0] AVG Duty = 5093%(X100)
7306 11:08:46.502329
7307 11:08:46.505834 ==DQ 1 ==
7308 11:08:46.508569 Final DQ duty delay cell = 0
7309 11:08:46.512285 [0] MAX Duty = 5031%(X100), DQS PI = 30
7310 11:08:46.515298 [0] MIN Duty = 4907%(X100), DQS PI = 18
7311 11:08:46.515380 [0] AVG Duty = 4969%(X100)
7312 11:08:46.515447
7313 11:08:46.518546 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7314 11:08:46.518628
7315 11:08:46.525274 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7316 11:08:46.528770 [DutyScan_Calibration_Flow] ====Done====
7317 11:08:46.528851 ==
7318 11:08:46.532024 Dram Type= 6, Freq= 0, CH_1, rank 0
7319 11:08:46.535329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7320 11:08:46.535411 ==
7321 11:08:46.538838 [Duty_Offset_Calibration]
7322 11:08:46.538920 B0:1 B1:1 CA:2
7323 11:08:46.538985
7324 11:08:46.541716 [DutyScan_Calibration_Flow] k_type=0
7325 11:08:46.552389
7326 11:08:46.552470 ==CLK 0==
7327 11:08:46.555288 Final CLK duty delay cell = 0
7328 11:08:46.558815 [0] MAX Duty = 5187%(X100), DQS PI = 24
7329 11:08:46.562252 [0] MIN Duty = 4938%(X100), DQS PI = 50
7330 11:08:46.562334 [0] AVG Duty = 5062%(X100)
7331 11:08:46.565165
7332 11:08:46.568785 CH1 CLK Duty spec in!! Max-Min= 249%
7333 11:08:46.572134 [DutyScan_Calibration_Flow] ====Done====
7334 11:08:46.572215
7335 11:08:46.575386 [DutyScan_Calibration_Flow] k_type=1
7336 11:08:46.592135
7337 11:08:46.592217 ==DQS 0 ==
7338 11:08:46.595569 Final DQS duty delay cell = 0
7339 11:08:46.598372 [0] MAX Duty = 5062%(X100), DQS PI = 22
7340 11:08:46.602014 [0] MIN Duty = 4813%(X100), DQS PI = 50
7341 11:08:46.605171 [0] AVG Duty = 4937%(X100)
7342 11:08:46.605253
7343 11:08:46.605319 ==DQS 1 ==
7344 11:08:46.608459 Final DQS duty delay cell = 0
7345 11:08:46.611911 [0] MAX Duty = 5062%(X100), DQS PI = 58
7346 11:08:46.614964 [0] MIN Duty = 4938%(X100), DQS PI = 12
7347 11:08:46.615046 [0] AVG Duty = 5000%(X100)
7348 11:08:46.618819
7349 11:08:46.622055 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7350 11:08:46.622151
7351 11:08:46.626104 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7352 11:08:46.628250 [DutyScan_Calibration_Flow] ====Done====
7353 11:08:46.628332
7354 11:08:46.631914 [DutyScan_Calibration_Flow] k_type=3
7355 11:08:46.648449
7356 11:08:46.648530 ==DQM 0 ==
7357 11:08:46.651994 Final DQM duty delay cell = 0
7358 11:08:46.655105 [0] MAX Duty = 5187%(X100), DQS PI = 20
7359 11:08:46.658526 [0] MIN Duty = 4844%(X100), DQS PI = 50
7360 11:08:46.662075 [0] AVG Duty = 5015%(X100)
7361 11:08:46.662157
7362 11:08:46.662222 ==DQM 1 ==
7363 11:08:46.665379 Final DQM duty delay cell = 0
7364 11:08:46.668756 [0] MAX Duty = 5125%(X100), DQS PI = 10
7365 11:08:46.671759 [0] MIN Duty = 4875%(X100), DQS PI = 22
7366 11:08:46.675489 [0] AVG Duty = 5000%(X100)
7367 11:08:46.675570
7368 11:08:46.678725 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7369 11:08:46.678807
7370 11:08:46.682288 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7371 11:08:46.685429 [DutyScan_Calibration_Flow] ====Done====
7372 11:08:46.685510
7373 11:08:46.688632 [DutyScan_Calibration_Flow] k_type=2
7374 11:08:46.705530
7375 11:08:46.705611 ==DQ 0 ==
7376 11:08:46.709280 Final DQ duty delay cell = 0
7377 11:08:46.712247 [0] MAX Duty = 5156%(X100), DQS PI = 20
7378 11:08:46.715556 [0] MIN Duty = 4907%(X100), DQS PI = 52
7379 11:08:46.715628 [0] AVG Duty = 5031%(X100)
7380 11:08:46.719417
7381 11:08:46.719514 ==DQ 1 ==
7382 11:08:46.722112 Final DQ duty delay cell = 0
7383 11:08:46.725151 [0] MAX Duty = 5093%(X100), DQS PI = 6
7384 11:08:46.729273 [0] MIN Duty = 5031%(X100), DQS PI = 0
7385 11:08:46.729352 [0] AVG Duty = 5062%(X100)
7386 11:08:46.729415
7387 11:08:46.732525 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7388 11:08:46.732600
7389 11:08:46.735686 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7390 11:08:46.742236 [DutyScan_Calibration_Flow] ====Done====
7391 11:08:46.745926 nWR fixed to 30
7392 11:08:46.746004 [ModeRegInit_LP4] CH0 RK0
7393 11:08:46.749020 [ModeRegInit_LP4] CH0 RK1
7394 11:08:46.752232 [ModeRegInit_LP4] CH1 RK0
7395 11:08:46.752308 [ModeRegInit_LP4] CH1 RK1
7396 11:08:46.755360 match AC timing 5
7397 11:08:46.758636 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7398 11:08:46.762156 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7399 11:08:46.768609 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7400 11:08:46.771799 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7401 11:08:46.778646 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7402 11:08:46.778723 [MiockJmeterHQA]
7403 11:08:46.778792
7404 11:08:46.782363 [DramcMiockJmeter] u1RxGatingPI = 0
7405 11:08:46.785244 0 : 4254, 4029
7406 11:08:46.785344 4 : 4257, 4032
7407 11:08:46.785435 8 : 4258, 4031
7408 11:08:46.788744 12 : 4252, 4027
7409 11:08:46.788836 16 : 4255, 4029
7410 11:08:46.792058 20 : 4365, 4140
7411 11:08:46.792129 24 : 4255, 4030
7412 11:08:46.795457 28 : 4368, 4140
7413 11:08:46.795526 32 : 4363, 4138
7414 11:08:46.795591 36 : 4250, 4025
7415 11:08:46.798546 40 : 4250, 4027
7416 11:08:46.798645 44 : 4250, 4027
7417 11:08:46.802329 48 : 4363, 4140
7418 11:08:46.802455 52 : 4255, 4029
7419 11:08:46.805705 56 : 4250, 4027
7420 11:08:46.805775 60 : 4253, 4029
7421 11:08:46.808617 64 : 4249, 4027
7422 11:08:46.808708 68 : 4252, 4029
7423 11:08:46.808772 72 : 4363, 4140
7424 11:08:46.812012 76 : 4366, 4140
7425 11:08:46.812081 80 : 4365, 4142
7426 11:08:46.815618 84 : 4362, 4140
7427 11:08:46.815716 88 : 4253, 4027
7428 11:08:46.818582 92 : 4254, 4030
7429 11:08:46.818653 96 : 4363, 3385
7430 11:08:46.818714 100 : 4360, 0
7431 11:08:46.822564 104 : 4361, 0
7432 11:08:46.822633 108 : 4252, 0
7433 11:08:46.825499 112 : 4361, 0
7434 11:08:46.825574 116 : 4252, 0
7435 11:08:46.825636 120 : 4253, 0
7436 11:08:46.829097 124 : 4250, 0
7437 11:08:46.829176 128 : 4258, 0
7438 11:08:46.831816 132 : 4360, 0
7439 11:08:46.831889 136 : 4252, 0
7440 11:08:46.831951 140 : 4252, 0
7441 11:08:46.835556 144 : 4360, 0
7442 11:08:46.835625 148 : 4253, 0
7443 11:08:46.835685 152 : 4363, 0
7444 11:08:46.838609 156 : 4250, 0
7445 11:08:46.838711 160 : 4250, 0
7446 11:08:46.841882 164 : 4250, 0
7447 11:08:46.841952 168 : 4250, 0
7448 11:08:46.842016 172 : 4252, 0
7449 11:08:46.845690 176 : 4250, 0
7450 11:08:46.845768 180 : 4250, 0
7451 11:08:46.848574 184 : 4250, 0
7452 11:08:46.848646 188 : 4254, 0
7453 11:08:46.848707 192 : 4250, 0
7454 11:08:46.851749 196 : 4253, 0
7455 11:08:46.851820 200 : 4360, 0
7456 11:08:46.855211 204 : 4361, 0
7457 11:08:46.855310 208 : 4250, 0
7458 11:08:46.855401 212 : 4365, 142
7459 11:08:46.858817 216 : 4250, 3747
7460 11:08:46.858891 220 : 4360, 4137
7461 11:08:46.861819 224 : 4361, 4137
7462 11:08:46.861888 228 : 4361, 4137
7463 11:08:46.865714 232 : 4250, 4027
7464 11:08:46.865816 236 : 4252, 4029
7465 11:08:46.869058 240 : 4361, 4137
7466 11:08:46.869127 244 : 4363, 4140
7467 11:08:46.872266 248 : 4250, 4026
7468 11:08:46.872338 252 : 4252, 4029
7469 11:08:46.872400 256 : 4365, 4143
7470 11:08:46.875878 260 : 4250, 4027
7471 11:08:46.875949 264 : 4363, 4140
7472 11:08:46.878669 268 : 4255, 4030
7473 11:08:46.878781 272 : 4360, 4137
7474 11:08:46.882121 276 : 4252, 4030
7475 11:08:46.882225 280 : 4249, 4027
7476 11:08:46.885339 284 : 4253, 4029
7477 11:08:46.885412 288 : 4255, 4029
7478 11:08:46.888991 292 : 4363, 4140
7479 11:08:46.889059 296 : 4250, 4027
7480 11:08:46.889118 300 : 4250, 4027
7481 11:08:46.892066 304 : 4255, 4029
7482 11:08:46.892134 308 : 4250, 4027
7483 11:08:46.895523 312 : 4363, 4138
7484 11:08:46.895607 316 : 4253, 4027
7485 11:08:46.898937 320 : 4255, 4029
7486 11:08:46.899021 324 : 4252, 4029
7487 11:08:46.902628 328 : 4250, 4027
7488 11:08:46.902738 332 : 4250, 2934
7489 11:08:46.905763 336 : 4253, 22
7490 11:08:46.905847
7491 11:08:46.905913 MIOCK jitter meter ch=0
7492 11:08:46.905974
7493 11:08:46.909008 1T = (336-100) = 236 dly cells
7494 11:08:46.915694 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7495 11:08:46.915802 ==
7496 11:08:46.918654 Dram Type= 6, Freq= 0, CH_0, rank 0
7497 11:08:46.921878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7498 11:08:46.921953 ==
7499 11:08:46.928422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7500 11:08:46.932413 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7501 11:08:46.935289 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7502 11:08:46.941919 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7503 11:08:46.952281 [CA 0] Center 44 (14~75) winsize 62
7504 11:08:46.956048 [CA 1] Center 44 (14~74) winsize 61
7505 11:08:46.958629 [CA 2] Center 39 (10~68) winsize 59
7506 11:08:46.965126 [CA 3] Center 39 (10~68) winsize 59
7507 11:08:46.965403 [CA 4] Center 37 (7~67) winsize 61
7508 11:08:46.968766 [CA 5] Center 37 (7~67) winsize 61
7509 11:08:46.968836
7510 11:08:46.972245 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7511 11:08:46.972312
7512 11:08:46.975534 [CATrainingPosCal] consider 1 rank data
7513 11:08:46.978680 u2DelayCellTimex100 = 275/100 ps
7514 11:08:46.982515 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7515 11:08:46.988682 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7516 11:08:46.991618 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7517 11:08:46.995228 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7518 11:08:46.998819 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7519 11:08:47.002465 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7520 11:08:47.002540
7521 11:08:47.005186 CA PerBit enable=1, Macro0, CA PI delay=37
7522 11:08:47.005261
7523 11:08:47.008819 [CBTSetCACLKResult] CA Dly = 37
7524 11:08:47.011998 CS Dly: 10 (0~41)
7525 11:08:47.015025 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7526 11:08:47.018301 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7527 11:08:47.018370 ==
7528 11:08:47.022239 Dram Type= 6, Freq= 0, CH_0, rank 1
7529 11:08:47.024962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7530 11:08:47.028646 ==
7531 11:08:47.032009 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7532 11:08:47.035141 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7533 11:08:47.041664 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7534 11:08:47.045012 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7535 11:08:47.056084 [CA 0] Center 44 (14~74) winsize 61
7536 11:08:47.059686 [CA 1] Center 43 (13~74) winsize 62
7537 11:08:47.062773 [CA 2] Center 39 (10~69) winsize 60
7538 11:08:47.065797 [CA 3] Center 38 (9~68) winsize 60
7539 11:08:47.069109 [CA 4] Center 37 (7~67) winsize 61
7540 11:08:47.072734 [CA 5] Center 37 (7~67) winsize 61
7541 11:08:47.072817
7542 11:08:47.076031 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7543 11:08:47.076130
7544 11:08:47.078983 [CATrainingPosCal] consider 2 rank data
7545 11:08:47.083030 u2DelayCellTimex100 = 275/100 ps
7546 11:08:47.085855 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7547 11:08:47.092301 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7548 11:08:47.095680 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7549 11:08:47.098739 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7550 11:08:47.102264 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7551 11:08:47.105570 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7552 11:08:47.105646
7553 11:08:47.109430 CA PerBit enable=1, Macro0, CA PI delay=37
7554 11:08:47.109509
7555 11:08:47.112741 [CBTSetCACLKResult] CA Dly = 37
7556 11:08:47.115840 CS Dly: 11 (0~44)
7557 11:08:47.119005 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7558 11:08:47.122177 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7559 11:08:47.122308
7560 11:08:47.125340 ----->DramcWriteLeveling(PI) begin...
7561 11:08:47.125465 ==
7562 11:08:47.128998 Dram Type= 6, Freq= 0, CH_0, rank 0
7563 11:08:47.136053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7564 11:08:47.136184 ==
7565 11:08:47.138776 Write leveling (Byte 0): 32 => 32
7566 11:08:47.138933 Write leveling (Byte 1): 27 => 27
7567 11:08:47.142152 DramcWriteLeveling(PI) end<-----
7568 11:08:47.142277
7569 11:08:47.142392 ==
7570 11:08:47.145487 Dram Type= 6, Freq= 0, CH_0, rank 0
7571 11:08:47.152570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 11:08:47.152700 ==
7573 11:08:47.155873 [Gating] SW mode calibration
7574 11:08:47.162311 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7575 11:08:47.166047 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7576 11:08:47.172136 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 11:08:47.175436 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 11:08:47.179262 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 11:08:47.182124 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 11:08:47.188997 1 4 16 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
7581 11:08:47.192001 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7582 11:08:47.195382 1 4 24 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
7583 11:08:47.202122 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 11:08:47.205928 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7585 11:08:47.209286 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7586 11:08:47.215506 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 11:08:47.218630 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 11:08:47.222529 1 5 16 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7589 11:08:47.228928 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
7590 11:08:47.232466 1 5 24 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
7591 11:08:47.235711 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 11:08:47.242298 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 11:08:47.245993 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 11:08:47.248590 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 11:08:47.255356 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 11:08:47.258504 1 6 16 | B1->B0 | 2323 3635 | 0 1 | (0 0) (1 1)
7597 11:08:47.261770 1 6 20 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
7598 11:08:47.268824 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
7599 11:08:47.271751 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 11:08:47.275568 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 11:08:47.282242 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 11:08:47.285617 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 11:08:47.288938 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 11:08:47.295594 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7605 11:08:47.298579 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7606 11:08:47.301656 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 11:08:47.305325 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 11:08:47.311928 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 11:08:47.315181 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 11:08:47.319042 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 11:08:47.325966 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 11:08:47.329107 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 11:08:47.332172 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 11:08:47.338878 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 11:08:47.341950 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 11:08:47.345359 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 11:08:47.351909 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 11:08:47.355581 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 11:08:47.358581 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7620 11:08:47.365480 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7621 11:08:47.368757 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7622 11:08:47.372365 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 11:08:47.375058 Total UI for P1: 0, mck2ui 16
7624 11:08:47.378953 best dqsien dly found for B0: ( 1, 9, 16)
7625 11:08:47.382281 Total UI for P1: 0, mck2ui 16
7626 11:08:47.384927 best dqsien dly found for B1: ( 1, 9, 20)
7627 11:08:47.388359 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7628 11:08:47.392659 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7629 11:08:47.392770
7630 11:08:47.398905 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7631 11:08:47.402063 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7632 11:08:47.402157 [Gating] SW calibration Done
7633 11:08:47.405069 ==
7634 11:08:47.408313 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 11:08:47.411596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 11:08:47.411712 ==
7637 11:08:47.411799 RX Vref Scan: 0
7638 11:08:47.411877
7639 11:08:47.414842 RX Vref 0 -> 0, step: 1
7640 11:08:47.414932
7641 11:08:47.418210 RX Delay 0 -> 252, step: 8
7642 11:08:47.421764 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7643 11:08:47.425423 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7644 11:08:47.428829 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7645 11:08:47.434923 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
7646 11:08:47.438960 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7647 11:08:47.441697 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7648 11:08:47.444999 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7649 11:08:47.448185 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7650 11:08:47.454921 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7651 11:08:47.458653 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7652 11:08:47.462038 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7653 11:08:47.465433 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7654 11:08:47.469201 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7655 11:08:47.475306 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7656 11:08:47.478940 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7657 11:08:47.481597 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7658 11:08:47.481674 ==
7659 11:08:47.485234 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 11:08:47.488615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 11:08:47.488700 ==
7662 11:08:47.491826 DQS Delay:
7663 11:08:47.491910 DQS0 = 0, DQS1 = 0
7664 11:08:47.495607 DQM Delay:
7665 11:08:47.495691 DQM0 = 132, DQM1 = 125
7666 11:08:47.495759 DQ Delay:
7667 11:08:47.498564 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
7668 11:08:47.501863 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7669 11:08:47.508150 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7670 11:08:47.511713 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7671 11:08:47.511797
7672 11:08:47.511864
7673 11:08:47.511927 ==
7674 11:08:47.514894 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 11:08:47.518526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 11:08:47.518610 ==
7677 11:08:47.518678
7678 11:08:47.518741
7679 11:08:47.521632 TX Vref Scan disable
7680 11:08:47.525040 == TX Byte 0 ==
7681 11:08:47.528735 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7682 11:08:47.531764 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7683 11:08:47.535114 == TX Byte 1 ==
7684 11:08:47.538312 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7685 11:08:47.541975 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7686 11:08:47.542059 ==
7687 11:08:47.545511 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 11:08:47.548624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 11:08:47.548713 ==
7690 11:08:47.564112
7691 11:08:47.567733 TX Vref early break, caculate TX vref
7692 11:08:47.571190 TX Vref=16, minBit 1, minWin=21, winSum=360
7693 11:08:47.574531 TX Vref=18, minBit 1, minWin=22, winSum=370
7694 11:08:47.577666 TX Vref=20, minBit 7, minWin=22, winSum=375
7695 11:08:47.581640 TX Vref=22, minBit 4, minWin=23, winSum=393
7696 11:08:47.584712 TX Vref=24, minBit 0, minWin=24, winSum=396
7697 11:08:47.591118 TX Vref=26, minBit 8, minWin=24, winSum=406
7698 11:08:47.594606 TX Vref=28, minBit 0, minWin=25, winSum=415
7699 11:08:47.598109 TX Vref=30, minBit 0, minWin=25, winSum=413
7700 11:08:47.601225 TX Vref=32, minBit 4, minWin=24, winSum=412
7701 11:08:47.604738 TX Vref=34, minBit 4, minWin=23, winSum=395
7702 11:08:47.607980 TX Vref=36, minBit 0, minWin=23, winSum=389
7703 11:08:47.614954 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
7704 11:08:47.615037
7705 11:08:47.618533 Final TX Range 0 Vref 28
7706 11:08:47.618630
7707 11:08:47.618696 ==
7708 11:08:47.621206 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 11:08:47.624443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 11:08:47.624526 ==
7711 11:08:47.624592
7712 11:08:47.624652
7713 11:08:47.627796 TX Vref Scan disable
7714 11:08:47.635359 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7715 11:08:47.635442 == TX Byte 0 ==
7716 11:08:47.637713 u2DelayCellOfst[0]=17 cells (5 PI)
7717 11:08:47.641870 u2DelayCellOfst[1]=21 cells (6 PI)
7718 11:08:47.644500 u2DelayCellOfst[2]=14 cells (4 PI)
7719 11:08:47.648196 u2DelayCellOfst[3]=17 cells (5 PI)
7720 11:08:47.651172 u2DelayCellOfst[4]=10 cells (3 PI)
7721 11:08:47.654325 u2DelayCellOfst[5]=0 cells (0 PI)
7722 11:08:47.658029 u2DelayCellOfst[6]=21 cells (6 PI)
7723 11:08:47.661302 u2DelayCellOfst[7]=21 cells (6 PI)
7724 11:08:47.665244 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7725 11:08:47.667983 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7726 11:08:47.671853 == TX Byte 1 ==
7727 11:08:47.671935 u2DelayCellOfst[8]=0 cells (0 PI)
7728 11:08:47.674662 u2DelayCellOfst[9]=0 cells (0 PI)
7729 11:08:47.677587 u2DelayCellOfst[10]=7 cells (2 PI)
7730 11:08:47.681251 u2DelayCellOfst[11]=0 cells (0 PI)
7731 11:08:47.684400 u2DelayCellOfst[12]=14 cells (4 PI)
7732 11:08:47.688063 u2DelayCellOfst[13]=10 cells (3 PI)
7733 11:08:47.691525 u2DelayCellOfst[14]=17 cells (5 PI)
7734 11:08:47.694321 u2DelayCellOfst[15]=14 cells (4 PI)
7735 11:08:47.698107 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7736 11:08:47.704414 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7737 11:08:47.704497 DramC Write-DBI on
7738 11:08:47.704563 ==
7739 11:08:47.707869 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 11:08:47.710915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 11:08:47.714748 ==
7742 11:08:47.714831
7743 11:08:47.714896
7744 11:08:47.714957 TX Vref Scan disable
7745 11:08:47.717889 == TX Byte 0 ==
7746 11:08:47.721449 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7747 11:08:47.724879 == TX Byte 1 ==
7748 11:08:47.727876 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7749 11:08:47.731702 DramC Write-DBI off
7750 11:08:47.731784
7751 11:08:47.731849 [DATLAT]
7752 11:08:47.731910 Freq=1600, CH0 RK0
7753 11:08:47.731970
7754 11:08:47.734207 DATLAT Default: 0xf
7755 11:08:47.734304 0, 0xFFFF, sum = 0
7756 11:08:47.737846 1, 0xFFFF, sum = 0
7757 11:08:47.741046 2, 0xFFFF, sum = 0
7758 11:08:47.741147 3, 0xFFFF, sum = 0
7759 11:08:47.744707 4, 0xFFFF, sum = 0
7760 11:08:47.744850 5, 0xFFFF, sum = 0
7761 11:08:47.747941 6, 0xFFFF, sum = 0
7762 11:08:47.748039 7, 0xFFFF, sum = 0
7763 11:08:47.750929 8, 0xFFFF, sum = 0
7764 11:08:47.751107 9, 0xFFFF, sum = 0
7765 11:08:47.754545 10, 0xFFFF, sum = 0
7766 11:08:47.754629 11, 0xFFFF, sum = 0
7767 11:08:47.757908 12, 0xFFFF, sum = 0
7768 11:08:47.758028 13, 0xFFFF, sum = 0
7769 11:08:47.761459 14, 0x0, sum = 1
7770 11:08:47.761533 15, 0x0, sum = 2
7771 11:08:47.764765 16, 0x0, sum = 3
7772 11:08:47.764844 17, 0x0, sum = 4
7773 11:08:47.767818 best_step = 15
7774 11:08:47.767889
7775 11:08:47.767969 ==
7776 11:08:47.771231 Dram Type= 6, Freq= 0, CH_0, rank 0
7777 11:08:47.774491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7778 11:08:47.774570 ==
7779 11:08:47.774650 RX Vref Scan: 1
7780 11:08:47.777858
7781 11:08:47.777938 Set Vref Range= 24 -> 127
7782 11:08:47.778042
7783 11:08:47.781223 RX Vref 24 -> 127, step: 1
7784 11:08:47.781302
7785 11:08:47.784639 RX Delay 11 -> 252, step: 4
7786 11:08:47.784712
7787 11:08:47.788106 Set Vref, RX VrefLevel [Byte0]: 24
7788 11:08:47.791031 [Byte1]: 24
7789 11:08:47.791112
7790 11:08:47.794624 Set Vref, RX VrefLevel [Byte0]: 25
7791 11:08:47.798084 [Byte1]: 25
7792 11:08:47.798175
7793 11:08:47.801256 Set Vref, RX VrefLevel [Byte0]: 26
7794 11:08:47.804932 [Byte1]: 26
7795 11:08:47.808308
7796 11:08:47.808387 Set Vref, RX VrefLevel [Byte0]: 27
7797 11:08:47.811365 [Byte1]: 27
7798 11:08:47.815811
7799 11:08:47.815888 Set Vref, RX VrefLevel [Byte0]: 28
7800 11:08:47.819369 [Byte1]: 28
7801 11:08:47.823358
7802 11:08:47.823434 Set Vref, RX VrefLevel [Byte0]: 29
7803 11:08:47.827171 [Byte1]: 29
7804 11:08:47.831019
7805 11:08:47.831099 Set Vref, RX VrefLevel [Byte0]: 30
7806 11:08:47.834741 [Byte1]: 30
7807 11:08:47.838799
7808 11:08:47.838875 Set Vref, RX VrefLevel [Byte0]: 31
7809 11:08:47.842461 [Byte1]: 31
7810 11:08:47.847134
7811 11:08:47.847213 Set Vref, RX VrefLevel [Byte0]: 32
7812 11:08:47.849604 [Byte1]: 32
7813 11:08:47.854279
7814 11:08:47.854386 Set Vref, RX VrefLevel [Byte0]: 33
7815 11:08:47.857240 [Byte1]: 33
7816 11:08:47.861673
7817 11:08:47.861750 Set Vref, RX VrefLevel [Byte0]: 34
7818 11:08:47.864893 [Byte1]: 34
7819 11:08:47.869337
7820 11:08:47.869418 Set Vref, RX VrefLevel [Byte0]: 35
7821 11:08:47.872799 [Byte1]: 35
7822 11:08:47.877118
7823 11:08:47.877199 Set Vref, RX VrefLevel [Byte0]: 36
7824 11:08:47.880410 [Byte1]: 36
7825 11:08:47.884536
7826 11:08:47.884617 Set Vref, RX VrefLevel [Byte0]: 37
7827 11:08:47.888040 [Byte1]: 37
7828 11:08:47.892088
7829 11:08:47.892167 Set Vref, RX VrefLevel [Byte0]: 38
7830 11:08:47.895090 [Byte1]: 38
7831 11:08:47.899630
7832 11:08:47.899707 Set Vref, RX VrefLevel [Byte0]: 39
7833 11:08:47.903550 [Byte1]: 39
7834 11:08:47.907434
7835 11:08:47.907531 Set Vref, RX VrefLevel [Byte0]: 40
7836 11:08:47.910381 [Byte1]: 40
7837 11:08:47.914964
7838 11:08:47.915040 Set Vref, RX VrefLevel [Byte0]: 41
7839 11:08:47.918098 [Byte1]: 41
7840 11:08:47.922978
7841 11:08:47.923059 Set Vref, RX VrefLevel [Byte0]: 42
7842 11:08:47.925844 [Byte1]: 42
7843 11:08:47.929859
7844 11:08:47.929955 Set Vref, RX VrefLevel [Byte0]: 43
7845 11:08:47.933737 [Byte1]: 43
7846 11:08:47.938167
7847 11:08:47.938248 Set Vref, RX VrefLevel [Byte0]: 44
7848 11:08:47.940702 [Byte1]: 44
7849 11:08:47.945093
7850 11:08:47.945171 Set Vref, RX VrefLevel [Byte0]: 45
7851 11:08:47.948510 [Byte1]: 45
7852 11:08:47.952930
7853 11:08:47.953007 Set Vref, RX VrefLevel [Byte0]: 46
7854 11:08:47.956954 [Byte1]: 46
7855 11:08:47.960754
7856 11:08:47.960836 Set Vref, RX VrefLevel [Byte0]: 47
7857 11:08:47.963967 [Byte1]: 47
7858 11:08:47.968219
7859 11:08:47.968297 Set Vref, RX VrefLevel [Byte0]: 48
7860 11:08:47.971761 [Byte1]: 48
7861 11:08:47.975632
7862 11:08:47.975708 Set Vref, RX VrefLevel [Byte0]: 49
7863 11:08:47.979086 [Byte1]: 49
7864 11:08:47.983458
7865 11:08:47.983538 Set Vref, RX VrefLevel [Byte0]: 50
7866 11:08:47.986571 [Byte1]: 50
7867 11:08:47.991313
7868 11:08:47.991389 Set Vref, RX VrefLevel [Byte0]: 51
7869 11:08:47.994550 [Byte1]: 51
7870 11:08:47.998680
7871 11:08:47.998757 Set Vref, RX VrefLevel [Byte0]: 52
7872 11:08:48.001796 [Byte1]: 52
7873 11:08:48.006257
7874 11:08:48.006335 Set Vref, RX VrefLevel [Byte0]: 53
7875 11:08:48.009683 [Byte1]: 53
7876 11:08:48.013710
7877 11:08:48.013839 Set Vref, RX VrefLevel [Byte0]: 54
7878 11:08:48.017381 [Byte1]: 54
7879 11:08:48.021662
7880 11:08:48.021743 Set Vref, RX VrefLevel [Byte0]: 55
7881 11:08:48.024982 [Byte1]: 55
7882 11:08:48.029073
7883 11:08:48.029186 Set Vref, RX VrefLevel [Byte0]: 56
7884 11:08:48.032504 [Byte1]: 56
7885 11:08:48.037146
7886 11:08:48.037227 Set Vref, RX VrefLevel [Byte0]: 57
7887 11:08:48.040418 [Byte1]: 57
7888 11:08:48.044217
7889 11:08:48.044298 Set Vref, RX VrefLevel [Byte0]: 58
7890 11:08:48.047958 [Byte1]: 58
7891 11:08:48.052159
7892 11:08:48.052240 Set Vref, RX VrefLevel [Byte0]: 59
7893 11:08:48.055409 [Byte1]: 59
7894 11:08:48.059786
7895 11:08:48.059866 Set Vref, RX VrefLevel [Byte0]: 60
7896 11:08:48.062944 [Byte1]: 60
7897 11:08:48.067366
7898 11:08:48.067448 Set Vref, RX VrefLevel [Byte0]: 61
7899 11:08:48.070652 [Byte1]: 61
7900 11:08:48.075018
7901 11:08:48.075100 Set Vref, RX VrefLevel [Byte0]: 62
7902 11:08:48.078604 [Byte1]: 62
7903 11:08:48.082113
7904 11:08:48.082226 Set Vref, RX VrefLevel [Byte0]: 63
7905 11:08:48.085757 [Byte1]: 63
7906 11:08:48.090357
7907 11:08:48.090461 Set Vref, RX VrefLevel [Byte0]: 64
7908 11:08:48.093169 [Byte1]: 64
7909 11:08:48.098213
7910 11:08:48.098312 Set Vref, RX VrefLevel [Byte0]: 65
7911 11:08:48.101251 [Byte1]: 65
7912 11:08:48.105000
7913 11:08:48.105084 Set Vref, RX VrefLevel [Byte0]: 66
7914 11:08:48.108279 [Byte1]: 66
7915 11:08:48.112983
7916 11:08:48.113064 Set Vref, RX VrefLevel [Byte0]: 67
7917 11:08:48.116502 [Byte1]: 67
7918 11:08:48.120252
7919 11:08:48.120333 Set Vref, RX VrefLevel [Byte0]: 68
7920 11:08:48.123509 [Byte1]: 68
7921 11:08:48.128333
7922 11:08:48.128415 Set Vref, RX VrefLevel [Byte0]: 69
7923 11:08:48.132019 [Byte1]: 69
7924 11:08:48.135572
7925 11:08:48.135654 Set Vref, RX VrefLevel [Byte0]: 70
7926 11:08:48.139081 [Byte1]: 70
7927 11:08:48.143273
7928 11:08:48.143354 Set Vref, RX VrefLevel [Byte0]: 71
7929 11:08:48.146608 [Byte1]: 71
7930 11:08:48.150987
7931 11:08:48.151068 Set Vref, RX VrefLevel [Byte0]: 72
7932 11:08:48.154021 [Byte1]: 72
7933 11:08:48.158324
7934 11:08:48.158451 Set Vref, RX VrefLevel [Byte0]: 73
7935 11:08:48.161872 [Byte1]: 73
7936 11:08:48.166224
7937 11:08:48.166305 Set Vref, RX VrefLevel [Byte0]: 74
7938 11:08:48.169972 [Byte1]: 74
7939 11:08:48.173884
7940 11:08:48.173969 Set Vref, RX VrefLevel [Byte0]: 75
7941 11:08:48.176797 [Byte1]: 75
7942 11:08:48.181829
7943 11:08:48.181911 Set Vref, RX VrefLevel [Byte0]: 76
7944 11:08:48.184496 [Byte1]: 76
7945 11:08:48.188827
7946 11:08:48.188908 Final RX Vref Byte 0 = 62 to rank0
7947 11:08:48.192358 Final RX Vref Byte 1 = 63 to rank0
7948 11:08:48.195399 Final RX Vref Byte 0 = 62 to rank1
7949 11:08:48.198981 Final RX Vref Byte 1 = 63 to rank1==
7950 11:08:48.202278 Dram Type= 6, Freq= 0, CH_0, rank 0
7951 11:08:48.208795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7952 11:08:48.208878 ==
7953 11:08:48.208945 DQS Delay:
7954 11:08:48.209006 DQS0 = 0, DQS1 = 0
7955 11:08:48.212010 DQM Delay:
7956 11:08:48.212092 DQM0 = 130, DQM1 = 122
7957 11:08:48.215715 DQ Delay:
7958 11:08:48.219563 DQ0 =130, DQ1 =134, DQ2 =126, DQ3 =126
7959 11:08:48.222278 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7960 11:08:48.225552 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
7961 11:08:48.228831 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =132
7962 11:08:48.228950
7963 11:08:48.229057
7964 11:08:48.229180
7965 11:08:48.231876 [DramC_TX_OE_Calibration] TA2
7966 11:08:48.235429 Original DQ_B0 (3 6) =30, OEN = 27
7967 11:08:48.239187 Original DQ_B1 (3 6) =30, OEN = 27
7968 11:08:48.242129 24, 0x0, End_B0=24 End_B1=24
7969 11:08:48.242250 25, 0x0, End_B0=25 End_B1=25
7970 11:08:48.245491 26, 0x0, End_B0=26 End_B1=26
7971 11:08:48.249482 27, 0x0, End_B0=27 End_B1=27
7972 11:08:48.252050 28, 0x0, End_B0=28 End_B1=28
7973 11:08:48.252185 29, 0x0, End_B0=29 End_B1=29
7974 11:08:48.255834 30, 0x0, End_B0=30 End_B1=30
7975 11:08:48.258606 31, 0x4141, End_B0=30 End_B1=30
7976 11:08:48.262526 Byte0 end_step=30 best_step=27
7977 11:08:48.265807 Byte1 end_step=30 best_step=27
7978 11:08:48.269028 Byte0 TX OE(2T, 0.5T) = (3, 3)
7979 11:08:48.269110 Byte1 TX OE(2T, 0.5T) = (3, 3)
7980 11:08:48.272107
7981 11:08:48.272221
7982 11:08:48.279600 [DQSOSCAuto] RK0, (LSB)MR18= 0x1105, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 401 ps
7983 11:08:48.281877 CH0 RK0: MR19=303, MR18=1105
7984 11:08:48.289117 CH0_RK0: MR19=0x303, MR18=0x1105, DQSOSC=401, MR23=63, INC=22, DEC=15
7985 11:08:48.289217
7986 11:08:48.291976 ----->DramcWriteLeveling(PI) begin...
7987 11:08:48.292075 ==
7988 11:08:48.295314 Dram Type= 6, Freq= 0, CH_0, rank 1
7989 11:08:48.298813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7990 11:08:48.298912 ==
7991 11:08:48.302057 Write leveling (Byte 0): 32 => 32
7992 11:08:48.305422 Write leveling (Byte 1): 26 => 26
7993 11:08:48.308531 DramcWriteLeveling(PI) end<-----
7994 11:08:48.308613
7995 11:08:48.308678 ==
7996 11:08:48.312563 Dram Type= 6, Freq= 0, CH_0, rank 1
7997 11:08:48.315744 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7998 11:08:48.315831 ==
7999 11:08:48.318978 [Gating] SW mode calibration
8000 11:08:48.325525 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8001 11:08:48.332088 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8002 11:08:48.335468 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 11:08:48.339382 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 11:08:48.345688 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 11:08:48.348836 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8006 11:08:48.351964 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8007 11:08:48.359164 1 4 20 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
8008 11:08:48.362408 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 11:08:48.365829 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 11:08:48.372396 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 11:08:48.375417 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8012 11:08:48.379054 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8013 11:08:48.385835 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
8014 11:08:48.388860 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8015 11:08:48.392527 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8016 11:08:48.395214 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8017 11:08:48.402489 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 11:08:48.405192 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 11:08:48.408662 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 11:08:48.415268 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8021 11:08:48.419533 1 6 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8022 11:08:48.421855 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8023 11:08:48.428757 1 6 20 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
8024 11:08:48.432163 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 11:08:48.435035 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 11:08:48.441876 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 11:08:48.445387 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 11:08:48.449414 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8029 11:08:48.455356 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8030 11:08:48.459180 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8031 11:08:48.462114 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8032 11:08:48.469027 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8033 11:08:48.471875 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 11:08:48.475849 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 11:08:48.482072 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 11:08:48.485408 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 11:08:48.488446 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 11:08:48.492419 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 11:08:48.498883 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 11:08:48.501907 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 11:08:48.505830 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 11:08:48.512304 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 11:08:48.515401 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 11:08:48.518547 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8045 11:08:48.525726 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8046 11:08:48.528999 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8047 11:08:48.532414 Total UI for P1: 0, mck2ui 16
8048 11:08:48.535912 best dqsien dly found for B0: ( 1, 9, 10)
8049 11:08:48.538367 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8050 11:08:48.545276 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8051 11:08:48.548680 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 11:08:48.552258 Total UI for P1: 0, mck2ui 16
8053 11:08:48.555872 best dqsien dly found for B1: ( 1, 9, 22)
8054 11:08:48.558580 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8055 11:08:48.561916 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
8056 11:08:48.562017
8057 11:08:48.566310 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8058 11:08:48.568943 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
8059 11:08:48.572091 [Gating] SW calibration Done
8060 11:08:48.572173 ==
8061 11:08:48.575898 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 11:08:48.579172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 11:08:48.581918 ==
8064 11:08:48.582026 RX Vref Scan: 0
8065 11:08:48.582118
8066 11:08:48.585718 RX Vref 0 -> 0, step: 1
8067 11:08:48.585799
8068 11:08:48.585865 RX Delay 0 -> 252, step: 8
8069 11:08:48.592119 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8070 11:08:48.595644 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8071 11:08:48.598754 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8072 11:08:48.601851 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8073 11:08:48.605930 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8074 11:08:48.612211 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8075 11:08:48.615906 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8076 11:08:48.618559 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8077 11:08:48.621830 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8078 11:08:48.625653 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8079 11:08:48.631781 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8080 11:08:48.635169 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8081 11:08:48.638819 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8082 11:08:48.642043 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8083 11:08:48.645481 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8084 11:08:48.651915 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8085 11:08:48.651997 ==
8086 11:08:48.655183 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 11:08:48.658347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 11:08:48.658465 ==
8089 11:08:48.658531 DQS Delay:
8090 11:08:48.662034 DQS0 = 0, DQS1 = 0
8091 11:08:48.662115 DQM Delay:
8092 11:08:48.665563 DQM0 = 131, DQM1 = 124
8093 11:08:48.665644 DQ Delay:
8094 11:08:48.668432 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8095 11:08:48.672152 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8096 11:08:48.674974 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
8097 11:08:48.679184 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8098 11:08:48.679266
8099 11:08:48.681772
8100 11:08:48.681853 ==
8101 11:08:48.685527 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 11:08:48.688713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 11:08:48.688795 ==
8104 11:08:48.688861
8105 11:08:48.688922
8106 11:08:48.692058 TX Vref Scan disable
8107 11:08:48.692140 == TX Byte 0 ==
8108 11:08:48.698626 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8109 11:08:48.701920 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8110 11:08:48.702003 == TX Byte 1 ==
8111 11:08:48.708767 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8112 11:08:48.712007 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8113 11:08:48.712089 ==
8114 11:08:48.715082 Dram Type= 6, Freq= 0, CH_0, rank 1
8115 11:08:48.718717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8116 11:08:48.718799 ==
8117 11:08:48.733775
8118 11:08:48.737222 TX Vref early break, caculate TX vref
8119 11:08:48.740564 TX Vref=16, minBit 9, minWin=21, winSum=367
8120 11:08:48.743786 TX Vref=18, minBit 3, minWin=23, winSum=380
8121 11:08:48.747082 TX Vref=20, minBit 8, minWin=23, winSum=387
8122 11:08:48.750828 TX Vref=22, minBit 9, minWin=23, winSum=397
8123 11:08:48.753756 TX Vref=24, minBit 1, minWin=25, winSum=407
8124 11:08:48.760482 TX Vref=26, minBit 9, minWin=24, winSum=414
8125 11:08:48.765948 TX Vref=28, minBit 0, minWin=26, winSum=418
8126 11:08:48.767327 TX Vref=30, minBit 11, minWin=25, winSum=418
8127 11:08:48.770659 TX Vref=32, minBit 0, minWin=25, winSum=412
8128 11:08:48.773774 TX Vref=34, minBit 1, minWin=24, winSum=400
8129 11:08:48.777607 TX Vref=36, minBit 0, minWin=24, winSum=393
8130 11:08:48.783623 [TxChooseVref] Worse bit 0, Min win 26, Win sum 418, Final Vref 28
8131 11:08:48.783706
8132 11:08:48.786922 Final TX Range 0 Vref 28
8133 11:08:48.787004
8134 11:08:48.787070 ==
8135 11:08:48.790310 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 11:08:48.794173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 11:08:48.794255 ==
8138 11:08:48.794321
8139 11:08:48.794381
8140 11:08:48.797417 TX Vref Scan disable
8141 11:08:48.803835 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8142 11:08:48.803917 == TX Byte 0 ==
8143 11:08:48.807294 u2DelayCellOfst[0]=14 cells (4 PI)
8144 11:08:48.810777 u2DelayCellOfst[1]=17 cells (5 PI)
8145 11:08:48.814198 u2DelayCellOfst[2]=10 cells (3 PI)
8146 11:08:48.817275 u2DelayCellOfst[3]=10 cells (3 PI)
8147 11:08:48.820211 u2DelayCellOfst[4]=7 cells (2 PI)
8148 11:08:48.823751 u2DelayCellOfst[5]=0 cells (0 PI)
8149 11:08:48.827142 u2DelayCellOfst[6]=17 cells (5 PI)
8150 11:08:48.830665 u2DelayCellOfst[7]=17 cells (5 PI)
8151 11:08:48.833677 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8152 11:08:48.837332 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8153 11:08:48.841082 == TX Byte 1 ==
8154 11:08:48.841164 u2DelayCellOfst[8]=0 cells (0 PI)
8155 11:08:48.843895 u2DelayCellOfst[9]=0 cells (0 PI)
8156 11:08:48.847269 u2DelayCellOfst[10]=3 cells (1 PI)
8157 11:08:48.850369 u2DelayCellOfst[11]=0 cells (0 PI)
8158 11:08:48.854043 u2DelayCellOfst[12]=10 cells (3 PI)
8159 11:08:48.857749 u2DelayCellOfst[13]=10 cells (3 PI)
8160 11:08:48.860432 u2DelayCellOfst[14]=14 cells (4 PI)
8161 11:08:48.863892 u2DelayCellOfst[15]=10 cells (3 PI)
8162 11:08:48.867129 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8163 11:08:48.873861 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8164 11:08:48.873943 DramC Write-DBI on
8165 11:08:48.874008 ==
8166 11:08:48.877247 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 11:08:48.880466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 11:08:48.884268 ==
8169 11:08:48.884418
8170 11:08:48.884514
8171 11:08:48.884605 TX Vref Scan disable
8172 11:08:48.887182 == TX Byte 0 ==
8173 11:08:48.890695 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8174 11:08:48.894099 == TX Byte 1 ==
8175 11:08:48.897660 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8176 11:08:48.897762 DramC Write-DBI off
8177 11:08:48.900663
8178 11:08:48.900771 [DATLAT]
8179 11:08:48.900838 Freq=1600, CH0 RK1
8180 11:08:48.900899
8181 11:08:48.903973 DATLAT Default: 0xf
8182 11:08:48.904083 0, 0xFFFF, sum = 0
8183 11:08:48.907501 1, 0xFFFF, sum = 0
8184 11:08:48.907578 2, 0xFFFF, sum = 0
8185 11:08:48.910356 3, 0xFFFF, sum = 0
8186 11:08:48.910493 4, 0xFFFF, sum = 0
8187 11:08:48.914129 5, 0xFFFF, sum = 0
8188 11:08:48.917200 6, 0xFFFF, sum = 0
8189 11:08:48.917283 7, 0xFFFF, sum = 0
8190 11:08:48.920573 8, 0xFFFF, sum = 0
8191 11:08:48.920656 9, 0xFFFF, sum = 0
8192 11:08:48.924219 10, 0xFFFF, sum = 0
8193 11:08:48.924302 11, 0xFFFF, sum = 0
8194 11:08:48.927208 12, 0xFFFF, sum = 0
8195 11:08:48.927291 13, 0xFFFF, sum = 0
8196 11:08:48.931475 14, 0x0, sum = 1
8197 11:08:48.931558 15, 0x0, sum = 2
8198 11:08:48.934016 16, 0x0, sum = 3
8199 11:08:48.934098 17, 0x0, sum = 4
8200 11:08:48.937733 best_step = 15
8201 11:08:48.937814
8202 11:08:48.937879 ==
8203 11:08:48.941079 Dram Type= 6, Freq= 0, CH_0, rank 1
8204 11:08:48.944214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8205 11:08:48.944296 ==
8206 11:08:48.944361 RX Vref Scan: 0
8207 11:08:48.944423
8208 11:08:48.947444 RX Vref 0 -> 0, step: 1
8209 11:08:48.947585
8210 11:08:48.950849 RX Delay 11 -> 252, step: 4
8211 11:08:48.953703 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8212 11:08:48.961061 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8213 11:08:48.963551 iDelay=195, Bit 2, Center 124 (67 ~ 182) 116
8214 11:08:48.967336 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8215 11:08:48.970362 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8216 11:08:48.973686 iDelay=195, Bit 5, Center 114 (59 ~ 170) 112
8217 11:08:48.977283 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8218 11:08:48.983871 iDelay=195, Bit 7, Center 134 (79 ~ 190) 112
8219 11:08:48.988020 iDelay=195, Bit 8, Center 114 (63 ~ 166) 104
8220 11:08:48.990332 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8221 11:08:48.993919 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8222 11:08:48.997407 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8223 11:08:49.003624 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8224 11:08:49.007241 iDelay=195, Bit 13, Center 130 (75 ~ 186) 112
8225 11:08:49.010698 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8226 11:08:49.014139 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8227 11:08:49.014221 ==
8228 11:08:49.017254 Dram Type= 6, Freq= 0, CH_0, rank 1
8229 11:08:49.024516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 11:08:49.024604 ==
8231 11:08:49.024670 DQS Delay:
8232 11:08:49.027396 DQS0 = 0, DQS1 = 0
8233 11:08:49.027478 DQM Delay:
8234 11:08:49.027543 DQM0 = 127, DQM1 = 123
8235 11:08:49.030385 DQ Delay:
8236 11:08:49.034089 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8237 11:08:49.037544 DQ4 =126, DQ5 =114, DQ6 =138, DQ7 =134
8238 11:08:49.040614 DQ8 =114, DQ9 =112, DQ10 =122, DQ11 =116
8239 11:08:49.044463 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8240 11:08:49.044548
8241 11:08:49.044612
8242 11:08:49.044673
8243 11:08:49.047522 [DramC_TX_OE_Calibration] TA2
8244 11:08:49.051048 Original DQ_B0 (3 6) =30, OEN = 27
8245 11:08:49.053989 Original DQ_B1 (3 6) =30, OEN = 27
8246 11:08:49.057306 24, 0x0, End_B0=24 End_B1=24
8247 11:08:49.057389 25, 0x0, End_B0=25 End_B1=25
8248 11:08:49.060779 26, 0x0, End_B0=26 End_B1=26
8249 11:08:49.063910 27, 0x0, End_B0=27 End_B1=27
8250 11:08:49.067439 28, 0x0, End_B0=28 End_B1=28
8251 11:08:49.070501 29, 0x0, End_B0=29 End_B1=29
8252 11:08:49.070584 30, 0x0, End_B0=30 End_B1=30
8253 11:08:49.074131 31, 0x4141, End_B0=30 End_B1=30
8254 11:08:49.077224 Byte0 end_step=30 best_step=27
8255 11:08:49.080212 Byte1 end_step=30 best_step=27
8256 11:08:49.083605 Byte0 TX OE(2T, 0.5T) = (3, 3)
8257 11:08:49.087173 Byte1 TX OE(2T, 0.5T) = (3, 3)
8258 11:08:49.087255
8259 11:08:49.087320
8260 11:08:49.094417 [DQSOSCAuto] RK1, (LSB)MR18= 0x150b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
8261 11:08:49.097382 CH0 RK1: MR19=303, MR18=150B
8262 11:08:49.103744 CH0_RK1: MR19=0x303, MR18=0x150B, DQSOSC=399, MR23=63, INC=23, DEC=15
8263 11:08:49.107350 [RxdqsGatingPostProcess] freq 1600
8264 11:08:49.110714 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8265 11:08:49.114016 best DQS0 dly(2T, 0.5T) = (1, 1)
8266 11:08:49.117506 best DQS1 dly(2T, 0.5T) = (1, 1)
8267 11:08:49.121044 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8268 11:08:49.124130 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8269 11:08:49.127479 best DQS0 dly(2T, 0.5T) = (1, 1)
8270 11:08:49.130955 best DQS1 dly(2T, 0.5T) = (1, 1)
8271 11:08:49.134069 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8272 11:08:49.137468 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8273 11:08:49.137550 Pre-setting of DQS Precalculation
8274 11:08:49.144146 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8275 11:08:49.144230 ==
8276 11:08:49.147533 Dram Type= 6, Freq= 0, CH_1, rank 0
8277 11:08:49.150824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8278 11:08:49.150943 ==
8279 11:08:49.157521 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8280 11:08:49.160939 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8281 11:08:49.164569 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8282 11:08:49.171606 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8283 11:08:49.180500 [CA 0] Center 42 (14~71) winsize 58
8284 11:08:49.183681 [CA 1] Center 42 (13~71) winsize 59
8285 11:08:49.186887 [CA 2] Center 37 (9~66) winsize 58
8286 11:08:49.189999 [CA 3] Center 36 (7~65) winsize 59
8287 11:08:49.193899 [CA 4] Center 37 (8~67) winsize 60
8288 11:08:49.196920 [CA 5] Center 36 (7~66) winsize 60
8289 11:08:49.197004
8290 11:08:49.200735 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8291 11:08:49.200824
8292 11:08:49.203383 [CATrainingPosCal] consider 1 rank data
8293 11:08:49.206765 u2DelayCellTimex100 = 275/100 ps
8294 11:08:49.210385 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8295 11:08:49.217078 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8296 11:08:49.220790 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8297 11:08:49.223520 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8298 11:08:49.227129 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8299 11:08:49.230605 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8300 11:08:49.230686
8301 11:08:49.233486 CA PerBit enable=1, Macro0, CA PI delay=36
8302 11:08:49.233606
8303 11:08:49.236911 [CBTSetCACLKResult] CA Dly = 36
8304 11:08:49.236993 CS Dly: 9 (0~40)
8305 11:08:49.243705 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8306 11:08:49.247805 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8307 11:08:49.247887 ==
8308 11:08:49.250593 Dram Type= 6, Freq= 0, CH_1, rank 1
8309 11:08:49.253740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 11:08:49.253869 ==
8311 11:08:49.260197 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8312 11:08:49.264048 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8313 11:08:49.266823 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8314 11:08:49.273669 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8315 11:08:49.283460 [CA 0] Center 43 (14~73) winsize 60
8316 11:08:49.287194 [CA 1] Center 43 (15~72) winsize 58
8317 11:08:49.290131 [CA 2] Center 37 (8~67) winsize 60
8318 11:08:49.293072 [CA 3] Center 37 (8~66) winsize 59
8319 11:08:49.296991 [CA 4] Center 38 (8~68) winsize 61
8320 11:08:49.300501 [CA 5] Center 36 (7~66) winsize 60
8321 11:08:49.300582
8322 11:08:49.303580 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8323 11:08:49.303661
8324 11:08:49.306845 [CATrainingPosCal] consider 2 rank data
8325 11:08:49.310106 u2DelayCellTimex100 = 275/100 ps
8326 11:08:49.313722 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8327 11:08:49.320262 CA1 delay=43 (15~71),Diff = 7 PI (24 cell)
8328 11:08:49.323302 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8329 11:08:49.326700 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8330 11:08:49.330116 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8331 11:08:49.333665 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8332 11:08:49.333771
8333 11:08:49.336927 CA PerBit enable=1, Macro0, CA PI delay=36
8334 11:08:49.337027
8335 11:08:49.340283 [CBTSetCACLKResult] CA Dly = 36
8336 11:08:49.343705 CS Dly: 11 (0~45)
8337 11:08:49.346813 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8338 11:08:49.351050 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8339 11:08:49.351131
8340 11:08:49.353926 ----->DramcWriteLeveling(PI) begin...
8341 11:08:49.354008 ==
8342 11:08:49.356620 Dram Type= 6, Freq= 0, CH_1, rank 0
8343 11:08:49.360202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8344 11:08:49.363227 ==
8345 11:08:49.363308 Write leveling (Byte 0): 25 => 25
8346 11:08:49.366611 Write leveling (Byte 1): 28 => 28
8347 11:08:49.369738 DramcWriteLeveling(PI) end<-----
8348 11:08:49.369844
8349 11:08:49.369936 ==
8350 11:08:49.373109 Dram Type= 6, Freq= 0, CH_1, rank 0
8351 11:08:49.379708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8352 11:08:49.379790 ==
8353 11:08:49.379854 [Gating] SW mode calibration
8354 11:08:49.389876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8355 11:08:49.393154 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8356 11:08:49.396325 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 11:08:49.403319 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 11:08:49.406543 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 11:08:49.410054 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 11:08:49.416754 1 4 16 | B1->B0 | 2929 2525 | 0 0 | (0 0) (0 0)
8361 11:08:49.419621 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 11:08:49.423285 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 11:08:49.429864 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 11:08:49.432902 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 11:08:49.436632 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 11:08:49.443182 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 11:08:49.446195 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8368 11:08:49.449859 1 5 16 | B1->B0 | 3232 3434 | 1 1 | (0 1) (1 0)
8369 11:08:49.456369 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 11:08:49.459363 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 11:08:49.463245 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 11:08:49.469692 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 11:08:49.472940 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 11:08:49.476276 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 11:08:49.482845 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 11:08:49.486905 1 6 16 | B1->B0 | 4646 3636 | 0 1 | (0 0) (0 0)
8377 11:08:49.489550 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 11:08:49.496064 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 11:08:49.499653 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 11:08:49.503449 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 11:08:49.506616 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 11:08:49.513074 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 11:08:49.516442 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 11:08:49.519818 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8385 11:08:49.526363 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8386 11:08:49.529384 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 11:08:49.532815 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 11:08:49.539803 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 11:08:49.543219 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 11:08:49.546444 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 11:08:49.553204 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 11:08:49.556352 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 11:08:49.559828 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 11:08:49.566507 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 11:08:49.569492 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 11:08:49.573025 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 11:08:49.579981 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 11:08:49.582719 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 11:08:49.586215 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8400 11:08:49.592801 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8401 11:08:49.596400 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 11:08:49.599605 Total UI for P1: 0, mck2ui 16
8403 11:08:49.602968 best dqsien dly found for B0: ( 1, 9, 14)
8404 11:08:49.606945 Total UI for P1: 0, mck2ui 16
8405 11:08:49.609417 best dqsien dly found for B1: ( 1, 9, 16)
8406 11:08:49.612736 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8407 11:08:49.616953 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8408 11:08:49.617035
8409 11:08:49.619400 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8410 11:08:49.623189 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8411 11:08:49.626217 [Gating] SW calibration Done
8412 11:08:49.626298 ==
8413 11:08:49.629655 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 11:08:49.632850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 11:08:49.632935 ==
8416 11:08:49.635999 RX Vref Scan: 0
8417 11:08:49.636082
8418 11:08:49.639493 RX Vref 0 -> 0, step: 1
8419 11:08:49.639607
8420 11:08:49.639712 RX Delay 0 -> 252, step: 8
8421 11:08:49.647182 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8422 11:08:49.649436 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8423 11:08:49.653115 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8424 11:08:49.656850 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8425 11:08:49.660221 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8426 11:08:49.662990 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8427 11:08:49.669589 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8428 11:08:49.672963 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8429 11:08:49.676567 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8430 11:08:49.679880 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8431 11:08:49.683499 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8432 11:08:49.689602 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8433 11:08:49.692863 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8434 11:08:49.696331 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8435 11:08:49.699441 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8436 11:08:49.702937 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8437 11:08:49.706583 ==
8438 11:08:49.709848 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 11:08:49.712832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 11:08:49.712913 ==
8441 11:08:49.712979 DQS Delay:
8442 11:08:49.716467 DQS0 = 0, DQS1 = 0
8443 11:08:49.716548 DQM Delay:
8444 11:08:49.719914 DQM0 = 134, DQM1 = 127
8445 11:08:49.719997 DQ Delay:
8446 11:08:49.722794 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8447 11:08:49.726434 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8448 11:08:49.729653 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8449 11:08:49.733078 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8450 11:08:49.733184
8451 11:08:49.733309
8452 11:08:49.733413 ==
8453 11:08:49.736760 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 11:08:49.743090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 11:08:49.743172 ==
8456 11:08:49.743237
8457 11:08:49.743297
8458 11:08:49.743355 TX Vref Scan disable
8459 11:08:49.746669 == TX Byte 0 ==
8460 11:08:49.749800 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8461 11:08:49.753327 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8462 11:08:49.756820 == TX Byte 1 ==
8463 11:08:49.760523 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8464 11:08:49.763471 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8465 11:08:49.766836 ==
8466 11:08:49.766918 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 11:08:49.773608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 11:08:49.773690 ==
8469 11:08:49.786087
8470 11:08:49.788919 TX Vref early break, caculate TX vref
8471 11:08:49.792798 TX Vref=16, minBit 8, minWin=19, winSum=361
8472 11:08:49.795315 TX Vref=18, minBit 8, minWin=21, winSum=375
8473 11:08:49.799444 TX Vref=20, minBit 8, minWin=22, winSum=380
8474 11:08:49.802019 TX Vref=22, minBit 8, minWin=23, winSum=396
8475 11:08:49.806002 TX Vref=24, minBit 5, minWin=24, winSum=401
8476 11:08:49.812143 TX Vref=26, minBit 8, minWin=24, winSum=410
8477 11:08:49.815306 TX Vref=28, minBit 8, minWin=25, winSum=416
8478 11:08:49.818855 TX Vref=30, minBit 1, minWin=25, winSum=418
8479 11:08:49.822210 TX Vref=32, minBit 8, minWin=24, winSum=411
8480 11:08:49.825543 TX Vref=34, minBit 8, minWin=23, winSum=393
8481 11:08:49.831884 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 30
8482 11:08:49.831966
8483 11:08:49.835422 Final TX Range 0 Vref 30
8484 11:08:49.835504
8485 11:08:49.835569 ==
8486 11:08:49.839117 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 11:08:49.842671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 11:08:49.842753 ==
8489 11:08:49.842819
8490 11:08:49.842879
8491 11:08:49.845770 TX Vref Scan disable
8492 11:08:49.852049 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8493 11:08:49.852131 == TX Byte 0 ==
8494 11:08:49.855580 u2DelayCellOfst[0]=17 cells (5 PI)
8495 11:08:49.859242 u2DelayCellOfst[1]=14 cells (4 PI)
8496 11:08:49.862324 u2DelayCellOfst[2]=0 cells (0 PI)
8497 11:08:49.865560 u2DelayCellOfst[3]=7 cells (2 PI)
8498 11:08:49.868934 u2DelayCellOfst[4]=7 cells (2 PI)
8499 11:08:49.869016 u2DelayCellOfst[5]=21 cells (6 PI)
8500 11:08:49.872052 u2DelayCellOfst[6]=17 cells (5 PI)
8501 11:08:49.875373 u2DelayCellOfst[7]=7 cells (2 PI)
8502 11:08:49.882338 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8503 11:08:49.886173 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8504 11:08:49.886255 == TX Byte 1 ==
8505 11:08:49.888994 u2DelayCellOfst[8]=0 cells (0 PI)
8506 11:08:49.892612 u2DelayCellOfst[9]=10 cells (3 PI)
8507 11:08:49.895604 u2DelayCellOfst[10]=14 cells (4 PI)
8508 11:08:49.899309 u2DelayCellOfst[11]=10 cells (3 PI)
8509 11:08:49.902452 u2DelayCellOfst[12]=17 cells (5 PI)
8510 11:08:49.905927 u2DelayCellOfst[13]=21 cells (6 PI)
8511 11:08:49.909160 u2DelayCellOfst[14]=21 cells (6 PI)
8512 11:08:49.912260 u2DelayCellOfst[15]=21 cells (6 PI)
8513 11:08:49.915745 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8514 11:08:49.919242 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8515 11:08:49.922631 DramC Write-DBI on
8516 11:08:49.922712 ==
8517 11:08:49.926192 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 11:08:49.928778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 11:08:49.928860 ==
8520 11:08:49.928926
8521 11:08:49.928987
8522 11:08:49.932292 TX Vref Scan disable
8523 11:08:49.935903 == TX Byte 0 ==
8524 11:08:49.938742 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8525 11:08:49.938823 == TX Byte 1 ==
8526 11:08:49.945771 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8527 11:08:49.945853 DramC Write-DBI off
8528 11:08:49.945917
8529 11:08:49.948908 [DATLAT]
8530 11:08:49.948989 Freq=1600, CH1 RK0
8531 11:08:49.949055
8532 11:08:49.952175 DATLAT Default: 0xf
8533 11:08:49.952257 0, 0xFFFF, sum = 0
8534 11:08:49.956518 1, 0xFFFF, sum = 0
8535 11:08:49.956601 2, 0xFFFF, sum = 0
8536 11:08:49.958619 3, 0xFFFF, sum = 0
8537 11:08:49.958702 4, 0xFFFF, sum = 0
8538 11:08:49.962238 5, 0xFFFF, sum = 0
8539 11:08:49.962321 6, 0xFFFF, sum = 0
8540 11:08:49.966176 7, 0xFFFF, sum = 0
8541 11:08:49.966259 8, 0xFFFF, sum = 0
8542 11:08:49.968928 9, 0xFFFF, sum = 0
8543 11:08:49.969011 10, 0xFFFF, sum = 0
8544 11:08:49.972347 11, 0xFFFF, sum = 0
8545 11:08:49.972457 12, 0xFFFF, sum = 0
8546 11:08:49.975806 13, 0xFFFF, sum = 0
8547 11:08:49.978744 14, 0x0, sum = 1
8548 11:08:49.978847 15, 0x0, sum = 2
8549 11:08:49.978951 16, 0x0, sum = 3
8550 11:08:49.982808 17, 0x0, sum = 4
8551 11:08:49.982881 best_step = 15
8552 11:08:49.982958
8553 11:08:49.983020 ==
8554 11:08:49.985623 Dram Type= 6, Freq= 0, CH_1, rank 0
8555 11:08:49.992932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8556 11:08:49.993031 ==
8557 11:08:49.993111 RX Vref Scan: 1
8558 11:08:49.993172
8559 11:08:49.996003 Set Vref Range= 24 -> 127
8560 11:08:49.996085
8561 11:08:49.999731 RX Vref 24 -> 127, step: 1
8562 11:08:49.999817
8563 11:08:50.002252 RX Delay 19 -> 252, step: 4
8564 11:08:50.002334
8565 11:08:50.005735 Set Vref, RX VrefLevel [Byte0]: 24
8566 11:08:50.005817 [Byte1]: 24
8567 11:08:50.010070
8568 11:08:50.010152 Set Vref, RX VrefLevel [Byte0]: 25
8569 11:08:50.013203 [Byte1]: 25
8570 11:08:50.017922
8571 11:08:50.018004 Set Vref, RX VrefLevel [Byte0]: 26
8572 11:08:50.020650 [Byte1]: 26
8573 11:08:50.024979
8574 11:08:50.025059 Set Vref, RX VrefLevel [Byte0]: 27
8575 11:08:50.028258 [Byte1]: 27
8576 11:08:50.032470
8577 11:08:50.032551 Set Vref, RX VrefLevel [Byte0]: 28
8578 11:08:50.036120 [Byte1]: 28
8579 11:08:50.040159
8580 11:08:50.040240 Set Vref, RX VrefLevel [Byte0]: 29
8581 11:08:50.043598 [Byte1]: 29
8582 11:08:50.047927
8583 11:08:50.048022 Set Vref, RX VrefLevel [Byte0]: 30
8584 11:08:50.051094 [Byte1]: 30
8585 11:08:50.055634
8586 11:08:50.055749 Set Vref, RX VrefLevel [Byte0]: 31
8587 11:08:50.059835 [Byte1]: 31
8588 11:08:50.062937
8589 11:08:50.063018 Set Vref, RX VrefLevel [Byte0]: 32
8590 11:08:50.066256 [Byte1]: 32
8591 11:08:50.070494
8592 11:08:50.070575 Set Vref, RX VrefLevel [Byte0]: 33
8593 11:08:50.073990 [Byte1]: 33
8594 11:08:50.078107
8595 11:08:50.078188 Set Vref, RX VrefLevel [Byte0]: 34
8596 11:08:50.081505 [Byte1]: 34
8597 11:08:50.086168
8598 11:08:50.086249 Set Vref, RX VrefLevel [Byte0]: 35
8599 11:08:50.088715 [Byte1]: 35
8600 11:08:50.093400
8601 11:08:50.093481 Set Vref, RX VrefLevel [Byte0]: 36
8602 11:08:50.096756 [Byte1]: 36
8603 11:08:50.100958
8604 11:08:50.101040 Set Vref, RX VrefLevel [Byte0]: 37
8605 11:08:50.104570 [Byte1]: 37
8606 11:08:50.109249
8607 11:08:50.109330 Set Vref, RX VrefLevel [Byte0]: 38
8608 11:08:50.111557 [Byte1]: 38
8609 11:08:50.115772
8610 11:08:50.115856 Set Vref, RX VrefLevel [Byte0]: 39
8611 11:08:50.119372 [Byte1]: 39
8612 11:08:50.124222
8613 11:08:50.124307 Set Vref, RX VrefLevel [Byte0]: 40
8614 11:08:50.126641 [Byte1]: 40
8615 11:08:50.131262
8616 11:08:50.131343 Set Vref, RX VrefLevel [Byte0]: 41
8617 11:08:50.135004 [Byte1]: 41
8618 11:08:50.138899
8619 11:08:50.138978 Set Vref, RX VrefLevel [Byte0]: 42
8620 11:08:50.142022 [Byte1]: 42
8621 11:08:50.146329
8622 11:08:50.146447 Set Vref, RX VrefLevel [Byte0]: 43
8623 11:08:50.149855 [Byte1]: 43
8624 11:08:50.154151
8625 11:08:50.154253 Set Vref, RX VrefLevel [Byte0]: 44
8626 11:08:50.157387 [Byte1]: 44
8627 11:08:50.161689
8628 11:08:50.161789 Set Vref, RX VrefLevel [Byte0]: 45
8629 11:08:50.164595 [Byte1]: 45
8630 11:08:50.169333
8631 11:08:50.169432 Set Vref, RX VrefLevel [Byte0]: 46
8632 11:08:50.172409 [Byte1]: 46
8633 11:08:50.176467
8634 11:08:50.176560 Set Vref, RX VrefLevel [Byte0]: 47
8635 11:08:50.179871 [Byte1]: 47
8636 11:08:50.183993
8637 11:08:50.184078 Set Vref, RX VrefLevel [Byte0]: 48
8638 11:08:50.187710 [Byte1]: 48
8639 11:08:50.191500
8640 11:08:50.191581 Set Vref, RX VrefLevel [Byte0]: 49
8641 11:08:50.194943 [Byte1]: 49
8642 11:08:50.199151
8643 11:08:50.199232 Set Vref, RX VrefLevel [Byte0]: 50
8644 11:08:50.202902 [Byte1]: 50
8645 11:08:50.207306
8646 11:08:50.207387 Set Vref, RX VrefLevel [Byte0]: 51
8647 11:08:50.210194 [Byte1]: 51
8648 11:08:50.214661
8649 11:08:50.214742 Set Vref, RX VrefLevel [Byte0]: 52
8650 11:08:50.217949 [Byte1]: 52
8651 11:08:50.222121
8652 11:08:50.222202 Set Vref, RX VrefLevel [Byte0]: 53
8653 11:08:50.225329 [Byte1]: 53
8654 11:08:50.230027
8655 11:08:50.230108 Set Vref, RX VrefLevel [Byte0]: 54
8656 11:08:50.232859 [Byte1]: 54
8657 11:08:50.237189
8658 11:08:50.237270 Set Vref, RX VrefLevel [Byte0]: 55
8659 11:08:50.240483 [Byte1]: 55
8660 11:08:50.244781
8661 11:08:50.244862 Set Vref, RX VrefLevel [Byte0]: 56
8662 11:08:50.248693 [Byte1]: 56
8663 11:08:50.252064
8664 11:08:50.252165 Set Vref, RX VrefLevel [Byte0]: 57
8665 11:08:50.255443 [Byte1]: 57
8666 11:08:50.259860
8667 11:08:50.260046 Set Vref, RX VrefLevel [Byte0]: 58
8668 11:08:50.263195 [Byte1]: 58
8669 11:08:50.267543
8670 11:08:50.267625 Set Vref, RX VrefLevel [Byte0]: 59
8671 11:08:50.271236 [Byte1]: 59
8672 11:08:50.274745
8673 11:08:50.274826 Set Vref, RX VrefLevel [Byte0]: 60
8674 11:08:50.278644 [Byte1]: 60
8675 11:08:50.282531
8676 11:08:50.282607 Set Vref, RX VrefLevel [Byte0]: 61
8677 11:08:50.285847 [Byte1]: 61
8678 11:08:50.290289
8679 11:08:50.290388 Set Vref, RX VrefLevel [Byte0]: 62
8680 11:08:50.293671 [Byte1]: 62
8681 11:08:50.298715
8682 11:08:50.298809 Set Vref, RX VrefLevel [Byte0]: 63
8683 11:08:50.301033 [Byte1]: 63
8684 11:08:50.305066
8685 11:08:50.305168 Set Vref, RX VrefLevel [Byte0]: 64
8686 11:08:50.309471 [Byte1]: 64
8687 11:08:50.312838
8688 11:08:50.312936 Set Vref, RX VrefLevel [Byte0]: 65
8689 11:08:50.316122 [Byte1]: 65
8690 11:08:50.320436
8691 11:08:50.320535 Set Vref, RX VrefLevel [Byte0]: 66
8692 11:08:50.323913 [Byte1]: 66
8693 11:08:50.328503
8694 11:08:50.328583 Set Vref, RX VrefLevel [Byte0]: 67
8695 11:08:50.331816 [Byte1]: 67
8696 11:08:50.335433
8697 11:08:50.335501 Set Vref, RX VrefLevel [Byte0]: 68
8698 11:08:50.338885 [Byte1]: 68
8699 11:08:50.343075
8700 11:08:50.343145 Set Vref, RX VrefLevel [Byte0]: 69
8701 11:08:50.346492 [Byte1]: 69
8702 11:08:50.350944
8703 11:08:50.351022 Set Vref, RX VrefLevel [Byte0]: 70
8704 11:08:50.354235 [Byte1]: 70
8705 11:08:50.358673
8706 11:08:50.358744 Set Vref, RX VrefLevel [Byte0]: 71
8707 11:08:50.361871 [Byte1]: 71
8708 11:08:50.365619
8709 11:08:50.365717 Set Vref, RX VrefLevel [Byte0]: 72
8710 11:08:50.369454 [Byte1]: 72
8711 11:08:50.373806
8712 11:08:50.373905 Set Vref, RX VrefLevel [Byte0]: 73
8713 11:08:50.376906 [Byte1]: 73
8714 11:08:50.381456
8715 11:08:50.381556 Set Vref, RX VrefLevel [Byte0]: 74
8716 11:08:50.384738 [Byte1]: 74
8717 11:08:50.388396
8718 11:08:50.388478 Final RX Vref Byte 0 = 56 to rank0
8719 11:08:50.392209 Final RX Vref Byte 1 = 59 to rank0
8720 11:08:50.394997 Final RX Vref Byte 0 = 56 to rank1
8721 11:08:50.398514 Final RX Vref Byte 1 = 59 to rank1==
8722 11:08:50.402531 Dram Type= 6, Freq= 0, CH_1, rank 0
8723 11:08:50.408454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8724 11:08:50.408552 ==
8725 11:08:50.408632 DQS Delay:
8726 11:08:50.408693 DQS0 = 0, DQS1 = 0
8727 11:08:50.411698 DQM Delay:
8728 11:08:50.411779 DQM0 = 130, DQM1 = 124
8729 11:08:50.414948 DQ Delay:
8730 11:08:50.418104 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8731 11:08:50.421572 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8732 11:08:50.425115 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =120
8733 11:08:50.428306 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8734 11:08:50.428393
8735 11:08:50.428458
8736 11:08:50.428532
8737 11:08:50.431573 [DramC_TX_OE_Calibration] TA2
8738 11:08:50.434938 Original DQ_B0 (3 6) =30, OEN = 27
8739 11:08:50.438498 Original DQ_B1 (3 6) =30, OEN = 27
8740 11:08:50.441657 24, 0x0, End_B0=24 End_B1=24
8741 11:08:50.441739 25, 0x0, End_B0=25 End_B1=25
8742 11:08:50.445472 26, 0x0, End_B0=26 End_B1=26
8743 11:08:50.448599 27, 0x0, End_B0=27 End_B1=27
8744 11:08:50.451434 28, 0x0, End_B0=28 End_B1=28
8745 11:08:50.454758 29, 0x0, End_B0=29 End_B1=29
8746 11:08:50.454871 30, 0x0, End_B0=30 End_B1=30
8747 11:08:50.458669 31, 0x4141, End_B0=30 End_B1=30
8748 11:08:50.461846 Byte0 end_step=30 best_step=27
8749 11:08:50.465048 Byte1 end_step=30 best_step=27
8750 11:08:50.468301 Byte0 TX OE(2T, 0.5T) = (3, 3)
8751 11:08:50.471695 Byte1 TX OE(2T, 0.5T) = (3, 3)
8752 11:08:50.471776
8753 11:08:50.471840
8754 11:08:50.478156 [DQSOSCAuto] RK0, (LSB)MR18= 0x14fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 399 ps
8755 11:08:50.481941 CH1 RK0: MR19=302, MR18=14FE
8756 11:08:50.489005 CH1_RK0: MR19=0x302, MR18=0x14FE, DQSOSC=399, MR23=63, INC=23, DEC=15
8757 11:08:50.489087
8758 11:08:50.491608 ----->DramcWriteLeveling(PI) begin...
8759 11:08:50.491690 ==
8760 11:08:50.495015 Dram Type= 6, Freq= 0, CH_1, rank 1
8761 11:08:50.498480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8762 11:08:50.498562 ==
8763 11:08:50.501696 Write leveling (Byte 0): 25 => 25
8764 11:08:50.504884 Write leveling (Byte 1): 26 => 26
8765 11:08:50.508143 DramcWriteLeveling(PI) end<-----
8766 11:08:50.508224
8767 11:08:50.508319 ==
8768 11:08:50.511722 Dram Type= 6, Freq= 0, CH_1, rank 1
8769 11:08:50.515245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8770 11:08:50.515326 ==
8771 11:08:50.518633 [Gating] SW mode calibration
8772 11:08:50.525584 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8773 11:08:50.531501 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8774 11:08:50.535823 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 11:08:50.538534 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 11:08:50.544914 1 4 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8777 11:08:50.548106 1 4 12 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
8778 11:08:50.551491 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 11:08:50.558376 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 11:08:50.561953 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 11:08:50.564930 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 11:08:50.571791 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 11:08:50.575137 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8784 11:08:50.578142 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
8785 11:08:50.584807 1 5 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (1 0)
8786 11:08:50.588205 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8787 11:08:50.591961 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 11:08:50.597901 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 11:08:50.602037 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 11:08:50.604612 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 11:08:50.611151 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8792 11:08:50.615275 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8793 11:08:50.618379 1 6 12 | B1->B0 | 2f2f 4545 | 0 0 | (0 0) (0 0)
8794 11:08:50.621710 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 11:08:50.628102 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 11:08:50.631474 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 11:08:50.634758 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 11:08:50.641703 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 11:08:50.644507 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8800 11:08:50.648193 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8801 11:08:50.654377 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8802 11:08:50.658219 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8803 11:08:50.661142 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 11:08:50.667929 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 11:08:50.671318 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 11:08:50.674526 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 11:08:50.681293 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 11:08:50.684469 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 11:08:50.687964 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 11:08:50.694605 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 11:08:50.698111 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 11:08:50.701716 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 11:08:50.708165 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 11:08:50.711544 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 11:08:50.715049 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 11:08:50.721131 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8817 11:08:50.724969 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8818 11:08:50.727958 Total UI for P1: 0, mck2ui 16
8819 11:08:50.731155 best dqsien dly found for B0: ( 1, 9, 8)
8820 11:08:50.734740 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 11:08:50.737780 Total UI for P1: 0, mck2ui 16
8822 11:08:50.741534 best dqsien dly found for B1: ( 1, 9, 12)
8823 11:08:50.744559 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8824 11:08:50.747727 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8825 11:08:50.747808
8826 11:08:50.751112 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8827 11:08:50.754243 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8828 11:08:50.757725 [Gating] SW calibration Done
8829 11:08:50.757806 ==
8830 11:08:50.761176 Dram Type= 6, Freq= 0, CH_1, rank 1
8831 11:08:50.768544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8832 11:08:50.768629 ==
8833 11:08:50.768696 RX Vref Scan: 0
8834 11:08:50.768758
8835 11:08:50.771745 RX Vref 0 -> 0, step: 1
8836 11:08:50.771826
8837 11:08:50.774109 RX Delay 0 -> 252, step: 8
8838 11:08:50.778039 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8839 11:08:50.781490 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8840 11:08:50.784362 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8841 11:08:50.787747 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8842 11:08:50.794261 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8843 11:08:50.798172 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8844 11:08:50.801959 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8845 11:08:50.804367 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8846 11:08:50.807661 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8847 11:08:50.814370 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8848 11:08:50.817884 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8849 11:08:50.821253 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8850 11:08:50.824724 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8851 11:08:50.827707 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8852 11:08:50.834191 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8853 11:08:50.838026 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8854 11:08:50.838133 ==
8855 11:08:50.841466 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 11:08:50.844572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 11:08:50.844654 ==
8858 11:08:50.847524 DQS Delay:
8859 11:08:50.847606 DQS0 = 0, DQS1 = 0
8860 11:08:50.847671 DQM Delay:
8861 11:08:50.851061 DQM0 = 132, DQM1 = 129
8862 11:08:50.851142 DQ Delay:
8863 11:08:50.854750 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8864 11:08:50.858322 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =127
8865 11:08:50.861725 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8866 11:08:50.868164 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8867 11:08:50.868246
8868 11:08:50.868312
8869 11:08:50.868374 ==
8870 11:08:50.870878 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 11:08:50.874682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 11:08:50.874764 ==
8873 11:08:50.874830
8874 11:08:50.874891
8875 11:08:50.878194 TX Vref Scan disable
8876 11:08:50.878275 == TX Byte 0 ==
8877 11:08:50.884989 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8878 11:08:50.887708 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8879 11:08:50.887789 == TX Byte 1 ==
8880 11:08:50.894822 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8881 11:08:50.897746 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8882 11:08:50.897853 ==
8883 11:08:50.901068 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 11:08:50.904777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 11:08:50.904860 ==
8886 11:08:50.918989
8887 11:08:50.922373 TX Vref early break, caculate TX vref
8888 11:08:50.925427 TX Vref=16, minBit 0, minWin=23, winSum=379
8889 11:08:50.928940 TX Vref=18, minBit 8, minWin=23, winSum=391
8890 11:08:50.932381 TX Vref=20, minBit 1, minWin=24, winSum=399
8891 11:08:50.935367 TX Vref=22, minBit 9, minWin=24, winSum=405
8892 11:08:50.939036 TX Vref=24, minBit 0, minWin=25, winSum=417
8893 11:08:50.943222 TX Vref=26, minBit 0, minWin=25, winSum=425
8894 11:08:50.948838 TX Vref=28, minBit 5, minWin=25, winSum=425
8895 11:08:50.952002 TX Vref=30, minBit 0, minWin=25, winSum=426
8896 11:08:50.955784 TX Vref=32, minBit 0, minWin=25, winSum=422
8897 11:08:50.958814 TX Vref=34, minBit 0, minWin=25, winSum=412
8898 11:08:50.962628 TX Vref=36, minBit 0, minWin=24, winSum=400
8899 11:08:50.969127 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 30
8900 11:08:50.969211
8901 11:08:50.972264 Final TX Range 0 Vref 30
8902 11:08:50.972348
8903 11:08:50.972412 ==
8904 11:08:50.975426 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 11:08:50.978965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 11:08:50.979048 ==
8907 11:08:50.979113
8908 11:08:50.979174
8909 11:08:50.982315 TX Vref Scan disable
8910 11:08:50.989006 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8911 11:08:50.989086 == TX Byte 0 ==
8912 11:08:50.992323 u2DelayCellOfst[0]=17 cells (5 PI)
8913 11:08:50.995711 u2DelayCellOfst[1]=10 cells (3 PI)
8914 11:08:50.999048 u2DelayCellOfst[2]=0 cells (0 PI)
8915 11:08:51.002529 u2DelayCellOfst[3]=7 cells (2 PI)
8916 11:08:51.005988 u2DelayCellOfst[4]=10 cells (3 PI)
8917 11:08:51.008904 u2DelayCellOfst[5]=21 cells (6 PI)
8918 11:08:51.012608 u2DelayCellOfst[6]=17 cells (5 PI)
8919 11:08:51.012689 u2DelayCellOfst[7]=7 cells (2 PI)
8920 11:08:51.019325 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8921 11:08:51.022527 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8922 11:08:51.022608 == TX Byte 1 ==
8923 11:08:51.025907 u2DelayCellOfst[8]=0 cells (0 PI)
8924 11:08:51.028901 u2DelayCellOfst[9]=7 cells (2 PI)
8925 11:08:51.032583 u2DelayCellOfst[10]=10 cells (3 PI)
8926 11:08:51.035903 u2DelayCellOfst[11]=7 cells (2 PI)
8927 11:08:51.039187 u2DelayCellOfst[12]=14 cells (4 PI)
8928 11:08:51.042580 u2DelayCellOfst[13]=17 cells (5 PI)
8929 11:08:51.045844 u2DelayCellOfst[14]=17 cells (5 PI)
8930 11:08:51.049280 u2DelayCellOfst[15]=14 cells (4 PI)
8931 11:08:51.052370 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8932 11:08:51.058965 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8933 11:08:51.059046 DramC Write-DBI on
8934 11:08:51.059110 ==
8935 11:08:51.062536 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 11:08:51.065465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 11:08:51.065546 ==
8938 11:08:51.068904
8939 11:08:51.068984
8940 11:08:51.069048 TX Vref Scan disable
8941 11:08:51.072170 == TX Byte 0 ==
8942 11:08:51.075401 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8943 11:08:51.078699 == TX Byte 1 ==
8944 11:08:51.082176 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8945 11:08:51.082258 DramC Write-DBI off
8946 11:08:51.085636
8947 11:08:51.085716 [DATLAT]
8948 11:08:51.085781 Freq=1600, CH1 RK1
8949 11:08:51.085841
8950 11:08:51.089346 DATLAT Default: 0xf
8951 11:08:51.089426 0, 0xFFFF, sum = 0
8952 11:08:51.092712 1, 0xFFFF, sum = 0
8953 11:08:51.092795 2, 0xFFFF, sum = 0
8954 11:08:51.096016 3, 0xFFFF, sum = 0
8955 11:08:51.096098 4, 0xFFFF, sum = 0
8956 11:08:51.098848 5, 0xFFFF, sum = 0
8957 11:08:51.098931 6, 0xFFFF, sum = 0
8958 11:08:51.102750 7, 0xFFFF, sum = 0
8959 11:08:51.105500 8, 0xFFFF, sum = 0
8960 11:08:51.105614 9, 0xFFFF, sum = 0
8961 11:08:51.108953 10, 0xFFFF, sum = 0
8962 11:08:51.109035 11, 0xFFFF, sum = 0
8963 11:08:51.112473 12, 0xFFFF, sum = 0
8964 11:08:51.112555 13, 0xFFFF, sum = 0
8965 11:08:51.115744 14, 0x0, sum = 1
8966 11:08:51.115826 15, 0x0, sum = 2
8967 11:08:51.119212 16, 0x0, sum = 3
8968 11:08:51.119295 17, 0x0, sum = 4
8969 11:08:51.119361 best_step = 15
8970 11:08:51.122530
8971 11:08:51.122610 ==
8972 11:08:51.125502 Dram Type= 6, Freq= 0, CH_1, rank 1
8973 11:08:51.129020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8974 11:08:51.129109 ==
8975 11:08:51.129204 RX Vref Scan: 0
8976 11:08:51.129265
8977 11:08:51.132335 RX Vref 0 -> 0, step: 1
8978 11:08:51.132416
8979 11:08:51.136236 RX Delay 11 -> 252, step: 4
8980 11:08:51.139117 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8981 11:08:51.145371 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8982 11:08:51.149084 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8983 11:08:51.151983 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8984 11:08:51.155562 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8985 11:08:51.158908 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8986 11:08:51.162248 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8987 11:08:51.168863 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8988 11:08:51.172557 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8989 11:08:51.175617 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8990 11:08:51.178691 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8991 11:08:51.182405 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
8992 11:08:51.189210 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8993 11:08:51.192397 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8994 11:08:51.195442 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8995 11:08:51.199537 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8996 11:08:51.199619 ==
8997 11:08:51.202549 Dram Type= 6, Freq= 0, CH_1, rank 1
8998 11:08:51.209231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8999 11:08:51.209314 ==
9000 11:08:51.209380 DQS Delay:
9001 11:08:51.212744 DQS0 = 0, DQS1 = 0
9002 11:08:51.212826 DQM Delay:
9003 11:08:51.212891 DQM0 = 129, DQM1 = 126
9004 11:08:51.216169 DQ Delay:
9005 11:08:51.218979 DQ0 =132, DQ1 =126, DQ2 =118, DQ3 =126
9006 11:08:51.222520 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =124
9007 11:08:51.225470 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9008 11:08:51.229086 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =136
9009 11:08:51.229168
9010 11:08:51.229232
9011 11:08:51.229291
9012 11:08:51.232088 [DramC_TX_OE_Calibration] TA2
9013 11:08:51.236149 Original DQ_B0 (3 6) =30, OEN = 27
9014 11:08:51.238837 Original DQ_B1 (3 6) =30, OEN = 27
9015 11:08:51.242892 24, 0x0, End_B0=24 End_B1=24
9016 11:08:51.242976 25, 0x0, End_B0=25 End_B1=25
9017 11:08:51.245738 26, 0x0, End_B0=26 End_B1=26
9018 11:08:51.248918 27, 0x0, End_B0=27 End_B1=27
9019 11:08:51.251914 28, 0x0, End_B0=28 End_B1=28
9020 11:08:51.255260 29, 0x0, End_B0=29 End_B1=29
9021 11:08:51.255343 30, 0x0, End_B0=30 End_B1=30
9022 11:08:51.258619 31, 0x5151, End_B0=30 End_B1=30
9023 11:08:51.263207 Byte0 end_step=30 best_step=27
9024 11:08:51.266157 Byte1 end_step=30 best_step=27
9025 11:08:51.268778 Byte0 TX OE(2T, 0.5T) = (3, 3)
9026 11:08:51.272207 Byte1 TX OE(2T, 0.5T) = (3, 3)
9027 11:08:51.272289
9028 11:08:51.272355
9029 11:08:51.278461 [DQSOSCAuto] RK1, (LSB)MR18= 0xe14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
9030 11:08:51.281881 CH1 RK1: MR19=303, MR18=E14
9031 11:08:51.289053 CH1_RK1: MR19=0x303, MR18=0xE14, DQSOSC=399, MR23=63, INC=23, DEC=15
9032 11:08:51.291975 [RxdqsGatingPostProcess] freq 1600
9033 11:08:51.295373 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9034 11:08:51.299321 best DQS0 dly(2T, 0.5T) = (1, 1)
9035 11:08:51.302190 best DQS1 dly(2T, 0.5T) = (1, 1)
9036 11:08:51.305600 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9037 11:08:51.308648 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9038 11:08:51.311589 best DQS0 dly(2T, 0.5T) = (1, 1)
9039 11:08:51.315915 best DQS1 dly(2T, 0.5T) = (1, 1)
9040 11:08:51.318607 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9041 11:08:51.322276 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9042 11:08:51.325203 Pre-setting of DQS Precalculation
9043 11:08:51.328861 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9044 11:08:51.335181 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9045 11:08:51.342285 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9046 11:08:51.342371
9047 11:08:51.345138
9048 11:08:51.345220 [Calibration Summary] 3200 Mbps
9049 11:08:51.348922 CH 0, Rank 0
9050 11:08:51.349003 SW Impedance : PASS
9051 11:08:51.352043 DUTY Scan : NO K
9052 11:08:51.355328 ZQ Calibration : PASS
9053 11:08:51.355496 Jitter Meter : NO K
9054 11:08:51.358315 CBT Training : PASS
9055 11:08:51.362016 Write leveling : PASS
9056 11:08:51.362098 RX DQS gating : PASS
9057 11:08:51.365085 RX DQ/DQS(RDDQC) : PASS
9058 11:08:51.369183 TX DQ/DQS : PASS
9059 11:08:51.369265 RX DATLAT : PASS
9060 11:08:51.371834 RX DQ/DQS(Engine): PASS
9061 11:08:51.371915 TX OE : PASS
9062 11:08:51.374775 All Pass.
9063 11:08:51.374857
9064 11:08:51.374922 CH 0, Rank 1
9065 11:08:51.378485 SW Impedance : PASS
9066 11:08:51.381899 DUTY Scan : NO K
9067 11:08:51.381980 ZQ Calibration : PASS
9068 11:08:51.385039 Jitter Meter : NO K
9069 11:08:51.385121 CBT Training : PASS
9070 11:08:51.388258 Write leveling : PASS
9071 11:08:51.391857 RX DQS gating : PASS
9072 11:08:51.391939 RX DQ/DQS(RDDQC) : PASS
9073 11:08:51.394420 TX DQ/DQS : PASS
9074 11:08:51.397966 RX DATLAT : PASS
9075 11:08:51.398048 RX DQ/DQS(Engine): PASS
9076 11:08:51.401352 TX OE : PASS
9077 11:08:51.401436 All Pass.
9078 11:08:51.401502
9079 11:08:51.404742 CH 1, Rank 0
9080 11:08:51.404825 SW Impedance : PASS
9081 11:08:51.407975 DUTY Scan : NO K
9082 11:08:51.411742 ZQ Calibration : PASS
9083 11:08:51.411825 Jitter Meter : NO K
9084 11:08:51.414626 CBT Training : PASS
9085 11:08:51.417830 Write leveling : PASS
9086 11:08:51.417912 RX DQS gating : PASS
9087 11:08:51.421190 RX DQ/DQS(RDDQC) : PASS
9088 11:08:51.424657 TX DQ/DQS : PASS
9089 11:08:51.424739 RX DATLAT : PASS
9090 11:08:51.427982 RX DQ/DQS(Engine): PASS
9091 11:08:51.431182 TX OE : PASS
9092 11:08:51.431340 All Pass.
9093 11:08:51.431406
9094 11:08:51.431468 CH 1, Rank 1
9095 11:08:51.434862 SW Impedance : PASS
9096 11:08:51.437793 DUTY Scan : NO K
9097 11:08:51.437937 ZQ Calibration : PASS
9098 11:08:51.441643 Jitter Meter : NO K
9099 11:08:51.441724 CBT Training : PASS
9100 11:08:51.444416 Write leveling : PASS
9101 11:08:51.447899 RX DQS gating : PASS
9102 11:08:51.447981 RX DQ/DQS(RDDQC) : PASS
9103 11:08:51.451559 TX DQ/DQS : PASS
9104 11:08:51.454651 RX DATLAT : PASS
9105 11:08:51.454748 RX DQ/DQS(Engine): PASS
9106 11:08:51.457969 TX OE : PASS
9107 11:08:51.458065 All Pass.
9108 11:08:51.458132
9109 11:08:51.461148 DramC Write-DBI on
9110 11:08:51.464482 PER_BANK_REFRESH: Hybrid Mode
9111 11:08:51.464611 TX_TRACKING: ON
9112 11:08:51.474935 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9113 11:08:51.481281 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9114 11:08:51.487757 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9115 11:08:51.491521 [FAST_K] Save calibration result to emmc
9116 11:08:51.494576 sync common calibartion params.
9117 11:08:51.497868 sync cbt_mode0:1, 1:1
9118 11:08:51.501109 dram_init: ddr_geometry: 2
9119 11:08:51.501193 dram_init: ddr_geometry: 2
9120 11:08:51.504861 dram_init: ddr_geometry: 2
9121 11:08:51.508535 0:dram_rank_size:100000000
9122 11:08:51.508629 1:dram_rank_size:100000000
9123 11:08:51.514481 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9124 11:08:51.518130 DFS_SHUFFLE_HW_MODE: ON
9125 11:08:51.521496 dramc_set_vcore_voltage set vcore to 725000
9126 11:08:51.525037 Read voltage for 1600, 0
9127 11:08:51.525121 Vio18 = 0
9128 11:08:51.525199 Vcore = 725000
9129 11:08:51.527952 Vdram = 0
9130 11:08:51.528036 Vddq = 0
9131 11:08:51.528102 Vmddr = 0
9132 11:08:51.531097 switch to 3200 Mbps bootup
9133 11:08:51.531180 [DramcRunTimeConfig]
9134 11:08:51.534587 PHYPLL
9135 11:08:51.534671 DPM_CONTROL_AFTERK: ON
9136 11:08:51.538303 PER_BANK_REFRESH: ON
9137 11:08:51.541132 REFRESH_OVERHEAD_REDUCTION: ON
9138 11:08:51.541215 CMD_PICG_NEW_MODE: OFF
9139 11:08:51.544506 XRTWTW_NEW_MODE: ON
9140 11:08:51.544589 XRTRTR_NEW_MODE: ON
9141 11:08:51.547999 TX_TRACKING: ON
9142 11:08:51.548083 RDSEL_TRACKING: OFF
9143 11:08:51.551455 DQS Precalculation for DVFS: ON
9144 11:08:51.554901 RX_TRACKING: OFF
9145 11:08:51.554984 HW_GATING DBG: ON
9146 11:08:51.557942 ZQCS_ENABLE_LP4: ON
9147 11:08:51.558025 RX_PICG_NEW_MODE: ON
9148 11:08:51.561378 TX_PICG_NEW_MODE: ON
9149 11:08:51.564426 ENABLE_RX_DCM_DPHY: ON
9150 11:08:51.564510 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9151 11:08:51.568423 DUMMY_READ_FOR_TRACKING: OFF
9152 11:08:51.571206 !!! SPM_CONTROL_AFTERK: OFF
9153 11:08:51.574237 !!! SPM could not control APHY
9154 11:08:51.574321 IMPEDANCE_TRACKING: ON
9155 11:08:51.577914 TEMP_SENSOR: ON
9156 11:08:51.578014 HW_SAVE_FOR_SR: OFF
9157 11:08:51.581517 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9158 11:08:51.584421 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9159 11:08:51.587844 Read ODT Tracking: ON
9160 11:08:51.591581 Refresh Rate DeBounce: ON
9161 11:08:51.591663 DFS_NO_QUEUE_FLUSH: ON
9162 11:08:51.594762 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9163 11:08:51.597821 ENABLE_DFS_RUNTIME_MRW: OFF
9164 11:08:51.601282 DDR_RESERVE_NEW_MODE: ON
9165 11:08:51.601364 MR_CBT_SWITCH_FREQ: ON
9166 11:08:51.604787 =========================
9167 11:08:51.623344 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9168 11:08:51.626766 dram_init: ddr_geometry: 2
9169 11:08:51.644875 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9170 11:08:51.647917 dram_init: dram init end (result: 0)
9171 11:08:51.654938 DRAM-K: Full calibration passed in 24564 msecs
9172 11:08:51.658525 MRC: failed to locate region type 0.
9173 11:08:51.658638 DRAM rank0 size:0x100000000,
9174 11:08:51.662046 DRAM rank1 size=0x100000000
9175 11:08:51.671685 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9176 11:08:51.678671 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9177 11:08:51.684732 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9178 11:08:51.691253 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9179 11:08:51.695103 DRAM rank0 size:0x100000000,
9180 11:08:51.698324 DRAM rank1 size=0x100000000
9181 11:08:51.698426 CBMEM:
9182 11:08:51.701396 IMD: root @ 0xfffff000 254 entries.
9183 11:08:51.704833 IMD: root @ 0xffffec00 62 entries.
9184 11:08:51.708262 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9185 11:08:51.711863 WARNING: RO_VPD is uninitialized or empty.
9186 11:08:51.718746 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9187 11:08:51.725159 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9188 11:08:51.737590 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9189 11:08:51.748904 BS: romstage times (exec / console): total (unknown) / 24071 ms
9190 11:08:51.748987
9191 11:08:51.749052
9192 11:08:51.759342 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9193 11:08:51.762207 ARM64: Exception handlers installed.
9194 11:08:51.766383 ARM64: Testing exception
9195 11:08:51.769485 ARM64: Done test exception
9196 11:08:51.769567 Enumerating buses...
9197 11:08:51.772466 Show all devs... Before device enumeration.
9198 11:08:51.776211 Root Device: enabled 1
9199 11:08:51.778913 CPU_CLUSTER: 0: enabled 1
9200 11:08:51.778994 CPU: 00: enabled 1
9201 11:08:51.782278 Compare with tree...
9202 11:08:51.782359 Root Device: enabled 1
9203 11:08:51.786133 CPU_CLUSTER: 0: enabled 1
9204 11:08:51.789924 CPU: 00: enabled 1
9205 11:08:51.790030 Root Device scanning...
9206 11:08:51.792768 scan_static_bus for Root Device
9207 11:08:51.795903 CPU_CLUSTER: 0 enabled
9208 11:08:51.798952 scan_static_bus for Root Device done
9209 11:08:51.802630 scan_bus: bus Root Device finished in 8 msecs
9210 11:08:51.802759 done
9211 11:08:51.809005 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9212 11:08:51.812243 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9213 11:08:51.819859 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9214 11:08:51.822282 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9215 11:08:51.825775 Allocating resources...
9216 11:08:51.825856 Reading resources...
9217 11:08:51.832445 Root Device read_resources bus 0 link: 0
9218 11:08:51.832528 DRAM rank0 size:0x100000000,
9219 11:08:51.835661 DRAM rank1 size=0x100000000
9220 11:08:51.839183 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9221 11:08:51.842297 CPU: 00 missing read_resources
9222 11:08:51.846061 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9223 11:08:51.852283 Root Device read_resources bus 0 link: 0 done
9224 11:08:51.852391 Done reading resources.
9225 11:08:51.859409 Show resources in subtree (Root Device)...After reading.
9226 11:08:51.862245 Root Device child on link 0 CPU_CLUSTER: 0
9227 11:08:51.865878 CPU_CLUSTER: 0 child on link 0 CPU: 00
9228 11:08:51.875747 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9229 11:08:51.875832 CPU: 00
9230 11:08:51.879110 Root Device assign_resources, bus 0 link: 0
9231 11:08:51.883163 CPU_CLUSTER: 0 missing set_resources
9232 11:08:51.886231 Root Device assign_resources, bus 0 link: 0 done
9233 11:08:51.889100 Done setting resources.
9234 11:08:51.895795 Show resources in subtree (Root Device)...After assigning values.
9235 11:08:51.899860 Root Device child on link 0 CPU_CLUSTER: 0
9236 11:08:51.902428 CPU_CLUSTER: 0 child on link 0 CPU: 00
9237 11:08:51.912718 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9238 11:08:51.912803 CPU: 00
9239 11:08:51.915795 Done allocating resources.
9240 11:08:51.919384 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9241 11:08:51.922771 Enabling resources...
9242 11:08:51.922852 done.
9243 11:08:51.926174 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9244 11:08:51.929591 Initializing devices...
9245 11:08:51.929706 Root Device init
9246 11:08:51.932904 init hardware done!
9247 11:08:51.936369 0x00000018: ctrlr->caps
9248 11:08:51.936453 52.000 MHz: ctrlr->f_max
9249 11:08:51.939594 0.400 MHz: ctrlr->f_min
9250 11:08:51.943072 0x40ff8080: ctrlr->voltages
9251 11:08:51.943155 sclk: 390625
9252 11:08:51.943220 Bus Width = 1
9253 11:08:51.946558 sclk: 390625
9254 11:08:51.946638 Bus Width = 1
9255 11:08:51.949467 Early init status = 3
9256 11:08:51.953059 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9257 11:08:51.956927 in-header: 03 fc 00 00 01 00 00 00
9258 11:08:51.960965 in-data: 00
9259 11:08:51.963415 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9260 11:08:51.969452 in-header: 03 fd 00 00 00 00 00 00
9261 11:08:51.971986 in-data:
9262 11:08:51.975265 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9263 11:08:51.980122 in-header: 03 fc 00 00 01 00 00 00
9264 11:08:51.983298 in-data: 00
9265 11:08:51.987044 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9266 11:08:51.992109 in-header: 03 fd 00 00 00 00 00 00
9267 11:08:51.995445 in-data:
9268 11:08:51.998768 [SSUSB] Setting up USB HOST controller...
9269 11:08:52.002904 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9270 11:08:52.005531 [SSUSB] phy power-on done.
9271 11:08:52.008898 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9272 11:08:52.016030 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9273 11:08:52.019431 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9274 11:08:52.025399 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9275 11:08:52.032145 read SPI 0x50eb0 0x2ad3: 1173 us, 9346 KB/s, 74.768 Mbps
9276 11:08:52.038623 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9277 11:08:52.045927 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9278 11:08:52.052208 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9279 11:08:52.055586 SPM: binary array size = 0x9dc
9280 11:08:52.058539 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9281 11:08:52.065590 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9282 11:08:52.071695 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9283 11:08:52.075214 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9284 11:08:52.082060 configure_display: Starting display init
9285 11:08:52.115182 anx7625_power_on_init: Init interface.
9286 11:08:52.118594 anx7625_disable_pd_protocol: Disabled PD feature.
9287 11:08:52.122416 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9288 11:08:52.150239 anx7625_start_dp_work: Secure OCM version=00
9289 11:08:52.153031 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9290 11:08:52.167692 sp_tx_get_edid_block: EDID Block = 1
9291 11:08:52.270670 Extracted contents:
9292 11:08:52.273759 header: 00 ff ff ff ff ff ff 00
9293 11:08:52.277129 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9294 11:08:52.280435 version: 01 04
9295 11:08:52.283782 basic params: 95 1f 11 78 0a
9296 11:08:52.287409 chroma info: 76 90 94 55 54 90 27 21 50 54
9297 11:08:52.290432 established: 00 00 00
9298 11:08:52.297491 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9299 11:08:52.300826 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9300 11:08:52.307565 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9301 11:08:52.313913 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9302 11:08:52.321099 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9303 11:08:52.321182 extensions: 00
9304 11:08:52.323975 checksum: fb
9305 11:08:52.324073
9306 11:08:52.327357 Manufacturer: IVO Model 57d Serial Number 0
9307 11:08:52.330583 Made week 0 of 2020
9308 11:08:52.330677 EDID version: 1.4
9309 11:08:52.334371 Digital display
9310 11:08:52.337869 6 bits per primary color channel
9311 11:08:52.337952 DisplayPort interface
9312 11:08:52.340905 Maximum image size: 31 cm x 17 cm
9313 11:08:52.340986 Gamma: 220%
9314 11:08:52.343881 Check DPMS levels
9315 11:08:52.347263 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9316 11:08:52.350585 First detailed timing is preferred timing
9317 11:08:52.354885 Established timings supported:
9318 11:08:52.357562 Standard timings supported:
9319 11:08:52.357643 Detailed timings
9320 11:08:52.363959 Hex of detail: 383680a07038204018303c0035ae10000019
9321 11:08:52.368461 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9322 11:08:52.370871 0780 0798 07c8 0820 hborder 0
9323 11:08:52.377486 0438 043b 0447 0458 vborder 0
9324 11:08:52.377567 -hsync -vsync
9325 11:08:52.381041 Did detailed timing
9326 11:08:52.384114 Hex of detail: 000000000000000000000000000000000000
9327 11:08:52.387521 Manufacturer-specified data, tag 0
9328 11:08:52.394009 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9329 11:08:52.394104 ASCII string: InfoVision
9330 11:08:52.401552 Hex of detail: 000000fe00523134304e574635205248200a
9331 11:08:52.401634 ASCII string: R140NWF5 RH
9332 11:08:52.404052 Checksum
9333 11:08:52.404132 Checksum: 0xfb (valid)
9334 11:08:52.410552 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9335 11:08:52.410636 DSI data_rate: 832800000 bps
9336 11:08:52.419271 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9337 11:08:52.421588 anx7625_parse_edid: pixelclock(138800).
9338 11:08:52.425263 hactive(1920), hsync(48), hfp(24), hbp(88)
9339 11:08:52.428517 vactive(1080), vsync(12), vfp(3), vbp(17)
9340 11:08:52.431888 anx7625_dsi_config: config dsi.
9341 11:08:52.438678 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9342 11:08:52.452765 anx7625_dsi_config: success to config DSI
9343 11:08:52.455704 anx7625_dp_start: MIPI phy setup OK.
9344 11:08:52.459427 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9345 11:08:52.462827 mtk_ddp_mode_set invalid vrefresh 60
9346 11:08:52.466010 main_disp_path_setup
9347 11:08:52.466090 ovl_layer_smi_id_en
9348 11:08:52.469342 ovl_layer_smi_id_en
9349 11:08:52.469423 ccorr_config
9350 11:08:52.469487 aal_config
9351 11:08:52.472513 gamma_config
9352 11:08:52.472594 postmask_config
9353 11:08:52.476387 dither_config
9354 11:08:52.479272 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9355 11:08:52.486858 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9356 11:08:52.489800 Root Device init finished in 554 msecs
9357 11:08:52.489884 CPU_CLUSTER: 0 init
9358 11:08:52.499150 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9359 11:08:52.503037 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9360 11:08:52.505903 APU_MBOX 0x190000b0 = 0x10001
9361 11:08:52.509824 APU_MBOX 0x190001b0 = 0x10001
9362 11:08:52.512581 APU_MBOX 0x190005b0 = 0x10001
9363 11:08:52.516096 APU_MBOX 0x190006b0 = 0x10001
9364 11:08:52.519498 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9365 11:08:52.531404 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9366 11:08:52.544025 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9367 11:08:52.551215 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9368 11:08:52.562320 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9369 11:08:52.571190 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9370 11:08:52.574727 CPU_CLUSTER: 0 init finished in 81 msecs
9371 11:08:52.577976 Devices initialized
9372 11:08:52.581855 Show all devs... After init.
9373 11:08:52.581963 Root Device: enabled 1
9374 11:08:52.585376 CPU_CLUSTER: 0: enabled 1
9375 11:08:52.588588 CPU: 00: enabled 1
9376 11:08:52.591961 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9377 11:08:52.594368 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9378 11:08:52.597857 ELOG: NV offset 0x57f000 size 0x1000
9379 11:08:52.605010 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9380 11:08:52.611351 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9381 11:08:52.614563 ELOG: Event(17) added with size 13 at 2024-03-03 11:08:52 UTC
9382 11:08:52.617792 out: cmd=0x121: 03 db 21 01 00 00 00 00
9383 11:08:52.622066 in-header: 03 de 00 00 2c 00 00 00
9384 11:08:52.635696 in-data: 81 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9385 11:08:52.641937 ELOG: Event(A1) added with size 10 at 2024-03-03 11:08:52 UTC
9386 11:08:52.649248 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9387 11:08:52.655635 ELOG: Event(A0) added with size 9 at 2024-03-03 11:08:52 UTC
9388 11:08:52.659291 elog_add_boot_reason: Logged dev mode boot
9389 11:08:52.661982 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9390 11:08:52.665501 Finalize devices...
9391 11:08:52.665616 Devices finalized
9392 11:08:52.672276 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9393 11:08:52.675432 Writing coreboot table at 0xffe64000
9394 11:08:52.679202 0. 000000000010a000-0000000000113fff: RAMSTAGE
9395 11:08:52.682039 1. 0000000040000000-00000000400fffff: RAM
9396 11:08:52.685830 2. 0000000040100000-000000004032afff: RAMSTAGE
9397 11:08:52.692406 3. 000000004032b000-00000000545fffff: RAM
9398 11:08:52.695701 4. 0000000054600000-000000005465ffff: BL31
9399 11:08:52.698789 5. 0000000054660000-00000000ffe63fff: RAM
9400 11:08:52.702262 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9401 11:08:52.708919 7. 0000000100000000-000000023fffffff: RAM
9402 11:08:52.709004 Passing 5 GPIOs to payload:
9403 11:08:52.715756 NAME | PORT | POLARITY | VALUE
9404 11:08:52.719188 EC in RW | 0x000000aa | low | undefined
9405 11:08:52.725769 EC interrupt | 0x00000005 | low | undefined
9406 11:08:52.728808 TPM interrupt | 0x000000ab | high | undefined
9407 11:08:52.731998 SD card detect | 0x00000011 | high | undefined
9408 11:08:52.739097 speaker enable | 0x00000093 | high | undefined
9409 11:08:52.741938 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9410 11:08:52.745373 in-header: 03 f9 00 00 02 00 00 00
9411 11:08:52.745456 in-data: 02 00
9412 11:08:52.748913 ADC[4]: Raw value=900590 ID=7
9413 11:08:52.753179 ADC[3]: Raw value=213336 ID=1
9414 11:08:52.753261 RAM Code: 0x71
9415 11:08:52.755329 ADC[6]: Raw value=74557 ID=0
9416 11:08:52.759109 ADC[5]: Raw value=212598 ID=1
9417 11:08:52.759190 SKU Code: 0x1
9418 11:08:52.765487 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum db2f
9419 11:08:52.769501 coreboot table: 964 bytes.
9420 11:08:52.772741 IMD ROOT 0. 0xfffff000 0x00001000
9421 11:08:52.776256 IMD SMALL 1. 0xffffe000 0x00001000
9422 11:08:52.779289 RO MCACHE 2. 0xffffc000 0x00001104
9423 11:08:52.783085 CONSOLE 3. 0xfff7c000 0x00080000
9424 11:08:52.785865 FMAP 4. 0xfff7b000 0x00000452
9425 11:08:52.789405 TIME STAMP 5. 0xfff7a000 0x00000910
9426 11:08:52.792984 VBOOT WORK 6. 0xfff66000 0x00014000
9427 11:08:52.795777 RAMOOPS 7. 0xffe66000 0x00100000
9428 11:08:52.799873 COREBOOT 8. 0xffe64000 0x00002000
9429 11:08:52.799955 IMD small region:
9430 11:08:52.802680 IMD ROOT 0. 0xffffec00 0x00000400
9431 11:08:52.805852 VPD 1. 0xffffeb80 0x0000006c
9432 11:08:52.808926 MMC STATUS 2. 0xffffeb60 0x00000004
9433 11:08:52.815662 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9434 11:08:52.815744 Probing TPM: done!
9435 11:08:52.822754 Connected to device vid:did:rid of 1ae0:0028:00
9436 11:08:52.829521 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9437 11:08:52.832808 Initialized TPM device CR50 revision 0
9438 11:08:52.836447 Checking cr50 for pending updates
9439 11:08:52.841828 Reading cr50 TPM mode
9440 11:08:52.850632 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9441 11:08:52.857372 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9442 11:08:52.897200 read SPI 0x3990ec 0x4f1b0: 34854 us, 9296 KB/s, 74.368 Mbps
9443 11:08:52.900542 Checking segment from ROM address 0x40100000
9444 11:08:52.903842 Checking segment from ROM address 0x4010001c
9445 11:08:52.910797 Loading segment from ROM address 0x40100000
9446 11:08:52.910881 code (compression=0)
9447 11:08:52.917137 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9448 11:08:52.927437 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9449 11:08:52.927521 it's not compressed!
9450 11:08:52.933789 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9451 11:08:52.937070 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9452 11:08:52.957990 Loading segment from ROM address 0x4010001c
9453 11:08:52.958076 Entry Point 0x80000000
9454 11:08:52.960985 Loaded segments
9455 11:08:52.964032 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9456 11:08:52.971342 Jumping to boot code at 0x80000000(0xffe64000)
9457 11:08:52.977858 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9458 11:08:52.984009 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9459 11:08:52.992025 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9460 11:08:52.995620 Checking segment from ROM address 0x40100000
9461 11:08:52.998514 Checking segment from ROM address 0x4010001c
9462 11:08:53.006508 Loading segment from ROM address 0x40100000
9463 11:08:53.006591 code (compression=1)
9464 11:08:53.012393 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9465 11:08:53.022071 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9466 11:08:53.022153 using LZMA
9467 11:08:53.031047 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9468 11:08:53.037706 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9469 11:08:53.040817 Loading segment from ROM address 0x4010001c
9470 11:08:53.040922 Entry Point 0x54601000
9471 11:08:53.043730 Loaded segments
9472 11:08:53.047082 NOTICE: MT8192 bl31_setup
9473 11:08:53.053945 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9474 11:08:53.057580 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9475 11:08:53.060518 WARNING: region 0:
9476 11:08:53.063756 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 11:08:53.063838 WARNING: region 1:
9478 11:08:53.071069 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9479 11:08:53.074153 WARNING: region 2:
9480 11:08:53.077443 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9481 11:08:53.080728 WARNING: region 3:
9482 11:08:53.084990 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9483 11:08:53.087472 WARNING: region 4:
9484 11:08:53.091283 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9485 11:08:53.094128 WARNING: region 5:
9486 11:08:53.097374 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 11:08:53.101137 WARNING: region 6:
9488 11:08:53.104100 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 11:08:53.104182 WARNING: region 7:
9490 11:08:53.111046 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 11:08:53.117646 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9492 11:08:53.121193 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9493 11:08:53.124539 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9494 11:08:53.131075 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9495 11:08:53.135022 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9496 11:08:53.138286 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9497 11:08:53.144430 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9498 11:08:53.147513 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9499 11:08:53.151719 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9500 11:08:53.157805 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9501 11:08:53.161599 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9502 11:08:53.164683 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9503 11:08:53.170981 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9504 11:08:53.174541 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9505 11:08:53.181643 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9506 11:08:53.184557 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9507 11:08:53.188578 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9508 11:08:53.195273 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9509 11:08:53.197897 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9510 11:08:53.201610 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9511 11:08:53.208241 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9512 11:08:53.211660 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9513 11:08:53.218032 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9514 11:08:53.221589 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9515 11:08:53.224770 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9516 11:08:53.231426 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9517 11:08:53.235103 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9518 11:08:53.238176 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9519 11:08:53.244888 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9520 11:08:53.248566 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9521 11:08:53.255595 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9522 11:08:53.258217 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9523 11:08:53.261674 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9524 11:08:53.265278 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9525 11:08:53.272798 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9526 11:08:53.275324 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9527 11:08:53.278842 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9528 11:08:53.281949 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9529 11:08:53.288778 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9530 11:08:53.291839 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9531 11:08:53.295902 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9532 11:08:53.299118 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9533 11:08:53.306013 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9534 11:08:53.308543 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9535 11:08:53.312114 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9536 11:08:53.314888 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9537 11:08:53.321813 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9538 11:08:53.325061 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9539 11:08:53.328648 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9540 11:08:53.335264 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9541 11:08:53.338835 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9542 11:08:53.345552 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9543 11:08:53.348374 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9544 11:08:53.352057 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9545 11:08:53.358334 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9546 11:08:53.362327 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9547 11:08:53.368524 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9548 11:08:53.372049 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9549 11:08:53.378404 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9550 11:08:53.382150 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9551 11:08:53.385318 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9552 11:08:53.391808 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9553 11:08:53.395822 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9554 11:08:53.402975 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9555 11:08:53.405917 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9556 11:08:53.412106 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9557 11:08:53.415450 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9558 11:08:53.418664 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9559 11:08:53.425663 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9560 11:08:53.428624 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9561 11:08:53.435624 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9562 11:08:53.439248 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9563 11:08:53.445711 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9564 11:08:53.448862 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9565 11:08:53.452347 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9566 11:08:53.458893 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9567 11:08:53.462615 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9568 11:08:53.469919 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9569 11:08:53.472484 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9570 11:08:53.480086 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9571 11:08:53.482603 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9572 11:08:53.485881 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9573 11:08:53.493789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9574 11:08:53.496704 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9575 11:08:53.502747 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9576 11:08:53.506581 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9577 11:08:53.510108 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9578 11:08:53.516779 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9579 11:08:53.520101 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9580 11:08:53.526383 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9581 11:08:53.529582 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9582 11:08:53.536466 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9583 11:08:53.539794 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9584 11:08:53.543062 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9585 11:08:53.549457 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9586 11:08:53.553148 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9587 11:08:53.556993 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9588 11:08:53.563250 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9589 11:08:53.566533 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9590 11:08:53.569846 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9591 11:08:53.573121 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9592 11:08:53.580094 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9593 11:08:53.583308 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9594 11:08:53.589764 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9595 11:08:53.593222 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9596 11:08:53.596776 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9597 11:08:53.603688 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9598 11:08:53.606695 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9599 11:08:53.613648 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9600 11:08:53.617190 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9601 11:08:53.620961 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9602 11:08:53.627241 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9603 11:08:53.630736 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9604 11:08:53.636907 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9605 11:08:53.640771 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9606 11:08:53.643694 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9607 11:08:53.647381 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9608 11:08:53.654233 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9609 11:08:53.657126 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9610 11:08:53.660416 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9611 11:08:53.666990 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9612 11:08:53.670845 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9613 11:08:53.673942 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9614 11:08:53.676877 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9615 11:08:53.683822 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9616 11:08:53.687201 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9617 11:08:53.694204 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9618 11:08:53.697587 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9619 11:08:53.701155 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9620 11:08:53.707551 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9621 11:08:53.710841 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9622 11:08:53.713867 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9623 11:08:53.720967 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9624 11:08:53.724357 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9625 11:08:53.730891 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9626 11:08:53.734777 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9627 11:08:53.737590 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9628 11:08:53.744327 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9629 11:08:53.747592 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9630 11:08:53.750679 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9631 11:08:53.757464 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9632 11:08:53.760709 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9633 11:08:53.767603 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9634 11:08:53.771110 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9635 11:08:53.774812 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9636 11:08:53.780749 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9637 11:08:53.784454 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9638 11:08:53.787419 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9639 11:08:53.794579 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9640 11:08:53.798266 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9641 11:08:53.804793 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9642 11:08:53.808113 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9643 11:08:53.811720 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9644 11:08:53.818049 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9645 11:08:53.821619 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9646 11:08:53.824460 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9647 11:08:53.831241 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9648 11:08:53.834387 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9649 11:08:53.841073 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9650 11:08:53.844743 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9651 11:08:53.847769 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9652 11:08:53.854620 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9653 11:08:53.858618 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9654 11:08:53.864596 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9655 11:08:53.867979 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9656 11:08:53.871784 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9657 11:08:53.878336 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9658 11:08:53.881372 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9659 11:08:53.885027 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9660 11:08:53.891357 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9661 11:08:53.894967 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9662 11:08:53.901056 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9663 11:08:53.904928 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9664 11:08:53.907620 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9665 11:08:53.914264 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9666 11:08:53.917801 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9667 11:08:53.923979 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9668 11:08:53.927550 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9669 11:08:53.930908 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9670 11:08:53.937699 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9671 11:08:53.941075 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9672 11:08:53.947633 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9673 11:08:53.951342 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9674 11:08:53.954267 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9675 11:08:53.960901 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9676 11:08:53.964561 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9677 11:08:53.967801 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9678 11:08:53.974113 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9679 11:08:53.977369 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9680 11:08:53.984194 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9681 11:08:53.988448 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9682 11:08:53.994232 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9683 11:08:53.997666 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9684 11:08:54.001031 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9685 11:08:54.007500 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9686 11:08:54.010766 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9687 11:08:54.017699 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9688 11:08:54.020904 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9689 11:08:54.024407 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9690 11:08:54.031448 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9691 11:08:54.034562 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9692 11:08:54.041154 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9693 11:08:54.044307 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9694 11:08:54.047890 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9695 11:08:54.054528 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9696 11:08:54.057820 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9697 11:08:54.064278 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9698 11:08:54.067635 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9699 11:08:54.070636 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9700 11:08:54.077745 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9701 11:08:54.081205 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9702 11:08:54.087832 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9703 11:08:54.091535 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9704 11:08:54.097729 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9705 11:08:54.101229 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9706 11:08:54.104168 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9707 11:08:54.110685 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9708 11:08:54.114165 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9709 11:08:54.120986 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9710 11:08:54.124402 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9711 11:08:54.127488 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9712 11:08:54.134211 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9713 11:08:54.137378 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9714 11:08:54.144200 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9715 11:08:54.147907 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9716 11:08:54.151057 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9717 11:08:54.158208 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9718 11:08:54.161317 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9719 11:08:54.167810 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9720 11:08:54.171512 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9721 11:08:54.174184 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9722 11:08:54.177624 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9723 11:08:54.184879 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9724 11:08:54.188034 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9725 11:08:54.190752 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9726 11:08:54.197365 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9727 11:08:54.201333 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9728 11:08:54.204051 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9729 11:08:54.211062 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9730 11:08:54.214412 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9731 11:08:54.217425 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9732 11:08:54.224683 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9733 11:08:54.227291 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9734 11:08:54.230816 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9735 11:08:54.238108 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9736 11:08:54.241385 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9737 11:08:54.244630 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9738 11:08:54.250942 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9739 11:08:54.254299 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9740 11:08:54.257520 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9741 11:08:54.264818 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9742 11:08:54.268099 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9743 11:08:54.274426 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9744 11:08:54.277617 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9745 11:08:54.281407 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9746 11:08:54.288170 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9747 11:08:54.291070 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9748 11:08:54.294566 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9749 11:08:54.300963 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9750 11:08:54.304233 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9751 11:08:54.310998 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9752 11:08:54.314324 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9753 11:08:54.317606 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9754 11:08:54.321104 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9755 11:08:54.328053 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9756 11:08:54.331339 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9757 11:08:54.338012 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9758 11:08:54.341332 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9759 11:08:54.344468 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9760 11:08:54.347999 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9761 11:08:54.354480 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9762 11:08:54.358173 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9763 11:08:54.361302 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9764 11:08:54.364371 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9765 11:08:54.371706 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9766 11:08:54.374561 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9767 11:08:54.377421 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9768 11:08:54.381050 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9769 11:08:54.387775 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9770 11:08:54.391418 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9771 11:08:54.394538 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9772 11:08:54.397386 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9773 11:08:54.404201 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9774 11:08:54.407944 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9775 11:08:54.414160 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9776 11:08:54.417488 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9777 11:08:54.424399 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9778 11:08:54.428050 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9779 11:08:54.431210 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9780 11:08:54.437799 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9781 11:08:54.441313 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9782 11:08:54.447611 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9783 11:08:54.450905 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9784 11:08:54.454533 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9785 11:08:54.461192 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9786 11:08:54.464496 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9787 11:08:54.471281 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9788 11:08:54.474620 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9789 11:08:54.477925 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9790 11:08:54.484351 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9791 11:08:54.487399 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9792 11:08:54.495073 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9793 11:08:54.497731 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9794 11:08:54.501044 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9795 11:08:54.507454 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9796 11:08:54.511060 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9797 11:08:54.518325 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9798 11:08:54.521423 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9799 11:08:54.524715 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9800 11:08:54.531612 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9801 11:08:54.534707 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9802 11:08:54.541402 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9803 11:08:54.544028 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9804 11:08:54.547972 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9805 11:08:54.554210 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9806 11:08:54.557605 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9807 11:08:54.564320 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9808 11:08:54.567789 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9809 11:08:54.570885 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9810 11:08:54.577387 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9811 11:08:54.580888 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9812 11:08:54.587728 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9813 11:08:54.591231 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9814 11:08:54.594416 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9815 11:08:54.600706 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9816 11:08:54.604444 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9817 11:08:54.611248 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9818 11:08:54.614592 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9819 11:08:54.620670 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9820 11:08:54.624199 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9821 11:08:54.627604 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9822 11:08:54.634526 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9823 11:08:54.637316 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9824 11:08:54.644136 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9825 11:08:54.647143 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9826 11:08:54.650516 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9827 11:08:54.657907 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9828 11:08:54.660701 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9829 11:08:54.663877 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9830 11:08:54.671455 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9831 11:08:54.674892 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9832 11:08:54.680853 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9833 11:08:54.684179 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9834 11:08:54.691256 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9835 11:08:54.694267 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9836 11:08:54.697697 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9837 11:08:54.703855 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9838 11:08:54.707507 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9839 11:08:54.713912 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9840 11:08:54.717893 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9841 11:08:54.721257 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9842 11:08:54.727698 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9843 11:08:54.730850 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9844 11:08:54.734162 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9845 11:08:54.741152 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9846 11:08:54.744778 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9847 11:08:54.751305 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9848 11:08:54.754351 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9849 11:08:54.760784 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9850 11:08:54.764260 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9851 11:08:54.771059 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9852 11:08:54.774338 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9853 11:08:54.777765 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9854 11:08:54.784082 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9855 11:08:54.787492 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9856 11:08:54.794482 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9857 11:08:54.797487 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9858 11:08:54.804119 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9859 11:08:54.807304 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9860 11:08:54.811286 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9861 11:08:54.818096 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9862 11:08:54.821055 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9863 11:08:54.827858 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9864 11:08:54.831009 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9865 11:08:54.837454 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9866 11:08:54.841377 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9867 11:08:54.844405 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9868 11:08:54.851020 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9869 11:08:54.854290 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9870 11:08:54.860867 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9871 11:08:54.864196 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9872 11:08:54.871012 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9873 11:08:54.874408 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9874 11:08:54.877980 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9875 11:08:54.884091 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9876 11:08:54.887872 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9877 11:08:54.894171 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9878 11:08:54.897166 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9879 11:08:54.903968 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9880 11:08:54.907508 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9881 11:08:54.910668 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9882 11:08:54.917825 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9883 11:08:54.921028 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9884 11:08:54.927590 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9885 11:08:54.930719 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9886 11:08:54.937138 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9887 11:08:54.941054 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9888 11:08:54.943900 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9889 11:08:54.950705 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9890 11:08:54.953980 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9891 11:08:54.961476 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9892 11:08:54.964003 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9893 11:08:54.967184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9894 11:08:54.974051 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9895 11:08:54.978201 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9896 11:08:54.984877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9897 11:08:54.987395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9898 11:08:54.994387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9899 11:08:54.997878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9900 11:08:55.004617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9901 11:08:55.007885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9902 11:08:55.014160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9903 11:08:55.017360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9904 11:08:55.023979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9905 11:08:55.027955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9906 11:08:55.031061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9907 11:08:55.037458 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9908 11:08:55.041019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9909 11:08:55.047167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9910 11:08:55.050631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9911 11:08:55.057329 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9912 11:08:55.060629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9913 11:08:55.067271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9914 11:08:55.071109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9915 11:08:55.077366 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9916 11:08:55.080586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9917 11:08:55.087538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9918 11:08:55.090901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9919 11:08:55.098001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9920 11:08:55.100873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9921 11:08:55.107583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9922 11:08:55.110817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9923 11:08:55.117528 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9924 11:08:55.120864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9925 11:08:55.124297 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9926 11:08:55.127122 INFO: [APUAPC] vio 0
9927 11:08:55.134214 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9928 11:08:55.137324 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9929 11:08:55.141323 INFO: [APUAPC] D0_APC_0: 0x400510
9930 11:08:55.144134 INFO: [APUAPC] D0_APC_1: 0x0
9931 11:08:55.147701 INFO: [APUAPC] D0_APC_2: 0x1540
9932 11:08:55.151056 INFO: [APUAPC] D0_APC_3: 0x0
9933 11:08:55.154025 INFO: [APUAPC] D1_APC_0: 0xffffffff
9934 11:08:55.157116 INFO: [APUAPC] D1_APC_1: 0xffffffff
9935 11:08:55.160847 INFO: [APUAPC] D1_APC_2: 0x3fffff
9936 11:08:55.164303 INFO: [APUAPC] D1_APC_3: 0x0
9937 11:08:55.167467 INFO: [APUAPC] D2_APC_0: 0xffffffff
9938 11:08:55.170530 INFO: [APUAPC] D2_APC_1: 0xffffffff
9939 11:08:55.174133 INFO: [APUAPC] D2_APC_2: 0x3fffff
9940 11:08:55.174271 INFO: [APUAPC] D2_APC_3: 0x0
9941 11:08:55.180854 INFO: [APUAPC] D3_APC_0: 0xffffffff
9942 11:08:55.184360 INFO: [APUAPC] D3_APC_1: 0xffffffff
9943 11:08:55.187290 INFO: [APUAPC] D3_APC_2: 0x3fffff
9944 11:08:55.187417 INFO: [APUAPC] D3_APC_3: 0x0
9945 11:08:55.190641 INFO: [APUAPC] D4_APC_0: 0xffffffff
9946 11:08:55.194464 INFO: [APUAPC] D4_APC_1: 0xffffffff
9947 11:08:55.197591 INFO: [APUAPC] D4_APC_2: 0x3fffff
9948 11:08:55.200457 INFO: [APUAPC] D4_APC_3: 0x0
9949 11:08:55.203929 INFO: [APUAPC] D5_APC_0: 0xffffffff
9950 11:08:55.207091 INFO: [APUAPC] D5_APC_1: 0xffffffff
9951 11:08:55.210735 INFO: [APUAPC] D5_APC_2: 0x3fffff
9952 11:08:55.213744 INFO: [APUAPC] D5_APC_3: 0x0
9953 11:08:55.217221 INFO: [APUAPC] D6_APC_0: 0xffffffff
9954 11:08:55.220345 INFO: [APUAPC] D6_APC_1: 0xffffffff
9955 11:08:55.223803 INFO: [APUAPC] D6_APC_2: 0x3fffff
9956 11:08:55.227301 INFO: [APUAPC] D6_APC_3: 0x0
9957 11:08:55.230662 INFO: [APUAPC] D7_APC_0: 0xffffffff
9958 11:08:55.233790 INFO: [APUAPC] D7_APC_1: 0xffffffff
9959 11:08:55.237279 INFO: [APUAPC] D7_APC_2: 0x3fffff
9960 11:08:55.241324 INFO: [APUAPC] D7_APC_3: 0x0
9961 11:08:55.244298 INFO: [APUAPC] D8_APC_0: 0xffffffff
9962 11:08:55.247177 INFO: [APUAPC] D8_APC_1: 0xffffffff
9963 11:08:55.250428 INFO: [APUAPC] D8_APC_2: 0x3fffff
9964 11:08:55.254038 INFO: [APUAPC] D8_APC_3: 0x0
9965 11:08:55.257516 INFO: [APUAPC] D9_APC_0: 0xffffffff
9966 11:08:55.260677 INFO: [APUAPC] D9_APC_1: 0xffffffff
9967 11:08:55.264199 INFO: [APUAPC] D9_APC_2: 0x3fffff
9968 11:08:55.267658 INFO: [APUAPC] D9_APC_3: 0x0
9969 11:08:55.270903 INFO: [APUAPC] D10_APC_0: 0xffffffff
9970 11:08:55.274546 INFO: [APUAPC] D10_APC_1: 0xffffffff
9971 11:08:55.276878 INFO: [APUAPC] D10_APC_2: 0x3fffff
9972 11:08:55.281124 INFO: [APUAPC] D10_APC_3: 0x0
9973 11:08:55.284331 INFO: [APUAPC] D11_APC_0: 0xffffffff
9974 11:08:55.286897 INFO: [APUAPC] D11_APC_1: 0xffffffff
9975 11:08:55.290259 INFO: [APUAPC] D11_APC_2: 0x3fffff
9976 11:08:55.293827 INFO: [APUAPC] D11_APC_3: 0x0
9977 11:08:55.297019 INFO: [APUAPC] D12_APC_0: 0xffffffff
9978 11:08:55.300658 INFO: [APUAPC] D12_APC_1: 0xffffffff
9979 11:08:55.303611 INFO: [APUAPC] D12_APC_2: 0x3fffff
9980 11:08:55.307125 INFO: [APUAPC] D12_APC_3: 0x0
9981 11:08:55.310495 INFO: [APUAPC] D13_APC_0: 0xffffffff
9982 11:08:55.314129 INFO: [APUAPC] D13_APC_1: 0xffffffff
9983 11:08:55.317287 INFO: [APUAPC] D13_APC_2: 0x3fffff
9984 11:08:55.320503 INFO: [APUAPC] D13_APC_3: 0x0
9985 11:08:55.323648 INFO: [APUAPC] D14_APC_0: 0xffffffff
9986 11:08:55.327325 INFO: [APUAPC] D14_APC_1: 0xffffffff
9987 11:08:55.330388 INFO: [APUAPC] D14_APC_2: 0x3fffff
9988 11:08:55.333940 INFO: [APUAPC] D14_APC_3: 0x0
9989 11:08:55.337408 INFO: [APUAPC] D15_APC_0: 0xffffffff
9990 11:08:55.340992 INFO: [APUAPC] D15_APC_1: 0xffffffff
9991 11:08:55.343716 INFO: [APUAPC] D15_APC_2: 0x3fffff
9992 11:08:55.347844 INFO: [APUAPC] D15_APC_3: 0x0
9993 11:08:55.350953 INFO: [APUAPC] APC_CON: 0x4
9994 11:08:55.353741 INFO: [NOCDAPC] D0_APC_0: 0x0
9995 11:08:55.357551 INFO: [NOCDAPC] D0_APC_1: 0x0
9996 11:08:55.357633 INFO: [NOCDAPC] D1_APC_0: 0x0
9997 11:08:55.360673 INFO: [NOCDAPC] D1_APC_1: 0xfff
9998 11:08:55.363783 INFO: [NOCDAPC] D2_APC_0: 0x0
9999 11:08:55.367229 INFO: [NOCDAPC] D2_APC_1: 0xfff
10000 11:08:55.370313 INFO: [NOCDAPC] D3_APC_0: 0x0
10001 11:08:55.373647 INFO: [NOCDAPC] D3_APC_1: 0xfff
10002 11:08:55.377661 INFO: [NOCDAPC] D4_APC_0: 0x0
10003 11:08:55.380622 INFO: [NOCDAPC] D4_APC_1: 0xfff
10004 11:08:55.383813 INFO: [NOCDAPC] D5_APC_0: 0x0
10005 11:08:55.387069 INFO: [NOCDAPC] D5_APC_1: 0xfff
10006 11:08:55.387192 INFO: [NOCDAPC] D6_APC_0: 0x0
10007 11:08:55.390473 INFO: [NOCDAPC] D6_APC_1: 0xfff
10008 11:08:55.394645 INFO: [NOCDAPC] D7_APC_0: 0x0
10009 11:08:55.396996 INFO: [NOCDAPC] D7_APC_1: 0xfff
10010 11:08:55.400782 INFO: [NOCDAPC] D8_APC_0: 0x0
10011 11:08:55.403715 INFO: [NOCDAPC] D8_APC_1: 0xfff
10012 11:08:55.407401 INFO: [NOCDAPC] D9_APC_0: 0x0
10013 11:08:55.411533 INFO: [NOCDAPC] D9_APC_1: 0xfff
10014 11:08:55.414249 INFO: [NOCDAPC] D10_APC_0: 0x0
10015 11:08:55.417288 INFO: [NOCDAPC] D10_APC_1: 0xfff
10016 11:08:55.420487 INFO: [NOCDAPC] D11_APC_0: 0x0
10017 11:08:55.420607 INFO: [NOCDAPC] D11_APC_1: 0xfff
10018 11:08:55.423888 INFO: [NOCDAPC] D12_APC_0: 0x0
10019 11:08:55.427201 INFO: [NOCDAPC] D12_APC_1: 0xfff
10020 11:08:55.430344 INFO: [NOCDAPC] D13_APC_0: 0x0
10021 11:08:55.433931 INFO: [NOCDAPC] D13_APC_1: 0xfff
10022 11:08:55.437420 INFO: [NOCDAPC] D14_APC_0: 0x0
10023 11:08:55.440542 INFO: [NOCDAPC] D14_APC_1: 0xfff
10024 11:08:55.444268 INFO: [NOCDAPC] D15_APC_0: 0x0
10025 11:08:55.447664 INFO: [NOCDAPC] D15_APC_1: 0xfff
10026 11:08:55.450894 INFO: [NOCDAPC] APC_CON: 0x4
10027 11:08:55.454790 INFO: [APUAPC] set_apusys_apc done
10028 11:08:55.457291 INFO: [DEVAPC] devapc_init done
10029 11:08:55.460629 INFO: GICv3 without legacy support detected.
10030 11:08:55.463834 INFO: ARM GICv3 driver initialized in EL3
10031 11:08:55.467045 INFO: Maximum SPI INTID supported: 639
10032 11:08:55.473796 INFO: BL31: Initializing runtime services
10033 11:08:55.476865 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10034 11:08:55.480590 INFO: SPM: enable CPC mode
10035 11:08:55.486940 INFO: mcdi ready for mcusys-off-idle and system suspend
10036 11:08:55.490791 INFO: BL31: Preparing for EL3 exit to normal world
10037 11:08:55.493845 INFO: Entry point address = 0x80000000
10038 11:08:55.497245 INFO: SPSR = 0x8
10039 11:08:55.501854
10040 11:08:55.501937
10041 11:08:55.502003
10042 11:08:55.505022 Starting depthcharge on Spherion...
10043 11:08:55.505123
10044 11:08:55.505190 Wipe memory regions:
10045 11:08:55.505251
10046 11:08:55.505966 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10047 11:08:55.506068 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10048 11:08:55.506152 Setting prompt string to ['asurada:']
10049 11:08:55.506232 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10050 11:08:55.508456 [0x00000040000000, 0x00000054600000)
10051 11:08:55.630975
10052 11:08:55.631094 [0x00000054660000, 0x00000080000000)
10053 11:08:55.891628
10054 11:08:55.891766 [0x000000821a7280, 0x000000ffe64000)
10055 11:08:56.636505
10056 11:08:56.636643 [0x00000100000000, 0x00000240000000)
10057 11:08:58.526835
10058 11:08:58.529674 Initializing XHCI USB controller at 0x11200000.
10059 11:08:59.567821
10060 11:08:59.571209 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10061 11:08:59.571300
10062 11:08:59.571366
10063 11:08:59.571429
10064 11:08:59.571712 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10066 11:08:59.672081 asurada: tftpboot 192.168.201.1 12925658/tftp-deploy-8e9hyeki/kernel/image.itb 12925658/tftp-deploy-8e9hyeki/kernel/cmdline
10067 11:08:59.672226 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10068 11:08:59.672310 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10069 11:08:59.677396 tftpboot 192.168.201.1 12925658/tftp-deploy-8e9hyeki/kernel/image.itp-deploy-8e9hyeki/kernel/cmdline
10070 11:08:59.677480
10071 11:08:59.677562 Waiting for link
10072 11:08:59.837382
10073 11:08:59.837526 R8152: Initializing
10074 11:08:59.837598
10075 11:08:59.840761 Version 6 (ocp_data = 5c30)
10076 11:08:59.840844
10077 11:08:59.843489 R8152: Done initializing
10078 11:08:59.843572
10079 11:08:59.843639 Adding net device
10080 11:09:01.746361
10081 11:09:01.746552 done.
10082 11:09:01.746623
10083 11:09:01.746686 MAC: 00:24:32:30:78:52
10084 11:09:01.746746
10085 11:09:01.749639 Sending DHCP discover... done.
10086 11:09:01.749777
10087 11:09:01.752965 Waiting for reply... done.
10088 11:09:01.753087
10089 11:09:01.756277 Sending DHCP request... done.
10090 11:09:01.756398
10091 11:09:01.761050 Waiting for reply... done.
10092 11:09:01.761173
10093 11:09:01.761301 My ip is 192.168.201.14
10094 11:09:01.761427
10095 11:09:01.764514 The DHCP server ip is 192.168.201.1
10096 11:09:01.764635
10097 11:09:01.771110 TFTP server IP predefined by user: 192.168.201.1
10098 11:09:01.771250
10099 11:09:01.777695 Bootfile predefined by user: 12925658/tftp-deploy-8e9hyeki/kernel/image.itb
10100 11:09:01.777820
10101 11:09:01.780691 Sending tftp read request... done.
10102 11:09:01.780795
10103 11:09:01.784557 Waiting for the transfer...
10104 11:09:01.784658
10105 11:09:02.333806 00000000 ################################################################
10106 11:09:02.333974
10107 11:09:02.875047 00080000 ################################################################
10108 11:09:02.875193
10109 11:09:03.417953 00100000 ################################################################
10110 11:09:03.418123
10111 11:09:03.954465 00180000 ################################################################
10112 11:09:03.954612
10113 11:09:04.489949 00200000 ################################################################
10114 11:09:04.490124
10115 11:09:05.040441 00280000 ################################################################
10116 11:09:05.040589
10117 11:09:05.572045 00300000 ################################################################
10118 11:09:05.572231
10119 11:09:06.094275 00380000 ################################################################
10120 11:09:06.094445
10121 11:09:06.625900 00400000 ################################################################
10122 11:09:06.626038
10123 11:09:07.156997 00480000 ################################################################
10124 11:09:07.157171
10125 11:09:07.697808 00500000 ################################################################
10126 11:09:07.697948
10127 11:09:08.242817 00580000 ################################################################
10128 11:09:08.242992
10129 11:09:08.786331 00600000 ################################################################
10130 11:09:08.786515
10131 11:09:09.324695 00680000 ################################################################
10132 11:09:09.324867
10133 11:09:09.872435 00700000 ################################################################
10134 11:09:09.872633
10135 11:09:10.399335 00780000 ################################################################
10136 11:09:10.399510
10137 11:09:10.935524 00800000 ################################################################
10138 11:09:10.935714
10139 11:09:11.457396 00880000 ################################################################
10140 11:09:11.457586
10141 11:09:11.986953 00900000 ################################################################
10142 11:09:11.987122
10143 11:09:12.522405 00980000 ################################################################
10144 11:09:12.522549
10145 11:09:13.063030 00a00000 ################################################################
10146 11:09:13.063186
10147 11:09:13.580802 00a80000 ################################################################
10148 11:09:13.580949
10149 11:09:14.112583 00b00000 ################################################################
10150 11:09:14.112793
10151 11:09:14.633445 00b80000 ################################################################
10152 11:09:14.633652
10153 11:09:15.151743 00c00000 ################################################################
10154 11:09:15.151892
10155 11:09:15.672270 00c80000 ################################################################
10156 11:09:15.672437
10157 11:09:16.191311 00d00000 ################################################################
10158 11:09:16.191461
10159 11:09:16.739795 00d80000 ################################################################
10160 11:09:16.739941
10161 11:09:17.280378 00e00000 ################################################################
10162 11:09:17.280596
10163 11:09:17.796271 00e80000 ################################################################
10164 11:09:17.796418
10165 11:09:18.329749 00f00000 ################################################################
10166 11:09:18.329905
10167 11:09:18.868750 00f80000 ################################################################
10168 11:09:18.868881
10169 11:09:19.395596 01000000 ################################################################
10170 11:09:19.395794
10171 11:09:19.921501 01080000 ################################################################
10172 11:09:19.921688
10173 11:09:20.465524 01100000 ################################################################
10174 11:09:20.465718
10175 11:09:21.021595 01180000 ################################################################
10176 11:09:21.021744
10177 11:09:21.567636 01200000 ################################################################
10178 11:09:21.567820
10179 11:09:22.134233 01280000 ################################################################
10180 11:09:22.134414
10181 11:09:22.685898 01300000 ################################################################
10182 11:09:22.686072
10183 11:09:23.247969 01380000 ################################################################
10184 11:09:23.248103
10185 11:09:23.799761 01400000 ################################################################
10186 11:09:23.799933
10187 11:09:24.346967 01480000 ################################################################
10188 11:09:24.347097
10189 11:09:24.917317 01500000 ################################################################
10190 11:09:24.917470
10191 11:09:25.483545 01580000 ################################################################
10192 11:09:25.483697
10193 11:09:26.054690 01600000 ################################################################
10194 11:09:26.054833
10195 11:09:26.618548 01680000 ################################################################
10196 11:09:26.618680
10197 11:09:27.177974 01700000 ################################################################
10198 11:09:27.178184
10199 11:09:27.748406 01780000 ################################################################
10200 11:09:27.748603
10201 11:09:28.316151 01800000 ################################################################
10202 11:09:28.316290
10203 11:09:28.891926 01880000 ################################################################
10204 11:09:28.892073
10205 11:09:29.438941 01900000 ################################################################
10206 11:09:29.439165
10207 11:09:29.984212 01980000 ################################################################
10208 11:09:29.984420
10209 11:09:30.525695 01a00000 ################################################################
10210 11:09:30.525918
10211 11:09:31.081480 01a80000 ################################################################
10212 11:09:31.081633
10213 11:09:31.637978 01b00000 ################################################################
10214 11:09:31.638196
10215 11:09:32.192938 01b80000 ################################################################
10216 11:09:32.193088
10217 11:09:32.737304 01c00000 ################################################################
10218 11:09:32.737457
10219 11:09:33.304410 01c80000 ################################################################
10220 11:09:33.304624
10221 11:09:33.889216 01d00000 ################################################################
10222 11:09:33.889426
10223 11:09:34.470317 01d80000 ################################################################
10224 11:09:34.470592
10225 11:09:35.048151 01e00000 ################################################################
10226 11:09:35.048295
10227 11:09:35.627423 01e80000 ################################################################
10228 11:09:35.627573
10229 11:09:36.226081 01f00000 ################################################################
10230 11:09:36.226228
10231 11:09:36.817086 01f80000 ################################################################
10232 11:09:36.817312
10233 11:09:37.396600 02000000 ################################################################
10234 11:09:37.396796
10235 11:09:37.956407 02080000 ################################################################
10236 11:09:37.956556
10237 11:09:38.523235 02100000 ################################################################
10238 11:09:38.523425
10239 11:09:39.086910 02180000 ################################################################
10240 11:09:39.087112
10241 11:09:39.658394 02200000 ################################################################
10242 11:09:39.658588
10243 11:09:40.232022 02280000 ################################################################
10244 11:09:40.232160
10245 11:09:40.789950 02300000 ################################################################
10246 11:09:40.790088
10247 11:09:41.324845 02380000 ################################################################
10248 11:09:41.324997
10249 11:09:41.859916 02400000 ################################################################
10250 11:09:41.860106
10251 11:09:42.418105 02480000 ################################################################
10252 11:09:42.418238
10253 11:09:42.996014 02500000 ################################################################
10254 11:09:42.996150
10255 11:09:43.556730 02580000 ################################################################
10256 11:09:43.556889
10257 11:09:44.118047 02600000 ################################################################
10258 11:09:44.118185
10259 11:09:44.695287 02680000 ################################################################
10260 11:09:44.695434
10261 11:09:45.278617 02700000 ################################################################
10262 11:09:45.278781
10263 11:09:45.858068 02780000 ################################################################
10264 11:09:45.858249
10265 11:09:46.433895 02800000 ################################################################
10266 11:09:46.434039
10267 11:09:47.010671 02880000 ################################################################
10268 11:09:47.010820
10269 11:09:47.586040 02900000 ################################################################
10270 11:09:47.586252
10271 11:09:48.174790 02980000 ################################################################
10272 11:09:48.174939
10273 11:09:48.763479 02a00000 ################################################################
10274 11:09:48.763660
10275 11:09:49.328086 02a80000 ################################################################
10276 11:09:49.328266
10277 11:09:49.894515 02b00000 ################################################################
10278 11:09:49.894717
10279 11:09:50.455374 02b80000 ################################################################
10280 11:09:50.455574
10281 11:09:51.030943 02c00000 ################################################################
10282 11:09:51.031167
10283 11:09:51.593258 02c80000 ################################################################
10284 11:09:51.593412
10285 11:09:52.173577 02d00000 ################################################################
10286 11:09:52.173764
10287 11:09:52.749463 02d80000 ################################################################
10288 11:09:52.749618
10289 11:09:53.323844 02e00000 ################################################################
10290 11:09:53.324003
10291 11:09:53.898404 02e80000 ################################################################
10292 11:09:53.898605
10293 11:09:54.468720 02f00000 ################################################################
10294 11:09:54.468879
10295 11:09:55.026747 02f80000 ################################################################
10296 11:09:55.026904
10297 11:09:55.600346 03000000 ################################################################
10298 11:09:55.600507
10299 11:09:56.159611 03080000 ################################################################
10300 11:09:56.159817
10301 11:09:56.273758 03100000 ############## done.
10302 11:09:56.273957
10303 11:09:56.276926 The bootfile was 51487238 bytes long.
10304 11:09:56.277125
10305 11:09:56.280261 Sending tftp read request... done.
10306 11:09:56.280374
10307 11:09:56.283744 Waiting for the transfer...
10308 11:09:56.283860
10309 11:09:56.283954 00000000 # done.
10310 11:09:56.284045
10311 11:09:56.290259 Command line loaded dynamically from TFTP file: 12925658/tftp-deploy-8e9hyeki/kernel/cmdline
10312 11:09:56.290369
10313 11:09:56.306067 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10314 11:09:56.306186
10315 11:09:56.306279 Loading FIT.
10316 11:09:56.306370
10317 11:09:56.309904 Image ramdisk-1 has 39380225 bytes.
10318 11:09:56.310006
10319 11:09:56.313004 Image fdt-1 has 47278 bytes.
10320 11:09:56.313105
10321 11:09:56.316779 Image kernel-1 has 12057697 bytes.
10322 11:09:56.316879
10323 11:09:56.323001 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10324 11:09:56.323111
10325 11:09:56.343135 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10326 11:09:56.343268
10327 11:09:56.346280 Choosing best match conf-1 for compat google,spherion-rev2.
10328 11:09:56.351740
10329 11:09:56.356226 Connected to device vid:did:rid of 1ae0:0028:00
10330 11:09:56.362106
10331 11:09:56.365493 tpm_get_response: command 0x17b, return code 0x0
10332 11:09:56.365601
10333 11:09:56.373416 ec_init: CrosEC protocol v3 supported (256, 248)
10334 11:09:56.373513
10335 11:09:56.375881 tpm_cleanup: add release locality here.
10336 11:09:56.375964
10337 11:09:56.379431 Shutting down all USB controllers.
10338 11:09:56.379512
10339 11:09:56.382665 Removing current net device
10340 11:09:56.382746
10341 11:09:56.385704 Exiting depthcharge with code 4 at timestamp: 90275761
10342 11:09:56.389757
10343 11:09:56.392425 LZMA decompressing kernel-1 to 0x821a6718
10344 11:09:56.392526
10345 11:09:56.396263 LZMA decompressing kernel-1 to 0x40000000
10346 11:09:57.895263
10347 11:09:57.895454 jumping to kernel
10348 11:09:57.896209 end: 2.2.4 bootloader-commands (duration 00:01:02) [common]
10349 11:09:57.896350 start: 2.2.5 auto-login-action (timeout 00:03:23) [common]
10350 11:09:57.896462 Setting prompt string to ['Linux version [0-9]']
10351 11:09:57.896566 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10352 11:09:57.896702 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10353 11:09:57.977111
10354 11:09:57.979944 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10355 11:09:57.983807 start: 2.2.5.1 login-action (timeout 00:03:23) [common]
10356 11:09:57.983931 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10357 11:09:57.984033 Setting prompt string to []
10358 11:09:57.984148 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10359 11:09:57.984259 Using line separator: #'\n'#
10360 11:09:57.984351 No login prompt set.
10361 11:09:57.984447 Parsing kernel messages
10362 11:09:57.984534 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10363 11:09:57.984701 [login-action] Waiting for messages, (timeout 00:03:23)
10364 11:09:57.984800 Waiting using forced prompt support (timeout 00:01:41)
10365 11:09:58.003267 [ 0.000000] Linux version 6.1.80-cip16 (KernelCI@build-j128891-arm64-gcc-10-defconfig-arm64-chromebook-nrg4h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024
10366 11:09:58.007314 [ 0.000000] random: crng init done
10367 11:09:58.014297 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10368 11:09:58.014456 [ 0.000000] efi: UEFI not found.
10369 11:09:58.023139 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10370 11:09:58.030079 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10371 11:09:58.039766 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10372 11:09:58.050773 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10373 11:09:58.056963 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10374 11:09:58.059717 [ 0.000000] printk: bootconsole [mtk8250] enabled
10375 11:09:58.069036 [ 0.000000] NUMA: No NUMA configuration found
10376 11:09:58.076202 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10377 11:09:58.081792 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10378 11:09:58.081908 [ 0.000000] Zone ranges:
10379 11:09:58.088505 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10380 11:09:58.091908 [ 0.000000] DMA32 empty
10381 11:09:58.098948 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10382 11:09:58.101916 [ 0.000000] Movable zone start for each node
10383 11:09:58.105331 [ 0.000000] Early memory node ranges
10384 11:09:58.111977 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10385 11:09:58.118630 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10386 11:09:58.125581 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10387 11:09:58.131874 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10388 11:09:58.139915 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10389 11:09:58.146094 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10390 11:09:58.201265 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10391 11:09:58.208409 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10392 11:09:58.214713 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10393 11:09:58.218000 [ 0.000000] psci: probing for conduit method from DT.
10394 11:09:58.224682 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10395 11:09:58.228105 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10396 11:09:58.234750 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10397 11:09:58.238241 [ 0.000000] psci: SMC Calling Convention v1.2
10398 11:09:58.244791 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10399 11:09:58.247825 [ 0.000000] Detected VIPT I-cache on CPU0
10400 11:09:58.254476 [ 0.000000] CPU features: detected: GIC system register CPU interface
10401 11:09:58.261018 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10402 11:09:58.268253 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10403 11:09:58.274290 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10404 11:09:58.281087 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10405 11:09:58.287718 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10406 11:09:58.294321 [ 0.000000] alternatives: applying boot alternatives
10407 11:09:58.298377 [ 0.000000] Fallback order for Node 0: 0
10408 11:09:58.304506 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10409 11:09:58.307866 [ 0.000000] Policy zone: Normal
10410 11:09:58.324220 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10411 11:09:58.334970 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10412 11:09:58.344738 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10413 11:09:58.355214 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10414 11:09:58.362869 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10415 11:09:58.364759 <6>[ 0.000000] software IO TLB: area num 8.
10416 11:09:58.421972 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10417 11:09:58.571001 <6>[ 0.000000] Memory: 7928740K/8385536K available (18048K kernel code, 4118K rwdata, 19616K rodata, 8448K init, 616K bss, 424028K reserved, 32768K cma-reserved)
10418 11:09:58.577194 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10419 11:09:58.583814 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10420 11:09:58.587122 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10421 11:09:58.593669 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10422 11:09:58.600843 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10423 11:09:58.604300 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10424 11:09:58.613853 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10425 11:09:58.620592 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10426 11:09:58.623760 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10427 11:09:58.632041 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10428 11:09:58.635293 <6>[ 0.000000] GICv3: 608 SPIs implemented
10429 11:09:58.641698 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10430 11:09:58.645106 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10431 11:09:58.648135 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10432 11:09:58.658809 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10433 11:09:58.668682 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10434 11:09:58.682198 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10435 11:09:58.688294 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10436 11:09:58.697328 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10437 11:09:58.711046 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10438 11:09:58.717740 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10439 11:09:58.724298 <6>[ 0.009229] Console: colour dummy device 80x25
10440 11:09:58.733464 <6>[ 0.013959] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10441 11:09:58.740228 <6>[ 0.024466] pid_max: default: 32768 minimum: 301
10442 11:09:58.744087 <6>[ 0.029338] LSM: Security Framework initializing
10443 11:09:58.750263 <6>[ 0.034277] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10444 11:09:58.760625 <6>[ 0.042092] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10445 11:09:58.767268 <6>[ 0.051521] cblist_init_generic: Setting adjustable number of callback queues.
10446 11:09:58.774015 <6>[ 0.058965] cblist_init_generic: Setting shift to 3 and lim to 1.
10447 11:09:58.783897 <6>[ 0.065344] cblist_init_generic: Setting adjustable number of callback queues.
10448 11:09:58.789896 <6>[ 0.072771] cblist_init_generic: Setting shift to 3 and lim to 1.
10449 11:09:58.793483 <6>[ 0.079170] rcu: Hierarchical SRCU implementation.
10450 11:09:58.800997 <6>[ 0.084185] rcu: Max phase no-delay instances is 1000.
10451 11:09:58.806858 <6>[ 0.091213] EFI services will not be available.
10452 11:09:58.810739 <6>[ 0.096166] smp: Bringing up secondary CPUs ...
10453 11:09:58.818017 <6>[ 0.101219] Detected VIPT I-cache on CPU1
10454 11:09:58.825114 <6>[ 0.101290] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10455 11:09:58.832001 <6>[ 0.101320] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10456 11:09:58.834749 <6>[ 0.101657] Detected VIPT I-cache on CPU2
10457 11:09:58.841883 <6>[ 0.101706] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10458 11:09:58.847830 <6>[ 0.101721] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10459 11:09:58.855046 <6>[ 0.101980] Detected VIPT I-cache on CPU3
10460 11:09:58.861664 <6>[ 0.102025] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10461 11:09:58.867695 <6>[ 0.102039] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10462 11:09:58.871491 <6>[ 0.102346] CPU features: detected: Spectre-v4
10463 11:09:58.877881 <6>[ 0.102352] CPU features: detected: Spectre-BHB
10464 11:09:58.881527 <6>[ 0.102357] Detected PIPT I-cache on CPU4
10465 11:09:58.888150 <6>[ 0.102413] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10466 11:09:58.894376 <6>[ 0.102430] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10467 11:09:58.901191 <6>[ 0.102726] Detected PIPT I-cache on CPU5
10468 11:09:58.907883 <6>[ 0.102788] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10469 11:09:58.914559 <6>[ 0.102804] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10470 11:09:58.917568 <6>[ 0.103085] Detected PIPT I-cache on CPU6
10471 11:09:58.924539 <6>[ 0.103149] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10472 11:09:58.931785 <6>[ 0.103165] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10473 11:09:58.937735 <6>[ 0.103464] Detected PIPT I-cache on CPU7
10474 11:09:58.944226 <6>[ 0.103530] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10475 11:09:58.951247 <6>[ 0.103547] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10476 11:09:58.954340 <6>[ 0.103594] smp: Brought up 1 node, 8 CPUs
10477 11:09:58.961452 <6>[ 0.245004] SMP: Total of 8 processors activated.
10478 11:09:58.964457 <6>[ 0.249925] CPU features: detected: 32-bit EL0 Support
10479 11:09:58.974316 <6>[ 0.255322] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10480 11:09:58.980930 <6>[ 0.264123] CPU features: detected: Common not Private translations
10481 11:09:58.984219 <6>[ 0.270599] CPU features: detected: CRC32 instructions
10482 11:09:58.991439 <6>[ 0.275950] CPU features: detected: RCpc load-acquire (LDAPR)
10483 11:09:58.998030 <6>[ 0.281947] CPU features: detected: LSE atomic instructions
10484 11:09:59.004574 <6>[ 0.287728] CPU features: detected: Privileged Access Never
10485 11:09:59.007639 <6>[ 0.293508] CPU features: detected: RAS Extension Support
10486 11:09:59.014116 <6>[ 0.299151] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10487 11:09:59.020795 <6>[ 0.306368] CPU: All CPU(s) started at EL2
10488 11:09:59.027815 <6>[ 0.310685] alternatives: applying system-wide alternatives
10489 11:09:59.036144 <6>[ 0.321508] devtmpfs: initialized
10490 11:09:59.048309 <6>[ 0.330418] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10491 11:09:59.059021 <6>[ 0.340383] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10492 11:09:59.064811 <6>[ 0.348404] pinctrl core: initialized pinctrl subsystem
10493 11:09:59.068313 <6>[ 0.355066] DMI not present or invalid.
10494 11:09:59.075117 <6>[ 0.359478] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10495 11:09:59.081544 <6>[ 0.366328] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10496 11:09:59.091659 <6>[ 0.373915] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10497 11:09:59.099233 <6>[ 0.382135] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10498 11:09:59.105156 <6>[ 0.390375] audit: initializing netlink subsys (disabled)
10499 11:09:59.115370 <5>[ 0.396070] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10500 11:09:59.118630 <6>[ 0.396780] thermal_sys: Registered thermal governor 'step_wise'
10501 11:09:59.125182 <6>[ 0.404038] thermal_sys: Registered thermal governor 'power_allocator'
10502 11:09:59.131724 <6>[ 0.410294] cpuidle: using governor menu
10503 11:09:59.134874 <6>[ 0.421255] NET: Registered PF_QIPCRTR protocol family
10504 11:09:59.142255 <6>[ 0.426733] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10505 11:09:59.148609 <6>[ 0.433838] ASID allocator initialised with 32768 entries
10506 11:09:59.155698 <6>[ 0.440416] Serial: AMBA PL011 UART driver
10507 11:09:59.164005 <4>[ 0.449176] Trying to register duplicate clock ID: 134
10508 11:09:59.218311 <6>[ 0.506777] KASLR enabled
10509 11:09:59.232448 <6>[ 0.514494] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10510 11:09:59.238895 <6>[ 0.521509] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10511 11:09:59.246370 <6>[ 0.527998] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10512 11:09:59.252674 <6>[ 0.535003] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10513 11:09:59.259629 <6>[ 0.541489] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10514 11:09:59.265621 <6>[ 0.548493] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10515 11:09:59.272044 <6>[ 0.554980] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10516 11:09:59.278711 <6>[ 0.561984] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10517 11:09:59.282568 <6>[ 0.569519] ACPI: Interpreter disabled.
10518 11:09:59.290250 <6>[ 0.575940] iommu: Default domain type: Translated
10519 11:09:59.297613 <6>[ 0.581054] iommu: DMA domain TLB invalidation policy: strict mode
10520 11:09:59.300379 <5>[ 0.587719] SCSI subsystem initialized
10521 11:09:59.307022 <6>[ 0.591890] usbcore: registered new interface driver usbfs
10522 11:09:59.314290 <6>[ 0.597620] usbcore: registered new interface driver hub
10523 11:09:59.317461 <6>[ 0.603174] usbcore: registered new device driver usb
10524 11:09:59.323489 <6>[ 0.609277] pps_core: LinuxPPS API ver. 1 registered
10525 11:09:59.333995 <6>[ 0.614468] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10526 11:09:59.337012 <6>[ 0.623815] PTP clock support registered
10527 11:09:59.340606 <6>[ 0.628060] EDAC MC: Ver: 3.0.0
10528 11:09:59.347534 <6>[ 0.633215] FPGA manager framework
10529 11:09:59.350744 <6>[ 0.636896] Advanced Linux Sound Architecture Driver Initialized.
10530 11:09:59.354615 <6>[ 0.643679] vgaarb: loaded
10531 11:09:59.362548 <6>[ 0.646804] clocksource: Switched to clocksource arch_sys_counter
10532 11:09:59.368098 <5>[ 0.653238] VFS: Disk quotas dquot_6.6.0
10533 11:09:59.374850 <6>[ 0.657424] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10534 11:09:59.378281 <6>[ 0.664611] pnp: PnP ACPI: disabled
10535 11:09:59.385948 <6>[ 0.671276] NET: Registered PF_INET protocol family
10536 11:09:59.395340 <6>[ 0.676868] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10537 11:09:59.406935 <6>[ 0.689153] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10538 11:09:59.417187 <6>[ 0.697966] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10539 11:09:59.423545 <6>[ 0.705936] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10540 11:09:59.430285 <6>[ 0.714637] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10541 11:09:59.443078 <6>[ 0.724386] TCP: Hash tables configured (established 65536 bind 65536)
10542 11:09:59.449324 <6>[ 0.731245] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10543 11:09:59.455900 <6>[ 0.738445] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10544 11:09:59.461812 <6>[ 0.746144] NET: Registered PF_UNIX/PF_LOCAL protocol family
10545 11:09:59.468798 <6>[ 0.752325] RPC: Registered named UNIX socket transport module.
10546 11:09:59.472077 <6>[ 0.758476] RPC: Registered udp transport module.
10547 11:09:59.478848 <6>[ 0.763409] RPC: Registered tcp transport module.
10548 11:09:59.485416 <6>[ 0.768343] RPC: Registered tcp NFSv4.1 backchannel transport module.
10549 11:09:59.488512 <6>[ 0.775012] PCI: CLS 0 bytes, default 64
10550 11:09:59.491998 <6>[ 0.779407] Unpacking initramfs...
10551 11:09:59.516786 <6>[ 0.798916] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10552 11:09:59.526837 <6>[ 0.807583] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10553 11:09:59.529951 <6>[ 0.816443] kvm [1]: IPA Size Limit: 40 bits
10554 11:09:59.536321 <6>[ 0.820970] kvm [1]: GICv3: no GICV resource entry
10555 11:09:59.540477 <6>[ 0.825993] kvm [1]: disabling GICv2 emulation
10556 11:09:59.547137 <6>[ 0.830681] kvm [1]: GIC system register CPU interface enabled
10557 11:09:59.550030 <6>[ 0.836846] kvm [1]: vgic interrupt IRQ18
10558 11:09:59.556726 <6>[ 0.841199] kvm [1]: VHE mode initialized successfully
10559 11:09:59.563517 <5>[ 0.847738] Initialise system trusted keyrings
10560 11:09:59.570084 <6>[ 0.852540] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10561 11:09:59.580162 <6>[ 0.862758] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10562 11:09:59.583734 <5>[ 0.869170] NFS: Registering the id_resolver key type
10563 11:09:59.587114 <5>[ 0.874472] Key type id_resolver registered
10564 11:09:59.593904 <5>[ 0.878886] Key type id_legacy registered
10565 11:09:59.600392 <6>[ 0.883168] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10566 11:09:59.607338 <6>[ 0.890087] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10567 11:09:59.614347 <6>[ 0.897798] 9p: Installing v9fs 9p2000 file system support
10568 11:09:59.650342 <5>[ 0.935411] Key type asymmetric registered
10569 11:09:59.653062 <5>[ 0.939744] Asymmetric key parser 'x509' registered
10570 11:09:59.663367 <6>[ 0.944926] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10571 11:09:59.666323 <6>[ 0.952547] io scheduler mq-deadline registered
10572 11:09:59.669891 <6>[ 0.957315] io scheduler kyber registered
10573 11:09:59.689815 <6>[ 0.974416] EINJ: ACPI disabled.
10574 11:09:59.721134 <4>[ 0.999566] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10575 11:09:59.730717 <4>[ 1.010202] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10576 11:09:59.745111 <6>[ 1.030943] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10577 11:09:59.753221 <6>[ 1.038974] printk: console [ttyS0] disabled
10578 11:09:59.781318 <6>[ 1.063607] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10579 11:09:59.787970 <6>[ 1.073084] printk: console [ttyS0] enabled
10580 11:09:59.791616 <6>[ 1.073084] printk: console [ttyS0] enabled
10581 11:09:59.797767 <6>[ 1.081977] printk: bootconsole [mtk8250] disabled
10582 11:09:59.801343 <6>[ 1.081977] printk: bootconsole [mtk8250] disabled
10583 11:09:59.807918 <6>[ 1.093428] SuperH (H)SCI(F) driver initialized
10584 11:09:59.811494 <6>[ 1.098749] msm_serial: driver initialized
10585 11:09:59.825596 <6>[ 1.107807] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10586 11:09:59.835627 <6>[ 1.116359] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10587 11:09:59.842505 <6>[ 1.124899] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10588 11:09:59.852107 <6>[ 1.133527] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10589 11:09:59.862029 <6>[ 1.142233] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10590 11:09:59.869026 <6>[ 1.150954] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10591 11:09:59.878442 <6>[ 1.159494] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10592 11:09:59.885405 <6>[ 1.168296] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10593 11:09:59.896047 <6>[ 1.176838] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10594 11:09:59.907151 <6>[ 1.192507] loop: module loaded
10595 11:09:59.913746 <6>[ 1.198601] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10596 11:09:59.936941 <4>[ 1.221951] mtk-pmic-keys: Failed to locate of_node [id: -1]
10597 11:09:59.943313 <6>[ 1.228847] megasas: 07.719.03.00-rc1
10598 11:09:59.953345 <6>[ 1.238491] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10599 11:09:59.960747 <6>[ 1.246194] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10600 11:09:59.977169 <6>[ 1.262906] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10601 11:10:00.033750 <6>[ 1.313012] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10602 11:10:01.081450 <6>[ 2.367413] Freeing initrd memory: 38452K
10603 11:10:01.091988 <6>[ 2.377447] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10604 11:10:01.102737 <6>[ 2.388548] tun: Universal TUN/TAP device driver, 1.6
10605 11:10:01.106024 <6>[ 2.394623] thunder_xcv, ver 1.0
10606 11:10:01.109507 <6>[ 2.398132] thunder_bgx, ver 1.0
10607 11:10:01.112442 <6>[ 2.401629] nicpf, ver 1.0
10608 11:10:01.123654 <6>[ 2.405664] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10609 11:10:01.126947 <6>[ 2.413140] hns3: Copyright (c) 2017 Huawei Corporation.
10610 11:10:01.132960 <6>[ 2.418745] hclge is initializing
10611 11:10:01.136449 <6>[ 2.422325] e1000: Intel(R) PRO/1000 Network Driver
10612 11:10:01.143251 <6>[ 2.427454] e1000: Copyright (c) 1999-2006 Intel Corporation.
10613 11:10:01.146686 <6>[ 2.433467] e1000e: Intel(R) PRO/1000 Network Driver
10614 11:10:01.153309 <6>[ 2.438683] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10615 11:10:01.159826 <6>[ 2.444868] igb: Intel(R) Gigabit Ethernet Network Driver
10616 11:10:01.166780 <6>[ 2.450517] igb: Copyright (c) 2007-2014 Intel Corporation.
10617 11:10:01.172858 <6>[ 2.456358] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10618 11:10:01.179909 <6>[ 2.462877] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10619 11:10:01.183892 <6>[ 2.469346] sky2: driver version 1.30
10620 11:10:01.190289 <6>[ 2.474348] VFIO - User Level meta-driver version: 0.3
10621 11:10:01.197389 <6>[ 2.482598] usbcore: registered new interface driver usb-storage
10622 11:10:01.203165 <6>[ 2.489055] usbcore: registered new device driver onboard-usb-hub
10623 11:10:01.212713 <6>[ 2.498228] mt6397-rtc mt6359-rtc: registered as rtc0
10624 11:10:01.222367 <6>[ 2.503695] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T11:10:01 UTC (1709464201)
10625 11:10:01.225526 <6>[ 2.513262] i2c_dev: i2c /dev entries driver
10626 11:10:01.242497 <6>[ 2.525113] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10627 11:10:01.263093 <6>[ 2.548106] cpu cpu0: EM: created perf domain
10628 11:10:01.265741 <6>[ 2.553037] cpu cpu4: EM: created perf domain
10629 11:10:01.273203 <6>[ 2.558624] sdhci: Secure Digital Host Controller Interface driver
10630 11:10:01.279843 <6>[ 2.565056] sdhci: Copyright(c) Pierre Ossman
10631 11:10:01.286376 <6>[ 2.570021] Synopsys Designware Multimedia Card Interface Driver
10632 11:10:01.292719 <6>[ 2.576665] sdhci-pltfm: SDHCI platform and OF driver helper
10633 11:10:01.296976 <6>[ 2.576780] mmc0: CQHCI version 5.10
10634 11:10:01.303232 <6>[ 2.586722] ledtrig-cpu: registered to indicate activity on CPUs
10635 11:10:01.309586 <6>[ 2.593626] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10636 11:10:01.315720 <6>[ 2.600676] usbcore: registered new interface driver usbhid
10637 11:10:01.320020 <6>[ 2.606498] usbhid: USB HID core driver
10638 11:10:01.326239 <6>[ 2.610716] spi_master spi0: will run message pump with realtime priority
10639 11:10:01.370331 <6>[ 2.649530] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10640 11:10:01.389876 <6>[ 2.665285] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10641 11:10:01.392721 <6>[ 2.678871] mmc0: Command Queue Engine enabled
10642 11:10:01.399476 <6>[ 2.683619] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10643 11:10:01.407241 <6>[ 2.690794] cros-ec-spi spi0.0: Chrome EC device registered
10644 11:10:01.410363 <6>[ 2.691030] mmcblk0: mmc0:0001 DA4128 116 GiB
10645 11:10:01.422443 <6>[ 2.707980] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10646 11:10:01.429906 <6>[ 2.715346] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10647 11:10:01.436375 <6>[ 2.721300] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10648 11:10:01.442704 <6>[ 2.727426] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10649 11:10:01.456957 <6>[ 2.739250] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10650 11:10:01.464729 <6>[ 2.749963] NET: Registered PF_PACKET protocol family
10651 11:10:01.467623 <6>[ 2.755401] 9pnet: Installing 9P2000 support
10652 11:10:01.474443 <5>[ 2.759952] Key type dns_resolver registered
10653 11:10:01.477797 <6>[ 2.765104] registered taskstats version 1
10654 11:10:01.484224 <5>[ 2.769492] Loading compiled-in X.509 certificates
10655 11:10:01.514436 <4>[ 2.793641] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10656 11:10:01.524718 <4>[ 2.804425] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10657 11:10:01.530810 <3>[ 2.815026] debugfs: File 'uA_load' in directory '/' already present!
10658 11:10:01.537396 <3>[ 2.821735] debugfs: File 'min_uV' in directory '/' already present!
10659 11:10:01.544112 <3>[ 2.828343] debugfs: File 'max_uV' in directory '/' already present!
10660 11:10:01.550690 <3>[ 2.834953] debugfs: File 'constraint_flags' in directory '/' already present!
10661 11:10:01.562167 <3>[ 2.844791] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10662 11:10:01.574444 <6>[ 2.860357] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10663 11:10:01.581889 <6>[ 2.867157] xhci-mtk 11200000.usb: xHCI Host Controller
10664 11:10:01.587789 <6>[ 2.872662] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10665 11:10:01.598479 <6>[ 2.880520] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10666 11:10:01.604429 <6>[ 2.889960] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10667 11:10:01.611217 <6>[ 2.896179] xhci-mtk 11200000.usb: xHCI Host Controller
10668 11:10:01.617909 <6>[ 2.901715] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10669 11:10:01.624342 <6>[ 2.909372] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10670 11:10:01.631479 <6>[ 2.917334] hub 1-0:1.0: USB hub found
10671 11:10:01.634648 <6>[ 2.921363] hub 1-0:1.0: 1 port detected
10672 11:10:01.641420 <6>[ 2.925659] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10673 11:10:01.648807 <6>[ 2.934495] hub 2-0:1.0: USB hub found
10674 11:10:01.651882 <6>[ 2.938519] hub 2-0:1.0: 1 port detected
10675 11:10:01.660902 <6>[ 2.946547] mtk-msdc 11f70000.mmc: Got CD GPIO
10676 11:10:01.674068 <6>[ 2.956354] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10677 11:10:01.680534 <6>[ 2.964407] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10678 11:10:01.690546 <4>[ 2.972348] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10679 11:10:01.700319 <6>[ 2.981926] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10680 11:10:01.707051 <6>[ 2.990009] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10681 11:10:01.714096 <6>[ 2.998044] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10682 11:10:01.723575 <6>[ 3.005987] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10683 11:10:01.730743 <6>[ 3.013805] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10684 11:10:01.740823 <6>[ 3.021630] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10685 11:10:01.750832 <6>[ 3.032121] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10686 11:10:01.756913 <6>[ 3.040489] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10687 11:10:01.767382 <6>[ 3.048835] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10688 11:10:01.773359 <6>[ 3.057172] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10689 11:10:01.783497 <6>[ 3.065510] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10690 11:10:01.789964 <6>[ 3.073847] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10691 11:10:01.800487 <6>[ 3.082184] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10692 11:10:01.806825 <6>[ 3.090521] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10693 11:10:01.816785 <6>[ 3.098861] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10694 11:10:01.823143 <6>[ 3.107198] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10695 11:10:01.833225 <6>[ 3.115535] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10696 11:10:01.839597 <6>[ 3.123872] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10697 11:10:01.850113 <6>[ 3.132211] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10698 11:10:01.859624 <6>[ 3.140549] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10699 11:10:01.866385 <6>[ 3.148885] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10700 11:10:01.873729 <6>[ 3.157607] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10701 11:10:01.879474 <6>[ 3.164741] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10702 11:10:01.886145 <6>[ 3.171511] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10703 11:10:01.893254 <6>[ 3.178269] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10704 11:10:01.899428 <6>[ 3.185203] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10705 11:10:01.909314 <6>[ 3.192040] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10706 11:10:01.919482 <6>[ 3.201169] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10707 11:10:01.929738 <6>[ 3.210292] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10708 11:10:01.940443 <6>[ 3.219586] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10709 11:10:01.949681 <6>[ 3.229053] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10710 11:10:01.956128 <6>[ 3.238520] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10711 11:10:01.965798 <6>[ 3.247640] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10712 11:10:01.976038 <6>[ 3.257107] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10713 11:10:01.985977 <6>[ 3.266225] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10714 11:10:01.996234 <6>[ 3.275523] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10715 11:10:02.005627 <6>[ 3.285683] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10716 11:10:02.016114 <6>[ 3.297433] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10717 11:10:02.064615 <6>[ 3.347080] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10718 11:10:02.219873 <6>[ 3.505221] hub 1-1:1.0: USB hub found
10719 11:10:02.223420 <6>[ 3.509765] hub 1-1:1.0: 4 ports detected
10720 11:10:02.233289 <6>[ 3.518155] hub 1-1:1.0: USB hub found
10721 11:10:02.235954 <6>[ 3.522464] hub 1-1:1.0: 4 ports detected
10722 11:10:02.344906 <6>[ 3.627441] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10723 11:10:02.371326 <6>[ 3.657163] hub 2-1:1.0: USB hub found
10724 11:10:02.374430 <6>[ 3.661662] hub 2-1:1.0: 3 ports detected
10725 11:10:02.383767 <6>[ 3.669796] hub 2-1:1.0: USB hub found
10726 11:10:02.387272 <6>[ 3.674271] hub 2-1:1.0: 3 ports detected
10727 11:10:02.560919 <6>[ 3.843126] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10728 11:10:02.692113 <6>[ 3.977976] hub 1-1.4:1.0: USB hub found
10729 11:10:02.696186 <6>[ 3.982501] hub 1-1.4:1.0: 2 ports detected
10730 11:10:02.703968 <6>[ 3.989727] hub 1-1.4:1.0: USB hub found
10731 11:10:02.707051 <6>[ 3.994242] hub 1-1.4:1.0: 2 ports detected
10732 11:10:02.776933 <6>[ 4.059207] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10733 11:10:03.004387 <6>[ 4.287128] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10734 11:10:03.196537 <6>[ 4.479123] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10735 11:10:14.309508 <6>[ 15.600138] ALSA device list:
10736 11:10:14.316245 <6>[ 15.603431] No soundcards found.
10737 11:10:14.324253 <6>[ 15.611439] Freeing unused kernel memory: 8448K
10738 11:10:14.328247 <6>[ 15.616877] Run /init as init process
10739 11:10:14.357372 <6>[ 15.644617] NET: Registered PF_INET6 protocol family
10740 11:10:14.364629 <6>[ 15.650886] Segment Routing with IPv6
10741 11:10:14.367323 <6>[ 15.654825] In-situ OAM (IOAM) with IPv6
10742 11:10:14.400304 <30>[ 15.667914] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10743 11:10:14.404185 <30>[ 15.691648] systemd[1]: Detected architecture arm64.
10744 11:10:14.404271
10745 11:10:14.410285 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10746 11:10:14.410368
10747 11:10:14.423733 <30>[ 15.711156] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10748 11:10:14.573998 <30>[ 15.858319] systemd[1]: Queued start job for default target Graphical Interface.
10749 11:10:14.632665 <30>[ 15.919812] systemd[1]: Created slice system-getty.slice.
10750 11:10:14.639269 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10751 11:10:14.656405 <30>[ 15.943703] systemd[1]: Created slice system-modprobe.slice.
10752 11:10:14.663137 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10753 11:10:14.684854 <30>[ 15.972092] systemd[1]: Created slice system-serial\x2dgetty.slice.
10754 11:10:14.694877 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10755 11:10:14.708599 <30>[ 15.996080] systemd[1]: Created slice User and Session Slice.
10756 11:10:14.715447 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10757 11:10:14.735629 <30>[ 16.019794] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10758 11:10:14.745480 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10759 11:10:14.763978 <30>[ 16.047843] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10760 11:10:14.770320 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10761 11:10:14.795045 <30>[ 16.075586] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10762 11:10:14.802010 <30>[ 16.087845] systemd[1]: Reached target Local Encrypted Volumes.
10763 11:10:14.808257 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10764 11:10:14.824215 <30>[ 16.111674] systemd[1]: Reached target Paths.
10765 11:10:14.827909 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10766 11:10:14.844062 <30>[ 16.131106] systemd[1]: Reached target Remote File Systems.
10767 11:10:14.851117 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10768 11:10:14.863761 <30>[ 16.151074] systemd[1]: Reached target Slices.
10769 11:10:14.866941 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10770 11:10:14.884784 <30>[ 16.171117] systemd[1]: Reached target Swap.
10771 11:10:14.887119 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10772 11:10:14.907287 <30>[ 16.191573] systemd[1]: Listening on initctl Compatibility Named Pipe.
10773 11:10:14.915989 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10774 11:10:14.929240 <30>[ 16.216600] systemd[1]: Listening on Journal Audit Socket.
10775 11:10:14.935760 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10776 11:10:14.953290 <30>[ 16.240262] systemd[1]: Listening on Journal Socket (/dev/log).
10777 11:10:14.959865 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10778 11:10:14.977256 <30>[ 16.264317] systemd[1]: Listening on Journal Socket.
10779 11:10:14.983604 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10780 11:10:14.999473 <30>[ 16.283780] systemd[1]: Listening on Network Service Netlink Socket.
10781 11:10:15.006583 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10782 11:10:15.021248 <30>[ 16.308356] systemd[1]: Listening on udev Control Socket.
10783 11:10:15.027376 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10784 11:10:15.044599 <30>[ 16.332176] systemd[1]: Listening on udev Kernel Socket.
10785 11:10:15.051297 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10786 11:10:15.091877 <30>[ 16.379179] systemd[1]: Mounting Huge Pages File System...
10787 11:10:15.098550 Mounting [0;1;39mHuge Pages File System[0m...
10788 11:10:15.113305 <30>[ 16.400700] systemd[1]: Mounting POSIX Message Queue File System...
10789 11:10:15.120033 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10790 11:10:15.137529 <30>[ 16.425154] systemd[1]: Mounting Kernel Debug File System...
10791 11:10:15.144302 Mounting [0;1;39mKernel Debug File System[0m...
10792 11:10:15.163239 <30>[ 16.447385] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10793 11:10:15.195447 <30>[ 16.479333] systemd[1]: Starting Create list of static device nodes for the current kernel...
10794 11:10:15.202083 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10795 11:10:15.223763 <30>[ 16.511029] systemd[1]: Starting Load Kernel Module configfs...
10796 11:10:15.230283 Starting [0;1;39mLoad Kernel Module configfs[0m...
10797 11:10:15.256479 <30>[ 16.543332] systemd[1]: Starting Load Kernel Module drm...
10798 11:10:15.262740 Starting [0;1;39mLoad Kernel Module drm[0m...
10799 11:10:15.279045 <30>[ 16.563206] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10800 11:10:15.292917 <30>[ 16.580290] systemd[1]: Starting Journal Service...
10801 11:10:15.296123 Starting [0;1;39mJournal Service[0m...
10802 11:10:15.314037 <30>[ 16.601613] systemd[1]: Starting Load Kernel Modules...
10803 11:10:15.320750 Starting [0;1;39mLoad Kernel Modules[0m...
10804 11:10:15.342843 <30>[ 16.626729] systemd[1]: Starting Remount Root and Kernel File Systems...
10805 11:10:15.349982 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10806 11:10:15.366571 <30>[ 16.654225] systemd[1]: Starting Coldplug All udev Devices...
10807 11:10:15.373271 Starting [0;1;39mColdplug All udev Devices[0m...
10808 11:10:15.391240 <30>[ 16.678457] systemd[1]: Started Journal Service.
10809 11:10:15.397467 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10810 11:10:15.413745 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10811 11:10:15.433161 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10812 11:10:15.448726 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10813 11:10:15.469030 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10814 11:10:15.486331 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10815 11:10:15.505837 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10816 11:10:15.520914 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10817 11:10:15.540379 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10818 11:10:15.559673 See 'systemctl status systemd-remount-fs.service' for details.
10819 11:10:15.607907 Mounting [0;1;39mKernel Configuration File System[0m...
10820 11:10:15.633207 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10821 11:10:15.645840 <46>[ 16.930107] systemd-journald[175]: Received client request to flush runtime journal.
10822 11:10:15.656551 Starting [0;1;39mLoad/Save Random Seed[0m...
10823 11:10:15.675900 Starting [0;1;39mApply Kernel Variables[0m...
10824 11:10:15.701504 Starting [0;1;39mCreate System Users[0m...
10825 11:10:15.724989 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10826 11:10:15.740787 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10827 11:10:15.764874 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10828 11:10:15.781243 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10829 11:10:15.797483 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10830 11:10:15.813318 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10831 11:10:15.872220 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10832 11:10:15.896302 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10833 11:10:15.912199 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10834 11:10:15.931857 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10835 11:10:15.984805 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10836 11:10:16.008038 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10837 11:10:16.029573 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10838 11:10:16.051513 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10839 11:10:16.105710 Starting [0;1;39mNetwork Service[0m...
10840 11:10:16.126667 Starting [0;1;39mNetwork Time Synchronization[0m...
10841 11:10:16.151504 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10842 11:10:16.184775 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10843 11:10:16.200742 <6>[ 17.484814] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10844 11:10:16.210757 <6>[ 17.494283] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10845 11:10:16.220532 [[0;32m OK [<6>[ 17.502465] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10846 11:10:16.230834 0m] Found device<6>[ 17.512842] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10847 11:10:16.233628 [0;1;39m/dev/ttyS0[0m.
10848 11:10:16.241695 <6>[ 17.528852] remoteproc remoteproc0: scp is available
10849 11:10:16.247954 <6>[ 17.534275] remoteproc remoteproc0: powering up scp
10850 11:10:16.255629 <6>[ 17.539411] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10851 11:10:16.261566 <6>[ 17.548031] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10852 11:10:16.267762 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10853 11:10:16.277465 <6>[ 17.564933] mc: Linux media interface: v0.10
10854 11:10:16.299956 [[0;32m OK [<4>[ 17.585172] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10855 11:10:16.309480 0m] Created slic<3>[ 17.589573] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10856 11:10:16.319769 e [0;1;39msyste<4>[ 17.593795] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10857 11:10:16.326273 m-systemd\x2dbac<3>[ 17.602164] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10858 11:10:16.336345 <3>[ 17.602175] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10859 11:10:16.342707 <3>[ 17.602360] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10860 11:10:16.349574 klight.slice[0m<6>[ 17.622384] videodev: Linux video capture interface: v2.00
10861 11:10:16.359524 <3>[ 17.628454] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10862 11:10:16.366196 <6>[ 17.631442] usbcore: registered new device driver r8152-cfgselector
10863 11:10:16.366273 .
10864 11:10:16.372720 <6>[ 17.652092] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10865 11:10:16.379203 <3>[ 17.658294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10866 11:10:16.385711 <6>[ 17.665376] pci_bus 0000:00: root bus resource [bus 00-ff]
10867 11:10:16.395797 <3>[ 17.673500] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10868 11:10:16.402509 <3>[ 17.673505] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10869 11:10:16.409511 <3>[ 17.673572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10870 11:10:16.419145 <3>[ 17.673628] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10871 11:10:16.429398 <6>[ 17.674607] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10872 11:10:16.435752 <6>[ 17.674615] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10873 11:10:16.442877 <6>[ 17.674619] remoteproc remoteproc0: remote processor scp is now up
10874 11:10:16.449159 <6>[ 17.679319] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10875 11:10:16.459471 <6>[ 17.679328] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10876 11:10:16.465908 <6>[ 17.679386] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10877 11:10:16.472857 <3>[ 17.687443] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10878 11:10:16.479149 <6>[ 17.695507] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10879 11:10:16.489154 <3>[ 17.703943] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10880 11:10:16.495940 <6>[ 17.704496] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10881 11:10:16.505660 <6>[ 17.707489] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10882 11:10:16.515715 <6>[ 17.707902] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10883 11:10:16.520020 <6>[ 17.711796] pci 0000:00:00.0: supports D1 D2
10884 11:10:16.528666 <3>[ 17.720299] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10885 11:10:16.535141 <6>[ 17.721822] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10886 11:10:16.545560 <6>[ 17.725386] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10887 11:10:16.551549 <6>[ 17.727262] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10888 11:10:16.558544 <3>[ 17.733769] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10889 11:10:16.568404 <6>[ 17.735236] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10890 11:10:16.574711 <6>[ 17.738647] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10891 11:10:16.585089 <6>[ 17.743201] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10892 11:10:16.594773 <4>[ 17.749113] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10893 11:10:16.601900 <4>[ 17.749124] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10894 11:10:16.611273 <3>[ 17.750783] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10895 11:10:16.614710 <6>[ 17.757153] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10896 11:10:16.618210 <6>[ 17.757790] Bluetooth: Core ver 2.22
10897 11:10:16.626100 <6>[ 17.757853] NET: Registered PF_BLUETOOTH protocol family
10898 11:10:16.632734 <6>[ 17.757857] Bluetooth: HCI device and connection manager initialized
10899 11:10:16.636528 <6>[ 17.757880] Bluetooth: HCI socket layer initialized
10900 11:10:16.642964 <6>[ 17.757886] Bluetooth: L2CAP socket layer initialized
10901 11:10:16.646916 <6>[ 17.757901] Bluetooth: SCO socket layer initialized
10902 11:10:16.657034 <3>[ 17.765123] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10903 11:10:16.663172 <6>[ 17.772605] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10904 11:10:16.670553 <3>[ 17.780683] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10905 11:10:16.677391 <6>[ 17.781526] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10906 11:10:16.690644 <6>[ 17.782574] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10907 11:10:16.697494 <6>[ 17.782668] usbcore: registered new interface driver uvcvideo
10908 11:10:16.704718 <6>[ 17.788312] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10909 11:10:16.711131 <3>[ 17.798439] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10910 11:10:16.721219 <6>[ 17.807424] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10911 11:10:16.724654 <6>[ 17.808125] usbcore: registered new interface driver btusb
10912 11:10:16.735754 <4>[ 17.809136] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10913 11:10:16.742285 <3>[ 17.809155] Bluetooth: hci0: Failed to load firmware file (-2)
10914 11:10:16.748590 <3>[ 17.809160] Bluetooth: hci0: Failed to set up firmware (-2)
10915 11:10:16.758680 <4>[ 17.809163] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10916 11:10:16.762584 <6>[ 17.814951] r8152 2-1.3:1.0 eth0: v1.12.13
10917 11:10:16.765982 <6>[ 17.820130] pci 0000:01:00.0: supports D1 D2
10918 11:10:16.772544 <6>[ 17.829365] usbcore: registered new interface driver r8152
10919 11:10:16.779434 <6>[ 17.830210] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10920 11:10:16.786213 <6>[ 17.837646] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10921 11:10:16.792733 <6>[ 17.850951] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10922 11:10:16.802269 <4>[ 17.863257] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10923 11:10:16.806167 <4>[ 17.863257] Fallback method does not support PEC.
10924 11:10:16.815843 <6>[ 17.869127] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10925 11:10:16.822723 <6>[ 17.869323] usbcore: registered new interface driver cdc_ether
10926 11:10:16.826147 <6>[ 17.886946] usbcore: registered new interface driver r8153_ecm
10927 11:10:16.836349 <6>[ 17.894504] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10928 11:10:16.842664 <6>[ 17.921567] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10929 11:10:16.849340 <3>[ 17.921797] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10930 11:10:16.859419 <3>[ 17.924328] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 11:10:16.865984 <6>[ 17.924820] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10932 11:10:16.873430 <6>[ 17.924833] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10933 11:10:16.883185 <6>[ 17.924847] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10934 11:10:16.893431 <3>[ 17.927162] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 11:10:16.900808 <3>[ 17.963496] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 11:10:16.907429 <6>[ 17.964017] pci 0000:00:00.0: PCI bridge to [bus 01]
10937 11:10:16.914362 <3>[ 17.971081] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10938 11:10:16.924399 <6>[ 17.983463] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10939 11:10:16.928276 <6>[ 17.983624] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10940 11:10:16.938543 <3>[ 17.995946] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 11:10:16.945454 <6>[ 17.997455] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10942 11:10:16.952623 <3>[ 18.028182] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 11:10:16.958489 <6>[ 18.029072] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10944 11:10:16.966002 <3>[ 18.055444] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 11:10:16.975936 <5>[ 18.090392] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10946 11:10:16.986075 <3>[ 18.120720] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 11:10:16.992783 <5>[ 18.138017] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10948 11:10:16.999201 <3>[ 18.165188] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 11:10:17.009190 <5>[ 18.168256] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10950 11:10:17.018896 <4>[ 18.301174] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10951 11:10:17.022437 <6>[ 18.310125] cfg80211: failed to load regulatory.db
10952 11:10:17.028824 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10953 11:10:17.044394 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10954 11:10:17.071311 <6>[ 18.355804] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10955 11:10:17.078344 <6>[ 18.363404] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10956 11:10:17.100078 Starting [0;1;39mLoad/Save Screen …o<6>[ 18.387462] mt7921e 0000:01:00.0: ASIC revision: 79610010
10957 11:10:17.103131 f leds:white:kbd_backlight[0m...
10958 11:10:17.127361 Starting [0;1;39mNetwork Name Resolution[0m...
10959 11:10:17.149828 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10960 11:10:17.169279 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10961 11:10:17.185614 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10962 11:10:17.202670 <6>[ 18.487282] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10963 11:10:17.206282 <6>[ 18.487282]
10964 11:10:17.338577 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10965 11:10:17.351740 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10966 11:10:17.370942 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10967 11:10:17.383419 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10968 11:10:17.400227 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10969 11:10:17.423223 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10970 11:10:17.435716 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10971 11:10:17.455252 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10972 11:10:17.474636 [[0;32m OK [<6>[ 18.755918] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10973 11:10:17.477552 0m] Reached target [0;1;39mSockets[0m.
10974 11:10:17.491400 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10975 11:10:17.512163 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10976 11:10:17.539818 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10977 11:10:17.570058 Starting [0;1;39mUser Login Management[0m...
10978 11:10:17.588240 Starting [0;1;39mPermit User Sessions[0m...
10979 11:10:17.607155 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10980 11:10:17.656834 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10981 11:10:17.676437 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10982 11:10:17.692739 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10983 11:10:17.712014 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10984 11:10:17.729643 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10985 11:10:17.743959 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10986 11:10:17.761961 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10987 11:10:17.780045 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10988 11:10:17.836941 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10989 11:10:17.876558 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10990 11:10:17.923173
10991 11:10:17.923282
10992 11:10:17.926492 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10993 11:10:17.926575
10994 11:10:17.929928 debian-bullseye-arm64 login: root (automatic login)
10995 11:10:17.930012
10996 11:10:17.930078
10997 11:10:17.947606 Linux debian-bullseye-arm64 6.1.80-cip16 #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024 aarch64
10998 11:10:17.947693
10999 11:10:17.953868 The programs included with the Debian GNU/Linux system are free software;
11000 11:10:17.960184 the exact distribution terms for each program are described in the
11001 11:10:17.963778 individual files in /usr/share/doc/*/copyright.
11002 11:10:17.963862
11003 11:10:17.970775 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11004 11:10:17.974031 permitted by applicable law.
11005 11:10:17.974454 Matched prompt #10: / #
11007 11:10:17.974659 Setting prompt string to ['/ #']
11008 11:10:17.974751 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11010 11:10:17.974943 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11011 11:10:17.975029 start: 2.2.6 expect-shell-connection (timeout 00:03:03) [common]
11012 11:10:17.975098 Setting prompt string to ['/ #']
11013 11:10:17.975157 Forcing a shell prompt, looking for ['/ #']
11015 11:10:18.025371 / #
11016 11:10:18.025492 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11017 11:10:18.025571 Waiting using forced prompt support (timeout 00:02:30)
11018 11:10:18.030386
11019 11:10:18.030669 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11020 11:10:18.030769 start: 2.2.7 export-device-env (timeout 00:03:03) [common]
11021 11:10:18.030865 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11022 11:10:18.030953 end: 2.2 depthcharge-retry (duration 00:01:57) [common]
11023 11:10:18.031044 end: 2 depthcharge-action (duration 00:01:57) [common]
11024 11:10:18.031134 start: 3 lava-test-retry (timeout 00:07:41) [common]
11025 11:10:18.031221 start: 3.1 lava-test-shell (timeout 00:07:41) [common]
11026 11:10:18.031295 Using namespace: common
11028 11:10:18.131642 / # #
11029 11:10:18.131797 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11030 11:10:18.136906 #
11031 11:10:18.137204 Using /lava-12925658
11033 11:10:18.237507 / # export SHELL=/bin/sh
11034 11:10:18.237665 <6>[ 19.448428] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307852: link becomes ready
11035 11:10:18.237771 <6>[ 19.456461] r8152 2-1.3:1.0 enx002432307852: carrier on
11036 11:10:18.242669 export SHELL=/bin/sh
11038 11:10:18.343163 / # . /lava-12925658/environment
11039 11:10:18.343357 . /lava-12925658/environment<6>[ 19.610005] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11040 11:10:18.348188
11042 11:10:18.448705 / # /lava-12925658/bin/lava-test-runner /lava-12925658/0
11043 11:10:18.448829 Test shell timeout: 10s (minimum of the action and connection timeout)
11044 11:10:18.453865 /lava-12925658/bin/lava-test-runner /lava-12925658/0
11045 11:10:18.478913 + export TESTRUN_ID=0_v4l2-compliance-uvc
11046 11:10:18.481506 + cd /lava-12925658/0/tests/0_v4l2-compliance-uvc
11047 11:10:18.481589 + cat uuid
11048 11:10:18.485105 + UUID=12925658_1.5.2.3.1
11049 11:10:18.485188 + set +x
11050 11:10:18.491859 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 12925658_1.5.2.3.1>
11051 11:10:18.492121 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 12925658_1.5.2.3.1
11052 11:10:18.492196 Starting test lava.0_v4l2-compliance-uvc (12925658_1.5.2.3.1)
11053 11:10:18.492282 Skipping test definition patterns.
11054 11:10:18.495133 + /usr/bin/v4l2-parser.sh -d uvcvideo
11055 11:10:18.501889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11056 11:10:18.501968 device: /dev/video0
11057 11:10:18.502203 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11059 11:10:25.093198 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11060 11:10:25.103860 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11061 11:10:25.112019
11062 11:10:25.128340 Compliance test for uvcvideo device /dev/video0:
11063 11:10:25.135262
11064 11:10:25.150931 Driver Info:
11065 11:10:25.162517 Driver name : uvcvideo
11066 11:10:25.175365 Card type : HD User Facing: HD User Facing
11067 11:10:25.186234 Bus info : usb-11200000.usb-1.4.1
11068 11:10:25.194419 Driver version : 6.1.80
11069 11:10:25.204799 Capabilities : 0x84a00001
11070 11:10:25.216342 Metadata Capture
11071 11:10:25.230435 Streaming
11072 11:10:25.242998 Extended Pix Format
11073 11:10:25.251627 Device Capabilities
11074 11:10:25.263446 Device Caps : 0x04200001
11075 11:10:25.276445 Streaming
11076 11:10:25.292244 Extended Pix Format
11077 11:10:25.303601 Media Driver Info:
11078 11:10:25.317847 Driver name : uvcvideo
11079 11:10:25.334737 Model : HD User Facing: HD User Facing
11080 11:10:25.343026 Serial : 200901010001
11081 11:10:25.357068 Bus info : usb-11200000.usb-1.4.1
11082 11:10:25.365835 Media version : 6.1.80
11083 11:10:25.380741 Hardware revision: 0x00009758 (38744)
11084 11:10:25.388976 Driver version : 6.1.80
11085 11:10:25.399609 Interface Info:
11086 11:10:25.415100 <LAVA_SIGNAL_TESTSET START Interface-Info>
11087 11:10:25.415184 ID : 0x03000002
11088 11:10:25.415425 Received signal: <TESTSET> START Interface-Info
11089 11:10:25.415501 Starting test_set Interface-Info
11090 11:10:25.427174 Type : V4L Video
11091 11:10:25.439288 Entity Info:
11092 11:10:25.446269 <LAVA_SIGNAL_TESTSET STOP>
11093 11:10:25.446536 Received signal: <TESTSET> STOP
11094 11:10:25.446628 Closing test_set Interface-Info
11095 11:10:25.455503 <LAVA_SIGNAL_TESTSET START Entity-Info>
11096 11:10:25.455758 Received signal: <TESTSET> START Entity-Info
11097 11:10:25.455828 Starting test_set Entity-Info
11098 11:10:25.458891 ID : 0x00000001 (1)
11099 11:10:25.469831 Name : HD User Facing: HD User Facing
11100 11:10:25.479548 Function : V4L2 I/O
11101 11:10:25.491844 Flags : default
11102 11:10:25.501682 Pad 0x01000007 : 0: Sink
11103 11:10:25.522535 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11104 11:10:25.527270
11105 11:10:25.539442 Required ioctls:
11106 11:10:25.545939 <LAVA_SIGNAL_TESTSET STOP>
11107 11:10:25.546194 Received signal: <TESTSET> STOP
11108 11:10:25.546266 Closing test_set Entity-Info
11109 11:10:25.555654 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11110 11:10:25.555907 Received signal: <TESTSET> START Required-ioctls
11111 11:10:25.555979 Starting test_set Required-ioctls
11112 11:10:25.558542 test MC information (see 'Media Driver Info' above): OK
11113 11:10:25.583395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11114 11:10:25.583696 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11116 11:10:25.586701 test VIDIOC_QUERYCAP: OK
11117 11:10:25.604818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11118 11:10:25.605123 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11120 11:10:25.608583 test invalid ioctls: OK
11121 11:10:25.634639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11122 11:10:25.634769
11123 11:10:25.635057 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11125 11:10:25.646862 Allow for multiple opens:
11126 11:10:25.654323 <LAVA_SIGNAL_TESTSET STOP>
11127 11:10:25.654648 Received signal: <TESTSET> STOP
11128 11:10:25.654763 Closing test_set Required-ioctls
11129 11:10:25.667599 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11130 11:10:25.667902 Received signal: <TESTSET> START Allow-for-multiple-opens
11131 11:10:25.668022 Starting test_set Allow-for-multiple-opens
11132 11:10:25.670311 test second /dev/video0 open: OK
11133 11:10:25.692503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11134 11:10:25.692809 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11136 11:10:25.695836 test VIDIOC_QUERYCAP: OK
11137 11:10:25.718557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11138 11:10:25.718867 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11140 11:10:25.721489 test VIDIOC_G/S_PRIORITY: OK
11141 11:10:25.741540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11142 11:10:25.741872 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11144 11:10:25.745027 test for unlimited opens: OK
11145 11:10:25.771396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11146 11:10:25.771483
11147 11:10:25.771719 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11149 11:10:25.783246 Debug ioctls:
11150 11:10:25.791863 <LAVA_SIGNAL_TESTSET STOP>
11151 11:10:25.792133 Received signal: <TESTSET> STOP
11152 11:10:25.792204 Closing test_set Allow-for-multiple-opens
11153 11:10:25.803092 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11154 11:10:25.803343 Received signal: <TESTSET> START Debug-ioctls
11155 11:10:25.803415 Starting test_set Debug-ioctls
11156 11:10:25.805860 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11157 11:10:25.827557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11158 11:10:25.827818 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11160 11:10:25.834027 test VIDIOC_LOG_STATUS: OK (Not Supported)
11161 11:10:25.852899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11162 11:10:25.853026
11163 11:10:25.853319 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11165 11:10:25.864347 Input ioctls:
11166 11:10:25.872216 <LAVA_SIGNAL_TESTSET STOP>
11167 11:10:25.872515 Received signal: <TESTSET> STOP
11168 11:10:25.872633 Closing test_set Debug-ioctls
11169 11:10:25.881914 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11170 11:10:25.882197 Received signal: <TESTSET> START Input-ioctls
11171 11:10:25.882285 Starting test_set Input-ioctls
11172 11:10:25.885091 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11173 11:10:25.910109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11174 11:10:25.910389 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11176 11:10:25.913274 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11177 11:10:25.934536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11178 11:10:25.934789 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11180 11:10:25.941991 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11181 11:10:25.959913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11182 11:10:25.960225 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11184 11:10:25.966618 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11185 11:10:25.985600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11186 11:10:25.985905 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11188 11:10:25.988193 test VIDIOC_G/S/ENUMINPUT: OK
11189 11:10:26.009694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11190 11:10:26.009999 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11192 11:10:26.012942 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11193 11:10:26.033003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11194 11:10:26.033323 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11196 11:10:26.037218 Inputs: 1 Audio Inputs: 0 Tuners: 0
11197 11:10:26.043582
11198 11:10:26.062556 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11199 11:10:26.088123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11200 11:10:26.088432 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11202 11:10:26.095773 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11203 11:10:26.115026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11204 11:10:26.115282 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11206 11:10:26.117965 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11207 11:10:26.140255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11208 11:10:26.140513 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11210 11:10:26.146971 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11211 11:10:26.166542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11212 11:10:26.166798 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11214 11:10:26.173254 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11215 11:10:26.191254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11216 11:10:26.191338
11217 11:10:26.191573 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11219 11:10:26.211101 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11220 11:10:26.232666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11221 11:10:26.232919 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11223 11:10:26.239056 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11224 11:10:26.263294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11225 11:10:26.263559 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11227 11:10:26.266934 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11228 11:10:26.282636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11229 11:10:26.282889 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11231 11:10:26.285735 test VIDIOC_G/S_EDID: OK (Not Supported)
11232 11:10:26.308690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11233 11:10:26.308774
11234 11:10:26.309009 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11236 11:10:26.320136 Control ioctls (Input 0):
11237 11:10:26.328316 <LAVA_SIGNAL_TESTSET STOP>
11238 11:10:26.328568 Received signal: <TESTSET> STOP
11239 11:10:26.328637 Closing test_set Input-ioctls
11240 11:10:26.338040 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11241 11:10:26.338292 Received signal: <TESTSET> START Control-ioctls-Input-0
11242 11:10:26.338362 Starting test_set Control-ioctls-Input-0
11243 11:10:26.341292 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11244 11:10:26.369394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11245 11:10:26.369479 test VIDIOC_QUERYCTRL: OK
11246 11:10:26.369715 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11248 11:10:26.394735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11249 11:10:26.394989 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11251 11:10:26.398290 test VIDIOC_G/S_CTRL: OK
11252 11:10:26.422604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11253 11:10:26.422863 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11255 11:10:26.426081 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11256 11:10:26.449026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11257 11:10:26.449281 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11259 11:10:26.455608 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11260 11:10:26.478036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11261 11:10:26.478290 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11263 11:10:26.481070 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11264 11:10:26.500193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11265 11:10:26.500458 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11267 11:10:26.503718 Standard Controls: 16 Private Controls: 0
11268 11:10:26.510144
11269 11:10:26.522090 Format ioctls (Input 0):
11270 11:10:26.528615 <LAVA_SIGNAL_TESTSET STOP>
11271 11:10:26.528867 Received signal: <TESTSET> STOP
11272 11:10:26.528937 Closing test_set Control-ioctls-Input-0
11273 11:10:26.538062 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11274 11:10:26.538332 Received signal: <TESTSET> START Format-ioctls-Input-0
11275 11:10:26.538412 Starting test_set Format-ioctls-Input-0
11276 11:10:26.541650 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11277 11:10:26.567944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11278 11:10:26.568198 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11280 11:10:26.570835 test VIDIOC_G/S_PARM: OK
11281 11:10:26.589874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11282 11:10:26.590127 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11284 11:10:26.593119 test VIDIOC_G_FBUF: OK (Not Supported)
11285 11:10:26.616014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11286 11:10:26.616319 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11288 11:10:26.619514 test VIDIOC_G_FMT: OK
11289 11:10:26.643047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11290 11:10:26.643367 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11292 11:10:26.645860 test VIDIOC_TRY_FMT: OK
11293 11:10:26.668524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11294 11:10:26.668829 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11296 11:10:26.674551 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11297 11:10:26.681192 test VIDIOC_S_FMT: OK
11298 11:10:26.708171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11299 11:10:26.708445 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11301 11:10:26.711568 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11302 11:10:26.733781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11303 11:10:26.734059 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11305 11:10:26.737296 test Cropping: OK (Not Supported)
11306 11:10:26.761124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11307 11:10:26.761382 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11309 11:10:26.764592 test Composing: OK (Not Supported)
11310 11:10:26.786376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11311 11:10:26.786640 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11313 11:10:26.789784 test Scaling: OK (Not Supported)
11314 11:10:26.810965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11315 11:10:26.811052
11316 11:10:26.811288 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11318 11:10:26.822269 Codec ioctls (Input 0):
11319 11:10:26.829777 <LAVA_SIGNAL_TESTSET STOP>
11320 11:10:26.830031 Received signal: <TESTSET> STOP
11321 11:10:26.830102 Closing test_set Format-ioctls-Input-0
11322 11:10:26.839895 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11323 11:10:26.840150 Received signal: <TESTSET> START Codec-ioctls-Input-0
11324 11:10:26.840222 Starting test_set Codec-ioctls-Input-0
11325 11:10:26.842965 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11326 11:10:26.864363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11327 11:10:26.864620 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11329 11:10:26.870404 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11330 11:10:26.888465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11331 11:10:26.888717 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11333 11:10:26.894416 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11334 11:10:26.912983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11335 11:10:26.913066
11336 11:10:26.913301 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11338 11:10:26.924030 Buffer ioctls (Input 0):
11339 11:10:26.931673 <LAVA_SIGNAL_TESTSET STOP>
11340 11:10:26.931925 Received signal: <TESTSET> STOP
11341 11:10:26.931996 Closing test_set Codec-ioctls-Input-0
11342 11:10:26.941314 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11343 11:10:26.941567 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11344 11:10:26.941640 Starting test_set Buffer-ioctls-Input-0
11345 11:10:26.944191 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11346 11:10:26.969640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11347 11:10:26.969728 test VIDIOC_EXPBUF: OK
11348 11:10:26.969966 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11350 11:10:26.992219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11351 11:10:26.992467 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11353 11:10:26.995955 test Requests: OK (Not Supported)
11354 11:10:27.016436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11355 11:10:27.016572
11356 11:10:27.016854 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11358 11:10:27.029432 Test input 0:
11359 11:10:27.038952
11360 11:10:27.050213 Streaming ioctls:
11361 11:10:27.056965 <LAVA_SIGNAL_TESTSET STOP>
11362 11:10:27.057217 Received signal: <TESTSET> STOP
11363 11:10:27.057286 Closing test_set Buffer-ioctls-Input-0
11364 11:10:27.073763 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11365 11:10:27.074016 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11366 11:10:27.074088 Starting test_set Streaming-ioctls_Test-input-0
11367 11:10:27.076971 test read/write: OK (Not Supported)
11368 11:10:27.098555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11369 11:10:27.098828 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11371 11:10:27.101399 test blocking wait: OK
11372 11:10:27.123420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11373 11:10:27.123675 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11375 11:10:27.132996 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11376 11:10:27.136647 test MMAP (no poll): FAIL
11377 11:10:27.160437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11378 11:10:27.160753 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11380 11:10:27.170836 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11381 11:10:27.170957 test MMAP (select): FAIL
11382 11:10:27.196038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11383 11:10:27.196321 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11385 11:10:27.206353 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11386 11:10:27.210457 test MMAP (epoll): FAIL
11387 11:10:27.236282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11388 11:10:27.236367
11389 11:10:27.236604 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11391 11:10:27.249459
11392 11:10:27.433492
11393 11:10:27.443195 test USERPTR (no poll): OK
11394 11:10:27.466530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11395 11:10:27.466617
11396 11:10:27.466858 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11398 11:10:27.480468
11399 11:10:27.671963
11400 11:10:27.679898 test USERPTR (select): OK
11401 11:10:27.709029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11402 11:10:27.709361 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11404 11:10:27.715026 test DMABUF: Cannot test, specify --expbuf-device
11405 11:10:27.720813
11406 11:10:27.738334 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11407 11:10:27.742391 <LAVA_TEST_RUNNER EXIT>
11408 11:10:27.742703 ok: lava_test_shell seems to have completed
11409 11:10:27.742829 Marking unfinished test run as failed
11411 11:10:27.744856 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11412 11:10:27.745067 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11413 11:10:27.745217 end: 3 lava-test-retry (duration 00:00:10) [common]
11414 11:10:27.745379 start: 4 finalize (timeout 00:07:31) [common]
11415 11:10:27.745536 start: 4.1 power-off (timeout 00:00:30) [common]
11416 11:10:27.745826 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11417 11:10:27.823164 >> Command sent successfully.
11418 11:10:27.826556 Returned 0 in 0 seconds
11419 11:10:27.927020 end: 4.1 power-off (duration 00:00:00) [common]
11421 11:10:27.927347 start: 4.2 read-feedback (timeout 00:07:31) [common]
11422 11:10:27.927626 Listened to connection for namespace 'common' for up to 1s
11423 11:10:28.928583 Finalising connection for namespace 'common'
11424 11:10:28.928775 Disconnecting from shell: Finalise
11425 11:10:28.928852 / #
11426 11:10:29.029186 end: 4.2 read-feedback (duration 00:00:01) [common]
11427 11:10:29.029360 end: 4 finalize (duration 00:00:01) [common]
11428 11:10:29.029475 Cleaning after the job
11429 11:10:29.029595 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925658/tftp-deploy-8e9hyeki/ramdisk
11430 11:10:29.035071 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925658/tftp-deploy-8e9hyeki/kernel
11431 11:10:29.050713 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925658/tftp-deploy-8e9hyeki/dtb
11432 11:10:29.050899 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925658/tftp-deploy-8e9hyeki/modules
11433 11:10:29.057925 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12925658
11434 11:10:29.125657 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12925658
11435 11:10:29.125839 Job finished correctly