Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 27
- Boot result: PASS
- Errors: 1
- Warnings: 1
- Kernel Warnings: 16
1 11:04:25.390876 lava-dispatcher, installed at version: 2024.01
2 11:04:25.391094 start: 0 validate
3 11:04:25.391233 Start time: 2024-03-03 11:04:25.391225+00:00 (UTC)
4 11:04:25.391368 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:04:25.391499 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 11:04:25.661418 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:04:25.662129 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:04:46.933335 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:04:46.934023 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:04:47.202691 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:04:47.203430 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:04:51.475440 validate duration: 26.08
14 11:04:51.476809 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:04:51.477395 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:04:51.477881 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:04:51.478504 Not decompressing ramdisk as can be used compressed.
18 11:04:51.478970 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 11:04:51.479327 saving as /var/lib/lava/dispatcher/tmp/12925635/tftp-deploy-3ozrlg70/ramdisk/rootfs.cpio.gz
20 11:04:51.479709 total size: 8181372 (7 MB)
21 11:04:51.748795 progress 0 % (0 MB)
22 11:04:51.751244 progress 5 % (0 MB)
23 11:04:51.753466 progress 10 % (0 MB)
24 11:04:51.755742 progress 15 % (1 MB)
25 11:04:51.757840 progress 20 % (1 MB)
26 11:04:51.760138 progress 25 % (1 MB)
27 11:04:51.762227 progress 30 % (2 MB)
28 11:04:51.764660 progress 35 % (2 MB)
29 11:04:51.766761 progress 40 % (3 MB)
30 11:04:51.769066 progress 45 % (3 MB)
31 11:04:51.771163 progress 50 % (3 MB)
32 11:04:51.773435 progress 55 % (4 MB)
33 11:04:51.775560 progress 60 % (4 MB)
34 11:04:51.777893 progress 65 % (5 MB)
35 11:04:51.780017 progress 70 % (5 MB)
36 11:04:51.782291 progress 75 % (5 MB)
37 11:04:51.784406 progress 80 % (6 MB)
38 11:04:51.786617 progress 85 % (6 MB)
39 11:04:51.788705 progress 90 % (7 MB)
40 11:04:51.790908 progress 95 % (7 MB)
41 11:04:51.793025 progress 100 % (7 MB)
42 11:04:51.793229 7 MB downloaded in 0.31 s (24.88 MB/s)
43 11:04:51.793390 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:04:51.793630 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:04:51.793716 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:04:51.793803 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:04:51.793945 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:04:51.794014 saving as /var/lib/lava/dispatcher/tmp/12925635/tftp-deploy-3ozrlg70/kernel/Image
50 11:04:51.794077 total size: 51599872 (49 MB)
51 11:04:51.794138 No compression specified
52 11:04:51.795207 progress 0 % (0 MB)
53 11:04:51.808434 progress 5 % (2 MB)
54 11:04:51.821866 progress 10 % (4 MB)
55 11:04:51.835334 progress 15 % (7 MB)
56 11:04:51.848580 progress 20 % (9 MB)
57 11:04:51.862019 progress 25 % (12 MB)
58 11:04:51.875613 progress 30 % (14 MB)
59 11:04:51.889233 progress 35 % (17 MB)
60 11:04:51.902496 progress 40 % (19 MB)
61 11:04:51.916239 progress 45 % (22 MB)
62 11:04:51.930209 progress 50 % (24 MB)
63 11:04:51.944017 progress 55 % (27 MB)
64 11:04:51.957303 progress 60 % (29 MB)
65 11:04:51.971271 progress 65 % (32 MB)
66 11:04:51.985139 progress 70 % (34 MB)
67 11:04:51.998810 progress 75 % (36 MB)
68 11:04:52.012150 progress 80 % (39 MB)
69 11:04:52.025708 progress 85 % (41 MB)
70 11:04:52.039163 progress 90 % (44 MB)
71 11:04:52.052201 progress 95 % (46 MB)
72 11:04:52.065374 progress 100 % (49 MB)
73 11:04:52.065640 49 MB downloaded in 0.27 s (181.21 MB/s)
74 11:04:52.065855 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:04:52.066099 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:04:52.066188 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:04:52.066274 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:04:52.066411 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:04:52.066480 saving as /var/lib/lava/dispatcher/tmp/12925635/tftp-deploy-3ozrlg70/dtb/mt8192-asurada-spherion-r0.dtb
81 11:04:52.066540 total size: 47278 (0 MB)
82 11:04:52.066601 No compression specified
83 11:04:52.067712 progress 69 % (0 MB)
84 11:04:52.068001 progress 100 % (0 MB)
85 11:04:52.068158 0 MB downloaded in 0.00 s (27.92 MB/s)
86 11:04:52.068285 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:04:52.068506 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:04:52.068589 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:04:52.068672 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:04:52.068786 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:04:52.068853 saving as /var/lib/lava/dispatcher/tmp/12925635/tftp-deploy-3ozrlg70/modules/modules.tar
93 11:04:52.068912 total size: 8628476 (8 MB)
94 11:04:52.068972 Using unxz to decompress xz
95 11:04:52.073226 progress 0 % (0 MB)
96 11:04:52.094210 progress 5 % (0 MB)
97 11:04:52.119420 progress 10 % (0 MB)
98 11:04:52.144891 progress 15 % (1 MB)
99 11:04:52.169475 progress 20 % (1 MB)
100 11:04:52.195679 progress 25 % (2 MB)
101 11:04:52.221245 progress 30 % (2 MB)
102 11:04:52.251932 progress 35 % (2 MB)
103 11:04:52.278966 progress 40 % (3 MB)
104 11:04:52.305911 progress 45 % (3 MB)
105 11:04:52.334674 progress 50 % (4 MB)
106 11:04:52.361285 progress 55 % (4 MB)
107 11:04:52.386578 progress 60 % (4 MB)
108 11:04:52.413238 progress 65 % (5 MB)
109 11:04:52.438935 progress 70 % (5 MB)
110 11:04:52.465162 progress 75 % (6 MB)
111 11:04:52.492133 progress 80 % (6 MB)
112 11:04:52.517230 progress 85 % (7 MB)
113 11:04:52.542518 progress 90 % (7 MB)
114 11:04:52.574087 progress 95 % (7 MB)
115 11:04:52.604369 progress 100 % (8 MB)
116 11:04:52.609890 8 MB downloaded in 0.54 s (15.21 MB/s)
117 11:04:52.610229 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:04:52.610633 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:04:52.610776 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:04:52.610916 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:04:52.611061 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:04:52.611190 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:04:52.611483 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm
125 11:04:52.611688 makedir: /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin
126 11:04:52.611840 makedir: /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/tests
127 11:04:52.611984 makedir: /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/results
128 11:04:52.612158 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-add-keys
129 11:04:52.612360 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-add-sources
130 11:04:52.612544 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-background-process-start
131 11:04:52.612734 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-background-process-stop
132 11:04:52.612914 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-common-functions
133 11:04:52.613092 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-echo-ipv4
134 11:04:52.613281 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-install-packages
135 11:04:52.613459 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-installed-packages
136 11:04:52.613638 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-os-build
137 11:04:52.613825 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-probe-channel
138 11:04:52.614004 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-probe-ip
139 11:04:52.614185 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-target-ip
140 11:04:52.614374 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-target-mac
141 11:04:52.614555 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-target-storage
142 11:04:52.614776 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-test-case
143 11:04:52.614963 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-test-event
144 11:04:52.615142 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-test-feedback
145 11:04:52.615360 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-test-raise
146 11:04:52.615556 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-test-reference
147 11:04:52.615748 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-test-runner
148 11:04:52.615935 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-test-set
149 11:04:52.616121 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-test-shell
150 11:04:52.616324 Updating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-install-packages (oe)
151 11:04:52.616563 Updating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/bin/lava-installed-packages (oe)
152 11:04:52.616744 Creating /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/environment
153 11:04:52.616898 LAVA metadata
154 11:04:52.617011 - LAVA_JOB_ID=12925635
155 11:04:52.617115 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:04:52.617275 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:04:52.617376 skipped lava-vland-overlay
158 11:04:52.617491 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:04:52.617612 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:04:52.617714 skipped lava-multinode-overlay
161 11:04:52.617826 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:04:52.617953 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:04:52.618071 Loading test definitions
164 11:04:52.618212 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:04:52.618328 Using /lava-12925635 at stage 0
166 11:04:52.618797 uuid=12925635_1.5.2.3.1 testdef=None
167 11:04:52.618920 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:04:52.619047 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:04:52.619842 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:04:52.620183 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:04:52.621116 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:04:52.621465 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:04:52.622377 runner path: /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/0/tests/0_dmesg test_uuid 12925635_1.5.2.3.1
176 11:04:52.622590 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:04:52.622935 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 11:04:52.623041 Using /lava-12925635 at stage 1
180 11:04:52.623483 uuid=12925635_1.5.2.3.5 testdef=None
181 11:04:52.623605 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 11:04:52.623736 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 11:04:52.624437 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 11:04:52.624778 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 11:04:52.625734 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 11:04:52.626075 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 11:04:52.627076 runner path: /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/1/tests/1_bootrr test_uuid 12925635_1.5.2.3.5
190 11:04:52.627281 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 11:04:52.627599 Creating lava-test-runner.conf files
193 11:04:52.627708 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/0 for stage 0
194 11:04:52.627841 - 0_dmesg
195 11:04:52.627956 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12925635/lava-overlay-01616jwm/lava-12925635/1 for stage 1
196 11:04:52.628090 - 1_bootrr
197 11:04:52.628226 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 11:04:52.628353 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 11:04:52.639813 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 11:04:52.639976 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 11:04:52.640104 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 11:04:52.640238 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 11:04:52.640365 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 11:04:52.895067 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 11:04:52.895589 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 11:04:52.895763 extracting modules file /var/lib/lava/dispatcher/tmp/12925635/tftp-deploy-3ozrlg70/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925635/extract-overlay-ramdisk-clb5hw0k/ramdisk
207 11:04:53.173134 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 11:04:53.173327 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 11:04:53.173459 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925635/compress-overlay-4e6f6e51/overlay-1.5.2.4.tar.gz to ramdisk
210 11:04:53.173546 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925635/compress-overlay-4e6f6e51/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12925635/extract-overlay-ramdisk-clb5hw0k/ramdisk
211 11:04:53.181948 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 11:04:53.182106 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 11:04:53.182200 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 11:04:53.182291 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 11:04:53.182371 Building ramdisk /var/lib/lava/dispatcher/tmp/12925635/extract-overlay-ramdisk-clb5hw0k/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12925635/extract-overlay-ramdisk-clb5hw0k/ramdisk
216 11:04:53.590148 >> 145361 blocks
217 11:04:56.009611 rename /var/lib/lava/dispatcher/tmp/12925635/extract-overlay-ramdisk-clb5hw0k/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12925635/tftp-deploy-3ozrlg70/ramdisk/ramdisk.cpio.gz
218 11:04:56.010122 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 11:04:56.010265 start: 1.5.8 prepare-kernel (timeout 00:09:55) [common]
220 11:04:56.010383 start: 1.5.8.1 prepare-fit (timeout 00:09:55) [common]
221 11:04:56.010512 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12925635/tftp-deploy-3ozrlg70/kernel/Image'
222 11:05:09.695627 Returned 0 in 13 seconds
223 11:05:09.796325 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12925635/tftp-deploy-3ozrlg70/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12925635/tftp-deploy-3ozrlg70/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12925635/tftp-deploy-3ozrlg70/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12925635/tftp-deploy-3ozrlg70/kernel/image.itb
224 11:05:10.194699 output: FIT description: Kernel Image image with one or more FDT blobs
225 11:05:10.195098 output: Created: Sun Mar 3 11:05:10 2024
226 11:05:10.195202 output: Image 0 (kernel-1)
227 11:05:10.195288 output: Description:
228 11:05:10.195388 output: Created: Sun Mar 3 11:05:10 2024
229 11:05:10.195485 output: Type: Kernel Image
230 11:05:10.195583 output: Compression: lzma compressed
231 11:05:10.195709 output: Data Size: 12057697 Bytes = 11775.09 KiB = 11.50 MiB
232 11:05:10.195825 output: Architecture: AArch64
233 11:05:10.195927 output: OS: Linux
234 11:05:10.196027 output: Load Address: 0x00000000
235 11:05:10.196126 output: Entry Point: 0x00000000
236 11:05:10.196225 output: Hash algo: crc32
237 11:05:10.196324 output: Hash value: cf43f4f3
238 11:05:10.196422 output: Image 1 (fdt-1)
239 11:05:10.196521 output: Description: mt8192-asurada-spherion-r0
240 11:05:10.196614 output: Created: Sun Mar 3 11:05:10 2024
241 11:05:10.196707 output: Type: Flat Device Tree
242 11:05:10.196799 output: Compression: uncompressed
243 11:05:10.196891 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 11:05:10.196982 output: Architecture: AArch64
245 11:05:10.197073 output: Hash algo: crc32
246 11:05:10.197164 output: Hash value: cc4352de
247 11:05:10.197255 output: Image 2 (ramdisk-1)
248 11:05:10.197346 output: Description: unavailable
249 11:05:10.197436 output: Created: Sun Mar 3 11:05:10 2024
250 11:05:10.197527 output: Type: RAMDisk Image
251 11:05:10.197618 output: Compression: Unknown Compression
252 11:05:10.197709 output: Data Size: 21411961 Bytes = 20910.12 KiB = 20.42 MiB
253 11:05:10.197801 output: Architecture: AArch64
254 11:05:10.197892 output: OS: Linux
255 11:05:10.197982 output: Load Address: unavailable
256 11:05:10.198073 output: Entry Point: unavailable
257 11:05:10.198163 output: Hash algo: crc32
258 11:05:10.198255 output: Hash value: 86edefb3
259 11:05:10.198347 output: Default Configuration: 'conf-1'
260 11:05:10.198438 output: Configuration 0 (conf-1)
261 11:05:10.198529 output: Description: mt8192-asurada-spherion-r0
262 11:05:10.198620 output: Kernel: kernel-1
263 11:05:10.198711 output: Init Ramdisk: ramdisk-1
264 11:05:10.198802 output: FDT: fdt-1
265 11:05:10.198893 output: Loadables: kernel-1
266 11:05:10.198984 output:
267 11:05:10.199228 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
268 11:05:10.199368 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
269 11:05:10.199516 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
270 11:05:10.199655 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
271 11:05:10.199817 No LXC device requested
272 11:05:10.199941 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 11:05:10.200068 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
274 11:05:10.200190 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 11:05:10.200299 Checking files for TFTP limit of 4294967296 bytes.
276 11:05:10.200974 end: 1 tftp-deploy (duration 00:00:19) [common]
277 11:05:10.201115 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 11:05:10.201243 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 11:05:10.201424 substitutions:
280 11:05:10.201522 - {DTB}: 12925635/tftp-deploy-3ozrlg70/dtb/mt8192-asurada-spherion-r0.dtb
281 11:05:10.201622 - {INITRD}: 12925635/tftp-deploy-3ozrlg70/ramdisk/ramdisk.cpio.gz
282 11:05:10.201745 - {KERNEL}: 12925635/tftp-deploy-3ozrlg70/kernel/Image
283 11:05:10.201853 - {LAVA_MAC}: None
284 11:05:10.201975 - {PRESEED_CONFIG}: None
285 11:05:10.202071 - {PRESEED_LOCAL}: None
286 11:05:10.202159 - {RAMDISK}: 12925635/tftp-deploy-3ozrlg70/ramdisk/ramdisk.cpio.gz
287 11:05:10.202245 - {ROOT_PART}: None
288 11:05:10.202330 - {ROOT}: None
289 11:05:10.202414 - {SERVER_IP}: 192.168.201.1
290 11:05:10.202497 - {TEE}: None
291 11:05:10.202580 Parsed boot commands:
292 11:05:10.202662 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 11:05:10.202888 Parsed boot commands: tftpboot 192.168.201.1 12925635/tftp-deploy-3ozrlg70/kernel/image.itb 12925635/tftp-deploy-3ozrlg70/kernel/cmdline
294 11:05:10.202977 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 11:05:10.203061 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 11:05:10.203150 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 11:05:10.203237 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 11:05:10.203309 Not connected, no need to disconnect.
299 11:05:10.203382 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 11:05:10.203466 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 11:05:10.203531 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
302 11:05:10.207811 Setting prompt string to ['lava-test: # ']
303 11:05:10.208245 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 11:05:10.208381 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 11:05:10.208511 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 11:05:10.208629 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 11:05:10.209051 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
308 11:05:15.346978 >> Command sent successfully.
309 11:05:15.349548 Returned 0 in 5 seconds
310 11:05:15.449984 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 11:05:15.450337 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 11:05:15.450435 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 11:05:15.450526 Setting prompt string to 'Starting depthcharge on Spherion...'
315 11:05:15.450598 Changing prompt to 'Starting depthcharge on Spherion...'
316 11:05:15.450666 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 11:05:15.450935 [Enter `^Ec?' for help]
318 11:05:15.623185
319 11:05:15.623350
320 11:05:15.623425 F0: 102B 0000
321 11:05:15.623494
322 11:05:15.626329 F3: 1001 0000 [0200]
323 11:05:15.626419
324 11:05:15.626486 F3: 1001 0000
325 11:05:15.626549
326 11:05:15.626613 F7: 102D 0000
327 11:05:15.626691
328 11:05:15.629745 F1: 0000 0000
329 11:05:15.629829
330 11:05:15.629895 V0: 0000 0000 [0001]
331 11:05:15.629962
332 11:05:15.632536 00: 0007 8000
333 11:05:15.632624
334 11:05:15.632691 01: 0000 0000
335 11:05:15.632755
336 11:05:15.636201 BP: 0C00 0209 [0000]
337 11:05:15.636284
338 11:05:15.636352 G0: 1182 0000
339 11:05:15.636415
340 11:05:15.640136 EC: 0000 0021 [4000]
341 11:05:15.640220
342 11:05:15.640288 S7: 0000 0000 [0000]
343 11:05:15.640351
344 11:05:15.643595 CC: 0000 0000 [0001]
345 11:05:15.643725
346 11:05:15.643794 T0: 0000 0040 [010F]
347 11:05:15.643857
348 11:05:15.646837 Jump to BL
349 11:05:15.646921
350 11:05:15.669530
351 11:05:15.669637
352 11:05:15.669706
353 11:05:15.676640 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 11:05:15.680401 ARM64: Exception handlers installed.
355 11:05:15.684514 ARM64: Testing exception
356 11:05:15.687284 ARM64: Done test exception
357 11:05:15.693758 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 11:05:15.704131 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 11:05:15.710899 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 11:05:15.720899 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 11:05:15.727983 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 11:05:15.737398 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 11:05:15.747863 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 11:05:15.755074 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 11:05:15.773722 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 11:05:15.776600 WDT: Last reset was cold boot
367 11:05:15.779574 SPI1(PAD0) initialized at 2873684 Hz
368 11:05:15.782678 SPI5(PAD0) initialized at 992727 Hz
369 11:05:15.785930 VBOOT: Loading verstage.
370 11:05:15.793134 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 11:05:15.796545 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 11:05:15.799306 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 11:05:15.802642 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 11:05:15.810396 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 11:05:15.817414 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 11:05:15.828268 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 11:05:15.828412
378 11:05:15.828494
379 11:05:15.837596 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 11:05:15.841023 ARM64: Exception handlers installed.
381 11:05:15.844254 ARM64: Testing exception
382 11:05:15.844343 ARM64: Done test exception
383 11:05:15.850723 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 11:05:15.854377 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 11:05:15.868638 Probing TPM: . done!
386 11:05:15.868737 TPM ready after 0 ms
387 11:05:15.875833 Connected to device vid:did:rid of 1ae0:0028:00
388 11:05:15.939536 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
389 11:05:15.939770 Initialized TPM device CR50 revision 0
390 11:05:15.951811 tlcl_send_startup: Startup return code is 0
391 11:05:15.951919 TPM: setup succeeded
392 11:05:15.962931 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 11:05:15.971455 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 11:05:15.983644 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 11:05:15.993752 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 11:05:15.996905 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 11:05:16.003661 in-header: 03 07 00 00 08 00 00 00
398 11:05:16.007195 in-data: aa e4 47 04 13 02 00 00
399 11:05:16.010837 Chrome EC: UHEPI supported
400 11:05:16.018421 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 11:05:16.022449 in-header: 03 ad 00 00 08 00 00 00
402 11:05:16.022569 in-data: 00 20 20 08 00 00 00 00
403 11:05:16.025787 Phase 1
404 11:05:16.029182 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 11:05:16.035820 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 11:05:16.039533 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 11:05:16.043285 Recovery requested (1009000e)
408 11:05:16.052500 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 11:05:16.058966 tlcl_extend: response is 0
410 11:05:16.068502 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 11:05:16.074038 tlcl_extend: response is 0
412 11:05:16.081451 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 11:05:16.100925 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
414 11:05:16.107970 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 11:05:16.108072
416 11:05:16.108139
417 11:05:16.118499 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 11:05:16.122119 ARM64: Exception handlers installed.
419 11:05:16.122214 ARM64: Testing exception
420 11:05:16.125591 ARM64: Done test exception
421 11:05:16.146725 pmic_efuse_setting: Set efuses in 11 msecs
422 11:05:16.150569 pmwrap_interface_init: Select PMIF_VLD_RDY
423 11:05:16.157093 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 11:05:16.160312 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 11:05:16.167388 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 11:05:16.171173 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 11:05:16.174692 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 11:05:16.182215 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 11:05:16.185331 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 11:05:16.189336 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 11:05:16.192887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 11:05:16.199585 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 11:05:16.203622 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 11:05:16.206853 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 11:05:16.214372 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 11:05:16.220352 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 11:05:16.223753 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 11:05:16.231441 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 11:05:16.234968 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 11:05:16.243035 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 11:05:16.246214 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 11:05:16.253705 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 11:05:16.257193 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 11:05:16.264382 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 11:05:16.271680 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 11:05:16.275148 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 11:05:16.279092 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 11:05:16.286312 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 11:05:16.289971 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 11:05:16.297174 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 11:05:16.300868 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 11:05:16.304607 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 11:05:16.311860 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 11:05:16.316148 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 11:05:16.319176 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 11:05:16.326440 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 11:05:16.330425 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 11:05:16.337632 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 11:05:16.340504 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 11:05:16.344889 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 11:05:16.351552 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 11:05:16.355412 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 11:05:16.359362 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 11:05:16.362587 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 11:05:16.366438 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 11:05:16.373421 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 11:05:16.376643 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 11:05:16.380412 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 11:05:16.384286 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 11:05:16.387895 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 11:05:16.395078 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 11:05:16.399077 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 11:05:16.402647 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 11:05:16.409865 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 11:05:16.417168 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 11:05:16.421894 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 11:05:16.432669 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 11:05:16.439348 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 11:05:16.443278 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 11:05:16.446850 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 11:05:16.454080 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 11:05:16.461464 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x1
483 11:05:16.465535 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 11:05:16.469137 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
485 11:05:16.475267 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 11:05:16.484149 [RTC]rtc_get_frequency_meter,154: input=15, output=834
487 11:05:16.493769 [RTC]rtc_get_frequency_meter,154: input=7, output=708
488 11:05:16.502868 [RTC]rtc_get_frequency_meter,154: input=11, output=771
489 11:05:16.512897 [RTC]rtc_get_frequency_meter,154: input=13, output=803
490 11:05:16.522249 [RTC]rtc_get_frequency_meter,154: input=12, output=788
491 11:05:16.531467 [RTC]rtc_get_frequency_meter,154: input=12, output=788
492 11:05:16.541413 [RTC]rtc_get_frequency_meter,154: input=13, output=803
493 11:05:16.545087 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
494 11:05:16.548792 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
495 11:05:16.556138 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 11:05:16.560043 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
497 11:05:16.563805 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 11:05:16.567295 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
499 11:05:16.570917 ADC[4]: Raw value=905618 ID=7
500 11:05:16.571005 ADC[3]: Raw value=214021 ID=1
501 11:05:16.574160 RAM Code: 0x71
502 11:05:16.578265 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 11:05:16.585450 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 11:05:16.592428 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 11:05:16.600054 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 11:05:16.603389 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 11:05:16.606692 in-header: 03 07 00 00 08 00 00 00
508 11:05:16.610673 in-data: aa e4 47 04 13 02 00 00
509 11:05:16.610765 Chrome EC: UHEPI supported
510 11:05:16.617788 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 11:05:16.621920 in-header: 03 ed 00 00 08 00 00 00
512 11:05:16.625451 in-data: 80 20 60 08 00 00 00 00
513 11:05:16.629089 MRC: failed to locate region type 0.
514 11:05:16.636379 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 11:05:16.636509 DRAM-K: Running full calibration
516 11:05:16.643606 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 11:05:16.647059 header.status = 0x0
518 11:05:16.651027 header.version = 0x6 (expected: 0x6)
519 11:05:16.651118 header.size = 0xd00 (expected: 0xd00)
520 11:05:16.654297 header.flags = 0x0
521 11:05:16.661843 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 11:05:16.678427 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
523 11:05:16.685351 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 11:05:16.689225 dram_init: ddr_geometry: 2
525 11:05:16.689318 [EMI] MDL number = 2
526 11:05:16.692927 [EMI] Get MDL freq = 0
527 11:05:16.693014 dram_init: ddr_type: 0
528 11:05:16.697329 is_discrete_lpddr4: 1
529 11:05:16.700787 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 11:05:16.700874
531 11:05:16.700940
532 11:05:16.701002 [Bian_co] ETT version 0.0.0.1
533 11:05:16.707836 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 11:05:16.707930
535 11:05:16.711429 dramc_set_vcore_voltage set vcore to 650000
536 11:05:16.711513 Read voltage for 800, 4
537 11:05:16.715130 Vio18 = 0
538 11:05:16.715309 Vcore = 650000
539 11:05:16.715426 Vdram = 0
540 11:05:16.719154 Vddq = 0
541 11:05:16.719286 Vmddr = 0
542 11:05:16.719390 dram_init: config_dvfs: 1
543 11:05:16.726002 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 11:05:16.729835 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 11:05:16.733380 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
546 11:05:16.737235 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
547 11:05:16.740889 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
548 11:05:16.745247 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
549 11:05:16.748140 MEM_TYPE=3, freq_sel=18
550 11:05:16.752032 sv_algorithm_assistance_LP4_1600
551 11:05:16.754992 ============ PULL DRAM RESETB DOWN ============
552 11:05:16.758723 ========== PULL DRAM RESETB DOWN end =========
553 11:05:16.765483 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 11:05:16.768791 ===================================
555 11:05:16.768889 LPDDR4 DRAM CONFIGURATION
556 11:05:16.771956 ===================================
557 11:05:16.775184 EX_ROW_EN[0] = 0x0
558 11:05:16.775274 EX_ROW_EN[1] = 0x0
559 11:05:16.778749 LP4Y_EN = 0x0
560 11:05:16.781785 WORK_FSP = 0x0
561 11:05:16.781870 WL = 0x2
562 11:05:16.785005 RL = 0x2
563 11:05:16.785136 BL = 0x2
564 11:05:16.788787 RPST = 0x0
565 11:05:16.788873 RD_PRE = 0x0
566 11:05:16.791545 WR_PRE = 0x1
567 11:05:16.791656 WR_PST = 0x0
568 11:05:16.794942 DBI_WR = 0x0
569 11:05:16.795028 DBI_RD = 0x0
570 11:05:16.798058 OTF = 0x1
571 11:05:16.801452 ===================================
572 11:05:16.804820 ===================================
573 11:05:16.804906 ANA top config
574 11:05:16.808086 ===================================
575 11:05:16.811396 DLL_ASYNC_EN = 0
576 11:05:16.815148 ALL_SLAVE_EN = 1
577 11:05:16.817915 NEW_RANK_MODE = 1
578 11:05:16.818006 DLL_IDLE_MODE = 1
579 11:05:16.821216 LP45_APHY_COMB_EN = 1
580 11:05:16.824885 TX_ODT_DIS = 1
581 11:05:16.828168 NEW_8X_MODE = 1
582 11:05:16.831537 ===================================
583 11:05:16.834510 ===================================
584 11:05:16.837924 data_rate = 1600
585 11:05:16.838011 CKR = 1
586 11:05:16.841558 DQ_P2S_RATIO = 8
587 11:05:16.844993 ===================================
588 11:05:16.847853 CA_P2S_RATIO = 8
589 11:05:16.850940 DQ_CA_OPEN = 0
590 11:05:16.854604 DQ_SEMI_OPEN = 0
591 11:05:16.854690 CA_SEMI_OPEN = 0
592 11:05:16.857668 CA_FULL_RATE = 0
593 11:05:16.861234 DQ_CKDIV4_EN = 1
594 11:05:16.864453 CA_CKDIV4_EN = 1
595 11:05:16.867922 CA_PREDIV_EN = 0
596 11:05:16.871210 PH8_DLY = 0
597 11:05:16.871295 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 11:05:16.874571 DQ_AAMCK_DIV = 4
599 11:05:16.877804 CA_AAMCK_DIV = 4
600 11:05:16.881056 CA_ADMCK_DIV = 4
601 11:05:16.884480 DQ_TRACK_CA_EN = 0
602 11:05:16.888141 CA_PICK = 800
603 11:05:16.891146 CA_MCKIO = 800
604 11:05:16.891247 MCKIO_SEMI = 0
605 11:05:16.894854 PLL_FREQ = 3068
606 11:05:16.898460 DQ_UI_PI_RATIO = 32
607 11:05:16.902928 CA_UI_PI_RATIO = 0
608 11:05:16.906131 ===================================
609 11:05:16.906235 ===================================
610 11:05:16.909120 memory_type:LPDDR4
611 11:05:16.913118 GP_NUM : 10
612 11:05:16.913227 SRAM_EN : 1
613 11:05:16.917115 MD32_EN : 0
614 11:05:16.920861 ===================================
615 11:05:16.920984 [ANA_INIT] >>>>>>>>>>>>>>
616 11:05:16.924710 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 11:05:16.928288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 11:05:16.932040 ===================================
619 11:05:16.934655 data_rate = 1600,PCW = 0X7600
620 11:05:16.938324 ===================================
621 11:05:16.941207 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 11:05:16.948362 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 11:05:16.951049 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 11:05:16.957977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 11:05:16.961097 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 11:05:16.964402 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 11:05:16.964555 [ANA_INIT] flow start
628 11:05:16.967982 [ANA_INIT] PLL >>>>>>>>
629 11:05:16.970618 [ANA_INIT] PLL <<<<<<<<
630 11:05:16.970778 [ANA_INIT] MIDPI >>>>>>>>
631 11:05:16.974157 [ANA_INIT] MIDPI <<<<<<<<
632 11:05:16.978337 [ANA_INIT] DLL >>>>>>>>
633 11:05:16.978484 [ANA_INIT] flow end
634 11:05:16.983754 ============ LP4 DIFF to SE enter ============
635 11:05:16.987589 ============ LP4 DIFF to SE exit ============
636 11:05:16.990911 [ANA_INIT] <<<<<<<<<<<<<
637 11:05:16.993984 [Flow] Enable top DCM control >>>>>
638 11:05:16.997625 [Flow] Enable top DCM control <<<<<
639 11:05:17.000135 Enable DLL master slave shuffle
640 11:05:17.003712 ==============================================================
641 11:05:17.007302 Gating Mode config
642 11:05:17.010257 ==============================================================
643 11:05:17.014268 Config description:
644 11:05:17.023874 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 11:05:17.030258 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 11:05:17.033537 SELPH_MODE 0: By rank 1: By Phase
647 11:05:17.040068 ==============================================================
648 11:05:17.043821 GAT_TRACK_EN = 1
649 11:05:17.046553 RX_GATING_MODE = 2
650 11:05:17.049815 RX_GATING_TRACK_MODE = 2
651 11:05:17.053446 SELPH_MODE = 1
652 11:05:17.056563 PICG_EARLY_EN = 1
653 11:05:17.056695 VALID_LAT_VALUE = 1
654 11:05:17.063336 ==============================================================
655 11:05:17.066258 Enter into Gating configuration >>>>
656 11:05:17.070268 Exit from Gating configuration <<<<
657 11:05:17.073171 Enter into DVFS_PRE_config >>>>>
658 11:05:17.083196 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 11:05:17.086269 Exit from DVFS_PRE_config <<<<<
660 11:05:17.089526 Enter into PICG configuration >>>>
661 11:05:17.093263 Exit from PICG configuration <<<<
662 11:05:17.096445 [RX_INPUT] configuration >>>>>
663 11:05:17.099280 [RX_INPUT] configuration <<<<<
664 11:05:17.106048 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 11:05:17.109667 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 11:05:17.116382 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 11:05:17.123131 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 11:05:17.129632 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 11:05:17.136384 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 11:05:17.139915 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 11:05:17.142915 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 11:05:17.146166 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 11:05:17.152685 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 11:05:17.156450 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 11:05:17.159373 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 11:05:17.162786 ===================================
677 11:05:17.166091 LPDDR4 DRAM CONFIGURATION
678 11:05:17.169878 ===================================
679 11:05:17.170025 EX_ROW_EN[0] = 0x0
680 11:05:17.172778 EX_ROW_EN[1] = 0x0
681 11:05:17.176114 LP4Y_EN = 0x0
682 11:05:17.176266 WORK_FSP = 0x0
683 11:05:17.179009 WL = 0x2
684 11:05:17.179144 RL = 0x2
685 11:05:17.182595 BL = 0x2
686 11:05:17.182748 RPST = 0x0
687 11:05:17.186116 RD_PRE = 0x0
688 11:05:17.186272 WR_PRE = 0x1
689 11:05:17.189622 WR_PST = 0x0
690 11:05:17.189756 DBI_WR = 0x0
691 11:05:17.192527 DBI_RD = 0x0
692 11:05:17.192673 OTF = 0x1
693 11:05:17.196179 ===================================
694 11:05:17.199010 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 11:05:17.206344 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 11:05:17.208999 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 11:05:17.212190 ===================================
698 11:05:17.215144 LPDDR4 DRAM CONFIGURATION
699 11:05:17.218572 ===================================
700 11:05:17.218732 EX_ROW_EN[0] = 0x10
701 11:05:17.222278 EX_ROW_EN[1] = 0x0
702 11:05:17.225046 LP4Y_EN = 0x0
703 11:05:17.225185 WORK_FSP = 0x0
704 11:05:17.228488 WL = 0x2
705 11:05:17.228631 RL = 0x2
706 11:05:17.232094 BL = 0x2
707 11:05:17.232239 RPST = 0x0
708 11:05:17.235633 RD_PRE = 0x0
709 11:05:17.235814 WR_PRE = 0x1
710 11:05:17.238354 WR_PST = 0x0
711 11:05:17.238494 DBI_WR = 0x0
712 11:05:17.241743 DBI_RD = 0x0
713 11:05:17.241876 OTF = 0x1
714 11:05:17.244849 ===================================
715 11:05:17.251832 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 11:05:17.256486 nWR fixed to 40
717 11:05:17.259431 [ModeRegInit_LP4] CH0 RK0
718 11:05:17.259582 [ModeRegInit_LP4] CH0 RK1
719 11:05:17.262827 [ModeRegInit_LP4] CH1 RK0
720 11:05:17.266176 [ModeRegInit_LP4] CH1 RK1
721 11:05:17.266268 match AC timing 13
722 11:05:17.272787 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 11:05:17.276011 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 11:05:17.279744 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 11:05:17.286504 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 11:05:17.289479 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 11:05:17.292735 [EMI DOE] emi_dcm 0
728 11:05:17.296133 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 11:05:17.296257 ==
730 11:05:17.299308 Dram Type= 6, Freq= 0, CH_0, rank 0
731 11:05:17.302891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 11:05:17.302981 ==
733 11:05:17.309133 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 11:05:17.316006 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 11:05:17.323858 [CA 0] Center 37 (6~68) winsize 63
736 11:05:17.327539 [CA 1] Center 37 (7~67) winsize 61
737 11:05:17.330270 [CA 2] Center 34 (4~65) winsize 62
738 11:05:17.333326 [CA 3] Center 34 (4~65) winsize 62
739 11:05:17.337435 [CA 4] Center 33 (3~64) winsize 62
740 11:05:17.340674 [CA 5] Center 33 (3~64) winsize 62
741 11:05:17.340766
742 11:05:17.343421 [CmdBusTrainingLP45] Vref(ca) range 1: 30
743 11:05:17.343508
744 11:05:17.347243 [CATrainingPosCal] consider 1 rank data
745 11:05:17.350893 u2DelayCellTimex100 = 270/100 ps
746 11:05:17.353399 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
747 11:05:17.359865 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
748 11:05:17.363343 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
749 11:05:17.366927 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
750 11:05:17.369864 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
751 11:05:17.373256 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
752 11:05:17.373345
753 11:05:17.377080 CA PerBit enable=1, Macro0, CA PI delay=33
754 11:05:17.377169
755 11:05:17.380078 [CBTSetCACLKResult] CA Dly = 33
756 11:05:17.380163 CS Dly: 6 (0~37)
757 11:05:17.383278 ==
758 11:05:17.387332 Dram Type= 6, Freq= 0, CH_0, rank 1
759 11:05:17.389683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 11:05:17.389770 ==
761 11:05:17.393186 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 11:05:17.399614 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 11:05:17.410429 [CA 0] Center 37 (6~68) winsize 63
764 11:05:17.413383 [CA 1] Center 37 (7~68) winsize 62
765 11:05:17.416184 [CA 2] Center 34 (4~65) winsize 62
766 11:05:17.419700 [CA 3] Center 34 (4~65) winsize 62
767 11:05:17.423896 [CA 4] Center 33 (3~64) winsize 62
768 11:05:17.426207 [CA 5] Center 33 (3~64) winsize 62
769 11:05:17.426324
770 11:05:17.430012 [CmdBusTrainingLP45] Vref(ca) range 1: 32
771 11:05:17.430131
772 11:05:17.433625 [CATrainingPosCal] consider 2 rank data
773 11:05:17.436744 u2DelayCellTimex100 = 270/100 ps
774 11:05:17.439567 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
775 11:05:17.446136 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
776 11:05:17.449666 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
777 11:05:17.453022 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
778 11:05:17.456556 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
779 11:05:17.459682 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
780 11:05:17.459835
781 11:05:17.463166 CA PerBit enable=1, Macro0, CA PI delay=33
782 11:05:17.463272
783 11:05:17.466342 [CBTSetCACLKResult] CA Dly = 33
784 11:05:17.469242 CS Dly: 6 (0~38)
785 11:05:17.469417
786 11:05:17.472894 ----->DramcWriteLeveling(PI) begin...
787 11:05:17.472982 ==
788 11:05:17.476578 Dram Type= 6, Freq= 0, CH_0, rank 0
789 11:05:17.479841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 11:05:17.479933 ==
791 11:05:17.483599 Write leveling (Byte 0): 34 => 34
792 11:05:17.483746 Write leveling (Byte 1): 29 => 29
793 11:05:17.487575 DramcWriteLeveling(PI) end<-----
794 11:05:17.487713
795 11:05:17.487830 ==
796 11:05:17.491466 Dram Type= 6, Freq= 0, CH_0, rank 0
797 11:05:17.494697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 11:05:17.497849 ==
799 11:05:17.497936 [Gating] SW mode calibration
800 11:05:17.505137 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 11:05:17.511607 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 11:05:17.515090 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 11:05:17.521875 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
804 11:05:17.525170 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
805 11:05:17.528284 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:05:17.535122 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:05:17.538673 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:05:17.541754 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:05:17.547923 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:05:17.551994 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:05:17.554736 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:05:17.557679 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 11:05:17.564927 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 11:05:17.568043 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 11:05:17.574202 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 11:05:17.577451 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 11:05:17.581161 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 11:05:17.587598 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 11:05:17.591293 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
820 11:05:17.594213 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
821 11:05:17.600990 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 11:05:17.604263 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:05:17.607772 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:05:17.610643 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:05:17.617649 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:05:17.620805 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:05:17.624186 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:05:17.630607 0 9 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
829 11:05:17.633825 0 9 12 | B1->B0 | 2a2a 3434 | 0 1 | (1 1) (1 1)
830 11:05:17.637639 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 11:05:17.643886 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 11:05:17.647439 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 11:05:17.650526 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 11:05:17.656947 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 11:05:17.660480 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
836 11:05:17.663793 0 10 8 | B1->B0 | 3333 2a2a | 0 1 | (0 1) (1 0)
837 11:05:17.670468 0 10 12 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
838 11:05:17.673896 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 11:05:17.677438 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 11:05:17.684133 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 11:05:17.687008 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 11:05:17.690657 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 11:05:17.697043 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 11:05:17.700300 0 11 8 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
845 11:05:17.703618 0 11 12 | B1->B0 | 3c3c 4646 | 1 0 | (1 1) (0 0)
846 11:05:17.710586 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 11:05:17.713814 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 11:05:17.716907 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 11:05:17.723907 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 11:05:17.727511 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 11:05:17.731102 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 11:05:17.734218 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
853 11:05:17.740773 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 11:05:17.744126 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 11:05:17.747045 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 11:05:17.753909 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 11:05:17.756854 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 11:05:17.760382 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 11:05:17.766590 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 11:05:17.770767 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 11:05:17.773218 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 11:05:17.779941 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 11:05:17.783917 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 11:05:17.786543 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 11:05:17.793740 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 11:05:17.796466 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 11:05:17.800216 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
868 11:05:17.806174 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
869 11:05:17.809520 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 11:05:17.813062 Total UI for P1: 0, mck2ui 16
871 11:05:17.816007 best dqsien dly found for B0: ( 0, 14, 8)
872 11:05:17.819391 Total UI for P1: 0, mck2ui 16
873 11:05:17.822864 best dqsien dly found for B1: ( 0, 14, 10)
874 11:05:17.826434 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
875 11:05:17.830816 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
876 11:05:17.830909
877 11:05:17.832749 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
878 11:05:17.839606 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
879 11:05:17.839745 [Gating] SW calibration Done
880 11:05:17.839858 ==
881 11:05:17.842406 Dram Type= 6, Freq= 0, CH_0, rank 0
882 11:05:17.849027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
883 11:05:17.849120 ==
884 11:05:17.849188 RX Vref Scan: 0
885 11:05:17.849249
886 11:05:17.852391 RX Vref 0 -> 0, step: 1
887 11:05:17.852477
888 11:05:17.855603 RX Delay -130 -> 252, step: 16
889 11:05:17.859503 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
890 11:05:17.862409 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
891 11:05:17.865692 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
892 11:05:17.871866 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
893 11:05:17.875116 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
894 11:05:17.878718 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
895 11:05:17.881649 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
896 11:05:17.885248 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
897 11:05:17.891916 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
898 11:05:17.895185 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
899 11:05:17.898094 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
900 11:05:17.901615 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
901 11:05:17.908271 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
902 11:05:17.911860 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
903 11:05:17.914834 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
904 11:05:17.918233 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
905 11:05:17.918323 ==
906 11:05:17.921804 Dram Type= 6, Freq= 0, CH_0, rank 0
907 11:05:17.928139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 11:05:17.928227 ==
909 11:05:17.928295 DQS Delay:
910 11:05:17.928357 DQS0 = 0, DQS1 = 0
911 11:05:17.931268 DQM Delay:
912 11:05:17.931352 DQM0 = 85, DQM1 = 74
913 11:05:17.934572 DQ Delay:
914 11:05:17.938394 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
915 11:05:17.942311 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
916 11:05:17.944659 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
917 11:05:17.948423 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
918 11:05:17.948508
919 11:05:17.948575
920 11:05:17.948636 ==
921 11:05:17.951639 Dram Type= 6, Freq= 0, CH_0, rank 0
922 11:05:17.954958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 11:05:17.955070 ==
924 11:05:17.955156
925 11:05:17.955238
926 11:05:17.958757 TX Vref Scan disable
927 11:05:17.958843 == TX Byte 0 ==
928 11:05:17.965333 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
929 11:05:17.969170 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
930 11:05:17.969283 == TX Byte 1 ==
931 11:05:17.974634 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
932 11:05:17.978302 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
933 11:05:17.978389 ==
934 11:05:17.981377 Dram Type= 6, Freq= 0, CH_0, rank 0
935 11:05:17.984541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 11:05:17.984652 ==
937 11:05:17.998814 TX Vref=22, minBit 2, minWin=27, winSum=441
938 11:05:18.002661 TX Vref=24, minBit 5, minWin=27, winSum=443
939 11:05:18.007408 TX Vref=26, minBit 3, minWin=27, winSum=443
940 11:05:18.009464 TX Vref=28, minBit 8, minWin=27, winSum=447
941 11:05:18.012191 TX Vref=30, minBit 9, minWin=27, winSum=448
942 11:05:18.018657 TX Vref=32, minBit 7, minWin=27, winSum=444
943 11:05:18.021936 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 30
944 11:05:18.022028
945 11:05:18.025439 Final TX Range 1 Vref 30
946 11:05:18.025526
947 11:05:18.025612 ==
948 11:05:18.028676 Dram Type= 6, Freq= 0, CH_0, rank 0
949 11:05:18.032166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 11:05:18.036051 ==
951 11:05:18.036150
952 11:05:18.036246
953 11:05:18.036329 TX Vref Scan disable
954 11:05:18.039107 == TX Byte 0 ==
955 11:05:18.042568 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
956 11:05:18.049017 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
957 11:05:18.049110 == TX Byte 1 ==
958 11:05:18.053044 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
959 11:05:18.058778 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
960 11:05:18.058868
961 11:05:18.058954 [DATLAT]
962 11:05:18.059036 Freq=800, CH0 RK0
963 11:05:18.059117
964 11:05:18.062187 DATLAT Default: 0xa
965 11:05:18.062266 0, 0xFFFF, sum = 0
966 11:05:18.065304 1, 0xFFFF, sum = 0
967 11:05:18.069043 2, 0xFFFF, sum = 0
968 11:05:18.069132 3, 0xFFFF, sum = 0
969 11:05:18.072518 4, 0xFFFF, sum = 0
970 11:05:18.072606 5, 0xFFFF, sum = 0
971 11:05:18.075993 6, 0xFFFF, sum = 0
972 11:05:18.076082 7, 0xFFFF, sum = 0
973 11:05:18.078740 8, 0xFFFF, sum = 0
974 11:05:18.078827 9, 0x0, sum = 1
975 11:05:18.081856 10, 0x0, sum = 2
976 11:05:18.081944 11, 0x0, sum = 3
977 11:05:18.082032 12, 0x0, sum = 4
978 11:05:18.086122 best_step = 10
979 11:05:18.086210
980 11:05:18.086299 ==
981 11:05:18.088484 Dram Type= 6, Freq= 0, CH_0, rank 0
982 11:05:18.092572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 11:05:18.092660 ==
984 11:05:18.095421 RX Vref Scan: 1
985 11:05:18.095531
986 11:05:18.098636 Set Vref Range= 32 -> 127
987 11:05:18.098734
988 11:05:18.098855 RX Vref 32 -> 127, step: 1
989 11:05:18.098955
990 11:05:18.101886 RX Delay -111 -> 252, step: 8
991 11:05:18.101972
992 11:05:18.105181 Set Vref, RX VrefLevel [Byte0]: 32
993 11:05:18.108321 [Byte1]: 32
994 11:05:18.111915
995 11:05:18.112003 Set Vref, RX VrefLevel [Byte0]: 33
996 11:05:18.115780 [Byte1]: 33
997 11:05:18.120331
998 11:05:18.120437 Set Vref, RX VrefLevel [Byte0]: 34
999 11:05:18.122963 [Byte1]: 34
1000 11:05:18.127328
1001 11:05:18.127439 Set Vref, RX VrefLevel [Byte0]: 35
1002 11:05:18.130772 [Byte1]: 35
1003 11:05:18.134915
1004 11:05:18.135003 Set Vref, RX VrefLevel [Byte0]: 36
1005 11:05:18.138169 [Byte1]: 36
1006 11:05:18.142723
1007 11:05:18.142809 Set Vref, RX VrefLevel [Byte0]: 37
1008 11:05:18.145971 [Byte1]: 37
1009 11:05:18.150292
1010 11:05:18.150379 Set Vref, RX VrefLevel [Byte0]: 38
1011 11:05:18.154095 [Byte1]: 38
1012 11:05:18.158053
1013 11:05:18.158138 Set Vref, RX VrefLevel [Byte0]: 39
1014 11:05:18.161569 [Byte1]: 39
1015 11:05:18.166053
1016 11:05:18.166181 Set Vref, RX VrefLevel [Byte0]: 40
1017 11:05:18.169301 [Byte1]: 40
1018 11:05:18.173909
1019 11:05:18.173997 Set Vref, RX VrefLevel [Byte0]: 41
1020 11:05:18.177194 [Byte1]: 41
1021 11:05:18.180598
1022 11:05:18.180683 Set Vref, RX VrefLevel [Byte0]: 42
1023 11:05:18.184063 [Byte1]: 42
1024 11:05:18.188946
1025 11:05:18.189034 Set Vref, RX VrefLevel [Byte0]: 43
1026 11:05:18.191866 [Byte1]: 43
1027 11:05:18.196302
1028 11:05:18.196390 Set Vref, RX VrefLevel [Byte0]: 44
1029 11:05:18.199122 [Byte1]: 44
1030 11:05:18.203604
1031 11:05:18.203740 Set Vref, RX VrefLevel [Byte0]: 45
1032 11:05:18.206795 [Byte1]: 45
1033 11:05:18.211173
1034 11:05:18.211316 Set Vref, RX VrefLevel [Byte0]: 46
1035 11:05:18.215292 [Byte1]: 46
1036 11:05:18.218951
1037 11:05:18.219039 Set Vref, RX VrefLevel [Byte0]: 47
1038 11:05:18.222767 [Byte1]: 47
1039 11:05:18.227086
1040 11:05:18.227171 Set Vref, RX VrefLevel [Byte0]: 48
1041 11:05:18.230039 [Byte1]: 48
1042 11:05:18.234502
1043 11:05:18.234587 Set Vref, RX VrefLevel [Byte0]: 49
1044 11:05:18.238166 [Byte1]: 49
1045 11:05:18.241677
1046 11:05:18.241761 Set Vref, RX VrefLevel [Byte0]: 50
1047 11:05:18.245392 [Byte1]: 50
1048 11:05:18.250224
1049 11:05:18.250306 Set Vref, RX VrefLevel [Byte0]: 51
1050 11:05:18.253295 [Byte1]: 51
1051 11:05:18.257134
1052 11:05:18.257216 Set Vref, RX VrefLevel [Byte0]: 52
1053 11:05:18.260391 [Byte1]: 52
1054 11:05:18.265103
1055 11:05:18.265185 Set Vref, RX VrefLevel [Byte0]: 53
1056 11:05:18.268254 [Byte1]: 53
1057 11:05:18.272418
1058 11:05:18.272504 Set Vref, RX VrefLevel [Byte0]: 54
1059 11:05:18.275843 [Byte1]: 54
1060 11:05:18.279935
1061 11:05:18.280034 Set Vref, RX VrefLevel [Byte0]: 55
1062 11:05:18.283884 [Byte1]: 55
1063 11:05:18.287667
1064 11:05:18.287771 Set Vref, RX VrefLevel [Byte0]: 56
1065 11:05:18.291034 [Byte1]: 56
1066 11:05:18.295408
1067 11:05:18.295491 Set Vref, RX VrefLevel [Byte0]: 57
1068 11:05:18.298574 [Byte1]: 57
1069 11:05:18.303317
1070 11:05:18.303399 Set Vref, RX VrefLevel [Byte0]: 58
1071 11:05:18.306789 [Byte1]: 58
1072 11:05:18.311413
1073 11:05:18.311494 Set Vref, RX VrefLevel [Byte0]: 59
1074 11:05:18.314238 [Byte1]: 59
1075 11:05:18.317999
1076 11:05:18.318180 Set Vref, RX VrefLevel [Byte0]: 60
1077 11:05:18.321871 [Byte1]: 60
1078 11:05:18.326120
1079 11:05:18.326278 Set Vref, RX VrefLevel [Byte0]: 61
1080 11:05:18.329252 [Byte1]: 61
1081 11:05:18.333686
1082 11:05:18.333839 Set Vref, RX VrefLevel [Byte0]: 62
1083 11:05:18.337172 [Byte1]: 62
1084 11:05:18.341132
1085 11:05:18.341289 Set Vref, RX VrefLevel [Byte0]: 63
1086 11:05:18.344552 [Byte1]: 63
1087 11:05:18.349069
1088 11:05:18.349231 Set Vref, RX VrefLevel [Byte0]: 64
1089 11:05:18.352657 [Byte1]: 64
1090 11:05:18.356939
1091 11:05:18.357090 Set Vref, RX VrefLevel [Byte0]: 65
1092 11:05:18.359607 [Byte1]: 65
1093 11:05:18.363893
1094 11:05:18.364047 Set Vref, RX VrefLevel [Byte0]: 66
1095 11:05:18.367644 [Byte1]: 66
1096 11:05:18.371730
1097 11:05:18.371887 Set Vref, RX VrefLevel [Byte0]: 67
1098 11:05:18.375229 [Byte1]: 67
1099 11:05:18.379603
1100 11:05:18.379793 Set Vref, RX VrefLevel [Byte0]: 68
1101 11:05:18.382629 [Byte1]: 68
1102 11:05:18.386769
1103 11:05:18.386917 Set Vref, RX VrefLevel [Byte0]: 69
1104 11:05:18.390689 [Byte1]: 69
1105 11:05:18.394463
1106 11:05:18.394616 Set Vref, RX VrefLevel [Byte0]: 70
1107 11:05:18.398119 [Byte1]: 70
1108 11:05:18.402679
1109 11:05:18.402834 Set Vref, RX VrefLevel [Byte0]: 71
1110 11:05:18.405425 [Byte1]: 71
1111 11:05:18.410394
1112 11:05:18.410546 Set Vref, RX VrefLevel [Byte0]: 72
1113 11:05:18.413155 [Byte1]: 72
1114 11:05:18.418065
1115 11:05:18.418238 Set Vref, RX VrefLevel [Byte0]: 73
1116 11:05:18.421276 [Byte1]: 73
1117 11:05:18.425222
1118 11:05:18.425369 Set Vref, RX VrefLevel [Byte0]: 74
1119 11:05:18.428294 [Byte1]: 74
1120 11:05:18.433263
1121 11:05:18.433413 Set Vref, RX VrefLevel [Byte0]: 75
1122 11:05:18.436280 [Byte1]: 75
1123 11:05:18.441177
1124 11:05:18.441331 Set Vref, RX VrefLevel [Byte0]: 76
1125 11:05:18.443570 [Byte1]: 76
1126 11:05:18.448187
1127 11:05:18.448339 Set Vref, RX VrefLevel [Byte0]: 77
1128 11:05:18.451761 [Byte1]: 77
1129 11:05:18.455970
1130 11:05:18.456260 Set Vref, RX VrefLevel [Byte0]: 78
1131 11:05:18.458947 [Byte1]: 78
1132 11:05:18.463808
1133 11:05:18.464034 Set Vref, RX VrefLevel [Byte0]: 79
1134 11:05:18.466797 [Byte1]: 79
1135 11:05:18.471100
1136 11:05:18.471316 Set Vref, RX VrefLevel [Byte0]: 80
1137 11:05:18.474486 [Byte1]: 80
1138 11:05:18.479280
1139 11:05:18.479469 Set Vref, RX VrefLevel [Byte0]: 81
1140 11:05:18.482632 [Byte1]: 81
1141 11:05:18.486449
1142 11:05:18.486603 Final RX Vref Byte 0 = 67 to rank0
1143 11:05:18.489821 Final RX Vref Byte 1 = 55 to rank0
1144 11:05:18.493157 Final RX Vref Byte 0 = 67 to rank1
1145 11:05:18.496349 Final RX Vref Byte 1 = 55 to rank1==
1146 11:05:18.499667 Dram Type= 6, Freq= 0, CH_0, rank 0
1147 11:05:18.506423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 11:05:18.506564 ==
1149 11:05:18.506661 DQS Delay:
1150 11:05:18.506750 DQS0 = 0, DQS1 = 0
1151 11:05:18.509857 DQM Delay:
1152 11:05:18.509964 DQM0 = 88, DQM1 = 76
1153 11:05:18.512884 DQ Delay:
1154 11:05:18.516582 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1155 11:05:18.519577 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1156 11:05:18.522992 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1157 11:05:18.526578 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1158 11:05:18.526678
1159 11:05:18.526759
1160 11:05:18.534066 [DQSOSCAuto] RK0, (LSB)MR18= 0x4223, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1161 11:05:18.536546 CH0 RK0: MR19=606, MR18=4223
1162 11:05:18.584017 CH0_RK0: MR19=0x606, MR18=0x4223, DQSOSC=393, MR23=63, INC=95, DEC=63
1163 11:05:18.584216
1164 11:05:18.584299 ----->DramcWriteLeveling(PI) begin...
1165 11:05:18.584377 ==
1166 11:05:18.584629 Dram Type= 6, Freq= 0, CH_0, rank 1
1167 11:05:18.584701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1168 11:05:18.584762 ==
1169 11:05:18.584819 Write leveling (Byte 0): 29 => 29
1170 11:05:18.584955 Write leveling (Byte 1): 29 => 29
1171 11:05:18.585030 DramcWriteLeveling(PI) end<-----
1172 11:05:18.585086
1173 11:05:18.585160 ==
1174 11:05:18.585257 Dram Type= 6, Freq= 0, CH_0, rank 1
1175 11:05:18.585651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1176 11:05:18.585735 ==
1177 11:05:18.585801 [Gating] SW mode calibration
1178 11:05:18.586667 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1179 11:05:18.612582 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1180 11:05:18.612715 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1181 11:05:18.613011 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1182 11:05:18.613081 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1183 11:05:18.613821 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 11:05:18.614545 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 11:05:18.614668 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 11:05:18.617119 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 11:05:18.620054 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 11:05:18.626551 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 11:05:18.629756 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 11:05:18.633466 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:05:18.639927 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:05:18.642964 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 11:05:18.646570 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 11:05:18.652574 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 11:05:18.657183 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 11:05:18.660215 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 11:05:18.666047 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1198 11:05:18.669452 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1199 11:05:18.673108 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 11:05:18.680130 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 11:05:18.682765 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 11:05:18.686029 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 11:05:18.692316 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 11:05:18.695406 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 11:05:18.699069 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 11:05:18.705764 0 9 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1207 11:05:18.708800 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1208 11:05:18.712356 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1209 11:05:18.719595 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1210 11:05:18.722652 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1211 11:05:18.725763 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1212 11:05:18.729674 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1213 11:05:18.736965 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1214 11:05:18.740650 0 10 8 | B1->B0 | 3030 2929 | 0 0 | (0 1) (1 1)
1215 11:05:18.743599 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1216 11:05:18.747085 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 11:05:18.754599 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 11:05:18.758028 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 11:05:18.760929 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:05:18.764384 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:05:18.770757 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1222 11:05:18.774205 0 11 8 | B1->B0 | 2626 3939 | 0 1 | (0 0) (1 1)
1223 11:05:18.777584 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1224 11:05:18.784741 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 11:05:18.787879 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 11:05:18.791128 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1227 11:05:18.797540 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1228 11:05:18.800988 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1229 11:05:18.803921 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1230 11:05:18.810603 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1231 11:05:18.814436 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 11:05:18.820632 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 11:05:18.824515 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 11:05:18.827388 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 11:05:18.831146 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 11:05:18.837330 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 11:05:18.840732 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 11:05:18.843840 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 11:05:18.850830 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 11:05:18.853876 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 11:05:18.857096 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 11:05:18.863620 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 11:05:18.867183 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 11:05:18.870484 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 11:05:18.877239 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 11:05:18.880583 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1247 11:05:18.883903 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1248 11:05:18.887278 Total UI for P1: 0, mck2ui 16
1249 11:05:18.890792 best dqsien dly found for B0: ( 0, 14, 8)
1250 11:05:18.893609 Total UI for P1: 0, mck2ui 16
1251 11:05:18.896953 best dqsien dly found for B1: ( 0, 14, 8)
1252 11:05:18.900899 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1253 11:05:18.904110 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1254 11:05:18.904192
1255 11:05:18.907163 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1256 11:05:18.910470 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1257 11:05:18.913575 [Gating] SW calibration Done
1258 11:05:18.913657 ==
1259 11:05:18.916529 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 11:05:18.923507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 11:05:18.923618 ==
1262 11:05:18.923742 RX Vref Scan: 0
1263 11:05:18.923804
1264 11:05:18.926848 RX Vref 0 -> 0, step: 1
1265 11:05:18.926931
1266 11:05:18.929971 RX Delay -130 -> 252, step: 16
1267 11:05:18.933877 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1268 11:05:18.937039 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1269 11:05:18.939901 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1270 11:05:18.946528 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1271 11:05:18.950273 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1272 11:05:18.953603 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1273 11:05:18.956443 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1274 11:05:18.960241 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1275 11:05:18.966342 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1276 11:05:18.969910 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1277 11:05:18.973438 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1278 11:05:18.976749 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1279 11:05:18.980159 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1280 11:05:18.986508 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1281 11:05:18.989500 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1282 11:05:18.992854 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1283 11:05:18.992935 ==
1284 11:05:18.996710 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 11:05:18.999516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 11:05:19.002902 ==
1287 11:05:19.002983 DQS Delay:
1288 11:05:19.003048 DQS0 = 0, DQS1 = 0
1289 11:05:19.006102 DQM Delay:
1290 11:05:19.006183 DQM0 = 84, DQM1 = 77
1291 11:05:19.006247 DQ Delay:
1292 11:05:19.009874 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1293 11:05:19.012979 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1294 11:05:19.016321 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1295 11:05:19.019310 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1296 11:05:19.019438
1297 11:05:19.019531
1298 11:05:19.023259 ==
1299 11:05:19.026327 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 11:05:19.029298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 11:05:19.029380 ==
1302 11:05:19.029445
1303 11:05:19.029504
1304 11:05:19.033647 TX Vref Scan disable
1305 11:05:19.033728 == TX Byte 0 ==
1306 11:05:19.039805 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1307 11:05:19.042672 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1308 11:05:19.042754 == TX Byte 1 ==
1309 11:05:19.049023 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1310 11:05:19.052640 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1311 11:05:19.052722 ==
1312 11:05:19.056022 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 11:05:19.059195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 11:05:19.059277 ==
1315 11:05:19.072689 TX Vref=22, minBit 1, minWin=27, winSum=441
1316 11:05:19.075550 TX Vref=24, minBit 8, minWin=27, winSum=447
1317 11:05:19.079325 TX Vref=26, minBit 9, minWin=27, winSum=446
1318 11:05:19.082757 TX Vref=28, minBit 9, minWin=27, winSum=449
1319 11:05:19.085924 TX Vref=30, minBit 9, minWin=27, winSum=450
1320 11:05:19.092492 TX Vref=32, minBit 9, minWin=27, winSum=447
1321 11:05:19.095758 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 30
1322 11:05:19.095839
1323 11:05:19.098855 Final TX Range 1 Vref 30
1324 11:05:19.098935
1325 11:05:19.098998 ==
1326 11:05:19.102262 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 11:05:19.105789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 11:05:19.108542 ==
1329 11:05:19.108622
1330 11:05:19.108685
1331 11:05:19.108744 TX Vref Scan disable
1332 11:05:19.112840 == TX Byte 0 ==
1333 11:05:19.116391 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1334 11:05:19.119277 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1335 11:05:19.123086 == TX Byte 1 ==
1336 11:05:19.125781 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1337 11:05:19.132704 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1338 11:05:19.132785
1339 11:05:19.132848 [DATLAT]
1340 11:05:19.132907 Freq=800, CH0 RK1
1341 11:05:19.132965
1342 11:05:19.135477 DATLAT Default: 0xa
1343 11:05:19.135583 0, 0xFFFF, sum = 0
1344 11:05:19.138756 1, 0xFFFF, sum = 0
1345 11:05:19.138838 2, 0xFFFF, sum = 0
1346 11:05:19.142547 3, 0xFFFF, sum = 0
1347 11:05:19.145374 4, 0xFFFF, sum = 0
1348 11:05:19.145455 5, 0xFFFF, sum = 0
1349 11:05:19.149099 6, 0xFFFF, sum = 0
1350 11:05:19.149180 7, 0xFFFF, sum = 0
1351 11:05:19.152266 8, 0xFFFF, sum = 0
1352 11:05:19.152347 9, 0x0, sum = 1
1353 11:05:19.155357 10, 0x0, sum = 2
1354 11:05:19.155437 11, 0x0, sum = 3
1355 11:05:19.155502 12, 0x0, sum = 4
1356 11:05:19.158415 best_step = 10
1357 11:05:19.158495
1358 11:05:19.158563 ==
1359 11:05:19.161811 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 11:05:19.165546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 11:05:19.165627 ==
1362 11:05:19.168701 RX Vref Scan: 0
1363 11:05:19.168783
1364 11:05:19.168846 RX Vref 0 -> 0, step: 1
1365 11:05:19.172357
1366 11:05:19.172437 RX Delay -111 -> 252, step: 8
1367 11:05:19.179486 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1368 11:05:19.182882 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1369 11:05:19.185799 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1370 11:05:19.188867 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1371 11:05:19.192752 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1372 11:05:19.198813 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1373 11:05:19.202217 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1374 11:05:19.206163 iDelay=217, Bit 7, Center 100 (-15 ~ 216) 232
1375 11:05:19.208932 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1376 11:05:19.212762 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1377 11:05:19.219376 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
1378 11:05:19.222029 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1379 11:05:19.226009 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1380 11:05:19.228956 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1381 11:05:19.235280 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1382 11:05:19.239193 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1383 11:05:19.239274 ==
1384 11:05:19.241910 Dram Type= 6, Freq= 0, CH_0, rank 1
1385 11:05:19.245424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 11:05:19.245505 ==
1387 11:05:19.248793 DQS Delay:
1388 11:05:19.248874 DQS0 = 0, DQS1 = 0
1389 11:05:19.248938 DQM Delay:
1390 11:05:19.251920 DQM0 = 87, DQM1 = 77
1391 11:05:19.252001 DQ Delay:
1392 11:05:19.255203 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =84
1393 11:05:19.259065 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =100
1394 11:05:19.261727 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1395 11:05:19.265014 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1396 11:05:19.265095
1397 11:05:19.265158
1398 11:05:19.275462 [DQSOSCAuto] RK1, (LSB)MR18= 0x3900, (MSB)MR19= 0x606, tDQSOscB0 = 410 ps tDQSOscB1 = 395 ps
1399 11:05:19.278527 CH0 RK1: MR19=606, MR18=3900
1400 11:05:19.281461 CH0_RK1: MR19=0x606, MR18=0x3900, DQSOSC=395, MR23=63, INC=94, DEC=63
1401 11:05:19.285234 [RxdqsGatingPostProcess] freq 800
1402 11:05:19.291658 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1403 11:05:19.295562 Pre-setting of DQS Precalculation
1404 11:05:19.297947 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1405 11:05:19.301553 ==
1406 11:05:19.301659 Dram Type= 6, Freq= 0, CH_1, rank 0
1407 11:05:19.307881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 11:05:19.307987 ==
1409 11:05:19.311323 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 11:05:19.318224 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 11:05:19.327810 [CA 0] Center 36 (6~67) winsize 62
1412 11:05:19.331613 [CA 1] Center 36 (6~67) winsize 62
1413 11:05:19.334935 [CA 2] Center 34 (4~65) winsize 62
1414 11:05:19.338077 [CA 3] Center 34 (3~65) winsize 63
1415 11:05:19.341307 [CA 4] Center 34 (4~65) winsize 62
1416 11:05:19.343907 [CA 5] Center 34 (4~65) winsize 62
1417 11:05:19.344010
1418 11:05:19.347374 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 11:05:19.347501
1420 11:05:19.350801 [CATrainingPosCal] consider 1 rank data
1421 11:05:19.353858 u2DelayCellTimex100 = 270/100 ps
1422 11:05:19.357824 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 11:05:19.364443 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 11:05:19.367564 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1425 11:05:19.370732 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1426 11:05:19.374498 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 11:05:19.377531 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 11:05:19.377635
1429 11:05:19.380482 CA PerBit enable=1, Macro0, CA PI delay=34
1430 11:05:19.380588
1431 11:05:19.383890 [CBTSetCACLKResult] CA Dly = 34
1432 11:05:19.387612 CS Dly: 5 (0~36)
1433 11:05:19.387724 ==
1434 11:05:19.390908 Dram Type= 6, Freq= 0, CH_1, rank 1
1435 11:05:19.394250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 11:05:19.394333 ==
1437 11:05:19.397508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1438 11:05:19.404674 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1439 11:05:19.414116 [CA 0] Center 36 (6~67) winsize 62
1440 11:05:19.418002 [CA 1] Center 37 (6~68) winsize 63
1441 11:05:19.421358 [CA 2] Center 34 (4~65) winsize 62
1442 11:05:19.425359 [CA 3] Center 34 (3~65) winsize 63
1443 11:05:19.428862 [CA 4] Center 34 (4~65) winsize 62
1444 11:05:19.432252 [CA 5] Center 34 (4~65) winsize 62
1445 11:05:19.432334
1446 11:05:19.435581 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1447 11:05:19.435661
1448 11:05:19.438600 [CATrainingPosCal] consider 2 rank data
1449 11:05:19.442636 u2DelayCellTimex100 = 270/100 ps
1450 11:05:19.445267 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1451 11:05:19.448569 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1452 11:05:19.452017 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1453 11:05:19.454950 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1454 11:05:19.458431 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1455 11:05:19.461786 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1456 11:05:19.461867
1457 11:05:19.468390 CA PerBit enable=1, Macro0, CA PI delay=34
1458 11:05:19.468472
1459 11:05:19.471836 [CBTSetCACLKResult] CA Dly = 34
1460 11:05:19.471917 CS Dly: 5 (0~37)
1461 11:05:19.471982
1462 11:05:19.475384 ----->DramcWriteLeveling(PI) begin...
1463 11:05:19.475466 ==
1464 11:05:19.478292 Dram Type= 6, Freq= 0, CH_1, rank 0
1465 11:05:19.481781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1466 11:05:19.485039 ==
1467 11:05:19.485120 Write leveling (Byte 0): 26 => 26
1468 11:05:19.488555 Write leveling (Byte 1): 27 => 27
1469 11:05:19.491995 DramcWriteLeveling(PI) end<-----
1470 11:05:19.492076
1471 11:05:19.492141 ==
1472 11:05:19.495448 Dram Type= 6, Freq= 0, CH_1, rank 0
1473 11:05:19.501892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1474 11:05:19.501974 ==
1475 11:05:19.502037 [Gating] SW mode calibration
1476 11:05:19.511956 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1477 11:05:19.515310 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1478 11:05:19.518435 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1479 11:05:19.524884 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1480 11:05:19.528279 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 11:05:19.531151 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 11:05:19.537760 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 11:05:19.541288 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 11:05:19.544749 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 11:05:19.551441 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 11:05:19.554798 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 11:05:19.557641 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 11:05:19.564594 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 11:05:19.568107 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 11:05:19.570690 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 11:05:19.577385 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 11:05:19.580857 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 11:05:19.584826 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 11:05:19.591077 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1495 11:05:19.594128 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1496 11:05:19.597548 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1497 11:05:19.604182 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 11:05:19.607160 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 11:05:19.610906 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 11:05:19.617238 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 11:05:19.620417 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 11:05:19.623941 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 11:05:19.630476 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 11:05:19.633550 0 9 8 | B1->B0 | 2c2c 3231 | 0 1 | (1 1) (0 0)
1505 11:05:19.637119 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1506 11:05:19.643642 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1507 11:05:19.647011 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1508 11:05:19.650211 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1509 11:05:19.657264 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1510 11:05:19.660526 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1511 11:05:19.663802 0 10 4 | B1->B0 | 3333 3333 | 1 1 | (1 0) (1 0)
1512 11:05:19.670433 0 10 8 | B1->B0 | 2e2e 2b2b | 0 0 | (0 0) (0 0)
1513 11:05:19.674028 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 11:05:19.677131 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 11:05:19.683920 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 11:05:19.686747 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 11:05:19.689919 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:05:19.697115 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:05:19.700344 0 11 4 | B1->B0 | 2727 2626 | 0 0 | (1 1) (1 1)
1520 11:05:19.703358 0 11 8 | B1->B0 | 3838 3f3f | 0 1 | (0 0) (0 0)
1521 11:05:19.709895 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 11:05:19.713480 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 11:05:19.716642 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1524 11:05:19.723409 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1525 11:05:19.726449 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 11:05:19.729918 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1527 11:05:19.736645 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 11:05:19.740376 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 11:05:19.742898 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 11:05:19.750389 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 11:05:19.753170 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 11:05:19.756199 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 11:05:19.762938 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 11:05:19.766059 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 11:05:19.769586 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 11:05:19.776392 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 11:05:19.779515 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 11:05:19.782794 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 11:05:19.786224 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 11:05:19.792907 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 11:05:19.796374 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 11:05:19.799283 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 11:05:19.805868 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1544 11:05:19.809001 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1545 11:05:19.812332 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1546 11:05:19.815890 Total UI for P1: 0, mck2ui 16
1547 11:05:19.819106 best dqsien dly found for B0: ( 0, 14, 6)
1548 11:05:19.822928 Total UI for P1: 0, mck2ui 16
1549 11:05:19.825624 best dqsien dly found for B1: ( 0, 14, 8)
1550 11:05:19.829343 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1551 11:05:19.832473 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1552 11:05:19.835747
1553 11:05:19.839116 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1554 11:05:19.842459 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1555 11:05:19.845635 [Gating] SW calibration Done
1556 11:05:19.845717 ==
1557 11:05:19.849078 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 11:05:19.852415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 11:05:19.852499 ==
1560 11:05:19.852565 RX Vref Scan: 0
1561 11:05:19.852625
1562 11:05:19.855627 RX Vref 0 -> 0, step: 1
1563 11:05:19.855762
1564 11:05:19.859023 RX Delay -130 -> 252, step: 16
1565 11:05:19.863016 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1566 11:05:19.865702 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1567 11:05:19.871945 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1568 11:05:19.875730 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1569 11:05:19.878605 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1570 11:05:19.881932 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1571 11:05:19.885271 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1572 11:05:19.892004 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1573 11:05:19.895024 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1574 11:05:19.898881 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1575 11:05:19.901817 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1576 11:05:19.908310 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1577 11:05:19.912140 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1578 11:05:19.915019 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1579 11:05:19.918293 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1580 11:05:19.921554 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1581 11:05:19.924737 ==
1582 11:05:19.928322 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 11:05:19.931598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 11:05:19.931731 ==
1585 11:05:19.931798 DQS Delay:
1586 11:05:19.934961 DQS0 = 0, DQS1 = 0
1587 11:05:19.935044 DQM Delay:
1588 11:05:19.938200 DQM0 = 89, DQM1 = 78
1589 11:05:19.938283 DQ Delay:
1590 11:05:19.941741 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1591 11:05:19.945047 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1592 11:05:19.948690 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1593 11:05:19.951664 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1594 11:05:19.951791
1595 11:05:19.951855
1596 11:05:19.951929 ==
1597 11:05:19.954857 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 11:05:19.958647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 11:05:19.958734 ==
1600 11:05:19.958799
1601 11:05:19.958858
1602 11:05:19.961879 TX Vref Scan disable
1603 11:05:19.964698 == TX Byte 0 ==
1604 11:05:19.968155 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1605 11:05:19.971169 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1606 11:05:19.974919 == TX Byte 1 ==
1607 11:05:19.978938 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1608 11:05:19.982514 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1609 11:05:19.982600 ==
1610 11:05:19.986658 Dram Type= 6, Freq= 0, CH_1, rank 0
1611 11:05:19.988424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1612 11:05:19.988506 ==
1613 11:05:20.002731 TX Vref=22, minBit 13, minWin=26, winSum=441
1614 11:05:20.006268 TX Vref=24, minBit 9, minWin=27, winSum=448
1615 11:05:20.009427 TX Vref=26, minBit 9, minWin=27, winSum=451
1616 11:05:20.012730 TX Vref=28, minBit 15, minWin=27, winSum=451
1617 11:05:20.016248 TX Vref=30, minBit 10, minWin=27, winSum=449
1618 11:05:20.022834 TX Vref=32, minBit 8, minWin=27, winSum=446
1619 11:05:20.026683 [TxChooseVref] Worse bit 9, Min win 27, Win sum 451, Final Vref 26
1620 11:05:20.026769
1621 11:05:20.029153 Final TX Range 1 Vref 26
1622 11:05:20.029236
1623 11:05:20.029300 ==
1624 11:05:20.033028 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 11:05:20.035870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 11:05:20.039145 ==
1627 11:05:20.039229
1628 11:05:20.039293
1629 11:05:20.039352 TX Vref Scan disable
1630 11:05:20.042981 == TX Byte 0 ==
1631 11:05:20.046160 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1632 11:05:20.052899 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1633 11:05:20.052992 == TX Byte 1 ==
1634 11:05:20.056323 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1635 11:05:20.063178 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1636 11:05:20.063270
1637 11:05:20.063334 [DATLAT]
1638 11:05:20.063394 Freq=800, CH1 RK0
1639 11:05:20.063452
1640 11:05:20.065974 DATLAT Default: 0xa
1641 11:05:20.066055 0, 0xFFFF, sum = 0
1642 11:05:20.069409 1, 0xFFFF, sum = 0
1643 11:05:20.069493 2, 0xFFFF, sum = 0
1644 11:05:20.073001 3, 0xFFFF, sum = 0
1645 11:05:20.076200 4, 0xFFFF, sum = 0
1646 11:05:20.076284 5, 0xFFFF, sum = 0
1647 11:05:20.079105 6, 0xFFFF, sum = 0
1648 11:05:20.079192 7, 0xFFFF, sum = 0
1649 11:05:20.082453 8, 0xFFFF, sum = 0
1650 11:05:20.082537 9, 0x0, sum = 1
1651 11:05:20.085964 10, 0x0, sum = 2
1652 11:05:20.086048 11, 0x0, sum = 3
1653 11:05:20.086114 12, 0x0, sum = 4
1654 11:05:20.090340 best_step = 10
1655 11:05:20.090424
1656 11:05:20.090489 ==
1657 11:05:20.092964 Dram Type= 6, Freq= 0, CH_1, rank 0
1658 11:05:20.096405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1659 11:05:20.096490 ==
1660 11:05:20.099101 RX Vref Scan: 1
1661 11:05:20.099183
1662 11:05:20.102422 Set Vref Range= 32 -> 127
1663 11:05:20.102505
1664 11:05:20.102569 RX Vref 32 -> 127, step: 1
1665 11:05:20.102628
1666 11:05:20.106478 RX Delay -95 -> 252, step: 8
1667 11:05:20.106560
1668 11:05:20.108943 Set Vref, RX VrefLevel [Byte0]: 32
1669 11:05:20.112779 [Byte1]: 32
1670 11:05:20.115694
1671 11:05:20.115790 Set Vref, RX VrefLevel [Byte0]: 33
1672 11:05:20.118727 [Byte1]: 33
1673 11:05:20.123354
1674 11:05:20.123447 Set Vref, RX VrefLevel [Byte0]: 34
1675 11:05:20.126684 [Byte1]: 34
1676 11:05:20.130621
1677 11:05:20.130706 Set Vref, RX VrefLevel [Byte0]: 35
1678 11:05:20.134044 [Byte1]: 35
1679 11:05:20.138374
1680 11:05:20.138459 Set Vref, RX VrefLevel [Byte0]: 36
1681 11:05:20.141890 [Byte1]: 36
1682 11:05:20.146229
1683 11:05:20.146314 Set Vref, RX VrefLevel [Byte0]: 37
1684 11:05:20.149703 [Byte1]: 37
1685 11:05:20.154144
1686 11:05:20.154233 Set Vref, RX VrefLevel [Byte0]: 38
1687 11:05:20.156723 [Byte1]: 38
1688 11:05:20.161168
1689 11:05:20.161254 Set Vref, RX VrefLevel [Byte0]: 39
1690 11:05:20.164719 [Byte1]: 39
1691 11:05:20.169105
1692 11:05:20.169206 Set Vref, RX VrefLevel [Byte0]: 40
1693 11:05:20.172976 [Byte1]: 40
1694 11:05:20.176497
1695 11:05:20.176581 Set Vref, RX VrefLevel [Byte0]: 41
1696 11:05:20.180103 [Byte1]: 41
1697 11:05:20.184183
1698 11:05:20.184267 Set Vref, RX VrefLevel [Byte0]: 42
1699 11:05:20.187200 [Byte1]: 42
1700 11:05:20.192034
1701 11:05:20.192119 Set Vref, RX VrefLevel [Byte0]: 43
1702 11:05:20.195218 [Byte1]: 43
1703 11:05:20.199317
1704 11:05:20.202179 Set Vref, RX VrefLevel [Byte0]: 44
1705 11:05:20.205336 [Byte1]: 44
1706 11:05:20.205421
1707 11:05:20.208885 Set Vref, RX VrefLevel [Byte0]: 45
1708 11:05:20.212314 [Byte1]: 45
1709 11:05:20.212400
1710 11:05:20.215597 Set Vref, RX VrefLevel [Byte0]: 46
1711 11:05:20.218915 [Byte1]: 46
1712 11:05:20.219001
1713 11:05:20.222462 Set Vref, RX VrefLevel [Byte0]: 47
1714 11:05:20.225789 [Byte1]: 47
1715 11:05:20.230005
1716 11:05:20.230098 Set Vref, RX VrefLevel [Byte0]: 48
1717 11:05:20.236423 [Byte1]: 48
1718 11:05:20.236515
1719 11:05:20.239295 Set Vref, RX VrefLevel [Byte0]: 49
1720 11:05:20.242995 [Byte1]: 49
1721 11:05:20.243081
1722 11:05:20.246471 Set Vref, RX VrefLevel [Byte0]: 50
1723 11:05:20.249713 [Byte1]: 50
1724 11:05:20.252413
1725 11:05:20.252516 Set Vref, RX VrefLevel [Byte0]: 51
1726 11:05:20.255809 [Byte1]: 51
1727 11:05:20.259894
1728 11:05:20.259979 Set Vref, RX VrefLevel [Byte0]: 52
1729 11:05:20.263479 [Byte1]: 52
1730 11:05:20.268006
1731 11:05:20.268095 Set Vref, RX VrefLevel [Byte0]: 53
1732 11:05:20.271842 [Byte1]: 53
1733 11:05:20.275214
1734 11:05:20.275301 Set Vref, RX VrefLevel [Byte0]: 54
1735 11:05:20.278459 [Byte1]: 54
1736 11:05:20.282948
1737 11:05:20.283040 Set Vref, RX VrefLevel [Byte0]: 55
1738 11:05:20.286181 [Byte1]: 55
1739 11:05:20.290521
1740 11:05:20.290608 Set Vref, RX VrefLevel [Byte0]: 56
1741 11:05:20.293705 [Byte1]: 56
1742 11:05:20.298000
1743 11:05:20.298091 Set Vref, RX VrefLevel [Byte0]: 57
1744 11:05:20.301504 [Byte1]: 57
1745 11:05:20.305642
1746 11:05:20.305737 Set Vref, RX VrefLevel [Byte0]: 58
1747 11:05:20.308940 [Byte1]: 58
1748 11:05:20.312926
1749 11:05:20.313013 Set Vref, RX VrefLevel [Byte0]: 59
1750 11:05:20.316434 [Byte1]: 59
1751 11:05:20.321206
1752 11:05:20.321298 Set Vref, RX VrefLevel [Byte0]: 60
1753 11:05:20.324611 [Byte1]: 60
1754 11:05:20.328574
1755 11:05:20.328667 Set Vref, RX VrefLevel [Byte0]: 61
1756 11:05:20.331437 [Byte1]: 61
1757 11:05:20.336230
1758 11:05:20.336319 Set Vref, RX VrefLevel [Byte0]: 62
1759 11:05:20.339140 [Byte1]: 62
1760 11:05:20.343631
1761 11:05:20.343758 Set Vref, RX VrefLevel [Byte0]: 63
1762 11:05:20.346972 [Byte1]: 63
1763 11:05:20.350902
1764 11:05:20.350987 Set Vref, RX VrefLevel [Byte0]: 64
1765 11:05:20.354898 [Byte1]: 64
1766 11:05:20.358563
1767 11:05:20.358650 Set Vref, RX VrefLevel [Byte0]: 65
1768 11:05:20.362027 [Byte1]: 65
1769 11:05:20.366404
1770 11:05:20.366491 Set Vref, RX VrefLevel [Byte0]: 66
1771 11:05:20.369614 [Byte1]: 66
1772 11:05:20.373851
1773 11:05:20.373941 Set Vref, RX VrefLevel [Byte0]: 67
1774 11:05:20.377392 [Byte1]: 67
1775 11:05:20.381308
1776 11:05:20.381409 Set Vref, RX VrefLevel [Byte0]: 68
1777 11:05:20.385107 [Byte1]: 68
1778 11:05:20.389708
1779 11:05:20.389826 Set Vref, RX VrefLevel [Byte0]: 69
1780 11:05:20.392711 [Byte1]: 69
1781 11:05:20.396788
1782 11:05:20.396873 Set Vref, RX VrefLevel [Byte0]: 70
1783 11:05:20.400524 [Byte1]: 70
1784 11:05:20.404871
1785 11:05:20.404959 Set Vref, RX VrefLevel [Byte0]: 71
1786 11:05:20.407893 [Byte1]: 71
1787 11:05:20.412158
1788 11:05:20.412244 Set Vref, RX VrefLevel [Byte0]: 72
1789 11:05:20.415935 [Byte1]: 72
1790 11:05:20.419778
1791 11:05:20.419866 Set Vref, RX VrefLevel [Byte0]: 73
1792 11:05:20.422699 [Byte1]: 73
1793 11:05:20.427213
1794 11:05:20.427305 Set Vref, RX VrefLevel [Byte0]: 74
1795 11:05:20.430705 [Byte1]: 74
1796 11:05:20.434771
1797 11:05:20.434866 Set Vref, RX VrefLevel [Byte0]: 75
1798 11:05:20.438193 [Byte1]: 75
1799 11:05:20.442259
1800 11:05:20.442346 Final RX Vref Byte 0 = 57 to rank0
1801 11:05:20.445561 Final RX Vref Byte 1 = 66 to rank0
1802 11:05:20.449393 Final RX Vref Byte 0 = 57 to rank1
1803 11:05:20.452421 Final RX Vref Byte 1 = 66 to rank1==
1804 11:05:20.455880 Dram Type= 6, Freq= 0, CH_1, rank 0
1805 11:05:20.462200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 11:05:20.462351 ==
1807 11:05:20.462416 DQS Delay:
1808 11:05:20.462477 DQS0 = 0, DQS1 = 0
1809 11:05:20.465588 DQM Delay:
1810 11:05:20.465686 DQM0 = 86, DQM1 = 78
1811 11:05:20.469358 DQ Delay:
1812 11:05:20.472534 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1813 11:05:20.476001 DQ4 =80, DQ5 =100, DQ6 =100, DQ7 =80
1814 11:05:20.479154 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1815 11:05:20.482503 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1816 11:05:20.482597
1817 11:05:20.482664
1818 11:05:20.489060 [DQSOSCAuto] RK0, (LSB)MR18= 0x2916, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
1819 11:05:20.492757 CH1 RK0: MR19=606, MR18=2916
1820 11:05:20.499078 CH1_RK0: MR19=0x606, MR18=0x2916, DQSOSC=399, MR23=63, INC=92, DEC=61
1821 11:05:20.499194
1822 11:05:20.502210 ----->DramcWriteLeveling(PI) begin...
1823 11:05:20.502299 ==
1824 11:05:20.505636 Dram Type= 6, Freq= 0, CH_1, rank 1
1825 11:05:20.509025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1826 11:05:20.509122 ==
1827 11:05:20.511960 Write leveling (Byte 0): 26 => 26
1828 11:05:20.515171 Write leveling (Byte 1): 31 => 31
1829 11:05:20.518627 DramcWriteLeveling(PI) end<-----
1830 11:05:20.518726
1831 11:05:20.518792 ==
1832 11:05:20.521782 Dram Type= 6, Freq= 0, CH_1, rank 1
1833 11:05:20.525488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 11:05:20.525598 ==
1835 11:05:20.528308 [Gating] SW mode calibration
1836 11:05:20.535223 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1837 11:05:20.541967 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1838 11:05:20.545349 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1839 11:05:20.552003 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1840 11:05:20.555570 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1841 11:05:20.558905 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 11:05:20.561656 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 11:05:20.568503 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 11:05:20.571788 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 11:05:20.575036 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 11:05:20.581278 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 11:05:20.585110 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 11:05:20.588391 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:05:20.594700 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 11:05:20.598183 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 11:05:20.601454 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 11:05:20.608006 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 11:05:20.611077 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 11:05:20.615340 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1855 11:05:20.621574 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1856 11:05:20.624639 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1857 11:05:20.627695 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 11:05:20.634376 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 11:05:20.637830 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 11:05:20.641681 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 11:05:20.647969 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 11:05:20.650921 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 11:05:20.655009 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 11:05:20.660842 0 9 8 | B1->B0 | 2e2e 2626 | 1 1 | (1 1) (1 1)
1865 11:05:20.664716 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1866 11:05:20.667664 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 11:05:20.674199 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1868 11:05:20.677584 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1869 11:05:20.680786 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1870 11:05:20.687538 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1871 11:05:20.691171 0 10 4 | B1->B0 | 3030 3434 | 0 1 | (0 1) (1 1)
1872 11:05:20.694078 0 10 8 | B1->B0 | 2424 2e2e | 1 1 | (1 0) (1 0)
1873 11:05:20.701270 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 11:05:20.704515 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 11:05:20.707223 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:05:20.713735 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:05:20.717862 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 11:05:20.721013 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:05:20.727241 0 11 4 | B1->B0 | 2525 2525 | 0 0 | (0 0) (1 1)
1880 11:05:20.730527 0 11 8 | B1->B0 | 3d3d 3535 | 0 0 | (0 0) (0 0)
1881 11:05:20.733860 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 11:05:20.740400 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 11:05:20.743583 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 11:05:20.747065 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 11:05:20.753743 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 11:05:20.756547 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 11:05:20.760138 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1888 11:05:20.766935 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 11:05:20.769827 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 11:05:20.773237 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 11:05:20.780086 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 11:05:20.783182 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 11:05:20.786520 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 11:05:20.793211 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 11:05:20.796382 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 11:05:20.799882 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 11:05:20.806580 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 11:05:20.809885 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 11:05:20.812783 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 11:05:20.820036 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 11:05:20.822904 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 11:05:20.826193 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 11:05:20.832954 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1904 11:05:20.835979 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1905 11:05:20.839254 Total UI for P1: 0, mck2ui 16
1906 11:05:20.842799 best dqsien dly found for B1: ( 0, 14, 4)
1907 11:05:20.846180 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 11:05:20.849286 Total UI for P1: 0, mck2ui 16
1909 11:05:20.852529 best dqsien dly found for B0: ( 0, 14, 6)
1910 11:05:20.856281 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1911 11:05:20.859261 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1912 11:05:20.859381
1913 11:05:20.862469 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1914 11:05:20.868995 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1915 11:05:20.869127 [Gating] SW calibration Done
1916 11:05:20.869195 ==
1917 11:05:20.872847 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 11:05:20.879417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 11:05:20.879558 ==
1920 11:05:20.879624 RX Vref Scan: 0
1921 11:05:20.879713
1922 11:05:20.882968 RX Vref 0 -> 0, step: 1
1923 11:05:20.883062
1924 11:05:20.885764 RX Delay -130 -> 252, step: 16
1925 11:05:20.889763 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1926 11:05:20.892476 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1927 11:05:20.895907 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1928 11:05:20.902327 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1929 11:05:20.905647 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1930 11:05:20.908964 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1931 11:05:20.912337 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1932 11:05:20.915834 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1933 11:05:20.922091 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1934 11:05:20.925898 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1935 11:05:20.928742 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1936 11:05:20.931941 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1937 11:05:20.938841 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1938 11:05:20.942162 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1939 11:05:20.945097 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1940 11:05:20.948721 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1941 11:05:20.948835 ==
1942 11:05:20.951546 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 11:05:20.958643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 11:05:20.958782 ==
1945 11:05:20.958850 DQS Delay:
1946 11:05:20.962005 DQS0 = 0, DQS1 = 0
1947 11:05:20.962117 DQM Delay:
1948 11:05:20.962183 DQM0 = 85, DQM1 = 78
1949 11:05:20.965113 DQ Delay:
1950 11:05:20.968145 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1951 11:05:20.971615 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1952 11:05:20.975102 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1953 11:05:20.978205 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1954 11:05:20.978309
1955 11:05:20.978372
1956 11:05:20.978432 ==
1957 11:05:20.981514 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 11:05:20.985436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 11:05:20.985543 ==
1960 11:05:20.985609
1961 11:05:20.985669
1962 11:05:20.988501 TX Vref Scan disable
1963 11:05:20.988596 == TX Byte 0 ==
1964 11:05:20.994991 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1965 11:05:20.998233 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1966 11:05:21.002151 == TX Byte 1 ==
1967 11:05:21.004839 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1968 11:05:21.008616 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1969 11:05:21.008730 ==
1970 11:05:21.011239 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 11:05:21.014587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 11:05:21.017781 ==
1973 11:05:21.029484 TX Vref=22, minBit 9, minWin=26, winSum=443
1974 11:05:21.033328 TX Vref=24, minBit 9, minWin=26, winSum=445
1975 11:05:21.036181 TX Vref=26, minBit 1, minWin=27, winSum=448
1976 11:05:21.039435 TX Vref=28, minBit 8, minWin=27, winSum=452
1977 11:05:21.043127 TX Vref=30, minBit 8, minWin=27, winSum=446
1978 11:05:21.049748 TX Vref=32, minBit 8, minWin=27, winSum=450
1979 11:05:21.053007 [TxChooseVref] Worse bit 8, Min win 27, Win sum 452, Final Vref 28
1980 11:05:21.053125
1981 11:05:21.055874 Final TX Range 1 Vref 28
1982 11:05:21.055964
1983 11:05:21.056030 ==
1984 11:05:21.059424 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 11:05:21.062455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 11:05:21.062557 ==
1987 11:05:21.066105
1988 11:05:21.066203
1989 11:05:21.066268 TX Vref Scan disable
1990 11:05:21.069437 == TX Byte 0 ==
1991 11:05:21.072858 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1992 11:05:21.076764 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1993 11:05:21.079501 == TX Byte 1 ==
1994 11:05:21.082508 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1995 11:05:21.089324 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1996 11:05:21.089459
1997 11:05:21.089529 [DATLAT]
1998 11:05:21.089590 Freq=800, CH1 RK1
1999 11:05:21.089649
2000 11:05:21.093190 DATLAT Default: 0xa
2001 11:05:21.093285 0, 0xFFFF, sum = 0
2002 11:05:21.095838 1, 0xFFFF, sum = 0
2003 11:05:21.095927 2, 0xFFFF, sum = 0
2004 11:05:21.099355 3, 0xFFFF, sum = 0
2005 11:05:21.102523 4, 0xFFFF, sum = 0
2006 11:05:21.102625 5, 0xFFFF, sum = 0
2007 11:05:21.105871 6, 0xFFFF, sum = 0
2008 11:05:21.105993 7, 0xFFFF, sum = 0
2009 11:05:21.109111 8, 0xFFFF, sum = 0
2010 11:05:21.109205 9, 0x0, sum = 1
2011 11:05:21.112566 10, 0x0, sum = 2
2012 11:05:21.112667 11, 0x0, sum = 3
2013 11:05:21.112733 12, 0x0, sum = 4
2014 11:05:21.115968 best_step = 10
2015 11:05:21.116057
2016 11:05:21.116122 ==
2017 11:05:21.119024 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 11:05:21.122594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 11:05:21.122697 ==
2020 11:05:21.125984 RX Vref Scan: 0
2021 11:05:21.126096
2022 11:05:21.129438 RX Vref 0 -> 0, step: 1
2023 11:05:21.129534
2024 11:05:21.129598 RX Delay -95 -> 252, step: 8
2025 11:05:21.136022 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2026 11:05:21.139093 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2027 11:05:21.142899 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2028 11:05:21.145596 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2029 11:05:21.153190 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2030 11:05:21.156076 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2031 11:05:21.159808 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2032 11:05:21.162400 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2033 11:05:21.165832 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2034 11:05:21.172729 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2035 11:05:21.176241 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2036 11:05:21.178879 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2037 11:05:21.182387 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2038 11:05:21.185455 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2039 11:05:21.191919 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
2040 11:05:21.195809 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2041 11:05:21.195930 ==
2042 11:05:21.199152 Dram Type= 6, Freq= 0, CH_1, rank 1
2043 11:05:21.202529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2044 11:05:21.202637 ==
2045 11:05:21.205612 DQS Delay:
2046 11:05:21.205707 DQS0 = 0, DQS1 = 0
2047 11:05:21.205774 DQM Delay:
2048 11:05:21.209719 DQM0 = 87, DQM1 = 79
2049 11:05:21.209814 DQ Delay:
2050 11:05:21.211991 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =84
2051 11:05:21.215118 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2052 11:05:21.218937 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
2053 11:05:21.221834 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
2054 11:05:21.221952
2055 11:05:21.222019
2056 11:05:21.232085 [DQSOSCAuto] RK1, (LSB)MR18= 0x110a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 405 ps
2057 11:05:21.235184 CH1 RK1: MR19=606, MR18=110A
2058 11:05:21.238494 CH1_RK1: MR19=0x606, MR18=0x110A, DQSOSC=405, MR23=63, INC=90, DEC=60
2059 11:05:21.241635 [RxdqsGatingPostProcess] freq 800
2060 11:05:21.248516 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2061 11:05:21.251891 Pre-setting of DQS Precalculation
2062 11:05:21.254965 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2063 11:05:21.264798 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2064 11:05:21.271487 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2065 11:05:21.271636
2066 11:05:21.271766
2067 11:05:21.274807 [Calibration Summary] 1600 Mbps
2068 11:05:21.274901 CH 0, Rank 0
2069 11:05:21.279062 SW Impedance : PASS
2070 11:05:21.279168 DUTY Scan : NO K
2071 11:05:21.281500 ZQ Calibration : PASS
2072 11:05:21.285161 Jitter Meter : NO K
2073 11:05:21.285273 CBT Training : PASS
2074 11:05:21.288182 Write leveling : PASS
2075 11:05:21.291092 RX DQS gating : PASS
2076 11:05:21.291198 RX DQ/DQS(RDDQC) : PASS
2077 11:05:21.294273 TX DQ/DQS : PASS
2078 11:05:21.297920 RX DATLAT : PASS
2079 11:05:21.298026 RX DQ/DQS(Engine): PASS
2080 11:05:21.301091 TX OE : NO K
2081 11:05:21.301189 All Pass.
2082 11:05:21.301257
2083 11:05:21.304656 CH 0, Rank 1
2084 11:05:21.304750 SW Impedance : PASS
2085 11:05:21.307814 DUTY Scan : NO K
2086 11:05:21.310751 ZQ Calibration : PASS
2087 11:05:21.310849 Jitter Meter : NO K
2088 11:05:21.314893 CBT Training : PASS
2089 11:05:21.317477 Write leveling : PASS
2090 11:05:21.317580 RX DQS gating : PASS
2091 11:05:21.321336 RX DQ/DQS(RDDQC) : PASS
2092 11:05:21.324852 TX DQ/DQS : PASS
2093 11:05:21.324974 RX DATLAT : PASS
2094 11:05:21.327544 RX DQ/DQS(Engine): PASS
2095 11:05:21.330509 TX OE : NO K
2096 11:05:21.330625 All Pass.
2097 11:05:21.330692
2098 11:05:21.330754 CH 1, Rank 0
2099 11:05:21.334091 SW Impedance : PASS
2100 11:05:21.337626 DUTY Scan : NO K
2101 11:05:21.337731 ZQ Calibration : PASS
2102 11:05:21.340811 Jitter Meter : NO K
2103 11:05:21.340912 CBT Training : PASS
2104 11:05:21.344590 Write leveling : PASS
2105 11:05:21.347422 RX DQS gating : PASS
2106 11:05:21.347547 RX DQ/DQS(RDDQC) : PASS
2107 11:05:21.350384 TX DQ/DQS : PASS
2108 11:05:21.353906 RX DATLAT : PASS
2109 11:05:21.354026 RX DQ/DQS(Engine): PASS
2110 11:05:21.357416 TX OE : NO K
2111 11:05:21.357520 All Pass.
2112 11:05:21.357584
2113 11:05:21.360583 CH 1, Rank 1
2114 11:05:21.360678 SW Impedance : PASS
2115 11:05:21.363900 DUTY Scan : NO K
2116 11:05:21.367022 ZQ Calibration : PASS
2117 11:05:21.367132 Jitter Meter : NO K
2118 11:05:21.371193 CBT Training : PASS
2119 11:05:21.373473 Write leveling : PASS
2120 11:05:21.373571 RX DQS gating : PASS
2121 11:05:21.377176 RX DQ/DQS(RDDQC) : PASS
2122 11:05:21.380083 TX DQ/DQS : PASS
2123 11:05:21.380186 RX DATLAT : PASS
2124 11:05:21.383433 RX DQ/DQS(Engine): PASS
2125 11:05:21.386596 TX OE : NO K
2126 11:05:21.386699 All Pass.
2127 11:05:21.386807
2128 11:05:21.386868 DramC Write-DBI off
2129 11:05:21.389982 PER_BANK_REFRESH: Hybrid Mode
2130 11:05:21.393768 TX_TRACKING: ON
2131 11:05:21.396962 [GetDramInforAfterCalByMRR] Vendor 6.
2132 11:05:21.400217 [GetDramInforAfterCalByMRR] Revision 606.
2133 11:05:21.403676 [GetDramInforAfterCalByMRR] Revision 2 0.
2134 11:05:21.403783 MR0 0x3b3b
2135 11:05:21.406716 MR8 0x5151
2136 11:05:21.410310 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2137 11:05:21.410422
2138 11:05:21.410488 MR0 0x3b3b
2139 11:05:21.410548 MR8 0x5151
2140 11:05:21.416686 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2141 11:05:21.416854
2142 11:05:21.423181 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2143 11:05:21.427201 [FAST_K] Save calibration result to emmc
2144 11:05:21.430158 [FAST_K] Save calibration result to emmc
2145 11:05:21.433514 dram_init: config_dvfs: 1
2146 11:05:21.436642 dramc_set_vcore_voltage set vcore to 662500
2147 11:05:21.440133 Read voltage for 1200, 2
2148 11:05:21.440244 Vio18 = 0
2149 11:05:21.443393 Vcore = 662500
2150 11:05:21.443483 Vdram = 0
2151 11:05:21.443549 Vddq = 0
2152 11:05:21.446853 Vmddr = 0
2153 11:05:21.450230 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2154 11:05:21.456761 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2155 11:05:21.456902 MEM_TYPE=3, freq_sel=15
2156 11:05:21.460039 sv_algorithm_assistance_LP4_1600
2157 11:05:21.467263 ============ PULL DRAM RESETB DOWN ============
2158 11:05:21.469952 ========== PULL DRAM RESETB DOWN end =========
2159 11:05:21.473076 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2160 11:05:21.475955 ===================================
2161 11:05:21.480020 LPDDR4 DRAM CONFIGURATION
2162 11:05:21.482596 ===================================
2163 11:05:21.482697 EX_ROW_EN[0] = 0x0
2164 11:05:21.486465 EX_ROW_EN[1] = 0x0
2165 11:05:21.489187 LP4Y_EN = 0x0
2166 11:05:21.489284 WORK_FSP = 0x0
2167 11:05:21.492606 WL = 0x4
2168 11:05:21.492703 RL = 0x4
2169 11:05:21.496305 BL = 0x2
2170 11:05:21.496403 RPST = 0x0
2171 11:05:21.499364 RD_PRE = 0x0
2172 11:05:21.499454 WR_PRE = 0x1
2173 11:05:21.502844 WR_PST = 0x0
2174 11:05:21.502943 DBI_WR = 0x0
2175 11:05:21.506688 DBI_RD = 0x0
2176 11:05:21.506803 OTF = 0x1
2177 11:05:21.509938 ===================================
2178 11:05:21.512703 ===================================
2179 11:05:21.516222 ANA top config
2180 11:05:21.519394 ===================================
2181 11:05:21.522866 DLL_ASYNC_EN = 0
2182 11:05:21.523006 ALL_SLAVE_EN = 0
2183 11:05:21.525821 NEW_RANK_MODE = 1
2184 11:05:21.528988 DLL_IDLE_MODE = 1
2185 11:05:21.532732 LP45_APHY_COMB_EN = 1
2186 11:05:21.532859 TX_ODT_DIS = 1
2187 11:05:21.536122 NEW_8X_MODE = 1
2188 11:05:21.539980 ===================================
2189 11:05:21.543160 ===================================
2190 11:05:21.545392 data_rate = 2400
2191 11:05:21.549144 CKR = 1
2192 11:05:21.552048 DQ_P2S_RATIO = 8
2193 11:05:21.555615 ===================================
2194 11:05:21.559046 CA_P2S_RATIO = 8
2195 11:05:21.559158 DQ_CA_OPEN = 0
2196 11:05:21.562250 DQ_SEMI_OPEN = 0
2197 11:05:21.565549 CA_SEMI_OPEN = 0
2198 11:05:21.569433 CA_FULL_RATE = 0
2199 11:05:21.572215 DQ_CKDIV4_EN = 0
2200 11:05:21.575517 CA_CKDIV4_EN = 0
2201 11:05:21.575622 CA_PREDIV_EN = 0
2202 11:05:21.578819 PH8_DLY = 17
2203 11:05:21.581799 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2204 11:05:21.585484 DQ_AAMCK_DIV = 4
2205 11:05:21.588328 CA_AAMCK_DIV = 4
2206 11:05:21.591977 CA_ADMCK_DIV = 4
2207 11:05:21.592091 DQ_TRACK_CA_EN = 0
2208 11:05:21.595178 CA_PICK = 1200
2209 11:05:21.598436 CA_MCKIO = 1200
2210 11:05:21.601850 MCKIO_SEMI = 0
2211 11:05:21.605177 PLL_FREQ = 2366
2212 11:05:21.608413 DQ_UI_PI_RATIO = 32
2213 11:05:21.612429 CA_UI_PI_RATIO = 0
2214 11:05:21.615376 ===================================
2215 11:05:21.618506 ===================================
2216 11:05:21.618622 memory_type:LPDDR4
2217 11:05:21.622254 GP_NUM : 10
2218 11:05:21.624916 SRAM_EN : 1
2219 11:05:21.625028 MD32_EN : 0
2220 11:05:21.628362 ===================================
2221 11:05:21.631531 [ANA_INIT] >>>>>>>>>>>>>>
2222 11:05:21.634646 <<<<<< [CONFIGURE PHASE]: ANA_TX
2223 11:05:21.638422 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2224 11:05:21.641343 ===================================
2225 11:05:21.644640 data_rate = 2400,PCW = 0X5b00
2226 11:05:21.648854 ===================================
2227 11:05:21.651452 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2228 11:05:21.655311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2229 11:05:21.661112 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2230 11:05:21.664495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2231 11:05:21.671423 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2232 11:05:21.674554 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2233 11:05:21.674673 [ANA_INIT] flow start
2234 11:05:21.677715 [ANA_INIT] PLL >>>>>>>>
2235 11:05:21.680935 [ANA_INIT] PLL <<<<<<<<
2236 11:05:21.681038 [ANA_INIT] MIDPI >>>>>>>>
2237 11:05:21.684621 [ANA_INIT] MIDPI <<<<<<<<
2238 11:05:21.688167 [ANA_INIT] DLL >>>>>>>>
2239 11:05:21.688274 [ANA_INIT] DLL <<<<<<<<
2240 11:05:21.691241 [ANA_INIT] flow end
2241 11:05:21.694869 ============ LP4 DIFF to SE enter ============
2242 11:05:21.697673 ============ LP4 DIFF to SE exit ============
2243 11:05:21.700971 [ANA_INIT] <<<<<<<<<<<<<
2244 11:05:21.704778 [Flow] Enable top DCM control >>>>>
2245 11:05:21.707431 [Flow] Enable top DCM control <<<<<
2246 11:05:21.710846 Enable DLL master slave shuffle
2247 11:05:21.717718 ==============================================================
2248 11:05:21.717861 Gating Mode config
2249 11:05:21.724521 ==============================================================
2250 11:05:21.724747 Config description:
2251 11:05:21.734650 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2252 11:05:21.741027 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2253 11:05:21.748212 SELPH_MODE 0: By rank 1: By Phase
2254 11:05:21.750592 ==============================================================
2255 11:05:21.753845 GAT_TRACK_EN = 1
2256 11:05:21.757307 RX_GATING_MODE = 2
2257 11:05:21.761141 RX_GATING_TRACK_MODE = 2
2258 11:05:21.763945 SELPH_MODE = 1
2259 11:05:21.767864 PICG_EARLY_EN = 1
2260 11:05:21.770532 VALID_LAT_VALUE = 1
2261 11:05:21.776780 ==============================================================
2262 11:05:21.780061 Enter into Gating configuration >>>>
2263 11:05:21.783481 Exit from Gating configuration <<<<
2264 11:05:21.787134 Enter into DVFS_PRE_config >>>>>
2265 11:05:21.796678 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2266 11:05:21.799887 Exit from DVFS_PRE_config <<<<<
2267 11:05:21.804061 Enter into PICG configuration >>>>
2268 11:05:21.807273 Exit from PICG configuration <<<<
2269 11:05:21.809956 [RX_INPUT] configuration >>>>>
2270 11:05:21.813089 [RX_INPUT] configuration <<<<<
2271 11:05:21.816439 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2272 11:05:21.823048 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2273 11:05:21.829502 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2274 11:05:21.833197 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2275 11:05:21.840232 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2276 11:05:21.846133 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2277 11:05:21.849966 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2278 11:05:21.856354 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2279 11:05:21.859738 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2280 11:05:21.862966 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2281 11:05:21.866286 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2282 11:05:21.873119 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2283 11:05:21.876151 ===================================
2284 11:05:21.876266 LPDDR4 DRAM CONFIGURATION
2285 11:05:21.879467 ===================================
2286 11:05:21.883030 EX_ROW_EN[0] = 0x0
2287 11:05:21.886217 EX_ROW_EN[1] = 0x0
2288 11:05:21.886332 LP4Y_EN = 0x0
2289 11:05:21.889391 WORK_FSP = 0x0
2290 11:05:21.889488 WL = 0x4
2291 11:05:21.892575 RL = 0x4
2292 11:05:21.892672 BL = 0x2
2293 11:05:21.896286 RPST = 0x0
2294 11:05:21.896384 RD_PRE = 0x0
2295 11:05:21.899459 WR_PRE = 0x1
2296 11:05:21.899566 WR_PST = 0x0
2297 11:05:21.902326 DBI_WR = 0x0
2298 11:05:21.902420 DBI_RD = 0x0
2299 11:05:21.905648 OTF = 0x1
2300 11:05:21.909327 ===================================
2301 11:05:21.912583 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2302 11:05:21.915741 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2303 11:05:21.922335 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2304 11:05:21.926420 ===================================
2305 11:05:21.926556 LPDDR4 DRAM CONFIGURATION
2306 11:05:21.928767 ===================================
2307 11:05:21.932150 EX_ROW_EN[0] = 0x10
2308 11:05:21.936656 EX_ROW_EN[1] = 0x0
2309 11:05:21.936795 LP4Y_EN = 0x0
2310 11:05:21.939444 WORK_FSP = 0x0
2311 11:05:21.939544 WL = 0x4
2312 11:05:21.942430 RL = 0x4
2313 11:05:21.942532 BL = 0x2
2314 11:05:21.946284 RPST = 0x0
2315 11:05:21.946384 RD_PRE = 0x0
2316 11:05:21.949152 WR_PRE = 0x1
2317 11:05:21.949242 WR_PST = 0x0
2318 11:05:21.952839 DBI_WR = 0x0
2319 11:05:21.952938 DBI_RD = 0x0
2320 11:05:21.955527 OTF = 0x1
2321 11:05:21.958750 ===================================
2322 11:05:21.965670 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2323 11:05:21.965841 ==
2324 11:05:21.968632 Dram Type= 6, Freq= 0, CH_0, rank 0
2325 11:05:21.972363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2326 11:05:21.972524 ==
2327 11:05:21.975339 [Duty_Offset_Calibration]
2328 11:05:21.975460 B0:1 B1:-1 CA:0
2329 11:05:21.975557
2330 11:05:21.978662 [DutyScan_Calibration_Flow] k_type=0
2331 11:05:21.988956
2332 11:05:21.989159 ==CLK 0==
2333 11:05:21.992592 Final CLK duty delay cell = 0
2334 11:05:21.995940 [0] MAX Duty = 5125%(X100), DQS PI = 24
2335 11:05:21.998932 [0] MIN Duty = 4907%(X100), DQS PI = 8
2336 11:05:21.999084 [0] AVG Duty = 5016%(X100)
2337 11:05:22.001958
2338 11:05:22.005349 CH0 CLK Duty spec in!! Max-Min= 218%
2339 11:05:22.008628 [DutyScan_Calibration_Flow] ====Done====
2340 11:05:22.008764
2341 11:05:22.011908 [DutyScan_Calibration_Flow] k_type=1
2342 11:05:22.026895
2343 11:05:22.027095 ==DQS 0 ==
2344 11:05:22.030011 Final DQS duty delay cell = -4
2345 11:05:22.033315 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2346 11:05:22.037014 [-4] MIN Duty = 4875%(X100), DQS PI = 6
2347 11:05:22.039847 [-4] AVG Duty = 4968%(X100)
2348 11:05:22.039977
2349 11:05:22.040077 ==DQS 1 ==
2350 11:05:22.043155 Final DQS duty delay cell = -4
2351 11:05:22.046411 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2352 11:05:22.050126 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2353 11:05:22.053685 [-4] AVG Duty = 4938%(X100)
2354 11:05:22.053836
2355 11:05:22.057230 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2356 11:05:22.057356
2357 11:05:22.060357 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2358 11:05:22.063135 [DutyScan_Calibration_Flow] ====Done====
2359 11:05:22.063260
2360 11:05:22.066550 [DutyScan_Calibration_Flow] k_type=3
2361 11:05:22.084991
2362 11:05:22.085190 ==DQM 0 ==
2363 11:05:22.088561 Final DQM duty delay cell = 0
2364 11:05:22.091214 [0] MAX Duty = 5031%(X100), DQS PI = 16
2365 11:05:22.094412 [0] MIN Duty = 4875%(X100), DQS PI = 8
2366 11:05:22.098425 [0] AVG Duty = 4953%(X100)
2367 11:05:22.098575
2368 11:05:22.098679 ==DQM 1 ==
2369 11:05:22.101296 Final DQM duty delay cell = 4
2370 11:05:22.104266 [4] MAX Duty = 5187%(X100), DQS PI = 14
2371 11:05:22.108010 [4] MIN Duty = 5000%(X100), DQS PI = 24
2372 11:05:22.110915 [4] AVG Duty = 5093%(X100)
2373 11:05:22.111055
2374 11:05:22.114664 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2375 11:05:22.114798
2376 11:05:22.117914 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2377 11:05:22.120768 [DutyScan_Calibration_Flow] ====Done====
2378 11:05:22.120897
2379 11:05:22.123951 [DutyScan_Calibration_Flow] k_type=2
2380 11:05:22.139848
2381 11:05:22.140047 ==DQ 0 ==
2382 11:05:22.143248 Final DQ duty delay cell = -4
2383 11:05:22.146465 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2384 11:05:22.149426 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2385 11:05:22.152793 [-4] AVG Duty = 4969%(X100)
2386 11:05:22.152934
2387 11:05:22.153038 ==DQ 1 ==
2388 11:05:22.156236 Final DQ duty delay cell = -4
2389 11:05:22.159432 [-4] MAX Duty = 5000%(X100), DQS PI = 56
2390 11:05:22.162893 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2391 11:05:22.165987 [-4] AVG Duty = 4938%(X100)
2392 11:05:22.166128
2393 11:05:22.169467 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2394 11:05:22.169598
2395 11:05:22.172602 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2396 11:05:22.175973 [DutyScan_Calibration_Flow] ====Done====
2397 11:05:22.176104 ==
2398 11:05:22.179154 Dram Type= 6, Freq= 0, CH_1, rank 0
2399 11:05:22.182348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2400 11:05:22.182467 ==
2401 11:05:22.185725 [Duty_Offset_Calibration]
2402 11:05:22.185825 B0:-1 B1:1 CA:1
2403 11:05:22.189117
2404 11:05:22.192983 [DutyScan_Calibration_Flow] k_type=0
2405 11:05:22.200530
2406 11:05:22.200673 ==CLK 0==
2407 11:05:22.203253 Final CLK duty delay cell = 0
2408 11:05:22.207272 [0] MAX Duty = 5156%(X100), DQS PI = 20
2409 11:05:22.210272 [0] MIN Duty = 4969%(X100), DQS PI = 62
2410 11:05:22.210410 [0] AVG Duty = 5062%(X100)
2411 11:05:22.213316
2412 11:05:22.217365 CH1 CLK Duty spec in!! Max-Min= 187%
2413 11:05:22.220152 [DutyScan_Calibration_Flow] ====Done====
2414 11:05:22.220286
2415 11:05:22.223573 [DutyScan_Calibration_Flow] k_type=1
2416 11:05:22.239806
2417 11:05:22.240006 ==DQS 0 ==
2418 11:05:22.243429 Final DQS duty delay cell = 0
2419 11:05:22.246680 [0] MAX Duty = 5156%(X100), DQS PI = 48
2420 11:05:22.249424 [0] MIN Duty = 4907%(X100), DQS PI = 6
2421 11:05:22.249556 [0] AVG Duty = 5031%(X100)
2422 11:05:22.252984
2423 11:05:22.253107 ==DQS 1 ==
2424 11:05:22.256057 Final DQS duty delay cell = 0
2425 11:05:22.259559 [0] MAX Duty = 5094%(X100), DQS PI = 12
2426 11:05:22.262924 [0] MIN Duty = 4969%(X100), DQS PI = 58
2427 11:05:22.266250 [0] AVG Duty = 5031%(X100)
2428 11:05:22.266394
2429 11:05:22.269038 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2430 11:05:22.269153
2431 11:05:22.272822 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2432 11:05:22.275843 [DutyScan_Calibration_Flow] ====Done====
2433 11:05:22.275981
2434 11:05:22.278915 [DutyScan_Calibration_Flow] k_type=3
2435 11:05:22.295557
2436 11:05:22.295767 ==DQM 0 ==
2437 11:05:22.298649 Final DQM duty delay cell = -4
2438 11:05:22.301565 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2439 11:05:22.305097 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2440 11:05:22.308335 [-4] AVG Duty = 4953%(X100)
2441 11:05:22.308482
2442 11:05:22.308584 ==DQM 1 ==
2443 11:05:22.311602 Final DQM duty delay cell = 0
2444 11:05:22.315186 [0] MAX Duty = 5156%(X100), DQS PI = 6
2445 11:05:22.317986 [0] MIN Duty = 4969%(X100), DQS PI = 28
2446 11:05:22.321583 [0] AVG Duty = 5062%(X100)
2447 11:05:22.321737
2448 11:05:22.324649 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2449 11:05:22.324772
2450 11:05:22.327962 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2451 11:05:22.331307 [DutyScan_Calibration_Flow] ====Done====
2452 11:05:22.331437
2453 11:05:22.334791 [DutyScan_Calibration_Flow] k_type=2
2454 11:05:22.352566
2455 11:05:22.352769 ==DQ 0 ==
2456 11:05:22.354977 Final DQ duty delay cell = 0
2457 11:05:22.358185 [0] MAX Duty = 5156%(X100), DQS PI = 28
2458 11:05:22.362294 [0] MIN Duty = 4907%(X100), DQS PI = 8
2459 11:05:22.362447 [0] AVG Duty = 5031%(X100)
2460 11:05:22.365029
2461 11:05:22.365153 ==DQ 1 ==
2462 11:05:22.368297 Final DQ duty delay cell = 0
2463 11:05:22.372209 [0] MAX Duty = 5124%(X100), DQS PI = 10
2464 11:05:22.375547 [0] MIN Duty = 4969%(X100), DQS PI = 0
2465 11:05:22.375702 [0] AVG Duty = 5046%(X100)
2466 11:05:22.375809
2467 11:05:22.378749 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2468 11:05:22.381916
2469 11:05:22.385456 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2470 11:05:22.388922 [DutyScan_Calibration_Flow] ====Done====
2471 11:05:22.391576 nWR fixed to 30
2472 11:05:22.391705 [ModeRegInit_LP4] CH0 RK0
2473 11:05:22.395012 [ModeRegInit_LP4] CH0 RK1
2474 11:05:22.398363 [ModeRegInit_LP4] CH1 RK0
2475 11:05:22.401343 [ModeRegInit_LP4] CH1 RK1
2476 11:05:22.401460 match AC timing 7
2477 11:05:22.404472 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2478 11:05:22.411138 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2479 11:05:22.414842 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2480 11:05:22.421540 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2481 11:05:22.424686 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2482 11:05:22.424803 ==
2483 11:05:22.428027 Dram Type= 6, Freq= 0, CH_0, rank 0
2484 11:05:22.431464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2485 11:05:22.431580 ==
2486 11:05:22.437672 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2487 11:05:22.444770 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2488 11:05:22.451434 [CA 0] Center 39 (9~70) winsize 62
2489 11:05:22.454721 [CA 1] Center 39 (9~70) winsize 62
2490 11:05:22.458017 [CA 2] Center 35 (5~66) winsize 62
2491 11:05:22.461363 [CA 3] Center 35 (5~65) winsize 61
2492 11:05:22.465588 [CA 4] Center 34 (4~64) winsize 61
2493 11:05:22.468380 [CA 5] Center 33 (4~63) winsize 60
2494 11:05:22.468500
2495 11:05:22.471631 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2496 11:05:22.471760
2497 11:05:22.475054 [CATrainingPosCal] consider 1 rank data
2498 11:05:22.477953 u2DelayCellTimex100 = 270/100 ps
2499 11:05:22.481399 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2500 11:05:22.488255 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2501 11:05:22.491040 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2502 11:05:22.494895 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2503 11:05:22.498949 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2504 11:05:22.501460 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2505 11:05:22.501565
2506 11:05:22.504382 CA PerBit enable=1, Macro0, CA PI delay=33
2507 11:05:22.504482
2508 11:05:22.507817 [CBTSetCACLKResult] CA Dly = 33
2509 11:05:22.511599 CS Dly: 8 (0~39)
2510 11:05:22.511764 ==
2511 11:05:22.514507 Dram Type= 6, Freq= 0, CH_0, rank 1
2512 11:05:22.517402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 11:05:22.517505 ==
2514 11:05:22.524367 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2515 11:05:22.528014 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2516 11:05:22.537446 [CA 0] Center 39 (9~70) winsize 62
2517 11:05:22.540604 [CA 1] Center 39 (9~70) winsize 62
2518 11:05:22.544017 [CA 2] Center 35 (5~66) winsize 62
2519 11:05:22.547410 [CA 3] Center 34 (4~65) winsize 62
2520 11:05:22.550597 [CA 4] Center 33 (3~64) winsize 62
2521 11:05:22.554027 [CA 5] Center 33 (3~63) winsize 61
2522 11:05:22.554137
2523 11:05:22.557799 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2524 11:05:22.557917
2525 11:05:22.560757 [CATrainingPosCal] consider 2 rank data
2526 11:05:22.563871 u2DelayCellTimex100 = 270/100 ps
2527 11:05:22.567124 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2528 11:05:22.574191 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2529 11:05:22.577178 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2530 11:05:22.580729 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2531 11:05:22.584083 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2532 11:05:22.587195 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2533 11:05:22.587302
2534 11:05:22.590204 CA PerBit enable=1, Macro0, CA PI delay=33
2535 11:05:22.590301
2536 11:05:22.593460 [CBTSetCACLKResult] CA Dly = 33
2537 11:05:22.593555 CS Dly: 9 (0~41)
2538 11:05:22.597063
2539 11:05:22.600562 ----->DramcWriteLeveling(PI) begin...
2540 11:05:22.600676 ==
2541 11:05:22.603363 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 11:05:22.607099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2543 11:05:22.607225 ==
2544 11:05:22.610464 Write leveling (Byte 0): 33 => 33
2545 11:05:22.613745 Write leveling (Byte 1): 28 => 28
2546 11:05:22.616707 DramcWriteLeveling(PI) end<-----
2547 11:05:22.616810
2548 11:05:22.616877 ==
2549 11:05:22.620679 Dram Type= 6, Freq= 0, CH_0, rank 0
2550 11:05:22.623699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2551 11:05:22.623819 ==
2552 11:05:22.627006 [Gating] SW mode calibration
2553 11:05:22.633328 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2554 11:05:22.639990 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2555 11:05:22.643596 0 15 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
2556 11:05:22.646789 0 15 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2557 11:05:22.653354 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2558 11:05:22.656912 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2559 11:05:22.660144 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2560 11:05:22.666592 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2561 11:05:22.669338 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2562 11:05:22.673850 0 15 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
2563 11:05:22.679461 1 0 0 | B1->B0 | 3333 2424 | 0 0 | (0 1) (0 0)
2564 11:05:22.683511 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2565 11:05:22.686255 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2566 11:05:22.692556 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2567 11:05:22.696539 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2568 11:05:22.699374 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2569 11:05:22.706169 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2570 11:05:22.709512 1 0 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
2571 11:05:22.712817 1 1 0 | B1->B0 | 2625 4646 | 1 0 | (0 0) (0 0)
2572 11:05:22.719463 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2573 11:05:22.722741 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 11:05:22.725753 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 11:05:22.732479 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 11:05:22.735952 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 11:05:22.739084 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2578 11:05:22.745765 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2579 11:05:22.749024 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2580 11:05:22.752286 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 11:05:22.758940 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 11:05:22.762224 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 11:05:22.765736 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 11:05:22.772168 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 11:05:22.775367 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 11:05:22.778934 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 11:05:22.785329 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 11:05:22.789076 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 11:05:22.792060 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 11:05:22.798590 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 11:05:22.802242 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 11:05:22.805201 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 11:05:22.808445 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 11:05:22.814975 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2595 11:05:22.818456 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2596 11:05:22.822061 Total UI for P1: 0, mck2ui 16
2597 11:05:22.825891 best dqsien dly found for B0: ( 1, 3, 28)
2598 11:05:22.828192 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2599 11:05:22.835120 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 11:05:22.838270 Total UI for P1: 0, mck2ui 16
2601 11:05:22.841512 best dqsien dly found for B1: ( 1, 4, 2)
2602 11:05:22.845504 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2603 11:05:22.847987 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2604 11:05:22.848115
2605 11:05:22.851887 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2606 11:05:22.854998 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2607 11:05:22.858090 [Gating] SW calibration Done
2608 11:05:22.858201 ==
2609 11:05:22.861263 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 11:05:22.864884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 11:05:22.864997 ==
2612 11:05:22.868616 RX Vref Scan: 0
2613 11:05:22.868725
2614 11:05:22.871659 RX Vref 0 -> 0, step: 1
2615 11:05:22.871806
2616 11:05:22.871878 RX Delay -40 -> 252, step: 8
2617 11:05:22.878161 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2618 11:05:22.881519 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2619 11:05:22.884692 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2620 11:05:22.888057 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2621 11:05:22.891404 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2622 11:05:22.898385 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2623 11:05:22.901311 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2624 11:05:22.904526 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2625 11:05:22.907647 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2626 11:05:22.910912 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2627 11:05:22.918149 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2628 11:05:22.921381 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2629 11:05:22.924958 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2630 11:05:22.927658 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2631 11:05:22.930992 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2632 11:05:22.937775 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2633 11:05:22.937922 ==
2634 11:05:22.941217 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 11:05:22.944433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 11:05:22.944539 ==
2637 11:05:22.944606 DQS Delay:
2638 11:05:22.947885 DQS0 = 0, DQS1 = 0
2639 11:05:22.947978 DQM Delay:
2640 11:05:22.951055 DQM0 = 119, DQM1 = 107
2641 11:05:22.951166 DQ Delay:
2642 11:05:22.954541 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2643 11:05:22.957701 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2644 11:05:22.961213 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2645 11:05:22.964264 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2646 11:05:22.964367
2647 11:05:22.964433
2648 11:05:22.967348 ==
2649 11:05:22.970563 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 11:05:22.973798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 11:05:22.973982 ==
2652 11:05:22.974051
2653 11:05:22.974113
2654 11:05:22.977400 TX Vref Scan disable
2655 11:05:22.977494 == TX Byte 0 ==
2656 11:05:22.983887 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2657 11:05:22.987089 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2658 11:05:22.987205 == TX Byte 1 ==
2659 11:05:22.994094 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2660 11:05:22.996863 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2661 11:05:22.996974 ==
2662 11:05:23.000328 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 11:05:23.003435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 11:05:23.003541 ==
2665 11:05:23.016653 TX Vref=22, minBit 1, minWin=25, winSum=416
2666 11:05:23.019453 TX Vref=24, minBit 8, minWin=25, winSum=423
2667 11:05:23.022834 TX Vref=26, minBit 4, minWin=26, winSum=427
2668 11:05:23.026444 TX Vref=28, minBit 10, minWin=26, winSum=435
2669 11:05:23.029428 TX Vref=30, minBit 5, minWin=26, winSum=433
2670 11:05:23.036226 TX Vref=32, minBit 4, minWin=26, winSum=429
2671 11:05:23.040178 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 28
2672 11:05:23.040302
2673 11:05:23.042902 Final TX Range 1 Vref 28
2674 11:05:23.042993
2675 11:05:23.043059 ==
2676 11:05:23.046045 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 11:05:23.049608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 11:05:23.052421 ==
2679 11:05:23.052524
2680 11:05:23.052591
2681 11:05:23.052652 TX Vref Scan disable
2682 11:05:23.056527 == TX Byte 0 ==
2683 11:05:23.059919 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2684 11:05:23.065983 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2685 11:05:23.066121 == TX Byte 1 ==
2686 11:05:23.069455 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2687 11:05:23.076274 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2688 11:05:23.076415
2689 11:05:23.076482 [DATLAT]
2690 11:05:23.076543 Freq=1200, CH0 RK0
2691 11:05:23.076602
2692 11:05:23.079032 DATLAT Default: 0xd
2693 11:05:23.082695 0, 0xFFFF, sum = 0
2694 11:05:23.082801 1, 0xFFFF, sum = 0
2695 11:05:23.086072 2, 0xFFFF, sum = 0
2696 11:05:23.086171 3, 0xFFFF, sum = 0
2697 11:05:23.089056 4, 0xFFFF, sum = 0
2698 11:05:23.089151 5, 0xFFFF, sum = 0
2699 11:05:23.092563 6, 0xFFFF, sum = 0
2700 11:05:23.092663 7, 0xFFFF, sum = 0
2701 11:05:23.095776 8, 0xFFFF, sum = 0
2702 11:05:23.095870 9, 0xFFFF, sum = 0
2703 11:05:23.099769 10, 0xFFFF, sum = 0
2704 11:05:23.099872 11, 0xFFFF, sum = 0
2705 11:05:23.102805 12, 0x0, sum = 1
2706 11:05:23.102899 13, 0x0, sum = 2
2707 11:05:23.105802 14, 0x0, sum = 3
2708 11:05:23.105910 15, 0x0, sum = 4
2709 11:05:23.109190 best_step = 13
2710 11:05:23.109285
2711 11:05:23.109351 ==
2712 11:05:23.112922 Dram Type= 6, Freq= 0, CH_0, rank 0
2713 11:05:23.115658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2714 11:05:23.115797 ==
2715 11:05:23.115864 RX Vref Scan: 1
2716 11:05:23.119096
2717 11:05:23.119188 Set Vref Range= 32 -> 127
2718 11:05:23.119255
2719 11:05:23.122316 RX Vref 32 -> 127, step: 1
2720 11:05:23.122409
2721 11:05:23.125805 RX Delay -21 -> 252, step: 4
2722 11:05:23.125903
2723 11:05:23.128821 Set Vref, RX VrefLevel [Byte0]: 32
2724 11:05:23.132716 [Byte1]: 32
2725 11:05:23.132830
2726 11:05:23.135548 Set Vref, RX VrefLevel [Byte0]: 33
2727 11:05:23.139395 [Byte1]: 33
2728 11:05:23.142748
2729 11:05:23.142852 Set Vref, RX VrefLevel [Byte0]: 34
2730 11:05:23.145898 [Byte1]: 34
2731 11:05:23.150794
2732 11:05:23.150913 Set Vref, RX VrefLevel [Byte0]: 35
2733 11:05:23.155110 [Byte1]: 35
2734 11:05:23.158430
2735 11:05:23.158543 Set Vref, RX VrefLevel [Byte0]: 36
2736 11:05:23.161739 [Byte1]: 36
2737 11:05:23.166691
2738 11:05:23.166818 Set Vref, RX VrefLevel [Byte0]: 37
2739 11:05:23.170059 [Byte1]: 37
2740 11:05:23.174315
2741 11:05:23.174439 Set Vref, RX VrefLevel [Byte0]: 38
2742 11:05:23.177633 [Byte1]: 38
2743 11:05:23.182452
2744 11:05:23.182581 Set Vref, RX VrefLevel [Byte0]: 39
2745 11:05:23.185689 [Byte1]: 39
2746 11:05:23.190656
2747 11:05:23.190783 Set Vref, RX VrefLevel [Byte0]: 40
2748 11:05:23.193613 [Byte1]: 40
2749 11:05:23.198808
2750 11:05:23.198935 Set Vref, RX VrefLevel [Byte0]: 41
2751 11:05:23.201884 [Byte1]: 41
2752 11:05:23.206770
2753 11:05:23.206901 Set Vref, RX VrefLevel [Byte0]: 42
2754 11:05:23.209509 [Byte1]: 42
2755 11:05:23.214352
2756 11:05:23.214476 Set Vref, RX VrefLevel [Byte0]: 43
2757 11:05:23.217146 [Byte1]: 43
2758 11:05:23.222302
2759 11:05:23.222433 Set Vref, RX VrefLevel [Byte0]: 44
2760 11:05:23.225473 [Byte1]: 44
2761 11:05:23.230433
2762 11:05:23.230570 Set Vref, RX VrefLevel [Byte0]: 45
2763 11:05:23.233114 [Byte1]: 45
2764 11:05:23.238328
2765 11:05:23.238542 Set Vref, RX VrefLevel [Byte0]: 46
2766 11:05:23.241968 [Byte1]: 46
2767 11:05:23.245556
2768 11:05:23.245662 Set Vref, RX VrefLevel [Byte0]: 47
2769 11:05:23.249090 [Byte1]: 47
2770 11:05:23.253963
2771 11:05:23.254087 Set Vref, RX VrefLevel [Byte0]: 48
2772 11:05:23.257083 [Byte1]: 48
2773 11:05:23.261535
2774 11:05:23.261654 Set Vref, RX VrefLevel [Byte0]: 49
2775 11:05:23.264763 [Byte1]: 49
2776 11:05:23.269943
2777 11:05:23.270075 Set Vref, RX VrefLevel [Byte0]: 50
2778 11:05:23.273704 [Byte1]: 50
2779 11:05:23.277822
2780 11:05:23.277950 Set Vref, RX VrefLevel [Byte0]: 51
2781 11:05:23.280634 [Byte1]: 51
2782 11:05:23.285562
2783 11:05:23.285688 Set Vref, RX VrefLevel [Byte0]: 52
2784 11:05:23.288601 [Byte1]: 52
2785 11:05:23.293786
2786 11:05:23.293915 Set Vref, RX VrefLevel [Byte0]: 53
2787 11:05:23.296570 [Byte1]: 53
2788 11:05:23.301263
2789 11:05:23.301386 Set Vref, RX VrefLevel [Byte0]: 54
2790 11:05:23.304362 [Byte1]: 54
2791 11:05:23.309880
2792 11:05:23.310012 Set Vref, RX VrefLevel [Byte0]: 55
2793 11:05:23.312462 [Byte1]: 55
2794 11:05:23.316873
2795 11:05:23.316998 Set Vref, RX VrefLevel [Byte0]: 56
2796 11:05:23.320504 [Byte1]: 56
2797 11:05:23.325035
2798 11:05:23.325162 Set Vref, RX VrefLevel [Byte0]: 57
2799 11:05:23.328739 [Byte1]: 57
2800 11:05:23.332938
2801 11:05:23.333064 Set Vref, RX VrefLevel [Byte0]: 58
2802 11:05:23.336584 [Byte1]: 58
2803 11:05:23.341276
2804 11:05:23.341400 Set Vref, RX VrefLevel [Byte0]: 59
2805 11:05:23.344734 [Byte1]: 59
2806 11:05:23.348757
2807 11:05:23.348872 Set Vref, RX VrefLevel [Byte0]: 60
2808 11:05:23.352245 [Byte1]: 60
2809 11:05:23.357769
2810 11:05:23.357901 Set Vref, RX VrefLevel [Byte0]: 61
2811 11:05:23.360330 [Byte1]: 61
2812 11:05:23.365322
2813 11:05:23.365447 Set Vref, RX VrefLevel [Byte0]: 62
2814 11:05:23.368516 [Byte1]: 62
2815 11:05:23.372495
2816 11:05:23.372608 Set Vref, RX VrefLevel [Byte0]: 63
2817 11:05:23.375970 [Byte1]: 63
2818 11:05:23.380518
2819 11:05:23.380644 Set Vref, RX VrefLevel [Byte0]: 64
2820 11:05:23.383957 [Byte1]: 64
2821 11:05:23.388765
2822 11:05:23.388893 Set Vref, RX VrefLevel [Byte0]: 65
2823 11:05:23.392172 [Byte1]: 65
2824 11:05:23.396713
2825 11:05:23.396838 Set Vref, RX VrefLevel [Byte0]: 66
2826 11:05:23.402932 [Byte1]: 66
2827 11:05:23.403069
2828 11:05:23.405954 Set Vref, RX VrefLevel [Byte0]: 67
2829 11:05:23.410428 [Byte1]: 67
2830 11:05:23.410553
2831 11:05:23.413358 Set Vref, RX VrefLevel [Byte0]: 68
2832 11:05:23.415996 [Byte1]: 68
2833 11:05:23.419879
2834 11:05:23.420004 Set Vref, RX VrefLevel [Byte0]: 69
2835 11:05:23.423587 [Byte1]: 69
2836 11:05:23.428554
2837 11:05:23.428913 Set Vref, RX VrefLevel [Byte0]: 70
2838 11:05:23.431468 [Byte1]: 70
2839 11:05:23.436243
2840 11:05:23.436363 Set Vref, RX VrefLevel [Byte0]: 71
2841 11:05:23.439242 [Byte1]: 71
2842 11:05:23.444095
2843 11:05:23.444218 Set Vref, RX VrefLevel [Byte0]: 72
2844 11:05:23.447074 [Byte1]: 72
2845 11:05:23.451883
2846 11:05:23.452004 Set Vref, RX VrefLevel [Byte0]: 73
2847 11:05:23.455579 [Byte1]: 73
2848 11:05:23.460409
2849 11:05:23.460536 Set Vref, RX VrefLevel [Byte0]: 74
2850 11:05:23.463805 [Byte1]: 74
2851 11:05:23.467527
2852 11:05:23.467641 Set Vref, RX VrefLevel [Byte0]: 75
2853 11:05:23.471192 [Byte1]: 75
2854 11:05:23.475412
2855 11:05:23.475532 Set Vref, RX VrefLevel [Byte0]: 76
2856 11:05:23.478691 [Byte1]: 76
2857 11:05:23.483622
2858 11:05:23.483759 Set Vref, RX VrefLevel [Byte0]: 77
2859 11:05:23.486745 [Byte1]: 77
2860 11:05:23.491198
2861 11:05:23.491354 Set Vref, RX VrefLevel [Byte0]: 78
2862 11:05:23.494707 [Byte1]: 78
2863 11:05:23.500728
2864 11:05:23.500905 Final RX Vref Byte 0 = 59 to rank0
2865 11:05:23.502974 Final RX Vref Byte 1 = 58 to rank0
2866 11:05:23.505979 Final RX Vref Byte 0 = 59 to rank1
2867 11:05:23.509168 Final RX Vref Byte 1 = 58 to rank1==
2868 11:05:23.512639 Dram Type= 6, Freq= 0, CH_0, rank 0
2869 11:05:23.519462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2870 11:05:23.519606 ==
2871 11:05:23.519702 DQS Delay:
2872 11:05:23.519783 DQS0 = 0, DQS1 = 0
2873 11:05:23.522966 DQM Delay:
2874 11:05:23.523106 DQM0 = 119, DQM1 = 107
2875 11:05:23.525887 DQ Delay:
2876 11:05:23.529230 DQ0 =118, DQ1 =120, DQ2 =116, DQ3 =114
2877 11:05:23.532782 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
2878 11:05:23.535932 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =102
2879 11:05:23.539395 DQ12 =112, DQ13 =112, DQ14 =122, DQ15 =114
2880 11:05:23.539512
2881 11:05:23.539580
2882 11:05:23.545975 [DQSOSCAuto] RK0, (LSB)MR18= 0xdf9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 405 ps
2883 11:05:23.549352 CH0 RK0: MR19=403, MR18=DF9
2884 11:05:23.555922 CH0_RK0: MR19=0x403, MR18=0xDF9, DQSOSC=405, MR23=63, INC=39, DEC=26
2885 11:05:23.556065
2886 11:05:23.559568 ----->DramcWriteLeveling(PI) begin...
2887 11:05:23.559666 ==
2888 11:05:23.562285 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 11:05:23.565826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 11:05:23.565957 ==
2891 11:05:23.569329 Write leveling (Byte 0): 31 => 31
2892 11:05:23.572607 Write leveling (Byte 1): 29 => 29
2893 11:05:23.575878 DramcWriteLeveling(PI) end<-----
2894 11:05:23.575999
2895 11:05:23.576067 ==
2896 11:05:23.579068 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 11:05:23.585774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 11:05:23.585918 ==
2899 11:05:23.585988 [Gating] SW mode calibration
2900 11:05:23.595638 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2901 11:05:23.599640 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2902 11:05:23.602580 0 15 0 | B1->B0 | 2322 3434 | 1 0 | (0 0) (0 0)
2903 11:05:23.609691 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
2904 11:05:23.612472 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 11:05:23.615963 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 11:05:23.622397 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 11:05:23.625636 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 11:05:23.629007 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 11:05:23.635817 0 15 28 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
2910 11:05:23.638776 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
2911 11:05:23.642360 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 11:05:23.648543 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 11:05:23.652066 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 11:05:23.655358 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 11:05:23.661916 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 11:05:23.665229 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 11:05:23.668946 1 0 28 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
2918 11:05:23.675591 1 1 0 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
2919 11:05:23.679149 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 11:05:23.682462 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 11:05:23.688704 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 11:05:23.692084 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 11:05:23.695025 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 11:05:23.702117 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 11:05:23.705159 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2926 11:05:23.708792 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2927 11:05:23.715472 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 11:05:23.718307 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 11:05:23.721510 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 11:05:23.728355 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 11:05:23.732307 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 11:05:23.734852 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 11:05:23.742030 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 11:05:23.744830 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 11:05:23.748167 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 11:05:23.754752 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 11:05:23.758096 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 11:05:23.762540 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 11:05:23.767870 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 11:05:23.771172 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2941 11:05:23.774504 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2942 11:05:23.777826 Total UI for P1: 0, mck2ui 16
2943 11:05:23.781502 best dqsien dly found for B0: ( 1, 3, 24)
2944 11:05:23.785114 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2945 11:05:23.791321 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 11:05:23.795115 Total UI for P1: 0, mck2ui 16
2947 11:05:23.798091 best dqsien dly found for B1: ( 1, 4, 0)
2948 11:05:23.801081 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2949 11:05:23.804366 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2950 11:05:23.804482
2951 11:05:23.807913 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2952 11:05:23.811517 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2953 11:05:23.814576 [Gating] SW calibration Done
2954 11:05:23.814685 ==
2955 11:05:23.819787 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 11:05:23.821195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 11:05:23.821287 ==
2958 11:05:23.824673 RX Vref Scan: 0
2959 11:05:23.824770
2960 11:05:23.827800 RX Vref 0 -> 0, step: 1
2961 11:05:23.827896
2962 11:05:23.827964 RX Delay -40 -> 252, step: 8
2963 11:05:23.834457 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2964 11:05:23.837782 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2965 11:05:23.841031 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2966 11:05:23.844100 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2967 11:05:23.847474 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2968 11:05:23.853979 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2969 11:05:23.857303 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2970 11:05:23.860679 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2971 11:05:23.864118 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
2972 11:05:23.867425 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2973 11:05:23.873937 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2974 11:05:23.877713 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2975 11:05:23.880461 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
2976 11:05:23.883930 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2977 11:05:23.890690 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2978 11:05:23.893476 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2979 11:05:23.893581 ==
2980 11:05:23.896806 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 11:05:23.900331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 11:05:23.900442 ==
2983 11:05:23.900510 DQS Delay:
2984 11:05:23.903597 DQS0 = 0, DQS1 = 0
2985 11:05:23.903697 DQM Delay:
2986 11:05:23.907497 DQM0 = 116, DQM1 = 109
2987 11:05:23.907602 DQ Delay:
2988 11:05:23.909958 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2989 11:05:23.913683 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2990 11:05:23.916636 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2991 11:05:23.923556 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =119
2992 11:05:23.923729
2993 11:05:23.923817
2994 11:05:23.923878 ==
2995 11:05:23.927115 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 11:05:23.930292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 11:05:23.930429 ==
2998 11:05:23.930497
2999 11:05:23.930558
3000 11:05:23.933611 TX Vref Scan disable
3001 11:05:23.933705 == TX Byte 0 ==
3002 11:05:23.940009 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3003 11:05:23.943413 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3004 11:05:23.943524 == TX Byte 1 ==
3005 11:05:23.949769 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3006 11:05:23.953056 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3007 11:05:23.953172 ==
3008 11:05:23.956481 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 11:05:23.959710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 11:05:23.959835 ==
3011 11:05:23.972925 TX Vref=22, minBit 1, minWin=25, winSum=413
3012 11:05:23.975558 TX Vref=24, minBit 0, minWin=26, winSum=420
3013 11:05:23.979229 TX Vref=26, minBit 2, minWin=26, winSum=425
3014 11:05:23.982925 TX Vref=28, minBit 4, minWin=26, winSum=427
3015 11:05:23.985936 TX Vref=30, minBit 4, minWin=26, winSum=429
3016 11:05:23.992176 TX Vref=32, minBit 13, minWin=25, winSum=424
3017 11:05:23.995628 [TxChooseVref] Worse bit 4, Min win 26, Win sum 429, Final Vref 30
3018 11:05:23.995790
3019 11:05:23.998912 Final TX Range 1 Vref 30
3020 11:05:23.999010
3021 11:05:23.999076 ==
3022 11:05:24.002114 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 11:05:24.005996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 11:05:24.008955 ==
3025 11:05:24.009063
3026 11:05:24.009130
3027 11:05:24.009190 TX Vref Scan disable
3028 11:05:24.012277 == TX Byte 0 ==
3029 11:05:24.015596 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3030 11:05:24.022373 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3031 11:05:24.022519 == TX Byte 1 ==
3032 11:05:24.025776 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3033 11:05:24.032227 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3034 11:05:24.032375
3035 11:05:24.032442 [DATLAT]
3036 11:05:24.032504 Freq=1200, CH0 RK1
3037 11:05:24.032564
3038 11:05:24.035979 DATLAT Default: 0xd
3039 11:05:24.036083 0, 0xFFFF, sum = 0
3040 11:05:24.038887 1, 0xFFFF, sum = 0
3041 11:05:24.042699 2, 0xFFFF, sum = 0
3042 11:05:24.042811 3, 0xFFFF, sum = 0
3043 11:05:24.045994 4, 0xFFFF, sum = 0
3044 11:05:24.046113 5, 0xFFFF, sum = 0
3045 11:05:24.048795 6, 0xFFFF, sum = 0
3046 11:05:24.048893 7, 0xFFFF, sum = 0
3047 11:05:24.052260 8, 0xFFFF, sum = 0
3048 11:05:24.052366 9, 0xFFFF, sum = 0
3049 11:05:24.055728 10, 0xFFFF, sum = 0
3050 11:05:24.055836 11, 0xFFFF, sum = 0
3051 11:05:24.059247 12, 0x0, sum = 1
3052 11:05:24.059357 13, 0x0, sum = 2
3053 11:05:24.062491 14, 0x0, sum = 3
3054 11:05:24.062595 15, 0x0, sum = 4
3055 11:05:24.065651 best_step = 13
3056 11:05:24.065752
3057 11:05:24.065818 ==
3058 11:05:24.069290 Dram Type= 6, Freq= 0, CH_0, rank 1
3059 11:05:24.072306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 11:05:24.072414 ==
3061 11:05:24.072483 RX Vref Scan: 0
3062 11:05:24.072545
3063 11:05:24.075895 RX Vref 0 -> 0, step: 1
3064 11:05:24.075992
3065 11:05:24.078595 RX Delay -21 -> 252, step: 4
3066 11:05:24.082064 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3067 11:05:24.088611 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3068 11:05:24.091875 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3069 11:05:24.095135 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3070 11:05:24.098804 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3071 11:05:24.102237 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3072 11:05:24.108724 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3073 11:05:24.111824 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3074 11:05:24.115360 iDelay=199, Bit 8, Center 100 (31 ~ 170) 140
3075 11:05:24.118285 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3076 11:05:24.121534 iDelay=199, Bit 10, Center 112 (43 ~ 182) 140
3077 11:05:24.128647 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3078 11:05:24.132086 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3079 11:05:24.134954 iDelay=199, Bit 13, Center 116 (51 ~ 182) 132
3080 11:05:24.138123 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3081 11:05:24.144943 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3082 11:05:24.145089 ==
3083 11:05:24.148710 Dram Type= 6, Freq= 0, CH_0, rank 1
3084 11:05:24.152002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 11:05:24.152121 ==
3086 11:05:24.152190 DQS Delay:
3087 11:05:24.154582 DQS0 = 0, DQS1 = 0
3088 11:05:24.154669 DQM Delay:
3089 11:05:24.157872 DQM0 = 116, DQM1 = 109
3090 11:05:24.157969 DQ Delay:
3091 11:05:24.161487 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3092 11:05:24.164480 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3093 11:05:24.167906 DQ8 =100, DQ9 =94, DQ10 =112, DQ11 =102
3094 11:05:24.171080 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =116
3095 11:05:24.171196
3096 11:05:24.174562
3097 11:05:24.181052 [DQSOSCAuto] RK1, (LSB)MR18= 0x8e3, (MSB)MR19= 0x403, tDQSOscB0 = 422 ps tDQSOscB1 = 406 ps
3098 11:05:24.185504 CH0 RK1: MR19=403, MR18=8E3
3099 11:05:24.191578 CH0_RK1: MR19=0x403, MR18=0x8E3, DQSOSC=406, MR23=63, INC=39, DEC=26
3100 11:05:24.191771 [RxdqsGatingPostProcess] freq 1200
3101 11:05:24.197654 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3102 11:05:24.200708 best DQS0 dly(2T, 0.5T) = (0, 11)
3103 11:05:24.204808 best DQS1 dly(2T, 0.5T) = (0, 12)
3104 11:05:24.207416 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3105 11:05:24.211189 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3106 11:05:24.213980 best DQS0 dly(2T, 0.5T) = (0, 11)
3107 11:05:24.217417 best DQS1 dly(2T, 0.5T) = (0, 12)
3108 11:05:24.220714 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3109 11:05:24.223921 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3110 11:05:24.227137 Pre-setting of DQS Precalculation
3111 11:05:24.231204 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3112 11:05:24.231343 ==
3113 11:05:24.234153 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 11:05:24.237123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 11:05:24.240600 ==
3116 11:05:24.244280 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3117 11:05:24.250448 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3118 11:05:24.258779 [CA 0] Center 37 (7~68) winsize 62
3119 11:05:24.262547 [CA 1] Center 37 (7~68) winsize 62
3120 11:05:24.265539 [CA 2] Center 34 (4~64) winsize 61
3121 11:05:24.269165 [CA 3] Center 33 (3~64) winsize 62
3122 11:05:24.271783 [CA 4] Center 34 (4~64) winsize 61
3123 11:05:24.275087 [CA 5] Center 33 (3~64) winsize 62
3124 11:05:24.275219
3125 11:05:24.278404 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3126 11:05:24.278514
3127 11:05:24.282506 [CATrainingPosCal] consider 1 rank data
3128 11:05:24.285538 u2DelayCellTimex100 = 270/100 ps
3129 11:05:24.288368 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3130 11:05:24.296117 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3131 11:05:24.298693 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3132 11:05:24.301834 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3133 11:05:24.304865 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3134 11:05:24.309274 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3135 11:05:24.309406
3136 11:05:24.311599 CA PerBit enable=1, Macro0, CA PI delay=33
3137 11:05:24.311734
3138 11:05:24.314899 [CBTSetCACLKResult] CA Dly = 33
3139 11:05:24.314992 CS Dly: 6 (0~37)
3140 11:05:24.318638 ==
3141 11:05:24.318740 Dram Type= 6, Freq= 0, CH_1, rank 1
3142 11:05:24.325359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 11:05:24.325499 ==
3144 11:05:24.328411 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3145 11:05:24.335139 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3146 11:05:24.344575 [CA 0] Center 37 (7~68) winsize 62
3147 11:05:24.347879 [CA 1] Center 38 (8~68) winsize 61
3148 11:05:24.351196 [CA 2] Center 34 (4~65) winsize 62
3149 11:05:24.354196 [CA 3] Center 33 (3~64) winsize 62
3150 11:05:24.357951 [CA 4] Center 34 (4~65) winsize 62
3151 11:05:24.360846 [CA 5] Center 33 (3~64) winsize 62
3152 11:05:24.360953
3153 11:05:24.364048 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3154 11:05:24.364146
3155 11:05:24.367496 [CATrainingPosCal] consider 2 rank data
3156 11:05:24.370721 u2DelayCellTimex100 = 270/100 ps
3157 11:05:24.374835 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3158 11:05:24.378203 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3159 11:05:24.384294 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3160 11:05:24.387513 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3161 11:05:24.390798 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3162 11:05:24.394174 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3163 11:05:24.394286
3164 11:05:24.397769 CA PerBit enable=1, Macro0, CA PI delay=33
3165 11:05:24.397871
3166 11:05:24.400966 [CBTSetCACLKResult] CA Dly = 33
3167 11:05:24.401062 CS Dly: 7 (0~40)
3168 11:05:24.401129
3169 11:05:24.404183 ----->DramcWriteLeveling(PI) begin...
3170 11:05:24.407651 ==
3171 11:05:24.410725 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 11:05:24.414017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 11:05:24.414126 ==
3174 11:05:24.417855 Write leveling (Byte 0): 24 => 24
3175 11:05:24.420622 Write leveling (Byte 1): 29 => 29
3176 11:05:24.423820 DramcWriteLeveling(PI) end<-----
3177 11:05:24.423925
3178 11:05:24.423992 ==
3179 11:05:24.427514 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 11:05:24.430655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 11:05:24.430762 ==
3182 11:05:24.433987 [Gating] SW mode calibration
3183 11:05:24.441086 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3184 11:05:24.447072 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3185 11:05:24.450735 0 15 0 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
3186 11:05:24.453831 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 11:05:24.460211 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 11:05:24.463404 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 11:05:24.467261 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 11:05:24.474072 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 11:05:24.476983 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3192 11:05:24.480152 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3193 11:05:24.486725 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 11:05:24.490289 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 11:05:24.493878 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 11:05:24.499914 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 11:05:24.503589 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 11:05:24.506566 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 11:05:24.513298 1 0 24 | B1->B0 | 2626 3636 | 0 0 | (0 0) (0 0)
3200 11:05:24.516598 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3201 11:05:24.520047 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 11:05:24.526568 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 11:05:24.529811 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 11:05:24.533197 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 11:05:24.536530 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 11:05:24.542799 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 11:05:24.546772 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3208 11:05:24.549856 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3209 11:05:24.556796 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 11:05:24.559936 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 11:05:24.566178 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 11:05:24.569470 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 11:05:24.572545 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 11:05:24.575842 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 11:05:24.582369 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 11:05:24.585692 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 11:05:24.589499 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 11:05:24.596256 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 11:05:24.599304 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 11:05:24.602531 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 11:05:24.609669 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 11:05:24.612726 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 11:05:24.615773 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3224 11:05:24.622861 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3225 11:05:24.625707 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 11:05:24.629865 Total UI for P1: 0, mck2ui 16
3227 11:05:24.632954 best dqsien dly found for B0: ( 1, 3, 26)
3228 11:05:24.635889 Total UI for P1: 0, mck2ui 16
3229 11:05:24.638988 best dqsien dly found for B1: ( 1, 3, 26)
3230 11:05:24.642092 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3231 11:05:24.645799 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3232 11:05:24.645951
3233 11:05:24.648802 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3234 11:05:24.651974 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3235 11:05:24.655437 [Gating] SW calibration Done
3236 11:05:24.655572 ==
3237 11:05:24.659114 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 11:05:24.665324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 11:05:24.665460 ==
3240 11:05:24.665531 RX Vref Scan: 0
3241 11:05:24.665593
3242 11:05:24.668801 RX Vref 0 -> 0, step: 1
3243 11:05:24.668898
3244 11:05:24.671830 RX Delay -40 -> 252, step: 8
3245 11:05:24.675291 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3246 11:05:24.678424 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3247 11:05:24.682020 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3248 11:05:24.688628 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3249 11:05:24.691745 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3250 11:05:24.694513 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3251 11:05:24.697936 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3252 11:05:24.702175 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3253 11:05:24.708166 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3254 11:05:24.711720 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3255 11:05:24.714731 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3256 11:05:24.718041 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3257 11:05:24.721312 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3258 11:05:24.727690 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3259 11:05:24.731757 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3260 11:05:24.734656 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3261 11:05:24.734808 ==
3262 11:05:24.738052 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 11:05:24.741294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 11:05:24.741436 ==
3265 11:05:24.744961 DQS Delay:
3266 11:05:24.745092 DQS0 = 0, DQS1 = 0
3267 11:05:24.747510 DQM Delay:
3268 11:05:24.747626 DQM0 = 118, DQM1 = 109
3269 11:05:24.750850 DQ Delay:
3270 11:05:24.754109 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =115
3271 11:05:24.757450 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3272 11:05:24.760825 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3273 11:05:24.764674 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3274 11:05:24.764798
3275 11:05:24.764867
3276 11:05:24.764928 ==
3277 11:05:24.767330 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 11:05:24.770573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 11:05:24.770678 ==
3280 11:05:24.770748
3281 11:05:24.770809
3282 11:05:24.774038 TX Vref Scan disable
3283 11:05:24.777421 == TX Byte 0 ==
3284 11:05:24.780714 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3285 11:05:24.783599 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3286 11:05:24.787157 == TX Byte 1 ==
3287 11:05:24.790608 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3288 11:05:24.793493 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3289 11:05:24.793606 ==
3290 11:05:24.797102 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 11:05:24.803958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 11:05:24.804100 ==
3293 11:05:24.814757 TX Vref=22, minBit 8, minWin=25, winSum=413
3294 11:05:24.817446 TX Vref=24, minBit 8, minWin=25, winSum=424
3295 11:05:24.820952 TX Vref=26, minBit 8, minWin=25, winSum=427
3296 11:05:24.823831 TX Vref=28, minBit 9, minWin=26, winSum=434
3297 11:05:24.827143 TX Vref=30, minBit 9, minWin=26, winSum=430
3298 11:05:24.833654 TX Vref=32, minBit 11, minWin=25, winSum=427
3299 11:05:24.837756 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 28
3300 11:05:24.837887
3301 11:05:24.841087 Final TX Range 1 Vref 28
3302 11:05:24.841186
3303 11:05:24.841253 ==
3304 11:05:24.843531 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 11:05:24.850593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 11:05:24.850732 ==
3307 11:05:24.850802
3308 11:05:24.850864
3309 11:05:24.850921 TX Vref Scan disable
3310 11:05:24.854219 == TX Byte 0 ==
3311 11:05:24.857241 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3312 11:05:24.864279 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3313 11:05:24.864458 == TX Byte 1 ==
3314 11:05:24.867787 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3315 11:05:24.874623 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3316 11:05:24.874772
3317 11:05:24.874869 [DATLAT]
3318 11:05:24.874961 Freq=1200, CH1 RK0
3319 11:05:24.875069
3320 11:05:24.877622 DATLAT Default: 0xd
3321 11:05:24.877715 0, 0xFFFF, sum = 0
3322 11:05:24.880444 1, 0xFFFF, sum = 0
3323 11:05:24.883889 2, 0xFFFF, sum = 0
3324 11:05:24.884004 3, 0xFFFF, sum = 0
3325 11:05:24.887311 4, 0xFFFF, sum = 0
3326 11:05:24.887441 5, 0xFFFF, sum = 0
3327 11:05:24.890391 6, 0xFFFF, sum = 0
3328 11:05:24.890486 7, 0xFFFF, sum = 0
3329 11:05:24.894242 8, 0xFFFF, sum = 0
3330 11:05:24.894351 9, 0xFFFF, sum = 0
3331 11:05:24.897667 10, 0xFFFF, sum = 0
3332 11:05:24.897768 11, 0xFFFF, sum = 0
3333 11:05:24.900606 12, 0x0, sum = 1
3334 11:05:24.900702 13, 0x0, sum = 2
3335 11:05:24.903918 14, 0x0, sum = 3
3336 11:05:24.904019 15, 0x0, sum = 4
3337 11:05:24.907234 best_step = 13
3338 11:05:24.907340
3339 11:05:24.907407 ==
3340 11:05:24.910599 Dram Type= 6, Freq= 0, CH_1, rank 0
3341 11:05:24.913604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3342 11:05:24.913736 ==
3343 11:05:24.913831 RX Vref Scan: 1
3344 11:05:24.913923
3345 11:05:24.916903 Set Vref Range= 32 -> 127
3346 11:05:24.916992
3347 11:05:24.920765 RX Vref 32 -> 127, step: 1
3348 11:05:24.920862
3349 11:05:24.924186 RX Delay -21 -> 252, step: 4
3350 11:05:24.924283
3351 11:05:24.927481 Set Vref, RX VrefLevel [Byte0]: 32
3352 11:05:24.930686 [Byte1]: 32
3353 11:05:24.930791
3354 11:05:24.933938 Set Vref, RX VrefLevel [Byte0]: 33
3355 11:05:24.937387 [Byte1]: 33
3356 11:05:24.940700
3357 11:05:24.940816 Set Vref, RX VrefLevel [Byte0]: 34
3358 11:05:24.944055 [Byte1]: 34
3359 11:05:24.948975
3360 11:05:24.949105 Set Vref, RX VrefLevel [Byte0]: 35
3361 11:05:24.951971 [Byte1]: 35
3362 11:05:24.956889
3363 11:05:24.957019 Set Vref, RX VrefLevel [Byte0]: 36
3364 11:05:24.959774 [Byte1]: 36
3365 11:05:24.965060
3366 11:05:24.965184 Set Vref, RX VrefLevel [Byte0]: 37
3367 11:05:24.968331 [Byte1]: 37
3368 11:05:24.972808
3369 11:05:24.972932 Set Vref, RX VrefLevel [Byte0]: 38
3370 11:05:24.975481 [Byte1]: 38
3371 11:05:24.980954
3372 11:05:24.981083 Set Vref, RX VrefLevel [Byte0]: 39
3373 11:05:24.984176 [Byte1]: 39
3374 11:05:24.988208
3375 11:05:24.988328 Set Vref, RX VrefLevel [Byte0]: 40
3376 11:05:24.991394 [Byte1]: 40
3377 11:05:24.996128
3378 11:05:24.996258 Set Vref, RX VrefLevel [Byte0]: 41
3379 11:05:24.999660 [Byte1]: 41
3380 11:05:25.003824
3381 11:05:25.003943 Set Vref, RX VrefLevel [Byte0]: 42
3382 11:05:25.007592 [Byte1]: 42
3383 11:05:25.012062
3384 11:05:25.012191 Set Vref, RX VrefLevel [Byte0]: 43
3385 11:05:25.015376 [Byte1]: 43
3386 11:05:25.019737
3387 11:05:25.019859 Set Vref, RX VrefLevel [Byte0]: 44
3388 11:05:25.023301 [Byte1]: 44
3389 11:05:25.027747
3390 11:05:25.027873 Set Vref, RX VrefLevel [Byte0]: 45
3391 11:05:25.031024 [Byte1]: 45
3392 11:05:25.036021
3393 11:05:25.036163 Set Vref, RX VrefLevel [Byte0]: 46
3394 11:05:25.039554 [Byte1]: 46
3395 11:05:25.043317
3396 11:05:25.043438 Set Vref, RX VrefLevel [Byte0]: 47
3397 11:05:25.046923 [Byte1]: 47
3398 11:05:25.052231
3399 11:05:25.052362 Set Vref, RX VrefLevel [Byte0]: 48
3400 11:05:25.054607 [Byte1]: 48
3401 11:05:25.059293
3402 11:05:25.059420 Set Vref, RX VrefLevel [Byte0]: 49
3403 11:05:25.062998 [Byte1]: 49
3404 11:05:25.067339
3405 11:05:25.067460 Set Vref, RX VrefLevel [Byte0]: 50
3406 11:05:25.070646 [Byte1]: 50
3407 11:05:25.075252
3408 11:05:25.075382 Set Vref, RX VrefLevel [Byte0]: 51
3409 11:05:25.078567 [Byte1]: 51
3410 11:05:25.083801
3411 11:05:25.083927 Set Vref, RX VrefLevel [Byte0]: 52
3412 11:05:25.086542 [Byte1]: 52
3413 11:05:25.091905
3414 11:05:25.092038 Set Vref, RX VrefLevel [Byte0]: 53
3415 11:05:25.095410 [Byte1]: 53
3416 11:05:25.099126
3417 11:05:25.099237 Set Vref, RX VrefLevel [Byte0]: 54
3418 11:05:25.102169 [Byte1]: 54
3419 11:05:25.106792
3420 11:05:25.106925 Set Vref, RX VrefLevel [Byte0]: 55
3421 11:05:25.110048 [Byte1]: 55
3422 11:05:25.114837
3423 11:05:25.114971 Set Vref, RX VrefLevel [Byte0]: 56
3424 11:05:25.118792 [Byte1]: 56
3425 11:05:25.122990
3426 11:05:25.123117 Set Vref, RX VrefLevel [Byte0]: 57
3427 11:05:25.126700 [Byte1]: 57
3428 11:05:25.130820
3429 11:05:25.130946 Set Vref, RX VrefLevel [Byte0]: 58
3430 11:05:25.134101 [Byte1]: 58
3431 11:05:25.138625
3432 11:05:25.138754 Set Vref, RX VrefLevel [Byte0]: 59
3433 11:05:25.142033 [Byte1]: 59
3434 11:05:25.146411
3435 11:05:25.146536 Set Vref, RX VrefLevel [Byte0]: 60
3436 11:05:25.150363 [Byte1]: 60
3437 11:05:25.154679
3438 11:05:25.154802 Set Vref, RX VrefLevel [Byte0]: 61
3439 11:05:25.157831 [Byte1]: 61
3440 11:05:25.162182
3441 11:05:25.162309 Set Vref, RX VrefLevel [Byte0]: 62
3442 11:05:25.165582 [Byte1]: 62
3443 11:05:25.170290
3444 11:05:25.170416 Set Vref, RX VrefLevel [Byte0]: 63
3445 11:05:25.174051 [Byte1]: 63
3446 11:05:25.177922
3447 11:05:25.178041 Set Vref, RX VrefLevel [Byte0]: 64
3448 11:05:25.181910 [Byte1]: 64
3449 11:05:25.186522
3450 11:05:25.186651 Set Vref, RX VrefLevel [Byte0]: 65
3451 11:05:25.189150 [Byte1]: 65
3452 11:05:25.194196
3453 11:05:25.194320 Set Vref, RX VrefLevel [Byte0]: 66
3454 11:05:25.197718 [Byte1]: 66
3455 11:05:25.202500
3456 11:05:25.202616 Set Vref, RX VrefLevel [Byte0]: 67
3457 11:05:25.205093 [Byte1]: 67
3458 11:05:25.210502
3459 11:05:25.210627 Set Vref, RX VrefLevel [Byte0]: 68
3460 11:05:25.216031 [Byte1]: 68
3461 11:05:25.216172
3462 11:05:25.219578 Set Vref, RX VrefLevel [Byte0]: 69
3463 11:05:25.223202 [Byte1]: 69
3464 11:05:25.223336
3465 11:05:25.226064 Set Vref, RX VrefLevel [Byte0]: 70
3466 11:05:25.229597 [Byte1]: 70
3467 11:05:25.234990
3468 11:05:25.235134 Final RX Vref Byte 0 = 47 to rank0
3469 11:05:25.236855 Final RX Vref Byte 1 = 52 to rank0
3470 11:05:25.240496 Final RX Vref Byte 0 = 47 to rank1
3471 11:05:25.243220 Final RX Vref Byte 1 = 52 to rank1==
3472 11:05:25.247023 Dram Type= 6, Freq= 0, CH_1, rank 0
3473 11:05:25.253101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3474 11:05:25.253231 ==
3475 11:05:25.253298 DQS Delay:
3476 11:05:25.257089 DQS0 = 0, DQS1 = 0
3477 11:05:25.257188 DQM Delay:
3478 11:05:25.260257 DQM0 = 115, DQM1 = 110
3479 11:05:25.260351 DQ Delay:
3480 11:05:25.263317 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3481 11:05:25.266618 DQ4 =112, DQ5 =126, DQ6 =126, DQ7 =114
3482 11:05:25.270509 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =100
3483 11:05:25.273101 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =118
3484 11:05:25.273211
3485 11:05:25.273277
3486 11:05:25.282753 [DQSOSCAuto] RK0, (LSB)MR18= 0xf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3487 11:05:25.282896 CH1 RK0: MR19=403, MR18=F4
3488 11:05:25.289605 CH1_RK0: MR19=0x403, MR18=0xF4, DQSOSC=410, MR23=63, INC=39, DEC=26
3489 11:05:25.289749
3490 11:05:25.293297 ----->DramcWriteLeveling(PI) begin...
3491 11:05:25.293404 ==
3492 11:05:25.296366 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 11:05:25.302626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 11:05:25.302771 ==
3495 11:05:25.305903 Write leveling (Byte 0): 23 => 23
3496 11:05:25.306000 Write leveling (Byte 1): 26 => 26
3497 11:05:25.309524 DramcWriteLeveling(PI) end<-----
3498 11:05:25.309629
3499 11:05:25.313041 ==
3500 11:05:25.313139 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 11:05:25.319143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3502 11:05:25.319268 ==
3503 11:05:25.323026 [Gating] SW mode calibration
3504 11:05:25.329502 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3505 11:05:25.332729 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3506 11:05:25.339586 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3507 11:05:25.342241 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 11:05:25.346147 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 11:05:25.352211 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 11:05:25.355411 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 11:05:25.359651 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 11:05:25.365813 0 15 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3513 11:05:25.369068 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 0)
3514 11:05:25.372207 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 11:05:25.378728 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 11:05:25.382385 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 11:05:25.385257 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 11:05:25.391774 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 11:05:25.395509 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 11:05:25.398450 1 0 24 | B1->B0 | 3d3d 2727 | 0 0 | (0 0) (0 0)
3521 11:05:25.405328 1 0 28 | B1->B0 | 4545 4444 | 0 1 | (0 0) (1 1)
3522 11:05:25.408658 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 11:05:25.411921 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 11:05:25.418317 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 11:05:25.421654 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 11:05:25.424659 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 11:05:25.431219 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 11:05:25.434644 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3529 11:05:25.438463 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3530 11:05:25.444507 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 11:05:25.448169 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 11:05:25.451420 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 11:05:25.457740 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 11:05:25.461785 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 11:05:25.464483 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 11:05:25.471410 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 11:05:25.473966 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 11:05:25.478105 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 11:05:25.484153 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 11:05:25.487390 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 11:05:25.491104 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 11:05:25.497261 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 11:05:25.500954 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 11:05:25.503866 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3545 11:05:25.510792 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3546 11:05:25.510941 Total UI for P1: 0, mck2ui 16
3547 11:05:25.516979 best dqsien dly found for B1: ( 1, 3, 24)
3548 11:05:25.520591 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 11:05:25.524157 Total UI for P1: 0, mck2ui 16
3550 11:05:25.526584 best dqsien dly found for B0: ( 1, 3, 26)
3551 11:05:25.530022 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3552 11:05:25.533530 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3553 11:05:25.533714
3554 11:05:25.536600 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3555 11:05:25.540179 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3556 11:05:25.543008 [Gating] SW calibration Done
3557 11:05:25.543113 ==
3558 11:05:25.546323 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 11:05:25.552912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 11:05:25.553044 ==
3561 11:05:25.553140 RX Vref Scan: 0
3562 11:05:25.553223
3563 11:05:25.556798 RX Vref 0 -> 0, step: 1
3564 11:05:25.556898
3565 11:05:25.560607 RX Delay -40 -> 252, step: 8
3566 11:05:25.563234 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3567 11:05:25.566193 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3568 11:05:25.569929 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3569 11:05:25.576420 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3570 11:05:25.579348 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3571 11:05:25.583889 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3572 11:05:25.585854 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3573 11:05:25.589286 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3574 11:05:25.596468 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3575 11:05:25.599153 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3576 11:05:25.602754 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3577 11:05:25.605696 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3578 11:05:25.609105 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3579 11:05:25.616345 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3580 11:05:25.619077 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3581 11:05:25.621968 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3582 11:05:25.622079 ==
3583 11:05:25.625384 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 11:05:25.629520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 11:05:25.632098 ==
3586 11:05:25.632207 DQS Delay:
3587 11:05:25.632296 DQS0 = 0, DQS1 = 0
3588 11:05:25.635417 DQM Delay:
3589 11:05:25.635542 DQM0 = 116, DQM1 = 110
3590 11:05:25.638848 DQ Delay:
3591 11:05:25.641927 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =111
3592 11:05:25.645257 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3593 11:05:25.648654 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3594 11:05:25.651821 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3595 11:05:25.651935
3596 11:05:25.652026
3597 11:05:25.652108 ==
3598 11:05:25.654974 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 11:05:25.658356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 11:05:25.658489 ==
3601 11:05:25.661937
3602 11:05:25.662073
3603 11:05:25.662175 TX Vref Scan disable
3604 11:05:25.665213 == TX Byte 0 ==
3605 11:05:25.668252 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3606 11:05:25.671559 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3607 11:05:25.675043 == TX Byte 1 ==
3608 11:05:25.678397 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3609 11:05:25.681276 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3610 11:05:25.681388 ==
3611 11:05:25.685055 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 11:05:25.691209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 11:05:25.691375 ==
3614 11:05:25.702100 TX Vref=22, minBit 1, minWin=26, winSum=427
3615 11:05:25.706174 TX Vref=24, minBit 3, minWin=26, winSum=432
3616 11:05:25.708735 TX Vref=26, minBit 13, minWin=26, winSum=437
3617 11:05:25.712558 TX Vref=28, minBit 9, minWin=26, winSum=439
3618 11:05:25.715393 TX Vref=30, minBit 9, minWin=26, winSum=437
3619 11:05:25.721743 TX Vref=32, minBit 9, minWin=25, winSum=432
3620 11:05:25.725453 [TxChooseVref] Worse bit 9, Min win 26, Win sum 439, Final Vref 28
3621 11:05:25.725576
3622 11:05:25.728766 Final TX Range 1 Vref 28
3623 11:05:25.728880
3624 11:05:25.728947 ==
3625 11:05:25.731940 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 11:05:25.735616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 11:05:25.738860 ==
3628 11:05:25.738977
3629 11:05:25.739044
3630 11:05:25.739105 TX Vref Scan disable
3631 11:05:25.741942 == TX Byte 0 ==
3632 11:05:25.745257 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3633 11:05:25.751901 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3634 11:05:25.752033 == TX Byte 1 ==
3635 11:05:25.754955 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3636 11:05:25.761960 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3637 11:05:25.762095
3638 11:05:25.762163 [DATLAT]
3639 11:05:25.762225 Freq=1200, CH1 RK1
3640 11:05:25.762284
3641 11:05:25.765072 DATLAT Default: 0xd
3642 11:05:25.768487 0, 0xFFFF, sum = 0
3643 11:05:25.768604 1, 0xFFFF, sum = 0
3644 11:05:25.771701 2, 0xFFFF, sum = 0
3645 11:05:25.771819 3, 0xFFFF, sum = 0
3646 11:05:25.775158 4, 0xFFFF, sum = 0
3647 11:05:25.775261 5, 0xFFFF, sum = 0
3648 11:05:25.778319 6, 0xFFFF, sum = 0
3649 11:05:25.778417 7, 0xFFFF, sum = 0
3650 11:05:25.781404 8, 0xFFFF, sum = 0
3651 11:05:25.781503 9, 0xFFFF, sum = 0
3652 11:05:25.784516 10, 0xFFFF, sum = 0
3653 11:05:25.784613 11, 0xFFFF, sum = 0
3654 11:05:25.787953 12, 0x0, sum = 1
3655 11:05:25.788050 13, 0x0, sum = 2
3656 11:05:25.791097 14, 0x0, sum = 3
3657 11:05:25.791225 15, 0x0, sum = 4
3658 11:05:25.794304 best_step = 13
3659 11:05:25.794422
3660 11:05:25.794515 ==
3661 11:05:25.798787 Dram Type= 6, Freq= 0, CH_1, rank 1
3662 11:05:25.801984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3663 11:05:25.802114 ==
3664 11:05:25.804628 RX Vref Scan: 0
3665 11:05:25.804742
3666 11:05:25.804835 RX Vref 0 -> 0, step: 1
3667 11:05:25.804924
3668 11:05:25.807754 RX Delay -21 -> 252, step: 4
3669 11:05:25.814517 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3670 11:05:25.817829 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3671 11:05:25.820991 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3672 11:05:25.824603 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3673 11:05:25.830971 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3674 11:05:25.834144 iDelay=199, Bit 5, Center 126 (63 ~ 190) 128
3675 11:05:25.837081 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3676 11:05:25.840379 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3677 11:05:25.844138 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3678 11:05:25.847440 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3679 11:05:25.854040 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3680 11:05:25.856849 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3681 11:05:25.860291 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3682 11:05:25.863448 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3683 11:05:25.870308 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3684 11:05:25.873707 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3685 11:05:25.873852 ==
3686 11:05:25.877190 Dram Type= 6, Freq= 0, CH_1, rank 1
3687 11:05:25.880138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3688 11:05:25.880281 ==
3689 11:05:25.883479 DQS Delay:
3690 11:05:25.883604 DQS0 = 0, DQS1 = 0
3691 11:05:25.883713 DQM Delay:
3692 11:05:25.887038 DQM0 = 117, DQM1 = 109
3693 11:05:25.887156 DQ Delay:
3694 11:05:25.890417 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3695 11:05:25.893702 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =116
3696 11:05:25.899899 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3697 11:05:25.903900 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =118
3698 11:05:25.904055
3699 11:05:25.904158
3700 11:05:25.909629 [DQSOSCAuto] RK1, (LSB)MR18= 0xf4f0, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
3701 11:05:25.913263 CH1 RK1: MR19=303, MR18=F4F0
3702 11:05:25.919921 CH1_RK1: MR19=0x303, MR18=0xF4F0, DQSOSC=415, MR23=63, INC=38, DEC=25
3703 11:05:25.923204 [RxdqsGatingPostProcess] freq 1200
3704 11:05:25.929859 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3705 11:05:25.930029 best DQS0 dly(2T, 0.5T) = (0, 11)
3706 11:05:25.933021 best DQS1 dly(2T, 0.5T) = (0, 11)
3707 11:05:25.936096 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3708 11:05:25.939663 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3709 11:05:25.942589 best DQS0 dly(2T, 0.5T) = (0, 11)
3710 11:05:25.945840 best DQS1 dly(2T, 0.5T) = (0, 11)
3711 11:05:25.949116 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3712 11:05:25.952895 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3713 11:05:25.956139 Pre-setting of DQS Precalculation
3714 11:05:25.962796 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3715 11:05:25.969499 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3716 11:05:25.976338 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3717 11:05:25.976522
3718 11:05:25.976630
3719 11:05:25.979609 [Calibration Summary] 2400 Mbps
3720 11:05:25.979773 CH 0, Rank 0
3721 11:05:25.982196 SW Impedance : PASS
3722 11:05:25.985324 DUTY Scan : NO K
3723 11:05:25.985452 ZQ Calibration : PASS
3724 11:05:25.988824 Jitter Meter : NO K
3725 11:05:25.991922 CBT Training : PASS
3726 11:05:25.992052 Write leveling : PASS
3727 11:05:25.995421 RX DQS gating : PASS
3728 11:05:25.998458 RX DQ/DQS(RDDQC) : PASS
3729 11:05:25.998584 TX DQ/DQS : PASS
3730 11:05:26.001893 RX DATLAT : PASS
3731 11:05:26.005192 RX DQ/DQS(Engine): PASS
3732 11:05:26.005326 TX OE : NO K
3733 11:05:26.005427 All Pass.
3734 11:05:26.008781
3735 11:05:26.008955 CH 0, Rank 1
3736 11:05:26.011520 SW Impedance : PASS
3737 11:05:26.011635 DUTY Scan : NO K
3738 11:05:26.015379 ZQ Calibration : PASS
3739 11:05:26.018605 Jitter Meter : NO K
3740 11:05:26.018736 CBT Training : PASS
3741 11:05:26.021698 Write leveling : PASS
3742 11:05:26.021814 RX DQS gating : PASS
3743 11:05:26.025301 RX DQ/DQS(RDDQC) : PASS
3744 11:05:26.027956 TX DQ/DQS : PASS
3745 11:05:26.028085 RX DATLAT : PASS
3746 11:05:26.031725 RX DQ/DQS(Engine): PASS
3747 11:05:26.035158 TX OE : NO K
3748 11:05:26.035278 All Pass.
3749 11:05:26.035344
3750 11:05:26.035404 CH 1, Rank 0
3751 11:05:26.038313 SW Impedance : PASS
3752 11:05:26.041401 DUTY Scan : NO K
3753 11:05:26.041501 ZQ Calibration : PASS
3754 11:05:26.044730 Jitter Meter : NO K
3755 11:05:26.047991 CBT Training : PASS
3756 11:05:26.048091 Write leveling : PASS
3757 11:05:26.051819 RX DQS gating : PASS
3758 11:05:26.054376 RX DQ/DQS(RDDQC) : PASS
3759 11:05:26.054476 TX DQ/DQS : PASS
3760 11:05:26.058403 RX DATLAT : PASS
3761 11:05:26.061218 RX DQ/DQS(Engine): PASS
3762 11:05:26.061319 TX OE : NO K
3763 11:05:26.064574 All Pass.
3764 11:05:26.064669
3765 11:05:26.064733 CH 1, Rank 1
3766 11:05:26.068047 SW Impedance : PASS
3767 11:05:26.068138 DUTY Scan : NO K
3768 11:05:26.071254 ZQ Calibration : PASS
3769 11:05:26.074052 Jitter Meter : NO K
3770 11:05:26.074150 CBT Training : PASS
3771 11:05:26.077336 Write leveling : PASS
3772 11:05:26.080999 RX DQS gating : PASS
3773 11:05:26.081111 RX DQ/DQS(RDDQC) : PASS
3774 11:05:26.084436 TX DQ/DQS : PASS
3775 11:05:26.087640 RX DATLAT : PASS
3776 11:05:26.087758 RX DQ/DQS(Engine): PASS
3777 11:05:26.090801 TX OE : NO K
3778 11:05:26.090896 All Pass.
3779 11:05:26.090964
3780 11:05:26.094441 DramC Write-DBI off
3781 11:05:26.097287 PER_BANK_REFRESH: Hybrid Mode
3782 11:05:26.097389 TX_TRACKING: ON
3783 11:05:26.107333 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3784 11:05:26.111060 [FAST_K] Save calibration result to emmc
3785 11:05:26.113783 dramc_set_vcore_voltage set vcore to 650000
3786 11:05:26.117086 Read voltage for 600, 5
3787 11:05:26.117228 Vio18 = 0
3788 11:05:26.117326 Vcore = 650000
3789 11:05:26.120661 Vdram = 0
3790 11:05:26.120781 Vddq = 0
3791 11:05:26.120874 Vmddr = 0
3792 11:05:26.127248 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3793 11:05:26.130150 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3794 11:05:26.133684 MEM_TYPE=3, freq_sel=19
3795 11:05:26.136921 sv_algorithm_assistance_LP4_1600
3796 11:05:26.140076 ============ PULL DRAM RESETB DOWN ============
3797 11:05:26.143643 ========== PULL DRAM RESETB DOWN end =========
3798 11:05:26.150159 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3799 11:05:26.153317 ===================================
3800 11:05:26.156612 LPDDR4 DRAM CONFIGURATION
3801 11:05:26.160438 ===================================
3802 11:05:26.160563 EX_ROW_EN[0] = 0x0
3803 11:05:26.163564 EX_ROW_EN[1] = 0x0
3804 11:05:26.163658 LP4Y_EN = 0x0
3805 11:05:26.166769 WORK_FSP = 0x0
3806 11:05:26.166867 WL = 0x2
3807 11:05:26.169804 RL = 0x2
3808 11:05:26.169899 BL = 0x2
3809 11:05:26.173511 RPST = 0x0
3810 11:05:26.173607 RD_PRE = 0x0
3811 11:05:26.176201 WR_PRE = 0x1
3812 11:05:26.180142 WR_PST = 0x0
3813 11:05:26.180255 DBI_WR = 0x0
3814 11:05:26.183005 DBI_RD = 0x0
3815 11:05:26.183095 OTF = 0x1
3816 11:05:26.186202 ===================================
3817 11:05:26.189490 ===================================
3818 11:05:26.192598 ANA top config
3819 11:05:26.192709 ===================================
3820 11:05:26.195939 DLL_ASYNC_EN = 0
3821 11:05:26.199252 ALL_SLAVE_EN = 1
3822 11:05:26.202657 NEW_RANK_MODE = 1
3823 11:05:26.205619 DLL_IDLE_MODE = 1
3824 11:05:26.205721 LP45_APHY_COMB_EN = 1
3825 11:05:26.209369 TX_ODT_DIS = 1
3826 11:05:26.212515 NEW_8X_MODE = 1
3827 11:05:26.216375 ===================================
3828 11:05:26.219183 ===================================
3829 11:05:26.222654 data_rate = 1200
3830 11:05:26.225778 CKR = 1
3831 11:05:26.228847 DQ_P2S_RATIO = 8
3832 11:05:26.232852 ===================================
3833 11:05:26.232972 CA_P2S_RATIO = 8
3834 11:05:26.235615 DQ_CA_OPEN = 0
3835 11:05:26.238886 DQ_SEMI_OPEN = 0
3836 11:05:26.241801 CA_SEMI_OPEN = 0
3837 11:05:26.245099 CA_FULL_RATE = 0
3838 11:05:26.248603 DQ_CKDIV4_EN = 1
3839 11:05:26.248722 CA_CKDIV4_EN = 1
3840 11:05:26.252184 CA_PREDIV_EN = 0
3841 11:05:26.255231 PH8_DLY = 0
3842 11:05:26.258643 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3843 11:05:26.261749 DQ_AAMCK_DIV = 4
3844 11:05:26.265217 CA_AAMCK_DIV = 4
3845 11:05:26.268578 CA_ADMCK_DIV = 4
3846 11:05:26.268692 DQ_TRACK_CA_EN = 0
3847 11:05:26.271365 CA_PICK = 600
3848 11:05:26.274973 CA_MCKIO = 600
3849 11:05:26.278513 MCKIO_SEMI = 0
3850 11:05:26.281820 PLL_FREQ = 2288
3851 11:05:26.284968 DQ_UI_PI_RATIO = 32
3852 11:05:26.288431 CA_UI_PI_RATIO = 0
3853 11:05:26.290936 ===================================
3854 11:05:26.294277 ===================================
3855 11:05:26.294382 memory_type:LPDDR4
3856 11:05:26.297899 GP_NUM : 10
3857 11:05:26.301449 SRAM_EN : 1
3858 11:05:26.301567 MD32_EN : 0
3859 11:05:26.304092 ===================================
3860 11:05:26.307345 [ANA_INIT] >>>>>>>>>>>>>>
3861 11:05:26.311095 <<<<<< [CONFIGURE PHASE]: ANA_TX
3862 11:05:26.314354 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3863 11:05:26.317173 ===================================
3864 11:05:26.321103 data_rate = 1200,PCW = 0X5800
3865 11:05:26.323851 ===================================
3866 11:05:26.327941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3867 11:05:26.330712 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3868 11:05:26.337078 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3869 11:05:26.340861 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3870 11:05:26.348071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3871 11:05:26.350676 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3872 11:05:26.350783 [ANA_INIT] flow start
3873 11:05:26.353713 [ANA_INIT] PLL >>>>>>>>
3874 11:05:26.357052 [ANA_INIT] PLL <<<<<<<<
3875 11:05:26.357161 [ANA_INIT] MIDPI >>>>>>>>
3876 11:05:26.360185 [ANA_INIT] MIDPI <<<<<<<<
3877 11:05:26.363687 [ANA_INIT] DLL >>>>>>>>
3878 11:05:26.363815 [ANA_INIT] flow end
3879 11:05:26.370123 ============ LP4 DIFF to SE enter ============
3880 11:05:26.373171 ============ LP4 DIFF to SE exit ============
3881 11:05:26.373283 [ANA_INIT] <<<<<<<<<<<<<
3882 11:05:26.376885 [Flow] Enable top DCM control >>>>>
3883 11:05:26.380562 [Flow] Enable top DCM control <<<<<
3884 11:05:26.383215 Enable DLL master slave shuffle
3885 11:05:26.390280 ==============================================================
3886 11:05:26.393436 Gating Mode config
3887 11:05:26.396396 ==============================================================
3888 11:05:26.399565 Config description:
3889 11:05:26.409790 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3890 11:05:26.416267 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3891 11:05:26.419874 SELPH_MODE 0: By rank 1: By Phase
3892 11:05:26.425893 ==============================================================
3893 11:05:26.429272 GAT_TRACK_EN = 1
3894 11:05:26.432480 RX_GATING_MODE = 2
3895 11:05:26.436543 RX_GATING_TRACK_MODE = 2
3896 11:05:26.439242 SELPH_MODE = 1
3897 11:05:26.442806 PICG_EARLY_EN = 1
3898 11:05:26.442918 VALID_LAT_VALUE = 1
3899 11:05:26.449424 ==============================================================
3900 11:05:26.452627 Enter into Gating configuration >>>>
3901 11:05:26.455667 Exit from Gating configuration <<<<
3902 11:05:26.459056 Enter into DVFS_PRE_config >>>>>
3903 11:05:26.469325 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3904 11:05:26.472431 Exit from DVFS_PRE_config <<<<<
3905 11:05:26.475736 Enter into PICG configuration >>>>
3906 11:05:26.479413 Exit from PICG configuration <<<<
3907 11:05:26.482064 [RX_INPUT] configuration >>>>>
3908 11:05:26.485667 [RX_INPUT] configuration <<<<<
3909 11:05:26.492699 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3910 11:05:26.495157 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3911 11:05:26.502022 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3912 11:05:26.508303 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3913 11:05:26.515217 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3914 11:05:26.521613 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3915 11:05:26.524682 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3916 11:05:26.527814 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3917 11:05:26.531442 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3918 11:05:26.538687 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3919 11:05:26.541506 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3920 11:05:26.544716 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3921 11:05:26.548018 ===================================
3922 11:05:26.551318 LPDDR4 DRAM CONFIGURATION
3923 11:05:26.554643 ===================================
3924 11:05:26.558027 EX_ROW_EN[0] = 0x0
3925 11:05:26.558139 EX_ROW_EN[1] = 0x0
3926 11:05:26.561721 LP4Y_EN = 0x0
3927 11:05:26.561824 WORK_FSP = 0x0
3928 11:05:26.564891 WL = 0x2
3929 11:05:26.564997 RL = 0x2
3930 11:05:26.567624 BL = 0x2
3931 11:05:26.567771 RPST = 0x0
3932 11:05:26.571659 RD_PRE = 0x0
3933 11:05:26.571803 WR_PRE = 0x1
3934 11:05:26.574512 WR_PST = 0x0
3935 11:05:26.574606 DBI_WR = 0x0
3936 11:05:26.577888 DBI_RD = 0x0
3937 11:05:26.578012 OTF = 0x1
3938 11:05:26.580959 ===================================
3939 11:05:26.587597 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3940 11:05:26.590982 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3941 11:05:26.594058 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3942 11:05:26.597643 ===================================
3943 11:05:26.601138 LPDDR4 DRAM CONFIGURATION
3944 11:05:26.603900 ===================================
3945 11:05:26.607109 EX_ROW_EN[0] = 0x10
3946 11:05:26.607217 EX_ROW_EN[1] = 0x0
3947 11:05:26.610996 LP4Y_EN = 0x0
3948 11:05:26.611097 WORK_FSP = 0x0
3949 11:05:26.614060 WL = 0x2
3950 11:05:26.614159 RL = 0x2
3951 11:05:26.617245 BL = 0x2
3952 11:05:26.617341 RPST = 0x0
3953 11:05:26.620820 RD_PRE = 0x0
3954 11:05:26.620919 WR_PRE = 0x1
3955 11:05:26.624106 WR_PST = 0x0
3956 11:05:26.624204 DBI_WR = 0x0
3957 11:05:26.626891 DBI_RD = 0x0
3958 11:05:26.626984 OTF = 0x1
3959 11:05:26.630221 ===================================
3960 11:05:26.637160 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3961 11:05:26.642026 nWR fixed to 30
3962 11:05:26.645732 [ModeRegInit_LP4] CH0 RK0
3963 11:05:26.645861 [ModeRegInit_LP4] CH0 RK1
3964 11:05:26.648323 [ModeRegInit_LP4] CH1 RK0
3965 11:05:26.651633 [ModeRegInit_LP4] CH1 RK1
3966 11:05:26.651791 match AC timing 17
3967 11:05:26.658949 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3968 11:05:26.661662 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3969 11:05:26.664653 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3970 11:05:26.671879 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3971 11:05:26.675118 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3972 11:05:26.675231 ==
3973 11:05:26.677899 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 11:05:26.681647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 11:05:26.684736 ==
3976 11:05:26.688399 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3977 11:05:26.694531 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3978 11:05:26.697992 [CA 0] Center 36 (6~66) winsize 61
3979 11:05:26.701067 [CA 1] Center 36 (6~66) winsize 61
3980 11:05:26.704797 [CA 2] Center 34 (3~65) winsize 63
3981 11:05:26.707809 [CA 3] Center 34 (3~65) winsize 63
3982 11:05:26.711088 [CA 4] Center 33 (3~64) winsize 62
3983 11:05:26.714112 [CA 5] Center 33 (3~64) winsize 62
3984 11:05:26.714241
3985 11:05:26.717492 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3986 11:05:26.717593
3987 11:05:26.720874 [CATrainingPosCal] consider 1 rank data
3988 11:05:26.724250 u2DelayCellTimex100 = 270/100 ps
3989 11:05:26.727860 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3990 11:05:26.730914 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3991 11:05:26.734407 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3992 11:05:26.740557 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3993 11:05:26.743782 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3994 11:05:26.747283 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3995 11:05:26.747427
3996 11:05:26.750249 CA PerBit enable=1, Macro0, CA PI delay=33
3997 11:05:26.750371
3998 11:05:26.753578 [CBTSetCACLKResult] CA Dly = 33
3999 11:05:26.753692 CS Dly: 4 (0~35)
4000 11:05:26.753781 ==
4001 11:05:26.757099 Dram Type= 6, Freq= 0, CH_0, rank 1
4002 11:05:26.763872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4003 11:05:26.764035 ==
4004 11:05:26.766765 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4005 11:05:26.773428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4006 11:05:26.777741 [CA 0] Center 36 (6~66) winsize 61
4007 11:05:26.780858 [CA 1] Center 36 (6~66) winsize 61
4008 11:05:26.784181 [CA 2] Center 34 (4~65) winsize 62
4009 11:05:26.786959 [CA 3] Center 34 (4~65) winsize 62
4010 11:05:26.790031 [CA 4] Center 33 (3~64) winsize 62
4011 11:05:26.793962 [CA 5] Center 33 (3~64) winsize 62
4012 11:05:26.794085
4013 11:05:26.797571 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4014 11:05:26.797678
4015 11:05:26.799979 [CATrainingPosCal] consider 2 rank data
4016 11:05:26.803436 u2DelayCellTimex100 = 270/100 ps
4017 11:05:26.810493 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4018 11:05:26.812996 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4019 11:05:26.816874 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4020 11:05:26.819866 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4021 11:05:26.823158 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4022 11:05:26.826425 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4023 11:05:26.826559
4024 11:05:26.829379 CA PerBit enable=1, Macro0, CA PI delay=33
4025 11:05:26.829474
4026 11:05:26.833129 [CBTSetCACLKResult] CA Dly = 33
4027 11:05:26.836438 CS Dly: 4 (0~36)
4028 11:05:26.836546
4029 11:05:26.839581 ----->DramcWriteLeveling(PI) begin...
4030 11:05:26.839729 ==
4031 11:05:26.842730 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 11:05:26.846415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 11:05:26.846524 ==
4034 11:05:26.849315 Write leveling (Byte 0): 33 => 33
4035 11:05:26.852966 Write leveling (Byte 1): 33 => 33
4036 11:05:26.856200 DramcWriteLeveling(PI) end<-----
4037 11:05:26.856311
4038 11:05:26.856378 ==
4039 11:05:26.859619 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 11:05:26.862482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 11:05:26.862583 ==
4042 11:05:26.866432 [Gating] SW mode calibration
4043 11:05:26.872327 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4044 11:05:26.878857 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4045 11:05:26.882420 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4046 11:05:26.889059 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4047 11:05:26.891923 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4048 11:05:26.895372 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4049 11:05:26.901684 0 9 16 | B1->B0 | 3030 2727 | 0 0 | (0 0) (1 1)
4050 11:05:26.904996 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 11:05:26.908339 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 11:05:26.914998 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 11:05:26.918273 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 11:05:26.921600 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 11:05:26.928186 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 11:05:26.931648 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4057 11:05:26.935646 0 10 16 | B1->B0 | 3636 4141 | 1 1 | (0 0) (0 0)
4058 11:05:26.940845 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 11:05:26.944600 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 11:05:26.947810 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 11:05:26.954190 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 11:05:26.957490 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 11:05:26.960823 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 11:05:26.967389 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 11:05:26.970752 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4066 11:05:26.974053 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 11:05:26.980377 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 11:05:26.983889 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 11:05:26.987015 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 11:05:26.993541 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 11:05:26.996793 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 11:05:27.000561 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 11:05:27.006751 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 11:05:27.010342 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 11:05:27.013742 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 11:05:27.020192 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 11:05:27.023881 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 11:05:27.026865 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 11:05:27.033567 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 11:05:27.037475 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 11:05:27.040311 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4082 11:05:27.043227 Total UI for P1: 0, mck2ui 16
4083 11:05:27.046332 best dqsien dly found for B0: ( 0, 13, 14)
4084 11:05:27.053463 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 11:05:27.056144 Total UI for P1: 0, mck2ui 16
4086 11:05:27.059942 best dqsien dly found for B1: ( 0, 13, 16)
4087 11:05:27.063123 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4088 11:05:27.066002 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4089 11:05:27.066096
4090 11:05:27.069154 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4091 11:05:27.072480 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4092 11:05:27.075636 [Gating] SW calibration Done
4093 11:05:27.075773 ==
4094 11:05:27.079138 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 11:05:27.082857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 11:05:27.082947 ==
4097 11:05:27.085696 RX Vref Scan: 0
4098 11:05:27.085781
4099 11:05:27.089215 RX Vref 0 -> 0, step: 1
4100 11:05:27.089300
4101 11:05:27.092570 RX Delay -230 -> 252, step: 16
4102 11:05:27.096576 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4103 11:05:27.099043 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4104 11:05:27.102668 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4105 11:05:27.105616 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4106 11:05:27.112298 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4107 11:05:27.116070 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4108 11:05:27.118878 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4109 11:05:27.122365 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4110 11:05:27.128907 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4111 11:05:27.131904 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4112 11:05:27.135053 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4113 11:05:27.138555 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4114 11:05:27.145053 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4115 11:05:27.148343 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4116 11:05:27.152068 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4117 11:05:27.154912 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4118 11:05:27.158861 ==
4119 11:05:27.161549 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 11:05:27.164686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 11:05:27.164782 ==
4122 11:05:27.164849 DQS Delay:
4123 11:05:27.167583 DQS0 = 0, DQS1 = 0
4124 11:05:27.167732 DQM Delay:
4125 11:05:27.170990 DQM0 = 42, DQM1 = 30
4126 11:05:27.171075 DQ Delay:
4127 11:05:27.174467 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4128 11:05:27.177692 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4129 11:05:27.181511 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4130 11:05:27.184616 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4131 11:05:27.184708
4132 11:05:27.184774
4133 11:05:27.184834 ==
4134 11:05:27.187423 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 11:05:27.191013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 11:05:27.191101 ==
4137 11:05:27.191167
4138 11:05:27.191227
4139 11:05:27.194211 TX Vref Scan disable
4140 11:05:27.197668 == TX Byte 0 ==
4141 11:05:27.200667 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4142 11:05:27.204051 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4143 11:05:27.208521 == TX Byte 1 ==
4144 11:05:27.210885 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4145 11:05:27.214433 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4146 11:05:27.214530 ==
4147 11:05:27.217320 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 11:05:27.223605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 11:05:27.223785 ==
4150 11:05:27.223910
4151 11:05:27.223998
4152 11:05:27.224084 TX Vref Scan disable
4153 11:05:27.228630 == TX Byte 0 ==
4154 11:05:27.232030 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4155 11:05:27.238547 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4156 11:05:27.238674 == TX Byte 1 ==
4157 11:05:27.241458 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4158 11:05:27.248461 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4159 11:05:27.248582
4160 11:05:27.248646 [DATLAT]
4161 11:05:27.248706 Freq=600, CH0 RK0
4162 11:05:27.248764
4163 11:05:27.251446 DATLAT Default: 0x9
4164 11:05:27.251556 0, 0xFFFF, sum = 0
4165 11:05:27.255119 1, 0xFFFF, sum = 0
4166 11:05:27.258679 2, 0xFFFF, sum = 0
4167 11:05:27.258784 3, 0xFFFF, sum = 0
4168 11:05:27.261620 4, 0xFFFF, sum = 0
4169 11:05:27.261712 5, 0xFFFF, sum = 0
4170 11:05:27.265060 6, 0xFFFF, sum = 0
4171 11:05:27.265150 7, 0xFFFF, sum = 0
4172 11:05:27.268075 8, 0x0, sum = 1
4173 11:05:27.268162 9, 0x0, sum = 2
4174 11:05:27.268229 10, 0x0, sum = 3
4175 11:05:27.271775 11, 0x0, sum = 4
4176 11:05:27.271862 best_step = 9
4177 11:05:27.271927
4178 11:05:27.271987 ==
4179 11:05:27.274883 Dram Type= 6, Freq= 0, CH_0, rank 0
4180 11:05:27.281129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 11:05:27.281257 ==
4182 11:05:27.281339 RX Vref Scan: 1
4183 11:05:27.281400
4184 11:05:27.284939 RX Vref 0 -> 0, step: 1
4185 11:05:27.285027
4186 11:05:27.287886 RX Delay -195 -> 252, step: 8
4187 11:05:27.287971
4188 11:05:27.291220 Set Vref, RX VrefLevel [Byte0]: 59
4189 11:05:27.294852 [Byte1]: 58
4190 11:05:27.294942
4191 11:05:27.297646 Final RX Vref Byte 0 = 59 to rank0
4192 11:05:27.301198 Final RX Vref Byte 1 = 58 to rank0
4193 11:05:27.304911 Final RX Vref Byte 0 = 59 to rank1
4194 11:05:27.307592 Final RX Vref Byte 1 = 58 to rank1==
4195 11:05:27.311208 Dram Type= 6, Freq= 0, CH_0, rank 0
4196 11:05:27.314239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 11:05:27.317244 ==
4198 11:05:27.317340 DQS Delay:
4199 11:05:27.317405 DQS0 = 0, DQS1 = 0
4200 11:05:27.320553 DQM Delay:
4201 11:05:27.320640 DQM0 = 43, DQM1 = 33
4202 11:05:27.323992 DQ Delay:
4203 11:05:27.327564 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4204 11:05:27.327727 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4205 11:05:27.330957 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4206 11:05:27.337193 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4207 11:05:27.337296
4208 11:05:27.337364
4209 11:05:27.343575 [DQSOSCAuto] RK0, (LSB)MR18= 0x653c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 390 ps
4210 11:05:27.347328 CH0 RK0: MR19=808, MR18=653C
4211 11:05:27.353726 CH0_RK0: MR19=0x808, MR18=0x653C, DQSOSC=390, MR23=63, INC=172, DEC=114
4212 11:05:27.353849
4213 11:05:27.356949 ----->DramcWriteLeveling(PI) begin...
4214 11:05:27.357037 ==
4215 11:05:27.360262 Dram Type= 6, Freq= 0, CH_0, rank 1
4216 11:05:27.363531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 11:05:27.363618 ==
4218 11:05:27.367077 Write leveling (Byte 0): 32 => 32
4219 11:05:27.369970 Write leveling (Byte 1): 31 => 31
4220 11:05:27.373374 DramcWriteLeveling(PI) end<-----
4221 11:05:27.373466
4222 11:05:27.373558 ==
4223 11:05:27.376694 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 11:05:27.379946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 11:05:27.380098 ==
4226 11:05:27.383586 [Gating] SW mode calibration
4227 11:05:27.390004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4228 11:05:27.396524 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4229 11:05:27.400002 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4230 11:05:27.407546 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 11:05:27.409652 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4232 11:05:27.413254 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (0 0) (0 0)
4233 11:05:27.419519 0 9 16 | B1->B0 | 2f2f 2a2a | 0 0 | (0 0) (1 1)
4234 11:05:27.422816 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 11:05:27.426322 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 11:05:27.432809 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 11:05:27.436237 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 11:05:27.439085 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 11:05:27.445741 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 11:05:27.450101 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
4241 11:05:27.452965 0 10 16 | B1->B0 | 3838 3f3f | 0 0 | (0 0) (1 1)
4242 11:05:27.459315 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 11:05:27.462796 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 11:05:27.465924 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 11:05:27.472348 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 11:05:27.475598 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 11:05:27.479244 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 11:05:27.485459 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4249 11:05:27.488963 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 11:05:27.491833 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 11:05:27.498551 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 11:05:27.502265 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 11:05:27.505963 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 11:05:27.511840 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 11:05:27.515584 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 11:05:27.518294 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 11:05:27.525275 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 11:05:27.529260 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 11:05:27.532072 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 11:05:27.538232 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 11:05:27.541707 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 11:05:27.544915 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 11:05:27.551524 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 11:05:27.554607 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 11:05:27.557910 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4266 11:05:27.564520 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 11:05:27.564642 Total UI for P1: 0, mck2ui 16
4268 11:05:27.571343 best dqsien dly found for B0: ( 0, 13, 16)
4269 11:05:27.571457 Total UI for P1: 0, mck2ui 16
4270 11:05:27.577824 best dqsien dly found for B1: ( 0, 13, 16)
4271 11:05:27.580979 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4272 11:05:27.584370 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4273 11:05:27.584469
4274 11:05:27.587627 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4275 11:05:27.590589 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4276 11:05:27.594399 [Gating] SW calibration Done
4277 11:05:27.594511 ==
4278 11:05:27.597099 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 11:05:27.600324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 11:05:27.600417 ==
4281 11:05:27.603603 RX Vref Scan: 0
4282 11:05:27.603747
4283 11:05:27.607162 RX Vref 0 -> 0, step: 1
4284 11:05:27.607246
4285 11:05:27.607311 RX Delay -230 -> 252, step: 16
4286 11:05:27.613889 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4287 11:05:27.617542 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4288 11:05:27.620629 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4289 11:05:27.624070 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4290 11:05:27.630549 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4291 11:05:27.633897 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4292 11:05:27.637578 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4293 11:05:27.640260 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4294 11:05:27.646613 iDelay=218, Bit 8, Center 33 (-134 ~ 201) 336
4295 11:05:27.650151 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4296 11:05:27.653101 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4297 11:05:27.656212 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4298 11:05:27.663222 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4299 11:05:27.666563 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4300 11:05:27.669924 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4301 11:05:27.673072 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4302 11:05:27.673193 ==
4303 11:05:27.676174 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 11:05:27.683169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 11:05:27.683294 ==
4306 11:05:27.683361 DQS Delay:
4307 11:05:27.686259 DQS0 = 0, DQS1 = 0
4308 11:05:27.686345 DQM Delay:
4309 11:05:27.689098 DQM0 = 45, DQM1 = 37
4310 11:05:27.689188 DQ Delay:
4311 11:05:27.693194 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =33
4312 11:05:27.695831 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4313 11:05:27.698868 DQ8 =33, DQ9 =25, DQ10 =33, DQ11 =33
4314 11:05:27.702124 DQ12 =33, DQ13 =41, DQ14 =57, DQ15 =41
4315 11:05:27.702217
4316 11:05:27.702282
4317 11:05:27.702340 ==
4318 11:05:27.706027 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 11:05:27.708844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 11:05:27.708933 ==
4321 11:05:27.708997
4322 11:05:27.709057
4323 11:05:27.712109 TX Vref Scan disable
4324 11:05:27.716175 == TX Byte 0 ==
4325 11:05:27.719119 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4326 11:05:27.721748 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4327 11:05:27.725215 == TX Byte 1 ==
4328 11:05:27.728447 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4329 11:05:27.732068 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4330 11:05:27.732176 ==
4331 11:05:27.735474 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 11:05:27.741789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 11:05:27.741923 ==
4334 11:05:27.741993
4335 11:05:27.742052
4336 11:05:27.742108 TX Vref Scan disable
4337 11:05:27.748221 == TX Byte 0 ==
4338 11:05:27.749636 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4339 11:05:27.756073 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4340 11:05:27.756191 == TX Byte 1 ==
4341 11:05:27.759876 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4342 11:05:27.766116 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4343 11:05:27.766242
4344 11:05:27.766308 [DATLAT]
4345 11:05:27.766368 Freq=600, CH0 RK1
4346 11:05:27.766425
4347 11:05:27.769560 DATLAT Default: 0x9
4348 11:05:27.773108 0, 0xFFFF, sum = 0
4349 11:05:27.773198 1, 0xFFFF, sum = 0
4350 11:05:27.775998 2, 0xFFFF, sum = 0
4351 11:05:27.776080 3, 0xFFFF, sum = 0
4352 11:05:27.779687 4, 0xFFFF, sum = 0
4353 11:05:27.779786 5, 0xFFFF, sum = 0
4354 11:05:27.782757 6, 0xFFFF, sum = 0
4355 11:05:27.782840 7, 0xFFFF, sum = 0
4356 11:05:27.785588 8, 0x0, sum = 1
4357 11:05:27.785670 9, 0x0, sum = 2
4358 11:05:27.789252 10, 0x0, sum = 3
4359 11:05:27.789335 11, 0x0, sum = 4
4360 11:05:27.789400 best_step = 9
4361 11:05:27.789459
4362 11:05:27.792554 ==
4363 11:05:27.795880 Dram Type= 6, Freq= 0, CH_0, rank 1
4364 11:05:27.799224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 11:05:27.799309 ==
4366 11:05:27.799375 RX Vref Scan: 0
4367 11:05:27.799436
4368 11:05:27.802477 RX Vref 0 -> 0, step: 1
4369 11:05:27.802560
4370 11:05:27.805568 RX Delay -179 -> 252, step: 8
4371 11:05:27.812311 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4372 11:05:27.815495 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4373 11:05:27.818813 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4374 11:05:27.822045 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4375 11:05:27.828800 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4376 11:05:27.832245 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4377 11:05:27.835262 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4378 11:05:27.838414 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4379 11:05:27.841630 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4380 11:05:27.848141 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4381 11:05:27.851831 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4382 11:05:27.854987 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4383 11:05:27.859014 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4384 11:05:27.865169 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4385 11:05:27.869817 iDelay=205, Bit 14, Center 48 (-107 ~ 204) 312
4386 11:05:27.871790 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4387 11:05:27.871877 ==
4388 11:05:27.875705 Dram Type= 6, Freq= 0, CH_0, rank 1
4389 11:05:27.879082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 11:05:27.881149 ==
4391 11:05:27.881234 DQS Delay:
4392 11:05:27.881305 DQS0 = 0, DQS1 = 0
4393 11:05:27.884812 DQM Delay:
4394 11:05:27.884899 DQM0 = 41, DQM1 = 34
4395 11:05:27.887757 DQ Delay:
4396 11:05:27.891513 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4397 11:05:27.891640 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =52
4398 11:05:27.894582 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4399 11:05:27.900868 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =40
4400 11:05:27.900984
4401 11:05:27.901050
4402 11:05:27.907815 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f12, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4403 11:05:27.911195 CH0 RK1: MR19=808, MR18=5F12
4404 11:05:27.917764 CH0_RK1: MR19=0x808, MR18=0x5F12, DQSOSC=391, MR23=63, INC=171, DEC=114
4405 11:05:27.920450 [RxdqsGatingPostProcess] freq 600
4406 11:05:27.923608 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4407 11:05:27.927111 Pre-setting of DQS Precalculation
4408 11:05:27.933969 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4409 11:05:27.934101 ==
4410 11:05:27.937113 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 11:05:27.940627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 11:05:27.940742 ==
4413 11:05:27.947032 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4414 11:05:27.953494 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4415 11:05:27.957012 [CA 0] Center 35 (5~66) winsize 62
4416 11:05:27.960373 [CA 1] Center 35 (5~66) winsize 62
4417 11:05:27.963603 [CA 2] Center 34 (3~65) winsize 63
4418 11:05:27.966520 [CA 3] Center 33 (3~64) winsize 62
4419 11:05:27.969912 [CA 4] Center 34 (4~65) winsize 62
4420 11:05:27.973091 [CA 5] Center 33 (3~64) winsize 62
4421 11:05:27.973194
4422 11:05:27.976926 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4423 11:05:27.977021
4424 11:05:27.979995 [CATrainingPosCal] consider 1 rank data
4425 11:05:27.983075 u2DelayCellTimex100 = 270/100 ps
4426 11:05:27.986007 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4427 11:05:27.989529 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4428 11:05:27.993134 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4429 11:05:27.996373 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4430 11:05:28.003060 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4431 11:05:28.005830 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4432 11:05:28.005918
4433 11:05:28.009361 CA PerBit enable=1, Macro0, CA PI delay=33
4434 11:05:28.009473
4435 11:05:28.012435 [CBTSetCACLKResult] CA Dly = 33
4436 11:05:28.012517 CS Dly: 4 (0~35)
4437 11:05:28.012583 ==
4438 11:05:28.015873 Dram Type= 6, Freq= 0, CH_1, rank 1
4439 11:05:28.021982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 11:05:28.022076 ==
4441 11:05:28.026345 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4442 11:05:28.031913 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4443 11:05:28.035789 [CA 0] Center 35 (5~66) winsize 62
4444 11:05:28.038425 [CA 1] Center 36 (6~66) winsize 61
4445 11:05:28.042348 [CA 2] Center 34 (4~65) winsize 62
4446 11:05:28.045269 [CA 3] Center 34 (3~65) winsize 63
4447 11:05:28.048546 [CA 4] Center 34 (4~65) winsize 62
4448 11:05:28.052255 [CA 5] Center 34 (3~65) winsize 63
4449 11:05:28.052343
4450 11:05:28.054808 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4451 11:05:28.054892
4452 11:05:28.058280 [CATrainingPosCal] consider 2 rank data
4453 11:05:28.061772 u2DelayCellTimex100 = 270/100 ps
4454 11:05:28.065050 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4455 11:05:28.071632 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4456 11:05:28.074941 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4457 11:05:28.078230 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4458 11:05:28.081136 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4459 11:05:28.085092 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4460 11:05:28.085182
4461 11:05:28.088352 CA PerBit enable=1, Macro0, CA PI delay=33
4462 11:05:28.088436
4463 11:05:28.091394 [CBTSetCACLKResult] CA Dly = 33
4464 11:05:28.094435 CS Dly: 4 (0~36)
4465 11:05:28.094519
4466 11:05:28.097861 ----->DramcWriteLeveling(PI) begin...
4467 11:05:28.097947 ==
4468 11:05:28.101159 Dram Type= 6, Freq= 0, CH_1, rank 0
4469 11:05:28.104664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4470 11:05:28.104751 ==
4471 11:05:28.107919 Write leveling (Byte 0): 30 => 30
4472 11:05:28.111616 Write leveling (Byte 1): 31 => 31
4473 11:05:28.114339 DramcWriteLeveling(PI) end<-----
4474 11:05:28.114427
4475 11:05:28.114493 ==
4476 11:05:28.117754 Dram Type= 6, Freq= 0, CH_1, rank 0
4477 11:05:28.121384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4478 11:05:28.121472 ==
4479 11:05:28.125300 [Gating] SW mode calibration
4480 11:05:28.130751 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4481 11:05:28.137406 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4482 11:05:28.140594 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4483 11:05:28.146957 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4484 11:05:28.150655 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4485 11:05:28.154182 0 9 12 | B1->B0 | 3333 2e2e | 0 1 | (0 0) (1 0)
4486 11:05:28.160461 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 11:05:28.163882 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 11:05:28.166829 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 11:05:28.173687 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 11:05:28.176511 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 11:05:28.179938 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 11:05:28.186690 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 11:05:28.189810 0 10 12 | B1->B0 | 3131 3939 | 0 1 | (0 0) (0 0)
4494 11:05:28.192812 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4495 11:05:28.199860 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 11:05:28.202676 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 11:05:28.206384 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 11:05:28.213115 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 11:05:28.216144 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 11:05:28.219826 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 11:05:28.226257 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4502 11:05:28.229511 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4503 11:05:28.233280 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 11:05:28.239884 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 11:05:28.243304 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 11:05:28.246140 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 11:05:28.252720 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 11:05:28.255815 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 11:05:28.259083 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 11:05:28.265865 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 11:05:28.268881 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 11:05:28.272066 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 11:05:28.279155 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 11:05:28.282434 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 11:05:28.285882 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 11:05:28.292093 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 11:05:28.295271 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4518 11:05:28.298987 Total UI for P1: 0, mck2ui 16
4519 11:05:28.302043 best dqsien dly found for B0: ( 0, 13, 10)
4520 11:05:28.305839 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 11:05:28.308990 Total UI for P1: 0, mck2ui 16
4522 11:05:28.311641 best dqsien dly found for B1: ( 0, 13, 14)
4523 11:05:28.315233 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4524 11:05:28.318421 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4525 11:05:28.318511
4526 11:05:28.325076 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4527 11:05:28.328090 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4528 11:05:28.331399 [Gating] SW calibration Done
4529 11:05:28.331486 ==
4530 11:05:28.334433 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 11:05:28.337966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 11:05:28.338053 ==
4533 11:05:28.338139 RX Vref Scan: 0
4534 11:05:28.338229
4535 11:05:28.341072 RX Vref 0 -> 0, step: 1
4536 11:05:28.341157
4537 11:05:28.344354 RX Delay -230 -> 252, step: 16
4538 11:05:28.348349 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4539 11:05:28.354833 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4540 11:05:28.357755 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4541 11:05:28.361130 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4542 11:05:28.364141 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4543 11:05:28.367411 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4544 11:05:28.374642 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4545 11:05:28.377519 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4546 11:05:28.380760 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4547 11:05:28.384168 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4548 11:05:28.390796 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4549 11:05:28.393542 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4550 11:05:28.396902 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4551 11:05:28.400475 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4552 11:05:28.407699 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4553 11:05:28.410570 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4554 11:05:28.410656 ==
4555 11:05:28.413982 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 11:05:28.416895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 11:05:28.416982 ==
4558 11:05:28.420253 DQS Delay:
4559 11:05:28.420339 DQS0 = 0, DQS1 = 0
4560 11:05:28.420405 DQM Delay:
4561 11:05:28.423422 DQM0 = 47, DQM1 = 38
4562 11:05:28.423506 DQ Delay:
4563 11:05:28.427090 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4564 11:05:28.430218 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4565 11:05:28.433431 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4566 11:05:28.437186 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4567 11:05:28.437272
4568 11:05:28.437340
4569 11:05:28.437400 ==
4570 11:05:28.439974 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 11:05:28.447437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 11:05:28.447545 ==
4573 11:05:28.447613
4574 11:05:28.447697
4575 11:05:28.449750 TX Vref Scan disable
4576 11:05:28.449833 == TX Byte 0 ==
4577 11:05:28.453296 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4578 11:05:28.460500 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4579 11:05:28.460601 == TX Byte 1 ==
4580 11:05:28.466847 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4581 11:05:28.469514 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4582 11:05:28.469602 ==
4583 11:05:28.473478 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 11:05:28.476492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 11:05:28.476580 ==
4586 11:05:28.476646
4587 11:05:28.476706
4588 11:05:28.479446 TX Vref Scan disable
4589 11:05:28.483222 == TX Byte 0 ==
4590 11:05:28.485798 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4591 11:05:28.489215 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4592 11:05:28.492798 == TX Byte 1 ==
4593 11:05:28.495771 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4594 11:05:28.499475 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4595 11:05:28.499564
4596 11:05:28.502491 [DATLAT]
4597 11:05:28.502574 Freq=600, CH1 RK0
4598 11:05:28.502641
4599 11:05:28.505778 DATLAT Default: 0x9
4600 11:05:28.505861 0, 0xFFFF, sum = 0
4601 11:05:28.509091 1, 0xFFFF, sum = 0
4602 11:05:28.509177 2, 0xFFFF, sum = 0
4603 11:05:28.512413 3, 0xFFFF, sum = 0
4604 11:05:28.512498 4, 0xFFFF, sum = 0
4605 11:05:28.515898 5, 0xFFFF, sum = 0
4606 11:05:28.515983 6, 0xFFFF, sum = 0
4607 11:05:28.519379 7, 0xFFFF, sum = 0
4608 11:05:28.519465 8, 0x0, sum = 1
4609 11:05:28.522144 9, 0x0, sum = 2
4610 11:05:28.522228 10, 0x0, sum = 3
4611 11:05:28.525466 11, 0x0, sum = 4
4612 11:05:28.525551 best_step = 9
4613 11:05:28.525618
4614 11:05:28.525678 ==
4615 11:05:28.528777 Dram Type= 6, Freq= 0, CH_1, rank 0
4616 11:05:28.535510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 11:05:28.535601 ==
4618 11:05:28.535676 RX Vref Scan: 1
4619 11:05:28.535771
4620 11:05:28.539047 RX Vref 0 -> 0, step: 1
4621 11:05:28.539130
4622 11:05:28.541875 RX Delay -179 -> 252, step: 8
4623 11:05:28.541962
4624 11:05:28.545839 Set Vref, RX VrefLevel [Byte0]: 47
4625 11:05:28.548738 [Byte1]: 52
4626 11:05:28.548822
4627 11:05:28.552401 Final RX Vref Byte 0 = 47 to rank0
4628 11:05:28.555468 Final RX Vref Byte 1 = 52 to rank0
4629 11:05:28.558609 Final RX Vref Byte 0 = 47 to rank1
4630 11:05:28.561628 Final RX Vref Byte 1 = 52 to rank1==
4631 11:05:28.565253 Dram Type= 6, Freq= 0, CH_1, rank 0
4632 11:05:28.568498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 11:05:28.568588 ==
4634 11:05:28.571718 DQS Delay:
4635 11:05:28.571802 DQS0 = 0, DQS1 = 0
4636 11:05:28.575316 DQM Delay:
4637 11:05:28.575399 DQM0 = 48, DQM1 = 36
4638 11:05:28.575465 DQ Delay:
4639 11:05:28.578452 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4640 11:05:28.581704 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =40
4641 11:05:28.584852 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4642 11:05:28.588564 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =48
4643 11:05:28.588656
4644 11:05:28.588722
4645 11:05:28.598575 [DQSOSCAuto] RK0, (LSB)MR18= 0x482e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4646 11:05:28.602066 CH1 RK0: MR19=808, MR18=482E
4647 11:05:28.608285 CH1_RK0: MR19=0x808, MR18=0x482E, DQSOSC=396, MR23=63, INC=167, DEC=111
4648 11:05:28.608401
4649 11:05:28.611412 ----->DramcWriteLeveling(PI) begin...
4650 11:05:28.611502 ==
4651 11:05:28.614749 Dram Type= 6, Freq= 0, CH_1, rank 1
4652 11:05:28.618161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4653 11:05:28.618255 ==
4654 11:05:28.621380 Write leveling (Byte 0): 30 => 30
4655 11:05:28.625017 Write leveling (Byte 1): 31 => 31
4656 11:05:28.628082 DramcWriteLeveling(PI) end<-----
4657 11:05:28.628174
4658 11:05:28.628241 ==
4659 11:05:28.631603 Dram Type= 6, Freq= 0, CH_1, rank 1
4660 11:05:28.634487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 11:05:28.634576 ==
4662 11:05:28.637452 [Gating] SW mode calibration
4663 11:05:28.644687 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4664 11:05:28.650689 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4665 11:05:28.654139 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4666 11:05:28.657775 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4667 11:05:28.664446 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4668 11:05:28.667399 0 9 12 | B1->B0 | 2f2f 3333 | 1 1 | (1 0) (1 0)
4669 11:05:28.670861 0 9 16 | B1->B0 | 2626 2929 | 0 1 | (0 0) (0 0)
4670 11:05:28.676991 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 11:05:28.680412 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 11:05:28.684052 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 11:05:28.691143 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 11:05:28.693851 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 11:05:28.697299 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 11:05:28.703938 0 10 12 | B1->B0 | 3737 2d2d | 1 0 | (0 0) (0 0)
4677 11:05:28.706719 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4678 11:05:28.710724 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 11:05:28.717026 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 11:05:28.720238 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 11:05:28.723284 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 11:05:28.730270 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 11:05:28.733139 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 11:05:28.736671 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4685 11:05:28.743992 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 11:05:28.746643 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 11:05:28.750540 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 11:05:28.756412 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 11:05:28.760118 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 11:05:28.763320 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 11:05:28.769895 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 11:05:28.772846 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 11:05:28.776439 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 11:05:28.782764 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 11:05:28.786244 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 11:05:28.789600 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 11:05:28.795870 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 11:05:28.799599 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 11:05:28.802768 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 11:05:28.808933 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4701 11:05:28.812745 Total UI for P1: 0, mck2ui 16
4702 11:05:28.816101 best dqsien dly found for B1: ( 0, 13, 10)
4703 11:05:28.820139 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4704 11:05:28.822959 Total UI for P1: 0, mck2ui 16
4705 11:05:28.825931 best dqsien dly found for B0: ( 0, 13, 12)
4706 11:05:28.828631 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4707 11:05:28.832386 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4708 11:05:28.832476
4709 11:05:28.835634 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4710 11:05:28.842047 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4711 11:05:28.842163 [Gating] SW calibration Done
4712 11:05:28.842230 ==
4713 11:05:28.845226 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 11:05:28.851875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 11:05:28.851990 ==
4716 11:05:28.852056 RX Vref Scan: 0
4717 11:05:28.852116
4718 11:05:28.855540 RX Vref 0 -> 0, step: 1
4719 11:05:28.855623
4720 11:05:28.858375 RX Delay -230 -> 252, step: 16
4721 11:05:28.862185 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4722 11:05:28.865324 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4723 11:05:28.871407 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4724 11:05:28.874845 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4725 11:05:28.878405 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4726 11:05:28.881490 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4727 11:05:28.885610 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4728 11:05:28.891513 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4729 11:05:28.894468 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4730 11:05:28.898402 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4731 11:05:28.901212 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4732 11:05:28.907879 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4733 11:05:28.910957 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4734 11:05:28.914335 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4735 11:05:28.917621 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4736 11:05:28.924206 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4737 11:05:28.924347 ==
4738 11:05:28.927736 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 11:05:28.930997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 11:05:28.931102 ==
4741 11:05:28.931196 DQS Delay:
4742 11:05:28.933941 DQS0 = 0, DQS1 = 0
4743 11:05:28.934047 DQM Delay:
4744 11:05:28.937419 DQM0 = 46, DQM1 = 38
4745 11:05:28.937524 DQ Delay:
4746 11:05:28.940386 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4747 11:05:28.944105 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4748 11:05:28.947279 DQ8 =17, DQ9 =33, DQ10 =41, DQ11 =25
4749 11:05:28.950868 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4750 11:05:28.950978
4751 11:05:28.951069
4752 11:05:28.951197 ==
4753 11:05:28.954181 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 11:05:28.960394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 11:05:28.960507 ==
4756 11:05:28.960601
4757 11:05:28.960688
4758 11:05:28.960773 TX Vref Scan disable
4759 11:05:28.964533 == TX Byte 0 ==
4760 11:05:28.967264 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4761 11:05:28.973491 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4762 11:05:28.973612 == TX Byte 1 ==
4763 11:05:28.976911 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4764 11:05:28.983662 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4765 11:05:28.983826 ==
4766 11:05:28.986769 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 11:05:28.990533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 11:05:28.990636 ==
4769 11:05:28.990725
4770 11:05:28.990837
4771 11:05:28.993712 TX Vref Scan disable
4772 11:05:28.996552 == TX Byte 0 ==
4773 11:05:28.999964 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4774 11:05:29.003895 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4775 11:05:29.007211 == TX Byte 1 ==
4776 11:05:29.009905 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4777 11:05:29.013323 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4778 11:05:29.013435
4779 11:05:29.016444 [DATLAT]
4780 11:05:29.016547 Freq=600, CH1 RK1
4781 11:05:29.016639
4782 11:05:29.020160 DATLAT Default: 0x9
4783 11:05:29.020270 0, 0xFFFF, sum = 0
4784 11:05:29.023105 1, 0xFFFF, sum = 0
4785 11:05:29.023218 2, 0xFFFF, sum = 0
4786 11:05:29.026375 3, 0xFFFF, sum = 0
4787 11:05:29.026479 4, 0xFFFF, sum = 0
4788 11:05:29.029617 5, 0xFFFF, sum = 0
4789 11:05:29.029713 6, 0xFFFF, sum = 0
4790 11:05:29.032664 7, 0xFFFF, sum = 0
4791 11:05:29.032764 8, 0x0, sum = 1
4792 11:05:29.035984 9, 0x0, sum = 2
4793 11:05:29.036073 10, 0x0, sum = 3
4794 11:05:29.039479 11, 0x0, sum = 4
4795 11:05:29.039573 best_step = 9
4796 11:05:29.039654
4797 11:05:29.039745 ==
4798 11:05:29.042667 Dram Type= 6, Freq= 0, CH_1, rank 1
4799 11:05:29.046168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4800 11:05:29.049305 ==
4801 11:05:29.049396 RX Vref Scan: 0
4802 11:05:29.049494
4803 11:05:29.053114 RX Vref 0 -> 0, step: 1
4804 11:05:29.053200
4805 11:05:29.055900 RX Delay -195 -> 252, step: 8
4806 11:05:29.059167 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4807 11:05:29.063001 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4808 11:05:29.069049 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4809 11:05:29.072588 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4810 11:05:29.076255 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4811 11:05:29.078913 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4812 11:05:29.086418 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4813 11:05:29.089289 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4814 11:05:29.092298 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4815 11:05:29.095572 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4816 11:05:29.099239 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4817 11:05:29.105506 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4818 11:05:29.108558 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4819 11:05:29.112384 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4820 11:05:29.119130 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4821 11:05:29.121603 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4822 11:05:29.121729 ==
4823 11:05:29.125794 Dram Type= 6, Freq= 0, CH_1, rank 1
4824 11:05:29.128410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4825 11:05:29.128519 ==
4826 11:05:29.131677 DQS Delay:
4827 11:05:29.131785 DQS0 = 0, DQS1 = 0
4828 11:05:29.131862 DQM Delay:
4829 11:05:29.134616 DQM0 = 45, DQM1 = 37
4830 11:05:29.134689 DQ Delay:
4831 11:05:29.138086 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4832 11:05:29.141458 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4833 11:05:29.144868 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4834 11:05:29.148209 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4835 11:05:29.148302
4836 11:05:29.148367
4837 11:05:29.158751 [DQSOSCAuto] RK1, (LSB)MR18= 0x261b, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
4838 11:05:29.161337 CH1 RK1: MR19=808, MR18=261B
4839 11:05:29.164563 CH1_RK1: MR19=0x808, MR18=0x261B, DQSOSC=402, MR23=63, INC=162, DEC=108
4840 11:05:29.167824 [RxdqsGatingPostProcess] freq 600
4841 11:05:29.174702 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4842 11:05:29.178545 Pre-setting of DQS Precalculation
4843 11:05:29.180955 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4844 11:05:29.191176 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4845 11:05:29.197752 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4846 11:05:29.197868
4847 11:05:29.197935
4848 11:05:29.201034 [Calibration Summary] 1200 Mbps
4849 11:05:29.201119 CH 0, Rank 0
4850 11:05:29.204173 SW Impedance : PASS
4851 11:05:29.204257 DUTY Scan : NO K
4852 11:05:29.207445 ZQ Calibration : PASS
4853 11:05:29.211139 Jitter Meter : NO K
4854 11:05:29.211226 CBT Training : PASS
4855 11:05:29.214819 Write leveling : PASS
4856 11:05:29.217373 RX DQS gating : PASS
4857 11:05:29.217459 RX DQ/DQS(RDDQC) : PASS
4858 11:05:29.221033 TX DQ/DQS : PASS
4859 11:05:29.224132 RX DATLAT : PASS
4860 11:05:29.224249 RX DQ/DQS(Engine): PASS
4861 11:05:29.228096 TX OE : NO K
4862 11:05:29.228231 All Pass.
4863 11:05:29.228340
4864 11:05:29.230787 CH 0, Rank 1
4865 11:05:29.230869 SW Impedance : PASS
4866 11:05:29.233962 DUTY Scan : NO K
4867 11:05:29.237417 ZQ Calibration : PASS
4868 11:05:29.237505 Jitter Meter : NO K
4869 11:05:29.240274 CBT Training : PASS
4870 11:05:29.244062 Write leveling : PASS
4871 11:05:29.244167 RX DQS gating : PASS
4872 11:05:29.246905 RX DQ/DQS(RDDQC) : PASS
4873 11:05:29.246994 TX DQ/DQS : PASS
4874 11:05:29.250366 RX DATLAT : PASS
4875 11:05:29.253889 RX DQ/DQS(Engine): PASS
4876 11:05:29.253977 TX OE : NO K
4877 11:05:29.256913 All Pass.
4878 11:05:29.256998
4879 11:05:29.257065 CH 1, Rank 0
4880 11:05:29.260425 SW Impedance : PASS
4881 11:05:29.260514 DUTY Scan : NO K
4882 11:05:29.263898 ZQ Calibration : PASS
4883 11:05:29.266905 Jitter Meter : NO K
4884 11:05:29.266992 CBT Training : PASS
4885 11:05:29.270270 Write leveling : PASS
4886 11:05:29.273345 RX DQS gating : PASS
4887 11:05:29.273429 RX DQ/DQS(RDDQC) : PASS
4888 11:05:29.276772 TX DQ/DQS : PASS
4889 11:05:29.279916 RX DATLAT : PASS
4890 11:05:29.280024 RX DQ/DQS(Engine): PASS
4891 11:05:29.283977 TX OE : NO K
4892 11:05:29.284062 All Pass.
4893 11:05:29.284128
4894 11:05:29.286902 CH 1, Rank 1
4895 11:05:29.286982 SW Impedance : PASS
4896 11:05:29.290282 DUTY Scan : NO K
4897 11:05:29.292773 ZQ Calibration : PASS
4898 11:05:29.292855 Jitter Meter : NO K
4899 11:05:29.296119 CBT Training : PASS
4900 11:05:29.299534 Write leveling : PASS
4901 11:05:29.299647 RX DQS gating : PASS
4902 11:05:29.303193 RX DQ/DQS(RDDQC) : PASS
4903 11:05:29.305910 TX DQ/DQS : PASS
4904 11:05:29.305993 RX DATLAT : PASS
4905 11:05:29.309710 RX DQ/DQS(Engine): PASS
4906 11:05:29.312629 TX OE : NO K
4907 11:05:29.312711 All Pass.
4908 11:05:29.312775
4909 11:05:29.312836 DramC Write-DBI off
4910 11:05:29.315850 PER_BANK_REFRESH: Hybrid Mode
4911 11:05:29.319244 TX_TRACKING: ON
4912 11:05:29.326374 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4913 11:05:29.329478 [FAST_K] Save calibration result to emmc
4914 11:05:29.335974 dramc_set_vcore_voltage set vcore to 662500
4915 11:05:29.336069 Read voltage for 933, 3
4916 11:05:29.338987 Vio18 = 0
4917 11:05:29.339069 Vcore = 662500
4918 11:05:29.339134 Vdram = 0
4919 11:05:29.342505 Vddq = 0
4920 11:05:29.342589 Vmddr = 0
4921 11:05:29.345535 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4922 11:05:29.352181 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4923 11:05:29.355824 MEM_TYPE=3, freq_sel=17
4924 11:05:29.359158 sv_algorithm_assistance_LP4_1600
4925 11:05:29.362035 ============ PULL DRAM RESETB DOWN ============
4926 11:05:29.365437 ========== PULL DRAM RESETB DOWN end =========
4927 11:05:29.371993 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4928 11:05:29.375478 ===================================
4929 11:05:29.375570 LPDDR4 DRAM CONFIGURATION
4930 11:05:29.378280 ===================================
4931 11:05:29.381701 EX_ROW_EN[0] = 0x0
4932 11:05:29.381785 EX_ROW_EN[1] = 0x0
4933 11:05:29.384993 LP4Y_EN = 0x0
4934 11:05:29.388398 WORK_FSP = 0x0
4935 11:05:29.388482 WL = 0x3
4936 11:05:29.391689 RL = 0x3
4937 11:05:29.391773 BL = 0x2
4938 11:05:29.395215 RPST = 0x0
4939 11:05:29.395298 RD_PRE = 0x0
4940 11:05:29.398315 WR_PRE = 0x1
4941 11:05:29.398398 WR_PST = 0x0
4942 11:05:29.401781 DBI_WR = 0x0
4943 11:05:29.401864 DBI_RD = 0x0
4944 11:05:29.405316 OTF = 0x1
4945 11:05:29.408506 ===================================
4946 11:05:29.411603 ===================================
4947 11:05:29.411717 ANA top config
4948 11:05:29.414721 ===================================
4949 11:05:29.417973 DLL_ASYNC_EN = 0
4950 11:05:29.421703 ALL_SLAVE_EN = 1
4951 11:05:29.421790 NEW_RANK_MODE = 1
4952 11:05:29.424832 DLL_IDLE_MODE = 1
4953 11:05:29.428035 LP45_APHY_COMB_EN = 1
4954 11:05:29.431989 TX_ODT_DIS = 1
4955 11:05:29.434733 NEW_8X_MODE = 1
4956 11:05:29.437695 ===================================
4957 11:05:29.441457 ===================================
4958 11:05:29.444358 data_rate = 1866
4959 11:05:29.444458 CKR = 1
4960 11:05:29.448193 DQ_P2S_RATIO = 8
4961 11:05:29.451059 ===================================
4962 11:05:29.454478 CA_P2S_RATIO = 8
4963 11:05:29.457539 DQ_CA_OPEN = 0
4964 11:05:29.460999 DQ_SEMI_OPEN = 0
4965 11:05:29.463991 CA_SEMI_OPEN = 0
4966 11:05:29.464076 CA_FULL_RATE = 0
4967 11:05:29.468248 DQ_CKDIV4_EN = 1
4968 11:05:29.470924 CA_CKDIV4_EN = 1
4969 11:05:29.474482 CA_PREDIV_EN = 0
4970 11:05:29.477287 PH8_DLY = 0
4971 11:05:29.480857 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4972 11:05:29.480942 DQ_AAMCK_DIV = 4
4973 11:05:29.484523 CA_AAMCK_DIV = 4
4974 11:05:29.487685 CA_ADMCK_DIV = 4
4975 11:05:29.490881 DQ_TRACK_CA_EN = 0
4976 11:05:29.493890 CA_PICK = 933
4977 11:05:29.497157 CA_MCKIO = 933
4978 11:05:29.497241 MCKIO_SEMI = 0
4979 11:05:29.501493 PLL_FREQ = 3732
4980 11:05:29.503848 DQ_UI_PI_RATIO = 32
4981 11:05:29.507180 CA_UI_PI_RATIO = 0
4982 11:05:29.510553 ===================================
4983 11:05:29.514088 ===================================
4984 11:05:29.517585 memory_type:LPDDR4
4985 11:05:29.517671 GP_NUM : 10
4986 11:05:29.520414 SRAM_EN : 1
4987 11:05:29.523830 MD32_EN : 0
4988 11:05:29.526858 ===================================
4989 11:05:29.526946 [ANA_INIT] >>>>>>>>>>>>>>
4990 11:05:29.530759 <<<<<< [CONFIGURE PHASE]: ANA_TX
4991 11:05:29.533766 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4992 11:05:29.537017 ===================================
4993 11:05:29.540537 data_rate = 1866,PCW = 0X8f00
4994 11:05:29.544523 ===================================
4995 11:05:29.546915 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4996 11:05:29.553528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4997 11:05:29.560076 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4998 11:05:29.563352 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4999 11:05:29.566650 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5000 11:05:29.571045 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5001 11:05:29.573489 [ANA_INIT] flow start
5002 11:05:29.573576 [ANA_INIT] PLL >>>>>>>>
5003 11:05:29.576147 [ANA_INIT] PLL <<<<<<<<
5004 11:05:29.580095 [ANA_INIT] MIDPI >>>>>>>>
5005 11:05:29.580185 [ANA_INIT] MIDPI <<<<<<<<
5006 11:05:29.582930 [ANA_INIT] DLL >>>>>>>>
5007 11:05:29.586685 [ANA_INIT] flow end
5008 11:05:29.589603 ============ LP4 DIFF to SE enter ============
5009 11:05:29.593099 ============ LP4 DIFF to SE exit ============
5010 11:05:29.596063 [ANA_INIT] <<<<<<<<<<<<<
5011 11:05:29.599111 [Flow] Enable top DCM control >>>>>
5012 11:05:29.602520 [Flow] Enable top DCM control <<<<<
5013 11:05:29.605616 Enable DLL master slave shuffle
5014 11:05:29.612252 ==============================================================
5015 11:05:29.612373 Gating Mode config
5016 11:05:29.618884 ==============================================================
5017 11:05:29.619009 Config description:
5018 11:05:29.628877 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5019 11:05:29.635854 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5020 11:05:29.642211 SELPH_MODE 0: By rank 1: By Phase
5021 11:05:29.645560 ==============================================================
5022 11:05:29.648310 GAT_TRACK_EN = 1
5023 11:05:29.652147 RX_GATING_MODE = 2
5024 11:05:29.655698 RX_GATING_TRACK_MODE = 2
5025 11:05:29.658491 SELPH_MODE = 1
5026 11:05:29.661893 PICG_EARLY_EN = 1
5027 11:05:29.665182 VALID_LAT_VALUE = 1
5028 11:05:29.672147 ==============================================================
5029 11:05:29.675398 Enter into Gating configuration >>>>
5030 11:05:29.678501 Exit from Gating configuration <<<<
5031 11:05:29.681377 Enter into DVFS_PRE_config >>>>>
5032 11:05:29.691115 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5033 11:05:29.694836 Exit from DVFS_PRE_config <<<<<
5034 11:05:29.697970 Enter into PICG configuration >>>>
5035 11:05:29.701175 Exit from PICG configuration <<<<
5036 11:05:29.705124 [RX_INPUT] configuration >>>>>
5037 11:05:29.707901 [RX_INPUT] configuration <<<<<
5038 11:05:29.711358 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5039 11:05:29.717796 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5040 11:05:29.724548 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5041 11:05:29.730678 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5042 11:05:29.734485 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5043 11:05:29.740647 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5044 11:05:29.744233 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5045 11:05:29.750253 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5046 11:05:29.753765 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5047 11:05:29.757170 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5048 11:05:29.760500 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5049 11:05:29.768434 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5050 11:05:29.770204 ===================================
5051 11:05:29.774407 LPDDR4 DRAM CONFIGURATION
5052 11:05:29.777228 ===================================
5053 11:05:29.777357 EX_ROW_EN[0] = 0x0
5054 11:05:29.780054 EX_ROW_EN[1] = 0x0
5055 11:05:29.780186 LP4Y_EN = 0x0
5056 11:05:29.783378 WORK_FSP = 0x0
5057 11:05:29.783491 WL = 0x3
5058 11:05:29.786871 RL = 0x3
5059 11:05:29.786954 BL = 0x2
5060 11:05:29.789880 RPST = 0x0
5061 11:05:29.789961 RD_PRE = 0x0
5062 11:05:29.793984 WR_PRE = 0x1
5063 11:05:29.794080 WR_PST = 0x0
5064 11:05:29.797369 DBI_WR = 0x0
5065 11:05:29.797460 DBI_RD = 0x0
5066 11:05:29.799798 OTF = 0x1
5067 11:05:29.803136 ===================================
5068 11:05:29.806877 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5069 11:05:29.810441 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5070 11:05:29.816720 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5071 11:05:29.819645 ===================================
5072 11:05:29.822862 LPDDR4 DRAM CONFIGURATION
5073 11:05:29.826688 ===================================
5074 11:05:29.826794 EX_ROW_EN[0] = 0x10
5075 11:05:29.829490 EX_ROW_EN[1] = 0x0
5076 11:05:29.829581 LP4Y_EN = 0x0
5077 11:05:29.832837 WORK_FSP = 0x0
5078 11:05:29.832929 WL = 0x3
5079 11:05:29.836155 RL = 0x3
5080 11:05:29.836247 BL = 0x2
5081 11:05:29.839591 RPST = 0x0
5082 11:05:29.839729 RD_PRE = 0x0
5083 11:05:29.842679 WR_PRE = 0x1
5084 11:05:29.846317 WR_PST = 0x0
5085 11:05:29.846428 DBI_WR = 0x0
5086 11:05:29.849532 DBI_RD = 0x0
5087 11:05:29.849627 OTF = 0x1
5088 11:05:29.852829 ===================================
5089 11:05:29.859240 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5090 11:05:29.862969 nWR fixed to 30
5091 11:05:29.866416 [ModeRegInit_LP4] CH0 RK0
5092 11:05:29.866523 [ModeRegInit_LP4] CH0 RK1
5093 11:05:29.869410 [ModeRegInit_LP4] CH1 RK0
5094 11:05:29.873093 [ModeRegInit_LP4] CH1 RK1
5095 11:05:29.873198 match AC timing 9
5096 11:05:29.879984 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5097 11:05:29.883160 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5098 11:05:29.886776 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5099 11:05:29.892602 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5100 11:05:29.895616 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5101 11:05:29.895768 ==
5102 11:05:29.899070 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 11:05:29.902771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 11:05:29.902862 ==
5105 11:05:29.908681 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5106 11:05:29.916040 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5107 11:05:29.918514 [CA 0] Center 37 (7~68) winsize 62
5108 11:05:29.921788 [CA 1] Center 37 (7~68) winsize 62
5109 11:05:29.925493 [CA 2] Center 35 (5~65) winsize 61
5110 11:05:29.928647 [CA 3] Center 35 (5~65) winsize 61
5111 11:05:29.931976 [CA 4] Center 33 (3~64) winsize 62
5112 11:05:29.935316 [CA 5] Center 33 (4~63) winsize 60
5113 11:05:29.935408
5114 11:05:29.938715 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5115 11:05:29.938804
5116 11:05:29.941603 [CATrainingPosCal] consider 1 rank data
5117 11:05:29.945517 u2DelayCellTimex100 = 270/100 ps
5118 11:05:29.948642 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5119 11:05:29.951564 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5120 11:05:29.955169 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5121 11:05:29.961466 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5122 11:05:29.965057 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5123 11:05:29.967901 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5124 11:05:29.968005
5125 11:05:29.971567 CA PerBit enable=1, Macro0, CA PI delay=33
5126 11:05:29.971716
5127 11:05:29.974505 [CBTSetCACLKResult] CA Dly = 33
5128 11:05:29.974597 CS Dly: 7 (0~38)
5129 11:05:29.977788 ==
5130 11:05:29.977891 Dram Type= 6, Freq= 0, CH_0, rank 1
5131 11:05:29.984725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5132 11:05:29.984862 ==
5133 11:05:29.987563 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5134 11:05:29.994391 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5135 11:05:29.998228 [CA 0] Center 37 (7~68) winsize 62
5136 11:05:30.001427 [CA 1] Center 37 (7~68) winsize 62
5137 11:05:30.004533 [CA 2] Center 34 (4~65) winsize 62
5138 11:05:30.007890 [CA 3] Center 34 (4~65) winsize 62
5139 11:05:30.011097 [CA 4] Center 33 (3~64) winsize 62
5140 11:05:30.014194 [CA 5] Center 33 (3~63) winsize 61
5141 11:05:30.014297
5142 11:05:30.018425 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5143 11:05:30.018570
5144 11:05:30.021413 [CATrainingPosCal] consider 2 rank data
5145 11:05:30.024697 u2DelayCellTimex100 = 270/100 ps
5146 11:05:30.027855 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5147 11:05:30.034219 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5148 11:05:30.037589 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5149 11:05:30.040670 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5150 11:05:30.044206 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5151 11:05:30.047607 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5152 11:05:30.047737
5153 11:05:30.050838 CA PerBit enable=1, Macro0, CA PI delay=33
5154 11:05:30.050926
5155 11:05:30.053983 [CBTSetCACLKResult] CA Dly = 33
5156 11:05:30.057601 CS Dly: 7 (0~39)
5157 11:05:30.057691
5158 11:05:30.060440 ----->DramcWriteLeveling(PI) begin...
5159 11:05:30.060558 ==
5160 11:05:30.064016 Dram Type= 6, Freq= 0, CH_0, rank 0
5161 11:05:30.067352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 11:05:30.067443 ==
5163 11:05:30.070586 Write leveling (Byte 0): 35 => 35
5164 11:05:30.073981 Write leveling (Byte 1): 27 => 27
5165 11:05:30.077738 DramcWriteLeveling(PI) end<-----
5166 11:05:30.077840
5167 11:05:30.077929 ==
5168 11:05:30.081069 Dram Type= 6, Freq= 0, CH_0, rank 0
5169 11:05:30.083931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 11:05:30.084025 ==
5171 11:05:30.087793 [Gating] SW mode calibration
5172 11:05:30.093717 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5173 11:05:30.100499 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5174 11:05:30.104202 0 14 0 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
5175 11:05:30.107030 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5176 11:05:30.113452 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 11:05:30.117039 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 11:05:30.123793 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 11:05:30.126859 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 11:05:30.129739 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 11:05:30.133287 0 14 28 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 1)
5182 11:05:30.140392 0 15 0 | B1->B0 | 3232 2626 | 1 0 | (1 1) (0 0)
5183 11:05:30.143326 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5184 11:05:30.149546 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 11:05:30.152556 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 11:05:30.156634 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 11:05:30.162787 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 11:05:30.166067 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 11:05:30.169403 0 15 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5190 11:05:30.175803 1 0 0 | B1->B0 | 2c2b 4040 | 1 0 | (1 1) (0 0)
5191 11:05:30.178852 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 11:05:30.182723 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 11:05:30.188782 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 11:05:30.193124 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 11:05:30.195991 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 11:05:30.202476 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 11:05:30.205825 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5198 11:05:30.208996 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5199 11:05:30.215181 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5200 11:05:30.218589 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 11:05:30.222104 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 11:05:30.228541 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 11:05:30.232232 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 11:05:30.235093 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 11:05:30.238707 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 11:05:30.245456 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 11:05:30.248650 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 11:05:30.251898 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 11:05:30.258383 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 11:05:30.261814 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 11:05:30.265000 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 11:05:30.271714 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 11:05:30.275294 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5214 11:05:30.278610 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5215 11:05:30.281944 Total UI for P1: 0, mck2ui 16
5216 11:05:30.285508 best dqsien dly found for B0: ( 1, 2, 28)
5217 11:05:30.291188 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 11:05:30.294832 Total UI for P1: 0, mck2ui 16
5219 11:05:30.298098 best dqsien dly found for B1: ( 1, 2, 30)
5220 11:05:30.301548 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5221 11:05:30.304766 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5222 11:05:30.304853
5223 11:05:30.307941 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5224 11:05:30.312877 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5225 11:05:30.314318 [Gating] SW calibration Done
5226 11:05:30.314404 ==
5227 11:05:30.318138 Dram Type= 6, Freq= 0, CH_0, rank 0
5228 11:05:30.320809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5229 11:05:30.320898 ==
5230 11:05:30.324115 RX Vref Scan: 0
5231 11:05:30.324220
5232 11:05:30.327889 RX Vref 0 -> 0, step: 1
5233 11:05:30.327976
5234 11:05:30.328062 RX Delay -80 -> 252, step: 8
5235 11:05:30.334470 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5236 11:05:30.337708 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5237 11:05:30.341132 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5238 11:05:30.344093 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5239 11:05:30.347618 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5240 11:05:30.350747 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5241 11:05:30.357465 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5242 11:05:30.360987 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5243 11:05:30.364268 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5244 11:05:30.367192 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5245 11:05:30.370777 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5246 11:05:30.377360 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5247 11:05:30.380957 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5248 11:05:30.383987 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5249 11:05:30.387045 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5250 11:05:30.390558 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5251 11:05:30.393762 ==
5252 11:05:30.397128 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 11:05:30.400578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 11:05:30.400664 ==
5255 11:05:30.400750 DQS Delay:
5256 11:05:30.404341 DQS0 = 0, DQS1 = 0
5257 11:05:30.404426 DQM Delay:
5258 11:05:30.406925 DQM0 = 96, DQM1 = 86
5259 11:05:30.407013 DQ Delay:
5260 11:05:30.410550 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5261 11:05:30.413952 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =103
5262 11:05:30.417140 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5263 11:05:30.419970 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5264 11:05:30.420055
5265 11:05:30.420140
5266 11:05:30.420220 ==
5267 11:05:30.423369 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 11:05:30.426398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 11:05:30.426484 ==
5270 11:05:30.426570
5271 11:05:30.429908
5272 11:05:30.430024 TX Vref Scan disable
5273 11:05:30.433344 == TX Byte 0 ==
5274 11:05:30.436335 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5275 11:05:30.439584 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5276 11:05:30.444117 == TX Byte 1 ==
5277 11:05:30.446413 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5278 11:05:30.449491 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5279 11:05:30.449581 ==
5280 11:05:30.452773 Dram Type= 6, Freq= 0, CH_0, rank 0
5281 11:05:30.459902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 11:05:30.460001 ==
5283 11:05:30.460068
5284 11:05:30.460129
5285 11:05:30.462867 TX Vref Scan disable
5286 11:05:30.462949 == TX Byte 0 ==
5287 11:05:30.469467 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5288 11:05:30.472731 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5289 11:05:30.472825 == TX Byte 1 ==
5290 11:05:30.478942 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5291 11:05:30.482576 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5292 11:05:30.482662
5293 11:05:30.482727 [DATLAT]
5294 11:05:30.485764 Freq=933, CH0 RK0
5295 11:05:30.485884
5296 11:05:30.485950 DATLAT Default: 0xd
5297 11:05:30.488781 0, 0xFFFF, sum = 0
5298 11:05:30.488866 1, 0xFFFF, sum = 0
5299 11:05:30.492119 2, 0xFFFF, sum = 0
5300 11:05:30.495466 3, 0xFFFF, sum = 0
5301 11:05:30.495553 4, 0xFFFF, sum = 0
5302 11:05:30.499234 5, 0xFFFF, sum = 0
5303 11:05:30.499319 6, 0xFFFF, sum = 0
5304 11:05:30.502420 7, 0xFFFF, sum = 0
5305 11:05:30.502504 8, 0xFFFF, sum = 0
5306 11:05:30.505225 9, 0xFFFF, sum = 0
5307 11:05:30.505309 10, 0x0, sum = 1
5308 11:05:30.509022 11, 0x0, sum = 2
5309 11:05:30.509111 12, 0x0, sum = 3
5310 11:05:30.512741 13, 0x0, sum = 4
5311 11:05:30.512830 best_step = 11
5312 11:05:30.512895
5313 11:05:30.512956 ==
5314 11:05:30.515778 Dram Type= 6, Freq= 0, CH_0, rank 0
5315 11:05:30.518930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 11:05:30.519013 ==
5317 11:05:30.522289 RX Vref Scan: 1
5318 11:05:30.522376
5319 11:05:30.525015 RX Vref 0 -> 0, step: 1
5320 11:05:30.525098
5321 11:05:30.525162 RX Delay -61 -> 252, step: 4
5322 11:05:30.525222
5323 11:05:30.528497 Set Vref, RX VrefLevel [Byte0]: 59
5324 11:05:30.531621 [Byte1]: 58
5325 11:05:30.536980
5326 11:05:30.537072 Final RX Vref Byte 0 = 59 to rank0
5327 11:05:30.540166 Final RX Vref Byte 1 = 58 to rank0
5328 11:05:30.543738 Final RX Vref Byte 0 = 59 to rank1
5329 11:05:30.546546 Final RX Vref Byte 1 = 58 to rank1==
5330 11:05:30.549631 Dram Type= 6, Freq= 0, CH_0, rank 0
5331 11:05:30.557138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5332 11:05:30.557253 ==
5333 11:05:30.557320 DQS Delay:
5334 11:05:30.557380 DQS0 = 0, DQS1 = 0
5335 11:05:30.559730 DQM Delay:
5336 11:05:30.559813 DQM0 = 97, DQM1 = 86
5337 11:05:30.563488 DQ Delay:
5338 11:05:30.566310 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =92
5339 11:05:30.569675 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5340 11:05:30.572745 DQ8 =80, DQ9 =78, DQ10 =86, DQ11 =82
5341 11:05:30.576460 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =90
5342 11:05:30.576552
5343 11:05:30.576618
5344 11:05:30.583206 [DQSOSCAuto] RK0, (LSB)MR18= 0x260d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 409 ps
5345 11:05:30.586153 CH0 RK0: MR19=505, MR18=260D
5346 11:05:30.592961 CH0_RK0: MR19=0x505, MR18=0x260D, DQSOSC=409, MR23=63, INC=64, DEC=43
5347 11:05:30.593076
5348 11:05:30.595882 ----->DramcWriteLeveling(PI) begin...
5349 11:05:30.595968 ==
5350 11:05:30.599333 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 11:05:30.602602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 11:05:30.602693 ==
5353 11:05:30.605856 Write leveling (Byte 0): 32 => 32
5354 11:05:30.609121 Write leveling (Byte 1): 31 => 31
5355 11:05:30.612532 DramcWriteLeveling(PI) end<-----
5356 11:05:30.612626
5357 11:05:30.612690 ==
5358 11:05:30.615597 Dram Type= 6, Freq= 0, CH_0, rank 1
5359 11:05:30.618862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 11:05:30.622213 ==
5361 11:05:30.622302 [Gating] SW mode calibration
5362 11:05:30.632350 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5363 11:05:30.636035 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5364 11:05:30.638766 0 14 0 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
5365 11:05:30.645483 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 11:05:30.648987 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 11:05:30.652219 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 11:05:30.658633 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 11:05:30.661763 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 11:05:30.665441 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 11:05:30.671481 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
5372 11:05:30.674873 0 15 0 | B1->B0 | 2f2f 2c2c | 0 0 | (0 0) (1 0)
5373 11:05:30.678419 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 11:05:30.684635 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 11:05:30.688443 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 11:05:30.691965 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 11:05:30.697929 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 11:05:30.701349 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 11:05:30.704780 0 15 28 | B1->B0 | 2828 2e2e | 0 0 | (1 1) (0 0)
5380 11:05:30.711258 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5381 11:05:30.714958 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 11:05:30.718206 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 11:05:30.724484 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 11:05:30.727802 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 11:05:30.731593 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 11:05:30.738046 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 11:05:30.740833 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 11:05:30.744538 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5389 11:05:30.751427 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 11:05:30.754093 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 11:05:30.757977 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 11:05:30.764538 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 11:05:30.767528 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 11:05:30.771083 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 11:05:30.777596 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 11:05:30.780768 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 11:05:30.784022 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 11:05:30.790985 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 11:05:30.793725 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 11:05:30.797260 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 11:05:30.803848 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 11:05:30.806956 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 11:05:30.810647 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5404 11:05:30.816554 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5405 11:05:30.819966 Total UI for P1: 0, mck2ui 16
5406 11:05:30.823345 best dqsien dly found for B0: ( 1, 2, 28)
5407 11:05:30.826855 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 11:05:30.829855 Total UI for P1: 0, mck2ui 16
5409 11:05:30.833607 best dqsien dly found for B1: ( 1, 2, 30)
5410 11:05:30.836705 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5411 11:05:30.840185 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5412 11:05:30.840275
5413 11:05:30.842910 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5414 11:05:30.849654 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5415 11:05:30.849761 [Gating] SW calibration Done
5416 11:05:30.849829 ==
5417 11:05:30.853583 Dram Type= 6, Freq= 0, CH_0, rank 1
5418 11:05:30.859648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5419 11:05:30.859798 ==
5420 11:05:30.859866 RX Vref Scan: 0
5421 11:05:30.859929
5422 11:05:30.862622 RX Vref 0 -> 0, step: 1
5423 11:05:30.862705
5424 11:05:30.865958 RX Delay -80 -> 252, step: 8
5425 11:05:30.869837 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5426 11:05:30.872521 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5427 11:05:30.875875 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5428 11:05:30.879620 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5429 11:05:30.885935 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5430 11:05:30.889135 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5431 11:05:30.892501 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5432 11:05:30.895676 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5433 11:05:30.898956 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5434 11:05:30.905792 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5435 11:05:30.909117 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5436 11:05:30.912400 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5437 11:05:30.915912 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5438 11:05:30.918696 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5439 11:05:30.925544 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5440 11:05:30.929029 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5441 11:05:30.929118 ==
5442 11:05:30.931939 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 11:05:30.935549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 11:05:30.935664 ==
5445 11:05:30.935798 DQS Delay:
5446 11:05:30.938582 DQS0 = 0, DQS1 = 0
5447 11:05:30.938691 DQM Delay:
5448 11:05:30.941723 DQM0 = 96, DQM1 = 90
5449 11:05:30.941821 DQ Delay:
5450 11:05:30.945039 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5451 11:05:30.948417 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5452 11:05:30.951484 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5453 11:05:30.954639 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5454 11:05:30.954724
5455 11:05:30.954790
5456 11:05:30.954850 ==
5457 11:05:30.958096 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 11:05:30.965076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 11:05:30.965175 ==
5460 11:05:30.965242
5461 11:05:30.965304
5462 11:05:30.965362 TX Vref Scan disable
5463 11:05:30.968511 == TX Byte 0 ==
5464 11:05:30.971365 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5465 11:05:30.978595 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5466 11:05:30.978688 == TX Byte 1 ==
5467 11:05:30.981560 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5468 11:05:30.988424 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5469 11:05:30.988528 ==
5470 11:05:30.990990 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 11:05:30.994523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 11:05:30.994608 ==
5473 11:05:30.994674
5474 11:05:30.994736
5475 11:05:30.997615 TX Vref Scan disable
5476 11:05:31.001505 == TX Byte 0 ==
5477 11:05:31.004353 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5478 11:05:31.008102 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5479 11:05:31.010995 == TX Byte 1 ==
5480 11:05:31.014382 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5481 11:05:31.017530 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5482 11:05:31.017614
5483 11:05:31.017680 [DATLAT]
5484 11:05:31.020993 Freq=933, CH0 RK1
5485 11:05:31.021078
5486 11:05:31.024211 DATLAT Default: 0xb
5487 11:05:31.024296 0, 0xFFFF, sum = 0
5488 11:05:31.027380 1, 0xFFFF, sum = 0
5489 11:05:31.027466 2, 0xFFFF, sum = 0
5490 11:05:31.031034 3, 0xFFFF, sum = 0
5491 11:05:31.031120 4, 0xFFFF, sum = 0
5492 11:05:31.034026 5, 0xFFFF, sum = 0
5493 11:05:31.034111 6, 0xFFFF, sum = 0
5494 11:05:31.037790 7, 0xFFFF, sum = 0
5495 11:05:31.037875 8, 0xFFFF, sum = 0
5496 11:05:31.040470 9, 0xFFFF, sum = 0
5497 11:05:31.040554 10, 0x0, sum = 1
5498 11:05:31.043949 11, 0x0, sum = 2
5499 11:05:31.044035 12, 0x0, sum = 3
5500 11:05:31.047097 13, 0x0, sum = 4
5501 11:05:31.047213 best_step = 11
5502 11:05:31.047281
5503 11:05:31.047343 ==
5504 11:05:31.050192 Dram Type= 6, Freq= 0, CH_0, rank 1
5505 11:05:31.057067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 11:05:31.057156 ==
5507 11:05:31.057239 RX Vref Scan: 0
5508 11:05:31.057302
5509 11:05:31.059865 RX Vref 0 -> 0, step: 1
5510 11:05:31.059948
5511 11:05:31.063454 RX Delay -61 -> 252, step: 4
5512 11:05:31.066761 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5513 11:05:31.070874 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5514 11:05:31.076927 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5515 11:05:31.080467 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5516 11:05:31.082796 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5517 11:05:31.086203 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5518 11:05:31.089820 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5519 11:05:31.096450 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5520 11:05:31.099923 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5521 11:05:31.103141 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5522 11:05:31.106195 iDelay=203, Bit 10, Center 88 (-9 ~ 186) 196
5523 11:05:31.109543 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5524 11:05:31.116202 iDelay=203, Bit 12, Center 94 (-1 ~ 190) 192
5525 11:05:31.119399 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5526 11:05:31.122590 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5527 11:05:31.126512 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5528 11:05:31.126599 ==
5529 11:05:31.129386 Dram Type= 6, Freq= 0, CH_0, rank 1
5530 11:05:31.132809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5531 11:05:31.135880 ==
5532 11:05:31.135967 DQS Delay:
5533 11:05:31.136033 DQS0 = 0, DQS1 = 0
5534 11:05:31.139246 DQM Delay:
5535 11:05:31.139328 DQM0 = 95, DQM1 = 87
5536 11:05:31.142301 DQ Delay:
5537 11:05:31.145943 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5538 11:05:31.146028 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5539 11:05:31.148885 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =82
5540 11:05:31.155331 DQ12 =94, DQ13 =92, DQ14 =96, DQ15 =92
5541 11:05:31.155417
5542 11:05:31.155482
5543 11:05:31.162269 [DQSOSCAuto] RK1, (LSB)MR18= 0x20f1, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 411 ps
5544 11:05:31.165688 CH0 RK1: MR19=504, MR18=20F1
5545 11:05:31.171920 CH0_RK1: MR19=0x504, MR18=0x20F1, DQSOSC=411, MR23=63, INC=64, DEC=42
5546 11:05:31.175098 [RxdqsGatingPostProcess] freq 933
5547 11:05:31.179022 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5548 11:05:31.182241 best DQS0 dly(2T, 0.5T) = (0, 10)
5549 11:05:31.185281 best DQS1 dly(2T, 0.5T) = (0, 10)
5550 11:05:31.188674 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5551 11:05:31.191573 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5552 11:05:31.194913 best DQS0 dly(2T, 0.5T) = (0, 10)
5553 11:05:31.198652 best DQS1 dly(2T, 0.5T) = (0, 10)
5554 11:05:31.201886 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5555 11:05:31.205079 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5556 11:05:31.208015 Pre-setting of DQS Precalculation
5557 11:05:31.211387 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5558 11:05:31.214620 ==
5559 11:05:31.217940 Dram Type= 6, Freq= 0, CH_1, rank 0
5560 11:05:31.221444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 11:05:31.221528 ==
5562 11:05:31.224864 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5563 11:05:31.231510 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5564 11:05:31.235272 [CA 0] Center 36 (6~67) winsize 62
5565 11:05:31.238089 [CA 1] Center 37 (6~68) winsize 63
5566 11:05:31.241329 [CA 2] Center 34 (4~65) winsize 62
5567 11:05:31.244688 [CA 3] Center 33 (3~64) winsize 62
5568 11:05:31.248089 [CA 4] Center 34 (4~64) winsize 61
5569 11:05:31.251079 [CA 5] Center 33 (3~64) winsize 62
5570 11:05:31.251164
5571 11:05:31.254698 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5572 11:05:31.254782
5573 11:05:31.257992 [CATrainingPosCal] consider 1 rank data
5574 11:05:31.261447 u2DelayCellTimex100 = 270/100 ps
5575 11:05:31.264322 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5576 11:05:31.271274 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5577 11:05:31.274718 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5578 11:05:31.277804 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5579 11:05:31.281194 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5580 11:05:31.285012 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5581 11:05:31.285095
5582 11:05:31.287712 CA PerBit enable=1, Macro0, CA PI delay=33
5583 11:05:31.287810
5584 11:05:31.291423 [CBTSetCACLKResult] CA Dly = 33
5585 11:05:31.294287 CS Dly: 5 (0~36)
5586 11:05:31.294369 ==
5587 11:05:31.297938 Dram Type= 6, Freq= 0, CH_1, rank 1
5588 11:05:31.300799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5589 11:05:31.300883 ==
5590 11:05:31.308524 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5591 11:05:31.311106 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5592 11:05:31.314831 [CA 0] Center 36 (6~67) winsize 62
5593 11:05:31.318600 [CA 1] Center 37 (7~67) winsize 61
5594 11:05:31.321593 [CA 2] Center 34 (4~65) winsize 62
5595 11:05:31.325500 [CA 3] Center 33 (3~64) winsize 62
5596 11:05:31.327865 [CA 4] Center 34 (3~65) winsize 63
5597 11:05:31.331126 [CA 5] Center 33 (3~64) winsize 62
5598 11:05:31.331210
5599 11:05:31.334362 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5600 11:05:31.334445
5601 11:05:31.338551 [CATrainingPosCal] consider 2 rank data
5602 11:05:31.341578 u2DelayCellTimex100 = 270/100 ps
5603 11:05:31.347765 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5604 11:05:31.350772 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5605 11:05:31.354270 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5606 11:05:31.358143 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5607 11:05:31.360609 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5608 11:05:31.364277 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5609 11:05:31.364361
5610 11:05:31.367831 CA PerBit enable=1, Macro0, CA PI delay=33
5611 11:05:31.367915
5612 11:05:31.370986 [CBTSetCACLKResult] CA Dly = 33
5613 11:05:31.374717 CS Dly: 6 (0~39)
5614 11:05:31.374800
5615 11:05:31.377319 ----->DramcWriteLeveling(PI) begin...
5616 11:05:31.377402 ==
5617 11:05:31.380907 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 11:05:31.383975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 11:05:31.384058 ==
5620 11:05:31.386968 Write leveling (Byte 0): 26 => 26
5621 11:05:31.390243 Write leveling (Byte 1): 28 => 28
5622 11:05:31.394291 DramcWriteLeveling(PI) end<-----
5623 11:05:31.394375
5624 11:05:31.394440 ==
5625 11:05:31.397399 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 11:05:31.400308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 11:05:31.400391 ==
5628 11:05:31.404027 [Gating] SW mode calibration
5629 11:05:31.410573 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5630 11:05:31.417296 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5631 11:05:31.420112 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5632 11:05:31.426861 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 11:05:31.430011 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 11:05:31.433332 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 11:05:31.440268 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 11:05:31.443319 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 11:05:31.446867 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5638 11:05:31.453294 0 14 28 | B1->B0 | 2e2e 2d2d | 0 0 | (1 0) (1 1)
5639 11:05:31.456074 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5640 11:05:31.459516 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 11:05:31.466161 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 11:05:31.470180 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 11:05:31.472770 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 11:05:31.479020 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 11:05:31.482967 0 15 24 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
5646 11:05:31.486147 0 15 28 | B1->B0 | 3737 3b3b | 1 0 | (0 0) (0 0)
5647 11:05:31.492911 1 0 0 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
5648 11:05:31.495641 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 11:05:31.499178 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 11:05:31.506013 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 11:05:31.508939 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 11:05:31.512439 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 11:05:31.518833 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5654 11:05:31.522375 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5655 11:05:31.525681 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 11:05:31.531907 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 11:05:31.535488 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 11:05:31.538482 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 11:05:31.545497 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 11:05:31.548665 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 11:05:31.551439 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 11:05:31.557947 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 11:05:31.561505 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 11:05:31.564866 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 11:05:31.571321 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 11:05:31.574396 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 11:05:31.578218 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 11:05:31.584496 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 11:05:31.588090 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5670 11:05:31.591101 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5671 11:05:31.597400 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5672 11:05:31.597489 Total UI for P1: 0, mck2ui 16
5673 11:05:31.603982 best dqsien dly found for B0: ( 1, 2, 26)
5674 11:05:31.604069 Total UI for P1: 0, mck2ui 16
5675 11:05:31.610958 best dqsien dly found for B1: ( 1, 2, 28)
5676 11:05:31.614440 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5677 11:05:31.617155 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5678 11:05:31.617240
5679 11:05:31.620363 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5680 11:05:31.623896 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5681 11:05:31.628013 [Gating] SW calibration Done
5682 11:05:31.628098 ==
5683 11:05:31.630323 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 11:05:31.634059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 11:05:31.634143 ==
5686 11:05:31.637492 RX Vref Scan: 0
5687 11:05:31.637578
5688 11:05:31.637644 RX Vref 0 -> 0, step: 1
5689 11:05:31.640743
5690 11:05:31.640824 RX Delay -80 -> 252, step: 8
5691 11:05:31.646946 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5692 11:05:31.650131 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5693 11:05:31.653935 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5694 11:05:31.657088 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5695 11:05:31.660023 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5696 11:05:31.664242 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5697 11:05:31.669891 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5698 11:05:31.673290 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5699 11:05:31.676748 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5700 11:05:31.680045 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5701 11:05:31.683375 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5702 11:05:31.689800 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5703 11:05:31.693064 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5704 11:05:31.696323 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5705 11:05:31.699649 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5706 11:05:31.703184 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5707 11:05:31.703268 ==
5708 11:05:31.706130 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 11:05:31.712894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 11:05:31.712990 ==
5711 11:05:31.713057 DQS Delay:
5712 11:05:31.716103 DQS0 = 0, DQS1 = 0
5713 11:05:31.716186 DQM Delay:
5714 11:05:31.719570 DQM0 = 102, DQM1 = 91
5715 11:05:31.719652 DQ Delay:
5716 11:05:31.722479 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5717 11:05:31.726814 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5718 11:05:31.729793 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5719 11:05:31.733113 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5720 11:05:31.733231
5721 11:05:31.733300
5722 11:05:31.733360 ==
5723 11:05:31.736478 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 11:05:31.739398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 11:05:31.739482 ==
5726 11:05:31.739547
5727 11:05:31.739609
5728 11:05:31.742614 TX Vref Scan disable
5729 11:05:31.745928 == TX Byte 0 ==
5730 11:05:31.749811 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5731 11:05:31.752650 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5732 11:05:31.756466 == TX Byte 1 ==
5733 11:05:31.759357 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5734 11:05:31.762180 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5735 11:05:31.762263 ==
5736 11:05:31.766083 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 11:05:31.772384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 11:05:31.772471 ==
5739 11:05:31.772537
5740 11:05:31.772597
5741 11:05:31.772656 TX Vref Scan disable
5742 11:05:31.776156 == TX Byte 0 ==
5743 11:05:31.779599 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5744 11:05:31.786345 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5745 11:05:31.786440 == TX Byte 1 ==
5746 11:05:31.789306 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5747 11:05:31.796187 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5748 11:05:31.796271
5749 11:05:31.796337 [DATLAT]
5750 11:05:31.796398 Freq=933, CH1 RK0
5751 11:05:31.796458
5752 11:05:31.799260 DATLAT Default: 0xd
5753 11:05:31.802943 0, 0xFFFF, sum = 0
5754 11:05:31.803028 1, 0xFFFF, sum = 0
5755 11:05:31.805875 2, 0xFFFF, sum = 0
5756 11:05:31.805959 3, 0xFFFF, sum = 0
5757 11:05:31.809276 4, 0xFFFF, sum = 0
5758 11:05:31.809362 5, 0xFFFF, sum = 0
5759 11:05:31.812439 6, 0xFFFF, sum = 0
5760 11:05:31.812523 7, 0xFFFF, sum = 0
5761 11:05:31.815696 8, 0xFFFF, sum = 0
5762 11:05:31.815781 9, 0xFFFF, sum = 0
5763 11:05:31.819003 10, 0x0, sum = 1
5764 11:05:31.819087 11, 0x0, sum = 2
5765 11:05:31.822493 12, 0x0, sum = 3
5766 11:05:31.822577 13, 0x0, sum = 4
5767 11:05:31.826237 best_step = 11
5768 11:05:31.826320
5769 11:05:31.826385 ==
5770 11:05:31.828487 Dram Type= 6, Freq= 0, CH_1, rank 0
5771 11:05:31.831876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 11:05:31.831962 ==
5773 11:05:31.835424 RX Vref Scan: 1
5774 11:05:31.835506
5775 11:05:31.835571 RX Vref 0 -> 0, step: 1
5776 11:05:31.835632
5777 11:05:31.838702 RX Delay -61 -> 252, step: 4
5778 11:05:31.838785
5779 11:05:31.841972 Set Vref, RX VrefLevel [Byte0]: 47
5780 11:05:31.845864 [Byte1]: 52
5781 11:05:31.848777
5782 11:05:31.848865 Final RX Vref Byte 0 = 47 to rank0
5783 11:05:31.852730 Final RX Vref Byte 1 = 52 to rank0
5784 11:05:31.855321 Final RX Vref Byte 0 = 47 to rank1
5785 11:05:31.858699 Final RX Vref Byte 1 = 52 to rank1==
5786 11:05:31.862418 Dram Type= 6, Freq= 0, CH_1, rank 0
5787 11:05:31.868800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 11:05:31.868891 ==
5789 11:05:31.868958 DQS Delay:
5790 11:05:31.869019 DQS0 = 0, DQS1 = 0
5791 11:05:31.871727 DQM Delay:
5792 11:05:31.871810 DQM0 = 101, DQM1 = 93
5793 11:05:31.875409 DQ Delay:
5794 11:05:31.878892 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5795 11:05:31.882430 DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =98
5796 11:05:31.885483 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =82
5797 11:05:31.888783 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =104
5798 11:05:31.888870
5799 11:05:31.888935
5800 11:05:31.895032 [DQSOSCAuto] RK0, (LSB)MR18= 0x1707, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 414 ps
5801 11:05:31.898441 CH1 RK0: MR19=505, MR18=1707
5802 11:05:31.904686 CH1_RK0: MR19=0x505, MR18=0x1707, DQSOSC=414, MR23=63, INC=63, DEC=42
5803 11:05:31.904785
5804 11:05:31.907887 ----->DramcWriteLeveling(PI) begin...
5805 11:05:31.907972 ==
5806 11:05:31.911544 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 11:05:31.914603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 11:05:31.918048 ==
5809 11:05:31.918132 Write leveling (Byte 0): 27 => 27
5810 11:05:31.921691 Write leveling (Byte 1): 27 => 27
5811 11:05:31.924470 DramcWriteLeveling(PI) end<-----
5812 11:05:31.924553
5813 11:05:31.924618 ==
5814 11:05:31.927863 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 11:05:31.934929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 11:05:31.935018 ==
5817 11:05:31.937500 [Gating] SW mode calibration
5818 11:05:31.944279 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5819 11:05:31.947194 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5820 11:05:31.954686 0 14 0 | B1->B0 | 3232 3131 | 1 0 | (1 1) (0 0)
5821 11:05:31.957200 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 11:05:31.960547 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 11:05:31.967338 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 11:05:31.970443 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 11:05:31.974060 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5826 11:05:31.980311 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5827 11:05:31.983496 0 14 28 | B1->B0 | 2424 2f2f | 0 1 | (0 0) (1 0)
5828 11:05:31.986718 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5829 11:05:31.994321 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 11:05:31.996944 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 11:05:32.000135 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 11:05:32.006521 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 11:05:32.009983 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 11:05:32.013505 0 15 24 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)
5835 11:05:32.020200 0 15 28 | B1->B0 | 3a3a 2f2e | 0 1 | (0 0) (0 0)
5836 11:05:32.023116 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 11:05:32.026426 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 11:05:32.033286 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 11:05:32.036393 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 11:05:32.039553 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 11:05:32.046721 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 11:05:32.049594 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5843 11:05:32.052768 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5844 11:05:32.059840 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5845 11:05:32.062977 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 11:05:32.066335 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 11:05:32.072830 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 11:05:32.076075 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 11:05:32.079168 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 11:05:32.086154 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 11:05:32.088797 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 11:05:32.092388 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 11:05:32.098853 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 11:05:32.102307 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 11:05:32.105512 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 11:05:32.112046 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 11:05:32.115912 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 11:05:32.119174 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5859 11:05:32.125169 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5860 11:05:32.128627 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5861 11:05:32.131803 Total UI for P1: 0, mck2ui 16
5862 11:05:32.135023 best dqsien dly found for B0: ( 1, 2, 26)
5863 11:05:32.138303 Total UI for P1: 0, mck2ui 16
5864 11:05:32.141772 best dqsien dly found for B1: ( 1, 2, 26)
5865 11:05:32.144907 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5866 11:05:32.148230 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5867 11:05:32.148316
5868 11:05:32.151889 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5869 11:05:32.154868 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5870 11:05:32.158472 [Gating] SW calibration Done
5871 11:05:32.158559 ==
5872 11:05:32.161572 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 11:05:32.167967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 11:05:32.168060 ==
5875 11:05:32.168125 RX Vref Scan: 0
5876 11:05:32.168186
5877 11:05:32.171097 RX Vref 0 -> 0, step: 1
5878 11:05:32.171181
5879 11:05:32.174776 RX Delay -80 -> 252, step: 8
5880 11:05:32.177960 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5881 11:05:32.181409 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5882 11:05:32.184581 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5883 11:05:32.188754 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5884 11:05:32.194689 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5885 11:05:32.198101 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5886 11:05:32.200999 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5887 11:05:32.204579 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5888 11:05:32.208116 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5889 11:05:32.211141 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5890 11:05:32.217238 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5891 11:05:32.220833 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5892 11:05:32.224900 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5893 11:05:32.227657 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5894 11:05:32.231568 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5895 11:05:32.237426 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5896 11:05:32.237514 ==
5897 11:05:32.240450 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 11:05:32.244323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 11:05:32.244407 ==
5900 11:05:32.244472 DQS Delay:
5901 11:05:32.247100 DQS0 = 0, DQS1 = 0
5902 11:05:32.247182 DQM Delay:
5903 11:05:32.250709 DQM0 = 99, DQM1 = 89
5904 11:05:32.250794 DQ Delay:
5905 11:05:32.254038 DQ0 =107, DQ1 =91, DQ2 =91, DQ3 =99
5906 11:05:32.257233 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5907 11:05:32.260573 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5908 11:05:32.263457 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5909 11:05:32.263565
5910 11:05:32.263657
5911 11:05:32.263772 ==
5912 11:05:32.266989 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 11:05:32.274041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 11:05:32.274132 ==
5915 11:05:32.274198
5916 11:05:32.274259
5917 11:05:32.274317 TX Vref Scan disable
5918 11:05:32.276548 == TX Byte 0 ==
5919 11:05:32.280262 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5920 11:05:32.286691 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5921 11:05:32.286780 == TX Byte 1 ==
5922 11:05:32.290022 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5923 11:05:32.297059 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5924 11:05:32.297174 ==
5925 11:05:32.300277 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 11:05:32.303380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 11:05:32.303489 ==
5928 11:05:32.303582
5929 11:05:32.303679
5930 11:05:32.306482 TX Vref Scan disable
5931 11:05:32.306588 == TX Byte 0 ==
5932 11:05:32.313228 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5933 11:05:32.316413 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5934 11:05:32.319881 == TX Byte 1 ==
5935 11:05:32.322948 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5936 11:05:32.326157 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5937 11:05:32.326267
5938 11:05:32.326359 [DATLAT]
5939 11:05:32.329636 Freq=933, CH1 RK1
5940 11:05:32.329743
5941 11:05:32.329836 DATLAT Default: 0xb
5942 11:05:32.332765 0, 0xFFFF, sum = 0
5943 11:05:32.336085 1, 0xFFFF, sum = 0
5944 11:05:32.336194 2, 0xFFFF, sum = 0
5945 11:05:32.339817 3, 0xFFFF, sum = 0
5946 11:05:32.339926 4, 0xFFFF, sum = 0
5947 11:05:32.342363 5, 0xFFFF, sum = 0
5948 11:05:32.342472 6, 0xFFFF, sum = 0
5949 11:05:32.345889 7, 0xFFFF, sum = 0
5950 11:05:32.345998 8, 0xFFFF, sum = 0
5951 11:05:32.349138 9, 0xFFFF, sum = 0
5952 11:05:32.349251 10, 0x0, sum = 1
5953 11:05:32.352624 11, 0x0, sum = 2
5954 11:05:32.352716 12, 0x0, sum = 3
5955 11:05:32.356110 13, 0x0, sum = 4
5956 11:05:32.356193 best_step = 11
5957 11:05:32.356257
5958 11:05:32.356317 ==
5959 11:05:32.359106 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 11:05:32.362972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 11:05:32.365910 ==
5962 11:05:32.365993 RX Vref Scan: 0
5963 11:05:32.366058
5964 11:05:32.369192 RX Vref 0 -> 0, step: 1
5965 11:05:32.369274
5966 11:05:32.372252 RX Delay -69 -> 252, step: 4
5967 11:05:32.376571 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5968 11:05:32.378715 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5969 11:05:32.385707 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5970 11:05:32.388542 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5971 11:05:32.391840 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
5972 11:05:32.395500 iDelay=207, Bit 5, Center 112 (27 ~ 198) 172
5973 11:05:32.399138 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5974 11:05:32.401887 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5975 11:05:32.408413 iDelay=207, Bit 8, Center 80 (-9 ~ 170) 180
5976 11:05:32.411749 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
5977 11:05:32.415679 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
5978 11:05:32.418317 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5979 11:05:32.422413 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5980 11:05:32.428278 iDelay=207, Bit 13, Center 98 (7 ~ 190) 184
5981 11:05:32.431472 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
5982 11:05:32.434921 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5983 11:05:32.435035 ==
5984 11:05:32.438166 Dram Type= 6, Freq= 0, CH_1, rank 1
5985 11:05:32.441565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5986 11:05:32.441676 ==
5987 11:05:32.445004 DQS Delay:
5988 11:05:32.445113 DQS0 = 0, DQS1 = 0
5989 11:05:32.447659 DQM Delay:
5990 11:05:32.447805 DQM0 = 101, DQM1 = 92
5991 11:05:32.451929 DQ Delay:
5992 11:05:32.452046 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
5993 11:05:32.454886 DQ4 =100, DQ5 =112, DQ6 =114, DQ7 =98
5994 11:05:32.458034 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =84
5995 11:05:32.464284 DQ12 =102, DQ13 =98, DQ14 =98, DQ15 =102
5996 11:05:32.464395
5997 11:05:32.464489
5998 11:05:32.470931 [DQSOSCAuto] RK1, (LSB)MR18= 0x701, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
5999 11:05:32.474432 CH1 RK1: MR19=505, MR18=701
6000 11:05:32.481240 CH1_RK1: MR19=0x505, MR18=0x701, DQSOSC=419, MR23=63, INC=61, DEC=41
6001 11:05:32.484114 [RxdqsGatingPostProcess] freq 933
6002 11:05:32.487687 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6003 11:05:32.490624 best DQS0 dly(2T, 0.5T) = (0, 10)
6004 11:05:32.494127 best DQS1 dly(2T, 0.5T) = (0, 10)
6005 11:05:32.497369 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6006 11:05:32.500875 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6007 11:05:32.504027 best DQS0 dly(2T, 0.5T) = (0, 10)
6008 11:05:32.506880 best DQS1 dly(2T, 0.5T) = (0, 10)
6009 11:05:32.510397 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6010 11:05:32.513683 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6011 11:05:32.516973 Pre-setting of DQS Precalculation
6012 11:05:32.520277 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6013 11:05:32.529918 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6014 11:05:32.537261 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6015 11:05:32.537371
6016 11:05:32.537435
6017 11:05:32.540952 [Calibration Summary] 1866 Mbps
6018 11:05:32.541037 CH 0, Rank 0
6019 11:05:32.543482 SW Impedance : PASS
6020 11:05:32.543565 DUTY Scan : NO K
6021 11:05:32.546541 ZQ Calibration : PASS
6022 11:05:32.550878 Jitter Meter : NO K
6023 11:05:32.550973 CBT Training : PASS
6024 11:05:32.553220 Write leveling : PASS
6025 11:05:32.556176 RX DQS gating : PASS
6026 11:05:32.556260 RX DQ/DQS(RDDQC) : PASS
6027 11:05:32.559843 TX DQ/DQS : PASS
6028 11:05:32.563384 RX DATLAT : PASS
6029 11:05:32.563476 RX DQ/DQS(Engine): PASS
6030 11:05:32.565930 TX OE : NO K
6031 11:05:32.566016 All Pass.
6032 11:05:32.566083
6033 11:05:32.569610 CH 0, Rank 1
6034 11:05:32.569696 SW Impedance : PASS
6035 11:05:32.573550 DUTY Scan : NO K
6036 11:05:32.576312 ZQ Calibration : PASS
6037 11:05:32.576397 Jitter Meter : NO K
6038 11:05:32.579679 CBT Training : PASS
6039 11:05:32.582593 Write leveling : PASS
6040 11:05:32.582676 RX DQS gating : PASS
6041 11:05:32.585800 RX DQ/DQS(RDDQC) : PASS
6042 11:05:32.589747 TX DQ/DQS : PASS
6043 11:05:32.589835 RX DATLAT : PASS
6044 11:05:32.592628 RX DQ/DQS(Engine): PASS
6045 11:05:32.595950 TX OE : NO K
6046 11:05:32.596034 All Pass.
6047 11:05:32.596100
6048 11:05:32.596160 CH 1, Rank 0
6049 11:05:32.598893 SW Impedance : PASS
6050 11:05:32.602721 DUTY Scan : NO K
6051 11:05:32.602807 ZQ Calibration : PASS
6052 11:05:32.606305 Jitter Meter : NO K
6053 11:05:32.609117 CBT Training : PASS
6054 11:05:32.609202 Write leveling : PASS
6055 11:05:32.612728 RX DQS gating : PASS
6056 11:05:32.615841 RX DQ/DQS(RDDQC) : PASS
6057 11:05:32.615924 TX DQ/DQS : PASS
6058 11:05:32.619058 RX DATLAT : PASS
6059 11:05:32.619141 RX DQ/DQS(Engine): PASS
6060 11:05:32.622210 TX OE : NO K
6061 11:05:32.622293 All Pass.
6062 11:05:32.622358
6063 11:05:32.626322 CH 1, Rank 1
6064 11:05:32.626404 SW Impedance : PASS
6065 11:05:32.628784 DUTY Scan : NO K
6066 11:05:32.632583 ZQ Calibration : PASS
6067 11:05:32.632693 Jitter Meter : NO K
6068 11:05:32.635310 CBT Training : PASS
6069 11:05:32.638989 Write leveling : PASS
6070 11:05:32.639074 RX DQS gating : PASS
6071 11:05:32.642097 RX DQ/DQS(RDDQC) : PASS
6072 11:05:32.645020 TX DQ/DQS : PASS
6073 11:05:32.645104 RX DATLAT : PASS
6074 11:05:32.648832 RX DQ/DQS(Engine): PASS
6075 11:05:32.651992 TX OE : NO K
6076 11:05:32.652082 All Pass.
6077 11:05:32.652148
6078 11:05:32.655553 DramC Write-DBI off
6079 11:05:32.655638 PER_BANK_REFRESH: Hybrid Mode
6080 11:05:32.658558 TX_TRACKING: ON
6081 11:05:32.668217 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6082 11:05:32.672197 [FAST_K] Save calibration result to emmc
6083 11:05:32.674797 dramc_set_vcore_voltage set vcore to 650000
6084 11:05:32.674881 Read voltage for 400, 6
6085 11:05:32.678380 Vio18 = 0
6086 11:05:32.678464 Vcore = 650000
6087 11:05:32.678529 Vdram = 0
6088 11:05:32.681522 Vddq = 0
6089 11:05:32.681606 Vmddr = 0
6090 11:05:32.687890 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6091 11:05:32.691278 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6092 11:05:32.694703 MEM_TYPE=3, freq_sel=20
6093 11:05:32.697870 sv_algorithm_assistance_LP4_800
6094 11:05:32.701182 ============ PULL DRAM RESETB DOWN ============
6095 11:05:32.704484 ========== PULL DRAM RESETB DOWN end =========
6096 11:05:32.711272 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6097 11:05:32.714436 ===================================
6098 11:05:32.714522 LPDDR4 DRAM CONFIGURATION
6099 11:05:32.717985 ===================================
6100 11:05:32.720884 EX_ROW_EN[0] = 0x0
6101 11:05:32.724402 EX_ROW_EN[1] = 0x0
6102 11:05:32.724485 LP4Y_EN = 0x0
6103 11:05:32.727425 WORK_FSP = 0x0
6104 11:05:32.727507 WL = 0x2
6105 11:05:32.731025 RL = 0x2
6106 11:05:32.731107 BL = 0x2
6107 11:05:32.734182 RPST = 0x0
6108 11:05:32.734264 RD_PRE = 0x0
6109 11:05:32.737438 WR_PRE = 0x1
6110 11:05:32.737519 WR_PST = 0x0
6111 11:05:32.741124 DBI_WR = 0x0
6112 11:05:32.741206 DBI_RD = 0x0
6113 11:05:32.743862 OTF = 0x1
6114 11:05:32.747780 ===================================
6115 11:05:32.750683 ===================================
6116 11:05:32.750768 ANA top config
6117 11:05:32.754066 ===================================
6118 11:05:32.757371 DLL_ASYNC_EN = 0
6119 11:05:32.760572 ALL_SLAVE_EN = 1
6120 11:05:32.763616 NEW_RANK_MODE = 1
6121 11:05:32.763737 DLL_IDLE_MODE = 1
6122 11:05:32.767201 LP45_APHY_COMB_EN = 1
6123 11:05:32.770271 TX_ODT_DIS = 1
6124 11:05:32.773899 NEW_8X_MODE = 1
6125 11:05:32.777137 ===================================
6126 11:05:32.780285 ===================================
6127 11:05:32.783389 data_rate = 800
6128 11:05:32.787158 CKR = 1
6129 11:05:32.787241 DQ_P2S_RATIO = 4
6130 11:05:32.790103 ===================================
6131 11:05:32.793527 CA_P2S_RATIO = 4
6132 11:05:32.796423 DQ_CA_OPEN = 0
6133 11:05:32.799903 DQ_SEMI_OPEN = 1
6134 11:05:32.803156 CA_SEMI_OPEN = 1
6135 11:05:32.806928 CA_FULL_RATE = 0
6136 11:05:32.807010 DQ_CKDIV4_EN = 0
6137 11:05:32.809638 CA_CKDIV4_EN = 1
6138 11:05:32.812855 CA_PREDIV_EN = 0
6139 11:05:32.816086 PH8_DLY = 0
6140 11:05:32.819802 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6141 11:05:32.822894 DQ_AAMCK_DIV = 0
6142 11:05:32.823012 CA_AAMCK_DIV = 0
6143 11:05:32.826573 CA_ADMCK_DIV = 4
6144 11:05:32.829491 DQ_TRACK_CA_EN = 0
6145 11:05:32.832659 CA_PICK = 800
6146 11:05:32.835965 CA_MCKIO = 400
6147 11:05:32.839763 MCKIO_SEMI = 400
6148 11:05:32.842599 PLL_FREQ = 3016
6149 11:05:32.845758 DQ_UI_PI_RATIO = 32
6150 11:05:32.845840 CA_UI_PI_RATIO = 32
6151 11:05:32.849144 ===================================
6152 11:05:32.852680 ===================================
6153 11:05:32.856280 memory_type:LPDDR4
6154 11:05:32.859157 GP_NUM : 10
6155 11:05:32.859238 SRAM_EN : 1
6156 11:05:32.862389 MD32_EN : 0
6157 11:05:32.865861 ===================================
6158 11:05:32.868696 [ANA_INIT] >>>>>>>>>>>>>>
6159 11:05:32.872169 <<<<<< [CONFIGURE PHASE]: ANA_TX
6160 11:05:32.875367 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6161 11:05:32.879192 ===================================
6162 11:05:32.879275 data_rate = 800,PCW = 0X7400
6163 11:05:32.882396 ===================================
6164 11:05:32.885694 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6165 11:05:32.892111 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6166 11:05:32.905192 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6167 11:05:32.908995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6168 11:05:32.911779 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6169 11:05:32.915315 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6170 11:05:32.918387 [ANA_INIT] flow start
6171 11:05:32.918471 [ANA_INIT] PLL >>>>>>>>
6172 11:05:32.921601 [ANA_INIT] PLL <<<<<<<<
6173 11:05:32.925249 [ANA_INIT] MIDPI >>>>>>>>
6174 11:05:32.928498 [ANA_INIT] MIDPI <<<<<<<<
6175 11:05:32.928580 [ANA_INIT] DLL >>>>>>>>
6176 11:05:32.932064 [ANA_INIT] flow end
6177 11:05:32.935858 ============ LP4 DIFF to SE enter ============
6178 11:05:32.937891 ============ LP4 DIFF to SE exit ============
6179 11:05:32.941216 [ANA_INIT] <<<<<<<<<<<<<
6180 11:05:32.944796 [Flow] Enable top DCM control >>>>>
6181 11:05:32.947791 [Flow] Enable top DCM control <<<<<
6182 11:05:32.951466 Enable DLL master slave shuffle
6183 11:05:32.957970 ==============================================================
6184 11:05:32.958058 Gating Mode config
6185 11:05:32.964271 ==============================================================
6186 11:05:32.964358 Config description:
6187 11:05:32.974119 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6188 11:05:32.981285 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6189 11:05:32.987859 SELPH_MODE 0: By rank 1: By Phase
6190 11:05:32.993816 ==============================================================
6191 11:05:32.993907 GAT_TRACK_EN = 0
6192 11:05:32.997209 RX_GATING_MODE = 2
6193 11:05:33.000693 RX_GATING_TRACK_MODE = 2
6194 11:05:33.003977 SELPH_MODE = 1
6195 11:05:33.007138 PICG_EARLY_EN = 1
6196 11:05:33.010511 VALID_LAT_VALUE = 1
6197 11:05:33.017323 ==============================================================
6198 11:05:33.020769 Enter into Gating configuration >>>>
6199 11:05:33.023660 Exit from Gating configuration <<<<
6200 11:05:33.027415 Enter into DVFS_PRE_config >>>>>
6201 11:05:33.036925 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6202 11:05:33.040223 Exit from DVFS_PRE_config <<<<<
6203 11:05:33.043497 Enter into PICG configuration >>>>
6204 11:05:33.046611 Exit from PICG configuration <<<<
6205 11:05:33.049909 [RX_INPUT] configuration >>>>>
6206 11:05:33.053340 [RX_INPUT] configuration <<<<<
6207 11:05:33.056972 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6208 11:05:33.062761 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6209 11:05:33.069365 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6210 11:05:33.076185 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6211 11:05:33.079410 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6212 11:05:33.086150 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6213 11:05:33.092445 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6214 11:05:33.096069 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6215 11:05:33.099114 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6216 11:05:33.102799 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6217 11:05:33.108876 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6218 11:05:33.112189 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6219 11:05:33.115794 ===================================
6220 11:05:33.118731 LPDDR4 DRAM CONFIGURATION
6221 11:05:33.122579 ===================================
6222 11:05:33.122661 EX_ROW_EN[0] = 0x0
6223 11:05:33.125663 EX_ROW_EN[1] = 0x0
6224 11:05:33.125744 LP4Y_EN = 0x0
6225 11:05:33.128640 WORK_FSP = 0x0
6226 11:05:33.128721 WL = 0x2
6227 11:05:33.132174 RL = 0x2
6228 11:05:33.132256 BL = 0x2
6229 11:05:33.135476 RPST = 0x0
6230 11:05:33.135570 RD_PRE = 0x0
6231 11:05:33.138705 WR_PRE = 0x1
6232 11:05:33.141904 WR_PST = 0x0
6233 11:05:33.141985 DBI_WR = 0x0
6234 11:05:33.145323 DBI_RD = 0x0
6235 11:05:33.145403 OTF = 0x1
6236 11:05:33.148605 ===================================
6237 11:05:33.152254 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6238 11:05:33.158389 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6239 11:05:33.161725 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6240 11:05:33.165291 ===================================
6241 11:05:33.168309 LPDDR4 DRAM CONFIGURATION
6242 11:05:33.172916 ===================================
6243 11:05:33.172999 EX_ROW_EN[0] = 0x10
6244 11:05:33.175477 EX_ROW_EN[1] = 0x0
6245 11:05:33.175558 LP4Y_EN = 0x0
6246 11:05:33.178603 WORK_FSP = 0x0
6247 11:05:33.178683 WL = 0x2
6248 11:05:33.181659 RL = 0x2
6249 11:05:33.181766 BL = 0x2
6250 11:05:33.185236 RPST = 0x0
6251 11:05:33.185318 RD_PRE = 0x0
6252 11:05:33.188028 WR_PRE = 0x1
6253 11:05:33.191520 WR_PST = 0x0
6254 11:05:33.191598 DBI_WR = 0x0
6255 11:05:33.194517 DBI_RD = 0x0
6256 11:05:33.194605 OTF = 0x1
6257 11:05:33.198011 ===================================
6258 11:05:33.204526 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6259 11:05:33.208390 nWR fixed to 30
6260 11:05:33.211738 [ModeRegInit_LP4] CH0 RK0
6261 11:05:33.211822 [ModeRegInit_LP4] CH0 RK1
6262 11:05:33.215192 [ModeRegInit_LP4] CH1 RK0
6263 11:05:33.218836 [ModeRegInit_LP4] CH1 RK1
6264 11:05:33.219020 match AC timing 19
6265 11:05:33.224995 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6266 11:05:33.228276 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6267 11:05:33.231406 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6268 11:05:33.238504 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6269 11:05:33.241442 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6270 11:05:33.241589 ==
6271 11:05:33.245165 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 11:05:33.248452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 11:05:33.248549 ==
6274 11:05:33.254481 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6275 11:05:33.261470 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6276 11:05:33.265016 [CA 0] Center 36 (8~64) winsize 57
6277 11:05:33.268095 [CA 1] Center 36 (8~64) winsize 57
6278 11:05:33.270976 [CA 2] Center 36 (8~64) winsize 57
6279 11:05:33.274545 [CA 3] Center 36 (8~64) winsize 57
6280 11:05:33.277649 [CA 4] Center 36 (8~64) winsize 57
6281 11:05:33.280931 [CA 5] Center 36 (8~64) winsize 57
6282 11:05:33.281015
6283 11:05:33.284505 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6284 11:05:33.284588
6285 11:05:33.288720 [CATrainingPosCal] consider 1 rank data
6286 11:05:33.290598 u2DelayCellTimex100 = 270/100 ps
6287 11:05:33.293924 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 11:05:33.298164 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 11:05:33.300625 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 11:05:33.304301 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 11:05:33.307478 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 11:05:33.310436 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 11:05:33.310520
6294 11:05:33.317138 CA PerBit enable=1, Macro0, CA PI delay=36
6295 11:05:33.317227
6296 11:05:33.317291 [CBTSetCACLKResult] CA Dly = 36
6297 11:05:33.320242 CS Dly: 1 (0~32)
6298 11:05:33.320324 ==
6299 11:05:33.323782 Dram Type= 6, Freq= 0, CH_0, rank 1
6300 11:05:33.327352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 11:05:33.327434 ==
6302 11:05:33.333430 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6303 11:05:33.340489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6304 11:05:33.343481 [CA 0] Center 36 (8~64) winsize 57
6305 11:05:33.346840 [CA 1] Center 36 (8~64) winsize 57
6306 11:05:33.350692 [CA 2] Center 36 (8~64) winsize 57
6307 11:05:33.350781 [CA 3] Center 36 (8~64) winsize 57
6308 11:05:33.353327 [CA 4] Center 36 (8~64) winsize 57
6309 11:05:33.358141 [CA 5] Center 36 (8~64) winsize 57
6310 11:05:33.358240
6311 11:05:33.363275 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6312 11:05:33.363362
6313 11:05:33.366702 [CATrainingPosCal] consider 2 rank data
6314 11:05:33.369872 u2DelayCellTimex100 = 270/100 ps
6315 11:05:33.373514 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 11:05:33.376596 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 11:05:33.379956 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 11:05:33.382772 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 11:05:33.386724 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 11:05:33.389370 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 11:05:33.389454
6322 11:05:33.392877 CA PerBit enable=1, Macro0, CA PI delay=36
6323 11:05:33.392958
6324 11:05:33.396334 [CBTSetCACLKResult] CA Dly = 36
6325 11:05:33.400227 CS Dly: 1 (0~32)
6326 11:05:33.400308
6327 11:05:33.403622 ----->DramcWriteLeveling(PI) begin...
6328 11:05:33.403713 ==
6329 11:05:33.406024 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 11:05:33.409632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 11:05:33.409713 ==
6332 11:05:33.413222 Write leveling (Byte 0): 40 => 8
6333 11:05:33.415658 Write leveling (Byte 1): 32 => 0
6334 11:05:33.419234 DramcWriteLeveling(PI) end<-----
6335 11:05:33.419314
6336 11:05:33.419377 ==
6337 11:05:33.422264 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 11:05:33.425977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 11:05:33.426058 ==
6340 11:05:33.428905 [Gating] SW mode calibration
6341 11:05:33.435479 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6342 11:05:33.442115 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6343 11:05:33.445841 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6344 11:05:33.452565 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6345 11:05:33.455484 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6346 11:05:33.458818 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 11:05:33.465487 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6348 11:05:33.468496 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6349 11:05:33.472161 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6350 11:05:33.478534 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 11:05:33.482125 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 11:05:33.485346 Total UI for P1: 0, mck2ui 16
6353 11:05:33.488240 best dqsien dly found for B0: ( 0, 14, 24)
6354 11:05:33.491422 Total UI for P1: 0, mck2ui 16
6355 11:05:33.495057 best dqsien dly found for B1: ( 0, 14, 24)
6356 11:05:33.498106 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6357 11:05:33.501184 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6358 11:05:33.501264
6359 11:05:33.504635 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6360 11:05:33.511429 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6361 11:05:33.511512 [Gating] SW calibration Done
6362 11:05:33.511577 ==
6363 11:05:33.514685 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 11:05:33.521145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 11:05:33.521230 ==
6366 11:05:33.521295 RX Vref Scan: 0
6367 11:05:33.521354
6368 11:05:33.524357 RX Vref 0 -> 0, step: 1
6369 11:05:33.524438
6370 11:05:33.527917 RX Delay -410 -> 252, step: 16
6371 11:05:33.530953 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6372 11:05:33.534793 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6373 11:05:33.541121 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6374 11:05:33.544192 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6375 11:05:33.548032 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6376 11:05:33.551001 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6377 11:05:33.557454 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6378 11:05:33.560976 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6379 11:05:33.564427 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6380 11:05:33.568211 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6381 11:05:33.573871 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6382 11:05:33.576931 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6383 11:05:33.580600 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6384 11:05:33.586795 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6385 11:05:33.590445 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6386 11:05:33.593866 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6387 11:05:33.593954 ==
6388 11:05:33.596818 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 11:05:33.600319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 11:05:33.603698 ==
6391 11:05:33.603853 DQS Delay:
6392 11:05:33.603965 DQS0 = 43, DQS1 = 59
6393 11:05:33.606901 DQM Delay:
6394 11:05:33.607026 DQM0 = 9, DQM1 = 12
6395 11:05:33.610166 DQ Delay:
6396 11:05:33.610291 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6397 11:05:33.613658 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6398 11:05:33.616756 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6399 11:05:33.620147 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6400 11:05:33.620249
6401 11:05:33.620316
6402 11:05:33.623623 ==
6403 11:05:33.623740 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 11:05:33.630013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 11:05:33.630096 ==
6406 11:05:33.630159
6407 11:05:33.630218
6408 11:05:33.633116 TX Vref Scan disable
6409 11:05:33.633197 == TX Byte 0 ==
6410 11:05:33.636336 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 11:05:33.643142 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 11:05:33.643223 == TX Byte 1 ==
6413 11:05:33.646575 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6414 11:05:33.652778 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6415 11:05:33.652861 ==
6416 11:05:33.656055 Dram Type= 6, Freq= 0, CH_0, rank 0
6417 11:05:33.659715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 11:05:33.659797 ==
6419 11:05:33.659862
6420 11:05:33.659921
6421 11:05:33.662594 TX Vref Scan disable
6422 11:05:33.662675 == TX Byte 0 ==
6423 11:05:33.669145 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6424 11:05:33.672644 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6425 11:05:33.672726 == TX Byte 1 ==
6426 11:05:33.679167 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6427 11:05:33.682416 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6428 11:05:33.682498
6429 11:05:33.682562 [DATLAT]
6430 11:05:33.685738 Freq=400, CH0 RK0
6431 11:05:33.685820
6432 11:05:33.685883 DATLAT Default: 0xf
6433 11:05:33.689574 0, 0xFFFF, sum = 0
6434 11:05:33.689656 1, 0xFFFF, sum = 0
6435 11:05:33.692118 2, 0xFFFF, sum = 0
6436 11:05:33.692199 3, 0xFFFF, sum = 0
6437 11:05:33.695450 4, 0xFFFF, sum = 0
6438 11:05:33.695532 5, 0xFFFF, sum = 0
6439 11:05:33.699040 6, 0xFFFF, sum = 0
6440 11:05:33.699122 7, 0xFFFF, sum = 0
6441 11:05:33.701930 8, 0xFFFF, sum = 0
6442 11:05:33.705245 9, 0xFFFF, sum = 0
6443 11:05:33.705334 10, 0xFFFF, sum = 0
6444 11:05:33.708458 11, 0xFFFF, sum = 0
6445 11:05:33.708540 12, 0xFFFF, sum = 0
6446 11:05:33.711818 13, 0x0, sum = 1
6447 11:05:33.711892 14, 0x0, sum = 2
6448 11:05:33.715148 15, 0x0, sum = 3
6449 11:05:33.715217 16, 0x0, sum = 4
6450 11:05:33.715293 best_step = 14
6451 11:05:33.718567
6452 11:05:33.718645 ==
6453 11:05:33.721785 Dram Type= 6, Freq= 0, CH_0, rank 0
6454 11:05:33.725476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 11:05:33.725563 ==
6456 11:05:33.725629 RX Vref Scan: 1
6457 11:05:33.725689
6458 11:05:33.728300 RX Vref 0 -> 0, step: 1
6459 11:05:33.728381
6460 11:05:33.731958 RX Delay -359 -> 252, step: 8
6461 11:05:33.732039
6462 11:05:33.734839 Set Vref, RX VrefLevel [Byte0]: 59
6463 11:05:33.738287 [Byte1]: 58
6464 11:05:33.742190
6465 11:05:33.742270 Final RX Vref Byte 0 = 59 to rank0
6466 11:05:33.746338 Final RX Vref Byte 1 = 58 to rank0
6467 11:05:33.749057 Final RX Vref Byte 0 = 59 to rank1
6468 11:05:33.752209 Final RX Vref Byte 1 = 58 to rank1==
6469 11:05:33.755506 Dram Type= 6, Freq= 0, CH_0, rank 0
6470 11:05:33.761921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 11:05:33.762005 ==
6472 11:05:33.762070 DQS Delay:
6473 11:05:33.765281 DQS0 = 48, DQS1 = 60
6474 11:05:33.765362 DQM Delay:
6475 11:05:33.765434 DQM0 = 12, DQM1 = 11
6476 11:05:33.768610 DQ Delay:
6477 11:05:33.771793 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6478 11:05:33.775061 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6479 11:05:33.775252 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6480 11:05:33.781954 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6481 11:05:33.782029
6482 11:05:33.782091
6483 11:05:33.788357 [DQSOSCAuto] RK0, (LSB)MR18= 0xb97b, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 386 ps
6484 11:05:33.791782 CH0 RK0: MR19=C0C, MR18=B97B
6485 11:05:33.797939 CH0_RK0: MR19=0xC0C, MR18=0xB97B, DQSOSC=386, MR23=63, INC=396, DEC=264
6486 11:05:33.798021 ==
6487 11:05:33.801273 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 11:05:33.804480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 11:05:33.804552 ==
6490 11:05:33.807848 [Gating] SW mode calibration
6491 11:05:33.814337 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6492 11:05:33.821250 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6493 11:05:33.824073 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6494 11:05:33.827466 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 11:05:33.834026 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6496 11:05:33.837560 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 11:05:33.841103 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 11:05:33.847894 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 11:05:33.850619 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 11:05:33.853968 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 11:05:33.860342 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 11:05:33.863816 Total UI for P1: 0, mck2ui 16
6503 11:05:33.867298 best dqsien dly found for B0: ( 0, 14, 24)
6504 11:05:33.870711 Total UI for P1: 0, mck2ui 16
6505 11:05:33.873683 best dqsien dly found for B1: ( 0, 14, 24)
6506 11:05:33.876915 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6507 11:05:33.880341 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6508 11:05:33.880414
6509 11:05:33.883589 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6510 11:05:33.886794 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6511 11:05:33.889795 [Gating] SW calibration Done
6512 11:05:33.889867 ==
6513 11:05:33.893520 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 11:05:33.896459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 11:05:33.899887 ==
6516 11:05:33.899968 RX Vref Scan: 0
6517 11:05:33.900031
6518 11:05:33.903231 RX Vref 0 -> 0, step: 1
6519 11:05:33.903312
6520 11:05:33.906798 RX Delay -410 -> 252, step: 16
6521 11:05:33.909679 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6522 11:05:33.912928 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6523 11:05:33.919470 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6524 11:05:33.922890 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6525 11:05:33.926171 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6526 11:05:33.929041 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6527 11:05:33.936009 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6528 11:05:33.939320 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6529 11:05:33.942949 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6530 11:05:33.946032 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6531 11:05:33.952399 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6532 11:05:33.955946 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6533 11:05:33.959283 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6534 11:05:33.962008 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6535 11:05:33.968956 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6536 11:05:33.972474 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6537 11:05:33.972565 ==
6538 11:05:33.975981 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 11:05:33.978631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 11:05:33.978743 ==
6541 11:05:33.982134 DQS Delay:
6542 11:05:33.982216 DQS0 = 43, DQS1 = 59
6543 11:05:33.985614 DQM Delay:
6544 11:05:33.985697 DQM0 = 10, DQM1 = 16
6545 11:05:33.988469 DQ Delay:
6546 11:05:33.988567 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6547 11:05:33.991651 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6548 11:05:33.995279 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6549 11:05:33.998653 DQ12 =24, DQ13 =24, DQ14 =32, DQ15 =24
6550 11:05:33.998735
6551 11:05:33.998801
6552 11:05:33.998861 ==
6553 11:05:34.002092 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 11:05:34.008447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 11:05:34.008531 ==
6556 11:05:34.008596
6557 11:05:34.008657
6558 11:05:34.008715 TX Vref Scan disable
6559 11:05:34.011826 == TX Byte 0 ==
6560 11:05:34.015068 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6561 11:05:34.018483 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6562 11:05:34.021420 == TX Byte 1 ==
6563 11:05:34.024775 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6564 11:05:34.028110 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6565 11:05:34.031472 ==
6566 11:05:34.034482 Dram Type= 6, Freq= 0, CH_0, rank 1
6567 11:05:34.038341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6568 11:05:34.038425 ==
6569 11:05:34.038523
6570 11:05:34.038584
6571 11:05:34.041214 TX Vref Scan disable
6572 11:05:34.041296 == TX Byte 0 ==
6573 11:05:34.044728 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6574 11:05:34.050986 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6575 11:05:34.051069 == TX Byte 1 ==
6576 11:05:34.054017 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6577 11:05:34.061353 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6578 11:05:34.061439
6579 11:05:34.061505 [DATLAT]
6580 11:05:34.061567 Freq=400, CH0 RK1
6581 11:05:34.061627
6582 11:05:34.064238 DATLAT Default: 0xe
6583 11:05:34.067646 0, 0xFFFF, sum = 0
6584 11:05:34.067794 1, 0xFFFF, sum = 0
6585 11:05:34.070569 2, 0xFFFF, sum = 0
6586 11:05:34.070652 3, 0xFFFF, sum = 0
6587 11:05:34.074235 4, 0xFFFF, sum = 0
6588 11:05:34.074318 5, 0xFFFF, sum = 0
6589 11:05:34.077210 6, 0xFFFF, sum = 0
6590 11:05:34.077293 7, 0xFFFF, sum = 0
6591 11:05:34.081183 8, 0xFFFF, sum = 0
6592 11:05:34.081267 9, 0xFFFF, sum = 0
6593 11:05:34.084027 10, 0xFFFF, sum = 0
6594 11:05:34.084111 11, 0xFFFF, sum = 0
6595 11:05:34.087372 12, 0xFFFF, sum = 0
6596 11:05:34.087455 13, 0x0, sum = 1
6597 11:05:34.090870 14, 0x0, sum = 2
6598 11:05:34.090954 15, 0x0, sum = 3
6599 11:05:34.093817 16, 0x0, sum = 4
6600 11:05:34.093900 best_step = 14
6601 11:05:34.093966
6602 11:05:34.094027 ==
6603 11:05:34.097453 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 11:05:34.103554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 11:05:34.103637 ==
6606 11:05:34.103738 RX Vref Scan: 0
6607 11:05:34.103799
6608 11:05:34.107478 RX Vref 0 -> 0, step: 1
6609 11:05:34.107577
6610 11:05:34.110850 RX Delay -359 -> 252, step: 8
6611 11:05:34.117100 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6612 11:05:34.120364 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6613 11:05:34.123913 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6614 11:05:34.126899 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6615 11:05:34.133208 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6616 11:05:34.136935 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6617 11:05:34.139962 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6618 11:05:34.143218 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6619 11:05:34.150172 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6620 11:05:34.153700 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6621 11:05:34.156451 iDelay=217, Bit 10, Center -44 (-295 ~ 208) 504
6622 11:05:34.163341 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6623 11:05:34.166630 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6624 11:05:34.170759 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6625 11:05:34.173116 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6626 11:05:34.179703 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6627 11:05:34.179786 ==
6628 11:05:34.183273 Dram Type= 6, Freq= 0, CH_0, rank 1
6629 11:05:34.186052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 11:05:34.186135 ==
6631 11:05:34.186201 DQS Delay:
6632 11:05:34.189638 DQS0 = 44, DQS1 = 56
6633 11:05:34.189721 DQM Delay:
6634 11:05:34.192891 DQM0 = 8, DQM1 = 10
6635 11:05:34.192974 DQ Delay:
6636 11:05:34.196073 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6637 11:05:34.199449 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6638 11:05:34.203093 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6639 11:05:34.205948 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6640 11:05:34.206032
6641 11:05:34.206097
6642 11:05:34.213425 [DQSOSCAuto] RK1, (LSB)MR18= 0xad3a, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps
6643 11:05:34.216559 CH0 RK1: MR19=C0C, MR18=AD3A
6644 11:05:34.222513 CH0_RK1: MR19=0xC0C, MR18=0xAD3A, DQSOSC=388, MR23=63, INC=392, DEC=261
6645 11:05:34.226070 [RxdqsGatingPostProcess] freq 400
6646 11:05:34.232564 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6647 11:05:34.235862 best DQS0 dly(2T, 0.5T) = (0, 10)
6648 11:05:34.235951 best DQS1 dly(2T, 0.5T) = (0, 10)
6649 11:05:34.239038 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6650 11:05:34.242501 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6651 11:05:34.245637 best DQS0 dly(2T, 0.5T) = (0, 10)
6652 11:05:34.249124 best DQS1 dly(2T, 0.5T) = (0, 10)
6653 11:05:34.252469 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6654 11:05:34.255955 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6655 11:05:34.258920 Pre-setting of DQS Precalculation
6656 11:05:34.266034 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6657 11:05:34.266118 ==
6658 11:05:34.269405 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 11:05:34.272249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 11:05:34.272333 ==
6661 11:05:34.278843 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6662 11:05:34.281880 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6663 11:05:34.285374 [CA 0] Center 36 (8~64) winsize 57
6664 11:05:34.288620 [CA 1] Center 36 (8~64) winsize 57
6665 11:05:34.291911 [CA 2] Center 36 (8~64) winsize 57
6666 11:05:34.295460 [CA 3] Center 36 (8~64) winsize 57
6667 11:05:34.298570 [CA 4] Center 36 (8~64) winsize 57
6668 11:05:34.301524 [CA 5] Center 36 (8~64) winsize 57
6669 11:05:34.301612
6670 11:05:34.305091 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6671 11:05:34.305175
6672 11:05:34.308478 [CATrainingPosCal] consider 1 rank data
6673 11:05:34.312263 u2DelayCellTimex100 = 270/100 ps
6674 11:05:34.315143 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 11:05:34.321650 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 11:05:34.325451 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 11:05:34.328313 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 11:05:34.331322 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 11:05:34.334608 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 11:05:34.334704
6681 11:05:34.338290 CA PerBit enable=1, Macro0, CA PI delay=36
6682 11:05:34.338393
6683 11:05:34.341807 [CBTSetCACLKResult] CA Dly = 36
6684 11:05:34.344722 CS Dly: 1 (0~32)
6685 11:05:34.344834 ==
6686 11:05:34.348555 Dram Type= 6, Freq= 0, CH_1, rank 1
6687 11:05:34.351823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 11:05:34.352230 ==
6689 11:05:34.358569 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6690 11:05:34.362440 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6691 11:05:34.364987 [CA 0] Center 36 (8~64) winsize 57
6692 11:05:34.368410 [CA 1] Center 36 (8~64) winsize 57
6693 11:05:34.371479 [CA 2] Center 36 (8~64) winsize 57
6694 11:05:34.374855 [CA 3] Center 36 (8~64) winsize 57
6695 11:05:34.378327 [CA 4] Center 36 (8~64) winsize 57
6696 11:05:34.381348 [CA 5] Center 36 (8~64) winsize 57
6697 11:05:34.381735
6698 11:05:34.384429 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6699 11:05:34.384819
6700 11:05:34.388284 [CATrainingPosCal] consider 2 rank data
6701 11:05:34.391769 u2DelayCellTimex100 = 270/100 ps
6702 11:05:34.394595 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 11:05:34.398543 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 11:05:34.405903 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 11:05:34.408245 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 11:05:34.411354 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 11:05:34.414584 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 11:05:34.415118
6709 11:05:34.417787 CA PerBit enable=1, Macro0, CA PI delay=36
6710 11:05:34.418312
6711 11:05:34.421471 [CBTSetCACLKResult] CA Dly = 36
6712 11:05:34.422050 CS Dly: 1 (0~32)
6713 11:05:34.422397
6714 11:05:34.424222 ----->DramcWriteLeveling(PI) begin...
6715 11:05:34.428119 ==
6716 11:05:34.430733 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 11:05:34.434364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 11:05:34.434807 ==
6719 11:05:34.437761 Write leveling (Byte 0): 40 => 8
6720 11:05:34.441253 Write leveling (Byte 1): 32 => 0
6721 11:05:34.444097 DramcWriteLeveling(PI) end<-----
6722 11:05:34.444520
6723 11:05:34.444855 ==
6724 11:05:34.447564 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 11:05:34.450848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 11:05:34.451379 ==
6727 11:05:34.454149 [Gating] SW mode calibration
6728 11:05:34.460688 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6729 11:05:34.467017 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6730 11:05:34.470687 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6731 11:05:34.473569 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6732 11:05:34.480437 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6733 11:05:34.483822 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 11:05:34.486908 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6735 11:05:34.494008 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6736 11:05:34.496653 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6737 11:05:34.500411 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 11:05:34.507177 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 11:05:34.507735 Total UI for P1: 0, mck2ui 16
6740 11:05:34.513439 best dqsien dly found for B0: ( 0, 14, 24)
6741 11:05:34.513972 Total UI for P1: 0, mck2ui 16
6742 11:05:34.520071 best dqsien dly found for B1: ( 0, 14, 24)
6743 11:05:34.523321 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6744 11:05:34.526472 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6745 11:05:34.526997
6746 11:05:34.530046 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6747 11:05:34.533507 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6748 11:05:34.536818 [Gating] SW calibration Done
6749 11:05:34.537246 ==
6750 11:05:34.539571 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 11:05:34.543582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 11:05:34.544159 ==
6753 11:05:34.546296 RX Vref Scan: 0
6754 11:05:34.546822
6755 11:05:34.547160 RX Vref 0 -> 0, step: 1
6756 11:05:34.547473
6757 11:05:34.549928 RX Delay -410 -> 252, step: 16
6758 11:05:34.556531 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6759 11:05:34.559449 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6760 11:05:34.562951 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6761 11:05:34.566451 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6762 11:05:34.572546 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6763 11:05:34.575776 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6764 11:05:34.579560 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6765 11:05:34.582643 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6766 11:05:34.589359 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6767 11:05:34.592374 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6768 11:05:34.595989 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6769 11:05:34.599348 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6770 11:05:34.605907 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6771 11:05:34.609076 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6772 11:05:34.612651 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6773 11:05:34.618859 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6774 11:05:34.619384 ==
6775 11:05:34.622520 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 11:05:34.625737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 11:05:34.626289 ==
6778 11:05:34.626637 DQS Delay:
6779 11:05:34.628348 DQS0 = 43, DQS1 = 51
6780 11:05:34.628769 DQM Delay:
6781 11:05:34.631780 DQM0 = 12, DQM1 = 14
6782 11:05:34.632202 DQ Delay:
6783 11:05:34.635272 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6784 11:05:34.638588 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6785 11:05:34.641745 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6786 11:05:34.645184 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6787 11:05:34.645699
6788 11:05:34.646040
6789 11:05:34.646349 ==
6790 11:05:34.648510 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 11:05:34.651487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 11:05:34.651962 ==
6793 11:05:34.652300
6794 11:05:34.652610
6795 11:05:34.655165 TX Vref Scan disable
6796 11:05:34.657906 == TX Byte 0 ==
6797 11:05:34.661674 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 11:05:34.665336 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 11:05:34.667801 == TX Byte 1 ==
6800 11:05:34.671499 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6801 11:05:34.674627 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6802 11:05:34.675055 ==
6803 11:05:34.677869 Dram Type= 6, Freq= 0, CH_1, rank 0
6804 11:05:34.681336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 11:05:34.684682 ==
6806 11:05:34.685102
6807 11:05:34.685437
6808 11:05:34.685751 TX Vref Scan disable
6809 11:05:34.687757 == TX Byte 0 ==
6810 11:05:34.690877 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6811 11:05:34.694066 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6812 11:05:34.697656 == TX Byte 1 ==
6813 11:05:34.700904 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6814 11:05:34.704644 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6815 11:05:34.705172
6816 11:05:34.707525 [DATLAT]
6817 11:05:34.708083 Freq=400, CH1 RK0
6818 11:05:34.708431
6819 11:05:34.711088 DATLAT Default: 0xf
6820 11:05:34.711750 0, 0xFFFF, sum = 0
6821 11:05:34.714091 1, 0xFFFF, sum = 0
6822 11:05:34.714621 2, 0xFFFF, sum = 0
6823 11:05:34.717484 3, 0xFFFF, sum = 0
6824 11:05:34.718015 4, 0xFFFF, sum = 0
6825 11:05:34.720640 5, 0xFFFF, sum = 0
6826 11:05:34.721172 6, 0xFFFF, sum = 0
6827 11:05:34.724129 7, 0xFFFF, sum = 0
6828 11:05:34.724665 8, 0xFFFF, sum = 0
6829 11:05:34.727507 9, 0xFFFF, sum = 0
6830 11:05:34.730552 10, 0xFFFF, sum = 0
6831 11:05:34.731088 11, 0xFFFF, sum = 0
6832 11:05:34.734215 12, 0xFFFF, sum = 0
6833 11:05:34.734642 13, 0x0, sum = 1
6834 11:05:34.737137 14, 0x0, sum = 2
6835 11:05:34.737563 15, 0x0, sum = 3
6836 11:05:34.740358 16, 0x0, sum = 4
6837 11:05:34.740784 best_step = 14
6838 11:05:34.741122
6839 11:05:34.741433 ==
6840 11:05:34.743180 Dram Type= 6, Freq= 0, CH_1, rank 0
6841 11:05:34.746783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 11:05:34.747209 ==
6843 11:05:34.750529 RX Vref Scan: 1
6844 11:05:34.751052
6845 11:05:34.753468 RX Vref 0 -> 0, step: 1
6846 11:05:34.754005
6847 11:05:34.754349 RX Delay -343 -> 252, step: 8
6848 11:05:34.756535
6849 11:05:34.756958 Set Vref, RX VrefLevel [Byte0]: 47
6850 11:05:34.760142 [Byte1]: 52
6851 11:05:34.765853
6852 11:05:34.766383 Final RX Vref Byte 0 = 47 to rank0
6853 11:05:34.769514 Final RX Vref Byte 1 = 52 to rank0
6854 11:05:34.772114 Final RX Vref Byte 0 = 47 to rank1
6855 11:05:34.775725 Final RX Vref Byte 1 = 52 to rank1==
6856 11:05:34.778933 Dram Type= 6, Freq= 0, CH_1, rank 0
6857 11:05:34.785646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 11:05:34.786168 ==
6859 11:05:34.786511 DQS Delay:
6860 11:05:34.788964 DQS0 = 44, DQS1 = 56
6861 11:05:34.789386 DQM Delay:
6862 11:05:34.789725 DQM0 = 8, DQM1 = 12
6863 11:05:34.791872 DQ Delay:
6864 11:05:34.795429 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6865 11:05:34.795999 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6866 11:05:34.798825 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6867 11:05:34.801994 DQ12 =24, DQ13 =16, DQ14 =20, DQ15 =20
6868 11:05:34.802420
6869 11:05:34.805553
6870 11:05:34.812095 [DQSOSCAuto] RK0, (LSB)MR18= 0x936a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6871 11:05:34.815211 CH1 RK0: MR19=C0C, MR18=936A
6872 11:05:34.821610 CH1_RK0: MR19=0xC0C, MR18=0x936A, DQSOSC=391, MR23=63, INC=386, DEC=257
6873 11:05:34.822121 ==
6874 11:05:34.825435 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 11:05:34.828143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 11:05:34.828572 ==
6877 11:05:34.832044 [Gating] SW mode calibration
6878 11:05:34.838552 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6879 11:05:34.845342 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6880 11:05:34.847908 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6881 11:05:34.851753 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6882 11:05:34.858196 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6883 11:05:34.861598 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 11:05:34.864692 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6885 11:05:34.871710 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6886 11:05:34.874787 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6887 11:05:34.878129 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 11:05:34.884440 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 11:05:34.884948 Total UI for P1: 0, mck2ui 16
6890 11:05:34.890868 best dqsien dly found for B0: ( 0, 14, 24)
6891 11:05:34.891461 Total UI for P1: 0, mck2ui 16
6892 11:05:34.898060 best dqsien dly found for B1: ( 0, 14, 24)
6893 11:05:34.901279 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6894 11:05:34.904825 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6895 11:05:34.905349
6896 11:05:34.908013 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6897 11:05:34.910752 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6898 11:05:34.914351 [Gating] SW calibration Done
6899 11:05:34.914876 ==
6900 11:05:34.917528 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 11:05:34.920884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 11:05:34.921437 ==
6903 11:05:34.924260 RX Vref Scan: 0
6904 11:05:34.924815
6905 11:05:34.925167 RX Vref 0 -> 0, step: 1
6906 11:05:34.925484
6907 11:05:34.927251 RX Delay -410 -> 252, step: 16
6908 11:05:34.934382 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6909 11:05:34.937758 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6910 11:05:34.940508 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6911 11:05:34.944536 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6912 11:05:34.950629 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6913 11:05:34.954298 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6914 11:05:34.956848 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6915 11:05:34.960419 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6916 11:05:34.967160 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6917 11:05:34.970489 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6918 11:05:34.973792 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6919 11:05:34.976877 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6920 11:05:34.983763 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6921 11:05:34.986639 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6922 11:05:34.989911 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6923 11:05:34.996345 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6924 11:05:34.996770 ==
6925 11:05:34.999859 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 11:05:35.003158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 11:05:35.003873 ==
6928 11:05:35.004483 DQS Delay:
6929 11:05:35.006619 DQS0 = 51, DQS1 = 51
6930 11:05:35.007095 DQM Delay:
6931 11:05:35.009595 DQM0 = 20, DQM1 = 14
6932 11:05:35.010042 DQ Delay:
6933 11:05:35.012770 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =24
6934 11:05:35.016111 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6935 11:05:35.019558 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6936 11:05:35.022276 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6937 11:05:35.022507
6938 11:05:35.022679
6939 11:05:35.022844 ==
6940 11:05:35.025690 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 11:05:35.029079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 11:05:35.029210 ==
6943 11:05:35.032545
6944 11:05:35.032657
6945 11:05:35.032747 TX Vref Scan disable
6946 11:05:35.036081 == TX Byte 0 ==
6947 11:05:35.039017 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6948 11:05:35.042074 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6949 11:05:35.045619 == TX Byte 1 ==
6950 11:05:35.049086 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6951 11:05:35.051917 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6952 11:05:35.052009 ==
6953 11:05:35.055611 Dram Type= 6, Freq= 0, CH_1, rank 1
6954 11:05:35.058661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6955 11:05:35.062173 ==
6956 11:05:35.062299
6957 11:05:35.062421
6958 11:05:35.062540 TX Vref Scan disable
6959 11:05:35.065346 == TX Byte 0 ==
6960 11:05:35.068221 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6961 11:05:35.071784 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6962 11:05:35.075285 == TX Byte 1 ==
6963 11:05:35.078217 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6964 11:05:35.081655 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6965 11:05:35.081754
6966 11:05:35.084746 [DATLAT]
6967 11:05:35.084888 Freq=400, CH1 RK1
6968 11:05:35.085012
6969 11:05:35.088330 DATLAT Default: 0xe
6970 11:05:35.088412 0, 0xFFFF, sum = 0
6971 11:05:35.091260 1, 0xFFFF, sum = 0
6972 11:05:35.091381 2, 0xFFFF, sum = 0
6973 11:05:35.094871 3, 0xFFFF, sum = 0
6974 11:05:35.094985 4, 0xFFFF, sum = 0
6975 11:05:35.098163 5, 0xFFFF, sum = 0
6976 11:05:35.098274 6, 0xFFFF, sum = 0
6977 11:05:35.101465 7, 0xFFFF, sum = 0
6978 11:05:35.101604 8, 0xFFFF, sum = 0
6979 11:05:35.104771 9, 0xFFFF, sum = 0
6980 11:05:35.104909 10, 0xFFFF, sum = 0
6981 11:05:35.108428 11, 0xFFFF, sum = 0
6982 11:05:35.110984 12, 0xFFFF, sum = 0
6983 11:05:35.111090 13, 0x0, sum = 1
6984 11:05:35.114177 14, 0x0, sum = 2
6985 11:05:35.114280 15, 0x0, sum = 3
6986 11:05:35.114374 16, 0x0, sum = 4
6987 11:05:35.117648 best_step = 14
6988 11:05:35.117773
6989 11:05:35.117892 ==
6990 11:05:35.121001 Dram Type= 6, Freq= 0, CH_1, rank 1
6991 11:05:35.124503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 11:05:35.124640 ==
6993 11:05:35.127749 RX Vref Scan: 0
6994 11:05:35.127881
6995 11:05:35.128000 RX Vref 0 -> 0, step: 1
6996 11:05:35.130870
6997 11:05:35.130999 RX Delay -343 -> 252, step: 8
6998 11:05:35.139551 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
6999 11:05:35.142546 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7000 11:05:35.145862 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7001 11:05:35.152778 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
7002 11:05:35.156209 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7003 11:05:35.159316 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7004 11:05:35.163159 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7005 11:05:35.169013 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7006 11:05:35.172629 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7007 11:05:35.175888 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7008 11:05:35.179320 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
7009 11:05:35.186038 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7010 11:05:35.189101 iDelay=225, Bit 12, Center -32 (-279 ~ 216) 496
7011 11:05:35.192526 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7012 11:05:35.199362 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7013 11:05:35.202392 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
7014 11:05:35.202648 ==
7015 11:05:35.206145 Dram Type= 6, Freq= 0, CH_1, rank 1
7016 11:05:35.208678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7017 11:05:35.208982 ==
7018 11:05:35.212343 DQS Delay:
7019 11:05:35.212786 DQS0 = 48, DQS1 = 56
7020 11:05:35.213278 DQM Delay:
7021 11:05:35.215625 DQM0 = 13, DQM1 = 11
7022 11:05:35.216120 DQ Delay:
7023 11:05:35.218620 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7024 11:05:35.222096 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
7025 11:05:35.225455 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7026 11:05:35.228455 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
7027 11:05:35.228589
7028 11:05:35.228750
7029 11:05:35.238298 [DQSOSCAuto] RK1, (LSB)MR18= 0x6252, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7030 11:05:35.238506 CH1 RK1: MR19=C0C, MR18=6252
7031 11:05:35.244722 CH1_RK1: MR19=0xC0C, MR18=0x6252, DQSOSC=397, MR23=63, INC=374, DEC=249
7032 11:05:35.248143 [RxdqsGatingPostProcess] freq 400
7033 11:05:35.254777 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7034 11:05:35.257849 best DQS0 dly(2T, 0.5T) = (0, 10)
7035 11:05:35.261239 best DQS1 dly(2T, 0.5T) = (0, 10)
7036 11:05:35.264187 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7037 11:05:35.268104 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7038 11:05:35.270703 best DQS0 dly(2T, 0.5T) = (0, 10)
7039 11:05:35.274223 best DQS1 dly(2T, 0.5T) = (0, 10)
7040 11:05:35.278059 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7041 11:05:35.280966 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7042 11:05:35.284374 Pre-setting of DQS Precalculation
7043 11:05:35.287919 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7044 11:05:35.294129 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7045 11:05:35.301036 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7046 11:05:35.301368
7047 11:05:35.304359
7048 11:05:35.304598 [Calibration Summary] 800 Mbps
7049 11:05:35.307228 CH 0, Rank 0
7050 11:05:35.307464 SW Impedance : PASS
7051 11:05:35.310878 DUTY Scan : NO K
7052 11:05:35.313839 ZQ Calibration : PASS
7053 11:05:35.314077 Jitter Meter : NO K
7054 11:05:35.317341 CBT Training : PASS
7055 11:05:35.320810 Write leveling : PASS
7056 11:05:35.321047 RX DQS gating : PASS
7057 11:05:35.324653 RX DQ/DQS(RDDQC) : PASS
7058 11:05:35.326853 TX DQ/DQS : PASS
7059 11:05:35.327090 RX DATLAT : PASS
7060 11:05:35.330744 RX DQ/DQS(Engine): PASS
7061 11:05:35.333537 TX OE : NO K
7062 11:05:35.333789 All Pass.
7063 11:05:35.333978
7064 11:05:35.334152 CH 0, Rank 1
7065 11:05:35.337101 SW Impedance : PASS
7066 11:05:35.340454 DUTY Scan : NO K
7067 11:05:35.340690 ZQ Calibration : PASS
7068 11:05:35.343362 Jitter Meter : NO K
7069 11:05:35.346958 CBT Training : PASS
7070 11:05:35.347333 Write leveling : NO K
7071 11:05:35.350390 RX DQS gating : PASS
7072 11:05:35.353568 RX DQ/DQS(RDDQC) : PASS
7073 11:05:35.354047 TX DQ/DQS : PASS
7074 11:05:35.356978 RX DATLAT : PASS
7075 11:05:35.357366 RX DQ/DQS(Engine): PASS
7076 11:05:35.360077 TX OE : NO K
7077 11:05:35.360707 All Pass.
7078 11:05:35.361252
7079 11:05:35.363265 CH 1, Rank 0
7080 11:05:35.363776 SW Impedance : PASS
7081 11:05:35.366851 DUTY Scan : NO K
7082 11:05:35.370044 ZQ Calibration : PASS
7083 11:05:35.370420 Jitter Meter : NO K
7084 11:05:35.373334 CBT Training : PASS
7085 11:05:35.376310 Write leveling : PASS
7086 11:05:35.376536 RX DQS gating : PASS
7087 11:05:35.379412 RX DQ/DQS(RDDQC) : PASS
7088 11:05:35.382883 TX DQ/DQS : PASS
7089 11:05:35.383053 RX DATLAT : PASS
7090 11:05:35.385903 RX DQ/DQS(Engine): PASS
7091 11:05:35.389298 TX OE : NO K
7092 11:05:35.389544 All Pass.
7093 11:05:35.389679
7094 11:05:35.389790 CH 1, Rank 1
7095 11:05:35.392784 SW Impedance : PASS
7096 11:05:35.396087 DUTY Scan : NO K
7097 11:05:35.396215 ZQ Calibration : PASS
7098 11:05:35.399470 Jitter Meter : NO K
7099 11:05:35.402803 CBT Training : PASS
7100 11:05:35.402903 Write leveling : NO K
7101 11:05:35.405622 RX DQS gating : PASS
7102 11:05:35.409319 RX DQ/DQS(RDDQC) : PASS
7103 11:05:35.409447 TX DQ/DQS : PASS
7104 11:05:35.412884 RX DATLAT : PASS
7105 11:05:35.415991 RX DQ/DQS(Engine): PASS
7106 11:05:35.416081 TX OE : NO K
7107 11:05:35.419009 All Pass.
7108 11:05:35.419094
7109 11:05:35.419159 DramC Write-DBI off
7110 11:05:35.422266 PER_BANK_REFRESH: Hybrid Mode
7111 11:05:35.422392 TX_TRACKING: ON
7112 11:05:35.432355 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7113 11:05:35.435474 [FAST_K] Save calibration result to emmc
7114 11:05:35.439222 dramc_set_vcore_voltage set vcore to 725000
7115 11:05:35.442679 Read voltage for 1600, 0
7116 11:05:35.442775 Vio18 = 0
7117 11:05:35.445446 Vcore = 725000
7118 11:05:35.445532 Vdram = 0
7119 11:05:35.445597 Vddq = 0
7120 11:05:35.449147 Vmddr = 0
7121 11:05:35.452135 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7122 11:05:35.458829 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7123 11:05:35.458964 MEM_TYPE=3, freq_sel=13
7124 11:05:35.461888 sv_algorithm_assistance_LP4_3733
7125 11:05:35.468847 ============ PULL DRAM RESETB DOWN ============
7126 11:05:35.472399 ========== PULL DRAM RESETB DOWN end =========
7127 11:05:35.475266 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7128 11:05:35.478268 ===================================
7129 11:05:35.481715 LPDDR4 DRAM CONFIGURATION
7130 11:05:35.485316 ===================================
7131 11:05:35.488937 EX_ROW_EN[0] = 0x0
7132 11:05:35.489034 EX_ROW_EN[1] = 0x0
7133 11:05:35.491719 LP4Y_EN = 0x0
7134 11:05:35.491820 WORK_FSP = 0x1
7135 11:05:35.494994 WL = 0x5
7136 11:05:35.495080 RL = 0x5
7137 11:05:35.498158 BL = 0x2
7138 11:05:35.498244 RPST = 0x0
7139 11:05:35.501462 RD_PRE = 0x0
7140 11:05:35.501549 WR_PRE = 0x1
7141 11:05:35.504809 WR_PST = 0x1
7142 11:05:35.504899 DBI_WR = 0x0
7143 11:05:35.508272 DBI_RD = 0x0
7144 11:05:35.508361 OTF = 0x1
7145 11:05:35.511381 ===================================
7146 11:05:35.514443 ===================================
7147 11:05:35.517962 ANA top config
7148 11:05:35.521461 ===================================
7149 11:05:35.524941 DLL_ASYNC_EN = 0
7150 11:05:35.525044 ALL_SLAVE_EN = 0
7151 11:05:35.527706 NEW_RANK_MODE = 1
7152 11:05:35.531009 DLL_IDLE_MODE = 1
7153 11:05:35.534477 LP45_APHY_COMB_EN = 1
7154 11:05:35.537831 TX_ODT_DIS = 0
7155 11:05:35.537934 NEW_8X_MODE = 1
7156 11:05:35.541132 ===================================
7157 11:05:35.544556 ===================================
7158 11:05:35.547897 data_rate = 3200
7159 11:05:35.551162 CKR = 1
7160 11:05:35.554311 DQ_P2S_RATIO = 8
7161 11:05:35.557536 ===================================
7162 11:05:35.561020 CA_P2S_RATIO = 8
7163 11:05:35.564531 DQ_CA_OPEN = 0
7164 11:05:35.564633 DQ_SEMI_OPEN = 0
7165 11:05:35.567438 CA_SEMI_OPEN = 0
7166 11:05:35.570701 CA_FULL_RATE = 0
7167 11:05:35.574161 DQ_CKDIV4_EN = 0
7168 11:05:35.577196 CA_CKDIV4_EN = 0
7169 11:05:35.581109 CA_PREDIV_EN = 0
7170 11:05:35.581200 PH8_DLY = 12
7171 11:05:35.583988 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7172 11:05:35.586955 DQ_AAMCK_DIV = 4
7173 11:05:35.590503 CA_AAMCK_DIV = 4
7174 11:05:35.594371 CA_ADMCK_DIV = 4
7175 11:05:35.596896 DQ_TRACK_CA_EN = 0
7176 11:05:35.601461 CA_PICK = 1600
7177 11:05:35.601552 CA_MCKIO = 1600
7178 11:05:35.603454 MCKIO_SEMI = 0
7179 11:05:35.606689 PLL_FREQ = 3068
7180 11:05:35.610608 DQ_UI_PI_RATIO = 32
7181 11:05:35.613276 CA_UI_PI_RATIO = 0
7182 11:05:35.616632 ===================================
7183 11:05:35.619851 ===================================
7184 11:05:35.623149 memory_type:LPDDR4
7185 11:05:35.623232 GP_NUM : 10
7186 11:05:35.626718 SRAM_EN : 1
7187 11:05:35.630118 MD32_EN : 0
7188 11:05:35.633144 ===================================
7189 11:05:35.633230 [ANA_INIT] >>>>>>>>>>>>>>
7190 11:05:35.636281 <<<<<< [CONFIGURE PHASE]: ANA_TX
7191 11:05:35.639718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7192 11:05:35.643162 ===================================
7193 11:05:35.646801 data_rate = 3200,PCW = 0X7600
7194 11:05:35.649513 ===================================
7195 11:05:35.652812 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7196 11:05:35.659710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7197 11:05:35.662911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7198 11:05:35.669910 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7199 11:05:35.673168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7200 11:05:35.676046 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7201 11:05:35.676129 [ANA_INIT] flow start
7202 11:05:35.679423 [ANA_INIT] PLL >>>>>>>>
7203 11:05:35.682920 [ANA_INIT] PLL <<<<<<<<
7204 11:05:35.685802 [ANA_INIT] MIDPI >>>>>>>>
7205 11:05:35.685885 [ANA_INIT] MIDPI <<<<<<<<
7206 11:05:35.689147 [ANA_INIT] DLL >>>>>>>>
7207 11:05:35.692309 [ANA_INIT] DLL <<<<<<<<
7208 11:05:35.692423 [ANA_INIT] flow end
7209 11:05:35.695903 ============ LP4 DIFF to SE enter ============
7210 11:05:35.702319 ============ LP4 DIFF to SE exit ============
7211 11:05:35.702424 [ANA_INIT] <<<<<<<<<<<<<
7212 11:05:35.705328 [Flow] Enable top DCM control >>>>>
7213 11:05:35.708695 [Flow] Enable top DCM control <<<<<
7214 11:05:35.712416 Enable DLL master slave shuffle
7215 11:05:35.718874 ==============================================================
7216 11:05:35.722158 Gating Mode config
7217 11:05:35.725160 ==============================================================
7218 11:05:35.728461 Config description:
7219 11:05:35.738588 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7220 11:05:35.745382 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7221 11:05:35.748887 SELPH_MODE 0: By rank 1: By Phase
7222 11:05:35.754981 ==============================================================
7223 11:05:35.758317 GAT_TRACK_EN = 1
7224 11:05:35.761552 RX_GATING_MODE = 2
7225 11:05:35.765484 RX_GATING_TRACK_MODE = 2
7226 11:05:35.768353 SELPH_MODE = 1
7227 11:05:35.768435 PICG_EARLY_EN = 1
7228 11:05:35.771621 VALID_LAT_VALUE = 1
7229 11:05:35.778632 ==============================================================
7230 11:05:35.782077 Enter into Gating configuration >>>>
7231 11:05:35.785406 Exit from Gating configuration <<<<
7232 11:05:35.788277 Enter into DVFS_PRE_config >>>>>
7233 11:05:35.798166 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7234 11:05:35.801888 Exit from DVFS_PRE_config <<<<<
7235 11:05:35.804813 Enter into PICG configuration >>>>
7236 11:05:35.807770 Exit from PICG configuration <<<<
7237 11:05:35.811299 [RX_INPUT] configuration >>>>>
7238 11:05:35.814332 [RX_INPUT] configuration <<<<<
7239 11:05:35.821958 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7240 11:05:35.824647 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7241 11:05:35.830985 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7242 11:05:35.837726 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7243 11:05:35.843924 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7244 11:05:35.850548 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7245 11:05:35.853933 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7246 11:05:35.857026 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7247 11:05:35.860168 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7248 11:05:35.867232 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7249 11:05:35.870115 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7250 11:05:35.873755 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7251 11:05:35.876665 ===================================
7252 11:05:35.880179 LPDDR4 DRAM CONFIGURATION
7253 11:05:35.883442 ===================================
7254 11:05:35.886842 EX_ROW_EN[0] = 0x0
7255 11:05:35.887160 EX_ROW_EN[1] = 0x0
7256 11:05:35.890231 LP4Y_EN = 0x0
7257 11:05:35.890548 WORK_FSP = 0x1
7258 11:05:35.893525 WL = 0x5
7259 11:05:35.893760 RL = 0x5
7260 11:05:35.896493 BL = 0x2
7261 11:05:35.896694 RPST = 0x0
7262 11:05:35.900217 RD_PRE = 0x0
7263 11:05:35.900404 WR_PRE = 0x1
7264 11:05:35.903405 WR_PST = 0x1
7265 11:05:35.903858 DBI_WR = 0x0
7266 11:05:35.906976 DBI_RD = 0x0
7267 11:05:35.907399 OTF = 0x1
7268 11:05:35.910368 ===================================
7269 11:05:35.916506 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7270 11:05:35.920091 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7271 11:05:35.923096 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7272 11:05:35.926573 ===================================
7273 11:05:35.930006 LPDDR4 DRAM CONFIGURATION
7274 11:05:35.933432 ===================================
7275 11:05:35.936536 EX_ROW_EN[0] = 0x10
7276 11:05:35.936807 EX_ROW_EN[1] = 0x0
7277 11:05:35.939324 LP4Y_EN = 0x0
7278 11:05:35.939598 WORK_FSP = 0x1
7279 11:05:35.942592 WL = 0x5
7280 11:05:35.942864 RL = 0x5
7281 11:05:35.946197 BL = 0x2
7282 11:05:35.946491 RPST = 0x0
7283 11:05:35.949684 RD_PRE = 0x0
7284 11:05:35.949957 WR_PRE = 0x1
7285 11:05:35.953104 WR_PST = 0x1
7286 11:05:35.953376 DBI_WR = 0x0
7287 11:05:35.956001 DBI_RD = 0x0
7288 11:05:35.956275 OTF = 0x1
7289 11:05:35.959023 ===================================
7290 11:05:35.966070 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7291 11:05:35.966347 ==
7292 11:05:35.969421 Dram Type= 6, Freq= 0, CH_0, rank 0
7293 11:05:35.975749 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7294 11:05:35.976028 ==
7295 11:05:35.976271 [Duty_Offset_Calibration]
7296 11:05:35.978898 B0:1 B1:-1 CA:0
7297 11:05:35.979170
7298 11:05:35.982249 [DutyScan_Calibration_Flow] k_type=0
7299 11:05:35.992187
7300 11:05:35.992359 ==CLK 0==
7301 11:05:35.995358 Final CLK duty delay cell = 0
7302 11:05:35.998521 [0] MAX Duty = 5125%(X100), DQS PI = 20
7303 11:05:36.001763 [0] MIN Duty = 4907%(X100), DQS PI = 4
7304 11:05:36.005206 [0] AVG Duty = 5016%(X100)
7305 11:05:36.005334
7306 11:05:36.008416 CH0 CLK Duty spec in!! Max-Min= 218%
7307 11:05:36.012012 [DutyScan_Calibration_Flow] ====Done====
7308 11:05:36.012113
7309 11:05:36.015065 [DutyScan_Calibration_Flow] k_type=1
7310 11:05:36.031254
7311 11:05:36.031391 ==DQS 0 ==
7312 11:05:36.034179 Final DQS duty delay cell = -4
7313 11:05:36.037801 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7314 11:05:36.040956 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7315 11:05:36.044164 [-4] AVG Duty = 4922%(X100)
7316 11:05:36.044261
7317 11:05:36.044348 ==DQS 1 ==
7318 11:05:36.047339 Final DQS duty delay cell = 0
7319 11:05:36.050563 [0] MAX Duty = 5156%(X100), DQS PI = 2
7320 11:05:36.053898 [0] MIN Duty = 5000%(X100), DQS PI = 22
7321 11:05:36.057098 [0] AVG Duty = 5078%(X100)
7322 11:05:36.057178
7323 11:05:36.060625 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7324 11:05:36.060706
7325 11:05:36.064044 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7326 11:05:36.067025 [DutyScan_Calibration_Flow] ====Done====
7327 11:05:36.067105
7328 11:05:36.070122 [DutyScan_Calibration_Flow] k_type=3
7329 11:05:36.088788
7330 11:05:36.089162 ==DQM 0 ==
7331 11:05:36.092217 Final DQM duty delay cell = 0
7332 11:05:36.095745 [0] MAX Duty = 5124%(X100), DQS PI = 22
7333 11:05:36.098650 [0] MIN Duty = 4907%(X100), DQS PI = 8
7334 11:05:36.101789 [0] AVG Duty = 5015%(X100)
7335 11:05:36.102271
7336 11:05:36.102579 ==DQM 1 ==
7337 11:05:36.105219 Final DQM duty delay cell = 0
7338 11:05:36.108936 [0] MAX Duty = 5031%(X100), DQS PI = 10
7339 11:05:36.112862 [0] MIN Duty = 4813%(X100), DQS PI = 20
7340 11:05:36.114990 [0] AVG Duty = 4922%(X100)
7341 11:05:36.115430
7342 11:05:36.118670 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7343 11:05:36.119048
7344 11:05:36.121848 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7345 11:05:36.124676 [DutyScan_Calibration_Flow] ====Done====
7346 11:05:36.125053
7347 11:05:36.128240 [DutyScan_Calibration_Flow] k_type=2
7348 11:05:36.144705
7349 11:05:36.144917 ==DQ 0 ==
7350 11:05:36.148420 Final DQ duty delay cell = -4
7351 11:05:36.151477 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7352 11:05:36.154840 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7353 11:05:36.157756 [-4] AVG Duty = 4953%(X100)
7354 11:05:36.157882
7355 11:05:36.157981 ==DQ 1 ==
7356 11:05:36.161090 Final DQ duty delay cell = 0
7357 11:05:36.164351 [0] MAX Duty = 5125%(X100), DQS PI = 2
7358 11:05:36.168064 [0] MIN Duty = 5000%(X100), DQS PI = 36
7359 11:05:36.170916 [0] AVG Duty = 5062%(X100)
7360 11:05:36.171015
7361 11:05:36.174536 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7362 11:05:36.174625
7363 11:05:36.178161 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7364 11:05:36.181306 [DutyScan_Calibration_Flow] ====Done====
7365 11:05:36.181388 ==
7366 11:05:36.184181 Dram Type= 6, Freq= 0, CH_1, rank 0
7367 11:05:36.187488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7368 11:05:36.187581 ==
7369 11:05:36.191025 [Duty_Offset_Calibration]
7370 11:05:36.191108 B0:-1 B1:1 CA:2
7371 11:05:36.191172
7372 11:05:36.194488 [DutyScan_Calibration_Flow] k_type=0
7373 11:05:36.205339
7374 11:05:36.205496 ==CLK 0==
7375 11:05:36.208888 Final CLK duty delay cell = 0
7376 11:05:36.212301 [0] MAX Duty = 5187%(X100), DQS PI = 22
7377 11:05:36.215474 [0] MIN Duty = 5000%(X100), DQS PI = 0
7378 11:05:36.218428 [0] AVG Duty = 5093%(X100)
7379 11:05:36.218508
7380 11:05:36.221765 CH1 CLK Duty spec in!! Max-Min= 187%
7381 11:05:36.225109 [DutyScan_Calibration_Flow] ====Done====
7382 11:05:36.225273
7383 11:05:36.228788 [DutyScan_Calibration_Flow] k_type=1
7384 11:05:36.245065
7385 11:05:36.245232 ==DQS 0 ==
7386 11:05:36.248713 Final DQS duty delay cell = 0
7387 11:05:36.252082 [0] MAX Duty = 5124%(X100), DQS PI = 18
7388 11:05:36.254822 [0] MIN Duty = 4907%(X100), DQS PI = 10
7389 11:05:36.258677 [0] AVG Duty = 5015%(X100)
7390 11:05:36.258932
7391 11:05:36.259052 ==DQS 1 ==
7392 11:05:36.262192 Final DQS duty delay cell = 0
7393 11:05:36.265186 [0] MAX Duty = 5093%(X100), DQS PI = 24
7394 11:05:36.268146 [0] MIN Duty = 4969%(X100), DQS PI = 56
7395 11:05:36.271514 [0] AVG Duty = 5031%(X100)
7396 11:05:36.271735
7397 11:05:36.275146 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7398 11:05:36.275309
7399 11:05:36.278024 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7400 11:05:36.281480 [DutyScan_Calibration_Flow] ====Done====
7401 11:05:36.281682
7402 11:05:36.284592 [DutyScan_Calibration_Flow] k_type=3
7403 11:05:36.302449
7404 11:05:36.302780 ==DQM 0 ==
7405 11:05:36.305395 Final DQM duty delay cell = 0
7406 11:05:36.308898 [0] MAX Duty = 5218%(X100), DQS PI = 18
7407 11:05:36.312296 [0] MIN Duty = 5031%(X100), DQS PI = 8
7408 11:05:36.315272 [0] AVG Duty = 5124%(X100)
7409 11:05:36.315558
7410 11:05:36.315820 ==DQM 1 ==
7411 11:05:36.318864 Final DQM duty delay cell = 0
7412 11:05:36.321729 [0] MAX Duty = 5125%(X100), DQS PI = 0
7413 11:05:36.325275 [0] MIN Duty = 4969%(X100), DQS PI = 34
7414 11:05:36.328395 [0] AVG Duty = 5047%(X100)
7415 11:05:36.328637
7416 11:05:36.331855 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7417 11:05:36.332096
7418 11:05:36.335400 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7419 11:05:36.338277 [DutyScan_Calibration_Flow] ====Done====
7420 11:05:36.338537
7421 11:05:36.341546 [DutyScan_Calibration_Flow] k_type=2
7422 11:05:36.359630
7423 11:05:36.360343 ==DQ 0 ==
7424 11:05:36.363276 Final DQ duty delay cell = 0
7425 11:05:36.366538 [0] MAX Duty = 5187%(X100), DQS PI = 32
7426 11:05:36.369135 [0] MIN Duty = 4906%(X100), DQS PI = 8
7427 11:05:36.369668 [0] AVG Duty = 5046%(X100)
7428 11:05:36.372838
7429 11:05:36.373258 ==DQ 1 ==
7430 11:05:36.375630 Final DQ duty delay cell = 0
7431 11:05:36.379053 [0] MAX Duty = 5125%(X100), DQS PI = 8
7432 11:05:36.383176 [0] MIN Duty = 4969%(X100), DQS PI = 56
7433 11:05:36.383766 [0] AVG Duty = 5047%(X100)
7434 11:05:36.385626
7435 11:05:36.388920 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7436 11:05:36.389450
7437 11:05:36.392119 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7438 11:05:36.395715 [DutyScan_Calibration_Flow] ====Done====
7439 11:05:36.398824 nWR fixed to 30
7440 11:05:36.402113 [ModeRegInit_LP4] CH0 RK0
7441 11:05:36.402636 [ModeRegInit_LP4] CH0 RK1
7442 11:05:36.405654 [ModeRegInit_LP4] CH1 RK0
7443 11:05:36.409038 [ModeRegInit_LP4] CH1 RK1
7444 11:05:36.409552 match AC timing 5
7445 11:05:36.415348 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7446 11:05:36.418956 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7447 11:05:36.422107 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7448 11:05:36.428457 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7449 11:05:36.431492 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7450 11:05:36.431959 [MiockJmeterHQA]
7451 11:05:36.435009
7452 11:05:36.435456 [DramcMiockJmeter] u1RxGatingPI = 0
7453 11:05:36.437750 0 : 4363, 4138
7454 11:05:36.438397 4 : 4257, 4030
7455 11:05:36.441333 8 : 4257, 4029
7456 11:05:36.441756 12 : 4252, 4027
7457 11:05:36.444703 16 : 4253, 4027
7458 11:05:36.445126 20 : 4363, 4137
7459 11:05:36.447840 24 : 4253, 4027
7460 11:05:36.448264 28 : 4253, 4026
7461 11:05:36.448604 32 : 4252, 4027
7462 11:05:36.450907 36 : 4254, 4029
7463 11:05:36.451333 40 : 4363, 4138
7464 11:05:36.454789 44 : 4255, 4029
7465 11:05:36.455383 48 : 4363, 4137
7466 11:05:36.457978 52 : 4250, 4027
7467 11:05:36.458403 56 : 4250, 4027
7468 11:05:36.461191 60 : 4250, 4027
7469 11:05:36.461628 64 : 4363, 4138
7470 11:05:36.461972 68 : 4250, 4027
7471 11:05:36.464604 72 : 4360, 4138
7472 11:05:36.465034 76 : 4250, 4027
7473 11:05:36.467634 80 : 4250, 4027
7474 11:05:36.468119 84 : 4250, 4027
7475 11:05:36.471106 88 : 4252, 4029
7476 11:05:36.471552 92 : 4360, 331
7477 11:05:36.472023 96 : 4252, 0
7478 11:05:36.474285 100 : 4361, 0
7479 11:05:36.474715 104 : 4360, 0
7480 11:05:36.477518 108 : 4250, 0
7481 11:05:36.477958 112 : 4250, 0
7482 11:05:36.478297 116 : 4360, 0
7483 11:05:36.480426 120 : 4361, 0
7484 11:05:36.480851 124 : 4252, 0
7485 11:05:36.483872 128 : 4250, 0
7486 11:05:36.484296 132 : 4250, 0
7487 11:05:36.484635 136 : 4253, 0
7488 11:05:36.487447 140 : 4250, 0
7489 11:05:36.487978 144 : 4250, 0
7490 11:05:36.490975 148 : 4253, 0
7491 11:05:36.491449 152 : 4363, 0
7492 11:05:36.492039 156 : 4360, 0
7493 11:05:36.493875 160 : 4363, 0
7494 11:05:36.494344 164 : 4250, 0
7495 11:05:36.494679 168 : 4360, 0
7496 11:05:36.497503 172 : 4361, 0
7497 11:05:36.497925 176 : 4250, 0
7498 11:05:36.500732 180 : 4250, 0
7499 11:05:36.501155 184 : 4250, 0
7500 11:05:36.501491 188 : 4253, 0
7501 11:05:36.504141 192 : 4250, 0
7502 11:05:36.504567 196 : 4250, 0
7503 11:05:36.506900 200 : 4252, 0
7504 11:05:36.507322 204 : 4361, 0
7505 11:05:36.507662 208 : 4360, 0
7506 11:05:36.510695 212 : 4250, 0
7507 11:05:36.511118 216 : 4250, 0
7508 11:05:36.513509 220 : 4360, 0
7509 11:05:36.513936 224 : 4360, 485
7510 11:05:36.516785 228 : 4250, 3112
7511 11:05:36.517224 232 : 4250, 4027
7512 11:05:36.517598 236 : 4250, 4027
7513 11:05:36.520404 240 : 4250, 4026
7514 11:05:36.520927 244 : 4250, 4027
7515 11:05:36.524083 248 : 4250, 4027
7516 11:05:36.524613 252 : 4252, 4029
7517 11:05:36.527437 256 : 4250, 4026
7518 11:05:36.528018 260 : 4360, 4138
7519 11:05:36.529948 264 : 4360, 4138
7520 11:05:36.530481 268 : 4250, 4027
7521 11:05:36.533706 272 : 4363, 4140
7522 11:05:36.534235 276 : 4250, 4026
7523 11:05:36.537112 280 : 4253, 4029
7524 11:05:36.537534 284 : 4250, 4027
7525 11:05:36.540211 288 : 4252, 4030
7526 11:05:36.540646 292 : 4250, 4027
7527 11:05:36.543516 296 : 4250, 4027
7528 11:05:36.543980 300 : 4250, 4027
7529 11:05:36.544326 304 : 4252, 4029
7530 11:05:36.546674 308 : 4250, 4026
7531 11:05:36.547205 312 : 4361, 4137
7532 11:05:36.550127 316 : 4360, 4138
7533 11:05:36.550656 320 : 4251, 4027
7534 11:05:36.553627 324 : 4364, 4140
7535 11:05:36.554317 328 : 4250, 4026
7536 11:05:36.556044 332 : 4250, 4027
7537 11:05:36.556471 336 : 4253, 3506
7538 11:05:36.559893 340 : 4252, 1535
7539 11:05:36.560425
7540 11:05:36.560802 MIOCK jitter meter ch=0
7541 11:05:36.563004
7542 11:05:36.563441 1T = (340-92) = 248 dly cells
7543 11:05:36.569924 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7544 11:05:36.570458 ==
7545 11:05:36.573247 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 11:05:36.576436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 11:05:36.576972 ==
7548 11:05:36.582910 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7549 11:05:36.585792 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7550 11:05:36.592601 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7551 11:05:36.595807 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7552 11:05:36.606570 [CA 0] Center 43 (13~74) winsize 62
7553 11:05:36.610112 [CA 1] Center 43 (13~74) winsize 62
7554 11:05:36.613485 [CA 2] Center 39 (10~69) winsize 60
7555 11:05:36.616759 [CA 3] Center 39 (9~69) winsize 61
7556 11:05:36.619471 [CA 4] Center 37 (8~66) winsize 59
7557 11:05:36.623046 [CA 5] Center 36 (7~66) winsize 60
7558 11:05:36.623572
7559 11:05:36.626207 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7560 11:05:36.626732
7561 11:05:36.633343 [CATrainingPosCal] consider 1 rank data
7562 11:05:36.633867 u2DelayCellTimex100 = 262/100 ps
7563 11:05:36.639859 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7564 11:05:36.642587 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7565 11:05:36.646276 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7566 11:05:36.648822 CA3 delay=39 (9~69),Diff = 3 PI (11 cell)
7567 11:05:36.652238 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7568 11:05:36.655445 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7569 11:05:36.656006
7570 11:05:36.658925 CA PerBit enable=1, Macro0, CA PI delay=36
7571 11:05:36.662195
7572 11:05:36.662625 [CBTSetCACLKResult] CA Dly = 36
7573 11:05:36.665773 CS Dly: 12 (0~43)
7574 11:05:36.668674 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7575 11:05:36.672058 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7576 11:05:36.674959 ==
7577 11:05:36.678578 Dram Type= 6, Freq= 0, CH_0, rank 1
7578 11:05:36.681902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7579 11:05:36.682432 ==
7580 11:05:36.685514 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7581 11:05:36.691470 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7582 11:05:36.694924 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7583 11:05:36.702087 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7584 11:05:36.710293 [CA 0] Center 42 (12~73) winsize 62
7585 11:05:36.713041 [CA 1] Center 43 (13~73) winsize 61
7586 11:05:36.716358 [CA 2] Center 37 (8~67) winsize 60
7587 11:05:36.719785 [CA 3] Center 37 (7~67) winsize 61
7588 11:05:36.723410 [CA 4] Center 36 (6~66) winsize 61
7589 11:05:36.726998 [CA 5] Center 35 (5~65) winsize 61
7590 11:05:36.727544
7591 11:05:36.729325 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7592 11:05:36.729746
7593 11:05:36.736340 [CATrainingPosCal] consider 2 rank data
7594 11:05:36.736850 u2DelayCellTimex100 = 262/100 ps
7595 11:05:36.743035 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7596 11:05:36.747040 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7597 11:05:36.749909 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7598 11:05:36.753255 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7599 11:05:36.756107 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7600 11:05:36.759716 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7601 11:05:36.760252
7602 11:05:36.762312 CA PerBit enable=1, Macro0, CA PI delay=36
7603 11:05:36.762936
7604 11:05:36.766123 [CBTSetCACLKResult] CA Dly = 36
7605 11:05:36.769436 CS Dly: 12 (0~44)
7606 11:05:36.772548 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7607 11:05:36.775482 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7608 11:05:36.775940
7609 11:05:36.778899 ----->DramcWriteLeveling(PI) begin...
7610 11:05:36.782810 ==
7611 11:05:36.783333 Dram Type= 6, Freq= 0, CH_0, rank 0
7612 11:05:36.789501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7613 11:05:36.790031 ==
7614 11:05:36.792604 Write leveling (Byte 0): 36 => 36
7615 11:05:36.795519 Write leveling (Byte 1): 28 => 28
7616 11:05:36.798878 DramcWriteLeveling(PI) end<-----
7617 11:05:36.799466
7618 11:05:36.799850 ==
7619 11:05:36.802780 Dram Type= 6, Freq= 0, CH_0, rank 0
7620 11:05:36.805731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7621 11:05:36.806156 ==
7622 11:05:36.808578 [Gating] SW mode calibration
7623 11:05:36.815341 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7624 11:05:36.822117 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7625 11:05:36.825503 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 11:05:36.828982 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 11:05:36.836076 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 11:05:36.838991 1 4 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7629 11:05:36.841528 1 4 16 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7630 11:05:36.848371 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7631 11:05:36.851792 1 4 24 | B1->B0 | 2f2e 3434 | 1 1 | (1 1) (1 1)
7632 11:05:36.855481 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7633 11:05:36.861802 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7634 11:05:36.865152 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7635 11:05:36.868037 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7636 11:05:36.874489 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
7637 11:05:36.878060 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7638 11:05:36.881551 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7639 11:05:36.888617 1 5 24 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7640 11:05:36.891338 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 11:05:36.894224 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 11:05:36.901249 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 11:05:36.904678 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 11:05:36.907605 1 6 12 | B1->B0 | 2323 3939 | 0 1 | (0 0) (1 1)
7645 11:05:36.913738 1 6 16 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7646 11:05:36.917481 1 6 20 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
7647 11:05:36.921212 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7648 11:05:36.927755 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 11:05:36.931274 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 11:05:36.934132 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 11:05:36.940494 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 11:05:36.943425 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7653 11:05:36.947149 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7654 11:05:36.953982 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7655 11:05:36.957428 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 11:05:36.960132 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 11:05:36.966942 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 11:05:36.970479 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 11:05:36.973205 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 11:05:36.979826 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 11:05:36.983452 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 11:05:36.986424 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 11:05:36.993255 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 11:05:36.996126 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 11:05:37.000066 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 11:05:37.006739 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 11:05:37.009534 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 11:05:37.013228 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7669 11:05:37.019269 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7670 11:05:37.019851 Total UI for P1: 0, mck2ui 16
7671 11:05:37.026425 best dqsien dly found for B0: ( 1, 9, 12)
7672 11:05:37.029106 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7673 11:05:37.032544 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7674 11:05:37.038817 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 11:05:37.039240 Total UI for P1: 0, mck2ui 16
7676 11:05:37.045456 best dqsien dly found for B1: ( 1, 9, 20)
7677 11:05:37.049284 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7678 11:05:37.052246 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7679 11:05:37.052676
7680 11:05:37.055693 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7681 11:05:37.059083 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7682 11:05:37.062285 [Gating] SW calibration Done
7683 11:05:37.062714 ==
7684 11:05:37.065552 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 11:05:37.069016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 11:05:37.069550 ==
7687 11:05:37.071715 RX Vref Scan: 0
7688 11:05:37.072145
7689 11:05:37.072485 RX Vref 0 -> 0, step: 1
7690 11:05:37.075130
7691 11:05:37.075552 RX Delay 0 -> 252, step: 8
7692 11:05:37.079141 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7693 11:05:37.085404 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7694 11:05:37.088224 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7695 11:05:37.091846 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7696 11:05:37.095147 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7697 11:05:37.101582 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7698 11:05:37.105239 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7699 11:05:37.108734 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7700 11:05:37.111661 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7701 11:05:37.114721 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7702 11:05:37.121298 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7703 11:05:37.125266 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7704 11:05:37.128166 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7705 11:05:37.131517 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7706 11:05:37.134794 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7707 11:05:37.141997 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7708 11:05:37.142529 ==
7709 11:05:37.144170 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 11:05:37.147625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 11:05:37.148092 ==
7712 11:05:37.148435 DQS Delay:
7713 11:05:37.151537 DQS0 = 0, DQS1 = 0
7714 11:05:37.152108 DQM Delay:
7715 11:05:37.154117 DQM0 = 136, DQM1 = 126
7716 11:05:37.154537 DQ Delay:
7717 11:05:37.157899 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =135
7718 11:05:37.160949 DQ4 =135, DQ5 =123, DQ6 =147, DQ7 =147
7719 11:05:37.164053 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7720 11:05:37.170676 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7721 11:05:37.171177
7722 11:05:37.171525
7723 11:05:37.171953 ==
7724 11:05:37.173815 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 11:05:37.177201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 11:05:37.177621 ==
7727 11:05:37.178124
7728 11:05:37.178467
7729 11:05:37.180365 TX Vref Scan disable
7730 11:05:37.180783 == TX Byte 0 ==
7731 11:05:37.186958 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7732 11:05:37.190742 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7733 11:05:37.191267 == TX Byte 1 ==
7734 11:05:37.197132 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7735 11:05:37.200642 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7736 11:05:37.201161 ==
7737 11:05:37.203773 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 11:05:37.207057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 11:05:37.207582 ==
7740 11:05:37.221904
7741 11:05:37.224876 TX Vref early break, caculate TX vref
7742 11:05:37.228542 TX Vref=16, minBit 6, minWin=22, winSum=372
7743 11:05:37.231578 TX Vref=18, minBit 0, minWin=23, winSum=380
7744 11:05:37.235246 TX Vref=20, minBit 0, minWin=24, winSum=391
7745 11:05:37.237927 TX Vref=22, minBit 1, minWin=24, winSum=401
7746 11:05:37.241538 TX Vref=24, minBit 0, minWin=25, winSum=413
7747 11:05:37.247850 TX Vref=26, minBit 0, minWin=25, winSum=417
7748 11:05:37.251714 TX Vref=28, minBit 7, minWin=24, winSum=416
7749 11:05:37.254787 TX Vref=30, minBit 4, minWin=24, winSum=412
7750 11:05:37.258533 TX Vref=32, minBit 7, minWin=23, winSum=402
7751 11:05:37.261492 TX Vref=34, minBit 4, minWin=23, winSum=395
7752 11:05:37.268374 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 26
7753 11:05:37.268897
7754 11:05:37.271229 Final TX Range 0 Vref 26
7755 11:05:37.271805
7756 11:05:37.272151 ==
7757 11:05:37.274465 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 11:05:37.277734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 11:05:37.278199 ==
7760 11:05:37.278546
7761 11:05:37.278860
7762 11:05:37.281199 TX Vref Scan disable
7763 11:05:37.287830 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7764 11:05:37.288354 == TX Byte 0 ==
7765 11:05:37.291039 u2DelayCellOfst[0]=14 cells (4 PI)
7766 11:05:37.294387 u2DelayCellOfst[1]=14 cells (4 PI)
7767 11:05:37.297549 u2DelayCellOfst[2]=7 cells (2 PI)
7768 11:05:37.300579 u2DelayCellOfst[3]=11 cells (3 PI)
7769 11:05:37.304285 u2DelayCellOfst[4]=7 cells (2 PI)
7770 11:05:37.307807 u2DelayCellOfst[5]=0 cells (0 PI)
7771 11:05:37.310992 u2DelayCellOfst[6]=18 cells (5 PI)
7772 11:05:37.314223 u2DelayCellOfst[7]=18 cells (5 PI)
7773 11:05:37.317490 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7774 11:05:37.320522 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7775 11:05:37.324138 == TX Byte 1 ==
7776 11:05:37.327871 u2DelayCellOfst[8]=0 cells (0 PI)
7777 11:05:37.330822 u2DelayCellOfst[9]=3 cells (1 PI)
7778 11:05:37.331335 u2DelayCellOfst[10]=7 cells (2 PI)
7779 11:05:37.333925 u2DelayCellOfst[11]=3 cells (1 PI)
7780 11:05:37.337353 u2DelayCellOfst[12]=11 cells (3 PI)
7781 11:05:37.340173 u2DelayCellOfst[13]=11 cells (3 PI)
7782 11:05:37.344203 u2DelayCellOfst[14]=14 cells (4 PI)
7783 11:05:37.347015 u2DelayCellOfst[15]=11 cells (3 PI)
7784 11:05:37.354129 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7785 11:05:37.356618 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7786 11:05:37.357157 DramC Write-DBI on
7787 11:05:37.357497 ==
7788 11:05:37.360337 Dram Type= 6, Freq= 0, CH_0, rank 0
7789 11:05:37.366533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7790 11:05:37.367038 ==
7791 11:05:37.367377
7792 11:05:37.367734
7793 11:05:37.368048 TX Vref Scan disable
7794 11:05:37.371209 == TX Byte 0 ==
7795 11:05:37.374765 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7796 11:05:37.377445 == TX Byte 1 ==
7797 11:05:37.381008 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7798 11:05:37.384244 DramC Write-DBI off
7799 11:05:37.384668
7800 11:05:37.385004 [DATLAT]
7801 11:05:37.385317 Freq=1600, CH0 RK0
7802 11:05:37.385621
7803 11:05:37.387603 DATLAT Default: 0xf
7804 11:05:37.391076 0, 0xFFFF, sum = 0
7805 11:05:37.391615 1, 0xFFFF, sum = 0
7806 11:05:37.393717 2, 0xFFFF, sum = 0
7807 11:05:37.394154 3, 0xFFFF, sum = 0
7808 11:05:37.397470 4, 0xFFFF, sum = 0
7809 11:05:37.397892 5, 0xFFFF, sum = 0
7810 11:05:37.400544 6, 0xFFFF, sum = 0
7811 11:05:37.400967 7, 0xFFFF, sum = 0
7812 11:05:37.404228 8, 0xFFFF, sum = 0
7813 11:05:37.404653 9, 0xFFFF, sum = 0
7814 11:05:37.407748 10, 0xFFFF, sum = 0
7815 11:05:37.408269 11, 0xFFFF, sum = 0
7816 11:05:37.410709 12, 0xFFFF, sum = 0
7817 11:05:37.411233 13, 0xFFFF, sum = 0
7818 11:05:37.413926 14, 0x0, sum = 1
7819 11:05:37.414368 15, 0x0, sum = 2
7820 11:05:37.417156 16, 0x0, sum = 3
7821 11:05:37.417679 17, 0x0, sum = 4
7822 11:05:37.420097 best_step = 15
7823 11:05:37.420510
7824 11:05:37.420837 ==
7825 11:05:37.423534 Dram Type= 6, Freq= 0, CH_0, rank 0
7826 11:05:37.427468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7827 11:05:37.428055 ==
7828 11:05:37.430555 RX Vref Scan: 1
7829 11:05:37.431079
7830 11:05:37.431413 Set Vref Range= 24 -> 127
7831 11:05:37.431778
7832 11:05:37.433463 RX Vref 24 -> 127, step: 1
7833 11:05:37.433980
7834 11:05:37.436804 RX Delay 19 -> 252, step: 4
7835 11:05:37.437320
7836 11:05:37.440372 Set Vref, RX VrefLevel [Byte0]: 24
7837 11:05:37.443424 [Byte1]: 24
7838 11:05:37.443877
7839 11:05:37.446718 Set Vref, RX VrefLevel [Byte0]: 25
7840 11:05:37.450749 [Byte1]: 25
7841 11:05:37.453977
7842 11:05:37.454491 Set Vref, RX VrefLevel [Byte0]: 26
7843 11:05:37.457658 [Byte1]: 26
7844 11:05:37.461739
7845 11:05:37.462257 Set Vref, RX VrefLevel [Byte0]: 27
7846 11:05:37.464382 [Byte1]: 27
7847 11:05:37.468962
7848 11:05:37.469380 Set Vref, RX VrefLevel [Byte0]: 28
7849 11:05:37.472371 [Byte1]: 28
7850 11:05:37.476411
7851 11:05:37.476893 Set Vref, RX VrefLevel [Byte0]: 29
7852 11:05:37.479651 [Byte1]: 29
7853 11:05:37.484600
7854 11:05:37.485217 Set Vref, RX VrefLevel [Byte0]: 30
7855 11:05:37.487468 [Byte1]: 30
7856 11:05:37.491790
7857 11:05:37.492293 Set Vref, RX VrefLevel [Byte0]: 31
7858 11:05:37.494877 [Byte1]: 31
7859 11:05:37.499157
7860 11:05:37.499607 Set Vref, RX VrefLevel [Byte0]: 32
7861 11:05:37.502864 [Byte1]: 32
7862 11:05:37.506526
7863 11:05:37.506953 Set Vref, RX VrefLevel [Byte0]: 33
7864 11:05:37.513542 [Byte1]: 33
7865 11:05:37.513954
7866 11:05:37.516212 Set Vref, RX VrefLevel [Byte0]: 34
7867 11:05:37.519442 [Byte1]: 34
7868 11:05:37.519922
7869 11:05:37.523168 Set Vref, RX VrefLevel [Byte0]: 35
7870 11:05:37.526429 [Byte1]: 35
7871 11:05:37.527064
7872 11:05:37.529571 Set Vref, RX VrefLevel [Byte0]: 36
7873 11:05:37.532642 [Byte1]: 36
7874 11:05:37.536809
7875 11:05:37.537224 Set Vref, RX VrefLevel [Byte0]: 37
7876 11:05:37.540409 [Byte1]: 37
7877 11:05:37.544557
7878 11:05:37.545105 Set Vref, RX VrefLevel [Byte0]: 38
7879 11:05:37.547977 [Byte1]: 38
7880 11:05:37.552072
7881 11:05:37.552581 Set Vref, RX VrefLevel [Byte0]: 39
7882 11:05:37.555262 [Byte1]: 39
7883 11:05:37.559995
7884 11:05:37.560408 Set Vref, RX VrefLevel [Byte0]: 40
7885 11:05:37.563132 [Byte1]: 40
7886 11:05:37.567263
7887 11:05:37.567729 Set Vref, RX VrefLevel [Byte0]: 41
7888 11:05:37.571070 [Byte1]: 41
7889 11:05:37.575272
7890 11:05:37.575856 Set Vref, RX VrefLevel [Byte0]: 42
7891 11:05:37.578584 [Byte1]: 42
7892 11:05:37.582716
7893 11:05:37.583238 Set Vref, RX VrefLevel [Byte0]: 43
7894 11:05:37.586293 [Byte1]: 43
7895 11:05:37.590306
7896 11:05:37.590844 Set Vref, RX VrefLevel [Byte0]: 44
7897 11:05:37.593564 [Byte1]: 44
7898 11:05:37.597704
7899 11:05:37.598140 Set Vref, RX VrefLevel [Byte0]: 45
7900 11:05:37.601171 [Byte1]: 45
7901 11:05:37.605385
7902 11:05:37.605899 Set Vref, RX VrefLevel [Byte0]: 46
7903 11:05:37.608614 [Byte1]: 46
7904 11:05:37.612989
7905 11:05:37.613526 Set Vref, RX VrefLevel [Byte0]: 47
7906 11:05:37.616288 [Byte1]: 47
7907 11:05:37.620702
7908 11:05:37.621226 Set Vref, RX VrefLevel [Byte0]: 48
7909 11:05:37.624045 [Byte1]: 48
7910 11:05:37.627710
7911 11:05:37.628139 Set Vref, RX VrefLevel [Byte0]: 49
7912 11:05:37.631388 [Byte1]: 49
7913 11:05:37.635896
7914 11:05:37.636407 Set Vref, RX VrefLevel [Byte0]: 50
7915 11:05:37.638935 [Byte1]: 50
7916 11:05:37.643233
7917 11:05:37.643788 Set Vref, RX VrefLevel [Byte0]: 51
7918 11:05:37.646822 [Byte1]: 51
7919 11:05:37.650257
7920 11:05:37.650676 Set Vref, RX VrefLevel [Byte0]: 52
7921 11:05:37.653875 [Byte1]: 52
7922 11:05:37.658124
7923 11:05:37.658643 Set Vref, RX VrefLevel [Byte0]: 53
7924 11:05:37.661792 [Byte1]: 53
7925 11:05:37.665949
7926 11:05:37.666467 Set Vref, RX VrefLevel [Byte0]: 54
7927 11:05:37.669172 [Byte1]: 54
7928 11:05:37.673571
7929 11:05:37.674093 Set Vref, RX VrefLevel [Byte0]: 55
7930 11:05:37.676512 [Byte1]: 55
7931 11:05:37.680648
7932 11:05:37.681169 Set Vref, RX VrefLevel [Byte0]: 56
7933 11:05:37.683958 [Byte1]: 56
7934 11:05:37.688618
7935 11:05:37.689137 Set Vref, RX VrefLevel [Byte0]: 57
7936 11:05:37.691839 [Byte1]: 57
7937 11:05:37.696574
7938 11:05:37.697194 Set Vref, RX VrefLevel [Byte0]: 58
7939 11:05:37.699418 [Byte1]: 58
7940 11:05:37.703802
7941 11:05:37.704322 Set Vref, RX VrefLevel [Byte0]: 59
7942 11:05:37.707233 [Byte1]: 59
7943 11:05:37.711264
7944 11:05:37.711728 Set Vref, RX VrefLevel [Byte0]: 60
7945 11:05:37.714246 [Byte1]: 60
7946 11:05:37.719131
7947 11:05:37.719782 Set Vref, RX VrefLevel [Byte0]: 61
7948 11:05:37.721981 [Byte1]: 61
7949 11:05:37.726417
7950 11:05:37.726929 Set Vref, RX VrefLevel [Byte0]: 62
7951 11:05:37.729485 [Byte1]: 62
7952 11:05:37.734084
7953 11:05:37.734611 Set Vref, RX VrefLevel [Byte0]: 63
7954 11:05:37.737424 [Byte1]: 63
7955 11:05:37.741383
7956 11:05:37.741865 Set Vref, RX VrefLevel [Byte0]: 64
7957 11:05:37.744546 [Byte1]: 64
7958 11:05:37.748839
7959 11:05:37.749259 Set Vref, RX VrefLevel [Byte0]: 65
7960 11:05:37.752250 [Byte1]: 65
7961 11:05:37.756495
7962 11:05:37.756924 Set Vref, RX VrefLevel [Byte0]: 66
7963 11:05:37.760125 [Byte1]: 66
7964 11:05:37.764033
7965 11:05:37.764451 Set Vref, RX VrefLevel [Byte0]: 67
7966 11:05:37.768025 [Byte1]: 67
7967 11:05:37.771626
7968 11:05:37.772231 Set Vref, RX VrefLevel [Byte0]: 68
7969 11:05:37.775266 [Byte1]: 68
7970 11:05:37.779298
7971 11:05:37.779947 Set Vref, RX VrefLevel [Byte0]: 69
7972 11:05:37.783041 [Byte1]: 69
7973 11:05:37.786907
7974 11:05:37.787743 Set Vref, RX VrefLevel [Byte0]: 70
7975 11:05:37.790551 [Byte1]: 70
7976 11:05:37.794493
7977 11:05:37.794952 Set Vref, RX VrefLevel [Byte0]: 71
7978 11:05:37.797465 [Byte1]: 71
7979 11:05:37.802044
7980 11:05:37.802469 Set Vref, RX VrefLevel [Byte0]: 72
7981 11:05:37.805158 [Byte1]: 72
7982 11:05:37.809628
7983 11:05:37.810055 Set Vref, RX VrefLevel [Byte0]: 73
7984 11:05:37.812726 [Byte1]: 73
7985 11:05:37.816876
7986 11:05:37.817302 Set Vref, RX VrefLevel [Byte0]: 74
7987 11:05:37.820116 [Byte1]: 74
7988 11:05:37.824458
7989 11:05:37.824752 Set Vref, RX VrefLevel [Byte0]: 75
7990 11:05:37.827739 [Byte1]: 75
7991 11:05:37.832322
7992 11:05:37.832644 Set Vref, RX VrefLevel [Byte0]: 76
7993 11:05:37.835375 [Byte1]: 76
7994 11:05:37.839302
7995 11:05:37.839595 Set Vref, RX VrefLevel [Byte0]: 77
7996 11:05:37.842992 [Byte1]: 77
7997 11:05:37.847236
7998 11:05:37.847416 Set Vref, RX VrefLevel [Byte0]: 78
7999 11:05:37.850568 [Byte1]: 78
8000 11:05:37.854997
8001 11:05:37.855260 Set Vref, RX VrefLevel [Byte0]: 79
8002 11:05:37.858217 [Byte1]: 79
8003 11:05:37.862724
8004 11:05:37.863024 Final RX Vref Byte 0 = 65 to rank0
8005 11:05:37.865926 Final RX Vref Byte 1 = 57 to rank0
8006 11:05:37.868756 Final RX Vref Byte 0 = 65 to rank1
8007 11:05:37.872285 Final RX Vref Byte 1 = 57 to rank1==
8008 11:05:37.876087 Dram Type= 6, Freq= 0, CH_0, rank 0
8009 11:05:37.882488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8010 11:05:37.882996 ==
8011 11:05:37.883488 DQS Delay:
8012 11:05:37.885572 DQS0 = 0, DQS1 = 0
8013 11:05:37.886089 DQM Delay:
8014 11:05:37.886569 DQM0 = 133, DQM1 = 123
8015 11:05:37.889158 DQ Delay:
8016 11:05:37.891943 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
8017 11:05:37.895514 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8018 11:05:37.898416 DQ8 =114, DQ9 =112, DQ10 =122, DQ11 =118
8019 11:05:37.901730 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =130
8020 11:05:37.902312
8021 11:05:37.902811
8022 11:05:37.903176
8023 11:05:37.905387 [DramC_TX_OE_Calibration] TA2
8024 11:05:37.908556 Original DQ_B0 (3 6) =30, OEN = 27
8025 11:05:37.912133 Original DQ_B1 (3 6) =30, OEN = 27
8026 11:05:37.915622 24, 0x0, End_B0=24 End_B1=24
8027 11:05:37.918447 25, 0x0, End_B0=25 End_B1=25
8028 11:05:37.918898 26, 0x0, End_B0=26 End_B1=26
8029 11:05:37.921792 27, 0x0, End_B0=27 End_B1=27
8030 11:05:37.925338 28, 0x0, End_B0=28 End_B1=28
8031 11:05:37.928177 29, 0x0, End_B0=29 End_B1=29
8032 11:05:37.928634 30, 0x0, End_B0=30 End_B1=30
8033 11:05:37.931460 31, 0x4141, End_B0=30 End_B1=30
8034 11:05:37.935192 Byte0 end_step=30 best_step=27
8035 11:05:37.937930 Byte1 end_step=30 best_step=27
8036 11:05:37.941370 Byte0 TX OE(2T, 0.5T) = (3, 3)
8037 11:05:37.944225 Byte1 TX OE(2T, 0.5T) = (3, 3)
8038 11:05:37.944655
8039 11:05:37.944992
8040 11:05:37.951531 [DQSOSCAuto] RK0, (LSB)MR18= 0x2213, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
8041 11:05:37.955243 CH0 RK0: MR19=303, MR18=2213
8042 11:05:37.961096 CH0_RK0: MR19=0x303, MR18=0x2213, DQSOSC=392, MR23=63, INC=24, DEC=16
8043 11:05:37.961605
8044 11:05:37.964175 ----->DramcWriteLeveling(PI) begin...
8045 11:05:37.964835 ==
8046 11:05:37.967612 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 11:05:37.970599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 11:05:37.973611 ==
8049 11:05:37.974004 Write leveling (Byte 0): 36 => 36
8050 11:05:37.977170 Write leveling (Byte 1): 28 => 28
8051 11:05:37.980762 DramcWriteLeveling(PI) end<-----
8052 11:05:37.981185
8053 11:05:37.981524 ==
8054 11:05:37.984144 Dram Type= 6, Freq= 0, CH_0, rank 1
8055 11:05:37.990731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8056 11:05:37.991159 ==
8057 11:05:37.993716 [Gating] SW mode calibration
8058 11:05:38.000875 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8059 11:05:38.003772 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8060 11:05:38.010509 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 11:05:38.013287 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 11:05:38.016998 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 11:05:38.023328 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 11:05:38.026765 1 4 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8065 11:05:38.030335 1 4 20 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8066 11:05:38.036442 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 11:05:38.039823 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 11:05:38.043148 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 11:05:38.049535 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 11:05:38.053208 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 11:05:38.056161 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8072 11:05:38.063093 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
8073 11:05:38.066266 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
8074 11:05:38.069501 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 11:05:38.076204 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 11:05:38.079445 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 11:05:38.082457 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 11:05:38.089107 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 11:05:38.092471 1 6 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8080 11:05:38.095497 1 6 16 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8081 11:05:38.102123 1 6 20 | B1->B0 | 4342 4646 | 1 0 | (0 0) (0 0)
8082 11:05:38.105548 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 11:05:38.109101 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 11:05:38.115784 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 11:05:38.118653 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 11:05:38.122170 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8087 11:05:38.128801 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8088 11:05:38.131766 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8089 11:05:38.135400 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8090 11:05:38.141495 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8091 11:05:38.145041 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 11:05:38.147988 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 11:05:38.154786 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 11:05:38.158444 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 11:05:38.161165 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 11:05:38.167897 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 11:05:38.171434 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 11:05:38.174679 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 11:05:38.180959 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 11:05:38.184442 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 11:05:38.187819 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 11:05:38.194380 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8103 11:05:38.197869 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8104 11:05:38.201312 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8105 11:05:38.204544 Total UI for P1: 0, mck2ui 16
8106 11:05:38.207221 best dqsien dly found for B0: ( 1, 9, 10)
8107 11:05:38.214229 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8108 11:05:38.217631 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8109 11:05:38.220485 Total UI for P1: 0, mck2ui 16
8110 11:05:38.224168 best dqsien dly found for B1: ( 1, 9, 16)
8111 11:05:38.227592 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8112 11:05:38.230593 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8113 11:05:38.231017
8114 11:05:38.233935 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8115 11:05:38.240572 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8116 11:05:38.241176 [Gating] SW calibration Done
8117 11:05:38.241657 ==
8118 11:05:38.243711 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 11:05:38.250712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 11:05:38.251347 ==
8121 11:05:38.251956 RX Vref Scan: 0
8122 11:05:38.252358
8123 11:05:38.253721 RX Vref 0 -> 0, step: 1
8124 11:05:38.254244
8125 11:05:38.257219 RX Delay 0 -> 252, step: 8
8126 11:05:38.260349 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8127 11:05:38.263652 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8128 11:05:38.267243 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8129 11:05:38.273749 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8130 11:05:38.277220 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8131 11:05:38.280331 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8132 11:05:38.283173 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8133 11:05:38.287295 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8134 11:05:38.293161 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8135 11:05:38.296655 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8136 11:05:38.299564 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8137 11:05:38.302965 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8138 11:05:38.306287 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8139 11:05:38.313061 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8140 11:05:38.316688 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8141 11:05:38.319644 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8142 11:05:38.320111 ==
8143 11:05:38.322841 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 11:05:38.326620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 11:05:38.327048 ==
8146 11:05:38.329469 DQS Delay:
8147 11:05:38.329895 DQS0 = 0, DQS1 = 0
8148 11:05:38.332773 DQM Delay:
8149 11:05:38.333197 DQM0 = 133, DQM1 = 129
8150 11:05:38.336368 DQ Delay:
8151 11:05:38.339615 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8152 11:05:38.342702 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8153 11:05:38.346204 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8154 11:05:38.349245 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
8155 11:05:38.349669
8156 11:05:38.350004
8157 11:05:38.350316 ==
8158 11:05:38.352887 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 11:05:38.355907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 11:05:38.356336 ==
8161 11:05:38.356679
8162 11:05:38.359476
8163 11:05:38.359948 TX Vref Scan disable
8164 11:05:38.362959 == TX Byte 0 ==
8165 11:05:38.365904 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8166 11:05:38.369445 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8167 11:05:38.372798 == TX Byte 1 ==
8168 11:05:38.376080 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8169 11:05:38.379299 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8170 11:05:38.379751 ==
8171 11:05:38.382356 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 11:05:38.389146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 11:05:38.389577 ==
8174 11:05:38.401816
8175 11:05:38.404793 TX Vref early break, caculate TX vref
8176 11:05:38.408116 TX Vref=16, minBit 1, minWin=22, winSum=379
8177 11:05:38.411563 TX Vref=18, minBit 1, minWin=23, winSum=389
8178 11:05:38.414803 TX Vref=20, minBit 0, minWin=24, winSum=400
8179 11:05:38.417921 TX Vref=22, minBit 3, minWin=24, winSum=405
8180 11:05:38.421452 TX Vref=24, minBit 1, minWin=24, winSum=409
8181 11:05:38.428062 TX Vref=26, minBit 0, minWin=25, winSum=418
8182 11:05:38.431486 TX Vref=28, minBit 2, minWin=24, winSum=409
8183 11:05:38.434484 TX Vref=30, minBit 0, minWin=24, winSum=400
8184 11:05:38.437834 TX Vref=32, minBit 0, minWin=24, winSum=398
8185 11:05:38.440958 TX Vref=34, minBit 2, minWin=23, winSum=390
8186 11:05:38.447807 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 26
8187 11:05:38.448234
8188 11:05:38.450705 Final TX Range 0 Vref 26
8189 11:05:38.451132
8190 11:05:38.451571 ==
8191 11:05:38.454284 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 11:05:38.457398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 11:05:38.457827 ==
8194 11:05:38.458167
8195 11:05:38.460951
8196 11:05:38.461376 TX Vref Scan disable
8197 11:05:38.467455 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8198 11:05:38.467931 == TX Byte 0 ==
8199 11:05:38.470456 u2DelayCellOfst[0]=14 cells (4 PI)
8200 11:05:38.473983 u2DelayCellOfst[1]=22 cells (6 PI)
8201 11:05:38.476961 u2DelayCellOfst[2]=14 cells (4 PI)
8202 11:05:38.480215 u2DelayCellOfst[3]=18 cells (5 PI)
8203 11:05:38.483717 u2DelayCellOfst[4]=11 cells (3 PI)
8204 11:05:38.487180 u2DelayCellOfst[5]=0 cells (0 PI)
8205 11:05:38.490736 u2DelayCellOfst[6]=22 cells (6 PI)
8206 11:05:38.493730 u2DelayCellOfst[7]=22 cells (6 PI)
8207 11:05:38.496878 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8208 11:05:38.500406 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8209 11:05:38.503988 == TX Byte 1 ==
8210 11:05:38.506842 u2DelayCellOfst[8]=0 cells (0 PI)
8211 11:05:38.510439 u2DelayCellOfst[9]=3 cells (1 PI)
8212 11:05:38.513379 u2DelayCellOfst[10]=7 cells (2 PI)
8213 11:05:38.517059 u2DelayCellOfst[11]=3 cells (1 PI)
8214 11:05:38.519863 u2DelayCellOfst[12]=11 cells (3 PI)
8215 11:05:38.523568 u2DelayCellOfst[13]=14 cells (4 PI)
8216 11:05:38.524026 u2DelayCellOfst[14]=18 cells (5 PI)
8217 11:05:38.526747 u2DelayCellOfst[15]=11 cells (3 PI)
8218 11:05:38.533424 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8219 11:05:38.536705 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8220 11:05:38.540132 DramC Write-DBI on
8221 11:05:38.540557 ==
8222 11:05:38.543134 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 11:05:38.546229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 11:05:38.546654 ==
8225 11:05:38.546993
8226 11:05:38.547302
8227 11:05:38.549808 TX Vref Scan disable
8228 11:05:38.550230 == TX Byte 0 ==
8229 11:05:38.556372 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8230 11:05:38.556800 == TX Byte 1 ==
8231 11:05:38.559632 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8232 11:05:38.562691 DramC Write-DBI off
8233 11:05:38.563111
8234 11:05:38.563444 [DATLAT]
8235 11:05:38.566240 Freq=1600, CH0 RK1
8236 11:05:38.566681
8237 11:05:38.567072 DATLAT Default: 0xf
8238 11:05:38.569274 0, 0xFFFF, sum = 0
8239 11:05:38.572799 1, 0xFFFF, sum = 0
8240 11:05:38.573227 2, 0xFFFF, sum = 0
8241 11:05:38.576284 3, 0xFFFF, sum = 0
8242 11:05:38.576709 4, 0xFFFF, sum = 0
8243 11:05:38.579344 5, 0xFFFF, sum = 0
8244 11:05:38.579822 6, 0xFFFF, sum = 0
8245 11:05:38.583264 7, 0xFFFF, sum = 0
8246 11:05:38.583735 8, 0xFFFF, sum = 0
8247 11:05:38.585662 9, 0xFFFF, sum = 0
8248 11:05:38.586091 10, 0xFFFF, sum = 0
8249 11:05:38.589376 11, 0xFFFF, sum = 0
8250 11:05:38.589806 12, 0xFFFF, sum = 0
8251 11:05:38.592794 13, 0xFFFF, sum = 0
8252 11:05:38.593224 14, 0x0, sum = 1
8253 11:05:38.595589 15, 0x0, sum = 2
8254 11:05:38.596079 16, 0x0, sum = 3
8255 11:05:38.599362 17, 0x0, sum = 4
8256 11:05:38.600000 best_step = 15
8257 11:05:38.600352
8258 11:05:38.600672 ==
8259 11:05:38.602150 Dram Type= 6, Freq= 0, CH_0, rank 1
8260 11:05:38.608863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 11:05:38.609295 ==
8262 11:05:38.609643 RX Vref Scan: 0
8263 11:05:38.610166
8264 11:05:38.612427 RX Vref 0 -> 0, step: 1
8265 11:05:38.612850
8266 11:05:38.615624 RX Delay 11 -> 252, step: 4
8267 11:05:38.618701 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8268 11:05:38.622214 iDelay=195, Bit 1, Center 136 (83 ~ 190) 108
8269 11:05:38.628854 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8270 11:05:38.631702 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8271 11:05:38.635124 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8272 11:05:38.638605 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8273 11:05:38.642061 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8274 11:05:38.648457 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8275 11:05:38.652190 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8276 11:05:38.655111 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8277 11:05:38.658620 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8278 11:05:38.661601 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8279 11:05:38.668211 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8280 11:05:38.671731 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8281 11:05:38.675034 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8282 11:05:38.678063 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8283 11:05:38.678488 ==
8284 11:05:38.681419 Dram Type= 6, Freq= 0, CH_0, rank 1
8285 11:05:38.687996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 11:05:38.688417 ==
8287 11:05:38.688752 DQS Delay:
8288 11:05:38.691411 DQS0 = 0, DQS1 = 0
8289 11:05:38.691868 DQM Delay:
8290 11:05:38.695063 DQM0 = 130, DQM1 = 125
8291 11:05:38.695481 DQ Delay:
8292 11:05:38.698167 DQ0 =128, DQ1 =136, DQ2 =126, DQ3 =128
8293 11:05:38.700946 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8294 11:05:38.704469 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8295 11:05:38.707951 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8296 11:05:38.708374
8297 11:05:38.708871
8298 11:05:38.709290
8299 11:05:38.711321 [DramC_TX_OE_Calibration] TA2
8300 11:05:38.714271 Original DQ_B0 (3 6) =30, OEN = 27
8301 11:05:38.718106 Original DQ_B1 (3 6) =30, OEN = 27
8302 11:05:38.721003 24, 0x0, End_B0=24 End_B1=24
8303 11:05:38.724155 25, 0x0, End_B0=25 End_B1=25
8304 11:05:38.724602 26, 0x0, End_B0=26 End_B1=26
8305 11:05:38.727542 27, 0x0, End_B0=27 End_B1=27
8306 11:05:38.731000 28, 0x0, End_B0=28 End_B1=28
8307 11:05:38.734229 29, 0x0, End_B0=29 End_B1=29
8308 11:05:38.734801 30, 0x0, End_B0=30 End_B1=30
8309 11:05:38.737264 31, 0x4545, End_B0=30 End_B1=30
8310 11:05:38.741038 Byte0 end_step=30 best_step=27
8311 11:05:38.744184 Byte1 end_step=30 best_step=27
8312 11:05:38.747705 Byte0 TX OE(2T, 0.5T) = (3, 3)
8313 11:05:38.750366 Byte1 TX OE(2T, 0.5T) = (3, 3)
8314 11:05:38.750784
8315 11:05:38.751107
8316 11:05:38.757005 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f03, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 394 ps
8317 11:05:38.760511 CH0 RK1: MR19=303, MR18=1F03
8318 11:05:38.766838 CH0_RK1: MR19=0x303, MR18=0x1F03, DQSOSC=394, MR23=63, INC=23, DEC=15
8319 11:05:38.770414 [RxdqsGatingPostProcess] freq 1600
8320 11:05:38.776917 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8321 11:05:38.777341 best DQS0 dly(2T, 0.5T) = (1, 1)
8322 11:05:38.780472 best DQS1 dly(2T, 0.5T) = (1, 1)
8323 11:05:38.783269 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8324 11:05:38.787065 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8325 11:05:38.790209 best DQS0 dly(2T, 0.5T) = (1, 1)
8326 11:05:38.793615 best DQS1 dly(2T, 0.5T) = (1, 1)
8327 11:05:38.796925 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8328 11:05:38.800536 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8329 11:05:38.803493 Pre-setting of DQS Precalculation
8330 11:05:38.806927 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8331 11:05:38.809971 ==
8332 11:05:38.810392 Dram Type= 6, Freq= 0, CH_1, rank 0
8333 11:05:38.816164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 11:05:38.816587 ==
8335 11:05:38.819572 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8336 11:05:38.826258 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8337 11:05:38.829415 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8338 11:05:38.836183 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8339 11:05:38.844201 [CA 0] Center 41 (12~71) winsize 60
8340 11:05:38.848093 [CA 1] Center 42 (13~72) winsize 60
8341 11:05:38.850808 [CA 2] Center 37 (8~66) winsize 59
8342 11:05:38.854489 [CA 3] Center 36 (7~65) winsize 59
8343 11:05:38.857416 [CA 4] Center 36 (7~66) winsize 60
8344 11:05:38.861011 [CA 5] Center 36 (7~66) winsize 60
8345 11:05:38.861570
8346 11:05:38.863882 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8347 11:05:38.864432
8348 11:05:38.871165 [CATrainingPosCal] consider 1 rank data
8349 11:05:38.871710 u2DelayCellTimex100 = 262/100 ps
8350 11:05:38.877562 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8351 11:05:38.880516 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8352 11:05:38.883596 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8353 11:05:38.887043 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8354 11:05:38.890121 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8355 11:05:38.893361 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8356 11:05:38.893890
8357 11:05:38.896764 CA PerBit enable=1, Macro0, CA PI delay=36
8358 11:05:38.897267
8359 11:05:38.900360 [CBTSetCACLKResult] CA Dly = 36
8360 11:05:38.903526 CS Dly: 10 (0~41)
8361 11:05:38.906841 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8362 11:05:38.910550 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8363 11:05:38.910994 ==
8364 11:05:38.913202 Dram Type= 6, Freq= 0, CH_1, rank 1
8365 11:05:38.919836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 11:05:38.920254 ==
8367 11:05:38.923484 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8368 11:05:38.930227 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8369 11:05:38.932996 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8370 11:05:38.939817 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8371 11:05:38.947975 [CA 0] Center 42 (12~72) winsize 61
8372 11:05:38.951217 [CA 1] Center 42 (13~72) winsize 60
8373 11:05:38.953961 [CA 2] Center 37 (8~67) winsize 60
8374 11:05:38.957254 [CA 3] Center 37 (8~67) winsize 60
8375 11:05:38.960864 [CA 4] Center 37 (8~67) winsize 60
8376 11:05:38.964479 [CA 5] Center 37 (8~66) winsize 59
8377 11:05:38.964887
8378 11:05:38.967606 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8379 11:05:38.968036
8380 11:05:38.973784 [CATrainingPosCal] consider 2 rank data
8381 11:05:38.974299 u2DelayCellTimex100 = 262/100 ps
8382 11:05:38.980241 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8383 11:05:38.983755 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8384 11:05:38.986976 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8385 11:05:38.990404 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8386 11:05:38.993543 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8387 11:05:38.996944 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8388 11:05:38.997359
8389 11:05:39.000130 CA PerBit enable=1, Macro0, CA PI delay=36
8390 11:05:39.000560
8391 11:05:39.003724 [CBTSetCACLKResult] CA Dly = 36
8392 11:05:39.006640 CS Dly: 11 (0~44)
8393 11:05:39.010137 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8394 11:05:39.013404 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8395 11:05:39.013815
8396 11:05:39.016368 ----->DramcWriteLeveling(PI) begin...
8397 11:05:39.020407 ==
8398 11:05:39.020824 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 11:05:39.026724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 11:05:39.027144 ==
8401 11:05:39.029616 Write leveling (Byte 0): 24 => 24
8402 11:05:39.033463 Write leveling (Byte 1): 27 => 27
8403 11:05:39.036479 DramcWriteLeveling(PI) end<-----
8404 11:05:39.036895
8405 11:05:39.037220 ==
8406 11:05:39.039466 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 11:05:39.042868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 11:05:39.043349 ==
8409 11:05:39.046363 [Gating] SW mode calibration
8410 11:05:39.052635 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8411 11:05:39.059484 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8412 11:05:39.062552 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 11:05:39.065829 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 11:05:39.072844 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 11:05:39.075656 1 4 12 | B1->B0 | 3131 3232 | 0 1 | (0 0) (1 1)
8416 11:05:39.079283 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 11:05:39.085578 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 11:05:39.089035 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 11:05:39.091976 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 11:05:39.098720 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 11:05:39.102297 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 11:05:39.105249 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8423 11:05:39.111925 1 5 12 | B1->B0 | 2f2f 2525 | 0 0 | (0 1) (1 0)
8424 11:05:39.115330 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8425 11:05:39.118690 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 11:05:39.125048 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 11:05:39.128781 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 11:05:39.131742 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 11:05:39.138090 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 11:05:39.141674 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 11:05:39.145018 1 6 12 | B1->B0 | 3a3a 4343 | 0 0 | (0 0) (0 0)
8432 11:05:39.151219 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 11:05:39.154710 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 11:05:39.158018 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 11:05:39.165007 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 11:05:39.168018 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 11:05:39.171511 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 11:05:39.177607 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8439 11:05:39.181498 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8440 11:05:39.184161 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8441 11:05:39.190673 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 11:05:39.194111 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 11:05:39.197490 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 11:05:39.204167 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 11:05:39.207283 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 11:05:39.210704 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 11:05:39.217290 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 11:05:39.220146 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 11:05:39.223780 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 11:05:39.230209 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 11:05:39.233285 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 11:05:39.236807 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 11:05:39.243141 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 11:05:39.246293 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8455 11:05:39.249865 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8456 11:05:39.256412 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8457 11:05:39.259487 Total UI for P1: 0, mck2ui 16
8458 11:05:39.263048 best dqsien dly found for B0: ( 1, 9, 10)
8459 11:05:39.265996 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 11:05:39.269271 Total UI for P1: 0, mck2ui 16
8461 11:05:39.273156 best dqsien dly found for B1: ( 1, 9, 12)
8462 11:05:39.276162 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8463 11:05:39.279444 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8464 11:05:39.279894
8465 11:05:39.283015 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8466 11:05:39.289683 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8467 11:05:39.290133 [Gating] SW calibration Done
8468 11:05:39.292913 ==
8469 11:05:39.293336 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 11:05:39.299138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 11:05:39.299563 ==
8472 11:05:39.299996 RX Vref Scan: 0
8473 11:05:39.300324
8474 11:05:39.302388 RX Vref 0 -> 0, step: 1
8475 11:05:39.302803
8476 11:05:39.305944 RX Delay 0 -> 252, step: 8
8477 11:05:39.309333 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8478 11:05:39.312348 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8479 11:05:39.315618 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8480 11:05:39.322359 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8481 11:05:39.325314 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8482 11:05:39.328606 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8483 11:05:39.332272 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8484 11:05:39.335137 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8485 11:05:39.341770 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8486 11:05:39.345234 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8487 11:05:39.348377 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8488 11:05:39.351907 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8489 11:05:39.358290 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8490 11:05:39.361752 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8491 11:05:39.364717 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8492 11:05:39.368292 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8493 11:05:39.368721 ==
8494 11:05:39.371381 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 11:05:39.377951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 11:05:39.378511 ==
8497 11:05:39.378989 DQS Delay:
8498 11:05:39.381490 DQS0 = 0, DQS1 = 0
8499 11:05:39.382090 DQM Delay:
8500 11:05:39.382599 DQM0 = 138, DQM1 = 130
8501 11:05:39.384772 DQ Delay:
8502 11:05:39.388197 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8503 11:05:39.390994 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8504 11:05:39.394747 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8505 11:05:39.398036 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8506 11:05:39.398651
8507 11:05:39.399130
8508 11:05:39.399806 ==
8509 11:05:39.401304 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 11:05:39.407807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 11:05:39.408279 ==
8512 11:05:39.408642
8513 11:05:39.408972
8514 11:05:39.409320 TX Vref Scan disable
8515 11:05:39.410881 == TX Byte 0 ==
8516 11:05:39.414127 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8517 11:05:39.421055 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8518 11:05:39.421660 == TX Byte 1 ==
8519 11:05:39.424179 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8520 11:05:39.430828 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8521 11:05:39.431256 ==
8522 11:05:39.433739 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 11:05:39.437140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 11:05:39.437539 ==
8525 11:05:39.449689
8526 11:05:39.453238 TX Vref early break, caculate TX vref
8527 11:05:39.456174 TX Vref=16, minBit 5, minWin=21, winSum=375
8528 11:05:39.459811 TX Vref=18, minBit 5, minWin=22, winSum=384
8529 11:05:39.463026 TX Vref=20, minBit 0, minWin=23, winSum=394
8530 11:05:39.466329 TX Vref=22, minBit 0, minWin=23, winSum=402
8531 11:05:39.469694 TX Vref=24, minBit 0, minWin=25, winSum=417
8532 11:05:39.476210 TX Vref=26, minBit 0, minWin=25, winSum=420
8533 11:05:39.479227 TX Vref=28, minBit 0, minWin=26, winSum=424
8534 11:05:39.482667 TX Vref=30, minBit 0, minWin=24, winSum=413
8535 11:05:39.486231 TX Vref=32, minBit 0, minWin=24, winSum=403
8536 11:05:39.489154 TX Vref=34, minBit 1, minWin=23, winSum=394
8537 11:05:39.495786 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
8538 11:05:39.496264
8539 11:05:39.499579 Final TX Range 0 Vref 28
8540 11:05:39.500058
8541 11:05:39.500599 ==
8542 11:05:39.502379 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 11:05:39.505663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 11:05:39.506148 ==
8545 11:05:39.506523
8546 11:05:39.506841
8547 11:05:39.509234 TX Vref Scan disable
8548 11:05:39.515858 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8549 11:05:39.516260 == TX Byte 0 ==
8550 11:05:39.519231 u2DelayCellOfst[0]=18 cells (5 PI)
8551 11:05:39.522259 u2DelayCellOfst[1]=14 cells (4 PI)
8552 11:05:39.525592 u2DelayCellOfst[2]=0 cells (0 PI)
8553 11:05:39.528854 u2DelayCellOfst[3]=7 cells (2 PI)
8554 11:05:39.532183 u2DelayCellOfst[4]=7 cells (2 PI)
8555 11:05:39.535572 u2DelayCellOfst[5]=18 cells (5 PI)
8556 11:05:39.538704 u2DelayCellOfst[6]=18 cells (5 PI)
8557 11:05:39.542106 u2DelayCellOfst[7]=7 cells (2 PI)
8558 11:05:39.545583 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8559 11:05:39.548709 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8560 11:05:39.552304 == TX Byte 1 ==
8561 11:05:39.555140 u2DelayCellOfst[8]=0 cells (0 PI)
8562 11:05:39.558932 u2DelayCellOfst[9]=3 cells (1 PI)
8563 11:05:39.559374 u2DelayCellOfst[10]=11 cells (3 PI)
8564 11:05:39.562425 u2DelayCellOfst[11]=3 cells (1 PI)
8565 11:05:39.565343 u2DelayCellOfst[12]=14 cells (4 PI)
8566 11:05:39.568405 u2DelayCellOfst[13]=18 cells (5 PI)
8567 11:05:39.572561 u2DelayCellOfst[14]=18 cells (5 PI)
8568 11:05:39.574766 u2DelayCellOfst[15]=18 cells (5 PI)
8569 11:05:39.582201 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8570 11:05:39.584786 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8571 11:05:39.585257 DramC Write-DBI on
8572 11:05:39.585604 ==
8573 11:05:39.588235 Dram Type= 6, Freq= 0, CH_1, rank 0
8574 11:05:39.594894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8575 11:05:39.595364 ==
8576 11:05:39.595892
8577 11:05:39.596370
8578 11:05:39.598308 TX Vref Scan disable
8579 11:05:39.598831 == TX Byte 0 ==
8580 11:05:39.605161 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8581 11:05:39.605724 == TX Byte 1 ==
8582 11:05:39.607854 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8583 11:05:39.611387 DramC Write-DBI off
8584 11:05:39.611947
8585 11:05:39.612343 [DATLAT]
8586 11:05:39.614688 Freq=1600, CH1 RK0
8587 11:05:39.615181
8588 11:05:39.615709 DATLAT Default: 0xf
8589 11:05:39.618056 0, 0xFFFF, sum = 0
8590 11:05:39.618565 1, 0xFFFF, sum = 0
8591 11:05:39.620892 2, 0xFFFF, sum = 0
8592 11:05:39.621468 3, 0xFFFF, sum = 0
8593 11:05:39.624107 4, 0xFFFF, sum = 0
8594 11:05:39.624617 5, 0xFFFF, sum = 0
8595 11:05:39.627896 6, 0xFFFF, sum = 0
8596 11:05:39.628377 7, 0xFFFF, sum = 0
8597 11:05:39.630733 8, 0xFFFF, sum = 0
8598 11:05:39.634273 9, 0xFFFF, sum = 0
8599 11:05:39.634847 10, 0xFFFF, sum = 0
8600 11:05:39.637839 11, 0xFFFF, sum = 0
8601 11:05:39.638444 12, 0xFFFF, sum = 0
8602 11:05:39.641082 13, 0xFFFF, sum = 0
8603 11:05:39.641506 14, 0x0, sum = 1
8604 11:05:39.644725 15, 0x0, sum = 2
8605 11:05:39.645151 16, 0x0, sum = 3
8606 11:05:39.647282 17, 0x0, sum = 4
8607 11:05:39.647747 best_step = 15
8608 11:05:39.648092
8609 11:05:39.648421 ==
8610 11:05:39.650599 Dram Type= 6, Freq= 0, CH_1, rank 0
8611 11:05:39.653836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8612 11:05:39.657404 ==
8613 11:05:39.657822 RX Vref Scan: 1
8614 11:05:39.658154
8615 11:05:39.660463 Set Vref Range= 24 -> 127
8616 11:05:39.660883
8617 11:05:39.663444 RX Vref 24 -> 127, step: 1
8618 11:05:39.663916
8619 11:05:39.664252 RX Delay 19 -> 252, step: 4
8620 11:05:39.664563
8621 11:05:39.667038 Set Vref, RX VrefLevel [Byte0]: 24
8622 11:05:39.669762 [Byte1]: 24
8623 11:05:39.673973
8624 11:05:39.674053 Set Vref, RX VrefLevel [Byte0]: 25
8625 11:05:39.677400 [Byte1]: 25
8626 11:05:39.681395
8627 11:05:39.681495 Set Vref, RX VrefLevel [Byte0]: 26
8628 11:05:39.687894 [Byte1]: 26
8629 11:05:39.687977
8630 11:05:39.690946 Set Vref, RX VrefLevel [Byte0]: 27
8631 11:05:39.694752 [Byte1]: 27
8632 11:05:39.694836
8633 11:05:39.697690 Set Vref, RX VrefLevel [Byte0]: 28
8634 11:05:39.700766 [Byte1]: 28
8635 11:05:39.700864
8636 11:05:39.704320 Set Vref, RX VrefLevel [Byte0]: 29
8637 11:05:39.707884 [Byte1]: 29
8638 11:05:39.711749
8639 11:05:39.711844 Set Vref, RX VrefLevel [Byte0]: 30
8640 11:05:39.714735 [Byte1]: 30
8641 11:05:39.718990
8642 11:05:39.719071 Set Vref, RX VrefLevel [Byte0]: 31
8643 11:05:39.722913 [Byte1]: 31
8644 11:05:39.726506
8645 11:05:39.726587 Set Vref, RX VrefLevel [Byte0]: 32
8646 11:05:39.730222 [Byte1]: 32
8647 11:05:39.734590
8648 11:05:39.734671 Set Vref, RX VrefLevel [Byte0]: 33
8649 11:05:39.737517 [Byte1]: 33
8650 11:05:39.741716
8651 11:05:39.741797 Set Vref, RX VrefLevel [Byte0]: 34
8652 11:05:39.745091 [Byte1]: 34
8653 11:05:39.749379
8654 11:05:39.749459 Set Vref, RX VrefLevel [Byte0]: 35
8655 11:05:39.752846 [Byte1]: 35
8656 11:05:39.757192
8657 11:05:39.757272 Set Vref, RX VrefLevel [Byte0]: 36
8658 11:05:39.760293 [Byte1]: 36
8659 11:05:39.764490
8660 11:05:39.764570 Set Vref, RX VrefLevel [Byte0]: 37
8661 11:05:39.767864 [Byte1]: 37
8662 11:05:39.772569
8663 11:05:39.772649 Set Vref, RX VrefLevel [Byte0]: 38
8664 11:05:39.775490 [Byte1]: 38
8665 11:05:39.779659
8666 11:05:39.779783 Set Vref, RX VrefLevel [Byte0]: 39
8667 11:05:39.783226 [Byte1]: 39
8668 11:05:39.787300
8669 11:05:39.787381 Set Vref, RX VrefLevel [Byte0]: 40
8670 11:05:39.790787 [Byte1]: 40
8671 11:05:39.794831
8672 11:05:39.794912 Set Vref, RX VrefLevel [Byte0]: 41
8673 11:05:39.797969 [Byte1]: 41
8674 11:05:39.802582
8675 11:05:39.802662 Set Vref, RX VrefLevel [Byte0]: 42
8676 11:05:39.805610 [Byte1]: 42
8677 11:05:39.810211
8678 11:05:39.810292 Set Vref, RX VrefLevel [Byte0]: 43
8679 11:05:39.813281 [Byte1]: 43
8680 11:05:39.817408
8681 11:05:39.817488 Set Vref, RX VrefLevel [Byte0]: 44
8682 11:05:39.820812 [Byte1]: 44
8683 11:05:39.825443
8684 11:05:39.825524 Set Vref, RX VrefLevel [Byte0]: 45
8685 11:05:39.828735 [Byte1]: 45
8686 11:05:39.833286
8687 11:05:39.833367 Set Vref, RX VrefLevel [Byte0]: 46
8688 11:05:39.836076 [Byte1]: 46
8689 11:05:39.840751
8690 11:05:39.840831 Set Vref, RX VrefLevel [Byte0]: 47
8691 11:05:39.843643 [Byte1]: 47
8692 11:05:39.847811
8693 11:05:39.847891 Set Vref, RX VrefLevel [Byte0]: 48
8694 11:05:39.851489 [Byte1]: 48
8695 11:05:39.855616
8696 11:05:39.855705 Set Vref, RX VrefLevel [Byte0]: 49
8697 11:05:39.859066 [Byte1]: 49
8698 11:05:39.863172
8699 11:05:39.863253 Set Vref, RX VrefLevel [Byte0]: 50
8700 11:05:39.866182 [Byte1]: 50
8701 11:05:39.870498
8702 11:05:39.870580 Set Vref, RX VrefLevel [Byte0]: 51
8703 11:05:39.873900 [Byte1]: 51
8704 11:05:39.878387
8705 11:05:39.878469 Set Vref, RX VrefLevel [Byte0]: 52
8706 11:05:39.881723 [Byte1]: 52
8707 11:05:39.885716
8708 11:05:39.885798 Set Vref, RX VrefLevel [Byte0]: 53
8709 11:05:39.889075 [Byte1]: 53
8710 11:05:39.893343
8711 11:05:39.893424 Set Vref, RX VrefLevel [Byte0]: 54
8712 11:05:39.896692 [Byte1]: 54
8713 11:05:39.900970
8714 11:05:39.901053 Set Vref, RX VrefLevel [Byte0]: 55
8715 11:05:39.904191 [Byte1]: 55
8716 11:05:39.908486
8717 11:05:39.908566 Set Vref, RX VrefLevel [Byte0]: 56
8718 11:05:39.911970 [Byte1]: 56
8719 11:05:39.916055
8720 11:05:39.916136 Set Vref, RX VrefLevel [Byte0]: 57
8721 11:05:39.919057 [Byte1]: 57
8722 11:05:39.923888
8723 11:05:39.923968 Set Vref, RX VrefLevel [Byte0]: 58
8724 11:05:39.926696 [Byte1]: 58
8725 11:05:39.931299
8726 11:05:39.931379 Set Vref, RX VrefLevel [Byte0]: 59
8727 11:05:39.934315 [Byte1]: 59
8728 11:05:39.938731
8729 11:05:39.938814 Set Vref, RX VrefLevel [Byte0]: 60
8730 11:05:39.942170 [Byte1]: 60
8731 11:05:39.946205
8732 11:05:39.946288 Set Vref, RX VrefLevel [Byte0]: 61
8733 11:05:39.949592 [Byte1]: 61
8734 11:05:39.954344
8735 11:05:39.954426 Set Vref, RX VrefLevel [Byte0]: 62
8736 11:05:39.957475 [Byte1]: 62
8737 11:05:39.961209
8738 11:05:39.961291 Set Vref, RX VrefLevel [Byte0]: 63
8739 11:05:39.964976 [Byte1]: 63
8740 11:05:39.969134
8741 11:05:39.969215 Set Vref, RX VrefLevel [Byte0]: 64
8742 11:05:39.972155 [Byte1]: 64
8743 11:05:39.976754
8744 11:05:39.976835 Set Vref, RX VrefLevel [Byte0]: 65
8745 11:05:39.980438 [Byte1]: 65
8746 11:05:39.984036
8747 11:05:39.984118 Set Vref, RX VrefLevel [Byte0]: 66
8748 11:05:39.987207 [Byte1]: 66
8749 11:05:39.991806
8750 11:05:39.991888 Set Vref, RX VrefLevel [Byte0]: 67
8751 11:05:39.994878 [Byte1]: 67
8752 11:05:39.999382
8753 11:05:39.999464 Set Vref, RX VrefLevel [Byte0]: 68
8754 11:05:40.003087 [Byte1]: 68
8755 11:05:40.006939
8756 11:05:40.007020 Set Vref, RX VrefLevel [Byte0]: 69
8757 11:05:40.010519 [Byte1]: 69
8758 11:05:40.014177
8759 11:05:40.017629 Set Vref, RX VrefLevel [Byte0]: 70
8760 11:05:40.020626 [Byte1]: 70
8761 11:05:40.020708
8762 11:05:40.024274 Set Vref, RX VrefLevel [Byte0]: 71
8763 11:05:40.027383 [Byte1]: 71
8764 11:05:40.027465
8765 11:05:40.030687 Set Vref, RX VrefLevel [Byte0]: 72
8766 11:05:40.034085 [Byte1]: 72
8767 11:05:40.034167
8768 11:05:40.037235 Set Vref, RX VrefLevel [Byte0]: 73
8769 11:05:40.040517 [Byte1]: 73
8770 11:05:40.044966
8771 11:05:40.045047 Set Vref, RX VrefLevel [Byte0]: 74
8772 11:05:40.048075 [Byte1]: 74
8773 11:05:40.052346
8774 11:05:40.052427 Set Vref, RX VrefLevel [Byte0]: 75
8775 11:05:40.055395 [Byte1]: 75
8776 11:05:40.059807
8777 11:05:40.059888 Final RX Vref Byte 0 = 53 to rank0
8778 11:05:40.062963 Final RX Vref Byte 1 = 61 to rank0
8779 11:05:40.066410 Final RX Vref Byte 0 = 53 to rank1
8780 11:05:40.069847 Final RX Vref Byte 1 = 61 to rank1==
8781 11:05:40.073178 Dram Type= 6, Freq= 0, CH_1, rank 0
8782 11:05:40.080145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 11:05:40.080244 ==
8784 11:05:40.080323 DQS Delay:
8785 11:05:40.082793 DQS0 = 0, DQS1 = 0
8786 11:05:40.082883 DQM Delay:
8787 11:05:40.082960 DQM0 = 135, DQM1 = 129
8788 11:05:40.086244 DQ Delay:
8789 11:05:40.089847 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8790 11:05:40.092521 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =130
8791 11:05:40.096026 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8792 11:05:40.099139 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =138
8793 11:05:40.099222
8794 11:05:40.099285
8795 11:05:40.099345
8796 11:05:40.102427 [DramC_TX_OE_Calibration] TA2
8797 11:05:40.105941 Original DQ_B0 (3 6) =30, OEN = 27
8798 11:05:40.109793 Original DQ_B1 (3 6) =30, OEN = 27
8799 11:05:40.112470 24, 0x0, End_B0=24 End_B1=24
8800 11:05:40.115855 25, 0x0, End_B0=25 End_B1=25
8801 11:05:40.115939 26, 0x0, End_B0=26 End_B1=26
8802 11:05:40.119265 27, 0x0, End_B0=27 End_B1=27
8803 11:05:40.122311 28, 0x0, End_B0=28 End_B1=28
8804 11:05:40.125909 29, 0x0, End_B0=29 End_B1=29
8805 11:05:40.125990 30, 0x0, End_B0=30 End_B1=30
8806 11:05:40.128920 31, 0x4141, End_B0=30 End_B1=30
8807 11:05:40.132281 Byte0 end_step=30 best_step=27
8808 11:05:40.135473 Byte1 end_step=30 best_step=27
8809 11:05:40.138875 Byte0 TX OE(2T, 0.5T) = (3, 3)
8810 11:05:40.142272 Byte1 TX OE(2T, 0.5T) = (3, 3)
8811 11:05:40.142353
8812 11:05:40.142418
8813 11:05:40.148873 [DQSOSCAuto] RK0, (LSB)MR18= 0x180e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8814 11:05:40.152049 CH1 RK0: MR19=303, MR18=180E
8815 11:05:40.158474 CH1_RK0: MR19=0x303, MR18=0x180E, DQSOSC=397, MR23=63, INC=23, DEC=15
8816 11:05:40.158557
8817 11:05:40.162208 ----->DramcWriteLeveling(PI) begin...
8818 11:05:40.162292 ==
8819 11:05:40.165124 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 11:05:40.168738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 11:05:40.168822 ==
8822 11:05:40.171730 Write leveling (Byte 0): 24 => 24
8823 11:05:40.175416 Write leveling (Byte 1): 27 => 27
8824 11:05:40.178599 DramcWriteLeveling(PI) end<-----
8825 11:05:40.178681
8826 11:05:40.178748 ==
8827 11:05:40.181705 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 11:05:40.188289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 11:05:40.188372 ==
8830 11:05:40.188437 [Gating] SW mode calibration
8831 11:05:40.198652 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8832 11:05:40.201599 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8833 11:05:40.204931 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 11:05:40.211541 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 11:05:40.214745 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 11:05:40.218080 1 4 12 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
8837 11:05:40.224638 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 11:05:40.227852 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 11:05:40.234551 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 11:05:40.238090 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8841 11:05:40.240884 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8842 11:05:40.247259 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8843 11:05:40.250796 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8844 11:05:40.254166 1 5 12 | B1->B0 | 2c2c 3434 | 0 1 | (0 1) (1 0)
8845 11:05:40.260826 1 5 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8846 11:05:40.263933 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 11:05:40.267353 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 11:05:40.273587 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 11:05:40.277246 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8850 11:05:40.280790 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8851 11:05:40.287328 1 6 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
8852 11:05:40.290458 1 6 12 | B1->B0 | 4646 2b2b | 0 0 | (0 0) (0 0)
8853 11:05:40.293629 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8854 11:05:40.300166 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 11:05:40.303803 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 11:05:40.306660 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 11:05:40.310177 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 11:05:40.316766 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8859 11:05:40.320450 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8860 11:05:40.323383 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8861 11:05:40.330066 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8862 11:05:40.333244 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 11:05:40.336621 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 11:05:40.343644 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 11:05:40.346603 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 11:05:40.349721 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 11:05:40.356442 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 11:05:40.359741 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 11:05:40.362964 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 11:05:40.369513 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 11:05:40.373276 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 11:05:40.376057 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 11:05:40.382779 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 11:05:40.386236 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 11:05:40.389551 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8876 11:05:40.396262 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8877 11:05:40.399278 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8878 11:05:40.402367 Total UI for P1: 0, mck2ui 16
8879 11:05:40.405861 best dqsien dly found for B0: ( 1, 9, 10)
8880 11:05:40.409190 Total UI for P1: 0, mck2ui 16
8881 11:05:40.412411 best dqsien dly found for B1: ( 1, 9, 10)
8882 11:05:40.415448 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8883 11:05:40.419071 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8884 11:05:40.419153
8885 11:05:40.422634 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8886 11:05:40.429030 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8887 11:05:40.429112 [Gating] SW calibration Done
8888 11:05:40.429178 ==
8889 11:05:40.432069 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 11:05:40.438960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 11:05:40.439043 ==
8892 11:05:40.439108 RX Vref Scan: 0
8893 11:05:40.439170
8894 11:05:40.442446 RX Vref 0 -> 0, step: 1
8895 11:05:40.442528
8896 11:05:40.445810 RX Delay 0 -> 252, step: 8
8897 11:05:40.448693 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8898 11:05:40.451930 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8899 11:05:40.455838 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8900 11:05:40.461848 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8901 11:05:40.465449 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8902 11:05:40.468599 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8903 11:05:40.472287 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8904 11:05:40.475308 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8905 11:05:40.481561 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8906 11:05:40.484826 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8907 11:05:40.488515 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8908 11:05:40.491888 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8909 11:05:40.494784 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8910 11:05:40.501671 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8911 11:05:40.504606 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8912 11:05:40.508401 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8913 11:05:40.508498 ==
8914 11:05:40.511402 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 11:05:40.518058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 11:05:40.518173 ==
8917 11:05:40.518240 DQS Delay:
8918 11:05:40.518301 DQS0 = 0, DQS1 = 0
8919 11:05:40.521535 DQM Delay:
8920 11:05:40.521654 DQM0 = 136, DQM1 = 131
8921 11:05:40.524334 DQ Delay:
8922 11:05:40.528133 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8923 11:05:40.531534 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8924 11:05:40.534790 DQ8 =115, DQ9 =115, DQ10 =135, DQ11 =123
8925 11:05:40.538122 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8926 11:05:40.538204
8927 11:05:40.538269
8928 11:05:40.538330 ==
8929 11:05:40.541194 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 11:05:40.544070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 11:05:40.547512 ==
8932 11:05:40.547623
8933 11:05:40.547770
8934 11:05:40.547868 TX Vref Scan disable
8935 11:05:40.551242 == TX Byte 0 ==
8936 11:05:40.554086 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8937 11:05:40.557333 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8938 11:05:40.560798 == TX Byte 1 ==
8939 11:05:40.563989 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8940 11:05:40.567083 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8941 11:05:40.570548 ==
8942 11:05:40.574011 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 11:05:40.577239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 11:05:40.577344 ==
8945 11:05:40.590791
8946 11:05:40.594007 TX Vref early break, caculate TX vref
8947 11:05:40.597159 TX Vref=16, minBit 0, minWin=23, winSum=382
8948 11:05:40.600624 TX Vref=18, minBit 0, minWin=23, winSum=392
8949 11:05:40.603728 TX Vref=20, minBit 1, minWin=23, winSum=401
8950 11:05:40.607332 TX Vref=22, minBit 1, minWin=25, winSum=413
8951 11:05:40.610147 TX Vref=24, minBit 0, minWin=25, winSum=418
8952 11:05:40.617040 TX Vref=26, minBit 0, minWin=25, winSum=421
8953 11:05:40.620232 TX Vref=28, minBit 0, minWin=25, winSum=420
8954 11:05:40.623877 TX Vref=30, minBit 0, minWin=24, winSum=415
8955 11:05:40.626911 TX Vref=32, minBit 0, minWin=23, winSum=407
8956 11:05:40.629842 TX Vref=34, minBit 0, minWin=23, winSum=401
8957 11:05:40.636739 TX Vref=36, minBit 0, minWin=22, winSum=389
8958 11:05:40.640263 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 26
8959 11:05:40.640348
8960 11:05:40.643322 Final TX Range 0 Vref 26
8961 11:05:40.643405
8962 11:05:40.643472 ==
8963 11:05:40.646717 Dram Type= 6, Freq= 0, CH_1, rank 1
8964 11:05:40.649878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8965 11:05:40.649962 ==
8966 11:05:40.653062
8967 11:05:40.653142
8968 11:05:40.653207 TX Vref Scan disable
8969 11:05:40.660124 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8970 11:05:40.660206 == TX Byte 0 ==
8971 11:05:40.663296 u2DelayCellOfst[0]=18 cells (5 PI)
8972 11:05:40.666660 u2DelayCellOfst[1]=11 cells (3 PI)
8973 11:05:40.669863 u2DelayCellOfst[2]=0 cells (0 PI)
8974 11:05:40.672845 u2DelayCellOfst[3]=7 cells (2 PI)
8975 11:05:40.676494 u2DelayCellOfst[4]=7 cells (2 PI)
8976 11:05:40.679410 u2DelayCellOfst[5]=22 cells (6 PI)
8977 11:05:40.682908 u2DelayCellOfst[6]=18 cells (5 PI)
8978 11:05:40.685983 u2DelayCellOfst[7]=7 cells (2 PI)
8979 11:05:40.689384 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8980 11:05:40.692643 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8981 11:05:40.696243 == TX Byte 1 ==
8982 11:05:40.699891 u2DelayCellOfst[8]=0 cells (0 PI)
8983 11:05:40.702670 u2DelayCellOfst[9]=7 cells (2 PI)
8984 11:05:40.706177 u2DelayCellOfst[10]=11 cells (3 PI)
8985 11:05:40.709118 u2DelayCellOfst[11]=7 cells (2 PI)
8986 11:05:40.712727 u2DelayCellOfst[12]=18 cells (5 PI)
8987 11:05:40.716183 u2DelayCellOfst[13]=18 cells (5 PI)
8988 11:05:40.716266 u2DelayCellOfst[14]=18 cells (5 PI)
8989 11:05:40.719136 u2DelayCellOfst[15]=18 cells (5 PI)
8990 11:05:40.725826 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8991 11:05:40.729435 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8992 11:05:40.732873 DramC Write-DBI on
8993 11:05:40.732955 ==
8994 11:05:40.735789 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 11:05:40.739174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 11:05:40.739256 ==
8997 11:05:40.739322
8998 11:05:40.739383
8999 11:05:40.742070 TX Vref Scan disable
9000 11:05:40.742152 == TX Byte 0 ==
9001 11:05:40.748654 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9002 11:05:40.748737 == TX Byte 1 ==
9003 11:05:40.752226 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9004 11:05:40.755286 DramC Write-DBI off
9005 11:05:40.755368
9006 11:05:40.755434 [DATLAT]
9007 11:05:40.758980 Freq=1600, CH1 RK1
9008 11:05:40.759076
9009 11:05:40.759141 DATLAT Default: 0xf
9010 11:05:40.762480 0, 0xFFFF, sum = 0
9011 11:05:40.762564 1, 0xFFFF, sum = 0
9012 11:05:40.766070 2, 0xFFFF, sum = 0
9013 11:05:40.768612 3, 0xFFFF, sum = 0
9014 11:05:40.768696 4, 0xFFFF, sum = 0
9015 11:05:40.772064 5, 0xFFFF, sum = 0
9016 11:05:40.772148 6, 0xFFFF, sum = 0
9017 11:05:40.775502 7, 0xFFFF, sum = 0
9018 11:05:40.775585 8, 0xFFFF, sum = 0
9019 11:05:40.778437 9, 0xFFFF, sum = 0
9020 11:05:40.778536 10, 0xFFFF, sum = 0
9021 11:05:40.781818 11, 0xFFFF, sum = 0
9022 11:05:40.781904 12, 0xFFFF, sum = 0
9023 11:05:40.785057 13, 0xFFFF, sum = 0
9024 11:05:40.785186 14, 0x0, sum = 1
9025 11:05:40.788440 15, 0x0, sum = 2
9026 11:05:40.788525 16, 0x0, sum = 3
9027 11:05:40.791542 17, 0x0, sum = 4
9028 11:05:40.791665 best_step = 15
9029 11:05:40.791762
9030 11:05:40.791824 ==
9031 11:05:40.795041 Dram Type= 6, Freq= 0, CH_1, rank 1
9032 11:05:40.801696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9033 11:05:40.801779 ==
9034 11:05:40.801845 RX Vref Scan: 0
9035 11:05:40.801907
9036 11:05:40.805273 RX Vref 0 -> 0, step: 1
9037 11:05:40.805376
9038 11:05:40.808195 RX Delay 11 -> 252, step: 4
9039 11:05:40.811884 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9040 11:05:40.814802 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9041 11:05:40.818332 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9042 11:05:40.825149 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9043 11:05:40.828265 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9044 11:05:40.831140 iDelay=203, Bit 5, Center 142 (91 ~ 194) 104
9045 11:05:40.834638 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9046 11:05:40.837803 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9047 11:05:40.844574 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9048 11:05:40.847746 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9049 11:05:40.851185 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9050 11:05:40.854484 iDelay=203, Bit 11, Center 120 (67 ~ 174) 108
9051 11:05:40.857823 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9052 11:05:40.864424 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9053 11:05:40.867826 iDelay=203, Bit 14, Center 132 (75 ~ 190) 116
9054 11:05:40.870781 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9055 11:05:40.870863 ==
9056 11:05:40.874357 Dram Type= 6, Freq= 0, CH_1, rank 1
9057 11:05:40.880797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9058 11:05:40.880885 ==
9059 11:05:40.880951 DQS Delay:
9060 11:05:40.881013 DQS0 = 0, DQS1 = 0
9061 11:05:40.884049 DQM Delay:
9062 11:05:40.884131 DQM0 = 133, DQM1 = 127
9063 11:05:40.887405 DQ Delay:
9064 11:05:40.890878 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9065 11:05:40.894414 DQ4 =134, DQ5 =142, DQ6 =146, DQ7 =130
9066 11:05:40.897463 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =120
9067 11:05:40.900638 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9068 11:05:40.900721
9069 11:05:40.900786
9070 11:05:40.900864
9071 11:05:40.904181 [DramC_TX_OE_Calibration] TA2
9072 11:05:40.907084 Original DQ_B0 (3 6) =30, OEN = 27
9073 11:05:40.910907 Original DQ_B1 (3 6) =30, OEN = 27
9074 11:05:40.913823 24, 0x0, End_B0=24 End_B1=24
9075 11:05:40.913907 25, 0x0, End_B0=25 End_B1=25
9076 11:05:40.917518 26, 0x0, End_B0=26 End_B1=26
9077 11:05:40.920579 27, 0x0, End_B0=27 End_B1=27
9078 11:05:40.923620 28, 0x0, End_B0=28 End_B1=28
9079 11:05:40.926964 29, 0x0, End_B0=29 End_B1=29
9080 11:05:40.927048 30, 0x0, End_B0=30 End_B1=30
9081 11:05:40.930666 31, 0x4141, End_B0=30 End_B1=30
9082 11:05:40.933725 Byte0 end_step=30 best_step=27
9083 11:05:40.937351 Byte1 end_step=30 best_step=27
9084 11:05:40.940409 Byte0 TX OE(2T, 0.5T) = (3, 3)
9085 11:05:40.943645 Byte1 TX OE(2T, 0.5T) = (3, 3)
9086 11:05:40.943784
9087 11:05:40.943888
9088 11:05:40.950003 [DQSOSCAuto] RK1, (LSB)MR18= 0x905, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 405 ps
9089 11:05:40.953590 CH1 RK1: MR19=303, MR18=905
9090 11:05:40.960068 CH1_RK1: MR19=0x303, MR18=0x905, DQSOSC=405, MR23=63, INC=22, DEC=15
9091 11:05:40.963660 [RxdqsGatingPostProcess] freq 1600
9092 11:05:40.966662 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9093 11:05:40.969585 best DQS0 dly(2T, 0.5T) = (1, 1)
9094 11:05:40.973326 best DQS1 dly(2T, 0.5T) = (1, 1)
9095 11:05:40.976495 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9096 11:05:40.979882 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9097 11:05:40.983319 best DQS0 dly(2T, 0.5T) = (1, 1)
9098 11:05:40.986261 best DQS1 dly(2T, 0.5T) = (1, 1)
9099 11:05:40.989612 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9100 11:05:40.992680 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9101 11:05:40.996318 Pre-setting of DQS Precalculation
9102 11:05:40.999495 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9103 11:05:41.006270 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9104 11:05:41.015701 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9105 11:05:41.015785
9106 11:05:41.015851
9107 11:05:41.019102 [Calibration Summary] 3200 Mbps
9108 11:05:41.019184 CH 0, Rank 0
9109 11:05:41.022971 SW Impedance : PASS
9110 11:05:41.023053 DUTY Scan : NO K
9111 11:05:41.025692 ZQ Calibration : PASS
9112 11:05:41.029162 Jitter Meter : NO K
9113 11:05:41.029244 CBT Training : PASS
9114 11:05:41.032411 Write leveling : PASS
9115 11:05:41.036190 RX DQS gating : PASS
9116 11:05:41.036272 RX DQ/DQS(RDDQC) : PASS
9117 11:05:41.038886 TX DQ/DQS : PASS
9118 11:05:41.042528 RX DATLAT : PASS
9119 11:05:41.042610 RX DQ/DQS(Engine): PASS
9120 11:05:41.045708 TX OE : PASS
9121 11:05:41.045795 All Pass.
9122 11:05:41.045868
9123 11:05:41.048770 CH 0, Rank 1
9124 11:05:41.048852 SW Impedance : PASS
9125 11:05:41.052366 DUTY Scan : NO K
9126 11:05:41.055371 ZQ Calibration : PASS
9127 11:05:41.055453 Jitter Meter : NO K
9128 11:05:41.058491 CBT Training : PASS
9129 11:05:41.058573 Write leveling : PASS
9130 11:05:41.062061 RX DQS gating : PASS
9131 11:05:41.064951 RX DQ/DQS(RDDQC) : PASS
9132 11:05:41.065033 TX DQ/DQS : PASS
9133 11:05:41.068675 RX DATLAT : PASS
9134 11:05:41.071677 RX DQ/DQS(Engine): PASS
9135 11:05:41.071793 TX OE : PASS
9136 11:05:41.075088 All Pass.
9137 11:05:41.075169
9138 11:05:41.075234 CH 1, Rank 0
9139 11:05:41.078160 SW Impedance : PASS
9140 11:05:41.078241 DUTY Scan : NO K
9141 11:05:41.081729 ZQ Calibration : PASS
9142 11:05:41.085291 Jitter Meter : NO K
9143 11:05:41.085373 CBT Training : PASS
9144 11:05:41.088259 Write leveling : PASS
9145 11:05:41.091638 RX DQS gating : PASS
9146 11:05:41.091761 RX DQ/DQS(RDDQC) : PASS
9147 11:05:41.094913 TX DQ/DQS : PASS
9148 11:05:41.098214 RX DATLAT : PASS
9149 11:05:41.098296 RX DQ/DQS(Engine): PASS
9150 11:05:41.101485 TX OE : PASS
9151 11:05:41.101568 All Pass.
9152 11:05:41.101632
9153 11:05:41.104673 CH 1, Rank 1
9154 11:05:41.104755 SW Impedance : PASS
9155 11:05:41.108094 DUTY Scan : NO K
9156 11:05:41.111394 ZQ Calibration : PASS
9157 11:05:41.111505 Jitter Meter : NO K
9158 11:05:41.114739 CBT Training : PASS
9159 11:05:41.117851 Write leveling : PASS
9160 11:05:41.117933 RX DQS gating : PASS
9161 11:05:41.121169 RX DQ/DQS(RDDQC) : PASS
9162 11:05:41.124543 TX DQ/DQS : PASS
9163 11:05:41.124626 RX DATLAT : PASS
9164 11:05:41.128133 RX DQ/DQS(Engine): PASS
9165 11:05:41.130910 TX OE : PASS
9166 11:05:41.130992 All Pass.
9167 11:05:41.131057
9168 11:05:41.131118 DramC Write-DBI on
9169 11:05:41.134594 PER_BANK_REFRESH: Hybrid Mode
9170 11:05:41.137677 TX_TRACKING: ON
9171 11:05:41.144282 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9172 11:05:41.154599 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9173 11:05:41.160610 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9174 11:05:41.164180 [FAST_K] Save calibration result to emmc
9175 11:05:41.167705 sync common calibartion params.
9176 11:05:41.170483 sync cbt_mode0:1, 1:1
9177 11:05:41.170565 dram_init: ddr_geometry: 2
9178 11:05:41.174236 dram_init: ddr_geometry: 2
9179 11:05:41.177071 dram_init: ddr_geometry: 2
9180 11:05:41.180494 0:dram_rank_size:100000000
9181 11:05:41.180600 1:dram_rank_size:100000000
9182 11:05:41.187180 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9183 11:05:41.190305 DFS_SHUFFLE_HW_MODE: ON
9184 11:05:41.193980 dramc_set_vcore_voltage set vcore to 725000
9185 11:05:41.194063 Read voltage for 1600, 0
9186 11:05:41.196972 Vio18 = 0
9187 11:05:41.197054 Vcore = 725000
9188 11:05:41.197119 Vdram = 0
9189 11:05:41.200421 Vddq = 0
9190 11:05:41.200503 Vmddr = 0
9191 11:05:41.203402 switch to 3200 Mbps bootup
9192 11:05:41.203503 [DramcRunTimeConfig]
9193 11:05:41.203619 PHYPLL
9194 11:05:41.207092 DPM_CONTROL_AFTERK: ON
9195 11:05:41.210176 PER_BANK_REFRESH: ON
9196 11:05:41.213377 REFRESH_OVERHEAD_REDUCTION: ON
9197 11:05:41.213459 CMD_PICG_NEW_MODE: OFF
9198 11:05:41.217495 XRTWTW_NEW_MODE: ON
9199 11:05:41.217576 XRTRTR_NEW_MODE: ON
9200 11:05:41.220511 TX_TRACKING: ON
9201 11:05:41.220593 RDSEL_TRACKING: OFF
9202 11:05:41.223592 DQS Precalculation for DVFS: ON
9203 11:05:41.226728 RX_TRACKING: OFF
9204 11:05:41.226848 HW_GATING DBG: ON
9205 11:05:41.230040 ZQCS_ENABLE_LP4: ON
9206 11:05:41.230122 RX_PICG_NEW_MODE: ON
9207 11:05:41.233219 TX_PICG_NEW_MODE: ON
9208 11:05:41.233302 ENABLE_RX_DCM_DPHY: ON
9209 11:05:41.236623 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9210 11:05:41.240268 DUMMY_READ_FOR_TRACKING: OFF
9211 11:05:41.242921 !!! SPM_CONTROL_AFTERK: OFF
9212 11:05:41.246613 !!! SPM could not control APHY
9213 11:05:41.246695 IMPEDANCE_TRACKING: ON
9214 11:05:41.249696 TEMP_SENSOR: ON
9215 11:05:41.249778 HW_SAVE_FOR_SR: OFF
9216 11:05:41.253090 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9217 11:05:41.256089 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9218 11:05:41.259540 Read ODT Tracking: ON
9219 11:05:41.262961 Refresh Rate DeBounce: ON
9220 11:05:41.263043 DFS_NO_QUEUE_FLUSH: ON
9221 11:05:41.266514 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9222 11:05:41.269323 ENABLE_DFS_RUNTIME_MRW: OFF
9223 11:05:41.273089 DDR_RESERVE_NEW_MODE: ON
9224 11:05:41.273171 MR_CBT_SWITCH_FREQ: ON
9225 11:05:41.276044 =========================
9226 11:05:41.295184 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9227 11:05:41.298653 dram_init: ddr_geometry: 2
9228 11:05:41.316706 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9229 11:05:41.319617 dram_init: dram init end (result: 0)
9230 11:05:41.326775 DRAM-K: Full calibration passed in 24677 msecs
9231 11:05:41.329823 MRC: failed to locate region type 0.
9232 11:05:41.329905 DRAM rank0 size:0x100000000,
9233 11:05:41.333105 DRAM rank1 size=0x100000000
9234 11:05:41.342725 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9235 11:05:41.349694 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9236 11:05:41.356103 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9237 11:05:41.365664 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9238 11:05:41.365748 DRAM rank0 size:0x100000000,
9239 11:05:41.369055 DRAM rank1 size=0x100000000
9240 11:05:41.369137 CBMEM:
9241 11:05:41.372823 IMD: root @ 0xfffff000 254 entries.
9242 11:05:41.375787 IMD: root @ 0xffffec00 62 entries.
9243 11:05:41.379507 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9244 11:05:41.385994 WARNING: RO_VPD is uninitialized or empty.
9245 11:05:41.388917 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9246 11:05:41.396948 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9247 11:05:41.409865 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9248 11:05:41.420868 BS: romstage times (exec / console): total (unknown) / 24164 ms
9249 11:05:41.421107
9250 11:05:41.421326
9251 11:05:41.430654 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9252 11:05:41.433965 ARM64: Exception handlers installed.
9253 11:05:41.437301 ARM64: Testing exception
9254 11:05:41.440632 ARM64: Done test exception
9255 11:05:41.440744 Enumerating buses...
9256 11:05:41.443942 Show all devs... Before device enumeration.
9257 11:05:41.447231 Root Device: enabled 1
9258 11:05:41.450411 CPU_CLUSTER: 0: enabled 1
9259 11:05:41.450575 CPU: 00: enabled 1
9260 11:05:41.453878 Compare with tree...
9261 11:05:41.453965 Root Device: enabled 1
9262 11:05:41.457010 CPU_CLUSTER: 0: enabled 1
9263 11:05:41.460433 CPU: 00: enabled 1
9264 11:05:41.460542 Root Device scanning...
9265 11:05:41.463521 scan_static_bus for Root Device
9266 11:05:41.466989 CPU_CLUSTER: 0 enabled
9267 11:05:41.470571 scan_static_bus for Root Device done
9268 11:05:41.473633 scan_bus: bus Root Device finished in 8 msecs
9269 11:05:41.473744 done
9270 11:05:41.480304 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9271 11:05:41.483880 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9272 11:05:41.490164 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9273 11:05:41.496897 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9274 11:05:41.497009 Allocating resources...
9275 11:05:41.499806 Reading resources...
9276 11:05:41.503944 Root Device read_resources bus 0 link: 0
9277 11:05:41.506116 DRAM rank0 size:0x100000000,
9278 11:05:41.506229 DRAM rank1 size=0x100000000
9279 11:05:41.513074 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9280 11:05:41.513159 CPU: 00 missing read_resources
9281 11:05:41.519338 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9282 11:05:41.522750 Root Device read_resources bus 0 link: 0 done
9283 11:05:41.526286 Done reading resources.
9284 11:05:41.529305 Show resources in subtree (Root Device)...After reading.
9285 11:05:41.532430 Root Device child on link 0 CPU_CLUSTER: 0
9286 11:05:41.535889 CPU_CLUSTER: 0 child on link 0 CPU: 00
9287 11:05:41.545943 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9288 11:05:41.546030 CPU: 00
9289 11:05:41.552513 Root Device assign_resources, bus 0 link: 0
9290 11:05:41.555437 CPU_CLUSTER: 0 missing set_resources
9291 11:05:41.559084 Root Device assign_resources, bus 0 link: 0 done
9292 11:05:41.562304 Done setting resources.
9293 11:05:41.565920 Show resources in subtree (Root Device)...After assigning values.
9294 11:05:41.571812 Root Device child on link 0 CPU_CLUSTER: 0
9295 11:05:41.575360 CPU_CLUSTER: 0 child on link 0 CPU: 00
9296 11:05:41.581606 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9297 11:05:41.585076 CPU: 00
9298 11:05:41.585181 Done allocating resources.
9299 11:05:41.591515 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9300 11:05:41.595120 Enabling resources...
9301 11:05:41.595202 done.
9302 11:05:41.598156 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9303 11:05:41.601858 Initializing devices...
9304 11:05:41.601939 Root Device init
9305 11:05:41.604937 init hardware done!
9306 11:05:41.608313 0x00000018: ctrlr->caps
9307 11:05:41.608396 52.000 MHz: ctrlr->f_max
9308 11:05:41.612219 0.400 MHz: ctrlr->f_min
9309 11:05:41.614533 0x40ff8080: ctrlr->voltages
9310 11:05:41.614642 sclk: 390625
9311 11:05:41.614761 Bus Width = 1
9312 11:05:41.618387 sclk: 390625
9313 11:05:41.618469 Bus Width = 1
9314 11:05:41.621645 Early init status = 3
9315 11:05:41.624475 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9316 11:05:41.629696 in-header: 03 fc 00 00 01 00 00 00
9317 11:05:41.632610 in-data: 00
9318 11:05:41.636013 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9319 11:05:41.641989 in-header: 03 fd 00 00 00 00 00 00
9320 11:05:41.644649 in-data:
9321 11:05:41.648309 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9322 11:05:41.652912 in-header: 03 fc 00 00 01 00 00 00
9323 11:05:41.656407 in-data: 00
9324 11:05:41.659342 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9325 11:05:41.664687 in-header: 03 fd 00 00 00 00 00 00
9326 11:05:41.667935 in-data:
9327 11:05:41.671745 [SSUSB] Setting up USB HOST controller...
9328 11:05:41.674864 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9329 11:05:41.678425 [SSUSB] phy power-on done.
9330 11:05:41.681873 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9331 11:05:41.687753 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9332 11:05:41.691276 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9333 11:05:41.697907 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9334 11:05:41.704695 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9335 11:05:41.711292 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9336 11:05:41.717777 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9337 11:05:41.724109 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9338 11:05:41.727409 SPM: binary array size = 0x9dc
9339 11:05:41.731108 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9340 11:05:41.737561 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9341 11:05:41.744049 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9342 11:05:41.750885 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9343 11:05:41.754132 configure_display: Starting display init
9344 11:05:41.788312 anx7625_power_on_init: Init interface.
9345 11:05:41.791637 anx7625_disable_pd_protocol: Disabled PD feature.
9346 11:05:41.794399 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9347 11:05:41.822294 anx7625_start_dp_work: Secure OCM version=00
9348 11:05:41.825956 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9349 11:05:41.840751 sp_tx_get_edid_block: EDID Block = 1
9350 11:05:41.943534 Extracted contents:
9351 11:05:41.946348 header: 00 ff ff ff ff ff ff 00
9352 11:05:41.949907 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9353 11:05:41.952969 version: 01 04
9354 11:05:41.956677 basic params: 95 1f 11 78 0a
9355 11:05:41.959708 chroma info: 76 90 94 55 54 90 27 21 50 54
9356 11:05:41.963069 established: 00 00 00
9357 11:05:41.969497 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9358 11:05:41.972756 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9359 11:05:41.979379 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9360 11:05:41.986025 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9361 11:05:41.992458 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9362 11:05:41.996133 extensions: 00
9363 11:05:41.996210 checksum: fb
9364 11:05:41.996272
9365 11:05:42.002296 Manufacturer: IVO Model 57d Serial Number 0
9366 11:05:42.002370 Made week 0 of 2020
9367 11:05:42.006009 EDID version: 1.4
9368 11:05:42.006085 Digital display
9369 11:05:42.009565 6 bits per primary color channel
9370 11:05:42.009644 DisplayPort interface
9371 11:05:42.012475 Maximum image size: 31 cm x 17 cm
9372 11:05:42.015554 Gamma: 220%
9373 11:05:42.015652 Check DPMS levels
9374 11:05:42.022141 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9375 11:05:42.025425 First detailed timing is preferred timing
9376 11:05:42.025501 Established timings supported:
9377 11:05:42.029055 Standard timings supported:
9378 11:05:42.032121 Detailed timings
9379 11:05:42.035203 Hex of detail: 383680a07038204018303c0035ae10000019
9380 11:05:42.042198 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9381 11:05:42.045639 0780 0798 07c8 0820 hborder 0
9382 11:05:42.048313 0438 043b 0447 0458 vborder 0
9383 11:05:42.052040 -hsync -vsync
9384 11:05:42.052122 Did detailed timing
9385 11:05:42.058409 Hex of detail: 000000000000000000000000000000000000
9386 11:05:42.061614 Manufacturer-specified data, tag 0
9387 11:05:42.064948 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9388 11:05:42.068174 ASCII string: InfoVision
9389 11:05:42.072310 Hex of detail: 000000fe00523134304e574635205248200a
9390 11:05:42.074959 ASCII string: R140NWF5 RH
9391 11:05:42.075027 Checksum
9392 11:05:42.078392 Checksum: 0xfb (valid)
9393 11:05:42.081572 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9394 11:05:42.084952 DSI data_rate: 832800000 bps
9395 11:05:42.091229 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9396 11:05:42.094836 anx7625_parse_edid: pixelclock(138800).
9397 11:05:42.098523 hactive(1920), hsync(48), hfp(24), hbp(88)
9398 11:05:42.101405 vactive(1080), vsync(12), vfp(3), vbp(17)
9399 11:05:42.104515 anx7625_dsi_config: config dsi.
9400 11:05:42.111235 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9401 11:05:42.124908 anx7625_dsi_config: success to config DSI
9402 11:05:42.128231 anx7625_dp_start: MIPI phy setup OK.
9403 11:05:42.131764 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9404 11:05:42.134845 mtk_ddp_mode_set invalid vrefresh 60
9405 11:05:42.138577 main_disp_path_setup
9406 11:05:42.138655 ovl_layer_smi_id_en
9407 11:05:42.141571 ovl_layer_smi_id_en
9408 11:05:42.141650 ccorr_config
9409 11:05:42.141718 aal_config
9410 11:05:42.145286 gamma_config
9411 11:05:42.145382 postmask_config
9412 11:05:42.148203 dither_config
9413 11:05:42.151348 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9414 11:05:42.158307 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9415 11:05:42.161560 Root Device init finished in 555 msecs
9416 11:05:42.164918 CPU_CLUSTER: 0 init
9417 11:05:42.171596 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9418 11:05:42.178195 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9419 11:05:42.178303 APU_MBOX 0x190000b0 = 0x10001
9420 11:05:42.181232 APU_MBOX 0x190001b0 = 0x10001
9421 11:05:42.184446 APU_MBOX 0x190005b0 = 0x10001
9422 11:05:42.187759 APU_MBOX 0x190006b0 = 0x10001
9423 11:05:42.194319 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9424 11:05:42.204612 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9425 11:05:42.216572 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9426 11:05:42.222988 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9427 11:05:42.235090 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9428 11:05:42.244522 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9429 11:05:42.247007 CPU_CLUSTER: 0 init finished in 81 msecs
9430 11:05:42.250860 Devices initialized
9431 11:05:42.253634 Show all devs... After init.
9432 11:05:42.253718 Root Device: enabled 1
9433 11:05:42.257443 CPU_CLUSTER: 0: enabled 1
9434 11:05:42.260408 CPU: 00: enabled 1
9435 11:05:42.263988 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9436 11:05:42.266980 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9437 11:05:42.270225 ELOG: NV offset 0x57f000 size 0x1000
9438 11:05:42.277193 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9439 11:05:42.283770 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9440 11:05:42.287077 ELOG: Event(17) added with size 13 at 2024-03-03 11:05:43 UTC
9441 11:05:42.293868 out: cmd=0x121: 03 db 21 01 00 00 00 00
9442 11:05:42.296711 in-header: 03 66 00 00 2c 00 00 00
9443 11:05:42.310106 in-data: f9 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9444 11:05:42.313025 ELOG: Event(A1) added with size 10 at 2024-03-03 11:05:43 UTC
9445 11:05:42.320008 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9446 11:05:42.326440 ELOG: Event(A0) added with size 9 at 2024-03-03 11:05:43 UTC
9447 11:05:42.329690 elog_add_boot_reason: Logged dev mode boot
9448 11:05:42.336393 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9449 11:05:42.336476 Finalize devices...
9450 11:05:42.339645 Devices finalized
9451 11:05:42.343293 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9452 11:05:42.346351 Writing coreboot table at 0xffe64000
9453 11:05:42.350096 0. 000000000010a000-0000000000113fff: RAMSTAGE
9454 11:05:42.356277 1. 0000000040000000-00000000400fffff: RAM
9455 11:05:42.359862 2. 0000000040100000-000000004032afff: RAMSTAGE
9456 11:05:42.362748 3. 000000004032b000-00000000545fffff: RAM
9457 11:05:42.366430 4. 0000000054600000-000000005465ffff: BL31
9458 11:05:42.369370 5. 0000000054660000-00000000ffe63fff: RAM
9459 11:05:42.376227 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9460 11:05:42.379239 7. 0000000100000000-000000023fffffff: RAM
9461 11:05:42.382824 Passing 5 GPIOs to payload:
9462 11:05:42.385959 NAME | PORT | POLARITY | VALUE
9463 11:05:42.392246 EC in RW | 0x000000aa | low | undefined
9464 11:05:42.395951 EC interrupt | 0x00000005 | low | undefined
9465 11:05:42.402700 TPM interrupt | 0x000000ab | high | undefined
9466 11:05:42.405823 SD card detect | 0x00000011 | high | undefined
9467 11:05:42.409371 speaker enable | 0x00000093 | high | undefined
9468 11:05:42.412345 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9469 11:05:42.415877 in-header: 03 f9 00 00 02 00 00 00
9470 11:05:42.419152 in-data: 02 00
9471 11:05:42.422681 ADC[4]: Raw value=904139 ID=7
9472 11:05:42.425788 ADC[3]: Raw value=213652 ID=1
9473 11:05:42.425896 RAM Code: 0x71
9474 11:05:42.429191 ADC[6]: Raw value=75036 ID=0
9475 11:05:42.432115 ADC[5]: Raw value=213652 ID=1
9476 11:05:42.432196 SKU Code: 0x1
9477 11:05:42.438785 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5d13
9478 11:05:42.438880 coreboot table: 964 bytes.
9479 11:05:42.442418 IMD ROOT 0. 0xfffff000 0x00001000
9480 11:05:42.445229 IMD SMALL 1. 0xffffe000 0x00001000
9481 11:05:42.448887 RO MCACHE 2. 0xffffc000 0x00001104
9482 11:05:42.451946 CONSOLE 3. 0xfff7c000 0x00080000
9483 11:05:42.455693 FMAP 4. 0xfff7b000 0x00000452
9484 11:05:42.458657 TIME STAMP 5. 0xfff7a000 0x00000910
9485 11:05:42.462130 VBOOT WORK 6. 0xfff66000 0x00014000
9486 11:05:42.465211 RAMOOPS 7. 0xffe66000 0x00100000
9487 11:05:42.468485 COREBOOT 8. 0xffe64000 0x00002000
9488 11:05:42.472181 IMD small region:
9489 11:05:42.475193 IMD ROOT 0. 0xffffec00 0x00000400
9490 11:05:42.478666 VPD 1. 0xffffeb80 0x0000006c
9491 11:05:42.481615 MMC STATUS 2. 0xffffeb60 0x00000004
9492 11:05:42.488323 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9493 11:05:42.488433 Probing TPM: done!
9494 11:05:42.495293 Connected to device vid:did:rid of 1ae0:0028:00
9495 11:05:42.502258 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9496 11:05:42.505461 Initialized TPM device CR50 revision 0
9497 11:05:42.508667 Checking cr50 for pending updates
9498 11:05:42.513943 Reading cr50 TPM mode
9499 11:05:42.522589 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9500 11:05:42.528754 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9501 11:05:42.569651 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9502 11:05:42.572757 Checking segment from ROM address 0x40100000
9503 11:05:42.575964 Checking segment from ROM address 0x4010001c
9504 11:05:42.582951 Loading segment from ROM address 0x40100000
9505 11:05:42.583063 code (compression=0)
9506 11:05:42.592750 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9507 11:05:42.599335 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9508 11:05:42.599418 it's not compressed!
9509 11:05:42.605778 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9510 11:05:42.608916 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9511 11:05:42.629707 Loading segment from ROM address 0x4010001c
9512 11:05:42.629791 Entry Point 0x80000000
9513 11:05:42.632984 Loaded segments
9514 11:05:42.636636 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9515 11:05:42.642961 Jumping to boot code at 0x80000000(0xffe64000)
9516 11:05:42.649581 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9517 11:05:42.656177 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9518 11:05:42.664278 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9519 11:05:42.667665 Checking segment from ROM address 0x40100000
9520 11:05:42.670698 Checking segment from ROM address 0x4010001c
9521 11:05:42.677301 Loading segment from ROM address 0x40100000
9522 11:05:42.677380 code (compression=1)
9523 11:05:42.683842 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9524 11:05:42.693789 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9525 11:05:42.693891 using LZMA
9526 11:05:42.702276 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9527 11:05:42.708716 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9528 11:05:42.712094 Loading segment from ROM address 0x4010001c
9529 11:05:42.712198 Entry Point 0x54601000
9530 11:05:42.715593 Loaded segments
9531 11:05:42.719353 NOTICE: MT8192 bl31_setup
9532 11:05:42.726015 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9533 11:05:42.729254 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9534 11:05:42.732610 WARNING: region 0:
9535 11:05:42.736155 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9536 11:05:42.736236 WARNING: region 1:
9537 11:05:42.742577 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9538 11:05:42.745769 WARNING: region 2:
9539 11:05:42.749400 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9540 11:05:42.752563 WARNING: region 3:
9541 11:05:42.758845 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9542 11:05:42.758927 WARNING: region 4:
9543 11:05:42.765600 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9544 11:05:42.765682 WARNING: region 5:
9545 11:05:42.768888 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9546 11:05:42.772414 WARNING: region 6:
9547 11:05:42.775793 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9548 11:05:42.778874 WARNING: region 7:
9549 11:05:42.782379 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9550 11:05:42.788569 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9551 11:05:42.792105 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9552 11:05:42.798817 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9553 11:05:42.801939 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9554 11:05:42.805430 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9555 11:05:42.811929 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9556 11:05:42.814958 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9557 11:05:42.818292 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9558 11:05:42.825352 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9559 11:05:42.828633 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9560 11:05:42.834600 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9561 11:05:42.838123 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9562 11:05:42.841228 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9563 11:05:42.847894 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9564 11:05:42.851466 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9565 11:05:42.858050 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9566 11:05:42.860948 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9567 11:05:42.864389 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9568 11:05:42.871555 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9569 11:05:42.874444 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9570 11:05:42.877810 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9571 11:05:42.884636 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9572 11:05:42.887832 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9573 11:05:42.894483 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9574 11:05:42.898159 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9575 11:05:42.901103 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9576 11:05:42.907574 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9577 11:05:42.910709 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9578 11:05:42.917206 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9579 11:05:42.920601 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9580 11:05:42.927034 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9581 11:05:42.930645 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9582 11:05:42.934283 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9583 11:05:42.936905 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9584 11:05:42.943876 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9585 11:05:42.947062 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9586 11:05:42.950407 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9587 11:05:42.954032 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9588 11:05:42.960326 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9589 11:05:42.963694 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9590 11:05:42.967181 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9591 11:05:42.970097 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9592 11:05:42.976602 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9593 11:05:42.980303 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9594 11:05:42.983862 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9595 11:05:42.990093 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9596 11:05:42.993475 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9597 11:05:42.996677 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9598 11:05:43.003609 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9599 11:05:43.006751 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9600 11:05:43.009978 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9601 11:05:43.016425 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9602 11:05:43.019825 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9603 11:05:43.026399 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9604 11:05:43.029899 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9605 11:05:43.036337 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9606 11:05:43.040224 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9607 11:05:43.042937 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9608 11:05:43.049463 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9609 11:05:43.053022 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9610 11:05:43.059830 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9611 11:05:43.063237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9612 11:05:43.069510 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9613 11:05:43.072928 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9614 11:05:43.079835 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9615 11:05:43.082916 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9616 11:05:43.085976 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9617 11:05:43.093104 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9618 11:05:43.096081 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9619 11:05:43.102862 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9620 11:05:43.106260 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9621 11:05:43.112658 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9622 11:05:43.116138 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9623 11:05:43.119483 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9624 11:05:43.126000 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9625 11:05:43.129266 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9626 11:05:43.135689 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9627 11:05:43.139316 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9628 11:05:43.145934 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9629 11:05:43.148757 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9630 11:05:43.156005 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9631 11:05:43.158978 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9632 11:05:43.165529 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9633 11:05:43.169212 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9634 11:05:43.172020 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9635 11:05:43.178702 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9636 11:05:43.182223 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9637 11:05:43.188722 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9638 11:05:43.191836 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9639 11:05:43.198934 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9640 11:05:43.201797 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9641 11:05:43.205044 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9642 11:05:43.211927 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9643 11:05:43.215455 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9644 11:05:43.221896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9645 11:05:43.225350 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9646 11:05:43.231836 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9647 11:05:43.235127 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9648 11:05:43.238527 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9649 11:05:43.241628 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9650 11:05:43.248235 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9651 11:05:43.251695 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9652 11:05:43.255805 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9653 11:05:43.261882 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9654 11:05:43.264963 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9655 11:05:43.271477 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9656 11:05:43.275098 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9657 11:05:43.277978 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9658 11:05:43.285010 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9659 11:05:43.287789 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9660 11:05:43.294945 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9661 11:05:43.297991 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9662 11:05:43.301316 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9663 11:05:43.307852 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9664 11:05:43.311303 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9665 11:05:43.318130 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9666 11:05:43.320927 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9667 11:05:43.324625 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9668 11:05:43.331141 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9669 11:05:43.334660 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9670 11:05:43.337562 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9671 11:05:43.340865 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9672 11:05:43.347527 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9673 11:05:43.351010 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9674 11:05:43.354153 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9675 11:05:43.360654 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9676 11:05:43.364275 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9677 11:05:43.367584 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9678 11:05:43.373804 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9679 11:05:43.377329 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9680 11:05:43.384044 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9681 11:05:43.386837 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9682 11:05:43.390774 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9683 11:05:43.397064 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9684 11:05:43.400489 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9685 11:05:43.407130 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9686 11:05:43.410162 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9687 11:05:43.413824 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9688 11:05:43.420102 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9689 11:05:43.423863 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9690 11:05:43.430282 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9691 11:05:43.433813 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9692 11:05:43.436740 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9693 11:05:43.443258 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9694 11:05:43.446924 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9695 11:05:43.453636 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9696 11:05:43.456837 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9697 11:05:43.459821 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9698 11:05:43.466451 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9699 11:05:43.469904 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9700 11:05:43.476245 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9701 11:05:43.479571 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9702 11:05:43.483196 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9703 11:05:43.489493 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9704 11:05:43.492887 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9705 11:05:43.499663 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9706 11:05:43.502729 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9707 11:05:43.506408 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9708 11:05:43.512453 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9709 11:05:43.516117 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9710 11:05:43.522336 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9711 11:05:43.525816 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9712 11:05:43.529283 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9713 11:05:43.536082 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9714 11:05:43.539392 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9715 11:05:43.545673 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9716 11:05:43.549110 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9717 11:05:43.552441 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9718 11:05:43.558899 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9719 11:05:43.562098 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9720 11:05:43.568768 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9721 11:05:43.571799 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9722 11:05:43.575844 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9723 11:05:43.581804 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9724 11:05:43.585618 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9725 11:05:43.591869 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9726 11:05:43.594878 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9727 11:05:43.598453 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9728 11:05:43.604984 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9729 11:05:43.608652 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9730 11:05:43.615011 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9731 11:05:43.617977 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9732 11:05:43.621549 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9733 11:05:43.627895 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9734 11:05:43.631609 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9735 11:05:43.637957 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9736 11:05:43.641181 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9737 11:05:43.644436 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9738 11:05:43.651000 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9739 11:05:43.654041 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9740 11:05:43.660745 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9741 11:05:43.664233 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9742 11:05:43.670721 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9743 11:05:43.674030 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9744 11:05:43.677564 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9745 11:05:43.684236 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9746 11:05:43.687151 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9747 11:05:43.693811 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9748 11:05:43.697607 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9749 11:05:43.703913 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9750 11:05:43.707058 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9751 11:05:43.710378 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9752 11:05:43.716889 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9753 11:05:43.720293 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9754 11:05:43.727090 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9755 11:05:43.729945 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9756 11:05:43.737055 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9757 11:05:43.740106 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9758 11:05:43.743526 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9759 11:05:43.750104 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9760 11:05:43.753721 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9761 11:05:43.760071 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9762 11:05:43.763649 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9763 11:05:43.769774 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9764 11:05:43.773289 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9765 11:05:43.776396 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9766 11:05:43.783068 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9767 11:05:43.785999 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9768 11:05:43.792599 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9769 11:05:43.796283 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9770 11:05:43.802449 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9771 11:05:43.806190 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9772 11:05:43.809442 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9773 11:05:43.816039 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9774 11:05:43.819565 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9775 11:05:43.825850 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9776 11:05:43.829462 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9777 11:05:43.832735 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9778 11:05:43.839169 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9779 11:05:43.842082 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9780 11:05:43.845975 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9781 11:05:43.852612 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9782 11:05:43.855586 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9783 11:05:43.859201 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9784 11:05:43.862042 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9785 11:05:43.868856 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9786 11:05:43.871859 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9787 11:05:43.878614 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9788 11:05:43.882252 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9789 11:05:43.885238 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9790 11:05:43.891876 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9791 11:05:43.895269 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9792 11:05:43.898492 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9793 11:05:43.904777 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9794 11:05:43.908780 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9795 11:05:43.915087 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9796 11:05:43.918394 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9797 11:05:43.921740 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9798 11:05:43.928000 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9799 11:05:43.931774 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9800 11:05:43.934535 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9801 11:05:43.941216 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9802 11:05:43.944832 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9803 11:05:43.948201 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9804 11:05:43.954756 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9805 11:05:43.957895 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9806 11:05:43.964474 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9807 11:05:43.968129 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9808 11:05:43.971478 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9809 11:05:43.977556 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9810 11:05:43.981310 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9811 11:05:43.987427 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9812 11:05:43.990815 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9813 11:05:43.994481 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9814 11:05:44.000920 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9815 11:05:44.004006 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9816 11:05:44.007349 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9817 11:05:44.013642 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9818 11:05:44.017202 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9819 11:05:44.020368 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9820 11:05:44.026928 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9821 11:05:44.030435 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9822 11:05:44.034064 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9823 11:05:44.037150 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9824 11:05:44.040518 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9825 11:05:44.046806 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9826 11:05:44.050757 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9827 11:05:44.053524 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9828 11:05:44.060075 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9829 11:05:44.063551 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9830 11:05:44.066703 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9831 11:05:44.070299 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9832 11:05:44.076258 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9833 11:05:44.079613 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9834 11:05:44.086686 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9835 11:05:44.089866 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9836 11:05:44.096291 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9837 11:05:44.099876 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9838 11:05:44.102738 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9839 11:05:44.109494 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9840 11:05:44.112773 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9841 11:05:44.119243 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9842 11:05:44.122693 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9843 11:05:44.129367 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9844 11:05:44.132277 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9845 11:05:44.135628 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9846 11:05:44.142502 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9847 11:05:44.145362 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9848 11:05:44.152186 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9849 11:05:44.155419 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9850 11:05:44.159244 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9851 11:05:44.165818 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9852 11:05:44.169035 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9853 11:05:44.175392 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9854 11:05:44.178502 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9855 11:05:44.182095 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9856 11:05:44.188719 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9857 11:05:44.191790 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9858 11:05:44.198325 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9859 11:05:44.201525 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9860 11:05:44.208148 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9861 11:05:44.211693 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9862 11:05:44.218342 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9863 11:05:44.221804 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9864 11:05:44.224875 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9865 11:05:44.231349 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9866 11:05:44.234826 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9867 11:05:44.241342 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9868 11:05:44.244828 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9869 11:05:44.247852 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9870 11:05:44.254687 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9871 11:05:44.257672 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9872 11:05:44.264217 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9873 11:05:44.267603 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9874 11:05:44.273918 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9875 11:05:44.277514 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9876 11:05:44.280640 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9877 11:05:44.287074 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9878 11:05:44.290630 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9879 11:05:44.297038 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9880 11:05:44.300431 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9881 11:05:44.303853 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9882 11:05:44.310335 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9883 11:05:44.314034 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9884 11:05:44.320047 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9885 11:05:44.323424 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9886 11:05:44.329979 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9887 11:05:44.333765 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9888 11:05:44.336591 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9889 11:05:44.343308 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9890 11:05:44.346772 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9891 11:05:44.353657 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9892 11:05:44.356292 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9893 11:05:44.359795 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9894 11:05:44.366588 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9895 11:05:44.369663 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9896 11:05:44.376269 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9897 11:05:44.379646 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9898 11:05:44.386246 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9899 11:05:44.389131 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9900 11:05:44.392750 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9901 11:05:44.399492 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9902 11:05:44.402436 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9903 11:05:44.408887 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9904 11:05:44.412073 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9905 11:05:44.419097 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9906 11:05:44.422194 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9907 11:05:44.428733 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9908 11:05:44.431726 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9909 11:05:44.435388 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9910 11:05:44.441845 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9911 11:05:44.445183 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9912 11:05:44.451745 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9913 11:05:44.455218 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9914 11:05:44.461968 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9915 11:05:44.464952 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9916 11:05:44.471332 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9917 11:05:44.474979 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9918 11:05:44.478117 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9919 11:05:44.484607 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9920 11:05:44.488148 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9921 11:05:44.494507 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9922 11:05:44.497908 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9923 11:05:44.504510 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9924 11:05:44.508035 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9925 11:05:44.514501 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9926 11:05:44.517263 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9927 11:05:44.520761 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9928 11:05:44.527170 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9929 11:05:44.530890 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9930 11:05:44.537288 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9931 11:05:44.540971 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9932 11:05:44.547390 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9933 11:05:44.551138 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9934 11:05:44.557026 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9935 11:05:44.560705 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9936 11:05:44.563790 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9937 11:05:44.570237 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9938 11:05:44.573255 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9939 11:05:44.580027 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9940 11:05:44.583088 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9941 11:05:44.589886 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9942 11:05:44.593408 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9943 11:05:44.596548 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9944 11:05:44.603026 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9945 11:05:44.606650 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9946 11:05:44.613153 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9947 11:05:44.616243 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9948 11:05:44.623292 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9949 11:05:44.626273 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9950 11:05:44.632638 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9951 11:05:44.636195 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9952 11:05:44.639453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9953 11:05:44.645945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9954 11:05:44.649066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9955 11:05:44.656057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9956 11:05:44.659164 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9957 11:05:44.665959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9958 11:05:44.669107 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9959 11:05:44.675771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9960 11:05:44.679332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9961 11:05:44.685730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9962 11:05:44.689132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9963 11:05:44.695313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9964 11:05:44.698866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9965 11:05:44.705154 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9966 11:05:44.708365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9967 11:05:44.715381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9968 11:05:44.718668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9969 11:05:44.725197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9970 11:05:44.728269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9971 11:05:44.735063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9972 11:05:44.738673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9973 11:05:44.745113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9974 11:05:44.748080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9975 11:05:44.754465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9976 11:05:44.758079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9977 11:05:44.764443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9978 11:05:44.768175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9979 11:05:44.774708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9980 11:05:44.778154 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9981 11:05:44.784725 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9982 11:05:44.788026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9983 11:05:44.794331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9984 11:05:44.797558 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9985 11:05:44.800693 INFO: [APUAPC] vio 0
9986 11:05:44.804139 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9987 11:05:44.811229 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9988 11:05:44.813918 INFO: [APUAPC] D0_APC_0: 0x400510
9989 11:05:44.817650 INFO: [APUAPC] D0_APC_1: 0x0
9990 11:05:44.817732 INFO: [APUAPC] D0_APC_2: 0x1540
9991 11:05:44.820722 INFO: [APUAPC] D0_APC_3: 0x0
9992 11:05:44.824029 INFO: [APUAPC] D1_APC_0: 0xffffffff
9993 11:05:44.826990 INFO: [APUAPC] D1_APC_1: 0xffffffff
9994 11:05:44.830847 INFO: [APUAPC] D1_APC_2: 0x3fffff
9995 11:05:44.833830 INFO: [APUAPC] D1_APC_3: 0x0
9996 11:05:44.837469 INFO: [APUAPC] D2_APC_0: 0xffffffff
9997 11:05:44.840490 INFO: [APUAPC] D2_APC_1: 0xffffffff
9998 11:05:44.843504 INFO: [APUAPC] D2_APC_2: 0x3fffff
9999 11:05:44.847243 INFO: [APUAPC] D2_APC_3: 0x0
10000 11:05:44.850618 INFO: [APUAPC] D3_APC_0: 0xffffffff
10001 11:05:44.853398 INFO: [APUAPC] D3_APC_1: 0xffffffff
10002 11:05:44.857232 INFO: [APUAPC] D3_APC_2: 0x3fffff
10003 11:05:44.860214 INFO: [APUAPC] D3_APC_3: 0x0
10004 11:05:44.863289 INFO: [APUAPC] D4_APC_0: 0xffffffff
10005 11:05:44.866842 INFO: [APUAPC] D4_APC_1: 0xffffffff
10006 11:05:44.870192 INFO: [APUAPC] D4_APC_2: 0x3fffff
10007 11:05:44.873535 INFO: [APUAPC] D4_APC_3: 0x0
10008 11:05:44.876698 INFO: [APUAPC] D5_APC_0: 0xffffffff
10009 11:05:44.880251 INFO: [APUAPC] D5_APC_1: 0xffffffff
10010 11:05:44.883380 INFO: [APUAPC] D5_APC_2: 0x3fffff
10011 11:05:44.886499 INFO: [APUAPC] D5_APC_3: 0x0
10012 11:05:44.889756 INFO: [APUAPC] D6_APC_0: 0xffffffff
10013 11:05:44.892699 INFO: [APUAPC] D6_APC_1: 0xffffffff
10014 11:05:44.896702 INFO: [APUAPC] D6_APC_2: 0x3fffff
10015 11:05:44.899571 INFO: [APUAPC] D6_APC_3: 0x0
10016 11:05:44.902925 INFO: [APUAPC] D7_APC_0: 0xffffffff
10017 11:05:44.906334 INFO: [APUAPC] D7_APC_1: 0xffffffff
10018 11:05:44.909527 INFO: [APUAPC] D7_APC_2: 0x3fffff
10019 11:05:44.913235 INFO: [APUAPC] D7_APC_3: 0x0
10020 11:05:44.915945 INFO: [APUAPC] D8_APC_0: 0xffffffff
10021 11:05:44.919421 INFO: [APUAPC] D8_APC_1: 0xffffffff
10022 11:05:44.922623 INFO: [APUAPC] D8_APC_2: 0x3fffff
10023 11:05:44.925893 INFO: [APUAPC] D8_APC_3: 0x0
10024 11:05:44.929550 INFO: [APUAPC] D9_APC_0: 0xffffffff
10025 11:05:44.932899 INFO: [APUAPC] D9_APC_1: 0xffffffff
10026 11:05:44.935653 INFO: [APUAPC] D9_APC_2: 0x3fffff
10027 11:05:44.939288 INFO: [APUAPC] D9_APC_3: 0x0
10028 11:05:44.942497 INFO: [APUAPC] D10_APC_0: 0xffffffff
10029 11:05:44.945943 INFO: [APUAPC] D10_APC_1: 0xffffffff
10030 11:05:44.948894 INFO: [APUAPC] D10_APC_2: 0x3fffff
10031 11:05:44.952358 INFO: [APUAPC] D10_APC_3: 0x0
10032 11:05:44.955808 INFO: [APUAPC] D11_APC_0: 0xffffffff
10033 11:05:44.958853 INFO: [APUAPC] D11_APC_1: 0xffffffff
10034 11:05:44.962480 INFO: [APUAPC] D11_APC_2: 0x3fffff
10035 11:05:44.965420 INFO: [APUAPC] D11_APC_3: 0x0
10036 11:05:44.969074 INFO: [APUAPC] D12_APC_0: 0xffffffff
10037 11:05:44.972014 INFO: [APUAPC] D12_APC_1: 0xffffffff
10038 11:05:44.975792 INFO: [APUAPC] D12_APC_2: 0x3fffff
10039 11:05:44.978572 INFO: [APUAPC] D12_APC_3: 0x0
10040 11:05:44.982086 INFO: [APUAPC] D13_APC_0: 0xffffffff
10041 11:05:44.985617 INFO: [APUAPC] D13_APC_1: 0xffffffff
10042 11:05:44.989070 INFO: [APUAPC] D13_APC_2: 0x3fffff
10043 11:05:44.991925 INFO: [APUAPC] D13_APC_3: 0x0
10044 11:05:44.995289 INFO: [APUAPC] D14_APC_0: 0xffffffff
10045 11:05:44.999208 INFO: [APUAPC] D14_APC_1: 0xffffffff
10046 11:05:45.002315 INFO: [APUAPC] D14_APC_2: 0x3fffff
10047 11:05:45.005176 INFO: [APUAPC] D14_APC_3: 0x0
10048 11:05:45.008690 INFO: [APUAPC] D15_APC_0: 0xffffffff
10049 11:05:45.011847 INFO: [APUAPC] D15_APC_1: 0xffffffff
10050 11:05:45.015425 INFO: [APUAPC] D15_APC_2: 0x3fffff
10051 11:05:45.018775 INFO: [APUAPC] D15_APC_3: 0x0
10052 11:05:45.022298 INFO: [APUAPC] APC_CON: 0x4
10053 11:05:45.025139 INFO: [NOCDAPC] D0_APC_0: 0x0
10054 11:05:45.028468 INFO: [NOCDAPC] D0_APC_1: 0x0
10055 11:05:45.031591 INFO: [NOCDAPC] D1_APC_0: 0x0
10056 11:05:45.035206 INFO: [NOCDAPC] D1_APC_1: 0xfff
10057 11:05:45.035294 INFO: [NOCDAPC] D2_APC_0: 0x0
10058 11:05:45.038665 INFO: [NOCDAPC] D2_APC_1: 0xfff
10059 11:05:45.041455 INFO: [NOCDAPC] D3_APC_0: 0x0
10060 11:05:45.044918 INFO: [NOCDAPC] D3_APC_1: 0xfff
10061 11:05:45.048234 INFO: [NOCDAPC] D4_APC_0: 0x0
10062 11:05:45.051259 INFO: [NOCDAPC] D4_APC_1: 0xfff
10063 11:05:45.054530 INFO: [NOCDAPC] D5_APC_0: 0x0
10064 11:05:45.058030 INFO: [NOCDAPC] D5_APC_1: 0xfff
10065 11:05:45.060990 INFO: [NOCDAPC] D6_APC_0: 0x0
10066 11:05:45.064646 INFO: [NOCDAPC] D6_APC_1: 0xfff
10067 11:05:45.067657 INFO: [NOCDAPC] D7_APC_0: 0x0
10068 11:05:45.071284 INFO: [NOCDAPC] D7_APC_1: 0xfff
10069 11:05:45.071415 INFO: [NOCDAPC] D8_APC_0: 0x0
10070 11:05:45.074221 INFO: [NOCDAPC] D8_APC_1: 0xfff
10071 11:05:45.077661 INFO: [NOCDAPC] D9_APC_0: 0x0
10072 11:05:45.081450 INFO: [NOCDAPC] D9_APC_1: 0xfff
10073 11:05:45.084477 INFO: [NOCDAPC] D10_APC_0: 0x0
10074 11:05:45.087451 INFO: [NOCDAPC] D10_APC_1: 0xfff
10075 11:05:45.090875 INFO: [NOCDAPC] D11_APC_0: 0x0
10076 11:05:45.094370 INFO: [NOCDAPC] D11_APC_1: 0xfff
10077 11:05:45.097297 INFO: [NOCDAPC] D12_APC_0: 0x0
10078 11:05:45.100822 INFO: [NOCDAPC] D12_APC_1: 0xfff
10079 11:05:45.103875 INFO: [NOCDAPC] D13_APC_0: 0x0
10080 11:05:45.107508 INFO: [NOCDAPC] D13_APC_1: 0xfff
10081 11:05:45.110407 INFO: [NOCDAPC] D14_APC_0: 0x0
10082 11:05:45.113923 INFO: [NOCDAPC] D14_APC_1: 0xfff
10083 11:05:45.117029 INFO: [NOCDAPC] D15_APC_0: 0x0
10084 11:05:45.120724 INFO: [NOCDAPC] D15_APC_1: 0xfff
10085 11:05:45.120806 INFO: [NOCDAPC] APC_CON: 0x4
10086 11:05:45.123579 INFO: [APUAPC] set_apusys_apc done
10087 11:05:45.127137 INFO: [DEVAPC] devapc_init done
10088 11:05:45.133573 INFO: GICv3 without legacy support detected.
10089 11:05:45.136843 INFO: ARM GICv3 driver initialized in EL3
10090 11:05:45.140244 INFO: Maximum SPI INTID supported: 639
10091 11:05:45.143608 INFO: BL31: Initializing runtime services
10092 11:05:45.149996 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10093 11:05:45.153508 INFO: SPM: enable CPC mode
10094 11:05:45.156575 INFO: mcdi ready for mcusys-off-idle and system suspend
10095 11:05:45.163161 INFO: BL31: Preparing for EL3 exit to normal world
10096 11:05:45.167113 INFO: Entry point address = 0x80000000
10097 11:05:45.167198 INFO: SPSR = 0x8
10098 11:05:45.173778
10099 11:05:45.173863
10100 11:05:45.173950
10101 11:05:45.177296 Starting depthcharge on Spherion...
10102 11:05:45.177381
10103 11:05:45.177468 Wipe memory regions:
10104 11:05:45.177549
10105 11:05:45.178411 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10106 11:05:45.178527 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10107 11:05:45.178620 Setting prompt string to ['asurada:']
10108 11:05:45.178718 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10109 11:05:45.180448 [0x00000040000000, 0x00000054600000)
10110 11:05:45.302909
10111 11:05:45.303064 [0x00000054660000, 0x00000080000000)
10112 11:05:45.563680
10113 11:05:45.563851 [0x000000821a7280, 0x000000ffe64000)
10114 11:05:46.308629
10115 11:05:46.308764 [0x00000100000000, 0x00000240000000)
10116 11:05:48.199143
10117 11:05:48.202465 Initializing XHCI USB controller at 0x11200000.
10118 11:05:49.240330
10119 11:05:49.243687 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10120 11:05:49.243825
10121 11:05:49.243926
10122 11:05:49.244015
10123 11:05:49.244351 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10125 11:05:49.344741 asurada: tftpboot 192.168.201.1 12925635/tftp-deploy-3ozrlg70/kernel/image.itb 12925635/tftp-deploy-3ozrlg70/kernel/cmdline
10126 11:05:49.344880 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10127 11:05:49.344968 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10128 11:05:49.348975 tftpboot 192.168.201.1 12925635/tftp-deploy-3ozrlg70/kernel/image.itp-deploy-3ozrlg70/kernel/cmdline
10129 11:05:49.349080
10130 11:05:49.349210 Waiting for link
10131 11:05:49.509885
10132 11:05:49.510021 R8152: Initializing
10133 11:05:49.510095
10134 11:05:49.512981 Version 6 (ocp_data = 5c30)
10135 11:05:49.513063
10136 11:05:49.516011 R8152: Done initializing
10137 11:05:49.516098
10138 11:05:49.516163 Adding net device
10139 11:05:51.419058
10140 11:05:51.419208 done.
10141 11:05:51.419276
10142 11:05:51.419337 MAC: 00:e0:4c:68:02:81
10143 11:05:51.419397
10144 11:05:51.422609 Sending DHCP discover... done.
10145 11:05:51.422711
10146 11:05:51.425916 Waiting for reply... done.
10147 11:05:51.426016
10148 11:05:51.429772 Sending DHCP request... done.
10149 11:05:51.429873
10150 11:05:51.434017 Waiting for reply... done.
10151 11:05:51.434099
10152 11:05:51.434165 My ip is 192.168.201.14
10153 11:05:51.434225
10154 11:05:51.437019 The DHCP server ip is 192.168.201.1
10155 11:05:51.437136
10156 11:05:51.443552 TFTP server IP predefined by user: 192.168.201.1
10157 11:05:51.443638
10158 11:05:51.450193 Bootfile predefined by user: 12925635/tftp-deploy-3ozrlg70/kernel/image.itb
10159 11:05:51.450304
10160 11:05:51.453199 Sending tftp read request... done.
10161 11:05:51.453315
10162 11:05:51.457278 Waiting for the transfer...
10163 11:05:51.457394
10164 11:05:51.982403 00000000 ################################################################
10165 11:05:51.982557
10166 11:05:52.504000 00080000 ################################################################
10167 11:05:52.504183
10168 11:05:53.031865 00100000 ################################################################
10169 11:05:53.032003
10170 11:05:53.552389 00180000 ################################################################
10171 11:05:53.552551
10172 11:05:54.089128 00200000 ################################################################
10173 11:05:54.089268
10174 11:05:54.615625 00280000 ################################################################
10175 11:05:54.615831
10176 11:05:55.158723 00300000 ################################################################
10177 11:05:55.158861
10178 11:05:55.693597 00380000 ################################################################
10179 11:05:55.693756
10180 11:05:56.231474 00400000 ################################################################
10181 11:05:56.231609
10182 11:05:56.762637 00480000 ################################################################
10183 11:05:56.762774
10184 11:05:57.277150 00500000 ################################################################
10185 11:05:57.277300
10186 11:05:57.811441 00580000 ################################################################
10187 11:05:57.811621
10188 11:05:58.347546 00600000 ################################################################
10189 11:05:58.347750
10190 11:05:58.870812 00680000 ################################################################
10191 11:05:58.870942
10192 11:05:59.435838 00700000 ################################################################
10193 11:05:59.436421
10194 11:06:00.102856 00780000 ################################################################
10195 11:06:00.103377
10196 11:06:00.798716 00800000 ################################################################
10197 11:06:00.799282
10198 11:06:01.479624 00880000 ################################################################
10199 11:06:01.480143
10200 11:06:02.027180 00900000 ################################################################
10201 11:06:02.027336
10202 11:06:02.567204 00980000 ################################################################
10203 11:06:02.567344
10204 11:06:03.119613 00a00000 ################################################################
10205 11:06:03.119789
10206 11:06:03.673163 00a80000 ################################################################
10207 11:06:03.673302
10208 11:06:04.247574 00b00000 ################################################################
10209 11:06:04.247751
10210 11:06:04.790378 00b80000 ################################################################
10211 11:06:04.790512
10212 11:06:05.434485 00c00000 ################################################################
10213 11:06:05.435026
10214 11:06:06.069356 00c80000 ################################################################
10215 11:06:06.069494
10216 11:06:06.670643 00d00000 ################################################################
10217 11:06:06.670811
10218 11:06:07.254488 00d80000 ################################################################
10219 11:06:07.254640
10220 11:06:07.923059 00e00000 ################################################################
10221 11:06:07.923595
10222 11:06:08.587696 00e80000 ################################################################
10223 11:06:08.588283
10224 11:06:09.263597 00f00000 ################################################################
10225 11:06:09.264239
10226 11:06:09.950358 00f80000 ################################################################
10227 11:06:09.950970
10228 11:06:10.621085 01000000 ################################################################
10229 11:06:10.621598
10230 11:06:11.302792 01080000 ################################################################
10231 11:06:11.303288
10232 11:06:11.967464 01100000 ################################################################
10233 11:06:11.967612
10234 11:06:12.549393 01180000 ################################################################
10235 11:06:12.549542
10236 11:06:13.215091 01200000 ################################################################
10237 11:06:13.215598
10238 11:06:13.881776 01280000 ################################################################
10239 11:06:13.882314
10240 11:06:14.530992 01300000 ################################################################
10241 11:06:14.531573
10242 11:06:15.087347 01380000 ################################################################
10243 11:06:15.087512
10244 11:06:15.676956 01400000 ################################################################
10245 11:06:15.677621
10246 11:06:16.334962 01480000 ################################################################
10247 11:06:16.335655
10248 11:06:16.919878 01500000 ################################################################
10249 11:06:16.920009
10250 11:06:17.498234 01580000 ################################################################
10251 11:06:17.498394
10252 11:06:18.065770 01600000 ################################################################
10253 11:06:18.065932
10254 11:06:18.629792 01680000 ################################################################
10255 11:06:18.629961
10256 11:06:19.168133 01700000 ################################################################
10257 11:06:19.168293
10258 11:06:19.728425 01780000 ################################################################
10259 11:06:19.728557
10260 11:06:20.281917 01800000 ################################################################
10261 11:06:20.282086
10262 11:06:20.854523 01880000 ################################################################
10263 11:06:20.854698
10264 11:06:21.391913 01900000 ################################################################
10265 11:06:21.392050
10266 11:06:21.943376 01980000 ################################################################
10267 11:06:21.943522
10268 11:06:22.508314 01a00000 ################################################################
10269 11:06:22.508459
10270 11:06:23.069279 01a80000 ################################################################
10271 11:06:23.069416
10272 11:06:23.622229 01b00000 ################################################################
10273 11:06:23.622366
10274 11:06:24.203977 01b80000 ################################################################
10275 11:06:24.204146
10276 11:06:24.759858 01c00000 ################################################################
10277 11:06:24.760007
10278 11:06:25.394218 01c80000 ################################################################
10279 11:06:25.394386
10280 11:06:26.086308 01d00000 ################################################################
10281 11:06:26.086453
10282 11:06:26.733345 01d80000 ################################################################
10283 11:06:26.733842
10284 11:06:27.312701 01e00000 ################################################################
10285 11:06:27.312863
10286 11:06:27.881006 01e80000 ################################################################
10287 11:06:27.881138
10288 11:06:28.452177 01f00000 ################################################################
10289 11:06:28.452318
10290 11:06:29.015526 01f80000 ############################################################ done.
10291 11:06:29.015677
10292 11:06:29.018725 The bootfile was 33518974 bytes long.
10293 11:06:29.018836
10294 11:06:29.021875 Sending tftp read request... done.
10295 11:06:29.021960
10296 11:06:29.022026 Waiting for the transfer...
10297 11:06:29.022088
10298 11:06:29.025486 00000000 # done.
10299 11:06:29.025577
10300 11:06:29.031964 Command line loaded dynamically from TFTP file: 12925635/tftp-deploy-3ozrlg70/kernel/cmdline
10301 11:06:29.032060
10302 11:06:29.045063 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10303 11:06:29.045267
10304 11:06:29.048749 Loading FIT.
10305 11:06:29.048953
10306 11:06:29.051545 Image ramdisk-1 has 21411961 bytes.
10307 11:06:29.051700
10308 11:06:29.055103 Image fdt-1 has 47278 bytes.
10309 11:06:29.055277
10310 11:06:29.058496 Image kernel-1 has 12057697 bytes.
10311 11:06:29.058742
10312 11:06:29.064930 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10313 11:06:29.065224
10314 11:06:29.085295 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10315 11:06:29.085819
10316 11:06:29.088222 Choosing best match conf-1 for compat google,spherion-rev2.
10317 11:06:29.092848
10318 11:06:29.097134 Connected to device vid:did:rid of 1ae0:0028:00
10319 11:06:29.104128
10320 11:06:29.107888 tpm_get_response: command 0x17b, return code 0x0
10321 11:06:29.108843
10322 11:06:29.111232 ec_init: CrosEC protocol v3 supported (256, 248)
10323 11:06:29.116089
10324 11:06:29.118061 tpm_cleanup: add release locality here.
10325 11:06:29.118483
10326 11:06:29.118818 Shutting down all USB controllers.
10327 11:06:29.121564
10328 11:06:29.121985 Removing current net device
10329 11:06:29.122324
10330 11:06:29.127947 Exiting depthcharge with code 4 at timestamp: 73454160
10331 11:06:29.128371
10332 11:06:29.131302 LZMA decompressing kernel-1 to 0x821a6718
10333 11:06:29.131755
10334 11:06:29.134777 LZMA decompressing kernel-1 to 0x40000000
10335 11:06:30.636051
10336 11:06:30.636642 jumping to kernel
10337 11:06:30.638370 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10338 11:06:30.638941 start: 2.2.5 auto-login-action (timeout 00:03:40) [common]
10339 11:06:30.639443 Setting prompt string to ['Linux version [0-9]']
10340 11:06:30.639851 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10341 11:06:30.640266 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10342 11:06:30.717771
10343 11:06:30.721772 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10344 11:06:30.725009 start: 2.2.5.1 login-action (timeout 00:03:39) [common]
10345 11:06:30.725493 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10346 11:06:30.725878 Setting prompt string to []
10347 11:06:30.726614 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10348 11:06:30.727086 Using line separator: #'\n'#
10349 11:06:30.727407 No login prompt set.
10350 11:06:30.727760 Parsing kernel messages
10351 11:06:30.728061 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10352 11:06:30.728583 [login-action] Waiting for messages, (timeout 00:03:39)
10353 11:06:30.728911 Waiting using forced prompt support (timeout 00:01:50)
10354 11:06:30.743939 [ 0.000000] Linux version 6.1.80-cip16 (KernelCI@build-j128891-arm64-gcc-10-defconfig-arm64-chromebook-nrg4h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024
10355 11:06:30.747227 [ 0.000000] random: crng init done
10356 11:06:30.753995 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10357 11:06:30.756834 [ 0.000000] efi: UEFI not found.
10358 11:06:30.763428 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10359 11:06:30.773735 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10360 11:06:30.783531 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10361 11:06:30.790484 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10362 11:06:30.796363 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10363 11:06:30.802743 [ 0.000000] printk: bootconsole [mtk8250] enabled
10364 11:06:30.809577 [ 0.000000] NUMA: No NUMA configuration found
10365 11:06:30.816090 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10366 11:06:30.822821 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10367 11:06:30.823247 [ 0.000000] Zone ranges:
10368 11:06:30.829371 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10369 11:06:30.832653 [ 0.000000] DMA32 empty
10370 11:06:30.839553 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10371 11:06:30.842819 [ 0.000000] Movable zone start for each node
10372 11:06:30.845800 [ 0.000000] Early memory node ranges
10373 11:06:30.851958 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10374 11:06:30.858677 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10375 11:06:30.865102 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10376 11:06:30.872112 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10377 11:06:30.878551 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10378 11:06:30.885293 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10379 11:06:30.942645 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10380 11:06:30.949055 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10381 11:06:30.955488 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10382 11:06:30.959181 [ 0.000000] psci: probing for conduit method from DT.
10383 11:06:30.965812 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10384 11:06:30.968570 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10385 11:06:30.975244 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10386 11:06:30.978653 [ 0.000000] psci: SMC Calling Convention v1.2
10387 11:06:30.985347 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10388 11:06:30.988790 [ 0.000000] Detected VIPT I-cache on CPU0
10389 11:06:30.995978 [ 0.000000] CPU features: detected: GIC system register CPU interface
10390 11:06:31.002107 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10391 11:06:31.008401 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10392 11:06:31.015081 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10393 11:06:31.024472 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10394 11:06:31.031348 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10395 11:06:31.034763 [ 0.000000] alternatives: applying boot alternatives
10396 11:06:31.041286 [ 0.000000] Fallback order for Node 0: 0
10397 11:06:31.047953 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10398 11:06:31.051593 [ 0.000000] Policy zone: Normal
10399 11:06:31.064450 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10400 11:06:31.074188 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10401 11:06:31.086834 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10402 11:06:31.096600 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10403 11:06:31.103408 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10404 11:06:31.106479 <6>[ 0.000000] software IO TLB: area num 8.
10405 11:06:31.164148 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10406 11:06:31.312689 <6>[ 0.000000] Memory: 7946284K/8385536K available (18048K kernel code, 4118K rwdata, 19616K rodata, 8448K init, 616K bss, 406484K reserved, 32768K cma-reserved)
10407 11:06:31.319422 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10408 11:06:31.326145 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10409 11:06:31.329312 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10410 11:06:31.335841 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10411 11:06:31.342991 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10412 11:06:31.349399 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10413 11:06:31.355489 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10414 11:06:31.362321 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10415 11:06:31.369019 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10416 11:06:31.375348 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10417 11:06:31.378524 <6>[ 0.000000] GICv3: 608 SPIs implemented
10418 11:06:31.381874 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10419 11:06:31.388547 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10420 11:06:31.391829 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10421 11:06:31.398555 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10422 11:06:31.411816 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10423 11:06:31.424858 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10424 11:06:31.431371 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10425 11:06:31.439615 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10426 11:06:31.452830 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10427 11:06:31.459586 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10428 11:06:31.466091 <6>[ 0.009230] Console: colour dummy device 80x25
10429 11:06:31.476193 <6>[ 0.013958] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10430 11:06:31.482853 <6>[ 0.024465] pid_max: default: 32768 minimum: 301
10431 11:06:31.485536 <6>[ 0.029336] LSM: Security Framework initializing
10432 11:06:31.492830 <6>[ 0.034276] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10433 11:06:31.502506 <6>[ 0.042089] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10434 11:06:31.512292 <6>[ 0.051390] cblist_init_generic: Setting adjustable number of callback queues.
10435 11:06:31.516107 <6>[ 0.058833] cblist_init_generic: Setting shift to 3 and lim to 1.
10436 11:06:31.525642 <6>[ 0.065172] cblist_init_generic: Setting adjustable number of callback queues.
10437 11:06:31.531775 <6>[ 0.072646] cblist_init_generic: Setting shift to 3 and lim to 1.
10438 11:06:31.535248 <6>[ 0.079046] rcu: Hierarchical SRCU implementation.
10439 11:06:31.542365 <6>[ 0.084061] rcu: Max phase no-delay instances is 1000.
10440 11:06:31.548527 <6>[ 0.091124] EFI services will not be available.
10441 11:06:31.551459 <6>[ 0.096079] smp: Bringing up secondary CPUs ...
10442 11:06:31.560849 <6>[ 0.101122] Detected VIPT I-cache on CPU1
10443 11:06:31.567090 <6>[ 0.101190] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10444 11:06:31.573504 <6>[ 0.101222] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10445 11:06:31.576916 <6>[ 0.101559] Detected VIPT I-cache on CPU2
10446 11:06:31.586526 <6>[ 0.101607] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10447 11:06:31.592929 <6>[ 0.101624] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10448 11:06:31.596433 <6>[ 0.101880] Detected VIPT I-cache on CPU3
10449 11:06:31.603088 <6>[ 0.101927] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10450 11:06:31.609528 <6>[ 0.101940] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10451 11:06:31.616071 <6>[ 0.102244] CPU features: detected: Spectre-v4
10452 11:06:31.619447 <6>[ 0.102250] CPU features: detected: Spectre-BHB
10453 11:06:31.622935 <6>[ 0.102255] Detected PIPT I-cache on CPU4
10454 11:06:31.629866 <6>[ 0.102313] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10455 11:06:31.639801 <6>[ 0.102330] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10456 11:06:31.642431 <6>[ 0.102623] Detected PIPT I-cache on CPU5
10457 11:06:31.648954 <6>[ 0.102684] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10458 11:06:31.655547 <6>[ 0.102701] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10459 11:06:31.659070 <6>[ 0.102985] Detected PIPT I-cache on CPU6
10460 11:06:31.670128 <6>[ 0.103050] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10461 11:06:31.675528 <6>[ 0.103066] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10462 11:06:31.678898 <6>[ 0.103365] Detected PIPT I-cache on CPU7
10463 11:06:31.685275 <6>[ 0.103430] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10464 11:06:31.692494 <6>[ 0.103446] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10465 11:06:31.695357 <6>[ 0.103493] smp: Brought up 1 node, 8 CPUs
10466 11:06:31.702333 <6>[ 0.244839] SMP: Total of 8 processors activated.
10467 11:06:31.708216 <6>[ 0.249791] CPU features: detected: 32-bit EL0 Support
10468 11:06:31.714984 <6>[ 0.255154] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10469 11:06:31.721345 <6>[ 0.263954] CPU features: detected: Common not Private translations
10470 11:06:31.728223 <6>[ 0.270470] CPU features: detected: CRC32 instructions
10471 11:06:31.734618 <6>[ 0.275822] CPU features: detected: RCpc load-acquire (LDAPR)
10472 11:06:31.738398 <6>[ 0.281782] CPU features: detected: LSE atomic instructions
10473 11:06:31.744463 <6>[ 0.287564] CPU features: detected: Privileged Access Never
10474 11:06:31.751540 <6>[ 0.293343] CPU features: detected: RAS Extension Support
10475 11:06:31.757960 <6>[ 0.298986] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10476 11:06:31.761595 <6>[ 0.306205] CPU: All CPU(s) started at EL2
10477 11:06:31.767483 <6>[ 0.310522] alternatives: applying system-wide alternatives
10478 11:06:31.778085 <6>[ 0.321282] devtmpfs: initialized
10479 11:06:31.793623 <6>[ 0.330098] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10480 11:06:31.800142 <6>[ 0.340061] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10481 11:06:31.806484 <6>[ 0.348119] pinctrl core: initialized pinctrl subsystem
10482 11:06:31.809926 <6>[ 0.354782] DMI not present or invalid.
10483 11:06:31.816653 <6>[ 0.359192] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10484 11:06:31.826602 <6>[ 0.366048] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10485 11:06:31.833283 <6>[ 0.373636] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10486 11:06:31.842752 <6>[ 0.381856] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10487 11:06:31.846413 <6>[ 0.390099] audit: initializing netlink subsys (disabled)
10488 11:06:31.856018 <5>[ 0.395791] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10489 11:06:31.862472 <6>[ 0.396497] thermal_sys: Registered thermal governor 'step_wise'
10490 11:06:31.869161 <6>[ 0.403759] thermal_sys: Registered thermal governor 'power_allocator'
10491 11:06:31.872810 <6>[ 0.410015] cpuidle: using governor menu
10492 11:06:31.879353 <6>[ 0.420975] NET: Registered PF_QIPCRTR protocol family
10493 11:06:31.885494 <6>[ 0.426450] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10494 11:06:31.892025 <6>[ 0.433558] ASID allocator initialised with 32768 entries
10495 11:06:31.895310 <6>[ 0.440126] Serial: AMBA PL011 UART driver
10496 11:06:31.905261 <4>[ 0.448879] Trying to register duplicate clock ID: 134
10497 11:06:31.959454 <6>[ 0.506347] KASLR enabled
10498 11:06:31.974167 <6>[ 0.514011] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10499 11:06:31.980488 <6>[ 0.521024] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10500 11:06:31.987403 <6>[ 0.527513] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10501 11:06:31.994042 <6>[ 0.534519] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10502 11:06:32.000593 <6>[ 0.541007] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10503 11:06:32.006600 <6>[ 0.548012] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10504 11:06:32.013556 <6>[ 0.554496] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10505 11:06:32.020310 <6>[ 0.561498] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10506 11:06:32.023668 <6>[ 0.569016] ACPI: Interpreter disabled.
10507 11:06:32.032380 <6>[ 0.575425] iommu: Default domain type: Translated
10508 11:06:32.038897 <6>[ 0.580537] iommu: DMA domain TLB invalidation policy: strict mode
10509 11:06:32.042386 <5>[ 0.587200] SCSI subsystem initialized
10510 11:06:32.048550 <6>[ 0.591369] usbcore: registered new interface driver usbfs
10511 11:06:32.055756 <6>[ 0.597098] usbcore: registered new interface driver hub
10512 11:06:32.058475 <6>[ 0.602648] usbcore: registered new device driver usb
10513 11:06:32.065613 <6>[ 0.608747] pps_core: LinuxPPS API ver. 1 registered
10514 11:06:32.075701 <6>[ 0.613941] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10515 11:06:32.078877 <6>[ 0.623290] PTP clock support registered
10516 11:06:32.081894 <6>[ 0.627532] EDAC MC: Ver: 3.0.0
10517 11:06:32.089813 <6>[ 0.632692] FPGA manager framework
10518 11:06:32.095805 <6>[ 0.636373] Advanced Linux Sound Architecture Driver Initialized.
10519 11:06:32.099044 <6>[ 0.643152] vgaarb: loaded
10520 11:06:32.106057 <6>[ 0.646305] clocksource: Switched to clocksource arch_sys_counter
10521 11:06:32.109483 <5>[ 0.652750] VFS: Disk quotas dquot_6.6.0
10522 11:06:32.115572 <6>[ 0.656933] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10523 11:06:32.118865 <6>[ 0.664123] pnp: PnP ACPI: disabled
10524 11:06:32.127309 <6>[ 0.670688] NET: Registered PF_INET protocol family
10525 11:06:32.137395 <6>[ 0.676276] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10526 11:06:32.149284 <6>[ 0.688578] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10527 11:06:32.158479 <6>[ 0.697388] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10528 11:06:32.165438 <6>[ 0.705361] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10529 11:06:32.175352 <6>[ 0.714059] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10530 11:06:32.181839 <6>[ 0.723801] TCP: Hash tables configured (established 65536 bind 65536)
10531 11:06:32.188552 <6>[ 0.730663] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10532 11:06:32.198507 <6>[ 0.737862] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10533 11:06:32.204675 <6>[ 0.745564] NET: Registered PF_UNIX/PF_LOCAL protocol family
10534 11:06:32.211158 <6>[ 0.751735] RPC: Registered named UNIX socket transport module.
10535 11:06:32.214284 <6>[ 0.757889] RPC: Registered udp transport module.
10536 11:06:32.220975 <6>[ 0.762819] RPC: Registered tcp transport module.
10537 11:06:32.227245 <6>[ 0.767751] RPC: Registered tcp NFSv4.1 backchannel transport module.
10538 11:06:32.230790 <6>[ 0.774416] PCI: CLS 0 bytes, default 64
10539 11:06:32.234058 <6>[ 0.778788] Unpacking initramfs...
10540 11:06:32.259663 <6>[ 0.798939] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10541 11:06:32.268814 <6>[ 0.807601] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10542 11:06:32.272083 <6>[ 0.816478] kvm [1]: IPA Size Limit: 40 bits
10543 11:06:32.278643 <6>[ 0.821004] kvm [1]: GICv3: no GICV resource entry
10544 11:06:32.282183 <6>[ 0.826025] kvm [1]: disabling GICv2 emulation
10545 11:06:32.289284 <6>[ 0.830712] kvm [1]: GIC system register CPU interface enabled
10546 11:06:32.292692 <6>[ 0.836865] kvm [1]: vgic interrupt IRQ18
10547 11:06:32.298876 <6>[ 0.841221] kvm [1]: VHE mode initialized successfully
10548 11:06:32.305793 <5>[ 0.847701] Initialise system trusted keyrings
10549 11:06:32.312143 <6>[ 0.852499] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10550 11:06:32.319414 <6>[ 0.862542] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10551 11:06:32.326472 <5>[ 0.868923] NFS: Registering the id_resolver key type
10552 11:06:32.329282 <5>[ 0.874226] Key type id_resolver registered
10553 11:06:32.335767 <5>[ 0.878642] Key type id_legacy registered
10554 11:06:32.342771 <6>[ 0.882923] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10555 11:06:32.349251 <6>[ 0.889843] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10556 11:06:32.355628 <6>[ 0.897562] 9p: Installing v9fs 9p2000 file system support
10557 11:06:32.392887 <5>[ 0.935718] Key type asymmetric registered
10558 11:06:32.395523 <5>[ 0.940055] Asymmetric key parser 'x509' registered
10559 11:06:32.405630 <6>[ 0.945242] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10560 11:06:32.408720 <6>[ 0.952860] io scheduler mq-deadline registered
10561 11:06:32.412230 <6>[ 0.957632] io scheduler kyber registered
10562 11:06:32.432148 <6>[ 0.974778] EINJ: ACPI disabled.
10563 11:06:32.463862 <4>[ 1.000417] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10564 11:06:32.474275 <4>[ 1.011038] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10565 11:06:32.488283 <6>[ 1.031458] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10566 11:06:32.496111 <6>[ 1.039379] printk: console [ttyS0] disabled
10567 11:06:32.524156 <6>[ 1.064029] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10568 11:06:32.530737 <6>[ 1.073507] printk: console [ttyS0] enabled
10569 11:06:32.533708 <6>[ 1.073507] printk: console [ttyS0] enabled
10570 11:06:32.540748 <6>[ 1.082400] printk: bootconsole [mtk8250] disabled
10571 11:06:32.544083 <6>[ 1.082400] printk: bootconsole [mtk8250] disabled
10572 11:06:32.550649 <6>[ 1.093624] SuperH (H)SCI(F) driver initialized
10573 11:06:32.553617 <6>[ 1.098908] msm_serial: driver initialized
10574 11:06:32.568264 <6>[ 1.107851] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10575 11:06:32.578151 <6>[ 1.116399] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10576 11:06:32.584969 <6>[ 1.124941] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10577 11:06:32.594967 <6>[ 1.133569] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10578 11:06:32.604628 <6>[ 1.142275] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10579 11:06:32.611160 <6>[ 1.150988] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10580 11:06:32.621246 <6>[ 1.159530] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10581 11:06:32.627814 <6>[ 1.168342] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10582 11:06:32.636890 <6>[ 1.176884] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10583 11:06:32.649391 <6>[ 1.192370] loop: module loaded
10584 11:06:32.656208 <6>[ 1.198508] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10585 11:06:32.678650 <4>[ 1.222101] mtk-pmic-keys: Failed to locate of_node [id: -1]
10586 11:06:32.686363 <6>[ 1.229144] megasas: 07.719.03.00-rc1
10587 11:06:32.695810 <6>[ 1.238952] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10588 11:06:32.702460 <6>[ 1.245726] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10589 11:06:32.719074 <6>[ 1.262136] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10590 11:06:32.779204 <6>[ 1.315841] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10591 11:06:33.160085 <6>[ 1.703515] Freeing initrd memory: 20908K
10592 11:06:33.176295 <6>[ 1.719342] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10593 11:06:33.187128 <6>[ 1.730189] tun: Universal TUN/TAP device driver, 1.6
10594 11:06:33.190639 <6>[ 1.736249] thunder_xcv, ver 1.0
10595 11:06:33.193773 <6>[ 1.739752] thunder_bgx, ver 1.0
10596 11:06:33.197053 <6>[ 1.743244] nicpf, ver 1.0
10597 11:06:33.206959 <6>[ 1.747253] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10598 11:06:33.210285 <6>[ 1.754729] hns3: Copyright (c) 2017 Huawei Corporation.
10599 11:06:33.216774 <6>[ 1.760315] hclge is initializing
10600 11:06:33.219885 <6>[ 1.763897] e1000: Intel(R) PRO/1000 Network Driver
10601 11:06:33.226824 <6>[ 1.769026] e1000: Copyright (c) 1999-2006 Intel Corporation.
10602 11:06:33.233094 <6>[ 1.775039] e1000e: Intel(R) PRO/1000 Network Driver
10603 11:06:33.236797 <6>[ 1.780254] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10604 11:06:33.243289 <6>[ 1.786442] igb: Intel(R) Gigabit Ethernet Network Driver
10605 11:06:33.250431 <6>[ 1.792092] igb: Copyright (c) 2007-2014 Intel Corporation.
10606 11:06:33.256801 <6>[ 1.797928] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10607 11:06:33.263292 <6>[ 1.804445] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10608 11:06:33.266748 <6>[ 1.810903] sky2: driver version 1.30
10609 11:06:33.272955 <6>[ 1.815903] VFIO - User Level meta-driver version: 0.3
10610 11:06:33.280534 <6>[ 1.824151] usbcore: registered new interface driver usb-storage
10611 11:06:33.287539 <6>[ 1.830594] usbcore: registered new device driver onboard-usb-hub
10612 11:06:33.296726 <6>[ 1.839744] mt6397-rtc mt6359-rtc: registered as rtc0
10613 11:06:33.306221 <6>[ 1.845207] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T11:06:34 UTC (1709463994)
10614 11:06:33.309641 <6>[ 1.854780] i2c_dev: i2c /dev entries driver
10615 11:06:33.327020 <6>[ 1.866418] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10616 11:06:33.347314 <6>[ 1.890434] cpu cpu0: EM: created perf domain
10617 11:06:33.350959 <6>[ 1.895383] cpu cpu4: EM: created perf domain
10618 11:06:33.357969 <6>[ 1.900977] sdhci: Secure Digital Host Controller Interface driver
10619 11:06:33.365002 <6>[ 1.907410] sdhci: Copyright(c) Pierre Ossman
10620 11:06:33.370744 <6>[ 1.912366] Synopsys Designware Multimedia Card Interface Driver
10621 11:06:33.377319 <6>[ 1.919003] sdhci-pltfm: SDHCI platform and OF driver helper
10622 11:06:33.380942 <6>[ 1.919073] mmc0: CQHCI version 5.10
10623 11:06:33.387402 <6>[ 1.929305] ledtrig-cpu: registered to indicate activity on CPUs
10624 11:06:33.394196 <6>[ 1.936394] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10625 11:06:33.401366 <6>[ 1.943456] usbcore: registered new interface driver usbhid
10626 11:06:33.404622 <6>[ 1.949278] usbhid: USB HID core driver
10627 11:06:33.413561 <6>[ 1.953480] spi_master spi0: will run message pump with realtime priority
10628 11:06:33.460137 <6>[ 1.996861] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10629 11:06:33.480043 <6>[ 2.012892] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10630 11:06:33.483023 <6>[ 2.026503] mmc0: Command Queue Engine enabled
10631 11:06:33.490261 <6>[ 2.028105] cros-ec-spi spi0.0: Chrome EC device registered
10632 11:06:33.496815 <6>[ 2.031245] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10633 11:06:33.500169 <6>[ 2.044405] mmcblk0: mmc0:0001 DA4128 116 GiB
10634 11:06:33.511543 <6>[ 2.051810] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10635 11:06:33.518011 <6>[ 2.054194] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10636 11:06:33.524850 <6>[ 2.062109] NET: Registered PF_PACKET protocol family
10637 11:06:33.527955 <6>[ 2.067987] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10638 11:06:33.534335 <6>[ 2.072486] 9pnet: Installing 9P2000 support
10639 11:06:33.538009 <6>[ 2.078283] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10640 11:06:33.544841 <5>[ 2.082189] Key type dns_resolver registered
10641 11:06:33.551282 <6>[ 2.087942] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10642 11:06:33.554674 <6>[ 2.092508] registered taskstats version 1
10643 11:06:33.557848 <5>[ 2.102832] Loading compiled-in X.509 certificates
10644 11:06:33.588266 <4>[ 2.125530] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10645 11:06:33.598554 <4>[ 2.136234] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10646 11:06:33.605145 <3>[ 2.146760] debugfs: File 'uA_load' in directory '/' already present!
10647 11:06:33.611873 <3>[ 2.153460] debugfs: File 'min_uV' in directory '/' already present!
10648 11:06:33.618726 <3>[ 2.160130] debugfs: File 'max_uV' in directory '/' already present!
10649 11:06:33.624909 <3>[ 2.166750] debugfs: File 'constraint_flags' in directory '/' already present!
10650 11:06:33.635598 <3>[ 2.176230] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10651 11:06:33.645492 <6>[ 2.189098] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10652 11:06:33.652635 <6>[ 2.195854] xhci-mtk 11200000.usb: xHCI Host Controller
10653 11:06:33.658854 <6>[ 2.201355] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10654 11:06:33.669220 <6>[ 2.209290] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10655 11:06:33.675780 <6>[ 2.218726] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10656 11:06:33.682674 <6>[ 2.224815] xhci-mtk 11200000.usb: xHCI Host Controller
10657 11:06:33.689124 <6>[ 2.230296] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10658 11:06:33.695625 <6>[ 2.237957] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10659 11:06:33.702258 <6>[ 2.245764] hub 1-0:1.0: USB hub found
10660 11:06:33.705945 <6>[ 2.249789] hub 1-0:1.0: 1 port detected
10661 11:06:33.715745 <6>[ 2.254087] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10662 11:06:33.718712 <6>[ 2.262797] hub 2-0:1.0: USB hub found
10663 11:06:33.722500 <6>[ 2.266839] hub 2-0:1.0: 1 port detected
10664 11:06:33.731087 <6>[ 2.274441] mtk-msdc 11f70000.mmc: Got CD GPIO
10665 11:06:33.744266 <6>[ 2.284063] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10666 11:06:33.750737 <6>[ 2.292112] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10667 11:06:33.760433 <4>[ 2.300061] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10668 11:06:33.769938 <6>[ 2.309590] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10669 11:06:33.776600 <6>[ 2.317668] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10670 11:06:33.786819 <6>[ 2.325772] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10671 11:06:33.793102 <6>[ 2.333694] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10672 11:06:33.800072 <6>[ 2.341511] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10673 11:06:33.809954 <6>[ 2.349330] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10674 11:06:33.819521 <6>[ 2.359903] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10675 11:06:33.829618 <6>[ 2.368276] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10676 11:06:33.836170 <6>[ 2.376614] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10677 11:06:33.846197 <6>[ 2.384954] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10678 11:06:33.852552 <6>[ 2.393291] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10679 11:06:33.862159 <6>[ 2.401630] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10680 11:06:33.869297 <6>[ 2.409967] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10681 11:06:33.878955 <6>[ 2.418304] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10682 11:06:33.885717 <6>[ 2.426640] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10683 11:06:33.895201 <6>[ 2.434977] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10684 11:06:33.902344 <6>[ 2.443315] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10685 11:06:33.912229 <6>[ 2.451652] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10686 11:06:33.918390 <6>[ 2.459989] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10687 11:06:33.929050 <6>[ 2.468326] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10688 11:06:33.935414 <6>[ 2.476664] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10689 11:06:33.941729 <6>[ 2.485418] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10690 11:06:33.949065 <6>[ 2.492590] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10691 11:06:33.956363 <6>[ 2.499365] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10692 11:06:33.965590 <6>[ 2.506133] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10693 11:06:33.972614 <6>[ 2.513071] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10694 11:06:33.982479 <6>[ 2.519933] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10695 11:06:33.989128 <6>[ 2.529062] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10696 11:06:33.998591 <6>[ 2.538187] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10697 11:06:34.008357 <6>[ 2.547480] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10698 11:06:34.018478 <6>[ 2.556947] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10699 11:06:34.028493 <6>[ 2.566414] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10700 11:06:34.034955 <6>[ 2.575532] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10701 11:06:34.045199 <6>[ 2.584998] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10702 11:06:34.054735 <6>[ 2.594116] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10703 11:06:34.064549 <6>[ 2.603411] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10704 11:06:34.074454 <6>[ 2.613570] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10705 11:06:34.085257 <6>[ 2.625052] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10706 11:06:34.134770 <6>[ 2.674609] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10707 11:06:34.288228 <6>[ 2.831204] hub 1-1:1.0: USB hub found
10708 11:06:34.290763 <6>[ 2.835609] hub 1-1:1.0: 4 ports detected
10709 11:06:34.300310 <6>[ 2.843666] hub 1-1:1.0: USB hub found
10710 11:06:34.303988 <6>[ 2.847999] hub 1-1:1.0: 4 ports detected
10711 11:06:34.414186 <6>[ 2.954659] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10712 11:06:34.440259 <6>[ 2.983873] hub 2-1:1.0: USB hub found
10713 11:06:34.443703 <6>[ 2.988369] hub 2-1:1.0: 3 ports detected
10714 11:06:34.452812 <6>[ 2.996244] hub 2-1:1.0: USB hub found
10715 11:06:34.455916 <6>[ 3.000696] hub 2-1:1.0: 3 ports detected
10716 11:06:34.630860 <6>[ 3.170645] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10717 11:06:34.763052 <6>[ 3.306416] hub 1-1.4:1.0: USB hub found
10718 11:06:34.765870 <6>[ 3.311072] hub 1-1.4:1.0: 2 ports detected
10719 11:06:34.775550 <6>[ 3.319396] hub 1-1.4:1.0: USB hub found
10720 11:06:34.779015 <6>[ 3.324005] hub 1-1.4:1.0: 2 ports detected
10721 11:06:34.842746 <6>[ 3.382812] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10722 11:06:35.077849 <6>[ 3.618626] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10723 11:06:35.269681 <6>[ 3.810623] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10724 11:06:46.379352 <6>[ 14.927658] ALSA device list:
10725 11:06:46.386197 <6>[ 14.930947] No soundcards found.
10726 11:06:46.393991 <6>[ 14.938899] Freeing unused kernel memory: 8448K
10727 11:06:46.397230 <6>[ 14.944264] Run /init as init process
10728 11:06:46.423839 Starting syslogd: OK
10729 11:06:46.427769 Starting klogd: OK
10730 11:06:46.434599 Running sysctl: OK
10731 11:06:46.441637 Populating /dev using udev: <30>[ 14.988133] udevd[187]: starting version 3.2.9
10732 11:06:46.451376 <27>[ 14.996547] udevd[187]: specified user 'tss' unknown
10733 11:06:46.458529 <27>[ 15.001982] udevd[187]: specified group 'tss' unknown
10734 11:06:46.464634 <30>[ 15.008729] udevd[188]: starting eudev-3.2.9
10735 11:06:46.491861 <27>[ 15.036576] udevd[188]: specified user 'tss' unknown
10736 11:06:46.498677 <27>[ 15.041945] udevd[188]: specified group 'tss' unknown
10737 11:06:46.675739 <3>[ 15.217533] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10738 11:06:46.681925 <6>[ 15.219179] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10739 11:06:46.691830 <3>[ 15.225743] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10740 11:06:46.698751 <6>[ 15.233283] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10741 11:06:46.708629 <3>[ 15.241307] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10742 11:06:46.715069 <6>[ 15.242025] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10743 11:06:46.725953 <6>[ 15.250130] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10744 11:06:46.732499 <6>[ 15.253059] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10745 11:06:46.739445 <3>[ 15.258193] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 11:06:46.746058 <6>[ 15.258819] usbcore: registered new device driver r8152-cfgselector
10747 11:06:46.755575 <4>[ 15.263972] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10748 11:06:46.759092 <4>[ 15.263972] Fallback method does not support PEC.
10749 11:06:46.765551 <6>[ 15.266030] remoteproc remoteproc0: scp is available
10750 11:06:46.772246 <3>[ 15.274433] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 11:06:46.781753 <3>[ 15.274439] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 11:06:46.788787 <3>[ 15.274455] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 11:06:46.795062 <6>[ 15.275454] mc: Linux media interface: v0.10
10754 11:06:46.801484 <3>[ 15.280395] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10755 11:06:46.808498 <6>[ 15.281874] remoteproc remoteproc0: powering up scp
10756 11:06:46.815033 <3>[ 15.290171] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 11:06:46.824845 <6>[ 15.297069] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10758 11:06:46.831493 <6>[ 15.307203] videodev: Linux video capture interface: v2.00
10759 11:06:46.838296 <3>[ 15.312781] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 11:06:46.844539 <4>[ 15.315955] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10761 11:06:46.854435 <3>[ 15.323615] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 11:06:46.858173 <6>[ 15.323973] Bluetooth: Core ver 2.22
10763 11:06:46.864120 <6>[ 15.324057] NET: Registered PF_BLUETOOTH protocol family
10764 11:06:46.870954 <6>[ 15.324059] Bluetooth: HCI device and connection manager initialized
10765 11:06:46.874515 <6>[ 15.324071] Bluetooth: HCI socket layer initialized
10766 11:06:46.881077 <6>[ 15.324075] Bluetooth: L2CAP socket layer initialized
10767 11:06:46.884225 <6>[ 15.324080] Bluetooth: SCO socket layer initialized
10768 11:06:46.891514 <4>[ 15.331689] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10769 11:06:46.901178 <3>[ 15.339865] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 11:06:46.907943 <6>[ 15.344173] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10771 11:06:46.914593 <3>[ 15.352942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 11:06:46.924366 <6>[ 15.358264] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10773 11:06:46.931415 <3>[ 15.366458] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 11:06:46.938052 <6>[ 15.391858] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10775 11:06:46.947655 <3>[ 15.395863] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 11:06:46.954355 <4>[ 15.402432] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10777 11:06:46.963751 <4>[ 15.402448] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10778 11:06:46.970222 <6>[ 15.403855] pci_bus 0000:00: root bus resource [bus 00-ff]
10779 11:06:46.977449 <3>[ 15.407861] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 11:06:46.983656 <6>[ 15.413329] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10781 11:06:46.993747 <3>[ 15.419926] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 11:06:47.000285 <3>[ 15.419932] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10783 11:06:47.010443 <6>[ 15.425060] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10784 11:06:47.019981 <3>[ 15.430468] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 11:06:47.023251 <6>[ 15.435558] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10786 11:06:47.033511 <3>[ 15.438962] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10787 11:06:47.036858 <6>[ 15.454540] r8152 2-1.3:1.0 eth0: v1.12.13
10788 11:06:47.049831 <6>[ 15.454886] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10789 11:06:47.056170 <6>[ 15.455367] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10790 11:06:47.066440 <6>[ 15.456544] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10791 11:06:47.072869 <6>[ 15.458579] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10792 11:06:47.079537 <6>[ 15.464691] usbcore: registered new interface driver r8152
10793 11:06:47.082723 <6>[ 15.473016] pci 0000:00:00.0: supports D1 D2
10794 11:06:47.092753 <6>[ 15.483567] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10795 11:06:47.099528 <6>[ 15.487892] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10796 11:06:47.106102 <6>[ 15.487896] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10797 11:06:47.116098 <6>[ 15.489013] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10798 11:06:47.122497 <6>[ 15.489104] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10799 11:06:47.128845 <6>[ 15.489129] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10800 11:06:47.135266 <6>[ 15.489146] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10801 11:06:47.142211 <6>[ 15.489161] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10802 11:06:47.148351 <6>[ 15.489267] pci 0000:01:00.0: supports D1 D2
10803 11:06:47.154861 <6>[ 15.489269] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10804 11:06:47.161756 <6>[ 15.498657] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10805 11:06:47.168264 <6>[ 15.502371] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10806 11:06:47.174664 <6>[ 15.502402] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10807 11:06:47.185180 <6>[ 15.502405] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10808 11:06:47.191750 <6>[ 15.502414] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10809 11:06:47.201486 <6>[ 15.502427] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10810 11:06:47.208348 <6>[ 15.502440] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10811 11:06:47.214861 <6>[ 15.502452] pci 0000:00:00.0: PCI bridge to [bus 01]
10812 11:06:47.221278 <6>[ 15.502457] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10813 11:06:47.228484 <6>[ 15.502606] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10814 11:06:47.234345 <6>[ 15.503078] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10815 11:06:47.241014 <6>[ 15.505559] remoteproc remoteproc0: remote processor scp is now up
10816 11:06:47.247615 <6>[ 15.505715] usbcore: registered new interface driver cdc_ether
10817 11:06:47.251093 <6>[ 15.506127] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10818 11:06:47.257401 <6>[ 15.506747] usbcore: registered new interface driver btusb
10819 11:06:47.267743 <4>[ 15.507142] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10820 11:06:47.274033 <3>[ 15.507156] Bluetooth: hci0: Failed to load firmware file (-2)
10821 11:06:47.280871 <3>[ 15.507159] Bluetooth: hci0: Failed to set up firmware (-2)
10822 11:06:47.290964 <4>[ 15.507163] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10823 11:06:47.303978 <6>[ 15.514917] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10824 11:06:47.310640 <6>[ 15.519894] usbcore: registered new interface driver r8153_ecm
10825 11:06:47.317443 <6>[ 15.521450] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10826 11:06:47.327296 <5>[ 15.521472] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10827 11:06:47.333729 <6>[ 15.523094] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10828 11:06:47.340220 <6>[ 15.527452] usbcore: registered new interface driver uvcvideo
10829 11:06:47.347033 <6>[ 15.535171] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10830 11:06:47.353259 <5>[ 15.545189] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10831 11:06:47.363327 <5>[ 15.903821] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10832 11:06:47.369937 <4>[ 15.912295] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10833 11:06:47.376371 <6>[ 15.921177] cfg80211: failed to load regulatory.db
10834 11:06:47.425968 <6>[ 15.967346] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10835 11:06:47.432029 <6>[ 15.974850] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10836 11:06:47.456514 <6>[ 16.001704] mt7921e 0000:01:00.0: ASIC revision: 79610010
10837 11:06:47.559991 <6>[ 16.102028] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10838 11:06:47.563239 <6>[ 16.102028]
10839 11:06:47.571058 done
10840 11:06:47.581109 Saving random seed: OK
10841 11:06:47.599919 Starting network: OK
10842 11:06:47.635013 Starting dropbear sshd: <6>[ 16.180555] NET: Registered PF_INET6 protocol family
10843 11:06:47.641848 <6>[ 16.186838] Segment Routing with IPv6
10844 11:06:47.645310 <6>[ 16.190802] In-situ OAM (IOAM) with IPv6
10845 11:06:47.648744 OK
10846 11:06:47.656571 /bin/sh: can't access tty; job control turned off
10847 11:06:47.656901 Matched prompt #10: / #
10849 11:06:47.657107 Setting prompt string to ['/ #']
10850 11:06:47.657197 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10852 11:06:47.657387 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10853 11:06:47.657472 start: 2.2.6 expect-shell-connection (timeout 00:03:23) [common]
10854 11:06:47.657542 Setting prompt string to ['/ #']
10855 11:06:47.657602 Forcing a shell prompt, looking for ['/ #']
10857 11:06:47.707784 / #
10858 11:06:47.707891 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10859 11:06:47.707966 Waiting using forced prompt support (timeout 00:02:30)
10860 11:06:47.712993
10861 11:06:47.713268 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10862 11:06:47.713370 start: 2.2.7 export-device-env (timeout 00:03:22) [common]
10863 11:06:47.713462 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10864 11:06:47.713581 end: 2.2 depthcharge-retry (duration 00:01:38) [common]
10865 11:06:47.713661 end: 2 depthcharge-action (duration 00:01:38) [common]
10866 11:06:47.713749 start: 3 lava-test-retry (timeout 00:01:00) [common]
10867 11:06:47.713831 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10868 11:06:47.713906 Using namespace: common
10870 11:06:47.814249 / # #
10871 11:06:47.814398 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10872 11:06:47.819663 #
10873 11:06:47.819953 Using /lava-12925635
10875 11:06:47.920286 / # <6>[ 16.369065] mt7921e 000export SHELL=/bin/sh
10876 11:06:47.920463 0:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10877 11:06:47.925737 export SHELL=/bin/sh
10879 11:06:48.026259 / # . /lava-12925635/environment
10880 11:06:48.031487 . /lava-12925635/environment
10882 11:06:48.132041 / # /lava-12925635/bin/lava-test-runner /lava-12925635/0
10883 11:06:48.132188 Test shell timeout: 10s (minimum of the action and connection timeout)
10884 11:06:48.137676 /lava-12925635/bin/lava-test-runner /lava-12925635/0
10885 11:06:48.156338 + export 'TESTRUN_ID=0_dmesg'
10886 11:06:48.163189 + c<8>[ 16.707497] <LAVA_SIGNAL_STARTRUN 0_dmesg 12925635_1.5.2.3.1>
10887 11:06:48.163448 Received signal: <STARTRUN> 0_dmesg 12925635_1.5.2.3.1
10888 11:06:48.163523 Starting test lava.0_dmesg (12925635_1.5.2.3.1)
10889 11:06:48.163606 Skipping test definition patterns.
10890 11:06:48.166372 d /lava-12925635/0/tests/0_dmesg
10891 11:06:48.166454 + cat uuid
10892 11:06:48.169609 + UUID=12925635_1.5.2.3.1
10893 11:06:48.169691 + set +x
10894 11:06:48.176036 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10895 11:06:48.186055 <8>[ 16.728022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10896 11:06:48.186310 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10898 11:06:48.204003 <8>[ 16.746466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10899 11:06:48.204257 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10901 11:06:48.223713 <8>[ 16.766190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10902 11:06:48.223965 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10904 11:06:48.227081 + set +x
10905 11:06:48.230430 <8>[ 16.775609] <LAVA_SIGNAL_ENDRUN 0_dmesg 12925635_1.5.2.3.1>
10906 11:06:48.230698 Received signal: <ENDRUN> 0_dmesg 12925635_1.5.2.3.1
10907 11:06:48.230782 Ending use of test pattern.
10908 11:06:48.230844 Ending test lava.0_dmesg (12925635_1.5.2.3.1), duration 0.07
10910 11:06:48.234403 <LAVA_TEST_RUNNER EXIT>
10911 11:06:48.234654 ok: lava_test_shell seems to have completed
10912 11:06:48.234760 alert: pass
crit: pass
emerg: pass
10913 11:06:48.234844 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10914 11:06:48.234927 end: 3 lava-test-retry (duration 00:00:01) [common]
10915 11:06:48.235011 start: 4 lava-test-retry (timeout 00:01:00) [common]
10916 11:06:48.235090 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10917 11:06:48.235153 Using namespace: common
10919 11:06:48.335483 / # #
10920 11:06:48.335622 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10921 11:06:48.335792 Using /lava-12925635
10923 11:06:48.436093 export SHELL=/bin/sh
10924 11:06:48.436306 #
10926 11:06:48.537012 / # export SHELL=/bin/sh. /lava-12925635/environment
10927 11:06:48.537645
10929 11:06:48.639057 / # . /lava-12925635/environment/lava-12925635/bin/lava-test-runner /lava-12925635/1
10930 11:06:48.639197 Test shell timeout: 10s (minimum of the action and connection timeout)
10931 11:06:48.639330
10932 11:06:48.645315 / # /lava-12925635/bin/lava-test-runner /lava-12925635/1
10933 11:06:48.671216 + export 'TESTRU<6>[ 17.213794] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10934 11:06:48.671425 N_ID=1_bootrr'
10935 11:06:48.678320 + cd /lava-12925<8>[ 17.222637] <LAVA_SIGNAL_STARTRUN 1_bootrr 12925635_1.5.2.3.5>
10936 11:06:48.678851 Received signal: <STARTRUN> 1_bootrr 12925635_1.5.2.3.5
10937 11:06:48.679103 Starting test lava.1_bootrr (12925635_1.5.2.3.5)
10938 11:06:48.679385 Skipping test definition patterns.
10939 11:06:48.681291 635/1/tests/1_bootrr
10940 11:06:48.681593 + cat uuid
10941 11:06:48.684723 + UUID=12925635_1.5.2.3.5
10942 11:06:48.685112 + set +x
10943 11:06:48.694611 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12925635/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10944 11:06:48.704280 + cd /opt/bootrr/libexec/bootrr<8>[ 17.246490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10945 11:06:48.704709
10946 11:06:48.705292 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10948 11:06:48.707760 + sh helpers/bootrr-auto
10949 11:06:48.710856 /lava-12925635/1/../bin/lava-test-case
10950 11:06:48.718035 /lava-12925635/1/../bin/lava-test-case
10951 11:06:48.724104 <8>[ 17.266073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10952 11:06:48.724778 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10954 11:06:48.729264 /usr/bin/tpm2_getcap
10955 11:06:48.764515 /lava-12925635/1/../bin/lava-test-case
10956 11:06:48.771587 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10958 11:06:48.774481 <8>[ 17.315814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10959 11:06:48.788740 /lava-12925635/1/../bin/lava-test-case
10960 11:06:48.795940 <8>[ 17.338914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10961 11:06:48.796192 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10963 11:06:48.807986 /lava-12925635/1/../bin/lava-test-case
10964 11:06:48.813893 <8>[ 17.356728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10965 11:06:48.814145 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10967 11:06:48.826367 /lava-12925635/1/../bin/lava-test-case
10968 11:06:48.835940 <8>[ 17.377048] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10969 11:06:48.836192 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10971 11:06:48.845940 /lava-12925635/1/../bin/lava-test-case
10972 11:06:48.852808 <8>[ 17.395095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10973 11:06:48.853095 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10975 11:06:48.865071 /lava-12925635/1/../bin/lava-test-case
10976 11:06:48.871963 <8>[ 17.414920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10977 11:06:48.872328 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10979 11:06:48.882202 /lava-12925635/1/../bin/lava-test-case
10980 11:06:48.888687 <8>[ 17.432261] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10981 11:06:48.888939 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10983 11:06:48.909963 /lava-12925635/1/../bin/lava-tes<8>[ 17.451052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10984 11:06:48.910075 t-case
10985 11:06:48.910339 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10987 11:06:48.917325 /lava-12925635/1/../bin/lava-test-case
10988 11:06:48.926951 <8>[ 17.467143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10989 11:06:48.927317 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10991 11:06:48.938630 /lava-12925635/1/../bin/lava-test-case
10992 11:06:48.945498 <8>[ 17.487482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10993 11:06:48.946019 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10995 11:06:48.957867 /lava-12925635/1/../bin/lava-test-case
10996 11:06:48.964621 <8>[ 17.506262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10997 11:06:48.965291 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10999 11:06:48.984684 /lava-12925635/1/../bin/lava-tes<8>[ 17.525135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11000 11:06:48.985142 t-case
11001 11:06:48.985729 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11003 11:06:49.004546 /lava-12925635/1/../bin/lava-tes<8>[ 17.545758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11004 11:06:49.004968 t-case
11005 11:06:49.005549 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11007 11:06:49.012973 /lava-12925635/1/../bin/lava-test-case
11008 11:06:49.019895 <8>[ 17.562810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11009 11:06:49.020568 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11011 11:06:49.033150 /lava-12925635/1/../bin/lava-test-case
11012 11:06:49.039781 <8>[ 17.582338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11013 11:06:49.040454 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11015 11:06:49.049321 /lava-12925635/1/../bin/lava-test-case
11016 11:06:49.055975 <8>[ 17.598493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11017 11:06:49.056649 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11019 11:06:49.073179 /lava-12925635/1/../bin/lava-test-case
11020 11:06:49.079664 <8>[ 17.621667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11021 11:06:49.080377 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11023 11:06:49.093641 /lava-12925635/1/../bin/lava-test-case
11024 11:06:49.099440 <8>[ 17.641058] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11025 11:06:49.100149 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11027 11:06:49.112815 /lava-12925635/1/../bin/lava-test-case
11028 11:06:49.119165 <8>[ 17.661247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11029 11:06:49.119835 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11031 11:06:49.130341 /lava-12925635/1/../bin/lava-test-case
11032 11:06:49.136857 <8>[ 17.679597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11033 11:06:49.137528 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11035 11:06:49.151107 /lava-12925635/1/../bin/lava-test-case
11036 11:06:49.157693 <8>[ 17.699700] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11037 11:06:49.158369 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11039 11:06:49.168422 /lava-12925635/1/../bin/lava-test-case
11040 11:06:49.174555 <8>[ 17.716060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11041 11:06:49.175232 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11043 11:06:49.198962 /lava-12925635/1/../bin/lava-tes<8>[ 17.740373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11044 11:06:49.199389 t-case
11045 11:06:49.200062 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11047 11:06:49.211129 /lava-12925635/1/../bin/lava-test-case
11048 11:06:49.217839 <8>[ 17.759346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11049 11:06:49.218515 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11051 11:06:49.234366 /lava-12925635/1/../bin/lava-tes<8>[ 17.775165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11052 11:06:49.234796 t-case
11053 11:06:49.235385 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11055 11:06:49.252077 /lava-12925635/1/../bin/lava-tes<8>[ 17.793246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11056 11:06:49.252598 t-case
11057 11:06:49.253195 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11059 11:06:49.268348 /lava-12925635/1/../bin/lava-tes<8>[ 17.809536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11060 11:06:49.268871 t-case
11061 11:06:49.269655 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11063 11:06:49.280744 /lava-12925635/1/../bin/lava-test-case
11064 11:06:49.287065 <8>[ 17.828691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11065 11:06:49.287810 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11067 11:06:49.306807 /lava-12925635/1/../bin/lava-tes<8>[ 17.847686] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11068 11:06:49.307407 t-case
11069 11:06:49.308105 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11071 11:06:49.318237 /lava-12925635/1/../bin/lava-test-case
11072 11:06:49.325272 <8>[ 17.866463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11073 11:06:49.326124 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11075 11:06:49.334334 /lava-12925635/1/../bin/lava-test-case
11076 11:06:49.341528 <8>[ 17.883925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11077 11:06:49.341782 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11079 11:06:49.358814 /lava-12925635/1/../bin/lava-tes<8>[ 17.900467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11080 11:06:49.358925 t-case
11081 11:06:49.359191 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11083 11:06:49.370992 /lava-12925635/1/../bin/lava-test-case
11084 11:06:49.377726 <8>[ 17.920052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11085 11:06:49.378080 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11087 11:06:49.390883 /lava-12925635/1/../bin/lava-test-case
11088 11:06:49.397669 <8>[ 17.940277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11089 11:06:49.397979 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11091 11:06:49.407582 /lava-12925635/1/../bin/lava-test-case
11092 11:06:49.414344 <8>[ 17.956534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11093 11:06:49.414799 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11095 11:06:49.428342 /lava-12925635/1/../bin/lava-test-case
11096 11:06:49.434956 <8>[ 17.976415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11097 11:06:49.435639 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11099 11:06:49.445516 /lava-12925635/1/../bin/lava-test-case
11100 11:06:49.452434 <8>[ 17.994049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11101 11:06:49.453122 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11103 11:06:49.466612 /lava-12925635/1/../bin/lava-test-case
11104 11:06:49.472858 <8>[ 18.014171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11105 11:06:49.473552 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11107 11:06:49.489309 /lava-12925635/1/../bin/lava-tes<8>[ 18.030283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11108 11:06:49.489822 t-case
11109 11:06:49.490421 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11111 11:06:49.507818 /lava-12925635/1/../bin/lava-tes<8>[ 18.048623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11112 11:06:49.508416 t-case
11113 11:06:49.509072 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11115 11:06:49.525149 /lava-12925635/1/../bin/lava-tes<8>[ 18.065954] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11116 11:06:49.525724 t-case
11117 11:06:49.526371 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11119 11:06:49.545520 /lava-12925635/1/../bin/lava-tes<8>[ 18.086283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11120 11:06:49.546064 t-case
11121 11:06:49.546702 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11123 11:06:49.556268 /lava-12925635/1/../bin/lava-test-case
11124 11:06:49.562534 <8>[ 18.104704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11125 11:06:49.563338 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11127 11:06:49.575434 /lava-12925635/1/../bin/lava-test-case
11128 11:06:49.582042 <8>[ 18.124265] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11129 11:06:49.582897 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11131 11:06:49.591806 /lava-12925635/1/../bin/lava-test-case
11132 11:06:49.598526 <8>[ 18.139955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11133 11:06:49.599381 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11135 11:06:49.610857 /lava-12925635/1/../bin/lava-test-case
11136 11:06:49.617211 <8>[ 18.159565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11137 11:06:49.617974 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11139 11:06:49.627739 /lava-12925635/1/../bin/lava-test-case
11140 11:06:49.634457 <8>[ 18.176269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11141 11:06:49.635137 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11143 11:06:49.647488 /lava-12925635/1/../bin/lava-test-case
11144 11:06:49.653781 <8>[ 18.195277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11145 11:06:49.654825 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11147 11:06:49.671039 /lava-12925635/1/../bin/lava-test-case
11148 11:06:49.677551 <8>[ 18.220202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11149 11:06:49.678235 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11151 11:06:49.687926 /lava-12925635/1/../bin/lava-test-case
11152 11:06:49.694138 <8>[ 18.235795] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11153 11:06:49.694878 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11155 11:06:49.704659 /lava-12925635/1/../bin/lava-test-case
11156 11:06:49.711559 <8>[ 18.254920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11157 11:06:49.712476 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11159 11:06:49.723963 /lava-12925635/1/../bin/lava-test-case
11160 11:06:49.730132 <8>[ 18.272064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11161 11:06:49.730978 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11163 11:06:49.742666 /lava-12925635/1/../bin/lava-test-case
11164 11:06:49.749835 <8>[ 18.290872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11165 11:06:49.750512 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11167 11:06:49.761774 /lava-12925635/1/../bin/lava-test-case
11168 11:06:49.768096 <8>[ 18.311517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11169 11:06:49.768367 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11171 11:06:49.778727 /lava-12925635/1/../bin/lava-test-case
11172 11:06:49.785161 <8>[ 18.327502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11173 11:06:49.785446 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11175 11:06:49.803424 /lava-12925635/1/../bin/lava-tes<8>[ 18.345172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11176 11:06:49.803523 t-case
11177 11:06:49.803772 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11179 11:06:49.814872 /lava-12925635/1/../bin/lava-test-case
11180 11:06:49.821731 <8>[ 18.364843] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11181 11:06:49.822050 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11183 11:06:49.831883 /lava-12925635/1/../bin/lava-test-case
11184 11:06:49.837808 <8>[ 18.379801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11185 11:06:49.838211 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11187 11:06:49.847950 /lava-12925635/1/../bin/lava-test-case
11188 11:06:49.854780 <8>[ 18.397739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11189 11:06:49.855478 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11191 11:06:49.871361 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11193 11:06:49.874583 /lava-12925635/1/../bin/lava-tes<8>[ 18.415905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11194 11:06:49.875199 t-case
11195 11:06:49.893813 /lava-12925635/1/../bin/lava-tes<8>[ 18.434273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11196 11:06:49.894248 t-case
11197 11:06:49.894844 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11199 11:06:49.912660 /lava-12925635/1/../bin/lava-tes<8>[ 18.453762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11200 11:06:49.913096 t-case
11201 11:06:49.913802 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11203 11:06:49.925235 /lava-12925635/1/../bin/lava-test-case
11204 11:06:49.931377 <8>[ 18.473044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11205 11:06:49.932104 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11207 11:06:49.950830 /lava-12925635/1/../bin/lava-tes<8>[ 18.492317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11208 11:06:49.951256 t-case
11209 11:06:49.951845 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11211 11:06:49.960019 /lava-12925635/1/../bin/lava-test-case
11212 11:06:49.966500 <8>[ 18.508286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11213 11:06:49.967328 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11215 11:06:49.985360 /lava-12925635/1/../bin/lava-tes<8>[ 18.526625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11216 11:06:49.985926 t-case
11217 11:06:49.986627 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11219 11:06:49.999017 /lava-12925635/1/../bin/lava-test-case
11220 11:06:50.005925 <8>[ 18.548061] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11221 11:06:50.006742 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11223 11:06:50.021153 /lava-12925635/1/../bin/lava-test-case
11224 11:06:50.027862 <8>[ 18.568866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11225 11:06:50.028575 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11227 11:06:50.047164 /lava-12925635/1/../bin/lava-tes<8>[ 18.588453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11228 11:06:50.047600 t-case
11229 11:06:50.048241 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11231 11:06:50.060412 /lava-12925635/1/../bin/lava-test-case
11232 11:06:50.066674 <8>[ 18.609175] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11233 11:06:50.067361 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11235 11:06:50.084162 /lava-12925635/1/../bin/lava-test-case
11236 11:06:50.090488 <8>[ 18.633791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11237 11:06:50.091319 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11239 11:06:50.103838 /lava-12925635/1/../bin/lava-test-case
11240 11:06:50.110498 <8>[ 18.652260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11241 11:06:50.111246 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11243 11:06:50.129006 /lava-12925635/1/../bin/lava-tes<8>[ 18.670355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11244 11:06:50.129586 t-case
11245 11:06:50.130352 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11247 11:06:50.141453 /lava-12925635/1/../bin/lava-test-case
11248 11:06:50.147992 <8>[ 18.690263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11249 11:06:50.148672 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11251 11:06:50.159381 /lava-12925635/1/../bin/lava-test-case
11252 11:06:50.165943 <8>[ 18.708341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11253 11:06:50.166625 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11255 11:06:50.178198 /lava-12925635/1/../bin/lava-test-case
11256 11:06:50.184700 <8>[ 18.726602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11257 11:06:50.185381 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11259 11:06:50.198125 /lava-12925635/1/../bin/lava-test-case
11260 11:06:50.204588 <8>[ 18.746065] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11261 11:06:50.205280 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11263 11:06:50.224829 /lava-12925635/1/../bin/lava-tes<8>[ 18.765747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11264 11:06:50.225259 t-case
11265 11:06:50.225848 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11267 11:06:50.240974 /lava-12925635/1/../bin/lava-test-case
11268 11:06:50.247243 <8>[ 18.789612] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11269 11:06:50.248016 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11271 11:06:50.266283 /lava-12925635/1/../bin/lava-tes<8>[ 18.807777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11272 11:06:50.266724 t-case
11273 11:06:50.267322 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11275 11:06:50.276240 /lava-12925635/1/../bin/lava-test-case
11276 11:06:50.282498 <8>[ 18.824936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11277 11:06:50.283188 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11279 11:06:50.295407 /lava-12925635/1/../bin/lava-test-case
11280 11:06:50.302104 <8>[ 18.844041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11281 11:06:50.302793 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11283 11:06:50.318302 /lava-12925635/1/../bin/lava-tes<8>[ 18.859711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11284 11:06:50.318753 t-case
11285 11:06:50.319385 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11287 11:06:50.329316 /lava-12925635/1/../bin/lava-test-case
11288 11:06:50.335930 <8>[ 18.878683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11289 11:06:50.336626 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11291 11:06:50.347083 /lava-12925635/1/../bin/lava-test-case
11292 11:06:50.353764 <8>[ 18.895479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11293 11:06:50.354586 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11295 11:06:50.366494 /lava-12925635/1/../bin/lava-test-case
11296 11:06:50.373220 <8>[ 18.915124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11297 11:06:50.374024 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11299 11:06:50.384457 /lava-12925635/1/../bin/lava-test-case
11300 11:06:50.390687 <8>[ 18.932901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11301 11:06:50.391382 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11303 11:06:50.403028 /lava-12925635/1/../bin/lava-test-case
11304 11:06:50.409518 <8>[ 18.952641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11305 11:06:50.410312 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11307 11:06:50.420823 /lava-12925635/1/../bin/lava-test-case
11308 11:06:50.427550 <8>[ 18.969887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11309 11:06:50.428423 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11311 11:06:50.439982 /lava-12925635/1/../bin/lava-test-case
11312 11:06:50.446277 <8>[ 18.988749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11313 11:06:50.446956 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11315 11:06:50.458135 /lava-12925635/1/../bin/lava-test-case
11316 11:06:50.464234 <8>[ 19.007157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11317 11:06:50.464946 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11319 11:06:50.478865 /lava-12925635/1/../bin/lava-test-case
11320 11:06:50.484979 <8>[ 19.027404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11321 11:06:50.485762 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11323 11:06:50.497141 /lava-12925635/1/../bin/lava-test-case
11324 11:06:50.503309 <8>[ 19.045105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11325 11:06:50.504185 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11327 11:06:50.520271 /lava-12925635/1/../bin/lava-tes<8>[ 19.061699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11328 11:06:50.520707 t-case
11329 11:06:50.521295 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11331 11:06:50.538466 /lava-12925635/1/../bin/lava-tes<8>[ 19.080301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11332 11:06:50.539057 t-case
11333 11:06:50.539798 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11335 11:06:50.554188 /lava-12925635/1/../bin/lava-tes<8>[ 19.095681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11336 11:06:50.554764 t-case
11337 11:06:50.555573 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11339 11:06:50.570432 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11341 11:06:50.572822 /lava-12925635/1/../bin/lava-tes<8>[ 19.114564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11342 11:06:50.573271 t-case
11343 11:06:50.588295 /lava-12925635/1/../bin/lava-tes<8>[ 19.129493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11344 11:06:50.588727 t-case
11345 11:06:50.589316 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11347 11:06:51.602196 /lava-12925635/1/../bin/lava-test-case
11348 11:06:51.608763 <8>[ 20.152317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11349 11:06:51.609490 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11351 11:06:51.617752 /lava-12925635/1/../bin/lava-test-case
11352 11:06:51.624359 <8>[ 20.166865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11353 11:06:51.625042 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11355 11:06:52.639871 /lava-12925635/1/../bin/lava-test-case
11356 11:06:52.646303 <8>[ 21.190791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11357 11:06:52.646576 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11359 11:06:52.656838 /lava-12925635/1/../bin/lava-test-case
11360 11:06:52.663379 <8>[ 21.205483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11361 11:06:52.663667 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11363 11:06:53.682024 /lava-12925635/1/../bin/lava-test-case
11364 11:06:53.688856 <8>[ 22.233051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11365 11:06:53.689662 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11367 11:06:53.700404 /lava-12925635/1/../bin/lava-test-case
11368 11:06:53.706842 <8>[ 22.249388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11369 11:06:53.707636 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11371 11:06:54.722385 /lava-12925635/1/../bin/lava-test-case
11372 11:06:54.729216 <8>[ 23.273510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11373 11:06:54.729748 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11375 11:06:54.739310 /lava-12925635/1/../bin/lava-test-case
11376 11:06:54.745892 <8>[ 23.288001] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11377 11:06:54.746413 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11379 11:06:55.761584 /lava-12925635/1/../bin/lava-test-case
11380 11:06:55.767796 <8>[ 24.312059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11381 11:06:55.768565 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11383 11:06:55.778017 /lava-12925635/1/../bin/lava-test-case
11384 11:06:55.783973 <8>[ 24.326826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11385 11:06:55.784661 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11387 11:06:56.801947 /lava-12925635/1/../bin/lava-test-case
11388 11:06:56.808538 <8>[ 25.353138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11389 11:06:56.809286 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11391 11:06:56.819612 /lava-12925635/1/../bin/lava-test-case
11392 11:06:56.826450 <8>[ 25.369240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11393 11:06:56.827245 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11395 11:06:57.841177 /lava-12925635/1/../bin/lava-test-case
11396 11:06:57.847348 <8>[ 26.392766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11397 11:06:57.847629 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11399 11:06:57.858565 /lava-12925635/1/../bin/lava-test-case
11400 11:06:57.865102 <8>[ 26.408624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11401 11:06:57.865369 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11403 11:06:57.876350 /lava-12925635/1/../bin/lava-test-case
11404 11:06:57.882482 <8>[ 26.426528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11405 11:06:57.882783 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11407 11:06:58.896220 /lava-12925635/1/../bin/lava-test-case
11408 11:06:58.902909 <8>[ 27.446088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11409 11:06:58.903601 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11411 11:06:58.914384 /lava-12925635/1/../bin/lava-test-case
11412 11:06:58.921181 <8>[ 27.464455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11413 11:06:58.921856 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11415 11:06:58.934026 /lava-12925635/1/../bin/lava-test-case
11416 11:06:58.940460 <8>[ 27.483859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11417 11:06:58.941134 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11419 11:06:58.951077 /lava-12925635/1/../bin/lava-test-case
11420 11:06:58.957255 <8>[ 27.500893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11421 11:06:58.957929 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11423 11:06:58.970774 /lava-12925635/1/../bin/lava-test-case
11424 11:06:58.977556 <8>[ 27.520737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11425 11:06:58.978228 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11427 11:06:58.998651 /lava-12925635/1/../bin/lava-tes<8>[ 27.540674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11428 11:06:58.999076 t-case
11429 11:06:58.999723 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11431 11:06:59.015736 /lava-12925635/1/../bin/lava-test-case
11432 11:06:59.022567 <8>[ 27.565478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11433 11:06:59.023244 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11435 11:06:59.036144 /lava-12925635/1/../bin/lava-test-case
11436 11:06:59.045952 <8>[ 27.587940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11437 11:06:59.046625 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11439 11:06:59.057918 /lava-12925635/1/../bin/lava-test-case
11440 11:06:59.064532 <8>[ 27.607687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11441 11:06:59.065226 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11443 11:06:59.083619 /lava-12925635/1/../bin/lava-tes<8>[ 27.625948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11444 11:06:59.084111 t-case
11445 11:06:59.084697 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11447 11:06:59.091577 /lava-12925635/1/../bin/lava-test-case
11448 11:06:59.101489 <8>[ 27.643168] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11449 11:06:59.102164 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11451 11:06:59.120373 /lava-12925635/1/../bin/lava-tes<8>[ 27.662891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11452 11:06:59.120852 t-case
11453 11:06:59.121454 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11455 11:06:59.129842 /lava-12925635/1/../bin/lava-test-case
11456 11:06:59.136372 <8>[ 27.679969] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11457 11:06:59.137057 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11459 11:06:59.150125 /lava-12925635/1/../bin/lava-test-case
11460 11:06:59.157506 <8>[ 27.699963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11461 11:06:59.158191 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11463 11:06:59.174451 /lava-12925635/1/../bin/lava-tes<8>[ 27.716978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11464 11:06:59.174889 t-case
11465 11:06:59.175485 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11467 11:06:59.187526 /lava-12925635/1/../bin/lava-test-case
11468 11:06:59.194066 <8>[ 27.736141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11469 11:06:59.194875 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11471 11:06:59.204933 /lava-12925635/1/../bin/lava-test-case
11472 11:06:59.211785 <8>[ 27.755030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11473 11:06:59.212652 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11475 11:06:59.225229 /lava-12925635/1/../bin/lava-test-case
11476 11:06:59.231948 <8>[ 27.774892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11477 11:06:59.232632 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11479 11:06:59.248982 /lava-12925635/1/../bin/lava-tes<8>[ 27.791256] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11480 11:06:59.249415 t-case
11481 11:06:59.250010 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11483 11:06:59.265521 /lava-12925635/1/../bin/lava-test-case
11484 11:06:59.271842 <8>[ 27.814604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11485 11:06:59.272526 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11487 11:06:59.289590 /lava-12925635/1/../bin/lava-tes<8>[ 27.832147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11488 11:06:59.290196 t-case
11489 11:06:59.290815 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11491 11:07:00.303612 /lava-12925635/1/../bin/lava-test-case
11492 11:07:00.309882 <8>[ 28.853512] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11493 11:07:00.310581 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11495 11:07:01.327814 /lava-12925635/1/../bin/lava-test-case
11496 11:07:01.334469 <8>[ 29.879210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11497 11:07:01.335171 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11499 11:07:01.351113 /lava-12925635/1/../bin/lava-tes<8>[ 29.892960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11500 11:07:01.351549 t-case
11501 11:07:01.352182 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11503 11:07:01.365909 /lava-12925635/1/../bin/lava-test-case
11504 11:07:01.372199 <8>[ 29.915933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11505 11:07:01.372871 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11507 11:07:01.381798 /lava-12925635/1/../bin/lava-test-case
11508 11:07:01.388703 <8>[ 29.931687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11509 11:07:01.389395 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11511 11:07:01.408120 /lava-12925635/1/../bin/lava-tes<8>[ 29.950714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11512 11:07:01.408642 t-case
11513 11:07:01.409235 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11515 11:07:01.425144 /lava-12925635/1/../bin/lava-tes<8>[ 29.967817] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11516 11:07:01.425583 t-case
11517 11:07:01.426422 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11519 11:07:01.440724 /lava-12925635/1/../bin/lava-tes<8>[ 29.986214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11520 11:07:01.441411 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11522 11:07:01.443435 t-case
11523 11:07:01.455949 /lava-12925635/1/../bin/lava-test-case
11524 11:07:01.462922 <8>[ 30.006426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11525 11:07:01.463613 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11527 11:07:01.475105 /lava-12925635/1/../bin/lava-test-case
11528 11:07:01.481871 <8>[ 30.024733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11529 11:07:01.482557 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11531 11:07:01.499833 /lava-12925635/1/../bin/lava-tes<8>[ 30.042242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11532 11:07:01.500271 t-case
11533 11:07:01.500865 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11535 11:07:01.511175 /lava-12925635/1/../bin/lava-test-case
11536 11:07:01.517659 <8>[ 30.061357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11537 11:07:01.518335 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11539 11:07:01.535566 /lava-12925635/1/../bin/lava-tes<8>[ 30.078022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11540 11:07:01.536040 t-case
11541 11:07:01.536626 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11543 11:07:01.554273 /lava-12925635/1/../bin/lava-tes<8>[ 30.096582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11544 11:07:01.554698 t-case
11545 11:07:01.555281 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11547 11:07:01.562079 /lava-12925635/1/../bin/lava-test-case
11548 11:07:01.568406 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11550 11:07:01.571546 <8>[ 30.113638] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11551 11:07:01.587074 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11553 11:07:01.590026 /lava-12925635/1/../bin/lava-tes<8>[ 30.132818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11554 11:07:01.590459 t-case
11555 11:07:01.606061 /lava-12925635/1/../bin/lava-tes<8>[ 30.148340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11556 11:07:01.606493 t-case
11557 11:07:01.607083 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11559 11:07:01.617750 /lava-12925635/1/../bin/lava-test-case
11560 11:07:01.623846 <8>[ 30.167689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11561 11:07:01.624636 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11563 11:07:01.633498 /lava-12925635/1/../bin/lava-test-case
11564 11:07:01.639803 <8>[ 30.182603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11565 11:07:01.640481 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11567 11:07:01.652255 /lava-12925635/1/../bin/lava-test-case
11568 11:07:01.658832 <8>[ 30.203005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11569 11:07:01.659513 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11571 11:07:01.668769 /lava-12925635/1/../bin/lava-test-case
11572 11:07:01.674753 <8>[ 30.218483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11573 11:07:01.675451 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11575 11:07:01.686467 /lava-12925635/1/../bin/lava-test-case
11576 11:07:01.693208 <8>[ 30.237388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11577 11:07:01.693893 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11579 11:07:02.705738 /lava-12925635/1/../bin/lava-test-case
11580 11:07:02.712881 <8>[ 31.255891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11581 11:07:02.713631 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11583 11:07:03.728117 /lava-12925635/1/../bin/lava-test-case
11584 11:07:03.733651 <8>[ 32.278890] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11585 11:07:03.733928 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11586 11:07:03.734023 Bad test result: blocked
11587 11:07:03.744882 /lava-12925635/1/../bin/lava-test-case
11588 11:07:03.751133 <8>[ 32.294385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11589 11:07:03.751393 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11591 11:07:04.765563 /lava-12925635/1/../bin/lava-test-case
11592 11:07:04.772704 <8>[ 33.317721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11593 11:07:04.773500 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11595 11:07:04.782439 /lava-12925635/1/../bin/lava-test-case
11596 11:07:04.789176 <8>[ 33.333235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11597 11:07:04.789969 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11599 11:07:04.807342 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11601 11:07:04.810879 /lava-12925635/1/../bin/lava-tes<8>[ 33.352994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11602 11:07:04.811312 t-case
11603 11:07:04.822329 /lava-12925635/1/../bin/lava-test-case
11604 11:07:04.828373 <8>[ 33.371639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11605 11:07:04.829183 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11607 11:07:04.838774 /lava-12925635/1/../bin/lava-test-case
11608 11:07:04.845032 <8>[ 33.389803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11609 11:07:04.845724 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11611 11:07:04.859081 /lava-12925635/1/../bin/lava-test-case
11612 11:07:04.866055 <8>[ 33.408829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11613 11:07:04.866859 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11615 11:07:04.881824 /lava-12925635/1/../bin/lava-tes<8>[ 33.424675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11616 11:07:04.882366 t-case
11617 11:07:04.882975 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11619 11:07:05.894887 /lava-12925635/1/../bin/lava-test-case
11620 11:07:05.901314 <8>[ 34.447115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11621 11:07:05.902010 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11623 11:07:05.913106 /lava-12925635/1/../bin/lava-test-case
11624 11:07:05.920193 <8>[ 34.464268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11625 11:07:05.921178 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11627 11:07:06.934284 /lava-12925635/1/../bin/lava-test-case
11628 11:07:06.940964 <8>[ 35.485937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11629 11:07:06.941765 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11631 11:07:06.951906 /lava-12925635/1/../bin/lava-test-case
11632 11:07:06.957629 <8>[ 35.501482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11633 11:07:06.958633 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11635 11:07:07.971832 /lava-12925635/1/../bin/lava-test-case
11636 11:07:07.978296 <8>[ 36.523789] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11637 11:07:07.978568 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11639 11:07:07.987759 /lava-12925635/1/../bin/lava-test-case
11640 11:07:07.994344 <8>[ 36.539102] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11641 11:07:07.994618 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11643 11:07:09.009548 /lava-12925635/1/../bin/lava-test-case
11644 11:07:09.016121 <8>[ 37.560014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11645 11:07:09.017042 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11647 11:07:09.035647 /lava-12925635/1/../bin/lava-tes<8>[ 37.579189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11648 11:07:09.036236 t-case
11649 11:07:09.036870 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11651 11:07:09.047208 /lava-12925635/1/../bin/lava-test-case
11652 11:07:09.054179 <8>[ 37.597962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11653 11:07:09.055031 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11655 11:07:09.064115 /lava-12925635/1/../bin/lava-test-case
11656 11:07:09.070884 <8>[ 37.614877] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11657 11:07:09.071781 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11659 11:07:09.079650 /lava-12925635/1/../bin/lava-test-case
11660 11:07:09.085978 <8>[ 37.630155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11661 11:07:09.086826 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11663 11:07:09.096572 /lava-12925635/1/../bin/lava-test-case
11664 11:07:09.103076 <8>[ 37.647987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11665 11:07:09.103984 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11667 11:07:09.119748 /lava-12925635/1/../bin/lava-tes<8>[ 37.662963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11668 11:07:09.120346 t-case
11669 11:07:09.121005 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11671 11:07:09.140562 /lava-12925635/1/../bin/lava-tes<8>[ 37.683542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11672 11:07:09.141135 t-case
11673 11:07:09.141784 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11675 11:07:09.156657 /lava-12925635/1/../bin/lava-tes<8>[ 37.699726] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11676 11:07:09.157138 t-case
11677 11:07:09.157736 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11679 11:07:09.170104 /lava-12925635/1/../bin/lava-test-case
11680 11:07:09.176223 <8>[ 37.721823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11681 11:07:09.176912 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11683 11:07:09.181883 + set +x
11684 11:07:09.185457 Received signal: <ENDRUN> 1_bootrr 12925635_1.5.2.3.5
11685 11:07:09.186001 Ending use of test pattern.
11686 11:07:09.186351 Ending test lava.1_bootrr (12925635_1.5.2.3.5), duration 20.51
11688 11:07:09.187934 <8>[ 37.732423] <LAVA_SIGNAL_ENDRUN 1_bootrr 12925635_1.5.2.3.5>
11689 11:07:09.188552 ok: lava_test_shell seems to have completed
11690 11:07:09.193454 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11691 11:07:09.194153 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11692 11:07:09.194587 end: 4 lava-test-retry (duration 00:00:21) [common]
11693 11:07:09.195043 start: 5 finalize (timeout 00:07:42) [common]
11694 11:07:09.195482 start: 5.1 power-off (timeout 00:00:30) [common]
11695 11:07:09.196266 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11696 11:07:09.316236 >> Command sent successfully.
11697 11:07:09.319929 Returned 0 in 0 seconds
11698 11:07:09.420812 end: 5.1 power-off (duration 00:00:00) [common]
11700 11:07:09.422394 start: 5.2 read-feedback (timeout 00:07:42) [common]
11702 11:07:09.424744 Listened to connection for namespace 'common' for up to 1s
11703 11:07:10.424084 Finalising connection for namespace 'common'
11704 11:07:10.424979 Disconnecting from shell: Finalise
11705 11:07:10.425548 / #
11706 11:07:10.526653 end: 5.2 read-feedback (duration 00:00:01) [common]
11707 11:07:10.527504 end: 5 finalize (duration 00:00:01) [common]
11708 11:07:10.528210 Cleaning after the job
11709 11:07:10.528811 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925635/tftp-deploy-3ozrlg70/ramdisk
11710 11:07:10.544707 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925635/tftp-deploy-3ozrlg70/kernel
11711 11:07:10.573319 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925635/tftp-deploy-3ozrlg70/dtb
11712 11:07:10.573659 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925635/tftp-deploy-3ozrlg70/modules
11713 11:07:10.584850 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12925635
11714 11:07:10.633752 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12925635
11715 11:07:10.633930 Job finished correctly