Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 37
- Boot result: PASS
- Errors: 1
- Warnings: 1
- Kernel Warnings: 17
1 11:04:14.706789 lava-dispatcher, installed at version: 2024.01
2 11:04:14.707031 start: 0 validate
3 11:04:14.707163 Start time: 2024-03-03 11:04:14.707154+00:00 (UTC)
4 11:04:14.707282 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:04:14.707448 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20240129.0%2Farm64%2Finitrd.cpio.gz exists
6 11:04:14.974136 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:04:14.974305 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:04:28.473498 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:04:28.473656 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:04:28.740937 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:04:28.741109 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20240129.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:04:29.270410 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:04:29.270584 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:04:32.272441 validate duration: 17.57
16 11:04:32.272691 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:04:32.272786 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:04:32.272870 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:04:32.273015 Not decompressing ramdisk as can be used compressed.
20 11:04:32.273135 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20240129.0/arm64/initrd.cpio.gz
21 11:04:32.273202 saving as /var/lib/lava/dispatcher/tmp/12925662/tftp-deploy-40xl1zo3/ramdisk/initrd.cpio.gz
22 11:04:32.273265 total size: 4663052 (4 MB)
23 11:04:32.539744 progress 0 % (0 MB)
24 11:04:32.541997 progress 5 % (0 MB)
25 11:04:32.544048 progress 10 % (0 MB)
26 11:04:32.546109 progress 15 % (0 MB)
27 11:04:32.548110 progress 20 % (0 MB)
28 11:04:32.550054 progress 25 % (1 MB)
29 11:04:32.552168 progress 30 % (1 MB)
30 11:04:32.554093 progress 35 % (1 MB)
31 11:04:32.556078 progress 40 % (1 MB)
32 11:04:32.558341 progress 45 % (2 MB)
33 11:04:32.560266 progress 50 % (2 MB)
34 11:04:32.562167 progress 55 % (2 MB)
35 11:04:32.564227 progress 60 % (2 MB)
36 11:04:32.566135 progress 65 % (2 MB)
37 11:04:32.568055 progress 70 % (3 MB)
38 11:04:32.569989 progress 75 % (3 MB)
39 11:04:32.572031 progress 80 % (3 MB)
40 11:04:32.573923 progress 85 % (3 MB)
41 11:04:32.576093 progress 90 % (4 MB)
42 11:04:32.578107 progress 95 % (4 MB)
43 11:04:32.580061 progress 100 % (4 MB)
44 11:04:32.580267 4 MB downloaded in 0.31 s (14.49 MB/s)
45 11:04:32.580477 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:04:32.580854 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:04:32.580973 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:04:32.581106 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:04:32.581293 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:04:32.581391 saving as /var/lib/lava/dispatcher/tmp/12925662/tftp-deploy-40xl1zo3/kernel/Image
52 11:04:32.581477 total size: 51599872 (49 MB)
53 11:04:32.581585 No compression specified
54 11:04:32.583124 progress 0 % (0 MB)
55 11:04:32.604955 progress 5 % (2 MB)
56 11:04:32.627699 progress 10 % (4 MB)
57 11:04:32.650259 progress 15 % (7 MB)
58 11:04:32.672422 progress 20 % (9 MB)
59 11:04:32.689003 progress 25 % (12 MB)
60 11:04:32.702708 progress 30 % (14 MB)
61 11:04:32.716514 progress 35 % (17 MB)
62 11:04:32.730115 progress 40 % (19 MB)
63 11:04:32.743895 progress 45 % (22 MB)
64 11:04:32.757700 progress 50 % (24 MB)
65 11:04:32.771979 progress 55 % (27 MB)
66 11:04:32.785859 progress 60 % (29 MB)
67 11:04:32.799583 progress 65 % (32 MB)
68 11:04:32.813113 progress 70 % (34 MB)
69 11:04:32.826699 progress 75 % (36 MB)
70 11:04:32.840214 progress 80 % (39 MB)
71 11:04:32.853771 progress 85 % (41 MB)
72 11:04:32.867355 progress 90 % (44 MB)
73 11:04:32.880498 progress 95 % (46 MB)
74 11:04:32.894633 progress 100 % (49 MB)
75 11:04:32.894917 49 MB downloaded in 0.31 s (157.00 MB/s)
76 11:04:32.895072 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:04:32.895329 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:04:32.895460 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:04:32.895589 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:04:32.895770 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:04:32.895855 saving as /var/lib/lava/dispatcher/tmp/12925662/tftp-deploy-40xl1zo3/dtb/mt8192-asurada-spherion-r0.dtb
83 11:04:32.895929 total size: 47278 (0 MB)
84 11:04:32.896024 No compression specified
85 11:04:32.897170 progress 69 % (0 MB)
86 11:04:32.897572 progress 100 % (0 MB)
87 11:04:32.897792 0 MB downloaded in 0.00 s (24.25 MB/s)
88 11:04:32.898019 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:04:32.898274 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:04:32.898362 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:04:32.898474 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:04:32.898611 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20240129.0/arm64/full.rootfs.tar.xz
94 11:04:32.898705 saving as /var/lib/lava/dispatcher/tmp/12925662/tftp-deploy-40xl1zo3/nfsrootfs/full.rootfs.tar
95 11:04:32.898772 total size: 125310928 (119 MB)
96 11:04:32.898836 Using unxz to decompress xz
97 11:04:32.903306 progress 0 % (0 MB)
98 11:04:33.256871 progress 5 % (6 MB)
99 11:04:33.606678 progress 10 % (11 MB)
100 11:04:33.971811 progress 15 % (17 MB)
101 11:04:34.171699 progress 20 % (23 MB)
102 11:04:34.352041 progress 25 % (29 MB)
103 11:04:34.723233 progress 30 % (35 MB)
104 11:04:35.089894 progress 35 % (41 MB)
105 11:04:35.587710 progress 40 % (47 MB)
106 11:04:36.007274 progress 45 % (53 MB)
107 11:04:36.460112 progress 50 % (59 MB)
108 11:04:36.826143 progress 55 % (65 MB)
109 11:04:37.205625 progress 60 % (71 MB)
110 11:04:37.573679 progress 65 % (77 MB)
111 11:04:37.960143 progress 70 % (83 MB)
112 11:04:38.369012 progress 75 % (89 MB)
113 11:04:38.859256 progress 80 % (95 MB)
114 11:04:39.299233 progress 85 % (101 MB)
115 11:04:39.592686 progress 90 % (107 MB)
116 11:04:39.941805 progress 95 % (113 MB)
117 11:04:40.387830 progress 100 % (119 MB)
118 11:04:40.394507 119 MB downloaded in 7.50 s (15.94 MB/s)
119 11:04:40.394775 end: 1.4.1 http-download (duration 00:00:07) [common]
121 11:04:40.395182 end: 1.4 download-retry (duration 00:00:07) [common]
122 11:04:40.395337 start: 1.5 download-retry (timeout 00:09:52) [common]
123 11:04:40.395495 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 11:04:40.395724 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:04:40.395844 saving as /var/lib/lava/dispatcher/tmp/12925662/tftp-deploy-40xl1zo3/modules/modules.tar
126 11:04:40.395958 total size: 8628476 (8 MB)
127 11:04:40.396071 Using unxz to decompress xz
128 11:04:40.665716 progress 0 % (0 MB)
129 11:04:40.686631 progress 5 % (0 MB)
130 11:04:40.712905 progress 10 % (0 MB)
131 11:04:40.739195 progress 15 % (1 MB)
132 11:04:40.764357 progress 20 % (1 MB)
133 11:04:40.789314 progress 25 % (2 MB)
134 11:04:40.813840 progress 30 % (2 MB)
135 11:04:40.842915 progress 35 % (2 MB)
136 11:04:40.868644 progress 40 % (3 MB)
137 11:04:40.895319 progress 45 % (3 MB)
138 11:04:40.923251 progress 50 % (4 MB)
139 11:04:40.956346 progress 55 % (4 MB)
140 11:04:40.980862 progress 60 % (4 MB)
141 11:04:41.008052 progress 65 % (5 MB)
142 11:04:41.036213 progress 70 % (5 MB)
143 11:04:41.062993 progress 75 % (6 MB)
144 11:04:41.090270 progress 80 % (6 MB)
145 11:04:41.115852 progress 85 % (7 MB)
146 11:04:41.141171 progress 90 % (7 MB)
147 11:04:41.172571 progress 95 % (7 MB)
148 11:04:41.202737 progress 100 % (8 MB)
149 11:04:41.208043 8 MB downloaded in 0.81 s (10.13 MB/s)
150 11:04:41.208424 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:04:41.208842 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:04:41.208981 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 11:04:41.209126 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 11:04:43.553016 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12925662/extract-nfsrootfs-7g5anr9b
156 11:04:43.553227 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 11:04:43.553330 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 11:04:43.553502 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b
159 11:04:43.553633 makedir: /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin
160 11:04:43.553735 makedir: /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/tests
161 11:04:43.553835 makedir: /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/results
162 11:04:43.553936 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-add-keys
163 11:04:43.554078 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-add-sources
164 11:04:43.554209 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-background-process-start
165 11:04:43.554338 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-background-process-stop
166 11:04:43.554464 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-common-functions
167 11:04:43.554593 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-echo-ipv4
168 11:04:43.554720 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-install-packages
169 11:04:43.554847 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-installed-packages
170 11:04:43.554973 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-os-build
171 11:04:43.555099 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-probe-channel
172 11:04:43.555224 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-probe-ip
173 11:04:43.555347 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-target-ip
174 11:04:43.555509 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-target-mac
175 11:04:43.555634 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-target-storage
176 11:04:43.555763 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-test-case
177 11:04:43.555891 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-test-event
178 11:04:43.556018 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-test-feedback
179 11:04:43.556142 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-test-raise
180 11:04:43.556267 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-test-reference
181 11:04:43.556392 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-test-runner
182 11:04:43.556517 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-test-set
183 11:04:43.556652 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-test-shell
184 11:04:43.556779 Updating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-install-packages (oe)
185 11:04:43.556934 Updating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/bin/lava-installed-packages (oe)
186 11:04:43.557060 Creating /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/environment
187 11:04:43.557156 LAVA metadata
188 11:04:43.557227 - LAVA_JOB_ID=12925662
189 11:04:43.557291 - LAVA_DISPATCHER_IP=192.168.201.1
190 11:04:43.557397 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
191 11:04:43.557463 skipped lava-vland-overlay
192 11:04:43.557553 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 11:04:43.557648 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
194 11:04:43.557708 skipped lava-multinode-overlay
195 11:04:43.557780 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 11:04:43.557858 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
197 11:04:43.557931 Loading test definitions
198 11:04:43.558019 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
199 11:04:43.558089 Using /lava-12925662 at stage 0
200 11:04:43.558445 uuid=12925662_1.6.2.3.1 testdef=None
201 11:04:43.558536 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 11:04:43.558622 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
203 11:04:43.559146 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 11:04:43.559395 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
206 11:04:43.560076 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 11:04:43.560314 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
209 11:04:43.560946 runner path: /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/0/tests/0_dmesg test_uuid 12925662_1.6.2.3.1
210 11:04:43.561121 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 11:04:43.561346 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:49) [common]
213 11:04:43.561419 Using /lava-12925662 at stage 1
214 11:04:43.561735 uuid=12925662_1.6.2.3.5 testdef=None
215 11:04:43.561824 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 11:04:43.561909 start: 1.6.2.3.6 test-overlay (timeout 00:09:49) [common]
217 11:04:43.562384 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 11:04:43.562602 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:49) [common]
220 11:04:43.563268 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 11:04:43.563539 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:49) [common]
223 11:04:43.564178 runner path: /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/1/tests/1_bootrr test_uuid 12925662_1.6.2.3.5
224 11:04:43.564338 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 11:04:43.564542 Creating lava-test-runner.conf files
227 11:04:43.564606 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/0 for stage 0
228 11:04:43.564698 - 0_dmesg
229 11:04:43.564779 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12925662/lava-overlay-83kzdg4b/lava-12925662/1 for stage 1
230 11:04:43.564871 - 1_bootrr
231 11:04:43.564969 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 11:04:43.565053 start: 1.6.2.4 compress-overlay (timeout 00:09:49) [common]
233 11:04:43.573176 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 11:04:43.573325 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:49) [common]
235 11:04:43.573416 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 11:04:43.573507 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 11:04:43.573595 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:49) [common]
238 11:04:43.697521 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 11:04:43.697961 start: 1.6.4 extract-modules (timeout 00:09:49) [common]
240 11:04:43.698075 extracting modules file /var/lib/lava/dispatcher/tmp/12925662/tftp-deploy-40xl1zo3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925662/extract-nfsrootfs-7g5anr9b
241 11:04:43.926180 extracting modules file /var/lib/lava/dispatcher/tmp/12925662/tftp-deploy-40xl1zo3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925662/extract-overlay-ramdisk-8mzd6720/ramdisk
242 11:04:44.158558 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 11:04:44.158730 start: 1.6.5 apply-overlay-tftp (timeout 00:09:48) [common]
244 11:04:44.158821 [common] Applying overlay to NFS
245 11:04:44.158893 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925662/compress-overlay-lsqn7hkv/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12925662/extract-nfsrootfs-7g5anr9b
246 11:04:44.167490 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 11:04:44.167643 start: 1.6.6 configure-preseed-file (timeout 00:09:48) [common]
248 11:04:44.167745 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 11:04:44.167834 start: 1.6.7 compress-ramdisk (timeout 00:09:48) [common]
250 11:04:44.167918 Building ramdisk /var/lib/lava/dispatcher/tmp/12925662/extract-overlay-ramdisk-8mzd6720/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12925662/extract-overlay-ramdisk-8mzd6720/ramdisk
251 11:04:44.504011 >> 119441 blocks
252 11:04:46.641841 rename /var/lib/lava/dispatcher/tmp/12925662/extract-overlay-ramdisk-8mzd6720/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12925662/tftp-deploy-40xl1zo3/ramdisk/ramdisk.cpio.gz
253 11:04:46.642446 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 11:04:46.642649 start: 1.6.8 prepare-kernel (timeout 00:09:46) [common]
255 11:04:46.642826 start: 1.6.8.1 prepare-fit (timeout 00:09:46) [common]
256 11:04:46.643012 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12925662/tftp-deploy-40xl1zo3/kernel/Image'
257 11:05:00.732481 Returned 0 in 14 seconds
258 11:05:00.833128 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12925662/tftp-deploy-40xl1zo3/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12925662/tftp-deploy-40xl1zo3/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12925662/tftp-deploy-40xl1zo3/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12925662/tftp-deploy-40xl1zo3/kernel/image.itb
259 11:05:01.208244 output: FIT description: Kernel Image image with one or more FDT blobs
260 11:05:01.208615 output: Created: Sun Mar 3 11:05:01 2024
261 11:05:01.208694 output: Image 0 (kernel-1)
262 11:05:01.208776 output: Description:
263 11:05:01.208855 output: Created: Sun Mar 3 11:05:01 2024
264 11:05:01.208918 output: Type: Kernel Image
265 11:05:01.208980 output: Compression: lzma compressed
266 11:05:01.209039 output: Data Size: 12057697 Bytes = 11775.09 KiB = 11.50 MiB
267 11:05:01.209102 output: Architecture: AArch64
268 11:05:01.209160 output: OS: Linux
269 11:05:01.209218 output: Load Address: 0x00000000
270 11:05:01.209276 output: Entry Point: 0x00000000
271 11:05:01.209330 output: Hash algo: crc32
272 11:05:01.209385 output: Hash value: cf43f4f3
273 11:05:01.209441 output: Image 1 (fdt-1)
274 11:05:01.209496 output: Description: mt8192-asurada-spherion-r0
275 11:05:01.209550 output: Created: Sun Mar 3 11:05:01 2024
276 11:05:01.209604 output: Type: Flat Device Tree
277 11:05:01.209657 output: Compression: uncompressed
278 11:05:01.209710 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 11:05:01.209763 output: Architecture: AArch64
280 11:05:01.209816 output: Hash algo: crc32
281 11:05:01.209868 output: Hash value: cc4352de
282 11:05:01.209921 output: Image 2 (ramdisk-1)
283 11:05:01.209974 output: Description: unavailable
284 11:05:01.210026 output: Created: Sun Mar 3 11:05:01 2024
285 11:05:01.210078 output: Type: RAMDisk Image
286 11:05:01.210132 output: Compression: Unknown Compression
287 11:05:01.210184 output: Data Size: 17798518 Bytes = 17381.37 KiB = 16.97 MiB
288 11:05:01.210237 output: Architecture: AArch64
289 11:05:01.210289 output: OS: Linux
290 11:05:01.210342 output: Load Address: unavailable
291 11:05:01.210395 output: Entry Point: unavailable
292 11:05:01.210447 output: Hash algo: crc32
293 11:05:01.210499 output: Hash value: 09de2058
294 11:05:01.210551 output: Default Configuration: 'conf-1'
295 11:05:01.210603 output: Configuration 0 (conf-1)
296 11:05:01.210655 output: Description: mt8192-asurada-spherion-r0
297 11:05:01.210708 output: Kernel: kernel-1
298 11:05:01.210760 output: Init Ramdisk: ramdisk-1
299 11:05:01.210813 output: FDT: fdt-1
300 11:05:01.210865 output: Loadables: kernel-1
301 11:05:01.210917 output:
302 11:05:01.211129 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
303 11:05:01.211232 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
304 11:05:01.211341 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
305 11:05:01.211480 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:31) [common]
306 11:05:01.211562 No LXC device requested
307 11:05:01.211643 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 11:05:01.211732 start: 1.8 deploy-device-env (timeout 00:09:31) [common]
309 11:05:01.211816 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 11:05:01.211883 Checking files for TFTP limit of 4294967296 bytes.
311 11:05:01.212428 end: 1 tftp-deploy (duration 00:00:29) [common]
312 11:05:01.212549 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 11:05:01.212643 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 11:05:01.212803 substitutions:
315 11:05:01.212869 - {DTB}: 12925662/tftp-deploy-40xl1zo3/dtb/mt8192-asurada-spherion-r0.dtb
316 11:05:01.212935 - {INITRD}: 12925662/tftp-deploy-40xl1zo3/ramdisk/ramdisk.cpio.gz
317 11:05:01.212995 - {KERNEL}: 12925662/tftp-deploy-40xl1zo3/kernel/Image
318 11:05:01.213053 - {LAVA_MAC}: None
319 11:05:01.213112 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12925662/extract-nfsrootfs-7g5anr9b
320 11:05:01.213168 - {NFS_SERVER_IP}: 192.168.201.1
321 11:05:01.213223 - {PRESEED_CONFIG}: None
322 11:05:01.213279 - {PRESEED_LOCAL}: None
323 11:05:01.213334 - {RAMDISK}: 12925662/tftp-deploy-40xl1zo3/ramdisk/ramdisk.cpio.gz
324 11:05:01.213390 - {ROOT_PART}: None
325 11:05:01.213445 - {ROOT}: None
326 11:05:01.213499 - {SERVER_IP}: 192.168.201.1
327 11:05:01.213552 - {TEE}: None
328 11:05:01.213606 Parsed boot commands:
329 11:05:01.213677 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 11:05:01.213955 Parsed boot commands: tftpboot 192.168.201.1 12925662/tftp-deploy-40xl1zo3/kernel/image.itb 12925662/tftp-deploy-40xl1zo3/kernel/cmdline
331 11:05:01.214045 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 11:05:01.214135 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 11:05:01.214228 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 11:05:01.214313 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 11:05:01.214384 Not connected, no need to disconnect.
336 11:05:01.214460 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 11:05:01.214544 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 11:05:01.214616 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
339 11:05:01.219166 Setting prompt string to ['lava-test: # ']
340 11:05:01.219682 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 11:05:01.219847 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 11:05:01.219978 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 11:05:01.220105 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 11:05:01.220400 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
345 11:05:06.352334 >> Command sent successfully.
346 11:05:06.354760 Returned 0 in 5 seconds
347 11:05:06.455180 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 11:05:06.455657 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 11:05:06.455792 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 11:05:06.455923 Setting prompt string to 'Starting depthcharge on Spherion...'
352 11:05:06.456027 Changing prompt to 'Starting depthcharge on Spherion...'
353 11:05:06.456162 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 11:05:06.456549 [Enter `^Ec?' for help]
355 11:05:06.629614
356 11:05:06.629799
357 11:05:06.629960 F0: 102B 0000
358 11:05:06.630119
359 11:05:06.630226 F3: 1001 0000 [0200]
360 11:05:06.632839
361 11:05:06.632960 F3: 1001 0000
362 11:05:06.633096
363 11:05:06.633215 F7: 102D 0000
364 11:05:06.633315
365 11:05:06.636249 F1: 0000 0000
366 11:05:06.636400
367 11:05:06.636487 V0: 0000 0000 [0001]
368 11:05:06.636610
369 11:05:06.639244 00: 0007 8000
370 11:05:06.639354
371 11:05:06.639463 01: 0000 0000
372 11:05:06.639585
373 11:05:06.642679 BP: 0C00 0209 [0000]
374 11:05:06.642795
375 11:05:06.642916 G0: 1182 0000
376 11:05:06.643044
377 11:05:06.646348 EC: 0000 0021 [4000]
378 11:05:06.646480
379 11:05:06.646606 S7: 0000 0000 [0000]
380 11:05:06.646739
381 11:05:06.650620 CC: 0000 0000 [0001]
382 11:05:06.650742
383 11:05:06.650837 T0: 0000 0040 [010F]
384 11:05:06.650933
385 11:05:06.651022 Jump to BL
386 11:05:06.651112
387 11:05:06.676098
388 11:05:06.676277
389 11:05:06.676382
390 11:05:06.683415 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 11:05:06.686984 ARM64: Exception handlers installed.
392 11:05:06.690637 ARM64: Testing exception
393 11:05:06.694135 ARM64: Done test exception
394 11:05:06.700524 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 11:05:06.710509 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 11:05:06.717781 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 11:05:06.727330 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 11:05:06.733967 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 11:05:06.744226 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 11:05:06.754838 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 11:05:06.761193 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 11:05:06.779208 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 11:05:06.782468 WDT: Last reset was cold boot
404 11:05:06.786385 SPI1(PAD0) initialized at 2873684 Hz
405 11:05:06.789325 SPI5(PAD0) initialized at 992727 Hz
406 11:05:06.792633 VBOOT: Loading verstage.
407 11:05:06.799244 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 11:05:06.802356 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 11:05:06.806085 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 11:05:06.809165 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 11:05:06.816954 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 11:05:06.823436 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 11:05:06.834172 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 11:05:06.834358
415 11:05:06.834469
416 11:05:06.844060 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 11:05:06.847353 ARM64: Exception handlers installed.
418 11:05:06.851163 ARM64: Testing exception
419 11:05:06.851296 ARM64: Done test exception
420 11:05:06.857891 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 11:05:06.861282 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:05:06.875283 Probing TPM: . done!
423 11:05:06.875480 TPM ready after 0 ms
424 11:05:06.884514 Connected to device vid:did:rid of 1ae0:0028:00
425 11:05:06.890721 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
426 11:05:06.948286 Initialized TPM device CR50 revision 0
427 11:05:06.958020 tlcl_send_startup: Startup return code is 0
428 11:05:06.958211 TPM: setup succeeded
429 11:05:06.969588 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 11:05:06.978561 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 11:05:06.991039 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 11:05:06.999413 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 11:05:07.003208 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 11:05:07.010247 in-header: 03 07 00 00 08 00 00 00
435 11:05:07.013262 in-data: aa e4 47 04 13 02 00 00
436 11:05:07.016663 Chrome EC: UHEPI supported
437 11:05:07.024205 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 11:05:07.027588 in-header: 03 95 00 00 08 00 00 00
439 11:05:07.031552 in-data: 18 20 20 08 00 00 00 00
440 11:05:07.031685 Phase 1
441 11:05:07.035032 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 11:05:07.042392 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 11:05:07.046267 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 11:05:07.050281 Recovery requested (1009000e)
445 11:05:07.058734 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 11:05:07.063678 tlcl_extend: response is 0
447 11:05:07.073160 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 11:05:07.078539 tlcl_extend: response is 0
449 11:05:07.085529 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 11:05:07.105528 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 11:05:07.112347 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 11:05:07.112519
453 11:05:07.112626
454 11:05:07.122487 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 11:05:07.125501 ARM64: Exception handlers installed.
456 11:05:07.128921 ARM64: Testing exception
457 11:05:07.129045 ARM64: Done test exception
458 11:05:07.150780 pmic_efuse_setting: Set efuses in 11 msecs
459 11:05:07.154158 pmwrap_interface_init: Select PMIF_VLD_RDY
460 11:05:07.160868 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 11:05:07.164321 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 11:05:07.171199 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 11:05:07.174802 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 11:05:07.178552 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 11:05:07.185506 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 11:05:07.189942 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 11:05:07.193452 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 11:05:07.196662 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 11:05:07.204600 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 11:05:07.207965 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 11:05:07.212400 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 11:05:07.215812 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 11:05:07.223643 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 11:05:07.230574 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 11:05:07.234306 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 11:05:07.241587 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 11:05:07.245115 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 11:05:07.252162 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 11:05:07.256263 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 11:05:07.263228 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 11:05:07.267170 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 11:05:07.274575 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 11:05:07.278301 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 11:05:07.285769 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 11:05:07.289389 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 11:05:07.296938 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 11:05:07.300744 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 11:05:07.304398 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 11:05:07.311520 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 11:05:07.315358 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 11:05:07.318912 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 11:05:07.325876 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 11:05:07.329629 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 11:05:07.333211 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 11:05:07.340866 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 11:05:07.344656 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 11:05:07.348164 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 11:05:07.355500 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 11:05:07.359101 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 11:05:07.362806 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 11:05:07.366379 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 11:05:07.373232 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 11:05:07.377033 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 11:05:07.380469 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 11:05:07.384171 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 11:05:07.387973 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 11:05:07.394913 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 11:05:07.398625 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 11:05:07.402119 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 11:05:07.406220 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 11:05:07.413279 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 11:05:07.420796 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 11:05:07.428360 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 11:05:07.435603 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 11:05:07.442571 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 11:05:07.450326 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 11:05:07.453587 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 11:05:07.457621 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 11:05:07.465025 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x23
520 11:05:07.468331 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 11:05:07.476339 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
522 11:05:07.479754 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 11:05:07.488475 [RTC]rtc_get_frequency_meter,154: input=15, output=853
524 11:05:07.499109 [RTC]rtc_get_frequency_meter,154: input=7, output=724
525 11:05:07.507710 [RTC]rtc_get_frequency_meter,154: input=11, output=789
526 11:05:07.517045 [RTC]rtc_get_frequency_meter,154: input=13, output=821
527 11:05:07.526751 [RTC]rtc_get_frequency_meter,154: input=12, output=805
528 11:05:07.536049 [RTC]rtc_get_frequency_meter,154: input=11, output=789
529 11:05:07.545643 [RTC]rtc_get_frequency_meter,154: input=12, output=806
530 11:05:07.550007 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
531 11:05:07.556810 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
532 11:05:07.560495 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 11:05:07.563987 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
534 11:05:07.567878 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 11:05:07.572214 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
536 11:05:07.575799 ADC[4]: Raw value=904064 ID=7
537 11:05:07.578927 ADC[3]: Raw value=213916 ID=1
538 11:05:07.579030 RAM Code: 0x71
539 11:05:07.582449 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 11:05:07.590296 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 11:05:07.597401 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 11:05:07.605028 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 11:05:07.605212 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 11:05:07.609513 in-header: 03 07 00 00 08 00 00 00
545 11:05:07.613036 in-data: aa e4 47 04 13 02 00 00
546 11:05:07.616741 Chrome EC: UHEPI supported
547 11:05:07.623889 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 11:05:07.627063 in-header: 03 95 00 00 08 00 00 00
549 11:05:07.631265 in-data: 18 20 20 08 00 00 00 00
550 11:05:07.634373 MRC: failed to locate region type 0.
551 11:05:07.642279 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 11:05:07.642420 DRAM-K: Running full calibration
553 11:05:07.649891 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 11:05:07.652896 header.status = 0x0
555 11:05:07.656918 header.version = 0x6 (expected: 0x6)
556 11:05:07.657031 header.size = 0xd00 (expected: 0xd00)
557 11:05:07.660609 header.flags = 0x0
558 11:05:07.667636 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 11:05:07.684648 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
560 11:05:07.692999 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 11:05:07.693147 dram_init: ddr_geometry: 2
562 11:05:07.695801 [EMI] MDL number = 2
563 11:05:07.699535 [EMI] Get MDL freq = 0
564 11:05:07.699635 dram_init: ddr_type: 0
565 11:05:07.703498 is_discrete_lpddr4: 1
566 11:05:07.706682 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 11:05:07.706780
568 11:05:07.706849
569 11:05:07.706934 [Bian_co] ETT version 0.0.0.1
570 11:05:07.714519 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 11:05:07.714642
572 11:05:07.717634 dramc_set_vcore_voltage set vcore to 650000
573 11:05:07.717729 Read voltage for 800, 4
574 11:05:07.721518 Vio18 = 0
575 11:05:07.721625 Vcore = 650000
576 11:05:07.721696 Vdram = 0
577 11:05:07.721759 Vddq = 0
578 11:05:07.725318 Vmddr = 0
579 11:05:07.725413 dram_init: config_dvfs: 1
580 11:05:07.732077 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 11:05:07.735574 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 11:05:07.738724 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
583 11:05:07.745671 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
584 11:05:07.749303 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
585 11:05:07.753105 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
586 11:05:07.753239 MEM_TYPE=3, freq_sel=18
587 11:05:07.756352 sv_algorithm_assistance_LP4_1600
588 11:05:07.760132 ============ PULL DRAM RESETB DOWN ============
589 11:05:07.763927 ========== PULL DRAM RESETB DOWN end =========
590 11:05:07.771624 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 11:05:07.774486 ===================================
592 11:05:07.774592 LPDDR4 DRAM CONFIGURATION
593 11:05:07.777877 ===================================
594 11:05:07.781106 EX_ROW_EN[0] = 0x0
595 11:05:07.781232 EX_ROW_EN[1] = 0x0
596 11:05:07.784256 LP4Y_EN = 0x0
597 11:05:07.784347 WORK_FSP = 0x0
598 11:05:07.787587 WL = 0x2
599 11:05:07.790800 RL = 0x2
600 11:05:07.790893 BL = 0x2
601 11:05:07.794324 RPST = 0x0
602 11:05:07.794415 RD_PRE = 0x0
603 11:05:07.798354 WR_PRE = 0x1
604 11:05:07.798446 WR_PST = 0x0
605 11:05:07.801266 DBI_WR = 0x0
606 11:05:07.801356 DBI_RD = 0x0
607 11:05:07.804270 OTF = 0x1
608 11:05:07.807621 ===================================
609 11:05:07.811244 ===================================
610 11:05:07.811379 ANA top config
611 11:05:07.814738 ===================================
612 11:05:07.817894 DLL_ASYNC_EN = 0
613 11:05:07.821096 ALL_SLAVE_EN = 1
614 11:05:07.821204 NEW_RANK_MODE = 1
615 11:05:07.824470 DLL_IDLE_MODE = 1
616 11:05:07.828009 LP45_APHY_COMB_EN = 1
617 11:05:07.830799 TX_ODT_DIS = 1
618 11:05:07.830907 NEW_8X_MODE = 1
619 11:05:07.834625 ===================================
620 11:05:07.837656 ===================================
621 11:05:07.840710 data_rate = 1600
622 11:05:07.843897 CKR = 1
623 11:05:07.847390 DQ_P2S_RATIO = 8
624 11:05:07.850819 ===================================
625 11:05:07.854176 CA_P2S_RATIO = 8
626 11:05:07.857791 DQ_CA_OPEN = 0
627 11:05:07.857935 DQ_SEMI_OPEN = 0
628 11:05:07.861425 CA_SEMI_OPEN = 0
629 11:05:07.864619 CA_FULL_RATE = 0
630 11:05:07.868097 DQ_CKDIV4_EN = 1
631 11:05:07.871653 CA_CKDIV4_EN = 1
632 11:05:07.871804 CA_PREDIV_EN = 0
633 11:05:07.874570 PH8_DLY = 0
634 11:05:07.877590 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 11:05:07.880945 DQ_AAMCK_DIV = 4
636 11:05:07.884616 CA_AAMCK_DIV = 4
637 11:05:07.887695 CA_ADMCK_DIV = 4
638 11:05:07.887835 DQ_TRACK_CA_EN = 0
639 11:05:07.891079 CA_PICK = 800
640 11:05:07.894395 CA_MCKIO = 800
641 11:05:07.898374 MCKIO_SEMI = 0
642 11:05:07.901418 PLL_FREQ = 3068
643 11:05:07.905637 DQ_UI_PI_RATIO = 32
644 11:05:07.905739 CA_UI_PI_RATIO = 0
645 11:05:07.909248 ===================================
646 11:05:07.912514 ===================================
647 11:05:07.916198 memory_type:LPDDR4
648 11:05:07.920001 GP_NUM : 10
649 11:05:07.920105 SRAM_EN : 1
650 11:05:07.923056 MD32_EN : 0
651 11:05:07.926518 ===================================
652 11:05:07.926682 [ANA_INIT] >>>>>>>>>>>>>>
653 11:05:07.930626 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 11:05:07.934105 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 11:05:07.937320 ===================================
656 11:05:07.940728 data_rate = 1600,PCW = 0X7600
657 11:05:07.943964 ===================================
658 11:05:07.947605 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 11:05:07.950556 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 11:05:07.957520 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 11:05:07.961170 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 11:05:07.964279 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 11:05:07.967249 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 11:05:07.970534 [ANA_INIT] flow start
665 11:05:07.974050 [ANA_INIT] PLL >>>>>>>>
666 11:05:07.974148 [ANA_INIT] PLL <<<<<<<<
667 11:05:07.977469 [ANA_INIT] MIDPI >>>>>>>>
668 11:05:07.980425 [ANA_INIT] MIDPI <<<<<<<<
669 11:05:07.983983 [ANA_INIT] DLL >>>>>>>>
670 11:05:07.984093 [ANA_INIT] flow end
671 11:05:07.988076 ============ LP4 DIFF to SE enter ============
672 11:05:07.994335 ============ LP4 DIFF to SE exit ============
673 11:05:07.994516 [ANA_INIT] <<<<<<<<<<<<<
674 11:05:07.997212 [Flow] Enable top DCM control >>>>>
675 11:05:08.000567 [Flow] Enable top DCM control <<<<<
676 11:05:08.004053 Enable DLL master slave shuffle
677 11:05:08.010182 ==============================================================
678 11:05:08.010295 Gating Mode config
679 11:05:08.016996 ==============================================================
680 11:05:08.020527 Config description:
681 11:05:08.030253 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 11:05:08.037451 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 11:05:08.040089 SELPH_MODE 0: By rank 1: By Phase
684 11:05:08.046816 ==============================================================
685 11:05:08.050181 GAT_TRACK_EN = 1
686 11:05:08.053275 RX_GATING_MODE = 2
687 11:05:08.053370 RX_GATING_TRACK_MODE = 2
688 11:05:08.056974 SELPH_MODE = 1
689 11:05:08.060120 PICG_EARLY_EN = 1
690 11:05:08.063971 VALID_LAT_VALUE = 1
691 11:05:08.069954 ==============================================================
692 11:05:08.073196 Enter into Gating configuration >>>>
693 11:05:08.076277 Exit from Gating configuration <<<<
694 11:05:08.079545 Enter into DVFS_PRE_config >>>>>
695 11:05:08.089843 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 11:05:08.093234 Exit from DVFS_PRE_config <<<<<
697 11:05:08.096269 Enter into PICG configuration >>>>
698 11:05:08.099777 Exit from PICG configuration <<<<
699 11:05:08.103218 [RX_INPUT] configuration >>>>>
700 11:05:08.106392 [RX_INPUT] configuration <<<<<
701 11:05:08.109384 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 11:05:08.116493 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 11:05:08.123280 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 11:05:08.129210 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 11:05:08.135867 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 11:05:08.139444 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 11:05:08.142541 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 11:05:08.149605 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 11:05:08.152743 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 11:05:08.156216 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 11:05:08.159279 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 11:05:08.166451 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 11:05:08.169303 ===================================
714 11:05:08.172810 LPDDR4 DRAM CONFIGURATION
715 11:05:08.175811 ===================================
716 11:05:08.175909 EX_ROW_EN[0] = 0x0
717 11:05:08.179146 EX_ROW_EN[1] = 0x0
718 11:05:08.179234 LP4Y_EN = 0x0
719 11:05:08.182403 WORK_FSP = 0x0
720 11:05:08.182492 WL = 0x2
721 11:05:08.185870 RL = 0x2
722 11:05:08.185958 BL = 0x2
723 11:05:08.189357 RPST = 0x0
724 11:05:08.189445 RD_PRE = 0x0
725 11:05:08.192549 WR_PRE = 0x1
726 11:05:08.192639 WR_PST = 0x0
727 11:05:08.195702 DBI_WR = 0x0
728 11:05:08.195789 DBI_RD = 0x0
729 11:05:08.199069 OTF = 0x1
730 11:05:08.202894 ===================================
731 11:05:08.205928 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 11:05:08.209459 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 11:05:08.216126 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 11:05:08.219168 ===================================
735 11:05:08.219299 LPDDR4 DRAM CONFIGURATION
736 11:05:08.223001 ===================================
737 11:05:08.225943 EX_ROW_EN[0] = 0x10
738 11:05:08.229115 EX_ROW_EN[1] = 0x0
739 11:05:08.229202 LP4Y_EN = 0x0
740 11:05:08.232313 WORK_FSP = 0x0
741 11:05:08.232424 WL = 0x2
742 11:05:08.235723 RL = 0x2
743 11:05:08.235811 BL = 0x2
744 11:05:08.238947 RPST = 0x0
745 11:05:08.239040 RD_PRE = 0x0
746 11:05:08.242423 WR_PRE = 0x1
747 11:05:08.242512 WR_PST = 0x0
748 11:05:08.245596 DBI_WR = 0x0
749 11:05:08.245687 DBI_RD = 0x0
750 11:05:08.249259 OTF = 0x1
751 11:05:08.252464 ===================================
752 11:05:08.259174 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 11:05:08.262301 nWR fixed to 40
754 11:05:08.262410 [ModeRegInit_LP4] CH0 RK0
755 11:05:08.265893 [ModeRegInit_LP4] CH0 RK1
756 11:05:08.268718 [ModeRegInit_LP4] CH1 RK0
757 11:05:08.272627 [ModeRegInit_LP4] CH1 RK1
758 11:05:08.272726 match AC timing 13
759 11:05:08.278890 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 11:05:08.281997 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 11:05:08.285633 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 11:05:08.291915 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 11:05:08.295164 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 11:05:08.295267 [EMI DOE] emi_dcm 0
765 11:05:08.302046 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 11:05:08.302159 ==
767 11:05:08.305173 Dram Type= 6, Freq= 0, CH_0, rank 0
768 11:05:08.308450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 11:05:08.308563 ==
770 11:05:08.315474 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 11:05:08.321555 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 11:05:08.329266 [CA 0] Center 37 (7~68) winsize 62
773 11:05:08.333012 [CA 1] Center 37 (6~68) winsize 63
774 11:05:08.336086 [CA 2] Center 34 (4~65) winsize 62
775 11:05:08.339057 [CA 3] Center 34 (4~65) winsize 62
776 11:05:08.342764 [CA 4] Center 33 (3~64) winsize 62
777 11:05:08.345728 [CA 5] Center 33 (3~64) winsize 62
778 11:05:08.345857
779 11:05:08.349098 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 11:05:08.349195
781 11:05:08.352844 [CATrainingPosCal] consider 1 rank data
782 11:05:08.356253 u2DelayCellTimex100 = 270/100 ps
783 11:05:08.359248 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
784 11:05:08.362353 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
785 11:05:08.369127 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
786 11:05:08.372509 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
787 11:05:08.375970 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
788 11:05:08.379080 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 11:05:08.379215
790 11:05:08.382230 CA PerBit enable=1, Macro0, CA PI delay=33
791 11:05:08.382362
792 11:05:08.385724 [CBTSetCACLKResult] CA Dly = 33
793 11:05:08.385815 CS Dly: 6 (0~37)
794 11:05:08.389220 ==
795 11:05:08.392108 Dram Type= 6, Freq= 0, CH_0, rank 1
796 11:05:08.395699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 11:05:08.395800 ==
798 11:05:08.398917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 11:05:08.405573 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 11:05:08.415491 [CA 0] Center 38 (7~69) winsize 63
801 11:05:08.419205 [CA 1] Center 37 (7~68) winsize 62
802 11:05:08.422975 [CA 2] Center 35 (4~66) winsize 63
803 11:05:08.425732 [CA 3] Center 34 (4~65) winsize 62
804 11:05:08.429272 [CA 4] Center 34 (3~65) winsize 63
805 11:05:08.433033 [CA 5] Center 33 (3~64) winsize 62
806 11:05:08.433134
807 11:05:08.435969 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 11:05:08.436083
809 11:05:08.439487 [CATrainingPosCal] consider 2 rank data
810 11:05:08.442346 u2DelayCellTimex100 = 270/100 ps
811 11:05:08.445718 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
812 11:05:08.448940 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
813 11:05:08.455759 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
814 11:05:08.459115 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
815 11:05:08.462073 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
816 11:05:08.465619 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 11:05:08.465733
818 11:05:08.469172 CA PerBit enable=1, Macro0, CA PI delay=33
819 11:05:08.469264
820 11:05:08.472964 [CBTSetCACLKResult] CA Dly = 33
821 11:05:08.473059 CS Dly: 6 (0~37)
822 11:05:08.473129
823 11:05:08.475500 ----->DramcWriteLeveling(PI) begin...
824 11:05:08.479519 ==
825 11:05:08.479613 Dram Type= 6, Freq= 0, CH_0, rank 0
826 11:05:08.486184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 11:05:08.486301 ==
828 11:05:08.490320 Write leveling (Byte 0): 31 => 31
829 11:05:08.490415 Write leveling (Byte 1): 26 => 26
830 11:05:08.493196 DramcWriteLeveling(PI) end<-----
831 11:05:08.493285
832 11:05:08.493359 ==
833 11:05:08.497875 Dram Type= 6, Freq= 0, CH_0, rank 0
834 11:05:08.500653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 11:05:08.503447 ==
836 11:05:08.503584 [Gating] SW mode calibration
837 11:05:08.510853 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 11:05:08.517424 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 11:05:08.520921 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 11:05:08.524008 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
841 11:05:08.530953 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
842 11:05:08.534389 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 11:05:08.537635 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 11:05:08.544021 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 11:05:08.547380 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 11:05:08.550292 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 11:05:08.557378 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 11:05:08.560612 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 11:05:08.563817 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 11:05:08.570559 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 11:05:08.573904 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 11:05:08.577187 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 11:05:08.583680 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 11:05:08.587188 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 11:05:08.590108 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
856 11:05:08.597189 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
857 11:05:08.600376 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
858 11:05:08.603828 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:05:08.610341 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:05:08.614184 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:05:08.617412 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:05:08.623630 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:05:08.626800 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:05:08.630353 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:05:08.636523 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
866 11:05:08.640070 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
867 11:05:08.643115 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 11:05:08.650140 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 11:05:08.653359 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 11:05:08.656537 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 11:05:08.662943 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 11:05:08.666353 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
873 11:05:08.669535 0 10 8 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
874 11:05:08.676182 0 10 12 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
875 11:05:08.679710 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:05:08.682968 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:05:08.689721 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:05:08.692953 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:05:08.696052 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 11:05:08.702936 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
881 11:05:08.706136 0 11 8 | B1->B0 | 2424 3f3e | 0 1 | (0 0) (0 0)
882 11:05:08.709922 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
883 11:05:08.716021 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 11:05:08.719071 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 11:05:08.722698 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 11:05:08.729104 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 11:05:08.732402 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 11:05:08.736063 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 11:05:08.742157 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
890 11:05:08.745768 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
891 11:05:08.748813 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 11:05:08.755651 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 11:05:08.759203 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 11:05:08.762343 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 11:05:08.768920 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 11:05:08.772469 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 11:05:08.775960 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 11:05:08.779024 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 11:05:08.785363 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 11:05:08.789393 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 11:05:08.792485 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 11:05:08.798866 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 11:05:08.802039 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 11:05:08.805360 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:05:08.812321 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
906 11:05:08.815778 Total UI for P1: 0, mck2ui 16
907 11:05:08.819116 best dqsien dly found for B0: ( 0, 14, 6)
908 11:05:08.822010 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
909 11:05:08.825944 Total UI for P1: 0, mck2ui 16
910 11:05:08.828633 best dqsien dly found for B1: ( 0, 14, 8)
911 11:05:08.831988 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
912 11:05:08.835253 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
913 11:05:08.835385
914 11:05:08.838408 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
915 11:05:08.842265 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
916 11:05:08.845345 [Gating] SW calibration Done
917 11:05:08.845497 ==
918 11:05:08.848453 Dram Type= 6, Freq= 0, CH_0, rank 0
919 11:05:08.852331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 11:05:08.855820 ==
921 11:05:08.855988 RX Vref Scan: 0
922 11:05:08.856107
923 11:05:08.860024 RX Vref 0 -> 0, step: 1
924 11:05:08.860187
925 11:05:08.860314 RX Delay -130 -> 252, step: 16
926 11:05:08.865986 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
927 11:05:08.869287 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
928 11:05:08.872495 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
929 11:05:08.875996 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
930 11:05:08.879303 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
931 11:05:08.886021 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
932 11:05:08.890053 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
933 11:05:08.892396 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
934 11:05:08.895969 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
935 11:05:08.898997 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
936 11:05:08.905486 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
937 11:05:08.908937 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
938 11:05:08.912182 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
939 11:05:08.915608 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
940 11:05:08.922192 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
941 11:05:08.925886 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
942 11:05:08.926035 ==
943 11:05:08.928846 Dram Type= 6, Freq= 0, CH_0, rank 0
944 11:05:08.932180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 11:05:08.932304 ==
946 11:05:08.932404 DQS Delay:
947 11:05:08.935699 DQS0 = 0, DQS1 = 0
948 11:05:08.935813 DQM Delay:
949 11:05:08.938885 DQM0 = 88, DQM1 = 75
950 11:05:08.939010 DQ Delay:
951 11:05:08.942511 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
952 11:05:08.945613 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
953 11:05:08.948894 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
954 11:05:08.952073 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
955 11:05:08.952195
956 11:05:08.952267
957 11:05:08.952331 ==
958 11:05:08.956020 Dram Type= 6, Freq= 0, CH_0, rank 0
959 11:05:08.959213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 11:05:08.962378 ==
961 11:05:08.962485
962 11:05:08.962554
963 11:05:08.962616 TX Vref Scan disable
964 11:05:08.965708 == TX Byte 0 ==
965 11:05:08.968838 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
966 11:05:08.972764 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
967 11:05:08.975936 == TX Byte 1 ==
968 11:05:08.978854 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
969 11:05:08.982002 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
970 11:05:08.985442 ==
971 11:05:08.989210 Dram Type= 6, Freq= 0, CH_0, rank 0
972 11:05:08.991918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 11:05:08.992033 ==
974 11:05:09.004981 TX Vref=22, minBit 3, minWin=26, winSum=436
975 11:05:09.008060 TX Vref=24, minBit 0, minWin=27, winSum=440
976 11:05:09.011792 TX Vref=26, minBit 1, minWin=27, winSum=446
977 11:05:09.015510 TX Vref=28, minBit 3, minWin=27, winSum=449
978 11:05:09.017916 TX Vref=30, minBit 0, minWin=28, winSum=452
979 11:05:09.024607 TX Vref=32, minBit 1, minWin=27, winSum=447
980 11:05:09.028056 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 30
981 11:05:09.028185
982 11:05:09.031373 Final TX Range 1 Vref 30
983 11:05:09.031459
984 11:05:09.031525 ==
985 11:05:09.034632 Dram Type= 6, Freq= 0, CH_0, rank 0
986 11:05:09.037728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 11:05:09.041229 ==
988 11:05:09.041324
989 11:05:09.041394
990 11:05:09.041485 TX Vref Scan disable
991 11:05:09.044819 == TX Byte 0 ==
992 11:05:09.048284 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
993 11:05:09.055308 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
994 11:05:09.055449 == TX Byte 1 ==
995 11:05:09.058242 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
996 11:05:09.064621 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
997 11:05:09.064755
998 11:05:09.064857 [DATLAT]
999 11:05:09.064948 Freq=800, CH0 RK0
1000 11:05:09.065040
1001 11:05:09.068732 DATLAT Default: 0xa
1002 11:05:09.070857 0, 0xFFFF, sum = 0
1003 11:05:09.070965 1, 0xFFFF, sum = 0
1004 11:05:09.074659 2, 0xFFFF, sum = 0
1005 11:05:09.074776 3, 0xFFFF, sum = 0
1006 11:05:09.077852 4, 0xFFFF, sum = 0
1007 11:05:09.077963 5, 0xFFFF, sum = 0
1008 11:05:09.080993 6, 0xFFFF, sum = 0
1009 11:05:09.081091 7, 0xFFFF, sum = 0
1010 11:05:09.084135 8, 0xFFFF, sum = 0
1011 11:05:09.084221 9, 0x0, sum = 1
1012 11:05:09.088014 10, 0x0, sum = 2
1013 11:05:09.088109 11, 0x0, sum = 3
1014 11:05:09.090750 12, 0x0, sum = 4
1015 11:05:09.090838 best_step = 10
1016 11:05:09.090905
1017 11:05:09.090969 ==
1018 11:05:09.094245 Dram Type= 6, Freq= 0, CH_0, rank 0
1019 11:05:09.097493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1020 11:05:09.097624 ==
1021 11:05:09.100677 RX Vref Scan: 1
1022 11:05:09.100811
1023 11:05:09.104139 Set Vref Range= 32 -> 127
1024 11:05:09.104274
1025 11:05:09.104401 RX Vref 32 -> 127, step: 1
1026 11:05:09.104517
1027 11:05:09.107479 RX Delay -111 -> 252, step: 8
1028 11:05:09.107609
1029 11:05:09.110728 Set Vref, RX VrefLevel [Byte0]: 32
1030 11:05:09.114040 [Byte1]: 32
1031 11:05:09.117490
1032 11:05:09.117625 Set Vref, RX VrefLevel [Byte0]: 33
1033 11:05:09.120832 [Byte1]: 33
1034 11:05:09.125336
1035 11:05:09.125480 Set Vref, RX VrefLevel [Byte0]: 34
1036 11:05:09.128445 [Byte1]: 34
1037 11:05:09.133787
1038 11:05:09.133930 Set Vref, RX VrefLevel [Byte0]: 35
1039 11:05:09.136276 [Byte1]: 35
1040 11:05:09.140783
1041 11:05:09.140911 Set Vref, RX VrefLevel [Byte0]: 36
1042 11:05:09.143998 [Byte1]: 36
1043 11:05:09.148231
1044 11:05:09.151550 Set Vref, RX VrefLevel [Byte0]: 37
1045 11:05:09.151650 [Byte1]: 37
1046 11:05:09.156144
1047 11:05:09.159532 Set Vref, RX VrefLevel [Byte0]: 38
1048 11:05:09.159630 [Byte1]: 38
1049 11:05:09.163996
1050 11:05:09.164089 Set Vref, RX VrefLevel [Byte0]: 39
1051 11:05:09.167606 [Byte1]: 39
1052 11:05:09.171644
1053 11:05:09.171746 Set Vref, RX VrefLevel [Byte0]: 40
1054 11:05:09.174842 [Byte1]: 40
1055 11:05:09.178968
1056 11:05:09.179066 Set Vref, RX VrefLevel [Byte0]: 41
1057 11:05:09.182444 [Byte1]: 41
1058 11:05:09.186636
1059 11:05:09.186791 Set Vref, RX VrefLevel [Byte0]: 42
1060 11:05:09.192812 [Byte1]: 42
1061 11:05:09.192969
1062 11:05:09.196731 Set Vref, RX VrefLevel [Byte0]: 43
1063 11:05:09.199723 [Byte1]: 43
1064 11:05:09.199853
1065 11:05:09.203017 Set Vref, RX VrefLevel [Byte0]: 44
1066 11:05:09.206194 [Byte1]: 44
1067 11:05:09.209553
1068 11:05:09.209690 Set Vref, RX VrefLevel [Byte0]: 45
1069 11:05:09.212777 [Byte1]: 45
1070 11:05:09.217195
1071 11:05:09.217343 Set Vref, RX VrefLevel [Byte0]: 46
1072 11:05:09.220567 [Byte1]: 46
1073 11:05:09.224558
1074 11:05:09.224694 Set Vref, RX VrefLevel [Byte0]: 47
1075 11:05:09.228095 [Byte1]: 47
1076 11:05:09.232201
1077 11:05:09.232303 Set Vref, RX VrefLevel [Byte0]: 48
1078 11:05:09.235507 [Byte1]: 48
1079 11:05:09.240193
1080 11:05:09.240298 Set Vref, RX VrefLevel [Byte0]: 49
1081 11:05:09.243555 [Byte1]: 49
1082 11:05:09.248084
1083 11:05:09.248181 Set Vref, RX VrefLevel [Byte0]: 50
1084 11:05:09.251263 [Byte1]: 50
1085 11:05:09.255595
1086 11:05:09.255739 Set Vref, RX VrefLevel [Byte0]: 51
1087 11:05:09.259031 [Byte1]: 51
1088 11:05:09.263539
1089 11:05:09.263682 Set Vref, RX VrefLevel [Byte0]: 52
1090 11:05:09.266612 [Byte1]: 52
1091 11:05:09.270367
1092 11:05:09.270502 Set Vref, RX VrefLevel [Byte0]: 53
1093 11:05:09.274212 [Byte1]: 53
1094 11:05:09.278481
1095 11:05:09.278617 Set Vref, RX VrefLevel [Byte0]: 54
1096 11:05:09.281731 [Byte1]: 54
1097 11:05:09.286444
1098 11:05:09.286588 Set Vref, RX VrefLevel [Byte0]: 55
1099 11:05:09.289598 [Byte1]: 55
1100 11:05:09.293899
1101 11:05:09.294040 Set Vref, RX VrefLevel [Byte0]: 56
1102 11:05:09.296845 [Byte1]: 56
1103 11:05:09.301447
1104 11:05:09.301592 Set Vref, RX VrefLevel [Byte0]: 57
1105 11:05:09.304361 [Byte1]: 57
1106 11:05:09.308829
1107 11:05:09.308964 Set Vref, RX VrefLevel [Byte0]: 58
1108 11:05:09.312427 [Byte1]: 58
1109 11:05:09.316437
1110 11:05:09.316573 Set Vref, RX VrefLevel [Byte0]: 59
1111 11:05:09.319982 [Byte1]: 59
1112 11:05:09.324236
1113 11:05:09.324372 Set Vref, RX VrefLevel [Byte0]: 60
1114 11:05:09.327210 [Byte1]: 60
1115 11:05:09.332172
1116 11:05:09.332291 Set Vref, RX VrefLevel [Byte0]: 61
1117 11:05:09.335101 [Byte1]: 61
1118 11:05:09.339263
1119 11:05:09.339398 Set Vref, RX VrefLevel [Byte0]: 62
1120 11:05:09.343032 [Byte1]: 62
1121 11:05:09.347036
1122 11:05:09.347153 Set Vref, RX VrefLevel [Byte0]: 63
1123 11:05:09.350226 [Byte1]: 63
1124 11:05:09.354517
1125 11:05:09.354633 Set Vref, RX VrefLevel [Byte0]: 64
1126 11:05:09.358305 [Byte1]: 64
1127 11:05:09.363226
1128 11:05:09.363356 Set Vref, RX VrefLevel [Byte0]: 65
1129 11:05:09.365506 [Byte1]: 65
1130 11:05:09.369974
1131 11:05:09.370085 Set Vref, RX VrefLevel [Byte0]: 66
1132 11:05:09.373188 [Byte1]: 66
1133 11:05:09.377382
1134 11:05:09.377510 Set Vref, RX VrefLevel [Byte0]: 67
1135 11:05:09.381109 [Byte1]: 67
1136 11:05:09.385251
1137 11:05:09.385376 Set Vref, RX VrefLevel [Byte0]: 68
1138 11:05:09.388373 [Byte1]: 68
1139 11:05:09.392726
1140 11:05:09.392842 Set Vref, RX VrefLevel [Byte0]: 69
1141 11:05:09.396302 [Byte1]: 69
1142 11:05:09.400281
1143 11:05:09.400394 Set Vref, RX VrefLevel [Byte0]: 70
1144 11:05:09.403768 [Byte1]: 70
1145 11:05:09.408134
1146 11:05:09.408254 Set Vref, RX VrefLevel [Byte0]: 71
1147 11:05:09.411719 [Byte1]: 71
1148 11:05:09.416291
1149 11:05:09.416418 Set Vref, RX VrefLevel [Byte0]: 72
1150 11:05:09.418995 [Byte1]: 72
1151 11:05:09.423198
1152 11:05:09.423331 Set Vref, RX VrefLevel [Byte0]: 73
1153 11:05:09.426597 [Byte1]: 73
1154 11:05:09.431148
1155 11:05:09.431271 Set Vref, RX VrefLevel [Byte0]: 74
1156 11:05:09.434232 [Byte1]: 74
1157 11:05:09.439468
1158 11:05:09.439606 Final RX Vref Byte 0 = 57 to rank0
1159 11:05:09.441964 Final RX Vref Byte 1 = 60 to rank0
1160 11:05:09.445402 Final RX Vref Byte 0 = 57 to rank1
1161 11:05:09.448753 Final RX Vref Byte 1 = 60 to rank1==
1162 11:05:09.451822 Dram Type= 6, Freq= 0, CH_0, rank 0
1163 11:05:09.458995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1164 11:05:09.459152 ==
1165 11:05:09.459253 DQS Delay:
1166 11:05:09.459345 DQS0 = 0, DQS1 = 0
1167 11:05:09.462314 DQM Delay:
1168 11:05:09.462408 DQM0 = 88, DQM1 = 77
1169 11:05:09.465488 DQ Delay:
1170 11:05:09.468567 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1171 11:05:09.471974 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1172 11:05:09.475385 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =76
1173 11:05:09.479265 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1174 11:05:09.479409
1175 11:05:09.479505
1176 11:05:09.485186 [DQSOSCAuto] RK0, (LSB)MR18= 0x322b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1177 11:05:09.488855 CH0 RK0: MR19=606, MR18=322B
1178 11:05:09.495455 CH0_RK0: MR19=0x606, MR18=0x322B, DQSOSC=397, MR23=63, INC=93, DEC=62
1179 11:05:09.495597
1180 11:05:09.498562 ----->DramcWriteLeveling(PI) begin...
1181 11:05:09.498667 ==
1182 11:05:09.501969 Dram Type= 6, Freq= 0, CH_0, rank 1
1183 11:05:09.505021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 11:05:09.505128 ==
1185 11:05:09.508949 Write leveling (Byte 0): 32 => 32
1186 11:05:09.512338 Write leveling (Byte 1): 26 => 26
1187 11:05:09.515896 DramcWriteLeveling(PI) end<-----
1188 11:05:09.516013
1189 11:05:09.516110 ==
1190 11:05:09.518646 Dram Type= 6, Freq= 0, CH_0, rank 1
1191 11:05:09.522242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1192 11:05:09.522359 ==
1193 11:05:09.524957 [Gating] SW mode calibration
1194 11:05:09.531736 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1195 11:05:09.538855 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1196 11:05:09.541764 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1197 11:05:09.584839 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1198 11:05:09.585855 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1199 11:05:09.586222 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 11:05:09.586351 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 11:05:09.586745 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 11:05:09.587084 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 11:05:09.587222 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 11:05:09.587335 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 11:05:09.587467 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 11:05:09.587587 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 11:05:09.590397 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 11:05:09.594263 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 11:05:09.600675 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 11:05:09.604313 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 11:05:09.607244 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 11:05:09.613761 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1213 11:05:09.617210 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1214 11:05:09.620270 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 11:05:09.627101 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 11:05:09.630199 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 11:05:09.634520 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 11:05:09.640275 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 11:05:09.643316 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:05:09.647098 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:05:09.653717 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:05:09.656790 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
1223 11:05:09.660364 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1224 11:05:09.667213 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1225 11:05:09.670145 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1226 11:05:09.673175 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1227 11:05:09.680234 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1228 11:05:09.683471 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1229 11:05:09.686406 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 0)
1230 11:05:09.693024 0 10 8 | B1->B0 | 3030 2424 | 0 0 | (0 1) (0 0)
1231 11:05:09.696209 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1232 11:05:09.699419 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:05:09.703822 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:05:09.709516 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:05:09.713083 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:05:09.716293 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:05:09.722868 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1238 11:05:09.726553 0 11 8 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
1239 11:05:09.731040 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1240 11:05:09.734081 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 11:05:09.741106 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1242 11:05:09.744499 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1243 11:05:09.747375 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1244 11:05:09.754557 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 11:05:09.758486 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1246 11:05:09.761860 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1247 11:05:09.765093 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1248 11:05:09.771670 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 11:05:09.774749 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 11:05:09.778611 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 11:05:09.784937 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 11:05:09.788072 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 11:05:09.791205 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 11:05:09.798261 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 11:05:09.801274 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 11:05:09.804586 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 11:05:09.811229 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 11:05:09.814428 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 11:05:09.817849 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 11:05:09.824433 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 11:05:09.827731 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 11:05:09.831328 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1263 11:05:09.834385 Total UI for P1: 0, mck2ui 16
1264 11:05:09.837889 best dqsien dly found for B0: ( 0, 14, 6)
1265 11:05:09.844393 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 11:05:09.844518 Total UI for P1: 0, mck2ui 16
1267 11:05:09.850743 best dqsien dly found for B1: ( 0, 14, 8)
1268 11:05:09.854049 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1269 11:05:09.857521 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1270 11:05:09.857618
1271 11:05:09.860820 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1272 11:05:09.864528 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1273 11:05:09.868062 [Gating] SW calibration Done
1274 11:05:09.868157 ==
1275 11:05:09.870788 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 11:05:09.874229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 11:05:09.874343 ==
1278 11:05:09.878099 RX Vref Scan: 0
1279 11:05:09.878190
1280 11:05:09.878255 RX Vref 0 -> 0, step: 1
1281 11:05:09.878316
1282 11:05:09.881116 RX Delay -130 -> 252, step: 16
1283 11:05:09.884167 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1284 11:05:09.890904 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1285 11:05:09.894145 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1286 11:05:09.897396 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1287 11:05:09.901156 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1288 11:05:09.904144 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1289 11:05:09.910474 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1290 11:05:09.914737 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1291 11:05:09.917563 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1292 11:05:09.920400 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1293 11:05:09.923818 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1294 11:05:09.930736 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1295 11:05:09.934072 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1296 11:05:09.937265 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1297 11:05:09.940525 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1298 11:05:09.944289 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1299 11:05:09.947394 ==
1300 11:05:09.950967 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 11:05:09.953890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 11:05:09.953988 ==
1303 11:05:09.954057 DQS Delay:
1304 11:05:09.957313 DQS0 = 0, DQS1 = 0
1305 11:05:09.957402 DQM Delay:
1306 11:05:09.960366 DQM0 = 85, DQM1 = 77
1307 11:05:09.960456 DQ Delay:
1308 11:05:09.964014 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1309 11:05:09.967270 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1310 11:05:09.970839 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1311 11:05:09.973787 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1312 11:05:09.973882
1313 11:05:09.973949
1314 11:05:09.974011 ==
1315 11:05:09.976948 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 11:05:09.980478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1317 11:05:09.980572 ==
1318 11:05:09.980640
1319 11:05:09.980703
1320 11:05:09.984072 TX Vref Scan disable
1321 11:05:09.987509 == TX Byte 0 ==
1322 11:05:09.990248 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1323 11:05:09.993949 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1324 11:05:09.997300 == TX Byte 1 ==
1325 11:05:10.001028 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1326 11:05:10.004094 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1327 11:05:10.004185 ==
1328 11:05:10.006805 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 11:05:10.010253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 11:05:10.013389 ==
1331 11:05:10.025684 TX Vref=22, minBit 1, minWin=27, winSum=441
1332 11:05:10.028891 TX Vref=24, minBit 1, minWin=27, winSum=444
1333 11:05:10.032520 TX Vref=26, minBit 1, minWin=27, winSum=447
1334 11:05:10.035716 TX Vref=28, minBit 0, minWin=28, winSum=453
1335 11:05:10.039007 TX Vref=30, minBit 4, minWin=27, winSum=451
1336 11:05:10.045374 TX Vref=32, minBit 2, minWin=27, winSum=450
1337 11:05:10.048929 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 28
1338 11:05:10.049034
1339 11:05:10.052400 Final TX Range 1 Vref 28
1340 11:05:10.052517
1341 11:05:10.052600 ==
1342 11:05:10.055815 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 11:05:10.059325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 11:05:10.059431 ==
1345 11:05:10.061906
1346 11:05:10.062018
1347 11:05:10.062086 TX Vref Scan disable
1348 11:05:10.065919 == TX Byte 0 ==
1349 11:05:10.069221 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1350 11:05:10.075660 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1351 11:05:10.075751 == TX Byte 1 ==
1352 11:05:10.078525 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1353 11:05:10.085044 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1354 11:05:10.085129
1355 11:05:10.085196 [DATLAT]
1356 11:05:10.085257 Freq=800, CH0 RK1
1357 11:05:10.085315
1358 11:05:10.088824 DATLAT Default: 0xa
1359 11:05:10.091857 0, 0xFFFF, sum = 0
1360 11:05:10.091944 1, 0xFFFF, sum = 0
1361 11:05:10.095036 2, 0xFFFF, sum = 0
1362 11:05:10.095121 3, 0xFFFF, sum = 0
1363 11:05:10.098864 4, 0xFFFF, sum = 0
1364 11:05:10.098951 5, 0xFFFF, sum = 0
1365 11:05:10.101683 6, 0xFFFF, sum = 0
1366 11:05:10.101770 7, 0xFFFF, sum = 0
1367 11:05:10.105189 8, 0xFFFF, sum = 0
1368 11:05:10.105268 9, 0x0, sum = 1
1369 11:05:10.108348 10, 0x0, sum = 2
1370 11:05:10.108422 11, 0x0, sum = 3
1371 11:05:10.111903 12, 0x0, sum = 4
1372 11:05:10.111978 best_step = 10
1373 11:05:10.112051
1374 11:05:10.112110 ==
1375 11:05:10.115124 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 11:05:10.118270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 11:05:10.118347 ==
1378 11:05:10.121743 RX Vref Scan: 0
1379 11:05:10.121823
1380 11:05:10.125157 RX Vref 0 -> 0, step: 1
1381 11:05:10.125233
1382 11:05:10.125295 RX Delay -95 -> 252, step: 8
1383 11:05:10.132280 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1384 11:05:10.135890 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1385 11:05:10.139046 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1386 11:05:10.141898 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1387 11:05:10.148811 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1388 11:05:10.151918 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1389 11:05:10.155554 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1390 11:05:10.158469 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1391 11:05:10.161738 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1392 11:05:10.168372 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1393 11:05:10.171639 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1394 11:05:10.175223 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1395 11:05:10.178239 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1396 11:05:10.181919 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1397 11:05:10.188398 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1398 11:05:10.191641 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1399 11:05:10.191725 ==
1400 11:05:10.194838 Dram Type= 6, Freq= 0, CH_0, rank 1
1401 11:05:10.198007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 11:05:10.198092 ==
1403 11:05:10.201538 DQS Delay:
1404 11:05:10.201627 DQS0 = 0, DQS1 = 0
1405 11:05:10.201695 DQM Delay:
1406 11:05:10.204592 DQM0 = 86, DQM1 = 77
1407 11:05:10.204668 DQ Delay:
1408 11:05:10.208627 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1409 11:05:10.211299 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1410 11:05:10.214896 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1411 11:05:10.217990 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1412 11:05:10.218090
1413 11:05:10.218182
1414 11:05:10.228033 [DQSOSCAuto] RK1, (LSB)MR18= 0x231f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
1415 11:05:10.231232 CH0 RK1: MR19=606, MR18=231F
1416 11:05:10.234794 CH0_RK1: MR19=0x606, MR18=0x231F, DQSOSC=401, MR23=63, INC=91, DEC=61
1417 11:05:10.238557 [RxdqsGatingPostProcess] freq 800
1418 11:05:10.244541 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1419 11:05:10.247903 Pre-setting of DQS Precalculation
1420 11:05:10.251567 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1421 11:05:10.251651 ==
1422 11:05:10.254609 Dram Type= 6, Freq= 0, CH_1, rank 0
1423 11:05:10.261644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 11:05:10.261729 ==
1425 11:05:10.264598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1426 11:05:10.270969 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1427 11:05:10.280592 [CA 0] Center 36 (6~67) winsize 62
1428 11:05:10.284131 [CA 1] Center 37 (6~68) winsize 63
1429 11:05:10.287008 [CA 2] Center 35 (5~66) winsize 62
1430 11:05:10.290350 [CA 3] Center 34 (4~65) winsize 62
1431 11:05:10.293973 [CA 4] Center 34 (4~65) winsize 62
1432 11:05:10.297905 [CA 5] Center 34 (4~65) winsize 62
1433 11:05:10.297990
1434 11:05:10.300344 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1435 11:05:10.300427
1436 11:05:10.303494 [CATrainingPosCal] consider 1 rank data
1437 11:05:10.307471 u2DelayCellTimex100 = 270/100 ps
1438 11:05:10.310162 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1439 11:05:10.317220 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1440 11:05:10.320582 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1441 11:05:10.323704 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1442 11:05:10.326969 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1443 11:05:10.330309 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1444 11:05:10.330432
1445 11:05:10.333458 CA PerBit enable=1, Macro0, CA PI delay=34
1446 11:05:10.333561
1447 11:05:10.337011 [CBTSetCACLKResult] CA Dly = 34
1448 11:05:10.337112 CS Dly: 4 (0~35)
1449 11:05:10.340071 ==
1450 11:05:10.343289 Dram Type= 6, Freq= 0, CH_1, rank 1
1451 11:05:10.347106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 11:05:10.347218 ==
1453 11:05:10.350263 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1454 11:05:10.356705 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1455 11:05:10.367056 [CA 0] Center 36 (6~67) winsize 62
1456 11:05:10.370077 [CA 1] Center 36 (6~67) winsize 62
1457 11:05:10.373067 [CA 2] Center 35 (4~66) winsize 63
1458 11:05:10.376407 [CA 3] Center 34 (3~65) winsize 63
1459 11:05:10.379529 [CA 4] Center 34 (4~65) winsize 62
1460 11:05:10.383482 [CA 5] Center 34 (3~65) winsize 63
1461 11:05:10.383615
1462 11:05:10.386762 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1463 11:05:10.386852
1464 11:05:10.389678 [CATrainingPosCal] consider 2 rank data
1465 11:05:10.392959 u2DelayCellTimex100 = 270/100 ps
1466 11:05:10.396568 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1467 11:05:10.399940 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1468 11:05:10.404116 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1469 11:05:10.407637 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1470 11:05:10.411583 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1471 11:05:10.414889 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1472 11:05:10.414974
1473 11:05:10.419038 CA PerBit enable=1, Macro0, CA PI delay=34
1474 11:05:10.419124
1475 11:05:10.422451 [CBTSetCACLKResult] CA Dly = 34
1476 11:05:10.427228 CS Dly: 5 (0~37)
1477 11:05:10.427339
1478 11:05:10.429790 ----->DramcWriteLeveling(PI) begin...
1479 11:05:10.429889 ==
1480 11:05:10.433134 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 11:05:10.436559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1482 11:05:10.436671 ==
1483 11:05:10.440472 Write leveling (Byte 0): 24 => 24
1484 11:05:10.443056 Write leveling (Byte 1): 26 => 26
1485 11:05:10.446732 DramcWriteLeveling(PI) end<-----
1486 11:05:10.446827
1487 11:05:10.446894 ==
1488 11:05:10.449964 Dram Type= 6, Freq= 0, CH_1, rank 0
1489 11:05:10.452869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1490 11:05:10.452996 ==
1491 11:05:10.456649 [Gating] SW mode calibration
1492 11:05:10.462985 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1493 11:05:10.469596 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1494 11:05:10.472846 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1495 11:05:10.476088 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1496 11:05:10.482752 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 11:05:10.486058 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 11:05:10.489729 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 11:05:10.492977 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 11:05:10.499448 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 11:05:10.502880 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 11:05:10.506846 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 11:05:10.512587 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 11:05:10.516469 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 11:05:10.519507 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 11:05:10.526297 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 11:05:10.529441 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 11:05:10.532679 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 11:05:10.539096 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 11:05:10.542517 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1511 11:05:10.546485 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1512 11:05:10.552184 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 11:05:10.555825 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 11:05:10.559044 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 11:05:10.565847 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 11:05:10.568878 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 11:05:10.572588 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:05:10.578772 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:05:10.582480 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:05:10.585915 0 9 8 | B1->B0 | 2929 3131 | 0 1 | (0 0) (1 1)
1521 11:05:10.592503 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1522 11:05:10.595416 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1523 11:05:10.598997 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1524 11:05:10.605505 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1525 11:05:10.609032 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1526 11:05:10.612294 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1527 11:05:10.618820 0 10 4 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 1)
1528 11:05:10.622466 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
1529 11:05:10.625340 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:05:10.632303 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:05:10.635453 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:05:10.638713 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:05:10.645417 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:05:10.648625 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:05:10.652134 0 11 4 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
1536 11:05:10.659008 0 11 8 | B1->B0 | 3939 4040 | 1 0 | (0 0) (0 0)
1537 11:05:10.661915 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 11:05:10.665414 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1539 11:05:10.671812 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1540 11:05:10.675101 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1541 11:05:10.678392 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1542 11:05:10.685058 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1543 11:05:10.688237 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1544 11:05:10.691428 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1545 11:05:10.698209 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 11:05:10.701309 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 11:05:10.704537 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 11:05:10.711879 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 11:05:10.714706 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 11:05:10.718018 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 11:05:10.724759 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 11:05:10.727754 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 11:05:10.731240 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 11:05:10.737680 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 11:05:10.741205 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 11:05:10.744429 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 11:05:10.751352 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 11:05:10.753991 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 11:05:10.757529 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 11:05:10.764458 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1561 11:05:10.764551 Total UI for P1: 0, mck2ui 16
1562 11:05:10.767747 best dqsien dly found for B0: ( 0, 14, 6)
1563 11:05:10.774286 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 11:05:10.777230 Total UI for P1: 0, mck2ui 16
1565 11:05:10.781022 best dqsien dly found for B1: ( 0, 14, 8)
1566 11:05:10.784006 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1567 11:05:10.787306 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1568 11:05:10.787462
1569 11:05:10.790543 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1570 11:05:10.793865 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1571 11:05:10.797397 [Gating] SW calibration Done
1572 11:05:10.797539 ==
1573 11:05:10.800647 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 11:05:10.803681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 11:05:10.803817 ==
1576 11:05:10.807083 RX Vref Scan: 0
1577 11:05:10.807201
1578 11:05:10.807321 RX Vref 0 -> 0, step: 1
1579 11:05:10.810758
1580 11:05:10.810890 RX Delay -130 -> 252, step: 16
1581 11:05:10.817031 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1582 11:05:10.820758 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1583 11:05:10.824307 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1584 11:05:10.826953 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1585 11:05:10.830633 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1586 11:05:10.836972 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1587 11:05:10.840448 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1588 11:05:10.843927 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1589 11:05:10.847247 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1590 11:05:10.850345 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1591 11:05:10.856940 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1592 11:05:10.860505 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1593 11:05:10.863518 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1594 11:05:10.866849 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1595 11:05:10.870331 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1596 11:05:10.877159 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1597 11:05:10.877320 ==
1598 11:05:10.880289 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 11:05:10.883464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 11:05:10.883584 ==
1601 11:05:10.883680 DQS Delay:
1602 11:05:10.886864 DQS0 = 0, DQS1 = 0
1603 11:05:10.886951 DQM Delay:
1604 11:05:10.890208 DQM0 = 88, DQM1 = 80
1605 11:05:10.890301 DQ Delay:
1606 11:05:10.893504 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1607 11:05:10.896711 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1608 11:05:10.899948 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1609 11:05:10.903531 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1610 11:05:10.903665
1611 11:05:10.903730
1612 11:05:10.903792 ==
1613 11:05:10.906658 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 11:05:10.910308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 11:05:10.913235 ==
1616 11:05:10.913329
1617 11:05:10.913388
1618 11:05:10.913445 TX Vref Scan disable
1619 11:05:10.916656 == TX Byte 0 ==
1620 11:05:10.920342 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1621 11:05:10.923270 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1622 11:05:10.926753 == TX Byte 1 ==
1623 11:05:10.930335 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1624 11:05:10.936429 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1625 11:05:10.936553 ==
1626 11:05:10.940485 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 11:05:10.943080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 11:05:10.943161 ==
1629 11:05:10.955622 TX Vref=22, minBit 4, minWin=26, winSum=439
1630 11:05:10.958959 TX Vref=24, minBit 6, minWin=26, winSum=443
1631 11:05:10.962153 TX Vref=26, minBit 6, minWin=26, winSum=445
1632 11:05:10.965844 TX Vref=28, minBit 0, minWin=27, winSum=454
1633 11:05:10.968807 TX Vref=30, minBit 1, minWin=27, winSum=454
1634 11:05:10.975978 TX Vref=32, minBit 0, minWin=27, winSum=451
1635 11:05:10.979696 [TxChooseVref] Worse bit 0, Min win 27, Win sum 454, Final Vref 28
1636 11:05:10.979802
1637 11:05:10.983093 Final TX Range 1 Vref 28
1638 11:05:10.983176
1639 11:05:10.983246 ==
1640 11:05:10.986133 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 11:05:10.989705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 11:05:10.989802 ==
1643 11:05:10.989870
1644 11:05:10.989930
1645 11:05:10.992898 TX Vref Scan disable
1646 11:05:10.996025 == TX Byte 0 ==
1647 11:05:10.999272 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1648 11:05:11.002652 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1649 11:05:11.006341 == TX Byte 1 ==
1650 11:05:11.009496 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1651 11:05:11.012936 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1652 11:05:11.013027
1653 11:05:11.016193 [DATLAT]
1654 11:05:11.016276 Freq=800, CH1 RK0
1655 11:05:11.016340
1656 11:05:11.019786 DATLAT Default: 0xa
1657 11:05:11.019903 0, 0xFFFF, sum = 0
1658 11:05:11.023093 1, 0xFFFF, sum = 0
1659 11:05:11.023219 2, 0xFFFF, sum = 0
1660 11:05:11.026158 3, 0xFFFF, sum = 0
1661 11:05:11.026243 4, 0xFFFF, sum = 0
1662 11:05:11.029698 5, 0xFFFF, sum = 0
1663 11:05:11.029825 6, 0xFFFF, sum = 0
1664 11:05:11.032970 7, 0xFFFF, sum = 0
1665 11:05:11.033065 8, 0xFFFF, sum = 0
1666 11:05:11.036523 9, 0x0, sum = 1
1667 11:05:11.036611 10, 0x0, sum = 2
1668 11:05:11.039515 11, 0x0, sum = 3
1669 11:05:11.039630 12, 0x0, sum = 4
1670 11:05:11.042818 best_step = 10
1671 11:05:11.042913
1672 11:05:11.042980 ==
1673 11:05:11.046423 Dram Type= 6, Freq= 0, CH_1, rank 0
1674 11:05:11.049786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1675 11:05:11.049881 ==
1676 11:05:11.052808 RX Vref Scan: 1
1677 11:05:11.052898
1678 11:05:11.052965 Set Vref Range= 32 -> 127
1679 11:05:11.053027
1680 11:05:11.056023 RX Vref 32 -> 127, step: 1
1681 11:05:11.056121
1682 11:05:11.059671 RX Delay -95 -> 252, step: 8
1683 11:05:11.059771
1684 11:05:11.063086 Set Vref, RX VrefLevel [Byte0]: 32
1685 11:05:11.066286 [Byte1]: 32
1686 11:05:11.066378
1687 11:05:11.069455 Set Vref, RX VrefLevel [Byte0]: 33
1688 11:05:11.072662 [Byte1]: 33
1689 11:05:11.076122
1690 11:05:11.076220 Set Vref, RX VrefLevel [Byte0]: 34
1691 11:05:11.080329 [Byte1]: 34
1692 11:05:11.083792
1693 11:05:11.083885 Set Vref, RX VrefLevel [Byte0]: 35
1694 11:05:11.087044 [Byte1]: 35
1695 11:05:11.091217
1696 11:05:11.091327 Set Vref, RX VrefLevel [Byte0]: 36
1697 11:05:11.094652 [Byte1]: 36
1698 11:05:11.098685
1699 11:05:11.098774 Set Vref, RX VrefLevel [Byte0]: 37
1700 11:05:11.102153 [Byte1]: 37
1701 11:05:11.106279
1702 11:05:11.106368 Set Vref, RX VrefLevel [Byte0]: 38
1703 11:05:11.109650 [Byte1]: 38
1704 11:05:11.114288
1705 11:05:11.114399 Set Vref, RX VrefLevel [Byte0]: 39
1706 11:05:11.117273 [Byte1]: 39
1707 11:05:11.121668
1708 11:05:11.121781 Set Vref, RX VrefLevel [Byte0]: 40
1709 11:05:11.125229 [Byte1]: 40
1710 11:05:11.129349
1711 11:05:11.129426 Set Vref, RX VrefLevel [Byte0]: 41
1712 11:05:11.132625 [Byte1]: 41
1713 11:05:11.136694
1714 11:05:11.136774 Set Vref, RX VrefLevel [Byte0]: 42
1715 11:05:11.139989 [Byte1]: 42
1716 11:05:11.144893
1717 11:05:11.144994 Set Vref, RX VrefLevel [Byte0]: 43
1718 11:05:11.147438 [Byte1]: 43
1719 11:05:11.151962
1720 11:05:11.152051 Set Vref, RX VrefLevel [Byte0]: 44
1721 11:05:11.155296 [Byte1]: 44
1722 11:05:11.159987
1723 11:05:11.160077 Set Vref, RX VrefLevel [Byte0]: 45
1724 11:05:11.163173 [Byte1]: 45
1725 11:05:11.167002
1726 11:05:11.167088 Set Vref, RX VrefLevel [Byte0]: 46
1727 11:05:11.170732 [Byte1]: 46
1728 11:05:11.175124
1729 11:05:11.175205 Set Vref, RX VrefLevel [Byte0]: 47
1730 11:05:11.178313 [Byte1]: 47
1731 11:05:11.182488
1732 11:05:11.182564 Set Vref, RX VrefLevel [Byte0]: 48
1733 11:05:11.185801 [Byte1]: 48
1734 11:05:11.190120
1735 11:05:11.190202 Set Vref, RX VrefLevel [Byte0]: 49
1736 11:05:11.193176 [Byte1]: 49
1737 11:05:11.198219
1738 11:05:11.198303 Set Vref, RX VrefLevel [Byte0]: 50
1739 11:05:11.200650 [Byte1]: 50
1740 11:05:11.205185
1741 11:05:11.205266 Set Vref, RX VrefLevel [Byte0]: 51
1742 11:05:11.208616 [Byte1]: 51
1743 11:05:11.213374
1744 11:05:11.213478 Set Vref, RX VrefLevel [Byte0]: 52
1745 11:05:11.215986 [Byte1]: 52
1746 11:05:11.220776
1747 11:05:11.220859 Set Vref, RX VrefLevel [Byte0]: 53
1748 11:05:11.223814 [Byte1]: 53
1749 11:05:11.228341
1750 11:05:11.228472 Set Vref, RX VrefLevel [Byte0]: 54
1751 11:05:11.231296 [Byte1]: 54
1752 11:05:11.235523
1753 11:05:11.235605 Set Vref, RX VrefLevel [Byte0]: 55
1754 11:05:11.238676 [Byte1]: 55
1755 11:05:11.242947
1756 11:05:11.243034 Set Vref, RX VrefLevel [Byte0]: 56
1757 11:05:11.246240 [Byte1]: 56
1758 11:05:11.250880
1759 11:05:11.250964 Set Vref, RX VrefLevel [Byte0]: 57
1760 11:05:11.254246 [Byte1]: 57
1761 11:05:11.258303
1762 11:05:11.258382 Set Vref, RX VrefLevel [Byte0]: 58
1763 11:05:11.261833 [Byte1]: 58
1764 11:05:11.266190
1765 11:05:11.266280 Set Vref, RX VrefLevel [Byte0]: 59
1766 11:05:11.269156 [Byte1]: 59
1767 11:05:11.273598
1768 11:05:11.273731 Set Vref, RX VrefLevel [Byte0]: 60
1769 11:05:11.276866 [Byte1]: 60
1770 11:05:11.281348
1771 11:05:11.281471 Set Vref, RX VrefLevel [Byte0]: 61
1772 11:05:11.284623 [Byte1]: 61
1773 11:05:11.288809
1774 11:05:11.288931 Set Vref, RX VrefLevel [Byte0]: 62
1775 11:05:11.292582 [Byte1]: 62
1776 11:05:11.296234
1777 11:05:11.296348 Set Vref, RX VrefLevel [Byte0]: 63
1778 11:05:11.299691 [Byte1]: 63
1779 11:05:11.303970
1780 11:05:11.304075 Set Vref, RX VrefLevel [Byte0]: 64
1781 11:05:11.307227 [Byte1]: 64
1782 11:05:11.311668
1783 11:05:11.311772 Set Vref, RX VrefLevel [Byte0]: 65
1784 11:05:11.314551 [Byte1]: 65
1785 11:05:11.318823
1786 11:05:11.318899 Set Vref, RX VrefLevel [Byte0]: 66
1787 11:05:11.322248 [Byte1]: 66
1788 11:05:11.326549
1789 11:05:11.329787 Set Vref, RX VrefLevel [Byte0]: 67
1790 11:05:11.329863 [Byte1]: 67
1791 11:05:11.334139
1792 11:05:11.334246 Set Vref, RX VrefLevel [Byte0]: 68
1793 11:05:11.337351 [Byte1]: 68
1794 11:05:11.341901
1795 11:05:11.342017 Set Vref, RX VrefLevel [Byte0]: 69
1796 11:05:11.345926 [Byte1]: 69
1797 11:05:11.349342
1798 11:05:11.349446 Set Vref, RX VrefLevel [Byte0]: 70
1799 11:05:11.352699 [Byte1]: 70
1800 11:05:11.357181
1801 11:05:11.357304 Set Vref, RX VrefLevel [Byte0]: 71
1802 11:05:11.360409 [Byte1]: 71
1803 11:05:11.365001
1804 11:05:11.365100 Set Vref, RX VrefLevel [Byte0]: 72
1805 11:05:11.367797 [Byte1]: 72
1806 11:05:11.372164
1807 11:05:11.372262 Set Vref, RX VrefLevel [Byte0]: 73
1808 11:05:11.375508 [Byte1]: 73
1809 11:05:11.380019
1810 11:05:11.380115 Final RX Vref Byte 0 = 57 to rank0
1811 11:05:11.383113 Final RX Vref Byte 1 = 59 to rank0
1812 11:05:11.386331 Final RX Vref Byte 0 = 57 to rank1
1813 11:05:11.390070 Final RX Vref Byte 1 = 59 to rank1==
1814 11:05:11.393105 Dram Type= 6, Freq= 0, CH_1, rank 0
1815 11:05:11.400389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1816 11:05:11.400490 ==
1817 11:05:11.400558 DQS Delay:
1818 11:05:11.400618 DQS0 = 0, DQS1 = 0
1819 11:05:11.402962 DQM Delay:
1820 11:05:11.403035 DQM0 = 86, DQM1 = 81
1821 11:05:11.406577 DQ Delay:
1822 11:05:11.410043 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1823 11:05:11.413053 DQ4 =80, DQ5 =96, DQ6 =100, DQ7 =84
1824 11:05:11.416557 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
1825 11:05:11.419443 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
1826 11:05:11.419527
1827 11:05:11.419592
1828 11:05:11.426192 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a2d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1829 11:05:11.429686 CH1 RK0: MR19=606, MR18=1A2D
1830 11:05:11.436349 CH1_RK0: MR19=0x606, MR18=0x1A2D, DQSOSC=398, MR23=63, INC=93, DEC=62
1831 11:05:11.436453
1832 11:05:11.439583 ----->DramcWriteLeveling(PI) begin...
1833 11:05:11.439674 ==
1834 11:05:11.442670 Dram Type= 6, Freq= 0, CH_1, rank 1
1835 11:05:11.445910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1836 11:05:11.445990 ==
1837 11:05:11.449721 Write leveling (Byte 0): 24 => 24
1838 11:05:11.452605 Write leveling (Byte 1): 29 => 29
1839 11:05:11.456335 DramcWriteLeveling(PI) end<-----
1840 11:05:11.456425
1841 11:05:11.456490 ==
1842 11:05:11.459376 Dram Type= 6, Freq= 0, CH_1, rank 1
1843 11:05:11.462665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1844 11:05:11.462745 ==
1845 11:05:11.466141 [Gating] SW mode calibration
1846 11:05:11.472777 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1847 11:05:11.479280 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1848 11:05:11.482422 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1849 11:05:11.489329 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1850 11:05:11.492431 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 11:05:11.495605 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 11:05:11.502712 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 11:05:11.505911 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 11:05:11.508899 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 11:05:11.515713 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 11:05:11.518924 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 11:05:11.522309 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 11:05:11.525656 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 11:05:11.532038 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 11:05:11.535615 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 11:05:11.538954 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 11:05:11.545408 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 11:05:11.548862 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 11:05:11.552248 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1865 11:05:11.558874 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1866 11:05:11.562077 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 11:05:11.565336 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 11:05:11.571761 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 11:05:11.575414 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 11:05:11.578947 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 11:05:11.585425 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 11:05:11.588992 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 11:05:11.592171 0 9 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1874 11:05:11.598676 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1875 11:05:11.601835 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 11:05:11.605487 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1877 11:05:11.612224 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1878 11:05:11.615070 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1879 11:05:11.619094 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1880 11:05:11.625476 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1881 11:05:11.628652 0 10 4 | B1->B0 | 3030 2c2c | 1 0 | (1 0) (0 0)
1882 11:05:11.631626 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:05:11.638598 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:05:11.641647 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:05:11.644878 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 11:05:11.651403 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:05:11.654749 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:05:11.658210 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:05:11.665027 0 11 4 | B1->B0 | 2626 3a3a | 0 0 | (0 0) (1 1)
1890 11:05:11.668194 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1891 11:05:11.671118 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 11:05:11.677887 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 11:05:11.681223 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 11:05:11.684473 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 11:05:11.691491 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 11:05:11.694743 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1897 11:05:11.697733 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1898 11:05:11.704634 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 11:05:11.708131 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 11:05:11.711546 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 11:05:11.718162 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 11:05:11.721390 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 11:05:11.724842 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 11:05:11.727746 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 11:05:11.734419 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 11:05:11.737639 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 11:05:11.741198 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 11:05:11.747657 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 11:05:11.750997 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 11:05:11.754043 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 11:05:11.760818 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 11:05:11.763910 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1913 11:05:11.767609 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1914 11:05:11.774470 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 11:05:11.777205 Total UI for P1: 0, mck2ui 16
1916 11:05:11.780880 best dqsien dly found for B0: ( 0, 14, 2)
1917 11:05:11.783921 Total UI for P1: 0, mck2ui 16
1918 11:05:11.787358 best dqsien dly found for B1: ( 0, 14, 4)
1919 11:05:11.791285 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1920 11:05:11.794093 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1921 11:05:11.794211
1922 11:05:11.797011 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1923 11:05:11.800324 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1924 11:05:11.803645 [Gating] SW calibration Done
1925 11:05:11.803865 ==
1926 11:05:11.806974 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 11:05:11.810332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 11:05:11.810501 ==
1929 11:05:11.813768 RX Vref Scan: 0
1930 11:05:11.813891
1931 11:05:11.814006 RX Vref 0 -> 0, step: 1
1932 11:05:11.817096
1933 11:05:11.817219 RX Delay -130 -> 252, step: 16
1934 11:05:11.823338 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1935 11:05:11.826892 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1936 11:05:11.830302 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1937 11:05:11.833318 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1938 11:05:11.836567 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1939 11:05:11.843632 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1940 11:05:11.847020 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1941 11:05:11.850181 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1942 11:05:11.853977 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1943 11:05:11.856577 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1944 11:05:11.863607 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1945 11:05:11.866726 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1946 11:05:11.870117 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1947 11:05:11.873399 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1948 11:05:11.876855 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1949 11:05:11.883297 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1950 11:05:11.883446 ==
1951 11:05:11.886659 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 11:05:11.890324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 11:05:11.890455 ==
1954 11:05:11.890570 DQS Delay:
1955 11:05:11.893259 DQS0 = 0, DQS1 = 0
1956 11:05:11.893382 DQM Delay:
1957 11:05:11.896684 DQM0 = 84, DQM1 = 80
1958 11:05:11.896809 DQ Delay:
1959 11:05:11.900076 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1960 11:05:11.902978 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1961 11:05:11.906526 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1962 11:05:11.909666 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1963 11:05:11.909774
1964 11:05:11.909868
1965 11:05:11.909957 ==
1966 11:05:11.913210 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 11:05:11.916462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 11:05:11.919668 ==
1969 11:05:11.919755
1970 11:05:11.919821
1971 11:05:11.919883 TX Vref Scan disable
1972 11:05:11.923023 == TX Byte 0 ==
1973 11:05:11.926552 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1974 11:05:11.930634 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1975 11:05:11.933671 == TX Byte 1 ==
1976 11:05:11.936303 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1977 11:05:11.939937 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1978 11:05:11.943216 ==
1979 11:05:11.946214 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 11:05:11.949704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 11:05:11.949795 ==
1982 11:05:11.962132 TX Vref=22, minBit 1, minWin=26, winSum=441
1983 11:05:11.965849 TX Vref=24, minBit 0, minWin=27, winSum=443
1984 11:05:11.969203 TX Vref=26, minBit 1, minWin=27, winSum=449
1985 11:05:11.972813 TX Vref=28, minBit 2, minWin=27, winSum=454
1986 11:05:11.975643 TX Vref=30, minBit 2, minWin=27, winSum=453
1987 11:05:11.982137 TX Vref=32, minBit 3, minWin=27, winSum=452
1988 11:05:11.985577 [TxChooseVref] Worse bit 2, Min win 27, Win sum 454, Final Vref 28
1989 11:05:11.985713
1990 11:05:11.988769 Final TX Range 1 Vref 28
1991 11:05:11.988895
1992 11:05:11.989004 ==
1993 11:05:11.992292 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 11:05:11.995477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 11:05:11.998878 ==
1996 11:05:11.999025
1997 11:05:11.999169
1998 11:05:11.999281 TX Vref Scan disable
1999 11:05:12.002509 == TX Byte 0 ==
2000 11:05:12.005529 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
2001 11:05:12.012435 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
2002 11:05:12.012569 == TX Byte 1 ==
2003 11:05:12.015369 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2004 11:05:12.022421 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2005 11:05:12.022532
2006 11:05:12.022633 [DATLAT]
2007 11:05:12.022730 Freq=800, CH1 RK1
2008 11:05:12.022861
2009 11:05:12.025733 DATLAT Default: 0xa
2010 11:05:12.025820 0, 0xFFFF, sum = 0
2011 11:05:12.029240 1, 0xFFFF, sum = 0
2012 11:05:12.032156 2, 0xFFFF, sum = 0
2013 11:05:12.032273 3, 0xFFFF, sum = 0
2014 11:05:12.035138 4, 0xFFFF, sum = 0
2015 11:05:12.035224 5, 0xFFFF, sum = 0
2016 11:05:12.038503 6, 0xFFFF, sum = 0
2017 11:05:12.038636 7, 0xFFFF, sum = 0
2018 11:05:12.041747 8, 0xFFFF, sum = 0
2019 11:05:12.041874 9, 0x0, sum = 1
2020 11:05:12.045191 10, 0x0, sum = 2
2021 11:05:12.045336 11, 0x0, sum = 3
2022 11:05:12.048546 12, 0x0, sum = 4
2023 11:05:12.048670 best_step = 10
2024 11:05:12.048822
2025 11:05:12.048984 ==
2026 11:05:12.051833 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 11:05:12.055137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 11:05:12.055262 ==
2029 11:05:12.058153 RX Vref Scan: 0
2030 11:05:12.058278
2031 11:05:12.061875 RX Vref 0 -> 0, step: 1
2032 11:05:12.061998
2033 11:05:12.062110 RX Delay -95 -> 252, step: 8
2034 11:05:12.068875 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2035 11:05:12.072151 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2036 11:05:12.075873 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2037 11:05:12.079021 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
2038 11:05:12.082103 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
2039 11:05:12.089152 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2040 11:05:12.092048 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2041 11:05:12.095794 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2042 11:05:12.098727 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
2043 11:05:12.102436 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2044 11:05:12.109243 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2045 11:05:12.112060 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2046 11:05:12.115460 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2047 11:05:12.118543 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2048 11:05:12.125112 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2049 11:05:12.129074 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2050 11:05:12.129169 ==
2051 11:05:12.132127 Dram Type= 6, Freq= 0, CH_1, rank 1
2052 11:05:12.135254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2053 11:05:12.135375 ==
2054 11:05:12.138276 DQS Delay:
2055 11:05:12.138363 DQS0 = 0, DQS1 = 0
2056 11:05:12.138451 DQM Delay:
2057 11:05:12.141961 DQM0 = 87, DQM1 = 85
2058 11:05:12.142050 DQ Delay:
2059 11:05:12.145788 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2060 11:05:12.148959 DQ4 =88, DQ5 =96, DQ6 =96, DQ7 =84
2061 11:05:12.151804 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =80
2062 11:05:12.154895 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =88
2063 11:05:12.154985
2064 11:05:12.155086
2065 11:05:12.165437 [DQSOSCAuto] RK1, (LSB)MR18= 0x223e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2066 11:05:12.165549 CH1 RK1: MR19=606, MR18=223E
2067 11:05:12.171460 CH1_RK1: MR19=0x606, MR18=0x223E, DQSOSC=394, MR23=63, INC=95, DEC=63
2068 11:05:12.174732 [RxdqsGatingPostProcess] freq 800
2069 11:05:12.181917 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2070 11:05:12.185315 Pre-setting of DQS Precalculation
2071 11:05:12.187921 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2072 11:05:12.198208 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2073 11:05:12.204665 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2074 11:05:12.204791
2075 11:05:12.204908
2076 11:05:12.207681 [Calibration Summary] 1600 Mbps
2077 11:05:12.207782 CH 0, Rank 0
2078 11:05:12.211600 SW Impedance : PASS
2079 11:05:12.211701 DUTY Scan : NO K
2080 11:05:12.214877 ZQ Calibration : PASS
2081 11:05:12.217981 Jitter Meter : NO K
2082 11:05:12.218096 CBT Training : PASS
2083 11:05:12.221360 Write leveling : PASS
2084 11:05:12.224259 RX DQS gating : PASS
2085 11:05:12.224370 RX DQ/DQS(RDDQC) : PASS
2086 11:05:12.227600 TX DQ/DQS : PASS
2087 11:05:12.231127 RX DATLAT : PASS
2088 11:05:12.231226 RX DQ/DQS(Engine): PASS
2089 11:05:12.234206 TX OE : NO K
2090 11:05:12.234307 All Pass.
2091 11:05:12.234423
2092 11:05:12.237822 CH 0, Rank 1
2093 11:05:12.237921 SW Impedance : PASS
2094 11:05:12.240732 DUTY Scan : NO K
2095 11:05:12.240831 ZQ Calibration : PASS
2096 11:05:12.244192 Jitter Meter : NO K
2097 11:05:12.247655 CBT Training : PASS
2098 11:05:12.247742 Write leveling : PASS
2099 11:05:12.250775 RX DQS gating : PASS
2100 11:05:12.254387 RX DQ/DQS(RDDQC) : PASS
2101 11:05:12.254489 TX DQ/DQS : PASS
2102 11:05:12.257438 RX DATLAT : PASS
2103 11:05:12.261032 RX DQ/DQS(Engine): PASS
2104 11:05:12.261133 TX OE : NO K
2105 11:05:12.264337 All Pass.
2106 11:05:12.264437
2107 11:05:12.264524 CH 1, Rank 0
2108 11:05:12.267373 SW Impedance : PASS
2109 11:05:12.267472 DUTY Scan : NO K
2110 11:05:12.270937 ZQ Calibration : PASS
2111 11:05:12.273779 Jitter Meter : NO K
2112 11:05:12.273878 CBT Training : PASS
2113 11:05:12.277466 Write leveling : PASS
2114 11:05:12.280962 RX DQS gating : PASS
2115 11:05:12.281052 RX DQ/DQS(RDDQC) : PASS
2116 11:05:12.284339 TX DQ/DQS : PASS
2117 11:05:12.287379 RX DATLAT : PASS
2118 11:05:12.287512 RX DQ/DQS(Engine): PASS
2119 11:05:12.290597 TX OE : NO K
2120 11:05:12.290685 All Pass.
2121 11:05:12.290752
2122 11:05:12.293833 CH 1, Rank 1
2123 11:05:12.293920 SW Impedance : PASS
2124 11:05:12.296949 DUTY Scan : NO K
2125 11:05:12.300711 ZQ Calibration : PASS
2126 11:05:12.300847 Jitter Meter : NO K
2127 11:05:12.303857 CBT Training : PASS
2128 11:05:12.303968 Write leveling : PASS
2129 11:05:12.307348 RX DQS gating : PASS
2130 11:05:12.310488 RX DQ/DQS(RDDQC) : PASS
2131 11:05:12.310577 TX DQ/DQS : PASS
2132 11:05:12.314173 RX DATLAT : PASS
2133 11:05:12.316856 RX DQ/DQS(Engine): PASS
2134 11:05:12.316945 TX OE : NO K
2135 11:05:12.320274 All Pass.
2136 11:05:12.320362
2137 11:05:12.320430 DramC Write-DBI off
2138 11:05:12.323735 PER_BANK_REFRESH: Hybrid Mode
2139 11:05:12.326775 TX_TRACKING: ON
2140 11:05:12.330646 [GetDramInforAfterCalByMRR] Vendor 6.
2141 11:05:12.333644 [GetDramInforAfterCalByMRR] Revision 606.
2142 11:05:12.336679 [GetDramInforAfterCalByMRR] Revision 2 0.
2143 11:05:12.336796 MR0 0x3b3b
2144 11:05:12.336899 MR8 0x5151
2145 11:05:12.343623 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2146 11:05:12.343743
2147 11:05:12.343813 MR0 0x3b3b
2148 11:05:12.343875 MR8 0x5151
2149 11:05:12.346913 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2150 11:05:12.347000
2151 11:05:12.356703 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2152 11:05:12.360011 [FAST_K] Save calibration result to emmc
2153 11:05:12.363412 [FAST_K] Save calibration result to emmc
2154 11:05:12.366912 dram_init: config_dvfs: 1
2155 11:05:12.369913 dramc_set_vcore_voltage set vcore to 662500
2156 11:05:12.373355 Read voltage for 1200, 2
2157 11:05:12.373496 Vio18 = 0
2158 11:05:12.373608 Vcore = 662500
2159 11:05:12.376945 Vdram = 0
2160 11:05:12.377072 Vddq = 0
2161 11:05:12.377187 Vmddr = 0
2162 11:05:12.383167 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2163 11:05:12.386789 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2164 11:05:12.390172 MEM_TYPE=3, freq_sel=15
2165 11:05:12.393643 sv_algorithm_assistance_LP4_1600
2166 11:05:12.396486 ============ PULL DRAM RESETB DOWN ============
2167 11:05:12.403306 ========== PULL DRAM RESETB DOWN end =========
2168 11:05:12.406921 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2169 11:05:12.409635 ===================================
2170 11:05:12.413112 LPDDR4 DRAM CONFIGURATION
2171 11:05:12.416659 ===================================
2172 11:05:12.416756 EX_ROW_EN[0] = 0x0
2173 11:05:12.420013 EX_ROW_EN[1] = 0x0
2174 11:05:12.420097 LP4Y_EN = 0x0
2175 11:05:12.423194 WORK_FSP = 0x0
2176 11:05:12.423270 WL = 0x4
2177 11:05:12.426371 RL = 0x4
2178 11:05:12.426456 BL = 0x2
2179 11:05:12.430258 RPST = 0x0
2180 11:05:12.430346 RD_PRE = 0x0
2181 11:05:12.432983 WR_PRE = 0x1
2182 11:05:12.433069 WR_PST = 0x0
2183 11:05:12.436684 DBI_WR = 0x0
2184 11:05:12.436772 DBI_RD = 0x0
2185 11:05:12.439688 OTF = 0x1
2186 11:05:12.443090 ===================================
2187 11:05:12.446535 ===================================
2188 11:05:12.446624 ANA top config
2189 11:05:12.450205 ===================================
2190 11:05:12.453221 DLL_ASYNC_EN = 0
2191 11:05:12.456428 ALL_SLAVE_EN = 0
2192 11:05:12.459659 NEW_RANK_MODE = 1
2193 11:05:12.459747 DLL_IDLE_MODE = 1
2194 11:05:12.463236 LP45_APHY_COMB_EN = 1
2195 11:05:12.466396 TX_ODT_DIS = 1
2196 11:05:12.469642 NEW_8X_MODE = 1
2197 11:05:12.473386 ===================================
2198 11:05:12.476391 ===================================
2199 11:05:12.479406 data_rate = 2400
2200 11:05:12.483185 CKR = 1
2201 11:05:12.483314 DQ_P2S_RATIO = 8
2202 11:05:12.486667 ===================================
2203 11:05:12.489495 CA_P2S_RATIO = 8
2204 11:05:12.492866 DQ_CA_OPEN = 0
2205 11:05:12.496161 DQ_SEMI_OPEN = 0
2206 11:05:12.499389 CA_SEMI_OPEN = 0
2207 11:05:12.499499 CA_FULL_RATE = 0
2208 11:05:12.502603 DQ_CKDIV4_EN = 0
2209 11:05:12.506306 CA_CKDIV4_EN = 0
2210 11:05:12.509377 CA_PREDIV_EN = 0
2211 11:05:12.512612 PH8_DLY = 17
2212 11:05:12.515869 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2213 11:05:12.519745 DQ_AAMCK_DIV = 4
2214 11:05:12.519877 CA_AAMCK_DIV = 4
2215 11:05:12.522547 CA_ADMCK_DIV = 4
2216 11:05:12.525814 DQ_TRACK_CA_EN = 0
2217 11:05:12.529439 CA_PICK = 1200
2218 11:05:12.532287 CA_MCKIO = 1200
2219 11:05:12.535822 MCKIO_SEMI = 0
2220 11:05:12.539030 PLL_FREQ = 2366
2221 11:05:12.539161 DQ_UI_PI_RATIO = 32
2222 11:05:12.542329 CA_UI_PI_RATIO = 0
2223 11:05:12.545657 ===================================
2224 11:05:12.549256 ===================================
2225 11:05:12.552055 memory_type:LPDDR4
2226 11:05:12.555807 GP_NUM : 10
2227 11:05:12.555897 SRAM_EN : 1
2228 11:05:12.559235 MD32_EN : 0
2229 11:05:12.562029 ===================================
2230 11:05:12.565501 [ANA_INIT] >>>>>>>>>>>>>>
2231 11:05:12.568539 <<<<<< [CONFIGURE PHASE]: ANA_TX
2232 11:05:12.572162 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2233 11:05:12.575456 ===================================
2234 11:05:12.575581 data_rate = 2400,PCW = 0X5b00
2235 11:05:12.578483 ===================================
2236 11:05:12.582210 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2237 11:05:12.588787 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2238 11:05:12.595294 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2239 11:05:12.599108 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2240 11:05:12.602169 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2241 11:05:12.605160 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2242 11:05:12.608474 [ANA_INIT] flow start
2243 11:05:12.608564 [ANA_INIT] PLL >>>>>>>>
2244 11:05:12.611566 [ANA_INIT] PLL <<<<<<<<
2245 11:05:12.615484 [ANA_INIT] MIDPI >>>>>>>>
2246 11:05:12.618107 [ANA_INIT] MIDPI <<<<<<<<
2247 11:05:12.618234 [ANA_INIT] DLL >>>>>>>>
2248 11:05:12.621836 [ANA_INIT] DLL <<<<<<<<
2249 11:05:12.624854 [ANA_INIT] flow end
2250 11:05:12.627971 ============ LP4 DIFF to SE enter ============
2251 11:05:12.631299 ============ LP4 DIFF to SE exit ============
2252 11:05:12.634864 [ANA_INIT] <<<<<<<<<<<<<
2253 11:05:12.638126 [Flow] Enable top DCM control >>>>>
2254 11:05:12.641807 [Flow] Enable top DCM control <<<<<
2255 11:05:12.644623 Enable DLL master slave shuffle
2256 11:05:12.648114 ==============================================================
2257 11:05:12.651198 Gating Mode config
2258 11:05:12.657980 ==============================================================
2259 11:05:12.658102 Config description:
2260 11:05:12.667921 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2261 11:05:12.674656 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2262 11:05:12.681013 SELPH_MODE 0: By rank 1: By Phase
2263 11:05:12.684034 ==============================================================
2264 11:05:12.688140 GAT_TRACK_EN = 1
2265 11:05:12.691275 RX_GATING_MODE = 2
2266 11:05:12.694177 RX_GATING_TRACK_MODE = 2
2267 11:05:12.697478 SELPH_MODE = 1
2268 11:05:12.701117 PICG_EARLY_EN = 1
2269 11:05:12.704604 VALID_LAT_VALUE = 1
2270 11:05:12.707829 ==============================================================
2271 11:05:12.711067 Enter into Gating configuration >>>>
2272 11:05:12.714328 Exit from Gating configuration <<<<
2273 11:05:12.717414 Enter into DVFS_PRE_config >>>>>
2274 11:05:12.731059 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2275 11:05:12.733990 Exit from DVFS_PRE_config <<<<<
2276 11:05:12.734090 Enter into PICG configuration >>>>
2277 11:05:12.737168 Exit from PICG configuration <<<<
2278 11:05:12.741035 [RX_INPUT] configuration >>>>>
2279 11:05:12.744064 [RX_INPUT] configuration <<<<<
2280 11:05:12.750736 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2281 11:05:12.754081 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2282 11:05:12.760523 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2283 11:05:12.767496 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2284 11:05:12.774211 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2285 11:05:12.780553 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2286 11:05:12.783578 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2287 11:05:12.787001 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2288 11:05:12.790333 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2289 11:05:12.797180 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2290 11:05:12.800281 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2291 11:05:12.803545 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2292 11:05:12.806990 ===================================
2293 11:05:12.810610 LPDDR4 DRAM CONFIGURATION
2294 11:05:12.813753 ===================================
2295 11:05:12.816931 EX_ROW_EN[0] = 0x0
2296 11:05:12.817039 EX_ROW_EN[1] = 0x0
2297 11:05:12.820423 LP4Y_EN = 0x0
2298 11:05:12.820539 WORK_FSP = 0x0
2299 11:05:12.823569 WL = 0x4
2300 11:05:12.823650 RL = 0x4
2301 11:05:12.826920 BL = 0x2
2302 11:05:12.827021 RPST = 0x0
2303 11:05:12.830290 RD_PRE = 0x0
2304 11:05:12.830380 WR_PRE = 0x1
2305 11:05:12.834424 WR_PST = 0x0
2306 11:05:12.834514 DBI_WR = 0x0
2307 11:05:12.837008 DBI_RD = 0x0
2308 11:05:12.837114 OTF = 0x1
2309 11:05:12.839986 ===================================
2310 11:05:12.846647 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2311 11:05:12.850065 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2312 11:05:12.853245 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2313 11:05:12.856806 ===================================
2314 11:05:12.860018 LPDDR4 DRAM CONFIGURATION
2315 11:05:12.862973 ===================================
2316 11:05:12.866433 EX_ROW_EN[0] = 0x10
2317 11:05:12.866569 EX_ROW_EN[1] = 0x0
2318 11:05:12.869967 LP4Y_EN = 0x0
2319 11:05:12.870132 WORK_FSP = 0x0
2320 11:05:12.873017 WL = 0x4
2321 11:05:12.873143 RL = 0x4
2322 11:05:12.876363 BL = 0x2
2323 11:05:12.876492 RPST = 0x0
2324 11:05:12.879621 RD_PRE = 0x0
2325 11:05:12.879748 WR_PRE = 0x1
2326 11:05:12.883184 WR_PST = 0x0
2327 11:05:12.883323 DBI_WR = 0x0
2328 11:05:12.886412 DBI_RD = 0x0
2329 11:05:12.886554 OTF = 0x1
2330 11:05:12.889889 ===================================
2331 11:05:12.896400 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2332 11:05:12.896544 ==
2333 11:05:12.899575 Dram Type= 6, Freq= 0, CH_0, rank 0
2334 11:05:12.906145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2335 11:05:12.906282 ==
2336 11:05:12.906399 [Duty_Offset_Calibration]
2337 11:05:12.909838 B0:2 B1:0 CA:4
2338 11:05:12.909962
2339 11:05:12.913349 [DutyScan_Calibration_Flow] k_type=0
2340 11:05:12.921209
2341 11:05:12.921357 ==CLK 0==
2342 11:05:12.923989 Final CLK duty delay cell = -4
2343 11:05:12.927443 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2344 11:05:12.930683 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2345 11:05:12.934624 [-4] AVG Duty = 4937%(X100)
2346 11:05:12.934718
2347 11:05:12.937664 CH0 CLK Duty spec in!! Max-Min= 187%
2348 11:05:12.940937 [DutyScan_Calibration_Flow] ====Done====
2349 11:05:12.941055
2350 11:05:12.943940 [DutyScan_Calibration_Flow] k_type=1
2351 11:05:12.959609
2352 11:05:12.959747 ==DQS 0 ==
2353 11:05:12.962810 Final DQS duty delay cell = -4
2354 11:05:12.966584 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2355 11:05:12.969432 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2356 11:05:12.973059 [-4] AVG Duty = 4922%(X100)
2357 11:05:12.973142
2358 11:05:12.973207 ==DQS 1 ==
2359 11:05:12.976250 Final DQS duty delay cell = 0
2360 11:05:12.979791 [0] MAX Duty = 5125%(X100), DQS PI = 4
2361 11:05:12.982986 [0] MIN Duty = 4969%(X100), DQS PI = 14
2362 11:05:12.986177 [0] AVG Duty = 5047%(X100)
2363 11:05:12.986260
2364 11:05:12.989325 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2365 11:05:12.989415
2366 11:05:12.992678 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2367 11:05:12.996251 [DutyScan_Calibration_Flow] ====Done====
2368 11:05:12.996343
2369 11:05:12.999487 [DutyScan_Calibration_Flow] k_type=3
2370 11:05:13.016414
2371 11:05:13.016544 ==DQM 0 ==
2372 11:05:13.019883 Final DQM duty delay cell = 0
2373 11:05:13.022680 [0] MAX Duty = 5125%(X100), DQS PI = 20
2374 11:05:13.026535 [0] MIN Duty = 4844%(X100), DQS PI = 52
2375 11:05:13.029984 [0] AVG Duty = 4984%(X100)
2376 11:05:13.030074
2377 11:05:13.030145 ==DQM 1 ==
2378 11:05:13.033040 Final DQM duty delay cell = 0
2379 11:05:13.036086 [0] MAX Duty = 4969%(X100), DQS PI = 2
2380 11:05:13.039462 [0] MIN Duty = 4875%(X100), DQS PI = 20
2381 11:05:13.042512 [0] AVG Duty = 4922%(X100)
2382 11:05:13.042599
2383 11:05:13.045960 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2384 11:05:13.046042
2385 11:05:13.049728 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2386 11:05:13.052662 [DutyScan_Calibration_Flow] ====Done====
2387 11:05:13.052755
2388 11:05:13.055913 [DutyScan_Calibration_Flow] k_type=2
2389 11:05:13.072049
2390 11:05:13.072182 ==DQ 0 ==
2391 11:05:13.075308 Final DQ duty delay cell = -4
2392 11:05:13.078497 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2393 11:05:13.081837 [-4] MIN Duty = 4844%(X100), DQS PI = 50
2394 11:05:13.085282 [-4] AVG Duty = 4922%(X100)
2395 11:05:13.085373
2396 11:05:13.085440 ==DQ 1 ==
2397 11:05:13.088532 Final DQ duty delay cell = 0
2398 11:05:13.091774 [0] MAX Duty = 5125%(X100), DQS PI = 6
2399 11:05:13.095479 [0] MIN Duty = 4938%(X100), DQS PI = 16
2400 11:05:13.098264 [0] AVG Duty = 5031%(X100)
2401 11:05:13.098394
2402 11:05:13.101455 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2403 11:05:13.101586
2404 11:05:13.104797 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2405 11:05:13.108192 [DutyScan_Calibration_Flow] ====Done====
2406 11:05:13.108325 ==
2407 11:05:13.111441 Dram Type= 6, Freq= 0, CH_1, rank 0
2408 11:05:13.115004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2409 11:05:13.115132 ==
2410 11:05:13.118292 [Duty_Offset_Calibration]
2411 11:05:13.118419 B0:0 B1:-1 CA:3
2412 11:05:13.118532
2413 11:05:13.121675 [DutyScan_Calibration_Flow] k_type=0
2414 11:05:13.131529
2415 11:05:13.131676 ==CLK 0==
2416 11:05:13.134617 Final CLK duty delay cell = -4
2417 11:05:13.137926 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2418 11:05:13.140995 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2419 11:05:13.144399 [-4] AVG Duty = 4938%(X100)
2420 11:05:13.144526
2421 11:05:13.147595 CH1 CLK Duty spec in!! Max-Min= 124%
2422 11:05:13.151125 [DutyScan_Calibration_Flow] ====Done====
2423 11:05:13.151252
2424 11:05:13.154197 [DutyScan_Calibration_Flow] k_type=1
2425 11:05:13.171264
2426 11:05:13.171402 ==DQS 0 ==
2427 11:05:13.174344 Final DQS duty delay cell = 0
2428 11:05:13.177617 [0] MAX Duty = 5187%(X100), DQS PI = 18
2429 11:05:13.180820 [0] MIN Duty = 4907%(X100), DQS PI = 38
2430 11:05:13.184263 [0] AVG Duty = 5047%(X100)
2431 11:05:13.184351
2432 11:05:13.184419 ==DQS 1 ==
2433 11:05:13.187761 Final DQS duty delay cell = 0
2434 11:05:13.190758 [0] MAX Duty = 5156%(X100), DQS PI = 8
2435 11:05:13.194003 [0] MIN Duty = 5031%(X100), DQS PI = 18
2436 11:05:13.198002 [0] AVG Duty = 5093%(X100)
2437 11:05:13.198109
2438 11:05:13.201023 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2439 11:05:13.201134
2440 11:05:13.204193 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2441 11:05:13.207795 [DutyScan_Calibration_Flow] ====Done====
2442 11:05:13.207933
2443 11:05:13.210917 [DutyScan_Calibration_Flow] k_type=3
2444 11:05:13.228829
2445 11:05:13.229007 ==DQM 0 ==
2446 11:05:13.231725 Final DQM duty delay cell = 0
2447 11:05:13.234909 [0] MAX Duty = 5031%(X100), DQS PI = 28
2448 11:05:13.238263 [0] MIN Duty = 4813%(X100), DQS PI = 38
2449 11:05:13.238350 [0] AVG Duty = 4922%(X100)
2450 11:05:13.241906
2451 11:05:13.241985 ==DQM 1 ==
2452 11:05:13.245147 Final DQM duty delay cell = 4
2453 11:05:13.248376 [4] MAX Duty = 5187%(X100), DQS PI = 30
2454 11:05:13.251689 [4] MIN Duty = 5062%(X100), DQS PI = 2
2455 11:05:13.251775 [4] AVG Duty = 5124%(X100)
2456 11:05:13.254805
2457 11:05:13.258204 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2458 11:05:13.258289
2459 11:05:13.261913 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2460 11:05:13.264929 [DutyScan_Calibration_Flow] ====Done====
2461 11:05:13.265009
2462 11:05:13.268086 [DutyScan_Calibration_Flow] k_type=2
2463 11:05:13.284621
2464 11:05:13.284727 ==DQ 0 ==
2465 11:05:13.287944 Final DQ duty delay cell = -4
2466 11:05:13.291959 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2467 11:05:13.294827 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2468 11:05:13.298009 [-4] AVG Duty = 4953%(X100)
2469 11:05:13.298090
2470 11:05:13.298162 ==DQ 1 ==
2471 11:05:13.301252 Final DQ duty delay cell = 4
2472 11:05:13.304785 [4] MAX Duty = 5156%(X100), DQS PI = 26
2473 11:05:13.308023 [4] MIN Duty = 5031%(X100), DQS PI = 62
2474 11:05:13.311390 [4] AVG Duty = 5093%(X100)
2475 11:05:13.311482
2476 11:05:13.314725 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2477 11:05:13.314810
2478 11:05:13.318011 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2479 11:05:13.321504 [DutyScan_Calibration_Flow] ====Done====
2480 11:05:13.324786 nWR fixed to 30
2481 11:05:13.327678 [ModeRegInit_LP4] CH0 RK0
2482 11:05:13.327760 [ModeRegInit_LP4] CH0 RK1
2483 11:05:13.331219 [ModeRegInit_LP4] CH1 RK0
2484 11:05:13.334982 [ModeRegInit_LP4] CH1 RK1
2485 11:05:13.335069 match AC timing 7
2486 11:05:13.341104 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2487 11:05:13.344463 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2488 11:05:13.347980 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2489 11:05:13.354560 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2490 11:05:13.358075 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2491 11:05:13.358168 ==
2492 11:05:13.360941 Dram Type= 6, Freq= 0, CH_0, rank 0
2493 11:05:13.364475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2494 11:05:13.364556 ==
2495 11:05:13.370832 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2496 11:05:13.377970 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2497 11:05:13.385175 [CA 0] Center 40 (10~70) winsize 61
2498 11:05:13.388401 [CA 1] Center 39 (9~70) winsize 62
2499 11:05:13.392189 [CA 2] Center 35 (5~66) winsize 62
2500 11:05:13.395447 [CA 3] Center 35 (5~66) winsize 62
2501 11:05:13.398838 [CA 4] Center 33 (3~64) winsize 62
2502 11:05:13.402201 [CA 5] Center 33 (3~63) winsize 61
2503 11:05:13.402299
2504 11:05:13.405665 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2505 11:05:13.405742
2506 11:05:13.408406 [CATrainingPosCal] consider 1 rank data
2507 11:05:13.411696 u2DelayCellTimex100 = 270/100 ps
2508 11:05:13.415061 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2509 11:05:13.422105 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2510 11:05:13.425097 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2511 11:05:13.428188 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2512 11:05:13.432027 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2513 11:05:13.435236 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2514 11:05:13.435325
2515 11:05:13.438244 CA PerBit enable=1, Macro0, CA PI delay=33
2516 11:05:13.438325
2517 11:05:13.441782 [CBTSetCACLKResult] CA Dly = 33
2518 11:05:13.444868 CS Dly: 7 (0~38)
2519 11:05:13.444946 ==
2520 11:05:13.448047 Dram Type= 6, Freq= 0, CH_0, rank 1
2521 11:05:13.451354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 11:05:13.451448 ==
2523 11:05:13.458217 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2524 11:05:13.461181 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2525 11:05:13.470922 [CA 0] Center 39 (9~70) winsize 62
2526 11:05:13.474310 [CA 1] Center 39 (9~70) winsize 62
2527 11:05:13.477635 [CA 2] Center 35 (5~66) winsize 62
2528 11:05:13.481285 [CA 3] Center 35 (5~66) winsize 62
2529 11:05:13.484534 [CA 4] Center 34 (4~65) winsize 62
2530 11:05:13.488115 [CA 5] Center 33 (3~64) winsize 62
2531 11:05:13.488215
2532 11:05:13.491537 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2533 11:05:13.491637
2534 11:05:13.494244 [CATrainingPosCal] consider 2 rank data
2535 11:05:13.497650 u2DelayCellTimex100 = 270/100 ps
2536 11:05:13.500732 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2537 11:05:13.507641 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2538 11:05:13.510946 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2539 11:05:13.513942 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2540 11:05:13.517387 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2541 11:05:13.520736 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2542 11:05:13.520819
2543 11:05:13.524018 CA PerBit enable=1, Macro0, CA PI delay=33
2544 11:05:13.524100
2545 11:05:13.527501 [CBTSetCACLKResult] CA Dly = 33
2546 11:05:13.530624 CS Dly: 8 (0~41)
2547 11:05:13.530706
2548 11:05:13.534120 ----->DramcWriteLeveling(PI) begin...
2549 11:05:13.534203 ==
2550 11:05:13.537340 Dram Type= 6, Freq= 0, CH_0, rank 0
2551 11:05:13.541000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2552 11:05:13.541115 ==
2553 11:05:13.544370 Write leveling (Byte 0): 33 => 33
2554 11:05:13.547035 Write leveling (Byte 1): 25 => 25
2555 11:05:13.550344 DramcWriteLeveling(PI) end<-----
2556 11:05:13.550453
2557 11:05:13.550532 ==
2558 11:05:13.554255 Dram Type= 6, Freq= 0, CH_0, rank 0
2559 11:05:13.557090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2560 11:05:13.557202 ==
2561 11:05:13.560355 [Gating] SW mode calibration
2562 11:05:13.567272 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2563 11:05:13.573637 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2564 11:05:13.577368 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2565 11:05:13.580348 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2566 11:05:13.587115 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2567 11:05:13.590493 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2568 11:05:13.593541 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2569 11:05:13.600751 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2570 11:05:13.603503 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
2571 11:05:13.607023 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2572 11:05:13.613817 1 0 0 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
2573 11:05:13.617050 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 11:05:13.620028 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 11:05:13.626573 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2576 11:05:13.630374 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2577 11:05:13.633057 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2578 11:05:13.639934 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2579 11:05:13.643330 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2580 11:05:13.646556 1 1 0 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2581 11:05:13.653579 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 11:05:13.656260 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 11:05:13.660321 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 11:05:13.666721 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 11:05:13.669856 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2586 11:05:13.673775 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2587 11:05:13.676796 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2588 11:05:13.683328 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2589 11:05:13.686621 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 11:05:13.689765 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 11:05:13.696504 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 11:05:13.699803 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 11:05:13.703498 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 11:05:13.709524 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 11:05:13.712825 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 11:05:13.716440 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 11:05:13.722809 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 11:05:13.726491 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 11:05:13.729563 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 11:05:13.736328 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 11:05:13.739477 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 11:05:13.742804 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 11:05:13.749601 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2604 11:05:13.752732 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2605 11:05:13.756330 Total UI for P1: 0, mck2ui 16
2606 11:05:13.759281 best dqsien dly found for B0: ( 1, 3, 28)
2607 11:05:13.762925 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 11:05:13.766227 Total UI for P1: 0, mck2ui 16
2609 11:05:13.770310 best dqsien dly found for B1: ( 1, 4, 0)
2610 11:05:13.772752 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2611 11:05:13.776544 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2612 11:05:13.776634
2613 11:05:13.782393 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2614 11:05:13.786705 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2615 11:05:13.786792 [Gating] SW calibration Done
2616 11:05:13.789161 ==
2617 11:05:13.792509 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 11:05:13.796010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 11:05:13.796095 ==
2620 11:05:13.796163 RX Vref Scan: 0
2621 11:05:13.796226
2622 11:05:13.799175 RX Vref 0 -> 0, step: 1
2623 11:05:13.799259
2624 11:05:13.802667 RX Delay -40 -> 252, step: 8
2625 11:05:13.806131 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2626 11:05:13.809238 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2627 11:05:13.815719 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2628 11:05:13.818932 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2629 11:05:13.822187 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2630 11:05:13.825434 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2631 11:05:13.828664 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2632 11:05:13.835496 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2633 11:05:13.839010 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2634 11:05:13.842325 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2635 11:05:13.845628 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2636 11:05:13.848632 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2637 11:05:13.855293 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2638 11:05:13.858497 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2639 11:05:13.862040 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2640 11:05:13.865147 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2641 11:05:13.865232 ==
2642 11:05:13.868621 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 11:05:13.871912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 11:05:13.875357 ==
2645 11:05:13.875458 DQS Delay:
2646 11:05:13.875529 DQS0 = 0, DQS1 = 0
2647 11:05:13.878842 DQM Delay:
2648 11:05:13.878921 DQM0 = 117, DQM1 = 107
2649 11:05:13.881962 DQ Delay:
2650 11:05:13.885104 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =111
2651 11:05:13.888395 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
2652 11:05:13.892085 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2653 11:05:13.895067 DQ12 =119, DQ13 =111, DQ14 =115, DQ15 =115
2654 11:05:13.895148
2655 11:05:13.895214
2656 11:05:13.895273 ==
2657 11:05:13.898190 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 11:05:13.901724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 11:05:13.901811 ==
2660 11:05:13.901878
2661 11:05:13.905252
2662 11:05:13.905334 TX Vref Scan disable
2663 11:05:13.909121 == TX Byte 0 ==
2664 11:05:13.912227 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2665 11:05:13.914778 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2666 11:05:13.918507 == TX Byte 1 ==
2667 11:05:13.921633 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2668 11:05:13.924914 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2669 11:05:13.924991 ==
2670 11:05:13.928314 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 11:05:13.935063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 11:05:13.935175 ==
2673 11:05:13.946437 TX Vref=22, minBit 3, minWin=25, winSum=415
2674 11:05:13.949493 TX Vref=24, minBit 1, minWin=25, winSum=418
2675 11:05:13.953145 TX Vref=26, minBit 3, minWin=26, winSum=424
2676 11:05:13.956123 TX Vref=28, minBit 1, minWin=26, winSum=428
2677 11:05:13.959425 TX Vref=30, minBit 2, minWin=26, winSum=428
2678 11:05:13.966000 TX Vref=32, minBit 4, minWin=26, winSum=428
2679 11:05:13.969699 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
2680 11:05:13.969803
2681 11:05:13.972714 Final TX Range 1 Vref 28
2682 11:05:13.972793
2683 11:05:13.972866 ==
2684 11:05:13.976018 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 11:05:13.979172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 11:05:13.982425 ==
2687 11:05:13.982505
2688 11:05:13.982571
2689 11:05:13.982629 TX Vref Scan disable
2690 11:05:13.986393 == TX Byte 0 ==
2691 11:05:13.989038 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2692 11:05:13.995636 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2693 11:05:13.995717 == TX Byte 1 ==
2694 11:05:13.999169 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2695 11:05:14.005993 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2696 11:05:14.006079
2697 11:05:14.006143 [DATLAT]
2698 11:05:14.006203 Freq=1200, CH0 RK0
2699 11:05:14.006269
2700 11:05:14.009136 DATLAT Default: 0xd
2701 11:05:14.012210 0, 0xFFFF, sum = 0
2702 11:05:14.012290 1, 0xFFFF, sum = 0
2703 11:05:14.015503 2, 0xFFFF, sum = 0
2704 11:05:14.015583 3, 0xFFFF, sum = 0
2705 11:05:14.019213 4, 0xFFFF, sum = 0
2706 11:05:14.019295 5, 0xFFFF, sum = 0
2707 11:05:14.022122 6, 0xFFFF, sum = 0
2708 11:05:14.022198 7, 0xFFFF, sum = 0
2709 11:05:14.025517 8, 0xFFFF, sum = 0
2710 11:05:14.025601 9, 0xFFFF, sum = 0
2711 11:05:14.028579 10, 0xFFFF, sum = 0
2712 11:05:14.028656 11, 0xFFFF, sum = 0
2713 11:05:14.032345 12, 0x0, sum = 1
2714 11:05:14.032438 13, 0x0, sum = 2
2715 11:05:14.035465 14, 0x0, sum = 3
2716 11:05:14.035545 15, 0x0, sum = 4
2717 11:05:14.038973 best_step = 13
2718 11:05:14.039046
2719 11:05:14.039107 ==
2720 11:05:14.041953 Dram Type= 6, Freq= 0, CH_0, rank 0
2721 11:05:14.045378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2722 11:05:14.045455 ==
2723 11:05:14.048737 RX Vref Scan: 1
2724 11:05:14.048810
2725 11:05:14.048879 Set Vref Range= 32 -> 127
2726 11:05:14.048961
2727 11:05:14.052035 RX Vref 32 -> 127, step: 1
2728 11:05:14.052115
2729 11:05:14.055293 RX Delay -21 -> 252, step: 4
2730 11:05:14.055384
2731 11:05:14.058675 Set Vref, RX VrefLevel [Byte0]: 32
2732 11:05:14.062254 [Byte1]: 32
2733 11:05:14.062336
2734 11:05:14.065137 Set Vref, RX VrefLevel [Byte0]: 33
2735 11:05:14.068947 [Byte1]: 33
2736 11:05:14.072666
2737 11:05:14.072767 Set Vref, RX VrefLevel [Byte0]: 34
2738 11:05:14.075664 [Byte1]: 34
2739 11:05:14.080246
2740 11:05:14.080332 Set Vref, RX VrefLevel [Byte0]: 35
2741 11:05:14.083376 [Byte1]: 35
2742 11:05:14.088357
2743 11:05:14.088448 Set Vref, RX VrefLevel [Byte0]: 36
2744 11:05:14.091797 [Byte1]: 36
2745 11:05:14.096757
2746 11:05:14.096870 Set Vref, RX VrefLevel [Byte0]: 37
2747 11:05:14.099328 [Byte1]: 37
2748 11:05:14.103969
2749 11:05:14.104073 Set Vref, RX VrefLevel [Byte0]: 38
2750 11:05:14.107429 [Byte1]: 38
2751 11:05:14.112415
2752 11:05:14.112505 Set Vref, RX VrefLevel [Byte0]: 39
2753 11:05:14.115507 [Byte1]: 39
2754 11:05:14.119894
2755 11:05:14.119979 Set Vref, RX VrefLevel [Byte0]: 40
2756 11:05:14.123439 [Byte1]: 40
2757 11:05:14.128401
2758 11:05:14.128491 Set Vref, RX VrefLevel [Byte0]: 41
2759 11:05:14.131290 [Byte1]: 41
2760 11:05:14.135893
2761 11:05:14.135977 Set Vref, RX VrefLevel [Byte0]: 42
2762 11:05:14.138982 [Byte1]: 42
2763 11:05:14.144093
2764 11:05:14.144189 Set Vref, RX VrefLevel [Byte0]: 43
2765 11:05:14.147132 [Byte1]: 43
2766 11:05:14.152408
2767 11:05:14.152492 Set Vref, RX VrefLevel [Byte0]: 44
2768 11:05:14.154978 [Byte1]: 44
2769 11:05:14.159597
2770 11:05:14.159680 Set Vref, RX VrefLevel [Byte0]: 45
2771 11:05:14.162714 [Byte1]: 45
2772 11:05:14.167245
2773 11:05:14.167356 Set Vref, RX VrefLevel [Byte0]: 46
2774 11:05:14.171216 [Byte1]: 46
2775 11:05:14.175767
2776 11:05:14.175965 Set Vref, RX VrefLevel [Byte0]: 47
2777 11:05:14.179085 [Byte1]: 47
2778 11:05:14.183801
2779 11:05:14.183908 Set Vref, RX VrefLevel [Byte0]: 48
2780 11:05:14.190283 [Byte1]: 48
2781 11:05:14.190390
2782 11:05:14.193422 Set Vref, RX VrefLevel [Byte0]: 49
2783 11:05:14.196391 [Byte1]: 49
2784 11:05:14.196480
2785 11:05:14.199923 Set Vref, RX VrefLevel [Byte0]: 50
2786 11:05:14.203189 [Byte1]: 50
2787 11:05:14.206986
2788 11:05:14.207087 Set Vref, RX VrefLevel [Byte0]: 51
2789 11:05:14.210255 [Byte1]: 51
2790 11:05:14.215253
2791 11:05:14.215399 Set Vref, RX VrefLevel [Byte0]: 52
2792 11:05:14.218391 [Byte1]: 52
2793 11:05:14.223082
2794 11:05:14.223241 Set Vref, RX VrefLevel [Byte0]: 53
2795 11:05:14.226510 [Byte1]: 53
2796 11:05:14.231056
2797 11:05:14.231155 Set Vref, RX VrefLevel [Byte0]: 54
2798 11:05:14.234207 [Byte1]: 54
2799 11:05:14.239200
2800 11:05:14.239309 Set Vref, RX VrefLevel [Byte0]: 55
2801 11:05:14.242202 [Byte1]: 55
2802 11:05:14.247309
2803 11:05:14.247428 Set Vref, RX VrefLevel [Byte0]: 56
2804 11:05:14.249971 [Byte1]: 56
2805 11:05:14.254709
2806 11:05:14.254797 Set Vref, RX VrefLevel [Byte0]: 57
2807 11:05:14.258070 [Byte1]: 57
2808 11:05:14.262933
2809 11:05:14.263016 Set Vref, RX VrefLevel [Byte0]: 58
2810 11:05:14.266009 [Byte1]: 58
2811 11:05:14.270746
2812 11:05:14.270844 Set Vref, RX VrefLevel [Byte0]: 59
2813 11:05:14.274272 [Byte1]: 59
2814 11:05:14.278789
2815 11:05:14.278888 Set Vref, RX VrefLevel [Byte0]: 60
2816 11:05:14.281855 [Byte1]: 60
2817 11:05:14.286524
2818 11:05:14.286622 Set Vref, RX VrefLevel [Byte0]: 61
2819 11:05:14.290403 [Byte1]: 61
2820 11:05:14.294570
2821 11:05:14.294780 Set Vref, RX VrefLevel [Byte0]: 62
2822 11:05:14.297747 [Byte1]: 62
2823 11:05:14.302353
2824 11:05:14.302551 Set Vref, RX VrefLevel [Byte0]: 63
2825 11:05:14.305557 [Byte1]: 63
2826 11:05:14.310600
2827 11:05:14.310766 Set Vref, RX VrefLevel [Byte0]: 64
2828 11:05:14.313487 [Byte1]: 64
2829 11:05:14.318001
2830 11:05:14.321622 Set Vref, RX VrefLevel [Byte0]: 65
2831 11:05:14.324650 [Byte1]: 65
2832 11:05:14.324801
2833 11:05:14.327843 Set Vref, RX VrefLevel [Byte0]: 66
2834 11:05:14.331511 [Byte1]: 66
2835 11:05:14.331609
2836 11:05:14.334931 Set Vref, RX VrefLevel [Byte0]: 67
2837 11:05:14.337780 [Byte1]: 67
2838 11:05:14.341894
2839 11:05:14.341978 Set Vref, RX VrefLevel [Byte0]: 68
2840 11:05:14.345084 [Byte1]: 68
2841 11:05:14.350105
2842 11:05:14.350182 Set Vref, RX VrefLevel [Byte0]: 69
2843 11:05:14.353628 [Byte1]: 69
2844 11:05:14.357728
2845 11:05:14.357815 Final RX Vref Byte 0 = 54 to rank0
2846 11:05:14.360989 Final RX Vref Byte 1 = 59 to rank0
2847 11:05:14.364142 Final RX Vref Byte 0 = 54 to rank1
2848 11:05:14.367772 Final RX Vref Byte 1 = 59 to rank1==
2849 11:05:14.371116 Dram Type= 6, Freq= 0, CH_0, rank 0
2850 11:05:14.377671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 11:05:14.377824 ==
2852 11:05:14.377929 DQS Delay:
2853 11:05:14.378041 DQS0 = 0, DQS1 = 0
2854 11:05:14.380984 DQM Delay:
2855 11:05:14.381124 DQM0 = 116, DQM1 = 105
2856 11:05:14.384576 DQ Delay:
2857 11:05:14.387447 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =112
2858 11:05:14.391225 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2859 11:05:14.394308 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2860 11:05:14.397393 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2861 11:05:14.397534
2862 11:05:14.397652
2863 11:05:14.404222 [DQSOSCAuto] RK0, (LSB)MR18= 0x1fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2864 11:05:14.407387 CH0 RK0: MR19=403, MR18=1FC
2865 11:05:14.414142 CH0_RK0: MR19=0x403, MR18=0x1FC, DQSOSC=409, MR23=63, INC=39, DEC=26
2866 11:05:14.414259
2867 11:05:14.417869 ----->DramcWriteLeveling(PI) begin...
2868 11:05:14.417956 ==
2869 11:05:14.420802 Dram Type= 6, Freq= 0, CH_0, rank 1
2870 11:05:14.424271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2871 11:05:14.427302 ==
2872 11:05:14.427425 Write leveling (Byte 0): 34 => 34
2873 11:05:14.430468 Write leveling (Byte 1): 28 => 28
2874 11:05:14.433864 DramcWriteLeveling(PI) end<-----
2875 11:05:14.433938
2876 11:05:14.434002 ==
2877 11:05:14.437061 Dram Type= 6, Freq= 0, CH_0, rank 1
2878 11:05:14.443759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2879 11:05:14.443848 ==
2880 11:05:14.447046 [Gating] SW mode calibration
2881 11:05:14.453501 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2882 11:05:14.457134 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2883 11:05:14.464074 0 15 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2884 11:05:14.466757 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2885 11:05:14.470038 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 11:05:14.476627 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 11:05:14.480648 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 11:05:14.483659 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2889 11:05:14.490199 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
2890 11:05:14.493304 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2891 11:05:14.496727 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
2892 11:05:14.503165 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 11:05:14.507314 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 11:05:14.509900 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 11:05:14.516489 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 11:05:14.519915 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 11:05:14.523400 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2898 11:05:14.529694 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2899 11:05:14.532859 1 1 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
2900 11:05:14.536222 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 11:05:14.539484 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 11:05:14.546633 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 11:05:14.549558 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 11:05:14.553268 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 11:05:14.559391 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2906 11:05:14.562646 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2907 11:05:14.566619 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2908 11:05:14.573029 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 11:05:14.576356 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 11:05:14.579293 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 11:05:14.586260 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 11:05:14.589465 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 11:05:14.592821 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 11:05:14.599910 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 11:05:14.602728 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 11:05:14.606724 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 11:05:14.612575 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 11:05:14.616110 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 11:05:14.619598 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 11:05:14.625929 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 11:05:14.629163 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2922 11:05:14.632709 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2923 11:05:14.639785 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2924 11:05:14.639976 Total UI for P1: 0, mck2ui 16
2925 11:05:14.646068 best dqsien dly found for B0: ( 1, 3, 26)
2926 11:05:14.649254 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 11:05:14.652431 Total UI for P1: 0, mck2ui 16
2928 11:05:14.656673 best dqsien dly found for B1: ( 1, 4, 0)
2929 11:05:14.658963 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2930 11:05:14.662526 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2931 11:05:14.662655
2932 11:05:14.665687 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2933 11:05:14.669183 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2934 11:05:14.672575 [Gating] SW calibration Done
2935 11:05:14.672692 ==
2936 11:05:14.675671 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 11:05:14.679253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 11:05:14.679358 ==
2939 11:05:14.682786 RX Vref Scan: 0
2940 11:05:14.682870
2941 11:05:14.685749 RX Vref 0 -> 0, step: 1
2942 11:05:14.685833
2943 11:05:14.685899 RX Delay -40 -> 252, step: 8
2944 11:05:14.692387 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2945 11:05:14.695540 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2946 11:05:14.698847 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2947 11:05:14.702026 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2948 11:05:14.708700 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2949 11:05:14.712448 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2950 11:05:14.715574 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2951 11:05:14.718751 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2952 11:05:14.722068 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2953 11:05:14.725421 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2954 11:05:14.732327 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2955 11:05:14.735705 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2956 11:05:14.738474 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2957 11:05:14.742054 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
2958 11:05:14.748345 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2959 11:05:14.751736 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2960 11:05:14.751904 ==
2961 11:05:14.755078 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 11:05:14.758893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 11:05:14.759057 ==
2964 11:05:14.761699 DQS Delay:
2965 11:05:14.761844 DQS0 = 0, DQS1 = 0
2966 11:05:14.761972 DQM Delay:
2967 11:05:14.765265 DQM0 = 115, DQM1 = 108
2968 11:05:14.765407 DQ Delay:
2969 11:05:14.768241 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2970 11:05:14.771942 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =119
2971 11:05:14.774935 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2972 11:05:14.778364 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2973 11:05:14.781861
2974 11:05:14.782031
2975 11:05:14.782154 ==
2976 11:05:14.785089 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 11:05:14.788178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 11:05:14.788327 ==
2979 11:05:14.788449
2980 11:05:14.788571
2981 11:05:14.791778 TX Vref Scan disable
2982 11:05:14.791943 == TX Byte 0 ==
2983 11:05:14.798205 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2984 11:05:14.801367 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2985 11:05:14.801518 == TX Byte 1 ==
2986 11:05:14.808004 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2987 11:05:14.811555 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2988 11:05:14.811707 ==
2989 11:05:14.815120 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 11:05:14.817997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 11:05:14.818119 ==
2992 11:05:14.831303 TX Vref=22, minBit 10, minWin=25, winSum=418
2993 11:05:14.834716 TX Vref=24, minBit 0, minWin=26, winSum=423
2994 11:05:14.838124 TX Vref=26, minBit 0, minWin=26, winSum=428
2995 11:05:14.841187 TX Vref=28, minBit 12, minWin=25, winSum=426
2996 11:05:14.844607 TX Vref=30, minBit 12, minWin=25, winSum=434
2997 11:05:14.850994 TX Vref=32, minBit 14, minWin=25, winSum=433
2998 11:05:14.854579 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 26
2999 11:05:14.854733
3000 11:05:14.857751 Final TX Range 1 Vref 26
3001 11:05:14.857880
3002 11:05:14.857997 ==
3003 11:05:14.861109 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 11:05:14.867516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 11:05:14.867652 ==
3006 11:05:14.867769
3007 11:05:14.867882
3008 11:05:14.867993 TX Vref Scan disable
3009 11:05:14.871078 == TX Byte 0 ==
3010 11:05:14.874419 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3011 11:05:14.881265 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3012 11:05:14.881401 == TX Byte 1 ==
3013 11:05:14.884647 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3014 11:05:14.891168 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3015 11:05:14.891301
3016 11:05:14.891427 [DATLAT]
3017 11:05:14.891540 Freq=1200, CH0 RK1
3018 11:05:14.891655
3019 11:05:14.894550 DATLAT Default: 0xd
3020 11:05:14.894675 0, 0xFFFF, sum = 0
3021 11:05:14.898056 1, 0xFFFF, sum = 0
3022 11:05:14.901506 2, 0xFFFF, sum = 0
3023 11:05:14.901633 3, 0xFFFF, sum = 0
3024 11:05:14.904484 4, 0xFFFF, sum = 0
3025 11:05:14.904605 5, 0xFFFF, sum = 0
3026 11:05:14.907764 6, 0xFFFF, sum = 0
3027 11:05:14.907897 7, 0xFFFF, sum = 0
3028 11:05:14.910738 8, 0xFFFF, sum = 0
3029 11:05:14.910865 9, 0xFFFF, sum = 0
3030 11:05:14.914676 10, 0xFFFF, sum = 0
3031 11:05:14.914810 11, 0xFFFF, sum = 0
3032 11:05:14.917936 12, 0x0, sum = 1
3033 11:05:14.918045 13, 0x0, sum = 2
3034 11:05:14.920963 14, 0x0, sum = 3
3035 11:05:14.921049 15, 0x0, sum = 4
3036 11:05:14.924354 best_step = 13
3037 11:05:14.924465
3038 11:05:14.924561 ==
3039 11:05:14.927519 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 11:05:14.931001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 11:05:14.931116 ==
3042 11:05:14.931213 RX Vref Scan: 0
3043 11:05:14.931304
3044 11:05:14.934157 RX Vref 0 -> 0, step: 1
3045 11:05:14.934241
3046 11:05:14.937688 RX Delay -21 -> 252, step: 4
3047 11:05:14.941075 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3048 11:05:14.947476 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3049 11:05:14.950962 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3050 11:05:14.954324 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3051 11:05:14.957270 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3052 11:05:14.961035 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3053 11:05:14.967498 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3054 11:05:14.971028 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3055 11:05:14.974045 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3056 11:05:14.977306 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3057 11:05:14.981459 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3058 11:05:14.987493 iDelay=195, Bit 11, Center 100 (31 ~ 170) 140
3059 11:05:14.990625 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3060 11:05:14.994527 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3061 11:05:14.997052 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3062 11:05:15.003943 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3063 11:05:15.004034 ==
3064 11:05:15.007859 Dram Type= 6, Freq= 0, CH_0, rank 1
3065 11:05:15.010571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 11:05:15.010657 ==
3067 11:05:15.010729 DQS Delay:
3068 11:05:15.013818 DQS0 = 0, DQS1 = 0
3069 11:05:15.013904 DQM Delay:
3070 11:05:15.017176 DQM0 = 116, DQM1 = 106
3071 11:05:15.017260 DQ Delay:
3072 11:05:15.020348 DQ0 =112, DQ1 =118, DQ2 =112, DQ3 =112
3073 11:05:15.023775 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
3074 11:05:15.027264 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3075 11:05:15.030556 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =112
3076 11:05:15.030642
3077 11:05:15.030709
3078 11:05:15.040713 [DQSOSCAuto] RK1, (LSB)MR18= 0xfaf8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
3079 11:05:15.043424 CH0 RK1: MR19=303, MR18=FAF8
3080 11:05:15.046894 CH0_RK1: MR19=0x303, MR18=0xFAF8, DQSOSC=412, MR23=63, INC=38, DEC=25
3081 11:05:15.050076 [RxdqsGatingPostProcess] freq 1200
3082 11:05:15.056844 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3083 11:05:15.060540 best DQS0 dly(2T, 0.5T) = (0, 11)
3084 11:05:15.063602 best DQS1 dly(2T, 0.5T) = (0, 12)
3085 11:05:15.067141 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3086 11:05:15.070343 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3087 11:05:15.073594 best DQS0 dly(2T, 0.5T) = (0, 11)
3088 11:05:15.076674 best DQS1 dly(2T, 0.5T) = (0, 12)
3089 11:05:15.079987 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3090 11:05:15.083192 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3091 11:05:15.086474 Pre-setting of DQS Precalculation
3092 11:05:15.090207 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3093 11:05:15.090299 ==
3094 11:05:15.093113 Dram Type= 6, Freq= 0, CH_1, rank 0
3095 11:05:15.096365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 11:05:15.096452 ==
3097 11:05:15.103212 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3098 11:05:15.110116 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3099 11:05:15.117522 [CA 0] Center 38 (8~68) winsize 61
3100 11:05:15.121133 [CA 1] Center 37 (7~68) winsize 62
3101 11:05:15.124154 [CA 2] Center 35 (6~65) winsize 60
3102 11:05:15.127724 [CA 3] Center 34 (4~64) winsize 61
3103 11:05:15.130877 [CA 4] Center 34 (5~64) winsize 60
3104 11:05:15.133913 [CA 5] Center 33 (3~64) winsize 62
3105 11:05:15.133999
3106 11:05:15.137205 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3107 11:05:15.137291
3108 11:05:15.140961 [CATrainingPosCal] consider 1 rank data
3109 11:05:15.144366 u2DelayCellTimex100 = 270/100 ps
3110 11:05:15.147375 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3111 11:05:15.154323 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3112 11:05:15.157535 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3113 11:05:15.160875 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3114 11:05:15.164030 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3115 11:05:15.167309 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3116 11:05:15.167443
3117 11:05:15.170958 CA PerBit enable=1, Macro0, CA PI delay=33
3118 11:05:15.171079
3119 11:05:15.173918 [CBTSetCACLKResult] CA Dly = 33
3120 11:05:15.174027 CS Dly: 5 (0~36)
3121 11:05:15.177208 ==
3122 11:05:15.180337 Dram Type= 6, Freq= 0, CH_1, rank 1
3123 11:05:15.184153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 11:05:15.184235 ==
3125 11:05:15.187316 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3126 11:05:15.193999 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3127 11:05:15.203302 [CA 0] Center 37 (7~68) winsize 62
3128 11:05:15.207094 [CA 1] Center 38 (8~68) winsize 61
3129 11:05:15.209793 [CA 2] Center 35 (5~65) winsize 61
3130 11:05:15.213197 [CA 3] Center 33 (3~64) winsize 62
3131 11:05:15.216355 [CA 4] Center 33 (3~64) winsize 62
3132 11:05:15.220187 [CA 5] Center 33 (4~63) winsize 60
3133 11:05:15.220285
3134 11:05:15.223084 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3135 11:05:15.223182
3136 11:05:15.226706 [CATrainingPosCal] consider 2 rank data
3137 11:05:15.229636 u2DelayCellTimex100 = 270/100 ps
3138 11:05:15.232951 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3139 11:05:15.240036 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3140 11:05:15.243031 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3141 11:05:15.246414 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3142 11:05:15.249946 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3143 11:05:15.252654 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3144 11:05:15.252736
3145 11:05:15.256260 CA PerBit enable=1, Macro0, CA PI delay=33
3146 11:05:15.256338
3147 11:05:15.259319 [CBTSetCACLKResult] CA Dly = 33
3148 11:05:15.262569 CS Dly: 6 (0~39)
3149 11:05:15.262673
3150 11:05:15.266066 ----->DramcWriteLeveling(PI) begin...
3151 11:05:15.266178 ==
3152 11:05:15.269423 Dram Type= 6, Freq= 0, CH_1, rank 0
3153 11:05:15.272868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3154 11:05:15.272955 ==
3155 11:05:15.275821 Write leveling (Byte 0): 27 => 27
3156 11:05:15.279358 Write leveling (Byte 1): 27 => 27
3157 11:05:15.282993 DramcWriteLeveling(PI) end<-----
3158 11:05:15.283120
3159 11:05:15.283242 ==
3160 11:05:15.285734 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 11:05:15.289337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 11:05:15.289468 ==
3163 11:05:15.292949 [Gating] SW mode calibration
3164 11:05:15.299282 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3165 11:05:15.306277 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3166 11:05:15.309779 0 15 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
3167 11:05:15.313046 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 11:05:15.319462 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 11:05:15.322672 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 11:05:15.325606 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3171 11:05:15.332429 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 11:05:15.336042 0 15 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
3173 11:05:15.339248 0 15 28 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
3174 11:05:15.346170 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 11:05:15.349225 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 11:05:15.352274 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 11:05:15.359235 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 11:05:15.362516 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 11:05:15.365821 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 11:05:15.368838 1 0 24 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
3181 11:05:15.375803 1 0 28 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
3182 11:05:15.379089 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 11:05:15.382413 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 11:05:15.389477 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 11:05:15.392792 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 11:05:15.395671 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 11:05:15.402528 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 11:05:15.405505 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3189 11:05:15.409302 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3190 11:05:15.416086 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 11:05:15.419227 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 11:05:15.423127 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 11:05:15.429174 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 11:05:15.432603 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 11:05:15.435515 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 11:05:15.443316 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 11:05:15.446130 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 11:05:15.448604 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 11:05:15.455484 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 11:05:15.458732 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 11:05:15.462151 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 11:05:15.468813 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 11:05:15.471746 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 11:05:15.475216 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3205 11:05:15.481557 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3206 11:05:15.485448 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 11:05:15.488074 Total UI for P1: 0, mck2ui 16
3208 11:05:15.491755 best dqsien dly found for B0: ( 1, 3, 26)
3209 11:05:15.495274 Total UI for P1: 0, mck2ui 16
3210 11:05:15.498227 best dqsien dly found for B1: ( 1, 3, 26)
3211 11:05:15.502095 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3212 11:05:15.504958 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3213 11:05:15.505079
3214 11:05:15.508318 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3215 11:05:15.511652 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3216 11:05:15.515219 [Gating] SW calibration Done
3217 11:05:15.515333 ==
3218 11:05:15.518289 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 11:05:15.521376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 11:05:15.525012 ==
3221 11:05:15.525145 RX Vref Scan: 0
3222 11:05:15.525265
3223 11:05:15.528227 RX Vref 0 -> 0, step: 1
3224 11:05:15.528313
3225 11:05:15.528381 RX Delay -40 -> 252, step: 8
3226 11:05:15.535019 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3227 11:05:15.538182 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3228 11:05:15.541558 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3229 11:05:15.545079 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3230 11:05:15.548380 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3231 11:05:15.554719 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3232 11:05:15.558599 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3233 11:05:15.561631 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3234 11:05:15.564785 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3235 11:05:15.568237 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3236 11:05:15.574949 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3237 11:05:15.577845 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3238 11:05:15.581644 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3239 11:05:15.585118 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3240 11:05:15.591020 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3241 11:05:15.594423 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3242 11:05:15.594517 ==
3243 11:05:15.597693 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 11:05:15.601245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 11:05:15.601332 ==
3246 11:05:15.601399 DQS Delay:
3247 11:05:15.604295 DQS0 = 0, DQS1 = 0
3248 11:05:15.604380 DQM Delay:
3249 11:05:15.607940 DQM0 = 115, DQM1 = 112
3250 11:05:15.608026 DQ Delay:
3251 11:05:15.611658 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3252 11:05:15.614521 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3253 11:05:15.617783 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3254 11:05:15.624388 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3255 11:05:15.624509
3256 11:05:15.624602
3257 11:05:15.624685 ==
3258 11:05:15.627633 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 11:05:15.631419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 11:05:15.631508 ==
3261 11:05:15.631597
3262 11:05:15.631680
3263 11:05:15.634433 TX Vref Scan disable
3264 11:05:15.634520 == TX Byte 0 ==
3265 11:05:15.641009 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3266 11:05:15.644287 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3267 11:05:15.644375 == TX Byte 1 ==
3268 11:05:15.651066 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3269 11:05:15.654408 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3270 11:05:15.654494 ==
3271 11:05:15.657627 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 11:05:15.661101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 11:05:15.661217 ==
3274 11:05:15.673256 TX Vref=22, minBit 9, minWin=24, winSum=409
3275 11:05:15.676705 TX Vref=24, minBit 1, minWin=25, winSum=413
3276 11:05:15.680003 TX Vref=26, minBit 1, minWin=25, winSum=416
3277 11:05:15.683004 TX Vref=28, minBit 3, minWin=25, winSum=425
3278 11:05:15.686594 TX Vref=30, minBit 1, minWin=26, winSum=429
3279 11:05:15.692791 TX Vref=32, minBit 1, minWin=26, winSum=423
3280 11:05:15.696291 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
3281 11:05:15.696386
3282 11:05:15.699453 Final TX Range 1 Vref 30
3283 11:05:15.699566
3284 11:05:15.699651 ==
3285 11:05:15.702863 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 11:05:15.706339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 11:05:15.709509 ==
3288 11:05:15.709597
3289 11:05:15.709664
3290 11:05:15.709725 TX Vref Scan disable
3291 11:05:15.712769 == TX Byte 0 ==
3292 11:05:15.716107 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3293 11:05:15.719678 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3294 11:05:15.722870 == TX Byte 1 ==
3295 11:05:15.726569 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3296 11:05:15.729446 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3297 11:05:15.733387
3298 11:05:15.733478 [DATLAT]
3299 11:05:15.733545 Freq=1200, CH1 RK0
3300 11:05:15.733625
3301 11:05:15.735926 DATLAT Default: 0xd
3302 11:05:15.736014 0, 0xFFFF, sum = 0
3303 11:05:15.739595 1, 0xFFFF, sum = 0
3304 11:05:15.739681 2, 0xFFFF, sum = 0
3305 11:05:15.743106 3, 0xFFFF, sum = 0
3306 11:05:15.746956 4, 0xFFFF, sum = 0
3307 11:05:15.747044 5, 0xFFFF, sum = 0
3308 11:05:15.749425 6, 0xFFFF, sum = 0
3309 11:05:15.749523 7, 0xFFFF, sum = 0
3310 11:05:15.753087 8, 0xFFFF, sum = 0
3311 11:05:15.753175 9, 0xFFFF, sum = 0
3312 11:05:15.755946 10, 0xFFFF, sum = 0
3313 11:05:15.756034 11, 0xFFFF, sum = 0
3314 11:05:15.760035 12, 0x0, sum = 1
3315 11:05:15.760122 13, 0x0, sum = 2
3316 11:05:15.762651 14, 0x0, sum = 3
3317 11:05:15.762737 15, 0x0, sum = 4
3318 11:05:15.762806 best_step = 13
3319 11:05:15.766352
3320 11:05:15.766439 ==
3321 11:05:15.769563 Dram Type= 6, Freq= 0, CH_1, rank 0
3322 11:05:15.772955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3323 11:05:15.773043 ==
3324 11:05:15.773111 RX Vref Scan: 1
3325 11:05:15.773174
3326 11:05:15.776054 Set Vref Range= 32 -> 127
3327 11:05:15.776138
3328 11:05:15.779626 RX Vref 32 -> 127, step: 1
3329 11:05:15.779711
3330 11:05:15.782425 RX Delay -13 -> 252, step: 4
3331 11:05:15.782510
3332 11:05:15.786183 Set Vref, RX VrefLevel [Byte0]: 32
3333 11:05:15.789673 [Byte1]: 32
3334 11:05:15.789759
3335 11:05:15.792993 Set Vref, RX VrefLevel [Byte0]: 33
3336 11:05:15.796036 [Byte1]: 33
3337 11:05:15.800271
3338 11:05:15.800358 Set Vref, RX VrefLevel [Byte0]: 34
3339 11:05:15.802606 [Byte1]: 34
3340 11:05:15.806888
3341 11:05:15.807003 Set Vref, RX VrefLevel [Byte0]: 35
3342 11:05:15.810572 [Byte1]: 35
3343 11:05:15.814808
3344 11:05:15.814912 Set Vref, RX VrefLevel [Byte0]: 36
3345 11:05:15.818364 [Byte1]: 36
3346 11:05:15.823039
3347 11:05:15.823132 Set Vref, RX VrefLevel [Byte0]: 37
3348 11:05:15.826191 [Byte1]: 37
3349 11:05:15.830557
3350 11:05:15.830649 Set Vref, RX VrefLevel [Byte0]: 38
3351 11:05:15.834020 [Byte1]: 38
3352 11:05:15.838875
3353 11:05:15.838964 Set Vref, RX VrefLevel [Byte0]: 39
3354 11:05:15.841766 [Byte1]: 39
3355 11:05:15.846877
3356 11:05:15.846969 Set Vref, RX VrefLevel [Byte0]: 40
3357 11:05:15.849910 [Byte1]: 40
3358 11:05:15.854442
3359 11:05:15.854532 Set Vref, RX VrefLevel [Byte0]: 41
3360 11:05:15.858084 [Byte1]: 41
3361 11:05:15.862287
3362 11:05:15.862379 Set Vref, RX VrefLevel [Byte0]: 42
3363 11:05:15.865553 [Byte1]: 42
3364 11:05:15.870234
3365 11:05:15.870322 Set Vref, RX VrefLevel [Byte0]: 43
3366 11:05:15.873293 [Byte1]: 43
3367 11:05:15.878156
3368 11:05:15.878240 Set Vref, RX VrefLevel [Byte0]: 44
3369 11:05:15.881351 [Byte1]: 44
3370 11:05:15.886460
3371 11:05:15.886547 Set Vref, RX VrefLevel [Byte0]: 45
3372 11:05:15.889639 [Byte1]: 45
3373 11:05:15.893770
3374 11:05:15.893906 Set Vref, RX VrefLevel [Byte0]: 46
3375 11:05:15.896910 [Byte1]: 46
3376 11:05:15.901969
3377 11:05:15.902096 Set Vref, RX VrefLevel [Byte0]: 47
3378 11:05:15.905095 [Byte1]: 47
3379 11:05:15.909992
3380 11:05:15.910119 Set Vref, RX VrefLevel [Byte0]: 48
3381 11:05:15.912748 [Byte1]: 48
3382 11:05:15.917847
3383 11:05:15.917933 Set Vref, RX VrefLevel [Byte0]: 49
3384 11:05:15.921030 [Byte1]: 49
3385 11:05:15.925154
3386 11:05:15.925239 Set Vref, RX VrefLevel [Byte0]: 50
3387 11:05:15.928735 [Byte1]: 50
3388 11:05:15.933245
3389 11:05:15.933329 Set Vref, RX VrefLevel [Byte0]: 51
3390 11:05:15.936559 [Byte1]: 51
3391 11:05:15.941374
3392 11:05:15.941458 Set Vref, RX VrefLevel [Byte0]: 52
3393 11:05:15.944277 [Byte1]: 52
3394 11:05:15.949460
3395 11:05:15.949542 Set Vref, RX VrefLevel [Byte0]: 53
3396 11:05:15.952127 [Byte1]: 53
3397 11:05:15.957214
3398 11:05:15.957298 Set Vref, RX VrefLevel [Byte0]: 54
3399 11:05:15.959903 [Byte1]: 54
3400 11:05:15.964589
3401 11:05:15.964672 Set Vref, RX VrefLevel [Byte0]: 55
3402 11:05:15.967803 [Byte1]: 55
3403 11:05:15.972451
3404 11:05:15.972536 Set Vref, RX VrefLevel [Byte0]: 56
3405 11:05:15.976254 [Byte1]: 56
3406 11:05:15.980258
3407 11:05:15.980350 Set Vref, RX VrefLevel [Byte0]: 57
3408 11:05:15.983706 [Byte1]: 57
3409 11:05:15.988354
3410 11:05:15.988438 Set Vref, RX VrefLevel [Byte0]: 58
3411 11:05:15.991709 [Byte1]: 58
3412 11:05:15.996046
3413 11:05:15.996129 Set Vref, RX VrefLevel [Byte0]: 59
3414 11:05:15.999380 [Byte1]: 59
3415 11:05:16.004435
3416 11:05:16.004520 Set Vref, RX VrefLevel [Byte0]: 60
3417 11:05:16.007289 [Byte1]: 60
3418 11:05:16.012081
3419 11:05:16.012165 Set Vref, RX VrefLevel [Byte0]: 61
3420 11:05:16.015156 [Byte1]: 61
3421 11:05:16.020000
3422 11:05:16.020112 Set Vref, RX VrefLevel [Byte0]: 62
3423 11:05:16.023421 [Byte1]: 62
3424 11:05:16.027595
3425 11:05:16.027679 Set Vref, RX VrefLevel [Byte0]: 63
3426 11:05:16.030936 [Byte1]: 63
3427 11:05:16.035930
3428 11:05:16.036015 Set Vref, RX VrefLevel [Byte0]: 64
3429 11:05:16.038735 [Byte1]: 64
3430 11:05:16.044007
3431 11:05:16.044127 Set Vref, RX VrefLevel [Byte0]: 65
3432 11:05:16.046724 [Byte1]: 65
3433 11:05:16.051504
3434 11:05:16.051630 Final RX Vref Byte 0 = 51 to rank0
3435 11:05:16.054625 Final RX Vref Byte 1 = 51 to rank0
3436 11:05:16.058469 Final RX Vref Byte 0 = 51 to rank1
3437 11:05:16.061232 Final RX Vref Byte 1 = 51 to rank1==
3438 11:05:16.064508 Dram Type= 6, Freq= 0, CH_1, rank 0
3439 11:05:16.071234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3440 11:05:16.071323 ==
3441 11:05:16.071402 DQS Delay:
3442 11:05:16.071465 DQS0 = 0, DQS1 = 0
3443 11:05:16.074613 DQM Delay:
3444 11:05:16.074727 DQM0 = 114, DQM1 = 112
3445 11:05:16.077946 DQ Delay:
3446 11:05:16.081353 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3447 11:05:16.084396 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3448 11:05:16.088119 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3449 11:05:16.090996 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =120
3450 11:05:16.091081
3451 11:05:16.091147
3452 11:05:16.101289 [DQSOSCAuto] RK0, (LSB)MR18= 0xf300, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3453 11:05:16.101377 CH1 RK0: MR19=304, MR18=F300
3454 11:05:16.107527 CH1_RK0: MR19=0x304, MR18=0xF300, DQSOSC=410, MR23=63, INC=39, DEC=26
3455 11:05:16.107615
3456 11:05:16.111660 ----->DramcWriteLeveling(PI) begin...
3457 11:05:16.111747 ==
3458 11:05:16.114075 Dram Type= 6, Freq= 0, CH_1, rank 1
3459 11:05:16.120782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 11:05:16.120869 ==
3461 11:05:16.124068 Write leveling (Byte 0): 26 => 26
3462 11:05:16.127415 Write leveling (Byte 1): 28 => 28
3463 11:05:16.127500 DramcWriteLeveling(PI) end<-----
3464 11:05:16.127568
3465 11:05:16.130628 ==
3466 11:05:16.134300 Dram Type= 6, Freq= 0, CH_1, rank 1
3467 11:05:16.137898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3468 11:05:16.137984 ==
3469 11:05:16.140790 [Gating] SW mode calibration
3470 11:05:16.147377 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3471 11:05:16.151073 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3472 11:05:16.157843 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3473 11:05:16.161222 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3474 11:05:16.164109 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3475 11:05:16.170498 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 11:05:16.174083 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3477 11:05:16.176899 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 11:05:16.183899 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
3479 11:05:16.187254 0 15 28 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
3480 11:05:16.190623 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3481 11:05:16.196849 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 11:05:16.200642 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 11:05:16.203779 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 11:05:16.210475 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 11:05:16.213663 1 0 20 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
3486 11:05:16.217180 1 0 24 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
3487 11:05:16.224027 1 0 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
3488 11:05:16.226896 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 11:05:16.230343 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 11:05:16.236857 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 11:05:16.240245 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 11:05:16.243568 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 11:05:16.250015 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 11:05:16.253106 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3495 11:05:16.256235 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3496 11:05:16.263472 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 11:05:16.266098 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 11:05:16.269707 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 11:05:16.275928 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 11:05:16.279635 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 11:05:16.283277 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 11:05:16.289183 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 11:05:16.292581 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 11:05:16.295843 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 11:05:16.302417 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 11:05:16.305912 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 11:05:16.308754 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 11:05:16.315481 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 11:05:16.319034 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3510 11:05:16.322387 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3511 11:05:16.329063 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3512 11:05:16.332046 Total UI for P1: 0, mck2ui 16
3513 11:05:16.335270 best dqsien dly found for B0: ( 1, 3, 22)
3514 11:05:16.338480 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 11:05:16.341724 Total UI for P1: 0, mck2ui 16
3516 11:05:16.344951 best dqsien dly found for B1: ( 1, 3, 28)
3517 11:05:16.348832 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3518 11:05:16.351594 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3519 11:05:16.351722
3520 11:05:16.354769 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3521 11:05:16.358630 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3522 11:05:16.361885 [Gating] SW calibration Done
3523 11:05:16.362007 ==
3524 11:05:16.364996 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 11:05:16.371226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 11:05:16.371349 ==
3527 11:05:16.371474 RX Vref Scan: 0
3528 11:05:16.371588
3529 11:05:16.374359 RX Vref 0 -> 0, step: 1
3530 11:05:16.374481
3531 11:05:16.378046 RX Delay -40 -> 252, step: 8
3532 11:05:16.381668 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3533 11:05:16.384505 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3534 11:05:16.387974 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3535 11:05:16.394101 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3536 11:05:16.397412 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3537 11:05:16.401023 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3538 11:05:16.404307 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3539 11:05:16.407287 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3540 11:05:16.413856 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3541 11:05:16.417266 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3542 11:05:16.420595 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3543 11:05:16.423631 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3544 11:05:16.427444 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3545 11:05:16.433625 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3546 11:05:16.436891 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3547 11:05:16.440210 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3548 11:05:16.440368 ==
3549 11:05:16.443613 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 11:05:16.447116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 11:05:16.450282 ==
3552 11:05:16.450408 DQS Delay:
3553 11:05:16.450523 DQS0 = 0, DQS1 = 0
3554 11:05:16.453679 DQM Delay:
3555 11:05:16.453816 DQM0 = 114, DQM1 = 111
3556 11:05:16.456710 DQ Delay:
3557 11:05:16.460157 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3558 11:05:16.463576 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =111
3559 11:05:16.466673 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3560 11:05:16.470132 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3561 11:05:16.470278
3562 11:05:16.470396
3563 11:05:16.470510 ==
3564 11:05:16.473613 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 11:05:16.476412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 11:05:16.476538 ==
3567 11:05:16.476653
3568 11:05:16.480032
3569 11:05:16.480155 TX Vref Scan disable
3570 11:05:16.483113 == TX Byte 0 ==
3571 11:05:16.486810 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3572 11:05:16.490046 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3573 11:05:16.493610 == TX Byte 1 ==
3574 11:05:16.496588 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3575 11:05:16.499830 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3576 11:05:16.499951 ==
3577 11:05:16.503032 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 11:05:16.509776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 11:05:16.509905 ==
3580 11:05:16.520659 TX Vref=22, minBit 1, minWin=25, winSum=425
3581 11:05:16.523818 TX Vref=24, minBit 3, minWin=25, winSum=425
3582 11:05:16.527478 TX Vref=26, minBit 1, minWin=26, winSum=430
3583 11:05:16.530081 TX Vref=28, minBit 2, minWin=26, winSum=432
3584 11:05:16.533565 TX Vref=30, minBit 9, minWin=26, winSum=433
3585 11:05:16.540189 TX Vref=32, minBit 3, minWin=26, winSum=433
3586 11:05:16.543538 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3587 11:05:16.543665
3588 11:05:16.546918 Final TX Range 1 Vref 30
3589 11:05:16.547025
3590 11:05:16.547119 ==
3591 11:05:16.550068 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 11:05:16.553272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 11:05:16.556741 ==
3594 11:05:16.556829
3595 11:05:16.556895
3596 11:05:16.556957 TX Vref Scan disable
3597 11:05:16.560276 == TX Byte 0 ==
3598 11:05:16.563198 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3599 11:05:16.569739 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3600 11:05:16.569825 == TX Byte 1 ==
3601 11:05:16.573381 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3602 11:05:16.579801 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3603 11:05:16.579888
3604 11:05:16.579955 [DATLAT]
3605 11:05:16.580016 Freq=1200, CH1 RK1
3606 11:05:16.580077
3607 11:05:16.583202 DATLAT Default: 0xd
3608 11:05:16.586630 0, 0xFFFF, sum = 0
3609 11:05:16.586715 1, 0xFFFF, sum = 0
3610 11:05:16.589820 2, 0xFFFF, sum = 0
3611 11:05:16.589940 3, 0xFFFF, sum = 0
3612 11:05:16.592819 4, 0xFFFF, sum = 0
3613 11:05:16.592929 5, 0xFFFF, sum = 0
3614 11:05:16.596016 6, 0xFFFF, sum = 0
3615 11:05:16.596149 7, 0xFFFF, sum = 0
3616 11:05:16.599539 8, 0xFFFF, sum = 0
3617 11:05:16.599660 9, 0xFFFF, sum = 0
3618 11:05:16.602585 10, 0xFFFF, sum = 0
3619 11:05:16.602691 11, 0xFFFF, sum = 0
3620 11:05:16.605800 12, 0x0, sum = 1
3621 11:05:16.605908 13, 0x0, sum = 2
3622 11:05:16.609203 14, 0x0, sum = 3
3623 11:05:16.609311 15, 0x0, sum = 4
3624 11:05:16.612765 best_step = 13
3625 11:05:16.612879
3626 11:05:16.612979 ==
3627 11:05:16.616674 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 11:05:16.619262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 11:05:16.619379 ==
3630 11:05:16.622737 RX Vref Scan: 0
3631 11:05:16.622845
3632 11:05:16.622941 RX Vref 0 -> 0, step: 1
3633 11:05:16.623034
3634 11:05:16.625791 RX Delay -13 -> 252, step: 4
3635 11:05:16.632472 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3636 11:05:16.635722 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3637 11:05:16.639019 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3638 11:05:16.642152 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3639 11:05:16.645302 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3640 11:05:16.652376 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3641 11:05:16.655080 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3642 11:05:16.658893 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3643 11:05:16.662317 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3644 11:05:16.668392 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3645 11:05:16.672053 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3646 11:05:16.674810 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3647 11:05:16.678137 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3648 11:05:16.681535 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3649 11:05:16.688066 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3650 11:05:16.691443 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3651 11:05:16.691573 ==
3652 11:05:16.694710 Dram Type= 6, Freq= 0, CH_1, rank 1
3653 11:05:16.697997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3654 11:05:16.698123 ==
3655 11:05:16.701007 DQS Delay:
3656 11:05:16.701130 DQS0 = 0, DQS1 = 0
3657 11:05:16.704433 DQM Delay:
3658 11:05:16.704558 DQM0 = 115, DQM1 = 112
3659 11:05:16.704672 DQ Delay:
3660 11:05:16.708222 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =114
3661 11:05:16.714434 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3662 11:05:16.717744 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3663 11:05:16.720840 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3664 11:05:16.720949
3665 11:05:16.721054
3666 11:05:16.727507 [DQSOSCAuto] RK1, (LSB)MR18= 0xf709, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3667 11:05:16.730985 CH1 RK1: MR19=304, MR18=F709
3668 11:05:16.737455 CH1_RK1: MR19=0x304, MR18=0xF709, DQSOSC=406, MR23=63, INC=39, DEC=26
3669 11:05:16.740631 [RxdqsGatingPostProcess] freq 1200
3670 11:05:16.747741 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3671 11:05:16.750441 best DQS0 dly(2T, 0.5T) = (0, 11)
3672 11:05:16.750566 best DQS1 dly(2T, 0.5T) = (0, 11)
3673 11:05:16.754011 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3674 11:05:16.757612 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3675 11:05:16.760350 best DQS0 dly(2T, 0.5T) = (0, 11)
3676 11:05:16.763726 best DQS1 dly(2T, 0.5T) = (0, 11)
3677 11:05:16.767183 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3678 11:05:16.770850 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3679 11:05:16.773536 Pre-setting of DQS Precalculation
3680 11:05:16.780554 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3681 11:05:16.786636 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3682 11:05:16.793764 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3683 11:05:16.793926
3684 11:05:16.794021
3685 11:05:16.796538 [Calibration Summary] 2400 Mbps
3686 11:05:16.799793 CH 0, Rank 0
3687 11:05:16.799896 SW Impedance : PASS
3688 11:05:16.802992 DUTY Scan : NO K
3689 11:05:16.803079 ZQ Calibration : PASS
3690 11:05:16.806591 Jitter Meter : NO K
3691 11:05:16.810000 CBT Training : PASS
3692 11:05:16.810092 Write leveling : PASS
3693 11:05:16.813012 RX DQS gating : PASS
3694 11:05:16.816204 RX DQ/DQS(RDDQC) : PASS
3695 11:05:16.816341 TX DQ/DQS : PASS
3696 11:05:16.819772 RX DATLAT : PASS
3697 11:05:16.822748 RX DQ/DQS(Engine): PASS
3698 11:05:16.822834 TX OE : NO K
3699 11:05:16.826204 All Pass.
3700 11:05:16.826293
3701 11:05:16.826380 CH 0, Rank 1
3702 11:05:16.829276 SW Impedance : PASS
3703 11:05:16.829352 DUTY Scan : NO K
3704 11:05:16.833070 ZQ Calibration : PASS
3705 11:05:16.836476 Jitter Meter : NO K
3706 11:05:16.836564 CBT Training : PASS
3707 11:05:16.839322 Write leveling : PASS
3708 11:05:16.842659 RX DQS gating : PASS
3709 11:05:16.842739 RX DQ/DQS(RDDQC) : PASS
3710 11:05:16.845919 TX DQ/DQS : PASS
3711 11:05:16.849068 RX DATLAT : PASS
3712 11:05:16.849151 RX DQ/DQS(Engine): PASS
3713 11:05:16.852496 TX OE : NO K
3714 11:05:16.852578 All Pass.
3715 11:05:16.852644
3716 11:05:16.855757 CH 1, Rank 0
3717 11:05:16.855839 SW Impedance : PASS
3718 11:05:16.858683 DUTY Scan : NO K
3719 11:05:16.862006 ZQ Calibration : PASS
3720 11:05:16.862095 Jitter Meter : NO K
3721 11:05:16.865245 CBT Training : PASS
3722 11:05:16.868899 Write leveling : PASS
3723 11:05:16.868994 RX DQS gating : PASS
3724 11:05:16.871847 RX DQ/DQS(RDDQC) : PASS
3725 11:05:16.875092 TX DQ/DQS : PASS
3726 11:05:16.875221 RX DATLAT : PASS
3727 11:05:16.878889 RX DQ/DQS(Engine): PASS
3728 11:05:16.882238 TX OE : NO K
3729 11:05:16.882363 All Pass.
3730 11:05:16.882479
3731 11:05:16.882589 CH 1, Rank 1
3732 11:05:16.885305 SW Impedance : PASS
3733 11:05:16.888994 DUTY Scan : NO K
3734 11:05:16.889118 ZQ Calibration : PASS
3735 11:05:16.892153 Jitter Meter : NO K
3736 11:05:16.892258 CBT Training : PASS
3737 11:05:16.895294 Write leveling : PASS
3738 11:05:16.898684 RX DQS gating : PASS
3739 11:05:16.898765 RX DQ/DQS(RDDQC) : PASS
3740 11:05:16.901964 TX DQ/DQS : PASS
3741 11:05:16.905276 RX DATLAT : PASS
3742 11:05:16.905352 RX DQ/DQS(Engine): PASS
3743 11:05:16.908476 TX OE : NO K
3744 11:05:16.908563 All Pass.
3745 11:05:16.908650
3746 11:05:16.911878 DramC Write-DBI off
3747 11:05:16.915005 PER_BANK_REFRESH: Hybrid Mode
3748 11:05:16.915096 TX_TRACKING: ON
3749 11:05:16.925096 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3750 11:05:16.928124 [FAST_K] Save calibration result to emmc
3751 11:05:16.931839 dramc_set_vcore_voltage set vcore to 650000
3752 11:05:16.934571 Read voltage for 600, 5
3753 11:05:16.934657 Vio18 = 0
3754 11:05:16.938464 Vcore = 650000
3755 11:05:16.938550 Vdram = 0
3756 11:05:16.938637 Vddq = 0
3757 11:05:16.938718 Vmddr = 0
3758 11:05:16.945033 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3759 11:05:16.951104 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3760 11:05:16.951263 MEM_TYPE=3, freq_sel=19
3761 11:05:16.954453 sv_algorithm_assistance_LP4_1600
3762 11:05:16.957639 ============ PULL DRAM RESETB DOWN ============
3763 11:05:16.964738 ========== PULL DRAM RESETB DOWN end =========
3764 11:05:16.967727 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3765 11:05:16.971173 ===================================
3766 11:05:16.974414 LPDDR4 DRAM CONFIGURATION
3767 11:05:16.977875 ===================================
3768 11:05:16.977960 EX_ROW_EN[0] = 0x0
3769 11:05:16.980843 EX_ROW_EN[1] = 0x0
3770 11:05:16.980939 LP4Y_EN = 0x0
3771 11:05:16.984438 WORK_FSP = 0x0
3772 11:05:16.987320 WL = 0x2
3773 11:05:16.987428 RL = 0x2
3774 11:05:16.990533 BL = 0x2
3775 11:05:16.990615 RPST = 0x0
3776 11:05:16.994434 RD_PRE = 0x0
3777 11:05:16.994517 WR_PRE = 0x1
3778 11:05:16.997444 WR_PST = 0x0
3779 11:05:16.997542 DBI_WR = 0x0
3780 11:05:17.000522 DBI_RD = 0x0
3781 11:05:17.000620 OTF = 0x1
3782 11:05:17.003826 ===================================
3783 11:05:17.007255 ===================================
3784 11:05:17.010494 ANA top config
3785 11:05:17.013502 ===================================
3786 11:05:17.013586 DLL_ASYNC_EN = 0
3787 11:05:17.017170 ALL_SLAVE_EN = 1
3788 11:05:17.020068 NEW_RANK_MODE = 1
3789 11:05:17.023551 DLL_IDLE_MODE = 1
3790 11:05:17.026755 LP45_APHY_COMB_EN = 1
3791 11:05:17.026870 TX_ODT_DIS = 1
3792 11:05:17.030037 NEW_8X_MODE = 1
3793 11:05:17.033740 ===================================
3794 11:05:17.036462 ===================================
3795 11:05:17.039878 data_rate = 1200
3796 11:05:17.042974 CKR = 1
3797 11:05:17.046631 DQ_P2S_RATIO = 8
3798 11:05:17.049924 ===================================
3799 11:05:17.053156 CA_P2S_RATIO = 8
3800 11:05:17.053244 DQ_CA_OPEN = 0
3801 11:05:17.056522 DQ_SEMI_OPEN = 0
3802 11:05:17.059681 CA_SEMI_OPEN = 0
3803 11:05:17.063214 CA_FULL_RATE = 0
3804 11:05:17.066216 DQ_CKDIV4_EN = 1
3805 11:05:17.069340 CA_CKDIV4_EN = 1
3806 11:05:17.069443 CA_PREDIV_EN = 0
3807 11:05:17.072905 PH8_DLY = 0
3808 11:05:17.075960 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3809 11:05:17.079594 DQ_AAMCK_DIV = 4
3810 11:05:17.082682 CA_AAMCK_DIV = 4
3811 11:05:17.085931 CA_ADMCK_DIV = 4
3812 11:05:17.086014 DQ_TRACK_CA_EN = 0
3813 11:05:17.089399 CA_PICK = 600
3814 11:05:17.092712 CA_MCKIO = 600
3815 11:05:17.096142 MCKIO_SEMI = 0
3816 11:05:17.099328 PLL_FREQ = 2288
3817 11:05:17.102570 DQ_UI_PI_RATIO = 32
3818 11:05:17.105574 CA_UI_PI_RATIO = 0
3819 11:05:17.109639 ===================================
3820 11:05:17.112516 ===================================
3821 11:05:17.112594 memory_type:LPDDR4
3822 11:05:17.115656 GP_NUM : 10
3823 11:05:17.119188 SRAM_EN : 1
3824 11:05:17.119302 MD32_EN : 0
3825 11:05:17.122826 ===================================
3826 11:05:17.125660 [ANA_INIT] >>>>>>>>>>>>>>
3827 11:05:17.129345 <<<<<< [CONFIGURE PHASE]: ANA_TX
3828 11:05:17.132553 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3829 11:05:17.135935 ===================================
3830 11:05:17.138728 data_rate = 1200,PCW = 0X5800
3831 11:05:17.142121 ===================================
3832 11:05:17.146077 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3833 11:05:17.148765 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3834 11:05:17.155709 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3835 11:05:17.159022 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3836 11:05:17.165627 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3837 11:05:17.168707 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3838 11:05:17.168790 [ANA_INIT] flow start
3839 11:05:17.172138 [ANA_INIT] PLL >>>>>>>>
3840 11:05:17.175313 [ANA_INIT] PLL <<<<<<<<
3841 11:05:17.175422 [ANA_INIT] MIDPI >>>>>>>>
3842 11:05:17.178401 [ANA_INIT] MIDPI <<<<<<<<
3843 11:05:17.181636 [ANA_INIT] DLL >>>>>>>>
3844 11:05:17.181723 [ANA_INIT] flow end
3845 11:05:17.188211 ============ LP4 DIFF to SE enter ============
3846 11:05:17.191677 ============ LP4 DIFF to SE exit ============
3847 11:05:17.195082 [ANA_INIT] <<<<<<<<<<<<<
3848 11:05:17.198238 [Flow] Enable top DCM control >>>>>
3849 11:05:17.201673 [Flow] Enable top DCM control <<<<<
3850 11:05:17.201765 Enable DLL master slave shuffle
3851 11:05:17.208020 ==============================================================
3852 11:05:17.211192 Gating Mode config
3853 11:05:17.214625 ==============================================================
3854 11:05:17.217898 Config description:
3855 11:05:17.227990 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3856 11:05:17.234173 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3857 11:05:17.237801 SELPH_MODE 0: By rank 1: By Phase
3858 11:05:17.244321 ==============================================================
3859 11:05:17.247270 GAT_TRACK_EN = 1
3860 11:05:17.250659 RX_GATING_MODE = 2
3861 11:05:17.253995 RX_GATING_TRACK_MODE = 2
3862 11:05:17.257324 SELPH_MODE = 1
3863 11:05:17.260609 PICG_EARLY_EN = 1
3864 11:05:17.260719 VALID_LAT_VALUE = 1
3865 11:05:17.267197 ==============================================================
3866 11:05:17.270238 Enter into Gating configuration >>>>
3867 11:05:17.273480 Exit from Gating configuration <<<<
3868 11:05:17.277292 Enter into DVFS_PRE_config >>>>>
3869 11:05:17.290095 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3870 11:05:17.290179 Exit from DVFS_PRE_config <<<<<
3871 11:05:17.293088 Enter into PICG configuration >>>>
3872 11:05:17.296494 Exit from PICG configuration <<<<
3873 11:05:17.299699 [RX_INPUT] configuration >>>>>
3874 11:05:17.303475 [RX_INPUT] configuration <<<<<
3875 11:05:17.309729 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3876 11:05:17.313290 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3877 11:05:17.319649 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3878 11:05:17.326105 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3879 11:05:17.332818 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3880 11:05:17.338978 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3881 11:05:17.342553 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3882 11:05:17.345663 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3883 11:05:17.352599 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3884 11:05:17.355760 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3885 11:05:17.358864 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3886 11:05:17.362098 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3887 11:05:17.365805 ===================================
3888 11:05:17.369286 LPDDR4 DRAM CONFIGURATION
3889 11:05:17.372634 ===================================
3890 11:05:17.375629 EX_ROW_EN[0] = 0x0
3891 11:05:17.375713 EX_ROW_EN[1] = 0x0
3892 11:05:17.379058 LP4Y_EN = 0x0
3893 11:05:17.379166 WORK_FSP = 0x0
3894 11:05:17.382147 WL = 0x2
3895 11:05:17.382235 RL = 0x2
3896 11:05:17.385355 BL = 0x2
3897 11:05:17.385438 RPST = 0x0
3898 11:05:17.388633 RD_PRE = 0x0
3899 11:05:17.392074 WR_PRE = 0x1
3900 11:05:17.392170 WR_PST = 0x0
3901 11:05:17.394914 DBI_WR = 0x0
3902 11:05:17.395010 DBI_RD = 0x0
3903 11:05:17.398323 OTF = 0x1
3904 11:05:17.401648 ===================================
3905 11:05:17.405166 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3906 11:05:17.408131 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3907 11:05:17.411456 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3908 11:05:17.414907 ===================================
3909 11:05:17.418199 LPDDR4 DRAM CONFIGURATION
3910 11:05:17.422148 ===================================
3911 11:05:17.424756 EX_ROW_EN[0] = 0x10
3912 11:05:17.424881 EX_ROW_EN[1] = 0x0
3913 11:05:17.428265 LP4Y_EN = 0x0
3914 11:05:17.428387 WORK_FSP = 0x0
3915 11:05:17.431239 WL = 0x2
3916 11:05:17.434604 RL = 0x2
3917 11:05:17.434726 BL = 0x2
3918 11:05:17.438011 RPST = 0x0
3919 11:05:17.438131 RD_PRE = 0x0
3920 11:05:17.441054 WR_PRE = 0x1
3921 11:05:17.441136 WR_PST = 0x0
3922 11:05:17.444358 DBI_WR = 0x0
3923 11:05:17.444484 DBI_RD = 0x0
3924 11:05:17.447763 OTF = 0x1
3925 11:05:17.451342 ===================================
3926 11:05:17.457666 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3927 11:05:17.461243 nWR fixed to 30
3928 11:05:17.461371 [ModeRegInit_LP4] CH0 RK0
3929 11:05:17.464571 [ModeRegInit_LP4] CH0 RK1
3930 11:05:17.467596 [ModeRegInit_LP4] CH1 RK0
3931 11:05:17.467681 [ModeRegInit_LP4] CH1 RK1
3932 11:05:17.470768 match AC timing 17
3933 11:05:17.473941 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3934 11:05:17.480926 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3935 11:05:17.483785 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3936 11:05:17.490674 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3937 11:05:17.494066 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3938 11:05:17.494175 ==
3939 11:05:17.497368 Dram Type= 6, Freq= 0, CH_0, rank 0
3940 11:05:17.500535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3941 11:05:17.500634 ==
3942 11:05:17.506861 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3943 11:05:17.513714 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3944 11:05:17.516642 [CA 0] Center 36 (6~67) winsize 62
3945 11:05:17.519948 [CA 1] Center 36 (5~67) winsize 63
3946 11:05:17.523726 [CA 2] Center 34 (4~65) winsize 62
3947 11:05:17.526980 [CA 3] Center 34 (3~65) winsize 63
3948 11:05:17.530101 [CA 4] Center 33 (3~64) winsize 62
3949 11:05:17.533387 [CA 5] Center 33 (2~64) winsize 63
3950 11:05:17.533507
3951 11:05:17.536394 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3952 11:05:17.536517
3953 11:05:17.539711 [CATrainingPosCal] consider 1 rank data
3954 11:05:17.542960 u2DelayCellTimex100 = 270/100 ps
3955 11:05:17.546472 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3956 11:05:17.549622 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3957 11:05:17.553317 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3958 11:05:17.556287 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3959 11:05:17.559804 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3960 11:05:17.566593 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3961 11:05:17.566720
3962 11:05:17.569571 CA PerBit enable=1, Macro0, CA PI delay=33
3963 11:05:17.569709
3964 11:05:17.572682 [CBTSetCACLKResult] CA Dly = 33
3965 11:05:17.572806 CS Dly: 6 (0~37)
3966 11:05:17.572917 ==
3967 11:05:17.575991 Dram Type= 6, Freq= 0, CH_0, rank 1
3968 11:05:17.579701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 11:05:17.583004 ==
3970 11:05:17.586279 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3971 11:05:17.592553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3972 11:05:17.595790 [CA 0] Center 36 (6~67) winsize 62
3973 11:05:17.599291 [CA 1] Center 36 (6~67) winsize 62
3974 11:05:17.602526 [CA 2] Center 34 (4~65) winsize 62
3975 11:05:17.605787 [CA 3] Center 34 (3~65) winsize 63
3976 11:05:17.609409 [CA 4] Center 34 (3~65) winsize 63
3977 11:05:17.612506 [CA 5] Center 33 (3~64) winsize 62
3978 11:05:17.612589
3979 11:05:17.616071 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3980 11:05:17.616209
3981 11:05:17.618783 [CATrainingPosCal] consider 2 rank data
3982 11:05:17.622181 u2DelayCellTimex100 = 270/100 ps
3983 11:05:17.625615 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3984 11:05:17.628768 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3985 11:05:17.635239 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3986 11:05:17.638374 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3987 11:05:17.642016 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3988 11:05:17.645257 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3989 11:05:17.645340
3990 11:05:17.648564 CA PerBit enable=1, Macro0, CA PI delay=33
3991 11:05:17.648647
3992 11:05:17.651799 [CBTSetCACLKResult] CA Dly = 33
3993 11:05:17.654756 CS Dly: 6 (0~37)
3994 11:05:17.654838
3995 11:05:17.658267 ----->DramcWriteLeveling(PI) begin...
3996 11:05:17.658351 ==
3997 11:05:17.661413 Dram Type= 6, Freq= 0, CH_0, rank 0
3998 11:05:17.664550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3999 11:05:17.664633 ==
4000 11:05:17.667953 Write leveling (Byte 0): 34 => 34
4001 11:05:17.671630 Write leveling (Byte 1): 30 => 30
4002 11:05:17.674696 DramcWriteLeveling(PI) end<-----
4003 11:05:17.674809
4004 11:05:17.674874 ==
4005 11:05:17.678209 Dram Type= 6, Freq= 0, CH_0, rank 0
4006 11:05:17.681412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 11:05:17.681495 ==
4008 11:05:17.684592 [Gating] SW mode calibration
4009 11:05:17.691385 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4010 11:05:17.697949 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4011 11:05:17.701021 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4012 11:05:17.704210 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4013 11:05:17.710790 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 11:05:17.714184 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4015 11:05:17.717621 0 9 16 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)
4016 11:05:17.724060 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 11:05:17.727241 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 11:05:17.730462 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 11:05:17.736725 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 11:05:17.740466 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 11:05:17.746947 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 11:05:17.750134 0 10 12 | B1->B0 | 2929 2d2d | 0 0 | (0 0) (0 0)
4023 11:05:17.754182 0 10 16 | B1->B0 | 3636 4040 | 1 0 | (0 0) (0 0)
4024 11:05:17.760519 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 11:05:17.763189 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 11:05:17.766709 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 11:05:17.773335 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 11:05:17.776541 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 11:05:17.779669 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 11:05:17.786600 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 11:05:17.789585 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4032 11:05:17.793654 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 11:05:17.799822 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 11:05:17.802893 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 11:05:17.806133 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 11:05:17.812466 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 11:05:17.815657 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 11:05:17.818897 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 11:05:17.826168 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 11:05:17.829216 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 11:05:17.832354 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 11:05:17.838870 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 11:05:17.842052 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 11:05:17.845465 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 11:05:17.852268 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 11:05:17.855648 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 11:05:17.858493 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4048 11:05:17.861769 Total UI for P1: 0, mck2ui 16
4049 11:05:17.865176 best dqsien dly found for B0: ( 0, 13, 14)
4050 11:05:17.872150 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 11:05:17.872229 Total UI for P1: 0, mck2ui 16
4052 11:05:17.878685 best dqsien dly found for B1: ( 0, 13, 16)
4053 11:05:17.881488 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4054 11:05:17.885157 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4055 11:05:17.885255
4056 11:05:17.888132 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4057 11:05:17.891944 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4058 11:05:17.894645 [Gating] SW calibration Done
4059 11:05:17.894718 ==
4060 11:05:17.898289 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 11:05:17.901285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 11:05:17.901359 ==
4063 11:05:17.904982 RX Vref Scan: 0
4064 11:05:17.905054
4065 11:05:17.905137 RX Vref 0 -> 0, step: 1
4066 11:05:17.907725
4067 11:05:17.907797 RX Delay -230 -> 252, step: 16
4068 11:05:17.914835 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4069 11:05:17.917965 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4070 11:05:17.921409 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4071 11:05:17.924418 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4072 11:05:17.931325 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4073 11:05:17.934441 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4074 11:05:17.938048 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4075 11:05:17.941269 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4076 11:05:17.944177 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4077 11:05:17.951097 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4078 11:05:17.954005 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4079 11:05:17.957448 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4080 11:05:17.960766 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4081 11:05:17.967577 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4082 11:05:17.970368 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4083 11:05:17.973714 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4084 11:05:17.973796 ==
4085 11:05:17.977023 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 11:05:17.983877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 11:05:17.983960 ==
4088 11:05:17.984026 DQS Delay:
4089 11:05:17.987490 DQS0 = 0, DQS1 = 0
4090 11:05:17.987572 DQM Delay:
4091 11:05:17.987638 DQM0 = 43, DQM1 = 35
4092 11:05:17.990406 DQ Delay:
4093 11:05:17.993543 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4094 11:05:17.997258 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4095 11:05:18.000242 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =33
4096 11:05:18.003785 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4097 11:05:18.003900
4098 11:05:18.003991
4099 11:05:18.004078 ==
4100 11:05:18.006843 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 11:05:18.010094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 11:05:18.010230 ==
4103 11:05:18.010295
4104 11:05:18.010356
4105 11:05:18.013645 TX Vref Scan disable
4106 11:05:18.016435 == TX Byte 0 ==
4107 11:05:18.019710 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4108 11:05:18.023655 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4109 11:05:18.026472 == TX Byte 1 ==
4110 11:05:18.029726 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4111 11:05:18.032975 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4112 11:05:18.033060 ==
4113 11:05:18.036567 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 11:05:18.039537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 11:05:18.043051 ==
4116 11:05:18.043135
4117 11:05:18.043201
4118 11:05:18.043263 TX Vref Scan disable
4119 11:05:18.046699 == TX Byte 0 ==
4120 11:05:18.050211 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4121 11:05:18.056962 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4122 11:05:18.057056 == TX Byte 1 ==
4123 11:05:18.060088 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4124 11:05:18.066587 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4125 11:05:18.066670
4126 11:05:18.066734 [DATLAT]
4127 11:05:18.066795 Freq=600, CH0 RK0
4128 11:05:18.066854
4129 11:05:18.070101 DATLAT Default: 0x9
4130 11:05:18.070198 0, 0xFFFF, sum = 0
4131 11:05:18.073275 1, 0xFFFF, sum = 0
4132 11:05:18.076654 2, 0xFFFF, sum = 0
4133 11:05:18.076738 3, 0xFFFF, sum = 0
4134 11:05:18.080035 4, 0xFFFF, sum = 0
4135 11:05:18.080151 5, 0xFFFF, sum = 0
4136 11:05:18.083328 6, 0xFFFF, sum = 0
4137 11:05:18.083447 7, 0xFFFF, sum = 0
4138 11:05:18.086765 8, 0x0, sum = 1
4139 11:05:18.086851 9, 0x0, sum = 2
4140 11:05:18.089636 10, 0x0, sum = 3
4141 11:05:18.089722 11, 0x0, sum = 4
4142 11:05:18.089790 best_step = 9
4143 11:05:18.089868
4144 11:05:18.093077 ==
4145 11:05:18.096305 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 11:05:18.099880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 11:05:18.099995 ==
4148 11:05:18.100089 RX Vref Scan: 1
4149 11:05:18.100186
4150 11:05:18.102878 RX Vref 0 -> 0, step: 1
4151 11:05:18.102977
4152 11:05:18.106292 RX Delay -195 -> 252, step: 8
4153 11:05:18.106395
4154 11:05:18.109560 Set Vref, RX VrefLevel [Byte0]: 54
4155 11:05:18.112577 [Byte1]: 59
4156 11:05:18.112681
4157 11:05:18.116043 Final RX Vref Byte 0 = 54 to rank0
4158 11:05:18.119635 Final RX Vref Byte 1 = 59 to rank0
4159 11:05:18.123271 Final RX Vref Byte 0 = 54 to rank1
4160 11:05:18.126195 Final RX Vref Byte 1 = 59 to rank1==
4161 11:05:18.129273 Dram Type= 6, Freq= 0, CH_0, rank 0
4162 11:05:18.135829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4163 11:05:18.135935 ==
4164 11:05:18.136040 DQS Delay:
4165 11:05:18.136137 DQS0 = 0, DQS1 = 0
4166 11:05:18.138944 DQM Delay:
4167 11:05:18.139045 DQM0 = 40, DQM1 = 32
4168 11:05:18.142216 DQ Delay:
4169 11:05:18.145873 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4170 11:05:18.148860 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4171 11:05:18.152071 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =28
4172 11:05:18.155849 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4173 11:05:18.155934
4174 11:05:18.155999
4175 11:05:18.161729 [DQSOSCAuto] RK0, (LSB)MR18= 0x443c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4176 11:05:18.165374 CH0 RK0: MR19=808, MR18=443C
4177 11:05:18.171698 CH0_RK0: MR19=0x808, MR18=0x443C, DQSOSC=396, MR23=63, INC=167, DEC=111
4178 11:05:18.171783
4179 11:05:18.175349 ----->DramcWriteLeveling(PI) begin...
4180 11:05:18.175441 ==
4181 11:05:18.178360 Dram Type= 6, Freq= 0, CH_0, rank 1
4182 11:05:18.181554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 11:05:18.181655 ==
4184 11:05:18.185328 Write leveling (Byte 0): 35 => 35
4185 11:05:18.188398 Write leveling (Byte 1): 28 => 28
4186 11:05:18.191679 DramcWriteLeveling(PI) end<-----
4187 11:05:18.191761
4188 11:05:18.191826 ==
4189 11:05:18.194803 Dram Type= 6, Freq= 0, CH_0, rank 1
4190 11:05:18.198264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 11:05:18.201115 ==
4192 11:05:18.201211 [Gating] SW mode calibration
4193 11:05:18.211656 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4194 11:05:18.214605 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4195 11:05:18.218012 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4196 11:05:18.224390 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4197 11:05:18.227853 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4198 11:05:18.231303 0 9 12 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 0)
4199 11:05:18.238086 0 9 16 | B1->B0 | 2e2e 2525 | 1 0 | (1 0) (0 0)
4200 11:05:18.241122 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 11:05:18.244395 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 11:05:18.251050 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 11:05:18.254393 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 11:05:18.257450 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 11:05:18.264131 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 11:05:18.267349 0 10 12 | B1->B0 | 2727 3535 | 0 0 | (0 0) (1 1)
4207 11:05:18.270978 0 10 16 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
4208 11:05:18.277653 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 11:05:18.280604 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 11:05:18.284299 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 11:05:18.290505 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 11:05:18.293757 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 11:05:18.297185 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 11:05:18.304252 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4215 11:05:18.306988 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 11:05:18.310435 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 11:05:18.316798 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 11:05:18.320274 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 11:05:18.323457 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 11:05:18.329887 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 11:05:18.333421 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 11:05:18.336475 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 11:05:18.343313 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 11:05:18.346837 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 11:05:18.349821 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 11:05:18.356383 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 11:05:18.359555 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 11:05:18.363032 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 11:05:18.369924 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 11:05:18.372907 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4231 11:05:18.376030 Total UI for P1: 0, mck2ui 16
4232 11:05:18.379291 best dqsien dly found for B0: ( 0, 13, 10)
4233 11:05:18.382762 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 11:05:18.385929 Total UI for P1: 0, mck2ui 16
4235 11:05:18.389482 best dqsien dly found for B1: ( 0, 13, 12)
4236 11:05:18.392753 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4237 11:05:18.399558 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4238 11:05:18.399641
4239 11:05:18.402104 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4240 11:05:18.405659 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4241 11:05:18.409045 [Gating] SW calibration Done
4242 11:05:18.409127 ==
4243 11:05:18.412040 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 11:05:18.415629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 11:05:18.415712 ==
4246 11:05:18.418785 RX Vref Scan: 0
4247 11:05:18.418867
4248 11:05:18.418932 RX Vref 0 -> 0, step: 1
4249 11:05:18.418993
4250 11:05:18.422393 RX Delay -230 -> 252, step: 16
4251 11:05:18.425347 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4252 11:05:18.431900 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4253 11:05:18.435080 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4254 11:05:18.438786 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4255 11:05:18.441613 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4256 11:05:18.448506 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4257 11:05:18.451949 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4258 11:05:18.454969 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4259 11:05:18.458174 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4260 11:05:18.464683 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4261 11:05:18.468091 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4262 11:05:18.471165 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4263 11:05:18.474466 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4264 11:05:18.481180 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4265 11:05:18.484476 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4266 11:05:18.488047 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4267 11:05:18.488151 ==
4268 11:05:18.491142 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 11:05:18.494748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 11:05:18.498080 ==
4271 11:05:18.498162 DQS Delay:
4272 11:05:18.498227 DQS0 = 0, DQS1 = 0
4273 11:05:18.500922 DQM Delay:
4274 11:05:18.501107 DQM0 = 42, DQM1 = 33
4275 11:05:18.504528 DQ Delay:
4276 11:05:18.504611 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4277 11:05:18.507796 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =41
4278 11:05:18.511118 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4279 11:05:18.514135 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4280 11:05:18.517378
4281 11:05:18.517460
4282 11:05:18.517525 ==
4283 11:05:18.521016 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 11:05:18.524159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 11:05:18.524242 ==
4286 11:05:18.524308
4287 11:05:18.524381
4288 11:05:18.527511 TX Vref Scan disable
4289 11:05:18.527607 == TX Byte 0 ==
4290 11:05:18.533963 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4291 11:05:18.537297 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4292 11:05:18.537373 == TX Byte 1 ==
4293 11:05:18.543786 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4294 11:05:18.546969 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4295 11:05:18.547046 ==
4296 11:05:18.550609 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 11:05:18.553983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 11:05:18.554065 ==
4299 11:05:18.556805
4300 11:05:18.556916
4301 11:05:18.556980 TX Vref Scan disable
4302 11:05:18.560744 == TX Byte 0 ==
4303 11:05:18.563964 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4304 11:05:18.570845 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4305 11:05:18.570928 == TX Byte 1 ==
4306 11:05:18.573913 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4307 11:05:18.580389 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4308 11:05:18.580471
4309 11:05:18.580535 [DATLAT]
4310 11:05:18.580595 Freq=600, CH0 RK1
4311 11:05:18.580653
4312 11:05:18.583555 DATLAT Default: 0x9
4313 11:05:18.583637 0, 0xFFFF, sum = 0
4314 11:05:18.586927 1, 0xFFFF, sum = 0
4315 11:05:18.590102 2, 0xFFFF, sum = 0
4316 11:05:18.590217 3, 0xFFFF, sum = 0
4317 11:05:18.593390 4, 0xFFFF, sum = 0
4318 11:05:18.593481 5, 0xFFFF, sum = 0
4319 11:05:18.596842 6, 0xFFFF, sum = 0
4320 11:05:18.596937 7, 0xFFFF, sum = 0
4321 11:05:18.600284 8, 0x0, sum = 1
4322 11:05:18.600367 9, 0x0, sum = 2
4323 11:05:18.603479 10, 0x0, sum = 3
4324 11:05:18.603594 11, 0x0, sum = 4
4325 11:05:18.603712 best_step = 9
4326 11:05:18.603802
4327 11:05:18.606799 ==
4328 11:05:18.609911 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 11:05:18.613047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 11:05:18.613125 ==
4331 11:05:18.613190 RX Vref Scan: 0
4332 11:05:18.613256
4333 11:05:18.616487 RX Vref 0 -> 0, step: 1
4334 11:05:18.616579
4335 11:05:18.619784 RX Delay -195 -> 252, step: 8
4336 11:05:18.626415 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4337 11:05:18.629692 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4338 11:05:18.633129 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4339 11:05:18.636348 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4340 11:05:18.639775 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4341 11:05:18.646077 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4342 11:05:18.649383 iDelay=205, Bit 6, Center 48 (-99 ~ 196) 296
4343 11:05:18.653264 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4344 11:05:18.656143 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4345 11:05:18.663157 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4346 11:05:18.666066 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4347 11:05:18.669614 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4348 11:05:18.672889 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4349 11:05:18.679529 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4350 11:05:18.682820 iDelay=205, Bit 14, Center 48 (-107 ~ 204) 312
4351 11:05:18.685761 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4352 11:05:18.685843 ==
4353 11:05:18.689229 Dram Type= 6, Freq= 0, CH_0, rank 1
4354 11:05:18.692477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 11:05:18.692585 ==
4356 11:05:18.696085 DQS Delay:
4357 11:05:18.696168 DQS0 = 0, DQS1 = 0
4358 11:05:18.699268 DQM Delay:
4359 11:05:18.699400 DQM0 = 41, DQM1 = 34
4360 11:05:18.699481 DQ Delay:
4361 11:05:18.702386 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4362 11:05:18.705811 DQ4 =48, DQ5 =28, DQ6 =48, DQ7 =48
4363 11:05:18.708777 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4364 11:05:18.712342 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =40
4365 11:05:18.712425
4366 11:05:18.715443
4367 11:05:18.722297 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e39, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4368 11:05:18.725331 CH0 RK1: MR19=808, MR18=3E39
4369 11:05:18.731863 CH0_RK1: MR19=0x808, MR18=0x3E39, DQSOSC=398, MR23=63, INC=165, DEC=110
4370 11:05:18.735144 [RxdqsGatingPostProcess] freq 600
4371 11:05:18.738396 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4372 11:05:18.741725 Pre-setting of DQS Precalculation
4373 11:05:18.748367 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4374 11:05:18.748450 ==
4375 11:05:18.751515 Dram Type= 6, Freq= 0, CH_1, rank 0
4376 11:05:18.755397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 11:05:18.755495 ==
4378 11:05:18.761680 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4379 11:05:18.768196 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4380 11:05:18.771232 [CA 0] Center 35 (5~66) winsize 62
4381 11:05:18.775302 [CA 1] Center 35 (5~66) winsize 62
4382 11:05:18.778413 [CA 2] Center 34 (4~65) winsize 62
4383 11:05:18.781355 [CA 3] Center 34 (4~65) winsize 62
4384 11:05:18.784463 [CA 4] Center 34 (4~65) winsize 62
4385 11:05:18.787829 [CA 5] Center 33 (3~64) winsize 62
4386 11:05:18.787905
4387 11:05:18.791087 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4388 11:05:18.791170
4389 11:05:18.794501 [CATrainingPosCal] consider 1 rank data
4390 11:05:18.797593 u2DelayCellTimex100 = 270/100 ps
4391 11:05:18.801261 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4392 11:05:18.804445 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4393 11:05:18.807554 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4394 11:05:18.810826 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4395 11:05:18.814085 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4396 11:05:18.817385 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4397 11:05:18.817459
4398 11:05:18.823767 CA PerBit enable=1, Macro0, CA PI delay=33
4399 11:05:18.823888
4400 11:05:18.827106 [CBTSetCACLKResult] CA Dly = 33
4401 11:05:18.827184 CS Dly: 5 (0~36)
4402 11:05:18.827248 ==
4403 11:05:18.830740 Dram Type= 6, Freq= 0, CH_1, rank 1
4404 11:05:18.833625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 11:05:18.833729 ==
4406 11:05:18.840221 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4407 11:05:18.846717 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4408 11:05:18.850496 [CA 0] Center 35 (5~66) winsize 62
4409 11:05:18.853508 [CA 1] Center 35 (5~66) winsize 62
4410 11:05:18.856926 [CA 2] Center 34 (4~65) winsize 62
4411 11:05:18.860169 [CA 3] Center 34 (3~65) winsize 63
4412 11:05:18.863305 [CA 4] Center 34 (3~65) winsize 63
4413 11:05:18.866520 [CA 5] Center 33 (3~64) winsize 62
4414 11:05:18.866603
4415 11:05:18.870175 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4416 11:05:18.870264
4417 11:05:18.873019 [CATrainingPosCal] consider 2 rank data
4418 11:05:18.876196 u2DelayCellTimex100 = 270/100 ps
4419 11:05:18.879781 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4420 11:05:18.882772 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4421 11:05:18.886173 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4422 11:05:18.892666 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4423 11:05:18.896060 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4424 11:05:18.899218 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4425 11:05:18.899321
4426 11:05:18.902933 CA PerBit enable=1, Macro0, CA PI delay=33
4427 11:05:18.903034
4428 11:05:18.906278 [CBTSetCACLKResult] CA Dly = 33
4429 11:05:18.906394 CS Dly: 5 (0~36)
4430 11:05:18.906490
4431 11:05:18.909472 ----->DramcWriteLeveling(PI) begin...
4432 11:05:18.912668 ==
4433 11:05:18.916221 Dram Type= 6, Freq= 0, CH_1, rank 0
4434 11:05:18.919391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4435 11:05:18.919486 ==
4436 11:05:18.922380 Write leveling (Byte 0): 30 => 30
4437 11:05:18.925858 Write leveling (Byte 1): 30 => 30
4438 11:05:18.929229 DramcWriteLeveling(PI) end<-----
4439 11:05:18.929310
4440 11:05:18.929374 ==
4441 11:05:18.932263 Dram Type= 6, Freq= 0, CH_1, rank 0
4442 11:05:18.935697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4443 11:05:18.935780 ==
4444 11:05:18.938889 [Gating] SW mode calibration
4445 11:05:18.945620 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4446 11:05:18.952288 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4447 11:05:18.955520 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4448 11:05:18.958929 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4449 11:05:18.965148 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4450 11:05:18.968739 0 9 12 | B1->B0 | 2f2f 2e2e | 0 0 | (1 1) (1 1)
4451 11:05:18.971907 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 11:05:18.978820 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 11:05:18.981746 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 11:05:18.984792 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 11:05:18.992489 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 11:05:18.994686 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 11:05:18.998204 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 11:05:19.004470 0 10 12 | B1->B0 | 3434 3a3a | 0 0 | (0 0) (0 0)
4459 11:05:19.008004 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4460 11:05:19.011558 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 11:05:19.018193 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 11:05:19.020906 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 11:05:19.024187 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 11:05:19.031154 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 11:05:19.034472 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 11:05:19.037895 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4467 11:05:19.044305 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4468 11:05:19.047614 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 11:05:19.051166 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 11:05:19.057221 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 11:05:19.060750 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 11:05:19.063816 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 11:05:19.070396 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 11:05:19.074031 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 11:05:19.077297 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 11:05:19.083921 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 11:05:19.086975 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 11:05:19.090204 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 11:05:19.096639 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 11:05:19.100157 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 11:05:19.103785 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 11:05:19.109949 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4483 11:05:19.110051 Total UI for P1: 0, mck2ui 16
4484 11:05:19.116954 best dqsien dly found for B0: ( 0, 13, 10)
4485 11:05:19.119804 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 11:05:19.123203 Total UI for P1: 0, mck2ui 16
4487 11:05:19.126596 best dqsien dly found for B1: ( 0, 13, 12)
4488 11:05:19.129802 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4489 11:05:19.132961 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4490 11:05:19.133043
4491 11:05:19.136439 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4492 11:05:19.143119 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4493 11:05:19.143214 [Gating] SW calibration Done
4494 11:05:19.143280 ==
4495 11:05:19.146343 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 11:05:19.152957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 11:05:19.153067 ==
4498 11:05:19.153161 RX Vref Scan: 0
4499 11:05:19.153255
4500 11:05:19.156229 RX Vref 0 -> 0, step: 1
4501 11:05:19.156324
4502 11:05:19.159320 RX Delay -230 -> 252, step: 16
4503 11:05:19.162305 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4504 11:05:19.165900 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4505 11:05:19.172541 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4506 11:05:19.175746 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4507 11:05:19.179280 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4508 11:05:19.182087 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4509 11:05:19.189249 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4510 11:05:19.192325 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4511 11:05:19.195483 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4512 11:05:19.198729 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4513 11:05:19.201961 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4514 11:05:19.208889 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4515 11:05:19.212236 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4516 11:05:19.215162 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4517 11:05:19.218956 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4518 11:05:19.225189 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4519 11:05:19.225271 ==
4520 11:05:19.228203 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 11:05:19.231871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 11:05:19.231957 ==
4523 11:05:19.232024 DQS Delay:
4524 11:05:19.234925 DQS0 = 0, DQS1 = 0
4525 11:05:19.235007 DQM Delay:
4526 11:05:19.238334 DQM0 = 42, DQM1 = 38
4527 11:05:19.238410 DQ Delay:
4528 11:05:19.241803 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4529 11:05:19.244978 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4530 11:05:19.248520 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4531 11:05:19.251692 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4532 11:05:19.251819
4533 11:05:19.251934
4534 11:05:19.252051 ==
4535 11:05:19.254962 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 11:05:19.258119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 11:05:19.261633 ==
4538 11:05:19.261717
4539 11:05:19.261780
4540 11:05:19.261838 TX Vref Scan disable
4541 11:05:19.264860 == TX Byte 0 ==
4542 11:05:19.268115 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4543 11:05:19.271319 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4544 11:05:19.275087 == TX Byte 1 ==
4545 11:05:19.278220 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4546 11:05:19.284394 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4547 11:05:19.284476 ==
4548 11:05:19.287575 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 11:05:19.290743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 11:05:19.290826 ==
4551 11:05:19.290926
4552 11:05:19.291047
4553 11:05:19.293973 TX Vref Scan disable
4554 11:05:19.298494 == TX Byte 0 ==
4555 11:05:19.300802 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4556 11:05:19.304002 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4557 11:05:19.307648 == TX Byte 1 ==
4558 11:05:19.310607 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4559 11:05:19.313861 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4560 11:05:19.313942
4561 11:05:19.317017 [DATLAT]
4562 11:05:19.317144 Freq=600, CH1 RK0
4563 11:05:19.317240
4564 11:05:19.320391 DATLAT Default: 0x9
4565 11:05:19.320472 0, 0xFFFF, sum = 0
4566 11:05:19.324221 1, 0xFFFF, sum = 0
4567 11:05:19.324304 2, 0xFFFF, sum = 0
4568 11:05:19.327296 3, 0xFFFF, sum = 0
4569 11:05:19.327433 4, 0xFFFF, sum = 0
4570 11:05:19.330828 5, 0xFFFF, sum = 0
4571 11:05:19.330938 6, 0xFFFF, sum = 0
4572 11:05:19.333705 7, 0xFFFF, sum = 0
4573 11:05:19.333788 8, 0x0, sum = 1
4574 11:05:19.336772 9, 0x0, sum = 2
4575 11:05:19.336870 10, 0x0, sum = 3
4576 11:05:19.340146 11, 0x0, sum = 4
4577 11:05:19.340239 best_step = 9
4578 11:05:19.340306
4579 11:05:19.340366 ==
4580 11:05:19.343574 Dram Type= 6, Freq= 0, CH_1, rank 0
4581 11:05:19.347032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 11:05:19.350060 ==
4583 11:05:19.350168 RX Vref Scan: 1
4584 11:05:19.350260
4585 11:05:19.353631 RX Vref 0 -> 0, step: 1
4586 11:05:19.353731
4587 11:05:19.356550 RX Delay -179 -> 252, step: 8
4588 11:05:19.356636
4589 11:05:19.359968 Set Vref, RX VrefLevel [Byte0]: 51
4590 11:05:19.363052 [Byte1]: 51
4591 11:05:19.363129
4592 11:05:19.366629 Final RX Vref Byte 0 = 51 to rank0
4593 11:05:19.369923 Final RX Vref Byte 1 = 51 to rank0
4594 11:05:19.373133 Final RX Vref Byte 0 = 51 to rank1
4595 11:05:19.376374 Final RX Vref Byte 1 = 51 to rank1==
4596 11:05:19.380000 Dram Type= 6, Freq= 0, CH_1, rank 0
4597 11:05:19.383719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 11:05:19.383806 ==
4599 11:05:19.386282 DQS Delay:
4600 11:05:19.386370 DQS0 = 0, DQS1 = 0
4601 11:05:19.386459 DQM Delay:
4602 11:05:19.389447 DQM0 = 41, DQM1 = 34
4603 11:05:19.389544 DQ Delay:
4604 11:05:19.392746 DQ0 =48, DQ1 =36, DQ2 =32, DQ3 =40
4605 11:05:19.396002 DQ4 =36, DQ5 =52, DQ6 =48, DQ7 =36
4606 11:05:19.399759 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4607 11:05:19.402605 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4608 11:05:19.402706
4609 11:05:19.402770
4610 11:05:19.413130 [DQSOSCAuto] RK0, (LSB)MR18= 0x314a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4611 11:05:19.415976 CH1 RK0: MR19=808, MR18=314A
4612 11:05:19.419683 CH1_RK0: MR19=0x808, MR18=0x314A, DQSOSC=395, MR23=63, INC=168, DEC=112
4613 11:05:19.422626
4614 11:05:19.425920 ----->DramcWriteLeveling(PI) begin...
4615 11:05:19.426004 ==
4616 11:05:19.428990 Dram Type= 6, Freq= 0, CH_1, rank 1
4617 11:05:19.432403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 11:05:19.432486 ==
4619 11:05:19.435632 Write leveling (Byte 0): 30 => 30
4620 11:05:19.438934 Write leveling (Byte 1): 30 => 30
4621 11:05:19.442460 DramcWriteLeveling(PI) end<-----
4622 11:05:19.442541
4623 11:05:19.442622 ==
4624 11:05:19.445838 Dram Type= 6, Freq= 0, CH_1, rank 1
4625 11:05:19.448713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 11:05:19.448800 ==
4627 11:05:19.452370 [Gating] SW mode calibration
4628 11:05:19.458818 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4629 11:05:19.465796 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4630 11:05:19.468767 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4631 11:05:19.472001 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4632 11:05:19.479012 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4633 11:05:19.482155 0 9 12 | B1->B0 | 3232 2c2c | 0 0 | (0 0) (0 1)
4634 11:05:19.485546 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 11:05:19.491705 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 11:05:19.495203 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 11:05:19.498683 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 11:05:19.504984 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 11:05:19.508079 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 11:05:19.511698 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4641 11:05:19.518448 0 10 12 | B1->B0 | 2a2a 3b3b | 0 0 | (0 0) (0 0)
4642 11:05:19.521548 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 11:05:19.525327 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 11:05:19.531763 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 11:05:19.534850 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 11:05:19.538055 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 11:05:19.544249 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 11:05:19.547990 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 11:05:19.551032 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4650 11:05:19.557601 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 11:05:19.560650 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 11:05:19.564467 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 11:05:19.570799 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 11:05:19.574384 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 11:05:19.577642 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 11:05:19.583797 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 11:05:19.587453 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 11:05:19.590551 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 11:05:19.597306 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 11:05:19.600304 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 11:05:19.603634 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 11:05:19.610638 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 11:05:19.613554 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 11:05:19.616680 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4665 11:05:19.623718 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4666 11:05:19.623842 Total UI for P1: 0, mck2ui 16
4667 11:05:19.629936 best dqsien dly found for B0: ( 0, 13, 8)
4668 11:05:19.633527 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 11:05:19.636648 Total UI for P1: 0, mck2ui 16
4670 11:05:19.640243 best dqsien dly found for B1: ( 0, 13, 12)
4671 11:05:19.643253 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4672 11:05:19.646678 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4673 11:05:19.646881
4674 11:05:19.649948 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4675 11:05:19.653219 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4676 11:05:19.656645 [Gating] SW calibration Done
4677 11:05:19.656764 ==
4678 11:05:19.659549 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 11:05:19.666216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 11:05:19.666342 ==
4681 11:05:19.666456 RX Vref Scan: 0
4682 11:05:19.666584
4683 11:05:19.669448 RX Vref 0 -> 0, step: 1
4684 11:05:19.669546
4685 11:05:19.673146 RX Delay -230 -> 252, step: 16
4686 11:05:19.676146 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4687 11:05:19.679639 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4688 11:05:19.682683 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4689 11:05:19.689217 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4690 11:05:19.692550 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4691 11:05:19.696028 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4692 11:05:19.699192 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4693 11:05:19.705993 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4694 11:05:19.709068 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4695 11:05:19.712129 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4696 11:05:19.715526 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4697 11:05:19.722060 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4698 11:05:19.725261 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4699 11:05:19.728571 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4700 11:05:19.731922 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4701 11:05:19.738369 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4702 11:05:19.738494 ==
4703 11:05:19.741645 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 11:05:19.745402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 11:05:19.745524 ==
4706 11:05:19.745675 DQS Delay:
4707 11:05:19.748534 DQS0 = 0, DQS1 = 0
4708 11:05:19.748654 DQM Delay:
4709 11:05:19.751773 DQM0 = 42, DQM1 = 39
4710 11:05:19.751894 DQ Delay:
4711 11:05:19.755069 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4712 11:05:19.758144 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4713 11:05:19.761946 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4714 11:05:19.764835 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4715 11:05:19.764955
4716 11:05:19.765063
4717 11:05:19.765172 ==
4718 11:05:19.768461 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 11:05:19.774518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 11:05:19.774602 ==
4721 11:05:19.774706
4722 11:05:19.774808
4723 11:05:19.774910 TX Vref Scan disable
4724 11:05:19.777735 == TX Byte 0 ==
4725 11:05:19.781307 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4726 11:05:19.787876 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4727 11:05:19.787959 == TX Byte 1 ==
4728 11:05:19.791146 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4729 11:05:19.797379 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4730 11:05:19.797503 ==
4731 11:05:19.800682 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 11:05:19.804281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 11:05:19.804417 ==
4734 11:05:19.804533
4735 11:05:19.804645
4736 11:05:19.807247 TX Vref Scan disable
4737 11:05:19.810572 == TX Byte 0 ==
4738 11:05:19.814128 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4739 11:05:19.817245 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4740 11:05:19.820817 == TX Byte 1 ==
4741 11:05:19.823888 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4742 11:05:19.827004 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4743 11:05:19.827126
4744 11:05:19.830465 [DATLAT]
4745 11:05:19.830588 Freq=600, CH1 RK1
4746 11:05:19.830702
4747 11:05:19.833701 DATLAT Default: 0x9
4748 11:05:19.833822 0, 0xFFFF, sum = 0
4749 11:05:19.837515 1, 0xFFFF, sum = 0
4750 11:05:19.837640 2, 0xFFFF, sum = 0
4751 11:05:19.840522 3, 0xFFFF, sum = 0
4752 11:05:19.840659 4, 0xFFFF, sum = 0
4753 11:05:19.843782 5, 0xFFFF, sum = 0
4754 11:05:19.843907 6, 0xFFFF, sum = 0
4755 11:05:19.847154 7, 0xFFFF, sum = 0
4756 11:05:19.847275 8, 0x0, sum = 1
4757 11:05:19.850143 9, 0x0, sum = 2
4758 11:05:19.850266 10, 0x0, sum = 3
4759 11:05:19.853587 11, 0x0, sum = 4
4760 11:05:19.853711 best_step = 9
4761 11:05:19.853848
4762 11:05:19.853975 ==
4763 11:05:19.856617 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 11:05:19.860690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 11:05:19.863555 ==
4766 11:05:19.863658 RX Vref Scan: 0
4767 11:05:19.863783
4768 11:05:19.866799 RX Vref 0 -> 0, step: 1
4769 11:05:19.866903
4770 11:05:19.869860 RX Delay -179 -> 252, step: 8
4771 11:05:19.873297 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4772 11:05:19.876647 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4773 11:05:19.883129 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4774 11:05:19.886435 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4775 11:05:19.889708 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4776 11:05:19.893094 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4777 11:05:19.899284 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4778 11:05:19.903283 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4779 11:05:19.907377 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4780 11:05:19.909606 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4781 11:05:19.916200 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4782 11:05:19.919534 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4783 11:05:19.922608 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4784 11:05:19.926062 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4785 11:05:19.932470 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4786 11:05:19.935666 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4787 11:05:19.935748 ==
4788 11:05:19.939077 Dram Type= 6, Freq= 0, CH_1, rank 1
4789 11:05:19.942144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4790 11:05:19.942277 ==
4791 11:05:19.945472 DQS Delay:
4792 11:05:19.945578 DQS0 = 0, DQS1 = 0
4793 11:05:19.945657 DQM Delay:
4794 11:05:19.948828 DQM0 = 38, DQM1 = 34
4795 11:05:19.948996 DQ Delay:
4796 11:05:19.951910 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =40
4797 11:05:19.955713 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4798 11:05:19.958392 DQ8 =20, DQ9 =24, DQ10 =40, DQ11 =24
4799 11:05:19.962023 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4800 11:05:19.962148
4801 11:05:19.962276
4802 11:05:19.971975 [DQSOSCAuto] RK1, (LSB)MR18= 0x3358, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4803 11:05:19.975056 CH1 RK1: MR19=808, MR18=3358
4804 11:05:19.981464 CH1_RK1: MR19=0x808, MR18=0x3358, DQSOSC=393, MR23=63, INC=169, DEC=113
4805 11:05:19.981602 [RxdqsGatingPostProcess] freq 600
4806 11:05:19.988322 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4807 11:05:19.991644 Pre-setting of DQS Precalculation
4808 11:05:19.994991 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4809 11:05:20.004758 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4810 11:05:20.011504 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4811 11:05:20.011656
4812 11:05:20.011771
4813 11:05:20.014783 [Calibration Summary] 1200 Mbps
4814 11:05:20.014907 CH 0, Rank 0
4815 11:05:20.017879 SW Impedance : PASS
4816 11:05:20.018015 DUTY Scan : NO K
4817 11:05:20.021398 ZQ Calibration : PASS
4818 11:05:20.025050 Jitter Meter : NO K
4819 11:05:20.025177 CBT Training : PASS
4820 11:05:20.027842 Write leveling : PASS
4821 11:05:20.030804 RX DQS gating : PASS
4822 11:05:20.030929 RX DQ/DQS(RDDQC) : PASS
4823 11:05:20.034216 TX DQ/DQS : PASS
4824 11:05:20.037456 RX DATLAT : PASS
4825 11:05:20.037594 RX DQ/DQS(Engine): PASS
4826 11:05:20.040894 TX OE : NO K
4827 11:05:20.041019 All Pass.
4828 11:05:20.041144
4829 11:05:20.043895 CH 0, Rank 1
4830 11:05:20.044023 SW Impedance : PASS
4831 11:05:20.047582 DUTY Scan : NO K
4832 11:05:20.050497 ZQ Calibration : PASS
4833 11:05:20.050629 Jitter Meter : NO K
4834 11:05:20.054263 CBT Training : PASS
4835 11:05:20.057332 Write leveling : PASS
4836 11:05:20.057460 RX DQS gating : PASS
4837 11:05:20.060791 RX DQ/DQS(RDDQC) : PASS
4838 11:05:20.063971 TX DQ/DQS : PASS
4839 11:05:20.064097 RX DATLAT : PASS
4840 11:05:20.067550 RX DQ/DQS(Engine): PASS
4841 11:05:20.070410 TX OE : NO K
4842 11:05:20.070516 All Pass.
4843 11:05:20.070608
4844 11:05:20.070697 CH 1, Rank 0
4845 11:05:20.073993 SW Impedance : PASS
4846 11:05:20.076760 DUTY Scan : NO K
4847 11:05:20.076862 ZQ Calibration : PASS
4848 11:05:20.080300 Jitter Meter : NO K
4849 11:05:20.083643 CBT Training : PASS
4850 11:05:20.083727 Write leveling : PASS
4851 11:05:20.087184 RX DQS gating : PASS
4852 11:05:20.089943 RX DQ/DQS(RDDQC) : PASS
4853 11:05:20.090025 TX DQ/DQS : PASS
4854 11:05:20.093648 RX DATLAT : PASS
4855 11:05:20.096843 RX DQ/DQS(Engine): PASS
4856 11:05:20.096926 TX OE : NO K
4857 11:05:20.096991 All Pass.
4858 11:05:20.100171
4859 11:05:20.100299 CH 1, Rank 1
4860 11:05:20.102943 SW Impedance : PASS
4861 11:05:20.103067 DUTY Scan : NO K
4862 11:05:20.106525 ZQ Calibration : PASS
4863 11:05:20.109974 Jitter Meter : NO K
4864 11:05:20.110081 CBT Training : PASS
4865 11:05:20.113357 Write leveling : PASS
4866 11:05:20.116333 RX DQS gating : PASS
4867 11:05:20.116466 RX DQ/DQS(RDDQC) : PASS
4868 11:05:20.119641 TX DQ/DQS : PASS
4869 11:05:20.119736 RX DATLAT : PASS
4870 11:05:20.122966 RX DQ/DQS(Engine): PASS
4871 11:05:20.126240 TX OE : NO K
4872 11:05:20.126353 All Pass.
4873 11:05:20.126448
4874 11:05:20.129215 DramC Write-DBI off
4875 11:05:20.132735 PER_BANK_REFRESH: Hybrid Mode
4876 11:05:20.132838 TX_TRACKING: ON
4877 11:05:20.142813 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4878 11:05:20.145725 [FAST_K] Save calibration result to emmc
4879 11:05:20.149084 dramc_set_vcore_voltage set vcore to 662500
4880 11:05:20.152333 Read voltage for 933, 3
4881 11:05:20.152421 Vio18 = 0
4882 11:05:20.152489 Vcore = 662500
4883 11:05:20.155589 Vdram = 0
4884 11:05:20.155668 Vddq = 0
4885 11:05:20.155743 Vmddr = 0
4886 11:05:20.162160 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4887 11:05:20.165973 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4888 11:05:20.168930 MEM_TYPE=3, freq_sel=17
4889 11:05:20.172816 sv_algorithm_assistance_LP4_1600
4890 11:05:20.175690 ============ PULL DRAM RESETB DOWN ============
4891 11:05:20.179071 ========== PULL DRAM RESETB DOWN end =========
4892 11:05:20.185284 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4893 11:05:20.188737 ===================================
4894 11:05:20.188816 LPDDR4 DRAM CONFIGURATION
4895 11:05:20.192156 ===================================
4896 11:05:20.195160 EX_ROW_EN[0] = 0x0
4897 11:05:20.198496 EX_ROW_EN[1] = 0x0
4898 11:05:20.198576 LP4Y_EN = 0x0
4899 11:05:20.202199 WORK_FSP = 0x0
4900 11:05:20.202283 WL = 0x3
4901 11:05:20.204918 RL = 0x3
4902 11:05:20.205028 BL = 0x2
4903 11:05:20.208520 RPST = 0x0
4904 11:05:20.208622 RD_PRE = 0x0
4905 11:05:20.212031 WR_PRE = 0x1
4906 11:05:20.212140 WR_PST = 0x0
4907 11:05:20.215213 DBI_WR = 0x0
4908 11:05:20.215325 DBI_RD = 0x0
4909 11:05:20.218307 OTF = 0x1
4910 11:05:20.221370 ===================================
4911 11:05:20.224985 ===================================
4912 11:05:20.225095 ANA top config
4913 11:05:20.228211 ===================================
4914 11:05:20.231737 DLL_ASYNC_EN = 0
4915 11:05:20.234920 ALL_SLAVE_EN = 1
4916 11:05:20.237958 NEW_RANK_MODE = 1
4917 11:05:20.241327 DLL_IDLE_MODE = 1
4918 11:05:20.241404 LP45_APHY_COMB_EN = 1
4919 11:05:20.244587 TX_ODT_DIS = 1
4920 11:05:20.247872 NEW_8X_MODE = 1
4921 11:05:20.251417 ===================================
4922 11:05:20.254245 ===================================
4923 11:05:20.257552 data_rate = 1866
4924 11:05:20.261042 CKR = 1
4925 11:05:20.261129 DQ_P2S_RATIO = 8
4926 11:05:20.264141 ===================================
4927 11:05:20.267921 CA_P2S_RATIO = 8
4928 11:05:20.270966 DQ_CA_OPEN = 0
4929 11:05:20.274559 DQ_SEMI_OPEN = 0
4930 11:05:20.277446 CA_SEMI_OPEN = 0
4931 11:05:20.281078 CA_FULL_RATE = 0
4932 11:05:20.281205 DQ_CKDIV4_EN = 1
4933 11:05:20.284219 CA_CKDIV4_EN = 1
4934 11:05:20.287530 CA_PREDIV_EN = 0
4935 11:05:20.290755 PH8_DLY = 0
4936 11:05:20.293919 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4937 11:05:20.297530 DQ_AAMCK_DIV = 4
4938 11:05:20.297663 CA_AAMCK_DIV = 4
4939 11:05:20.300609 CA_ADMCK_DIV = 4
4940 11:05:20.303828 DQ_TRACK_CA_EN = 0
4941 11:05:20.307138 CA_PICK = 933
4942 11:05:20.310643 CA_MCKIO = 933
4943 11:05:20.314122 MCKIO_SEMI = 0
4944 11:05:20.317252 PLL_FREQ = 3732
4945 11:05:20.317360 DQ_UI_PI_RATIO = 32
4946 11:05:20.320863 CA_UI_PI_RATIO = 0
4947 11:05:20.324121 ===================================
4948 11:05:20.327256 ===================================
4949 11:05:20.330292 memory_type:LPDDR4
4950 11:05:20.333951 GP_NUM : 10
4951 11:05:20.334078 SRAM_EN : 1
4952 11:05:20.336794 MD32_EN : 0
4953 11:05:20.340147 ===================================
4954 11:05:20.343321 [ANA_INIT] >>>>>>>>>>>>>>
4955 11:05:20.346798 <<<<<< [CONFIGURE PHASE]: ANA_TX
4956 11:05:20.350176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4957 11:05:20.353640 ===================================
4958 11:05:20.353768 data_rate = 1866,PCW = 0X8f00
4959 11:05:20.356871 ===================================
4960 11:05:20.360026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4961 11:05:20.366668 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4962 11:05:20.372958 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4963 11:05:20.376574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4964 11:05:20.379786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4965 11:05:20.383070 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4966 11:05:20.386631 [ANA_INIT] flow start
4967 11:05:20.389701 [ANA_INIT] PLL >>>>>>>>
4968 11:05:20.389826 [ANA_INIT] PLL <<<<<<<<
4969 11:05:20.392933 [ANA_INIT] MIDPI >>>>>>>>
4970 11:05:20.396245 [ANA_INIT] MIDPI <<<<<<<<
4971 11:05:20.396368 [ANA_INIT] DLL >>>>>>>>
4972 11:05:20.399645 [ANA_INIT] flow end
4973 11:05:20.403428 ============ LP4 DIFF to SE enter ============
4974 11:05:20.405989 ============ LP4 DIFF to SE exit ============
4975 11:05:20.409662 [ANA_INIT] <<<<<<<<<<<<<
4976 11:05:20.412703 [Flow] Enable top DCM control >>>>>
4977 11:05:20.416037 [Flow] Enable top DCM control <<<<<
4978 11:05:20.419098 Enable DLL master slave shuffle
4979 11:05:20.425780 ==============================================================
4980 11:05:20.425869 Gating Mode config
4981 11:05:20.432642 ==============================================================
4982 11:05:20.435684 Config description:
4983 11:05:20.442547 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4984 11:05:20.448770 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4985 11:05:20.455387 SELPH_MODE 0: By rank 1: By Phase
4986 11:05:20.462150 ==============================================================
4987 11:05:20.465507 GAT_TRACK_EN = 1
4988 11:05:20.465592 RX_GATING_MODE = 2
4989 11:05:20.469107 RX_GATING_TRACK_MODE = 2
4990 11:05:20.472086 SELPH_MODE = 1
4991 11:05:20.475454 PICG_EARLY_EN = 1
4992 11:05:20.478714 VALID_LAT_VALUE = 1
4993 11:05:20.485001 ==============================================================
4994 11:05:20.488470 Enter into Gating configuration >>>>
4995 11:05:20.491769 Exit from Gating configuration <<<<
4996 11:05:20.495058 Enter into DVFS_PRE_config >>>>>
4997 11:05:20.504989 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4998 11:05:20.508603 Exit from DVFS_PRE_config <<<<<
4999 11:05:20.511576 Enter into PICG configuration >>>>
5000 11:05:20.515118 Exit from PICG configuration <<<<
5001 11:05:20.518474 [RX_INPUT] configuration >>>>>
5002 11:05:20.521821 [RX_INPUT] configuration <<<<<
5003 11:05:20.524983 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5004 11:05:20.531504 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5005 11:05:20.538128 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5006 11:05:20.544403 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5007 11:05:20.550978 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5008 11:05:20.554378 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5009 11:05:20.561050 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5010 11:05:20.564459 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5011 11:05:20.567494 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5012 11:05:20.570929 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5013 11:05:20.577318 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5014 11:05:20.580876 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5015 11:05:20.584220 ===================================
5016 11:05:20.587756 LPDDR4 DRAM CONFIGURATION
5017 11:05:20.590872 ===================================
5018 11:05:20.590965 EX_ROW_EN[0] = 0x0
5019 11:05:20.593719 EX_ROW_EN[1] = 0x0
5020 11:05:20.593809 LP4Y_EN = 0x0
5021 11:05:20.597179 WORK_FSP = 0x0
5022 11:05:20.597266 WL = 0x3
5023 11:05:20.600624 RL = 0x3
5024 11:05:20.600708 BL = 0x2
5025 11:05:20.603978 RPST = 0x0
5026 11:05:20.606943 RD_PRE = 0x0
5027 11:05:20.607029 WR_PRE = 0x1
5028 11:05:20.610491 WR_PST = 0x0
5029 11:05:20.610577 DBI_WR = 0x0
5030 11:05:20.613701 DBI_RD = 0x0
5031 11:05:20.613775 OTF = 0x1
5032 11:05:20.617185 ===================================
5033 11:05:20.620604 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5034 11:05:20.627111 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5035 11:05:20.629933 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5036 11:05:20.633553 ===================================
5037 11:05:20.636773 LPDDR4 DRAM CONFIGURATION
5038 11:05:20.640256 ===================================
5039 11:05:20.640352 EX_ROW_EN[0] = 0x10
5040 11:05:20.643202 EX_ROW_EN[1] = 0x0
5041 11:05:20.643318 LP4Y_EN = 0x0
5042 11:05:20.646495 WORK_FSP = 0x0
5043 11:05:20.646579 WL = 0x3
5044 11:05:20.649687 RL = 0x3
5045 11:05:20.652812 BL = 0x2
5046 11:05:20.652910 RPST = 0x0
5047 11:05:20.656079 RD_PRE = 0x0
5048 11:05:20.656191 WR_PRE = 0x1
5049 11:05:20.659845 WR_PST = 0x0
5050 11:05:20.659928 DBI_WR = 0x0
5051 11:05:20.663021 DBI_RD = 0x0
5052 11:05:20.663135 OTF = 0x1
5053 11:05:20.666062 ===================================
5054 11:05:20.672810 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5055 11:05:20.677238 nWR fixed to 30
5056 11:05:20.680326 [ModeRegInit_LP4] CH0 RK0
5057 11:05:20.680409 [ModeRegInit_LP4] CH0 RK1
5058 11:05:20.683234 [ModeRegInit_LP4] CH1 RK0
5059 11:05:20.686771 [ModeRegInit_LP4] CH1 RK1
5060 11:05:20.686858 match AC timing 9
5061 11:05:20.693291 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5062 11:05:20.696792 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5063 11:05:20.699645 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5064 11:05:20.706510 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5065 11:05:20.709588 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5066 11:05:20.709726 ==
5067 11:05:20.712832 Dram Type= 6, Freq= 0, CH_0, rank 0
5068 11:05:20.716533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5069 11:05:20.716615 ==
5070 11:05:20.722746 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5071 11:05:20.729426 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5072 11:05:20.732641 [CA 0] Center 37 (7~68) winsize 62
5073 11:05:20.736220 [CA 1] Center 37 (7~68) winsize 62
5074 11:05:20.739473 [CA 2] Center 34 (4~64) winsize 61
5075 11:05:20.742646 [CA 3] Center 34 (4~64) winsize 61
5076 11:05:20.746231 [CA 4] Center 32 (2~63) winsize 62
5077 11:05:20.749314 [CA 5] Center 32 (2~63) winsize 62
5078 11:05:20.749399
5079 11:05:20.752626 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5080 11:05:20.752742
5081 11:05:20.756366 [CATrainingPosCal] consider 1 rank data
5082 11:05:20.759332 u2DelayCellTimex100 = 270/100 ps
5083 11:05:20.762530 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5084 11:05:20.765611 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5085 11:05:20.769100 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5086 11:05:20.775601 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5087 11:05:20.778901 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5088 11:05:20.782118 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5089 11:05:20.782203
5090 11:05:20.785372 CA PerBit enable=1, Macro0, CA PI delay=32
5091 11:05:20.785457
5092 11:05:20.788797 [CBTSetCACLKResult] CA Dly = 32
5093 11:05:20.788882 CS Dly: 6 (0~37)
5094 11:05:20.788948 ==
5095 11:05:20.791975 Dram Type= 6, Freq= 0, CH_0, rank 1
5096 11:05:20.798910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 11:05:20.798997 ==
5098 11:05:20.801971 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5099 11:05:20.808542 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5100 11:05:20.812391 [CA 0] Center 37 (7~68) winsize 62
5101 11:05:20.815768 [CA 1] Center 37 (7~68) winsize 62
5102 11:05:20.818604 [CA 2] Center 34 (4~65) winsize 62
5103 11:05:20.822047 [CA 3] Center 34 (4~65) winsize 62
5104 11:05:20.825927 [CA 4] Center 33 (3~64) winsize 62
5105 11:05:20.828747 [CA 5] Center 32 (2~63) winsize 62
5106 11:05:20.828837
5107 11:05:20.831511 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5108 11:05:20.831596
5109 11:05:20.834991 [CATrainingPosCal] consider 2 rank data
5110 11:05:20.838367 u2DelayCellTimex100 = 270/100 ps
5111 11:05:20.844981 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5112 11:05:20.848126 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5113 11:05:20.851223 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5114 11:05:20.854547 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5115 11:05:20.858262 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5116 11:05:20.861276 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5117 11:05:20.861361
5118 11:05:20.864342 CA PerBit enable=1, Macro0, CA PI delay=32
5119 11:05:20.864426
5120 11:05:20.867623 [CBTSetCACLKResult] CA Dly = 32
5121 11:05:20.871236 CS Dly: 7 (0~39)
5122 11:05:20.871345
5123 11:05:20.874264 ----->DramcWriteLeveling(PI) begin...
5124 11:05:20.874378 ==
5125 11:05:20.878090 Dram Type= 6, Freq= 0, CH_0, rank 0
5126 11:05:20.881479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5127 11:05:20.881563 ==
5128 11:05:20.884440 Write leveling (Byte 0): 30 => 30
5129 11:05:20.887668 Write leveling (Byte 1): 28 => 28
5130 11:05:20.890719 DramcWriteLeveling(PI) end<-----
5131 11:05:20.890829
5132 11:05:20.890897 ==
5133 11:05:20.893930 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 11:05:20.897497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 11:05:20.897582 ==
5136 11:05:20.901068 [Gating] SW mode calibration
5137 11:05:20.907152 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5138 11:05:20.913803 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5139 11:05:20.916957 0 14 0 | B1->B0 | 2828 3434 | 1 0 | (0 0) (0 0)
5140 11:05:20.923509 0 14 4 | B1->B0 | 3433 3434 | 1 1 | (0 0) (1 1)
5141 11:05:20.926907 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 11:05:20.930249 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 11:05:20.936691 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 11:05:20.939958 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 11:05:20.943757 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5146 11:05:20.950279 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 1)
5147 11:05:20.953471 0 15 0 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
5148 11:05:20.957029 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5149 11:05:20.963199 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 11:05:20.966620 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 11:05:20.969792 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 11:05:20.976622 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 11:05:20.979643 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5154 11:05:20.982794 0 15 28 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
5155 11:05:20.989760 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5156 11:05:20.993018 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 11:05:20.996059 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 11:05:21.002830 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 11:05:21.006218 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 11:05:21.009127 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 11:05:21.016182 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 11:05:21.019079 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5163 11:05:21.022328 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5164 11:05:21.029429 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 11:05:21.032547 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 11:05:21.035529 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 11:05:21.042316 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 11:05:21.045475 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 11:05:21.048653 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 11:05:21.055195 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 11:05:21.058691 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 11:05:21.061870 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 11:05:21.068384 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 11:05:21.072271 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 11:05:21.075184 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 11:05:21.082526 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 11:05:21.085370 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 11:05:21.088571 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5179 11:05:21.095496 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5180 11:05:21.095593 Total UI for P1: 0, mck2ui 16
5181 11:05:21.101835 best dqsien dly found for B0: ( 1, 2, 28)
5182 11:05:21.104629 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5183 11:05:21.108132 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 11:05:21.111337 Total UI for P1: 0, mck2ui 16
5185 11:05:21.115014 best dqsien dly found for B1: ( 1, 3, 2)
5186 11:05:21.118047 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5187 11:05:21.121179 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5188 11:05:21.121301
5189 11:05:21.127994 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5190 11:05:21.131662 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5191 11:05:21.134504 [Gating] SW calibration Done
5192 11:05:21.134586 ==
5193 11:05:21.137424 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 11:05:21.140907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 11:05:21.140989 ==
5196 11:05:21.141054 RX Vref Scan: 0
5197 11:05:21.141114
5198 11:05:21.144379 RX Vref 0 -> 0, step: 1
5199 11:05:21.144461
5200 11:05:21.147738 RX Delay -80 -> 252, step: 8
5201 11:05:21.150912 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5202 11:05:21.154223 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5203 11:05:21.160755 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5204 11:05:21.163990 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5205 11:05:21.167275 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5206 11:05:21.170798 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5207 11:05:21.173842 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5208 11:05:21.177451 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5209 11:05:21.183597 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5210 11:05:21.187075 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5211 11:05:21.190130 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5212 11:05:21.193461 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5213 11:05:21.197112 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5214 11:05:21.200188 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5215 11:05:21.206765 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5216 11:05:21.210871 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5217 11:05:21.210953 ==
5218 11:05:21.213631 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 11:05:21.216679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 11:05:21.216761 ==
5221 11:05:21.219953 DQS Delay:
5222 11:05:21.220035 DQS0 = 0, DQS1 = 0
5223 11:05:21.220099 DQM Delay:
5224 11:05:21.223210 DQM0 = 99, DQM1 = 89
5225 11:05:21.223291 DQ Delay:
5226 11:05:21.226440 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5227 11:05:21.230015 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5228 11:05:21.233143 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =83
5229 11:05:21.236488 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5230 11:05:21.236584
5231 11:05:21.236648
5232 11:05:21.239806 ==
5233 11:05:21.242975 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 11:05:21.246084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 11:05:21.246167 ==
5236 11:05:21.246232
5237 11:05:21.246292
5238 11:05:21.249230 TX Vref Scan disable
5239 11:05:21.249312 == TX Byte 0 ==
5240 11:05:21.255783 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5241 11:05:21.259090 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5242 11:05:21.259203 == TX Byte 1 ==
5243 11:05:21.265941 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5244 11:05:21.268919 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5245 11:05:21.269002 ==
5246 11:05:21.272372 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 11:05:21.276038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 11:05:21.276122 ==
5249 11:05:21.276187
5250 11:05:21.276264
5251 11:05:21.279268 TX Vref Scan disable
5252 11:05:21.282328 == TX Byte 0 ==
5253 11:05:21.285623 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5254 11:05:21.288978 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5255 11:05:21.292166 == TX Byte 1 ==
5256 11:05:21.295602 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5257 11:05:21.298822 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5258 11:05:21.298904
5259 11:05:21.301829 [DATLAT]
5260 11:05:21.301938 Freq=933, CH0 RK0
5261 11:05:21.302031
5262 11:05:21.305191 DATLAT Default: 0xd
5263 11:05:21.305291 0, 0xFFFF, sum = 0
5264 11:05:21.308375 1, 0xFFFF, sum = 0
5265 11:05:21.308458 2, 0xFFFF, sum = 0
5266 11:05:21.311667 3, 0xFFFF, sum = 0
5267 11:05:21.311753 4, 0xFFFF, sum = 0
5268 11:05:21.315165 5, 0xFFFF, sum = 0
5269 11:05:21.318637 6, 0xFFFF, sum = 0
5270 11:05:21.318721 7, 0xFFFF, sum = 0
5271 11:05:21.321917 8, 0xFFFF, sum = 0
5272 11:05:21.322003 9, 0xFFFF, sum = 0
5273 11:05:21.325141 10, 0x0, sum = 1
5274 11:05:21.325225 11, 0x0, sum = 2
5275 11:05:21.325291 12, 0x0, sum = 3
5276 11:05:21.328457 13, 0x0, sum = 4
5277 11:05:21.328558 best_step = 11
5278 11:05:21.328637
5279 11:05:21.331670 ==
5280 11:05:21.331753 Dram Type= 6, Freq= 0, CH_0, rank 0
5281 11:05:21.338296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 11:05:21.338379 ==
5283 11:05:21.338459 RX Vref Scan: 1
5284 11:05:21.338535
5285 11:05:21.341537 RX Vref 0 -> 0, step: 1
5286 11:05:21.341633
5287 11:05:21.344770 RX Delay -53 -> 252, step: 4
5288 11:05:21.344854
5289 11:05:21.348300 Set Vref, RX VrefLevel [Byte0]: 54
5290 11:05:21.351545 [Byte1]: 59
5291 11:05:21.351644
5292 11:05:21.354829 Final RX Vref Byte 0 = 54 to rank0
5293 11:05:21.358211 Final RX Vref Byte 1 = 59 to rank0
5294 11:05:21.361208 Final RX Vref Byte 0 = 54 to rank1
5295 11:05:21.364479 Final RX Vref Byte 1 = 59 to rank1==
5296 11:05:21.368070 Dram Type= 6, Freq= 0, CH_0, rank 0
5297 11:05:21.371267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 11:05:21.374698 ==
5299 11:05:21.374781 DQS Delay:
5300 11:05:21.374846 DQS0 = 0, DQS1 = 0
5301 11:05:21.377411 DQM Delay:
5302 11:05:21.377494 DQM0 = 99, DQM1 = 88
5303 11:05:21.380993 DQ Delay:
5304 11:05:21.384106 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5305 11:05:21.387318 DQ4 =100, DQ5 =90, DQ6 =110, DQ7 =106
5306 11:05:21.390794 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =82
5307 11:05:21.394193 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =94
5308 11:05:21.394276
5309 11:05:21.394342
5310 11:05:21.400574 [DQSOSCAuto] RK0, (LSB)MR18= 0x1711, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5311 11:05:21.403703 CH0 RK0: MR19=505, MR18=1711
5312 11:05:21.410569 CH0_RK0: MR19=0x505, MR18=0x1711, DQSOSC=414, MR23=63, INC=63, DEC=42
5313 11:05:21.410656
5314 11:05:21.413474 ----->DramcWriteLeveling(PI) begin...
5315 11:05:21.413558 ==
5316 11:05:21.416972 Dram Type= 6, Freq= 0, CH_0, rank 1
5317 11:05:21.420488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 11:05:21.420596 ==
5319 11:05:21.423558 Write leveling (Byte 0): 33 => 33
5320 11:05:21.427469 Write leveling (Byte 1): 30 => 30
5321 11:05:21.430167 DramcWriteLeveling(PI) end<-----
5322 11:05:21.430275
5323 11:05:21.430377 ==
5324 11:05:21.433739 Dram Type= 6, Freq= 0, CH_0, rank 1
5325 11:05:21.440284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 11:05:21.440374 ==
5327 11:05:21.440441 [Gating] SW mode calibration
5328 11:05:21.450071 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5329 11:05:21.453110 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5330 11:05:21.459633 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5331 11:05:21.463039 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 11:05:21.466128 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 11:05:21.472840 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 11:05:21.476590 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 11:05:21.479910 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 11:05:21.485746 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5337 11:05:21.488998 0 14 28 | B1->B0 | 3434 2525 | 0 0 | (0 0) (0 0)
5338 11:05:21.492484 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5339 11:05:21.499024 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 11:05:21.502375 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 11:05:21.505464 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 11:05:21.512156 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 11:05:21.515600 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 11:05:21.518867 0 15 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5345 11:05:21.525438 0 15 28 | B1->B0 | 2727 4242 | 0 0 | (0 0) (0 0)
5346 11:05:21.528660 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5347 11:05:21.531909 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 11:05:21.538949 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 11:05:21.541852 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 11:05:21.545313 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 11:05:21.552114 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 11:05:21.555015 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5353 11:05:21.558447 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5354 11:05:21.564961 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5355 11:05:21.568473 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 11:05:21.571937 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 11:05:21.578621 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 11:05:21.581385 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 11:05:21.584576 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 11:05:21.591261 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 11:05:21.594667 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 11:05:21.598126 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 11:05:21.604345 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 11:05:21.607572 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 11:05:21.611475 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 11:05:21.617648 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 11:05:21.621360 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 11:05:21.623997 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 11:05:21.630999 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5370 11:05:21.634014 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5371 11:05:21.637624 Total UI for P1: 0, mck2ui 16
5372 11:05:21.640583 best dqsien dly found for B0: ( 1, 2, 28)
5373 11:05:21.643981 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 11:05:21.647310 Total UI for P1: 0, mck2ui 16
5375 11:05:21.650480 best dqsien dly found for B1: ( 1, 3, 0)
5376 11:05:21.654267 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5377 11:05:21.656949 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5378 11:05:21.657031
5379 11:05:21.663388 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5380 11:05:21.667079 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5381 11:05:21.667161 [Gating] SW calibration Done
5382 11:05:21.670513 ==
5383 11:05:21.673635 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 11:05:21.677261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 11:05:21.677344 ==
5386 11:05:21.677408 RX Vref Scan: 0
5387 11:05:21.677468
5388 11:05:21.679762 RX Vref 0 -> 0, step: 1
5389 11:05:21.679843
5390 11:05:21.683245 RX Delay -80 -> 252, step: 8
5391 11:05:21.686661 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5392 11:05:21.690075 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5393 11:05:21.693275 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5394 11:05:21.699747 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5395 11:05:21.702846 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5396 11:05:21.706266 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5397 11:05:21.710382 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5398 11:05:21.712970 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5399 11:05:21.719261 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5400 11:05:21.723015 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5401 11:05:21.726287 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5402 11:05:21.729423 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5403 11:05:21.732967 iDelay=200, Bit 12, Center 95 (8 ~ 183) 176
5404 11:05:21.736086 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5405 11:05:21.742432 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5406 11:05:21.745821 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5407 11:05:21.745920 ==
5408 11:05:21.749231 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 11:05:21.752554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 11:05:21.752627 ==
5411 11:05:21.756159 DQS Delay:
5412 11:05:21.756263 DQS0 = 0, DQS1 = 0
5413 11:05:21.756353 DQM Delay:
5414 11:05:21.759317 DQM0 = 97, DQM1 = 91
5415 11:05:21.759451 DQ Delay:
5416 11:05:21.762470 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5417 11:05:21.765577 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5418 11:05:21.768648 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5419 11:05:21.772211 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5420 11:05:21.772287
5421 11:05:21.772367
5422 11:05:21.772427 ==
5423 11:05:21.775475 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 11:05:21.781922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 11:05:21.782022 ==
5426 11:05:21.782110
5427 11:05:21.782206
5428 11:05:21.782292 TX Vref Scan disable
5429 11:05:21.785957 == TX Byte 0 ==
5430 11:05:21.789130 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5431 11:05:21.795548 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5432 11:05:21.795654 == TX Byte 1 ==
5433 11:05:21.798696 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5434 11:05:21.805429 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5435 11:05:21.805505 ==
5436 11:05:21.808545 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 11:05:21.812771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 11:05:21.812882 ==
5439 11:05:21.812985
5440 11:05:21.813059
5441 11:05:21.815183 TX Vref Scan disable
5442 11:05:21.815280 == TX Byte 0 ==
5443 11:05:21.822323 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5444 11:05:21.825141 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5445 11:05:21.828800 == TX Byte 1 ==
5446 11:05:21.831896 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5447 11:05:21.835069 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5448 11:05:21.835144
5449 11:05:21.835206 [DATLAT]
5450 11:05:21.838201 Freq=933, CH0 RK1
5451 11:05:21.838273
5452 11:05:21.841994 DATLAT Default: 0xb
5453 11:05:21.842068 0, 0xFFFF, sum = 0
5454 11:05:21.844757 1, 0xFFFF, sum = 0
5455 11:05:21.844862 2, 0xFFFF, sum = 0
5456 11:05:21.847991 3, 0xFFFF, sum = 0
5457 11:05:21.848064 4, 0xFFFF, sum = 0
5458 11:05:21.851913 5, 0xFFFF, sum = 0
5459 11:05:21.851986 6, 0xFFFF, sum = 0
5460 11:05:21.854973 7, 0xFFFF, sum = 0
5461 11:05:21.855070 8, 0xFFFF, sum = 0
5462 11:05:21.857914 9, 0xFFFF, sum = 0
5463 11:05:21.858004 10, 0x0, sum = 1
5464 11:05:21.861474 11, 0x0, sum = 2
5465 11:05:21.861576 12, 0x0, sum = 3
5466 11:05:21.864561 13, 0x0, sum = 4
5467 11:05:21.864671 best_step = 11
5468 11:05:21.864763
5469 11:05:21.864847 ==
5470 11:05:21.867635 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 11:05:21.870940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 11:05:21.874375 ==
5473 11:05:21.874491 RX Vref Scan: 0
5474 11:05:21.874586
5475 11:05:21.877997 RX Vref 0 -> 0, step: 1
5476 11:05:21.878072
5477 11:05:21.881033 RX Delay -53 -> 252, step: 4
5478 11:05:21.884302 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5479 11:05:21.887666 iDelay=195, Bit 1, Center 100 (11 ~ 190) 180
5480 11:05:21.891176 iDelay=195, Bit 2, Center 94 (7 ~ 182) 176
5481 11:05:21.897496 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5482 11:05:21.900934 iDelay=195, Bit 4, Center 100 (11 ~ 190) 180
5483 11:05:21.904171 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5484 11:05:21.907227 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5485 11:05:21.910779 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5486 11:05:21.917253 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5487 11:05:21.920593 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5488 11:05:21.923766 iDelay=195, Bit 10, Center 92 (3 ~ 182) 180
5489 11:05:21.927796 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5490 11:05:21.930370 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5491 11:05:21.937115 iDelay=195, Bit 13, Center 96 (7 ~ 186) 180
5492 11:05:21.940380 iDelay=195, Bit 14, Center 96 (7 ~ 186) 180
5493 11:05:21.944028 iDelay=195, Bit 15, Center 96 (7 ~ 186) 180
5494 11:05:21.944111 ==
5495 11:05:21.947263 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 11:05:21.950513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 11:05:21.950597 ==
5498 11:05:21.953996 DQS Delay:
5499 11:05:21.954079 DQS0 = 0, DQS1 = 0
5500 11:05:21.954144 DQM Delay:
5501 11:05:21.957059 DQM0 = 97, DQM1 = 89
5502 11:05:21.957145 DQ Delay:
5503 11:05:21.960470 DQ0 =94, DQ1 =100, DQ2 =94, DQ3 =94
5504 11:05:21.963785 DQ4 =100, DQ5 =86, DQ6 =108, DQ7 =104
5505 11:05:21.966695 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =84
5506 11:05:21.969945 DQ12 =94, DQ13 =96, DQ14 =96, DQ15 =96
5507 11:05:21.970053
5508 11:05:21.970156
5509 11:05:21.980392 [DQSOSCAuto] RK1, (LSB)MR18= 0x110d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5510 11:05:21.983137 CH0 RK1: MR19=505, MR18=110D
5511 11:05:21.989988 CH0_RK1: MR19=0x505, MR18=0x110D, DQSOSC=416, MR23=63, INC=62, DEC=41
5512 11:05:21.990099 [RxdqsGatingPostProcess] freq 933
5513 11:05:21.996400 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5514 11:05:21.999669 best DQS0 dly(2T, 0.5T) = (0, 10)
5515 11:05:22.003155 best DQS1 dly(2T, 0.5T) = (0, 11)
5516 11:05:22.006259 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5517 11:05:22.009326 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5518 11:05:22.012745 best DQS0 dly(2T, 0.5T) = (0, 10)
5519 11:05:22.015955 best DQS1 dly(2T, 0.5T) = (0, 11)
5520 11:05:22.019305 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5521 11:05:22.022553 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5522 11:05:22.025609 Pre-setting of DQS Precalculation
5523 11:05:22.029150 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5524 11:05:22.029234 ==
5525 11:05:22.032323 Dram Type= 6, Freq= 0, CH_1, rank 0
5526 11:05:22.039207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5527 11:05:22.039319 ==
5528 11:05:22.042277 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5529 11:05:22.049146 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5530 11:05:22.052222 [CA 0] Center 36 (6~67) winsize 62
5531 11:05:22.055648 [CA 1] Center 36 (6~67) winsize 62
5532 11:05:22.059660 [CA 2] Center 34 (4~65) winsize 62
5533 11:05:22.062239 [CA 3] Center 33 (3~64) winsize 62
5534 11:05:22.065875 [CA 4] Center 34 (4~64) winsize 61
5535 11:05:22.068499 [CA 5] Center 33 (3~64) winsize 62
5536 11:05:22.068576
5537 11:05:22.072246 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5538 11:05:22.072355
5539 11:05:22.075629 [CATrainingPosCal] consider 1 rank data
5540 11:05:22.078518 u2DelayCellTimex100 = 270/100 ps
5541 11:05:22.081576 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5542 11:05:22.088321 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5543 11:05:22.091530 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5544 11:05:22.094937 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5545 11:05:22.098105 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5546 11:05:22.101289 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5547 11:05:22.101376
5548 11:05:22.105057 CA PerBit enable=1, Macro0, CA PI delay=33
5549 11:05:22.105141
5550 11:05:22.107871 [CBTSetCACLKResult] CA Dly = 33
5551 11:05:22.111226 CS Dly: 4 (0~35)
5552 11:05:22.111334 ==
5553 11:05:22.114587 Dram Type= 6, Freq= 0, CH_1, rank 1
5554 11:05:22.118000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 11:05:22.118084 ==
5556 11:05:22.124351 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5557 11:05:22.127740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5558 11:05:22.132220 [CA 0] Center 36 (6~67) winsize 62
5559 11:05:22.135598 [CA 1] Center 36 (6~67) winsize 62
5560 11:05:22.138836 [CA 2] Center 34 (4~65) winsize 62
5561 11:05:22.141990 [CA 3] Center 33 (3~64) winsize 62
5562 11:05:22.145219 [CA 4] Center 33 (3~64) winsize 62
5563 11:05:22.148634 [CA 5] Center 33 (3~64) winsize 62
5564 11:05:22.148707
5565 11:05:22.151779 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5566 11:05:22.151865
5567 11:05:22.155137 [CATrainingPosCal] consider 2 rank data
5568 11:05:22.158618 u2DelayCellTimex100 = 270/100 ps
5569 11:05:22.161337 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5570 11:05:22.168187 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5571 11:05:22.171502 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5572 11:05:22.174697 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5573 11:05:22.177687 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5574 11:05:22.181336 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5575 11:05:22.181458
5576 11:05:22.185016 CA PerBit enable=1, Macro0, CA PI delay=33
5577 11:05:22.185139
5578 11:05:22.187674 [CBTSetCACLKResult] CA Dly = 33
5579 11:05:22.190776 CS Dly: 5 (0~37)
5580 11:05:22.190902
5581 11:05:22.194355 ----->DramcWriteLeveling(PI) begin...
5582 11:05:22.194481 ==
5583 11:05:22.197510 Dram Type= 6, Freq= 0, CH_1, rank 0
5584 11:05:22.200960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5585 11:05:22.201081 ==
5586 11:05:22.204350 Write leveling (Byte 0): 29 => 29
5587 11:05:22.207331 Write leveling (Byte 1): 30 => 30
5588 11:05:22.210718 DramcWriteLeveling(PI) end<-----
5589 11:05:22.210833
5590 11:05:22.210944 ==
5591 11:05:22.213864 Dram Type= 6, Freq= 0, CH_1, rank 0
5592 11:05:22.217085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 11:05:22.217206 ==
5594 11:05:22.220564 [Gating] SW mode calibration
5595 11:05:22.227061 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5596 11:05:22.233833 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5597 11:05:22.236929 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 11:05:22.243496 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 11:05:22.246752 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 11:05:22.249896 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 11:05:22.256557 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 11:05:22.260254 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 11:05:22.263285 0 14 24 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 0)
5604 11:05:22.269735 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5605 11:05:22.273274 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 11:05:22.276409 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 11:05:22.283258 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 11:05:22.286702 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 11:05:22.289448 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 11:05:22.296378 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 11:05:22.299879 0 15 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5612 11:05:22.302883 0 15 28 | B1->B0 | 3837 3d3d | 1 0 | (0 0) (0 0)
5613 11:05:22.309296 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 11:05:22.313200 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 11:05:22.316143 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 11:05:22.322706 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 11:05:22.326324 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 11:05:22.329343 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 11:05:22.336057 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 11:05:22.339368 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5621 11:05:22.342708 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 11:05:22.349089 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 11:05:22.352420 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 11:05:22.355859 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 11:05:22.362128 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 11:05:22.366088 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 11:05:22.369072 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 11:05:22.375788 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 11:05:22.378831 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 11:05:22.381931 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 11:05:22.388406 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 11:05:22.392374 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 11:05:22.394976 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 11:05:22.401713 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 11:05:22.404746 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5636 11:05:22.407984 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5637 11:05:22.414952 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 11:05:22.415083 Total UI for P1: 0, mck2ui 16
5639 11:05:22.421531 best dqsien dly found for B0: ( 1, 2, 28)
5640 11:05:22.421646 Total UI for P1: 0, mck2ui 16
5641 11:05:22.428048 best dqsien dly found for B1: ( 1, 2, 26)
5642 11:05:22.431095 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5643 11:05:22.434365 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5644 11:05:22.434480
5645 11:05:22.437818 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5646 11:05:22.441180 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5647 11:05:22.444413 [Gating] SW calibration Done
5648 11:05:22.444516 ==
5649 11:05:22.447552 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 11:05:22.450952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 11:05:22.451104 ==
5652 11:05:22.454189 RX Vref Scan: 0
5653 11:05:22.454346
5654 11:05:22.454462 RX Vref 0 -> 0, step: 1
5655 11:05:22.457531
5656 11:05:22.457657 RX Delay -80 -> 252, step: 8
5657 11:05:22.463832 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5658 11:05:22.467681 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5659 11:05:22.471159 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5660 11:05:22.474508 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5661 11:05:22.477196 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5662 11:05:22.480729 iDelay=208, Bit 5, Center 103 (8 ~ 199) 192
5663 11:05:22.487174 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5664 11:05:22.490919 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5665 11:05:22.493706 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5666 11:05:22.497250 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5667 11:05:22.500363 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5668 11:05:22.503555 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5669 11:05:22.510006 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5670 11:05:22.513796 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5671 11:05:22.516781 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5672 11:05:22.520534 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5673 11:05:22.520619 ==
5674 11:05:22.523398 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 11:05:22.529922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 11:05:22.530009 ==
5677 11:05:22.530076 DQS Delay:
5678 11:05:22.530138 DQS0 = 0, DQS1 = 0
5679 11:05:22.533167 DQM Delay:
5680 11:05:22.533251 DQM0 = 99, DQM1 = 96
5681 11:05:22.536819 DQ Delay:
5682 11:05:22.539868 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5683 11:05:22.543060 DQ4 =99, DQ5 =103, DQ6 =107, DQ7 =99
5684 11:05:22.546422 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5685 11:05:22.549743 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5686 11:05:22.549828
5687 11:05:22.549894
5688 11:05:22.549956 ==
5689 11:05:22.552856 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 11:05:22.556042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 11:05:22.556126 ==
5692 11:05:22.556192
5693 11:05:22.556253
5694 11:05:22.559959 TX Vref Scan disable
5695 11:05:22.562756 == TX Byte 0 ==
5696 11:05:22.566132 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5697 11:05:22.569445 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5698 11:05:22.572367 == TX Byte 1 ==
5699 11:05:22.575967 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5700 11:05:22.579341 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5701 11:05:22.579432 ==
5702 11:05:22.582265 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 11:05:22.588904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 11:05:22.588988 ==
5705 11:05:22.589054
5706 11:05:22.589114
5707 11:05:22.589172 TX Vref Scan disable
5708 11:05:22.593031 == TX Byte 0 ==
5709 11:05:22.596221 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5710 11:05:22.603149 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5711 11:05:22.603235 == TX Byte 1 ==
5712 11:05:22.606380 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5713 11:05:22.612635 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5714 11:05:22.612732
5715 11:05:22.612797 [DATLAT]
5716 11:05:22.612857 Freq=933, CH1 RK0
5717 11:05:22.612917
5718 11:05:22.615996 DATLAT Default: 0xd
5719 11:05:22.619435 0, 0xFFFF, sum = 0
5720 11:05:22.619520 1, 0xFFFF, sum = 0
5721 11:05:22.622533 2, 0xFFFF, sum = 0
5722 11:05:22.622616 3, 0xFFFF, sum = 0
5723 11:05:22.626203 4, 0xFFFF, sum = 0
5724 11:05:22.626286 5, 0xFFFF, sum = 0
5725 11:05:22.629089 6, 0xFFFF, sum = 0
5726 11:05:22.629172 7, 0xFFFF, sum = 0
5727 11:05:22.632463 8, 0xFFFF, sum = 0
5728 11:05:22.632545 9, 0xFFFF, sum = 0
5729 11:05:22.635722 10, 0x0, sum = 1
5730 11:05:22.635805 11, 0x0, sum = 2
5731 11:05:22.638879 12, 0x0, sum = 3
5732 11:05:22.638962 13, 0x0, sum = 4
5733 11:05:22.642526 best_step = 11
5734 11:05:22.642608
5735 11:05:22.642671 ==
5736 11:05:22.645916 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 11:05:22.648693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 11:05:22.648779 ==
5739 11:05:22.648844 RX Vref Scan: 1
5740 11:05:22.651978
5741 11:05:22.652092 RX Vref 0 -> 0, step: 1
5742 11:05:22.652226
5743 11:05:22.655559 RX Delay -53 -> 252, step: 4
5744 11:05:22.655642
5745 11:05:22.659157 Set Vref, RX VrefLevel [Byte0]: 51
5746 11:05:22.661929 [Byte1]: 51
5747 11:05:22.665403
5748 11:05:22.665518 Final RX Vref Byte 0 = 51 to rank0
5749 11:05:22.669205 Final RX Vref Byte 1 = 51 to rank0
5750 11:05:22.672353 Final RX Vref Byte 0 = 51 to rank1
5751 11:05:22.675477 Final RX Vref Byte 1 = 51 to rank1==
5752 11:05:22.679052 Dram Type= 6, Freq= 0, CH_1, rank 0
5753 11:05:22.685478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 11:05:22.685594 ==
5755 11:05:22.685660 DQS Delay:
5756 11:05:22.688310 DQS0 = 0, DQS1 = 0
5757 11:05:22.688392 DQM Delay:
5758 11:05:22.688457 DQM0 = 98, DQM1 = 94
5759 11:05:22.692057 DQ Delay:
5760 11:05:22.695703 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =100
5761 11:05:22.698148 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =90
5762 11:05:22.701954 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5763 11:05:22.704844 DQ12 =102, DQ13 =104, DQ14 =100, DQ15 =104
5764 11:05:22.704927
5765 11:05:22.704991
5766 11:05:22.711476 [DQSOSCAuto] RK0, (LSB)MR18= 0xa1a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5767 11:05:22.715225 CH1 RK0: MR19=505, MR18=A1A
5768 11:05:22.721505 CH1_RK0: MR19=0x505, MR18=0xA1A, DQSOSC=413, MR23=63, INC=63, DEC=42
5769 11:05:22.721589
5770 11:05:22.724775 ----->DramcWriteLeveling(PI) begin...
5771 11:05:22.724859 ==
5772 11:05:22.728168 Dram Type= 6, Freq= 0, CH_1, rank 1
5773 11:05:22.731522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 11:05:22.734689 ==
5775 11:05:22.734774 Write leveling (Byte 0): 23 => 23
5776 11:05:22.737686 Write leveling (Byte 1): 30 => 30
5777 11:05:22.740860 DramcWriteLeveling(PI) end<-----
5778 11:05:22.740945
5779 11:05:22.741011 ==
5780 11:05:22.744465 Dram Type= 6, Freq= 0, CH_1, rank 1
5781 11:05:22.751469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 11:05:22.751583 ==
5783 11:05:22.751648 [Gating] SW mode calibration
5784 11:05:22.761432 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5785 11:05:22.764569 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5786 11:05:22.771400 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 11:05:22.774610 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 11:05:22.777921 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 11:05:22.784336 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 11:05:22.787550 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5791 11:05:22.791042 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5792 11:05:22.797776 0 14 24 | B1->B0 | 3333 2c2c | 1 1 | (1 1) (1 0)
5793 11:05:22.800577 0 14 28 | B1->B0 | 2929 2323 | 1 0 | (1 0) (1 0)
5794 11:05:22.804129 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5795 11:05:22.810775 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 11:05:22.813670 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 11:05:22.817355 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 11:05:22.823871 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 11:05:22.826881 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5800 11:05:22.830333 0 15 24 | B1->B0 | 2a2a 3232 | 1 0 | (0 0) (1 1)
5801 11:05:22.837511 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5802 11:05:22.840374 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 11:05:22.843663 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 11:05:22.850449 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 11:05:22.853495 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 11:05:22.856734 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 11:05:22.863469 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 11:05:22.866376 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5809 11:05:22.870043 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5810 11:05:22.876725 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5811 11:05:22.879773 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 11:05:22.882975 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 11:05:22.889727 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 11:05:22.892669 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 11:05:22.896150 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 11:05:22.902689 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 11:05:22.906152 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 11:05:22.909397 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 11:05:22.916164 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 11:05:22.919265 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 11:05:22.922544 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 11:05:22.928673 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 11:05:22.932244 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 11:05:22.935503 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5825 11:05:22.942253 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5826 11:05:22.942340 Total UI for P1: 0, mck2ui 16
5827 11:05:22.948891 best dqsien dly found for B0: ( 1, 2, 24)
5828 11:05:22.952213 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 11:05:22.954956 Total UI for P1: 0, mck2ui 16
5830 11:05:22.958246 best dqsien dly found for B1: ( 1, 2, 28)
5831 11:05:22.961731 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5832 11:05:22.965057 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5833 11:05:22.965158
5834 11:05:22.968416 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5835 11:05:22.971427 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5836 11:05:22.974735 [Gating] SW calibration Done
5837 11:05:22.974817 ==
5838 11:05:22.978046 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 11:05:22.985082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 11:05:22.985167 ==
5841 11:05:22.985233 RX Vref Scan: 0
5842 11:05:22.985294
5843 11:05:22.988211 RX Vref 0 -> 0, step: 1
5844 11:05:22.988294
5845 11:05:22.991588 RX Delay -80 -> 252, step: 8
5846 11:05:22.994745 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5847 11:05:22.998285 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5848 11:05:23.001120 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5849 11:05:23.004789 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5850 11:05:23.011027 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5851 11:05:23.014382 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5852 11:05:23.017820 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5853 11:05:23.021539 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5854 11:05:23.024016 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5855 11:05:23.027911 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5856 11:05:23.034221 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5857 11:05:23.037670 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5858 11:05:23.040527 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5859 11:05:23.044449 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5860 11:05:23.047149 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5861 11:05:23.053725 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5862 11:05:23.053822 ==
5863 11:05:23.057134 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 11:05:23.060641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 11:05:23.060768 ==
5866 11:05:23.060884 DQS Delay:
5867 11:05:23.063753 DQS0 = 0, DQS1 = 0
5868 11:05:23.063872 DQM Delay:
5869 11:05:23.066690 DQM0 = 97, DQM1 = 94
5870 11:05:23.066839 DQ Delay:
5871 11:05:23.069965 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5872 11:05:23.073885 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5873 11:05:23.076401 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5874 11:05:23.079757 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5875 11:05:23.079844
5876 11:05:23.079910
5877 11:05:23.079971 ==
5878 11:05:23.083017 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 11:05:23.090013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 11:05:23.090097 ==
5881 11:05:23.090163
5882 11:05:23.090224
5883 11:05:23.090282 TX Vref Scan disable
5884 11:05:23.093508 == TX Byte 0 ==
5885 11:05:23.096363 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5886 11:05:23.102965 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5887 11:05:23.103048 == TX Byte 1 ==
5888 11:05:23.106738 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5889 11:05:23.112915 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5890 11:05:23.113041 ==
5891 11:05:23.116176 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 11:05:23.119260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 11:05:23.119414 ==
5894 11:05:23.119552
5895 11:05:23.119658
5896 11:05:23.122552 TX Vref Scan disable
5897 11:05:23.126114 == TX Byte 0 ==
5898 11:05:23.129398 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5899 11:05:23.133033 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5900 11:05:23.136081 == TX Byte 1 ==
5901 11:05:23.139345 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5902 11:05:23.142982 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5903 11:05:23.143063
5904 11:05:23.145753 [DATLAT]
5905 11:05:23.145872 Freq=933, CH1 RK1
5906 11:05:23.145937
5907 11:05:23.149392 DATLAT Default: 0xb
5908 11:05:23.149473 0, 0xFFFF, sum = 0
5909 11:05:23.152783 1, 0xFFFF, sum = 0
5910 11:05:23.152865 2, 0xFFFF, sum = 0
5911 11:05:23.155737 3, 0xFFFF, sum = 0
5912 11:05:23.155819 4, 0xFFFF, sum = 0
5913 11:05:23.159283 5, 0xFFFF, sum = 0
5914 11:05:23.159424 6, 0xFFFF, sum = 0
5915 11:05:23.162684 7, 0xFFFF, sum = 0
5916 11:05:23.162812 8, 0xFFFF, sum = 0
5917 11:05:23.165702 9, 0xFFFF, sum = 0
5918 11:05:23.165829 10, 0x0, sum = 1
5919 11:05:23.169087 11, 0x0, sum = 2
5920 11:05:23.169215 12, 0x0, sum = 3
5921 11:05:23.172319 13, 0x0, sum = 4
5922 11:05:23.172444 best_step = 11
5923 11:05:23.172557
5924 11:05:23.172661 ==
5925 11:05:23.175401 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 11:05:23.182233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 11:05:23.182356 ==
5928 11:05:23.182472 RX Vref Scan: 0
5929 11:05:23.182580
5930 11:05:23.185553 RX Vref 0 -> 0, step: 1
5931 11:05:23.185674
5932 11:05:23.188622 RX Delay -53 -> 252, step: 4
5933 11:05:23.192120 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5934 11:05:23.195254 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5935 11:05:23.201766 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5936 11:05:23.205345 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5937 11:05:23.208585 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5938 11:05:23.211657 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5939 11:05:23.215127 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5940 11:05:23.221996 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5941 11:05:23.225032 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5942 11:05:23.228096 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5943 11:05:23.231530 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5944 11:05:23.234503 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5945 11:05:23.241926 iDelay=199, Bit 12, Center 102 (15 ~ 190) 176
5946 11:05:23.244363 iDelay=199, Bit 13, Center 102 (11 ~ 194) 184
5947 11:05:23.247696 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5948 11:05:23.251062 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5949 11:05:23.251177 ==
5950 11:05:23.254467 Dram Type= 6, Freq= 0, CH_1, rank 1
5951 11:05:23.257803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5952 11:05:23.261032 ==
5953 11:05:23.261113 DQS Delay:
5954 11:05:23.261179 DQS0 = 0, DQS1 = 0
5955 11:05:23.264599 DQM Delay:
5956 11:05:23.264702 DQM0 = 97, DQM1 = 92
5957 11:05:23.267579 DQ Delay:
5958 11:05:23.270760 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =96
5959 11:05:23.273951 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
5960 11:05:23.277569 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =86
5961 11:05:23.280763 DQ12 =102, DQ13 =102, DQ14 =96, DQ15 =100
5962 11:05:23.280846
5963 11:05:23.280911
5964 11:05:23.287418 [DQSOSCAuto] RK1, (LSB)MR18= 0x81e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 419 ps
5965 11:05:23.290447 CH1 RK1: MR19=505, MR18=81E
5966 11:05:23.297322 CH1_RK1: MR19=0x505, MR18=0x81E, DQSOSC=412, MR23=63, INC=63, DEC=42
5967 11:05:23.300642 [RxdqsGatingPostProcess] freq 933
5968 11:05:23.303616 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5969 11:05:23.307273 best DQS0 dly(2T, 0.5T) = (0, 10)
5970 11:05:23.310339 best DQS1 dly(2T, 0.5T) = (0, 10)
5971 11:05:23.313487 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5972 11:05:23.317222 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5973 11:05:23.320179 best DQS0 dly(2T, 0.5T) = (0, 10)
5974 11:05:23.323239 best DQS1 dly(2T, 0.5T) = (0, 10)
5975 11:05:23.327036 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5976 11:05:23.330394 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5977 11:05:23.333858 Pre-setting of DQS Precalculation
5978 11:05:23.337163 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5979 11:05:23.346648 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5980 11:05:23.352993 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5981 11:05:23.353163
5982 11:05:23.353232
5983 11:05:23.356401 [Calibration Summary] 1866 Mbps
5984 11:05:23.356485 CH 0, Rank 0
5985 11:05:23.360007 SW Impedance : PASS
5986 11:05:23.362738 DUTY Scan : NO K
5987 11:05:23.362845 ZQ Calibration : PASS
5988 11:05:23.366423 Jitter Meter : NO K
5989 11:05:23.366534 CBT Training : PASS
5990 11:05:23.369769 Write leveling : PASS
5991 11:05:23.372828 RX DQS gating : PASS
5992 11:05:23.372960 RX DQ/DQS(RDDQC) : PASS
5993 11:05:23.376082 TX DQ/DQS : PASS
5994 11:05:23.379522 RX DATLAT : PASS
5995 11:05:23.379618 RX DQ/DQS(Engine): PASS
5996 11:05:23.382602 TX OE : NO K
5997 11:05:23.382685 All Pass.
5998 11:05:23.382751
5999 11:05:23.385924 CH 0, Rank 1
6000 11:05:23.386007 SW Impedance : PASS
6001 11:05:23.389167 DUTY Scan : NO K
6002 11:05:23.392592 ZQ Calibration : PASS
6003 11:05:23.392679 Jitter Meter : NO K
6004 11:05:23.396112 CBT Training : PASS
6005 11:05:23.399091 Write leveling : PASS
6006 11:05:23.399175 RX DQS gating : PASS
6007 11:05:23.402689 RX DQ/DQS(RDDQC) : PASS
6008 11:05:23.405861 TX DQ/DQS : PASS
6009 11:05:23.405945 RX DATLAT : PASS
6010 11:05:23.409132 RX DQ/DQS(Engine): PASS
6011 11:05:23.412661 TX OE : NO K
6012 11:05:23.412745 All Pass.
6013 11:05:23.412812
6014 11:05:23.412874 CH 1, Rank 0
6015 11:05:23.415858 SW Impedance : PASS
6016 11:05:23.418976 DUTY Scan : NO K
6017 11:05:23.419059 ZQ Calibration : PASS
6018 11:05:23.422715 Jitter Meter : NO K
6019 11:05:23.425686 CBT Training : PASS
6020 11:05:23.425797 Write leveling : PASS
6021 11:05:23.428937 RX DQS gating : PASS
6022 11:05:23.432126 RX DQ/DQS(RDDQC) : PASS
6023 11:05:23.432210 TX DQ/DQS : PASS
6024 11:05:23.435346 RX DATLAT : PASS
6025 11:05:23.438869 RX DQ/DQS(Engine): PASS
6026 11:05:23.438976 TX OE : NO K
6027 11:05:23.439072 All Pass.
6028 11:05:23.441856
6029 11:05:23.441940 CH 1, Rank 1
6030 11:05:23.445498 SW Impedance : PASS
6031 11:05:23.445582 DUTY Scan : NO K
6032 11:05:23.448778 ZQ Calibration : PASS
6033 11:05:23.451994 Jitter Meter : NO K
6034 11:05:23.452077 CBT Training : PASS
6035 11:05:23.455229 Write leveling : PASS
6036 11:05:23.455339 RX DQS gating : PASS
6037 11:05:23.458189 RX DQ/DQS(RDDQC) : PASS
6038 11:05:23.461994 TX DQ/DQS : PASS
6039 11:05:23.462078 RX DATLAT : PASS
6040 11:05:23.465233 RX DQ/DQS(Engine): PASS
6041 11:05:23.468333 TX OE : NO K
6042 11:05:23.468417 All Pass.
6043 11:05:23.468483
6044 11:05:23.471596 DramC Write-DBI off
6045 11:05:23.471679 PER_BANK_REFRESH: Hybrid Mode
6046 11:05:23.474878 TX_TRACKING: ON
6047 11:05:23.484906 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6048 11:05:23.488349 [FAST_K] Save calibration result to emmc
6049 11:05:23.491282 dramc_set_vcore_voltage set vcore to 650000
6050 11:05:23.494542 Read voltage for 400, 6
6051 11:05:23.494627 Vio18 = 0
6052 11:05:23.494693 Vcore = 650000
6053 11:05:23.498141 Vdram = 0
6054 11:05:23.498225 Vddq = 0
6055 11:05:23.498290 Vmddr = 0
6056 11:05:23.504480 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6057 11:05:23.507523 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6058 11:05:23.510860 MEM_TYPE=3, freq_sel=20
6059 11:05:23.514176 sv_algorithm_assistance_LP4_800
6060 11:05:23.517474 ============ PULL DRAM RESETB DOWN ============
6061 11:05:23.521152 ========== PULL DRAM RESETB DOWN end =========
6062 11:05:23.527278 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6063 11:05:23.530964 ===================================
6064 11:05:23.531051 LPDDR4 DRAM CONFIGURATION
6065 11:05:23.534290 ===================================
6066 11:05:23.537898 EX_ROW_EN[0] = 0x0
6067 11:05:23.540711 EX_ROW_EN[1] = 0x0
6068 11:05:23.540796 LP4Y_EN = 0x0
6069 11:05:23.543836 WORK_FSP = 0x0
6070 11:05:23.543948 WL = 0x2
6071 11:05:23.547039 RL = 0x2
6072 11:05:23.547124 BL = 0x2
6073 11:05:23.550380 RPST = 0x0
6074 11:05:23.550497 RD_PRE = 0x0
6075 11:05:23.553755 WR_PRE = 0x1
6076 11:05:23.553868 WR_PST = 0x0
6077 11:05:23.557355 DBI_WR = 0x0
6078 11:05:23.557462 DBI_RD = 0x0
6079 11:05:23.560362 OTF = 0x1
6080 11:05:23.563795 ===================================
6081 11:05:23.567157 ===================================
6082 11:05:23.567262 ANA top config
6083 11:05:23.570360 ===================================
6084 11:05:23.573634 DLL_ASYNC_EN = 0
6085 11:05:23.576959 ALL_SLAVE_EN = 1
6086 11:05:23.580121 NEW_RANK_MODE = 1
6087 11:05:23.580205 DLL_IDLE_MODE = 1
6088 11:05:23.583709 LP45_APHY_COMB_EN = 1
6089 11:05:23.586944 TX_ODT_DIS = 1
6090 11:05:23.590503 NEW_8X_MODE = 1
6091 11:05:23.593262 ===================================
6092 11:05:23.596587 ===================================
6093 11:05:23.600234 data_rate = 800
6094 11:05:23.603189 CKR = 1
6095 11:05:23.603273 DQ_P2S_RATIO = 4
6096 11:05:23.606704 ===================================
6097 11:05:23.609669 CA_P2S_RATIO = 4
6098 11:05:23.612788 DQ_CA_OPEN = 0
6099 11:05:23.616481 DQ_SEMI_OPEN = 1
6100 11:05:23.619502 CA_SEMI_OPEN = 1
6101 11:05:23.622943 CA_FULL_RATE = 0
6102 11:05:23.623027 DQ_CKDIV4_EN = 0
6103 11:05:23.626085 CA_CKDIV4_EN = 1
6104 11:05:23.629546 CA_PREDIV_EN = 0
6105 11:05:23.632886 PH8_DLY = 0
6106 11:05:23.635903 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6107 11:05:23.639186 DQ_AAMCK_DIV = 0
6108 11:05:23.639290 CA_AAMCK_DIV = 0
6109 11:05:23.642976 CA_ADMCK_DIV = 4
6110 11:05:23.646123 DQ_TRACK_CA_EN = 0
6111 11:05:23.649283 CA_PICK = 800
6112 11:05:23.652747 CA_MCKIO = 400
6113 11:05:23.655642 MCKIO_SEMI = 400
6114 11:05:23.659275 PLL_FREQ = 3016
6115 11:05:23.662229 DQ_UI_PI_RATIO = 32
6116 11:05:23.662313 CA_UI_PI_RATIO = 32
6117 11:05:23.665832 ===================================
6118 11:05:23.669044 ===================================
6119 11:05:23.672371 memory_type:LPDDR4
6120 11:05:23.675979 GP_NUM : 10
6121 11:05:23.676064 SRAM_EN : 1
6122 11:05:23.678901 MD32_EN : 0
6123 11:05:23.682355 ===================================
6124 11:05:23.685501 [ANA_INIT] >>>>>>>>>>>>>>
6125 11:05:23.688656 <<<<<< [CONFIGURE PHASE]: ANA_TX
6126 11:05:23.691933 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6127 11:05:23.695114 ===================================
6128 11:05:23.698555 data_rate = 800,PCW = 0X7400
6129 11:05:23.701595 ===================================
6130 11:05:23.705174 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6131 11:05:23.708346 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6132 11:05:23.721547 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6133 11:05:23.724733 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6134 11:05:23.727776 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6135 11:05:23.731258 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6136 11:05:23.734399 [ANA_INIT] flow start
6137 11:05:23.737907 [ANA_INIT] PLL >>>>>>>>
6138 11:05:23.738009 [ANA_INIT] PLL <<<<<<<<
6139 11:05:23.741126 [ANA_INIT] MIDPI >>>>>>>>
6140 11:05:23.744230 [ANA_INIT] MIDPI <<<<<<<<
6141 11:05:23.744353 [ANA_INIT] DLL >>>>>>>>
6142 11:05:23.747560 [ANA_INIT] flow end
6143 11:05:23.750970 ============ LP4 DIFF to SE enter ============
6144 11:05:23.754159 ============ LP4 DIFF to SE exit ============
6145 11:05:23.757846 [ANA_INIT] <<<<<<<<<<<<<
6146 11:05:23.761255 [Flow] Enable top DCM control >>>>>
6147 11:05:23.764063 [Flow] Enable top DCM control <<<<<
6148 11:05:23.767552 Enable DLL master slave shuffle
6149 11:05:23.773961 ==============================================================
6150 11:05:23.774044 Gating Mode config
6151 11:05:23.780632 ==============================================================
6152 11:05:23.783828 Config description:
6153 11:05:23.791018 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6154 11:05:23.797093 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6155 11:05:23.803812 SELPH_MODE 0: By rank 1: By Phase
6156 11:05:23.809947 ==============================================================
6157 11:05:23.813478 GAT_TRACK_EN = 0
6158 11:05:23.813555 RX_GATING_MODE = 2
6159 11:05:23.816592 RX_GATING_TRACK_MODE = 2
6160 11:05:23.820433 SELPH_MODE = 1
6161 11:05:23.823483 PICG_EARLY_EN = 1
6162 11:05:23.827023 VALID_LAT_VALUE = 1
6163 11:05:23.834188 ==============================================================
6164 11:05:23.836747 Enter into Gating configuration >>>>
6165 11:05:23.839772 Exit from Gating configuration <<<<
6166 11:05:23.843428 Enter into DVFS_PRE_config >>>>>
6167 11:05:23.852828 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6168 11:05:23.856656 Exit from DVFS_PRE_config <<<<<
6169 11:05:23.859562 Enter into PICG configuration >>>>
6170 11:05:23.862784 Exit from PICG configuration <<<<
6171 11:05:23.865985 [RX_INPUT] configuration >>>>>
6172 11:05:23.869318 [RX_INPUT] configuration <<<<<
6173 11:05:23.872592 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6174 11:05:23.879283 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6175 11:05:23.885971 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6176 11:05:23.892435 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6177 11:05:23.899200 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6178 11:05:23.902302 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6179 11:05:23.909447 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6180 11:05:23.912252 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6181 11:05:23.915499 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6182 11:05:23.918702 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6183 11:05:23.925509 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6184 11:05:23.928505 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6185 11:05:23.931664 ===================================
6186 11:05:23.935111 LPDDR4 DRAM CONFIGURATION
6187 11:05:23.938317 ===================================
6188 11:05:23.938402 EX_ROW_EN[0] = 0x0
6189 11:05:23.941824 EX_ROW_EN[1] = 0x0
6190 11:05:23.941922 LP4Y_EN = 0x0
6191 11:05:23.945234 WORK_FSP = 0x0
6192 11:05:23.945344 WL = 0x2
6193 11:05:23.948338 RL = 0x2
6194 11:05:23.951737 BL = 0x2
6195 11:05:23.951830 RPST = 0x0
6196 11:05:23.955149 RD_PRE = 0x0
6197 11:05:23.955254 WR_PRE = 0x1
6198 11:05:23.958109 WR_PST = 0x0
6199 11:05:23.958212 DBI_WR = 0x0
6200 11:05:23.961276 DBI_RD = 0x0
6201 11:05:23.961354 OTF = 0x1
6202 11:05:23.964680 ===================================
6203 11:05:23.968285 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6204 11:05:23.975131 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6205 11:05:23.978084 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6206 11:05:23.981266 ===================================
6207 11:05:23.984444 LPDDR4 DRAM CONFIGURATION
6208 11:05:23.988114 ===================================
6209 11:05:23.988190 EX_ROW_EN[0] = 0x10
6210 11:05:23.991037 EX_ROW_EN[1] = 0x0
6211 11:05:23.991142 LP4Y_EN = 0x0
6212 11:05:23.994473 WORK_FSP = 0x0
6213 11:05:23.997611 WL = 0x2
6214 11:05:23.997686 RL = 0x2
6215 11:05:24.001001 BL = 0x2
6216 11:05:24.001075 RPST = 0x0
6217 11:05:24.004361 RD_PRE = 0x0
6218 11:05:24.004468 WR_PRE = 0x1
6219 11:05:24.007665 WR_PST = 0x0
6220 11:05:24.007741 DBI_WR = 0x0
6221 11:05:24.010854 DBI_RD = 0x0
6222 11:05:24.010928 OTF = 0x1
6223 11:05:24.014233 ===================================
6224 11:05:24.020615 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6225 11:05:24.024976 nWR fixed to 30
6226 11:05:24.028244 [ModeRegInit_LP4] CH0 RK0
6227 11:05:24.028354 [ModeRegInit_LP4] CH0 RK1
6228 11:05:24.031375 [ModeRegInit_LP4] CH1 RK0
6229 11:05:24.035102 [ModeRegInit_LP4] CH1 RK1
6230 11:05:24.035210 match AC timing 19
6231 11:05:24.041574 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6232 11:05:24.044860 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6233 11:05:24.048144 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6234 11:05:24.054730 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6235 11:05:24.058194 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6236 11:05:24.058300 ==
6237 11:05:24.061141 Dram Type= 6, Freq= 0, CH_0, rank 0
6238 11:05:24.064895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6239 11:05:24.064973 ==
6240 11:05:24.071165 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6241 11:05:24.077718 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6242 11:05:24.081102 [CA 0] Center 36 (8~64) winsize 57
6243 11:05:24.084607 [CA 1] Center 36 (8~64) winsize 57
6244 11:05:24.087560 [CA 2] Center 36 (8~64) winsize 57
6245 11:05:24.091211 [CA 3] Center 36 (8~64) winsize 57
6246 11:05:24.094245 [CA 4] Center 36 (8~64) winsize 57
6247 11:05:24.097328 [CA 5] Center 36 (8~64) winsize 57
6248 11:05:24.097403
6249 11:05:24.100589 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6250 11:05:24.100692
6251 11:05:24.104334 [CATrainingPosCal] consider 1 rank data
6252 11:05:24.107338 u2DelayCellTimex100 = 270/100 ps
6253 11:05:24.110388 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 11:05:24.114301 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 11:05:24.117789 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 11:05:24.120530 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 11:05:24.124106 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 11:05:24.127433 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 11:05:24.127518
6260 11:05:24.130487 CA PerBit enable=1, Macro0, CA PI delay=36
6261 11:05:24.133958
6262 11:05:24.134067 [CBTSetCACLKResult] CA Dly = 36
6263 11:05:24.137152 CS Dly: 1 (0~32)
6264 11:05:24.137261 ==
6265 11:05:24.140253 Dram Type= 6, Freq= 0, CH_0, rank 1
6266 11:05:24.143814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 11:05:24.143902 ==
6268 11:05:24.150180 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6269 11:05:24.156992 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6270 11:05:24.160134 [CA 0] Center 36 (8~64) winsize 57
6271 11:05:24.163288 [CA 1] Center 36 (8~64) winsize 57
6272 11:05:24.167103 [CA 2] Center 36 (8~64) winsize 57
6273 11:05:24.167206 [CA 3] Center 36 (8~64) winsize 57
6274 11:05:24.169798 [CA 4] Center 36 (8~64) winsize 57
6275 11:05:24.173186 [CA 5] Center 36 (8~64) winsize 57
6276 11:05:24.173285
6277 11:05:24.180259 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6278 11:05:24.180373
6279 11:05:24.183350 [CATrainingPosCal] consider 2 rank data
6280 11:05:24.186425 u2DelayCellTimex100 = 270/100 ps
6281 11:05:24.189942 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 11:05:24.192964 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 11:05:24.196771 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 11:05:24.199909 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 11:05:24.203018 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 11:05:24.206290 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 11:05:24.206396
6288 11:05:24.209833 CA PerBit enable=1, Macro0, CA PI delay=36
6289 11:05:24.209934
6290 11:05:24.212742 [CBTSetCACLKResult] CA Dly = 36
6291 11:05:24.216087 CS Dly: 1 (0~32)
6292 11:05:24.216162
6293 11:05:24.219444 ----->DramcWriteLeveling(PI) begin...
6294 11:05:24.219554 ==
6295 11:05:24.222706 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 11:05:24.226028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 11:05:24.226138 ==
6298 11:05:24.229525 Write leveling (Byte 0): 40 => 8
6299 11:05:24.232981 Write leveling (Byte 1): 40 => 8
6300 11:05:24.236071 DramcWriteLeveling(PI) end<-----
6301 11:05:24.236160
6302 11:05:24.236254 ==
6303 11:05:24.239314 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 11:05:24.242244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 11:05:24.242344 ==
6306 11:05:24.245904 [Gating] SW mode calibration
6307 11:05:24.252443 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6308 11:05:24.258952 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6309 11:05:24.262006 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6310 11:05:24.268592 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6311 11:05:24.272202 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 11:05:24.275253 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6313 11:05:24.282309 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 11:05:24.284992 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 11:05:24.288724 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 11:05:24.294892 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6317 11:05:24.298195 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6318 11:05:24.301822 Total UI for P1: 0, mck2ui 16
6319 11:05:24.305026 best dqsien dly found for B0: ( 0, 14, 24)
6320 11:05:24.308119 Total UI for P1: 0, mck2ui 16
6321 11:05:24.311619 best dqsien dly found for B1: ( 0, 14, 24)
6322 11:05:24.314585 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6323 11:05:24.318535 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6324 11:05:24.318634
6325 11:05:24.321586 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6326 11:05:24.324575 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6327 11:05:24.328257 [Gating] SW calibration Done
6328 11:05:24.328332 ==
6329 11:05:24.331302 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 11:05:24.337790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 11:05:24.337893 ==
6332 11:05:24.337984 RX Vref Scan: 0
6333 11:05:24.338046
6334 11:05:24.341427 RX Vref 0 -> 0, step: 1
6335 11:05:24.341504
6336 11:05:24.344366 RX Delay -410 -> 252, step: 16
6337 11:05:24.347762 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6338 11:05:24.350960 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6339 11:05:24.357821 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6340 11:05:24.360827 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6341 11:05:24.363955 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6342 11:05:24.367614 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6343 11:05:24.374001 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6344 11:05:24.377587 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6345 11:05:24.380621 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6346 11:05:24.384162 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6347 11:05:24.390688 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6348 11:05:24.393773 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6349 11:05:24.397275 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6350 11:05:24.403608 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6351 11:05:24.406766 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6352 11:05:24.410140 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6353 11:05:24.410247 ==
6354 11:05:24.413324 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 11:05:24.416954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 11:05:24.420398 ==
6357 11:05:24.420485 DQS Delay:
6358 11:05:24.420548 DQS0 = 35, DQS1 = 51
6359 11:05:24.423533 DQM Delay:
6360 11:05:24.423604 DQM0 = 4, DQM1 = 10
6361 11:05:24.426976 DQ Delay:
6362 11:05:24.427072 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6363 11:05:24.430025 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6364 11:05:24.433253 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6365 11:05:24.436396 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6366 11:05:24.436468
6367 11:05:24.436540
6368 11:05:24.436605 ==
6369 11:05:24.439843 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 11:05:24.446432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 11:05:24.446534 ==
6372 11:05:24.446624
6373 11:05:24.446718
6374 11:05:24.450172 TX Vref Scan disable
6375 11:05:24.450269 == TX Byte 0 ==
6376 11:05:24.452884 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6377 11:05:24.459641 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6378 11:05:24.459719 == TX Byte 1 ==
6379 11:05:24.462716 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6380 11:05:24.469093 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6381 11:05:24.469219 ==
6382 11:05:24.472788 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 11:05:24.476051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 11:05:24.476136 ==
6385 11:05:24.476201
6386 11:05:24.476261
6387 11:05:24.479309 TX Vref Scan disable
6388 11:05:24.479419 == TX Byte 0 ==
6389 11:05:24.482441 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6390 11:05:24.489145 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6391 11:05:24.489224 == TX Byte 1 ==
6392 11:05:24.492344 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6393 11:05:24.498844 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6394 11:05:24.498969
6395 11:05:24.499075 [DATLAT]
6396 11:05:24.499184 Freq=400, CH0 RK0
6397 11:05:24.499272
6398 11:05:24.502451 DATLAT Default: 0xf
6399 11:05:24.505692 0, 0xFFFF, sum = 0
6400 11:05:24.505825 1, 0xFFFF, sum = 0
6401 11:05:24.509138 2, 0xFFFF, sum = 0
6402 11:05:24.509220 3, 0xFFFF, sum = 0
6403 11:05:24.512112 4, 0xFFFF, sum = 0
6404 11:05:24.512194 5, 0xFFFF, sum = 0
6405 11:05:24.515379 6, 0xFFFF, sum = 0
6406 11:05:24.515474 7, 0xFFFF, sum = 0
6407 11:05:24.518806 8, 0xFFFF, sum = 0
6408 11:05:24.518957 9, 0xFFFF, sum = 0
6409 11:05:24.521943 10, 0xFFFF, sum = 0
6410 11:05:24.522025 11, 0xFFFF, sum = 0
6411 11:05:24.525845 12, 0xFFFF, sum = 0
6412 11:05:24.525927 13, 0x0, sum = 1
6413 11:05:24.529177 14, 0x0, sum = 2
6414 11:05:24.529261 15, 0x0, sum = 3
6415 11:05:24.531939 16, 0x0, sum = 4
6416 11:05:24.532020 best_step = 14
6417 11:05:24.532083
6418 11:05:24.532142 ==
6419 11:05:24.535187 Dram Type= 6, Freq= 0, CH_0, rank 0
6420 11:05:24.541800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 11:05:24.541885 ==
6422 11:05:24.541952 RX Vref Scan: 1
6423 11:05:24.542013
6424 11:05:24.545652 RX Vref 0 -> 0, step: 1
6425 11:05:24.545734
6426 11:05:24.548373 RX Delay -343 -> 252, step: 8
6427 11:05:24.548471
6428 11:05:24.551932 Set Vref, RX VrefLevel [Byte0]: 54
6429 11:05:24.555307 [Byte1]: 59
6430 11:05:24.558135
6431 11:05:24.558217 Final RX Vref Byte 0 = 54 to rank0
6432 11:05:24.561546 Final RX Vref Byte 1 = 59 to rank0
6433 11:05:24.565052 Final RX Vref Byte 0 = 54 to rank1
6434 11:05:24.567994 Final RX Vref Byte 1 = 59 to rank1==
6435 11:05:24.571641 Dram Type= 6, Freq= 0, CH_0, rank 0
6436 11:05:24.577878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 11:05:24.577963 ==
6438 11:05:24.578028 DQS Delay:
6439 11:05:24.581349 DQS0 = 44, DQS1 = 60
6440 11:05:24.581458 DQM Delay:
6441 11:05:24.581552 DQM0 = 10, DQM1 = 17
6442 11:05:24.584631 DQ Delay:
6443 11:05:24.587911 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6444 11:05:24.590898 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6445 11:05:24.594734 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6446 11:05:24.597730 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6447 11:05:24.597846
6448 11:05:24.597941
6449 11:05:24.604083 [DQSOSCAuto] RK0, (LSB)MR18= 0x9689, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6450 11:05:24.607378 CH0 RK0: MR19=C0C, MR18=9689
6451 11:05:24.614051 CH0_RK0: MR19=0xC0C, MR18=0x9689, DQSOSC=391, MR23=63, INC=386, DEC=257
6452 11:05:24.614175 ==
6453 11:05:24.617221 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 11:05:24.620772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 11:05:24.620895 ==
6456 11:05:24.623964 [Gating] SW mode calibration
6457 11:05:24.630453 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6458 11:05:24.637079 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6459 11:05:24.640398 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6460 11:05:24.646875 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6461 11:05:24.650065 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 11:05:24.653590 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6463 11:05:24.660095 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 11:05:24.663648 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 11:05:24.666437 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 11:05:24.673406 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6467 11:05:24.676607 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6468 11:05:24.679787 Total UI for P1: 0, mck2ui 16
6469 11:05:24.682928 best dqsien dly found for B0: ( 0, 14, 24)
6470 11:05:24.686187 Total UI for P1: 0, mck2ui 16
6471 11:05:24.689360 best dqsien dly found for B1: ( 0, 14, 24)
6472 11:05:24.693215 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6473 11:05:24.696426 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6474 11:05:24.696537
6475 11:05:24.699606 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6476 11:05:24.702726 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6477 11:05:24.706581 [Gating] SW calibration Done
6478 11:05:24.706664 ==
6479 11:05:24.709481 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 11:05:24.713247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 11:05:24.715960 ==
6482 11:05:24.716040 RX Vref Scan: 0
6483 11:05:24.716104
6484 11:05:24.719550 RX Vref 0 -> 0, step: 1
6485 11:05:24.719672
6486 11:05:24.722918 RX Delay -410 -> 252, step: 16
6487 11:05:24.726166 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6488 11:05:24.729175 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6489 11:05:24.732615 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6490 11:05:24.739312 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6491 11:05:24.742421 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6492 11:05:24.746073 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6493 11:05:24.749009 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6494 11:05:24.755834 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6495 11:05:24.758645 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6496 11:05:24.762198 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6497 11:05:24.769488 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6498 11:05:24.772105 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6499 11:05:24.775594 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6500 11:05:24.778741 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6501 11:05:24.785061 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6502 11:05:24.788277 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6503 11:05:24.788360 ==
6504 11:05:24.791767 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 11:05:24.795213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 11:05:24.795293 ==
6507 11:05:24.798222 DQS Delay:
6508 11:05:24.798308 DQS0 = 35, DQS1 = 51
6509 11:05:24.801587 DQM Delay:
6510 11:05:24.801693 DQM0 = 9, DQM1 = 9
6511 11:05:24.801783 DQ Delay:
6512 11:05:24.805264 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6513 11:05:24.808264 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6514 11:05:24.811998 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6515 11:05:24.814869 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6516 11:05:24.814951
6517 11:05:24.815016
6518 11:05:24.815076 ==
6519 11:05:24.818008 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 11:05:24.821347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 11:05:24.824743 ==
6522 11:05:24.824824
6523 11:05:24.824888
6524 11:05:24.824948 TX Vref Scan disable
6525 11:05:24.827922 == TX Byte 0 ==
6526 11:05:24.831336 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6527 11:05:24.834308 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6528 11:05:24.837659 == TX Byte 1 ==
6529 11:05:24.841242 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6530 11:05:24.844270 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6531 11:05:24.844368 ==
6532 11:05:24.848000 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 11:05:24.854202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 11:05:24.854317 ==
6535 11:05:24.854381
6536 11:05:24.854441
6537 11:05:24.857781 TX Vref Scan disable
6538 11:05:24.857863 == TX Byte 0 ==
6539 11:05:24.861034 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6540 11:05:24.867767 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6541 11:05:24.867851 == TX Byte 1 ==
6542 11:05:24.870805 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6543 11:05:24.877565 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6544 11:05:24.877648
6545 11:05:24.877712 [DATLAT]
6546 11:05:24.877773 Freq=400, CH0 RK1
6547 11:05:24.877832
6548 11:05:24.880583 DATLAT Default: 0xe
6549 11:05:24.884050 0, 0xFFFF, sum = 0
6550 11:05:24.884133 1, 0xFFFF, sum = 0
6551 11:05:24.887000 2, 0xFFFF, sum = 0
6552 11:05:24.887128 3, 0xFFFF, sum = 0
6553 11:05:24.890524 4, 0xFFFF, sum = 0
6554 11:05:24.890622 5, 0xFFFF, sum = 0
6555 11:05:24.893663 6, 0xFFFF, sum = 0
6556 11:05:24.893749 7, 0xFFFF, sum = 0
6557 11:05:24.897208 8, 0xFFFF, sum = 0
6558 11:05:24.897292 9, 0xFFFF, sum = 0
6559 11:05:24.900386 10, 0xFFFF, sum = 0
6560 11:05:24.900470 11, 0xFFFF, sum = 0
6561 11:05:24.903816 12, 0xFFFF, sum = 0
6562 11:05:24.903964 13, 0x0, sum = 1
6563 11:05:24.906760 14, 0x0, sum = 2
6564 11:05:24.906878 15, 0x0, sum = 3
6565 11:05:24.910417 16, 0x0, sum = 4
6566 11:05:24.910559 best_step = 14
6567 11:05:24.910687
6568 11:05:24.910811 ==
6569 11:05:24.913539 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 11:05:24.920472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 11:05:24.920556 ==
6572 11:05:24.920623 RX Vref Scan: 0
6573 11:05:24.920697
6574 11:05:24.923674 RX Vref 0 -> 0, step: 1
6575 11:05:24.923759
6576 11:05:24.926878 RX Delay -343 -> 252, step: 8
6577 11:05:24.933327 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6578 11:05:24.936864 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6579 11:05:24.940363 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6580 11:05:24.943332 iDelay=217, Bit 3, Center -36 (-271 ~ 200) 472
6581 11:05:24.950145 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6582 11:05:24.953303 iDelay=217, Bit 5, Center -44 (-279 ~ 192) 472
6583 11:05:24.956765 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6584 11:05:24.959876 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6585 11:05:24.966661 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6586 11:05:24.970073 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6587 11:05:24.973013 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6588 11:05:24.976705 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6589 11:05:24.982691 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6590 11:05:24.986166 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6591 11:05:24.989591 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6592 11:05:24.996371 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6593 11:05:24.996457 ==
6594 11:05:24.999450 Dram Type= 6, Freq= 0, CH_0, rank 1
6595 11:05:25.002749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 11:05:25.002858 ==
6597 11:05:25.002959 DQS Delay:
6598 11:05:25.006277 DQS0 = 44, DQS1 = 60
6599 11:05:25.006382 DQM Delay:
6600 11:05:25.009428 DQM0 = 10, DQM1 = 16
6601 11:05:25.009512 DQ Delay:
6602 11:05:25.012337 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6603 11:05:25.015791 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6604 11:05:25.018924 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6605 11:05:25.022419 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6606 11:05:25.022527
6607 11:05:25.022617
6608 11:05:25.028961 [DQSOSCAuto] RK1, (LSB)MR18= 0x847c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6609 11:05:25.032605 CH0 RK1: MR19=C0C, MR18=847C
6610 11:05:25.039171 CH0_RK1: MR19=0xC0C, MR18=0x847C, DQSOSC=393, MR23=63, INC=382, DEC=254
6611 11:05:25.041979 [RxdqsGatingPostProcess] freq 400
6612 11:05:25.048496 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6613 11:05:25.052160 best DQS0 dly(2T, 0.5T) = (0, 10)
6614 11:05:25.055479 best DQS1 dly(2T, 0.5T) = (0, 10)
6615 11:05:25.058575 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6616 11:05:25.061820 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6617 11:05:25.061928 best DQS0 dly(2T, 0.5T) = (0, 10)
6618 11:05:25.065306 best DQS1 dly(2T, 0.5T) = (0, 10)
6619 11:05:25.068345 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6620 11:05:25.071899 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6621 11:05:25.074853 Pre-setting of DQS Precalculation
6622 11:05:25.081483 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6623 11:05:25.081570 ==
6624 11:05:25.085010 Dram Type= 6, Freq= 0, CH_1, rank 0
6625 11:05:25.088764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6626 11:05:25.088846 ==
6627 11:05:25.094994 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6628 11:05:25.101660 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6629 11:05:25.105060 [CA 0] Center 36 (8~64) winsize 57
6630 11:05:25.107947 [CA 1] Center 36 (8~64) winsize 57
6631 11:05:25.108081 [CA 2] Center 36 (8~64) winsize 57
6632 11:05:25.111157 [CA 3] Center 36 (8~64) winsize 57
6633 11:05:25.114475 [CA 4] Center 36 (8~64) winsize 57
6634 11:05:25.117767 [CA 5] Center 36 (8~64) winsize 57
6635 11:05:25.117865
6636 11:05:25.124484 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6637 11:05:25.124559
6638 11:05:25.127553 [CATrainingPosCal] consider 1 rank data
6639 11:05:25.131086 u2DelayCellTimex100 = 270/100 ps
6640 11:05:25.134212 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 11:05:25.137279 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 11:05:25.140828 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 11:05:25.144003 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 11:05:25.147385 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 11:05:25.150526 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 11:05:25.150608
6647 11:05:25.154387 CA PerBit enable=1, Macro0, CA PI delay=36
6648 11:05:25.154469
6649 11:05:25.157185 [CBTSetCACLKResult] CA Dly = 36
6650 11:05:25.160477 CS Dly: 1 (0~32)
6651 11:05:25.160590 ==
6652 11:05:25.163852 Dram Type= 6, Freq= 0, CH_1, rank 1
6653 11:05:25.167472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 11:05:25.167556 ==
6655 11:05:25.173858 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6656 11:05:25.180106 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6657 11:05:25.183539 [CA 0] Center 36 (8~64) winsize 57
6658 11:05:25.186786 [CA 1] Center 36 (8~64) winsize 57
6659 11:05:25.186871 [CA 2] Center 36 (8~64) winsize 57
6660 11:05:25.190195 [CA 3] Center 36 (8~64) winsize 57
6661 11:05:25.193354 [CA 4] Center 36 (8~64) winsize 57
6662 11:05:25.197334 [CA 5] Center 36 (8~64) winsize 57
6663 11:05:25.197419
6664 11:05:25.199989 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6665 11:05:25.203080
6666 11:05:25.206432 [CATrainingPosCal] consider 2 rank data
6667 11:05:25.210074 u2DelayCellTimex100 = 270/100 ps
6668 11:05:25.213086 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 11:05:25.216335 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 11:05:25.219546 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 11:05:25.223052 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 11:05:25.225941 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 11:05:25.229293 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 11:05:25.229374
6675 11:05:25.232919 CA PerBit enable=1, Macro0, CA PI delay=36
6676 11:05:25.233001
6677 11:05:25.236070 [CBTSetCACLKResult] CA Dly = 36
6678 11:05:25.239156 CS Dly: 1 (0~32)
6679 11:05:25.239245
6680 11:05:25.242594 ----->DramcWriteLeveling(PI) begin...
6681 11:05:25.242678 ==
6682 11:05:25.245663 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 11:05:25.249512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 11:05:25.249655 ==
6685 11:05:25.252217 Write leveling (Byte 0): 40 => 8
6686 11:05:25.255883 Write leveling (Byte 1): 40 => 8
6687 11:05:25.259157 DramcWriteLeveling(PI) end<-----
6688 11:05:25.259264
6689 11:05:25.259356 ==
6690 11:05:25.262341 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 11:05:25.266348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 11:05:25.266431 ==
6693 11:05:25.269059 [Gating] SW mode calibration
6694 11:05:25.275475 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6695 11:05:25.282146 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6696 11:05:25.285373 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6697 11:05:25.291932 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6698 11:05:25.295265 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 11:05:25.298886 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6700 11:05:25.305117 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 11:05:25.308282 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 11:05:25.311347 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 11:05:25.318285 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6704 11:05:25.321602 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6705 11:05:25.324930 Total UI for P1: 0, mck2ui 16
6706 11:05:25.327990 best dqsien dly found for B0: ( 0, 14, 24)
6707 11:05:25.331370 Total UI for P1: 0, mck2ui 16
6708 11:05:25.334463 best dqsien dly found for B1: ( 0, 14, 24)
6709 11:05:25.338111 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6710 11:05:25.341375 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6711 11:05:25.341464
6712 11:05:25.344661 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6713 11:05:25.348316 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6714 11:05:25.351078 [Gating] SW calibration Done
6715 11:05:25.351160 ==
6716 11:05:25.354204 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 11:05:25.360962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 11:05:25.361042 ==
6719 11:05:25.361106 RX Vref Scan: 0
6720 11:05:25.361166
6721 11:05:25.364272 RX Vref 0 -> 0, step: 1
6722 11:05:25.364347
6723 11:05:25.367168 RX Delay -410 -> 252, step: 16
6724 11:05:25.371035 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6725 11:05:25.374035 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6726 11:05:25.380531 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6727 11:05:25.383966 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6728 11:05:25.387414 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6729 11:05:25.390332 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6730 11:05:25.396818 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6731 11:05:25.400355 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6732 11:05:25.403386 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6733 11:05:25.406846 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6734 11:05:25.413326 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6735 11:05:25.416789 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6736 11:05:25.420268 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6737 11:05:25.426412 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6738 11:05:25.429556 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6739 11:05:25.432949 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6740 11:05:25.433033 ==
6741 11:05:25.436554 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 11:05:25.439769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 11:05:25.442972 ==
6744 11:05:25.443046 DQS Delay:
6745 11:05:25.443110 DQS0 = 43, DQS1 = 51
6746 11:05:25.446363 DQM Delay:
6747 11:05:25.446440 DQM0 = 13, DQM1 = 13
6748 11:05:25.449343 DQ Delay:
6749 11:05:25.449427 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6750 11:05:25.452729 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6751 11:05:25.456333 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6752 11:05:25.459420 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6753 11:05:25.459504
6754 11:05:25.459569
6755 11:05:25.462764 ==
6756 11:05:25.465660 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 11:05:25.469268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 11:05:25.469352 ==
6759 11:05:25.469419
6760 11:05:25.469480
6761 11:05:25.472336 TX Vref Scan disable
6762 11:05:25.472436 == TX Byte 0 ==
6763 11:05:25.476223 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6764 11:05:25.482404 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6765 11:05:25.482487 == TX Byte 1 ==
6766 11:05:25.485633 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6767 11:05:25.492710 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6768 11:05:25.492792 ==
6769 11:05:25.495691 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 11:05:25.498708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 11:05:25.498815 ==
6772 11:05:25.498916
6773 11:05:25.499010
6774 11:05:25.502263 TX Vref Scan disable
6775 11:05:25.502345 == TX Byte 0 ==
6776 11:05:25.505620 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6777 11:05:25.512172 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6778 11:05:25.512255 == TX Byte 1 ==
6779 11:05:25.515296 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6780 11:05:25.521847 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6781 11:05:25.521999
6782 11:05:25.522092 [DATLAT]
6783 11:05:25.525156 Freq=400, CH1 RK0
6784 11:05:25.525238
6785 11:05:25.525302 DATLAT Default: 0xf
6786 11:05:25.528917 0, 0xFFFF, sum = 0
6787 11:05:25.529000 1, 0xFFFF, sum = 0
6788 11:05:25.531853 2, 0xFFFF, sum = 0
6789 11:05:25.531940 3, 0xFFFF, sum = 0
6790 11:05:25.535484 4, 0xFFFF, sum = 0
6791 11:05:25.535566 5, 0xFFFF, sum = 0
6792 11:05:25.538641 6, 0xFFFF, sum = 0
6793 11:05:25.538764 7, 0xFFFF, sum = 0
6794 11:05:25.541554 8, 0xFFFF, sum = 0
6795 11:05:25.541636 9, 0xFFFF, sum = 0
6796 11:05:25.545160 10, 0xFFFF, sum = 0
6797 11:05:25.545269 11, 0xFFFF, sum = 0
6798 11:05:25.548331 12, 0xFFFF, sum = 0
6799 11:05:25.548440 13, 0x0, sum = 1
6800 11:05:25.551489 14, 0x0, sum = 2
6801 11:05:25.551571 15, 0x0, sum = 3
6802 11:05:25.555342 16, 0x0, sum = 4
6803 11:05:25.555494 best_step = 14
6804 11:05:25.555561
6805 11:05:25.555621 ==
6806 11:05:25.558181 Dram Type= 6, Freq= 0, CH_1, rank 0
6807 11:05:25.565285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 11:05:25.565370 ==
6809 11:05:25.565435 RX Vref Scan: 1
6810 11:05:25.565495
6811 11:05:25.568167 RX Vref 0 -> 0, step: 1
6812 11:05:25.568238
6813 11:05:25.571558 RX Delay -343 -> 252, step: 8
6814 11:05:25.571629
6815 11:05:25.574810 Set Vref, RX VrefLevel [Byte0]: 51
6816 11:05:25.578138 [Byte1]: 51
6817 11:05:25.581442
6818 11:05:25.581516 Final RX Vref Byte 0 = 51 to rank0
6819 11:05:25.584910 Final RX Vref Byte 1 = 51 to rank0
6820 11:05:25.588189 Final RX Vref Byte 0 = 51 to rank1
6821 11:05:25.591294 Final RX Vref Byte 1 = 51 to rank1==
6822 11:05:25.594383 Dram Type= 6, Freq= 0, CH_1, rank 0
6823 11:05:25.601015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 11:05:25.601115 ==
6825 11:05:25.601181 DQS Delay:
6826 11:05:25.604639 DQS0 = 44, DQS1 = 52
6827 11:05:25.604714 DQM Delay:
6828 11:05:25.604776 DQM0 = 11, DQM1 = 11
6829 11:05:25.608241 DQ Delay:
6830 11:05:25.611184 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6831 11:05:25.611256 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6832 11:05:25.614532 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6833 11:05:25.617532 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =16
6834 11:05:25.617608
6835 11:05:25.621147
6836 11:05:25.627760 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f86, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 397 ps
6837 11:05:25.631279 CH1 RK0: MR19=C0C, MR18=5F86
6838 11:05:25.637761 CH1_RK0: MR19=0xC0C, MR18=0x5F86, DQSOSC=393, MR23=63, INC=382, DEC=254
6839 11:05:25.637886 ==
6840 11:05:25.640993 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 11:05:25.643961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 11:05:25.644108 ==
6843 11:05:25.647265 [Gating] SW mode calibration
6844 11:05:25.654023 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6845 11:05:25.660251 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6846 11:05:25.663928 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6847 11:05:25.666896 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6848 11:05:25.673538 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 11:05:25.676720 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6850 11:05:25.680188 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 11:05:25.686609 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 11:05:25.690181 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 11:05:25.693429 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6854 11:05:25.700238 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6855 11:05:25.700324 Total UI for P1: 0, mck2ui 16
6856 11:05:25.707024 best dqsien dly found for B0: ( 0, 14, 24)
6857 11:05:25.707135 Total UI for P1: 0, mck2ui 16
6858 11:05:25.713109 best dqsien dly found for B1: ( 0, 14, 24)
6859 11:05:25.716564 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6860 11:05:25.719683 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6861 11:05:25.719813
6862 11:05:25.723235 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6863 11:05:25.726577 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6864 11:05:25.729563 [Gating] SW calibration Done
6865 11:05:25.729650 ==
6866 11:05:25.732860 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 11:05:25.736458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 11:05:25.736570 ==
6869 11:05:25.740152 RX Vref Scan: 0
6870 11:05:25.740238
6871 11:05:25.743241 RX Vref 0 -> 0, step: 1
6872 11:05:25.743327
6873 11:05:25.743423 RX Delay -410 -> 252, step: 16
6874 11:05:25.749455 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6875 11:05:25.752521 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6876 11:05:25.755778 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6877 11:05:25.759340 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6878 11:05:25.765865 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6879 11:05:25.769374 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6880 11:05:25.772541 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6881 11:05:25.778841 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6882 11:05:25.782584 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6883 11:05:25.785649 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6884 11:05:25.788942 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6885 11:05:25.795558 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6886 11:05:25.798688 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6887 11:05:25.802358 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6888 11:05:25.805541 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6889 11:05:25.812266 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6890 11:05:25.812372 ==
6891 11:05:25.815487 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 11:05:25.818853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 11:05:25.818961 ==
6894 11:05:25.819053 DQS Delay:
6895 11:05:25.822233 DQS0 = 43, DQS1 = 51
6896 11:05:25.822348 DQM Delay:
6897 11:05:25.825655 DQM0 = 9, DQM1 = 14
6898 11:05:25.825762 DQ Delay:
6899 11:05:25.828690 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6900 11:05:25.831860 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6901 11:05:25.835613 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6902 11:05:25.838298 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6903 11:05:25.838380
6904 11:05:25.838444
6905 11:05:25.838541 ==
6906 11:05:25.842174 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 11:05:25.844863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 11:05:25.844947 ==
6909 11:05:25.845012
6910 11:05:25.845073
6911 11:05:25.848493 TX Vref Scan disable
6912 11:05:25.851656 == TX Byte 0 ==
6913 11:05:25.854748 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6914 11:05:25.858585 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6915 11:05:25.861554 == TX Byte 1 ==
6916 11:05:25.864989 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6917 11:05:25.868265 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6918 11:05:25.868348 ==
6919 11:05:25.871619 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 11:05:25.878086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 11:05:25.878215 ==
6922 11:05:25.878329
6923 11:05:25.878442
6924 11:05:25.878551 TX Vref Scan disable
6925 11:05:25.881557 == TX Byte 0 ==
6926 11:05:25.884701 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6927 11:05:25.888038 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6928 11:05:25.891019 == TX Byte 1 ==
6929 11:05:25.894329 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6930 11:05:25.897658 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6931 11:05:25.897772
6932 11:05:25.901185 [DATLAT]
6933 11:05:25.901284 Freq=400, CH1 RK1
6934 11:05:25.901414
6935 11:05:25.904434 DATLAT Default: 0xe
6936 11:05:25.904550 0, 0xFFFF, sum = 0
6937 11:05:25.907747 1, 0xFFFF, sum = 0
6938 11:05:25.907849 2, 0xFFFF, sum = 0
6939 11:05:25.910824 3, 0xFFFF, sum = 0
6940 11:05:25.910908 4, 0xFFFF, sum = 0
6941 11:05:25.914144 5, 0xFFFF, sum = 0
6942 11:05:25.914228 6, 0xFFFF, sum = 0
6943 11:05:25.917510 7, 0xFFFF, sum = 0
6944 11:05:25.920551 8, 0xFFFF, sum = 0
6945 11:05:25.920659 9, 0xFFFF, sum = 0
6946 11:05:25.923959 10, 0xFFFF, sum = 0
6947 11:05:25.924065 11, 0xFFFF, sum = 0
6948 11:05:25.927087 12, 0xFFFF, sum = 0
6949 11:05:25.927211 13, 0x0, sum = 1
6950 11:05:25.930255 14, 0x0, sum = 2
6951 11:05:25.930390 15, 0x0, sum = 3
6952 11:05:25.933876 16, 0x0, sum = 4
6953 11:05:25.934008 best_step = 14
6954 11:05:25.934123
6955 11:05:25.934235 ==
6956 11:05:25.937109 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 11:05:25.940653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 11:05:25.943886 ==
6959 11:05:25.944008 RX Vref Scan: 0
6960 11:05:25.944122
6961 11:05:25.946956 RX Vref 0 -> 0, step: 1
6962 11:05:25.947079
6963 11:05:25.950136 RX Delay -343 -> 252, step: 8
6964 11:05:25.956889 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6965 11:05:25.960162 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6966 11:05:25.964100 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6967 11:05:25.966695 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6968 11:05:25.973217 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6969 11:05:25.976580 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6970 11:05:25.979920 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6971 11:05:25.983285 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6972 11:05:25.989450 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6973 11:05:25.993182 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6974 11:05:25.996517 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6975 11:05:25.999669 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6976 11:05:26.005981 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6977 11:05:26.009159 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6978 11:05:26.013098 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6979 11:05:26.019408 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6980 11:05:26.019515 ==
6981 11:05:26.022593 Dram Type= 6, Freq= 0, CH_1, rank 1
6982 11:05:26.025703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6983 11:05:26.025830 ==
6984 11:05:26.025942 DQS Delay:
6985 11:05:26.029260 DQS0 = 48, DQS1 = 52
6986 11:05:26.029365 DQM Delay:
6987 11:05:26.032272 DQM0 = 12, DQM1 = 11
6988 11:05:26.032376 DQ Delay:
6989 11:05:26.036232 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6990 11:05:26.039004 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
6991 11:05:26.042340 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6992 11:05:26.045671 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6993 11:05:26.045777
6994 11:05:26.045873
6995 11:05:26.052270 [DQSOSCAuto] RK1, (LSB)MR18= 0x70a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
6996 11:05:26.055749 CH1 RK1: MR19=C0C, MR18=70A9
6997 11:05:26.062119 CH1_RK1: MR19=0xC0C, MR18=0x70A9, DQSOSC=388, MR23=63, INC=392, DEC=261
6998 11:05:26.065127 [RxdqsGatingPostProcess] freq 400
6999 11:05:26.071822 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7000 11:05:26.075496 best DQS0 dly(2T, 0.5T) = (0, 10)
7001 11:05:26.078516 best DQS1 dly(2T, 0.5T) = (0, 10)
7002 11:05:26.081505 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7003 11:05:26.084917 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7004 11:05:26.085023 best DQS0 dly(2T, 0.5T) = (0, 10)
7005 11:05:26.088370 best DQS1 dly(2T, 0.5T) = (0, 10)
7006 11:05:26.091521 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7007 11:05:26.094909 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7008 11:05:26.098085 Pre-setting of DQS Precalculation
7009 11:05:26.104574 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7010 11:05:26.111349 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7011 11:05:26.117916 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7012 11:05:26.118046
7013 11:05:26.118162
7014 11:05:26.120996 [Calibration Summary] 800 Mbps
7015 11:05:26.124249 CH 0, Rank 0
7016 11:05:26.124333 SW Impedance : PASS
7017 11:05:26.127767 DUTY Scan : NO K
7018 11:05:26.130917 ZQ Calibration : PASS
7019 11:05:26.131022 Jitter Meter : NO K
7020 11:05:26.134315 CBT Training : PASS
7021 11:05:26.134418 Write leveling : PASS
7022 11:05:26.137667 RX DQS gating : PASS
7023 11:05:26.140753 RX DQ/DQS(RDDQC) : PASS
7024 11:05:26.140867 TX DQ/DQS : PASS
7025 11:05:26.143950 RX DATLAT : PASS
7026 11:05:26.147164 RX DQ/DQS(Engine): PASS
7027 11:05:26.147272 TX OE : NO K
7028 11:05:26.150511 All Pass.
7029 11:05:26.150596
7030 11:05:26.150662 CH 0, Rank 1
7031 11:05:26.154747 SW Impedance : PASS
7032 11:05:26.154838 DUTY Scan : NO K
7033 11:05:26.157293 ZQ Calibration : PASS
7034 11:05:26.160553 Jitter Meter : NO K
7035 11:05:26.160637 CBT Training : PASS
7036 11:05:26.163922 Write leveling : NO K
7037 11:05:26.167131 RX DQS gating : PASS
7038 11:05:26.167215 RX DQ/DQS(RDDQC) : PASS
7039 11:05:26.170352 TX DQ/DQS : PASS
7040 11:05:26.174196 RX DATLAT : PASS
7041 11:05:26.174281 RX DQ/DQS(Engine): PASS
7042 11:05:26.177091 TX OE : NO K
7043 11:05:26.177213 All Pass.
7044 11:05:26.177329
7045 11:05:26.180108 CH 1, Rank 0
7046 11:05:26.180242 SW Impedance : PASS
7047 11:05:26.184415 DUTY Scan : NO K
7048 11:05:26.186918 ZQ Calibration : PASS
7049 11:05:26.187039 Jitter Meter : NO K
7050 11:05:26.190137 CBT Training : PASS
7051 11:05:26.193490 Write leveling : PASS
7052 11:05:26.193613 RX DQS gating : PASS
7053 11:05:26.196760 RX DQ/DQS(RDDQC) : PASS
7054 11:05:26.200004 TX DQ/DQS : PASS
7055 11:05:26.200128 RX DATLAT : PASS
7056 11:05:26.203843 RX DQ/DQS(Engine): PASS
7057 11:05:26.206747 TX OE : NO K
7058 11:05:26.206890 All Pass.
7059 11:05:26.207018
7060 11:05:26.207129 CH 1, Rank 1
7061 11:05:26.210256 SW Impedance : PASS
7062 11:05:26.213216 DUTY Scan : NO K
7063 11:05:26.213334 ZQ Calibration : PASS
7064 11:05:26.216862 Jitter Meter : NO K
7065 11:05:26.219623 CBT Training : PASS
7066 11:05:26.219741 Write leveling : NO K
7067 11:05:26.223469 RX DQS gating : PASS
7068 11:05:26.223590 RX DQ/DQS(RDDQC) : PASS
7069 11:05:26.226356 TX DQ/DQS : PASS
7070 11:05:26.229749 RX DATLAT : PASS
7071 11:05:26.229889 RX DQ/DQS(Engine): PASS
7072 11:05:26.233088 TX OE : NO K
7073 11:05:26.233189 All Pass.
7074 11:05:26.233292
7075 11:05:26.236222 DramC Write-DBI off
7076 11:05:26.239599 PER_BANK_REFRESH: Hybrid Mode
7077 11:05:26.239707 TX_TRACKING: ON
7078 11:05:26.249264 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7079 11:05:26.252513 [FAST_K] Save calibration result to emmc
7080 11:05:26.256052 dramc_set_vcore_voltage set vcore to 725000
7081 11:05:26.258928 Read voltage for 1600, 0
7082 11:05:26.259030 Vio18 = 0
7083 11:05:26.262450 Vcore = 725000
7084 11:05:26.262549 Vdram = 0
7085 11:05:26.262641 Vddq = 0
7086 11:05:26.262777 Vmddr = 0
7087 11:05:26.269449 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7088 11:05:26.275508 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7089 11:05:26.275612 MEM_TYPE=3, freq_sel=13
7090 11:05:26.279020 sv_algorithm_assistance_LP4_3733
7091 11:05:26.285365 ============ PULL DRAM RESETB DOWN ============
7092 11:05:26.288677 ========== PULL DRAM RESETB DOWN end =========
7093 11:05:26.292314 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7094 11:05:26.295160 ===================================
7095 11:05:26.298878 LPDDR4 DRAM CONFIGURATION
7096 11:05:26.302119 ===================================
7097 11:05:26.302225 EX_ROW_EN[0] = 0x0
7098 11:05:26.305095 EX_ROW_EN[1] = 0x0
7099 11:05:26.308307 LP4Y_EN = 0x0
7100 11:05:26.308413 WORK_FSP = 0x1
7101 11:05:26.312117 WL = 0x5
7102 11:05:26.312223 RL = 0x5
7103 11:05:26.315142 BL = 0x2
7104 11:05:26.315247 RPST = 0x0
7105 11:05:26.318911 RD_PRE = 0x0
7106 11:05:26.319015 WR_PRE = 0x1
7107 11:05:26.322172 WR_PST = 0x1
7108 11:05:26.322279 DBI_WR = 0x0
7109 11:05:26.325400 DBI_RD = 0x0
7110 11:05:26.325485 OTF = 0x1
7111 11:05:26.328418 ===================================
7112 11:05:26.331468 ===================================
7113 11:05:26.334977 ANA top config
7114 11:05:26.338396 ===================================
7115 11:05:26.341402 DLL_ASYNC_EN = 0
7116 11:05:26.341494 ALL_SLAVE_EN = 0
7117 11:05:26.344885 NEW_RANK_MODE = 1
7118 11:05:26.347971 DLL_IDLE_MODE = 1
7119 11:05:26.350942 LP45_APHY_COMB_EN = 1
7120 11:05:26.351059 TX_ODT_DIS = 0
7121 11:05:26.354734 NEW_8X_MODE = 1
7122 11:05:26.357966 ===================================
7123 11:05:26.361375 ===================================
7124 11:05:26.364593 data_rate = 3200
7125 11:05:26.368192 CKR = 1
7126 11:05:26.370943 DQ_P2S_RATIO = 8
7127 11:05:26.374268 ===================================
7128 11:05:26.377761 CA_P2S_RATIO = 8
7129 11:05:26.377845 DQ_CA_OPEN = 0
7130 11:05:26.380894 DQ_SEMI_OPEN = 0
7131 11:05:26.384067 CA_SEMI_OPEN = 0
7132 11:05:26.387293 CA_FULL_RATE = 0
7133 11:05:26.390918 DQ_CKDIV4_EN = 0
7134 11:05:26.394067 CA_CKDIV4_EN = 0
7135 11:05:26.397553 CA_PREDIV_EN = 0
7136 11:05:26.397657 PH8_DLY = 12
7137 11:05:26.400900 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7138 11:05:26.403980 DQ_AAMCK_DIV = 4
7139 11:05:26.407354 CA_AAMCK_DIV = 4
7140 11:05:26.410540 CA_ADMCK_DIV = 4
7141 11:05:26.413548 DQ_TRACK_CA_EN = 0
7142 11:05:26.417355 CA_PICK = 1600
7143 11:05:26.417470 CA_MCKIO = 1600
7144 11:05:26.420255 MCKIO_SEMI = 0
7145 11:05:26.423453 PLL_FREQ = 3068
7146 11:05:26.427183 DQ_UI_PI_RATIO = 32
7147 11:05:26.430463 CA_UI_PI_RATIO = 0
7148 11:05:26.434258 ===================================
7149 11:05:26.436682 ===================================
7150 11:05:26.439926 memory_type:LPDDR4
7151 11:05:26.440055 GP_NUM : 10
7152 11:05:26.443597 SRAM_EN : 1
7153 11:05:26.443723 MD32_EN : 0
7154 11:05:26.446616 ===================================
7155 11:05:26.449795 [ANA_INIT] >>>>>>>>>>>>>>
7156 11:05:26.453280 <<<<<< [CONFIGURE PHASE]: ANA_TX
7157 11:05:26.456350 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7158 11:05:26.459813 ===================================
7159 11:05:26.463018 data_rate = 3200,PCW = 0X7600
7160 11:05:26.466129 ===================================
7161 11:05:26.469617 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7162 11:05:26.476379 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7163 11:05:26.479733 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7164 11:05:26.485995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7165 11:05:26.489525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7166 11:05:26.492657 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7167 11:05:26.496287 [ANA_INIT] flow start
7168 11:05:26.496369 [ANA_INIT] PLL >>>>>>>>
7169 11:05:26.499248 [ANA_INIT] PLL <<<<<<<<
7170 11:05:26.502371 [ANA_INIT] MIDPI >>>>>>>>
7171 11:05:26.502481 [ANA_INIT] MIDPI <<<<<<<<
7172 11:05:26.505859 [ANA_INIT] DLL >>>>>>>>
7173 11:05:26.508905 [ANA_INIT] DLL <<<<<<<<
7174 11:05:26.509010 [ANA_INIT] flow end
7175 11:05:26.515929 ============ LP4 DIFF to SE enter ============
7176 11:05:26.518829 ============ LP4 DIFF to SE exit ============
7177 11:05:26.521946 [ANA_INIT] <<<<<<<<<<<<<
7178 11:05:26.525476 [Flow] Enable top DCM control >>>>>
7179 11:05:26.528840 [Flow] Enable top DCM control <<<<<
7180 11:05:26.528961 Enable DLL master slave shuffle
7181 11:05:26.534904 ==============================================================
7182 11:05:26.538372 Gating Mode config
7183 11:05:26.541558 ==============================================================
7184 11:05:26.544976 Config description:
7185 11:05:26.554812 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7186 11:05:26.561912 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7187 11:05:26.564797 SELPH_MODE 0: By rank 1: By Phase
7188 11:05:26.571545 ==============================================================
7189 11:05:26.574694 GAT_TRACK_EN = 1
7190 11:05:26.578470 RX_GATING_MODE = 2
7191 11:05:26.581435 RX_GATING_TRACK_MODE = 2
7192 11:05:26.584808 SELPH_MODE = 1
7193 11:05:26.588175 PICG_EARLY_EN = 1
7194 11:05:26.588275 VALID_LAT_VALUE = 1
7195 11:05:26.594343 ==============================================================
7196 11:05:26.598174 Enter into Gating configuration >>>>
7197 11:05:26.600876 Exit from Gating configuration <<<<
7198 11:05:26.604290 Enter into DVFS_PRE_config >>>>>
7199 11:05:26.614362 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7200 11:05:26.617647 Exit from DVFS_PRE_config <<<<<
7201 11:05:26.621179 Enter into PICG configuration >>>>
7202 11:05:26.624055 Exit from PICG configuration <<<<
7203 11:05:26.627307 [RX_INPUT] configuration >>>>>
7204 11:05:26.630944 [RX_INPUT] configuration <<<<<
7205 11:05:26.637468 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7206 11:05:26.640890 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7207 11:05:26.646845 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7208 11:05:26.654027 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7209 11:05:26.660328 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7210 11:05:26.667150 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7211 11:05:26.670428 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7212 11:05:26.673435 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7213 11:05:26.676728 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7214 11:05:26.683048 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7215 11:05:26.686226 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7216 11:05:26.689781 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7217 11:05:26.693339 ===================================
7218 11:05:26.696288 LPDDR4 DRAM CONFIGURATION
7219 11:05:26.699535 ===================================
7220 11:05:26.703483 EX_ROW_EN[0] = 0x0
7221 11:05:26.703568 EX_ROW_EN[1] = 0x0
7222 11:05:26.705985 LP4Y_EN = 0x0
7223 11:05:26.706098 WORK_FSP = 0x1
7224 11:05:26.709654 WL = 0x5
7225 11:05:26.709739 RL = 0x5
7226 11:05:26.712808 BL = 0x2
7227 11:05:26.712894 RPST = 0x0
7228 11:05:26.715834 RD_PRE = 0x0
7229 11:05:26.715919 WR_PRE = 0x1
7230 11:05:26.719344 WR_PST = 0x1
7231 11:05:26.722578 DBI_WR = 0x0
7232 11:05:26.722663 DBI_RD = 0x0
7233 11:05:26.726233 OTF = 0x1
7234 11:05:26.729218 ===================================
7235 11:05:26.732550 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7236 11:05:26.736203 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7237 11:05:26.738958 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7238 11:05:26.742212 ===================================
7239 11:05:26.745876 LPDDR4 DRAM CONFIGURATION
7240 11:05:26.749334 ===================================
7241 11:05:26.752559 EX_ROW_EN[0] = 0x10
7242 11:05:26.752658 EX_ROW_EN[1] = 0x0
7243 11:05:26.756291 LP4Y_EN = 0x0
7244 11:05:26.756380 WORK_FSP = 0x1
7245 11:05:26.758635 WL = 0x5
7246 11:05:26.758721 RL = 0x5
7247 11:05:26.762018 BL = 0x2
7248 11:05:26.765621 RPST = 0x0
7249 11:05:26.765750 RD_PRE = 0x0
7250 11:05:26.768760 WR_PRE = 0x1
7251 11:05:26.768849 WR_PST = 0x1
7252 11:05:26.771747 DBI_WR = 0x0
7253 11:05:26.771870 DBI_RD = 0x0
7254 11:05:26.775108 OTF = 0x1
7255 11:05:26.778760 ===================================
7256 11:05:26.785022 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7257 11:05:26.785155 ==
7258 11:05:26.788186 Dram Type= 6, Freq= 0, CH_0, rank 0
7259 11:05:26.791366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7260 11:05:26.791484 ==
7261 11:05:26.795018 [Duty_Offset_Calibration]
7262 11:05:26.795127 B0:2 B1:0 CA:4
7263 11:05:26.795220
7264 11:05:26.798193 [DutyScan_Calibration_Flow] k_type=0
7265 11:05:26.808085
7266 11:05:26.808175 ==CLK 0==
7267 11:05:26.810963 Final CLK duty delay cell = -4
7268 11:05:26.814381 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7269 11:05:26.817380 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7270 11:05:26.821263 [-4] AVG Duty = 4922%(X100)
7271 11:05:26.821350
7272 11:05:26.824637 CH0 CLK Duty spec in!! Max-Min= 218%
7273 11:05:26.827394 [DutyScan_Calibration_Flow] ====Done====
7274 11:05:26.827477
7275 11:05:26.830606 [DutyScan_Calibration_Flow] k_type=1
7276 11:05:26.847926
7277 11:05:26.848011 ==DQS 0 ==
7278 11:05:26.851410 Final DQS duty delay cell = 0
7279 11:05:26.854585 [0] MAX Duty = 5218%(X100), DQS PI = 38
7280 11:05:26.857955 [0] MIN Duty = 5093%(X100), DQS PI = 8
7281 11:05:26.861357 [0] AVG Duty = 5155%(X100)
7282 11:05:26.861441
7283 11:05:26.861506 ==DQS 1 ==
7284 11:05:26.864364 Final DQS duty delay cell = 0
7285 11:05:26.867655 [0] MAX Duty = 5187%(X100), DQS PI = 2
7286 11:05:26.871159 [0] MIN Duty = 4969%(X100), DQS PI = 10
7287 11:05:26.874278 [0] AVG Duty = 5078%(X100)
7288 11:05:26.874361
7289 11:05:26.877592 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7290 11:05:26.877676
7291 11:05:26.880751 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7292 11:05:26.884077 [DutyScan_Calibration_Flow] ====Done====
7293 11:05:26.884191
7294 11:05:26.887799 [DutyScan_Calibration_Flow] k_type=3
7295 11:05:26.904974
7296 11:05:26.905056 ==DQM 0 ==
7297 11:05:26.908385 Final DQM duty delay cell = 0
7298 11:05:26.911904 [0] MAX Duty = 5124%(X100), DQS PI = 20
7299 11:05:26.915130 [0] MIN Duty = 4844%(X100), DQS PI = 54
7300 11:05:26.918188 [0] AVG Duty = 4984%(X100)
7301 11:05:26.918310
7302 11:05:26.918423 ==DQM 1 ==
7303 11:05:26.921111 Final DQM duty delay cell = 0
7304 11:05:26.925070 [0] MAX Duty = 5000%(X100), DQS PI = 4
7305 11:05:26.927902 [0] MIN Duty = 4844%(X100), DQS PI = 18
7306 11:05:26.931263 [0] AVG Duty = 4922%(X100)
7307 11:05:26.931406
7308 11:05:26.934242 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7309 11:05:26.934363
7310 11:05:26.937543 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7311 11:05:26.941079 [DutyScan_Calibration_Flow] ====Done====
7312 11:05:26.941182
7313 11:05:26.944160 [DutyScan_Calibration_Flow] k_type=2
7314 11:05:26.962202
7315 11:05:26.962339 ==DQ 0 ==
7316 11:05:26.965324 Final DQ duty delay cell = 0
7317 11:05:26.968623 [0] MAX Duty = 5156%(X100), DQS PI = 22
7318 11:05:26.971965 [0] MIN Duty = 4969%(X100), DQS PI = 10
7319 11:05:26.972088 [0] AVG Duty = 5062%(X100)
7320 11:05:26.975678
7321 11:05:26.975807 ==DQ 1 ==
7322 11:05:26.979213 Final DQ duty delay cell = 0
7323 11:05:26.981957 [0] MAX Duty = 5187%(X100), DQS PI = 2
7324 11:05:26.984825 [0] MIN Duty = 4938%(X100), DQS PI = 14
7325 11:05:26.984926 [0] AVG Duty = 5062%(X100)
7326 11:05:26.988167
7327 11:05:26.991714 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7328 11:05:26.991798
7329 11:05:26.995206 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7330 11:05:26.997977 [DutyScan_Calibration_Flow] ====Done====
7331 11:05:26.998061 ==
7332 11:05:27.001649 Dram Type= 6, Freq= 0, CH_1, rank 0
7333 11:05:27.005040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7334 11:05:27.005131 ==
7335 11:05:27.008229 [Duty_Offset_Calibration]
7336 11:05:27.008313 B0:0 B1:-1 CA:3
7337 11:05:27.008378
7338 11:05:27.011338 [DutyScan_Calibration_Flow] k_type=0
7339 11:05:27.021451
7340 11:05:27.021535 ==CLK 0==
7341 11:05:27.025157 Final CLK duty delay cell = -4
7342 11:05:27.028112 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7343 11:05:27.031280 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7344 11:05:27.034529 [-4] AVG Duty = 4922%(X100)
7345 11:05:27.034612
7346 11:05:27.038301 CH1 CLK Duty spec in!! Max-Min= 156%
7347 11:05:27.041323 [DutyScan_Calibration_Flow] ====Done====
7348 11:05:27.041407
7349 11:05:27.044385 [DutyScan_Calibration_Flow] k_type=1
7350 11:05:27.060520
7351 11:05:27.060660 ==DQS 0 ==
7352 11:05:27.064041 Final DQS duty delay cell = 0
7353 11:05:27.067288 [0] MAX Duty = 5250%(X100), DQS PI = 30
7354 11:05:27.070500 [0] MIN Duty = 4907%(X100), DQS PI = 56
7355 11:05:27.074000 [0] AVG Duty = 5078%(X100)
7356 11:05:27.074123
7357 11:05:27.074238 ==DQS 1 ==
7358 11:05:27.076919 Final DQS duty delay cell = -4
7359 11:05:27.080374 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7360 11:05:27.083684 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7361 11:05:27.087105 [-4] AVG Duty = 4906%(X100)
7362 11:05:27.087228
7363 11:05:27.090147 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7364 11:05:27.090271
7365 11:05:27.093401 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7366 11:05:27.096676 [DutyScan_Calibration_Flow] ====Done====
7367 11:05:27.096797
7368 11:05:27.099901 [DutyScan_Calibration_Flow] k_type=3
7369 11:05:27.117845
7370 11:05:27.117971 ==DQM 0 ==
7371 11:05:27.120923 Final DQM duty delay cell = 0
7372 11:05:27.124251 [0] MAX Duty = 5062%(X100), DQS PI = 30
7373 11:05:27.128183 [0] MIN Duty = 4750%(X100), DQS PI = 40
7374 11:05:27.131015 [0] AVG Duty = 4906%(X100)
7375 11:05:27.131132
7376 11:05:27.131241 ==DQM 1 ==
7377 11:05:27.134322 Final DQM duty delay cell = 0
7378 11:05:27.137552 [0] MAX Duty = 5000%(X100), DQS PI = 30
7379 11:05:27.140678 [0] MIN Duty = 4813%(X100), DQS PI = 0
7380 11:05:27.144171 [0] AVG Duty = 4906%(X100)
7381 11:05:27.144329
7382 11:05:27.147941 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7383 11:05:27.148059
7384 11:05:27.151134 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7385 11:05:27.154025 [DutyScan_Calibration_Flow] ====Done====
7386 11:05:27.154176
7387 11:05:27.157281 [DutyScan_Calibration_Flow] k_type=2
7388 11:05:27.173958
7389 11:05:27.174089 ==DQ 0 ==
7390 11:05:27.177196 Final DQ duty delay cell = -4
7391 11:05:27.180705 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7392 11:05:27.183869 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7393 11:05:27.187549 [-4] AVG Duty = 4891%(X100)
7394 11:05:27.187671
7395 11:05:27.187782 ==DQ 1 ==
7396 11:05:27.190712 Final DQ duty delay cell = 0
7397 11:05:27.193829 [0] MAX Duty = 5062%(X100), DQS PI = 32
7398 11:05:27.197207 [0] MIN Duty = 4875%(X100), DQS PI = 0
7399 11:05:27.200179 [0] AVG Duty = 4968%(X100)
7400 11:05:27.200260
7401 11:05:27.203728 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7402 11:05:27.203809
7403 11:05:27.206666 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7404 11:05:27.209948 [DutyScan_Calibration_Flow] ====Done====
7405 11:05:27.213483 nWR fixed to 30
7406 11:05:27.216791 [ModeRegInit_LP4] CH0 RK0
7407 11:05:27.216911 [ModeRegInit_LP4] CH0 RK1
7408 11:05:27.219932 [ModeRegInit_LP4] CH1 RK0
7409 11:05:27.223564 [ModeRegInit_LP4] CH1 RK1
7410 11:05:27.223645 match AC timing 5
7411 11:05:27.230003 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7412 11:05:27.233349 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7413 11:05:27.236750 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7414 11:05:27.242915 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7415 11:05:27.246688 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7416 11:05:27.249785 [MiockJmeterHQA]
7417 11:05:27.249865
7418 11:05:27.252779 [DramcMiockJmeter] u1RxGatingPI = 0
7419 11:05:27.252898 0 : 4252, 4027
7420 11:05:27.252964 4 : 4252, 4027
7421 11:05:27.256118 8 : 4363, 4138
7422 11:05:27.256192 12 : 4252, 4027
7423 11:05:27.259488 16 : 4363, 4137
7424 11:05:27.259588 20 : 4252, 4027
7425 11:05:27.262764 24 : 4361, 4138
7426 11:05:27.262846 28 : 4253, 4026
7427 11:05:27.262910 32 : 4250, 4027
7428 11:05:27.266292 36 : 4250, 4027
7429 11:05:27.266374 40 : 4361, 4137
7430 11:05:27.269684 44 : 4361, 4138
7431 11:05:27.269809 48 : 4250, 4026
7432 11:05:27.272720 52 : 4250, 4027
7433 11:05:27.272801 56 : 4250, 4027
7434 11:05:27.276303 60 : 4250, 4027
7435 11:05:27.276384 64 : 4252, 4029
7436 11:05:27.276449 68 : 4360, 4137
7437 11:05:27.279312 72 : 4250, 4027
7438 11:05:27.279418 76 : 4252, 4027
7439 11:05:27.282767 80 : 4250, 4026
7440 11:05:27.282851 84 : 4252, 4030
7441 11:05:27.286121 88 : 4250, 4027
7442 11:05:27.286218 92 : 4361, 4137
7443 11:05:27.289060 96 : 4361, 2752
7444 11:05:27.289174 100 : 4250, 0
7445 11:05:27.289270 104 : 4250, 0
7446 11:05:27.292449 108 : 4252, 0
7447 11:05:27.292532 112 : 4250, 0
7448 11:05:27.295808 116 : 4250, 0
7449 11:05:27.295892 120 : 4253, 0
7450 11:05:27.295958 124 : 4250, 0
7451 11:05:27.299333 128 : 4250, 0
7452 11:05:27.299432 132 : 4250, 0
7453 11:05:27.299499 136 : 4361, 0
7454 11:05:27.302339 140 : 4360, 0
7455 11:05:27.302469 144 : 4250, 0
7456 11:05:27.306044 148 : 4250, 0
7457 11:05:27.306171 152 : 4250, 0
7458 11:05:27.306287 156 : 4250, 0
7459 11:05:27.309043 160 : 4250, 0
7460 11:05:27.309170 164 : 4250, 0
7461 11:05:27.312372 168 : 4361, 0
7462 11:05:27.312480 172 : 4250, 0
7463 11:05:27.312575 176 : 4250, 0
7464 11:05:27.315746 180 : 4250, 0
7465 11:05:27.315839 184 : 4252, 0
7466 11:05:27.318920 188 : 4361, 0
7467 11:05:27.319031 192 : 4360, 0
7468 11:05:27.319127 196 : 4363, 0
7469 11:05:27.322309 200 : 4250, 0
7470 11:05:27.322412 204 : 4250, 0
7471 11:05:27.325133 208 : 4250, 0
7472 11:05:27.325244 212 : 4250, 0
7473 11:05:27.325340 216 : 4250, 0
7474 11:05:27.328827 220 : 4361, 1120
7475 11:05:27.328934 224 : 4250, 4021
7476 11:05:27.332416 228 : 4363, 4140
7477 11:05:27.332501 232 : 4250, 4027
7478 11:05:27.335173 236 : 4361, 4138
7479 11:05:27.335257 240 : 4360, 4137
7480 11:05:27.338979 244 : 4250, 4026
7481 11:05:27.339063 248 : 4250, 4027
7482 11:05:27.342054 252 : 4363, 4139
7483 11:05:27.342139 256 : 4250, 4027
7484 11:05:27.345196 260 : 4250, 4027
7485 11:05:27.345294 264 : 4250, 4027
7486 11:05:27.345376 268 : 4252, 4029
7487 11:05:27.348505 272 : 4250, 4027
7488 11:05:27.348589 276 : 4250, 4026
7489 11:05:27.351695 280 : 4361, 4137
7490 11:05:27.351780 284 : 4250, 4027
7491 11:05:27.354822 288 : 4250, 4027
7492 11:05:27.354906 292 : 4360, 4138
7493 11:05:27.358250 296 : 4250, 4027
7494 11:05:27.358335 300 : 4250, 4027
7495 11:05:27.361603 304 : 4363, 4139
7496 11:05:27.361688 308 : 4250, 4027
7497 11:05:27.365204 312 : 4250, 4027
7498 11:05:27.365336 316 : 4250, 4027
7499 11:05:27.368384 320 : 4253, 4030
7500 11:05:27.368512 324 : 4250, 4027
7501 11:05:27.371248 328 : 4250, 4027
7502 11:05:27.371381 332 : 4363, 3854
7503 11:05:27.374668 336 : 4250, 1414
7504 11:05:27.374795
7505 11:05:27.374910 MIOCK jitter meter ch=0
7506 11:05:27.375018
7507 11:05:27.378010 1T = (336-100) = 236 dly cells
7508 11:05:27.384981 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7509 11:05:27.385115 ==
7510 11:05:27.388027 Dram Type= 6, Freq= 0, CH_0, rank 0
7511 11:05:27.391151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7512 11:05:27.391280 ==
7513 11:05:27.397739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7514 11:05:27.400936 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7515 11:05:27.404466 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7516 11:05:27.410805 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7517 11:05:27.421034 [CA 0] Center 43 (13~74) winsize 62
7518 11:05:27.423824 [CA 1] Center 43 (13~73) winsize 61
7519 11:05:27.427210 [CA 2] Center 39 (10~68) winsize 59
7520 11:05:27.430356 [CA 3] Center 38 (9~67) winsize 59
7521 11:05:27.433499 [CA 4] Center 36 (7~66) winsize 60
7522 11:05:27.437075 [CA 5] Center 36 (6~66) winsize 61
7523 11:05:27.437165
7524 11:05:27.440572 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7525 11:05:27.440670
7526 11:05:27.446656 [CATrainingPosCal] consider 1 rank data
7527 11:05:27.446759 u2DelayCellTimex100 = 275/100 ps
7528 11:05:27.453206 CA0 delay=43 (13~74),Diff = 7 PI (24 cell)
7529 11:05:27.457095 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7530 11:05:27.460007 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7531 11:05:27.463682 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7532 11:05:27.466440 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7533 11:05:27.469808 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7534 11:05:27.469914
7535 11:05:27.472982 CA PerBit enable=1, Macro0, CA PI delay=36
7536 11:05:27.476192
7537 11:05:27.476265 [CBTSetCACLKResult] CA Dly = 36
7538 11:05:27.479271 CS Dly: 11 (0~42)
7539 11:05:27.482678 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7540 11:05:27.486269 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7541 11:05:27.489634 ==
7542 11:05:27.492640 Dram Type= 6, Freq= 0, CH_0, rank 1
7543 11:05:27.495730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7544 11:05:27.495853 ==
7545 11:05:27.503050 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7546 11:05:27.505967 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7547 11:05:27.509335 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7548 11:05:27.515717 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7549 11:05:27.524334 [CA 0] Center 44 (14~75) winsize 62
7550 11:05:27.527503 [CA 1] Center 44 (14~74) winsize 61
7551 11:05:27.531116 [CA 2] Center 39 (10~69) winsize 60
7552 11:05:27.534384 [CA 3] Center 39 (10~68) winsize 59
7553 11:05:27.537387 [CA 4] Center 37 (7~67) winsize 61
7554 11:05:27.540664 [CA 5] Center 36 (7~66) winsize 60
7555 11:05:27.540746
7556 11:05:27.544320 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7557 11:05:27.544402
7558 11:05:27.551583 [CATrainingPosCal] consider 2 rank data
7559 11:05:27.551664 u2DelayCellTimex100 = 275/100 ps
7560 11:05:27.557795 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7561 11:05:27.560370 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7562 11:05:27.563784 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7563 11:05:27.567354 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7564 11:05:27.570151 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7565 11:05:27.573866 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7566 11:05:27.573947
7567 11:05:27.576822 CA PerBit enable=1, Macro0, CA PI delay=36
7568 11:05:27.576904
7569 11:05:27.580013 [CBTSetCACLKResult] CA Dly = 36
7570 11:05:27.583451 CS Dly: 11 (0~43)
7571 11:05:27.587295 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7572 11:05:27.590253 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7573 11:05:27.590350
7574 11:05:27.596755 ----->DramcWriteLeveling(PI) begin...
7575 11:05:27.596923 ==
7576 11:05:27.600126 Dram Type= 6, Freq= 0, CH_0, rank 0
7577 11:05:27.603390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7578 11:05:27.603546 ==
7579 11:05:27.606459 Write leveling (Byte 0): 35 => 35
7580 11:05:27.609793 Write leveling (Byte 1): 25 => 25
7581 11:05:27.613385 DramcWriteLeveling(PI) end<-----
7582 11:05:27.613507
7583 11:05:27.613618 ==
7584 11:05:27.616130 Dram Type= 6, Freq= 0, CH_0, rank 0
7585 11:05:27.619379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7586 11:05:27.619512 ==
7587 11:05:27.623036 [Gating] SW mode calibration
7588 11:05:27.629557 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7589 11:05:27.636326 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7590 11:05:27.639540 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 11:05:27.642913 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 11:05:27.649042 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 11:05:27.652644 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7594 11:05:27.655737 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7595 11:05:27.662481 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7596 11:05:27.665982 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 11:05:27.669156 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 11:05:27.675288 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 11:05:27.678936 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 11:05:27.682218 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7601 11:05:27.688585 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
7602 11:05:27.692028 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7603 11:05:27.695662 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7604 11:05:27.701980 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7605 11:05:27.705112 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 11:05:27.708897 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 11:05:27.715073 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 11:05:27.718480 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7609 11:05:27.721499 1 6 12 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (0 0)
7610 11:05:27.728108 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7611 11:05:27.731108 1 6 20 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
7612 11:05:27.734742 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 11:05:27.741177 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 11:05:27.744557 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 11:05:27.747533 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 11:05:27.754481 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7617 11:05:27.757397 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7618 11:05:27.764114 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7619 11:05:27.767489 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7620 11:05:27.770680 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7621 11:05:27.777236 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 11:05:27.780765 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 11:05:27.783630 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 11:05:27.790378 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 11:05:27.793689 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 11:05:27.796905 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 11:05:27.803542 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 11:05:27.806376 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 11:05:27.809691 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 11:05:27.816586 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 11:05:27.819508 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 11:05:27.823022 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7633 11:05:27.829924 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7634 11:05:27.832962 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7635 11:05:27.836626 Total UI for P1: 0, mck2ui 16
7636 11:05:27.839862 best dqsien dly found for B0: ( 1, 9, 10)
7637 11:05:27.843147 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7638 11:05:27.849511 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 11:05:27.849639 Total UI for P1: 0, mck2ui 16
7640 11:05:27.856596 best dqsien dly found for B1: ( 1, 9, 20)
7641 11:05:27.859164 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7642 11:05:27.862647 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7643 11:05:27.862771
7644 11:05:27.866117 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7645 11:05:27.869463 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7646 11:05:27.872595 [Gating] SW calibration Done
7647 11:05:27.872678 ==
7648 11:05:27.875804 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 11:05:27.878960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 11:05:27.879043 ==
7651 11:05:27.882543 RX Vref Scan: 0
7652 11:05:27.882625
7653 11:05:27.882690 RX Vref 0 -> 0, step: 1
7654 11:05:27.882751
7655 11:05:27.886065 RX Delay 0 -> 252, step: 8
7656 11:05:27.889147 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7657 11:05:27.895382 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7658 11:05:27.898913 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7659 11:05:27.902104 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7660 11:05:27.905319 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7661 11:05:27.912397 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7662 11:05:27.915528 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7663 11:05:27.918685 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7664 11:05:27.921602 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7665 11:05:27.925086 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7666 11:05:27.932098 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7667 11:05:27.934971 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7668 11:05:27.938359 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7669 11:05:27.941550 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7670 11:05:27.944858 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7671 11:05:27.951500 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7672 11:05:27.951582 ==
7673 11:05:27.954637 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 11:05:27.958382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 11:05:27.958505 ==
7676 11:05:27.958621 DQS Delay:
7677 11:05:27.961449 DQS0 = 0, DQS1 = 0
7678 11:05:27.961558 DQM Delay:
7679 11:05:27.964586 DQM0 = 130, DQM1 = 126
7680 11:05:27.964678 DQ Delay:
7681 11:05:27.967905 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =123
7682 11:05:27.971511 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7683 11:05:27.974631 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
7684 11:05:27.981166 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7685 11:05:27.981247
7686 11:05:27.981329
7687 11:05:27.981390 ==
7688 11:05:27.984731 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 11:05:27.987623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 11:05:27.987729 ==
7691 11:05:27.987818
7692 11:05:27.987903
7693 11:05:27.991428 TX Vref Scan disable
7694 11:05:27.991513 == TX Byte 0 ==
7695 11:05:27.997524 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7696 11:05:28.000800 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7697 11:05:28.000883 == TX Byte 1 ==
7698 11:05:28.007292 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7699 11:05:28.010958 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7700 11:05:28.011069 ==
7701 11:05:28.014078 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 11:05:28.017466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 11:05:28.017573 ==
7704 11:05:28.033607
7705 11:05:28.036797 TX Vref early break, caculate TX vref
7706 11:05:28.040185 TX Vref=16, minBit 8, minWin=22, winSum=367
7707 11:05:28.043422 TX Vref=18, minBit 1, minWin=23, winSum=378
7708 11:05:28.046612 TX Vref=20, minBit 8, minWin=23, winSum=390
7709 11:05:28.049735 TX Vref=22, minBit 5, minWin=24, winSum=399
7710 11:05:28.053086 TX Vref=24, minBit 0, minWin=25, winSum=409
7711 11:05:28.060312 TX Vref=26, minBit 1, minWin=25, winSum=413
7712 11:05:28.063383 TX Vref=28, minBit 2, minWin=25, winSum=416
7713 11:05:28.066479 TX Vref=30, minBit 2, minWin=25, winSum=416
7714 11:05:28.069680 TX Vref=32, minBit 4, minWin=24, winSum=403
7715 11:05:28.072860 TX Vref=34, minBit 2, minWin=24, winSum=397
7716 11:05:28.079483 TX Vref=36, minBit 2, minWin=23, winSum=386
7717 11:05:28.082923 [TxChooseVref] Worse bit 2, Min win 25, Win sum 416, Final Vref 28
7718 11:05:28.083008
7719 11:05:28.086063 Final TX Range 0 Vref 28
7720 11:05:28.086159
7721 11:05:28.086225 ==
7722 11:05:28.089396 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 11:05:28.092759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 11:05:28.095914 ==
7725 11:05:28.095995
7726 11:05:28.096060
7727 11:05:28.096120 TX Vref Scan disable
7728 11:05:28.103028 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7729 11:05:28.103118 == TX Byte 0 ==
7730 11:05:28.105854 u2DelayCellOfst[0]=10 cells (3 PI)
7731 11:05:28.109362 u2DelayCellOfst[1]=14 cells (4 PI)
7732 11:05:28.112958 u2DelayCellOfst[2]=10 cells (3 PI)
7733 11:05:28.115803 u2DelayCellOfst[3]=10 cells (3 PI)
7734 11:05:28.118988 u2DelayCellOfst[4]=10 cells (3 PI)
7735 11:05:28.122750 u2DelayCellOfst[5]=0 cells (0 PI)
7736 11:05:28.125785 u2DelayCellOfst[6]=14 cells (4 PI)
7737 11:05:28.128867 u2DelayCellOfst[7]=17 cells (5 PI)
7738 11:05:28.132117 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7739 11:05:28.138753 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7740 11:05:28.138836 == TX Byte 1 ==
7741 11:05:28.141867 u2DelayCellOfst[8]=0 cells (0 PI)
7742 11:05:28.145805 u2DelayCellOfst[9]=0 cells (0 PI)
7743 11:05:28.148627 u2DelayCellOfst[10]=3 cells (1 PI)
7744 11:05:28.152077 u2DelayCellOfst[11]=0 cells (0 PI)
7745 11:05:28.155401 u2DelayCellOfst[12]=10 cells (3 PI)
7746 11:05:28.158741 u2DelayCellOfst[13]=7 cells (2 PI)
7747 11:05:28.162069 u2DelayCellOfst[14]=14 cells (4 PI)
7748 11:05:28.165104 u2DelayCellOfst[15]=10 cells (3 PI)
7749 11:05:28.169076 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7750 11:05:28.171693 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7751 11:05:28.174936 DramC Write-DBI on
7752 11:05:28.175068 ==
7753 11:05:28.178219 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 11:05:28.181601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 11:05:28.181709 ==
7756 11:05:28.181801
7757 11:05:28.181900
7758 11:05:28.185131 TX Vref Scan disable
7759 11:05:28.188097 == TX Byte 0 ==
7760 11:05:28.191321 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7761 11:05:28.191437 == TX Byte 1 ==
7762 11:05:28.198055 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7763 11:05:28.198137 DramC Write-DBI off
7764 11:05:28.198235
7765 11:05:28.198326 [DATLAT]
7766 11:05:28.201314 Freq=1600, CH0 RK0
7767 11:05:28.201446
7768 11:05:28.204402 DATLAT Default: 0xf
7769 11:05:28.204483 0, 0xFFFF, sum = 0
7770 11:05:28.207763 1, 0xFFFF, sum = 0
7771 11:05:28.207842 2, 0xFFFF, sum = 0
7772 11:05:28.210904 3, 0xFFFF, sum = 0
7773 11:05:28.210980 4, 0xFFFF, sum = 0
7774 11:05:28.215013 5, 0xFFFF, sum = 0
7775 11:05:28.215125 6, 0xFFFF, sum = 0
7776 11:05:28.217711 7, 0xFFFF, sum = 0
7777 11:05:28.217788 8, 0xFFFF, sum = 0
7778 11:05:28.221260 9, 0xFFFF, sum = 0
7779 11:05:28.221337 10, 0xFFFF, sum = 0
7780 11:05:28.224278 11, 0xFFFF, sum = 0
7781 11:05:28.227527 12, 0xFFFF, sum = 0
7782 11:05:28.227657 13, 0xFFFF, sum = 0
7783 11:05:28.230985 14, 0x0, sum = 1
7784 11:05:28.231116 15, 0x0, sum = 2
7785 11:05:28.231238 16, 0x0, sum = 3
7786 11:05:28.234344 17, 0x0, sum = 4
7787 11:05:28.234471 best_step = 15
7788 11:05:28.234587
7789 11:05:28.237654 ==
7790 11:05:28.240932 Dram Type= 6, Freq= 0, CH_0, rank 0
7791 11:05:28.243845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7792 11:05:28.243926 ==
7793 11:05:28.243991 RX Vref Scan: 1
7794 11:05:28.244064
7795 11:05:28.247146 Set Vref Range= 24 -> 127
7796 11:05:28.247219
7797 11:05:28.250786 RX Vref 24 -> 127, step: 1
7798 11:05:28.250866
7799 11:05:28.254115 RX Delay 11 -> 252, step: 4
7800 11:05:28.254198
7801 11:05:28.257058 Set Vref, RX VrefLevel [Byte0]: 24
7802 11:05:28.260506 [Byte1]: 24
7803 11:05:28.260583
7804 11:05:28.263873 Set Vref, RX VrefLevel [Byte0]: 25
7805 11:05:28.267209 [Byte1]: 25
7806 11:05:28.267287
7807 11:05:28.270583 Set Vref, RX VrefLevel [Byte0]: 26
7808 11:05:28.273286 [Byte1]: 26
7809 11:05:28.277396
7810 11:05:28.277474 Set Vref, RX VrefLevel [Byte0]: 27
7811 11:05:28.280616 [Byte1]: 27
7812 11:05:28.285154
7813 11:05:28.285236 Set Vref, RX VrefLevel [Byte0]: 28
7814 11:05:28.288643 [Byte1]: 28
7815 11:05:28.292613
7816 11:05:28.292696 Set Vref, RX VrefLevel [Byte0]: 29
7817 11:05:28.295807 [Byte1]: 29
7818 11:05:28.300432
7819 11:05:28.300509 Set Vref, RX VrefLevel [Byte0]: 30
7820 11:05:28.303642 [Byte1]: 30
7821 11:05:28.307901
7822 11:05:28.307980 Set Vref, RX VrefLevel [Byte0]: 31
7823 11:05:28.310976 [Byte1]: 31
7824 11:05:28.315272
7825 11:05:28.315380 Set Vref, RX VrefLevel [Byte0]: 32
7826 11:05:28.318615 [Byte1]: 32
7827 11:05:28.322898
7828 11:05:28.323003 Set Vref, RX VrefLevel [Byte0]: 33
7829 11:05:28.326911 [Byte1]: 33
7830 11:05:28.330808
7831 11:05:28.330921 Set Vref, RX VrefLevel [Byte0]: 34
7832 11:05:28.333937 [Byte1]: 34
7833 11:05:28.338023
7834 11:05:28.338123 Set Vref, RX VrefLevel [Byte0]: 35
7835 11:05:28.342112 [Byte1]: 35
7836 11:05:28.345922
7837 11:05:28.346027 Set Vref, RX VrefLevel [Byte0]: 36
7838 11:05:28.348953 [Byte1]: 36
7839 11:05:28.353382
7840 11:05:28.353471 Set Vref, RX VrefLevel [Byte0]: 37
7841 11:05:28.356789 [Byte1]: 37
7842 11:05:28.361649
7843 11:05:28.361755 Set Vref, RX VrefLevel [Byte0]: 38
7844 11:05:28.364146 [Byte1]: 38
7845 11:05:28.368840
7846 11:05:28.368929 Set Vref, RX VrefLevel [Byte0]: 39
7847 11:05:28.371970 [Byte1]: 39
7848 11:05:28.376125
7849 11:05:28.376238 Set Vref, RX VrefLevel [Byte0]: 40
7850 11:05:28.379335 [Byte1]: 40
7851 11:05:28.383797
7852 11:05:28.383916 Set Vref, RX VrefLevel [Byte0]: 41
7853 11:05:28.387178 [Byte1]: 41
7854 11:05:28.391824
7855 11:05:28.391917 Set Vref, RX VrefLevel [Byte0]: 42
7856 11:05:28.394614 [Byte1]: 42
7857 11:05:28.398861
7858 11:05:28.398962 Set Vref, RX VrefLevel [Byte0]: 43
7859 11:05:28.402529 [Byte1]: 43
7860 11:05:28.406854
7861 11:05:28.406958 Set Vref, RX VrefLevel [Byte0]: 44
7862 11:05:28.409860 [Byte1]: 44
7863 11:05:28.414195
7864 11:05:28.414326 Set Vref, RX VrefLevel [Byte0]: 45
7865 11:05:28.417743 [Byte1]: 45
7866 11:05:28.422150
7867 11:05:28.422248 Set Vref, RX VrefLevel [Byte0]: 46
7868 11:05:28.425352 [Byte1]: 46
7869 11:05:28.429661
7870 11:05:28.429754 Set Vref, RX VrefLevel [Byte0]: 47
7871 11:05:28.432941 [Byte1]: 47
7872 11:05:28.436917
7873 11:05:28.436999 Set Vref, RX VrefLevel [Byte0]: 48
7874 11:05:28.440499 [Byte1]: 48
7875 11:05:28.444888
7876 11:05:28.444964 Set Vref, RX VrefLevel [Byte0]: 49
7877 11:05:28.448049 [Byte1]: 49
7878 11:05:28.452327
7879 11:05:28.452404 Set Vref, RX VrefLevel [Byte0]: 50
7880 11:05:28.455767 [Byte1]: 50
7881 11:05:28.459875
7882 11:05:28.459993 Set Vref, RX VrefLevel [Byte0]: 51
7883 11:05:28.463158 [Byte1]: 51
7884 11:05:28.467572
7885 11:05:28.467657 Set Vref, RX VrefLevel [Byte0]: 52
7886 11:05:28.471322 [Byte1]: 52
7887 11:05:28.475115
7888 11:05:28.475216 Set Vref, RX VrefLevel [Byte0]: 53
7889 11:05:28.478276 [Byte1]: 53
7890 11:05:28.482775
7891 11:05:28.482853 Set Vref, RX VrefLevel [Byte0]: 54
7892 11:05:28.485944 [Byte1]: 54
7893 11:05:28.490529
7894 11:05:28.490602 Set Vref, RX VrefLevel [Byte0]: 55
7895 11:05:28.493774 [Byte1]: 55
7896 11:05:28.498019
7897 11:05:28.498101 Set Vref, RX VrefLevel [Byte0]: 56
7898 11:05:28.501699 [Byte1]: 56
7899 11:05:28.505575
7900 11:05:28.505657 Set Vref, RX VrefLevel [Byte0]: 57
7901 11:05:28.508946 [Byte1]: 57
7902 11:05:28.513661
7903 11:05:28.513787 Set Vref, RX VrefLevel [Byte0]: 58
7904 11:05:28.519535 [Byte1]: 58
7905 11:05:28.519620
7906 11:05:28.522988 Set Vref, RX VrefLevel [Byte0]: 59
7907 11:05:28.526156 [Byte1]: 59
7908 11:05:28.526238
7909 11:05:28.529680 Set Vref, RX VrefLevel [Byte0]: 60
7910 11:05:28.532596 [Byte1]: 60
7911 11:05:28.536244
7912 11:05:28.536325 Set Vref, RX VrefLevel [Byte0]: 61
7913 11:05:28.539259 [Byte1]: 61
7914 11:05:28.543705
7915 11:05:28.543781 Set Vref, RX VrefLevel [Byte0]: 62
7916 11:05:28.547063 [Byte1]: 62
7917 11:05:28.551326
7918 11:05:28.551421 Set Vref, RX VrefLevel [Byte0]: 63
7919 11:05:28.555032 [Byte1]: 63
7920 11:05:28.559006
7921 11:05:28.559078 Set Vref, RX VrefLevel [Byte0]: 64
7922 11:05:28.562322 [Byte1]: 64
7923 11:05:28.567046
7924 11:05:28.567121 Set Vref, RX VrefLevel [Byte0]: 65
7925 11:05:28.570302 [Byte1]: 65
7926 11:05:28.574356
7927 11:05:28.574431 Set Vref, RX VrefLevel [Byte0]: 66
7928 11:05:28.577597 [Byte1]: 66
7929 11:05:28.582130
7930 11:05:28.582210 Set Vref, RX VrefLevel [Byte0]: 67
7931 11:05:28.585019 [Byte1]: 67
7932 11:05:28.589187
7933 11:05:28.589282 Set Vref, RX VrefLevel [Byte0]: 68
7934 11:05:28.592588 [Byte1]: 68
7935 11:05:28.596931
7936 11:05:28.597073 Set Vref, RX VrefLevel [Byte0]: 69
7937 11:05:28.600456 [Byte1]: 69
7938 11:05:28.604598
7939 11:05:28.604700 Set Vref, RX VrefLevel [Byte0]: 70
7940 11:05:28.607775 [Byte1]: 70
7941 11:05:28.612105
7942 11:05:28.612207 Set Vref, RX VrefLevel [Byte0]: 71
7943 11:05:28.615694 [Byte1]: 71
7944 11:05:28.619839
7945 11:05:28.619940 Set Vref, RX VrefLevel [Byte0]: 72
7946 11:05:28.623252 [Byte1]: 72
7947 11:05:28.627611
7948 11:05:28.627726 Set Vref, RX VrefLevel [Byte0]: 73
7949 11:05:28.630868 [Byte1]: 73
7950 11:05:28.635104
7951 11:05:28.635224 Set Vref, RX VrefLevel [Byte0]: 74
7952 11:05:28.638313 [Byte1]: 74
7953 11:05:28.642683
7954 11:05:28.642805 Final RX Vref Byte 0 = 55 to rank0
7955 11:05:28.646062 Final RX Vref Byte 1 = 62 to rank0
7956 11:05:28.650125 Final RX Vref Byte 0 = 55 to rank1
7957 11:05:28.652466 Final RX Vref Byte 1 = 62 to rank1==
7958 11:05:28.656082 Dram Type= 6, Freq= 0, CH_0, rank 0
7959 11:05:28.662625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7960 11:05:28.662749 ==
7961 11:05:28.662862 DQS Delay:
7962 11:05:28.666195 DQS0 = 0, DQS1 = 0
7963 11:05:28.666314 DQM Delay:
7964 11:05:28.666426 DQM0 = 128, DQM1 = 123
7965 11:05:28.669107 DQ Delay:
7966 11:05:28.672376 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =124
7967 11:05:28.675852 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7968 11:05:28.678861 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7969 11:05:28.682060 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =130
7970 11:05:28.682184
7971 11:05:28.682299
7972 11:05:28.682405
7973 11:05:28.685891 [DramC_TX_OE_Calibration] TA2
7974 11:05:28.688522 Original DQ_B0 (3 6) =30, OEN = 27
7975 11:05:28.692024 Original DQ_B1 (3 6) =30, OEN = 27
7976 11:05:28.695330 24, 0x0, End_B0=24 End_B1=24
7977 11:05:28.698905 25, 0x0, End_B0=25 End_B1=25
7978 11:05:28.699040 26, 0x0, End_B0=26 End_B1=26
7979 11:05:28.701779 27, 0x0, End_B0=27 End_B1=27
7980 11:05:28.704995 28, 0x0, End_B0=28 End_B1=28
7981 11:05:28.708598 29, 0x0, End_B0=29 End_B1=29
7982 11:05:28.708692 30, 0x0, End_B0=30 End_B1=30
7983 11:05:28.711886 31, 0x4141, End_B0=30 End_B1=30
7984 11:05:28.715035 Byte0 end_step=30 best_step=27
7985 11:05:28.718187 Byte1 end_step=30 best_step=27
7986 11:05:28.721378 Byte0 TX OE(2T, 0.5T) = (3, 3)
7987 11:05:28.724674 Byte1 TX OE(2T, 0.5T) = (3, 3)
7988 11:05:28.724773
7989 11:05:28.724861
7990 11:05:28.731569 [DQSOSCAuto] RK0, (LSB)MR18= 0x1914, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7991 11:05:28.734672 CH0 RK0: MR19=303, MR18=1914
7992 11:05:28.741340 CH0_RK0: MR19=0x303, MR18=0x1914, DQSOSC=397, MR23=63, INC=23, DEC=15
7993 11:05:28.741462
7994 11:05:28.744442 ----->DramcWriteLeveling(PI) begin...
7995 11:05:28.744568 ==
7996 11:05:28.747975 Dram Type= 6, Freq= 0, CH_0, rank 1
7997 11:05:28.750987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7998 11:05:28.751110 ==
7999 11:05:28.754272 Write leveling (Byte 0): 34 => 34
8000 11:05:28.757854 Write leveling (Byte 1): 26 => 26
8001 11:05:28.761268 DramcWriteLeveling(PI) end<-----
8002 11:05:28.761350
8003 11:05:28.761429 ==
8004 11:05:28.764287 Dram Type= 6, Freq= 0, CH_0, rank 1
8005 11:05:28.770785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8006 11:05:28.770909 ==
8007 11:05:28.771045 [Gating] SW mode calibration
8008 11:05:28.780659 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8009 11:05:28.783837 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8010 11:05:28.791032 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 11:05:28.793852 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 11:05:28.797770 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8013 11:05:28.803856 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8014 11:05:28.807136 1 4 16 | B1->B0 | 2727 3434 | 0 1 | (1 1) (1 1)
8015 11:05:28.810345 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8016 11:05:28.817933 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 11:05:28.820569 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 11:05:28.823982 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 11:05:28.830045 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8020 11:05:28.833495 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
8021 11:05:28.836631 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8022 11:05:28.843595 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8023 11:05:28.846791 1 5 20 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
8024 11:05:28.849902 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 11:05:28.856326 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 11:05:28.859713 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 11:05:28.863467 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8028 11:05:28.869970 1 6 8 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
8029 11:05:28.873020 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8030 11:05:28.876449 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (1 1) (0 0)
8031 11:05:28.883124 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8032 11:05:28.886169 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 11:05:28.889540 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 11:05:28.895778 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 11:05:28.899332 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8036 11:05:28.902827 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8037 11:05:28.909533 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8038 11:05:28.913031 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8039 11:05:28.916000 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8040 11:05:28.922754 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 11:05:28.925890 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 11:05:28.928998 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 11:05:28.935540 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 11:05:28.939286 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 11:05:28.942547 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 11:05:28.948859 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 11:05:28.952647 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 11:05:28.955538 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 11:05:28.961902 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 11:05:28.965432 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 11:05:28.968423 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8052 11:05:28.974924 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8053 11:05:28.978808 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8054 11:05:28.982041 Total UI for P1: 0, mck2ui 16
8055 11:05:28.985440 best dqsien dly found for B0: ( 1, 9, 6)
8056 11:05:28.988434 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8057 11:05:28.994730 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8058 11:05:28.998334 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 11:05:29.001628 Total UI for P1: 0, mck2ui 16
8060 11:05:29.004730 best dqsien dly found for B1: ( 1, 9, 18)
8061 11:05:29.007954 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8062 11:05:29.011489 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8063 11:05:29.011594
8064 11:05:29.014667 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8065 11:05:29.018024 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8066 11:05:29.021147 [Gating] SW calibration Done
8067 11:05:29.021227 ==
8068 11:05:29.024234 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 11:05:29.031097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 11:05:29.031194 ==
8071 11:05:29.031257 RX Vref Scan: 0
8072 11:05:29.031317
8073 11:05:29.034136 RX Vref 0 -> 0, step: 1
8074 11:05:29.034217
8075 11:05:29.037562 RX Delay 0 -> 252, step: 8
8076 11:05:29.040958 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8077 11:05:29.043970 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8078 11:05:29.047192 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8079 11:05:29.050827 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8080 11:05:29.057383 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8081 11:05:29.060446 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8082 11:05:29.063848 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8083 11:05:29.067143 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8084 11:05:29.070466 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8085 11:05:29.077163 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8086 11:05:29.080210 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8087 11:05:29.083830 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8088 11:05:29.086870 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8089 11:05:29.093333 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8090 11:05:29.097015 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8091 11:05:29.100153 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8092 11:05:29.100243 ==
8093 11:05:29.103595 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 11:05:29.106622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 11:05:29.106722 ==
8096 11:05:29.110211 DQS Delay:
8097 11:05:29.110295 DQS0 = 0, DQS1 = 0
8098 11:05:29.113325 DQM Delay:
8099 11:05:29.113409 DQM0 = 132, DQM1 = 124
8100 11:05:29.116640 DQ Delay:
8101 11:05:29.120171 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8102 11:05:29.122909 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8103 11:05:29.126608 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
8104 11:05:29.129534 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8105 11:05:29.129616
8106 11:05:29.129681
8107 11:05:29.129740 ==
8108 11:05:29.132871 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 11:05:29.136514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 11:05:29.136591 ==
8111 11:05:29.136654
8112 11:05:29.139447
8113 11:05:29.139522 TX Vref Scan disable
8114 11:05:29.142934 == TX Byte 0 ==
8115 11:05:29.146148 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8116 11:05:29.149424 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8117 11:05:29.152626 == TX Byte 1 ==
8118 11:05:29.156229 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8119 11:05:29.159748 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8120 11:05:29.159856 ==
8121 11:05:29.162615 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 11:05:29.169145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 11:05:29.169254 ==
8124 11:05:29.182073
8125 11:05:29.184971 TX Vref early break, caculate TX vref
8126 11:05:29.188297 TX Vref=16, minBit 9, minWin=22, winSum=378
8127 11:05:29.191684 TX Vref=18, minBit 8, minWin=23, winSum=389
8128 11:05:29.194653 TX Vref=20, minBit 2, minWin=24, winSum=396
8129 11:05:29.197993 TX Vref=22, minBit 10, minWin=24, winSum=404
8130 11:05:29.204732 TX Vref=24, minBit 1, minWin=25, winSum=406
8131 11:05:29.207810 TX Vref=26, minBit 4, minWin=25, winSum=416
8132 11:05:29.211308 TX Vref=28, minBit 4, minWin=25, winSum=420
8133 11:05:29.214483 TX Vref=30, minBit 2, minWin=25, winSum=412
8134 11:05:29.217604 TX Vref=32, minBit 7, minWin=24, winSum=403
8135 11:05:29.221488 TX Vref=34, minBit 4, minWin=24, winSum=398
8136 11:05:29.227774 [TxChooseVref] Worse bit 4, Min win 25, Win sum 420, Final Vref 28
8137 11:05:29.227860
8138 11:05:29.231038 Final TX Range 0 Vref 28
8139 11:05:29.231123
8140 11:05:29.231208 ==
8141 11:05:29.234606 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 11:05:29.237614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 11:05:29.237700 ==
8144 11:05:29.237785
8145 11:05:29.240687
8146 11:05:29.240771 TX Vref Scan disable
8147 11:05:29.247527 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8148 11:05:29.247633 == TX Byte 0 ==
8149 11:05:29.250667 u2DelayCellOfst[0]=10 cells (3 PI)
8150 11:05:29.254231 u2DelayCellOfst[1]=14 cells (4 PI)
8151 11:05:29.257101 u2DelayCellOfst[2]=7 cells (2 PI)
8152 11:05:29.260605 u2DelayCellOfst[3]=10 cells (3 PI)
8153 11:05:29.264000 u2DelayCellOfst[4]=7 cells (2 PI)
8154 11:05:29.267178 u2DelayCellOfst[5]=0 cells (0 PI)
8155 11:05:29.270565 u2DelayCellOfst[6]=14 cells (4 PI)
8156 11:05:29.274258 u2DelayCellOfst[7]=14 cells (4 PI)
8157 11:05:29.276918 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8158 11:05:29.280602 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8159 11:05:29.283747 == TX Byte 1 ==
8160 11:05:29.286954 u2DelayCellOfst[8]=0 cells (0 PI)
8161 11:05:29.290495 u2DelayCellOfst[9]=0 cells (0 PI)
8162 11:05:29.293711 u2DelayCellOfst[10]=3 cells (1 PI)
8163 11:05:29.296606 u2DelayCellOfst[11]=3 cells (1 PI)
8164 11:05:29.300445 u2DelayCellOfst[12]=10 cells (3 PI)
8165 11:05:29.303247 u2DelayCellOfst[13]=10 cells (3 PI)
8166 11:05:29.303386 u2DelayCellOfst[14]=14 cells (4 PI)
8167 11:05:29.306945 u2DelayCellOfst[15]=10 cells (3 PI)
8168 11:05:29.313046 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8169 11:05:29.316358 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8170 11:05:29.319982 DramC Write-DBI on
8171 11:05:29.320067 ==
8172 11:05:29.323122 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 11:05:29.326882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 11:05:29.326990 ==
8175 11:05:29.327080
8176 11:05:29.327173
8177 11:05:29.329540 TX Vref Scan disable
8178 11:05:29.329646 == TX Byte 0 ==
8179 11:05:29.336407 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8180 11:05:29.336485 == TX Byte 1 ==
8181 11:05:29.342605 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8182 11:05:29.342759 DramC Write-DBI off
8183 11:05:29.342855
8184 11:05:29.342930 [DATLAT]
8185 11:05:29.345840 Freq=1600, CH0 RK1
8186 11:05:29.345969
8187 11:05:29.349241 DATLAT Default: 0xf
8188 11:05:29.349324 0, 0xFFFF, sum = 0
8189 11:05:29.352658 1, 0xFFFF, sum = 0
8190 11:05:29.352741 2, 0xFFFF, sum = 0
8191 11:05:29.356471 3, 0xFFFF, sum = 0
8192 11:05:29.356554 4, 0xFFFF, sum = 0
8193 11:05:29.359382 5, 0xFFFF, sum = 0
8194 11:05:29.359481 6, 0xFFFF, sum = 0
8195 11:05:29.362537 7, 0xFFFF, sum = 0
8196 11:05:29.362620 8, 0xFFFF, sum = 0
8197 11:05:29.365699 9, 0xFFFF, sum = 0
8198 11:05:29.365781 10, 0xFFFF, sum = 0
8199 11:05:29.369296 11, 0xFFFF, sum = 0
8200 11:05:29.369380 12, 0xFFFF, sum = 0
8201 11:05:29.372484 13, 0xFFFF, sum = 0
8202 11:05:29.372574 14, 0x0, sum = 1
8203 11:05:29.375736 15, 0x0, sum = 2
8204 11:05:29.375815 16, 0x0, sum = 3
8205 11:05:29.379103 17, 0x0, sum = 4
8206 11:05:29.379210 best_step = 15
8207 11:05:29.379299
8208 11:05:29.379433 ==
8209 11:05:29.382421 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 11:05:29.388988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 11:05:29.389066 ==
8212 11:05:29.389130 RX Vref Scan: 0
8213 11:05:29.389189
8214 11:05:29.392059 RX Vref 0 -> 0, step: 1
8215 11:05:29.392133
8216 11:05:29.395222 RX Delay 11 -> 252, step: 4
8217 11:05:29.398923 iDelay=187, Bit 0, Center 124 (75 ~ 174) 100
8218 11:05:29.401982 iDelay=187, Bit 1, Center 130 (79 ~ 182) 104
8219 11:05:29.408317 iDelay=187, Bit 2, Center 122 (71 ~ 174) 104
8220 11:05:29.412093 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8221 11:05:29.415239 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8222 11:05:29.418319 iDelay=187, Bit 5, Center 120 (67 ~ 174) 108
8223 11:05:29.421767 iDelay=187, Bit 6, Center 138 (91 ~ 186) 96
8224 11:05:29.428381 iDelay=187, Bit 7, Center 136 (87 ~ 186) 100
8225 11:05:29.431253 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8226 11:05:29.434663 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8227 11:05:29.437970 iDelay=187, Bit 10, Center 128 (75 ~ 182) 108
8228 11:05:29.441138 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8229 11:05:29.447775 iDelay=187, Bit 12, Center 126 (75 ~ 178) 104
8230 11:05:29.450912 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8231 11:05:29.454416 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8232 11:05:29.457941 iDelay=187, Bit 15, Center 130 (79 ~ 182) 104
8233 11:05:29.458066 ==
8234 11:05:29.461228 Dram Type= 6, Freq= 0, CH_0, rank 1
8235 11:05:29.467803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 11:05:29.467929 ==
8237 11:05:29.468042 DQS Delay:
8238 11:05:29.471225 DQS0 = 0, DQS1 = 0
8239 11:05:29.471307 DQM Delay:
8240 11:05:29.474321 DQM0 = 128, DQM1 = 123
8241 11:05:29.474402 DQ Delay:
8242 11:05:29.477801 DQ0 =124, DQ1 =130, DQ2 =122, DQ3 =126
8243 11:05:29.480861 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =136
8244 11:05:29.484050 DQ8 =114, DQ9 =110, DQ10 =128, DQ11 =118
8245 11:05:29.487313 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8246 11:05:29.487449
8247 11:05:29.487515
8248 11:05:29.487575
8249 11:05:29.490794 [DramC_TX_OE_Calibration] TA2
8250 11:05:29.494126 Original DQ_B0 (3 6) =30, OEN = 27
8251 11:05:29.497530 Original DQ_B1 (3 6) =30, OEN = 27
8252 11:05:29.500515 24, 0x0, End_B0=24 End_B1=24
8253 11:05:29.503652 25, 0x0, End_B0=25 End_B1=25
8254 11:05:29.503734 26, 0x0, End_B0=26 End_B1=26
8255 11:05:29.507081 27, 0x0, End_B0=27 End_B1=27
8256 11:05:29.510653 28, 0x0, End_B0=28 End_B1=28
8257 11:05:29.513585 29, 0x0, End_B0=29 End_B1=29
8258 11:05:29.517220 30, 0x0, End_B0=30 End_B1=30
8259 11:05:29.517302 31, 0x4141, End_B0=30 End_B1=30
8260 11:05:29.520241 Byte0 end_step=30 best_step=27
8261 11:05:29.523368 Byte1 end_step=30 best_step=27
8262 11:05:29.527049 Byte0 TX OE(2T, 0.5T) = (3, 3)
8263 11:05:29.530442 Byte1 TX OE(2T, 0.5T) = (3, 3)
8264 11:05:29.530528
8265 11:05:29.530612
8266 11:05:29.537107 [DQSOSCAuto] RK1, (LSB)MR18= 0x1513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8267 11:05:29.540264 CH0 RK1: MR19=303, MR18=1513
8268 11:05:29.546714 CH0_RK1: MR19=0x303, MR18=0x1513, DQSOSC=399, MR23=63, INC=23, DEC=15
8269 11:05:29.550145 [RxdqsGatingPostProcess] freq 1600
8270 11:05:29.556615 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8271 11:05:29.560099 best DQS0 dly(2T, 0.5T) = (1, 1)
8272 11:05:29.560208 best DQS1 dly(2T, 0.5T) = (1, 1)
8273 11:05:29.563147 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8274 11:05:29.566848 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8275 11:05:29.569746 best DQS0 dly(2T, 0.5T) = (1, 1)
8276 11:05:29.573097 best DQS1 dly(2T, 0.5T) = (1, 1)
8277 11:05:29.576279 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8278 11:05:29.579632 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8279 11:05:29.582546 Pre-setting of DQS Precalculation
8280 11:05:29.589558 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8281 11:05:29.589644 ==
8282 11:05:29.592382 Dram Type= 6, Freq= 0, CH_1, rank 0
8283 11:05:29.595895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8284 11:05:29.595992 ==
8285 11:05:29.602728 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8286 11:05:29.605760 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8287 11:05:29.609217 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8288 11:05:29.615300 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8289 11:05:29.624586 [CA 0] Center 42 (13~72) winsize 60
8290 11:05:29.628013 [CA 1] Center 42 (13~72) winsize 60
8291 11:05:29.630917 [CA 2] Center 39 (10~68) winsize 59
8292 11:05:29.634103 [CA 3] Center 38 (9~67) winsize 59
8293 11:05:29.637532 [CA 4] Center 38 (9~68) winsize 60
8294 11:05:29.640823 [CA 5] Center 37 (7~67) winsize 61
8295 11:05:29.640904
8296 11:05:29.644220 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8297 11:05:29.644302
8298 11:05:29.650945 [CATrainingPosCal] consider 1 rank data
8299 11:05:29.651027 u2DelayCellTimex100 = 275/100 ps
8300 11:05:29.657349 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8301 11:05:29.660562 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8302 11:05:29.663759 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
8303 11:05:29.667306 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8304 11:05:29.670902 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8305 11:05:29.674126 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8306 11:05:29.674211
8307 11:05:29.677023 CA PerBit enable=1, Macro0, CA PI delay=37
8308 11:05:29.677108
8309 11:05:29.680573 [CBTSetCACLKResult] CA Dly = 37
8310 11:05:29.683759 CS Dly: 8 (0~39)
8311 11:05:29.687298 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8312 11:05:29.690261 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8313 11:05:29.690346 ==
8314 11:05:29.693565 Dram Type= 6, Freq= 0, CH_1, rank 1
8315 11:05:29.700841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 11:05:29.700928 ==
8317 11:05:29.703805 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8318 11:05:29.710101 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8319 11:05:29.713174 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8320 11:05:29.719959 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8321 11:05:29.727807 [CA 0] Center 42 (12~72) winsize 61
8322 11:05:29.730796 [CA 1] Center 42 (13~72) winsize 60
8323 11:05:29.734089 [CA 2] Center 38 (9~68) winsize 60
8324 11:05:29.737444 [CA 3] Center 37 (8~67) winsize 60
8325 11:05:29.740996 [CA 4] Center 37 (7~67) winsize 61
8326 11:05:29.744010 [CA 5] Center 37 (7~67) winsize 61
8327 11:05:29.744095
8328 11:05:29.747216 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8329 11:05:29.747301
8330 11:05:29.753875 [CATrainingPosCal] consider 2 rank data
8331 11:05:29.753960 u2DelayCellTimex100 = 275/100 ps
8332 11:05:29.760925 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8333 11:05:29.764103 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8334 11:05:29.767222 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
8335 11:05:29.770563 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8336 11:05:29.773897 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8337 11:05:29.777352 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8338 11:05:29.777437
8339 11:05:29.780434 CA PerBit enable=1, Macro0, CA PI delay=37
8340 11:05:29.780520
8341 11:05:29.783649 [CBTSetCACLKResult] CA Dly = 37
8342 11:05:29.786902 CS Dly: 9 (0~42)
8343 11:05:29.790252 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8344 11:05:29.793488 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8345 11:05:29.793572
8346 11:05:29.796730 ----->DramcWriteLeveling(PI) begin...
8347 11:05:29.796837 ==
8348 11:05:29.799831 Dram Type= 6, Freq= 0, CH_1, rank 0
8349 11:05:29.806605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8350 11:05:29.806704 ==
8351 11:05:29.809928 Write leveling (Byte 0): 26 => 26
8352 11:05:29.813210 Write leveling (Byte 1): 27 => 27
8353 11:05:29.816335 DramcWriteLeveling(PI) end<-----
8354 11:05:29.816416
8355 11:05:29.816480 ==
8356 11:05:29.819984 Dram Type= 6, Freq= 0, CH_1, rank 0
8357 11:05:29.823359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 11:05:29.823463 ==
8359 11:05:29.826509 [Gating] SW mode calibration
8360 11:05:29.832817 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8361 11:05:29.839761 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8362 11:05:29.842888 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 11:05:29.846445 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 11:05:29.852951 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8365 11:05:29.856014 1 4 12 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
8366 11:05:29.859249 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 11:05:29.865848 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 11:05:29.869199 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 11:05:29.872191 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 11:05:29.878530 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 11:05:29.882013 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 11:05:29.885697 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8373 11:05:29.891805 1 5 12 | B1->B0 | 3333 2727 | 0 0 | (0 1) (1 0)
8374 11:05:29.895566 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8375 11:05:29.898714 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 11:05:29.905008 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 11:05:29.908484 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 11:05:29.911758 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 11:05:29.918316 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 11:05:29.921504 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8381 11:05:29.925208 1 6 12 | B1->B0 | 2626 4242 | 0 0 | (0 0) (0 0)
8382 11:05:29.931531 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 11:05:29.935206 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 11:05:29.938249 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 11:05:29.944546 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 11:05:29.948109 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 11:05:29.951537 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 11:05:29.957711 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 11:05:29.961366 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8390 11:05:29.964647 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 11:05:29.971258 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8392 11:05:29.974203 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 11:05:29.977612 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 11:05:29.984310 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 11:05:29.987572 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 11:05:29.990594 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 11:05:29.997404 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 11:05:30.000549 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 11:05:30.004242 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 11:05:30.010532 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 11:05:30.014069 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 11:05:30.017193 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 11:05:30.023603 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 11:05:30.026901 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8405 11:05:30.030397 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8406 11:05:30.036914 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8407 11:05:30.037023 Total UI for P1: 0, mck2ui 16
8408 11:05:30.043206 best dqsien dly found for B0: ( 1, 9, 10)
8409 11:05:30.046488 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 11:05:30.049936 Total UI for P1: 0, mck2ui 16
8411 11:05:30.053254 best dqsien dly found for B1: ( 1, 9, 14)
8412 11:05:30.056547 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8413 11:05:30.059842 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8414 11:05:30.059928
8415 11:05:30.063405 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8416 11:05:30.066544 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8417 11:05:30.070502 [Gating] SW calibration Done
8418 11:05:30.070584 ==
8419 11:05:30.072996 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 11:05:30.080058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 11:05:30.080157 ==
8422 11:05:30.080252 RX Vref Scan: 0
8423 11:05:30.080314
8424 11:05:30.083092 RX Vref 0 -> 0, step: 1
8425 11:05:30.083210
8426 11:05:30.086352 RX Delay 0 -> 252, step: 8
8427 11:05:30.089583 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8428 11:05:30.092644 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8429 11:05:30.096512 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8430 11:05:30.099455 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8431 11:05:30.105886 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8432 11:05:30.109305 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8433 11:05:30.112377 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8434 11:05:30.115886 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8435 11:05:30.119269 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8436 11:05:30.125674 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8437 11:05:30.128942 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8438 11:05:30.132346 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8439 11:05:30.135809 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8440 11:05:30.142564 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8441 11:05:30.145246 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8442 11:05:30.148455 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8443 11:05:30.148558 ==
8444 11:05:30.152554 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 11:05:30.155330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 11:05:30.158693 ==
8447 11:05:30.158821 DQS Delay:
8448 11:05:30.158937 DQS0 = 0, DQS1 = 0
8449 11:05:30.161920 DQM Delay:
8450 11:05:30.162043 DQM0 = 134, DQM1 = 129
8451 11:05:30.165404 DQ Delay:
8452 11:05:30.168473 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8453 11:05:30.172119 DQ4 =127, DQ5 =143, DQ6 =147, DQ7 =127
8454 11:05:30.175311 DQ8 =111, DQ9 =119, DQ10 =127, DQ11 =123
8455 11:05:30.178456 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8456 11:05:30.178542
8457 11:05:30.178609
8458 11:05:30.178669 ==
8459 11:05:30.181513 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 11:05:30.185255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 11:05:30.185332 ==
8462 11:05:30.188437
8463 11:05:30.188509
8464 11:05:30.188573 TX Vref Scan disable
8465 11:05:30.191535 == TX Byte 0 ==
8466 11:05:30.194712 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8467 11:05:30.198256 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8468 11:05:30.201330 == TX Byte 1 ==
8469 11:05:30.204889 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8470 11:05:30.209325 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8471 11:05:30.209424 ==
8472 11:05:30.211563 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 11:05:30.217829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 11:05:30.217961 ==
8475 11:05:30.229578
8476 11:05:30.232618 TX Vref early break, caculate TX vref
8477 11:05:30.236138 TX Vref=16, minBit 8, minWin=21, winSum=370
8478 11:05:30.239583 TX Vref=18, minBit 8, minWin=21, winSum=378
8479 11:05:30.242516 TX Vref=20, minBit 8, minWin=23, winSum=388
8480 11:05:30.246455 TX Vref=22, minBit 8, minWin=23, winSum=396
8481 11:05:30.249071 TX Vref=24, minBit 8, minWin=24, winSum=408
8482 11:05:30.255900 TX Vref=26, minBit 3, minWin=25, winSum=412
8483 11:05:30.259018 TX Vref=28, minBit 11, minWin=25, winSum=421
8484 11:05:30.262540 TX Vref=30, minBit 9, minWin=24, winSum=414
8485 11:05:30.265869 TX Vref=32, minBit 9, minWin=24, winSum=405
8486 11:05:30.269258 TX Vref=34, minBit 11, minWin=23, winSum=398
8487 11:05:30.275765 [TxChooseVref] Worse bit 11, Min win 25, Win sum 421, Final Vref 28
8488 11:05:30.275876
8489 11:05:30.279242 Final TX Range 0 Vref 28
8490 11:05:30.279318
8491 11:05:30.279438 ==
8492 11:05:30.282234 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 11:05:30.286434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 11:05:30.286535 ==
8495 11:05:30.286613
8496 11:05:30.289086
8497 11:05:30.289187 TX Vref Scan disable
8498 11:05:30.295518 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8499 11:05:30.295607 == TX Byte 0 ==
8500 11:05:30.298743 u2DelayCellOfst[0]=14 cells (4 PI)
8501 11:05:30.301918 u2DelayCellOfst[1]=7 cells (2 PI)
8502 11:05:30.305546 u2DelayCellOfst[2]=0 cells (0 PI)
8503 11:05:30.308468 u2DelayCellOfst[3]=3 cells (1 PI)
8504 11:05:30.311821 u2DelayCellOfst[4]=7 cells (2 PI)
8505 11:05:30.314914 u2DelayCellOfst[5]=14 cells (4 PI)
8506 11:05:30.318303 u2DelayCellOfst[6]=14 cells (4 PI)
8507 11:05:30.321884 u2DelayCellOfst[7]=3 cells (1 PI)
8508 11:05:30.325268 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8509 11:05:30.328157 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8510 11:05:30.331382 == TX Byte 1 ==
8511 11:05:30.335230 u2DelayCellOfst[8]=0 cells (0 PI)
8512 11:05:30.338174 u2DelayCellOfst[9]=3 cells (1 PI)
8513 11:05:30.341382 u2DelayCellOfst[10]=10 cells (3 PI)
8514 11:05:30.344573 u2DelayCellOfst[11]=7 cells (2 PI)
8515 11:05:30.344656 u2DelayCellOfst[12]=14 cells (4 PI)
8516 11:05:30.348018 u2DelayCellOfst[13]=17 cells (5 PI)
8517 11:05:30.351542 u2DelayCellOfst[14]=17 cells (5 PI)
8518 11:05:30.354897 u2DelayCellOfst[15]=21 cells (6 PI)
8519 11:05:30.361559 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8520 11:05:30.364757 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8521 11:05:30.367509 DramC Write-DBI on
8522 11:05:30.367591 ==
8523 11:05:30.370938 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 11:05:30.374076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 11:05:30.374159 ==
8526 11:05:30.374224
8527 11:05:30.374283
8528 11:05:30.377709 TX Vref Scan disable
8529 11:05:30.377792 == TX Byte 0 ==
8530 11:05:30.384827 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8531 11:05:30.384912 == TX Byte 1 ==
8532 11:05:30.387409 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8533 11:05:30.390598 DramC Write-DBI off
8534 11:05:30.390681
8535 11:05:30.390747 [DATLAT]
8536 11:05:30.393770 Freq=1600, CH1 RK0
8537 11:05:30.393854
8538 11:05:30.393919 DATLAT Default: 0xf
8539 11:05:30.397080 0, 0xFFFF, sum = 0
8540 11:05:30.397165 1, 0xFFFF, sum = 0
8541 11:05:30.400876 2, 0xFFFF, sum = 0
8542 11:05:30.404225 3, 0xFFFF, sum = 0
8543 11:05:30.404310 4, 0xFFFF, sum = 0
8544 11:05:30.407315 5, 0xFFFF, sum = 0
8545 11:05:30.407424 6, 0xFFFF, sum = 0
8546 11:05:30.410408 7, 0xFFFF, sum = 0
8547 11:05:30.410492 8, 0xFFFF, sum = 0
8548 11:05:30.414012 9, 0xFFFF, sum = 0
8549 11:05:30.414097 10, 0xFFFF, sum = 0
8550 11:05:30.416800 11, 0xFFFF, sum = 0
8551 11:05:30.416885 12, 0xFFFF, sum = 0
8552 11:05:30.420558 13, 0xFFFF, sum = 0
8553 11:05:30.420643 14, 0x0, sum = 1
8554 11:05:30.423922 15, 0x0, sum = 2
8555 11:05:30.424034 16, 0x0, sum = 3
8556 11:05:30.426714 17, 0x0, sum = 4
8557 11:05:30.426816 best_step = 15
8558 11:05:30.426906
8559 11:05:30.426993 ==
8560 11:05:30.430057 Dram Type= 6, Freq= 0, CH_1, rank 0
8561 11:05:30.436646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8562 11:05:30.436731 ==
8563 11:05:30.436798 RX Vref Scan: 1
8564 11:05:30.436860
8565 11:05:30.440160 Set Vref Range= 24 -> 127
8566 11:05:30.440244
8567 11:05:30.443407 RX Vref 24 -> 127, step: 1
8568 11:05:30.443491
8569 11:05:30.443570 RX Delay 11 -> 252, step: 4
8570 11:05:30.443634
8571 11:05:30.447084 Set Vref, RX VrefLevel [Byte0]: 24
8572 11:05:30.449823 [Byte1]: 24
8573 11:05:30.454378
8574 11:05:30.454461 Set Vref, RX VrefLevel [Byte0]: 25
8575 11:05:30.457516 [Byte1]: 25
8576 11:05:30.461579
8577 11:05:30.461670 Set Vref, RX VrefLevel [Byte0]: 26
8578 11:05:30.465022 [Byte1]: 26
8579 11:05:30.469174
8580 11:05:30.469258 Set Vref, RX VrefLevel [Byte0]: 27
8581 11:05:30.472792 [Byte1]: 27
8582 11:05:30.477319
8583 11:05:30.477406 Set Vref, RX VrefLevel [Byte0]: 28
8584 11:05:30.480316 [Byte1]: 28
8585 11:05:30.484546
8586 11:05:30.484628 Set Vref, RX VrefLevel [Byte0]: 29
8587 11:05:30.487963 [Byte1]: 29
8588 11:05:30.492579
8589 11:05:30.492660 Set Vref, RX VrefLevel [Byte0]: 30
8590 11:05:30.495629 [Byte1]: 30
8591 11:05:30.500422
8592 11:05:30.500503 Set Vref, RX VrefLevel [Byte0]: 31
8593 11:05:30.503127 [Byte1]: 31
8594 11:05:30.507292
8595 11:05:30.507432 Set Vref, RX VrefLevel [Byte0]: 32
8596 11:05:30.510643 [Byte1]: 32
8597 11:05:30.514898
8598 11:05:30.514980 Set Vref, RX VrefLevel [Byte0]: 33
8599 11:05:30.518243 [Byte1]: 33
8600 11:05:30.522472
8601 11:05:30.522554 Set Vref, RX VrefLevel [Byte0]: 34
8602 11:05:30.526443 [Byte1]: 34
8603 11:05:30.530282
8604 11:05:30.530364 Set Vref, RX VrefLevel [Byte0]: 35
8605 11:05:30.533316 [Byte1]: 35
8606 11:05:30.538065
8607 11:05:30.538147 Set Vref, RX VrefLevel [Byte0]: 36
8608 11:05:30.541106 [Byte1]: 36
8609 11:05:30.545586
8610 11:05:30.545670 Set Vref, RX VrefLevel [Byte0]: 37
8611 11:05:30.548999 [Byte1]: 37
8612 11:05:30.553392
8613 11:05:30.553473 Set Vref, RX VrefLevel [Byte0]: 38
8614 11:05:30.556520 [Byte1]: 38
8615 11:05:30.560544
8616 11:05:30.560626 Set Vref, RX VrefLevel [Byte0]: 39
8617 11:05:30.563883 [Byte1]: 39
8618 11:05:30.568350
8619 11:05:30.568432 Set Vref, RX VrefLevel [Byte0]: 40
8620 11:05:30.572038 [Byte1]: 40
8621 11:05:30.575936
8622 11:05:30.576018 Set Vref, RX VrefLevel [Byte0]: 41
8623 11:05:30.579191 [Byte1]: 41
8624 11:05:30.583911
8625 11:05:30.583993 Set Vref, RX VrefLevel [Byte0]: 42
8626 11:05:30.590084 [Byte1]: 42
8627 11:05:30.590203
8628 11:05:30.593527 Set Vref, RX VrefLevel [Byte0]: 43
8629 11:05:30.596545 [Byte1]: 43
8630 11:05:30.596629
8631 11:05:30.599714 Set Vref, RX VrefLevel [Byte0]: 44
8632 11:05:30.603178 [Byte1]: 44
8633 11:05:30.606687
8634 11:05:30.606797 Set Vref, RX VrefLevel [Byte0]: 45
8635 11:05:30.609478 [Byte1]: 45
8636 11:05:30.614664
8637 11:05:30.614796 Set Vref, RX VrefLevel [Byte0]: 46
8638 11:05:30.617406 [Byte1]: 46
8639 11:05:30.621611
8640 11:05:30.621714 Set Vref, RX VrefLevel [Byte0]: 47
8641 11:05:30.625143 [Byte1]: 47
8642 11:05:30.629469
8643 11:05:30.629571 Set Vref, RX VrefLevel [Byte0]: 48
8644 11:05:30.632599 [Byte1]: 48
8645 11:05:30.636754
8646 11:05:30.636861 Set Vref, RX VrefLevel [Byte0]: 49
8647 11:05:30.640052 [Byte1]: 49
8648 11:05:30.644568
8649 11:05:30.644672 Set Vref, RX VrefLevel [Byte0]: 50
8650 11:05:30.647925 [Byte1]: 50
8651 11:05:30.652487
8652 11:05:30.652592 Set Vref, RX VrefLevel [Byte0]: 51
8653 11:05:30.655554 [Byte1]: 51
8654 11:05:30.659794
8655 11:05:30.659895 Set Vref, RX VrefLevel [Byte0]: 52
8656 11:05:30.663113 [Byte1]: 52
8657 11:05:30.667129
8658 11:05:30.667243 Set Vref, RX VrefLevel [Byte0]: 53
8659 11:05:30.670443 [Byte1]: 53
8660 11:05:30.675315
8661 11:05:30.675448 Set Vref, RX VrefLevel [Byte0]: 54
8662 11:05:30.678070 [Byte1]: 54
8663 11:05:30.682416
8664 11:05:30.682500 Set Vref, RX VrefLevel [Byte0]: 55
8665 11:05:30.685846 [Byte1]: 55
8666 11:05:30.690292
8667 11:05:30.690376 Set Vref, RX VrefLevel [Byte0]: 56
8668 11:05:30.693268 [Byte1]: 56
8669 11:05:30.697915
8670 11:05:30.697998 Set Vref, RX VrefLevel [Byte0]: 57
8671 11:05:30.701019 [Byte1]: 57
8672 11:05:30.705265
8673 11:05:30.705349 Set Vref, RX VrefLevel [Byte0]: 58
8674 11:05:30.708715 [Byte1]: 58
8675 11:05:30.713326
8676 11:05:30.713434 Set Vref, RX VrefLevel [Byte0]: 59
8677 11:05:30.716522 [Byte1]: 59
8678 11:05:30.720679
8679 11:05:30.720763 Set Vref, RX VrefLevel [Byte0]: 60
8680 11:05:30.724311 [Byte1]: 60
8681 11:05:30.728105
8682 11:05:30.728189 Set Vref, RX VrefLevel [Byte0]: 61
8683 11:05:30.731550 [Byte1]: 61
8684 11:05:30.735949
8685 11:05:30.736090 Set Vref, RX VrefLevel [Byte0]: 62
8686 11:05:30.739204 [Byte1]: 62
8687 11:05:30.743622
8688 11:05:30.743705 Set Vref, RX VrefLevel [Byte0]: 63
8689 11:05:30.746725 [Byte1]: 63
8690 11:05:30.751055
8691 11:05:30.754602 Set Vref, RX VrefLevel [Byte0]: 64
8692 11:05:30.757593 [Byte1]: 64
8693 11:05:30.757677
8694 11:05:30.760785 Set Vref, RX VrefLevel [Byte0]: 65
8695 11:05:30.763997 [Byte1]: 65
8696 11:05:30.764092
8697 11:05:30.767797 Set Vref, RX VrefLevel [Byte0]: 66
8698 11:05:30.770939 [Byte1]: 66
8699 11:05:30.774072
8700 11:05:30.774197 Set Vref, RX VrefLevel [Byte0]: 67
8701 11:05:30.778184 [Byte1]: 67
8702 11:05:30.781646
8703 11:05:30.781766 Set Vref, RX VrefLevel [Byte0]: 68
8704 11:05:30.784719 [Byte1]: 68
8705 11:05:30.789186
8706 11:05:30.789301 Set Vref, RX VrefLevel [Byte0]: 69
8707 11:05:30.792505 [Byte1]: 69
8708 11:05:30.796794
8709 11:05:30.796924 Set Vref, RX VrefLevel [Byte0]: 70
8710 11:05:30.800314 [Byte1]: 70
8711 11:05:30.804436
8712 11:05:30.804520 Final RX Vref Byte 0 = 57 to rank0
8713 11:05:30.807481 Final RX Vref Byte 1 = 60 to rank0
8714 11:05:30.810981 Final RX Vref Byte 0 = 57 to rank1
8715 11:05:30.813916 Final RX Vref Byte 1 = 60 to rank1==
8716 11:05:30.817422 Dram Type= 6, Freq= 0, CH_1, rank 0
8717 11:05:30.824200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 11:05:30.824301 ==
8719 11:05:30.824386 DQS Delay:
8720 11:05:30.827760 DQS0 = 0, DQS1 = 0
8721 11:05:30.827897 DQM Delay:
8722 11:05:30.828028 DQM0 = 132, DQM1 = 129
8723 11:05:30.830518 DQ Delay:
8724 11:05:30.833775 DQ0 =140, DQ1 =130, DQ2 =118, DQ3 =132
8725 11:05:30.837538 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8726 11:05:30.840367 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =120
8727 11:05:30.843880 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8728 11:05:30.843988
8729 11:05:30.844081
8730 11:05:30.844169
8731 11:05:30.846954 [DramC_TX_OE_Calibration] TA2
8732 11:05:30.850195 Original DQ_B0 (3 6) =30, OEN = 27
8733 11:05:30.854093 Original DQ_B1 (3 6) =30, OEN = 27
8734 11:05:30.856763 24, 0x0, End_B0=24 End_B1=24
8735 11:05:30.860370 25, 0x0, End_B0=25 End_B1=25
8736 11:05:30.860454 26, 0x0, End_B0=26 End_B1=26
8737 11:05:30.864066 27, 0x0, End_B0=27 End_B1=27
8738 11:05:30.866963 28, 0x0, End_B0=28 End_B1=28
8739 11:05:30.870047 29, 0x0, End_B0=29 End_B1=29
8740 11:05:30.870165 30, 0x0, End_B0=30 End_B1=30
8741 11:05:30.873650 31, 0x4141, End_B0=30 End_B1=30
8742 11:05:30.876439 Byte0 end_step=30 best_step=27
8743 11:05:30.880074 Byte1 end_step=30 best_step=27
8744 11:05:30.883938 Byte0 TX OE(2T, 0.5T) = (3, 3)
8745 11:05:30.886552 Byte1 TX OE(2T, 0.5T) = (3, 3)
8746 11:05:30.886649
8747 11:05:30.886740
8748 11:05:30.893097 [DQSOSCAuto] RK0, (LSB)MR18= 0xd17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8749 11:05:30.896636 CH1 RK0: MR19=303, MR18=D17
8750 11:05:30.903384 CH1_RK0: MR19=0x303, MR18=0xD17, DQSOSC=398, MR23=63, INC=23, DEC=15
8751 11:05:30.903527
8752 11:05:30.906249 ----->DramcWriteLeveling(PI) begin...
8753 11:05:30.906376 ==
8754 11:05:30.909785 Dram Type= 6, Freq= 0, CH_1, rank 1
8755 11:05:30.913387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8756 11:05:30.913489 ==
8757 11:05:30.916619 Write leveling (Byte 0): 25 => 25
8758 11:05:30.919554 Write leveling (Byte 1): 29 => 29
8759 11:05:30.922615 DramcWriteLeveling(PI) end<-----
8760 11:05:30.922763
8761 11:05:30.922907 ==
8762 11:05:30.926318 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 11:05:30.929406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 11:05:30.932779 ==
8765 11:05:30.932886 [Gating] SW mode calibration
8766 11:05:30.942734 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8767 11:05:30.946091 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8768 11:05:30.949495 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 11:05:30.955912 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 11:05:30.959049 1 4 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8771 11:05:30.962333 1 4 12 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8772 11:05:30.968953 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 11:05:30.972388 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 11:05:30.975660 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 11:05:30.982042 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 11:05:30.985156 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 11:05:30.988522 1 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8778 11:05:30.995584 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8779 11:05:30.998670 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8780 11:05:31.002257 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 11:05:31.008629 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 11:05:31.011693 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 11:05:31.015462 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 11:05:31.021800 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 11:05:31.024809 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 11:05:31.028230 1 6 8 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8787 11:05:31.034671 1 6 12 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
8788 11:05:31.038570 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 11:05:31.041447 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 11:05:31.048262 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 11:05:31.051171 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 11:05:31.054427 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 11:05:31.061096 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 11:05:31.064724 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8795 11:05:31.067672 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8796 11:05:31.074518 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8797 11:05:31.078243 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 11:05:31.081363 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 11:05:31.087506 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 11:05:31.090876 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 11:05:31.093964 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 11:05:31.100416 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 11:05:31.104043 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 11:05:31.106927 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 11:05:31.113688 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 11:05:31.117285 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 11:05:31.120129 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 11:05:31.126550 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 11:05:31.130108 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8810 11:05:31.136826 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8811 11:05:31.139830 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8812 11:05:31.143569 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 11:05:31.146339 Total UI for P1: 0, mck2ui 16
8814 11:05:31.149787 best dqsien dly found for B0: ( 1, 9, 8)
8815 11:05:31.152993 Total UI for P1: 0, mck2ui 16
8816 11:05:31.156529 best dqsien dly found for B1: ( 1, 9, 14)
8817 11:05:31.160026 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8818 11:05:31.163342 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8819 11:05:31.163467
8820 11:05:31.166280 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8821 11:05:31.172706 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8822 11:05:31.172789 [Gating] SW calibration Done
8823 11:05:31.176437 ==
8824 11:05:31.176520 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 11:05:31.182591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 11:05:31.182692 ==
8827 11:05:31.182790 RX Vref Scan: 0
8828 11:05:31.182866
8829 11:05:31.185946 RX Vref 0 -> 0, step: 1
8830 11:05:31.186048
8831 11:05:31.189178 RX Delay 0 -> 252, step: 8
8832 11:05:31.192614 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8833 11:05:31.195694 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8834 11:05:31.199229 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8835 11:05:31.205707 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8836 11:05:31.209356 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8837 11:05:31.212477 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8838 11:05:31.215567 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8839 11:05:31.219293 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8840 11:05:31.225310 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8841 11:05:31.228830 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8842 11:05:31.232575 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8843 11:05:31.235457 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8844 11:05:31.241801 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8845 11:05:31.244964 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8846 11:05:31.248579 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8847 11:05:31.251703 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8848 11:05:31.251826 ==
8849 11:05:31.254726 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 11:05:31.261738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 11:05:31.261862 ==
8852 11:05:31.261973 DQS Delay:
8853 11:05:31.264645 DQS0 = 0, DQS1 = 0
8854 11:05:31.264767 DQM Delay:
8855 11:05:31.268248 DQM0 = 133, DQM1 = 130
8856 11:05:31.268366 DQ Delay:
8857 11:05:31.271315 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =127
8858 11:05:31.274953 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =135
8859 11:05:31.278269 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8860 11:05:31.281707 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8861 11:05:31.281792
8862 11:05:31.281858
8863 11:05:31.281940 ==
8864 11:05:31.284747 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 11:05:31.291004 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 11:05:31.291107 ==
8867 11:05:31.291210
8868 11:05:31.291301
8869 11:05:31.291399 TX Vref Scan disable
8870 11:05:31.294534 == TX Byte 0 ==
8871 11:05:31.297948 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8872 11:05:31.304307 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8873 11:05:31.304391 == TX Byte 1 ==
8874 11:05:31.307758 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8875 11:05:31.314334 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8876 11:05:31.314442 ==
8877 11:05:31.317885 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 11:05:31.320832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 11:05:31.320924 ==
8880 11:05:31.334754
8881 11:05:31.338281 TX Vref early break, caculate TX vref
8882 11:05:31.341327 TX Vref=16, minBit 9, minWin=21, winSum=374
8883 11:05:31.344768 TX Vref=18, minBit 1, minWin=23, winSum=385
8884 11:05:31.348166 TX Vref=20, minBit 9, minWin=22, winSum=391
8885 11:05:31.351187 TX Vref=22, minBit 12, minWin=24, winSum=404
8886 11:05:31.354531 TX Vref=24, minBit 9, minWin=24, winSum=409
8887 11:05:31.361058 TX Vref=26, minBit 9, minWin=24, winSum=416
8888 11:05:31.364561 TX Vref=28, minBit 0, minWin=26, winSum=423
8889 11:05:31.368255 TX Vref=30, minBit 9, minWin=25, winSum=417
8890 11:05:31.371619 TX Vref=32, minBit 0, minWin=25, winSum=415
8891 11:05:31.374326 TX Vref=34, minBit 9, minWin=24, winSum=404
8892 11:05:31.381047 TX Vref=36, minBit 8, minWin=23, winSum=393
8893 11:05:31.384299 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 28
8894 11:05:31.384421
8895 11:05:31.387683 Final TX Range 0 Vref 28
8896 11:05:31.387811
8897 11:05:31.387929 ==
8898 11:05:31.391027 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 11:05:31.394246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 11:05:31.397446 ==
8901 11:05:31.397521
8902 11:05:31.397585
8903 11:05:31.397646 TX Vref Scan disable
8904 11:05:31.404257 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8905 11:05:31.404342 == TX Byte 0 ==
8906 11:05:31.407724 u2DelayCellOfst[0]=14 cells (4 PI)
8907 11:05:31.410895 u2DelayCellOfst[1]=10 cells (3 PI)
8908 11:05:31.414126 u2DelayCellOfst[2]=0 cells (0 PI)
8909 11:05:31.417404 u2DelayCellOfst[3]=3 cells (1 PI)
8910 11:05:31.420396 u2DelayCellOfst[4]=7 cells (2 PI)
8911 11:05:31.424048 u2DelayCellOfst[5]=17 cells (5 PI)
8912 11:05:31.427093 u2DelayCellOfst[6]=17 cells (5 PI)
8913 11:05:31.430311 u2DelayCellOfst[7]=7 cells (2 PI)
8914 11:05:31.433698 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8915 11:05:31.437333 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8916 11:05:31.440551 == TX Byte 1 ==
8917 11:05:31.443968 u2DelayCellOfst[8]=0 cells (0 PI)
8918 11:05:31.446985 u2DelayCellOfst[9]=3 cells (1 PI)
8919 11:05:31.450596 u2DelayCellOfst[10]=10 cells (3 PI)
8920 11:05:31.453503 u2DelayCellOfst[11]=7 cells (2 PI)
8921 11:05:31.457105 u2DelayCellOfst[12]=17 cells (5 PI)
8922 11:05:31.460059 u2DelayCellOfst[13]=17 cells (5 PI)
8923 11:05:31.463196 u2DelayCellOfst[14]=21 cells (6 PI)
8924 11:05:31.463315 u2DelayCellOfst[15]=17 cells (5 PI)
8925 11:05:31.470126 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8926 11:05:31.473199 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8927 11:05:31.476463 DramC Write-DBI on
8928 11:05:31.476587 ==
8929 11:05:31.480111 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 11:05:31.483427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 11:05:31.483553 ==
8932 11:05:31.483670
8933 11:05:31.483775
8934 11:05:31.486559 TX Vref Scan disable
8935 11:05:31.486684 == TX Byte 0 ==
8936 11:05:31.493255 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8937 11:05:31.493378 == TX Byte 1 ==
8938 11:05:31.496460 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8939 11:05:31.499872 DramC Write-DBI off
8940 11:05:31.499994
8941 11:05:31.500108 [DATLAT]
8942 11:05:31.502831 Freq=1600, CH1 RK1
8943 11:05:31.502955
8944 11:05:31.503065 DATLAT Default: 0xf
8945 11:05:31.506146 0, 0xFFFF, sum = 0
8946 11:05:31.509959 1, 0xFFFF, sum = 0
8947 11:05:31.510087 2, 0xFFFF, sum = 0
8948 11:05:31.512904 3, 0xFFFF, sum = 0
8949 11:05:31.513030 4, 0xFFFF, sum = 0
8950 11:05:31.516195 5, 0xFFFF, sum = 0
8951 11:05:31.516319 6, 0xFFFF, sum = 0
8952 11:05:31.519216 7, 0xFFFF, sum = 0
8953 11:05:31.519337 8, 0xFFFF, sum = 0
8954 11:05:31.522735 9, 0xFFFF, sum = 0
8955 11:05:31.522860 10, 0xFFFF, sum = 0
8956 11:05:31.525873 11, 0xFFFF, sum = 0
8957 11:05:31.525998 12, 0xFFFF, sum = 0
8958 11:05:31.529166 13, 0xFFFF, sum = 0
8959 11:05:31.529273 14, 0x0, sum = 1
8960 11:05:31.532826 15, 0x0, sum = 2
8961 11:05:31.532929 16, 0x0, sum = 3
8962 11:05:31.536102 17, 0x0, sum = 4
8963 11:05:31.536201 best_step = 15
8964 11:05:31.536290
8965 11:05:31.536376 ==
8966 11:05:31.539174 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 11:05:31.545983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 11:05:31.546067 ==
8969 11:05:31.546133 RX Vref Scan: 0
8970 11:05:31.546194
8971 11:05:31.549523 RX Vref 0 -> 0, step: 1
8972 11:05:31.549607
8973 11:05:31.552535 RX Delay 11 -> 252, step: 4
8974 11:05:31.556161 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8975 11:05:31.559110 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8976 11:05:31.562291 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8977 11:05:31.568878 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8978 11:05:31.572192 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8979 11:05:31.575765 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8980 11:05:31.578629 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8981 11:05:31.582291 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8982 11:05:31.588487 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8983 11:05:31.591820 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8984 11:05:31.595123 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8985 11:05:31.598470 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8986 11:05:31.605191 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8987 11:05:31.608291 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8988 11:05:31.611687 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8989 11:05:31.614935 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8990 11:05:31.615033 ==
8991 11:05:31.618562 Dram Type= 6, Freq= 0, CH_1, rank 1
8992 11:05:31.625435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8993 11:05:31.625565 ==
8994 11:05:31.625680 DQS Delay:
8995 11:05:31.628217 DQS0 = 0, DQS1 = 0
8996 11:05:31.628339 DQM Delay:
8997 11:05:31.628450 DQM0 = 131, DQM1 = 128
8998 11:05:31.631415 DQ Delay:
8999 11:05:31.634645 DQ0 =136, DQ1 =128, DQ2 =120, DQ3 =128
9000 11:05:31.638164 DQ4 =132, DQ5 =142, DQ6 =140, DQ7 =128
9001 11:05:31.641520 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
9002 11:05:31.644475 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9003 11:05:31.644597
9004 11:05:31.644721
9005 11:05:31.644827
9006 11:05:31.647967 [DramC_TX_OE_Calibration] TA2
9007 11:05:31.651294 Original DQ_B0 (3 6) =30, OEN = 27
9008 11:05:31.654468 Original DQ_B1 (3 6) =30, OEN = 27
9009 11:05:31.657967 24, 0x0, End_B0=24 End_B1=24
9010 11:05:31.660975 25, 0x0, End_B0=25 End_B1=25
9011 11:05:31.661093 26, 0x0, End_B0=26 End_B1=26
9012 11:05:31.665338 27, 0x0, End_B0=27 End_B1=27
9013 11:05:31.667777 28, 0x0, End_B0=28 End_B1=28
9014 11:05:31.670948 29, 0x0, End_B0=29 End_B1=29
9015 11:05:31.671079 30, 0x0, End_B0=30 End_B1=30
9016 11:05:31.674361 31, 0x4141, End_B0=30 End_B1=30
9017 11:05:31.677490 Byte0 end_step=30 best_step=27
9018 11:05:31.681009 Byte1 end_step=30 best_step=27
9019 11:05:31.683894 Byte0 TX OE(2T, 0.5T) = (3, 3)
9020 11:05:31.687540 Byte1 TX OE(2T, 0.5T) = (3, 3)
9021 11:05:31.687641
9022 11:05:31.687741
9023 11:05:31.693995 [DQSOSCAuto] RK1, (LSB)MR18= 0x111e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9024 11:05:31.697164 CH1 RK1: MR19=303, MR18=111E
9025 11:05:31.703856 CH1_RK1: MR19=0x303, MR18=0x111E, DQSOSC=394, MR23=63, INC=23, DEC=15
9026 11:05:31.707382 [RxdqsGatingPostProcess] freq 1600
9027 11:05:31.714227 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9028 11:05:31.714333 best DQS0 dly(2T, 0.5T) = (1, 1)
9029 11:05:31.716968 best DQS1 dly(2T, 0.5T) = (1, 1)
9030 11:05:31.720545 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9031 11:05:31.723340 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9032 11:05:31.727310 best DQS0 dly(2T, 0.5T) = (1, 1)
9033 11:05:31.730195 best DQS1 dly(2T, 0.5T) = (1, 1)
9034 11:05:31.733357 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9035 11:05:31.737055 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9036 11:05:31.739811 Pre-setting of DQS Precalculation
9037 11:05:31.743317 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9038 11:05:31.753251 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9039 11:05:31.759721 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9040 11:05:31.759852
9041 11:05:31.759965
9042 11:05:31.763170 [Calibration Summary] 3200 Mbps
9043 11:05:31.763299 CH 0, Rank 0
9044 11:05:31.766320 SW Impedance : PASS
9045 11:05:31.769595 DUTY Scan : NO K
9046 11:05:31.769680 ZQ Calibration : PASS
9047 11:05:31.773311 Jitter Meter : NO K
9048 11:05:31.776187 CBT Training : PASS
9049 11:05:31.776278 Write leveling : PASS
9050 11:05:31.779372 RX DQS gating : PASS
9051 11:05:31.779483 RX DQ/DQS(RDDQC) : PASS
9052 11:05:31.782656 TX DQ/DQS : PASS
9053 11:05:31.786499 RX DATLAT : PASS
9054 11:05:31.786579 RX DQ/DQS(Engine): PASS
9055 11:05:31.789207 TX OE : PASS
9056 11:05:31.789282 All Pass.
9057 11:05:31.789345
9058 11:05:31.793087 CH 0, Rank 1
9059 11:05:31.793195 SW Impedance : PASS
9060 11:05:31.796040 DUTY Scan : NO K
9061 11:05:31.799358 ZQ Calibration : PASS
9062 11:05:31.799470 Jitter Meter : NO K
9063 11:05:31.802440 CBT Training : PASS
9064 11:05:31.806152 Write leveling : PASS
9065 11:05:31.806235 RX DQS gating : PASS
9066 11:05:31.809276 RX DQ/DQS(RDDQC) : PASS
9067 11:05:31.812531 TX DQ/DQS : PASS
9068 11:05:31.812616 RX DATLAT : PASS
9069 11:05:31.815861 RX DQ/DQS(Engine): PASS
9070 11:05:31.818964 TX OE : PASS
9071 11:05:31.819044 All Pass.
9072 11:05:31.819108
9073 11:05:31.819168 CH 1, Rank 0
9074 11:05:31.822144 SW Impedance : PASS
9075 11:05:31.826143 DUTY Scan : NO K
9076 11:05:31.826230 ZQ Calibration : PASS
9077 11:05:31.829132 Jitter Meter : NO K
9078 11:05:31.832194 CBT Training : PASS
9079 11:05:31.832280 Write leveling : PASS
9080 11:05:31.835370 RX DQS gating : PASS
9081 11:05:31.838601 RX DQ/DQS(RDDQC) : PASS
9082 11:05:31.838693 TX DQ/DQS : PASS
9083 11:05:31.841829 RX DATLAT : PASS
9084 11:05:31.845192 RX DQ/DQS(Engine): PASS
9085 11:05:31.845277 TX OE : PASS
9086 11:05:31.845342 All Pass.
9087 11:05:31.848708
9088 11:05:31.848793 CH 1, Rank 1
9089 11:05:31.851871 SW Impedance : PASS
9090 11:05:31.851948 DUTY Scan : NO K
9091 11:05:31.855249 ZQ Calibration : PASS
9092 11:05:31.858573 Jitter Meter : NO K
9093 11:05:31.858657 CBT Training : PASS
9094 11:05:31.862006 Write leveling : PASS
9095 11:05:31.864853 RX DQS gating : PASS
9096 11:05:31.864936 RX DQ/DQS(RDDQC) : PASS
9097 11:05:31.868392 TX DQ/DQS : PASS
9098 11:05:31.868475 RX DATLAT : PASS
9099 11:05:31.871660 RX DQ/DQS(Engine): PASS
9100 11:05:31.874867 TX OE : PASS
9101 11:05:31.874950 All Pass.
9102 11:05:31.875016
9103 11:05:31.878153 DramC Write-DBI on
9104 11:05:31.881469 PER_BANK_REFRESH: Hybrid Mode
9105 11:05:31.881551 TX_TRACKING: ON
9106 11:05:31.891305 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9107 11:05:31.897858 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9108 11:05:31.904411 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9109 11:05:31.907669 [FAST_K] Save calibration result to emmc
9110 11:05:31.911291 sync common calibartion params.
9111 11:05:31.914462 sync cbt_mode0:1, 1:1
9112 11:05:31.918077 dram_init: ddr_geometry: 2
9113 11:05:31.918200 dram_init: ddr_geometry: 2
9114 11:05:31.920908 dram_init: ddr_geometry: 2
9115 11:05:31.923869 0:dram_rank_size:100000000
9116 11:05:31.927177 1:dram_rank_size:100000000
9117 11:05:31.930619 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9118 11:05:31.933955 DFS_SHUFFLE_HW_MODE: ON
9119 11:05:31.937601 dramc_set_vcore_voltage set vcore to 725000
9120 11:05:31.940414 Read voltage for 1600, 0
9121 11:05:31.940570 Vio18 = 0
9122 11:05:31.940682 Vcore = 725000
9123 11:05:31.944031 Vdram = 0
9124 11:05:31.944114 Vddq = 0
9125 11:05:31.944194 Vmddr = 0
9126 11:05:31.947128 switch to 3200 Mbps bootup
9127 11:05:31.950421 [DramcRunTimeConfig]
9128 11:05:31.950503 PHYPLL
9129 11:05:31.950568 DPM_CONTROL_AFTERK: ON
9130 11:05:31.953557 PER_BANK_REFRESH: ON
9131 11:05:31.957023 REFRESH_OVERHEAD_REDUCTION: ON
9132 11:05:31.957104 CMD_PICG_NEW_MODE: OFF
9133 11:05:31.960512 XRTWTW_NEW_MODE: ON
9134 11:05:31.963487 XRTRTR_NEW_MODE: ON
9135 11:05:31.963569 TX_TRACKING: ON
9136 11:05:31.967258 RDSEL_TRACKING: OFF
9137 11:05:31.967356 DQS Precalculation for DVFS: ON
9138 11:05:31.970025 RX_TRACKING: OFF
9139 11:05:31.970107 HW_GATING DBG: ON
9140 11:05:31.973532 ZQCS_ENABLE_LP4: ON
9141 11:05:31.976571 RX_PICG_NEW_MODE: ON
9142 11:05:31.976700 TX_PICG_NEW_MODE: ON
9143 11:05:31.980314 ENABLE_RX_DCM_DPHY: ON
9144 11:05:31.983186 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9145 11:05:31.983270 DUMMY_READ_FOR_TRACKING: OFF
9146 11:05:31.986859 !!! SPM_CONTROL_AFTERK: OFF
9147 11:05:31.989862 !!! SPM could not control APHY
9148 11:05:31.993257 IMPEDANCE_TRACKING: ON
9149 11:05:31.993341 TEMP_SENSOR: ON
9150 11:05:31.996584 HW_SAVE_FOR_SR: OFF
9151 11:05:31.999662 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9152 11:05:32.002992 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9153 11:05:32.003114 Read ODT Tracking: ON
9154 11:05:32.006418 Refresh Rate DeBounce: ON
9155 11:05:32.010166 DFS_NO_QUEUE_FLUSH: ON
9156 11:05:32.013433 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9157 11:05:32.013517 ENABLE_DFS_RUNTIME_MRW: OFF
9158 11:05:32.016278 DDR_RESERVE_NEW_MODE: ON
9159 11:05:32.019492 MR_CBT_SWITCH_FREQ: ON
9160 11:05:32.019576 =========================
9161 11:05:32.039702 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9162 11:05:32.042702 dram_init: ddr_geometry: 2
9163 11:05:32.061641 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9164 11:05:32.064740 dram_init: dram init end (result: 0)
9165 11:05:32.071005 DRAM-K: Full calibration passed in 24416 msecs
9166 11:05:32.074412 MRC: failed to locate region type 0.
9167 11:05:32.074508 DRAM rank0 size:0x100000000,
9168 11:05:32.077622 DRAM rank1 size=0x100000000
9169 11:05:32.087608 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9170 11:05:32.094163 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9171 11:05:32.100602 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9172 11:05:32.110595 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9173 11:05:32.110680 DRAM rank0 size:0x100000000,
9174 11:05:32.113979 DRAM rank1 size=0x100000000
9175 11:05:32.114062 CBMEM:
9176 11:05:32.117550 IMD: root @ 0xfffff000 254 entries.
9177 11:05:32.120903 IMD: root @ 0xffffec00 62 entries.
9178 11:05:32.123893 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9179 11:05:32.130313 WARNING: RO_VPD is uninitialized or empty.
9180 11:05:32.133687 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9181 11:05:32.141194 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9182 11:05:32.153763 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9183 11:05:32.165764 BS: romstage times (exec / console): total (unknown) / 23944 ms
9184 11:05:32.165857
9185 11:05:32.165943
9186 11:05:32.175090 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9187 11:05:32.178564 ARM64: Exception handlers installed.
9188 11:05:32.181859 ARM64: Testing exception
9189 11:05:32.185012 ARM64: Done test exception
9190 11:05:32.185097 Enumerating buses...
9191 11:05:32.188509 Show all devs... Before device enumeration.
9192 11:05:32.191613 Root Device: enabled 1
9193 11:05:32.194809 CPU_CLUSTER: 0: enabled 1
9194 11:05:32.194895 CPU: 00: enabled 1
9195 11:05:32.198332 Compare with tree...
9196 11:05:32.198443 Root Device: enabled 1
9197 11:05:32.201625 CPU_CLUSTER: 0: enabled 1
9198 11:05:32.204700 CPU: 00: enabled 1
9199 11:05:32.204787 Root Device scanning...
9200 11:05:32.208307 scan_static_bus for Root Device
9201 11:05:32.211373 CPU_CLUSTER: 0 enabled
9202 11:05:32.215074 scan_static_bus for Root Device done
9203 11:05:32.217897 scan_bus: bus Root Device finished in 8 msecs
9204 11:05:32.217985 done
9205 11:05:32.224869 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9206 11:05:32.227613 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9207 11:05:32.234480 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9208 11:05:32.241290 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9209 11:05:32.241418 Allocating resources...
9210 11:05:32.244583 Reading resources...
9211 11:05:32.247586 Root Device read_resources bus 0 link: 0
9212 11:05:32.251454 DRAM rank0 size:0x100000000,
9213 11:05:32.251571 DRAM rank1 size=0x100000000
9214 11:05:32.257322 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9215 11:05:32.257446 CPU: 00 missing read_resources
9216 11:05:32.263740 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9217 11:05:32.267269 Root Device read_resources bus 0 link: 0 done
9218 11:05:32.270587 Done reading resources.
9219 11:05:32.273658 Show resources in subtree (Root Device)...After reading.
9220 11:05:32.276829 Root Device child on link 0 CPU_CLUSTER: 0
9221 11:05:32.280583 CPU_CLUSTER: 0 child on link 0 CPU: 00
9222 11:05:32.290186 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9223 11:05:32.290291 CPU: 00
9224 11:05:32.296669 Root Device assign_resources, bus 0 link: 0
9225 11:05:32.299907 CPU_CLUSTER: 0 missing set_resources
9226 11:05:32.303276 Root Device assign_resources, bus 0 link: 0 done
9227 11:05:32.306595 Done setting resources.
9228 11:05:32.310000 Show resources in subtree (Root Device)...After assigning values.
9229 11:05:32.316503 Root Device child on link 0 CPU_CLUSTER: 0
9230 11:05:32.319690 CPU_CLUSTER: 0 child on link 0 CPU: 00
9231 11:05:32.326249 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9232 11:05:32.329892 CPU: 00
9233 11:05:32.329975 Done allocating resources.
9234 11:05:32.336156 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9235 11:05:32.336241 Enabling resources...
9236 11:05:32.339723 done.
9237 11:05:32.342935 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9238 11:05:32.346649 Initializing devices...
9239 11:05:32.346729 Root Device init
9240 11:05:32.349790 init hardware done!
9241 11:05:32.349864 0x00000018: ctrlr->caps
9242 11:05:32.353087 52.000 MHz: ctrlr->f_max
9243 11:05:32.356526 0.400 MHz: ctrlr->f_min
9244 11:05:32.359623 0x40ff8080: ctrlr->voltages
9245 11:05:32.359720 sclk: 390625
9246 11:05:32.359815 Bus Width = 1
9247 11:05:32.362796 sclk: 390625
9248 11:05:32.362883 Bus Width = 1
9249 11:05:32.366126 Early init status = 3
9250 11:05:32.369076 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9251 11:05:32.373688 in-header: 03 fc 00 00 01 00 00 00
9252 11:05:32.377283 in-data: 00
9253 11:05:32.380627 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9254 11:05:32.386068 in-header: 03 fd 00 00 00 00 00 00
9255 11:05:32.389189 in-data:
9256 11:05:32.392499 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9257 11:05:32.397239 in-header: 03 fc 00 00 01 00 00 00
9258 11:05:32.400345 in-data: 00
9259 11:05:32.403889 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9260 11:05:32.409564 in-header: 03 fd 00 00 00 00 00 00
9261 11:05:32.412883 in-data:
9262 11:05:32.415905 [SSUSB] Setting up USB HOST controller...
9263 11:05:32.419248 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9264 11:05:32.422619 [SSUSB] phy power-on done.
9265 11:05:32.426176 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9266 11:05:32.432385 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9267 11:05:32.435699 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9268 11:05:32.442155 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9269 11:05:32.448622 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9270 11:05:32.455478 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9271 11:05:32.461809 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9272 11:05:32.468317 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9273 11:05:32.472182 SPM: binary array size = 0x9dc
9274 11:05:32.475074 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9275 11:05:32.481575 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9276 11:05:32.488442 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9277 11:05:32.494792 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9278 11:05:32.498056 configure_display: Starting display init
9279 11:05:32.532480 anx7625_power_on_init: Init interface.
9280 11:05:32.536244 anx7625_disable_pd_protocol: Disabled PD feature.
9281 11:05:32.539438 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9282 11:05:32.566948 anx7625_start_dp_work: Secure OCM version=00
9283 11:05:32.570195 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9284 11:05:32.585778 sp_tx_get_edid_block: EDID Block = 1
9285 11:05:32.687662 Extracted contents:
9286 11:05:32.691130 header: 00 ff ff ff ff ff ff 00
9287 11:05:32.694273 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9288 11:05:32.697475 version: 01 04
9289 11:05:32.700631 basic params: 95 1f 11 78 0a
9290 11:05:32.704310 chroma info: 76 90 94 55 54 90 27 21 50 54
9291 11:05:32.707556 established: 00 00 00
9292 11:05:32.713970 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9293 11:05:32.721138 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9294 11:05:32.723589 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9295 11:05:32.730590 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9296 11:05:32.737016 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9297 11:05:32.740075 extensions: 00
9298 11:05:32.740157 checksum: fb
9299 11:05:32.740222
9300 11:05:32.747008 Manufacturer: IVO Model 57d Serial Number 0
9301 11:05:32.747110 Made week 0 of 2020
9302 11:05:32.750513 EDID version: 1.4
9303 11:05:32.750596 Digital display
9304 11:05:32.753275 6 bits per primary color channel
9305 11:05:32.756494 DisplayPort interface
9306 11:05:32.756576 Maximum image size: 31 cm x 17 cm
9307 11:05:32.760019 Gamma: 220%
9308 11:05:32.760101 Check DPMS levels
9309 11:05:32.766878 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9310 11:05:32.769759 First detailed timing is preferred timing
9311 11:05:32.772984 Established timings supported:
9312 11:05:32.773067 Standard timings supported:
9313 11:05:32.776766 Detailed timings
9314 11:05:32.779512 Hex of detail: 383680a07038204018303c0035ae10000019
9315 11:05:32.786568 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9316 11:05:32.790203 0780 0798 07c8 0820 hborder 0
9317 11:05:32.792578 0438 043b 0447 0458 vborder 0
9318 11:05:32.795863 -hsync -vsync
9319 11:05:32.795988 Did detailed timing
9320 11:05:32.802662 Hex of detail: 000000000000000000000000000000000000
9321 11:05:32.806318 Manufacturer-specified data, tag 0
9322 11:05:32.809042 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9323 11:05:32.812552 ASCII string: InfoVision
9324 11:05:32.815952 Hex of detail: 000000fe00523134304e574635205248200a
9325 11:05:32.819278 ASCII string: R140NWF5 RH
9326 11:05:32.819411 Checksum
9327 11:05:32.822401 Checksum: 0xfb (valid)
9328 11:05:32.825976 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9329 11:05:32.829137 DSI data_rate: 832800000 bps
9330 11:05:32.836021 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9331 11:05:32.839094 anx7625_parse_edid: pixelclock(138800).
9332 11:05:32.842192 hactive(1920), hsync(48), hfp(24), hbp(88)
9333 11:05:32.845196 vactive(1080), vsync(12), vfp(3), vbp(17)
9334 11:05:32.848531 anx7625_dsi_config: config dsi.
9335 11:05:32.855251 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9336 11:05:32.870790 anx7625_dsi_config: success to config DSI
9337 11:05:32.873394 anx7625_dp_start: MIPI phy setup OK.
9338 11:05:32.876247 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9339 11:05:32.879731 mtk_ddp_mode_set invalid vrefresh 60
9340 11:05:32.883452 main_disp_path_setup
9341 11:05:32.883562 ovl_layer_smi_id_en
9342 11:05:32.886108 ovl_layer_smi_id_en
9343 11:05:32.886190 ccorr_config
9344 11:05:32.886254 aal_config
9345 11:05:32.889500 gamma_config
9346 11:05:32.889581 postmask_config
9347 11:05:32.892621 dither_config
9348 11:05:32.895848 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9349 11:05:32.902724 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9350 11:05:32.905822 Root Device init finished in 555 msecs
9351 11:05:32.909310 CPU_CLUSTER: 0 init
9352 11:05:32.915801 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9353 11:05:32.922413 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9354 11:05:32.922496 APU_MBOX 0x190000b0 = 0x10001
9355 11:05:32.926415 APU_MBOX 0x190001b0 = 0x10001
9356 11:05:32.929312 APU_MBOX 0x190005b0 = 0x10001
9357 11:05:32.932421 APU_MBOX 0x190006b0 = 0x10001
9358 11:05:32.939055 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9359 11:05:32.948705 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9360 11:05:32.960833 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9361 11:05:32.967863 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9362 11:05:32.979225 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9363 11:05:32.988667 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9364 11:05:32.992238 CPU_CLUSTER: 0 init finished in 81 msecs
9365 11:05:32.995302 Devices initialized
9366 11:05:32.998261 Show all devs... After init.
9367 11:05:32.998345 Root Device: enabled 1
9368 11:05:33.001633 CPU_CLUSTER: 0: enabled 1
9369 11:05:33.004883 CPU: 00: enabled 1
9370 11:05:33.009095 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9371 11:05:33.011678 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9372 11:05:33.015018 ELOG: NV offset 0x57f000 size 0x1000
9373 11:05:33.022204 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9374 11:05:33.028258 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9375 11:05:33.031705 ELOG: Event(17) added with size 13 at 2024-03-03 11:05:34 UTC
9376 11:05:33.034647 out: cmd=0x121: 03 db 21 01 00 00 00 00
9377 11:05:33.039054 in-header: 03 33 00 00 2c 00 00 00
9378 11:05:33.051749 in-data: 2c 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9379 11:05:33.058548 ELOG: Event(A1) added with size 10 at 2024-03-03 11:05:34 UTC
9380 11:05:33.064896 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9381 11:05:33.071592 ELOG: Event(A0) added with size 9 at 2024-03-03 11:05:34 UTC
9382 11:05:33.074909 elog_add_boot_reason: Logged dev mode boot
9383 11:05:33.077997 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9384 11:05:33.081721 Finalize devices...
9385 11:05:33.081802 Devices finalized
9386 11:05:33.087973 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9387 11:05:33.091457 Writing coreboot table at 0xffe64000
9388 11:05:33.095109 0. 000000000010a000-0000000000113fff: RAMSTAGE
9389 11:05:33.098008 1. 0000000040000000-00000000400fffff: RAM
9390 11:05:33.104538 2. 0000000040100000-000000004032afff: RAMSTAGE
9391 11:05:33.107694 3. 000000004032b000-00000000545fffff: RAM
9392 11:05:33.110987 4. 0000000054600000-000000005465ffff: BL31
9393 11:05:33.114466 5. 0000000054660000-00000000ffe63fff: RAM
9394 11:05:33.121195 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9395 11:05:33.124259 7. 0000000100000000-000000023fffffff: RAM
9396 11:05:33.127542 Passing 5 GPIOs to payload:
9397 11:05:33.130823 NAME | PORT | POLARITY | VALUE
9398 11:05:33.137233 EC in RW | 0x000000aa | low | undefined
9399 11:05:33.140499 EC interrupt | 0x00000005 | low | undefined
9400 11:05:33.143719 TPM interrupt | 0x000000ab | high | undefined
9401 11:05:33.150591 SD card detect | 0x00000011 | high | undefined
9402 11:05:33.154134 speaker enable | 0x00000093 | high | undefined
9403 11:05:33.157317 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9404 11:05:33.160807 in-header: 03 f9 00 00 02 00 00 00
9405 11:05:33.164687 in-data: 02 00
9406 11:05:33.167515 ADC[4]: Raw value=902955 ID=7
9407 11:05:33.170837 ADC[3]: Raw value=213546 ID=1
9408 11:05:33.170919 RAM Code: 0x71
9409 11:05:33.173847 ADC[6]: Raw value=74630 ID=0
9410 11:05:33.177845 ADC[5]: Raw value=213916 ID=1
9411 11:05:33.177928 SKU Code: 0x1
9412 11:05:33.184192 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7483
9413 11:05:33.184275 coreboot table: 964 bytes.
9414 11:05:33.187408 IMD ROOT 0. 0xfffff000 0x00001000
9415 11:05:33.190346 IMD SMALL 1. 0xffffe000 0x00001000
9416 11:05:33.193494 RO MCACHE 2. 0xffffc000 0x00001104
9417 11:05:33.197096 CONSOLE 3. 0xfff7c000 0x00080000
9418 11:05:33.200729 FMAP 4. 0xfff7b000 0x00000452
9419 11:05:33.203561 TIME STAMP 5. 0xfff7a000 0x00000910
9420 11:05:33.207177 VBOOT WORK 6. 0xfff66000 0x00014000
9421 11:05:33.210441 RAMOOPS 7. 0xffe66000 0x00100000
9422 11:05:33.213650 COREBOOT 8. 0xffe64000 0x00002000
9423 11:05:33.216834 IMD small region:
9424 11:05:33.220422 IMD ROOT 0. 0xffffec00 0x00000400
9425 11:05:33.223544 VPD 1. 0xffffeb80 0x0000006c
9426 11:05:33.226600 MMC STATUS 2. 0xffffeb60 0x00000004
9427 11:05:33.233125 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9428 11:05:33.233209 Probing TPM: done!
9429 11:05:33.240440 Connected to device vid:did:rid of 1ae0:0028:00
9430 11:05:33.247072 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9431 11:05:33.250194 Initialized TPM device CR50 revision 0
9432 11:05:33.253495 Checking cr50 for pending updates
9433 11:05:33.259050 Reading cr50 TPM mode
9434 11:05:33.267754 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9435 11:05:33.274351 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9436 11:05:33.314211 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9437 11:05:33.317688 Checking segment from ROM address 0x40100000
9438 11:05:33.324277 Checking segment from ROM address 0x4010001c
9439 11:05:33.327730 Loading segment from ROM address 0x40100000
9440 11:05:33.327813 code (compression=0)
9441 11:05:33.337381 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9442 11:05:33.344077 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9443 11:05:33.344162 it's not compressed!
9444 11:05:33.350541 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9445 11:05:33.357385 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9446 11:05:33.374982 Loading segment from ROM address 0x4010001c
9447 11:05:33.375066 Entry Point 0x80000000
9448 11:05:33.378036 Loaded segments
9449 11:05:33.381666 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9450 11:05:33.388015 Jumping to boot code at 0x80000000(0xffe64000)
9451 11:05:33.395017 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9452 11:05:33.401587 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9453 11:05:33.409520 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9454 11:05:33.412660 Checking segment from ROM address 0x40100000
9455 11:05:33.415637 Checking segment from ROM address 0x4010001c
9456 11:05:33.422163 Loading segment from ROM address 0x40100000
9457 11:05:33.422246 code (compression=1)
9458 11:05:33.428966 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9459 11:05:33.438767 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9460 11:05:33.438882 using LZMA
9461 11:05:33.447771 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9462 11:05:33.454378 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9463 11:05:33.457438 Loading segment from ROM address 0x4010001c
9464 11:05:33.457553 Entry Point 0x54601000
9465 11:05:33.460834 Loaded segments
9466 11:05:33.464372 NOTICE: MT8192 bl31_setup
9467 11:05:33.471333 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9468 11:05:33.474494 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9469 11:05:33.477712 WARNING: region 0:
9470 11:05:33.481450 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 11:05:33.481580 WARNING: region 1:
9472 11:05:33.487669 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9473 11:05:33.490948 WARNING: region 2:
9474 11:05:33.494487 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9475 11:05:33.497499 WARNING: region 3:
9476 11:05:33.500942 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9477 11:05:33.504716 WARNING: region 4:
9478 11:05:33.511023 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9479 11:05:33.511111 WARNING: region 5:
9480 11:05:33.514226 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 11:05:33.517304 WARNING: region 6:
9482 11:05:33.520745 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 11:05:33.524353 WARNING: region 7:
9484 11:05:33.527485 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 11:05:33.534297 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9486 11:05:33.537505 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9487 11:05:33.540620 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9488 11:05:33.547196 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9489 11:05:33.550667 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9490 11:05:33.557618 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9491 11:05:33.560635 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9492 11:05:33.564089 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9493 11:05:33.570827 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9494 11:05:33.574219 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9495 11:05:33.577060 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9496 11:05:33.583895 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9497 11:05:33.587166 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9498 11:05:33.593619 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9499 11:05:33.597384 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9500 11:05:33.600614 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9501 11:05:33.607271 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9502 11:05:33.610323 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9503 11:05:33.617181 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9504 11:05:33.620330 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9505 11:05:33.623554 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9506 11:05:33.630518 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9507 11:05:33.633583 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9508 11:05:33.636885 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9509 11:05:33.643603 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9510 11:05:33.646703 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9511 11:05:33.653793 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9512 11:05:33.656970 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9513 11:05:33.663706 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9514 11:05:33.666920 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9515 11:05:33.670224 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9516 11:05:33.676955 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9517 11:05:33.680010 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9518 11:05:33.683259 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9519 11:05:33.687096 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9520 11:05:33.693182 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9521 11:05:33.696873 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9522 11:05:33.700068 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9523 11:05:33.703232 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9524 11:05:33.709743 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9525 11:05:33.713621 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9526 11:05:33.716683 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9527 11:05:33.719903 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9528 11:05:33.726258 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9529 11:05:33.729888 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9530 11:05:33.732892 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9531 11:05:33.740111 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9532 11:05:33.743009 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9533 11:05:33.746189 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9534 11:05:33.752984 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9535 11:05:33.756232 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9536 11:05:33.762599 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9537 11:05:33.766141 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9538 11:05:33.769288 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9539 11:05:33.775974 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9540 11:05:33.779833 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9541 11:05:33.786044 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9542 11:05:33.789199 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9543 11:05:33.796420 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9544 11:05:33.799323 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9545 11:05:33.805938 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9546 11:05:33.808879 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9547 11:05:33.812393 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9548 11:05:33.818968 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9549 11:05:33.822321 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9550 11:05:33.829111 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9551 11:05:33.832364 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9552 11:05:33.839208 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9553 11:05:33.842303 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9554 11:05:33.845396 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9555 11:05:33.852082 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9556 11:05:33.855517 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9557 11:05:33.862318 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9558 11:05:33.865742 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9559 11:05:33.872139 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9560 11:05:33.875178 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9561 11:05:33.881989 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9562 11:05:33.885428 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9563 11:05:33.888751 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9564 11:05:33.895529 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9565 11:05:33.898973 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9566 11:05:33.905191 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9567 11:05:33.908784 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9568 11:05:33.915157 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9569 11:05:33.918523 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9570 11:05:33.921591 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9571 11:05:33.928461 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9572 11:05:33.931655 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9573 11:05:33.938218 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9574 11:05:33.941654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9575 11:05:33.948283 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9576 11:05:33.951315 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9577 11:05:33.958570 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9578 11:05:33.961524 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9579 11:05:33.964932 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9580 11:05:33.971536 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9581 11:05:33.974882 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9582 11:05:33.977935 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9583 11:05:33.984955 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9584 11:05:33.988315 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9585 11:05:33.991224 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9586 11:05:33.998265 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9587 11:05:34.001073 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9588 11:05:34.007962 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9589 11:05:34.011373 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9590 11:05:34.014509 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9591 11:05:34.021028 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9592 11:05:34.024519 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9593 11:05:34.031023 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9594 11:05:34.034471 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9595 11:05:34.037766 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9596 11:05:34.044326 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9597 11:05:34.047445 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9598 11:05:34.054135 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9599 11:05:34.057281 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9600 11:05:34.060834 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9601 11:05:34.064100 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9602 11:05:34.070734 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9603 11:05:34.074068 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9604 11:05:34.077191 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9605 11:05:34.083722 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9606 11:05:34.087403 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9607 11:05:34.090727 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9608 11:05:34.093953 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9609 11:05:34.100519 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9610 11:05:34.103739 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9611 11:05:34.110539 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9612 11:05:34.113703 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9613 11:05:34.120378 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9614 11:05:34.123542 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9615 11:05:34.127221 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9616 11:05:34.133684 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9617 11:05:34.137216 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9618 11:05:34.140130 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9619 11:05:34.146916 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9620 11:05:34.150173 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9621 11:05:34.156934 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9622 11:05:34.160380 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9623 11:05:34.163189 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9624 11:05:34.169913 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9625 11:05:34.173431 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9626 11:05:34.180184 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9627 11:05:34.183240 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9628 11:05:34.186455 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9629 11:05:34.193064 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9630 11:05:34.196475 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9631 11:05:34.202924 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9632 11:05:34.206236 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9633 11:05:34.209745 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9634 11:05:34.216158 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9635 11:05:34.219378 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9636 11:05:34.226182 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9637 11:05:34.229347 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9638 11:05:34.232993 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9639 11:05:34.239601 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9640 11:05:34.242622 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9641 11:05:34.249895 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9642 11:05:34.252803 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9643 11:05:34.256079 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9644 11:05:34.262731 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9645 11:05:34.266097 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9646 11:05:34.269211 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9647 11:05:34.276016 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9648 11:05:34.279640 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9649 11:05:34.285950 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9650 11:05:34.289494 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9651 11:05:34.292433 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9652 11:05:34.299040 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9653 11:05:34.302390 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9654 11:05:34.308499 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9655 11:05:34.311845 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9656 11:05:34.318677 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9657 11:05:34.322044 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9658 11:05:34.325202 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9659 11:05:34.332178 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9660 11:05:34.335185 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9661 11:05:34.341711 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9662 11:05:34.344736 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9663 11:05:34.348758 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9664 11:05:34.354786 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9665 11:05:34.358028 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9666 11:05:34.364817 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9667 11:05:34.368192 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9668 11:05:34.371285 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9669 11:05:34.378115 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9670 11:05:34.381311 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9671 11:05:34.384481 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9672 11:05:34.391388 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9673 11:05:34.394748 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9674 11:05:34.401438 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9675 11:05:34.404316 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9676 11:05:34.411111 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9677 11:05:34.414163 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9678 11:05:34.417357 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9679 11:05:34.424048 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9680 11:05:34.427327 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9681 11:05:34.433976 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9682 11:05:34.439142 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9683 11:05:34.443939 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9684 11:05:34.446965 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9685 11:05:34.450668 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9686 11:05:34.457298 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9687 11:05:34.460499 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9688 11:05:34.466971 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9689 11:05:34.470302 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9690 11:05:34.477052 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9691 11:05:34.480397 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9692 11:05:34.483218 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9693 11:05:34.490064 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9694 11:05:34.493251 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9695 11:05:34.499742 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9696 11:05:34.502996 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9697 11:05:34.509775 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9698 11:05:34.513243 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9699 11:05:34.516460 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9700 11:05:34.522914 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9701 11:05:34.526368 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9702 11:05:34.533043 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9703 11:05:34.536000 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9704 11:05:34.542409 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9705 11:05:34.546131 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9706 11:05:34.549614 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9707 11:05:34.555533 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9708 11:05:34.559131 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9709 11:05:34.565726 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9710 11:05:34.568857 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9711 11:05:34.575319 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9712 11:05:34.578597 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9713 11:05:34.582240 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9714 11:05:34.588941 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9715 11:05:34.591923 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9716 11:05:34.595475 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9717 11:05:34.598571 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9718 11:05:34.605110 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9719 11:05:34.608247 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9720 11:05:34.612102 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9721 11:05:34.618423 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9722 11:05:34.621640 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9723 11:05:34.628139 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9724 11:05:34.631620 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9725 11:05:34.634885 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9726 11:05:34.641633 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9727 11:05:34.644414 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9728 11:05:34.647668 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9729 11:05:34.654436 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9730 11:05:34.657710 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9731 11:05:34.664478 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9732 11:05:34.667518 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9733 11:05:34.671235 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9734 11:05:34.677911 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9735 11:05:34.681177 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9736 11:05:34.687597 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9737 11:05:34.690621 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9738 11:05:34.693914 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9739 11:05:34.700374 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9740 11:05:34.703937 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9741 11:05:34.706805 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9742 11:05:34.713531 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9743 11:05:34.716760 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9744 11:05:34.723357 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9745 11:05:34.726488 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9746 11:05:34.730000 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9747 11:05:34.736437 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9748 11:05:34.739911 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9749 11:05:34.743018 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9750 11:05:34.749397 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9751 11:05:34.752749 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9752 11:05:34.759592 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9753 11:05:34.762507 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9754 11:05:34.765991 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9755 11:05:34.769570 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9756 11:05:34.776109 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9757 11:05:34.779168 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9758 11:05:34.782713 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9759 11:05:34.785885 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9760 11:05:34.792161 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9761 11:05:34.795545 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9762 11:05:34.798953 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9763 11:05:34.802305 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9764 11:05:34.808723 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9765 11:05:34.812007 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9766 11:05:34.815336 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9767 11:05:34.821774 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9768 11:05:34.825589 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9769 11:05:34.831935 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9770 11:05:34.834797 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9771 11:05:34.841640 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9772 11:05:34.844616 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9773 11:05:34.848159 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9774 11:05:34.854692 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9775 11:05:34.858089 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9776 11:05:34.864759 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9777 11:05:34.867795 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9778 11:05:34.874348 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9779 11:05:34.877437 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9780 11:05:34.881266 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9781 11:05:34.888000 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9782 11:05:34.890898 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9783 11:05:34.897606 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9784 11:05:34.900761 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9785 11:05:34.903833 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9786 11:05:34.910809 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9787 11:05:34.914226 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9788 11:05:34.920580 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9789 11:05:34.924154 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9790 11:05:34.926966 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9791 11:05:34.933855 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9792 11:05:34.936745 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9793 11:05:34.943882 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9794 11:05:34.947158 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9795 11:05:34.953423 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9796 11:05:34.956683 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9797 11:05:34.963476 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9798 11:05:34.966523 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9799 11:05:34.969936 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9800 11:05:34.976355 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9801 11:05:34.979569 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9802 11:05:34.985999 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9803 11:05:34.989305 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9804 11:05:34.993355 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9805 11:05:34.999323 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9806 11:05:35.002577 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9807 11:05:35.009575 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9808 11:05:35.012737 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9809 11:05:35.018945 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9810 11:05:35.022568 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9811 11:05:35.025703 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9812 11:05:35.032355 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9813 11:05:35.035563 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9814 11:05:35.042234 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9815 11:05:35.045439 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9816 11:05:35.048806 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9817 11:05:35.055388 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9818 11:05:35.058478 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9819 11:05:35.065361 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9820 11:05:35.068243 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9821 11:05:35.074801 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9822 11:05:35.078482 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9823 11:05:35.081563 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9824 11:05:35.088302 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9825 11:05:35.091620 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9826 11:05:35.097760 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9827 11:05:35.101177 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9828 11:05:35.107903 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9829 11:05:35.111338 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9830 11:05:35.114272 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9831 11:05:35.120767 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9832 11:05:35.124058 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9833 11:05:35.131099 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9834 11:05:35.133902 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9835 11:05:35.140468 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9836 11:05:35.143764 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9837 11:05:35.150084 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9838 11:05:35.153726 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9839 11:05:35.156798 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9840 11:05:35.163514 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9841 11:05:35.166973 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9842 11:05:35.173525 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9843 11:05:35.176593 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9844 11:05:35.183203 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9845 11:05:35.186718 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9846 11:05:35.190309 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9847 11:05:35.196160 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9848 11:05:35.199682 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9849 11:05:35.206272 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9850 11:05:35.209453 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9851 11:05:35.216153 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9852 11:05:35.219478 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9853 11:05:35.226090 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9854 11:05:35.229026 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9855 11:05:35.233146 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9856 11:05:35.238906 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9857 11:05:35.242629 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9858 11:05:35.248835 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9859 11:05:35.252444 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9860 11:05:35.258830 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9861 11:05:35.261903 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9862 11:05:35.268605 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9863 11:05:35.272090 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9864 11:05:35.275202 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9865 11:05:35.281625 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9866 11:05:35.285001 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9867 11:05:35.291724 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9868 11:05:35.295158 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9869 11:05:35.301546 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9870 11:05:35.305278 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9871 11:05:35.311489 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9872 11:05:35.314764 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9873 11:05:35.321600 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9874 11:05:35.324512 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9875 11:05:35.327795 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9876 11:05:35.334864 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9877 11:05:35.338145 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9878 11:05:35.344283 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9879 11:05:35.348019 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9880 11:05:35.354415 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9881 11:05:35.357660 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9882 11:05:35.364032 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9883 11:05:35.367977 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9884 11:05:35.370847 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9885 11:05:35.377281 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9886 11:05:35.380374 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9887 11:05:35.386939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9888 11:05:35.390366 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9889 11:05:35.397604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9890 11:05:35.400191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9891 11:05:35.406844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9892 11:05:35.410138 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9893 11:05:35.416946 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9894 11:05:35.420290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9895 11:05:35.426644 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9896 11:05:35.429808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9897 11:05:35.436478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9898 11:05:35.440093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9899 11:05:35.442845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9900 11:05:35.450120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9901 11:05:35.453361 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9902 11:05:35.459269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9903 11:05:35.463032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9904 11:05:35.469294 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9905 11:05:35.473115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9906 11:05:35.479267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9907 11:05:35.482368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9908 11:05:35.489073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9909 11:05:35.492705 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9910 11:05:35.499403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9911 11:05:35.505555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9912 11:05:35.509246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9913 11:05:35.515340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9914 11:05:35.518794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9915 11:05:35.525173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9916 11:05:35.528593 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9917 11:05:35.535240 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9918 11:05:35.538186 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9919 11:05:35.541452 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9920 11:05:35.545002 INFO: [APUAPC] vio 0
9921 11:05:35.551626 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9922 11:05:35.554985 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9923 11:05:35.557967 INFO: [APUAPC] D0_APC_0: 0x400510
9924 11:05:35.561124 INFO: [APUAPC] D0_APC_1: 0x0
9925 11:05:35.564606 INFO: [APUAPC] D0_APC_2: 0x1540
9926 11:05:35.567886 INFO: [APUAPC] D0_APC_3: 0x0
9927 11:05:35.571265 INFO: [APUAPC] D1_APC_0: 0xffffffff
9928 11:05:35.574696 INFO: [APUAPC] D1_APC_1: 0xffffffff
9929 11:05:35.577900 INFO: [APUAPC] D1_APC_2: 0x3fffff
9930 11:05:35.581447 INFO: [APUAPC] D1_APC_3: 0x0
9931 11:05:35.584234 INFO: [APUAPC] D2_APC_0: 0xffffffff
9932 11:05:35.587721 INFO: [APUAPC] D2_APC_1: 0xffffffff
9933 11:05:35.591295 INFO: [APUAPC] D2_APC_2: 0x3fffff
9934 11:05:35.594120 INFO: [APUAPC] D2_APC_3: 0x0
9935 11:05:35.597595 INFO: [APUAPC] D3_APC_0: 0xffffffff
9936 11:05:35.600675 INFO: [APUAPC] D3_APC_1: 0xffffffff
9937 11:05:35.604711 INFO: [APUAPC] D3_APC_2: 0x3fffff
9938 11:05:35.607684 INFO: [APUAPC] D3_APC_3: 0x0
9939 11:05:35.610827 INFO: [APUAPC] D4_APC_0: 0xffffffff
9940 11:05:35.614529 INFO: [APUAPC] D4_APC_1: 0xffffffff
9941 11:05:35.617520 INFO: [APUAPC] D4_APC_2: 0x3fffff
9942 11:05:35.617649 INFO: [APUAPC] D4_APC_3: 0x0
9943 11:05:35.624196 INFO: [APUAPC] D5_APC_0: 0xffffffff
9944 11:05:35.627419 INFO: [APUAPC] D5_APC_1: 0xffffffff
9945 11:05:35.630780 INFO: [APUAPC] D5_APC_2: 0x3fffff
9946 11:05:35.630908 INFO: [APUAPC] D5_APC_3: 0x0
9947 11:05:35.633903 INFO: [APUAPC] D6_APC_0: 0xffffffff
9948 11:05:35.640405 INFO: [APUAPC] D6_APC_1: 0xffffffff
9949 11:05:35.643998 INFO: [APUAPC] D6_APC_2: 0x3fffff
9950 11:05:35.644125 INFO: [APUAPC] D6_APC_3: 0x0
9951 11:05:35.647202 INFO: [APUAPC] D7_APC_0: 0xffffffff
9952 11:05:35.650381 INFO: [APUAPC] D7_APC_1: 0xffffffff
9953 11:05:35.653811 INFO: [APUAPC] D7_APC_2: 0x3fffff
9954 11:05:35.657285 INFO: [APUAPC] D7_APC_3: 0x0
9955 11:05:35.660169 INFO: [APUAPC] D8_APC_0: 0xffffffff
9956 11:05:35.663582 INFO: [APUAPC] D8_APC_1: 0xffffffff
9957 11:05:35.667092 INFO: [APUAPC] D8_APC_2: 0x3fffff
9958 11:05:35.669954 INFO: [APUAPC] D8_APC_3: 0x0
9959 11:05:35.673383 INFO: [APUAPC] D9_APC_0: 0xffffffff
9960 11:05:35.676842 INFO: [APUAPC] D9_APC_1: 0xffffffff
9961 11:05:35.680019 INFO: [APUAPC] D9_APC_2: 0x3fffff
9962 11:05:35.683183 INFO: [APUAPC] D9_APC_3: 0x0
9963 11:05:35.686551 INFO: [APUAPC] D10_APC_0: 0xffffffff
9964 11:05:35.689822 INFO: [APUAPC] D10_APC_1: 0xffffffff
9965 11:05:35.692876 INFO: [APUAPC] D10_APC_2: 0x3fffff
9966 11:05:35.696519 INFO: [APUAPC] D10_APC_3: 0x0
9967 11:05:35.699767 INFO: [APUAPC] D11_APC_0: 0xffffffff
9968 11:05:35.703642 INFO: [APUAPC] D11_APC_1: 0xffffffff
9969 11:05:35.706223 INFO: [APUAPC] D11_APC_2: 0x3fffff
9970 11:05:35.709898 INFO: [APUAPC] D11_APC_3: 0x0
9971 11:05:35.713170 INFO: [APUAPC] D12_APC_0: 0xffffffff
9972 11:05:35.716154 INFO: [APUAPC] D12_APC_1: 0xffffffff
9973 11:05:35.722487 INFO: [APUAPC] D12_APC_2: 0x3fffff
9974 11:05:35.722614 INFO: [APUAPC] D12_APC_3: 0x0
9975 11:05:35.726363 INFO: [APUAPC] D13_APC_0: 0xffffffff
9976 11:05:35.732585 INFO: [APUAPC] D13_APC_1: 0xffffffff
9977 11:05:35.735860 INFO: [APUAPC] D13_APC_2: 0x3fffff
9978 11:05:35.735987 INFO: [APUAPC] D13_APC_3: 0x0
9979 11:05:35.742386 INFO: [APUAPC] D14_APC_0: 0xffffffff
9980 11:05:35.745655 INFO: [APUAPC] D14_APC_1: 0xffffffff
9981 11:05:35.748808 INFO: [APUAPC] D14_APC_2: 0x3fffff
9982 11:05:35.752675 INFO: [APUAPC] D14_APC_3: 0x0
9983 11:05:35.755673 INFO: [APUAPC] D15_APC_0: 0xffffffff
9984 11:05:35.758886 INFO: [APUAPC] D15_APC_1: 0xffffffff
9985 11:05:35.762015 INFO: [APUAPC] D15_APC_2: 0x3fffff
9986 11:05:35.765574 INFO: [APUAPC] D15_APC_3: 0x0
9987 11:05:35.765703 INFO: [APUAPC] APC_CON: 0x4
9988 11:05:35.768899 INFO: [NOCDAPC] D0_APC_0: 0x0
9989 11:05:35.772175 INFO: [NOCDAPC] D0_APC_1: 0x0
9990 11:05:35.775165 INFO: [NOCDAPC] D1_APC_0: 0x0
9991 11:05:35.778560 INFO: [NOCDAPC] D1_APC_1: 0xfff
9992 11:05:35.781962 INFO: [NOCDAPC] D2_APC_0: 0x0
9993 11:05:35.784866 INFO: [NOCDAPC] D2_APC_1: 0xfff
9994 11:05:35.788552 INFO: [NOCDAPC] D3_APC_0: 0x0
9995 11:05:35.791413 INFO: [NOCDAPC] D3_APC_1: 0xfff
9996 11:05:35.795190 INFO: [NOCDAPC] D4_APC_0: 0x0
9997 11:05:35.798097 INFO: [NOCDAPC] D4_APC_1: 0xfff
9998 11:05:35.798222 INFO: [NOCDAPC] D5_APC_0: 0x0
9999 11:05:35.801216 INFO: [NOCDAPC] D5_APC_1: 0xfff
10000 11:05:35.804747 INFO: [NOCDAPC] D6_APC_0: 0x0
10001 11:05:35.807834 INFO: [NOCDAPC] D6_APC_1: 0xfff
10002 11:05:35.811210 INFO: [NOCDAPC] D7_APC_0: 0x0
10003 11:05:35.814614 INFO: [NOCDAPC] D7_APC_1: 0xfff
10004 11:05:35.817812 INFO: [NOCDAPC] D8_APC_0: 0x0
10005 11:05:35.821665 INFO: [NOCDAPC] D8_APC_1: 0xfff
10006 11:05:35.824673 INFO: [NOCDAPC] D9_APC_0: 0x0
10007 11:05:35.827875 INFO: [NOCDAPC] D9_APC_1: 0xfff
10008 11:05:35.830983 INFO: [NOCDAPC] D10_APC_0: 0x0
10009 11:05:35.834845 INFO: [NOCDAPC] D10_APC_1: 0xfff
10010 11:05:35.837973 INFO: [NOCDAPC] D11_APC_0: 0x0
10011 11:05:35.841225 INFO: [NOCDAPC] D11_APC_1: 0xfff
10012 11:05:35.841350 INFO: [NOCDAPC] D12_APC_0: 0x0
10013 11:05:35.844349 INFO: [NOCDAPC] D12_APC_1: 0xfff
10014 11:05:35.848041 INFO: [NOCDAPC] D13_APC_0: 0x0
10015 11:05:35.850763 INFO: [NOCDAPC] D13_APC_1: 0xfff
10016 11:05:35.854007 INFO: [NOCDAPC] D14_APC_0: 0x0
10017 11:05:35.857676 INFO: [NOCDAPC] D14_APC_1: 0xfff
10018 11:05:35.860729 INFO: [NOCDAPC] D15_APC_0: 0x0
10019 11:05:35.863914 INFO: [NOCDAPC] D15_APC_1: 0xfff
10020 11:05:35.867315 INFO: [NOCDAPC] APC_CON: 0x4
10021 11:05:35.870812 INFO: [APUAPC] set_apusys_apc done
10022 11:05:35.874050 INFO: [DEVAPC] devapc_init done
10023 11:05:35.877312 INFO: GICv3 without legacy support detected.
10024 11:05:35.880334 INFO: ARM GICv3 driver initialized in EL3
10025 11:05:35.883965 INFO: Maximum SPI INTID supported: 639
10026 11:05:35.890396 INFO: BL31: Initializing runtime services
10027 11:05:35.893948 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10028 11:05:35.897182 INFO: SPM: enable CPC mode
10029 11:05:35.903669 INFO: mcdi ready for mcusys-off-idle and system suspend
10030 11:05:35.907110 INFO: BL31: Preparing for EL3 exit to normal world
10031 11:05:35.910177 INFO: Entry point address = 0x80000000
10032 11:05:35.913290 INFO: SPSR = 0x8
10033 11:05:35.919176
10034 11:05:35.919278
10035 11:05:35.919376
10036 11:05:35.922192 Starting depthcharge on Spherion...
10037 11:05:35.922266
10038 11:05:35.922327 Wipe memory regions:
10039 11:05:35.922387
10040 11:05:35.923205 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10041 11:05:35.923334 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10042 11:05:35.923710 Setting prompt string to ['asurada:']
10043 11:05:35.923794 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10044 11:05:35.925792 [0x00000040000000, 0x00000054600000)
10045 11:05:36.047835
10046 11:05:36.047963 [0x00000054660000, 0x00000080000000)
10047 11:05:36.308354
10048 11:05:36.308547 [0x000000821a7280, 0x000000ffe64000)
10049 11:05:37.053186
10050 11:05:37.053323 [0x00000100000000, 0x00000240000000)
10051 11:05:38.942144
10052 11:05:38.945622 Initializing XHCI USB controller at 0x11200000.
10053 11:05:39.984394
10054 11:05:39.987508 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10055 11:05:39.987658
10056 11:05:39.987775
10057 11:05:39.987888
10058 11:05:39.988247 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10060 11:05:40.088684 asurada: tftpboot 192.168.201.1 12925662/tftp-deploy-40xl1zo3/kernel/image.itb 12925662/tftp-deploy-40xl1zo3/kernel/cmdline
10061 11:05:40.088820 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10062 11:05:40.088906 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10063 11:05:40.092841 tftpboot 192.168.201.1 12925662/tftp-deploy-40xl1zo3/kernel/image.ittp-deploy-40xl1zo3/kernel/cmdline
10064 11:05:40.092928
10065 11:05:40.093013 Waiting for link
10066 11:05:40.253331
10067 11:05:40.253516 R8152: Initializing
10068 11:05:40.253636
10069 11:05:40.256671 Version 6 (ocp_data = 5c30)
10070 11:05:40.256770
10071 11:05:40.259845 R8152: Done initializing
10072 11:05:40.259954
10073 11:05:40.260051 Adding net device
10074 11:05:42.115249
10075 11:05:42.115411 done.
10076 11:05:42.115496
10077 11:05:42.115557 MAC: 00:24:32:30:7c:7b
10078 11:05:42.115614
10079 11:05:42.118654 Sending DHCP discover... done.
10080 11:05:42.118754
10081 11:05:42.122419 Waiting for reply... done.
10082 11:05:42.122501
10083 11:05:42.125256 Sending DHCP request... done.
10084 11:05:42.125338
10085 11:05:42.129578 Waiting for reply... done.
10086 11:05:42.129659
10087 11:05:42.129722 My ip is 192.168.201.14
10088 11:05:42.129782
10089 11:05:42.132353 The DHCP server ip is 192.168.201.1
10090 11:05:42.132435
10091 11:05:42.138974 TFTP server IP predefined by user: 192.168.201.1
10092 11:05:42.139056
10093 11:05:42.145829 Bootfile predefined by user: 12925662/tftp-deploy-40xl1zo3/kernel/image.itb
10094 11:05:42.145912
10095 11:05:42.148857 Sending tftp read request... done.
10096 11:05:42.148961
10097 11:05:42.152957 Waiting for the transfer...
10098 11:05:42.153038
10099 11:05:42.686894 00000000 ################################################################
10100 11:05:42.687074
10101 11:05:43.214573 00080000 ################################################################
10102 11:05:43.214735
10103 11:05:43.747503 00100000 ################################################################
10104 11:05:43.747638
10105 11:05:44.284800 00180000 ################################################################
10106 11:05:44.284952
10107 11:05:44.814083 00200000 ################################################################
10108 11:05:44.814219
10109 11:05:45.346691 00280000 ################################################################
10110 11:05:45.346837
10111 11:05:45.883750 00300000 ################################################################
10112 11:05:45.883953
10113 11:05:46.432204 00380000 ################################################################
10114 11:05:46.432340
10115 11:05:46.973302 00400000 ################################################################
10116 11:05:46.973466
10117 11:05:47.519484 00480000 ################################################################
10118 11:05:47.519624
10119 11:05:48.059924 00500000 ################################################################
10120 11:05:48.060067
10121 11:05:48.605284 00580000 ################################################################
10122 11:05:48.605421
10123 11:05:49.144714 00600000 ################################################################
10124 11:05:49.144913
10125 11:05:49.687823 00680000 ################################################################
10126 11:05:49.687999
10127 11:05:50.223864 00700000 ################################################################
10128 11:05:50.224002
10129 11:05:50.760330 00780000 ################################################################
10130 11:05:50.760468
10131 11:05:51.289468 00800000 ################################################################
10132 11:05:51.289599
10133 11:05:51.833914 00880000 ################################################################
10134 11:05:51.834109
10135 11:05:52.361139 00900000 ################################################################
10136 11:05:52.361267
10137 11:05:52.907270 00980000 ################################################################
10138 11:05:52.907423
10139 11:05:53.454757 00a00000 ################################################################
10140 11:05:53.454890
10141 11:05:54.000990 00a80000 ################################################################
10142 11:05:54.001124
10143 11:05:54.539083 00b00000 ################################################################
10144 11:05:54.539221
10145 11:05:55.077592 00b80000 ################################################################
10146 11:05:55.077725
10147 11:05:55.638774 00c00000 ################################################################
10148 11:05:55.638914
10149 11:05:56.198520 00c80000 ################################################################
10150 11:05:56.198740
10151 11:05:56.750164 00d00000 ################################################################
10152 11:05:56.750375
10153 11:05:57.302801 00d80000 ################################################################
10154 11:05:57.302943
10155 11:05:57.831022 00e00000 ################################################################
10156 11:05:57.831229
10157 11:05:58.356553 00e80000 ################################################################
10158 11:05:58.356705
10159 11:05:58.885299 00f00000 ################################################################
10160 11:05:58.885448
10161 11:05:59.418112 00f80000 ################################################################
10162 11:05:59.418245
10163 11:05:59.943489 01000000 ################################################################
10164 11:05:59.943657
10165 11:06:00.477319 01080000 ################################################################
10166 11:06:00.477456
10167 11:06:01.015755 01100000 ################################################################
10168 11:06:01.015947
10169 11:06:01.543136 01180000 ################################################################
10170 11:06:01.543269
10171 11:06:02.070820 01200000 ################################################################
10172 11:06:02.070980
10173 11:06:02.609382 01280000 ################################################################
10174 11:06:02.609571
10175 11:06:03.151813 01300000 ################################################################
10176 11:06:03.151963
10177 11:06:03.689985 01380000 ################################################################
10178 11:06:03.690128
10179 11:06:04.239321 01400000 ################################################################
10180 11:06:04.239492
10181 11:06:04.775728 01480000 ################################################################
10182 11:06:04.775868
10183 11:06:05.307649 01500000 ################################################################
10184 11:06:05.307807
10185 11:06:05.855755 01580000 ################################################################
10186 11:06:05.855898
10187 11:06:06.393148 01600000 ################################################################
10188 11:06:06.393324
10189 11:06:06.938855 01680000 ################################################################
10190 11:06:06.939066
10191 11:06:07.474581 01700000 ################################################################
10192 11:06:07.474754
10193 11:06:08.024306 01780000 ################################################################
10194 11:06:08.024448
10195 11:06:08.562862 01800000 ################################################################
10196 11:06:08.563025
10197 11:06:09.098062 01880000 ################################################################
10198 11:06:09.098199
10199 11:06:09.629626 01900000 ################################################################
10200 11:06:09.629772
10201 11:06:10.166976 01980000 ################################################################
10202 11:06:10.167185
10203 11:06:10.719976 01a00000 ################################################################
10204 11:06:10.720123
10205 11:06:11.260603 01a80000 ################################################################
10206 11:06:11.260760
10207 11:06:11.790946 01b00000 ################################################################
10208 11:06:11.791104
10209 11:06:12.330298 01b80000 ################################################################
10210 11:06:12.330469
10211 11:06:12.886162 01c00000 ################################################################
10212 11:06:12.886307
10213 11:06:12.910082 01c80000 ### done.
10214 11:06:12.910167
10215 11:06:12.913281 The bootfile was 29905530 bytes long.
10216 11:06:12.913366
10217 11:06:12.916418 Sending tftp read request... done.
10218 11:06:12.916539
10219 11:06:12.916604 Waiting for the transfer...
10220 11:06:12.916693
10221 11:06:12.919469 00000000 # done.
10222 11:06:12.919552
10223 11:06:12.926386 Command line loaded dynamically from TFTP file: 12925662/tftp-deploy-40xl1zo3/kernel/cmdline
10224 11:06:12.926487
10225 11:06:12.949425 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12925662/extract-nfsrootfs-7g5anr9b,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10226 11:06:12.949515
10227 11:06:12.949580 Loading FIT.
10228 11:06:12.949639
10229 11:06:12.952962 Image ramdisk-1 has 17798518 bytes.
10230 11:06:12.953044
10231 11:06:12.955745 Image fdt-1 has 47278 bytes.
10232 11:06:12.955826
10233 11:06:12.959177 Image kernel-1 has 12057697 bytes.
10234 11:06:12.959257
10235 11:06:12.969673 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10236 11:06:12.969758
10237 11:06:12.985673 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10238 11:06:12.985759
10239 11:06:12.992101 Choosing best match conf-1 for compat google,spherion-rev2.
10240 11:06:12.992183
10241 11:06:13.000268 Connected to device vid:did:rid of 1ae0:0028:00
10242 11:06:13.006832
10243 11:06:13.010062 tpm_get_response: command 0x17b, return code 0x0
10244 11:06:13.010144
10245 11:06:13.013249 ec_init: CrosEC protocol v3 supported (256, 248)
10246 11:06:13.017122
10247 11:06:13.020821 tpm_cleanup: add release locality here.
10248 11:06:13.020902
10249 11:06:13.020966 Shutting down all USB controllers.
10250 11:06:13.024344
10251 11:06:13.024438 Removing current net device
10252 11:06:13.024502
10253 11:06:13.031297 Exiting depthcharge with code 4 at timestamp: 66350680
10254 11:06:13.031419
10255 11:06:13.034154 LZMA decompressing kernel-1 to 0x821a6718
10256 11:06:13.034235
10257 11:06:13.037472 LZMA decompressing kernel-1 to 0x40000000
10258 11:06:14.537967
10259 11:06:14.538100 jumping to kernel
10260 11:06:14.538551 end: 2.2.4 bootloader-commands (duration 00:00:39) [common]
10261 11:06:14.538649 start: 2.2.5 auto-login-action (timeout 00:03:47) [common]
10262 11:06:14.538726 Setting prompt string to ['Linux version [0-9]']
10263 11:06:14.538798 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10264 11:06:14.538865 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10265 11:06:14.620883
10266 11:06:14.624202 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10267 11:06:14.627568 start: 2.2.5.1 login-action (timeout 00:03:47) [common]
10268 11:06:14.627664 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10269 11:06:14.627736 Setting prompt string to []
10270 11:06:14.627812 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10271 11:06:14.627883 Using line separator: #'\n'#
10272 11:06:14.627942 No login prompt set.
10273 11:06:14.628003 Parsing kernel messages
10274 11:06:14.628058 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10275 11:06:14.628166 [login-action] Waiting for messages, (timeout 00:03:47)
10276 11:06:14.628230 Waiting using forced prompt support (timeout 00:01:53)
10277 11:06:14.647303 [ 0.000000] Linux version 6.1.80-cip16 (KernelCI@build-j128891-arm64-gcc-10-defconfig-arm64-chromebook-nrg4h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024
10278 11:06:14.650852 [ 0.000000] random: crng init done
10279 11:06:14.656955 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10280 11:06:14.660187 [ 0.000000] efi: UEFI not found.
10281 11:06:14.667122 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10282 11:06:14.676828 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10283 11:06:14.683656 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10284 11:06:14.693546 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10285 11:06:14.699864 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10286 11:06:14.706390 [ 0.000000] printk: bootconsole [mtk8250] enabled
10287 11:06:14.713235 [ 0.000000] NUMA: No NUMA configuration found
10288 11:06:14.719916 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10289 11:06:14.726470 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10290 11:06:14.726559 [ 0.000000] Zone ranges:
10291 11:06:14.732704 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10292 11:06:14.736227 [ 0.000000] DMA32 empty
10293 11:06:14.742842 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10294 11:06:14.745764 [ 0.000000] Movable zone start for each node
10295 11:06:14.749348 [ 0.000000] Early memory node ranges
10296 11:06:14.756288 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10297 11:06:14.762441 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10298 11:06:14.768776 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10299 11:06:14.775301 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10300 11:06:14.781916 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10301 11:06:14.788660 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10302 11:06:14.844898 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10303 11:06:14.851686 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10304 11:06:14.858337 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10305 11:06:14.861541 [ 0.000000] psci: probing for conduit method from DT.
10306 11:06:14.868343 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10307 11:06:14.872005 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10308 11:06:14.878150 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10309 11:06:14.881194 [ 0.000000] psci: SMC Calling Convention v1.2
10310 11:06:14.887851 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10311 11:06:14.891081 [ 0.000000] Detected VIPT I-cache on CPU0
10312 11:06:14.897714 [ 0.000000] CPU features: detected: GIC system register CPU interface
10313 11:06:14.904511 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10314 11:06:14.910899 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10315 11:06:14.917269 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10316 11:06:14.927779 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10317 11:06:14.934015 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10318 11:06:14.936980 [ 0.000000] alternatives: applying boot alternatives
10319 11:06:14.943778 [ 0.000000] Fallback order for Node 0: 0
10320 11:06:14.950277 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10321 11:06:14.953872 [ 0.000000] Policy zone: Normal
10322 11:06:14.976835 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12925662/extract-nfsrootfs-7g5anr9b,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10323 11:06:14.987032 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10324 11:06:14.998045 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10325 11:06:15.007968 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10326 11:06:15.014431 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10327 11:06:15.017467 <6>[ 0.000000] software IO TLB: area num 8.
10328 11:06:15.074453 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10329 11:06:15.223648 <6>[ 0.000000] Memory: 7949812K/8385536K available (18048K kernel code, 4118K rwdata, 19616K rodata, 8448K init, 616K bss, 402956K reserved, 32768K cma-reserved)
10330 11:06:15.230359 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10331 11:06:15.236971 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10332 11:06:15.240298 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10333 11:06:15.246293 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10334 11:06:15.252955 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10335 11:06:15.256488 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10336 11:06:15.265936 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10337 11:06:15.272643 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10338 11:06:15.279488 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10339 11:06:15.286364 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10340 11:06:15.288829 <6>[ 0.000000] GICv3: 608 SPIs implemented
10341 11:06:15.292450 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10342 11:06:15.299195 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10343 11:06:15.302096 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10344 11:06:15.309090 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10345 11:06:15.321890 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10346 11:06:15.334913 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10347 11:06:15.341660 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10348 11:06:15.350651 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10349 11:06:15.363075 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10350 11:06:15.369631 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10351 11:06:15.376415 <6>[ 0.009182] Console: colour dummy device 80x25
10352 11:06:15.385941 <6>[ 0.013902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10353 11:06:15.393011 <6>[ 0.024344] pid_max: default: 32768 minimum: 301
10354 11:06:15.396480 <6>[ 0.029216] LSM: Security Framework initializing
10355 11:06:15.402668 <6>[ 0.034155] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10356 11:06:15.413076 <6>[ 0.041968] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10357 11:06:15.422513 <6>[ 0.051435] cblist_init_generic: Setting adjustable number of callback queues.
10358 11:06:15.425886 <6>[ 0.058878] cblist_init_generic: Setting shift to 3 and lim to 1.
10359 11:06:15.435630 <6>[ 0.065256] cblist_init_generic: Setting adjustable number of callback queues.
10360 11:06:15.442207 <6>[ 0.072729] cblist_init_generic: Setting shift to 3 and lim to 1.
10361 11:06:15.445591 <6>[ 0.079168] rcu: Hierarchical SRCU implementation.
10362 11:06:15.452387 <6>[ 0.084183] rcu: Max phase no-delay instances is 1000.
10363 11:06:15.458820 <6>[ 0.091239] EFI services will not be available.
10364 11:06:15.462446 <6>[ 0.096198] smp: Bringing up secondary CPUs ...
10365 11:06:15.470779 <6>[ 0.101248] Detected VIPT I-cache on CPU1
10366 11:06:15.477601 <6>[ 0.101317] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10367 11:06:15.484635 <6>[ 0.101351] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10368 11:06:15.487101 <6>[ 0.101693] Detected VIPT I-cache on CPU2
10369 11:06:15.493939 <6>[ 0.101747] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10370 11:06:15.503827 <6>[ 0.101764] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10371 11:06:15.507328 <6>[ 0.102023] Detected VIPT I-cache on CPU3
10372 11:06:15.514046 <6>[ 0.102069] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10373 11:06:15.520213 <6>[ 0.102082] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10374 11:06:15.526784 <6>[ 0.102390] CPU features: detected: Spectre-v4
10375 11:06:15.530333 <6>[ 0.102396] CPU features: detected: Spectre-BHB
10376 11:06:15.533400 <6>[ 0.102402] Detected PIPT I-cache on CPU4
10377 11:06:15.540003 <6>[ 0.102457] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10378 11:06:15.546692 <6>[ 0.102474] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10379 11:06:15.553399 <6>[ 0.102770] Detected PIPT I-cache on CPU5
10380 11:06:15.559855 <6>[ 0.102832] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10381 11:06:15.566179 <6>[ 0.102848] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10382 11:06:15.569824 <6>[ 0.103131] Detected PIPT I-cache on CPU6
10383 11:06:15.576213 <6>[ 0.103197] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10384 11:06:15.586394 <6>[ 0.103213] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10385 11:06:15.589532 <6>[ 0.103511] Detected PIPT I-cache on CPU7
10386 11:06:15.595992 <6>[ 0.103577] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10387 11:06:15.602704 <6>[ 0.103592] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10388 11:06:15.605904 <6>[ 0.103639] smp: Brought up 1 node, 8 CPUs
10389 11:06:15.612395 <6>[ 0.244984] SMP: Total of 8 processors activated.
10390 11:06:15.615712 <6>[ 0.249905] CPU features: detected: 32-bit EL0 Support
10391 11:06:15.626283 <6>[ 0.255302] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10392 11:06:15.632642 <6>[ 0.264102] CPU features: detected: Common not Private translations
10393 11:06:15.639098 <6>[ 0.270618] CPU features: detected: CRC32 instructions
10394 11:06:15.645776 <6>[ 0.276003] CPU features: detected: RCpc load-acquire (LDAPR)
10395 11:06:15.648821 <6>[ 0.281999] CPU features: detected: LSE atomic instructions
10396 11:06:15.655354 <6>[ 0.287781] CPU features: detected: Privileged Access Never
10397 11:06:15.662059 <6>[ 0.293560] CPU features: detected: RAS Extension Support
10398 11:06:15.668542 <6>[ 0.299204] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10399 11:06:15.671764 <6>[ 0.306469] CPU: All CPU(s) started at EL2
10400 11:06:15.678516 <6>[ 0.310785] alternatives: applying system-wide alternatives
10401 11:06:15.688421 <6>[ 0.321634] devtmpfs: initialized
10402 11:06:15.704854 <6>[ 0.330616] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10403 11:06:15.711167 <6>[ 0.340578] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10404 11:06:15.717574 <6>[ 0.348609] pinctrl core: initialized pinctrl subsystem
10405 11:06:15.720821 <6>[ 0.355280] DMI not present or invalid.
10406 11:06:15.727411 <6>[ 0.359687] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10407 11:06:15.737306 <6>[ 0.366516] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10408 11:06:15.743805 <6>[ 0.374104] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10409 11:06:15.753946 <6>[ 0.382315] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10410 11:06:15.757016 <6>[ 0.390558] audit: initializing netlink subsys (disabled)
10411 11:06:15.767131 <5>[ 0.396253] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10412 11:06:15.774039 <6>[ 0.396955] thermal_sys: Registered thermal governor 'step_wise'
10413 11:06:15.779998 <6>[ 0.404218] thermal_sys: Registered thermal governor 'power_allocator'
10414 11:06:15.783555 <6>[ 0.410475] cpuidle: using governor menu
10415 11:06:15.791149 <6>[ 0.421438] NET: Registered PF_QIPCRTR protocol family
10416 11:06:15.796502 <6>[ 0.426920] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10417 11:06:15.803209 <6>[ 0.434022] ASID allocator initialised with 32768 entries
10418 11:06:15.806765 <6>[ 0.440596] Serial: AMBA PL011 UART driver
10419 11:06:15.816423 <4>[ 0.449355] Trying to register duplicate clock ID: 134
10420 11:06:15.870789 <6>[ 0.507009] KASLR enabled
10421 11:06:15.885436 <6>[ 0.514699] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10422 11:06:15.891492 <6>[ 0.521712] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10423 11:06:15.898199 <6>[ 0.528203] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10424 11:06:15.904988 <6>[ 0.535209] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10425 11:06:15.911664 <6>[ 0.541698] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10426 11:06:15.917965 <6>[ 0.548703] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10427 11:06:15.924429 <6>[ 0.555192] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10428 11:06:15.931474 <6>[ 0.562198] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10429 11:06:15.934144 <6>[ 0.569725] ACPI: Interpreter disabled.
10430 11:06:15.943636 <6>[ 0.576143] iommu: Default domain type: Translated
10431 11:06:15.950041 <6>[ 0.581254] iommu: DMA domain TLB invalidation policy: strict mode
10432 11:06:15.953529 <5>[ 0.587914] SCSI subsystem initialized
10433 11:06:15.959854 <6>[ 0.592079] usbcore: registered new interface driver usbfs
10434 11:06:15.966378 <6>[ 0.597811] usbcore: registered new interface driver hub
10435 11:06:15.969448 <6>[ 0.603361] usbcore: registered new device driver usb
10436 11:06:15.976784 <6>[ 0.609464] pps_core: LinuxPPS API ver. 1 registered
10437 11:06:15.987084 <6>[ 0.614658] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10438 11:06:15.989513 <6>[ 0.624006] PTP clock support registered
10439 11:06:15.992840 <6>[ 0.628248] EDAC MC: Ver: 3.0.0
10440 11:06:16.000604 <6>[ 0.633400] FPGA manager framework
10441 11:06:16.007285 <6>[ 0.637079] Advanced Linux Sound Architecture Driver Initialized.
10442 11:06:16.010533 <6>[ 0.643861] vgaarb: loaded
10443 11:06:16.016795 <6>[ 0.647034] clocksource: Switched to clocksource arch_sys_counter
10444 11:06:16.019994 <5>[ 0.653469] VFS: Disk quotas dquot_6.6.0
10445 11:06:16.026585 <6>[ 0.657653] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10446 11:06:16.030184 <6>[ 0.664840] pnp: PnP ACPI: disabled
10447 11:06:16.038523 <6>[ 0.671489] NET: Registered PF_INET protocol family
10448 11:06:16.048335 <6>[ 0.677073] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10449 11:06:16.059911 <6>[ 0.689384] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10450 11:06:16.069980 <6>[ 0.698198] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10451 11:06:16.076797 <6>[ 0.706171] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10452 11:06:16.086150 <6>[ 0.714873] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10453 11:06:16.092766 <6>[ 0.724616] TCP: Hash tables configured (established 65536 bind 65536)
10454 11:06:16.099280 <6>[ 0.731478] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10455 11:06:16.109540 <6>[ 0.738677] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10456 11:06:16.115536 <6>[ 0.746378] NET: Registered PF_UNIX/PF_LOCAL protocol family
10457 11:06:16.122481 <6>[ 0.752561] RPC: Registered named UNIX socket transport module.
10458 11:06:16.125544 <6>[ 0.758717] RPC: Registered udp transport module.
10459 11:06:16.132366 <6>[ 0.763647] RPC: Registered tcp transport module.
10460 11:06:16.138679 <6>[ 0.768579] RPC: Registered tcp NFSv4.1 backchannel transport module.
10461 11:06:16.142028 <6>[ 0.775246] PCI: CLS 0 bytes, default 64
10462 11:06:16.145450 <6>[ 0.779647] Unpacking initramfs...
10463 11:06:16.169517 <6>[ 0.799155] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10464 11:06:16.179406 <6>[ 0.807823] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10465 11:06:16.182609 <6>[ 0.816687] kvm [1]: IPA Size Limit: 40 bits
10466 11:06:16.189529 <6>[ 0.821216] kvm [1]: GICv3: no GICV resource entry
10467 11:06:16.192546 <6>[ 0.826236] kvm [1]: disabling GICv2 emulation
10468 11:06:16.199103 <6>[ 0.830922] kvm [1]: GIC system register CPU interface enabled
10469 11:06:16.202745 <6>[ 0.837096] kvm [1]: vgic interrupt IRQ18
10470 11:06:16.209576 <6>[ 0.841450] kvm [1]: VHE mode initialized successfully
10471 11:06:16.215787 <5>[ 0.847941] Initialise system trusted keyrings
10472 11:06:16.222420 <6>[ 0.852812] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10473 11:06:16.230394 <6>[ 0.862882] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10474 11:06:16.236707 <5>[ 0.869318] NFS: Registering the id_resolver key type
10475 11:06:16.239940 <5>[ 0.874616] Key type id_resolver registered
10476 11:06:16.246580 <5>[ 0.879030] Key type id_legacy registered
10477 11:06:16.253036 <6>[ 0.883305] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10478 11:06:16.259543 <6>[ 0.890227] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10479 11:06:16.266269 <6>[ 0.897951] 9p: Installing v9fs 9p2000 file system support
10480 11:06:16.302753 <5>[ 0.935714] Key type asymmetric registered
10481 11:06:16.306318 <5>[ 0.940043] Asymmetric key parser 'x509' registered
10482 11:06:16.315761 <6>[ 0.945231] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10483 11:06:16.319419 <6>[ 0.952865] io scheduler mq-deadline registered
10484 11:06:16.322784 <6>[ 0.957634] io scheduler kyber registered
10485 11:06:16.341776 <6>[ 0.974690] EINJ: ACPI disabled.
10486 11:06:16.373733 <4>[ 1.000220] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10487 11:06:16.383609 <4>[ 1.010855] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10488 11:06:16.398989 <6>[ 1.031553] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10489 11:06:16.407018 <6>[ 1.039664] printk: console [ttyS0] disabled
10490 11:06:16.434739 <6>[ 1.064294] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10491 11:06:16.441333 <6>[ 1.073782] printk: console [ttyS0] enabled
10492 11:06:16.444598 <6>[ 1.073782] printk: console [ttyS0] enabled
10493 11:06:16.451185 <6>[ 1.082675] printk: bootconsole [mtk8250] disabled
10494 11:06:16.454208 <6>[ 1.082675] printk: bootconsole [mtk8250] disabled
10495 11:06:16.460870 <6>[ 1.094017] SuperH (H)SCI(F) driver initialized
10496 11:06:16.464541 <6>[ 1.099310] msm_serial: driver initialized
10497 11:06:16.479196 <6>[ 1.108310] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10498 11:06:16.488539 <6>[ 1.116860] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10499 11:06:16.495517 <6>[ 1.125403] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10500 11:06:16.505208 <6>[ 1.134033] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10501 11:06:16.515417 <6>[ 1.142739] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10502 11:06:16.521692 <6>[ 1.151460] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10503 11:06:16.531724 <6>[ 1.159999] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10504 11:06:16.538330 <6>[ 1.168807] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10505 11:06:16.548088 <6>[ 1.177352] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10506 11:06:16.560139 <6>[ 1.192968] loop: module loaded
10507 11:06:16.566995 <6>[ 1.198923] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10508 11:06:16.589372 <4>[ 1.222358] mtk-pmic-keys: Failed to locate of_node [id: -1]
10509 11:06:16.596578 <6>[ 1.229376] megasas: 07.719.03.00-rc1
10510 11:06:16.606060 <6>[ 1.238889] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10511 11:06:16.613374 <6>[ 1.246410] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10512 11:06:16.630101 <6>[ 1.262970] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10513 11:06:16.685762 <6>[ 1.312315] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10514 11:06:16.891723 <6>[ 1.524509] Freeing initrd memory: 17376K
10515 11:06:16.901900 <6>[ 1.534923] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10516 11:06:16.912765 <6>[ 1.545900] tun: Universal TUN/TAP device driver, 1.6
10517 11:06:16.916484 <6>[ 1.551962] thunder_xcv, ver 1.0
10518 11:06:16.919651 <6>[ 1.555465] thunder_bgx, ver 1.0
10519 11:06:16.922532 <6>[ 1.558958] nicpf, ver 1.0
10520 11:06:16.933524 <6>[ 1.562980] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10521 11:06:16.936760 <6>[ 1.570457] hns3: Copyright (c) 2017 Huawei Corporation.
10522 11:06:16.940178 <6>[ 1.576044] hclge is initializing
10523 11:06:16.946696 <6>[ 1.579623] e1000: Intel(R) PRO/1000 Network Driver
10524 11:06:16.953136 <6>[ 1.584752] e1000: Copyright (c) 1999-2006 Intel Corporation.
10525 11:06:16.956681 <6>[ 1.590768] e1000e: Intel(R) PRO/1000 Network Driver
10526 11:06:16.963177 <6>[ 1.595984] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10527 11:06:16.969689 <6>[ 1.602170] igb: Intel(R) Gigabit Ethernet Network Driver
10528 11:06:16.976538 <6>[ 1.607820] igb: Copyright (c) 2007-2014 Intel Corporation.
10529 11:06:16.983030 <6>[ 1.613655] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10530 11:06:16.989827 <6>[ 1.620172] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10531 11:06:16.992732 <6>[ 1.626634] sky2: driver version 1.30
10532 11:06:16.999880 <6>[ 1.631631] VFIO - User Level meta-driver version: 0.3
10533 11:06:17.006633 <6>[ 1.639834] usbcore: registered new interface driver usb-storage
10534 11:06:17.013557 <6>[ 1.646274] usbcore: registered new device driver onboard-usb-hub
10535 11:06:17.022342 <6>[ 1.655403] mt6397-rtc mt6359-rtc: registered as rtc0
10536 11:06:17.032071 <6>[ 1.660864] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T11:06:18 UTC (1709463978)
10537 11:06:17.035690 <6>[ 1.670430] i2c_dev: i2c /dev entries driver
10538 11:06:17.052439 <6>[ 1.682201] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10539 11:06:17.073014 <6>[ 1.706170] cpu cpu0: EM: created perf domain
10540 11:06:17.076205 <6>[ 1.711100] cpu cpu4: EM: created perf domain
10541 11:06:17.083592 <6>[ 1.716695] sdhci: Secure Digital Host Controller Interface driver
10542 11:06:17.090578 <6>[ 1.723128] sdhci: Copyright(c) Pierre Ossman
10543 11:06:17.097024 <6>[ 1.728097] Synopsys Designware Multimedia Card Interface Driver
10544 11:06:17.103874 <6>[ 1.734733] sdhci-pltfm: SDHCI platform and OF driver helper
10545 11:06:17.106765 <6>[ 1.734769] mmc0: CQHCI version 5.10
10546 11:06:17.113533 <6>[ 1.744750] ledtrig-cpu: registered to indicate activity on CPUs
10547 11:06:17.120555 <6>[ 1.751833] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10548 11:06:17.126959 <6>[ 1.758898] usbcore: registered new interface driver usbhid
10549 11:06:17.130326 <6>[ 1.764721] usbhid: USB HID core driver
10550 11:06:17.136652 <6>[ 1.768913] spi_master spi0: will run message pump with realtime priority
10551 11:06:17.185117 <6>[ 1.811821] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10552 11:06:17.204320 <6>[ 1.827454] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10553 11:06:17.207965 <6>[ 1.842327] mmc0: Command Queue Engine enabled
10554 11:06:17.215051 <6>[ 1.842549] cros-ec-spi spi0.0: Chrome EC device registered
10555 11:06:17.221612 <6>[ 1.847080] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10556 11:06:17.227953 <6>[ 1.860127] mmcblk0: mmc0:0001 DA4128 116 GiB
10557 11:06:17.237785 <6>[ 1.866038] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10558 11:06:17.244532 <6>[ 1.873513] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10559 11:06:17.247839 <6>[ 1.876540] NET: Registered PF_PACKET protocol family
10560 11:06:17.254418 <6>[ 1.882641] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10561 11:06:17.257836 <6>[ 1.886658] 9pnet: Installing 9P2000 support
10562 11:06:17.264420 <6>[ 1.892481] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10563 11:06:17.268219 <5>[ 1.896362] Key type dns_resolver registered
10564 11:06:17.274769 <6>[ 1.902206] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10565 11:06:17.278235 <6>[ 1.906623] registered taskstats version 1
10566 11:06:17.284129 <5>[ 1.916997] Loading compiled-in X.509 certificates
10567 11:06:17.311842 <4>[ 1.938259] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10568 11:06:17.321721 <4>[ 1.948957] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10569 11:06:17.328856 <3>[ 1.959485] debugfs: File 'uA_load' in directory '/' already present!
10570 11:06:17.335011 <3>[ 1.966185] debugfs: File 'min_uV' in directory '/' already present!
10571 11:06:17.341557 <3>[ 1.972792] debugfs: File 'max_uV' in directory '/' already present!
10572 11:06:17.349032 <3>[ 1.979456] debugfs: File 'constraint_flags' in directory '/' already present!
10573 11:06:17.359322 <3>[ 1.989082] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10574 11:06:17.368247 <6>[ 2.001476] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10575 11:06:17.375128 <6>[ 2.008104] xhci-mtk 11200000.usb: xHCI Host Controller
10576 11:06:17.381852 <6>[ 2.013590] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10577 11:06:17.392221 <6>[ 2.021548] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10578 11:06:17.398415 <6>[ 2.031008] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10579 11:06:17.405420 <6>[ 2.037088] xhci-mtk 11200000.usb: xHCI Host Controller
10580 11:06:17.411749 <6>[ 2.042572] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10581 11:06:17.418563 <6>[ 2.050228] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10582 11:06:17.425147 <6>[ 2.058091] hub 1-0:1.0: USB hub found
10583 11:06:17.428301 <6>[ 2.062110] hub 1-0:1.0: 1 port detected
10584 11:06:17.438275 <6>[ 2.066379] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10585 11:06:17.441729 <6>[ 2.075077] hub 2-0:1.0: USB hub found
10586 11:06:17.444866 <6>[ 2.079086] hub 2-0:1.0: 1 port detected
10587 11:06:17.454381 <6>[ 2.087257] mtk-msdc 11f70000.mmc: Got CD GPIO
10588 11:06:17.467557 <6>[ 2.097246] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10589 11:06:17.474071 <6>[ 2.105272] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10590 11:06:17.484054 <4>[ 2.113173] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10591 11:06:17.494020 <6>[ 2.122701] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10592 11:06:17.500363 <6>[ 2.130777] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10593 11:06:17.507218 <6>[ 2.138793] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10594 11:06:17.516912 <6>[ 2.146709] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10595 11:06:17.523847 <6>[ 2.154528] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10596 11:06:17.533855 <6>[ 2.162344] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10597 11:06:17.543717 <6>[ 2.172724] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10598 11:06:17.550540 <6>[ 2.181081] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10599 11:06:17.560196 <6>[ 2.189426] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10600 11:06:17.567016 <6>[ 2.197766] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10601 11:06:17.576879 <6>[ 2.206104] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10602 11:06:17.583469 <6>[ 2.214441] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10603 11:06:17.593036 <6>[ 2.222778] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10604 11:06:17.600480 <6>[ 2.231115] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10605 11:06:17.609988 <6>[ 2.239457] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10606 11:06:17.619575 <6>[ 2.247794] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10607 11:06:17.626445 <6>[ 2.256140] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10608 11:06:17.636143 <6>[ 2.264478] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10609 11:06:17.642885 <6>[ 2.272815] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10610 11:06:17.653392 <6>[ 2.281152] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10611 11:06:17.659311 <6>[ 2.289490] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10612 11:06:17.666242 <6>[ 2.298224] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10613 11:06:17.673101 <6>[ 2.305372] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10614 11:06:17.679103 <6>[ 2.312131] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10615 11:06:17.686279 <6>[ 2.318886] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10616 11:06:17.695870 <6>[ 2.325825] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10617 11:06:17.702920 <6>[ 2.332669] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10618 11:06:17.712495 <6>[ 2.341798] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10619 11:06:17.722476 <6>[ 2.350917] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10620 11:06:17.732389 <6>[ 2.360211] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10621 11:06:17.742470 <6>[ 2.369680] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10622 11:06:17.749018 <6>[ 2.379146] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10623 11:06:17.759096 <6>[ 2.388265] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10624 11:06:17.769119 <6>[ 2.397733] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10625 11:06:17.778563 <6>[ 2.406850] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10626 11:06:17.788427 <6>[ 2.416146] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10627 11:06:17.798605 <6>[ 2.426305] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10628 11:06:17.808683 <6>[ 2.437786] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10629 11:06:17.815271 <6>[ 2.447441] Trying to probe devices needed for running init ...
10630 11:06:17.853419 <6>[ 2.483302] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10631 11:06:18.008617 <6>[ 2.641260] hub 1-1:1.0: USB hub found
10632 11:06:18.011539 <6>[ 2.645776] hub 1-1:1.0: 4 ports detected
10633 11:06:18.021275 <6>[ 2.654339] hub 1-1:1.0: USB hub found
10634 11:06:18.024250 <6>[ 2.658687] hub 1-1:1.0: 4 ports detected
10635 11:06:18.133712 <6>[ 2.763584] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10636 11:06:18.159541 <6>[ 2.792269] hub 2-1:1.0: USB hub found
10637 11:06:18.162183 <6>[ 2.796729] hub 2-1:1.0: 3 ports detected
10638 11:06:18.170492 <6>[ 2.803812] hub 2-1:1.0: USB hub found
10639 11:06:18.173642 <6>[ 2.808256] hub 2-1:1.0: 3 ports detected
10640 11:06:18.349943 <6>[ 2.979387] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10641 11:06:18.481041 <6>[ 3.114365] hub 1-1.4:1.0: USB hub found
10642 11:06:18.484396 <6>[ 3.118887] hub 1-1.4:1.0: 2 ports detected
10643 11:06:18.492607 <6>[ 3.125979] hub 1-1.4:1.0: USB hub found
10644 11:06:18.496071 <6>[ 3.130538] hub 1-1.4:1.0: 2 ports detected
10645 11:06:18.561466 <6>[ 3.191387] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10646 11:06:18.793865 <6>[ 3.423352] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10647 11:06:18.985339 <6>[ 3.615344] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10648 11:06:30.098399 <6>[ 14.736358] ALSA device list:
10649 11:06:30.104904 <6>[ 14.739655] No soundcards found.
10650 11:06:30.112917 <6>[ 14.747609] Freeing unused kernel memory: 8448K
10651 11:06:30.116223 <6>[ 14.753016] Run /init as init process
10652 11:06:30.127962 Loading, please wait...
10653 11:06:30.152256 Starting version 247.3-7+deb11u4
10654 11:06:30.354403 <6>[ 14.985210] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10655 11:06:30.365343 <6>[ 14.999678] remoteproc remoteproc0: scp is available
10656 11:06:30.371784 <6>[ 15.005243] remoteproc remoteproc0: powering up scp
10657 11:06:30.378506 <6>[ 15.010400] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10658 11:06:30.385315 <6>[ 15.018902] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10659 11:06:30.391611 <3>[ 15.022300] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10660 11:06:30.402512 <3>[ 15.033561] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10661 11:06:30.409328 <3>[ 15.041921] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10662 11:06:30.417048 <6>[ 15.051539] mc: Linux media interface: v0.10
10663 11:06:30.423667 <3>[ 15.051524] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10664 11:06:30.430114 <6>[ 15.056478] usbcore: registered new device driver r8152-cfgselector
10665 11:06:30.440278 <6>[ 15.059273] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10666 11:06:30.446802 <6>[ 15.059293] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10667 11:06:30.456695 <6>[ 15.059298] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10668 11:06:30.463421 <3>[ 15.064241] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 11:06:30.469814 <6>[ 15.081691] videodev: Linux video capture interface: v2.00
10670 11:06:30.476658 <3>[ 15.086986] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10671 11:06:30.486636 <4>[ 15.096807] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10672 11:06:30.492913 <3>[ 15.103767] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10673 11:06:30.502892 <3>[ 15.103782] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10674 11:06:30.509954 <3>[ 15.110881] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 11:06:30.516197 <6>[ 15.113075] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10676 11:06:30.522785 <6>[ 15.116764] Bluetooth: Core ver 2.22
10677 11:06:30.526124 <6>[ 15.116843] NET: Registered PF_BLUETOOTH protocol family
10678 11:06:30.532566 <6>[ 15.116847] Bluetooth: HCI device and connection manager initialized
10679 11:06:30.539523 <6>[ 15.116880] Bluetooth: HCI socket layer initialized
10680 11:06:30.542752 <6>[ 15.116888] Bluetooth: L2CAP socket layer initialized
10681 11:06:30.549278 <6>[ 15.116896] Bluetooth: SCO socket layer initialized
10682 11:06:30.555806 <4>[ 15.117907] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10683 11:06:30.565992 <3>[ 15.125728] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10684 11:06:30.572758 <6>[ 15.180468] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10685 11:06:30.578986 <6>[ 15.183734] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10686 11:06:30.586053 <6>[ 15.183760] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10687 11:06:30.592369 <6>[ 15.183778] remoteproc remoteproc0: remote processor scp is now up
10688 11:06:30.603050 <3>[ 15.183773] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 11:06:30.609115 <3>[ 15.183787] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10690 11:06:30.619577 <3>[ 15.183844] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 11:06:30.625841 <3>[ 15.183850] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10692 11:06:30.635945 <3>[ 15.183855] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 11:06:30.642495 <3>[ 15.183862] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 11:06:30.649314 <3>[ 15.183867] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10695 11:06:30.659629 <3>[ 15.183896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10696 11:06:30.663087 <6>[ 15.188768] pci_bus 0000:00: root bus resource [bus 00-ff]
10697 11:06:30.672826 <6>[ 15.188774] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10698 11:06:30.682916 <6>[ 15.188778] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10699 11:06:30.685948 <6>[ 15.188815] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10700 11:06:30.695861 <4>[ 15.208644] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10701 11:06:30.702961 <4>[ 15.208644] Fallback method does not support PEC.
10702 11:06:30.709403 <6>[ 15.212013] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10703 11:06:30.715666 <6>[ 15.214563] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10704 11:06:30.725764 <6>[ 15.217867] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10705 11:06:30.735783 <6>[ 15.239763] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10706 11:06:30.739469 <6>[ 15.241620] pci 0000:00:00.0: supports D1 D2
10707 11:06:30.749194 <6>[ 15.250840] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10708 11:06:30.755550 <6>[ 15.257363] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10709 11:06:30.765513 <6>[ 15.258510] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10710 11:06:30.772279 <6>[ 15.269980] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10711 11:06:30.781838 <3>[ 15.272819] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10712 11:06:30.788708 <6>[ 15.273883] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10713 11:06:30.795396 <6>[ 15.284298] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10714 11:06:30.805105 <6>[ 15.289972] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10715 11:06:30.811684 <4>[ 15.318861] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10716 11:06:30.821627 <6>[ 15.320821] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10717 11:06:30.827898 <3>[ 15.321612] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10718 11:06:30.837829 <4>[ 15.327073] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10719 11:06:30.844552 <6>[ 15.340709] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10720 11:06:30.851106 <6>[ 15.341965] usbcore: registered new interface driver btusb
10721 11:06:30.860789 <4>[ 15.342459] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10722 11:06:30.867157 <3>[ 15.342466] Bluetooth: hci0: Failed to load firmware file (-2)
10723 11:06:30.873828 <3>[ 15.342469] Bluetooth: hci0: Failed to set up firmware (-2)
10724 11:06:30.883868 <4>[ 15.342472] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10725 11:06:30.890498 <6>[ 15.356888] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10726 11:06:30.894091 <6>[ 15.364779] pci 0000:01:00.0: supports D1 D2
10727 11:06:30.907337 <6>[ 15.376071] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10728 11:06:30.913896 <6>[ 15.379276] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10729 11:06:30.920529 <6>[ 15.391193] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10730 11:06:30.926960 <6>[ 15.395482] usbcore: registered new interface driver uvcvideo
10731 11:06:30.933631 <6>[ 15.395783] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10732 11:06:30.943509 <6>[ 15.403464] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10733 11:06:30.947144 <6>[ 15.415289] r8152 2-1.3:1.0 eth0: v1.12.13
10734 11:06:30.953532 <6>[ 15.421524] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10735 11:06:30.963256 <6>[ 15.421532] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10736 11:06:30.970206 <6>[ 15.421545] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10737 11:06:30.976381 <6>[ 15.427893] usbcore: registered new interface driver r8152
10738 11:06:30.982958 <6>[ 15.436141] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10739 11:06:30.989659 <6>[ 15.436153] pci 0000:00:00.0: PCI bridge to [bus 01]
10740 11:06:30.996091 <6>[ 15.477334] usbcore: registered new interface driver cdc_ether
10741 11:06:31.002695 <6>[ 15.484427] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10742 11:06:31.009663 <6>[ 15.484570] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10743 11:06:31.015996 <6>[ 15.506966] usbcore: registered new interface driver r8153_ecm
10744 11:06:31.022432 <6>[ 15.513138] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10745 11:06:31.029157 <6>[ 15.539513] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10746 11:06:31.032458 <6>[ 15.547706] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10747 11:06:31.061836 <5>[ 15.693173] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10748 11:06:31.082534 <5>[ 15.713936] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10749 11:06:31.089339 <5>[ 15.721346] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10750 11:06:31.099198 <4>[ 15.729788] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10751 11:06:31.105643 <6>[ 15.738671] cfg80211: failed to load regulatory.db
10752 11:06:31.152925 <6>[ 15.784207] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10753 11:06:31.159704 <6>[ 15.791713] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10754 11:06:31.183658 <6>[ 15.818377] mt7921e 0000:01:00.0: ASIC revision: 79610010
10755 11:06:31.287962 <6>[ 15.919074] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10756 11:06:31.291347 <6>[ 15.919074]
10757 11:06:31.302580 Begin: Loading essential drivers ... done.
10758 11:06:31.305812 Begin: Running /scripts/init-premount ... done.
10759 11:06:31.312318 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10760 11:06:31.322173 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10761 11:06:31.325666 Device /sys/class/net/enx002432307c7b found
10762 11:06:31.325747 done.
10763 11:06:31.359703 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10764 11:06:31.559485 <6>[ 16.190585] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10765 11:06:32.354133 <6>[ 16.988875] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10766 11:06:32.401934 <6>[ 17.036877] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10767 11:06:32.526118 IP-Config: no response after 2 secs - giving up
10768 11:06:32.559829 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10769 11:06:32.588694 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:a1 mtu 1500 DHCP
10770 11:06:33.297026 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10771 11:06:33.303834 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10772 11:06:33.310125 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10773 11:06:33.316986 host : mt8192-asurada-spherion-r0-cbg-2
10774 11:06:33.323554 domain : lava-rack
10775 11:06:33.330354 rootserver: 192.168.201.1 rootpath:
10776 11:06:33.330436 filename :
10777 11:06:33.417492 done.
10778 11:06:33.424675 Begin: Running /scripts/nfs-bottom ... done.
10779 11:06:33.442339 Begin: Running /scripts/init-bottom ... done.
10780 11:06:34.678418 <6>[ 19.313510] NET: Registered PF_INET6 protocol family
10781 11:06:34.686545 <6>[ 19.321279] Segment Routing with IPv6
10782 11:06:34.689483 <6>[ 19.325232] In-situ OAM (IOAM) with IPv6
10783 11:06:34.818863 <30>[ 19.434094] systemd[1]: systemd 247.3-7+deb11u4 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10784 11:06:34.825797 <30>[ 19.458511] systemd[1]: Detected architecture arm64.
10785 11:06:34.844909
10786 11:06:34.848064 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10787 11:06:34.848185
10788 11:06:34.867340 <30>[ 19.502183] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10789 11:06:35.711488 <30>[ 20.343234] systemd[1]: Queued start job for default target Graphical Interface.
10790 11:06:35.746881 <30>[ 20.381889] systemd[1]: Created slice system-getty.slice.
10791 11:06:35.753452 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10792 11:06:35.769390 <30>[ 20.404628] systemd[1]: Created slice system-modprobe.slice.
10793 11:06:35.776147 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10794 11:06:35.793258 <30>[ 20.428572] systemd[1]: Created slice system-serial\x2dgetty.slice.
10795 11:06:35.803670 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10796 11:06:35.817283 <30>[ 20.452377] systemd[1]: Created slice User and Session Slice.
10797 11:06:35.824030 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10798 11:06:35.844387 <30>[ 20.476195] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10799 11:06:35.854000 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10800 11:06:35.871805 <30>[ 20.503522] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10801 11:06:35.878405 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10802 11:06:35.899113 <30>[ 20.527438] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10803 11:06:35.905547 <30>[ 20.539609] systemd[1]: Reached target Local Encrypted Volumes.
10804 11:06:35.911938 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10805 11:06:35.928515 <30>[ 20.563855] systemd[1]: Reached target Paths.
10806 11:06:35.935329 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10807 11:06:35.948423 <30>[ 20.583320] systemd[1]: Reached target Remote File Systems.
10808 11:06:35.954955 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10809 11:06:35.972375 <30>[ 20.607603] systemd[1]: Reached target Slices.
10810 11:06:35.979155 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10811 11:06:35.992422 <30>[ 20.627334] systemd[1]: Reached target Swap.
10812 11:06:35.995340 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10813 11:06:36.016116 <30>[ 20.647804] systemd[1]: Listening on initctl Compatibility Named Pipe.
10814 11:06:36.022449 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10815 11:06:36.029061 <30>[ 20.664067] systemd[1]: Listening on Journal Audit Socket.
10816 11:06:36.035637 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10817 11:06:36.053474 <30>[ 20.688670] systemd[1]: Listening on Journal Socket (/dev/log).
10818 11:06:36.060001 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10819 11:06:36.076677 <30>[ 20.711886] systemd[1]: Listening on Journal Socket.
10820 11:06:36.083230 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10821 11:06:36.100719 <30>[ 20.732878] systemd[1]: Listening on Network Service Netlink Socket.
10822 11:06:36.107527 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10823 11:06:36.123172 <30>[ 20.758175] systemd[1]: Listening on udev Control Socket.
10824 11:06:36.129781 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10825 11:06:36.144549 <30>[ 20.779756] systemd[1]: Listening on udev Kernel Socket.
10826 11:06:36.151155 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10827 11:06:36.208286 <30>[ 20.843476] systemd[1]: Mounting Huge Pages File System...
10828 11:06:36.214857 Mounting [0;1;39mHuge Pages File System[0m...
10829 11:06:36.232489 <30>[ 20.867635] systemd[1]: Mounting POSIX Message Queue File System...
10830 11:06:36.239681 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10831 11:06:36.259576 <30>[ 20.894656] systemd[1]: Mounting Kernel Debug File System...
10832 11:06:36.265799 Mounting [0;1;39mKernel Debug File System[0m...
10833 11:06:36.284094 <30>[ 20.915835] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10834 11:06:36.323587 <30>[ 20.955920] systemd[1]: Starting Create list of static device nodes for the current kernel...
10835 11:06:36.333882 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10836 11:06:36.353145 <30>[ 20.988332] systemd[1]: Starting Load Kernel Module configfs...
10837 11:06:36.359790 Starting [0;1;39mLoad Kernel Module configfs[0m...
10838 11:06:36.380131 <30>[ 21.015289] systemd[1]: Starting Load Kernel Module drm...
10839 11:06:36.386848 Starting [0;1;39mLoad Kernel Module drm[0m...
10840 11:06:36.404866 <30>[ 21.040148] systemd[1]: Starting Load Kernel Module fuse...
10841 11:06:36.412055 Starting [0;1;39mLoad Kernel Module fuse[0m...
10842 11:06:36.432667 <30>[ 21.064546] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10843 11:06:36.464141 <6>[ 21.098970] fuse: init (API version 7.37)
10844 11:06:36.473181 <30>[ 21.108201] systemd[1]: Starting Journal Service...
10845 11:06:36.479835 Starting [0;1;39mJournal Service[0m...
10846 11:06:36.503258 <30>[ 21.138356] systemd[1]: Starting Load Kernel Modules...
10847 11:06:36.510443 Starting [0;1;39mLoad Kernel Modules[0m...
10848 11:06:36.531829 <30>[ 21.163128] systemd[1]: Starting Remount Root and Kernel File Systems...
10849 11:06:36.537663 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10850 11:06:36.556779 <30>[ 21.191945] systemd[1]: Starting Coldplug All udev Devices...
10851 11:06:36.563537 Starting [0;1;39mColdplug All udev Devices[0m...
10852 11:06:36.580713 <30>[ 21.216082] systemd[1]: Mounted Huge Pages File System.
10853 11:06:36.587561 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10854 11:06:36.604639 <30>[ 21.239932] systemd[1]: Mounted POSIX Message Queue File System.
10855 11:06:36.618364 [[0;32m OK [0m] Mounted [0;<3>[ 21.248904] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10856 11:06:36.621857 1;39mPOSIX Message Queue File System[0m.
10857 11:06:36.636489 <30>[ 21.271771] systemd[1]: Mounted Kernel Debug File System.
10858 11:06:36.643298 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10859 11:06:36.653212 <3>[ 21.283159] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10860 11:06:36.663108 <30>[ 21.293395] systemd[1]: Finished Create list of static device nodes for the current kernel.
10861 11:06:36.669756 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10862 11:06:36.685758 <30>[ 21.320586] systemd[1]: modprobe@configfs.service: Succeeded.
10863 11:06:36.693347 <30>[ 21.327971] systemd[1]: Finished Load Kernel Module configfs.
10864 11:06:36.703280 <3>[ 21.330255] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10865 11:06:36.709671 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10866 11:06:36.725718 <30>[ 21.360472] systemd[1]: modprobe@drm.service: Succeeded.
10867 11:06:36.735356 <3>[ 21.365405] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10868 11:06:36.739012 <30>[ 21.367014] systemd[1]: Finished Load Kernel Module drm.
10869 11:06:36.745375 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10870 11:06:36.763880 <3>[ 21.395831] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10871 11:06:36.770639 <30>[ 21.396808] systemd[1]: modprobe@fuse.service: Succeeded.
10872 11:06:36.777015 <30>[ 21.411656] systemd[1]: Finished Load Kernel Module fuse.
10873 11:06:36.784014 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10874 11:06:36.794330 <3>[ 21.425112] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 11:06:36.802446 <30>[ 21.437403] systemd[1]: Finished Load Kernel Modules.
10876 11:06:36.808893 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10877 11:06:36.822356 <3>[ 21.454421] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 11:06:36.833468 <30>[ 21.465608] systemd[1]: Finished Remount Root and Kernel File Systems.
10879 11:06:36.840102 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10880 11:06:36.853287 <3>[ 21.484924] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 11:06:36.882489 <3>[ 21.514325] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 11:06:36.898244 <30>[ 21.533661] systemd[1]: Mounting FUSE Control File System...
10883 11:06:36.905615 Mounting [0;1;39mFUSE Control File System[0m...
10884 11:06:36.916179 <3>[ 21.548304] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 11:06:36.930135 <30>[ 21.562017] systemd[1]: Mounting Kernel Configuration File System...
10886 11:06:36.933595 Mounting [0;1;39mKernel Configuration File System[0m...
10887 11:06:36.957097 <30>[ 21.588603] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10888 11:06:36.967377 <30>[ 21.597682] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10889 11:06:37.001195 <30>[ 21.636361] systemd[1]: Starting Load/Save Random Seed...
10890 11:06:37.007811 Starting [0;1;39mLoad/Save Random Seed[0m...
10891 11:06:37.023256 <30>[ 21.658718] systemd[1]: Starting Apply Kernel Variables...
10892 11:06:37.030230 Starting [0;1;39mApply Kernel Variables[0m...
10893 11:06:37.050573 <30>[ 21.685806] systemd[1]: Starting Create System Users...
10894 11:06:37.057488 Starting [0;1;39mCreate System Users[0m...
10895 11:06:37.074612 <30>[ 21.709995] systemd[1]: Started Journal Service.
10896 11:06:37.081795 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10897 11:06:37.101840 <4>[ 21.726765] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10898 11:06:37.111220 <3>[ 21.742644] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10899 11:06:37.114723 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10900 11:06:37.141706 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10901 11:06:37.155959 See 'systemctl status systemd-udev-trigger.service' for details.
10902 11:06:37.177160 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10903 11:06:37.198049 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10904 11:06:37.213856 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10905 11:06:37.230006 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10906 11:06:37.277083 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10907 11:06:37.296798 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10908 11:06:37.346076 <46>[ 21.978006] systemd-journald[292]: Received client request to flush runtime journal.
10909 11:06:37.412985 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10910 11:06:37.424647 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10911 11:06:37.440213 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10912 11:06:37.504443 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10913 11:06:38.761991 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10914 11:06:38.801106 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10915 11:06:38.867884 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10916 11:06:38.920829 Starting [0;1;39mNetwork Service[0m...
10917 11:06:39.257819 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10918 11:06:39.276073 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10919 11:06:39.328675 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10920 11:06:39.618473 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10921 11:06:39.635989 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10922 11:06:39.656897 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10923 11:06:39.696960 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10924 11:06:39.713120 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10925 11:06:39.733311 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10926 11:06:39.748334 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10927 11:06:39.824719 Starting [0;1;39mNetwork Name Resolution[0m...
10928 11:06:39.853798 Starting [0;1;39mNetwork Time Synchronization[0m...
10929 11:06:39.873520 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10930 11:06:39.938127 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10931 11:06:40.295509 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10932 11:06:40.312735 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10933 11:06:40.335279 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10934 11:06:40.352280 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10935 11:06:40.367812 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10936 11:06:40.395967 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10937 11:06:40.422044 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10938 11:06:40.447239 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10939 11:06:40.485985 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10940 11:06:40.500935 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10941 11:06:40.523248 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10942 11:06:40.535863 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10943 11:06:40.551857 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10944 11:06:40.592650 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10945 11:06:41.288033 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10946 11:06:41.672599 Starting [0;1;39mUser Login Management[0m...
10947 11:06:41.693140 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10948 11:06:41.715284 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10949 11:06:41.734908 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10950 11:06:41.792918 Starting [0;1;39mPermit User Sessions[0m...
10951 11:06:41.910674 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10952 11:06:41.948326 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10953 11:06:42.012626 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10954 11:06:42.018972 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10955 11:06:42.043451 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10956 11:06:42.065868 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10957 11:06:42.074369 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10958 11:06:42.098332 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10959 11:06:42.162134 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10960 11:06:42.203166 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10961 11:06:42.293393
10962 11:06:42.293519
10963 11:06:42.296938 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10964 11:06:42.297021
10965 11:06:42.300066 debian-bullseye-arm64 login: root (automatic login)
10966 11:06:42.300148
10967 11:06:42.300213
10968 11:06:42.619572 Linux debian-bullseye-arm64 6.1.80-cip16 #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024 aarch64
10969 11:06:42.619737
10970 11:06:42.626296 The programs included with the Debian GNU/Linux system are free software;
10971 11:06:42.632422 the exact distribution terms for each program are described in the
10972 11:06:42.636112 individual files in /usr/share/doc/*/copyright.
10973 11:06:42.636197
10974 11:06:42.642200 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10975 11:06:42.645639 permitted by applicable law.
10976 11:06:42.737083 Matched prompt #10: / #
10978 11:06:42.737338 Setting prompt string to ['/ #']
10979 11:06:42.737435 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10981 11:06:42.737630 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10982 11:06:42.737721 start: 2.2.6 expect-shell-connection (timeout 00:03:18) [common]
10983 11:06:42.737793 Setting prompt string to ['/ #']
10984 11:06:42.737854 Forcing a shell prompt, looking for ['/ #']
10986 11:06:42.788068 / #
10987 11:06:42.788170 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10988 11:06:42.788272 Waiting using forced prompt support (timeout 00:02:30)
10989 11:06:42.793240
10990 11:06:42.793567 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10991 11:06:42.793714 start: 2.2.7 export-device-env (timeout 00:03:18) [common]
10993 11:06:42.894075 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12925662/extract-nfsrootfs-7g5anr9b'
10994 11:06:42.899376 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12925662/extract-nfsrootfs-7g5anr9b'
10996 11:06:42.999922 / # export NFS_SERVER_IP='192.168.201.1'
10997 11:06:43.005427 export NFS_SERVER_IP='192.168.201.1'
10998 11:06:43.005715 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10999 11:06:43.005812 end: 2.2 depthcharge-retry (duration 00:01:42) [common]
11000 11:06:43.005899 end: 2 depthcharge-action (duration 00:01:42) [common]
11001 11:06:43.005993 start: 3 lava-test-retry (timeout 00:01:00) [common]
11002 11:06:43.006083 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11003 11:06:43.006162 Using namespace: common
11005 11:06:43.106494 / # #
11006 11:06:43.106628 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11007 11:06:43.111673 #
11008 11:06:43.111940 Using /lava-12925662
11010 11:06:43.212291 / # export SHELL=/bin/sh
11011 11:06:43.217580 export SHELL=/bin/sh
11013 11:06:43.318079 / # . /lava-12925662/environment
11014 11:06:43.324083 . /lava-12925662/environment
11016 11:06:43.430244 / # /lava-12925662/bin/lava-test-runner /lava-12925662/0
11017 11:06:43.430377 Test shell timeout: 10s (minimum of the action and connection timeout)
11018 11:06:43.435703 /lava-12925662/bin/lava-test-runner /lava-12925662/0
11019 11:06:43.693683 + export TESTRUN_ID=0_dmesg
11020 11:06:43.696688 + cd /lava-12925662/0/tests/0_dmesg
11021 11:06:43.700055 + cat uuid
11022 11:06:43.714324 + UUID=12925662_<8>[ 28.347210] <LAVA_SIGNAL_STARTRUN 0_dmesg 12925662_1.6.2.3.1>
11023 11:06:43.714472 1.6.2.3.1
11024 11:06:43.714573 + set +x
11025 11:06:43.714815 Received signal: <STARTRUN> 0_dmesg 12925662_1.6.2.3.1
11026 11:06:43.714885 Starting test lava.0_dmesg (12925662_1.6.2.3.1)
11027 11:06:43.714987 Skipping test definition patterns.
11028 11:06:43.720656 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11029 11:06:43.831423 <8>[ 28.464318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11030 11:06:43.831724 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11032 11:06:43.917160 <8>[ 28.550204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11033 11:06:43.917492 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11035 11:06:44.006541 <8>[ 28.639319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11036 11:06:44.006840 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11038 11:06:44.010382 + set +x
11039 11:06:44.013458 <8>[ 28.649009] <LAVA_SIGNAL_ENDRUN 0_dmesg 12925662_1.6.2.3.1>
11040 11:06:44.013769 Received signal: <ENDRUN> 0_dmesg 12925662_1.6.2.3.1
11041 11:06:44.013864 Ending use of test pattern.
11042 11:06:44.013956 Ending test lava.0_dmesg (12925662_1.6.2.3.1), duration 0.30
11044 11:06:44.022243 <LAVA_TEST_RUNNER EXIT>
11045 11:06:44.022495 ok: lava_test_shell seems to have completed
11046 11:06:44.022598 alert: pass
crit: pass
emerg: pass
11047 11:06:44.022687 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11048 11:06:44.022772 end: 3 lava-test-retry (duration 00:00:01) [common]
11049 11:06:44.022856 start: 4 lava-test-retry (timeout 00:01:00) [common]
11050 11:06:44.022937 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11051 11:06:44.023001 Using namespace: common
11053 11:06:44.123324 / # #
11054 11:06:44.123504 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11055 11:06:44.123659 Using /lava-12925662
11057 11:06:44.223980 export SHELL=/bin/sh
11058 11:06:44.224129 #
11060 11:06:44.324704 / # export SHELL=/bin/sh. /lava-12925662/environment
11061 11:06:44.324877
11063 11:06:44.425390 / # . /lava-12925662/environment/lava-12925662/bin/lava-test-runner /lava-12925662/1
11064 11:06:44.425516 Test shell timeout: 10s (minimum of the action and connection timeout)
11065 11:06:44.425689
11066 11:06:44.430953 / # /lava-12925662/bin/lava-test-runner /lava-12925662/1
11067 11:06:44.563649 + export TESTRUN_ID=1_bootrr
11068 11:06:44.567911 + cd /lava-12925662/1/tests/1_bootrr
11069 11:06:44.569591 + cat uuid
11070 11:06:44.584600 + UUID=12925662_1.<8>[ 29.217393] <LAVA_SIGNAL_STARTRUN 1_bootrr 12925662_1.6.2.3.5>
11071 11:06:44.584687 6.2.3.5
11072 11:06:44.584755 + set +x
11073 11:06:44.584992 Received signal: <STARTRUN> 1_bootrr 12925662_1.6.2.3.5
11074 11:06:44.585058 Starting test lava.1_bootrr (12925662_1.6.2.3.5)
11075 11:06:44.585138 Skipping test definition patterns.
11076 11:06:44.597621 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12925662/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11077 11:06:44.601735 + cd /opt/bootrr/libexec/bootrr
11078 11:06:44.601828 + sh helpers/bootrr-auto
11079 11:06:44.679736 /lava-12925662/1/../bin/lava-test-case
11080 11:06:44.713231 <8>[ 29.346044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11081 11:06:44.713503 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11083 11:06:44.764952 /lava-12925662/1/../bin/lava-test-case
11084 11:06:44.795854 <8>[ 29.428488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11085 11:06:44.796121 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11087 11:06:44.822810 /lava-12925662/1/../bin/lava-test-case
11088 11:06:44.853908 <8>[ 29.486162] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11089 11:06:44.854196 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11091 11:06:44.922237 /lava-12925662/1/../bin/lava-test-case
11092 11:06:44.953954 <8>[ 29.586662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11093 11:06:44.954219 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11095 11:06:44.997835 /lava-12925662/1/../bin/lava-test-case
11096 11:06:45.028628 <8>[ 29.661710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11097 11:06:45.028902 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11099 11:06:45.068850 /lava-12925662/1/../bin/lava-test-case
11100 11:06:45.099652 <8>[ 29.732158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11101 11:06:45.099926 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11103 11:06:45.141718 /lava-12925662/1/../bin/lava-test-case
11104 11:06:45.176101 <8>[ 29.809114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11105 11:06:45.176373 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11107 11:06:45.217211 /lava-12925662/1/../bin/lava-test-case
11108 11:06:45.251008 <8>[ 29.884021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11109 11:06:45.251274 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11111 11:06:45.283312 /lava-12925662/1/../bin/lava-test-case
11112 11:06:45.312301 <8>[ 29.945246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11113 11:06:45.312573 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11115 11:06:45.353322 /lava-12925662/1/../bin/lava-test-case
11116 11:06:45.385241 <8>[ 30.017711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11117 11:06:45.385505 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11119 11:06:45.409663 /lava-12925662/1/../bin/lava-test-case
11120 11:06:45.441425 <8>[ 30.073871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11121 11:06:45.441689 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11123 11:06:45.482072 /lava-12925662/1/../bin/lava-test-case
11124 11:06:45.512810 <8>[ 30.145859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11125 11:06:45.513072 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11127 11:06:45.553767 /lava-12925662/1/../bin/lava-test-case
11128 11:06:45.587443 <8>[ 30.220664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11129 11:06:45.587705 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11131 11:06:45.633354 /lava-12925662/1/../bin/lava-test-case
11132 11:06:45.662963 <8>[ 30.295569] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11133 11:06:45.663226 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11135 11:06:45.705673 /lava-12925662/1/../bin/lava-test-case
11136 11:06:45.739600 <8>[ 30.372429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11137 11:06:45.739867 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11139 11:06:45.765144 /lava-12925662/1/../bin/lava-test-case
11140 11:06:45.797238 <8>[ 30.430075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11141 11:06:45.797504 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11143 11:06:45.840438 /lava-12925662/1/../bin/lava-test-case
11144 11:06:45.871840 <8>[ 30.504975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11145 11:06:45.872132 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11147 11:06:45.896879 /lava-12925662/1/../bin/lava-test-case
11148 11:06:45.927462 <8>[ 30.560319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11149 11:06:45.927750 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11151 11:06:45.972843 /lava-12925662/1/../bin/lava-test-case
11152 11:06:46.005622 <8>[ 30.638733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11153 11:06:46.005889 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11155 11:06:46.033552 /lava-12925662/1/../bin/lava-test-case
11156 11:06:46.067291 <8>[ 30.700603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11157 11:06:46.067582 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11159 11:06:46.109126 /lava-12925662/1/../bin/lava-test-case
11160 11:06:46.141522 <8>[ 30.774757] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11161 11:06:46.141812 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11163 11:06:46.165211 /lava-12925662/1/../bin/lava-test-case
11164 11:06:46.197956 <8>[ 30.830852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11165 11:06:46.198251 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11167 11:06:46.239189 /lava-12925662/1/../bin/lava-test-case
11168 11:06:46.269979 <8>[ 30.902923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11169 11:06:46.270259 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11171 11:06:46.302233 /lava-12925662/1/../bin/lava-test-case
11172 11:06:46.329527 <8>[ 30.962299] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11173 11:06:46.329829 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11175 11:06:46.367480 /lava-12925662/1/../bin/lava-test-case
11176 11:06:46.398272 <8>[ 31.031421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11177 11:06:46.398563 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11179 11:06:46.435431 /lava-12925662/1/../bin/lava-test-case
11180 11:06:46.464863 <8>[ 31.098067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11181 11:06:46.465125 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11183 11:06:46.491748 /lava-12925662/1/../bin/lava-test-case
11184 11:06:46.520655 <8>[ 31.153768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11185 11:06:46.520916 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11187 11:06:46.561341 /lava-12925662/1/../bin/lava-test-case
11188 11:06:46.593968 <8>[ 31.226972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11189 11:06:46.594233 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11191 11:06:46.626174 /lava-12925662/1/../bin/lava-test-case
11192 11:06:46.654866 <8>[ 31.288004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11193 11:06:46.655127 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11195 11:06:46.694798 /lava-12925662/1/../bin/lava-test-case
11196 11:06:46.725904 <8>[ 31.358687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11197 11:06:46.726172 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11199 11:06:46.762615 /lava-12925662/1/../bin/lava-test-case
11200 11:06:46.793219 <8>[ 31.426370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11201 11:06:46.793480 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11203 11:06:46.834322 /lava-12925662/1/../bin/lava-test-case
11204 11:06:46.868296 <8>[ 31.501271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11205 11:06:46.868559 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11207 11:06:46.910733 /lava-12925662/1/../bin/lava-test-case
11208 11:06:46.939479 <8>[ 31.572483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11209 11:06:46.939779 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11211 11:06:46.970127 /lava-12925662/1/../bin/lava-test-case
11212 11:06:47.001533 <8>[ 31.634439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11213 11:06:47.001843 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11215 11:06:47.044494 /lava-12925662/1/../bin/lava-test-case
11216 11:06:47.074856 <8>[ 31.708198] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11217 11:06:47.075155 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11219 11:06:47.117231 /lava-12925662/1/../bin/lava-test-case
11220 11:06:47.152306 <8>[ 31.785056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11221 11:06:47.152569 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11223 11:06:47.175340 /lava-12925662/1/../bin/lava-test-case
11224 11:06:47.204252 <8>[ 31.837106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11225 11:06:47.204515 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11227 11:06:47.245795 /lava-12925662/1/../bin/lava-test-case
11228 11:06:47.281010 <8>[ 31.914270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11229 11:06:47.281332 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11231 11:06:47.312294 /lava-12925662/1/../bin/lava-test-case
11232 11:06:47.342230 <8>[ 31.975591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11233 11:06:47.342557 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11235 11:06:47.382514 /lava-12925662/1/../bin/lava-test-case
11236 11:06:47.417081 <8>[ 32.050035] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11237 11:06:47.417396 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11239 11:06:47.442884 /lava-12925662/1/../bin/lava-test-case
11240 11:06:47.477366 <8>[ 32.110654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11241 11:06:47.477680 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11243 11:06:47.519273 /lava-12925662/1/../bin/lava-test-case
11244 11:06:47.549123 <8>[ 32.182071] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11245 11:06:47.549435 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11247 11:06:47.573126 /lava-12925662/1/../bin/lava-test-case
11248 11:06:47.601724 <8>[ 32.234970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11249 11:06:47.602038 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11251 11:06:47.664270 /lava-12925662/1/../bin/lava-test-case
11252 11:06:47.695637 <8>[ 32.328718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11253 11:06:47.695958 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11255 11:06:47.721490 /lava-12925662/1/../bin/lava-test-case
11256 11:06:47.753354 <8>[ 32.386442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11257 11:06:47.753701 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11259 11:06:47.795844 /lava-12925662/1/../bin/lava-test-case
11260 11:06:47.829320 <8>[ 32.462700] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11261 11:06:47.829585 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11263 11:06:47.855172 /lava-12925662/1/../bin/lava-test-case
11264 11:06:47.887230 <8>[ 32.520646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11265 11:06:47.887510 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11267 11:06:47.928746 /lava-12925662/1/../bin/lava-test-case
11268 11:06:47.961908 <8>[ 32.595279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11269 11:06:47.962170 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11271 11:06:47.992698 /lava-12925662/1/../bin/lava-test-case
11272 11:06:48.023614 <8>[ 32.656941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11273 11:06:48.023878 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11275 11:06:48.063072 /lava-12925662/1/../bin/lava-test-case
11276 11:06:48.090440 <8>[ 32.723618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11277 11:06:48.090701 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11279 11:06:48.127140 /lava-12925662/1/../bin/lava-test-case
11280 11:06:48.156756 <8>[ 32.790048] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11281 11:06:48.157020 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11283 11:06:48.182525 /lava-12925662/1/../bin/lava-test-case
11284 11:06:48.211676 <8>[ 32.845116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11285 11:06:48.211939 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11287 11:06:48.254139 /lava-12925662/1/../bin/lava-test-case
11288 11:06:48.288025 <8>[ 32.921156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11289 11:06:48.288290 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11291 11:06:48.319627 /lava-12925662/1/../bin/lava-test-case
11292 11:06:48.355474 <8>[ 32.988182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11293 11:06:48.355771 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11295 11:06:48.397324 /lava-12925662/1/../bin/lava-test-case
11296 11:06:48.433786 <8>[ 33.066929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11297 11:06:48.434115 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11299 11:06:48.474196 /lava-12925662/1/../bin/lava-test-case
11300 11:06:48.505191 <8>[ 33.138199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11301 11:06:48.505513 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11303 11:06:48.545800 /lava-12925662/1/../bin/lava-test-case
11304 11:06:48.581387 <8>[ 33.214504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11305 11:06:48.581699 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11307 11:06:48.624568 /lava-12925662/1/../bin/lava-test-case
11308 11:06:48.663454 <8>[ 33.296640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11309 11:06:48.663723 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11311 11:06:48.705729 /lava-12925662/1/../bin/lava-test-case
11312 11:06:48.735205 <8>[ 33.368376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11313 11:06:48.735469 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11315 11:06:48.758334 /lava-12925662/1/../bin/lava-test-case
11316 11:06:48.790475 <8>[ 33.423669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11317 11:06:48.790740 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11319 11:06:48.832197 /lava-12925662/1/../bin/lava-test-case
11320 11:06:48.866596 <8>[ 33.499944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11321 11:06:48.866862 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11323 11:06:48.908158 /lava-12925662/1/../bin/lava-test-case
11324 11:06:48.944239 <8>[ 33.577041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11325 11:06:48.944503 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11327 11:06:48.975204 /lava-12925662/1/../bin/lava-test-case
11328 11:06:49.009197 <8>[ 33.642581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11329 11:06:49.009555 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11331 11:06:49.049179 /lava-12925662/1/../bin/lava-test-case
11332 11:06:49.080857 <8>[ 33.714474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11333 11:06:49.081175 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11335 11:06:49.105801 /lava-12925662/1/../bin/lava-test-case
11336 11:06:49.136949 <8>[ 33.770239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11337 11:06:49.137266 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11339 11:06:49.179103 /lava-12925662/1/../bin/lava-test-case
11340 11:06:49.210650 <8>[ 33.844121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11341 11:06:49.210911 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11343 11:06:49.236710 /lava-12925662/1/../bin/lava-test-case
11344 11:06:49.272435 <8>[ 33.905446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11345 11:06:49.272792 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11347 11:06:49.321291 /lava-12925662/1/../bin/lava-test-case
11348 11:06:49.356755 <8>[ 33.990166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11349 11:06:49.357075 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11351 11:06:49.398143 /lava-12925662/1/../bin/lava-test-case
11352 11:06:49.433024 <8>[ 34.066590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11353 11:06:49.433346 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11355 11:06:49.473861 /lava-12925662/1/../bin/lava-test-case
11356 11:06:49.505242 <8>[ 34.138661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11357 11:06:49.505585 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11359 11:06:49.548492 /lava-12925662/1/../bin/lava-test-case
11360 11:06:49.583392 <8>[ 34.217051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11361 11:06:49.583729 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11363 11:06:49.623659 /lava-12925662/1/../bin/lava-test-case
11364 11:06:49.658678 <8>[ 34.292390] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11365 11:06:49.658993 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11367 11:06:49.701757 /lava-12925662/1/../bin/lava-test-case
11368 11:06:49.737912 <8>[ 34.371205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11369 11:06:49.738234 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11371 11:06:49.779692 /lava-12925662/1/../bin/lava-test-case
11372 11:06:49.811149 <8>[ 34.444521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11373 11:06:49.811418 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11375 11:06:49.853089 /lava-12925662/1/../bin/lava-test-case
11376 11:06:49.889672 <8>[ 34.523258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11377 11:06:49.889987 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11379 11:06:49.933788 /lava-12925662/1/../bin/lava-test-case
11380 11:06:49.964550 <8>[ 34.597643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11381 11:06:49.964860 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11383 11:06:50.008473 /lava-12925662/1/../bin/lava-test-case
11384 11:06:50.040128 <8>[ 34.673917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11385 11:06:50.040451 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11387 11:06:50.081940 /lava-12925662/1/../bin/lava-test-case
11388 11:06:50.116062 <8>[ 34.749620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11389 11:06:50.116381 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11391 11:06:50.159267 /lava-12925662/1/../bin/lava-test-case
11392 11:06:50.191839 <8>[ 34.825136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11393 11:06:50.192154 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11395 11:06:50.234241 /lava-12925662/1/../bin/lava-test-case
11396 11:06:50.269403 <8>[ 34.902648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11397 11:06:50.269716 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11399 11:06:50.312090 /lava-12925662/1/../bin/lava-test-case
11400 11:06:50.347324 <8>[ 34.980807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11401 11:06:50.347685 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11403 11:06:50.397177 /lava-12925662/1/../bin/lava-test-case
11404 11:06:50.434310 <8>[ 35.067071] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11405 11:06:50.434653 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11407 11:06:50.459756 /lava-12925662/1/../bin/lava-test-case
11408 11:06:50.491227 <8>[ 35.124904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11409 11:06:50.491549 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11411 11:06:50.538308 /lava-12925662/1/../bin/lava-test-case
11412 11:06:50.573136 <8>[ 35.206683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11413 11:06:50.573489 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11415 11:06:50.597127 /lava-12925662/1/../bin/lava-test-case
11416 11:06:50.629113 <8>[ 35.262442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11417 11:06:50.629381 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11419 11:06:50.669051 /lava-12925662/1/../bin/lava-test-case
11420 11:06:50.698780 <8>[ 35.332154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11421 11:06:50.699087 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11423 11:06:50.729654 /lava-12925662/1/../bin/lava-test-case
11424 11:06:50.759958 <8>[ 35.393381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11425 11:06:50.760229 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11427 11:06:50.798044 /lava-12925662/1/../bin/lava-test-case
11428 11:06:50.825773 <8>[ 35.459185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11429 11:06:50.826046 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11431 11:06:50.849620 /lava-12925662/1/../bin/lava-test-case
11432 11:06:50.882258 <8>[ 35.515719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11433 11:06:50.882520 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11435 11:06:50.922944 /lava-12925662/1/../bin/lava-test-case
11436 11:06:50.956359 <8>[ 35.589401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11437 11:06:50.956630 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11439 11:06:50.980859 /lava-12925662/1/../bin/lava-test-case
11440 11:06:51.014027 <8>[ 35.647719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11441 11:06:51.014291 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11443 11:06:51.056028 /lava-12925662/1/../bin/lava-test-case
11444 11:06:51.089867 <8>[ 35.723305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11445 11:06:51.090133 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11447 11:06:51.116323 /lava-12925662/1/../bin/lava-test-case
11448 11:06:51.152167 <8>[ 35.784876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11449 11:06:51.152429 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11451 11:06:51.193058 /lava-12925662/1/../bin/lava-test-case
11452 11:06:51.225755 <8>[ 35.858785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11453 11:06:51.226024 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11455 11:06:51.266366 /lava-12925662/1/../bin/lava-test-case
11456 11:06:51.299704 <8>[ 35.933284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11457 11:06:51.299965 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11459 11:06:51.330503 /lava-12925662/1/../bin/lava-test-case
11460 11:06:51.366241 <8>[ 35.999951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11461 11:06:51.366516 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11463 11:06:51.409307 /lava-12925662/1/../bin/lava-test-case
11464 11:06:51.442445 <8>[ 36.075774] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11465 11:06:51.442709 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11467 11:06:51.467039 /lava-12925662/1/../bin/lava-test-case
11468 11:06:51.499064 <8>[ 36.132800] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11469 11:06:51.499325 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11471 11:06:51.542428 /lava-12925662/1/../bin/lava-test-case
11472 11:06:51.573875 <8>[ 36.207656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11473 11:06:51.574133 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11475 11:06:51.598161 /lava-12925662/1/../bin/lava-test-case
11476 11:06:51.629352 <8>[ 36.262822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11477 11:06:51.629647 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11479 11:06:52.693866 /lava-12925662/1/../bin/lava-test-case
11480 11:06:52.726243 <8>[ 37.359799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11481 11:06:52.726537 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11483 11:06:52.750526 /lava-12925662/1/../bin/lava-test-case
11484 11:06:52.779547 <8>[ 37.413064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11485 11:06:52.779810 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11487 11:06:53.829775 /lava-12925662/1/../bin/lava-test-case
11488 11:06:53.860894 <8>[ 38.494999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11489 11:06:53.861176 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11491 11:06:53.887259 /lava-12925662/1/../bin/lava-test-case
11492 11:06:53.919135 <8>[ 38.552902] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11493 11:06:53.919417 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11495 11:06:54.977954 /lava-12925662/1/../bin/lava-test-case
11496 11:06:55.017641 <8>[ 39.651374] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11497 11:06:55.018037 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11499 11:06:55.042573 /lava-12925662/1/../bin/lava-test-case
11500 11:06:55.077239 <8>[ 39.711166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11501 11:06:55.077626 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11503 11:06:56.129975 /lava-12925662/1/../bin/lava-test-case
11504 11:06:56.169679 <8>[ 40.803946] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11505 11:06:56.170056 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11507 11:06:56.196648 /lava-12925662/1/../bin/lava-test-case
11508 11:06:56.229299 <8>[ 40.863282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11509 11:06:56.229686 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11511 11:06:57.279324 /lava-12925662/1/../bin/lava-test-case
11512 11:06:57.312883 <8>[ 41.947376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11513 11:06:57.313208 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11515 11:06:57.339138 /lava-12925662/1/../bin/lava-test-case
11516 11:06:57.375306 <8>[ 42.009360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11517 11:06:57.375665 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11519 11:06:58.425991 /lava-12925662/1/../bin/lava-test-case
11520 11:06:58.460961 <8>[ 43.095548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11521 11:06:58.461394 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11523 11:06:58.485445 /lava-12925662/1/../bin/lava-test-case
11524 11:06:58.515302 <8>[ 43.149558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11525 11:06:58.515719 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11527 11:06:59.567822 /lava-12925662/1/../bin/lava-test-case
11528 11:06:59.602545 <8>[ 44.236892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11529 11:06:59.602914 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11531 11:06:59.628416 /lava-12925662/1/../bin/lava-test-case
11532 11:06:59.663082 <8>[ 44.297735] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11533 11:06:59.663457 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11535 11:06:59.691639 /lava-12925662/1/../bin/lava-test-case
11536 11:06:59.724075 <8>[ 44.359002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11537 11:06:59.724451 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11539 11:07:00.781455 /lava-12925662/1/../bin/lava-test-case
11540 11:07:00.814374 <8>[ 45.449217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11541 11:07:00.814755 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11543 11:07:00.839062 /lava-12925662/1/../bin/lava-test-case
11544 11:07:00.868812 <8>[ 45.503619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11545 11:07:00.869143 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11547 11:07:00.910840 /lava-12925662/1/../bin/lava-test-case
11548 11:07:00.941476 <8>[ 45.576433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11549 11:07:00.941810 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11551 11:07:00.967620 /lava-12925662/1/../bin/lava-test-case
11552 11:07:00.999417 <8>[ 45.633974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11553 11:07:00.999742 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11555 11:07:01.039489 /lava-12925662/1/../bin/lava-test-case
11556 11:07:01.067483 <8>[ 45.701888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11557 11:07:01.067919 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11559 11:07:01.112684 /lava-12925662/1/../bin/lava-test-case
11560 11:07:01.142538 <8>[ 45.777345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11561 11:07:01.142898 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11563 11:07:01.186238 /lava-12925662/1/../bin/lava-test-case
11564 11:07:01.221473 <8>[ 45.855623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11565 11:07:01.221805 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11567 11:07:01.246211 /lava-12925662/1/../bin/lava-test-case
11568 11:07:01.275670 <8>[ 45.910353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11569 11:07:01.276031 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11571 11:07:01.316621 /lava-12925662/1/../bin/lava-test-case
11572 11:07:01.348668 <8>[ 45.983476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11573 11:07:01.348954 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11575 11:07:01.388232 /lava-12925662/1/../bin/lava-test-case
11576 11:07:01.421531 <8>[ 46.056388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11577 11:07:01.421888 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11579 11:07:01.455050 /lava-12925662/1/../bin/lava-test-case
11580 11:07:01.486812 <8>[ 46.121872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11581 11:07:01.487219 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11583 11:07:01.517910 <6>[ 46.159226] vpu: disabling
11584 11:07:01.521310 <6>[ 46.162340] vproc2: disabling
11585 11:07:01.524755 <6>[ 46.166188] vproc1: disabling
11586 11:07:01.528076 <6>[ 46.169707] vaud18: disabling
11587 11:07:01.535941 <6>[ 46.173452] vsram_others: disabling
11588 11:07:01.539055 <6>[ 46.177702] va09: disabling
11589 11:07:01.541868 <6>[ 46.181127] vsram_md: disabling
11590 11:07:01.545082 <6>[ 46.184971] Vgpu: disabling
11591 11:07:01.551687 /lava-12925662/1/../bin/lava-test-case
11592 11:07:01.584961 <8>[ 46.219742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11593 11:07:01.585372 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11595 11:07:01.612169 /lava-12925662/1/../bin/lava-test-case
11596 11:07:01.645112 <8>[ 46.279637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11597 11:07:01.645489 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11599 11:07:01.686496 /lava-12925662/1/../bin/lava-test-case
11600 11:07:01.720040 <8>[ 46.354775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11601 11:07:01.720371 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11603 11:07:01.747066 /lava-12925662/1/../bin/lava-test-case
11604 11:07:01.779850 <8>[ 46.414269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11605 11:07:01.780180 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11607 11:07:01.833175 /lava-12925662/1/../bin/lava-test-case
11608 11:07:01.867070 <8>[ 46.501862] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11609 11:07:01.867458 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11611 11:07:01.895669 /lava-12925662/1/../bin/lava-test-case
11612 11:07:01.928610 <8>[ 46.563226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11613 11:07:01.929053 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11615 11:07:01.969145 /lava-12925662/1/../bin/lava-test-case
11616 11:07:02.002266 <8>[ 46.637227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11617 11:07:02.002619 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11619 11:07:02.031064 /lava-12925662/1/../bin/lava-test-case
11620 11:07:02.063165 <8>[ 46.697635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11621 11:07:02.063538 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11623 11:07:02.104540 /lava-12925662/1/../bin/lava-test-case
11624 11:07:02.140931 <8>[ 46.775803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11625 11:07:02.141253 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11627 11:07:02.165077 /lava-12925662/1/../bin/lava-test-case
11628 11:07:02.194352 <8>[ 46.829101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11629 11:07:02.194735 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11631 11:07:03.250249 /lava-12925662/1/../bin/lava-test-case
11632 11:07:03.283814 <8>[ 47.918897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11633 11:07:03.284112 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11635 11:07:04.340783 /lava-12925662/1/../bin/lava-test-case
11636 11:07:04.374322 <8>[ 49.009366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11637 11:07:04.374665 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11639 11:07:04.401026 /lava-12925662/1/../bin/lava-test-case
11640 11:07:04.433794 <8>[ 49.068924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11641 11:07:04.434079 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11643 11:07:04.475500 /lava-12925662/1/../bin/lava-test-case
11644 11:07:04.508493 <8>[ 49.143518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11645 11:07:04.508769 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11647 11:07:04.533911 /lava-12925662/1/../bin/lava-test-case
11648 11:07:04.568355 <8>[ 49.199369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11649 11:07:04.568694 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11651 11:07:04.604814 /lava-12925662/1/../bin/lava-test-case
11652 11:07:04.633942 <8>[ 49.269087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11653 11:07:04.634250 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11655 11:07:04.667743 /lava-12925662/1/../bin/lava-test-case
11656 11:07:04.700747 <8>[ 49.335924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11657 11:07:04.701034 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11659 11:07:04.739414 /lava-12925662/1/../bin/lava-test-case
11660 11:07:04.771551 <8>[ 49.406561] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11661 11:07:04.771841 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11663 11:07:04.795774 /lava-12925662/1/../bin/lava-test-case
11664 11:07:04.828473 <8>[ 49.463671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11665 11:07:04.828747 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11667 11:07:04.867406 /lava-12925662/1/../bin/lava-test-case
11668 11:07:04.901185 <8>[ 49.536582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11669 11:07:04.901470 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11671 11:07:04.931305 /lava-12925662/1/../bin/lava-test-case
11672 11:07:04.962988 <8>[ 49.598175] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11673 11:07:04.963299 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11675 11:07:05.010265 /lava-12925662/1/../bin/lava-test-case
11676 11:07:05.042995 <8>[ 49.678123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11677 11:07:05.043319 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11679 11:07:05.067811 /lava-12925662/1/../bin/lava-test-case
11680 11:07:05.101354 <8>[ 49.736515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11681 11:07:05.101628 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11683 11:07:05.141621 /lava-12925662/1/../bin/lava-test-case
11684 11:07:05.175438 <8>[ 49.810470] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11685 11:07:05.175761 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11687 11:07:05.199936 /lava-12925662/1/../bin/lava-test-case
11688 11:07:05.233445 <8>[ 49.868476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11689 11:07:05.233801 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11691 11:07:05.274423 /lava-12925662/1/../bin/lava-test-case
11692 11:07:05.307278 <8>[ 49.942518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11693 11:07:05.307583 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11695 11:07:05.338970 /lava-12925662/1/../bin/lava-test-case
11696 11:07:05.373611 <8>[ 50.008576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11697 11:07:05.374013 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11699 11:07:05.413578 /lava-12925662/1/../bin/lava-test-case
11700 11:07:05.446211 <8>[ 50.081421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11701 11:07:05.446545 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11703 11:07:05.471971 /lava-12925662/1/../bin/lava-test-case
11704 11:07:05.507745 <8>[ 50.142701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11705 11:07:05.508069 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11707 11:07:05.548811 /lava-12925662/1/../bin/lava-test-case
11708 11:07:05.582150 <8>[ 50.217351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11709 11:07:05.582472 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11711 11:07:05.607207 /lava-12925662/1/../bin/lava-test-case
11712 11:07:05.639627 <8>[ 50.274443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11713 11:07:05.640036 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11715 11:07:05.686376 /lava-12925662/1/../bin/lava-test-case
11716 11:07:05.717041 <8>[ 50.352315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11717 11:07:05.717431 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11719 11:07:06.756553 /lava-12925662/1/../bin/lava-test-case
11720 11:07:06.791115 <8>[ 51.426465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11721 11:07:06.791446 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11723 11:07:07.827290 /lava-12925662/1/../bin/lava-test-case
11724 11:07:07.861770 <8>[ 52.497178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11725 11:07:07.862180 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11726 11:07:07.862361 Bad test result: blocked
11727 11:07:07.887919 /lava-12925662/1/../bin/lava-test-case
11728 11:07:07.918603 <8>[ 52.553996] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11729 11:07:07.918929 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11731 11:07:08.974740 /lava-12925662/1/../bin/lava-test-case
11732 11:07:09.009872 <8>[ 53.645285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11733 11:07:09.010225 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11735 11:07:09.036050 /lava-12925662/1/../bin/lava-test-case
11736 11:07:09.066115 <8>[ 53.701330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11737 11:07:09.066444 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11739 11:07:09.103641 /lava-12925662/1/../bin/lava-test-case
11740 11:07:09.136983 <8>[ 53.772608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11741 11:07:09.137313 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11743 11:07:09.175774 /lava-12925662/1/../bin/lava-test-case
11744 11:07:09.210908 <8>[ 53.846374] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11745 11:07:09.211317 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11747 11:07:09.236527 /lava-12925662/1/../bin/lava-test-case
11748 11:07:09.270865 <8>[ 53.906046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11749 11:07:09.271275 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11751 11:07:09.317926 /lava-12925662/1/../bin/lava-test-case
11752 11:07:09.351357 <8>[ 53.987121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11753 11:07:09.351788 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11755 11:07:09.379248 /lava-12925662/1/../bin/lava-test-case
11756 11:07:09.412010 <8>[ 54.047607] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11757 11:07:09.412414 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11759 11:07:10.465590 /lava-12925662/1/../bin/lava-test-case
11760 11:07:10.499757 <8>[ 55.135821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11761 11:07:10.500144 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11763 11:07:10.523622 /lava-12925662/1/../bin/lava-test-case
11764 11:07:10.556904 <8>[ 55.192705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11765 11:07:10.557343 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11767 11:07:11.610877 /lava-12925662/1/../bin/lava-test-case
11768 11:07:11.647207 <8>[ 56.282762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11769 11:07:11.647567 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11771 11:07:11.671885 /lava-12925662/1/../bin/lava-test-case
11772 11:07:11.706625 <8>[ 56.342680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11773 11:07:11.706970 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11775 11:07:12.760756 /lava-12925662/1/../bin/lava-test-case
11776 11:07:12.802745 <8>[ 57.438787] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11777 11:07:12.803125 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11779 11:07:12.827198 /lava-12925662/1/../bin/lava-test-case
11780 11:07:12.860449 <8>[ 57.496558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11781 11:07:12.860782 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11783 11:07:13.914327 /lava-12925662/1/../bin/lava-test-case
11784 11:07:13.949304 <8>[ 58.585649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11785 11:07:13.949649 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11787 11:07:13.976170 /lava-12925662/1/../bin/lava-test-case
11788 11:07:14.008538 <8>[ 58.644598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11789 11:07:14.008857 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11791 11:07:14.051084 /lava-12925662/1/../bin/lava-test-case
11792 11:07:14.083223 <8>[ 58.719376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11793 11:07:14.083603 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11795 11:07:14.123237 /lava-12925662/1/../bin/lava-test-case
11796 11:07:14.157063 <8>[ 58.793108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11797 11:07:14.157394 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11799 11:07:14.181575 /lava-12925662/1/../bin/lava-test-case
11800 11:07:14.210934 <8>[ 58.847287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11801 11:07:14.211269 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11803 11:07:14.255377 /lava-12925662/1/../bin/lava-test-case
11804 11:07:14.286069 <8>[ 58.922301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11805 11:07:14.286359 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11807 11:07:14.310935 /lava-12925662/1/../bin/lava-test-case
11808 11:07:14.340171 <8>[ 58.976717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11809 11:07:14.340501 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11811 11:07:14.381560 /lava-12925662/1/../bin/lava-test-case
11812 11:07:14.414183 <8>[ 59.050610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11813 11:07:14.414535 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11815 11:07:14.439717 /lava-12925662/1/../bin/lava-test-case
11816 11:07:14.473506 <8>[ 59.109803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11817 11:07:14.473832 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11819 11:07:14.516478 /lava-12925662/1/../bin/lava-test-case
11820 11:07:14.549512 <8>[ 59.185618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11821 11:07:14.549838 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11823 11:07:14.562089 + set +x
11824 11:07:14.565761 Received signal: <ENDRUN> 1_bootrr 12925662_1.6.2.3.5
11825 11:07:14.565914 Ending use of test pattern.
11826 11:07:14.566032 Ending test lava.1_bootrr (12925662_1.6.2.3.5), duration 29.98
11828 11:07:14.568739 <8>[ 59.204838] <LAVA_SIGNAL_ENDRUN 1_bootrr 12925662_1.6.2.3.5>
11829 11:07:14.574304 <LAVA_TEST_RUNNER EXIT>
11830 11:07:14.574601 ok: lava_test_shell seems to have completed
11831 11:07:14.576039 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11832 11:07:14.576187 end: 4.1 lava-test-shell (duration 00:00:31) [common]
11833 11:07:14.576275 end: 4 lava-test-retry (duration 00:00:31) [common]
11834 11:07:14.576390 start: 5 finalize (timeout 00:07:18) [common]
11835 11:07:14.576527 start: 5.1 power-off (timeout 00:00:30) [common]
11836 11:07:14.576799 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11837 11:07:14.654871 >> Command sent successfully.
11838 11:07:14.657367 Returned 0 in 0 seconds
11839 11:07:14.757792 end: 5.1 power-off (duration 00:00:00) [common]
11841 11:07:14.758142 start: 5.2 read-feedback (timeout 00:07:18) [common]
11842 11:07:14.758451 Listened to connection for namespace 'common' for up to 1s
11843 11:07:15.759416 Finalising connection for namespace 'common'
11844 11:07:15.759615 Disconnecting from shell: Finalise
11845 11:07:15.759704 / #
11846 11:07:15.860071 end: 5.2 read-feedback (duration 00:00:01) [common]
11847 11:07:15.860252 end: 5 finalize (duration 00:00:01) [common]
11848 11:07:15.860370 Cleaning after the job
11849 11:07:15.860470 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925662/tftp-deploy-40xl1zo3/ramdisk
11850 11:07:15.863297 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925662/tftp-deploy-40xl1zo3/kernel
11851 11:07:15.876546 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925662/tftp-deploy-40xl1zo3/dtb
11852 11:07:15.876737 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925662/tftp-deploy-40xl1zo3/nfsrootfs
11853 11:07:15.952698 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925662/tftp-deploy-40xl1zo3/modules
11854 11:07:15.960120 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12925662
11855 11:07:16.340600 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12925662
11856 11:07:16.340781 Job finished correctly