Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 32
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 16
1 11:03:58.382508 lava-dispatcher, installed at version: 2024.01
2 11:03:58.382731 start: 0 validate
3 11:03:58.382858 Start time: 2024-03-03 11:03:58.382851+00:00 (UTC)
4 11:03:58.382976 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:03:58.383099 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240129.0%2Farm64%2Frootfs.cpio.gz exists
6 11:03:58.653805 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:03:58.654517 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:04:22.421959 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:04:22.422672 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:04:22.692374 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:04:22.693188 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:04:25.966255 validate duration: 27.58
14 11:04:25.967567 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:04:25.968170 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:04:25.968664 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:04:25.969339 Not decompressing ramdisk as can be used compressed.
18 11:04:25.969796 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240129.0/arm64/rootfs.cpio.gz
19 11:04:25.970205 saving as /var/lib/lava/dispatcher/tmp/12925608/tftp-deploy-eut2f_1y/ramdisk/rootfs.cpio.gz
20 11:04:25.970561 total size: 47861385 (45 MB)
21 11:04:26.239417 progress 0 % (0 MB)
22 11:04:26.252326 progress 5 % (2 MB)
23 11:04:26.264847 progress 10 % (4 MB)
24 11:04:26.277119 progress 15 % (6 MB)
25 11:04:26.289363 progress 20 % (9 MB)
26 11:04:26.301718 progress 25 % (11 MB)
27 11:04:26.313985 progress 30 % (13 MB)
28 11:04:26.326275 progress 35 % (16 MB)
29 11:04:26.338793 progress 40 % (18 MB)
30 11:04:26.351512 progress 45 % (20 MB)
31 11:04:26.364305 progress 50 % (22 MB)
32 11:04:26.377011 progress 55 % (25 MB)
33 11:04:26.389514 progress 60 % (27 MB)
34 11:04:26.401793 progress 65 % (29 MB)
35 11:04:26.414108 progress 70 % (31 MB)
36 11:04:26.426366 progress 75 % (34 MB)
37 11:04:26.438644 progress 80 % (36 MB)
38 11:04:26.451463 progress 85 % (38 MB)
39 11:04:26.464045 progress 90 % (41 MB)
40 11:04:26.476716 progress 95 % (43 MB)
41 11:04:26.489017 progress 100 % (45 MB)
42 11:04:26.489238 45 MB downloaded in 0.52 s (88.00 MB/s)
43 11:04:26.489398 end: 1.1.1 http-download (duration 00:00:01) [common]
45 11:04:26.489633 end: 1.1 download-retry (duration 00:00:01) [common]
46 11:04:26.489719 start: 1.2 download-retry (timeout 00:09:59) [common]
47 11:04:26.489802 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 11:04:26.489940 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:04:26.490007 saving as /var/lib/lava/dispatcher/tmp/12925608/tftp-deploy-eut2f_1y/kernel/Image
50 11:04:26.490066 total size: 51599872 (49 MB)
51 11:04:26.490126 No compression specified
52 11:04:26.491316 progress 0 % (0 MB)
53 11:04:26.504851 progress 5 % (2 MB)
54 11:04:26.518256 progress 10 % (4 MB)
55 11:04:26.531570 progress 15 % (7 MB)
56 11:04:26.544837 progress 20 % (9 MB)
57 11:04:26.558249 progress 25 % (12 MB)
58 11:04:26.571744 progress 30 % (14 MB)
59 11:04:26.585357 progress 35 % (17 MB)
60 11:04:26.598410 progress 40 % (19 MB)
61 11:04:26.611750 progress 45 % (22 MB)
62 11:04:26.625245 progress 50 % (24 MB)
63 11:04:26.638758 progress 55 % (27 MB)
64 11:04:26.652147 progress 60 % (29 MB)
65 11:04:26.665634 progress 65 % (32 MB)
66 11:04:26.679302 progress 70 % (34 MB)
67 11:04:26.692774 progress 75 % (36 MB)
68 11:04:26.706025 progress 80 % (39 MB)
69 11:04:26.719277 progress 85 % (41 MB)
70 11:04:26.732614 progress 90 % (44 MB)
71 11:04:26.746056 progress 95 % (46 MB)
72 11:04:26.759561 progress 100 % (49 MB)
73 11:04:26.759795 49 MB downloaded in 0.27 s (182.44 MB/s)
74 11:04:26.759947 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:04:26.760174 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:04:26.760263 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:04:26.760350 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:04:26.760489 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:04:26.760556 saving as /var/lib/lava/dispatcher/tmp/12925608/tftp-deploy-eut2f_1y/dtb/mt8192-asurada-spherion-r0.dtb
81 11:04:26.760617 total size: 47278 (0 MB)
82 11:04:26.760677 No compression specified
83 11:04:26.761824 progress 69 % (0 MB)
84 11:04:26.762098 progress 100 % (0 MB)
85 11:04:26.762252 0 MB downloaded in 0.00 s (27.61 MB/s)
86 11:04:26.762370 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:04:26.762587 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:04:26.762670 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:04:26.762750 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:04:26.762860 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:04:26.762926 saving as /var/lib/lava/dispatcher/tmp/12925608/tftp-deploy-eut2f_1y/modules/modules.tar
93 11:04:26.762984 total size: 8628476 (8 MB)
94 11:04:26.763043 Using unxz to decompress xz
95 11:04:26.767209 progress 0 % (0 MB)
96 11:04:26.787489 progress 5 % (0 MB)
97 11:04:26.811214 progress 10 % (0 MB)
98 11:04:26.834920 progress 15 % (1 MB)
99 11:04:26.857421 progress 20 % (1 MB)
100 11:04:26.882294 progress 25 % (2 MB)
101 11:04:26.907217 progress 30 % (2 MB)
102 11:04:26.936887 progress 35 % (2 MB)
103 11:04:26.963722 progress 40 % (3 MB)
104 11:04:26.989466 progress 45 % (3 MB)
105 11:04:27.015236 progress 50 % (4 MB)
106 11:04:27.041241 progress 55 % (4 MB)
107 11:04:27.066482 progress 60 % (4 MB)
108 11:04:27.092925 progress 65 % (5 MB)
109 11:04:27.117672 progress 70 % (5 MB)
110 11:04:27.142468 progress 75 % (6 MB)
111 11:04:27.170506 progress 80 % (6 MB)
112 11:04:27.196524 progress 85 % (7 MB)
113 11:04:27.222170 progress 90 % (7 MB)
114 11:04:27.253811 progress 95 % (7 MB)
115 11:04:27.284653 progress 100 % (8 MB)
116 11:04:27.289983 8 MB downloaded in 0.53 s (15.61 MB/s)
117 11:04:27.290265 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:04:27.290520 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:04:27.290657 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:04:27.290782 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:04:27.290874 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:04:27.290962 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:04:27.291225 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq
125 11:04:27.291362 makedir: /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin
126 11:04:27.291481 makedir: /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/tests
127 11:04:27.291592 makedir: /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/results
128 11:04:27.291710 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-add-keys
129 11:04:27.291856 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-add-sources
130 11:04:27.291987 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-background-process-start
131 11:04:27.292117 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-background-process-stop
132 11:04:27.292242 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-common-functions
133 11:04:27.292381 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-echo-ipv4
134 11:04:27.292522 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-install-packages
135 11:04:27.292645 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-installed-packages
136 11:04:27.292804 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-os-build
137 11:04:27.292927 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-probe-channel
138 11:04:27.293054 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-probe-ip
139 11:04:27.293209 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-target-ip
140 11:04:27.293334 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-target-mac
141 11:04:27.293474 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-target-storage
142 11:04:27.293618 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-test-case
143 11:04:27.293744 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-test-event
144 11:04:27.293868 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-test-feedback
145 11:04:27.294020 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-test-raise
146 11:04:27.294174 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-test-reference
147 11:04:27.294297 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-test-runner
148 11:04:27.294434 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-test-set
149 11:04:27.294573 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-test-shell
150 11:04:27.294705 Updating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-install-packages (oe)
151 11:04:27.294889 Updating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/bin/lava-installed-packages (oe)
152 11:04:27.295029 Creating /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/environment
153 11:04:27.295130 LAVA metadata
154 11:04:27.295215 - LAVA_JOB_ID=12925608
155 11:04:27.295294 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:04:27.295407 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:04:27.295488 skipped lava-vland-overlay
158 11:04:27.295590 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:04:27.295673 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:04:27.295766 skipped lava-multinode-overlay
161 11:04:27.295870 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:04:27.295982 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:04:27.296086 Loading test definitions
164 11:04:27.296209 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:04:27.296293 Using /lava-12925608 at stage 0
166 11:04:27.296604 uuid=12925608_1.5.2.3.1 testdef=None
167 11:04:27.296692 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:04:27.296797 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:04:27.297360 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:04:27.297624 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:04:27.298241 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:04:27.298500 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:04:27.299211 runner path: /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/0/tests/0_igt-gpu-panfrost test_uuid 12925608_1.5.2.3.1
176 11:04:27.299384 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:04:27.299586 Creating lava-test-runner.conf files
179 11:04:27.299647 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12925608/lava-overlay-fdl695iq/lava-12925608/0 for stage 0
180 11:04:27.299735 - 0_igt-gpu-panfrost
181 11:04:27.299829 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:04:27.299910 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:04:27.307637 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:04:27.307743 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:04:27.307841 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:04:27.307927 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:04:27.308042 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:04:29.131185 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 11:04:29.131602 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 11:04:29.131767 extracting modules file /var/lib/lava/dispatcher/tmp/12925608/tftp-deploy-eut2f_1y/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925608/extract-overlay-ramdisk-xyc7noqr/ramdisk
191 11:04:29.369280 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:04:29.369457 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 11:04:29.369559 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925608/compress-overlay-myzjjh80/overlay-1.5.2.4.tar.gz to ramdisk
194 11:04:29.369632 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925608/compress-overlay-myzjjh80/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12925608/extract-overlay-ramdisk-xyc7noqr/ramdisk
195 11:04:29.376521 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:04:29.376642 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 11:04:29.376790 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:04:29.376896 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 11:04:29.376978 Building ramdisk /var/lib/lava/dispatcher/tmp/12925608/extract-overlay-ramdisk-xyc7noqr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12925608/extract-overlay-ramdisk-xyc7noqr/ramdisk
200 11:04:30.677742 >> 465512 blocks
201 11:04:36.826203 rename /var/lib/lava/dispatcher/tmp/12925608/extract-overlay-ramdisk-xyc7noqr/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12925608/tftp-deploy-eut2f_1y/ramdisk/ramdisk.cpio.gz
202 11:04:36.826662 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 11:04:36.826787 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 11:04:36.826890 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 11:04:36.827001 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12925608/tftp-deploy-eut2f_1y/kernel/Image'
206 11:04:49.378813 Returned 0 in 12 seconds
207 11:04:49.479462 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12925608/tftp-deploy-eut2f_1y/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12925608/tftp-deploy-eut2f_1y/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12925608/tftp-deploy-eut2f_1y/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12925608/tftp-deploy-eut2f_1y/kernel/image.itb
208 11:04:50.389560 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:04:50.389944 output: Created: Sun Mar 3 11:04:50 2024
210 11:04:50.390020 output: Image 0 (kernel-1)
211 11:04:50.390088 output: Description:
212 11:04:50.390152 output: Created: Sun Mar 3 11:04:50 2024
213 11:04:50.390211 output: Type: Kernel Image
214 11:04:50.390269 output: Compression: lzma compressed
215 11:04:50.390323 output: Data Size: 12057697 Bytes = 11775.09 KiB = 11.50 MiB
216 11:04:50.390378 output: Architecture: AArch64
217 11:04:50.390434 output: OS: Linux
218 11:04:50.390501 output: Load Address: 0x00000000
219 11:04:50.390569 output: Entry Point: 0x00000000
220 11:04:50.390624 output: Hash algo: crc32
221 11:04:50.390679 output: Hash value: cf43f4f3
222 11:04:50.390735 output: Image 1 (fdt-1)
223 11:04:50.390789 output: Description: mt8192-asurada-spherion-r0
224 11:04:50.390844 output: Created: Sun Mar 3 11:04:50 2024
225 11:04:50.390896 output: Type: Flat Device Tree
226 11:04:50.390963 output: Compression: uncompressed
227 11:04:50.391015 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 11:04:50.391067 output: Architecture: AArch64
229 11:04:50.391168 output: Hash algo: crc32
230 11:04:50.391288 output: Hash value: cc4352de
231 11:04:50.391345 output: Image 2 (ramdisk-1)
232 11:04:50.391399 output: Description: unavailable
233 11:04:50.391451 output: Created: Sun Mar 3 11:04:50 2024
234 11:04:50.391504 output: Type: RAMDisk Image
235 11:04:50.391599 output: Compression: Unknown Compression
236 11:04:50.391697 output: Data Size: 61001726 Bytes = 59572.00 KiB = 58.18 MiB
237 11:04:50.391754 output: Architecture: AArch64
238 11:04:50.391807 output: OS: Linux
239 11:04:50.391859 output: Load Address: unavailable
240 11:04:50.391911 output: Entry Point: unavailable
241 11:04:50.391962 output: Hash algo: crc32
242 11:04:50.392014 output: Hash value: 39c152ab
243 11:04:50.392065 output: Default Configuration: 'conf-1'
244 11:04:50.392117 output: Configuration 0 (conf-1)
245 11:04:50.392168 output: Description: mt8192-asurada-spherion-r0
246 11:04:50.392220 output: Kernel: kernel-1
247 11:04:50.392272 output: Init Ramdisk: ramdisk-1
248 11:04:50.392323 output: FDT: fdt-1
249 11:04:50.392374 output: Loadables: kernel-1
250 11:04:50.392426 output:
251 11:04:50.392651 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 11:04:50.392817 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 11:04:50.392922 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 11:04:50.393014 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 11:04:50.393097 No LXC device requested
256 11:04:50.393179 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:04:50.393268 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 11:04:50.393346 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:04:50.393419 Checking files for TFTP limit of 4294967296 bytes.
260 11:04:50.393921 end: 1 tftp-deploy (duration 00:00:24) [common]
261 11:04:50.394022 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:04:50.394114 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:04:50.394244 substitutions:
264 11:04:50.394310 - {DTB}: 12925608/tftp-deploy-eut2f_1y/dtb/mt8192-asurada-spherion-r0.dtb
265 11:04:50.394375 - {INITRD}: 12925608/tftp-deploy-eut2f_1y/ramdisk/ramdisk.cpio.gz
266 11:04:50.394434 - {KERNEL}: 12925608/tftp-deploy-eut2f_1y/kernel/Image
267 11:04:50.394491 - {LAVA_MAC}: None
268 11:04:50.394557 - {PRESEED_CONFIG}: None
269 11:04:50.394633 - {PRESEED_LOCAL}: None
270 11:04:50.394720 - {RAMDISK}: 12925608/tftp-deploy-eut2f_1y/ramdisk/ramdisk.cpio.gz
271 11:04:50.394779 - {ROOT_PART}: None
272 11:04:50.394834 - {ROOT}: None
273 11:04:50.394889 - {SERVER_IP}: 192.168.201.1
274 11:04:50.394943 - {TEE}: None
275 11:04:50.394997 Parsed boot commands:
276 11:04:50.395050 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:04:50.395228 Parsed boot commands: tftpboot 192.168.201.1 12925608/tftp-deploy-eut2f_1y/kernel/image.itb 12925608/tftp-deploy-eut2f_1y/kernel/cmdline
278 11:04:50.395318 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:04:50.395407 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:04:50.395499 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:04:50.395583 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:04:50.395653 Not connected, no need to disconnect.
283 11:04:50.395728 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:04:50.395807 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:04:50.395873 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 11:04:50.399999 Setting prompt string to ['lava-test: # ']
287 11:04:50.400377 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:04:50.400486 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:04:50.400591 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:04:50.400685 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:04:50.401117 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 11:04:55.535859 >> Command sent successfully.
293 11:04:55.538668 Returned 0 in 5 seconds
294 11:04:55.639127 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:04:55.639463 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:04:55.639566 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:04:55.639652 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:04:55.639717 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:04:55.639785 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:04:55.640061 [Enter `^Ec?' for help]
302 11:04:55.822458
303 11:04:55.822621
304 11:04:55.822693 F0: 102B 0000
305 11:04:55.822758
306 11:04:55.822823 F3: 1001 0000 [0200]
307 11:04:55.822882
308 11:04:55.826374 F3: 1001 0000
309 11:04:55.826461
310 11:04:55.826527 F7: 102D 0000
311 11:04:55.826590
312 11:04:55.828953 F1: 0000 0000
313 11:04:55.829038
314 11:04:55.829107 V0: 0000 0000 [0001]
315 11:04:55.829170
316 11:04:55.833147 00: 0007 8000
317 11:04:55.833236
318 11:04:55.833303 01: 0000 0000
319 11:04:55.833366
320 11:04:55.833425 BP: 0C00 0209 [0000]
321 11:04:55.835977
322 11:04:55.836061 G0: 1182 0000
323 11:04:55.836127
324 11:04:55.836189 EC: 0000 0021 [4000]
325 11:04:55.836248
326 11:04:55.839806 S7: 0000 0000 [0000]
327 11:04:55.839892
328 11:04:55.842755 CC: 0000 0000 [0001]
329 11:04:55.842840
330 11:04:55.842907 T0: 0000 0040 [010F]
331 11:04:55.842974
332 11:04:55.843034 Jump to BL
333 11:04:55.843093
334 11:04:55.869859
335 11:04:55.870018
336 11:04:55.870085
337 11:04:55.875918 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:04:55.879633 ARM64: Exception handlers installed.
339 11:04:55.882801 ARM64: Testing exception
340 11:04:55.885722 ARM64: Done test exception
341 11:04:55.892641 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:04:55.902355 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:04:55.909817 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:04:55.919805 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:04:55.926186 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:04:55.936676 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:04:55.947828 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:04:55.954085 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:04:55.971706 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:04:55.975341 WDT: Last reset was cold boot
351 11:04:55.978761 SPI1(PAD0) initialized at 2873684 Hz
352 11:04:55.982033 SPI5(PAD0) initialized at 992727 Hz
353 11:04:55.985324 VBOOT: Loading verstage.
354 11:04:55.991872 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:04:55.995450 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:04:55.998494 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:04:56.001920 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:04:56.009785 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:04:56.016387 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:04:56.026833 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
361 11:04:56.026964
362 11:04:56.027033
363 11:04:56.037140 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:04:56.040429 ARM64: Exception handlers installed.
365 11:04:56.043696 ARM64: Testing exception
366 11:04:56.043788 ARM64: Done test exception
367 11:04:56.051313 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:04:56.053665 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:04:56.067856 Probing TPM: . done!
370 11:04:56.067996 TPM ready after 0 ms
371 11:04:56.074788 Connected to device vid:did:rid of 1ae0:0028:00
372 11:04:56.081778 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 11:04:56.085307 Initialized TPM device CR50 revision 0
374 11:04:56.134876 tlcl_send_startup: Startup return code is 0
375 11:04:56.135033 TPM: setup succeeded
376 11:04:56.147047 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:04:56.154685 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:04:56.165584 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:04:56.174378 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:04:56.177933 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:04:56.180964 in-header: 03 07 00 00 08 00 00 00
382 11:04:56.184393 in-data: aa e4 47 04 13 02 00 00
383 11:04:56.187202 Chrome EC: UHEPI supported
384 11:04:56.193921 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:04:56.197163 in-header: 03 9d 00 00 08 00 00 00
386 11:04:56.201757 in-data: 10 20 20 08 00 00 00 00
387 11:04:56.201941 Phase 1
388 11:04:56.204043 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:04:56.211583 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:04:56.217059 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:04:56.220557 Recovery requested (1009000e)
392 11:04:56.228286 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:04:56.232996 tlcl_extend: response is 0
394 11:04:56.241069 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:04:56.246368 tlcl_extend: response is 0
396 11:04:56.253042 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:04:56.273120 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
398 11:04:56.280125 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:04:56.280247
400 11:04:56.280312
401 11:04:56.290215 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:04:56.293478 ARM64: Exception handlers installed.
403 11:04:56.297390 ARM64: Testing exception
404 11:04:56.297480 ARM64: Done test exception
405 11:04:56.318904 pmic_efuse_setting: Set efuses in 11 msecs
406 11:04:56.322439 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:04:56.329133 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:04:56.332895 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:04:56.339542 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:04:56.343367 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:04:56.347159 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:04:56.353858 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:04:56.358219 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:04:56.361436 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:04:56.367550 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:04:56.371223 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:04:56.374441 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:04:56.381502 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:04:56.384249 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:04:56.391709 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:04:56.398085 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:04:56.402115 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:04:56.408752 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:04:56.415392 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:04:56.418550 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:04:56.424913 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:04:56.431692 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:04:56.435289 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:04:56.441762 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:04:56.448082 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:04:56.451894 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:04:56.458678 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:04:56.461767 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:04:56.468535 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:04:56.471802 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:04:56.478517 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:04:56.481906 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:04:56.488596 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:04:56.491394 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:04:56.499312 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:04:56.501348 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:04:56.507965 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:04:56.511781 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:04:56.518447 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:04:56.521316 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:04:56.528071 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:04:56.531878 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:04:56.535404 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:04:56.541447 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:04:56.545270 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:04:56.548164 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:04:56.554610 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:04:56.558704 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:04:56.561204 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:04:56.564697 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:04:56.571472 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:04:56.574826 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:04:56.581740 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:04:56.591884 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:04:56.594577 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:04:56.604730 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:04:56.611711 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:04:56.614524 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:04:56.622541 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:04:56.624533 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:04:56.631483 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x7
467 11:04:56.638651 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:04:56.641566 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 11:04:56.644714 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:04:56.656040 [RTC]rtc_get_frequency_meter,154: input=15, output=764
471 11:04:56.665858 [RTC]rtc_get_frequency_meter,154: input=23, output=949
472 11:04:56.676078 [RTC]rtc_get_frequency_meter,154: input=19, output=857
473 11:04:56.684581 [RTC]rtc_get_frequency_meter,154: input=17, output=811
474 11:04:56.693860 [RTC]rtc_get_frequency_meter,154: input=16, output=787
475 11:04:56.704224 [RTC]rtc_get_frequency_meter,154: input=16, output=787
476 11:04:56.713254 [RTC]rtc_get_frequency_meter,154: input=17, output=810
477 11:04:56.716571 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 11:04:56.723797 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 11:04:56.726784 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:04:56.730000 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 11:04:56.737120 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:04:56.740349 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 11:04:56.744152 ADC[4]: Raw value=670432 ID=5
484 11:04:56.744246 ADC[3]: Raw value=212917 ID=1
485 11:04:56.747149 RAM Code: 0x51
486 11:04:56.750199 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:04:56.757081 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:04:56.763672 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 11:04:56.770426 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 11:04:56.773754 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:04:56.776674 in-header: 03 07 00 00 08 00 00 00
492 11:04:56.780091 in-data: aa e4 47 04 13 02 00 00
493 11:04:56.784165 Chrome EC: UHEPI supported
494 11:04:56.790755 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:04:56.793792 in-header: 03 d5 00 00 08 00 00 00
496 11:04:56.796839 in-data: 98 20 60 08 00 00 00 00
497 11:04:56.800622 MRC: failed to locate region type 0.
498 11:04:56.806855 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:04:56.806968 DRAM-K: Running full calibration
500 11:04:56.813348 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 11:04:56.816529 header.status = 0x0
502 11:04:56.819918 header.version = 0x6 (expected: 0x6)
503 11:04:56.824118 header.size = 0xd00 (expected: 0xd00)
504 11:04:56.824212 header.flags = 0x0
505 11:04:56.830330 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:04:56.848679 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
507 11:04:56.854787 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:04:56.857967 dram_init: ddr_geometry: 0
509 11:04:56.861318 [EMI] MDL number = 0
510 11:04:56.861412 [EMI] Get MDL freq = 0
511 11:04:56.864748 dram_init: ddr_type: 0
512 11:04:56.864836 is_discrete_lpddr4: 1
513 11:04:56.869041 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:04:56.869128
515 11:04:56.869195
516 11:04:56.871864 [Bian_co] ETT version 0.0.0.1
517 11:04:56.878603 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 11:04:56.878696
519 11:04:56.881525 dramc_set_vcore_voltage set vcore to 650000
520 11:04:56.881611 Read voltage for 800, 4
521 11:04:56.885219 Vio18 = 0
522 11:04:56.885306 Vcore = 650000
523 11:04:56.885373 Vdram = 0
524 11:04:56.888091 Vddq = 0
525 11:04:56.888173 Vmddr = 0
526 11:04:56.893355 dram_init: config_dvfs: 1
527 11:04:56.895174 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:04:56.901295 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:04:56.905420 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 11:04:56.908689 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 11:04:56.911864 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 11:04:56.914936 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 11:04:56.918926 MEM_TYPE=3, freq_sel=18
534 11:04:56.922158 sv_algorithm_assistance_LP4_1600
535 11:04:56.925190 ============ PULL DRAM RESETB DOWN ============
536 11:04:56.928730 ========== PULL DRAM RESETB DOWN end =========
537 11:04:56.935079 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:04:56.938080 ===================================
539 11:04:56.938169 LPDDR4 DRAM CONFIGURATION
540 11:04:56.944017 ===================================
541 11:04:56.945423 EX_ROW_EN[0] = 0x0
542 11:04:56.948316 EX_ROW_EN[1] = 0x0
543 11:04:56.948402 LP4Y_EN = 0x0
544 11:04:56.951170 WORK_FSP = 0x0
545 11:04:56.951253 WL = 0x2
546 11:04:56.954711 RL = 0x2
547 11:04:56.954795 BL = 0x2
548 11:04:56.957959 RPST = 0x0
549 11:04:56.958043 RD_PRE = 0x0
550 11:04:56.961317 WR_PRE = 0x1
551 11:04:56.961400 WR_PST = 0x0
552 11:04:56.964530 DBI_WR = 0x0
553 11:04:56.964642 DBI_RD = 0x0
554 11:04:56.967938 OTF = 0x1
555 11:04:56.971313 ===================================
556 11:04:56.975317 ===================================
557 11:04:56.975406 ANA top config
558 11:04:56.978112 ===================================
559 11:04:56.981576 DLL_ASYNC_EN = 0
560 11:04:56.984788 ALL_SLAVE_EN = 1
561 11:04:56.988640 NEW_RANK_MODE = 1
562 11:04:56.988760 DLL_IDLE_MODE = 1
563 11:04:56.991507 LP45_APHY_COMB_EN = 1
564 11:04:56.995073 TX_ODT_DIS = 1
565 11:04:56.998323 NEW_8X_MODE = 1
566 11:04:57.001767 ===================================
567 11:04:57.004971 ===================================
568 11:04:57.005065 data_rate = 1600
569 11:04:57.008989 CKR = 1
570 11:04:57.012311 DQ_P2S_RATIO = 8
571 11:04:57.015515 ===================================
572 11:04:57.019351 CA_P2S_RATIO = 8
573 11:04:57.021837 DQ_CA_OPEN = 0
574 11:04:57.025913 DQ_SEMI_OPEN = 0
575 11:04:57.026002 CA_SEMI_OPEN = 0
576 11:04:57.028306 CA_FULL_RATE = 0
577 11:04:57.031936 DQ_CKDIV4_EN = 1
578 11:04:57.035331 CA_CKDIV4_EN = 1
579 11:04:57.038255 CA_PREDIV_EN = 0
580 11:04:57.041799 PH8_DLY = 0
581 11:04:57.041885 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:04:57.044921 DQ_AAMCK_DIV = 4
583 11:04:57.048673 CA_AAMCK_DIV = 4
584 11:04:57.051222 CA_ADMCK_DIV = 4
585 11:04:57.055229 DQ_TRACK_CA_EN = 0
586 11:04:57.058362 CA_PICK = 800
587 11:04:57.058447 CA_MCKIO = 800
588 11:04:57.061454 MCKIO_SEMI = 0
589 11:04:57.064929 PLL_FREQ = 3068
590 11:04:57.068054 DQ_UI_PI_RATIO = 32
591 11:04:57.071632 CA_UI_PI_RATIO = 0
592 11:04:57.074858 ===================================
593 11:04:57.078305 ===================================
594 11:04:57.081443 memory_type:LPDDR4
595 11:04:57.081534 GP_NUM : 10
596 11:04:57.086046 SRAM_EN : 1
597 11:04:57.086132 MD32_EN : 0
598 11:04:57.088100 ===================================
599 11:04:57.091805 [ANA_INIT] >>>>>>>>>>>>>>
600 11:04:57.094889 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:04:57.100170 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:04:57.103839 ===================================
603 11:04:57.105059 data_rate = 1600,PCW = 0X7600
604 11:04:57.108634 ===================================
605 11:04:57.111892 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:04:57.115413 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:04:57.121507 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:04:57.128156 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:04:57.131872 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:04:57.134758 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:04:57.134845 [ANA_INIT] flow start
612 11:04:57.138349 [ANA_INIT] PLL >>>>>>>>
613 11:04:57.141460 [ANA_INIT] PLL <<<<<<<<
614 11:04:57.141546 [ANA_INIT] MIDPI >>>>>>>>
615 11:04:57.145414 [ANA_INIT] MIDPI <<<<<<<<
616 11:04:57.148032 [ANA_INIT] DLL >>>>>>>>
617 11:04:57.148119 [ANA_INIT] flow end
618 11:04:57.154875 ============ LP4 DIFF to SE enter ============
619 11:04:57.157846 ============ LP4 DIFF to SE exit ============
620 11:04:57.157941 [ANA_INIT] <<<<<<<<<<<<<
621 11:04:57.161745 [Flow] Enable top DCM control >>>>>
622 11:04:57.164987 [Flow] Enable top DCM control <<<<<
623 11:04:57.168342 Enable DLL master slave shuffle
624 11:04:57.174462 ==============================================================
625 11:04:57.177778 Gating Mode config
626 11:04:57.181131 ==============================================================
627 11:04:57.185325 Config description:
628 11:04:57.194545 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:04:57.201692 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:04:57.205936 SELPH_MODE 0: By rank 1: By Phase
631 11:04:57.212039 ==============================================================
632 11:04:57.214551 GAT_TRACK_EN = 1
633 11:04:57.217714 RX_GATING_MODE = 2
634 11:04:57.217810 RX_GATING_TRACK_MODE = 2
635 11:04:57.221191 SELPH_MODE = 1
636 11:04:57.224697 PICG_EARLY_EN = 1
637 11:04:57.228217 VALID_LAT_VALUE = 1
638 11:04:57.234708 ==============================================================
639 11:04:57.237659 Enter into Gating configuration >>>>
640 11:04:57.241238 Exit from Gating configuration <<<<
641 11:04:57.244571 Enter into DVFS_PRE_config >>>>>
642 11:04:57.254446 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:04:57.258119 Exit from DVFS_PRE_config <<<<<
644 11:04:57.261100 Enter into PICG configuration >>>>
645 11:04:57.265069 Exit from PICG configuration <<<<
646 11:04:57.267804 [RX_INPUT] configuration >>>>>
647 11:04:57.271659 [RX_INPUT] configuration <<<<<
648 11:04:57.274614 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:04:57.280949 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:04:57.288371 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:04:57.291433 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:04:57.297979 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:04:57.304342 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:04:57.308283 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:04:57.314514 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:04:57.317711 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:04:57.320971 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:04:57.324494 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:04:57.330941 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:04:57.334711 ===================================
661 11:04:57.334808 LPDDR4 DRAM CONFIGURATION
662 11:04:57.337692 ===================================
663 11:04:57.341118 EX_ROW_EN[0] = 0x0
664 11:04:57.344642 EX_ROW_EN[1] = 0x0
665 11:04:57.344737 LP4Y_EN = 0x0
666 11:04:57.347656 WORK_FSP = 0x0
667 11:04:57.347742 WL = 0x2
668 11:04:57.351797 RL = 0x2
669 11:04:57.351882 BL = 0x2
670 11:04:57.354362 RPST = 0x0
671 11:04:57.354447 RD_PRE = 0x0
672 11:04:57.357724 WR_PRE = 0x1
673 11:04:57.357810 WR_PST = 0x0
674 11:04:57.361060 DBI_WR = 0x0
675 11:04:57.361146 DBI_RD = 0x0
676 11:04:57.364711 OTF = 0x1
677 11:04:57.367971 ===================================
678 11:04:57.371663 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:04:57.374993 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:04:57.378023 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:04:57.381685 ===================================
682 11:04:57.384949 LPDDR4 DRAM CONFIGURATION
683 11:04:57.387765 ===================================
684 11:04:57.391188 EX_ROW_EN[0] = 0x10
685 11:04:57.391277 EX_ROW_EN[1] = 0x0
686 11:04:57.394896 LP4Y_EN = 0x0
687 11:04:57.394981 WORK_FSP = 0x0
688 11:04:57.398225 WL = 0x2
689 11:04:57.398310 RL = 0x2
690 11:04:57.401208 BL = 0x2
691 11:04:57.401292 RPST = 0x0
692 11:04:57.404688 RD_PRE = 0x0
693 11:04:57.404820 WR_PRE = 0x1
694 11:04:57.407955 WR_PST = 0x0
695 11:04:57.408039 DBI_WR = 0x0
696 11:04:57.413750 DBI_RD = 0x0
697 11:04:57.414606 OTF = 0x1
698 11:04:57.418080 ===================================
699 11:04:57.421647 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:04:57.426250 nWR fixed to 40
701 11:04:57.429933 [ModeRegInit_LP4] CH0 RK0
702 11:04:57.430023 [ModeRegInit_LP4] CH0 RK1
703 11:04:57.432892 [ModeRegInit_LP4] CH1 RK0
704 11:04:57.436235 [ModeRegInit_LP4] CH1 RK1
705 11:04:57.436322 match AC timing 12
706 11:04:57.442946 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 11:04:57.445978 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:04:57.449609 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:04:57.456905 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:04:57.459673 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:04:57.462801 [EMI DOE] emi_dcm 0
712 11:04:57.465837 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:04:57.465930 ==
714 11:04:57.470146 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:04:57.473167 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 11:04:57.473256 ==
717 11:04:57.479818 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:04:57.485914 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:04:57.493667 [CA 0] Center 37 (7~68) winsize 62
720 11:04:57.497788 [CA 1] Center 37 (7~68) winsize 62
721 11:04:57.500409 [CA 2] Center 35 (5~66) winsize 62
722 11:04:57.503857 [CA 3] Center 35 (5~66) winsize 62
723 11:04:57.507294 [CA 4] Center 34 (4~65) winsize 62
724 11:04:57.510597 [CA 5] Center 33 (3~64) winsize 62
725 11:04:57.510694
726 11:04:57.513973 [CmdBusTrainingLP45] Vref(ca) range 1: 30
727 11:04:57.514062
728 11:04:57.517009 [CATrainingPosCal] consider 1 rank data
729 11:04:57.520644 u2DelayCellTimex100 = 270/100 ps
730 11:04:57.523427 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 11:04:57.527250 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
732 11:04:57.534192 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 11:04:57.537026 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
734 11:04:57.540837 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
735 11:04:57.543616 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 11:04:57.543710
737 11:04:57.547019 CA PerBit enable=1, Macro0, CA PI delay=33
738 11:04:57.547107
739 11:04:57.550217 [CBTSetCACLKResult] CA Dly = 33
740 11:04:57.550303 CS Dly: 5 (0~36)
741 11:04:57.554703 ==
742 11:04:57.554794 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:04:57.560463 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 11:04:57.560558 ==
745 11:04:57.563514 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:04:57.570651 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:04:57.580077 [CA 0] Center 37 (7~68) winsize 62
748 11:04:57.583302 [CA 1] Center 37 (6~68) winsize 63
749 11:04:57.586344 [CA 2] Center 35 (5~66) winsize 62
750 11:04:57.589513 [CA 3] Center 34 (4~65) winsize 62
751 11:04:57.592764 [CA 4] Center 33 (3~64) winsize 62
752 11:04:57.596563 [CA 5] Center 33 (3~64) winsize 62
753 11:04:57.596654
754 11:04:57.599755 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:04:57.599841
756 11:04:57.603516 [CATrainingPosCal] consider 2 rank data
757 11:04:57.606672 u2DelayCellTimex100 = 270/100 ps
758 11:04:57.609410 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 11:04:57.613473 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 11:04:57.620278 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 11:04:57.623352 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
762 11:04:57.626786 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
763 11:04:57.629687 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 11:04:57.629779
765 11:04:57.632757 CA PerBit enable=1, Macro0, CA PI delay=33
766 11:04:57.632844
767 11:04:57.636166 [CBTSetCACLKResult] CA Dly = 33
768 11:04:57.636253 CS Dly: 6 (0~38)
769 11:04:57.636319
770 11:04:57.640584 ----->DramcWriteLeveling(PI) begin...
771 11:04:57.643108 ==
772 11:04:57.646401 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:04:57.649865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 11:04:57.649957 ==
775 11:04:57.653238 Write leveling (Byte 0): 28 => 28
776 11:04:57.656446 Write leveling (Byte 1): 28 => 28
777 11:04:57.659637 DramcWriteLeveling(PI) end<-----
778 11:04:57.659729
779 11:04:57.659795 ==
780 11:04:57.663763 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:04:57.666187 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 11:04:57.666280 ==
783 11:04:57.670715 [Gating] SW mode calibration
784 11:04:57.676203 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:04:57.682691 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:04:57.686628 0 6 0 | B1->B0 | 2f2f 3030 | 1 1 | (1 0) (1 1)
787 11:04:57.689622 0 6 4 | B1->B0 | 2929 2424 | 0 0 | (1 1) (0 0)
788 11:04:57.693101 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:04:57.700753 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:04:57.703128 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:04:57.706158 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:04:57.712643 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:04:57.716215 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:04:57.719545 0 7 0 | B1->B0 | 2525 2e2d | 0 1 | (0 0) (1 1)
795 11:04:57.726214 0 7 4 | B1->B0 | 3838 4141 | 0 0 | (0 0) (0 0)
796 11:04:57.729809 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 11:04:57.732826 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 11:04:57.739231 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 11:04:57.743391 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 11:04:57.746273 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 11:04:57.752957 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 11:04:57.756408 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
803 11:04:57.759827 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
804 11:04:57.766057 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 11:04:57.769551 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 11:04:57.772891 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 11:04:57.779554 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 11:04:57.783182 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 11:04:57.785965 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 11:04:57.789157 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 11:04:57.795868 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 11:04:57.799200 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 11:04:57.804011 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 11:04:57.809648 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 11:04:57.813705 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 11:04:57.816393 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 11:04:57.822543 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 11:04:57.826840 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
819 11:04:57.829646 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
820 11:04:57.833318 Total UI for P1: 0, mck2ui 16
821 11:04:57.836629 best dqsien dly found for B0: ( 0, 10, 0)
822 11:04:57.839658 Total UI for P1: 0, mck2ui 16
823 11:04:57.842634 best dqsien dly found for B1: ( 0, 10, 0)
824 11:04:57.845747 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
825 11:04:57.849619 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
826 11:04:57.849712
827 11:04:57.855667 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
828 11:04:57.859374 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
829 11:04:57.862914 [Gating] SW calibration Done
830 11:04:57.863003 ==
831 11:04:57.866039 Dram Type= 6, Freq= 0, CH_0, rank 0
832 11:04:57.869737 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 11:04:57.869826 ==
834 11:04:57.869894 RX Vref Scan: 0
835 11:04:57.869955
836 11:04:57.872834 RX Vref 0 -> 0, step: 1
837 11:04:57.872918
838 11:04:57.876455 RX Delay -130 -> 252, step: 16
839 11:04:57.880653 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
840 11:04:57.882997 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 11:04:57.886919 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
842 11:04:57.893691 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 11:04:57.896227 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
844 11:04:57.899817 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
845 11:04:57.903416 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
846 11:04:57.907648 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
847 11:04:57.912889 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
848 11:04:57.916412 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
849 11:04:57.919832 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 11:04:57.923278 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 11:04:57.926503 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 11:04:57.932626 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
853 11:04:57.936219 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 11:04:57.940140 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 11:04:57.940230 ==
856 11:04:57.942845 Dram Type= 6, Freq= 0, CH_0, rank 0
857 11:04:57.946234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 11:04:57.946346 ==
859 11:04:57.949955 DQS Delay:
860 11:04:57.950039 DQS0 = 0, DQS1 = 0
861 11:04:57.953068 DQM Delay:
862 11:04:57.953152 DQM0 = 82, DQM1 = 73
863 11:04:57.953218 DQ Delay:
864 11:04:57.956065 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
865 11:04:57.959349 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
866 11:04:57.962968 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
867 11:04:57.966643 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
868 11:04:57.966734
869 11:04:57.966799
870 11:04:57.969415 ==
871 11:04:57.973000 Dram Type= 6, Freq= 0, CH_0, rank 0
872 11:04:57.978079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 11:04:57.978174 ==
874 11:04:57.978240
875 11:04:57.978299
876 11:04:57.979463 TX Vref Scan disable
877 11:04:57.979544 == TX Byte 0 ==
878 11:04:57.983134 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
879 11:04:57.989190 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
880 11:04:57.989288 == TX Byte 1 ==
881 11:04:57.992768 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
882 11:04:57.999918 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
883 11:04:58.000024 ==
884 11:04:58.002867 Dram Type= 6, Freq= 0, CH_0, rank 0
885 11:04:58.005905 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 11:04:58.005997 ==
887 11:04:58.018955 TX Vref=22, minBit 0, minWin=27, winSum=444
888 11:04:58.022228 TX Vref=24, minBit 2, minWin=27, winSum=447
889 11:04:58.025479 TX Vref=26, minBit 4, minWin=27, winSum=449
890 11:04:58.028901 TX Vref=28, minBit 4, minWin=27, winSum=454
891 11:04:58.033755 TX Vref=30, minBit 0, minWin=28, winSum=456
892 11:04:58.035626 TX Vref=32, minBit 0, minWin=28, winSum=454
893 11:04:58.042315 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
894 11:04:58.042420
895 11:04:58.045751 Final TX Range 1 Vref 30
896 11:04:58.045839
897 11:04:58.045904 ==
898 11:04:58.049164 Dram Type= 6, Freq= 0, CH_0, rank 0
899 11:04:58.052507 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 11:04:58.052608 ==
901 11:04:58.052674
902 11:04:58.055650
903 11:04:58.055733 TX Vref Scan disable
904 11:04:58.058927 == TX Byte 0 ==
905 11:04:58.061899 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
906 11:04:58.068986 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
907 11:04:58.069097 == TX Byte 1 ==
908 11:04:58.072582 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
909 11:04:58.078841 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
910 11:04:58.078943
911 11:04:58.079010 [DATLAT]
912 11:04:58.079071 Freq=800, CH0 RK0
913 11:04:58.079130
914 11:04:58.083519 DATLAT Default: 0xa
915 11:04:58.083604 0, 0xFFFF, sum = 0
916 11:04:58.086232 1, 0xFFFF, sum = 0
917 11:04:58.086317 2, 0xFFFF, sum = 0
918 11:04:58.089069 3, 0xFFFF, sum = 0
919 11:04:58.092290 4, 0xFFFF, sum = 0
920 11:04:58.092396 5, 0xFFFF, sum = 0
921 11:04:58.095254 6, 0xFFFF, sum = 0
922 11:04:58.095340 7, 0xFFFF, sum = 0
923 11:04:58.098711 8, 0x0, sum = 1
924 11:04:58.098797 9, 0x0, sum = 2
925 11:04:58.098864 10, 0x0, sum = 3
926 11:04:58.102000 11, 0x0, sum = 4
927 11:04:58.102086 best_step = 9
928 11:04:58.102152
929 11:04:58.102212 ==
930 11:04:58.105912 Dram Type= 6, Freq= 0, CH_0, rank 0
931 11:04:58.111866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 11:04:58.111976 ==
933 11:04:58.112043 RX Vref Scan: 1
934 11:04:58.112104
935 11:04:58.115226 Set Vref Range= 32 -> 127
936 11:04:58.115311
937 11:04:58.119391 RX Vref 32 -> 127, step: 1
938 11:04:58.119479
939 11:04:58.122720 RX Delay -111 -> 252, step: 8
940 11:04:58.122804
941 11:04:58.125562 Set Vref, RX VrefLevel [Byte0]: 32
942 11:04:58.128602 [Byte1]: 32
943 11:04:58.128714
944 11:04:58.132070 Set Vref, RX VrefLevel [Byte0]: 33
945 11:04:58.135725 [Byte1]: 33
946 11:04:58.135810
947 11:04:58.139068 Set Vref, RX VrefLevel [Byte0]: 34
948 11:04:58.142599 [Byte1]: 34
949 11:04:58.142684
950 11:04:58.145493 Set Vref, RX VrefLevel [Byte0]: 35
951 11:04:58.148440 [Byte1]: 35
952 11:04:58.153037
953 11:04:58.153126 Set Vref, RX VrefLevel [Byte0]: 36
954 11:04:58.156041 [Byte1]: 36
955 11:04:58.160608
956 11:04:58.160716 Set Vref, RX VrefLevel [Byte0]: 37
957 11:04:58.164044 [Byte1]: 37
958 11:04:58.168081
959 11:04:58.168169 Set Vref, RX VrefLevel [Byte0]: 38
960 11:04:58.171418 [Byte1]: 38
961 11:04:58.175875
962 11:04:58.175966 Set Vref, RX VrefLevel [Byte0]: 39
963 11:04:58.179232 [Byte1]: 39
964 11:04:58.184924
965 11:04:58.185019 Set Vref, RX VrefLevel [Byte0]: 40
966 11:04:58.186596 [Byte1]: 40
967 11:04:58.191036
968 11:04:58.191123 Set Vref, RX VrefLevel [Byte0]: 41
969 11:04:58.194643 [Byte1]: 41
970 11:04:58.198870
971 11:04:58.198962 Set Vref, RX VrefLevel [Byte0]: 42
972 11:04:58.201932 [Byte1]: 42
973 11:04:58.206728
974 11:04:58.206824 Set Vref, RX VrefLevel [Byte0]: 43
975 11:04:58.209710 [Byte1]: 43
976 11:04:58.213862
977 11:04:58.213954 Set Vref, RX VrefLevel [Byte0]: 44
978 11:04:58.217096 [Byte1]: 44
979 11:04:58.221238
980 11:04:58.221326 Set Vref, RX VrefLevel [Byte0]: 45
981 11:04:58.224854 [Byte1]: 45
982 11:04:58.229041
983 11:04:58.229163 Set Vref, RX VrefLevel [Byte0]: 46
984 11:04:58.232447 [Byte1]: 46
985 11:04:58.236660
986 11:04:58.236783 Set Vref, RX VrefLevel [Byte0]: 47
987 11:04:58.240354 [Byte1]: 47
988 11:04:58.245759
989 11:04:58.245851 Set Vref, RX VrefLevel [Byte0]: 48
990 11:04:58.248021 [Byte1]: 48
991 11:04:58.252231
992 11:04:58.252316 Set Vref, RX VrefLevel [Byte0]: 49
993 11:04:58.255521 [Byte1]: 49
994 11:04:58.260458
995 11:04:58.260547 Set Vref, RX VrefLevel [Byte0]: 50
996 11:04:58.263021 [Byte1]: 50
997 11:04:58.268305
998 11:04:58.268399 Set Vref, RX VrefLevel [Byte0]: 51
999 11:04:58.270898 [Byte1]: 51
1000 11:04:58.275652
1001 11:04:58.275740 Set Vref, RX VrefLevel [Byte0]: 52
1002 11:04:58.278172 [Byte1]: 52
1003 11:04:58.282596
1004 11:04:58.282685 Set Vref, RX VrefLevel [Byte0]: 53
1005 11:04:58.286515 [Byte1]: 53
1006 11:04:58.291623
1007 11:04:58.291717 Set Vref, RX VrefLevel [Byte0]: 54
1008 11:04:58.293862 [Byte1]: 54
1009 11:04:58.298476
1010 11:04:58.298564 Set Vref, RX VrefLevel [Byte0]: 55
1011 11:04:58.301758 [Byte1]: 55
1012 11:04:58.305765
1013 11:04:58.305861 Set Vref, RX VrefLevel [Byte0]: 56
1014 11:04:58.308906 [Byte1]: 56
1015 11:04:58.313815
1016 11:04:58.313909 Set Vref, RX VrefLevel [Byte0]: 57
1017 11:04:58.316534 [Byte1]: 57
1018 11:04:58.321382
1019 11:04:58.321474 Set Vref, RX VrefLevel [Byte0]: 58
1020 11:04:58.324056 [Byte1]: 58
1021 11:04:58.328608
1022 11:04:58.328697 Set Vref, RX VrefLevel [Byte0]: 59
1023 11:04:58.332179 [Byte1]: 59
1024 11:04:58.336572
1025 11:04:58.336666 Set Vref, RX VrefLevel [Byte0]: 60
1026 11:04:58.339437 [Byte1]: 60
1027 11:04:58.346165
1028 11:04:58.346261 Set Vref, RX VrefLevel [Byte0]: 61
1029 11:04:58.347891 [Byte1]: 61
1030 11:04:58.351554
1031 11:04:58.351640 Set Vref, RX VrefLevel [Byte0]: 62
1032 11:04:58.355176 [Byte1]: 62
1033 11:04:58.358945
1034 11:04:58.359031 Set Vref, RX VrefLevel [Byte0]: 63
1035 11:04:58.362224 [Byte1]: 63
1036 11:04:58.366747
1037 11:04:58.366837 Set Vref, RX VrefLevel [Byte0]: 64
1038 11:04:58.373252 [Byte1]: 64
1039 11:04:58.373347
1040 11:04:58.376885 Set Vref, RX VrefLevel [Byte0]: 65
1041 11:04:58.380356 [Byte1]: 65
1042 11:04:58.380440
1043 11:04:58.383282 Set Vref, RX VrefLevel [Byte0]: 66
1044 11:04:58.387250 [Byte1]: 66
1045 11:04:58.387334
1046 11:04:58.389851 Set Vref, RX VrefLevel [Byte0]: 67
1047 11:04:58.393714 [Byte1]: 67
1048 11:04:58.397726
1049 11:04:58.397817 Set Vref, RX VrefLevel [Byte0]: 68
1050 11:04:58.400489 [Byte1]: 68
1051 11:04:58.405160
1052 11:04:58.405250 Set Vref, RX VrefLevel [Byte0]: 69
1053 11:04:58.408541 [Byte1]: 69
1054 11:04:58.412870
1055 11:04:58.412965 Set Vref, RX VrefLevel [Byte0]: 70
1056 11:04:58.415758 [Byte1]: 70
1057 11:04:58.420794
1058 11:04:58.420882 Set Vref, RX VrefLevel [Byte0]: 71
1059 11:04:58.424248 [Byte1]: 71
1060 11:04:58.428008
1061 11:04:58.428093 Set Vref, RX VrefLevel [Byte0]: 72
1062 11:04:58.431836 [Byte1]: 72
1063 11:04:58.436032
1064 11:04:58.436120 Set Vref, RX VrefLevel [Byte0]: 73
1065 11:04:58.439011 [Byte1]: 73
1066 11:04:58.443101
1067 11:04:58.443185 Final RX Vref Byte 0 = 53 to rank0
1068 11:04:58.446812 Final RX Vref Byte 1 = 55 to rank0
1069 11:04:58.450549 Final RX Vref Byte 0 = 53 to rank1
1070 11:04:58.454023 Final RX Vref Byte 1 = 55 to rank1==
1071 11:04:58.456555 Dram Type= 6, Freq= 0, CH_0, rank 0
1072 11:04:58.463436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1073 11:04:58.463534 ==
1074 11:04:58.463601 DQS Delay:
1075 11:04:58.463661 DQS0 = 0, DQS1 = 0
1076 11:04:58.466279 DQM Delay:
1077 11:04:58.466359 DQM0 = 83, DQM1 = 73
1078 11:04:58.470106 DQ Delay:
1079 11:04:58.473352 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1080 11:04:58.473437 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1081 11:04:58.477342 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1082 11:04:58.479826 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1083 11:04:58.483510
1084 11:04:58.483594
1085 11:04:58.489839 [DQSOSCAuto] RK0, (LSB)MR18= 0x3232, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
1086 11:04:58.493381 CH0 RK0: MR19=606, MR18=3232
1087 11:04:58.500685 CH0_RK0: MR19=0x606, MR18=0x3232, DQSOSC=397, MR23=63, INC=93, DEC=62
1088 11:04:58.500837
1089 11:04:58.503375 ----->DramcWriteLeveling(PI) begin...
1090 11:04:58.503460 ==
1091 11:04:58.507493 Dram Type= 6, Freq= 0, CH_0, rank 1
1092 11:04:58.509930 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1093 11:04:58.510018 ==
1094 11:04:58.513848 Write leveling (Byte 0): 32 => 32
1095 11:04:58.516690 Write leveling (Byte 1): 28 => 28
1096 11:04:58.520472 DramcWriteLeveling(PI) end<-----
1097 11:04:58.520558
1098 11:04:58.520625 ==
1099 11:04:58.523443 Dram Type= 6, Freq= 0, CH_0, rank 1
1100 11:04:58.526706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1101 11:04:58.526790 ==
1102 11:04:58.530165 [Gating] SW mode calibration
1103 11:04:58.537415 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1104 11:04:58.543557 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1105 11:04:58.546619 0 6 0 | B1->B0 | 3333 3030 | 0 0 | (0 1) (0 0)
1106 11:04:58.549905 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1107 11:04:58.557618 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1108 11:04:58.559754 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1109 11:04:58.563188 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1110 11:04:58.569885 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1111 11:04:58.573978 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 11:04:58.576365 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 11:04:58.583561 0 7 0 | B1->B0 | 2727 2e2e | 0 1 | (0 0) (0 0)
1114 11:04:58.586679 0 7 4 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
1115 11:04:58.590066 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1116 11:04:58.596467 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1117 11:04:58.600919 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1118 11:04:58.603138 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 11:04:58.606447 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 11:04:58.613134 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 11:04:58.616365 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 11:04:58.620225 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1123 11:04:58.627011 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1124 11:04:58.630071 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1125 11:04:58.635038 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1126 11:04:58.640301 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 11:04:58.643260 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 11:04:58.646779 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 11:04:58.653035 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 11:04:58.656457 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 11:04:58.660010 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 11:04:58.666589 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 11:04:58.669584 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 11:04:58.672992 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 11:04:58.680239 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 11:04:58.683150 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 11:04:58.687482 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1138 11:04:58.693263 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1139 11:04:58.693361 Total UI for P1: 0, mck2ui 16
1140 11:04:58.696545 best dqsien dly found for B0: ( 0, 10, 0)
1141 11:04:58.700017 Total UI for P1: 0, mck2ui 16
1142 11:04:58.703855 best dqsien dly found for B1: ( 0, 10, 0)
1143 11:04:58.707103 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1144 11:04:58.709977 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1145 11:04:58.713020
1146 11:04:58.716374 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1147 11:04:58.720186 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1148 11:04:58.723210 [Gating] SW calibration Done
1149 11:04:58.723298 ==
1150 11:04:58.727591 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 11:04:58.730144 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1152 11:04:58.730233 ==
1153 11:04:58.730374 RX Vref Scan: 0
1154 11:04:58.730439
1155 11:04:58.733817 RX Vref 0 -> 0, step: 1
1156 11:04:58.733899
1157 11:04:58.737005 RX Delay -130 -> 252, step: 16
1158 11:04:58.739753 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1159 11:04:58.743556 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1160 11:04:58.790766 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1161 11:04:58.790926 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1162 11:04:58.791196 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1163 11:04:58.791506 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1164 11:04:58.791588 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1165 11:04:58.791841 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1166 11:04:58.792503 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1167 11:04:58.793310 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1168 11:04:58.793393 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1169 11:04:58.793806 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1170 11:04:58.794386 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1171 11:04:58.822681 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1172 11:04:58.822838 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1173 11:04:58.823541 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1174 11:04:58.823623 ==
1175 11:04:58.825142 Dram Type= 6, Freq= 0, CH_0, rank 1
1176 11:04:58.825225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1177 11:04:58.825292 ==
1178 11:04:58.826211 DQS Delay:
1179 11:04:58.826293 DQS0 = 0, DQS1 = 0
1180 11:04:58.826359 DQM Delay:
1181 11:04:58.826667 DQM0 = 82, DQM1 = 74
1182 11:04:58.826750 DQ Delay:
1183 11:04:58.826815 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1184 11:04:58.827065 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1185 11:04:58.827130 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1186 11:04:58.830006 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1187 11:04:58.830090
1188 11:04:58.830155
1189 11:04:58.830215 ==
1190 11:04:58.833017 Dram Type= 6, Freq= 0, CH_0, rank 1
1191 11:04:58.836137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1192 11:04:58.836223 ==
1193 11:04:58.836327
1194 11:04:58.836388
1195 11:04:58.839790 TX Vref Scan disable
1196 11:04:58.839874 == TX Byte 0 ==
1197 11:04:58.846237 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1198 11:04:58.849429 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1199 11:04:58.849518 == TX Byte 1 ==
1200 11:04:58.856712 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1201 11:04:58.860145 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1202 11:04:58.860238 ==
1203 11:04:58.863971 Dram Type= 6, Freq= 0, CH_0, rank 1
1204 11:04:58.866022 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1205 11:04:58.866106 ==
1206 11:04:58.880855 TX Vref=22, minBit 13, minWin=27, winSum=448
1207 11:04:58.884558 TX Vref=24, minBit 14, minWin=27, winSum=448
1208 11:04:58.887270 TX Vref=26, minBit 0, minWin=28, winSum=455
1209 11:04:58.890621 TX Vref=28, minBit 0, minWin=28, winSum=456
1210 11:04:58.893952 TX Vref=30, minBit 0, minWin=28, winSum=458
1211 11:04:58.900339 TX Vref=32, minBit 0, minWin=28, winSum=455
1212 11:04:58.903905 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30
1213 11:04:58.904000
1214 11:04:58.908206 Final TX Range 1 Vref 30
1215 11:04:58.908303
1216 11:04:58.908371 ==
1217 11:04:58.910849 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 11:04:58.913505 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1219 11:04:58.918642 ==
1220 11:04:58.918736
1221 11:04:58.918802
1222 11:04:58.918863 TX Vref Scan disable
1223 11:04:58.920346 == TX Byte 0 ==
1224 11:04:58.924071 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1225 11:04:58.930727 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1226 11:04:58.930831 == TX Byte 1 ==
1227 11:04:58.934259 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1228 11:04:58.940398 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1229 11:04:58.940493
1230 11:04:58.940560 [DATLAT]
1231 11:04:58.940620 Freq=800, CH0 RK1
1232 11:04:58.940680
1233 11:04:58.943614 DATLAT Default: 0x9
1234 11:04:58.943695 0, 0xFFFF, sum = 0
1235 11:04:58.947737 1, 0xFFFF, sum = 0
1236 11:04:58.950805 2, 0xFFFF, sum = 0
1237 11:04:58.950891 3, 0xFFFF, sum = 0
1238 11:04:58.954009 4, 0xFFFF, sum = 0
1239 11:04:58.954093 5, 0xFFFF, sum = 0
1240 11:04:58.956832 6, 0xFFFF, sum = 0
1241 11:04:58.956920 7, 0xFFFF, sum = 0
1242 11:04:58.960579 8, 0x0, sum = 1
1243 11:04:58.960665 9, 0x0, sum = 2
1244 11:04:58.960738 10, 0x0, sum = 3
1245 11:04:58.963824 11, 0x0, sum = 4
1246 11:04:58.963908 best_step = 9
1247 11:04:58.963972
1248 11:04:58.964031 ==
1249 11:04:58.967171 Dram Type= 6, Freq= 0, CH_0, rank 1
1250 11:04:58.973713 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1251 11:04:58.973814 ==
1252 11:04:58.973881 RX Vref Scan: 0
1253 11:04:58.973941
1254 11:04:58.977564 RX Vref 0 -> 0, step: 1
1255 11:04:58.977647
1256 11:04:58.980654 RX Delay -111 -> 252, step: 8
1257 11:04:58.984640 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1258 11:04:58.987419 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1259 11:04:58.995958 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1260 11:04:58.996988 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1261 11:04:59.001047 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1262 11:04:59.003804 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1263 11:04:59.007584 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1264 11:04:59.013915 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1265 11:04:59.016983 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1266 11:04:59.020496 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1267 11:04:59.024493 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1268 11:04:59.027560 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1269 11:04:59.033846 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1270 11:04:59.037820 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1271 11:04:59.040597 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1272 11:04:59.045026 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1273 11:04:59.045125 ==
1274 11:04:59.047319 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 11:04:59.054133 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1276 11:04:59.054246 ==
1277 11:04:59.054315 DQS Delay:
1278 11:04:59.054377 DQS0 = 0, DQS1 = 0
1279 11:04:59.057438 DQM Delay:
1280 11:04:59.057523 DQM0 = 86, DQM1 = 75
1281 11:04:59.061605 DQ Delay:
1282 11:04:59.064574 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1283 11:04:59.064665 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1284 11:04:59.067554 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1285 11:04:59.074273 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1286 11:04:59.074389
1287 11:04:59.074455
1288 11:04:59.080347 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1289 11:04:59.083771 CH0 RK1: MR19=606, MR18=4A4A
1290 11:04:59.090641 CH0_RK1: MR19=0x606, MR18=0x4A4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1291 11:04:59.093683 [RxdqsGatingPostProcess] freq 800
1292 11:04:59.096965 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1293 11:04:59.100229 Pre-setting of DQS Precalculation
1294 11:04:59.107268 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1295 11:04:59.107416 ==
1296 11:04:59.110607 Dram Type= 6, Freq= 0, CH_1, rank 0
1297 11:04:59.114489 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1298 11:04:59.114590 ==
1299 11:04:59.120162 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1300 11:04:59.123492 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1301 11:04:59.133263 [CA 0] Center 36 (6~67) winsize 62
1302 11:04:59.137284 [CA 1] Center 36 (5~67) winsize 63
1303 11:04:59.139921 [CA 2] Center 34 (4~65) winsize 62
1304 11:04:59.143202 [CA 3] Center 34 (4~65) winsize 62
1305 11:04:59.148026 [CA 4] Center 33 (3~64) winsize 62
1306 11:04:59.150629 [CA 5] Center 33 (3~63) winsize 61
1307 11:04:59.150724
1308 11:04:59.153502 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1309 11:04:59.153588
1310 11:04:59.157341 [CATrainingPosCal] consider 1 rank data
1311 11:04:59.159877 u2DelayCellTimex100 = 270/100 ps
1312 11:04:59.163494 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1313 11:04:59.170271 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1314 11:04:59.173521 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1315 11:04:59.176544 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1316 11:04:59.179798 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1317 11:04:59.184227 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1318 11:04:59.184322
1319 11:04:59.186561 CA PerBit enable=1, Macro0, CA PI delay=33
1320 11:04:59.186644
1321 11:04:59.190625 [CBTSetCACLKResult] CA Dly = 33
1322 11:04:59.190711 CS Dly: 4 (0~35)
1323 11:04:59.193398 ==
1324 11:04:59.196247 Dram Type= 6, Freq= 0, CH_1, rank 1
1325 11:04:59.200034 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1326 11:04:59.200132 ==
1327 11:04:59.203097 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1328 11:04:59.209849 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1329 11:04:59.220256 [CA 0] Center 36 (6~67) winsize 62
1330 11:04:59.222334 [CA 1] Center 36 (5~67) winsize 63
1331 11:04:59.225667 [CA 2] Center 34 (4~65) winsize 62
1332 11:04:59.230092 [CA 3] Center 33 (3~64) winsize 62
1333 11:04:59.232490 [CA 4] Center 33 (3~64) winsize 62
1334 11:04:59.235737 [CA 5] Center 33 (3~64) winsize 62
1335 11:04:59.235824
1336 11:04:59.240118 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1337 11:04:59.240278
1338 11:04:59.242343 [CATrainingPosCal] consider 2 rank data
1339 11:04:59.245649 u2DelayCellTimex100 = 270/100 ps
1340 11:04:59.249368 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1341 11:04:59.252676 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1342 11:04:59.260071 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1343 11:04:59.262593 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1344 11:04:59.265932 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1345 11:04:59.268877 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1346 11:04:59.268964
1347 11:04:59.272392 CA PerBit enable=1, Macro0, CA PI delay=33
1348 11:04:59.272479
1349 11:04:59.276073 [CBTSetCACLKResult] CA Dly = 33
1350 11:04:59.276179 CS Dly: 5 (0~37)
1351 11:04:59.276248
1352 11:04:59.278987 ----->DramcWriteLeveling(PI) begin...
1353 11:04:59.282145 ==
1354 11:04:59.286441 Dram Type= 6, Freq= 0, CH_1, rank 0
1355 11:04:59.289539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1356 11:04:59.289630 ==
1357 11:04:59.292695 Write leveling (Byte 0): 25 => 25
1358 11:04:59.296416 Write leveling (Byte 1): 25 => 25
1359 11:04:59.298919 DramcWriteLeveling(PI) end<-----
1360 11:04:59.299004
1361 11:04:59.299068 ==
1362 11:04:59.302246 Dram Type= 6, Freq= 0, CH_1, rank 0
1363 11:04:59.306966 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1364 11:04:59.307058 ==
1365 11:04:59.308666 [Gating] SW mode calibration
1366 11:04:59.315689 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1367 11:04:59.319244 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1368 11:04:59.325847 0 6 0 | B1->B0 | 2f2f 2424 | 0 0 | (1 1) (0 0)
1369 11:04:59.329213 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1370 11:04:59.332610 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1371 11:04:59.338695 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1372 11:04:59.342315 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1373 11:04:59.345686 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1374 11:04:59.352233 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 11:04:59.355700 0 6 28 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
1376 11:04:59.359098 0 7 0 | B1->B0 | 2e2e 4040 | 1 0 | (0 0) (0 0)
1377 11:04:59.366135 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1378 11:04:59.368697 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1379 11:04:59.372284 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1380 11:04:59.378767 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1381 11:04:59.382445 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1382 11:04:59.385585 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 11:04:59.392900 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 11:04:59.395437 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1385 11:04:59.399635 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1386 11:04:59.406002 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1387 11:04:59.408640 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1388 11:04:59.412612 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 11:04:59.418917 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 11:04:59.422579 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 11:04:59.425528 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 11:04:59.428935 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 11:04:59.435431 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 11:04:59.439107 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 11:04:59.444297 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 11:04:59.449332 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 11:04:59.452570 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 11:04:59.455959 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 11:04:59.462735 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1400 11:04:59.466135 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1401 11:04:59.468798 Total UI for P1: 0, mck2ui 16
1402 11:04:59.473249 best dqsien dly found for B0: ( 0, 9, 28)
1403 11:04:59.476280 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1404 11:04:59.479153 Total UI for P1: 0, mck2ui 16
1405 11:04:59.482233 best dqsien dly found for B1: ( 0, 10, 0)
1406 11:04:59.485779 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1407 11:04:59.489147 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1408 11:04:59.489232
1409 11:04:59.495201 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1410 11:04:59.498963 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1411 11:04:59.499053 [Gating] SW calibration Done
1412 11:04:59.501895 ==
1413 11:04:59.505774 Dram Type= 6, Freq= 0, CH_1, rank 0
1414 11:04:59.509090 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1415 11:04:59.509187 ==
1416 11:04:59.509253 RX Vref Scan: 0
1417 11:04:59.509314
1418 11:04:59.512355 RX Vref 0 -> 0, step: 1
1419 11:04:59.512465
1420 11:04:59.515726 RX Delay -130 -> 252, step: 16
1421 11:04:59.519096 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1422 11:04:59.523053 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1423 11:04:59.525884 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1424 11:04:59.532124 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1425 11:04:59.535966 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1426 11:04:59.539188 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1427 11:04:59.543256 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1428 11:04:59.545520 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1429 11:04:59.552045 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1430 11:04:59.555261 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1431 11:04:59.559263 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1432 11:04:59.561776 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1433 11:04:59.565451 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1434 11:04:59.572249 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1435 11:04:59.575642 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1436 11:04:59.579288 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1437 11:04:59.579375 ==
1438 11:04:59.581984 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 11:04:59.585283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1440 11:04:59.588444 ==
1441 11:04:59.588526 DQS Delay:
1442 11:04:59.588589 DQS0 = 0, DQS1 = 0
1443 11:04:59.592242 DQM Delay:
1444 11:04:59.592323 DQM0 = 81, DQM1 = 71
1445 11:04:59.595430 DQ Delay:
1446 11:04:59.595513 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1447 11:04:59.598642 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1448 11:04:59.602272 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1449 11:04:59.605251 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1450 11:04:59.605335
1451 11:04:59.608905
1452 11:04:59.608993 ==
1453 11:04:59.611772 Dram Type= 6, Freq= 0, CH_1, rank 0
1454 11:04:59.615770 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1455 11:04:59.615857 ==
1456 11:04:59.615922
1457 11:04:59.615979
1458 11:04:59.618646 TX Vref Scan disable
1459 11:04:59.618741 == TX Byte 0 ==
1460 11:04:59.625111 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1461 11:04:59.628447 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1462 11:04:59.628537 == TX Byte 1 ==
1463 11:04:59.635162 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1464 11:04:59.638325 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1465 11:04:59.638413 ==
1466 11:04:59.641627 Dram Type= 6, Freq= 0, CH_1, rank 0
1467 11:04:59.646541 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1468 11:04:59.646627 ==
1469 11:04:59.658245 TX Vref=22, minBit 3, minWin=26, winSum=446
1470 11:04:59.661334 TX Vref=24, minBit 1, minWin=27, winSum=451
1471 11:04:59.665585 TX Vref=26, minBit 3, minWin=27, winSum=452
1472 11:04:59.668552 TX Vref=28, minBit 0, minWin=28, winSum=456
1473 11:04:59.671500 TX Vref=30, minBit 3, minWin=28, winSum=456
1474 11:04:59.678499 TX Vref=32, minBit 3, minWin=28, winSum=456
1475 11:04:59.681882 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 28
1476 11:04:59.681975
1477 11:04:59.685149 Final TX Range 1 Vref 28
1478 11:04:59.685234
1479 11:04:59.685297 ==
1480 11:04:59.688341 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 11:04:59.692570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1482 11:04:59.692682 ==
1483 11:04:59.695015
1484 11:04:59.695097
1485 11:04:59.695161 TX Vref Scan disable
1486 11:04:59.698610 == TX Byte 0 ==
1487 11:04:59.701601 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1488 11:04:59.704715 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1489 11:04:59.708261 == TX Byte 1 ==
1490 11:04:59.711937 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1491 11:04:59.715312 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1492 11:04:59.718528
1493 11:04:59.718616 [DATLAT]
1494 11:04:59.718680 Freq=800, CH1 RK0
1495 11:04:59.718740
1496 11:04:59.721735 DATLAT Default: 0xa
1497 11:04:59.721817 0, 0xFFFF, sum = 0
1498 11:04:59.725095 1, 0xFFFF, sum = 0
1499 11:04:59.725179 2, 0xFFFF, sum = 0
1500 11:04:59.728183 3, 0xFFFF, sum = 0
1501 11:04:59.728264 4, 0xFFFF, sum = 0
1502 11:04:59.731267 5, 0xFFFF, sum = 0
1503 11:04:59.734719 6, 0xFFFF, sum = 0
1504 11:04:59.734806 7, 0xFFFF, sum = 0
1505 11:04:59.734872 8, 0x0, sum = 1
1506 11:04:59.738522 9, 0x0, sum = 2
1507 11:04:59.738607 10, 0x0, sum = 3
1508 11:04:59.741480 11, 0x0, sum = 4
1509 11:04:59.741568 best_step = 9
1510 11:04:59.741632
1511 11:04:59.741691 ==
1512 11:04:59.744936 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 11:04:59.751969 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1514 11:04:59.752070 ==
1515 11:04:59.752138 RX Vref Scan: 1
1516 11:04:59.752197
1517 11:04:59.754929 Set Vref Range= 32 -> 127
1518 11:04:59.755013
1519 11:04:59.759261 RX Vref 32 -> 127, step: 1
1520 11:04:59.759343
1521 11:04:59.763695 RX Delay -111 -> 252, step: 8
1522 11:04:59.763785
1523 11:04:59.763850 Set Vref, RX VrefLevel [Byte0]: 32
1524 11:04:59.764800 [Byte1]: 32
1525 11:04:59.769005
1526 11:04:59.769096 Set Vref, RX VrefLevel [Byte0]: 33
1527 11:04:59.772549 [Byte1]: 33
1528 11:04:59.776944
1529 11:04:59.777040 Set Vref, RX VrefLevel [Byte0]: 34
1530 11:04:59.780060 [Byte1]: 34
1531 11:04:59.784576
1532 11:04:59.784693 Set Vref, RX VrefLevel [Byte0]: 35
1533 11:04:59.788101 [Byte1]: 35
1534 11:04:59.792465
1535 11:04:59.792554 Set Vref, RX VrefLevel [Byte0]: 36
1536 11:04:59.795177 [Byte1]: 36
1537 11:04:59.799736
1538 11:04:59.799825 Set Vref, RX VrefLevel [Byte0]: 37
1539 11:04:59.803082 [Byte1]: 37
1540 11:04:59.807962
1541 11:04:59.808057 Set Vref, RX VrefLevel [Byte0]: 38
1542 11:04:59.810909 [Byte1]: 38
1543 11:04:59.815038
1544 11:04:59.815129 Set Vref, RX VrefLevel [Byte0]: 39
1545 11:04:59.818590 [Byte1]: 39
1546 11:04:59.822622
1547 11:04:59.822709 Set Vref, RX VrefLevel [Byte0]: 40
1548 11:04:59.826700 [Byte1]: 40
1549 11:04:59.830111
1550 11:04:59.830196 Set Vref, RX VrefLevel [Byte0]: 41
1551 11:04:59.834629 [Byte1]: 41
1552 11:04:59.838790
1553 11:04:59.838878 Set Vref, RX VrefLevel [Byte0]: 42
1554 11:04:59.841666 [Byte1]: 42
1555 11:04:59.845270
1556 11:04:59.845355 Set Vref, RX VrefLevel [Byte0]: 43
1557 11:04:59.849147 [Byte1]: 43
1558 11:04:59.853620
1559 11:04:59.853753 Set Vref, RX VrefLevel [Byte0]: 44
1560 11:04:59.856439 [Byte1]: 44
1561 11:04:59.860908
1562 11:04:59.861031 Set Vref, RX VrefLevel [Byte0]: 45
1563 11:04:59.864321 [Byte1]: 45
1564 11:04:59.868730
1565 11:04:59.868857 Set Vref, RX VrefLevel [Byte0]: 46
1566 11:04:59.872557 [Byte1]: 46
1567 11:04:59.877105
1568 11:04:59.877194 Set Vref, RX VrefLevel [Byte0]: 47
1569 11:04:59.880029 [Byte1]: 47
1570 11:04:59.883916
1571 11:04:59.884001 Set Vref, RX VrefLevel [Byte0]: 48
1572 11:04:59.887109 [Byte1]: 48
1573 11:04:59.891308
1574 11:04:59.891392 Set Vref, RX VrefLevel [Byte0]: 49
1575 11:04:59.894439 [Byte1]: 49
1576 11:04:59.900287
1577 11:04:59.900376 Set Vref, RX VrefLevel [Byte0]: 50
1578 11:04:59.902711 [Byte1]: 50
1579 11:04:59.906799
1580 11:04:59.906888 Set Vref, RX VrefLevel [Byte0]: 51
1581 11:04:59.909967 [Byte1]: 51
1582 11:04:59.914428
1583 11:04:59.914522 Set Vref, RX VrefLevel [Byte0]: 52
1584 11:04:59.917514 [Byte1]: 52
1585 11:04:59.921992
1586 11:04:59.922081 Set Vref, RX VrefLevel [Byte0]: 53
1587 11:04:59.925494 [Byte1]: 53
1588 11:04:59.929719
1589 11:04:59.929819 Set Vref, RX VrefLevel [Byte0]: 54
1590 11:04:59.932943 [Byte1]: 54
1591 11:04:59.937365
1592 11:04:59.937451 Set Vref, RX VrefLevel [Byte0]: 55
1593 11:04:59.940519 [Byte1]: 55
1594 11:04:59.945925
1595 11:04:59.946010 Set Vref, RX VrefLevel [Byte0]: 56
1596 11:04:59.948219 [Byte1]: 56
1597 11:04:59.953245
1598 11:04:59.953330 Set Vref, RX VrefLevel [Byte0]: 57
1599 11:04:59.957164 [Byte1]: 57
1600 11:04:59.960416
1601 11:04:59.960499 Set Vref, RX VrefLevel [Byte0]: 58
1602 11:04:59.963591 [Byte1]: 58
1603 11:04:59.968551
1604 11:04:59.968640 Set Vref, RX VrefLevel [Byte0]: 59
1605 11:04:59.971363 [Byte1]: 59
1606 11:04:59.975490
1607 11:04:59.975573 Set Vref, RX VrefLevel [Byte0]: 60
1608 11:04:59.978782 [Byte1]: 60
1609 11:04:59.983000
1610 11:04:59.983084 Set Vref, RX VrefLevel [Byte0]: 61
1611 11:04:59.986803 [Byte1]: 61
1612 11:04:59.991861
1613 11:04:59.991951 Set Vref, RX VrefLevel [Byte0]: 62
1614 11:04:59.994733 [Byte1]: 62
1615 11:04:59.998743
1616 11:04:59.998829 Set Vref, RX VrefLevel [Byte0]: 63
1617 11:05:00.001688 [Byte1]: 63
1618 11:05:00.006297
1619 11:05:00.006384 Set Vref, RX VrefLevel [Byte0]: 64
1620 11:05:00.013013 [Byte1]: 64
1621 11:05:00.013124
1622 11:05:00.016504 Set Vref, RX VrefLevel [Byte0]: 65
1623 11:05:00.020186 [Byte1]: 65
1624 11:05:00.020272
1625 11:05:00.022593 Set Vref, RX VrefLevel [Byte0]: 66
1626 11:05:00.027045 [Byte1]: 66
1627 11:05:00.029025
1628 11:05:00.029109 Set Vref, RX VrefLevel [Byte0]: 67
1629 11:05:00.033027 [Byte1]: 67
1630 11:05:00.037213
1631 11:05:00.037298 Set Vref, RX VrefLevel [Byte0]: 68
1632 11:05:00.040124 [Byte1]: 68
1633 11:05:00.044845
1634 11:05:00.044932 Set Vref, RX VrefLevel [Byte0]: 69
1635 11:05:00.049147 [Byte1]: 69
1636 11:05:00.052242
1637 11:05:00.052323 Set Vref, RX VrefLevel [Byte0]: 70
1638 11:05:00.055420 [Byte1]: 70
1639 11:05:00.059923
1640 11:05:00.060006 Set Vref, RX VrefLevel [Byte0]: 71
1641 11:05:00.063326 [Byte1]: 71
1642 11:05:00.067747
1643 11:05:00.067832 Set Vref, RX VrefLevel [Byte0]: 72
1644 11:05:00.070773 [Byte1]: 72
1645 11:05:00.075053
1646 11:05:00.075141 Set Vref, RX VrefLevel [Byte0]: 73
1647 11:05:00.078534 [Byte1]: 73
1648 11:05:00.083213
1649 11:05:00.083301 Set Vref, RX VrefLevel [Byte0]: 74
1650 11:05:00.086070 [Byte1]: 74
1651 11:05:00.090747
1652 11:05:00.090831 Final RX Vref Byte 0 = 60 to rank0
1653 11:05:00.093574 Final RX Vref Byte 1 = 58 to rank0
1654 11:05:00.097073 Final RX Vref Byte 0 = 60 to rank1
1655 11:05:00.100268 Final RX Vref Byte 1 = 58 to rank1==
1656 11:05:00.104602 Dram Type= 6, Freq= 0, CH_1, rank 0
1657 11:05:00.111097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1658 11:05:00.111213 ==
1659 11:05:00.111279 DQS Delay:
1660 11:05:00.111338 DQS0 = 0, DQS1 = 0
1661 11:05:00.114271 DQM Delay:
1662 11:05:00.114367 DQM0 = 79, DQM1 = 71
1663 11:05:00.116615 DQ Delay:
1664 11:05:00.120260 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1665 11:05:00.120346 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1666 11:05:00.123653 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1667 11:05:00.129907 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =80
1668 11:05:00.130001
1669 11:05:00.130066
1670 11:05:00.137133 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d4d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1671 11:05:00.140298 CH1 RK0: MR19=606, MR18=4D4D
1672 11:05:00.146648 CH1_RK0: MR19=0x606, MR18=0x4D4D, DQSOSC=390, MR23=63, INC=97, DEC=64
1673 11:05:00.146751
1674 11:05:00.150566 ----->DramcWriteLeveling(PI) begin...
1675 11:05:00.150652 ==
1676 11:05:00.153591 Dram Type= 6, Freq= 0, CH_1, rank 1
1677 11:05:00.157306 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1678 11:05:00.157390 ==
1679 11:05:00.160464 Write leveling (Byte 0): 27 => 27
1680 11:05:00.163460 Write leveling (Byte 1): 25 => 25
1681 11:05:00.166545 DramcWriteLeveling(PI) end<-----
1682 11:05:00.166628
1683 11:05:00.166693 ==
1684 11:05:00.170334 Dram Type= 6, Freq= 0, CH_1, rank 1
1685 11:05:00.173141 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1686 11:05:00.173227 ==
1687 11:05:00.177808 [Gating] SW mode calibration
1688 11:05:00.183506 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1689 11:05:00.190054 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1690 11:05:00.193455 0 6 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
1691 11:05:00.197122 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1692 11:05:00.203507 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1693 11:05:00.206824 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1694 11:05:00.209994 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1695 11:05:00.216800 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1696 11:05:00.220346 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1697 11:05:00.222968 0 6 28 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
1698 11:05:00.229978 0 7 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1699 11:05:00.233992 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1700 11:05:00.236427 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1701 11:05:00.243340 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1702 11:05:00.246671 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1703 11:05:00.249871 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1704 11:05:00.256722 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1705 11:05:00.260479 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1706 11:05:00.263073 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1707 11:05:00.270164 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1708 11:05:00.273079 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1709 11:05:00.276832 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1710 11:05:00.283510 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1711 11:05:00.287109 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1712 11:05:00.289803 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1713 11:05:00.293649 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1714 11:05:00.299764 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1715 11:05:00.303284 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1716 11:05:00.306707 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1717 11:05:00.312932 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1718 11:05:00.316226 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 11:05:00.319495 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 11:05:00.326133 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 11:05:00.330197 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1722 11:05:00.333367 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1723 11:05:00.336941 Total UI for P1: 0, mck2ui 16
1724 11:05:00.339605 best dqsien dly found for B0: ( 0, 9, 28)
1725 11:05:00.347627 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1726 11:05:00.347739 Total UI for P1: 0, mck2ui 16
1727 11:05:00.352899 best dqsien dly found for B1: ( 0, 9, 30)
1728 11:05:00.357686 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1729 11:05:00.359312 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1730 11:05:00.359401
1731 11:05:00.363382 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1732 11:05:00.365998 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1733 11:05:00.370123 [Gating] SW calibration Done
1734 11:05:00.370219 ==
1735 11:05:00.373163 Dram Type= 6, Freq= 0, CH_1, rank 1
1736 11:05:00.376746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1737 11:05:00.376851 ==
1738 11:05:00.379845 RX Vref Scan: 0
1739 11:05:00.379930
1740 11:05:00.380016 RX Vref 0 -> 0, step: 1
1741 11:05:00.380095
1742 11:05:00.382852 RX Delay -130 -> 252, step: 16
1743 11:05:00.389608 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1744 11:05:00.393163 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1745 11:05:00.396487 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1746 11:05:00.399379 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1747 11:05:00.403371 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1748 11:05:00.405793 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1749 11:05:00.413320 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1750 11:05:00.415973 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1751 11:05:00.419675 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1752 11:05:00.423071 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1753 11:05:00.426118 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1754 11:05:00.432573 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1755 11:05:00.436206 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1756 11:05:00.439490 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1757 11:05:00.442926 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1758 11:05:00.448993 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1759 11:05:00.449090 ==
1760 11:05:00.452763 Dram Type= 6, Freq= 0, CH_1, rank 1
1761 11:05:00.456244 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1762 11:05:00.456332 ==
1763 11:05:00.456398 DQS Delay:
1764 11:05:00.459518 DQS0 = 0, DQS1 = 0
1765 11:05:00.459604 DQM Delay:
1766 11:05:00.462793 DQM0 = 83, DQM1 = 70
1767 11:05:00.462878 DQ Delay:
1768 11:05:00.466391 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1769 11:05:00.470259 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1770 11:05:00.473245 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1771 11:05:00.477627 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1772 11:05:00.477715
1773 11:05:00.477781
1774 11:05:00.477854 ==
1775 11:05:00.479526 Dram Type= 6, Freq= 0, CH_1, rank 1
1776 11:05:00.483150 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1777 11:05:00.483234 ==
1778 11:05:00.483298
1779 11:05:00.483357
1780 11:05:00.486885 TX Vref Scan disable
1781 11:05:00.489032 == TX Byte 0 ==
1782 11:05:00.492427 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1783 11:05:00.497384 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1784 11:05:00.499403 == TX Byte 1 ==
1785 11:05:00.502995 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1786 11:05:00.505800 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1787 11:05:00.505885 ==
1788 11:05:00.509759 Dram Type= 6, Freq= 0, CH_1, rank 1
1789 11:05:00.516569 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1790 11:05:00.516695 ==
1791 11:05:00.527581 TX Vref=22, minBit 1, minWin=28, winSum=453
1792 11:05:00.530680 TX Vref=24, minBit 8, minWin=27, winSum=453
1793 11:05:00.534729 TX Vref=26, minBit 0, minWin=28, winSum=455
1794 11:05:00.538319 TX Vref=28, minBit 0, minWin=28, winSum=458
1795 11:05:00.541143 TX Vref=30, minBit 1, minWin=28, winSum=457
1796 11:05:00.544309 TX Vref=32, minBit 0, minWin=28, winSum=456
1797 11:05:00.551475 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1798 11:05:00.551580
1799 11:05:00.554475 Final TX Range 1 Vref 28
1800 11:05:00.554557
1801 11:05:00.554620 ==
1802 11:05:00.557417 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 11:05:00.561228 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1804 11:05:00.561317 ==
1805 11:05:00.561381
1806 11:05:00.564121
1807 11:05:00.564201 TX Vref Scan disable
1808 11:05:00.567229 == TX Byte 0 ==
1809 11:05:00.570426 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1810 11:05:00.577441 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1811 11:05:00.577540 == TX Byte 1 ==
1812 11:05:00.580833 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1813 11:05:00.588209 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1814 11:05:00.588314
1815 11:05:00.588380 [DATLAT]
1816 11:05:00.588439 Freq=800, CH1 RK1
1817 11:05:00.588499
1818 11:05:00.590555 DATLAT Default: 0x9
1819 11:05:00.590637 0, 0xFFFF, sum = 0
1820 11:05:00.594173 1, 0xFFFF, sum = 0
1821 11:05:00.597172 2, 0xFFFF, sum = 0
1822 11:05:00.597258 3, 0xFFFF, sum = 0
1823 11:05:00.600142 4, 0xFFFF, sum = 0
1824 11:05:00.600226 5, 0xFFFF, sum = 0
1825 11:05:00.604205 6, 0xFFFF, sum = 0
1826 11:05:00.604289 7, 0xFFFF, sum = 0
1827 11:05:00.607734 8, 0x0, sum = 1
1828 11:05:00.607821 9, 0x0, sum = 2
1829 11:05:00.607887 10, 0x0, sum = 3
1830 11:05:00.610232 11, 0x0, sum = 4
1831 11:05:00.610317 best_step = 9
1832 11:05:00.610381
1833 11:05:00.610440 ==
1834 11:05:00.613986 Dram Type= 6, Freq= 0, CH_1, rank 1
1835 11:05:00.620832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1836 11:05:00.620963 ==
1837 11:05:00.621053 RX Vref Scan: 0
1838 11:05:00.621133
1839 11:05:00.623506 RX Vref 0 -> 0, step: 1
1840 11:05:00.623614
1841 11:05:00.627034 RX Delay -111 -> 252, step: 8
1842 11:05:00.630522 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1843 11:05:00.633613 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
1844 11:05:00.640211 iDelay=209, Bit 2, Center 72 (-47 ~ 192) 240
1845 11:05:00.644208 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1846 11:05:00.647289 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1847 11:05:00.650809 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1848 11:05:00.653738 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1849 11:05:00.660115 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1850 11:05:00.663480 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1851 11:05:00.666847 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1852 11:05:00.670220 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1853 11:05:00.673444 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1854 11:05:00.679987 iDelay=209, Bit 12, Center 84 (-39 ~ 208) 248
1855 11:05:00.683440 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
1856 11:05:00.686974 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1857 11:05:00.690420 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1858 11:05:00.690509 ==
1859 11:05:00.693265 Dram Type= 6, Freq= 0, CH_1, rank 1
1860 11:05:00.700228 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1861 11:05:00.700331 ==
1862 11:05:00.700418 DQS Delay:
1863 11:05:00.703639 DQS0 = 0, DQS1 = 0
1864 11:05:00.703724 DQM Delay:
1865 11:05:00.706576 DQM0 = 82, DQM1 = 72
1866 11:05:00.706661 DQ Delay:
1867 11:05:00.710553 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1868 11:05:00.713503 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =80
1869 11:05:00.717830 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1870 11:05:00.720718 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
1871 11:05:00.720868
1872 11:05:00.720963
1873 11:05:00.726391 [DQSOSCAuto] RK1, (LSB)MR18= 0x3434, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1874 11:05:00.729899 CH1 RK1: MR19=606, MR18=3434
1875 11:05:00.736664 CH1_RK1: MR19=0x606, MR18=0x3434, DQSOSC=396, MR23=63, INC=94, DEC=62
1876 11:05:00.740052 [RxdqsGatingPostProcess] freq 800
1877 11:05:00.743424 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1878 11:05:00.746437 Pre-setting of DQS Precalculation
1879 11:05:00.753249 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1880 11:05:00.759757 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1881 11:05:00.767448 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1882 11:05:00.767568
1883 11:05:00.767633
1884 11:05:00.770162 [Calibration Summary] 1600 Mbps
1885 11:05:00.770246 CH 0, Rank 0
1886 11:05:00.773494 SW Impedance : PASS
1887 11:05:00.776552 DUTY Scan : NO K
1888 11:05:00.776638 ZQ Calibration : PASS
1889 11:05:00.779703 Jitter Meter : NO K
1890 11:05:00.783981 CBT Training : PASS
1891 11:05:00.784069 Write leveling : PASS
1892 11:05:00.786070 RX DQS gating : PASS
1893 11:05:00.789977 RX DQ/DQS(RDDQC) : PASS
1894 11:05:00.790063 TX DQ/DQS : PASS
1895 11:05:00.792861 RX DATLAT : PASS
1896 11:05:00.792944 RX DQ/DQS(Engine): PASS
1897 11:05:00.796621 TX OE : NO K
1898 11:05:00.796714 All Pass.
1899 11:05:00.796815
1900 11:05:00.799768 CH 0, Rank 1
1901 11:05:00.799851 SW Impedance : PASS
1902 11:05:00.803138 DUTY Scan : NO K
1903 11:05:00.806227 ZQ Calibration : PASS
1904 11:05:00.806313 Jitter Meter : NO K
1905 11:05:00.810154 CBT Training : PASS
1906 11:05:00.813233 Write leveling : PASS
1907 11:05:00.813326 RX DQS gating : PASS
1908 11:05:00.816554 RX DQ/DQS(RDDQC) : PASS
1909 11:05:00.820122 TX DQ/DQS : PASS
1910 11:05:00.820212 RX DATLAT : PASS
1911 11:05:00.824515 RX DQ/DQS(Engine): PASS
1912 11:05:00.826649 TX OE : NO K
1913 11:05:00.826734 All Pass.
1914 11:05:00.826799
1915 11:05:00.826858 CH 1, Rank 0
1916 11:05:00.830192 SW Impedance : PASS
1917 11:05:00.833097 DUTY Scan : NO K
1918 11:05:00.833182 ZQ Calibration : PASS
1919 11:05:00.836254 Jitter Meter : NO K
1920 11:05:00.839975 CBT Training : PASS
1921 11:05:00.840063 Write leveling : PASS
1922 11:05:00.842882 RX DQS gating : PASS
1923 11:05:00.842965 RX DQ/DQS(RDDQC) : PASS
1924 11:05:00.846525 TX DQ/DQS : PASS
1925 11:05:00.849774 RX DATLAT : PASS
1926 11:05:00.849865 RX DQ/DQS(Engine): PASS
1927 11:05:00.853609 TX OE : NO K
1928 11:05:00.853697 All Pass.
1929 11:05:00.853763
1930 11:05:00.857206 CH 1, Rank 1
1931 11:05:00.857292 SW Impedance : PASS
1932 11:05:00.860089 DUTY Scan : NO K
1933 11:05:00.863239 ZQ Calibration : PASS
1934 11:05:00.863324 Jitter Meter : NO K
1935 11:05:00.866229 CBT Training : PASS
1936 11:05:00.869410 Write leveling : PASS
1937 11:05:00.869496 RX DQS gating : PASS
1938 11:05:00.872962 RX DQ/DQS(RDDQC) : PASS
1939 11:05:00.876050 TX DQ/DQS : PASS
1940 11:05:00.876139 RX DATLAT : PASS
1941 11:05:00.880186 RX DQ/DQS(Engine): PASS
1942 11:05:00.880278 TX OE : NO K
1943 11:05:00.883651 All Pass.
1944 11:05:00.883727
1945 11:05:00.883788 DramC Write-DBI off
1946 11:05:00.886821 PER_BANK_REFRESH: Hybrid Mode
1947 11:05:00.889899 TX_TRACKING: ON
1948 11:05:00.893117 [GetDramInforAfterCalByMRR] Vendor 6.
1949 11:05:00.896558 [GetDramInforAfterCalByMRR] Revision 606.
1950 11:05:00.900124 [GetDramInforAfterCalByMRR] Revision 2 0.
1951 11:05:00.900211 MR0 0x3939
1952 11:05:00.900277 MR8 0x1111
1953 11:05:00.906981 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1954 11:05:00.907081
1955 11:05:00.907148 MR0 0x3939
1956 11:05:00.907209 MR8 0x1111
1957 11:05:00.909861 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1958 11:05:00.909945
1959 11:05:00.919655 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1960 11:05:00.922865 [FAST_K] Save calibration result to emmc
1961 11:05:00.926150 [FAST_K] Save calibration result to emmc
1962 11:05:00.933143 dram_init: config_dvfs: 1
1963 11:05:00.934086 dramc_set_vcore_voltage set vcore to 662500
1964 11:05:00.936601 Read voltage for 1200, 2
1965 11:05:00.936685 Vio18 = 0
1966 11:05:00.936758 Vcore = 662500
1967 11:05:00.939377 Vdram = 0
1968 11:05:00.939460 Vddq = 0
1969 11:05:00.939524 Vmddr = 0
1970 11:05:00.946391 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1971 11:05:00.950093 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1972 11:05:00.952893 MEM_TYPE=3, freq_sel=15
1973 11:05:00.956150 sv_algorithm_assistance_LP4_1600
1974 11:05:00.959726 ============ PULL DRAM RESETB DOWN ============
1975 11:05:00.966600 ========== PULL DRAM RESETB DOWN end =========
1976 11:05:00.970497 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1977 11:05:00.972720 ===================================
1978 11:05:00.976470 LPDDR4 DRAM CONFIGURATION
1979 11:05:00.979434 ===================================
1980 11:05:00.979521 EX_ROW_EN[0] = 0x0
1981 11:05:00.982844 EX_ROW_EN[1] = 0x0
1982 11:05:00.982926 LP4Y_EN = 0x0
1983 11:05:00.985863 WORK_FSP = 0x0
1984 11:05:00.985946 WL = 0x4
1985 11:05:00.989485 RL = 0x4
1986 11:05:00.989567 BL = 0x2
1987 11:05:00.992786 RPST = 0x0
1988 11:05:00.992882 RD_PRE = 0x0
1989 11:05:00.995961 WR_PRE = 0x1
1990 11:05:00.996044 WR_PST = 0x0
1991 11:05:00.999918 DBI_WR = 0x0
1992 11:05:01.000001 DBI_RD = 0x0
1993 11:05:01.002883 OTF = 0x1
1994 11:05:01.006384 ===================================
1995 11:05:01.009589 ===================================
1996 11:05:01.009676 ANA top config
1997 11:05:01.012732 ===================================
1998 11:05:01.016017 DLL_ASYNC_EN = 0
1999 11:05:01.019428 ALL_SLAVE_EN = 0
2000 11:05:01.022801 NEW_RANK_MODE = 1
2001 11:05:01.022891 DLL_IDLE_MODE = 1
2002 11:05:01.026008 LP45_APHY_COMB_EN = 1
2003 11:05:01.029430 TX_ODT_DIS = 1
2004 11:05:01.032954 NEW_8X_MODE = 1
2005 11:05:01.036000 ===================================
2006 11:05:01.039352 ===================================
2007 11:05:01.043040 data_rate = 2400
2008 11:05:01.043128 CKR = 1
2009 11:05:01.046314 DQ_P2S_RATIO = 8
2010 11:05:01.049151 ===================================
2011 11:05:01.052817 CA_P2S_RATIO = 8
2012 11:05:01.056896 DQ_CA_OPEN = 0
2013 11:05:01.059615 DQ_SEMI_OPEN = 0
2014 11:05:01.062917 CA_SEMI_OPEN = 0
2015 11:05:01.063001 CA_FULL_RATE = 0
2016 11:05:01.066234 DQ_CKDIV4_EN = 0
2017 11:05:01.069444 CA_CKDIV4_EN = 0
2018 11:05:01.072930 CA_PREDIV_EN = 0
2019 11:05:01.076158 PH8_DLY = 17
2020 11:05:01.079343 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2021 11:05:01.079430 DQ_AAMCK_DIV = 4
2022 11:05:01.083000 CA_AAMCK_DIV = 4
2023 11:05:01.086204 CA_ADMCK_DIV = 4
2024 11:05:01.089409 DQ_TRACK_CA_EN = 0
2025 11:05:01.093292 CA_PICK = 1200
2026 11:05:01.095966 CA_MCKIO = 1200
2027 11:05:01.099154 MCKIO_SEMI = 0
2028 11:05:01.099239 PLL_FREQ = 2366
2029 11:05:01.102701 DQ_UI_PI_RATIO = 32
2030 11:05:01.105740 CA_UI_PI_RATIO = 0
2031 11:05:01.109272 ===================================
2032 11:05:01.112656 ===================================
2033 11:05:01.116164 memory_type:LPDDR4
2034 11:05:01.119222 GP_NUM : 10
2035 11:05:01.119310 SRAM_EN : 1
2036 11:05:01.122499 MD32_EN : 0
2037 11:05:01.126067 ===================================
2038 11:05:01.126151 [ANA_INIT] >>>>>>>>>>>>>>
2039 11:05:01.129728 <<<<<< [CONFIGURE PHASE]: ANA_TX
2040 11:05:01.133695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2041 11:05:01.136178 ===================================
2042 11:05:01.140558 data_rate = 2400,PCW = 0X5b00
2043 11:05:01.142412 ===================================
2044 11:05:01.147306 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2045 11:05:01.152850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2046 11:05:01.157122 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2047 11:05:01.162578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2048 11:05:01.165861 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2049 11:05:01.169625 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2050 11:05:01.172870 [ANA_INIT] flow start
2051 11:05:01.172957 [ANA_INIT] PLL >>>>>>>>
2052 11:05:01.176769 [ANA_INIT] PLL <<<<<<<<
2053 11:05:01.179115 [ANA_INIT] MIDPI >>>>>>>>
2054 11:05:01.179199 [ANA_INIT] MIDPI <<<<<<<<
2055 11:05:01.182274 [ANA_INIT] DLL >>>>>>>>
2056 11:05:01.185697 [ANA_INIT] DLL <<<<<<<<
2057 11:05:01.185782 [ANA_INIT] flow end
2058 11:05:01.189544 ============ LP4 DIFF to SE enter ============
2059 11:05:01.195698 ============ LP4 DIFF to SE exit ============
2060 11:05:01.195799 [ANA_INIT] <<<<<<<<<<<<<
2061 11:05:01.199969 [Flow] Enable top DCM control >>>>>
2062 11:05:01.202828 [Flow] Enable top DCM control <<<<<
2063 11:05:01.206054 Enable DLL master slave shuffle
2064 11:05:01.213098 ==============================================================
2065 11:05:01.213213 Gating Mode config
2066 11:05:01.219694 ==============================================================
2067 11:05:01.222237 Config description:
2068 11:05:01.232744 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2069 11:05:01.239389 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2070 11:05:01.242763 SELPH_MODE 0: By rank 1: By Phase
2071 11:05:01.249018 ==============================================================
2072 11:05:01.252595 GAT_TRACK_EN = 1
2073 11:05:01.256183 RX_GATING_MODE = 2
2074 11:05:01.256270 RX_GATING_TRACK_MODE = 2
2075 11:05:01.259016 SELPH_MODE = 1
2076 11:05:01.262307 PICG_EARLY_EN = 1
2077 11:05:01.266757 VALID_LAT_VALUE = 1
2078 11:05:01.272308 ==============================================================
2079 11:05:01.276245 Enter into Gating configuration >>>>
2080 11:05:01.279353 Exit from Gating configuration <<<<
2081 11:05:01.283115 Enter into DVFS_PRE_config >>>>>
2082 11:05:01.292536 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2083 11:05:01.295604 Exit from DVFS_PRE_config <<<<<
2084 11:05:01.299007 Enter into PICG configuration >>>>
2085 11:05:01.302238 Exit from PICG configuration <<<<
2086 11:05:01.305749 [RX_INPUT] configuration >>>>>
2087 11:05:01.305841 [RX_INPUT] configuration <<<<<
2088 11:05:01.312619 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2089 11:05:01.318819 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2090 11:05:01.325811 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2091 11:05:01.328821 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2092 11:05:01.335473 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2093 11:05:01.341977 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2094 11:05:01.345979 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2095 11:05:01.349249 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2096 11:05:01.355696 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2097 11:05:01.359562 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2098 11:05:01.362254 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2099 11:05:01.368974 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2100 11:05:01.373115 ===================================
2101 11:05:01.373202 LPDDR4 DRAM CONFIGURATION
2102 11:05:01.375947 ===================================
2103 11:05:01.379296 EX_ROW_EN[0] = 0x0
2104 11:05:01.379376 EX_ROW_EN[1] = 0x0
2105 11:05:01.382803 LP4Y_EN = 0x0
2106 11:05:01.382882 WORK_FSP = 0x0
2107 11:05:01.385516 WL = 0x4
2108 11:05:01.389423 RL = 0x4
2109 11:05:01.389503 BL = 0x2
2110 11:05:01.392160 RPST = 0x0
2111 11:05:01.392240 RD_PRE = 0x0
2112 11:05:01.395802 WR_PRE = 0x1
2113 11:05:01.395882 WR_PST = 0x0
2114 11:05:01.399453 DBI_WR = 0x0
2115 11:05:01.399534 DBI_RD = 0x0
2116 11:05:01.402550 OTF = 0x1
2117 11:05:01.405231 ===================================
2118 11:05:01.409177 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2119 11:05:01.412237 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2120 11:05:01.415518 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2121 11:05:01.418812 ===================================
2122 11:05:01.422380 LPDDR4 DRAM CONFIGURATION
2123 11:05:01.425270 ===================================
2124 11:05:01.429015 EX_ROW_EN[0] = 0x10
2125 11:05:01.429099 EX_ROW_EN[1] = 0x0
2126 11:05:01.432281 LP4Y_EN = 0x0
2127 11:05:01.432360 WORK_FSP = 0x0
2128 11:05:01.436287 WL = 0x4
2129 11:05:01.436367 RL = 0x4
2130 11:05:01.438847 BL = 0x2
2131 11:05:01.438927 RPST = 0x0
2132 11:05:01.442185 RD_PRE = 0x0
2133 11:05:01.442265 WR_PRE = 0x1
2134 11:05:01.445343 WR_PST = 0x0
2135 11:05:01.448866 DBI_WR = 0x0
2136 11:05:01.448945 DBI_RD = 0x0
2137 11:05:01.452360 OTF = 0x1
2138 11:05:01.455642 ===================================
2139 11:05:01.458855 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2140 11:05:01.461958 ==
2141 11:05:01.462037 Dram Type= 6, Freq= 0, CH_0, rank 0
2142 11:05:01.469149 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2143 11:05:01.469230 ==
2144 11:05:01.472677 [Duty_Offset_Calibration]
2145 11:05:01.472860 B0:0 B1:2 CA:1
2146 11:05:01.472943
2147 11:05:01.475515 [DutyScan_Calibration_Flow] k_type=0
2148 11:05:01.485113
2149 11:05:01.485194 ==CLK 0==
2150 11:05:01.488356 Final CLK duty delay cell = 0
2151 11:05:01.491762 [0] MAX Duty = 5093%(X100), DQS PI = 12
2152 11:05:01.494901 [0] MIN Duty = 4938%(X100), DQS PI = 52
2153 11:05:01.494981 [0] AVG Duty = 5015%(X100)
2154 11:05:01.498619
2155 11:05:01.501737 CH0 CLK Duty spec in!! Max-Min= 155%
2156 11:05:01.504994 [DutyScan_Calibration_Flow] ====Done====
2157 11:05:01.505073
2158 11:05:01.508486 [DutyScan_Calibration_Flow] k_type=1
2159 11:05:01.523931
2160 11:05:01.524024 ==DQS 0 ==
2161 11:05:01.527199 Final DQS duty delay cell = 0
2162 11:05:01.530570 [0] MAX Duty = 5125%(X100), DQS PI = 32
2163 11:05:01.534313 [0] MIN Duty = 5031%(X100), DQS PI = 6
2164 11:05:01.534393 [0] AVG Duty = 5078%(X100)
2165 11:05:01.537269
2166 11:05:01.537349 ==DQS 1 ==
2167 11:05:01.540965 Final DQS duty delay cell = 0
2168 11:05:01.544220 [0] MAX Duty = 5062%(X100), DQS PI = 58
2169 11:05:01.547405 [0] MIN Duty = 4906%(X100), DQS PI = 16
2170 11:05:01.550476 [0] AVG Duty = 4984%(X100)
2171 11:05:01.550555
2172 11:05:01.554157 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2173 11:05:01.554238
2174 11:05:01.557374 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2175 11:05:01.560607 [DutyScan_Calibration_Flow] ====Done====
2176 11:05:01.560687
2177 11:05:01.563580 [DutyScan_Calibration_Flow] k_type=3
2178 11:05:01.581558
2179 11:05:01.581650 ==DQM 0 ==
2180 11:05:01.585609 Final DQM duty delay cell = 0
2181 11:05:01.588613 [0] MAX Duty = 5156%(X100), DQS PI = 22
2182 11:05:01.591814 [0] MIN Duty = 4969%(X100), DQS PI = 40
2183 11:05:01.595158 [0] AVG Duty = 5062%(X100)
2184 11:05:01.595238
2185 11:05:01.595300 ==DQM 1 ==
2186 11:05:01.597599 Final DQM duty delay cell = 4
2187 11:05:01.601128 [4] MAX Duty = 5187%(X100), DQS PI = 54
2188 11:05:01.604128 [4] MIN Duty = 5000%(X100), DQS PI = 18
2189 11:05:01.607716 [4] AVG Duty = 5093%(X100)
2190 11:05:01.607808
2191 11:05:01.611104 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2192 11:05:01.611183
2193 11:05:01.614431 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2194 11:05:01.618054 [DutyScan_Calibration_Flow] ====Done====
2195 11:05:01.618164
2196 11:05:01.620809 [DutyScan_Calibration_Flow] k_type=2
2197 11:05:01.636027
2198 11:05:01.636111 ==DQ 0 ==
2199 11:05:01.639615 Final DQ duty delay cell = -4
2200 11:05:01.642919 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2201 11:05:01.646202 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2202 11:05:01.649711 [-4] AVG Duty = 4937%(X100)
2203 11:05:01.649791
2204 11:05:01.649854 ==DQ 1 ==
2205 11:05:01.652586 Final DQ duty delay cell = -4
2206 11:05:01.656067 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2207 11:05:01.659556 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2208 11:05:01.663142 [-4] AVG Duty = 4984%(X100)
2209 11:05:01.663221
2210 11:05:01.666236 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2211 11:05:01.666316
2212 11:05:01.669443 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2213 11:05:01.672972 [DutyScan_Calibration_Flow] ====Done====
2214 11:05:01.673082 ==
2215 11:05:01.676152 Dram Type= 6, Freq= 0, CH_1, rank 0
2216 11:05:01.680075 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2217 11:05:01.680157 ==
2218 11:05:01.682724 [Duty_Offset_Calibration]
2219 11:05:01.682805 B0:0 B1:4 CA:-5
2220 11:05:01.682870
2221 11:05:01.686576 [DutyScan_Calibration_Flow] k_type=0
2222 11:05:01.696699
2223 11:05:01.696789 ==CLK 0==
2224 11:05:01.700607 Final CLK duty delay cell = 0
2225 11:05:01.704267 [0] MAX Duty = 5125%(X100), DQS PI = 16
2226 11:05:01.706843 [0] MIN Duty = 4875%(X100), DQS PI = 48
2227 11:05:01.706924 [0] AVG Duty = 5000%(X100)
2228 11:05:01.711198
2229 11:05:01.713787 CH1 CLK Duty spec in!! Max-Min= 250%
2230 11:05:01.716509 [DutyScan_Calibration_Flow] ====Done====
2231 11:05:01.716590
2232 11:05:01.719960 [DutyScan_Calibration_Flow] k_type=1
2233 11:05:01.736020
2234 11:05:01.736104 ==DQS 0 ==
2235 11:05:01.738632 Final DQS duty delay cell = 0
2236 11:05:01.742240 [0] MAX Duty = 5125%(X100), DQS PI = 16
2237 11:05:01.745327 [0] MIN Duty = 4875%(X100), DQS PI = 40
2238 11:05:01.748902 [0] AVG Duty = 5000%(X100)
2239 11:05:01.748984
2240 11:05:01.749048 ==DQS 1 ==
2241 11:05:01.752276 Final DQS duty delay cell = -4
2242 11:05:01.755473 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2243 11:05:01.758527 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2244 11:05:01.762059 [-4] AVG Duty = 4953%(X100)
2245 11:05:01.762141
2246 11:05:01.765278 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2247 11:05:01.765359
2248 11:05:01.768596 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2249 11:05:01.771881 [DutyScan_Calibration_Flow] ====Done====
2250 11:05:01.771962
2251 11:05:01.775059 [DutyScan_Calibration_Flow] k_type=3
2252 11:05:01.790462
2253 11:05:01.790545 ==DQM 0 ==
2254 11:05:01.794325 Final DQM duty delay cell = -4
2255 11:05:01.797372 [-4] MAX Duty = 5094%(X100), DQS PI = 30
2256 11:05:01.800427 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2257 11:05:01.803806 [-4] AVG Duty = 4969%(X100)
2258 11:05:01.803887
2259 11:05:01.803952 ==DQM 1 ==
2260 11:05:01.807412 Final DQM duty delay cell = -4
2261 11:05:01.810674 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2262 11:05:01.814794 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2263 11:05:01.817135 [-4] AVG Duty = 4968%(X100)
2264 11:05:01.817219
2265 11:05:01.820527 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2266 11:05:01.820608
2267 11:05:01.823373 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2268 11:05:01.826927 [DutyScan_Calibration_Flow] ====Done====
2269 11:05:01.827007
2270 11:05:01.830378 [DutyScan_Calibration_Flow] k_type=2
2271 11:05:01.847384
2272 11:05:01.847466 ==DQ 0 ==
2273 11:05:01.850690 Final DQ duty delay cell = 0
2274 11:05:01.854274 [0] MAX Duty = 5062%(X100), DQS PI = 0
2275 11:05:01.857372 [0] MIN Duty = 4938%(X100), DQS PI = 44
2276 11:05:01.857453 [0] AVG Duty = 5000%(X100)
2277 11:05:01.857517
2278 11:05:01.860679 ==DQ 1 ==
2279 11:05:01.864289 Final DQ duty delay cell = 0
2280 11:05:01.867780 [0] MAX Duty = 5031%(X100), DQS PI = 6
2281 11:05:01.870960 [0] MIN Duty = 4875%(X100), DQS PI = 16
2282 11:05:01.871039 [0] AVG Duty = 4953%(X100)
2283 11:05:01.871102
2284 11:05:01.873600 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2285 11:05:01.873680
2286 11:05:01.881062 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2287 11:05:01.883990 [DutyScan_Calibration_Flow] ====Done====
2288 11:05:01.887366 nWR fixed to 30
2289 11:05:01.887470 [ModeRegInit_LP4] CH0 RK0
2290 11:05:01.890663 [ModeRegInit_LP4] CH0 RK1
2291 11:05:01.894597 [ModeRegInit_LP4] CH1 RK0
2292 11:05:01.894678 [ModeRegInit_LP4] CH1 RK1
2293 11:05:01.898124 match AC timing 6
2294 11:05:01.901329 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2295 11:05:01.904075 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2296 11:05:01.910456 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2297 11:05:01.914148 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2298 11:05:01.920824 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2299 11:05:01.920934 ==
2300 11:05:01.924877 Dram Type= 6, Freq= 0, CH_0, rank 0
2301 11:05:01.927075 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2302 11:05:01.927156 ==
2303 11:05:01.934122 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2304 11:05:01.937123 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2305 11:05:01.947132 [CA 0] Center 39 (9~70) winsize 62
2306 11:05:01.950751 [CA 1] Center 39 (9~70) winsize 62
2307 11:05:01.953471 [CA 2] Center 36 (5~67) winsize 63
2308 11:05:01.956730 [CA 3] Center 35 (5~66) winsize 62
2309 11:05:01.959908 [CA 4] Center 34 (4~65) winsize 62
2310 11:05:01.963527 [CA 5] Center 33 (3~64) winsize 62
2311 11:05:01.963606
2312 11:05:01.967457 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2313 11:05:01.967538
2314 11:05:01.969975 [CATrainingPosCal] consider 1 rank data
2315 11:05:01.973301 u2DelayCellTimex100 = 270/100 ps
2316 11:05:01.977745 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2317 11:05:01.983674 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2318 11:05:01.987098 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2319 11:05:01.989886 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2320 11:05:01.993467 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2321 11:05:01.996860 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2322 11:05:01.996941
2323 11:05:01.999802 CA PerBit enable=1, Macro0, CA PI delay=33
2324 11:05:01.999881
2325 11:05:02.003828 [CBTSetCACLKResult] CA Dly = 33
2326 11:05:02.006801 CS Dly: 7 (0~38)
2327 11:05:02.006880 ==
2328 11:05:02.009897 Dram Type= 6, Freq= 0, CH_0, rank 1
2329 11:05:02.013470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2330 11:05:02.013554 ==
2331 11:05:02.020010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2332 11:05:02.023589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2333 11:05:02.032741 [CA 0] Center 39 (8~70) winsize 63
2334 11:05:02.035643 [CA 1] Center 39 (8~70) winsize 63
2335 11:05:02.039812 [CA 2] Center 36 (5~67) winsize 63
2336 11:05:02.043330 [CA 3] Center 35 (4~66) winsize 63
2337 11:05:02.045719 [CA 4] Center 33 (3~64) winsize 62
2338 11:05:02.049593 [CA 5] Center 33 (3~64) winsize 62
2339 11:05:02.049673
2340 11:05:02.052236 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2341 11:05:02.052314
2342 11:05:02.055730 [CATrainingPosCal] consider 2 rank data
2343 11:05:02.059650 u2DelayCellTimex100 = 270/100 ps
2344 11:05:02.062351 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2345 11:05:02.065674 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2346 11:05:02.072265 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2347 11:05:02.076201 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2348 11:05:02.079016 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2349 11:05:02.083047 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2350 11:05:02.083128
2351 11:05:02.085743 CA PerBit enable=1, Macro0, CA PI delay=33
2352 11:05:02.085823
2353 11:05:02.088981 [CBTSetCACLKResult] CA Dly = 33
2354 11:05:02.089061 CS Dly: 7 (0~39)
2355 11:05:02.092550
2356 11:05:02.096379 ----->DramcWriteLeveling(PI) begin...
2357 11:05:02.096460 ==
2358 11:05:02.099145 Dram Type= 6, Freq= 0, CH_0, rank 0
2359 11:05:02.102013 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2360 11:05:02.102094 ==
2361 11:05:02.105572 Write leveling (Byte 0): 29 => 29
2362 11:05:02.108856 Write leveling (Byte 1): 25 => 25
2363 11:05:02.112231 DramcWriteLeveling(PI) end<-----
2364 11:05:02.112311
2365 11:05:02.112373 ==
2366 11:05:02.115908 Dram Type= 6, Freq= 0, CH_0, rank 0
2367 11:05:02.119291 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2368 11:05:02.119374 ==
2369 11:05:02.122087 [Gating] SW mode calibration
2370 11:05:02.128865 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2371 11:05:02.135703 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2372 11:05:02.139562 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2373 11:05:02.142263 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2374 11:05:02.148585 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2375 11:05:02.152161 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2376 11:05:02.156102 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2377 11:05:02.158961 0 11 20 | B1->B0 | 3030 2a2a | 1 1 | (0 1) (1 0)
2378 11:05:02.165943 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2379 11:05:02.168945 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2380 11:05:02.172133 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2381 11:05:02.178855 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2382 11:05:02.182248 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2383 11:05:02.185349 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2384 11:05:02.192049 0 12 16 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
2385 11:05:02.195691 0 12 20 | B1->B0 | 2f2f 3939 | 0 0 | (0 0) (0 0)
2386 11:05:02.198707 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2387 11:05:02.205245 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2388 11:05:02.208383 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2389 11:05:02.211972 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2390 11:05:02.218465 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2391 11:05:02.222020 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2392 11:05:02.225352 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2393 11:05:02.233920 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2394 11:05:02.235087 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2395 11:05:02.238342 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2396 11:05:02.245624 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2397 11:05:02.248560 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2398 11:05:02.251924 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2399 11:05:02.258845 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2400 11:05:02.261832 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2401 11:05:02.265253 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2402 11:05:02.272129 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2403 11:05:02.275206 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2404 11:05:02.278720 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2405 11:05:02.281881 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 11:05:02.289321 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 11:05:02.291645 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 11:05:02.295086 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2409 11:05:02.301753 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2410 11:05:02.304910 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2411 11:05:02.308310 Total UI for P1: 0, mck2ui 16
2412 11:05:02.311707 best dqsien dly found for B0: ( 0, 15, 18)
2413 11:05:02.315357 Total UI for P1: 0, mck2ui 16
2414 11:05:02.318415 best dqsien dly found for B1: ( 0, 15, 18)
2415 11:05:02.321535 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2416 11:05:02.324843 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2417 11:05:02.324926
2418 11:05:02.328584 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2419 11:05:02.331781 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2420 11:05:02.335773 [Gating] SW calibration Done
2421 11:05:02.335855 ==
2422 11:05:02.338454 Dram Type= 6, Freq= 0, CH_0, rank 0
2423 11:05:02.345342 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2424 11:05:02.345425 ==
2425 11:05:02.345489 RX Vref Scan: 0
2426 11:05:02.345548
2427 11:05:02.348520 RX Vref 0 -> 0, step: 1
2428 11:05:02.348626
2429 11:05:02.351884 RX Delay -40 -> 252, step: 8
2430 11:05:02.355123 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2431 11:05:02.358277 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2432 11:05:02.362230 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2433 11:05:02.364913 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2434 11:05:02.372253 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2435 11:05:02.374981 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2436 11:05:02.378308 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2437 11:05:02.382151 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2438 11:05:02.386566 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2439 11:05:02.391522 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2440 11:05:02.395443 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2441 11:05:02.399309 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2442 11:05:02.401669 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2443 11:05:02.405051 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2444 11:05:02.411743 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2445 11:05:02.414902 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2446 11:05:02.414990 ==
2447 11:05:02.418462 Dram Type= 6, Freq= 0, CH_0, rank 0
2448 11:05:02.421874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2449 11:05:02.421959 ==
2450 11:05:02.425040 DQS Delay:
2451 11:05:02.425122 DQS0 = 0, DQS1 = 0
2452 11:05:02.425185 DQM Delay:
2453 11:05:02.428230 DQM0 = 115, DQM1 = 106
2454 11:05:02.428313 DQ Delay:
2455 11:05:02.431835 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2456 11:05:02.434949 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2457 11:05:02.438628 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2458 11:05:02.442473 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =119
2459 11:05:02.444896
2460 11:05:02.444977
2461 11:05:02.445040 ==
2462 11:05:02.448857 Dram Type= 6, Freq= 0, CH_0, rank 0
2463 11:05:02.452261 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2464 11:05:02.452346 ==
2465 11:05:02.452410
2466 11:05:02.452468
2467 11:05:02.455665 TX Vref Scan disable
2468 11:05:02.455745 == TX Byte 0 ==
2469 11:05:02.461580 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2470 11:05:02.465564 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2471 11:05:02.465645 == TX Byte 1 ==
2472 11:05:02.472073 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2473 11:05:02.475231 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2474 11:05:02.475312 ==
2475 11:05:02.478136 Dram Type= 6, Freq= 0, CH_0, rank 0
2476 11:05:02.481818 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2477 11:05:02.481898 ==
2478 11:05:02.494325 TX Vref=22, minBit 1, minWin=25, winSum=413
2479 11:05:02.497445 TX Vref=24, minBit 8, minWin=25, winSum=420
2480 11:05:02.501223 TX Vref=26, minBit 8, minWin=25, winSum=425
2481 11:05:02.504274 TX Vref=28, minBit 8, minWin=26, winSum=434
2482 11:05:02.507713 TX Vref=30, minBit 8, minWin=26, winSum=435
2483 11:05:02.510865 TX Vref=32, minBit 8, minWin=26, winSum=432
2484 11:05:02.517680 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 30
2485 11:05:02.517775
2486 11:05:02.521119 Final TX Range 1 Vref 30
2487 11:05:02.521199
2488 11:05:02.521263 ==
2489 11:05:02.524343 Dram Type= 6, Freq= 0, CH_0, rank 0
2490 11:05:02.527478 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2491 11:05:02.527560 ==
2492 11:05:02.527623
2493 11:05:02.530790
2494 11:05:02.530870 TX Vref Scan disable
2495 11:05:02.534255 == TX Byte 0 ==
2496 11:05:02.538396 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2497 11:05:02.541068 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2498 11:05:02.544339 == TX Byte 1 ==
2499 11:05:02.547375 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2500 11:05:02.550956 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2501 11:05:02.551038
2502 11:05:02.554510 [DATLAT]
2503 11:05:02.554590 Freq=1200, CH0 RK0
2504 11:05:02.554654
2505 11:05:02.558238 DATLAT Default: 0xd
2506 11:05:02.558320 0, 0xFFFF, sum = 0
2507 11:05:02.560691 1, 0xFFFF, sum = 0
2508 11:05:02.560779 2, 0xFFFF, sum = 0
2509 11:05:02.564478 3, 0xFFFF, sum = 0
2510 11:05:02.564559 4, 0xFFFF, sum = 0
2511 11:05:02.567686 5, 0xFFFF, sum = 0
2512 11:05:02.571475 6, 0xFFFF, sum = 0
2513 11:05:02.571556 7, 0xFFFF, sum = 0
2514 11:05:02.574193 8, 0xFFFF, sum = 0
2515 11:05:02.574275 9, 0xFFFF, sum = 0
2516 11:05:02.577575 10, 0xFFFF, sum = 0
2517 11:05:02.577657 11, 0x0, sum = 1
2518 11:05:02.581704 12, 0x0, sum = 2
2519 11:05:02.581786 13, 0x0, sum = 3
2520 11:05:02.581851 14, 0x0, sum = 4
2521 11:05:02.585172 best_step = 12
2522 11:05:02.585252
2523 11:05:02.585315 ==
2524 11:05:02.587105 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 11:05:02.590479 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2526 11:05:02.590560 ==
2527 11:05:02.595015 RX Vref Scan: 1
2528 11:05:02.595097
2529 11:05:02.597491 Set Vref Range= 32 -> 127
2530 11:05:02.597571
2531 11:05:02.597634 RX Vref 32 -> 127, step: 1
2532 11:05:02.597692
2533 11:05:02.601268 RX Delay -21 -> 252, step: 4
2534 11:05:02.601348
2535 11:05:02.604087 Set Vref, RX VrefLevel [Byte0]: 32
2536 11:05:02.607283 [Byte1]: 32
2537 11:05:02.610999
2538 11:05:02.611083 Set Vref, RX VrefLevel [Byte0]: 33
2539 11:05:02.613767 [Byte1]: 33
2540 11:05:02.618853
2541 11:05:02.618965 Set Vref, RX VrefLevel [Byte0]: 34
2542 11:05:02.622031 [Byte1]: 34
2543 11:05:02.626681
2544 11:05:02.626786 Set Vref, RX VrefLevel [Byte0]: 35
2545 11:05:02.629830 [Byte1]: 35
2546 11:05:02.634893
2547 11:05:02.634999 Set Vref, RX VrefLevel [Byte0]: 36
2548 11:05:02.638284 [Byte1]: 36
2549 11:05:02.642753
2550 11:05:02.642856 Set Vref, RX VrefLevel [Byte0]: 37
2551 11:05:02.645742 [Byte1]: 37
2552 11:05:02.650655
2553 11:05:02.650757 Set Vref, RX VrefLevel [Byte0]: 38
2554 11:05:02.653666 [Byte1]: 38
2555 11:05:02.660045
2556 11:05:02.660150 Set Vref, RX VrefLevel [Byte0]: 39
2557 11:05:02.662000 [Byte1]: 39
2558 11:05:02.666625
2559 11:05:02.666728 Set Vref, RX VrefLevel [Byte0]: 40
2560 11:05:02.669198 [Byte1]: 40
2561 11:05:02.675183
2562 11:05:02.675289 Set Vref, RX VrefLevel [Byte0]: 41
2563 11:05:02.677605 [Byte1]: 41
2564 11:05:02.682017
2565 11:05:02.682117 Set Vref, RX VrefLevel [Byte0]: 42
2566 11:05:02.685720 [Byte1]: 42
2567 11:05:02.690975
2568 11:05:02.691078 Set Vref, RX VrefLevel [Byte0]: 43
2569 11:05:02.693337 [Byte1]: 43
2570 11:05:02.697893
2571 11:05:02.697993 Set Vref, RX VrefLevel [Byte0]: 44
2572 11:05:02.701138 [Byte1]: 44
2573 11:05:02.705445
2574 11:05:02.705545 Set Vref, RX VrefLevel [Byte0]: 45
2575 11:05:02.709631 [Byte1]: 45
2576 11:05:02.713794
2577 11:05:02.713895 Set Vref, RX VrefLevel [Byte0]: 46
2578 11:05:02.717038 [Byte1]: 46
2579 11:05:02.721917
2580 11:05:02.721998 Set Vref, RX VrefLevel [Byte0]: 47
2581 11:05:02.724677 [Byte1]: 47
2582 11:05:02.729726
2583 11:05:02.729805 Set Vref, RX VrefLevel [Byte0]: 48
2584 11:05:02.732668 [Byte1]: 48
2585 11:05:02.738222
2586 11:05:02.738301 Set Vref, RX VrefLevel [Byte0]: 49
2587 11:05:02.741039 [Byte1]: 49
2588 11:05:02.746202
2589 11:05:02.746282 Set Vref, RX VrefLevel [Byte0]: 50
2590 11:05:02.748529 [Byte1]: 50
2591 11:05:02.753540
2592 11:05:02.753620 Set Vref, RX VrefLevel [Byte0]: 51
2593 11:05:02.757343 [Byte1]: 51
2594 11:05:02.761150
2595 11:05:02.761230 Set Vref, RX VrefLevel [Byte0]: 52
2596 11:05:02.764849 [Byte1]: 52
2597 11:05:02.770585
2598 11:05:02.770687 Set Vref, RX VrefLevel [Byte0]: 53
2599 11:05:02.774549 [Byte1]: 53
2600 11:05:02.778253
2601 11:05:02.778355 Set Vref, RX VrefLevel [Byte0]: 54
2602 11:05:02.780324 [Byte1]: 54
2603 11:05:02.785090
2604 11:05:02.785192 Set Vref, RX VrefLevel [Byte0]: 55
2605 11:05:02.788159 [Byte1]: 55
2606 11:05:02.793007
2607 11:05:02.793106 Set Vref, RX VrefLevel [Byte0]: 56
2608 11:05:02.796596 [Byte1]: 56
2609 11:05:02.800654
2610 11:05:02.800792 Set Vref, RX VrefLevel [Byte0]: 57
2611 11:05:02.805061 [Byte1]: 57
2612 11:05:02.808696
2613 11:05:02.808850 Set Vref, RX VrefLevel [Byte0]: 58
2614 11:05:02.812351 [Byte1]: 58
2615 11:05:02.817607
2616 11:05:02.817713 Set Vref, RX VrefLevel [Byte0]: 59
2617 11:05:02.820268 [Byte1]: 59
2618 11:05:02.824624
2619 11:05:02.824771 Set Vref, RX VrefLevel [Byte0]: 60
2620 11:05:02.827761 [Byte1]: 60
2621 11:05:02.832938
2622 11:05:02.833040 Set Vref, RX VrefLevel [Byte0]: 61
2623 11:05:02.835674 [Byte1]: 61
2624 11:05:02.840345
2625 11:05:02.840446 Set Vref, RX VrefLevel [Byte0]: 62
2626 11:05:02.843933 [Byte1]: 62
2627 11:05:02.848498
2628 11:05:02.848600 Set Vref, RX VrefLevel [Byte0]: 63
2629 11:05:02.852034 [Byte1]: 63
2630 11:05:02.856953
2631 11:05:02.857055 Set Vref, RX VrefLevel [Byte0]: 64
2632 11:05:02.859324 [Byte1]: 64
2633 11:05:02.863979
2634 11:05:02.864080 Set Vref, RX VrefLevel [Byte0]: 65
2635 11:05:02.868222 [Byte1]: 65
2636 11:05:02.872776
2637 11:05:02.872878 Set Vref, RX VrefLevel [Byte0]: 66
2638 11:05:02.876345 [Byte1]: 66
2639 11:05:02.880009
2640 11:05:02.880111 Set Vref, RX VrefLevel [Byte0]: 67
2641 11:05:02.883282 [Byte1]: 67
2642 11:05:02.888013
2643 11:05:02.888114 Final RX Vref Byte 0 = 46 to rank0
2644 11:05:02.893118 Final RX Vref Byte 1 = 47 to rank0
2645 11:05:02.895765 Final RX Vref Byte 0 = 46 to rank1
2646 11:05:02.898251 Final RX Vref Byte 1 = 47 to rank1==
2647 11:05:02.901207 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 11:05:02.907562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2649 11:05:02.907669 ==
2650 11:05:02.907761 DQS Delay:
2651 11:05:02.907850 DQS0 = 0, DQS1 = 0
2652 11:05:02.911868 DQM Delay:
2653 11:05:02.911972 DQM0 = 114, DQM1 = 105
2654 11:05:02.914523 DQ Delay:
2655 11:05:02.917699 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2656 11:05:02.921375 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2657 11:05:02.924929 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2658 11:05:02.928209 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2659 11:05:02.928310
2660 11:05:02.928397
2661 11:05:02.934552 [DQSOSCAuto] RK0, (LSB)MR18= 0x505, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
2662 11:05:02.937756 CH0 RK0: MR19=404, MR18=505
2663 11:05:02.944725 CH0_RK0: MR19=0x404, MR18=0x505, DQSOSC=408, MR23=63, INC=39, DEC=26
2664 11:05:02.944829
2665 11:05:02.947592 ----->DramcWriteLeveling(PI) begin...
2666 11:05:02.947691 ==
2667 11:05:02.950871 Dram Type= 6, Freq= 0, CH_0, rank 1
2668 11:05:02.954583 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2669 11:05:02.954684 ==
2670 11:05:02.957849 Write leveling (Byte 0): 27 => 27
2671 11:05:02.960626 Write leveling (Byte 1): 24 => 24
2672 11:05:02.964330 DramcWriteLeveling(PI) end<-----
2673 11:05:02.964435
2674 11:05:02.964526 ==
2675 11:05:02.967508 Dram Type= 6, Freq= 0, CH_0, rank 1
2676 11:05:02.974304 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2677 11:05:02.974411 ==
2678 11:05:02.974503 [Gating] SW mode calibration
2679 11:05:02.984444 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2680 11:05:02.987998 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2681 11:05:02.990800 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2682 11:05:02.997543 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2683 11:05:03.000467 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2684 11:05:03.005143 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2685 11:05:03.012926 0 11 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2686 11:05:03.016010 0 11 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (1 0)
2687 11:05:03.019432 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2688 11:05:03.023969 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2689 11:05:03.027276 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2690 11:05:03.031510 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2691 11:05:03.037819 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2692 11:05:03.041160 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2693 11:05:03.044150 0 12 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2694 11:05:03.051079 0 12 20 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2695 11:05:03.053742 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2696 11:05:03.057261 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2697 11:05:03.064090 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2698 11:05:03.067291 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2699 11:05:03.070434 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2700 11:05:03.077058 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2701 11:05:03.080932 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2702 11:05:03.084102 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2703 11:05:03.090695 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2704 11:05:03.094083 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2705 11:05:03.097687 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2706 11:05:03.103810 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2707 11:05:03.109629 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2708 11:05:03.111139 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2709 11:05:03.116866 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2710 11:05:03.120903 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2711 11:05:03.123760 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2712 11:05:03.130907 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 11:05:03.134193 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 11:05:03.137192 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 11:05:03.140437 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 11:05:03.146897 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 11:05:03.150127 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2718 11:05:03.153815 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2719 11:05:03.160230 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2720 11:05:03.164087 Total UI for P1: 0, mck2ui 16
2721 11:05:03.166830 best dqsien dly found for B0: ( 0, 15, 18)
2722 11:05:03.166935 Total UI for P1: 0, mck2ui 16
2723 11:05:03.174972 best dqsien dly found for B1: ( 0, 15, 18)
2724 11:05:03.177135 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2725 11:05:03.180218 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2726 11:05:03.180323
2727 11:05:03.183322 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2728 11:05:03.187177 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2729 11:05:03.190184 [Gating] SW calibration Done
2730 11:05:03.190291 ==
2731 11:05:03.193596 Dram Type= 6, Freq= 0, CH_0, rank 1
2732 11:05:03.197273 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2733 11:05:03.197381 ==
2734 11:05:03.200485 RX Vref Scan: 0
2735 11:05:03.200589
2736 11:05:03.200681 RX Vref 0 -> 0, step: 1
2737 11:05:03.204348
2738 11:05:03.204452 RX Delay -40 -> 252, step: 8
2739 11:05:03.210179 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2740 11:05:03.213563 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2741 11:05:03.216639 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2742 11:05:03.220133 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2743 11:05:03.225076 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2744 11:05:03.228503 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2745 11:05:03.233937 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2746 11:05:03.237067 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2747 11:05:03.240678 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2748 11:05:03.243883 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2749 11:05:03.247155 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2750 11:05:03.253633 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2751 11:05:03.257060 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2752 11:05:03.260630 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2753 11:05:03.264415 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2754 11:05:03.267113 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2755 11:05:03.267221 ==
2756 11:05:03.270556 Dram Type= 6, Freq= 0, CH_0, rank 1
2757 11:05:03.277306 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2758 11:05:03.277417 ==
2759 11:05:03.277513 DQS Delay:
2760 11:05:03.280227 DQS0 = 0, DQS1 = 0
2761 11:05:03.280330 DQM Delay:
2762 11:05:03.283472 DQM0 = 114, DQM1 = 106
2763 11:05:03.283577 DQ Delay:
2764 11:05:03.287707 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2765 11:05:03.290539 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2766 11:05:03.293832 DQ8 =91, DQ9 =91, DQ10 =111, DQ11 =99
2767 11:05:03.296814 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2768 11:05:03.296919
2769 11:05:03.297010
2770 11:05:03.297106 ==
2771 11:05:03.299991 Dram Type= 6, Freq= 0, CH_0, rank 1
2772 11:05:03.303791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2773 11:05:03.307233 ==
2774 11:05:03.307338
2775 11:05:03.307430
2776 11:05:03.307519 TX Vref Scan disable
2777 11:05:03.310368 == TX Byte 0 ==
2778 11:05:03.313995 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2779 11:05:03.317114 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2780 11:05:03.320274 == TX Byte 1 ==
2781 11:05:03.323855 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2782 11:05:03.326645 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2783 11:05:03.331946 ==
2784 11:05:03.333598 Dram Type= 6, Freq= 0, CH_0, rank 1
2785 11:05:03.337160 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2786 11:05:03.337266 ==
2787 11:05:03.348242 TX Vref=22, minBit 8, minWin=25, winSum=421
2788 11:05:03.351243 TX Vref=24, minBit 8, minWin=25, winSum=422
2789 11:05:03.354945 TX Vref=26, minBit 8, minWin=25, winSum=425
2790 11:05:03.358317 TX Vref=28, minBit 1, minWin=26, winSum=429
2791 11:05:03.362117 TX Vref=30, minBit 8, minWin=25, winSum=433
2792 11:05:03.364998 TX Vref=32, minBit 8, minWin=26, winSum=434
2793 11:05:03.371164 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 32
2794 11:05:03.371267
2795 11:05:03.374611 Final TX Range 1 Vref 32
2796 11:05:03.374714
2797 11:05:03.374804 ==
2798 11:05:03.378315 Dram Type= 6, Freq= 0, CH_0, rank 1
2799 11:05:03.381458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2800 11:05:03.381563 ==
2801 11:05:03.381659
2802 11:05:03.384733
2803 11:05:03.384850 TX Vref Scan disable
2804 11:05:03.388206 == TX Byte 0 ==
2805 11:05:03.391573 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2806 11:05:03.394620 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2807 11:05:03.398011 == TX Byte 1 ==
2808 11:05:03.401203 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2809 11:05:03.404981 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2810 11:05:03.405086
2811 11:05:03.409246 [DATLAT]
2812 11:05:03.409350 Freq=1200, CH0 RK1
2813 11:05:03.409442
2814 11:05:03.411081 DATLAT Default: 0xc
2815 11:05:03.411184 0, 0xFFFF, sum = 0
2816 11:05:03.414313 1, 0xFFFF, sum = 0
2817 11:05:03.414418 2, 0xFFFF, sum = 0
2818 11:05:03.417971 3, 0xFFFF, sum = 0
2819 11:05:03.418086 4, 0xFFFF, sum = 0
2820 11:05:03.421302 5, 0xFFFF, sum = 0
2821 11:05:03.421407 6, 0xFFFF, sum = 0
2822 11:05:03.424292 7, 0xFFFF, sum = 0
2823 11:05:03.427762 8, 0xFFFF, sum = 0
2824 11:05:03.427867 9, 0xFFFF, sum = 0
2825 11:05:03.431473 10, 0xFFFF, sum = 0
2826 11:05:03.431579 11, 0x0, sum = 1
2827 11:05:03.436613 12, 0x0, sum = 2
2828 11:05:03.436753 13, 0x0, sum = 3
2829 11:05:03.436848 14, 0x0, sum = 4
2830 11:05:03.438012 best_step = 12
2831 11:05:03.438112
2832 11:05:03.438201 ==
2833 11:05:03.441550 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 11:05:03.445951 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2835 11:05:03.446057 ==
2836 11:05:03.449006 RX Vref Scan: 0
2837 11:05:03.449108
2838 11:05:03.449198 RX Vref 0 -> 0, step: 1
2839 11:05:03.451491
2840 11:05:03.451591 RX Delay -21 -> 252, step: 4
2841 11:05:03.458408 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2842 11:05:03.461798 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2843 11:05:03.465149 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2844 11:05:03.468615 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2845 11:05:03.471766 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2846 11:05:03.477924 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2847 11:05:03.481272 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2848 11:05:03.485537 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
2849 11:05:03.488449 iDelay=195, Bit 8, Center 92 (31 ~ 154) 124
2850 11:05:03.491305 iDelay=195, Bit 9, Center 88 (27 ~ 150) 124
2851 11:05:03.498356 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2852 11:05:03.501438 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2853 11:05:03.504816 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2854 11:05:03.507850 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2855 11:05:03.511604 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
2856 11:05:03.518368 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2857 11:05:03.518491 ==
2858 11:05:03.521541 Dram Type= 6, Freq= 0, CH_0, rank 1
2859 11:05:03.525481 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2860 11:05:03.525587 ==
2861 11:05:03.525679 DQS Delay:
2862 11:05:03.527944 DQS0 = 0, DQS1 = 0
2863 11:05:03.528061 DQM Delay:
2864 11:05:03.531508 DQM0 = 115, DQM1 = 105
2865 11:05:03.531613 DQ Delay:
2866 11:05:03.534731 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2867 11:05:03.538729 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =124
2868 11:05:03.542139 DQ8 =92, DQ9 =88, DQ10 =110, DQ11 =96
2869 11:05:03.545249 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2870 11:05:03.545353
2871 11:05:03.545443
2872 11:05:03.555950 [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2873 11:05:03.558763 CH0 RK1: MR19=404, MR18=B0B
2874 11:05:03.561188 CH0_RK1: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
2875 11:05:03.564995 [RxdqsGatingPostProcess] freq 1200
2876 11:05:03.572137 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2877 11:05:03.574729 Pre-setting of DQS Precalculation
2878 11:05:03.578690 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2879 11:05:03.578795 ==
2880 11:05:03.581706 Dram Type= 6, Freq= 0, CH_1, rank 0
2881 11:05:03.587975 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2882 11:05:03.588082 ==
2883 11:05:03.591032 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2884 11:05:03.597602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2885 11:05:03.606466 [CA 0] Center 37 (7~68) winsize 62
2886 11:05:03.610785 [CA 1] Center 37 (6~68) winsize 63
2887 11:05:03.613217 [CA 2] Center 34 (4~65) winsize 62
2888 11:05:03.616270 [CA 3] Center 33 (3~64) winsize 62
2889 11:05:03.619744 [CA 4] Center 32 (2~63) winsize 62
2890 11:05:03.623156 [CA 5] Center 32 (2~63) winsize 62
2891 11:05:03.623259
2892 11:05:03.626695 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2893 11:05:03.626801
2894 11:05:03.629744 [CATrainingPosCal] consider 1 rank data
2895 11:05:03.633309 u2DelayCellTimex100 = 270/100 ps
2896 11:05:03.636927 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2897 11:05:03.639908 CA1 delay=37 (6~68),Diff = 5 PI (24 cell)
2898 11:05:03.646236 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2899 11:05:03.651918 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2900 11:05:03.654002 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2901 11:05:03.656816 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2902 11:05:03.656920
2903 11:05:03.660117 CA PerBit enable=1, Macro0, CA PI delay=32
2904 11:05:03.660219
2905 11:05:03.663287 [CBTSetCACLKResult] CA Dly = 32
2906 11:05:03.663389 CS Dly: 6 (0~37)
2907 11:05:03.666282 ==
2908 11:05:03.666386 Dram Type= 6, Freq= 0, CH_1, rank 1
2909 11:05:03.672942 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2910 11:05:03.673047 ==
2911 11:05:03.676631 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2912 11:05:03.683586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2913 11:05:03.691960 [CA 0] Center 37 (7~68) winsize 62
2914 11:05:03.695029 [CA 1] Center 37 (7~68) winsize 62
2915 11:05:03.698572 [CA 2] Center 34 (3~65) winsize 63
2916 11:05:03.702144 [CA 3] Center 33 (3~64) winsize 62
2917 11:05:03.705010 [CA 4] Center 32 (2~63) winsize 62
2918 11:05:03.708376 [CA 5] Center 32 (2~63) winsize 62
2919 11:05:03.708482
2920 11:05:03.712281 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2921 11:05:03.712388
2922 11:05:03.715815 [CATrainingPosCal] consider 2 rank data
2923 11:05:03.718301 u2DelayCellTimex100 = 270/100 ps
2924 11:05:03.721668 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2925 11:05:03.725589 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2926 11:05:03.731684 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2927 11:05:03.735040 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2928 11:05:03.738043 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2929 11:05:03.741617 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2930 11:05:03.741726
2931 11:05:03.744795 CA PerBit enable=1, Macro0, CA PI delay=32
2932 11:05:03.744902
2933 11:05:03.748154 [CBTSetCACLKResult] CA Dly = 32
2934 11:05:03.748260 CS Dly: 6 (0~38)
2935 11:05:03.748353
2936 11:05:03.751542 ----->DramcWriteLeveling(PI) begin...
2937 11:05:03.754769 ==
2938 11:05:03.758275 Dram Type= 6, Freq= 0, CH_1, rank 0
2939 11:05:03.762293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2940 11:05:03.762399 ==
2941 11:05:03.764879 Write leveling (Byte 0): 20 => 20
2942 11:05:03.768950 Write leveling (Byte 1): 23 => 23
2943 11:05:03.771377 DramcWriteLeveling(PI) end<-----
2944 11:05:03.771482
2945 11:05:03.771573 ==
2946 11:05:03.774708 Dram Type= 6, Freq= 0, CH_1, rank 0
2947 11:05:03.779205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2948 11:05:03.779311 ==
2949 11:05:03.781876 [Gating] SW mode calibration
2950 11:05:03.788157 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2951 11:05:03.792007 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2952 11:05:03.798665 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2953 11:05:03.801741 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2954 11:05:03.804971 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2955 11:05:03.811537 0 11 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2956 11:05:03.814608 0 11 16 | B1->B0 | 3232 2c2c | 0 0 | (0 0) (1 0)
2957 11:05:03.818086 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2958 11:05:03.824755 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2959 11:05:03.828093 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2960 11:05:03.831348 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2961 11:05:03.838163 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 11:05:03.841868 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2963 11:05:03.844454 0 12 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
2964 11:05:03.851637 0 12 16 | B1->B0 | 2d2d 3f3f | 0 0 | (0 0) (0 0)
2965 11:05:03.854775 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 11:05:03.857803 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 11:05:03.864490 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 11:05:03.867817 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 11:05:03.870995 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 11:05:03.877829 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 11:05:03.881581 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 11:05:03.886101 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2973 11:05:03.891535 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2974 11:05:03.894957 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 11:05:03.898285 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 11:05:03.904206 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 11:05:03.908034 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 11:05:03.911249 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 11:05:03.917821 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 11:05:03.921234 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 11:05:03.924618 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 11:05:03.931359 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 11:05:03.934645 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 11:05:03.937490 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 11:05:03.944136 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 11:05:03.947692 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 11:05:03.951172 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 11:05:03.957384 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2989 11:05:03.960456 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2990 11:05:03.964085 Total UI for P1: 0, mck2ui 16
2991 11:05:03.967380 best dqsien dly found for B0: ( 0, 15, 16)
2992 11:05:03.970868 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2993 11:05:03.973863 Total UI for P1: 0, mck2ui 16
2994 11:05:03.977249 best dqsien dly found for B1: ( 0, 15, 20)
2995 11:05:03.980645 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2996 11:05:03.984410 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2997 11:05:03.984519
2998 11:05:03.987220 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2999 11:05:03.993994 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3000 11:05:03.994107 [Gating] SW calibration Done
3001 11:05:03.994200 ==
3002 11:05:03.997631 Dram Type= 6, Freq= 0, CH_1, rank 0
3003 11:05:04.004380 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3004 11:05:04.004493 ==
3005 11:05:04.004588 RX Vref Scan: 0
3006 11:05:04.004679
3007 11:05:04.007384 RX Vref 0 -> 0, step: 1
3008 11:05:04.007487
3009 11:05:04.010984 RX Delay -40 -> 252, step: 8
3010 11:05:04.013990 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3011 11:05:04.017135 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3012 11:05:04.020599 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3013 11:05:04.027695 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3014 11:05:04.030515 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3015 11:05:04.034768 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3016 11:05:04.037046 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3017 11:05:04.040643 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3018 11:05:04.046986 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3019 11:05:04.050624 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3020 11:05:04.054163 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3021 11:05:04.057225 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3022 11:05:04.060628 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3023 11:05:04.067254 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3024 11:05:04.070860 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3025 11:05:04.073827 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3026 11:05:04.073909 ==
3027 11:05:04.077032 Dram Type= 6, Freq= 0, CH_1, rank 0
3028 11:05:04.080598 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3029 11:05:04.080717 ==
3030 11:05:04.083506 DQS Delay:
3031 11:05:04.083587 DQS0 = 0, DQS1 = 0
3032 11:05:04.086974 DQM Delay:
3033 11:05:04.087057 DQM0 = 116, DQM1 = 108
3034 11:05:04.087121 DQ Delay:
3035 11:05:04.090476 DQ0 =123, DQ1 =107, DQ2 =107, DQ3 =115
3036 11:05:04.096680 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3037 11:05:04.100318 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3038 11:05:04.103425 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3039 11:05:04.103510
3040 11:05:04.103574
3041 11:05:04.103633 ==
3042 11:05:04.106807 Dram Type= 6, Freq= 0, CH_1, rank 0
3043 11:05:04.110676 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3044 11:05:04.110763 ==
3045 11:05:04.110828
3046 11:05:04.110887
3047 11:05:04.113576 TX Vref Scan disable
3048 11:05:04.113658 == TX Byte 0 ==
3049 11:05:04.120135 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3050 11:05:04.123536 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3051 11:05:04.123655 == TX Byte 1 ==
3052 11:05:04.130345 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3053 11:05:04.133316 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3054 11:05:04.133435 ==
3055 11:05:04.136843 Dram Type= 6, Freq= 0, CH_1, rank 0
3056 11:05:04.140643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3057 11:05:04.140765 ==
3058 11:05:04.152996 TX Vref=22, minBit 1, minWin=25, winSum=407
3059 11:05:04.156404 TX Vref=24, minBit 0, minWin=25, winSum=415
3060 11:05:04.159804 TX Vref=26, minBit 0, minWin=26, winSum=420
3061 11:05:04.163496 TX Vref=28, minBit 15, minWin=25, winSum=429
3062 11:05:04.167285 TX Vref=30, minBit 8, minWin=26, winSum=429
3063 11:05:04.173582 TX Vref=32, minBit 1, minWin=26, winSum=426
3064 11:05:04.176245 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 30
3065 11:05:04.176358
3066 11:05:04.180403 Final TX Range 1 Vref 30
3067 11:05:04.180511
3068 11:05:04.180603 ==
3069 11:05:04.183136 Dram Type= 6, Freq= 0, CH_1, rank 0
3070 11:05:04.186240 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3071 11:05:04.186350 ==
3072 11:05:04.189968
3073 11:05:04.190077
3074 11:05:04.190170 TX Vref Scan disable
3075 11:05:04.193049 == TX Byte 0 ==
3076 11:05:04.196146 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3077 11:05:04.199754 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3078 11:05:04.203222 == TX Byte 1 ==
3079 11:05:04.206406 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3080 11:05:04.209753 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3081 11:05:04.212649
3082 11:05:04.212795 [DATLAT]
3083 11:05:04.212886 Freq=1200, CH1 RK0
3084 11:05:04.212975
3085 11:05:04.216137 DATLAT Default: 0xd
3086 11:05:04.216239 0, 0xFFFF, sum = 0
3087 11:05:04.219386 1, 0xFFFF, sum = 0
3088 11:05:04.219497 2, 0xFFFF, sum = 0
3089 11:05:04.222901 3, 0xFFFF, sum = 0
3090 11:05:04.223006 4, 0xFFFF, sum = 0
3091 11:05:04.226694 5, 0xFFFF, sum = 0
3092 11:05:04.229806 6, 0xFFFF, sum = 0
3093 11:05:04.229913 7, 0xFFFF, sum = 0
3094 11:05:04.232934 8, 0xFFFF, sum = 0
3095 11:05:04.233039 9, 0xFFFF, sum = 0
3096 11:05:04.236444 10, 0xFFFF, sum = 0
3097 11:05:04.236548 11, 0x0, sum = 1
3098 11:05:04.241422 12, 0x0, sum = 2
3099 11:05:04.241528 13, 0x0, sum = 3
3100 11:05:04.241621 14, 0x0, sum = 4
3101 11:05:04.243544 best_step = 12
3102 11:05:04.243646
3103 11:05:04.243737 ==
3104 11:05:04.248026 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 11:05:04.250548 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3106 11:05:04.250653 ==
3107 11:05:04.253244 RX Vref Scan: 1
3108 11:05:04.253350
3109 11:05:04.256166 Set Vref Range= 32 -> 127
3110 11:05:04.256272
3111 11:05:04.256364 RX Vref 32 -> 127, step: 1
3112 11:05:04.256453
3113 11:05:04.259483 RX Delay -29 -> 252, step: 4
3114 11:05:04.259590
3115 11:05:04.262771 Set Vref, RX VrefLevel [Byte0]: 32
3116 11:05:04.267248 [Byte1]: 32
3117 11:05:04.270283
3118 11:05:04.270389 Set Vref, RX VrefLevel [Byte0]: 33
3119 11:05:04.273228 [Byte1]: 33
3120 11:05:04.277610
3121 11:05:04.277717 Set Vref, RX VrefLevel [Byte0]: 34
3122 11:05:04.281619 [Byte1]: 34
3123 11:05:04.285575
3124 11:05:04.285681 Set Vref, RX VrefLevel [Byte0]: 35
3125 11:05:04.288622 [Byte1]: 35
3126 11:05:04.293254
3127 11:05:04.293361 Set Vref, RX VrefLevel [Byte0]: 36
3128 11:05:04.296567 [Byte1]: 36
3129 11:05:04.301307
3130 11:05:04.301414 Set Vref, RX VrefLevel [Byte0]: 37
3131 11:05:04.304824 [Byte1]: 37
3132 11:05:04.309438
3133 11:05:04.309545 Set Vref, RX VrefLevel [Byte0]: 38
3134 11:05:04.312663 [Byte1]: 38
3135 11:05:04.317496
3136 11:05:04.317601 Set Vref, RX VrefLevel [Byte0]: 39
3137 11:05:04.320884 [Byte1]: 39
3138 11:05:04.325224
3139 11:05:04.325304 Set Vref, RX VrefLevel [Byte0]: 40
3140 11:05:04.328711 [Byte1]: 40
3141 11:05:04.333576
3142 11:05:04.333657 Set Vref, RX VrefLevel [Byte0]: 41
3143 11:05:04.336616 [Byte1]: 41
3144 11:05:04.341121
3145 11:05:04.341202 Set Vref, RX VrefLevel [Byte0]: 42
3146 11:05:04.344964 [Byte1]: 42
3147 11:05:04.349981
3148 11:05:04.350062 Set Vref, RX VrefLevel [Byte0]: 43
3149 11:05:04.352656 [Byte1]: 43
3150 11:05:04.358203
3151 11:05:04.358284 Set Vref, RX VrefLevel [Byte0]: 44
3152 11:05:04.361630 [Byte1]: 44
3153 11:05:04.365497
3154 11:05:04.365606 Set Vref, RX VrefLevel [Byte0]: 45
3155 11:05:04.368659 [Byte1]: 45
3156 11:05:04.373576
3157 11:05:04.373681 Set Vref, RX VrefLevel [Byte0]: 46
3158 11:05:04.376357 [Byte1]: 46
3159 11:05:04.381216
3160 11:05:04.381323 Set Vref, RX VrefLevel [Byte0]: 47
3161 11:05:04.384646 [Byte1]: 47
3162 11:05:04.388659
3163 11:05:04.388773 Set Vref, RX VrefLevel [Byte0]: 48
3164 11:05:04.393026 [Byte1]: 48
3165 11:05:04.397405
3166 11:05:04.397519 Set Vref, RX VrefLevel [Byte0]: 49
3167 11:05:04.400167 [Byte1]: 49
3168 11:05:04.405719
3169 11:05:04.405828 Set Vref, RX VrefLevel [Byte0]: 50
3170 11:05:04.408102 [Byte1]: 50
3171 11:05:04.413459
3172 11:05:04.413571 Set Vref, RX VrefLevel [Byte0]: 51
3173 11:05:04.415981 [Byte1]: 51
3174 11:05:04.421038
3175 11:05:04.421167 Set Vref, RX VrefLevel [Byte0]: 52
3176 11:05:04.423726 [Byte1]: 52
3177 11:05:04.429408
3178 11:05:04.429530 Set Vref, RX VrefLevel [Byte0]: 53
3179 11:05:04.431761 [Byte1]: 53
3180 11:05:04.436828
3181 11:05:04.436939 Set Vref, RX VrefLevel [Byte0]: 54
3182 11:05:04.441129 [Byte1]: 54
3183 11:05:04.444383
3184 11:05:04.444493 Set Vref, RX VrefLevel [Byte0]: 55
3185 11:05:04.447859 [Byte1]: 55
3186 11:05:04.452514
3187 11:05:04.452621 Set Vref, RX VrefLevel [Byte0]: 56
3188 11:05:04.456292 [Byte1]: 56
3189 11:05:04.460513
3190 11:05:04.460622 Set Vref, RX VrefLevel [Byte0]: 57
3191 11:05:04.464959 [Byte1]: 57
3192 11:05:04.468187
3193 11:05:04.468293 Set Vref, RX VrefLevel [Byte0]: 58
3194 11:05:04.471664 [Byte1]: 58
3195 11:05:04.476225
3196 11:05:04.476331 Set Vref, RX VrefLevel [Byte0]: 59
3197 11:05:04.480620 [Byte1]: 59
3198 11:05:04.486494
3199 11:05:04.486604 Set Vref, RX VrefLevel [Byte0]: 60
3200 11:05:04.487722 [Byte1]: 60
3201 11:05:04.492082
3202 11:05:04.492188 Set Vref, RX VrefLevel [Byte0]: 61
3203 11:05:04.495441 [Byte1]: 61
3204 11:05:04.500123
3205 11:05:04.500230 Set Vref, RX VrefLevel [Byte0]: 62
3206 11:05:04.503877 [Byte1]: 62
3207 11:05:04.508855
3208 11:05:04.508963 Set Vref, RX VrefLevel [Byte0]: 63
3209 11:05:04.511444 [Byte1]: 63
3210 11:05:04.516435
3211 11:05:04.516541 Set Vref, RX VrefLevel [Byte0]: 64
3212 11:05:04.519282 [Byte1]: 64
3213 11:05:04.525053
3214 11:05:04.525165 Set Vref, RX VrefLevel [Byte0]: 65
3215 11:05:04.527928 [Byte1]: 65
3216 11:05:04.532501
3217 11:05:04.532608 Set Vref, RX VrefLevel [Byte0]: 66
3218 11:05:04.535322 [Byte1]: 66
3219 11:05:04.540027
3220 11:05:04.540133 Final RX Vref Byte 0 = 54 to rank0
3221 11:05:04.543692 Final RX Vref Byte 1 = 48 to rank0
3222 11:05:04.547040 Final RX Vref Byte 0 = 54 to rank1
3223 11:05:04.550396 Final RX Vref Byte 1 = 48 to rank1==
3224 11:05:04.554337 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 11:05:04.560530 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3226 11:05:04.560640 ==
3227 11:05:04.560741 DQS Delay:
3228 11:05:04.560833 DQS0 = 0, DQS1 = 0
3229 11:05:04.563449 DQM Delay:
3230 11:05:04.563552 DQM0 = 115, DQM1 = 105
3231 11:05:04.566767 DQ Delay:
3232 11:05:04.570783 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3233 11:05:04.573664 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3234 11:05:04.576448 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3235 11:05:04.579955 DQ12 =114, DQ13 =116, DQ14 =114, DQ15 =116
3236 11:05:04.580061
3237 11:05:04.580152
3238 11:05:04.587357 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3239 11:05:04.591072 CH1 RK0: MR19=404, MR18=1A1A
3240 11:05:04.597355 CH1_RK0: MR19=0x404, MR18=0x1A1A, DQSOSC=400, MR23=63, INC=40, DEC=27
3241 11:05:04.597459
3242 11:05:04.599723 ----->DramcWriteLeveling(PI) begin...
3243 11:05:04.599829 ==
3244 11:05:04.603552 Dram Type= 6, Freq= 0, CH_1, rank 1
3245 11:05:04.606912 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3246 11:05:04.610115 ==
3247 11:05:04.610286 Write leveling (Byte 0): 23 => 23
3248 11:05:04.612969 Write leveling (Byte 1): 21 => 21
3249 11:05:04.616399 DramcWriteLeveling(PI) end<-----
3250 11:05:04.616504
3251 11:05:04.616592 ==
3252 11:05:04.620066 Dram Type= 6, Freq= 0, CH_1, rank 1
3253 11:05:04.627007 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3254 11:05:04.627115 ==
3255 11:05:04.627207 [Gating] SW mode calibration
3256 11:05:04.636392 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3257 11:05:04.641519 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3258 11:05:04.646631 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3259 11:05:04.649800 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3260 11:05:04.653071 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3261 11:05:04.656626 0 11 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
3262 11:05:04.663822 0 11 16 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
3263 11:05:04.666855 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3264 11:05:04.670056 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3265 11:05:04.676538 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3266 11:05:04.679603 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3267 11:05:04.683125 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3268 11:05:04.690003 0 12 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3269 11:05:04.693130 0 12 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
3270 11:05:04.698232 0 12 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3271 11:05:04.703331 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3272 11:05:04.706579 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3273 11:05:04.710197 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3274 11:05:04.716639 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3275 11:05:04.719955 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3276 11:05:04.722920 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3277 11:05:04.729815 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3278 11:05:04.733050 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3279 11:05:04.736115 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3280 11:05:04.742769 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3281 11:05:04.746142 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3282 11:05:04.749766 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3283 11:05:04.756305 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3284 11:05:04.759733 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 11:05:04.762811 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 11:05:04.770007 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 11:05:04.773323 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 11:05:04.776480 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 11:05:04.779259 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 11:05:04.786432 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 11:05:04.789490 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 11:05:04.792607 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3293 11:05:04.799482 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3294 11:05:04.802698 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3295 11:05:04.806517 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3296 11:05:04.809916 Total UI for P1: 0, mck2ui 16
3297 11:05:04.813361 best dqsien dly found for B0: ( 0, 15, 12)
3298 11:05:04.816608 Total UI for P1: 0, mck2ui 16
3299 11:05:04.819521 best dqsien dly found for B1: ( 0, 15, 16)
3300 11:05:04.823130 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3301 11:05:04.826943 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3302 11:05:04.829088
3303 11:05:04.833483 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3304 11:05:04.835790 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3305 11:05:04.839259 [Gating] SW calibration Done
3306 11:05:04.839364 ==
3307 11:05:04.842638 Dram Type= 6, Freq= 0, CH_1, rank 1
3308 11:05:04.846126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3309 11:05:04.846233 ==
3310 11:05:04.846324 RX Vref Scan: 0
3311 11:05:04.846412
3312 11:05:04.849291 RX Vref 0 -> 0, step: 1
3313 11:05:04.849395
3314 11:05:04.853212 RX Delay -40 -> 252, step: 8
3315 11:05:04.855911 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3316 11:05:04.859089 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3317 11:05:04.866380 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3318 11:05:04.869421 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3319 11:05:04.873106 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3320 11:05:04.876124 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3321 11:05:04.879723 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3322 11:05:04.882981 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3323 11:05:04.889660 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3324 11:05:04.893211 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3325 11:05:04.896559 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3326 11:05:04.900208 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3327 11:05:04.902885 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3328 11:05:04.909169 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3329 11:05:04.913057 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3330 11:05:04.915902 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3331 11:05:04.916007 ==
3332 11:05:04.919259 Dram Type= 6, Freq= 0, CH_1, rank 1
3333 11:05:04.923133 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3334 11:05:04.927114 ==
3335 11:05:04.927220 DQS Delay:
3336 11:05:04.927311 DQS0 = 0, DQS1 = 0
3337 11:05:04.931580 DQM Delay:
3338 11:05:04.931685 DQM0 = 116, DQM1 = 105
3339 11:05:04.932619 DQ Delay:
3340 11:05:04.936470 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3341 11:05:04.939636 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3342 11:05:04.943377 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
3343 11:05:04.946158 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3344 11:05:04.946263
3345 11:05:04.946354
3346 11:05:04.946441 ==
3347 11:05:04.949664 Dram Type= 6, Freq= 0, CH_1, rank 1
3348 11:05:04.952730 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3349 11:05:04.952835 ==
3350 11:05:04.952927
3351 11:05:04.953014
3352 11:05:04.956930 TX Vref Scan disable
3353 11:05:04.958972 == TX Byte 0 ==
3354 11:05:04.962353 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3355 11:05:04.965822 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3356 11:05:04.969214 == TX Byte 1 ==
3357 11:05:04.973203 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3358 11:05:04.975583 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3359 11:05:04.975688 ==
3360 11:05:04.979007 Dram Type= 6, Freq= 0, CH_1, rank 1
3361 11:05:04.982601 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3362 11:05:04.986227 ==
3363 11:05:04.995992 TX Vref=22, minBit 3, minWin=25, winSum=418
3364 11:05:04.999184 TX Vref=24, minBit 7, minWin=25, winSum=420
3365 11:05:05.002500 TX Vref=26, minBit 9, minWin=25, winSum=423
3366 11:05:05.005852 TX Vref=28, minBit 3, minWin=26, winSum=431
3367 11:05:05.009277 TX Vref=30, minBit 0, minWin=26, winSum=434
3368 11:05:05.013120 TX Vref=32, minBit 0, minWin=26, winSum=431
3369 11:05:05.019186 [TxChooseVref] Worse bit 0, Min win 26, Win sum 434, Final Vref 30
3370 11:05:05.019300
3371 11:05:05.022844 Final TX Range 1 Vref 30
3372 11:05:05.022949
3373 11:05:05.023040 ==
3374 11:05:05.025604 Dram Type= 6, Freq= 0, CH_1, rank 1
3375 11:05:05.029941 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3376 11:05:05.030047 ==
3377 11:05:05.030138
3378 11:05:05.032273
3379 11:05:05.032376 TX Vref Scan disable
3380 11:05:05.035657 == TX Byte 0 ==
3381 11:05:05.039199 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3382 11:05:05.042717 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3383 11:05:05.047451 == TX Byte 1 ==
3384 11:05:05.050044 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3385 11:05:05.052597 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3386 11:05:05.056020
3387 11:05:05.056123 [DATLAT]
3388 11:05:05.056213 Freq=1200, CH1 RK1
3389 11:05:05.056301
3390 11:05:05.059106 DATLAT Default: 0xc
3391 11:05:05.059208 0, 0xFFFF, sum = 0
3392 11:05:05.062699 1, 0xFFFF, sum = 0
3393 11:05:05.062804 2, 0xFFFF, sum = 0
3394 11:05:05.065966 3, 0xFFFF, sum = 0
3395 11:05:05.066048 4, 0xFFFF, sum = 0
3396 11:05:05.069096 5, 0xFFFF, sum = 0
3397 11:05:05.072368 6, 0xFFFF, sum = 0
3398 11:05:05.072450 7, 0xFFFF, sum = 0
3399 11:05:05.075393 8, 0xFFFF, sum = 0
3400 11:05:05.075474 9, 0xFFFF, sum = 0
3401 11:05:05.078680 10, 0xFFFF, sum = 0
3402 11:05:05.078764 11, 0x0, sum = 1
3403 11:05:05.082261 12, 0x0, sum = 2
3404 11:05:05.082345 13, 0x0, sum = 3
3405 11:05:05.082411 14, 0x0, sum = 4
3406 11:05:05.086115 best_step = 12
3407 11:05:05.086196
3408 11:05:05.086260 ==
3409 11:05:05.088689 Dram Type= 6, Freq= 0, CH_1, rank 1
3410 11:05:05.092511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3411 11:05:05.092594 ==
3412 11:05:05.095686 RX Vref Scan: 0
3413 11:05:05.095767
3414 11:05:05.095831 RX Vref 0 -> 0, step: 1
3415 11:05:05.098717
3416 11:05:05.098799 RX Delay -29 -> 252, step: 4
3417 11:05:05.106098 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3418 11:05:05.109674 iDelay=199, Bit 1, Center 112 (43 ~ 182) 140
3419 11:05:05.112717 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3420 11:05:05.115931 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3421 11:05:05.119596 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3422 11:05:05.126919 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3423 11:05:05.128959 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3424 11:05:05.132477 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3425 11:05:05.136256 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3426 11:05:05.139048 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3427 11:05:05.145936 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3428 11:05:05.149486 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3429 11:05:05.152813 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3430 11:05:05.156748 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3431 11:05:05.159725 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3432 11:05:05.166222 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3433 11:05:05.166306 ==
3434 11:05:05.169892 Dram Type= 6, Freq= 0, CH_1, rank 1
3435 11:05:05.172949 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3436 11:05:05.173032 ==
3437 11:05:05.173097 DQS Delay:
3438 11:05:05.176837 DQS0 = 0, DQS1 = 0
3439 11:05:05.176919 DQM Delay:
3440 11:05:05.179461 DQM0 = 115, DQM1 = 103
3441 11:05:05.179543 DQ Delay:
3442 11:05:05.183393 DQ0 =116, DQ1 =112, DQ2 =108, DQ3 =112
3443 11:05:05.186747 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3444 11:05:05.189197 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3445 11:05:05.192699 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =112
3446 11:05:05.192834
3447 11:05:05.192900
3448 11:05:05.202695 [DQSOSCAuto] RK1, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3449 11:05:05.206152 CH1 RK1: MR19=404, MR18=C0C
3450 11:05:05.209049 CH1_RK1: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3451 11:05:05.212399 [RxdqsGatingPostProcess] freq 1200
3452 11:05:05.219248 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3453 11:05:05.222451 Pre-setting of DQS Precalculation
3454 11:05:05.225667 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3455 11:05:05.235929 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3456 11:05:05.242609 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3457 11:05:05.242693
3458 11:05:05.242758
3459 11:05:05.246125 [Calibration Summary] 2400 Mbps
3460 11:05:05.246207 CH 0, Rank 0
3461 11:05:05.249734 SW Impedance : PASS
3462 11:05:05.249816 DUTY Scan : NO K
3463 11:05:05.252772 ZQ Calibration : PASS
3464 11:05:05.256776 Jitter Meter : NO K
3465 11:05:05.256858 CBT Training : PASS
3466 11:05:05.258974 Write leveling : PASS
3467 11:05:05.262353 RX DQS gating : PASS
3468 11:05:05.262434 RX DQ/DQS(RDDQC) : PASS
3469 11:05:05.265895 TX DQ/DQS : PASS
3470 11:05:05.269176 RX DATLAT : PASS
3471 11:05:05.269257 RX DQ/DQS(Engine): PASS
3472 11:05:05.273370 TX OE : NO K
3473 11:05:05.273452 All Pass.
3474 11:05:05.273516
3475 11:05:05.276112 CH 0, Rank 1
3476 11:05:05.276192 SW Impedance : PASS
3477 11:05:05.279132 DUTY Scan : NO K
3478 11:05:05.279214 ZQ Calibration : PASS
3479 11:05:05.282271 Jitter Meter : NO K
3480 11:05:05.286597 CBT Training : PASS
3481 11:05:05.286678 Write leveling : PASS
3482 11:05:05.289201 RX DQS gating : PASS
3483 11:05:05.292693 RX DQ/DQS(RDDQC) : PASS
3484 11:05:05.292786 TX DQ/DQS : PASS
3485 11:05:05.295520 RX DATLAT : PASS
3486 11:05:05.299149 RX DQ/DQS(Engine): PASS
3487 11:05:05.299231 TX OE : NO K
3488 11:05:05.302773 All Pass.
3489 11:05:05.302855
3490 11:05:05.302920 CH 1, Rank 0
3491 11:05:05.306011 SW Impedance : PASS
3492 11:05:05.306093 DUTY Scan : NO K
3493 11:05:05.308903 ZQ Calibration : PASS
3494 11:05:05.312007 Jitter Meter : NO K
3495 11:05:05.312088 CBT Training : PASS
3496 11:05:05.315459 Write leveling : PASS
3497 11:05:05.319382 RX DQS gating : PASS
3498 11:05:05.319467 RX DQ/DQS(RDDQC) : PASS
3499 11:05:05.322386 TX DQ/DQS : PASS
3500 11:05:05.322470 RX DATLAT : PASS
3501 11:05:05.325699 RX DQ/DQS(Engine): PASS
3502 11:05:05.329231 TX OE : NO K
3503 11:05:05.329313 All Pass.
3504 11:05:05.329377
3505 11:05:05.329437 CH 1, Rank 1
3506 11:05:05.331867 SW Impedance : PASS
3507 11:05:05.335694 DUTY Scan : NO K
3508 11:05:05.335777 ZQ Calibration : PASS
3509 11:05:05.339871 Jitter Meter : NO K
3510 11:05:05.343186 CBT Training : PASS
3511 11:05:05.343268 Write leveling : PASS
3512 11:05:05.345757 RX DQS gating : PASS
3513 11:05:05.348860 RX DQ/DQS(RDDQC) : PASS
3514 11:05:05.348942 TX DQ/DQS : PASS
3515 11:05:05.351959 RX DATLAT : PASS
3516 11:05:05.356005 RX DQ/DQS(Engine): PASS
3517 11:05:05.356087 TX OE : NO K
3518 11:05:05.358717 All Pass.
3519 11:05:05.358798
3520 11:05:05.358862 DramC Write-DBI off
3521 11:05:05.362360 PER_BANK_REFRESH: Hybrid Mode
3522 11:05:05.362442 TX_TRACKING: ON
3523 11:05:05.372978 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3524 11:05:05.375862 [FAST_K] Save calibration result to emmc
3525 11:05:05.379012 dramc_set_vcore_voltage set vcore to 650000
3526 11:05:05.382046 Read voltage for 600, 5
3527 11:05:05.382127 Vio18 = 0
3528 11:05:05.386559 Vcore = 650000
3529 11:05:05.386640 Vdram = 0
3530 11:05:05.386704 Vddq = 0
3531 11:05:05.386763 Vmddr = 0
3532 11:05:05.392539 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3533 11:05:05.399832 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3534 11:05:05.399914 MEM_TYPE=3, freq_sel=19
3535 11:05:05.401882 sv_algorithm_assistance_LP4_1600
3536 11:05:05.405462 ============ PULL DRAM RESETB DOWN ============
3537 11:05:05.411827 ========== PULL DRAM RESETB DOWN end =========
3538 11:05:05.415428 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3539 11:05:05.418635 ===================================
3540 11:05:05.422378 LPDDR4 DRAM CONFIGURATION
3541 11:05:05.424924 ===================================
3542 11:05:05.425014 EX_ROW_EN[0] = 0x0
3543 11:05:05.428821 EX_ROW_EN[1] = 0x0
3544 11:05:05.428903 LP4Y_EN = 0x0
3545 11:05:05.432170 WORK_FSP = 0x0
3546 11:05:05.435776 WL = 0x2
3547 11:05:05.435858 RL = 0x2
3548 11:05:05.438842 BL = 0x2
3549 11:05:05.438923 RPST = 0x0
3550 11:05:05.442017 RD_PRE = 0x0
3551 11:05:05.442097 WR_PRE = 0x1
3552 11:05:05.445186 WR_PST = 0x0
3553 11:05:05.445267 DBI_WR = 0x0
3554 11:05:05.449225 DBI_RD = 0x0
3555 11:05:05.449306 OTF = 0x1
3556 11:05:05.451902 ===================================
3557 11:05:05.454941 ===================================
3558 11:05:05.458681 ANA top config
3559 11:05:05.461736 ===================================
3560 11:05:05.461818 DLL_ASYNC_EN = 0
3561 11:05:05.466020 ALL_SLAVE_EN = 1
3562 11:05:05.468611 NEW_RANK_MODE = 1
3563 11:05:05.472023 DLL_IDLE_MODE = 1
3564 11:05:05.472104 LP45_APHY_COMB_EN = 1
3565 11:05:05.475295 TX_ODT_DIS = 1
3566 11:05:05.479509 NEW_8X_MODE = 1
3567 11:05:05.481826 ===================================
3568 11:05:05.485098 ===================================
3569 11:05:05.488717 data_rate = 1200
3570 11:05:05.491974 CKR = 1
3571 11:05:05.495053 DQ_P2S_RATIO = 8
3572 11:05:05.498495 ===================================
3573 11:05:05.498576 CA_P2S_RATIO = 8
3574 11:05:05.502254 DQ_CA_OPEN = 0
3575 11:05:05.505102 DQ_SEMI_OPEN = 0
3576 11:05:05.508636 CA_SEMI_OPEN = 0
3577 11:05:05.511677 CA_FULL_RATE = 0
3578 11:05:05.515293 DQ_CKDIV4_EN = 1
3579 11:05:05.515375 CA_CKDIV4_EN = 1
3580 11:05:05.518083 CA_PREDIV_EN = 0
3581 11:05:05.522422 PH8_DLY = 0
3582 11:05:05.524952 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3583 11:05:05.528488 DQ_AAMCK_DIV = 4
3584 11:05:05.531561 CA_AAMCK_DIV = 4
3585 11:05:05.531643 CA_ADMCK_DIV = 4
3586 11:05:05.534764 DQ_TRACK_CA_EN = 0
3587 11:05:05.538122 CA_PICK = 600
3588 11:05:05.541289 CA_MCKIO = 600
3589 11:05:05.544699 MCKIO_SEMI = 0
3590 11:05:05.548599 PLL_FREQ = 2288
3591 11:05:05.551844 DQ_UI_PI_RATIO = 32
3592 11:05:05.551926 CA_UI_PI_RATIO = 0
3593 11:05:05.554308 ===================================
3594 11:05:05.558576 ===================================
3595 11:05:05.561563 memory_type:LPDDR4
3596 11:05:05.564658 GP_NUM : 10
3597 11:05:05.564746 SRAM_EN : 1
3598 11:05:05.567668 MD32_EN : 0
3599 11:05:05.571208 ===================================
3600 11:05:05.574515 [ANA_INIT] >>>>>>>>>>>>>>
3601 11:05:05.577452 <<<<<< [CONFIGURE PHASE]: ANA_TX
3602 11:05:05.580900 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3603 11:05:05.584433 ===================================
3604 11:05:05.584516 data_rate = 1200,PCW = 0X5800
3605 11:05:05.588391 ===================================
3606 11:05:05.590666 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3607 11:05:05.598023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3608 11:05:05.604361 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3609 11:05:05.608573 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3610 11:05:05.611936 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3611 11:05:05.613913 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3612 11:05:05.618031 [ANA_INIT] flow start
3613 11:05:05.620620 [ANA_INIT] PLL >>>>>>>>
3614 11:05:05.620744 [ANA_INIT] PLL <<<<<<<<
3615 11:05:05.623793 [ANA_INIT] MIDPI >>>>>>>>
3616 11:05:05.627459 [ANA_INIT] MIDPI <<<<<<<<
3617 11:05:05.627541 [ANA_INIT] DLL >>>>>>>>
3618 11:05:05.630693 [ANA_INIT] flow end
3619 11:05:05.634180 ============ LP4 DIFF to SE enter ============
3620 11:05:05.637317 ============ LP4 DIFF to SE exit ============
3621 11:05:05.640962 [ANA_INIT] <<<<<<<<<<<<<
3622 11:05:05.643913 [Flow] Enable top DCM control >>>>>
3623 11:05:05.647040 [Flow] Enable top DCM control <<<<<
3624 11:05:05.650668 Enable DLL master slave shuffle
3625 11:05:05.657123 ==============================================================
3626 11:05:05.657207 Gating Mode config
3627 11:05:05.664055 ==============================================================
3628 11:05:05.664138 Config description:
3629 11:05:05.674609 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3630 11:05:05.680186 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3631 11:05:05.686709 SELPH_MODE 0: By rank 1: By Phase
3632 11:05:05.693180 ==============================================================
3633 11:05:05.693265 GAT_TRACK_EN = 1
3634 11:05:05.696637 RX_GATING_MODE = 2
3635 11:05:05.699965 RX_GATING_TRACK_MODE = 2
3636 11:05:05.703366 SELPH_MODE = 1
3637 11:05:05.707093 PICG_EARLY_EN = 1
3638 11:05:05.709997 VALID_LAT_VALUE = 1
3639 11:05:05.717690 ==============================================================
3640 11:05:05.720589 Enter into Gating configuration >>>>
3641 11:05:05.723059 Exit from Gating configuration <<<<
3642 11:05:05.726475 Enter into DVFS_PRE_config >>>>>
3643 11:05:05.736334 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3644 11:05:05.740020 Exit from DVFS_PRE_config <<<<<
3645 11:05:05.743771 Enter into PICG configuration >>>>
3646 11:05:05.746173 Exit from PICG configuration <<<<
3647 11:05:05.750156 [RX_INPUT] configuration >>>>>
3648 11:05:05.753172 [RX_INPUT] configuration <<<<<
3649 11:05:05.756005 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3650 11:05:05.762834 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3651 11:05:05.769371 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3652 11:05:05.772729 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3653 11:05:05.779752 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3654 11:05:05.785907 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3655 11:05:05.789354 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3656 11:05:05.795537 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3657 11:05:05.799154 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3658 11:05:05.802554 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3659 11:05:05.805480 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3660 11:05:05.812040 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3661 11:05:05.816050 ===================================
3662 11:05:05.816134 LPDDR4 DRAM CONFIGURATION
3663 11:05:05.818640 ===================================
3664 11:05:05.822504 EX_ROW_EN[0] = 0x0
3665 11:05:05.827219 EX_ROW_EN[1] = 0x0
3666 11:05:05.827305 LP4Y_EN = 0x0
3667 11:05:05.828674 WORK_FSP = 0x0
3668 11:05:05.828805 WL = 0x2
3669 11:05:05.832298 RL = 0x2
3670 11:05:05.832380 BL = 0x2
3671 11:05:05.835530 RPST = 0x0
3672 11:05:05.835631 RD_PRE = 0x0
3673 11:05:05.839279 WR_PRE = 0x1
3674 11:05:05.839361 WR_PST = 0x0
3675 11:05:05.841554 DBI_WR = 0x0
3676 11:05:05.841636 DBI_RD = 0x0
3677 11:05:05.845372 OTF = 0x1
3678 11:05:05.848418 ===================================
3679 11:05:05.851942 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3680 11:05:05.855297 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3681 11:05:05.862013 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3682 11:05:05.865062 ===================================
3683 11:05:05.865146 LPDDR4 DRAM CONFIGURATION
3684 11:05:05.869468 ===================================
3685 11:05:05.871727 EX_ROW_EN[0] = 0x10
3686 11:05:05.875021 EX_ROW_EN[1] = 0x0
3687 11:05:05.875103 LP4Y_EN = 0x0
3688 11:05:05.877883 WORK_FSP = 0x0
3689 11:05:05.877964 WL = 0x2
3690 11:05:05.881301 RL = 0x2
3691 11:05:05.881382 BL = 0x2
3692 11:05:05.885251 RPST = 0x0
3693 11:05:05.885334 RD_PRE = 0x0
3694 11:05:05.888461 WR_PRE = 0x1
3695 11:05:05.888542 WR_PST = 0x0
3696 11:05:05.891731 DBI_WR = 0x0
3697 11:05:05.891812 DBI_RD = 0x0
3698 11:05:05.894897 OTF = 0x1
3699 11:05:05.898420 ===================================
3700 11:05:05.904464 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3701 11:05:05.908054 nWR fixed to 30
3702 11:05:05.911139 [ModeRegInit_LP4] CH0 RK0
3703 11:05:05.911220 [ModeRegInit_LP4] CH0 RK1
3704 11:05:05.914431 [ModeRegInit_LP4] CH1 RK0
3705 11:05:05.917833 [ModeRegInit_LP4] CH1 RK1
3706 11:05:05.917927 match AC timing 16
3707 11:05:05.924455 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3708 11:05:05.928636 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3709 11:05:05.931769 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3710 11:05:05.937664 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3711 11:05:05.940945 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3712 11:05:05.941027 ==
3713 11:05:05.944562 Dram Type= 6, Freq= 0, CH_0, rank 0
3714 11:05:05.948061 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3715 11:05:05.948143 ==
3716 11:05:05.953774 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3717 11:05:05.961041 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3718 11:05:05.964412 [CA 0] Center 35 (5~66) winsize 62
3719 11:05:05.967177 [CA 1] Center 35 (5~66) winsize 62
3720 11:05:05.970779 [CA 2] Center 34 (4~65) winsize 62
3721 11:05:05.973638 [CA 3] Center 34 (4~65) winsize 62
3722 11:05:05.977340 [CA 4] Center 33 (3~64) winsize 62
3723 11:05:05.980414 [CA 5] Center 33 (3~64) winsize 62
3724 11:05:05.980495
3725 11:05:05.984676 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3726 11:05:05.984808
3727 11:05:05.987013 [CATrainingPosCal] consider 1 rank data
3728 11:05:05.990178 u2DelayCellTimex100 = 270/100 ps
3729 11:05:05.993605 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3730 11:05:05.997873 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3731 11:05:06.000247 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3732 11:05:06.003534 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3733 11:05:06.010496 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3734 11:05:06.013665 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3735 11:05:06.013747
3736 11:05:06.016493 CA PerBit enable=1, Macro0, CA PI delay=33
3737 11:05:06.016574
3738 11:05:06.020026 [CBTSetCACLKResult] CA Dly = 33
3739 11:05:06.020162 CS Dly: 6 (0~37)
3740 11:05:06.020262 ==
3741 11:05:06.023098 Dram Type= 6, Freq= 0, CH_0, rank 1
3742 11:05:06.030635 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3743 11:05:06.030722 ==
3744 11:05:06.033660 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3745 11:05:06.040261 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3746 11:05:06.043636 [CA 0] Center 35 (5~66) winsize 62
3747 11:05:06.046768 [CA 1] Center 35 (5~66) winsize 62
3748 11:05:06.050391 [CA 2] Center 34 (4~65) winsize 62
3749 11:05:06.052919 [CA 3] Center 34 (4~65) winsize 62
3750 11:05:06.056792 [CA 4] Center 33 (3~64) winsize 62
3751 11:05:06.059939 [CA 5] Center 33 (3~64) winsize 62
3752 11:05:06.060020
3753 11:05:06.062921 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3754 11:05:06.063003
3755 11:05:06.066573 [CATrainingPosCal] consider 2 rank data
3756 11:05:06.070313 u2DelayCellTimex100 = 270/100 ps
3757 11:05:06.073791 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3758 11:05:06.079624 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3759 11:05:06.082667 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3760 11:05:06.085905 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3761 11:05:06.089260 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3762 11:05:06.093022 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3763 11:05:06.093104
3764 11:05:06.096118 CA PerBit enable=1, Macro0, CA PI delay=33
3765 11:05:06.096193
3766 11:05:06.099694 [CBTSetCACLKResult] CA Dly = 33
3767 11:05:06.102582 CS Dly: 5 (0~36)
3768 11:05:06.102664
3769 11:05:06.107028 ----->DramcWriteLeveling(PI) begin...
3770 11:05:06.107112 ==
3771 11:05:06.109171 Dram Type= 6, Freq= 0, CH_0, rank 0
3772 11:05:06.112995 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3773 11:05:06.113078 ==
3774 11:05:06.115520 Write leveling (Byte 0): 30 => 30
3775 11:05:06.119311 Write leveling (Byte 1): 29 => 29
3776 11:05:06.122371 DramcWriteLeveling(PI) end<-----
3777 11:05:06.122456
3778 11:05:06.122540 ==
3779 11:05:06.125792 Dram Type= 6, Freq= 0, CH_0, rank 0
3780 11:05:06.129323 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3781 11:05:06.129407 ==
3782 11:05:06.133037 [Gating] SW mode calibration
3783 11:05:06.139456 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3784 11:05:06.146017 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3785 11:05:06.149626 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3786 11:05:06.152874 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3787 11:05:06.158705 0 5 8 | B1->B0 | 3232 3232 | 1 0 | (1 0) (0 1)
3788 11:05:06.162244 0 5 12 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
3789 11:05:06.165993 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3790 11:05:06.172459 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3791 11:05:06.175751 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3792 11:05:06.178873 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3793 11:05:06.185129 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3794 11:05:06.188815 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3795 11:05:06.192464 0 6 8 | B1->B0 | 2b2b 3030 | 0 0 | (0 0) (0 0)
3796 11:05:06.199425 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3797 11:05:06.201601 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3798 11:05:06.205335 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3799 11:05:06.211690 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3800 11:05:06.214617 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3801 11:05:06.218375 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3802 11:05:06.224950 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3803 11:05:06.227830 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3804 11:05:06.231514 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3805 11:05:06.238000 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3806 11:05:06.241167 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3807 11:05:06.244592 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3808 11:05:06.251042 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3809 11:05:06.254423 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3810 11:05:06.257719 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3811 11:05:06.266132 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 11:05:06.269184 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 11:05:06.270684 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 11:05:06.278346 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 11:05:06.280689 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 11:05:06.284515 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 11:05:06.291286 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 11:05:06.294072 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 11:05:06.297519 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3820 11:05:06.302308 Total UI for P1: 0, mck2ui 16
3821 11:05:06.305008 best dqsien dly found for B0: ( 0, 9, 6)
3822 11:05:06.312240 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3823 11:05:06.314175 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3824 11:05:06.317758 Total UI for P1: 0, mck2ui 16
3825 11:05:06.320579 best dqsien dly found for B1: ( 0, 9, 10)
3826 11:05:06.323888 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3827 11:05:06.327156 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3828 11:05:06.327265
3829 11:05:06.330551 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3830 11:05:06.333816 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3831 11:05:06.337661 [Gating] SW calibration Done
3832 11:05:06.337743 ==
3833 11:05:06.340650 Dram Type= 6, Freq= 0, CH_0, rank 0
3834 11:05:06.344066 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3835 11:05:06.344148 ==
3836 11:05:06.347382 RX Vref Scan: 0
3837 11:05:06.347463
3838 11:05:06.350574 RX Vref 0 -> 0, step: 1
3839 11:05:06.350655
3840 11:05:06.353905 RX Delay -230 -> 252, step: 16
3841 11:05:06.357336 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3842 11:05:06.360184 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3843 11:05:06.363425 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3844 11:05:06.370194 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3845 11:05:06.373722 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3846 11:05:06.376596 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3847 11:05:06.380291 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3848 11:05:06.383319 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
3849 11:05:06.390960 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3850 11:05:06.395008 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3851 11:05:06.397816 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3852 11:05:06.399810 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3853 11:05:06.406542 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3854 11:05:06.409954 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3855 11:05:06.413415 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3856 11:05:06.417116 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3857 11:05:06.417196 ==
3858 11:05:06.420789 Dram Type= 6, Freq= 0, CH_0, rank 0
3859 11:05:06.426536 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3860 11:05:06.426619 ==
3861 11:05:06.426683 DQS Delay:
3862 11:05:06.430198 DQS0 = 0, DQS1 = 0
3863 11:05:06.430278 DQM Delay:
3864 11:05:06.430342 DQM0 = 39, DQM1 = 33
3865 11:05:06.433234 DQ Delay:
3866 11:05:06.436186 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3867 11:05:06.439606 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =57
3868 11:05:06.443548 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3869 11:05:06.446175 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3870 11:05:06.446256
3871 11:05:06.446318
3872 11:05:06.446377 ==
3873 11:05:06.450068 Dram Type= 6, Freq= 0, CH_0, rank 0
3874 11:05:06.453311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3875 11:05:06.453392 ==
3876 11:05:06.453455
3877 11:05:06.453513
3878 11:05:06.456730 TX Vref Scan disable
3879 11:05:06.459208 == TX Byte 0 ==
3880 11:05:06.462766 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3881 11:05:06.466242 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3882 11:05:06.468927 == TX Byte 1 ==
3883 11:05:06.472499 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3884 11:05:06.476175 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3885 11:05:06.476255 ==
3886 11:05:06.479516 Dram Type= 6, Freq= 0, CH_0, rank 0
3887 11:05:06.485456 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3888 11:05:06.485538 ==
3889 11:05:06.485602
3890 11:05:06.485660
3891 11:05:06.485716 TX Vref Scan disable
3892 11:05:06.490035 == TX Byte 0 ==
3893 11:05:06.493360 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3894 11:05:06.500499 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3895 11:05:06.500581 == TX Byte 1 ==
3896 11:05:06.503119 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3897 11:05:06.510163 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3898 11:05:06.510244
3899 11:05:06.510307 [DATLAT]
3900 11:05:06.510366 Freq=600, CH0 RK0
3901 11:05:06.510423
3902 11:05:06.513386 DATLAT Default: 0x9
3903 11:05:06.513465 0, 0xFFFF, sum = 0
3904 11:05:06.518267 1, 0xFFFF, sum = 0
3905 11:05:06.518349 2, 0xFFFF, sum = 0
3906 11:05:06.520185 3, 0xFFFF, sum = 0
3907 11:05:06.522926 4, 0xFFFF, sum = 0
3908 11:05:06.523010 5, 0xFFFF, sum = 0
3909 11:05:06.526520 6, 0xFFFF, sum = 0
3910 11:05:06.526611 7, 0x0, sum = 1
3911 11:05:06.526677 8, 0x0, sum = 2
3912 11:05:06.529436 9, 0x0, sum = 3
3913 11:05:06.529517 10, 0x0, sum = 4
3914 11:05:06.532873 best_step = 8
3915 11:05:06.532952
3916 11:05:06.533016 ==
3917 11:05:06.536277 Dram Type= 6, Freq= 0, CH_0, rank 0
3918 11:05:06.539344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3919 11:05:06.539425 ==
3920 11:05:06.542565 RX Vref Scan: 1
3921 11:05:06.542644
3922 11:05:06.542706 RX Vref 0 -> 0, step: 1
3923 11:05:06.542765
3924 11:05:06.546174 RX Delay -195 -> 252, step: 8
3925 11:05:06.546254
3926 11:05:06.549716 Set Vref, RX VrefLevel [Byte0]: 46
3927 11:05:06.552586 [Byte1]: 47
3928 11:05:06.556725
3929 11:05:06.556820 Final RX Vref Byte 0 = 46 to rank0
3930 11:05:06.560320 Final RX Vref Byte 1 = 47 to rank0
3931 11:05:06.563283 Final RX Vref Byte 0 = 46 to rank1
3932 11:05:06.567126 Final RX Vref Byte 1 = 47 to rank1==
3933 11:05:06.569737 Dram Type= 6, Freq= 0, CH_0, rank 0
3934 11:05:06.576834 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3935 11:05:06.576916 ==
3936 11:05:06.576979 DQS Delay:
3937 11:05:06.579922 DQS0 = 0, DQS1 = 0
3938 11:05:06.580000 DQM Delay:
3939 11:05:06.580063 DQM0 = 39, DQM1 = 30
3940 11:05:06.583211 DQ Delay:
3941 11:05:06.587174 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
3942 11:05:06.590152 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =44
3943 11:05:06.593283 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
3944 11:05:06.596356 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
3945 11:05:06.596435
3946 11:05:06.596497
3947 11:05:06.603101 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a4a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
3948 11:05:06.606160 CH0 RK0: MR19=808, MR18=4A4A
3949 11:05:06.612831 CH0_RK0: MR19=0x808, MR18=0x4A4A, DQSOSC=395, MR23=63, INC=168, DEC=112
3950 11:05:06.612916
3951 11:05:06.616215 ----->DramcWriteLeveling(PI) begin...
3952 11:05:06.616295 ==
3953 11:05:06.620257 Dram Type= 6, Freq= 0, CH_0, rank 1
3954 11:05:06.623288 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3955 11:05:06.623375 ==
3956 11:05:06.626902 Write leveling (Byte 0): 31 => 31
3957 11:05:06.630185 Write leveling (Byte 1): 31 => 31
3958 11:05:06.632888 DramcWriteLeveling(PI) end<-----
3959 11:05:06.632968
3960 11:05:06.633030 ==
3961 11:05:06.636657 Dram Type= 6, Freq= 0, CH_0, rank 1
3962 11:05:06.639800 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3963 11:05:06.643359 ==
3964 11:05:06.643439 [Gating] SW mode calibration
3965 11:05:06.649400 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3966 11:05:06.656168 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3967 11:05:06.660306 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3968 11:05:06.666159 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3969 11:05:06.669566 0 5 8 | B1->B0 | 3232 2f2f | 0 0 | (1 0) (0 0)
3970 11:05:06.672941 0 5 12 | B1->B0 | 2929 2727 | 1 1 | (1 0) (0 0)
3971 11:05:06.679384 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 11:05:06.682585 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 11:05:06.686100 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 11:05:06.692355 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 11:05:06.696435 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 11:05:06.698742 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 11:05:06.705567 0 6 8 | B1->B0 | 2a2a 2c2c | 1 1 | (0 0) (1 1)
3978 11:05:06.708599 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 11:05:06.712004 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 11:05:06.719063 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 11:05:06.723581 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 11:05:06.725942 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 11:05:06.732908 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 11:05:06.735728 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 11:05:06.738907 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3986 11:05:06.745381 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3987 11:05:06.748904 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 11:05:06.753027 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 11:05:06.758669 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 11:05:06.761963 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 11:05:06.765337 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 11:05:06.768826 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 11:05:06.775061 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 11:05:06.778404 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 11:05:06.781874 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 11:05:06.788641 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 11:05:06.791923 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 11:05:06.795659 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 11:05:06.801606 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 11:05:06.805910 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 11:05:06.808630 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4002 11:05:06.814961 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 11:05:06.818835 Total UI for P1: 0, mck2ui 16
4004 11:05:06.822629 best dqsien dly found for B0: ( 0, 9, 8)
4005 11:05:06.822715 Total UI for P1: 0, mck2ui 16
4006 11:05:06.828966 best dqsien dly found for B1: ( 0, 9, 10)
4007 11:05:06.831346 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4008 11:05:06.835521 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4009 11:05:06.835604
4010 11:05:06.838618 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4011 11:05:06.841347 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4012 11:05:06.845614 [Gating] SW calibration Done
4013 11:05:06.845696 ==
4014 11:05:06.848062 Dram Type= 6, Freq= 0, CH_0, rank 1
4015 11:05:06.851353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4016 11:05:06.851436 ==
4017 11:05:06.855512 RX Vref Scan: 0
4018 11:05:06.855594
4019 11:05:06.855677 RX Vref 0 -> 0, step: 1
4020 11:05:06.857776
4021 11:05:06.857857 RX Delay -230 -> 252, step: 16
4022 11:05:06.864603 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4023 11:05:06.868690 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4024 11:05:06.873006 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4025 11:05:06.874887 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4026 11:05:06.881242 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4027 11:05:06.884658 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4028 11:05:06.887634 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4029 11:05:06.892465 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4030 11:05:06.895000 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4031 11:05:06.901058 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4032 11:05:06.904303 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4033 11:05:06.907751 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4034 11:05:06.910771 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4035 11:05:06.917771 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4036 11:05:06.920775 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4037 11:05:06.924031 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4038 11:05:06.924112 ==
4039 11:05:06.928039 Dram Type= 6, Freq= 0, CH_0, rank 1
4040 11:05:06.930647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4041 11:05:06.934876 ==
4042 11:05:06.934956 DQS Delay:
4043 11:05:06.935019 DQS0 = 0, DQS1 = 0
4044 11:05:06.937694 DQM Delay:
4045 11:05:06.937772 DQM0 = 40, DQM1 = 32
4046 11:05:06.940497 DQ Delay:
4047 11:05:06.943939 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4048 11:05:06.944018 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4049 11:05:06.947273 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4050 11:05:06.954429 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4051 11:05:06.954507
4052 11:05:06.954569
4053 11:05:06.954627 ==
4054 11:05:06.957399 Dram Type= 6, Freq= 0, CH_0, rank 1
4055 11:05:06.960514 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4056 11:05:06.960619 ==
4057 11:05:06.960715
4058 11:05:06.960816
4059 11:05:06.963669 TX Vref Scan disable
4060 11:05:06.963748 == TX Byte 0 ==
4061 11:05:06.970072 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4062 11:05:06.974458 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4063 11:05:06.974537 == TX Byte 1 ==
4064 11:05:06.981036 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4065 11:05:06.984978 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4066 11:05:06.985056 ==
4067 11:05:06.986877 Dram Type= 6, Freq= 0, CH_0, rank 1
4068 11:05:06.989960 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4069 11:05:06.990039 ==
4070 11:05:06.990102
4071 11:05:06.995958
4072 11:05:06.996036 TX Vref Scan disable
4073 11:05:06.996986 == TX Byte 0 ==
4074 11:05:06.999957 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4075 11:05:07.006819 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4076 11:05:07.006898 == TX Byte 1 ==
4077 11:05:07.010344 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4078 11:05:07.013860 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4079 11:05:07.016952
4080 11:05:07.017030 [DATLAT]
4081 11:05:07.017092 Freq=600, CH0 RK1
4082 11:05:07.017150
4083 11:05:07.020807 DATLAT Default: 0x8
4084 11:05:07.020923 0, 0xFFFF, sum = 0
4085 11:05:07.023184 1, 0xFFFF, sum = 0
4086 11:05:07.023265 2, 0xFFFF, sum = 0
4087 11:05:07.027837 3, 0xFFFF, sum = 0
4088 11:05:07.027968 4, 0xFFFF, sum = 0
4089 11:05:07.029815 5, 0xFFFF, sum = 0
4090 11:05:07.033333 6, 0xFFFF, sum = 0
4091 11:05:07.033413 7, 0x0, sum = 1
4092 11:05:07.033477 8, 0x0, sum = 2
4093 11:05:07.037134 9, 0x0, sum = 3
4094 11:05:07.037213 10, 0x0, sum = 4
4095 11:05:07.040603 best_step = 8
4096 11:05:07.040683
4097 11:05:07.040797 ==
4098 11:05:07.043857 Dram Type= 6, Freq= 0, CH_0, rank 1
4099 11:05:07.047523 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4100 11:05:07.047603 ==
4101 11:05:07.050794 RX Vref Scan: 0
4102 11:05:07.050873
4103 11:05:07.050935 RX Vref 0 -> 0, step: 1
4104 11:05:07.050993
4105 11:05:07.053509 RX Delay -195 -> 252, step: 8
4106 11:05:07.060214 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4107 11:05:07.064021 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4108 11:05:07.067524 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4109 11:05:07.071029 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4110 11:05:07.077014 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4111 11:05:07.080591 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4112 11:05:07.084068 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4113 11:05:07.086885 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4114 11:05:07.090233 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4115 11:05:07.097710 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4116 11:05:07.101796 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4117 11:05:07.103596 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4118 11:05:07.106922 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4119 11:05:07.113272 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4120 11:05:07.116624 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4121 11:05:07.120103 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4122 11:05:07.120185 ==
4123 11:05:07.123388 Dram Type= 6, Freq= 0, CH_0, rank 1
4124 11:05:07.126719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4125 11:05:07.129978 ==
4126 11:05:07.130060 DQS Delay:
4127 11:05:07.130124 DQS0 = 0, DQS1 = 0
4128 11:05:07.133220 DQM Delay:
4129 11:05:07.133301 DQM0 = 42, DQM1 = 33
4130 11:05:07.136930 DQ Delay:
4131 11:05:07.139980 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4132 11:05:07.140062 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4133 11:05:07.143428 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4134 11:05:07.149741 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4135 11:05:07.149822
4136 11:05:07.149886
4137 11:05:07.156566 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f6f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4138 11:05:07.159976 CH0 RK1: MR19=808, MR18=6F6F
4139 11:05:07.166955 CH0_RK1: MR19=0x808, MR18=0x6F6F, DQSOSC=389, MR23=63, INC=173, DEC=115
4140 11:05:07.169545 [RxdqsGatingPostProcess] freq 600
4141 11:05:07.172843 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4142 11:05:07.176587 Pre-setting of DQS Precalculation
4143 11:05:07.182916 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4144 11:05:07.182996 ==
4145 11:05:07.186996 Dram Type= 6, Freq= 0, CH_1, rank 0
4146 11:05:07.190198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4147 11:05:07.190278 ==
4148 11:05:07.196225 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4149 11:05:07.199428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4150 11:05:07.203804 [CA 0] Center 35 (5~66) winsize 62
4151 11:05:07.209426 [CA 1] Center 35 (5~66) winsize 62
4152 11:05:07.210560 [CA 2] Center 33 (3~64) winsize 62
4153 11:05:07.213988 [CA 3] Center 33 (3~64) winsize 62
4154 11:05:07.217169 [CA 4] Center 33 (2~64) winsize 63
4155 11:05:07.220218 [CA 5] Center 33 (2~64) winsize 63
4156 11:05:07.220377
4157 11:05:07.223620 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4158 11:05:07.223716
4159 11:05:07.227070 [CATrainingPosCal] consider 1 rank data
4160 11:05:07.230858 u2DelayCellTimex100 = 270/100 ps
4161 11:05:07.233477 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4162 11:05:07.240306 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4163 11:05:07.243493 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4164 11:05:07.246866 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4165 11:05:07.250324 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4166 11:05:07.253208 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4167 11:05:07.253333
4168 11:05:07.256660 CA PerBit enable=1, Macro0, CA PI delay=33
4169 11:05:07.256831
4170 11:05:07.260653 [CBTSetCACLKResult] CA Dly = 33
4171 11:05:07.263628 CS Dly: 3 (0~34)
4172 11:05:07.263972 ==
4173 11:05:07.266960 Dram Type= 6, Freq= 0, CH_1, rank 1
4174 11:05:07.270420 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4175 11:05:07.270884 ==
4176 11:05:07.276762 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4177 11:05:07.280004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4178 11:05:07.284805 [CA 0] Center 35 (5~66) winsize 62
4179 11:05:07.288189 [CA 1] Center 34 (4~65) winsize 62
4180 11:05:07.291590 [CA 2] Center 33 (3~64) winsize 62
4181 11:05:07.294401 [CA 3] Center 33 (3~64) winsize 62
4182 11:05:07.298047 [CA 4] Center 32 (2~63) winsize 62
4183 11:05:07.300619 [CA 5] Center 32 (2~63) winsize 62
4184 11:05:07.301072
4185 11:05:07.304440 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4186 11:05:07.304902
4187 11:05:07.308282 [CATrainingPosCal] consider 2 rank data
4188 11:05:07.313323 u2DelayCellTimex100 = 270/100 ps
4189 11:05:07.315594 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4190 11:05:07.320300 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4191 11:05:07.323389 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4192 11:05:07.327109 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4193 11:05:07.330368 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4194 11:05:07.334294 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4195 11:05:07.334444
4196 11:05:07.336669 CA PerBit enable=1, Macro0, CA PI delay=32
4197 11:05:07.336792
4198 11:05:07.340478 [CBTSetCACLKResult] CA Dly = 32
4199 11:05:07.343061 CS Dly: 3 (0~35)
4200 11:05:07.343152
4201 11:05:07.346845 ----->DramcWriteLeveling(PI) begin...
4202 11:05:07.346938 ==
4203 11:05:07.349916 Dram Type= 6, Freq= 0, CH_1, rank 0
4204 11:05:07.352946 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4205 11:05:07.353034 ==
4206 11:05:07.356364 Write leveling (Byte 0): 27 => 27
4207 11:05:07.359741 Write leveling (Byte 1): 27 => 27
4208 11:05:07.362791 DramcWriteLeveling(PI) end<-----
4209 11:05:07.362872
4210 11:05:07.362936 ==
4211 11:05:07.366182 Dram Type= 6, Freq= 0, CH_1, rank 0
4212 11:05:07.369683 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4213 11:05:07.369779 ==
4214 11:05:07.373150 [Gating] SW mode calibration
4215 11:05:07.379909 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4216 11:05:07.387352 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4217 11:05:07.390713 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4218 11:05:07.393646 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4219 11:05:07.399794 0 5 8 | B1->B0 | 3030 2828 | 0 0 | (1 1) (1 1)
4220 11:05:07.403687 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 11:05:07.406972 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 11:05:07.412694 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 11:05:07.416577 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 11:05:07.421689 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 11:05:07.426067 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 11:05:07.429747 0 6 4 | B1->B0 | 2424 2d2d | 0 0 | (1 1) (0 0)
4227 11:05:07.432754 0 6 8 | B1->B0 | 3737 4545 | 0 0 | (1 1) (0 0)
4228 11:05:07.439977 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 11:05:07.443519 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 11:05:07.447056 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 11:05:07.452478 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 11:05:07.456124 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 11:05:07.458794 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 11:05:07.465529 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4235 11:05:07.469806 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4236 11:05:07.472574 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 11:05:07.479055 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 11:05:07.482040 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 11:05:07.486162 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 11:05:07.492050 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 11:05:07.495341 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 11:05:07.498869 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 11:05:07.505311 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 11:05:07.508488 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:05:07.511626 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 11:05:07.518334 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 11:05:07.521698 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 11:05:07.524833 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 11:05:07.531687 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 11:05:07.535108 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4251 11:05:07.538195 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 11:05:07.541632 Total UI for P1: 0, mck2ui 16
4253 11:05:07.545107 best dqsien dly found for B0: ( 0, 9, 4)
4254 11:05:07.548225 Total UI for P1: 0, mck2ui 16
4255 11:05:07.552776 best dqsien dly found for B1: ( 0, 9, 6)
4256 11:05:07.555744 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4257 11:05:07.558103 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4258 11:05:07.558182
4259 11:05:07.561874 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4260 11:05:07.567819 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4261 11:05:07.567899 [Gating] SW calibration Done
4262 11:05:07.567961 ==
4263 11:05:07.571371 Dram Type= 6, Freq= 0, CH_1, rank 0
4264 11:05:07.578191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4265 11:05:07.578272 ==
4266 11:05:07.578336 RX Vref Scan: 0
4267 11:05:07.578394
4268 11:05:07.581174 RX Vref 0 -> 0, step: 1
4269 11:05:07.581254
4270 11:05:07.584834 RX Delay -230 -> 252, step: 16
4271 11:05:07.588522 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4272 11:05:07.591183 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4273 11:05:07.597858 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4274 11:05:07.601141 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4275 11:05:07.604535 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4276 11:05:07.607791 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4277 11:05:07.610976 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4278 11:05:07.617656 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4279 11:05:07.620958 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4280 11:05:07.624663 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4281 11:05:07.628851 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4282 11:05:07.634806 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4283 11:05:07.637905 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4284 11:05:07.640843 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4285 11:05:07.643796 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4286 11:05:07.650457 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4287 11:05:07.650552 ==
4288 11:05:07.653947 Dram Type= 6, Freq= 0, CH_1, rank 0
4289 11:05:07.657474 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4290 11:05:07.657563 ==
4291 11:05:07.657641 DQS Delay:
4292 11:05:07.660370 DQS0 = 0, DQS1 = 0
4293 11:05:07.660456 DQM Delay:
4294 11:05:07.664176 DQM0 = 39, DQM1 = 34
4295 11:05:07.664262 DQ Delay:
4296 11:05:07.667245 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4297 11:05:07.670379 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4298 11:05:07.673729 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4299 11:05:07.677380 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4300 11:05:07.677473
4301 11:05:07.677552
4302 11:05:07.677628 ==
4303 11:05:07.680130 Dram Type= 6, Freq= 0, CH_1, rank 0
4304 11:05:07.683615 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4305 11:05:07.687080 ==
4306 11:05:07.687168
4307 11:05:07.687245
4308 11:05:07.687319 TX Vref Scan disable
4309 11:05:07.690503 == TX Byte 0 ==
4310 11:05:07.693920 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4311 11:05:07.696625 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4312 11:05:07.700279 == TX Byte 1 ==
4313 11:05:07.703600 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4314 11:05:07.706803 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4315 11:05:07.710303 ==
4316 11:05:07.713494 Dram Type= 6, Freq= 0, CH_1, rank 0
4317 11:05:07.716905 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4318 11:05:07.717030 ==
4319 11:05:07.717096
4320 11:05:07.717155
4321 11:05:07.719657 TX Vref Scan disable
4322 11:05:07.723211 == TX Byte 0 ==
4323 11:05:07.726331 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4324 11:05:07.729851 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4325 11:05:07.732867 == TX Byte 1 ==
4326 11:05:07.736125 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4327 11:05:07.739659 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4328 11:05:07.739757
4329 11:05:07.739821 [DATLAT]
4330 11:05:07.743521 Freq=600, CH1 RK0
4331 11:05:07.743693
4332 11:05:07.743789 DATLAT Default: 0x9
4333 11:05:07.747035 0, 0xFFFF, sum = 0
4334 11:05:07.750622 1, 0xFFFF, sum = 0
4335 11:05:07.750782 2, 0xFFFF, sum = 0
4336 11:05:07.753146 3, 0xFFFF, sum = 0
4337 11:05:07.753298 4, 0xFFFF, sum = 0
4338 11:05:07.756475 5, 0xFFFF, sum = 0
4339 11:05:07.756562 6, 0xFFFF, sum = 0
4340 11:05:07.759310 7, 0x0, sum = 1
4341 11:05:07.759398 8, 0x0, sum = 2
4342 11:05:07.759467 9, 0x0, sum = 3
4343 11:05:07.763324 10, 0x0, sum = 4
4344 11:05:07.763496 best_step = 8
4345 11:05:07.763579
4346 11:05:07.763649 ==
4347 11:05:07.766027 Dram Type= 6, Freq= 0, CH_1, rank 0
4348 11:05:07.773106 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4349 11:05:07.773286 ==
4350 11:05:07.773382 RX Vref Scan: 1
4351 11:05:07.773464
4352 11:05:07.776318 RX Vref 0 -> 0, step: 1
4353 11:05:07.776504
4354 11:05:07.779368 RX Delay -195 -> 252, step: 8
4355 11:05:07.779567
4356 11:05:07.782395 Set Vref, RX VrefLevel [Byte0]: 54
4357 11:05:07.786815 [Byte1]: 48
4358 11:05:07.787052
4359 11:05:07.789214 Final RX Vref Byte 0 = 54 to rank0
4360 11:05:07.793369 Final RX Vref Byte 1 = 48 to rank0
4361 11:05:07.796352 Final RX Vref Byte 0 = 54 to rank1
4362 11:05:07.799709 Final RX Vref Byte 1 = 48 to rank1==
4363 11:05:07.803115 Dram Type= 6, Freq= 0, CH_1, rank 0
4364 11:05:07.806366 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4365 11:05:07.809496 ==
4366 11:05:07.809889 DQS Delay:
4367 11:05:07.810128 DQS0 = 0, DQS1 = 0
4368 11:05:07.812651 DQM Delay:
4369 11:05:07.813170 DQM0 = 38, DQM1 = 30
4370 11:05:07.816900 DQ Delay:
4371 11:05:07.817427 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4372 11:05:07.819752 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4373 11:05:07.822522 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4374 11:05:07.826260 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4375 11:05:07.826675
4376 11:05:07.829206
4377 11:05:07.835878 [DQSOSCAuto] RK0, (LSB)MR18= 0x7878, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4378 11:05:07.839320 CH1 RK0: MR19=808, MR18=7878
4379 11:05:07.847327 CH1_RK0: MR19=0x808, MR18=0x7878, DQSOSC=387, MR23=63, INC=175, DEC=116
4380 11:05:07.847830
4381 11:05:07.850002 ----->DramcWriteLeveling(PI) begin...
4382 11:05:07.850526 ==
4383 11:05:07.852631 Dram Type= 6, Freq= 0, CH_1, rank 1
4384 11:05:07.855599 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4385 11:05:07.856014 ==
4386 11:05:07.859518 Write leveling (Byte 0): 30 => 30
4387 11:05:07.862961 Write leveling (Byte 1): 26 => 26
4388 11:05:07.866080 DramcWriteLeveling(PI) end<-----
4389 11:05:07.866603
4390 11:05:07.866931 ==
4391 11:05:07.868831 Dram Type= 6, Freq= 0, CH_1, rank 1
4392 11:05:07.872283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4393 11:05:07.872845 ==
4394 11:05:07.875716 [Gating] SW mode calibration
4395 11:05:07.882519 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4396 11:05:07.890062 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4397 11:05:07.892591 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4398 11:05:07.895567 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4399 11:05:07.902202 0 5 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4400 11:05:07.905720 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4401 11:05:07.908968 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 11:05:07.915868 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4403 11:05:07.919376 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4404 11:05:07.921982 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 11:05:07.929822 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 11:05:07.932309 0 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4407 11:05:07.935914 0 6 8 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
4408 11:05:07.942420 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 11:05:07.944921 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4410 11:05:07.948396 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 11:05:07.954931 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 11:05:07.959145 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 11:05:07.962338 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 11:05:07.968352 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 11:05:07.972026 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4416 11:05:07.975636 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 11:05:07.981326 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 11:05:07.985140 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 11:05:07.988317 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 11:05:07.994726 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 11:05:07.998609 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 11:05:08.000685 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 11:05:08.008628 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 11:05:08.011175 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 11:05:08.014200 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 11:05:08.020874 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 11:05:08.023834 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 11:05:08.027770 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 11:05:08.033836 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 11:05:08.037043 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4431 11:05:08.040752 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 11:05:08.044325 Total UI for P1: 0, mck2ui 16
4433 11:05:08.047219 best dqsien dly found for B0: ( 0, 9, 4)
4434 11:05:08.050905 Total UI for P1: 0, mck2ui 16
4435 11:05:08.053882 best dqsien dly found for B1: ( 0, 9, 6)
4436 11:05:08.057324 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4437 11:05:08.060467 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4438 11:05:08.061036
4439 11:05:08.067404 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4440 11:05:08.070215 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4441 11:05:08.073557 [Gating] SW calibration Done
4442 11:05:08.074078 ==
4443 11:05:08.076892 Dram Type= 6, Freq= 0, CH_1, rank 1
4444 11:05:08.080422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4445 11:05:08.080983 ==
4446 11:05:08.081320 RX Vref Scan: 0
4447 11:05:08.081632
4448 11:05:08.084561 RX Vref 0 -> 0, step: 1
4449 11:05:08.085130
4450 11:05:08.087421 RX Delay -230 -> 252, step: 16
4451 11:05:08.091128 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4452 11:05:08.093414 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4453 11:05:08.099824 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4454 11:05:08.103496 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4455 11:05:08.106853 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4456 11:05:08.110086 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4457 11:05:08.116351 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4458 11:05:08.119887 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4459 11:05:08.123808 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4460 11:05:08.126717 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4461 11:05:08.133934 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4462 11:05:08.136809 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4463 11:05:08.140077 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4464 11:05:08.144209 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4465 11:05:08.150071 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4466 11:05:08.153356 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4467 11:05:08.153862 ==
4468 11:05:08.157062 Dram Type= 6, Freq= 0, CH_1, rank 1
4469 11:05:08.159863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4470 11:05:08.160372 ==
4471 11:05:08.163140 DQS Delay:
4472 11:05:08.163646 DQS0 = 0, DQS1 = 0
4473 11:05:08.163981 DQM Delay:
4474 11:05:08.166188 DQM0 = 42, DQM1 = 34
4475 11:05:08.166700 DQ Delay:
4476 11:05:08.169662 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4477 11:05:08.172837 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4478 11:05:08.175793 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4479 11:05:08.179230 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4480 11:05:08.179742
4481 11:05:08.180076
4482 11:05:08.180384 ==
4483 11:05:08.183193 Dram Type= 6, Freq= 0, CH_1, rank 1
4484 11:05:08.189242 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4485 11:05:08.189763 ==
4486 11:05:08.190275
4487 11:05:08.190675
4488 11:05:08.190987 TX Vref Scan disable
4489 11:05:08.193000 == TX Byte 0 ==
4490 11:05:08.196559 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4491 11:05:08.203301 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4492 11:05:08.203812 == TX Byte 1 ==
4493 11:05:08.206169 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4494 11:05:08.212701 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4495 11:05:08.213251 ==
4496 11:05:08.216032 Dram Type= 6, Freq= 0, CH_1, rank 1
4497 11:05:08.219556 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4498 11:05:08.220075 ==
4499 11:05:08.220407
4500 11:05:08.220744
4501 11:05:08.222435 TX Vref Scan disable
4502 11:05:08.226341 == TX Byte 0 ==
4503 11:05:08.229106 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4504 11:05:08.232565 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4505 11:05:08.235628 == TX Byte 1 ==
4506 11:05:08.239322 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4507 11:05:08.243208 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4508 11:05:08.243721
4509 11:05:08.244049 [DATLAT]
4510 11:05:08.246105 Freq=600, CH1 RK1
4511 11:05:08.246609
4512 11:05:08.248829 DATLAT Default: 0x8
4513 11:05:08.249245 0, 0xFFFF, sum = 0
4514 11:05:08.253023 1, 0xFFFF, sum = 0
4515 11:05:08.253534 2, 0xFFFF, sum = 0
4516 11:05:08.255665 3, 0xFFFF, sum = 0
4517 11:05:08.256082 4, 0xFFFF, sum = 0
4518 11:05:08.258733 5, 0xFFFF, sum = 0
4519 11:05:08.259153 6, 0xFFFF, sum = 0
4520 11:05:08.262136 7, 0x0, sum = 1
4521 11:05:08.262652 8, 0x0, sum = 2
4522 11:05:08.266435 9, 0x0, sum = 3
4523 11:05:08.266965 10, 0x0, sum = 4
4524 11:05:08.267304 best_step = 8
4525 11:05:08.267608
4526 11:05:08.269022 ==
4527 11:05:08.272264 Dram Type= 6, Freq= 0, CH_1, rank 1
4528 11:05:08.275761 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4529 11:05:08.276272 ==
4530 11:05:08.276603 RX Vref Scan: 0
4531 11:05:08.276952
4532 11:05:08.278957 RX Vref 0 -> 0, step: 1
4533 11:05:08.279465
4534 11:05:08.281840 RX Delay -195 -> 252, step: 8
4535 11:05:08.288911 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4536 11:05:08.291698 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4537 11:05:08.295297 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4538 11:05:08.298739 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4539 11:05:08.305046 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4540 11:05:08.308521 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4541 11:05:08.312941 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4542 11:05:08.315957 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4543 11:05:08.318218 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4544 11:05:08.325019 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4545 11:05:08.327666 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4546 11:05:08.331319 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4547 11:05:08.334679 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4548 11:05:08.342024 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4549 11:05:08.344480 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4550 11:05:08.347915 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4551 11:05:08.348434 ==
4552 11:05:08.351650 Dram Type= 6, Freq= 0, CH_1, rank 1
4553 11:05:08.358567 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4554 11:05:08.359136 ==
4555 11:05:08.359590 DQS Delay:
4556 11:05:08.359923 DQS0 = 0, DQS1 = 0
4557 11:05:08.360850 DQM Delay:
4558 11:05:08.361516 DQM0 = 37, DQM1 = 30
4559 11:05:08.364377 DQ Delay:
4560 11:05:08.367455 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4561 11:05:08.370885 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4562 11:05:08.373967 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4563 11:05:08.377380 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4564 11:05:08.377793
4565 11:05:08.378222
4566 11:05:08.384586 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4567 11:05:08.387479 CH1 RK1: MR19=808, MR18=5E5E
4568 11:05:08.394804 CH1_RK1: MR19=0x808, MR18=0x5E5E, DQSOSC=392, MR23=63, INC=170, DEC=113
4569 11:05:08.397475 [RxdqsGatingPostProcess] freq 600
4570 11:05:08.400985 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4571 11:05:08.404149 Pre-setting of DQS Precalculation
4572 11:05:08.410880 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4573 11:05:08.417396 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4574 11:05:08.423590 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4575 11:05:08.424102
4576 11:05:08.424441
4577 11:05:08.428074 [Calibration Summary] 1200 Mbps
4578 11:05:08.430819 CH 0, Rank 0
4579 11:05:08.431292 SW Impedance : PASS
4580 11:05:08.433771 DUTY Scan : NO K
4581 11:05:08.434178 ZQ Calibration : PASS
4582 11:05:08.436512 Jitter Meter : NO K
4583 11:05:08.439869 CBT Training : PASS
4584 11:05:08.440275 Write leveling : PASS
4585 11:05:08.443043 RX DQS gating : PASS
4586 11:05:08.446314 RX DQ/DQS(RDDQC) : PASS
4587 11:05:08.446727 TX DQ/DQS : PASS
4588 11:05:08.450029 RX DATLAT : PASS
4589 11:05:08.453406 RX DQ/DQS(Engine): PASS
4590 11:05:08.453815 TX OE : NO K
4591 11:05:08.456282 All Pass.
4592 11:05:08.456843
4593 11:05:08.457176 CH 0, Rank 1
4594 11:05:08.459575 SW Impedance : PASS
4595 11:05:08.459981 DUTY Scan : NO K
4596 11:05:08.463636 ZQ Calibration : PASS
4597 11:05:08.466959 Jitter Meter : NO K
4598 11:05:08.467468 CBT Training : PASS
4599 11:05:08.470399 Write leveling : PASS
4600 11:05:08.473506 RX DQS gating : PASS
4601 11:05:08.473917 RX DQ/DQS(RDDQC) : PASS
4602 11:05:08.476229 TX DQ/DQS : PASS
4603 11:05:08.479788 RX DATLAT : PASS
4604 11:05:08.480299 RX DQ/DQS(Engine): PASS
4605 11:05:08.483141 TX OE : NO K
4606 11:05:08.483548 All Pass.
4607 11:05:08.483871
4608 11:05:08.487256 CH 1, Rank 0
4609 11:05:08.487661 SW Impedance : PASS
4610 11:05:08.489329 DUTY Scan : NO K
4611 11:05:08.493070 ZQ Calibration : PASS
4612 11:05:08.493496 Jitter Meter : NO K
4613 11:05:08.496098 CBT Training : PASS
4614 11:05:08.499063 Write leveling : PASS
4615 11:05:08.499509 RX DQS gating : PASS
4616 11:05:08.503194 RX DQ/DQS(RDDQC) : PASS
4617 11:05:08.503702 TX DQ/DQS : PASS
4618 11:05:08.506935 RX DATLAT : PASS
4619 11:05:08.510188 RX DQ/DQS(Engine): PASS
4620 11:05:08.510692 TX OE : NO K
4621 11:05:08.513161 All Pass.
4622 11:05:08.513667
4623 11:05:08.513995 CH 1, Rank 1
4624 11:05:08.516558 SW Impedance : PASS
4625 11:05:08.517125 DUTY Scan : NO K
4626 11:05:08.519060 ZQ Calibration : PASS
4627 11:05:08.522608 Jitter Meter : NO K
4628 11:05:08.523115 CBT Training : PASS
4629 11:05:08.525960 Write leveling : PASS
4630 11:05:08.529626 RX DQS gating : PASS
4631 11:05:08.530055 RX DQ/DQS(RDDQC) : PASS
4632 11:05:08.532814 TX DQ/DQS : PASS
4633 11:05:08.535761 RX DATLAT : PASS
4634 11:05:08.536272 RX DQ/DQS(Engine): PASS
4635 11:05:08.538972 TX OE : NO K
4636 11:05:08.539491 All Pass.
4637 11:05:08.539818
4638 11:05:08.542347 DramC Write-DBI off
4639 11:05:08.545740 PER_BANK_REFRESH: Hybrid Mode
4640 11:05:08.546154 TX_TRACKING: ON
4641 11:05:08.556196 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4642 11:05:08.558810 [FAST_K] Save calibration result to emmc
4643 11:05:08.562578 dramc_set_vcore_voltage set vcore to 662500
4644 11:05:08.565419 Read voltage for 933, 3
4645 11:05:08.565926 Vio18 = 0
4646 11:05:08.566415 Vcore = 662500
4647 11:05:08.568506 Vdram = 0
4648 11:05:08.568948 Vddq = 0
4649 11:05:08.569274 Vmddr = 0
4650 11:05:08.575476 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4651 11:05:08.578476 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4652 11:05:08.582355 MEM_TYPE=3, freq_sel=17
4653 11:05:08.585206 sv_algorithm_assistance_LP4_1600
4654 11:05:08.589016 ============ PULL DRAM RESETB DOWN ============
4655 11:05:08.592048 ========== PULL DRAM RESETB DOWN end =========
4656 11:05:08.598857 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4657 11:05:08.602780 ===================================
4658 11:05:08.605351 LPDDR4 DRAM CONFIGURATION
4659 11:05:08.608448 ===================================
4660 11:05:08.609008 EX_ROW_EN[0] = 0x0
4661 11:05:08.612173 EX_ROW_EN[1] = 0x0
4662 11:05:08.612679 LP4Y_EN = 0x0
4663 11:05:08.615539 WORK_FSP = 0x0
4664 11:05:08.616089 WL = 0x3
4665 11:05:08.618854 RL = 0x3
4666 11:05:08.619357 BL = 0x2
4667 11:05:08.621352 RPST = 0x0
4668 11:05:08.621765 RD_PRE = 0x0
4669 11:05:08.624746 WR_PRE = 0x1
4670 11:05:08.625161 WR_PST = 0x0
4671 11:05:08.627869 DBI_WR = 0x0
4672 11:05:08.631255 DBI_RD = 0x0
4673 11:05:08.631667 OTF = 0x1
4674 11:05:08.634854 ===================================
4675 11:05:08.638308 ===================================
4676 11:05:08.638823 ANA top config
4677 11:05:08.641226 ===================================
4678 11:05:08.645099 DLL_ASYNC_EN = 0
4679 11:05:08.648177 ALL_SLAVE_EN = 1
4680 11:05:08.651382 NEW_RANK_MODE = 1
4681 11:05:08.655284 DLL_IDLE_MODE = 1
4682 11:05:08.655802 LP45_APHY_COMB_EN = 1
4683 11:05:08.658226 TX_ODT_DIS = 1
4684 11:05:08.661596 NEW_8X_MODE = 1
4685 11:05:08.664587 ===================================
4686 11:05:08.668022 ===================================
4687 11:05:08.671251 data_rate = 1866
4688 11:05:08.675003 CKR = 1
4689 11:05:08.675512 DQ_P2S_RATIO = 8
4690 11:05:08.677513 ===================================
4691 11:05:08.680865 CA_P2S_RATIO = 8
4692 11:05:08.684527 DQ_CA_OPEN = 0
4693 11:05:08.687468 DQ_SEMI_OPEN = 0
4694 11:05:08.690523 CA_SEMI_OPEN = 0
4695 11:05:08.693943 CA_FULL_RATE = 0
4696 11:05:08.697491 DQ_CKDIV4_EN = 1
4697 11:05:08.697910 CA_CKDIV4_EN = 1
4698 11:05:08.700754 CA_PREDIV_EN = 0
4699 11:05:08.703979 PH8_DLY = 0
4700 11:05:08.707305 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4701 11:05:08.710727 DQ_AAMCK_DIV = 4
4702 11:05:08.713585 CA_AAMCK_DIV = 4
4703 11:05:08.714006 CA_ADMCK_DIV = 4
4704 11:05:08.717518 DQ_TRACK_CA_EN = 0
4705 11:05:08.720991 CA_PICK = 933
4706 11:05:08.723629 CA_MCKIO = 933
4707 11:05:08.727629 MCKIO_SEMI = 0
4708 11:05:08.730045 PLL_FREQ = 3732
4709 11:05:08.733830 DQ_UI_PI_RATIO = 32
4710 11:05:08.734240 CA_UI_PI_RATIO = 0
4711 11:05:08.736608 ===================================
4712 11:05:08.741252 ===================================
4713 11:05:08.743759 memory_type:LPDDR4
4714 11:05:08.747019 GP_NUM : 10
4715 11:05:08.747532 SRAM_EN : 1
4716 11:05:08.750719 MD32_EN : 0
4717 11:05:08.753836 ===================================
4718 11:05:08.756648 [ANA_INIT] >>>>>>>>>>>>>>
4719 11:05:08.759934 <<<<<< [CONFIGURE PHASE]: ANA_TX
4720 11:05:08.763633 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4721 11:05:08.767266 ===================================
4722 11:05:08.767809 data_rate = 1866,PCW = 0X8f00
4723 11:05:08.769921 ===================================
4724 11:05:08.774444 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4725 11:05:08.780786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4726 11:05:08.787494 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4727 11:05:08.789513 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4728 11:05:08.793261 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4729 11:05:08.796279 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4730 11:05:08.799784 [ANA_INIT] flow start
4731 11:05:08.803455 [ANA_INIT] PLL >>>>>>>>
4732 11:05:08.803963 [ANA_INIT] PLL <<<<<<<<
4733 11:05:08.806421 [ANA_INIT] MIDPI >>>>>>>>
4734 11:05:08.810077 [ANA_INIT] MIDPI <<<<<<<<
4735 11:05:08.810587 [ANA_INIT] DLL >>>>>>>>
4736 11:05:08.813124 [ANA_INIT] flow end
4737 11:05:08.816559 ============ LP4 DIFF to SE enter ============
4738 11:05:08.819566 ============ LP4 DIFF to SE exit ============
4739 11:05:08.823110 [ANA_INIT] <<<<<<<<<<<<<
4740 11:05:08.825949 [Flow] Enable top DCM control >>>>>
4741 11:05:08.829285 [Flow] Enable top DCM control <<<<<
4742 11:05:08.832804 Enable DLL master slave shuffle
4743 11:05:08.839715 ==============================================================
4744 11:05:08.840224 Gating Mode config
4745 11:05:08.845915 ==============================================================
4746 11:05:08.849627 Config description:
4747 11:05:08.857412 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4748 11:05:08.862845 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4749 11:05:08.869642 SELPH_MODE 0: By rank 1: By Phase
4750 11:05:08.876368 ==============================================================
4751 11:05:08.876927 GAT_TRACK_EN = 1
4752 11:05:08.878929 RX_GATING_MODE = 2
4753 11:05:08.882570 RX_GATING_TRACK_MODE = 2
4754 11:05:08.885606 SELPH_MODE = 1
4755 11:05:08.889275 PICG_EARLY_EN = 1
4756 11:05:08.892052 VALID_LAT_VALUE = 1
4757 11:05:08.899457 ==============================================================
4758 11:05:08.902417 Enter into Gating configuration >>>>
4759 11:05:08.905986 Exit from Gating configuration <<<<
4760 11:05:08.908659 Enter into DVFS_PRE_config >>>>>
4761 11:05:08.918902 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4762 11:05:08.922564 Exit from DVFS_PRE_config <<<<<
4763 11:05:08.926020 Enter into PICG configuration >>>>
4764 11:05:08.928245 Exit from PICG configuration <<<<
4765 11:05:08.931828 [RX_INPUT] configuration >>>>>
4766 11:05:08.934962 [RX_INPUT] configuration <<<<<
4767 11:05:08.938068 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4768 11:05:08.945213 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4769 11:05:08.951902 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4770 11:05:08.958426 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4771 11:05:08.961594 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4772 11:05:08.968848 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4773 11:05:08.971330 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4774 11:05:08.977868 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4775 11:05:08.981974 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4776 11:05:08.985451 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4777 11:05:08.988504 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4778 11:05:08.994893 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4779 11:05:08.998594 ===================================
4780 11:05:09.001181 LPDDR4 DRAM CONFIGURATION
4781 11:05:09.004537 ===================================
4782 11:05:09.005014 EX_ROW_EN[0] = 0x0
4783 11:05:09.007955 EX_ROW_EN[1] = 0x0
4784 11:05:09.008499 LP4Y_EN = 0x0
4785 11:05:09.010801 WORK_FSP = 0x0
4786 11:05:09.011238 WL = 0x3
4787 11:05:09.014801 RL = 0x3
4788 11:05:09.015360 BL = 0x2
4789 11:05:09.017714 RPST = 0x0
4790 11:05:09.018142 RD_PRE = 0x0
4791 11:05:09.020960 WR_PRE = 0x1
4792 11:05:09.021388 WR_PST = 0x0
4793 11:05:09.024136 DBI_WR = 0x0
4794 11:05:09.024580 DBI_RD = 0x0
4795 11:05:09.027333 OTF = 0x1
4796 11:05:09.030866 ===================================
4797 11:05:09.034227 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4798 11:05:09.037090 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4799 11:05:09.043875 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4800 11:05:09.047144 ===================================
4801 11:05:09.050713 LPDDR4 DRAM CONFIGURATION
4802 11:05:09.053928 ===================================
4803 11:05:09.054440 EX_ROW_EN[0] = 0x10
4804 11:05:09.056863 EX_ROW_EN[1] = 0x0
4805 11:05:09.057280 LP4Y_EN = 0x0
4806 11:05:09.060273 WORK_FSP = 0x0
4807 11:05:09.060826 WL = 0x3
4808 11:05:09.063888 RL = 0x3
4809 11:05:09.064393 BL = 0x2
4810 11:05:09.066829 RPST = 0x0
4811 11:05:09.067352 RD_PRE = 0x0
4812 11:05:09.070023 WR_PRE = 0x1
4813 11:05:09.073393 WR_PST = 0x0
4814 11:05:09.073812 DBI_WR = 0x0
4815 11:05:09.077247 DBI_RD = 0x0
4816 11:05:09.077763 OTF = 0x1
4817 11:05:09.080444 ===================================
4818 11:05:09.087539 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4819 11:05:09.091423 nWR fixed to 30
4820 11:05:09.094469 [ModeRegInit_LP4] CH0 RK0
4821 11:05:09.094999 [ModeRegInit_LP4] CH0 RK1
4822 11:05:09.097126 [ModeRegInit_LP4] CH1 RK0
4823 11:05:09.100407 [ModeRegInit_LP4] CH1 RK1
4824 11:05:09.100986 match AC timing 8
4825 11:05:09.107522 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4826 11:05:09.110008 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4827 11:05:09.113979 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4828 11:05:09.119840 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4829 11:05:09.123689 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4830 11:05:09.124202 ==
4831 11:05:09.127226 Dram Type= 6, Freq= 0, CH_0, rank 0
4832 11:05:09.129640 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4833 11:05:09.130060 ==
4834 11:05:09.137229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4835 11:05:09.143354 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4836 11:05:09.147193 [CA 0] Center 38 (8~69) winsize 62
4837 11:05:09.149522 [CA 1] Center 38 (8~69) winsize 62
4838 11:05:09.153662 [CA 2] Center 36 (6~67) winsize 62
4839 11:05:09.156297 [CA 3] Center 35 (5~66) winsize 62
4840 11:05:09.159846 [CA 4] Center 34 (4~65) winsize 62
4841 11:05:09.163266 [CA 5] Center 34 (4~65) winsize 62
4842 11:05:09.163776
4843 11:05:09.167424 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4844 11:05:09.167936
4845 11:05:09.169651 [CATrainingPosCal] consider 1 rank data
4846 11:05:09.172915 u2DelayCellTimex100 = 270/100 ps
4847 11:05:09.176011 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4848 11:05:09.179254 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4849 11:05:09.183183 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4850 11:05:09.189394 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4851 11:05:09.192101 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4852 11:05:09.195749 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4853 11:05:09.196284
4854 11:05:09.198850 CA PerBit enable=1, Macro0, CA PI delay=34
4855 11:05:09.199276
4856 11:05:09.203371 [CBTSetCACLKResult] CA Dly = 34
4857 11:05:09.203902 CS Dly: 6 (0~37)
4858 11:05:09.204347 ==
4859 11:05:09.206262 Dram Type= 6, Freq= 0, CH_0, rank 1
4860 11:05:09.212218 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4861 11:05:09.212773 ==
4862 11:05:09.216044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4863 11:05:09.222101 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4864 11:05:09.225177 [CA 0] Center 38 (8~69) winsize 62
4865 11:05:09.229152 [CA 1] Center 38 (7~69) winsize 63
4866 11:05:09.232034 [CA 2] Center 36 (6~67) winsize 62
4867 11:05:09.235221 [CA 3] Center 35 (5~66) winsize 62
4868 11:05:09.240127 [CA 4] Center 34 (4~64) winsize 61
4869 11:05:09.242534 [CA 5] Center 34 (4~65) winsize 62
4870 11:05:09.243049
4871 11:05:09.245852 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4872 11:05:09.246369
4873 11:05:09.248603 [CATrainingPosCal] consider 2 rank data
4874 11:05:09.251751 u2DelayCellTimex100 = 270/100 ps
4875 11:05:09.255723 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4876 11:05:09.259409 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4877 11:05:09.265094 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4878 11:05:09.268483 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4879 11:05:09.272113 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4880 11:05:09.275131 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4881 11:05:09.275650
4882 11:05:09.278724 CA PerBit enable=1, Macro0, CA PI delay=34
4883 11:05:09.279242
4884 11:05:09.281747 [CBTSetCACLKResult] CA Dly = 34
4885 11:05:09.285209 CS Dly: 7 (0~39)
4886 11:05:09.285722
4887 11:05:09.288733 ----->DramcWriteLeveling(PI) begin...
4888 11:05:09.289158 ==
4889 11:05:09.291470 Dram Type= 6, Freq= 0, CH_0, rank 0
4890 11:05:09.294605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4891 11:05:09.295021 ==
4892 11:05:09.298274 Write leveling (Byte 0): 27 => 27
4893 11:05:09.301481 Write leveling (Byte 1): 28 => 28
4894 11:05:09.304858 DramcWriteLeveling(PI) end<-----
4895 11:05:09.305376
4896 11:05:09.305797 ==
4897 11:05:09.308287 Dram Type= 6, Freq= 0, CH_0, rank 0
4898 11:05:09.311394 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4899 11:05:09.311953 ==
4900 11:05:09.314606 [Gating] SW mode calibration
4901 11:05:09.321229 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4902 11:05:09.327994 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4903 11:05:09.331843 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4904 11:05:09.334454 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4905 11:05:09.341325 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4906 11:05:09.344322 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4907 11:05:09.348071 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4908 11:05:09.354537 0 10 20 | B1->B0 | 3232 3030 | 0 0 | (0 1) (0 1)
4909 11:05:09.357553 0 10 24 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (1 0)
4910 11:05:09.360688 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4911 11:05:09.367714 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4912 11:05:09.370888 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4913 11:05:09.374645 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4914 11:05:09.381003 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4915 11:05:09.384792 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4916 11:05:09.388034 0 11 20 | B1->B0 | 2828 2929 | 0 0 | (0 0) (0 0)
4917 11:05:09.393497 0 11 24 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4918 11:05:09.397195 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4919 11:05:09.400288 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4920 11:05:09.407461 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4921 11:05:09.410682 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4922 11:05:09.414188 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4923 11:05:09.421066 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4924 11:05:09.423462 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4925 11:05:09.427193 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4926 11:05:09.433685 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4927 11:05:09.436977 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4928 11:05:09.439966 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4929 11:05:09.446626 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4930 11:05:09.450059 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4931 11:05:09.452898 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4932 11:05:09.460755 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 11:05:09.463556 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 11:05:09.466781 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 11:05:09.473209 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 11:05:09.476145 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 11:05:09.479841 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 11:05:09.486343 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 11:05:09.489321 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 11:05:09.492950 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4941 11:05:09.499507 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4942 11:05:09.500026 Total UI for P1: 0, mck2ui 16
4943 11:05:09.506127 best dqsien dly found for B0: ( 0, 14, 20)
4944 11:05:09.506641 Total UI for P1: 0, mck2ui 16
4945 11:05:09.513126 best dqsien dly found for B1: ( 0, 14, 20)
4946 11:05:09.515927 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4947 11:05:09.519216 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4948 11:05:09.519631
4949 11:05:09.523361 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4950 11:05:09.526218 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4951 11:05:09.529249 [Gating] SW calibration Done
4952 11:05:09.529660 ==
4953 11:05:09.532638 Dram Type= 6, Freq= 0, CH_0, rank 0
4954 11:05:09.535950 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4955 11:05:09.536369 ==
4956 11:05:09.538924 RX Vref Scan: 0
4957 11:05:09.539331
4958 11:05:09.539656 RX Vref 0 -> 0, step: 1
4959 11:05:09.539960
4960 11:05:09.542655 RX Delay -80 -> 252, step: 8
4961 11:05:09.549441 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4962 11:05:09.552290 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4963 11:05:09.555612 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4964 11:05:09.559205 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4965 11:05:09.562919 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4966 11:05:09.566143 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
4967 11:05:09.572402 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
4968 11:05:09.575547 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4969 11:05:09.578745 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4970 11:05:09.582749 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4971 11:05:09.586191 iDelay=208, Bit 10, Center 83 (-8 ~ 175) 184
4972 11:05:09.592650 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
4973 11:05:09.595426 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
4974 11:05:09.599213 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4975 11:05:09.601732 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4976 11:05:09.606530 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
4977 11:05:09.607088 ==
4978 11:05:09.609033 Dram Type= 6, Freq= 0, CH_0, rank 0
4979 11:05:09.615497 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4980 11:05:09.616056 ==
4981 11:05:09.616418 DQS Delay:
4982 11:05:09.618149 DQS0 = 0, DQS1 = 0
4983 11:05:09.618601 DQM Delay:
4984 11:05:09.618958 DQM0 = 95, DQM1 = 85
4985 11:05:09.622463 DQ Delay:
4986 11:05:09.624652 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
4987 11:05:09.628265 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
4988 11:05:09.631849 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
4989 11:05:09.635198 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
4990 11:05:09.635612
4991 11:05:09.635936
4992 11:05:09.636239 ==
4993 11:05:09.637810 Dram Type= 6, Freq= 0, CH_0, rank 0
4994 11:05:09.642604 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4995 11:05:09.643120 ==
4996 11:05:09.643453
4997 11:05:09.643753
4998 11:05:09.644511 TX Vref Scan disable
4999 11:05:09.644973 == TX Byte 0 ==
5000 11:05:09.651998 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5001 11:05:09.655862 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5002 11:05:09.658047 == TX Byte 1 ==
5003 11:05:09.661706 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5004 11:05:09.665345 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5005 11:05:09.665858 ==
5006 11:05:09.667852 Dram Type= 6, Freq= 0, CH_0, rank 0
5007 11:05:09.671104 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5008 11:05:09.671646 ==
5009 11:05:09.674385
5010 11:05:09.674925
5011 11:05:09.675285 TX Vref Scan disable
5012 11:05:09.677943 == TX Byte 0 ==
5013 11:05:09.681232 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5014 11:05:09.687968 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5015 11:05:09.688553 == TX Byte 1 ==
5016 11:05:09.691387 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5017 11:05:09.697967 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5018 11:05:09.698488
5019 11:05:09.698820 [DATLAT]
5020 11:05:09.699164 Freq=933, CH0 RK0
5021 11:05:09.699489
5022 11:05:09.701504 DATLAT Default: 0xd
5023 11:05:09.704188 0, 0xFFFF, sum = 0
5024 11:05:09.704610 1, 0xFFFF, sum = 0
5025 11:05:09.707425 2, 0xFFFF, sum = 0
5026 11:05:09.707847 3, 0xFFFF, sum = 0
5027 11:05:09.710891 4, 0xFFFF, sum = 0
5028 11:05:09.711411 5, 0xFFFF, sum = 0
5029 11:05:09.714335 6, 0xFFFF, sum = 0
5030 11:05:09.714850 7, 0xFFFF, sum = 0
5031 11:05:09.717377 8, 0xFFFF, sum = 0
5032 11:05:09.717802 9, 0xFFFF, sum = 0
5033 11:05:09.726868 10, 0x0, sum = 1
5034 11:05:09.727292 11, 0x0, sum = 2
5035 11:05:09.727626 12, 0x0, sum = 3
5036 11:05:09.727936 13, 0x0, sum = 4
5037 11:05:09.728231 best_step = 11
5038 11:05:09.728875
5039 11:05:09.729199 ==
5040 11:05:09.730260 Dram Type= 6, Freq= 0, CH_0, rank 0
5041 11:05:09.733787 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5042 11:05:09.734207 ==
5043 11:05:09.734552 RX Vref Scan: 1
5044 11:05:09.735472
5045 11:05:09.737379 RX Vref 0 -> 0, step: 1
5046 11:05:09.737849
5047 11:05:09.740858 RX Delay -69 -> 252, step: 4
5048 11:05:09.741275
5049 11:05:09.744123 Set Vref, RX VrefLevel [Byte0]: 46
5050 11:05:09.748454 [Byte1]: 47
5051 11:05:09.750836
5052 11:05:09.751248 Final RX Vref Byte 0 = 46 to rank0
5053 11:05:09.754460 Final RX Vref Byte 1 = 47 to rank0
5054 11:05:09.757120 Final RX Vref Byte 0 = 46 to rank1
5055 11:05:09.761174 Final RX Vref Byte 1 = 47 to rank1==
5056 11:05:09.763826 Dram Type= 6, Freq= 0, CH_0, rank 0
5057 11:05:09.770891 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5058 11:05:09.771405 ==
5059 11:05:09.771742 DQS Delay:
5060 11:05:09.773691 DQS0 = 0, DQS1 = 0
5061 11:05:09.774123 DQM Delay:
5062 11:05:09.774457 DQM0 = 97, DQM1 = 86
5063 11:05:09.777245 DQ Delay:
5064 11:05:09.779976 DQ0 =92, DQ1 =100, DQ2 =94, DQ3 =94
5065 11:05:09.783747 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5066 11:05:09.786608 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =78
5067 11:05:09.789731 DQ12 =94, DQ13 =94, DQ14 =96, DQ15 =96
5068 11:05:09.790391
5069 11:05:09.790759
5070 11:05:09.796291 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 413 ps
5071 11:05:09.799517 CH0 RK0: MR19=505, MR18=1A1A
5072 11:05:09.806486 CH0_RK0: MR19=0x505, MR18=0x1A1A, DQSOSC=413, MR23=63, INC=63, DEC=42
5073 11:05:09.806785
5074 11:05:09.809445 ----->DramcWriteLeveling(PI) begin...
5075 11:05:09.809694 ==
5076 11:05:09.814448 Dram Type= 6, Freq= 0, CH_0, rank 1
5077 11:05:09.816974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5078 11:05:09.817125 ==
5079 11:05:09.819328 Write leveling (Byte 0): 28 => 28
5080 11:05:09.823494 Write leveling (Byte 1): 28 => 28
5081 11:05:09.826338 DramcWriteLeveling(PI) end<-----
5082 11:05:09.827107
5083 11:05:09.827507 ==
5084 11:05:09.829240 Dram Type= 6, Freq= 0, CH_0, rank 1
5085 11:05:09.832397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5086 11:05:09.835955 ==
5087 11:05:09.836185 [Gating] SW mode calibration
5088 11:05:09.846062 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5089 11:05:09.849811 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5090 11:05:09.852654 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5091 11:05:09.859776 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5092 11:05:09.861996 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5093 11:05:09.865481 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 11:05:09.872553 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 11:05:09.875725 0 10 20 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5096 11:05:09.878777 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5097 11:05:09.885532 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5098 11:05:09.888731 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5099 11:05:09.892375 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5100 11:05:09.898667 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 11:05:09.901729 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 11:05:09.905536 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 11:05:09.912077 0 11 20 | B1->B0 | 2727 3535 | 0 0 | (1 1) (0 0)
5104 11:05:09.914730 0 11 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5105 11:05:09.918345 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5106 11:05:09.924556 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 11:05:09.927937 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5108 11:05:09.931729 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 11:05:09.937887 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 11:05:09.941169 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 11:05:09.945232 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5112 11:05:09.950869 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5113 11:05:09.955166 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 11:05:09.957944 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 11:05:09.964701 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 11:05:09.967707 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 11:05:09.970872 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 11:05:09.977565 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 11:05:09.981152 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 11:05:09.984037 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 11:05:09.991680 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 11:05:09.994037 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 11:05:09.997771 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 11:05:10.005252 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 11:05:10.008217 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 11:05:10.010668 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 11:05:10.017710 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5128 11:05:10.020917 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 11:05:10.024290 Total UI for P1: 0, mck2ui 16
5130 11:05:10.027217 best dqsien dly found for B0: ( 0, 14, 20)
5131 11:05:10.030712 Total UI for P1: 0, mck2ui 16
5132 11:05:10.033833 best dqsien dly found for B1: ( 0, 14, 20)
5133 11:05:10.037471 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5134 11:05:10.040418 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5135 11:05:10.040798
5136 11:05:10.043617 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5137 11:05:10.050470 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5138 11:05:10.050704 [Gating] SW calibration Done
5139 11:05:10.050930 ==
5140 11:05:10.054259 Dram Type= 6, Freq= 0, CH_0, rank 1
5141 11:05:10.060006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5142 11:05:10.060161 ==
5143 11:05:10.060283 RX Vref Scan: 0
5144 11:05:10.060398
5145 11:05:10.063482 RX Vref 0 -> 0, step: 1
5146 11:05:10.063613
5147 11:05:10.066562 RX Delay -80 -> 252, step: 8
5148 11:05:10.069924 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5149 11:05:10.073728 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5150 11:05:10.076746 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5151 11:05:10.080200 iDelay=200, Bit 3, Center 91 (0 ~ 183) 184
5152 11:05:10.087299 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5153 11:05:10.090598 iDelay=200, Bit 5, Center 91 (-8 ~ 191) 200
5154 11:05:10.093776 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5155 11:05:10.096560 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5156 11:05:10.100228 iDelay=200, Bit 8, Center 71 (-24 ~ 167) 192
5157 11:05:10.102935 iDelay=200, Bit 9, Center 67 (-32 ~ 167) 200
5158 11:05:10.109646 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5159 11:05:10.112804 iDelay=200, Bit 11, Center 75 (-16 ~ 167) 184
5160 11:05:10.116498 iDelay=200, Bit 12, Center 87 (-8 ~ 183) 192
5161 11:05:10.119632 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5162 11:05:10.122844 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5163 11:05:10.129787 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5164 11:05:10.129896 ==
5165 11:05:10.133076 Dram Type= 6, Freq= 0, CH_0, rank 1
5166 11:05:10.136128 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5167 11:05:10.136252 ==
5168 11:05:10.136356 DQS Delay:
5169 11:05:10.139445 DQS0 = 0, DQS1 = 0
5170 11:05:10.139527 DQM Delay:
5171 11:05:10.142881 DQM0 = 97, DQM1 = 83
5172 11:05:10.143206 DQ Delay:
5173 11:05:10.146334 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5174 11:05:10.149634 DQ4 =99, DQ5 =91, DQ6 =103, DQ7 =103
5175 11:05:10.152636 DQ8 =71, DQ9 =67, DQ10 =87, DQ11 =75
5176 11:05:10.156505 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =91
5177 11:05:10.156696
5178 11:05:10.156909
5179 11:05:10.157093 ==
5180 11:05:10.159872 Dram Type= 6, Freq= 0, CH_0, rank 1
5181 11:05:10.163179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5182 11:05:10.166185 ==
5183 11:05:10.166375
5184 11:05:10.166572
5185 11:05:10.166758 TX Vref Scan disable
5186 11:05:10.169815 == TX Byte 0 ==
5187 11:05:10.173710 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5188 11:05:10.176537 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5189 11:05:10.179178 == TX Byte 1 ==
5190 11:05:10.182556 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5191 11:05:10.186401 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5192 11:05:10.189620 ==
5193 11:05:10.189809 Dram Type= 6, Freq= 0, CH_0, rank 1
5194 11:05:10.195771 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5195 11:05:10.195974 ==
5196 11:05:10.196126
5197 11:05:10.196266
5198 11:05:10.199258 TX Vref Scan disable
5199 11:05:10.199448 == TX Byte 0 ==
5200 11:05:10.205442 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5201 11:05:10.208677 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5202 11:05:10.208849 == TX Byte 1 ==
5203 11:05:10.215257 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5204 11:05:10.218854 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5205 11:05:10.218973
5206 11:05:10.219066 [DATLAT]
5207 11:05:10.221902 Freq=933, CH0 RK1
5208 11:05:10.222026
5209 11:05:10.222108 DATLAT Default: 0xb
5210 11:05:10.225218 0, 0xFFFF, sum = 0
5211 11:05:10.225328 1, 0xFFFF, sum = 0
5212 11:05:10.228332 2, 0xFFFF, sum = 0
5213 11:05:10.228432 3, 0xFFFF, sum = 0
5214 11:05:10.232149 4, 0xFFFF, sum = 0
5215 11:05:10.234999 5, 0xFFFF, sum = 0
5216 11:05:10.235088 6, 0xFFFF, sum = 0
5217 11:05:10.238837 7, 0xFFFF, sum = 0
5218 11:05:10.238927 8, 0xFFFF, sum = 0
5219 11:05:10.241624 9, 0xFFFF, sum = 0
5220 11:05:10.241709 10, 0x0, sum = 1
5221 11:05:10.245107 11, 0x0, sum = 2
5222 11:05:10.245191 12, 0x0, sum = 3
5223 11:05:10.245276 13, 0x0, sum = 4
5224 11:05:10.248968 best_step = 11
5225 11:05:10.249050
5226 11:05:10.249134 ==
5227 11:05:10.252065 Dram Type= 6, Freq= 0, CH_0, rank 1
5228 11:05:10.255177 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5229 11:05:10.255261 ==
5230 11:05:10.258615 RX Vref Scan: 0
5231 11:05:10.258696
5232 11:05:10.262751 RX Vref 0 -> 0, step: 1
5233 11:05:10.262832
5234 11:05:10.262916 RX Delay -77 -> 252, step: 4
5235 11:05:10.269442 iDelay=199, Bit 0, Center 94 (7 ~ 182) 176
5236 11:05:10.272870 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5237 11:05:10.275542 iDelay=199, Bit 2, Center 96 (7 ~ 186) 180
5238 11:05:10.279581 iDelay=199, Bit 3, Center 90 (3 ~ 178) 176
5239 11:05:10.282574 iDelay=199, Bit 4, Center 102 (15 ~ 190) 176
5240 11:05:10.286360 iDelay=199, Bit 5, Center 90 (-5 ~ 186) 192
5241 11:05:10.293504 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5242 11:05:10.296305 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5243 11:05:10.299125 iDelay=199, Bit 8, Center 74 (-13 ~ 162) 176
5244 11:05:10.302266 iDelay=199, Bit 9, Center 74 (-13 ~ 162) 176
5245 11:05:10.305453 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5246 11:05:10.312908 iDelay=199, Bit 11, Center 76 (-9 ~ 162) 172
5247 11:05:10.315535 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5248 11:05:10.318957 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5249 11:05:10.322223 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5250 11:05:10.326839 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5251 11:05:10.327247 ==
5252 11:05:10.329086 Dram Type= 6, Freq= 0, CH_0, rank 1
5253 11:05:10.336992 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5254 11:05:10.337505 ==
5255 11:05:10.337816 DQS Delay:
5256 11:05:10.338797 DQS0 = 0, DQS1 = 0
5257 11:05:10.339179 DQM Delay:
5258 11:05:10.339486 DQM0 = 97, DQM1 = 86
5259 11:05:10.342176 DQ Delay:
5260 11:05:10.346263 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =90
5261 11:05:10.349097 DQ4 =102, DQ5 =90, DQ6 =104, DQ7 =108
5262 11:05:10.353713 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =76
5263 11:05:10.356640 DQ12 =94, DQ13 =92, DQ14 =96, DQ15 =94
5264 11:05:10.357232
5265 11:05:10.357603
5266 11:05:10.362563 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5267 11:05:10.365545 CH0 RK1: MR19=505, MR18=2E2E
5268 11:05:10.372635 CH0_RK1: MR19=0x505, MR18=0x2E2E, DQSOSC=407, MR23=63, INC=65, DEC=43
5269 11:05:10.376628 [RxdqsGatingPostProcess] freq 933
5270 11:05:10.380397 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5271 11:05:10.382050 Pre-setting of DQS Precalculation
5272 11:05:10.389006 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5273 11:05:10.389578 ==
5274 11:05:10.392446 Dram Type= 6, Freq= 0, CH_1, rank 0
5275 11:05:10.395605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5276 11:05:10.396168 ==
5277 11:05:10.402073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5278 11:05:10.409373 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5279 11:05:10.412192 [CA 0] Center 37 (6~68) winsize 63
5280 11:05:10.415107 [CA 1] Center 37 (6~68) winsize 63
5281 11:05:10.418167 [CA 2] Center 35 (5~65) winsize 61
5282 11:05:10.422625 [CA 3] Center 34 (4~65) winsize 62
5283 11:05:10.425439 [CA 4] Center 32 (2~63) winsize 62
5284 11:05:10.428616 [CA 5] Center 33 (2~64) winsize 63
5285 11:05:10.429198
5286 11:05:10.431534 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5287 11:05:10.431992
5288 11:05:10.435329 [CATrainingPosCal] consider 1 rank data
5289 11:05:10.438347 u2DelayCellTimex100 = 270/100 ps
5290 11:05:10.442787 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5291 11:05:10.445323 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5292 11:05:10.448095 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5293 11:05:10.452102 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5294 11:05:10.454907 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5295 11:05:10.461780 CA5 delay=33 (2~64),Diff = 1 PI (6 cell)
5296 11:05:10.462194
5297 11:05:10.465156 CA PerBit enable=1, Macro0, CA PI delay=32
5298 11:05:10.465571
5299 11:05:10.468079 [CBTSetCACLKResult] CA Dly = 32
5300 11:05:10.468491 CS Dly: 5 (0~36)
5301 11:05:10.468869 ==
5302 11:05:10.471749 Dram Type= 6, Freq= 0, CH_1, rank 1
5303 11:05:10.475012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5304 11:05:10.477859 ==
5305 11:05:10.482173 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5306 11:05:10.488547 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5307 11:05:10.491494 [CA 0] Center 37 (6~68) winsize 63
5308 11:05:10.494556 [CA 1] Center 37 (6~68) winsize 63
5309 11:05:10.497867 [CA 2] Center 34 (4~65) winsize 62
5310 11:05:10.500935 [CA 3] Center 34 (4~64) winsize 61
5311 11:05:10.504818 [CA 4] Center 33 (2~64) winsize 63
5312 11:05:10.508259 [CA 5] Center 33 (3~63) winsize 61
5313 11:05:10.508823
5314 11:05:10.511122 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5315 11:05:10.511657
5316 11:05:10.516439 [CATrainingPosCal] consider 2 rank data
5317 11:05:10.518157 u2DelayCellTimex100 = 270/100 ps
5318 11:05:10.522212 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5319 11:05:10.525476 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5320 11:05:10.527295 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5321 11:05:10.534748 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5322 11:05:10.537628 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5323 11:05:10.541132 CA5 delay=33 (3~63),Diff = 1 PI (6 cell)
5324 11:05:10.541584
5325 11:05:10.544785 CA PerBit enable=1, Macro0, CA PI delay=32
5326 11:05:10.545334
5327 11:05:10.547765 [CBTSetCACLKResult] CA Dly = 32
5328 11:05:10.548329 CS Dly: 5 (0~37)
5329 11:05:10.548694
5330 11:05:10.550870 ----->DramcWriteLeveling(PI) begin...
5331 11:05:10.554452 ==
5332 11:05:10.554908 Dram Type= 6, Freq= 0, CH_1, rank 0
5333 11:05:10.561122 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5334 11:05:10.561696 ==
5335 11:05:10.564514 Write leveling (Byte 0): 22 => 22
5336 11:05:10.567886 Write leveling (Byte 1): 23 => 23
5337 11:05:10.571539 DramcWriteLeveling(PI) end<-----
5338 11:05:10.572053
5339 11:05:10.572380 ==
5340 11:05:10.574682 Dram Type= 6, Freq= 0, CH_1, rank 0
5341 11:05:10.577290 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5342 11:05:10.577710 ==
5343 11:05:10.580502 [Gating] SW mode calibration
5344 11:05:10.587454 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5345 11:05:10.590634 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5346 11:05:10.597640 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 11:05:10.600747 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 11:05:10.603856 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 11:05:10.611852 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 11:05:10.613892 0 10 16 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5351 11:05:10.618780 0 10 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5352 11:05:10.623637 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 11:05:10.627282 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 11:05:10.630711 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 11:05:10.637259 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 11:05:10.639737 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 11:05:10.643298 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 11:05:10.650173 0 11 16 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
5359 11:05:10.653314 0 11 20 | B1->B0 | 2626 4444 | 0 0 | (0 0) (0 0)
5360 11:05:10.656195 0 11 24 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
5361 11:05:10.663499 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 11:05:10.666789 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 11:05:10.671503 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 11:05:10.676777 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 11:05:10.679658 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 11:05:10.684349 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5367 11:05:10.690548 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5368 11:05:10.693338 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 11:05:10.697325 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 11:05:10.703395 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 11:05:10.706253 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 11:05:10.709977 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 11:05:10.716203 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 11:05:10.719738 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 11:05:10.723394 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 11:05:10.729584 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 11:05:10.732892 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 11:05:10.735949 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 11:05:10.742797 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 11:05:10.746456 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 11:05:10.749906 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 11:05:10.756646 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5383 11:05:10.760254 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5384 11:05:10.763095 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 11:05:10.765898 Total UI for P1: 0, mck2ui 16
5386 11:05:10.769046 best dqsien dly found for B0: ( 0, 14, 18)
5387 11:05:10.772894 Total UI for P1: 0, mck2ui 16
5388 11:05:10.776005 best dqsien dly found for B1: ( 0, 14, 20)
5389 11:05:10.778971 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5390 11:05:10.782324 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5391 11:05:10.782884
5392 11:05:10.789485 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5393 11:05:10.792334 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5394 11:05:10.795980 [Gating] SW calibration Done
5395 11:05:10.796602 ==
5396 11:05:10.799074 Dram Type= 6, Freq= 0, CH_1, rank 0
5397 11:05:10.802473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5398 11:05:10.803041 ==
5399 11:05:10.803409 RX Vref Scan: 0
5400 11:05:10.803747
5401 11:05:10.806612 RX Vref 0 -> 0, step: 1
5402 11:05:10.807171
5403 11:05:10.809483 RX Delay -80 -> 252, step: 8
5404 11:05:10.812009 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5405 11:05:10.815685 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5406 11:05:10.822122 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5407 11:05:10.825131 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5408 11:05:10.829232 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5409 11:05:10.832459 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5410 11:05:10.835578 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5411 11:05:10.839372 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5412 11:05:10.844991 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5413 11:05:10.848855 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5414 11:05:10.853200 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5415 11:05:10.855160 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5416 11:05:10.859242 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5417 11:05:10.865341 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5418 11:05:10.868479 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5419 11:05:10.871958 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5420 11:05:10.872530 ==
5421 11:05:10.875347 Dram Type= 6, Freq= 0, CH_1, rank 0
5422 11:05:10.878423 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5423 11:05:10.878991 ==
5424 11:05:10.881424 DQS Delay:
5425 11:05:10.881880 DQS0 = 0, DQS1 = 0
5426 11:05:10.885784 DQM Delay:
5427 11:05:10.886346 DQM0 = 94, DQM1 = 86
5428 11:05:10.886717 DQ Delay:
5429 11:05:10.888490 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5430 11:05:10.891539 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =95
5431 11:05:10.894738 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =75
5432 11:05:10.898725 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =95
5433 11:05:10.899288
5434 11:05:10.899657
5435 11:05:10.901036 ==
5436 11:05:10.905486 Dram Type= 6, Freq= 0, CH_1, rank 0
5437 11:05:10.908126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5438 11:05:10.908692 ==
5439 11:05:10.909106
5440 11:05:10.909442
5441 11:05:10.910810 TX Vref Scan disable
5442 11:05:10.911266 == TX Byte 0 ==
5443 11:05:10.918284 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5444 11:05:10.923135 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5445 11:05:10.923703 == TX Byte 1 ==
5446 11:05:10.927915 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5447 11:05:10.930959 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5448 11:05:10.931428 ==
5449 11:05:10.934317 Dram Type= 6, Freq= 0, CH_1, rank 0
5450 11:05:10.938113 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5451 11:05:10.938576 ==
5452 11:05:10.938956
5453 11:05:10.939314
5454 11:05:10.941095 TX Vref Scan disable
5455 11:05:10.944006 == TX Byte 0 ==
5456 11:05:10.948446 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5457 11:05:10.951058 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5458 11:05:10.954420 == TX Byte 1 ==
5459 11:05:10.957440 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5460 11:05:10.961190 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5461 11:05:10.961750
5462 11:05:10.964391 [DATLAT]
5463 11:05:10.965008 Freq=933, CH1 RK0
5464 11:05:10.965386
5465 11:05:10.967742 DATLAT Default: 0xd
5466 11:05:10.968318 0, 0xFFFF, sum = 0
5467 11:05:10.971293 1, 0xFFFF, sum = 0
5468 11:05:10.971863 2, 0xFFFF, sum = 0
5469 11:05:10.974238 3, 0xFFFF, sum = 0
5470 11:05:10.974808 4, 0xFFFF, sum = 0
5471 11:05:10.978459 5, 0xFFFF, sum = 0
5472 11:05:10.979049 6, 0xFFFF, sum = 0
5473 11:05:10.980869 7, 0xFFFF, sum = 0
5474 11:05:10.981335 8, 0xFFFF, sum = 0
5475 11:05:10.984160 9, 0xFFFF, sum = 0
5476 11:05:10.984766 10, 0x0, sum = 1
5477 11:05:10.987849 11, 0x0, sum = 2
5478 11:05:10.988419 12, 0x0, sum = 3
5479 11:05:10.991066 13, 0x0, sum = 4
5480 11:05:10.991634 best_step = 11
5481 11:05:10.992002
5482 11:05:10.992342 ==
5483 11:05:10.994504 Dram Type= 6, Freq= 0, CH_1, rank 0
5484 11:05:11.000349 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5485 11:05:11.000942 ==
5486 11:05:11.001313 RX Vref Scan: 1
5487 11:05:11.001653
5488 11:05:11.004386 RX Vref 0 -> 0, step: 1
5489 11:05:11.004992
5490 11:05:11.007028 RX Delay -69 -> 252, step: 4
5491 11:05:11.007487
5492 11:05:11.011090 Set Vref, RX VrefLevel [Byte0]: 54
5493 11:05:11.014392 [Byte1]: 48
5494 11:05:11.014952
5495 11:05:11.017082 Final RX Vref Byte 0 = 54 to rank0
5496 11:05:11.020996 Final RX Vref Byte 1 = 48 to rank0
5497 11:05:11.024294 Final RX Vref Byte 0 = 54 to rank1
5498 11:05:11.027093 Final RX Vref Byte 1 = 48 to rank1==
5499 11:05:11.030574 Dram Type= 6, Freq= 0, CH_1, rank 0
5500 11:05:11.033767 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5501 11:05:11.034332 ==
5502 11:05:11.036968 DQS Delay:
5503 11:05:11.037423 DQS0 = 0, DQS1 = 0
5504 11:05:11.037787 DQM Delay:
5505 11:05:11.040151 DQM0 = 94, DQM1 = 88
5506 11:05:11.040787 DQ Delay:
5507 11:05:11.043882 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5508 11:05:11.046757 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5509 11:05:11.050584 DQ8 =70, DQ9 =76, DQ10 =90, DQ11 =80
5510 11:05:11.053642 DQ12 =96, DQ13 =100, DQ14 =96, DQ15 =98
5511 11:05:11.054102
5512 11:05:11.054468
5513 11:05:11.063264 [DQSOSCAuto] RK0, (LSB)MR18= 0x3131, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5514 11:05:11.067165 CH1 RK0: MR19=505, MR18=3131
5515 11:05:11.070434 CH1_RK0: MR19=0x505, MR18=0x3131, DQSOSC=406, MR23=63, INC=65, DEC=43
5516 11:05:11.073949
5517 11:05:11.076515 ----->DramcWriteLeveling(PI) begin...
5518 11:05:11.077027 ==
5519 11:05:11.080334 Dram Type= 6, Freq= 0, CH_1, rank 1
5520 11:05:11.083998 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5521 11:05:11.084558 ==
5522 11:05:11.088008 Write leveling (Byte 0): 26 => 26
5523 11:05:11.090467 Write leveling (Byte 1): 26 => 26
5524 11:05:11.093186 DramcWriteLeveling(PI) end<-----
5525 11:05:11.093745
5526 11:05:11.094113 ==
5527 11:05:11.096860 Dram Type= 6, Freq= 0, CH_1, rank 1
5528 11:05:11.100101 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5529 11:05:11.100664 ==
5530 11:05:11.104139 [Gating] SW mode calibration
5531 11:05:11.109945 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5532 11:05:11.116992 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5533 11:05:11.120031 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5534 11:05:11.123491 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5535 11:05:11.129712 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5536 11:05:11.133572 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5537 11:05:11.137074 0 10 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
5538 11:05:11.143954 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5539 11:05:11.146158 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5540 11:05:11.149905 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5541 11:05:11.156877 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5542 11:05:11.160040 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5543 11:05:11.162641 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5544 11:05:11.169940 0 11 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5545 11:05:11.172514 0 11 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
5546 11:05:11.176424 0 11 20 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
5547 11:05:11.182646 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5548 11:05:11.186316 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5549 11:05:11.189416 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5550 11:05:11.195979 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5551 11:05:11.199445 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5552 11:05:11.202872 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5553 11:05:11.209042 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5554 11:05:11.212308 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5555 11:05:11.215638 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5556 11:05:11.222465 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5557 11:05:11.225562 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5558 11:05:11.228340 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5559 11:05:11.235273 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5560 11:05:11.238457 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5561 11:05:11.242064 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 11:05:11.249198 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 11:05:11.252284 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 11:05:11.254958 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 11:05:11.261761 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 11:05:11.265627 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 11:05:11.268689 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 11:05:11.275746 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 11:05:11.278736 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5570 11:05:11.281882 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 11:05:11.285225 Total UI for P1: 0, mck2ui 16
5572 11:05:11.288788 best dqsien dly found for B0: ( 0, 14, 16)
5573 11:05:11.291778 Total UI for P1: 0, mck2ui 16
5574 11:05:11.294968 best dqsien dly found for B1: ( 0, 14, 16)
5575 11:05:11.298111 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5576 11:05:11.302000 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5577 11:05:11.302548
5578 11:05:11.305570 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5579 11:05:11.312451 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5580 11:05:11.313105 [Gating] SW calibration Done
5581 11:05:11.314892 ==
5582 11:05:11.315438 Dram Type= 6, Freq= 0, CH_1, rank 1
5583 11:05:11.321452 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5584 11:05:11.322006 ==
5585 11:05:11.322376 RX Vref Scan: 0
5586 11:05:11.322714
5587 11:05:11.324331 RX Vref 0 -> 0, step: 1
5588 11:05:11.324861
5589 11:05:11.328072 RX Delay -80 -> 252, step: 8
5590 11:05:11.331069 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5591 11:05:11.334882 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5592 11:05:11.337495 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5593 11:05:11.344638 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5594 11:05:11.348498 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5595 11:05:11.351150 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5596 11:05:11.354205 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5597 11:05:11.357821 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5598 11:05:11.361100 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5599 11:05:11.367704 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5600 11:05:11.371569 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5601 11:05:11.374204 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5602 11:05:11.378316 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5603 11:05:11.382354 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5604 11:05:11.384464 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5605 11:05:11.390888 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5606 11:05:11.391434 ==
5607 11:05:11.394033 Dram Type= 6, Freq= 0, CH_1, rank 1
5608 11:05:11.397106 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5609 11:05:11.397717 ==
5610 11:05:11.398082 DQS Delay:
5611 11:05:11.401698 DQS0 = 0, DQS1 = 0
5612 11:05:11.402250 DQM Delay:
5613 11:05:11.403820 DQM0 = 98, DQM1 = 87
5614 11:05:11.404271 DQ Delay:
5615 11:05:11.407168 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =95
5616 11:05:11.410239 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5617 11:05:11.413476 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =75
5618 11:05:11.417642 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =91
5619 11:05:11.418184
5620 11:05:11.418543
5621 11:05:11.418877 ==
5622 11:05:11.420112 Dram Type= 6, Freq= 0, CH_1, rank 1
5623 11:05:11.427262 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5624 11:05:11.427813 ==
5625 11:05:11.428177
5626 11:05:11.428511
5627 11:05:11.428888 TX Vref Scan disable
5628 11:05:11.429791 == TX Byte 0 ==
5629 11:05:11.433962 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5630 11:05:11.440151 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5631 11:05:11.440702 == TX Byte 1 ==
5632 11:05:11.443557 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5633 11:05:11.450273 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5634 11:05:11.450825 ==
5635 11:05:11.453362 Dram Type= 6, Freq= 0, CH_1, rank 1
5636 11:05:11.456639 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5637 11:05:11.457145 ==
5638 11:05:11.457512
5639 11:05:11.457844
5640 11:05:11.459495 TX Vref Scan disable
5641 11:05:11.459942 == TX Byte 0 ==
5642 11:05:11.466420 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5643 11:05:11.469719 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5644 11:05:11.472801 == TX Byte 1 ==
5645 11:05:11.476901 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5646 11:05:11.479770 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5647 11:05:11.480318
5648 11:05:11.480678 [DATLAT]
5649 11:05:11.483097 Freq=933, CH1 RK1
5650 11:05:11.483549
5651 11:05:11.487443 DATLAT Default: 0xb
5652 11:05:11.487994 0, 0xFFFF, sum = 0
5653 11:05:11.489767 1, 0xFFFF, sum = 0
5654 11:05:11.490230 2, 0xFFFF, sum = 0
5655 11:05:11.492579 3, 0xFFFF, sum = 0
5656 11:05:11.493090 4, 0xFFFF, sum = 0
5657 11:05:11.496096 5, 0xFFFF, sum = 0
5658 11:05:11.496589 6, 0xFFFF, sum = 0
5659 11:05:11.501006 7, 0xFFFF, sum = 0
5660 11:05:11.501559 8, 0xFFFF, sum = 0
5661 11:05:11.503075 9, 0xFFFF, sum = 0
5662 11:05:11.503532 10, 0x0, sum = 1
5663 11:05:11.505907 11, 0x0, sum = 2
5664 11:05:11.506366 12, 0x0, sum = 3
5665 11:05:11.509485 13, 0x0, sum = 4
5666 11:05:11.510046 best_step = 11
5667 11:05:11.510403
5668 11:05:11.510733 ==
5669 11:05:11.512652 Dram Type= 6, Freq= 0, CH_1, rank 1
5670 11:05:11.515955 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5671 11:05:11.516412 ==
5672 11:05:11.519479 RX Vref Scan: 0
5673 11:05:11.520024
5674 11:05:11.522742 RX Vref 0 -> 0, step: 1
5675 11:05:11.523195
5676 11:05:11.523556 RX Delay -69 -> 252, step: 4
5677 11:05:11.530622 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5678 11:05:11.533757 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5679 11:05:11.537203 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5680 11:05:11.541010 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5681 11:05:11.543886 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5682 11:05:11.547245 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5683 11:05:11.553544 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5684 11:05:11.556812 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5685 11:05:11.560540 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5686 11:05:11.564324 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5687 11:05:11.567364 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5688 11:05:11.574041 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5689 11:05:11.577176 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5690 11:05:11.580660 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5691 11:05:11.583642 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5692 11:05:11.587398 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5693 11:05:11.587947 ==
5694 11:05:11.590798 Dram Type= 6, Freq= 0, CH_1, rank 1
5695 11:05:11.596864 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5696 11:05:11.597423 ==
5697 11:05:11.597794 DQS Delay:
5698 11:05:11.600965 DQS0 = 0, DQS1 = 0
5699 11:05:11.601425 DQM Delay:
5700 11:05:11.601790 DQM0 = 96, DQM1 = 87
5701 11:05:11.603665 DQ Delay:
5702 11:05:11.607280 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92
5703 11:05:11.610157 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =94
5704 11:05:11.613850 DQ8 =74, DQ9 =74, DQ10 =86, DQ11 =80
5705 11:05:11.616886 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5706 11:05:11.617349
5707 11:05:11.617709
5708 11:05:11.623806 [DQSOSCAuto] RK1, (LSB)MR18= 0x2424, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5709 11:05:11.627214 CH1 RK1: MR19=505, MR18=2424
5710 11:05:11.633376 CH1_RK1: MR19=0x505, MR18=0x2424, DQSOSC=410, MR23=63, INC=64, DEC=42
5711 11:05:11.636814 [RxdqsGatingPostProcess] freq 933
5712 11:05:11.641105 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5713 11:05:11.644255 Pre-setting of DQS Precalculation
5714 11:05:11.650956 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5715 11:05:11.656918 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5716 11:05:11.663730 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5717 11:05:11.664284
5718 11:05:11.664645
5719 11:05:11.666650 [Calibration Summary] 1866 Mbps
5720 11:05:11.669615 CH 0, Rank 0
5721 11:05:11.670067 SW Impedance : PASS
5722 11:05:11.673246 DUTY Scan : NO K
5723 11:05:11.673698 ZQ Calibration : PASS
5724 11:05:11.677094 Jitter Meter : NO K
5725 11:05:11.680025 CBT Training : PASS
5726 11:05:11.680576 Write leveling : PASS
5727 11:05:11.682882 RX DQS gating : PASS
5728 11:05:11.686590 RX DQ/DQS(RDDQC) : PASS
5729 11:05:11.687158 TX DQ/DQS : PASS
5730 11:05:11.689813 RX DATLAT : PASS
5731 11:05:11.692933 RX DQ/DQS(Engine): PASS
5732 11:05:11.693412 TX OE : NO K
5733 11:05:11.697202 All Pass.
5734 11:05:11.697768
5735 11:05:11.698134 CH 0, Rank 1
5736 11:05:11.699838 SW Impedance : PASS
5737 11:05:11.700294 DUTY Scan : NO K
5738 11:05:11.705419 ZQ Calibration : PASS
5739 11:05:11.706539 Jitter Meter : NO K
5740 11:05:11.707001 CBT Training : PASS
5741 11:05:11.709517 Write leveling : PASS
5742 11:05:11.712963 RX DQS gating : PASS
5743 11:05:11.713514 RX DQ/DQS(RDDQC) : PASS
5744 11:05:11.716009 TX DQ/DQS : PASS
5745 11:05:11.719416 RX DATLAT : PASS
5746 11:05:11.719964 RX DQ/DQS(Engine): PASS
5747 11:05:11.722571 TX OE : NO K
5748 11:05:11.723025 All Pass.
5749 11:05:11.723380
5750 11:05:11.726340 CH 1, Rank 0
5751 11:05:11.726889 SW Impedance : PASS
5752 11:05:11.729012 DUTY Scan : NO K
5753 11:05:11.732274 ZQ Calibration : PASS
5754 11:05:11.732760 Jitter Meter : NO K
5755 11:05:11.737077 CBT Training : PASS
5756 11:05:11.737633 Write leveling : PASS
5757 11:05:11.739441 RX DQS gating : PASS
5758 11:05:11.742369 RX DQ/DQS(RDDQC) : PASS
5759 11:05:11.742827 TX DQ/DQS : PASS
5760 11:05:11.745820 RX DATLAT : PASS
5761 11:05:11.748857 RX DQ/DQS(Engine): PASS
5762 11:05:11.749317 TX OE : NO K
5763 11:05:11.752655 All Pass.
5764 11:05:11.753148
5765 11:05:11.753512 CH 1, Rank 1
5766 11:05:11.756014 SW Impedance : PASS
5767 11:05:11.756469 DUTY Scan : NO K
5768 11:05:11.759306 ZQ Calibration : PASS
5769 11:05:11.762852 Jitter Meter : NO K
5770 11:05:11.763438 CBT Training : PASS
5771 11:05:11.765571 Write leveling : PASS
5772 11:05:11.770619 RX DQS gating : PASS
5773 11:05:11.771167 RX DQ/DQS(RDDQC) : PASS
5774 11:05:11.772763 TX DQ/DQS : PASS
5775 11:05:11.775835 RX DATLAT : PASS
5776 11:05:11.776388 RX DQ/DQS(Engine): PASS
5777 11:05:11.779667 TX OE : NO K
5778 11:05:11.780220 All Pass.
5779 11:05:11.780587
5780 11:05:11.782880 DramC Write-DBI off
5781 11:05:11.785642 PER_BANK_REFRESH: Hybrid Mode
5782 11:05:11.786192 TX_TRACKING: ON
5783 11:05:11.795273 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5784 11:05:11.799123 [FAST_K] Save calibration result to emmc
5785 11:05:11.802139 dramc_set_vcore_voltage set vcore to 650000
5786 11:05:11.805550 Read voltage for 400, 6
5787 11:05:11.806101 Vio18 = 0
5788 11:05:11.806504 Vcore = 650000
5789 11:05:11.808965 Vdram = 0
5790 11:05:11.809514 Vddq = 0
5791 11:05:11.809882 Vmddr = 0
5792 11:05:11.815127 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5793 11:05:11.818316 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5794 11:05:11.821504 MEM_TYPE=3, freq_sel=20
5795 11:05:11.825501 sv_algorithm_assistance_LP4_800
5796 11:05:11.828302 ============ PULL DRAM RESETB DOWN ============
5797 11:05:11.831662 ========== PULL DRAM RESETB DOWN end =========
5798 11:05:11.838385 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5799 11:05:11.841677 ===================================
5800 11:05:11.844687 LPDDR4 DRAM CONFIGURATION
5801 11:05:11.848227 ===================================
5802 11:05:11.848826 EX_ROW_EN[0] = 0x0
5803 11:05:11.851740 EX_ROW_EN[1] = 0x0
5804 11:05:11.852288 LP4Y_EN = 0x0
5805 11:05:11.855389 WORK_FSP = 0x0
5806 11:05:11.855941 WL = 0x2
5807 11:05:11.858744 RL = 0x2
5808 11:05:11.859292 BL = 0x2
5809 11:05:11.861447 RPST = 0x0
5810 11:05:11.861908 RD_PRE = 0x0
5811 11:05:11.864613 WR_PRE = 0x1
5812 11:05:11.865199 WR_PST = 0x0
5813 11:05:11.868818 DBI_WR = 0x0
5814 11:05:11.869376 DBI_RD = 0x0
5815 11:05:11.872620 OTF = 0x1
5816 11:05:11.875108 ===================================
5817 11:05:11.878194 ===================================
5818 11:05:11.878748 ANA top config
5819 11:05:11.881096 ===================================
5820 11:05:11.885165 DLL_ASYNC_EN = 0
5821 11:05:11.888017 ALL_SLAVE_EN = 1
5822 11:05:11.891308 NEW_RANK_MODE = 1
5823 11:05:11.894140 DLL_IDLE_MODE = 1
5824 11:05:11.894601 LP45_APHY_COMB_EN = 1
5825 11:05:11.898001 TX_ODT_DIS = 1
5826 11:05:11.901337 NEW_8X_MODE = 1
5827 11:05:11.904478 ===================================
5828 11:05:11.907639 ===================================
5829 11:05:11.910740 data_rate = 800
5830 11:05:11.914329 CKR = 1
5831 11:05:11.914878 DQ_P2S_RATIO = 4
5832 11:05:11.917606 ===================================
5833 11:05:11.920971 CA_P2S_RATIO = 4
5834 11:05:11.924622 DQ_CA_OPEN = 0
5835 11:05:11.927685 DQ_SEMI_OPEN = 1
5836 11:05:11.931244 CA_SEMI_OPEN = 1
5837 11:05:11.934193 CA_FULL_RATE = 0
5838 11:05:11.934654 DQ_CKDIV4_EN = 0
5839 11:05:11.937519 CA_CKDIV4_EN = 1
5840 11:05:11.940447 CA_PREDIV_EN = 0
5841 11:05:11.943775 PH8_DLY = 0
5842 11:05:11.947684 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5843 11:05:11.950263 DQ_AAMCK_DIV = 0
5844 11:05:11.950719 CA_AAMCK_DIV = 0
5845 11:05:11.953540 CA_ADMCK_DIV = 4
5846 11:05:11.957163 DQ_TRACK_CA_EN = 0
5847 11:05:11.960449 CA_PICK = 800
5848 11:05:11.963756 CA_MCKIO = 400
5849 11:05:11.967091 MCKIO_SEMI = 400
5850 11:05:11.970671 PLL_FREQ = 3016
5851 11:05:11.973498 DQ_UI_PI_RATIO = 32
5852 11:05:11.973953 CA_UI_PI_RATIO = 32
5853 11:05:11.977588 ===================================
5854 11:05:11.980346 ===================================
5855 11:05:11.983689 memory_type:LPDDR4
5856 11:05:11.986753 GP_NUM : 10
5857 11:05:11.987300 SRAM_EN : 1
5858 11:05:11.990066 MD32_EN : 0
5859 11:05:11.993819 ===================================
5860 11:05:11.997674 [ANA_INIT] >>>>>>>>>>>>>>
5861 11:05:12.000186 <<<<<< [CONFIGURE PHASE]: ANA_TX
5862 11:05:12.003688 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5863 11:05:12.007108 ===================================
5864 11:05:12.007568 data_rate = 800,PCW = 0X7400
5865 11:05:12.010408 ===================================
5866 11:05:12.013545 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5867 11:05:12.019557 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5868 11:05:12.033492 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5869 11:05:12.036669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5870 11:05:12.040164 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5871 11:05:12.042893 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5872 11:05:12.046369 [ANA_INIT] flow start
5873 11:05:12.046931 [ANA_INIT] PLL >>>>>>>>
5874 11:05:12.049856 [ANA_INIT] PLL <<<<<<<<
5875 11:05:12.053210 [ANA_INIT] MIDPI >>>>>>>>
5876 11:05:12.053671 [ANA_INIT] MIDPI <<<<<<<<
5877 11:05:12.057069 [ANA_INIT] DLL >>>>>>>>
5878 11:05:12.059581 [ANA_INIT] flow end
5879 11:05:12.063070 ============ LP4 DIFF to SE enter ============
5880 11:05:12.066231 ============ LP4 DIFF to SE exit ============
5881 11:05:12.069425 [ANA_INIT] <<<<<<<<<<<<<
5882 11:05:12.073471 [Flow] Enable top DCM control >>>>>
5883 11:05:12.076427 [Flow] Enable top DCM control <<<<<
5884 11:05:12.079457 Enable DLL master slave shuffle
5885 11:05:12.086327 ==============================================================
5886 11:05:12.086879 Gating Mode config
5887 11:05:12.092589 ==============================================================
5888 11:05:12.093188 Config description:
5889 11:05:12.103126 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5890 11:05:12.109283 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5891 11:05:12.116166 SELPH_MODE 0: By rank 1: By Phase
5892 11:05:12.119005 ==============================================================
5893 11:05:12.122739 GAT_TRACK_EN = 0
5894 11:05:12.125897 RX_GATING_MODE = 2
5895 11:05:12.129107 RX_GATING_TRACK_MODE = 2
5896 11:05:12.132556 SELPH_MODE = 1
5897 11:05:12.135826 PICG_EARLY_EN = 1
5898 11:05:12.139600 VALID_LAT_VALUE = 1
5899 11:05:12.142779 ==============================================================
5900 11:05:12.145447 Enter into Gating configuration >>>>
5901 11:05:12.149687 Exit from Gating configuration <<<<
5902 11:05:12.152547 Enter into DVFS_PRE_config >>>>>
5903 11:05:12.165667 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5904 11:05:12.168322 Exit from DVFS_PRE_config <<<<<
5905 11:05:12.172266 Enter into PICG configuration >>>>
5906 11:05:12.176018 Exit from PICG configuration <<<<
5907 11:05:12.176565 [RX_INPUT] configuration >>>>>
5908 11:05:12.178657 [RX_INPUT] configuration <<<<<
5909 11:05:12.185213 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5910 11:05:12.188442 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5911 11:05:12.195544 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5912 11:05:12.201705 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5913 11:05:12.208079 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5914 11:05:12.215559 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5915 11:05:12.218179 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5916 11:05:12.221993 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5917 11:05:12.228391 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5918 11:05:12.231866 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5919 11:05:12.235053 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5920 11:05:12.241347 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5921 11:05:12.245067 ===================================
5922 11:05:12.245632 LPDDR4 DRAM CONFIGURATION
5923 11:05:12.247625 ===================================
5924 11:05:12.251471 EX_ROW_EN[0] = 0x0
5925 11:05:12.252020 EX_ROW_EN[1] = 0x0
5926 11:05:12.254506 LP4Y_EN = 0x0
5927 11:05:12.254958 WORK_FSP = 0x0
5928 11:05:12.257628 WL = 0x2
5929 11:05:12.261111 RL = 0x2
5930 11:05:12.261678 BL = 0x2
5931 11:05:12.264431 RPST = 0x0
5932 11:05:12.265148 RD_PRE = 0x0
5933 11:05:12.268402 WR_PRE = 0x1
5934 11:05:12.269039 WR_PST = 0x0
5935 11:05:12.271715 DBI_WR = 0x0
5936 11:05:12.272262 DBI_RD = 0x0
5937 11:05:12.274068 OTF = 0x1
5938 11:05:12.277728 ===================================
5939 11:05:12.281201 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5940 11:05:12.284742 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5941 11:05:12.290978 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5942 11:05:12.294143 ===================================
5943 11:05:12.294712 LPDDR4 DRAM CONFIGURATION
5944 11:05:12.297216 ===================================
5945 11:05:12.300787 EX_ROW_EN[0] = 0x10
5946 11:05:12.301346 EX_ROW_EN[1] = 0x0
5947 11:05:12.304432 LP4Y_EN = 0x0
5948 11:05:12.305029 WORK_FSP = 0x0
5949 11:05:12.307625 WL = 0x2
5950 11:05:12.311128 RL = 0x2
5951 11:05:12.311689 BL = 0x2
5952 11:05:12.314226 RPST = 0x0
5953 11:05:12.314771 RD_PRE = 0x0
5954 11:05:12.318148 WR_PRE = 0x1
5955 11:05:12.318690 WR_PST = 0x0
5956 11:05:12.320610 DBI_WR = 0x0
5957 11:05:12.321207 DBI_RD = 0x0
5958 11:05:12.323732 OTF = 0x1
5959 11:05:12.327066 ===================================
5960 11:05:12.334380 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5961 11:05:12.337052 nWR fixed to 30
5962 11:05:12.337598 [ModeRegInit_LP4] CH0 RK0
5963 11:05:12.340321 [ModeRegInit_LP4] CH0 RK1
5964 11:05:12.343970 [ModeRegInit_LP4] CH1 RK0
5965 11:05:12.344421 [ModeRegInit_LP4] CH1 RK1
5966 11:05:12.347496 match AC timing 18
5967 11:05:12.350748 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5968 11:05:12.353340 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5969 11:05:12.360400 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5970 11:05:12.363641 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5971 11:05:12.370791 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5972 11:05:12.371353 ==
5973 11:05:12.375052 Dram Type= 6, Freq= 0, CH_0, rank 0
5974 11:05:12.376923 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5975 11:05:12.377393 ==
5976 11:05:12.383530 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5977 11:05:12.390184 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5978 11:05:12.390746 [CA 0] Center 36 (8~64) winsize 57
5979 11:05:12.393364 [CA 1] Center 36 (8~64) winsize 57
5980 11:05:12.396588 [CA 2] Center 36 (8~64) winsize 57
5981 11:05:12.400053 [CA 3] Center 36 (8~64) winsize 57
5982 11:05:12.403125 [CA 4] Center 36 (8~64) winsize 57
5983 11:05:12.406790 [CA 5] Center 36 (8~64) winsize 57
5984 11:05:12.407350
5985 11:05:12.410277 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5986 11:05:12.410869
5987 11:05:12.413653 [CATrainingPosCal] consider 1 rank data
5988 11:05:12.416624 u2DelayCellTimex100 = 270/100 ps
5989 11:05:12.420348 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5990 11:05:12.423310 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5991 11:05:12.430115 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
5992 11:05:12.433687 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
5993 11:05:12.436501 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
5994 11:05:12.439430 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
5995 11:05:12.439962
5996 11:05:12.443250 CA PerBit enable=1, Macro0, CA PI delay=36
5997 11:05:12.443815
5998 11:05:12.446339 [CBTSetCACLKResult] CA Dly = 36
5999 11:05:12.446814 CS Dly: 1 (0~32)
6000 11:05:12.449347 ==
6001 11:05:12.452983 Dram Type= 6, Freq= 0, CH_0, rank 1
6002 11:05:12.456355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6003 11:05:12.456971 ==
6004 11:05:12.459465 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6005 11:05:12.466536 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6006 11:05:12.469585 [CA 0] Center 36 (8~64) winsize 57
6007 11:05:12.472408 [CA 1] Center 36 (8~64) winsize 57
6008 11:05:12.476407 [CA 2] Center 36 (8~64) winsize 57
6009 11:05:12.479477 [CA 3] Center 36 (8~64) winsize 57
6010 11:05:12.483120 [CA 4] Center 36 (8~64) winsize 57
6011 11:05:12.486599 [CA 5] Center 36 (8~64) winsize 57
6012 11:05:12.487160
6013 11:05:12.489125 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6014 11:05:12.489584
6015 11:05:12.492313 [CATrainingPosCal] consider 2 rank data
6016 11:05:12.495848 u2DelayCellTimex100 = 270/100 ps
6017 11:05:12.499272 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6018 11:05:12.503096 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6019 11:05:12.506003 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6020 11:05:12.509249 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6021 11:05:12.515833 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6022 11:05:12.519475 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6023 11:05:12.520049
6024 11:05:12.522183 CA PerBit enable=1, Macro0, CA PI delay=36
6025 11:05:12.522644
6026 11:05:12.525343 [CBTSetCACLKResult] CA Dly = 36
6027 11:05:12.525801 CS Dly: 1 (0~32)
6028 11:05:12.526182
6029 11:05:12.529262 ----->DramcWriteLeveling(PI) begin...
6030 11:05:12.529827 ==
6031 11:05:12.532299 Dram Type= 6, Freq= 0, CH_0, rank 0
6032 11:05:12.539565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6033 11:05:12.540180 ==
6034 11:05:12.542013 Write leveling (Byte 0): 32 => 0
6035 11:05:12.545623 Write leveling (Byte 1): 32 => 0
6036 11:05:12.546162 DramcWriteLeveling(PI) end<-----
6037 11:05:12.546534
6038 11:05:12.549339 ==
6039 11:05:12.552360 Dram Type= 6, Freq= 0, CH_0, rank 0
6040 11:05:12.555716 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6041 11:05:12.556277 ==
6042 11:05:12.559764 [Gating] SW mode calibration
6043 11:05:12.566071 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6044 11:05:12.568670 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6045 11:05:12.575128 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6046 11:05:12.578905 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6047 11:05:12.582234 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6048 11:05:12.588473 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6049 11:05:12.592278 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6050 11:05:12.595636 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6051 11:05:12.602215 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6052 11:05:12.604857 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6053 11:05:12.608963 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6054 11:05:12.611680 Total UI for P1: 0, mck2ui 16
6055 11:05:12.614954 best dqsien dly found for B0: ( 0, 10, 16)
6056 11:05:12.618669 Total UI for P1: 0, mck2ui 16
6057 11:05:12.621666 best dqsien dly found for B1: ( 0, 10, 24)
6058 11:05:12.625099 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6059 11:05:12.628377 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6060 11:05:12.628997
6061 11:05:12.635375 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6062 11:05:12.638679 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6063 11:05:12.641623 [Gating] SW calibration Done
6064 11:05:12.642101 ==
6065 11:05:12.644836 Dram Type= 6, Freq= 0, CH_0, rank 0
6066 11:05:12.648241 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6067 11:05:12.648933 ==
6068 11:05:12.649319 RX Vref Scan: 0
6069 11:05:12.649887
6070 11:05:12.651791 RX Vref 0 -> 0, step: 1
6071 11:05:12.652354
6072 11:05:12.655196 RX Delay -410 -> 252, step: 16
6073 11:05:12.659018 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6074 11:05:12.664899 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6075 11:05:12.668503 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6076 11:05:12.671794 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6077 11:05:12.674761 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6078 11:05:12.681137 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6079 11:05:12.684842 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6080 11:05:12.687992 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6081 11:05:12.690959 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6082 11:05:12.698095 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6083 11:05:12.701501 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6084 11:05:12.704888 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6085 11:05:12.707898 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6086 11:05:12.714426 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6087 11:05:12.717514 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6088 11:05:12.720515 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6089 11:05:12.721152 ==
6090 11:05:12.724832 Dram Type= 6, Freq= 0, CH_0, rank 0
6091 11:05:12.730894 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6092 11:05:12.731454 ==
6093 11:05:12.731822 DQS Delay:
6094 11:05:12.733835 DQS0 = 51, DQS1 = 59
6095 11:05:12.734323 DQM Delay:
6096 11:05:12.734690 DQM0 = 12, DQM1 = 15
6097 11:05:12.737609 DQ Delay:
6098 11:05:12.740586 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6099 11:05:12.741221 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6100 11:05:12.744195 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6101 11:05:12.747141 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6102 11:05:12.747637
6103 11:05:12.751052
6104 11:05:12.751510 ==
6105 11:05:12.753913 Dram Type= 6, Freq= 0, CH_0, rank 0
6106 11:05:12.756946 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6107 11:05:12.757408 ==
6108 11:05:12.757776
6109 11:05:12.758113
6110 11:05:12.760179 TX Vref Scan disable
6111 11:05:12.760636 == TX Byte 0 ==
6112 11:05:12.763720 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6113 11:05:12.770330 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6114 11:05:12.770892 == TX Byte 1 ==
6115 11:05:12.773670 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6116 11:05:12.780507 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6117 11:05:12.781125 ==
6118 11:05:12.783885 Dram Type= 6, Freq= 0, CH_0, rank 0
6119 11:05:12.786769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6120 11:05:12.787338 ==
6121 11:05:12.787703
6122 11:05:12.788040
6123 11:05:12.790131 TX Vref Scan disable
6124 11:05:12.790688 == TX Byte 0 ==
6125 11:05:12.796468 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6126 11:05:12.800834 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6127 11:05:12.801305 == TX Byte 1 ==
6128 11:05:12.806750 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6129 11:05:12.810283 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6130 11:05:12.810761
6131 11:05:12.811124 [DATLAT]
6132 11:05:12.813911 Freq=400, CH0 RK0
6133 11:05:12.814374
6134 11:05:12.814735 DATLAT Default: 0xf
6135 11:05:12.817818 0, 0xFFFF, sum = 0
6136 11:05:12.818371 1, 0xFFFF, sum = 0
6137 11:05:12.820796 2, 0xFFFF, sum = 0
6138 11:05:12.821283 3, 0xFFFF, sum = 0
6139 11:05:12.823351 4, 0xFFFF, sum = 0
6140 11:05:12.826244 5, 0xFFFF, sum = 0
6141 11:05:12.826738 6, 0xFFFF, sum = 0
6142 11:05:12.829786 7, 0xFFFF, sum = 0
6143 11:05:12.830284 8, 0xFFFF, sum = 0
6144 11:05:12.833382 9, 0xFFFF, sum = 0
6145 11:05:12.833861 10, 0xFFFF, sum = 0
6146 11:05:12.836402 11, 0xFFFF, sum = 0
6147 11:05:12.836912 12, 0x0, sum = 1
6148 11:05:12.839541 13, 0x0, sum = 2
6149 11:05:12.840051 14, 0x0, sum = 3
6150 11:05:12.843147 15, 0x0, sum = 4
6151 11:05:12.843626 best_step = 13
6152 11:05:12.844124
6153 11:05:12.844756 ==
6154 11:05:12.846963 Dram Type= 6, Freq= 0, CH_0, rank 0
6155 11:05:12.849262 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6156 11:05:12.849863 ==
6157 11:05:12.852702 RX Vref Scan: 1
6158 11:05:12.853353
6159 11:05:12.856532 RX Vref 0 -> 0, step: 1
6160 11:05:12.857016
6161 11:05:12.859054 RX Delay -359 -> 252, step: 8
6162 11:05:12.859500
6163 11:05:12.863178 Set Vref, RX VrefLevel [Byte0]: 46
6164 11:05:12.863649 [Byte1]: 47
6165 11:05:12.868493
6166 11:05:12.868974 Final RX Vref Byte 0 = 46 to rank0
6167 11:05:12.872479 Final RX Vref Byte 1 = 47 to rank0
6168 11:05:12.875355 Final RX Vref Byte 0 = 46 to rank1
6169 11:05:12.878645 Final RX Vref Byte 1 = 47 to rank1==
6170 11:05:12.881646 Dram Type= 6, Freq= 0, CH_0, rank 0
6171 11:05:12.888483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6172 11:05:12.889236 ==
6173 11:05:12.889810 DQS Delay:
6174 11:05:12.892283 DQS0 = 52, DQS1 = 68
6175 11:05:12.892877 DQM Delay:
6176 11:05:12.893225 DQM0 = 10, DQM1 = 17
6177 11:05:12.896042 DQ Delay:
6178 11:05:12.898203 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6179 11:05:12.901456 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6180 11:05:12.901881 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6181 11:05:12.904685 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =28
6182 11:05:12.908849
6183 11:05:12.909357
6184 11:05:12.914945 [DQSOSCAuto] RK0, (LSB)MR18= 0xa2a2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6185 11:05:12.918309 CH0 RK0: MR19=C0C, MR18=A2A2
6186 11:05:12.925017 CH0_RK0: MR19=0xC0C, MR18=0xA2A2, DQSOSC=389, MR23=63, INC=390, DEC=260
6187 11:05:12.925579 ==
6188 11:05:12.929075 Dram Type= 6, Freq= 0, CH_0, rank 1
6189 11:05:12.931120 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6190 11:05:12.931539 ==
6191 11:05:12.934356 [Gating] SW mode calibration
6192 11:05:12.941131 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6193 11:05:12.948240 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6194 11:05:12.951205 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6195 11:05:12.954616 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6196 11:05:12.960676 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6197 11:05:12.964148 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6198 11:05:12.968288 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6199 11:05:12.974880 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6200 11:05:12.977629 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6201 11:05:12.982182 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6202 11:05:12.989000 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6203 11:05:12.989557 Total UI for P1: 0, mck2ui 16
6204 11:05:12.990620 best dqsien dly found for B0: ( 0, 10, 16)
6205 11:05:12.994394 Total UI for P1: 0, mck2ui 16
6206 11:05:12.997728 best dqsien dly found for B1: ( 0, 10, 24)
6207 11:05:13.004219 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6208 11:05:13.007676 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6209 11:05:13.008241
6210 11:05:13.011444 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6211 11:05:13.014568 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6212 11:05:13.017673 [Gating] SW calibration Done
6213 11:05:13.018248 ==
6214 11:05:13.021166 Dram Type= 6, Freq= 0, CH_0, rank 1
6215 11:05:13.023765 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6216 11:05:13.024232 ==
6217 11:05:13.027104 RX Vref Scan: 0
6218 11:05:13.027567
6219 11:05:13.027933 RX Vref 0 -> 0, step: 1
6220 11:05:13.028276
6221 11:05:13.031734 RX Delay -410 -> 252, step: 16
6222 11:05:13.037631 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6223 11:05:13.040933 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6224 11:05:13.045017 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6225 11:05:13.047164 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6226 11:05:13.053819 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6227 11:05:13.056817 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6228 11:05:13.060252 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6229 11:05:13.063559 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6230 11:05:13.069964 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6231 11:05:13.073356 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6232 11:05:13.076776 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6233 11:05:13.080039 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6234 11:05:13.087405 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6235 11:05:13.090432 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6236 11:05:13.093692 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6237 11:05:13.099963 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6238 11:05:13.100530 ==
6239 11:05:13.103312 Dram Type= 6, Freq= 0, CH_0, rank 1
6240 11:05:13.106257 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6241 11:05:13.106724 ==
6242 11:05:13.107090 DQS Delay:
6243 11:05:13.109848 DQS0 = 43, DQS1 = 59
6244 11:05:13.110316 DQM Delay:
6245 11:05:13.113807 DQM0 = 7, DQM1 = 15
6246 11:05:13.114267 DQ Delay:
6247 11:05:13.116474 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6248 11:05:13.119382 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6249 11:05:13.122688 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6250 11:05:13.125936 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6251 11:05:13.126355
6252 11:05:13.126687
6253 11:05:13.126993 ==
6254 11:05:13.129495 Dram Type= 6, Freq= 0, CH_0, rank 1
6255 11:05:13.132732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6256 11:05:13.133358 ==
6257 11:05:13.133707
6258 11:05:13.134018
6259 11:05:13.135873 TX Vref Scan disable
6260 11:05:13.136319 == TX Byte 0 ==
6261 11:05:13.143329 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6262 11:05:13.146233 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6263 11:05:13.146653 == TX Byte 1 ==
6264 11:05:13.152670 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6265 11:05:13.156099 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6266 11:05:13.156608 ==
6267 11:05:13.158996 Dram Type= 6, Freq= 0, CH_0, rank 1
6268 11:05:13.162303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6269 11:05:13.162723 ==
6270 11:05:13.163052
6271 11:05:13.163356
6272 11:05:13.166152 TX Vref Scan disable
6273 11:05:13.168924 == TX Byte 0 ==
6274 11:05:13.172526 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6275 11:05:13.175923 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6276 11:05:13.178945 == TX Byte 1 ==
6277 11:05:13.182785 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6278 11:05:13.185554 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6279 11:05:13.186018
6280 11:05:13.186383 [DATLAT]
6281 11:05:13.188666 Freq=400, CH0 RK1
6282 11:05:13.189176
6283 11:05:13.189541 DATLAT Default: 0xd
6284 11:05:13.193294 0, 0xFFFF, sum = 0
6285 11:05:13.193852 1, 0xFFFF, sum = 0
6286 11:05:13.196385 2, 0xFFFF, sum = 0
6287 11:05:13.196990 3, 0xFFFF, sum = 0
6288 11:05:13.198793 4, 0xFFFF, sum = 0
6289 11:05:13.202238 5, 0xFFFF, sum = 0
6290 11:05:13.202706 6, 0xFFFF, sum = 0
6291 11:05:13.206149 7, 0xFFFF, sum = 0
6292 11:05:13.206710 8, 0xFFFF, sum = 0
6293 11:05:13.208746 9, 0xFFFF, sum = 0
6294 11:05:13.209240 10, 0xFFFF, sum = 0
6295 11:05:13.211979 11, 0xFFFF, sum = 0
6296 11:05:13.212440 12, 0x0, sum = 1
6297 11:05:13.215450 13, 0x0, sum = 2
6298 11:05:13.215911 14, 0x0, sum = 3
6299 11:05:13.218842 15, 0x0, sum = 4
6300 11:05:13.219304 best_step = 13
6301 11:05:13.219664
6302 11:05:13.219998 ==
6303 11:05:13.222327 Dram Type= 6, Freq= 0, CH_0, rank 1
6304 11:05:13.226042 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6305 11:05:13.229185 ==
6306 11:05:13.229640 RX Vref Scan: 0
6307 11:05:13.230013
6308 11:05:13.232244 RX Vref 0 -> 0, step: 1
6309 11:05:13.232538
6310 11:05:13.235701 RX Delay -359 -> 252, step: 8
6311 11:05:13.238556 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6312 11:05:13.244610 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6313 11:05:13.248037 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6314 11:05:13.251322 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6315 11:05:13.258247 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6316 11:05:13.264150 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6317 11:05:13.265068 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6318 11:05:13.268601 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6319 11:05:13.274715 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6320 11:05:13.279353 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6321 11:05:13.281460 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6322 11:05:13.285127 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6323 11:05:13.291473 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6324 11:05:13.294974 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6325 11:05:13.297985 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6326 11:05:13.301796 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6327 11:05:13.304603 ==
6328 11:05:13.307874 Dram Type= 6, Freq= 0, CH_0, rank 1
6329 11:05:13.311336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6330 11:05:13.312019 ==
6331 11:05:13.312571 DQS Delay:
6332 11:05:13.314842 DQS0 = 52, DQS1 = 60
6333 11:05:13.315645 DQM Delay:
6334 11:05:13.317541 DQM0 = 11, DQM1 = 10
6335 11:05:13.318000 DQ Delay:
6336 11:05:13.321733 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =4
6337 11:05:13.324584 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6338 11:05:13.327638 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6339 11:05:13.331085 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6340 11:05:13.331541
6341 11:05:13.331896
6342 11:05:13.337693 [DQSOSCAuto] RK1, (LSB)MR18= 0xb7b7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6343 11:05:13.341470 CH0 RK1: MR19=C0C, MR18=B7B7
6344 11:05:13.347064 CH0_RK1: MR19=0xC0C, MR18=0xB7B7, DQSOSC=387, MR23=63, INC=394, DEC=262
6345 11:05:13.351190 [RxdqsGatingPostProcess] freq 400
6346 11:05:13.357096 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6347 11:05:13.357555 Pre-setting of DQS Precalculation
6348 11:05:13.364573 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6349 11:05:13.365197 ==
6350 11:05:13.368307 Dram Type= 6, Freq= 0, CH_1, rank 0
6351 11:05:13.370439 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6352 11:05:13.370900 ==
6353 11:05:13.377324 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6354 11:05:13.385687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6355 11:05:13.387037 [CA 0] Center 36 (8~64) winsize 57
6356 11:05:13.390826 [CA 1] Center 36 (8~64) winsize 57
6357 11:05:13.393721 [CA 2] Center 36 (8~64) winsize 57
6358 11:05:13.394178 [CA 3] Center 36 (8~64) winsize 57
6359 11:05:13.396979 [CA 4] Center 36 (8~64) winsize 57
6360 11:05:13.400430 [CA 5] Center 36 (8~64) winsize 57
6361 11:05:13.400923
6362 11:05:13.408209 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6363 11:05:13.408826
6364 11:05:13.410124 [CATrainingPosCal] consider 1 rank data
6365 11:05:13.413863 u2DelayCellTimex100 = 270/100 ps
6366 11:05:13.417092 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6367 11:05:13.420854 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6368 11:05:13.423357 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6369 11:05:13.426715 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6370 11:05:13.430486 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6371 11:05:13.433710 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6372 11:05:13.434190
6373 11:05:13.436581 CA PerBit enable=1, Macro0, CA PI delay=36
6374 11:05:13.437106
6375 11:05:13.440061 [CBTSetCACLKResult] CA Dly = 36
6376 11:05:13.443481 CS Dly: 1 (0~32)
6377 11:05:13.443964 ==
6378 11:05:13.446903 Dram Type= 6, Freq= 0, CH_1, rank 1
6379 11:05:13.450209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6380 11:05:13.450737 ==
6381 11:05:13.456187 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6382 11:05:13.462777 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6383 11:05:13.466427 [CA 0] Center 36 (8~64) winsize 57
6384 11:05:13.466885 [CA 1] Center 36 (8~64) winsize 57
6385 11:05:13.471243 [CA 2] Center 36 (8~64) winsize 57
6386 11:05:13.474617 [CA 3] Center 36 (8~64) winsize 57
6387 11:05:13.476368 [CA 4] Center 36 (8~64) winsize 57
6388 11:05:13.480639 [CA 5] Center 36 (8~64) winsize 57
6389 11:05:13.481217
6390 11:05:13.482785 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6391 11:05:13.483237
6392 11:05:13.489357 [CATrainingPosCal] consider 2 rank data
6393 11:05:13.489910 u2DelayCellTimex100 = 270/100 ps
6394 11:05:13.495955 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6395 11:05:13.499589 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6396 11:05:13.502410 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6397 11:05:13.506439 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6398 11:05:13.509152 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6399 11:05:13.512535 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6400 11:05:13.513028
6401 11:05:13.515864 CA PerBit enable=1, Macro0, CA PI delay=36
6402 11:05:13.516413
6403 11:05:13.519749 [CBTSetCACLKResult] CA Dly = 36
6404 11:05:13.523315 CS Dly: 1 (0~32)
6405 11:05:13.523861
6406 11:05:13.525845 ----->DramcWriteLeveling(PI) begin...
6407 11:05:13.526423 ==
6408 11:05:13.528864 Dram Type= 6, Freq= 0, CH_1, rank 0
6409 11:05:13.532661 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6410 11:05:13.533169 ==
6411 11:05:13.535489 Write leveling (Byte 0): 32 => 0
6412 11:05:13.539270 Write leveling (Byte 1): 32 => 0
6413 11:05:13.542528 DramcWriteLeveling(PI) end<-----
6414 11:05:13.543001
6415 11:05:13.543362 ==
6416 11:05:13.545422 Dram Type= 6, Freq= 0, CH_1, rank 0
6417 11:05:13.548398 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6418 11:05:13.548910 ==
6419 11:05:13.552406 [Gating] SW mode calibration
6420 11:05:13.558535 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6421 11:05:13.566252 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6422 11:05:13.568339 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6423 11:05:13.572662 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 11:05:13.579168 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 11:05:13.582002 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6426 11:05:13.585220 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 11:05:13.591729 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 11:05:13.595588 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 11:05:13.598587 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6430 11:05:13.605912 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 11:05:13.606464 Total UI for P1: 0, mck2ui 16
6432 11:05:13.611615 best dqsien dly found for B0: ( 0, 10, 16)
6433 11:05:13.612165 Total UI for P1: 0, mck2ui 16
6434 11:05:13.618928 best dqsien dly found for B1: ( 0, 10, 16)
6435 11:05:13.621514 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6436 11:05:13.624522 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6437 11:05:13.625140
6438 11:05:13.627990 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6439 11:05:13.632015 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6440 11:05:13.634606 [Gating] SW calibration Done
6441 11:05:13.635063 ==
6442 11:05:13.637330 Dram Type= 6, Freq= 0, CH_1, rank 0
6443 11:05:13.641269 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6444 11:05:13.641830 ==
6445 11:05:13.644371 RX Vref Scan: 0
6446 11:05:13.644923
6447 11:05:13.648200 RX Vref 0 -> 0, step: 1
6448 11:05:13.648914
6449 11:05:13.649298 RX Delay -410 -> 252, step: 16
6450 11:05:13.654374 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6451 11:05:13.658244 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6452 11:05:13.660842 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6453 11:05:13.664628 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6454 11:05:13.671252 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6455 11:05:13.674259 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6456 11:05:13.677447 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6457 11:05:13.684509 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6458 11:05:13.687648 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6459 11:05:13.690741 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6460 11:05:13.694732 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6461 11:05:13.701743 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6462 11:05:13.704346 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6463 11:05:13.707252 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6464 11:05:13.710955 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6465 11:05:13.717142 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6466 11:05:13.718112 ==
6467 11:05:13.720164 Dram Type= 6, Freq= 0, CH_1, rank 0
6468 11:05:13.723621 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6469 11:05:13.724081 ==
6470 11:05:13.726777 DQS Delay:
6471 11:05:13.727451 DQS0 = 43, DQS1 = 59
6472 11:05:13.727834 DQM Delay:
6473 11:05:13.730742 DQM0 = 6, DQM1 = 15
6474 11:05:13.731309 DQ Delay:
6475 11:05:13.733329 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6476 11:05:13.736673 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6477 11:05:13.741080 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6478 11:05:13.743441 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6479 11:05:13.743950
6480 11:05:13.744401
6481 11:05:13.744798 ==
6482 11:05:13.746830 Dram Type= 6, Freq= 0, CH_1, rank 0
6483 11:05:13.750177 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6484 11:05:13.750742 ==
6485 11:05:13.753466
6486 11:05:13.753925
6487 11:05:13.754468 TX Vref Scan disable
6488 11:05:13.756746 == TX Byte 0 ==
6489 11:05:13.759658 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6490 11:05:13.763159 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6491 11:05:13.767330 == TX Byte 1 ==
6492 11:05:13.770040 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6493 11:05:13.773783 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6494 11:05:13.774239 ==
6495 11:05:13.776354 Dram Type= 6, Freq= 0, CH_1, rank 0
6496 11:05:13.783273 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6497 11:05:13.783833 ==
6498 11:05:13.784192
6499 11:05:13.784499
6500 11:05:13.784871 TX Vref Scan disable
6501 11:05:13.786234 == TX Byte 0 ==
6502 11:05:13.790041 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6503 11:05:13.793336 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6504 11:05:13.796625 == TX Byte 1 ==
6505 11:05:13.800676 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6506 11:05:13.803482 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6507 11:05:13.803956
6508 11:05:13.806553 [DATLAT]
6509 11:05:13.807094 Freq=400, CH1 RK0
6510 11:05:13.807462
6511 11:05:13.809766 DATLAT Default: 0xf
6512 11:05:13.810234 0, 0xFFFF, sum = 0
6513 11:05:13.813376 1, 0xFFFF, sum = 0
6514 11:05:13.813800 2, 0xFFFF, sum = 0
6515 11:05:13.816026 3, 0xFFFF, sum = 0
6516 11:05:13.816525 4, 0xFFFF, sum = 0
6517 11:05:13.820345 5, 0xFFFF, sum = 0
6518 11:05:13.820911 6, 0xFFFF, sum = 0
6519 11:05:13.823150 7, 0xFFFF, sum = 0
6520 11:05:13.826147 8, 0xFFFF, sum = 0
6521 11:05:13.826585 9, 0xFFFF, sum = 0
6522 11:05:13.830297 10, 0xFFFF, sum = 0
6523 11:05:13.830722 11, 0xFFFF, sum = 0
6524 11:05:13.832520 12, 0x0, sum = 1
6525 11:05:13.833021 13, 0x0, sum = 2
6526 11:05:13.835941 14, 0x0, sum = 3
6527 11:05:13.836364 15, 0x0, sum = 4
6528 11:05:13.836748 best_step = 13
6529 11:05:13.837098
6530 11:05:13.839824 ==
6531 11:05:13.842543 Dram Type= 6, Freq= 0, CH_1, rank 0
6532 11:05:13.846335 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6533 11:05:13.846768 ==
6534 11:05:13.847160 RX Vref Scan: 1
6535 11:05:13.847479
6536 11:05:13.849085 RX Vref 0 -> 0, step: 1
6537 11:05:13.849498
6538 11:05:13.852578 RX Delay -359 -> 252, step: 8
6539 11:05:13.853047
6540 11:05:13.856263 Set Vref, RX VrefLevel [Byte0]: 54
6541 11:05:13.859170 [Byte1]: 48
6542 11:05:13.863778
6543 11:05:13.864286 Final RX Vref Byte 0 = 54 to rank0
6544 11:05:13.867123 Final RX Vref Byte 1 = 48 to rank0
6545 11:05:13.869507 Final RX Vref Byte 0 = 54 to rank1
6546 11:05:13.872646 Final RX Vref Byte 1 = 48 to rank1==
6547 11:05:13.875954 Dram Type= 6, Freq= 0, CH_1, rank 0
6548 11:05:13.882605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6549 11:05:13.883117 ==
6550 11:05:13.883452 DQS Delay:
6551 11:05:13.886340 DQS0 = 48, DQS1 = 64
6552 11:05:13.886856 DQM Delay:
6553 11:05:13.887197 DQM0 = 7, DQM1 = 16
6554 11:05:13.889779 DQ Delay:
6555 11:05:13.892944 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6556 11:05:13.893461 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6557 11:05:13.896016 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =8
6558 11:05:13.899431 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6559 11:05:13.899942
6560 11:05:13.902384
6561 11:05:13.909142 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0d0, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6562 11:05:13.912411 CH1 RK0: MR19=C0C, MR18=D0D0
6563 11:05:13.918909 CH1_RK0: MR19=0xC0C, MR18=0xD0D0, DQSOSC=384, MR23=63, INC=400, DEC=267
6564 11:05:13.919397 ==
6565 11:05:13.922957 Dram Type= 6, Freq= 0, CH_1, rank 1
6566 11:05:13.926447 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6567 11:05:13.926868 ==
6568 11:05:13.929097 [Gating] SW mode calibration
6569 11:05:13.935784 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6570 11:05:13.942863 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6571 11:05:13.945285 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6572 11:05:13.949524 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6573 11:05:13.955426 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6574 11:05:13.958435 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6575 11:05:13.962136 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6576 11:05:13.968921 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6577 11:05:13.972330 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6578 11:05:13.976186 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6579 11:05:13.978400 Total UI for P1: 0, mck2ui 16
6580 11:05:13.981906 best dqsien dly found for B0: ( 0, 10, 8)
6581 11:05:13.988796 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6582 11:05:13.989363 Total UI for P1: 0, mck2ui 16
6583 11:05:13.994936 best dqsien dly found for B1: ( 0, 10, 16)
6584 11:05:13.998708 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6585 11:05:14.001194 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6586 11:05:14.001658
6587 11:05:14.004839 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6588 11:05:14.008409 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6589 11:05:14.011367 [Gating] SW calibration Done
6590 11:05:14.011926 ==
6591 11:05:14.015007 Dram Type= 6, Freq= 0, CH_1, rank 1
6592 11:05:14.018368 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6593 11:05:14.018931 ==
6594 11:05:14.021888 RX Vref Scan: 0
6595 11:05:14.022438
6596 11:05:14.022802 RX Vref 0 -> 0, step: 1
6597 11:05:14.023141
6598 11:05:14.024802 RX Delay -410 -> 252, step: 16
6599 11:05:14.031642 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6600 11:05:14.034489 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6601 11:05:14.037480 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6602 11:05:14.041502 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6603 11:05:14.047434 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6604 11:05:14.051159 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6605 11:05:14.055037 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6606 11:05:14.057305 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6607 11:05:14.065463 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6608 11:05:14.067650 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6609 11:05:14.071800 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6610 11:05:14.074952 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6611 11:05:14.081251 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6612 11:05:14.083884 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6613 11:05:14.087955 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6614 11:05:14.094546 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6615 11:05:14.095068 ==
6616 11:05:14.097455 Dram Type= 6, Freq= 0, CH_1, rank 1
6617 11:05:14.100905 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6618 11:05:14.101469 ==
6619 11:05:14.101834 DQS Delay:
6620 11:05:14.104671 DQS0 = 43, DQS1 = 59
6621 11:05:14.105267 DQM Delay:
6622 11:05:14.107356 DQM0 = 10, DQM1 = 18
6623 11:05:14.107918 DQ Delay:
6624 11:05:14.110167 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6625 11:05:14.113715 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6626 11:05:14.117182 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6627 11:05:14.120471 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6628 11:05:14.121073
6629 11:05:14.121497
6630 11:05:14.121836 ==
6631 11:05:14.123320 Dram Type= 6, Freq= 0, CH_1, rank 1
6632 11:05:14.127161 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6633 11:05:14.127770 ==
6634 11:05:14.128149
6635 11:05:14.128486
6636 11:05:14.132208 TX Vref Scan disable
6637 11:05:14.132799 == TX Byte 0 ==
6638 11:05:14.137213 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6639 11:05:14.140755 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6640 11:05:14.141227 == TX Byte 1 ==
6641 11:05:14.146622 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6642 11:05:14.150075 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6643 11:05:14.150497 ==
6644 11:05:14.153671 Dram Type= 6, Freq= 0, CH_1, rank 1
6645 11:05:14.157018 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6646 11:05:14.157439 ==
6647 11:05:14.157998
6648 11:05:14.158380
6649 11:05:14.160001 TX Vref Scan disable
6650 11:05:14.160416 == TX Byte 0 ==
6651 11:05:14.166921 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6652 11:05:14.169977 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6653 11:05:14.170526 == TX Byte 1 ==
6654 11:05:14.176916 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6655 11:05:14.180065 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6656 11:05:14.180482
6657 11:05:14.180890 [DATLAT]
6658 11:05:14.185030 Freq=400, CH1 RK1
6659 11:05:14.185520
6660 11:05:14.185854 DATLAT Default: 0xd
6661 11:05:14.186503 0, 0xFFFF, sum = 0
6662 11:05:14.186840 1, 0xFFFF, sum = 0
6663 11:05:14.190009 2, 0xFFFF, sum = 0
6664 11:05:14.190520 3, 0xFFFF, sum = 0
6665 11:05:14.192941 4, 0xFFFF, sum = 0
6666 11:05:14.193364 5, 0xFFFF, sum = 0
6667 11:05:14.197095 6, 0xFFFF, sum = 0
6668 11:05:14.197616 7, 0xFFFF, sum = 0
6669 11:05:14.199906 8, 0xFFFF, sum = 0
6670 11:05:14.203547 9, 0xFFFF, sum = 0
6671 11:05:14.204109 10, 0xFFFF, sum = 0
6672 11:05:14.207110 11, 0xFFFF, sum = 0
6673 11:05:14.207665 12, 0x0, sum = 1
6674 11:05:14.210026 13, 0x0, sum = 2
6675 11:05:14.210493 14, 0x0, sum = 3
6676 11:05:14.210864 15, 0x0, sum = 4
6677 11:05:14.213904 best_step = 13
6678 11:05:14.214462
6679 11:05:14.214825 ==
6680 11:05:14.216695 Dram Type= 6, Freq= 0, CH_1, rank 1
6681 11:05:14.219464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6682 11:05:14.219925 ==
6683 11:05:14.222870 RX Vref Scan: 0
6684 11:05:14.223399
6685 11:05:14.226119 RX Vref 0 -> 0, step: 1
6686 11:05:14.226587
6687 11:05:14.226949 RX Delay -359 -> 252, step: 8
6688 11:05:14.235042 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6689 11:05:14.238233 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6690 11:05:14.242007 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6691 11:05:14.245621 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6692 11:05:14.252375 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6693 11:05:14.256039 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6694 11:05:14.258331 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6695 11:05:14.261824 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6696 11:05:14.268227 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6697 11:05:14.271269 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6698 11:05:14.274979 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6699 11:05:14.281062 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6700 11:05:14.284778 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6701 11:05:14.288803 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6702 11:05:14.291346 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6703 11:05:14.298033 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6704 11:05:14.298454 ==
6705 11:05:14.301698 Dram Type= 6, Freq= 0, CH_1, rank 1
6706 11:05:14.305024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6707 11:05:14.305527 ==
6708 11:05:14.305868 DQS Delay:
6709 11:05:14.308271 DQS0 = 48, DQS1 = 64
6710 11:05:14.308829 DQM Delay:
6711 11:05:14.312008 DQM0 = 9, DQM1 = 15
6712 11:05:14.312502 DQ Delay:
6713 11:05:14.314667 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6714 11:05:14.318699 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6715 11:05:14.321662 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6716 11:05:14.324798 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6717 11:05:14.325337
6718 11:05:14.325785
6719 11:05:14.331095 [DQSOSCAuto] RK1, (LSB)MR18= 0xa7a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6720 11:05:14.334358 CH1 RK1: MR19=C0C, MR18=A7A7
6721 11:05:14.341149 CH1_RK1: MR19=0xC0C, MR18=0xA7A7, DQSOSC=389, MR23=63, INC=390, DEC=260
6722 11:05:14.344212 [RxdqsGatingPostProcess] freq 400
6723 11:05:14.350690 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6724 11:05:14.354230 Pre-setting of DQS Precalculation
6725 11:05:14.357727 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6726 11:05:14.364876 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6727 11:05:14.371020 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6728 11:05:14.371548
6729 11:05:14.374774
6730 11:05:14.375357 [Calibration Summary] 800 Mbps
6731 11:05:14.377469 CH 0, Rank 0
6732 11:05:14.377927 SW Impedance : PASS
6733 11:05:14.380293 DUTY Scan : NO K
6734 11:05:14.383547 ZQ Calibration : PASS
6735 11:05:14.384004 Jitter Meter : NO K
6736 11:05:14.386901 CBT Training : PASS
6737 11:05:14.390547 Write leveling : PASS
6738 11:05:14.390968 RX DQS gating : PASS
6739 11:05:14.394343 RX DQ/DQS(RDDQC) : PASS
6740 11:05:14.397065 TX DQ/DQS : PASS
6741 11:05:14.397492 RX DATLAT : PASS
6742 11:05:14.400513 RX DQ/DQS(Engine): PASS
6743 11:05:14.403427 TX OE : NO K
6744 11:05:14.403848 All Pass.
6745 11:05:14.404182
6746 11:05:14.404489 CH 0, Rank 1
6747 11:05:14.407219 SW Impedance : PASS
6748 11:05:14.409941 DUTY Scan : NO K
6749 11:05:14.410364 ZQ Calibration : PASS
6750 11:05:14.413709 Jitter Meter : NO K
6751 11:05:14.416694 CBT Training : PASS
6752 11:05:14.417228 Write leveling : NO K
6753 11:05:14.420054 RX DQS gating : PASS
6754 11:05:14.420562 RX DQ/DQS(RDDQC) : PASS
6755 11:05:14.423544 TX DQ/DQS : PASS
6756 11:05:14.427528 RX DATLAT : PASS
6757 11:05:14.427948 RX DQ/DQS(Engine): PASS
6758 11:05:14.429729 TX OE : NO K
6759 11:05:14.430152 All Pass.
6760 11:05:14.430486
6761 11:05:14.433389 CH 1, Rank 0
6762 11:05:14.433805 SW Impedance : PASS
6763 11:05:14.436690 DUTY Scan : NO K
6764 11:05:14.439825 ZQ Calibration : PASS
6765 11:05:14.440242 Jitter Meter : NO K
6766 11:05:14.444186 CBT Training : PASS
6767 11:05:14.446524 Write leveling : PASS
6768 11:05:14.446946 RX DQS gating : PASS
6769 11:05:14.449806 RX DQ/DQS(RDDQC) : PASS
6770 11:05:14.452960 TX DQ/DQS : PASS
6771 11:05:14.453394 RX DATLAT : PASS
6772 11:05:14.456825 RX DQ/DQS(Engine): PASS
6773 11:05:14.460125 TX OE : NO K
6774 11:05:14.460547 All Pass.
6775 11:05:14.460944
6776 11:05:14.461260 CH 1, Rank 1
6777 11:05:14.463092 SW Impedance : PASS
6778 11:05:14.466338 DUTY Scan : NO K
6779 11:05:14.466755 ZQ Calibration : PASS
6780 11:05:14.469734 Jitter Meter : NO K
6781 11:05:14.472929 CBT Training : PASS
6782 11:05:14.473346 Write leveling : NO K
6783 11:05:14.476603 RX DQS gating : PASS
6784 11:05:14.480243 RX DQ/DQS(RDDQC) : PASS
6785 11:05:14.480805 TX DQ/DQS : PASS
6786 11:05:14.483384 RX DATLAT : PASS
6787 11:05:14.483935 RX DQ/DQS(Engine): PASS
6788 11:05:14.485994 TX OE : NO K
6789 11:05:14.486458 All Pass.
6790 11:05:14.486821
6791 11:05:14.490742 DramC Write-DBI off
6792 11:05:14.492702 PER_BANK_REFRESH: Hybrid Mode
6793 11:05:14.493222 TX_TRACKING: ON
6794 11:05:14.502723 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6795 11:05:14.506653 [FAST_K] Save calibration result to emmc
6796 11:05:14.509331 dramc_set_vcore_voltage set vcore to 725000
6797 11:05:14.512694 Read voltage for 1600, 0
6798 11:05:14.513293 Vio18 = 0
6799 11:05:14.516042 Vcore = 725000
6800 11:05:14.516595 Vdram = 0
6801 11:05:14.517076 Vddq = 0
6802 11:05:14.517626 Vmddr = 0
6803 11:05:14.522936 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6804 11:05:14.529246 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6805 11:05:14.529800 MEM_TYPE=3, freq_sel=13
6806 11:05:14.532477 sv_algorithm_assistance_LP4_3733
6807 11:05:14.535563 ============ PULL DRAM RESETB DOWN ============
6808 11:05:14.542081 ========== PULL DRAM RESETB DOWN end =========
6809 11:05:14.546424 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6810 11:05:14.548993 ===================================
6811 11:05:14.552455 LPDDR4 DRAM CONFIGURATION
6812 11:05:14.555381 ===================================
6813 11:05:14.555939 EX_ROW_EN[0] = 0x0
6814 11:05:14.558546 EX_ROW_EN[1] = 0x0
6815 11:05:14.562565 LP4Y_EN = 0x0
6816 11:05:14.563116 WORK_FSP = 0x1
6817 11:05:14.565770 WL = 0x5
6818 11:05:14.566247 RL = 0x5
6819 11:05:14.569051 BL = 0x2
6820 11:05:14.569509 RPST = 0x0
6821 11:05:14.572466 RD_PRE = 0x0
6822 11:05:14.572965 WR_PRE = 0x1
6823 11:05:14.575468 WR_PST = 0x1
6824 11:05:14.576060 DBI_WR = 0x0
6825 11:05:14.578835 DBI_RD = 0x0
6826 11:05:14.579400 OTF = 0x1
6827 11:05:14.582337 ===================================
6828 11:05:14.586005 ===================================
6829 11:05:14.589477 ANA top config
6830 11:05:14.592009 ===================================
6831 11:05:14.592562 DLL_ASYNC_EN = 0
6832 11:05:14.595149 ALL_SLAVE_EN = 0
6833 11:05:14.599081 NEW_RANK_MODE = 1
6834 11:05:14.602061 DLL_IDLE_MODE = 1
6835 11:05:14.605756 LP45_APHY_COMB_EN = 1
6836 11:05:14.606306 TX_ODT_DIS = 0
6837 11:05:14.608548 NEW_8X_MODE = 1
6838 11:05:14.611858 ===================================
6839 11:05:14.615342 ===================================
6840 11:05:14.618673 data_rate = 3200
6841 11:05:14.622260 CKR = 1
6842 11:05:14.625210 DQ_P2S_RATIO = 8
6843 11:05:14.628228 ===================================
6844 11:05:14.632551 CA_P2S_RATIO = 8
6845 11:05:14.633138 DQ_CA_OPEN = 0
6846 11:05:14.634926 DQ_SEMI_OPEN = 0
6847 11:05:14.638184 CA_SEMI_OPEN = 0
6848 11:05:14.642108 CA_FULL_RATE = 0
6849 11:05:14.644597 DQ_CKDIV4_EN = 0
6850 11:05:14.648240 CA_CKDIV4_EN = 0
6851 11:05:14.648893 CA_PREDIV_EN = 0
6852 11:05:14.651771 PH8_DLY = 12
6853 11:05:14.654953 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6854 11:05:14.658369 DQ_AAMCK_DIV = 4
6855 11:05:14.660867 CA_AAMCK_DIV = 4
6856 11:05:14.664165 CA_ADMCK_DIV = 4
6857 11:05:14.664622 DQ_TRACK_CA_EN = 0
6858 11:05:14.667870 CA_PICK = 1600
6859 11:05:14.671702 CA_MCKIO = 1600
6860 11:05:14.674271 MCKIO_SEMI = 0
6861 11:05:14.678371 PLL_FREQ = 3068
6862 11:05:14.680893 DQ_UI_PI_RATIO = 32
6863 11:05:14.684447 CA_UI_PI_RATIO = 0
6864 11:05:14.687773 ===================================
6865 11:05:14.691436 ===================================
6866 11:05:14.692052 memory_type:LPDDR4
6867 11:05:14.694187 GP_NUM : 10
6868 11:05:14.697421 SRAM_EN : 1
6869 11:05:14.697879 MD32_EN : 0
6870 11:05:14.701242 ===================================
6871 11:05:14.704446 [ANA_INIT] >>>>>>>>>>>>>>
6872 11:05:14.707831 <<<<<< [CONFIGURE PHASE]: ANA_TX
6873 11:05:14.711308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6874 11:05:14.713923 ===================================
6875 11:05:14.717119 data_rate = 3200,PCW = 0X7600
6876 11:05:14.720536 ===================================
6877 11:05:14.723781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6878 11:05:14.727599 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6879 11:05:14.734407 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6880 11:05:14.737278 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6881 11:05:14.740178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6882 11:05:14.746806 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6883 11:05:14.747225 [ANA_INIT] flow start
6884 11:05:14.751119 [ANA_INIT] PLL >>>>>>>>
6885 11:05:14.751538 [ANA_INIT] PLL <<<<<<<<
6886 11:05:14.754270 [ANA_INIT] MIDPI >>>>>>>>
6887 11:05:14.757356 [ANA_INIT] MIDPI <<<<<<<<
6888 11:05:14.760409 [ANA_INIT] DLL >>>>>>>>
6889 11:05:14.760887 [ANA_INIT] DLL <<<<<<<<
6890 11:05:14.763348 [ANA_INIT] flow end
6891 11:05:14.766908 ============ LP4 DIFF to SE enter ============
6892 11:05:14.770380 ============ LP4 DIFF to SE exit ============
6893 11:05:14.773521 [ANA_INIT] <<<<<<<<<<<<<
6894 11:05:14.776980 [Flow] Enable top DCM control >>>>>
6895 11:05:14.780249 [Flow] Enable top DCM control <<<<<
6896 11:05:14.783763 Enable DLL master slave shuffle
6897 11:05:14.790149 ==============================================================
6898 11:05:14.790629 Gating Mode config
6899 11:05:14.796619 ==============================================================
6900 11:05:14.797155 Config description:
6901 11:05:14.806577 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6902 11:05:14.813279 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6903 11:05:14.819601 SELPH_MODE 0: By rank 1: By Phase
6904 11:05:14.823249 ==============================================================
6905 11:05:14.826614 GAT_TRACK_EN = 1
6906 11:05:14.830300 RX_GATING_MODE = 2
6907 11:05:14.832728 RX_GATING_TRACK_MODE = 2
6908 11:05:14.836627 SELPH_MODE = 1
6909 11:05:14.839103 PICG_EARLY_EN = 1
6910 11:05:14.843771 VALID_LAT_VALUE = 1
6911 11:05:14.849827 ==============================================================
6912 11:05:14.852315 Enter into Gating configuration >>>>
6913 11:05:14.856538 Exit from Gating configuration <<<<
6914 11:05:14.859356 Enter into DVFS_PRE_config >>>>>
6915 11:05:14.868976 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6916 11:05:14.872689 Exit from DVFS_PRE_config <<<<<
6917 11:05:14.876163 Enter into PICG configuration >>>>
6918 11:05:14.879352 Exit from PICG configuration <<<<
6919 11:05:14.882663 [RX_INPUT] configuration >>>>>
6920 11:05:14.885911 [RX_INPUT] configuration <<<<<
6921 11:05:14.889022 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6922 11:05:14.896077 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6923 11:05:14.902125 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6924 11:05:14.905643 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6925 11:05:14.913768 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6926 11:05:14.918804 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6927 11:05:14.922674 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6928 11:05:14.928402 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6929 11:05:14.932412 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6930 11:05:14.935430 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6931 11:05:14.938267 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6932 11:05:14.944762 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6933 11:05:14.948566 ===================================
6934 11:05:14.949031 LPDDR4 DRAM CONFIGURATION
6935 11:05:14.952121 ===================================
6936 11:05:14.955097 EX_ROW_EN[0] = 0x0
6937 11:05:14.959294 EX_ROW_EN[1] = 0x0
6938 11:05:14.959805 LP4Y_EN = 0x0
6939 11:05:14.961304 WORK_FSP = 0x1
6940 11:05:14.961720 WL = 0x5
6941 11:05:14.964792 RL = 0x5
6942 11:05:14.965211 BL = 0x2
6943 11:05:14.967858 RPST = 0x0
6944 11:05:14.968272 RD_PRE = 0x0
6945 11:05:14.971280 WR_PRE = 0x1
6946 11:05:14.971840 WR_PST = 0x1
6947 11:05:14.974560 DBI_WR = 0x0
6948 11:05:14.975044 DBI_RD = 0x0
6949 11:05:14.977826 OTF = 0x1
6950 11:05:14.981527 ===================================
6951 11:05:14.984557 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6952 11:05:14.988340 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6953 11:05:14.995054 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6954 11:05:14.997546 ===================================
6955 11:05:14.998017 LPDDR4 DRAM CONFIGURATION
6956 11:05:15.000938 ===================================
6957 11:05:15.004636 EX_ROW_EN[0] = 0x10
6958 11:05:15.007579 EX_ROW_EN[1] = 0x0
6959 11:05:15.008022 LP4Y_EN = 0x0
6960 11:05:15.010961 WORK_FSP = 0x1
6961 11:05:15.011417 WL = 0x5
6962 11:05:15.014257 RL = 0x5
6963 11:05:15.014735 BL = 0x2
6964 11:05:15.017592 RPST = 0x0
6965 11:05:15.018052 RD_PRE = 0x0
6966 11:05:15.020845 WR_PRE = 0x1
6967 11:05:15.021333 WR_PST = 0x1
6968 11:05:15.024319 DBI_WR = 0x0
6969 11:05:15.024774 DBI_RD = 0x0
6970 11:05:15.027786 OTF = 0x1
6971 11:05:15.030635 ===================================
6972 11:05:15.037429 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6973 11:05:15.037859 ==
6974 11:05:15.041078 Dram Type= 6, Freq= 0, CH_0, rank 0
6975 11:05:15.044911 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6976 11:05:15.045445 ==
6977 11:05:15.047509 [Duty_Offset_Calibration]
6978 11:05:15.047931 B0:0 B1:2 CA:1
6979 11:05:15.048363
6980 11:05:15.050932 [DutyScan_Calibration_Flow] k_type=0
6981 11:05:15.061811
6982 11:05:15.062301 ==CLK 0==
6983 11:05:15.065010 Final CLK duty delay cell = 0
6984 11:05:15.068281 [0] MAX Duty = 5187%(X100), DQS PI = 24
6985 11:05:15.071571 [0] MIN Duty = 4938%(X100), DQS PI = 54
6986 11:05:15.075675 [0] AVG Duty = 5062%(X100)
6987 11:05:15.076200
6988 11:05:15.078229 CH0 CLK Duty spec in!! Max-Min= 249%
6989 11:05:15.082201 [DutyScan_Calibration_Flow] ====Done====
6990 11:05:15.082725
6991 11:05:15.085662 [DutyScan_Calibration_Flow] k_type=1
6992 11:05:15.102070
6993 11:05:15.102644 ==DQS 0 ==
6994 11:05:15.105204 Final DQS duty delay cell = 0
6995 11:05:15.108902 [0] MAX Duty = 5156%(X100), DQS PI = 34
6996 11:05:15.111938 [0] MIN Duty = 5031%(X100), DQS PI = 6
6997 11:05:15.112518 [0] AVG Duty = 5093%(X100)
6998 11:05:15.115209
6999 11:05:15.115800 ==DQS 1 ==
7000 11:05:15.118565 Final DQS duty delay cell = 0
7001 11:05:15.122404 [0] MAX Duty = 5031%(X100), DQS PI = 4
7002 11:05:15.124794 [0] MIN Duty = 4876%(X100), DQS PI = 16
7003 11:05:15.125298 [0] AVG Duty = 4953%(X100)
7004 11:05:15.128108
7005 11:05:15.131635 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7006 11:05:15.132089
7007 11:05:15.134994 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7008 11:05:15.138613 [DutyScan_Calibration_Flow] ====Done====
7009 11:05:15.139068
7010 11:05:15.143560 [DutyScan_Calibration_Flow] k_type=3
7011 11:05:15.158658
7012 11:05:15.159246 ==DQM 0 ==
7013 11:05:15.162473 Final DQM duty delay cell = 0
7014 11:05:15.166119 [0] MAX Duty = 5187%(X100), DQS PI = 24
7015 11:05:15.169062 [0] MIN Duty = 4907%(X100), DQS PI = 56
7016 11:05:15.172242 [0] AVG Duty = 5047%(X100)
7017 11:05:15.172691
7018 11:05:15.173113 ==DQM 1 ==
7019 11:05:15.175996 Final DQM duty delay cell = 0
7020 11:05:15.179951 [0] MAX Duty = 5031%(X100), DQS PI = 52
7021 11:05:15.182089 [0] MIN Duty = 4782%(X100), DQS PI = 14
7022 11:05:15.185064 [0] AVG Duty = 4906%(X100)
7023 11:05:15.185520
7024 11:05:15.188624 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7025 11:05:15.189231
7026 11:05:15.192404 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7027 11:05:15.195097 [DutyScan_Calibration_Flow] ====Done====
7028 11:05:15.195552
7029 11:05:15.198555 [DutyScan_Calibration_Flow] k_type=2
7030 11:05:15.215250
7031 11:05:15.215788 ==DQ 0 ==
7032 11:05:15.219139 Final DQ duty delay cell = 0
7033 11:05:15.222014 [0] MAX Duty = 5218%(X100), DQS PI = 18
7034 11:05:15.225323 [0] MIN Duty = 4969%(X100), DQS PI = 8
7035 11:05:15.225782 [0] AVG Duty = 5093%(X100)
7036 11:05:15.228290
7037 11:05:15.228765 ==DQ 1 ==
7038 11:05:15.232065 Final DQ duty delay cell = -4
7039 11:05:15.235045 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7040 11:05:15.238119 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7041 11:05:15.241346 [-4] AVG Duty = 4953%(X100)
7042 11:05:15.241801
7043 11:05:15.244949 CH0 DQ 0 Duty spec in!! Max-Min= 249%
7044 11:05:15.245407
7045 11:05:15.248253 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7046 11:05:15.251257 [DutyScan_Calibration_Flow] ====Done====
7047 11:05:15.251774 ==
7048 11:05:15.254645 Dram Type= 6, Freq= 0, CH_1, rank 0
7049 11:05:15.257966 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7050 11:05:15.258425 ==
7051 11:05:15.261377 [Duty_Offset_Calibration]
7052 11:05:15.261832 B0:0 B1:4 CA:-5
7053 11:05:15.262190
7054 11:05:15.264183 [DutyScan_Calibration_Flow] k_type=0
7055 11:05:15.276186
7056 11:05:15.276783 ==CLK 0==
7057 11:05:15.278931 Final CLK duty delay cell = 0
7058 11:05:15.282592 [0] MAX Duty = 5156%(X100), DQS PI = 20
7059 11:05:15.285413 [0] MIN Duty = 4875%(X100), DQS PI = 50
7060 11:05:15.288996 [0] AVG Duty = 5015%(X100)
7061 11:05:15.289540
7062 11:05:15.292611 CH1 CLK Duty spec in!! Max-Min= 281%
7063 11:05:15.295945 [DutyScan_Calibration_Flow] ====Done====
7064 11:05:15.296491
7065 11:05:15.299757 [DutyScan_Calibration_Flow] k_type=1
7066 11:05:15.314985
7067 11:05:15.315527 ==DQS 0 ==
7068 11:05:15.318042 Final DQS duty delay cell = 0
7069 11:05:15.321266 [0] MAX Duty = 5187%(X100), DQS PI = 18
7070 11:05:15.324678 [0] MIN Duty = 4876%(X100), DQS PI = 42
7071 11:05:15.328107 [0] AVG Duty = 5031%(X100)
7072 11:05:15.328557
7073 11:05:15.328970 ==DQS 1 ==
7074 11:05:15.331290 Final DQS duty delay cell = -4
7075 11:05:15.334426 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7076 11:05:15.337553 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7077 11:05:15.341212 [-4] AVG Duty = 4922%(X100)
7078 11:05:15.341816
7079 11:05:15.344042 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7080 11:05:15.344519
7081 11:05:15.347641 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7082 11:05:15.350925 [DutyScan_Calibration_Flow] ====Done====
7083 11:05:15.351399
7084 11:05:15.354153 [DutyScan_Calibration_Flow] k_type=3
7085 11:05:15.370524
7086 11:05:15.371045 ==DQM 0 ==
7087 11:05:15.374060 Final DQM duty delay cell = -4
7088 11:05:15.377903 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7089 11:05:15.380237 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7090 11:05:15.383830 [-4] AVG Duty = 4937%(X100)
7091 11:05:15.384394
7092 11:05:15.384972 ==DQM 1 ==
7093 11:05:15.386595 Final DQM duty delay cell = -4
7094 11:05:15.389840 [-4] MAX Duty = 5093%(X100), DQS PI = 18
7095 11:05:15.393661 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7096 11:05:15.396217 [-4] AVG Duty = 5000%(X100)
7097 11:05:15.396688
7098 11:05:15.400172 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7099 11:05:15.400792
7100 11:05:15.402833 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7101 11:05:15.406104 [DutyScan_Calibration_Flow] ====Done====
7102 11:05:15.406579
7103 11:05:15.409680 [DutyScan_Calibration_Flow] k_type=2
7104 11:05:15.427528
7105 11:05:15.427954 ==DQ 0 ==
7106 11:05:15.431635 Final DQ duty delay cell = 0
7107 11:05:15.434390 [0] MAX Duty = 5093%(X100), DQS PI = 20
7108 11:05:15.437856 [0] MIN Duty = 4938%(X100), DQS PI = 46
7109 11:05:15.438115 [0] AVG Duty = 5015%(X100)
7110 11:05:15.441050
7111 11:05:15.441277 ==DQ 1 ==
7112 11:05:15.444034 Final DQ duty delay cell = 0
7113 11:05:15.447198 [0] MAX Duty = 5031%(X100), DQS PI = 2
7114 11:05:15.450878 [0] MIN Duty = 4876%(X100), DQS PI = 28
7115 11:05:15.451059 [0] AVG Duty = 4953%(X100)
7116 11:05:15.453941
7117 11:05:15.457476 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7118 11:05:15.457604
7119 11:05:15.460416 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7120 11:05:15.463487 [DutyScan_Calibration_Flow] ====Done====
7121 11:05:15.467000 nWR fixed to 30
7122 11:05:15.467115 [ModeRegInit_LP4] CH0 RK0
7123 11:05:15.470607 [ModeRegInit_LP4] CH0 RK1
7124 11:05:15.473534 [ModeRegInit_LP4] CH1 RK0
7125 11:05:15.477146 [ModeRegInit_LP4] CH1 RK1
7126 11:05:15.477258 match AC timing 4
7127 11:05:15.484373 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7128 11:05:15.487400 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7129 11:05:15.490615 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7130 11:05:15.496799 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7131 11:05:15.500643 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7132 11:05:15.500765 [MiockJmeterHQA]
7133 11:05:15.500855
7134 11:05:15.503505 [DramcMiockJmeter] u1RxGatingPI = 0
7135 11:05:15.507140 0 : 4366, 4137
7136 11:05:15.507557 4 : 4363, 4137
7137 11:05:15.510555 8 : 4250, 4024
7138 11:05:15.511066 12 : 4368, 4140
7139 11:05:15.511403 16 : 4253, 4026
7140 11:05:15.514588 20 : 4255, 4030
7141 11:05:15.515111 24 : 4363, 4137
7142 11:05:15.516926 28 : 4253, 4026
7143 11:05:15.517341 32 : 4368, 4140
7144 11:05:15.520746 36 : 4250, 4026
7145 11:05:15.521233 40 : 4252, 4026
7146 11:05:15.524594 44 : 4250, 4027
7147 11:05:15.525153 48 : 4255, 4029
7148 11:05:15.525493 52 : 4249, 4027
7149 11:05:15.527711 56 : 4250, 4026
7150 11:05:15.528226 60 : 4363, 4140
7151 11:05:15.530345 64 : 4253, 4030
7152 11:05:15.530763 68 : 4250, 4027
7153 11:05:15.534424 72 : 4251, 4027
7154 11:05:15.534989 76 : 4360, 4137
7155 11:05:15.536893 80 : 4250, 4026
7156 11:05:15.537357 84 : 4361, 4137
7157 11:05:15.537899 88 : 4250, 4027
7158 11:05:15.540308 92 : 4361, 4138
7159 11:05:15.540796 96 : 4250, 4027
7160 11:05:15.543524 100 : 4250, 2431
7161 11:05:15.543984 104 : 4250, 0
7162 11:05:15.547234 108 : 4252, 0
7163 11:05:15.547793 112 : 4252, 0
7164 11:05:15.548165 116 : 4250, 0
7165 11:05:15.550553 120 : 4253, 0
7166 11:05:15.551023 124 : 4250, 0
7167 11:05:15.553386 128 : 4250, 0
7168 11:05:15.553847 132 : 4252, 0
7169 11:05:15.554212 136 : 4361, 0
7170 11:05:15.557127 140 : 4361, 0
7171 11:05:15.557602 144 : 4250, 0
7172 11:05:15.558092 148 : 4255, 0
7173 11:05:15.560348 152 : 4360, 0
7174 11:05:15.560802 156 : 4250, 0
7175 11:05:15.563202 160 : 4255, 0
7176 11:05:15.563617 164 : 4250, 0
7177 11:05:15.563950 168 : 4250, 0
7178 11:05:15.567043 172 : 4250, 0
7179 11:05:15.567459 176 : 4250, 0
7180 11:05:15.570118 180 : 4250, 0
7181 11:05:15.570534 184 : 4252, 0
7182 11:05:15.570863 188 : 4363, 0
7183 11:05:15.573217 192 : 4360, 0
7184 11:05:15.573680 196 : 4366, 0
7185 11:05:15.576590 200 : 4255, 0
7186 11:05:15.577032 204 : 4361, 0
7187 11:05:15.577363 208 : 4250, 0
7188 11:05:15.579735 212 : 4255, 0
7189 11:05:15.580149 216 : 4250, 0
7190 11:05:15.583351 220 : 4360, 708
7191 11:05:15.583858 224 : 4250, 4012
7192 11:05:15.584191 228 : 4250, 4027
7193 11:05:15.587170 232 : 4250, 4027
7194 11:05:15.587605 236 : 4250, 4027
7195 11:05:15.590134 240 : 4250, 4027
7196 11:05:15.590640 244 : 4250, 4027
7197 11:05:15.592903 248 : 4253, 4029
7198 11:05:15.593320 252 : 4250, 4027
7199 11:05:15.597118 256 : 4360, 4137
7200 11:05:15.597533 260 : 4250, 4026
7201 11:05:15.599729 264 : 4250, 4027
7202 11:05:15.600147 268 : 4250, 4027
7203 11:05:15.603121 272 : 4361, 4137
7204 11:05:15.603607 276 : 4360, 4137
7205 11:05:15.606369 280 : 4250, 4027
7206 11:05:15.606909 284 : 4363, 4140
7207 11:05:15.610358 288 : 4251, 4027
7208 11:05:15.610776 292 : 4250, 4026
7209 11:05:15.611110 296 : 4250, 4026
7210 11:05:15.613146 300 : 4258, 4032
7211 11:05:15.613569 304 : 4250, 4027
7212 11:05:15.616376 308 : 4361, 4137
7213 11:05:15.616946 312 : 4361, 4137
7214 11:05:15.619672 316 : 4250, 4027
7215 11:05:15.620190 320 : 4361, 4138
7216 11:05:15.622998 324 : 4361, 4138
7217 11:05:15.623575 328 : 4363, 4137
7218 11:05:15.627002 332 : 4250, 4027
7219 11:05:15.627466 336 : 4364, 3838
7220 11:05:15.629533 340 : 4250, 1724
7221 11:05:15.630007
7222 11:05:15.630368 MIOCK jitter meter ch=0
7223 11:05:15.630709
7224 11:05:15.633052 1T = (340-104) = 236 dly cells
7225 11:05:15.639869 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7226 11:05:15.640327 ==
7227 11:05:15.644702 Dram Type= 6, Freq= 0, CH_0, rank 0
7228 11:05:15.645838 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7229 11:05:15.646295 ==
7230 11:05:15.652660 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7231 11:05:15.656570 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7232 11:05:15.662942 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7233 11:05:15.666245 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7234 11:05:15.675292 [CA 0] Center 42 (12~73) winsize 62
7235 11:05:15.679061 [CA 1] Center 42 (12~73) winsize 62
7236 11:05:15.681981 [CA 2] Center 39 (9~69) winsize 61
7237 11:05:15.685212 [CA 3] Center 38 (9~68) winsize 60
7238 11:05:15.688689 [CA 4] Center 37 (7~67) winsize 61
7239 11:05:15.691662 [CA 5] Center 36 (6~66) winsize 61
7240 11:05:15.692117
7241 11:05:15.695206 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7242 11:05:15.695665
7243 11:05:15.698129 [CATrainingPosCal] consider 1 rank data
7244 11:05:15.702828 u2DelayCellTimex100 = 275/100 ps
7245 11:05:15.705175 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7246 11:05:15.711892 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7247 11:05:15.715520 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7248 11:05:15.719097 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7249 11:05:15.721650 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7250 11:05:15.724917 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7251 11:05:15.725401
7252 11:05:15.727699 CA PerBit enable=1, Macro0, CA PI delay=36
7253 11:05:15.728112
7254 11:05:15.731914 [CBTSetCACLKResult] CA Dly = 36
7255 11:05:15.734842 CS Dly: 10 (0~41)
7256 11:05:15.737662 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7257 11:05:15.741400 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7258 11:05:15.741834 ==
7259 11:05:15.745230 Dram Type= 6, Freq= 0, CH_0, rank 1
7260 11:05:15.751310 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7261 11:05:15.751748 ==
7262 11:05:15.754228 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7263 11:05:15.757847 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7264 11:05:15.764603 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7265 11:05:15.771916 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7266 11:05:15.778223 [CA 0] Center 42 (12~73) winsize 62
7267 11:05:15.781921 [CA 1] Center 42 (12~73) winsize 62
7268 11:05:15.785084 [CA 2] Center 38 (9~68) winsize 60
7269 11:05:15.787911 [CA 3] Center 38 (8~68) winsize 61
7270 11:05:15.791930 [CA 4] Center 36 (6~66) winsize 61
7271 11:05:15.795278 [CA 5] Center 36 (6~66) winsize 61
7272 11:05:15.795838
7273 11:05:15.797564 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7274 11:05:15.798028
7275 11:05:15.801666 [CATrainingPosCal] consider 2 rank data
7276 11:05:15.804491 u2DelayCellTimex100 = 275/100 ps
7277 11:05:15.807480 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7278 11:05:15.814169 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7279 11:05:15.817827 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7280 11:05:15.821742 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7281 11:05:15.824256 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7282 11:05:15.827902 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7283 11:05:15.828453
7284 11:05:15.830922 CA PerBit enable=1, Macro0, CA PI delay=36
7285 11:05:15.831382
7286 11:05:15.835543 [CBTSetCACLKResult] CA Dly = 36
7287 11:05:15.838241 CS Dly: 10 (0~42)
7288 11:05:15.841388 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7289 11:05:15.844436 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7290 11:05:15.845031
7291 11:05:15.847162 ----->DramcWriteLeveling(PI) begin...
7292 11:05:15.847629 ==
7293 11:05:15.850698 Dram Type= 6, Freq= 0, CH_0, rank 0
7294 11:05:15.857775 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7295 11:05:15.858408 ==
7296 11:05:15.860629 Write leveling (Byte 0): 29 => 29
7297 11:05:15.861135 Write leveling (Byte 1): 26 => 26
7298 11:05:15.864952 DramcWriteLeveling(PI) end<-----
7299 11:05:15.865440
7300 11:05:15.867194 ==
7301 11:05:15.867809 Dram Type= 6, Freq= 0, CH_0, rank 0
7302 11:05:15.874335 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7303 11:05:15.874660 ==
7304 11:05:15.877341 [Gating] SW mode calibration
7305 11:05:15.884367 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7306 11:05:15.887696 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7307 11:05:15.894002 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7308 11:05:15.896961 0 12 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7309 11:05:15.900572 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7310 11:05:15.906975 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7311 11:05:15.911417 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7312 11:05:15.913818 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7313 11:05:15.920809 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7314 11:05:15.923658 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7315 11:05:15.928182 0 13 0 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
7316 11:05:15.933853 0 13 4 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0)
7317 11:05:15.937122 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7318 11:05:15.941849 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7319 11:05:15.947141 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7320 11:05:15.950366 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7321 11:05:15.953205 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7322 11:05:15.960764 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7323 11:05:15.963536 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7324 11:05:15.966541 0 14 4 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
7325 11:05:15.974517 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7326 11:05:15.976252 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7327 11:05:15.980176 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7328 11:05:15.986228 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7329 11:05:15.990407 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7330 11:05:15.993646 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7331 11:05:15.999530 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7332 11:05:16.003008 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7333 11:05:16.006680 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7334 11:05:16.013275 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7335 11:05:16.016542 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7336 11:05:16.019722 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7337 11:05:16.026339 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7338 11:05:16.029468 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7339 11:05:16.033381 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7340 11:05:16.038928 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7341 11:05:16.043380 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7342 11:05:16.046075 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7343 11:05:16.052058 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7344 11:05:16.055523 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7345 11:05:16.059304 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7346 11:05:16.065285 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7347 11:05:16.068587 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7348 11:05:16.072087 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7349 11:05:16.075657 Total UI for P1: 0, mck2ui 16
7350 11:05:16.078968 best dqsien dly found for B0: ( 1, 0, 30)
7351 11:05:16.085531 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7352 11:05:16.086077 Total UI for P1: 0, mck2ui 16
7353 11:05:16.088499 best dqsien dly found for B1: ( 1, 1, 4)
7354 11:05:16.095460 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7355 11:05:16.099016 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7356 11:05:16.099563
7357 11:05:16.102270 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7358 11:05:16.104889 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7359 11:05:16.108545 [Gating] SW calibration Done
7360 11:05:16.109150 ==
7361 11:05:16.111824 Dram Type= 6, Freq= 0, CH_0, rank 0
7362 11:05:16.115567 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7363 11:05:16.116120 ==
7364 11:05:16.118697 RX Vref Scan: 0
7365 11:05:16.119253
7366 11:05:16.119615 RX Vref 0 -> 0, step: 1
7367 11:05:16.119949
7368 11:05:16.121852 RX Delay 0 -> 252, step: 8
7369 11:05:16.125588 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7370 11:05:16.128547 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7371 11:05:16.134792 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7372 11:05:16.138039 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7373 11:05:16.141264 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7374 11:05:16.145060 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7375 11:05:16.148107 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7376 11:05:16.154875 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
7377 11:05:16.158337 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7378 11:05:16.162513 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7379 11:05:16.165979 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7380 11:05:16.168313 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7381 11:05:16.175439 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7382 11:05:16.177971 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7383 11:05:16.181565 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7384 11:05:16.184433 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7385 11:05:16.184942 ==
7386 11:05:16.188450 Dram Type= 6, Freq= 0, CH_0, rank 0
7387 11:05:16.194470 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7388 11:05:16.195043 ==
7389 11:05:16.195409 DQS Delay:
7390 11:05:16.198483 DQS0 = 0, DQS1 = 0
7391 11:05:16.199033 DQM Delay:
7392 11:05:16.201329 DQM0 = 129, DQM1 = 124
7393 11:05:16.201857 DQ Delay:
7394 11:05:16.204690 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7395 11:05:16.207843 DQ4 =135, DQ5 =115, DQ6 =139, DQ7 =135
7396 11:05:16.211538 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7397 11:05:16.214660 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7398 11:05:16.215211
7399 11:05:16.215576
7400 11:05:16.215911 ==
7401 11:05:16.218829 Dram Type= 6, Freq= 0, CH_0, rank 0
7402 11:05:16.224660 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7403 11:05:16.225252 ==
7404 11:05:16.225622
7405 11:05:16.225956
7406 11:05:16.226276 TX Vref Scan disable
7407 11:05:16.228205 == TX Byte 0 ==
7408 11:05:16.230689 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7409 11:05:16.237689 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7410 11:05:16.238240 == TX Byte 1 ==
7411 11:05:16.241106 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7412 11:05:16.248428 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7413 11:05:16.249019 ==
7414 11:05:16.250786 Dram Type= 6, Freq= 0, CH_0, rank 0
7415 11:05:16.253692 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7416 11:05:16.254169 ==
7417 11:05:16.266929
7418 11:05:16.269807 TX Vref early break, caculate TX vref
7419 11:05:16.273384 TX Vref=16, minBit 8, minWin=22, winSum=373
7420 11:05:16.280127 TX Vref=18, minBit 9, minWin=22, winSum=381
7421 11:05:16.281033 TX Vref=20, minBit 8, minWin=23, winSum=387
7422 11:05:16.283448 TX Vref=22, minBit 8, minWin=23, winSum=396
7423 11:05:16.286957 TX Vref=24, minBit 8, minWin=24, winSum=402
7424 11:05:16.293751 TX Vref=26, minBit 9, minWin=24, winSum=413
7425 11:05:16.297329 TX Vref=28, minBit 1, minWin=25, winSum=413
7426 11:05:16.300333 TX Vref=30, minBit 4, minWin=25, winSum=411
7427 11:05:16.303014 TX Vref=32, minBit 8, minWin=23, winSum=397
7428 11:05:16.306778 TX Vref=34, minBit 3, minWin=23, winSum=390
7429 11:05:16.313269 [TxChooseVref] Worse bit 1, Min win 25, Win sum 413, Final Vref 28
7430 11:05:16.313819
7431 11:05:16.317107 Final TX Range 0 Vref 28
7432 11:05:16.317656
7433 11:05:16.318018 ==
7434 11:05:16.319480 Dram Type= 6, Freq= 0, CH_0, rank 0
7435 11:05:16.323755 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7436 11:05:16.324312 ==
7437 11:05:16.324679
7438 11:05:16.325046
7439 11:05:16.326026 TX Vref Scan disable
7440 11:05:16.333162 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7441 11:05:16.333707 == TX Byte 0 ==
7442 11:05:16.336966 u2DelayCellOfst[0]=10 cells (3 PI)
7443 11:05:16.339765 u2DelayCellOfst[1]=17 cells (5 PI)
7444 11:05:16.343722 u2DelayCellOfst[2]=14 cells (4 PI)
7445 11:05:16.346376 u2DelayCellOfst[3]=10 cells (3 PI)
7446 11:05:16.349848 u2DelayCellOfst[4]=7 cells (2 PI)
7447 11:05:16.354109 u2DelayCellOfst[5]=0 cells (0 PI)
7448 11:05:16.355989 u2DelayCellOfst[6]=17 cells (5 PI)
7449 11:05:16.359525 u2DelayCellOfst[7]=17 cells (5 PI)
7450 11:05:16.363393 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7451 11:05:16.366338 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7452 11:05:16.369968 == TX Byte 1 ==
7453 11:05:16.370427 u2DelayCellOfst[8]=3 cells (1 PI)
7454 11:05:16.373258 u2DelayCellOfst[9]=0 cells (0 PI)
7455 11:05:16.376023 u2DelayCellOfst[10]=10 cells (3 PI)
7456 11:05:16.379480 u2DelayCellOfst[11]=7 cells (2 PI)
7457 11:05:16.383772 u2DelayCellOfst[12]=17 cells (5 PI)
7458 11:05:16.385895 u2DelayCellOfst[13]=17 cells (5 PI)
7459 11:05:16.389281 u2DelayCellOfst[14]=17 cells (5 PI)
7460 11:05:16.393339 u2DelayCellOfst[15]=14 cells (4 PI)
7461 11:05:16.396308 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7462 11:05:16.402725 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7463 11:05:16.403280 DramC Write-DBI on
7464 11:05:16.403647 ==
7465 11:05:16.406292 Dram Type= 6, Freq= 0, CH_0, rank 0
7466 11:05:16.412906 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7467 11:05:16.413470 ==
7468 11:05:16.413842
7469 11:05:16.414178
7470 11:05:16.414500 TX Vref Scan disable
7471 11:05:16.415812 == TX Byte 0 ==
7472 11:05:16.419460 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7473 11:05:16.422431 == TX Byte 1 ==
7474 11:05:16.425850 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7475 11:05:16.429249 DramC Write-DBI off
7476 11:05:16.429705
7477 11:05:16.430060 [DATLAT]
7478 11:05:16.430396 Freq=1600, CH0 RK0
7479 11:05:16.430722
7480 11:05:16.432698 DATLAT Default: 0xf
7481 11:05:16.435873 0, 0xFFFF, sum = 0
7482 11:05:16.436444 1, 0xFFFF, sum = 0
7483 11:05:16.438897 2, 0xFFFF, sum = 0
7484 11:05:16.439719 3, 0xFFFF, sum = 0
7485 11:05:16.442433 4, 0xFFFF, sum = 0
7486 11:05:16.442898 5, 0xFFFF, sum = 0
7487 11:05:16.445326 6, 0xFFFF, sum = 0
7488 11:05:16.445955 7, 0xFFFF, sum = 0
7489 11:05:16.449742 8, 0xFFFF, sum = 0
7490 11:05:16.450220 9, 0xFFFF, sum = 0
7491 11:05:16.452577 10, 0xFFFF, sum = 0
7492 11:05:16.453100 11, 0xFFFF, sum = 0
7493 11:05:16.455617 12, 0xBFF, sum = 0
7494 11:05:16.456082 13, 0x0, sum = 1
7495 11:05:16.458581 14, 0x0, sum = 2
7496 11:05:16.459046 15, 0x0, sum = 3
7497 11:05:16.461992 16, 0x0, sum = 4
7498 11:05:16.462642 best_step = 14
7499 11:05:16.463023
7500 11:05:16.463369 ==
7501 11:05:16.465349 Dram Type= 6, Freq= 0, CH_0, rank 0
7502 11:05:16.471644 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7503 11:05:16.472114 ==
7504 11:05:16.472626 RX Vref Scan: 1
7505 11:05:16.473016
7506 11:05:16.475199 Set Vref Range= 24 -> 127
7507 11:05:16.475657
7508 11:05:16.478235 RX Vref 24 -> 127, step: 1
7509 11:05:16.478680
7510 11:05:16.479121 RX Delay 11 -> 252, step: 4
7511 11:05:16.482047
7512 11:05:16.482462 Set Vref, RX VrefLevel [Byte0]: 24
7513 11:05:16.485644 [Byte1]: 24
7514 11:05:16.489671
7515 11:05:16.490100 Set Vref, RX VrefLevel [Byte0]: 25
7516 11:05:16.492929 [Byte1]: 25
7517 11:05:16.497139
7518 11:05:16.497555 Set Vref, RX VrefLevel [Byte0]: 26
7519 11:05:16.500675 [Byte1]: 26
7520 11:05:16.505115
7521 11:05:16.505534 Set Vref, RX VrefLevel [Byte0]: 27
7522 11:05:16.507449 [Byte1]: 27
7523 11:05:16.512599
7524 11:05:16.513052 Set Vref, RX VrefLevel [Byte0]: 28
7525 11:05:16.515723 [Byte1]: 28
7526 11:05:16.519918
7527 11:05:16.520422 Set Vref, RX VrefLevel [Byte0]: 29
7528 11:05:16.524008 [Byte1]: 29
7529 11:05:16.528243
7530 11:05:16.528829 Set Vref, RX VrefLevel [Byte0]: 30
7531 11:05:16.531672 [Byte1]: 30
7532 11:05:16.535394
7533 11:05:16.535954 Set Vref, RX VrefLevel [Byte0]: 31
7534 11:05:16.538286 [Byte1]: 31
7535 11:05:16.542418
7536 11:05:16.542873 Set Vref, RX VrefLevel [Byte0]: 32
7537 11:05:16.546024 [Byte1]: 32
7538 11:05:16.550290
7539 11:05:16.550860 Set Vref, RX VrefLevel [Byte0]: 33
7540 11:05:16.553294 [Byte1]: 33
7541 11:05:16.557898
7542 11:05:16.558356 Set Vref, RX VrefLevel [Byte0]: 34
7543 11:05:16.560949 [Byte1]: 34
7544 11:05:16.565185
7545 11:05:16.565645 Set Vref, RX VrefLevel [Byte0]: 35
7546 11:05:16.568851 [Byte1]: 35
7547 11:05:16.573215
7548 11:05:16.573678 Set Vref, RX VrefLevel [Byte0]: 36
7549 11:05:16.577016 [Byte1]: 36
7550 11:05:16.580418
7551 11:05:16.581028 Set Vref, RX VrefLevel [Byte0]: 37
7552 11:05:16.583953 [Byte1]: 37
7553 11:05:16.588326
7554 11:05:16.588924 Set Vref, RX VrefLevel [Byte0]: 38
7555 11:05:16.591405 [Byte1]: 38
7556 11:05:16.595697
7557 11:05:16.596153 Set Vref, RX VrefLevel [Byte0]: 39
7558 11:05:16.599407 [Byte1]: 39
7559 11:05:16.604019
7560 11:05:16.604566 Set Vref, RX VrefLevel [Byte0]: 40
7561 11:05:16.608137 [Byte1]: 40
7562 11:05:16.610984
7563 11:05:16.611440 Set Vref, RX VrefLevel [Byte0]: 41
7564 11:05:16.614528 [Byte1]: 41
7565 11:05:16.619167
7566 11:05:16.619717 Set Vref, RX VrefLevel [Byte0]: 42
7567 11:05:16.623063 [Byte1]: 42
7568 11:05:16.626618
7569 11:05:16.627130 Set Vref, RX VrefLevel [Byte0]: 43
7570 11:05:16.629665 [Byte1]: 43
7571 11:05:16.634026
7572 11:05:16.634482 Set Vref, RX VrefLevel [Byte0]: 44
7573 11:05:16.637432 [Byte1]: 44
7574 11:05:16.642237
7575 11:05:16.642712 Set Vref, RX VrefLevel [Byte0]: 45
7576 11:05:16.646227 [Byte1]: 45
7577 11:05:16.649039
7578 11:05:16.649601 Set Vref, RX VrefLevel [Byte0]: 46
7579 11:05:16.652238 [Byte1]: 46
7580 11:05:16.656907
7581 11:05:16.657372 Set Vref, RX VrefLevel [Byte0]: 47
7582 11:05:16.660761 [Byte1]: 47
7583 11:05:16.664279
7584 11:05:16.664767 Set Vref, RX VrefLevel [Byte0]: 48
7585 11:05:16.667650 [Byte1]: 48
7586 11:05:16.672226
7587 11:05:16.672681 Set Vref, RX VrefLevel [Byte0]: 49
7588 11:05:16.675009 [Byte1]: 49
7589 11:05:16.679370
7590 11:05:16.679825 Set Vref, RX VrefLevel [Byte0]: 50
7591 11:05:16.683460 [Byte1]: 50
7592 11:05:16.687115
7593 11:05:16.687574 Set Vref, RX VrefLevel [Byte0]: 51
7594 11:05:16.690411 [Byte1]: 51
7595 11:05:16.694516
7596 11:05:16.694930 Set Vref, RX VrefLevel [Byte0]: 52
7597 11:05:16.698427 [Byte1]: 52
7598 11:05:16.702737
7599 11:05:16.703191 Set Vref, RX VrefLevel [Byte0]: 53
7600 11:05:16.705877 [Byte1]: 53
7601 11:05:16.710028
7602 11:05:16.710444 Set Vref, RX VrefLevel [Byte0]: 54
7603 11:05:16.713619 [Byte1]: 54
7604 11:05:16.718356
7605 11:05:16.718768 Set Vref, RX VrefLevel [Byte0]: 55
7606 11:05:16.720870 [Byte1]: 55
7607 11:05:16.725668
7608 11:05:16.726085 Set Vref, RX VrefLevel [Byte0]: 56
7609 11:05:16.728619 [Byte1]: 56
7610 11:05:16.732854
7611 11:05:16.733409 Set Vref, RX VrefLevel [Byte0]: 57
7612 11:05:16.737789 [Byte1]: 57
7613 11:05:16.740567
7614 11:05:16.741106 Set Vref, RX VrefLevel [Byte0]: 58
7615 11:05:16.743808 [Byte1]: 58
7616 11:05:16.748021
7617 11:05:16.748473 Set Vref, RX VrefLevel [Byte0]: 59
7618 11:05:16.751847 [Byte1]: 59
7619 11:05:16.755688
7620 11:05:16.756144 Set Vref, RX VrefLevel [Byte0]: 60
7621 11:05:16.759332 [Byte1]: 60
7622 11:05:16.763462
7623 11:05:16.764022 Set Vref, RX VrefLevel [Byte0]: 61
7624 11:05:16.766399 [Byte1]: 61
7625 11:05:16.770854
7626 11:05:16.771531 Set Vref, RX VrefLevel [Byte0]: 62
7627 11:05:16.774972 [Byte1]: 62
7628 11:05:16.778782
7629 11:05:16.779262 Set Vref, RX VrefLevel [Byte0]: 63
7630 11:05:16.781995 [Byte1]: 63
7631 11:05:16.786130
7632 11:05:16.786684 Set Vref, RX VrefLevel [Byte0]: 64
7633 11:05:16.789721 [Byte1]: 64
7634 11:05:16.793814
7635 11:05:16.794371 Set Vref, RX VrefLevel [Byte0]: 65
7636 11:05:16.798791 [Byte1]: 65
7637 11:05:16.801589
7638 11:05:16.802073 Set Vref, RX VrefLevel [Byte0]: 66
7639 11:05:16.805438 [Byte1]: 66
7640 11:05:16.808995
7641 11:05:16.809466 Set Vref, RX VrefLevel [Byte0]: 67
7642 11:05:16.812843 [Byte1]: 67
7643 11:05:16.817591
7644 11:05:16.818140 Set Vref, RX VrefLevel [Byte0]: 68
7645 11:05:16.821273 [Byte1]: 68
7646 11:05:16.825035
7647 11:05:16.825587 Set Vref, RX VrefLevel [Byte0]: 69
7648 11:05:16.827563 [Byte1]: 69
7649 11:05:16.832185
7650 11:05:16.832939 Set Vref, RX VrefLevel [Byte0]: 70
7651 11:05:16.835321 [Byte1]: 70
7652 11:05:16.839754
7653 11:05:16.840242 Set Vref, RX VrefLevel [Byte0]: 71
7654 11:05:16.842785 [Byte1]: 71
7655 11:05:16.847838
7656 11:05:16.848396 Final RX Vref Byte 0 = 53 to rank0
7657 11:05:16.850293 Final RX Vref Byte 1 = 54 to rank0
7658 11:05:16.853962 Final RX Vref Byte 0 = 53 to rank1
7659 11:05:16.857439 Final RX Vref Byte 1 = 54 to rank1==
7660 11:05:16.860330 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 11:05:16.867457 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7662 11:05:16.868018 ==
7663 11:05:16.868387 DQS Delay:
7664 11:05:16.869931 DQS0 = 0, DQS1 = 0
7665 11:05:16.870571 DQM Delay:
7666 11:05:16.870952 DQM0 = 126, DQM1 = 120
7667 11:05:16.873457 DQ Delay:
7668 11:05:16.877062 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7669 11:05:16.879950 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7670 11:05:16.884205 DQ8 =108, DQ9 =104, DQ10 =120, DQ11 =112
7671 11:05:16.886759 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7672 11:05:16.887319
7673 11:05:16.887685
7674 11:05:16.888017
7675 11:05:16.891382 [DramC_TX_OE_Calibration] TA2
7676 11:05:16.893513 Original DQ_B0 (3 6) =30, OEN = 27
7677 11:05:16.897020 Original DQ_B1 (3 6) =30, OEN = 27
7678 11:05:16.900187 24, 0x0, End_B0=24 End_B1=24
7679 11:05:16.900798 25, 0x0, End_B0=25 End_B1=25
7680 11:05:16.903715 26, 0x0, End_B0=26 End_B1=26
7681 11:05:16.906926 27, 0x0, End_B0=27 End_B1=27
7682 11:05:16.910326 28, 0x0, End_B0=28 End_B1=28
7683 11:05:16.914324 29, 0x0, End_B0=29 End_B1=29
7684 11:05:16.914926 30, 0x0, End_B0=30 End_B1=30
7685 11:05:16.916822 31, 0x4141, End_B0=30 End_B1=30
7686 11:05:16.920398 Byte0 end_step=30 best_step=27
7687 11:05:16.923752 Byte1 end_step=30 best_step=27
7688 11:05:16.927714 Byte0 TX OE(2T, 0.5T) = (3, 3)
7689 11:05:16.929639 Byte1 TX OE(2T, 0.5T) = (3, 3)
7690 11:05:16.930102
7691 11:05:16.930459
7692 11:05:16.937493 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7693 11:05:16.940846 CH0 RK0: MR19=303, MR18=1A1A
7694 11:05:16.946469 CH0_RK0: MR19=0x303, MR18=0x1A1A, DQSOSC=396, MR23=63, INC=23, DEC=15
7695 11:05:16.946931
7696 11:05:16.950091 ----->DramcWriteLeveling(PI) begin...
7697 11:05:16.950553 ==
7698 11:05:16.953382 Dram Type= 6, Freq= 0, CH_0, rank 1
7699 11:05:16.956324 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7700 11:05:16.956831 ==
7701 11:05:16.959775 Write leveling (Byte 0): 28 => 28
7702 11:05:16.962861 Write leveling (Byte 1): 24 => 24
7703 11:05:16.965910 DramcWriteLeveling(PI) end<-----
7704 11:05:16.966368
7705 11:05:16.966730 ==
7706 11:05:16.969500 Dram Type= 6, Freq= 0, CH_0, rank 1
7707 11:05:16.972951 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7708 11:05:16.973516 ==
7709 11:05:16.976078 [Gating] SW mode calibration
7710 11:05:16.982556 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7711 11:05:16.989086 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7712 11:05:16.992840 0 12 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
7713 11:05:17.000151 0 12 4 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7714 11:05:17.002956 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7715 11:05:17.006168 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7716 11:05:17.013086 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7717 11:05:17.015860 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7718 11:05:17.019616 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7719 11:05:17.026067 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7720 11:05:17.028897 0 13 0 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 1)
7721 11:05:17.031995 0 13 4 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (1 0)
7722 11:05:17.039626 0 13 8 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
7723 11:05:17.042392 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7724 11:05:17.045598 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7725 11:05:17.052141 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7726 11:05:17.055777 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7727 11:05:17.058702 0 13 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7728 11:05:17.065811 0 14 0 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7729 11:05:17.068799 0 14 4 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
7730 11:05:17.071519 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7731 11:05:17.078923 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7732 11:05:17.082182 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7733 11:05:17.085420 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7734 11:05:17.093398 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7735 11:05:17.095441 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7736 11:05:17.098317 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7737 11:05:17.104905 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7738 11:05:17.108770 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7739 11:05:17.111952 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7740 11:05:17.118978 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7741 11:05:17.121422 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7742 11:05:17.125193 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7743 11:05:17.131859 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7744 11:05:17.135245 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7745 11:05:17.137975 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7746 11:05:17.144506 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7747 11:05:17.147798 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7748 11:05:17.151340 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7749 11:05:17.157414 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7750 11:05:17.162410 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7751 11:05:17.164410 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7752 11:05:17.171784 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7753 11:05:17.175375 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7754 11:05:17.178306 Total UI for P1: 0, mck2ui 16
7755 11:05:17.181223 best dqsien dly found for B0: ( 1, 0, 28)
7756 11:05:17.184605 Total UI for P1: 0, mck2ui 16
7757 11:05:17.187890 best dqsien dly found for B1: ( 1, 1, 0)
7758 11:05:17.191218 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7759 11:05:17.193545 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
7760 11:05:17.194002
7761 11:05:17.196952 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7762 11:05:17.200892 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
7763 11:05:17.203742 [Gating] SW calibration Done
7764 11:05:17.204298 ==
7765 11:05:17.207973 Dram Type= 6, Freq= 0, CH_0, rank 1
7766 11:05:17.210891 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7767 11:05:17.211453 ==
7768 11:05:17.214021 RX Vref Scan: 0
7769 11:05:17.214575
7770 11:05:17.217630 RX Vref 0 -> 0, step: 1
7771 11:05:17.218200
7772 11:05:17.218574 RX Delay 0 -> 252, step: 8
7773 11:05:17.224469 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7774 11:05:17.227229 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7775 11:05:17.230928 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7776 11:05:17.233742 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7777 11:05:17.237056 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7778 11:05:17.244055 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7779 11:05:17.246970 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7780 11:05:17.250094 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7781 11:05:17.253216 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7782 11:05:17.256520 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7783 11:05:17.263373 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7784 11:05:17.266435 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7785 11:05:17.269845 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7786 11:05:17.273169 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7787 11:05:17.279945 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7788 11:05:17.284908 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7789 11:05:17.285487 ==
7790 11:05:17.286710 Dram Type= 6, Freq= 0, CH_0, rank 1
7791 11:05:17.291497 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7792 11:05:17.292056 ==
7793 11:05:17.294214 DQS Delay:
7794 11:05:17.294671 DQS0 = 0, DQS1 = 0
7795 11:05:17.295036 DQM Delay:
7796 11:05:17.296228 DQM0 = 130, DQM1 = 123
7797 11:05:17.296682 DQ Delay:
7798 11:05:17.299093 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7799 11:05:17.302706 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7800 11:05:17.306285 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7801 11:05:17.312940 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7802 11:05:17.313496
7803 11:05:17.313866
7804 11:05:17.314204 ==
7805 11:05:17.315948 Dram Type= 6, Freq= 0, CH_0, rank 1
7806 11:05:17.319477 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7807 11:05:17.320037 ==
7808 11:05:17.320406
7809 11:05:17.320781
7810 11:05:17.322263 TX Vref Scan disable
7811 11:05:17.322770 == TX Byte 0 ==
7812 11:05:17.329181 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7813 11:05:17.332545 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7814 11:05:17.336075 == TX Byte 1 ==
7815 11:05:17.338913 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7816 11:05:17.342748 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7817 11:05:17.343205 ==
7818 11:05:17.345367 Dram Type= 6, Freq= 0, CH_0, rank 1
7819 11:05:17.348956 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7820 11:05:17.352895 ==
7821 11:05:17.363972
7822 11:05:17.366902 TX Vref early break, caculate TX vref
7823 11:05:17.371067 TX Vref=16, minBit 9, minWin=22, winSum=372
7824 11:05:17.373773 TX Vref=18, minBit 2, minWin=23, winSum=385
7825 11:05:17.376794 TX Vref=20, minBit 1, minWin=23, winSum=393
7826 11:05:17.380237 TX Vref=22, minBit 9, minWin=23, winSum=397
7827 11:05:17.383135 TX Vref=24, minBit 8, minWin=24, winSum=413
7828 11:05:17.390060 TX Vref=26, minBit 1, minWin=25, winSum=414
7829 11:05:17.393489 TX Vref=28, minBit 8, minWin=25, winSum=418
7830 11:05:17.396396 TX Vref=30, minBit 1, minWin=25, winSum=415
7831 11:05:17.400276 TX Vref=32, minBit 8, minWin=24, winSum=405
7832 11:05:17.403968 TX Vref=34, minBit 8, minWin=23, winSum=396
7833 11:05:17.410164 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 28
7834 11:05:17.410755
7835 11:05:17.412973 Final TX Range 0 Vref 28
7836 11:05:17.413529
7837 11:05:17.413896 ==
7838 11:05:17.416677 Dram Type= 6, Freq= 0, CH_0, rank 1
7839 11:05:17.419680 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7840 11:05:17.420236 ==
7841 11:05:17.420607
7842 11:05:17.421035
7843 11:05:17.422912 TX Vref Scan disable
7844 11:05:17.429641 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7845 11:05:17.430199 == TX Byte 0 ==
7846 11:05:17.433227 u2DelayCellOfst[0]=14 cells (4 PI)
7847 11:05:17.436558 u2DelayCellOfst[1]=17 cells (5 PI)
7848 11:05:17.439521 u2DelayCellOfst[2]=14 cells (4 PI)
7849 11:05:17.443310 u2DelayCellOfst[3]=14 cells (4 PI)
7850 11:05:17.446308 u2DelayCellOfst[4]=10 cells (3 PI)
7851 11:05:17.449523 u2DelayCellOfst[5]=0 cells (0 PI)
7852 11:05:17.452742 u2DelayCellOfst[6]=17 cells (5 PI)
7853 11:05:17.455971 u2DelayCellOfst[7]=17 cells (5 PI)
7854 11:05:17.459732 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7855 11:05:17.462636 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7856 11:05:17.466081 == TX Byte 1 ==
7857 11:05:17.469248 u2DelayCellOfst[8]=3 cells (1 PI)
7858 11:05:17.472794 u2DelayCellOfst[9]=0 cells (0 PI)
7859 11:05:17.473424 u2DelayCellOfst[10]=10 cells (3 PI)
7860 11:05:17.475963 u2DelayCellOfst[11]=7 cells (2 PI)
7861 11:05:17.479260 u2DelayCellOfst[12]=14 cells (4 PI)
7862 11:05:17.482611 u2DelayCellOfst[13]=17 cells (5 PI)
7863 11:05:17.486018 u2DelayCellOfst[14]=21 cells (6 PI)
7864 11:05:17.489084 u2DelayCellOfst[15]=17 cells (5 PI)
7865 11:05:17.496126 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
7866 11:05:17.499150 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7867 11:05:17.499706 DramC Write-DBI on
7868 11:05:17.500077 ==
7869 11:05:17.502932 Dram Type= 6, Freq= 0, CH_0, rank 1
7870 11:05:17.509237 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7871 11:05:17.509794 ==
7872 11:05:17.510162
7873 11:05:17.510498
7874 11:05:17.510818 TX Vref Scan disable
7875 11:05:17.513245 == TX Byte 0 ==
7876 11:05:17.516803 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7877 11:05:17.520364 == TX Byte 1 ==
7878 11:05:17.523061 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7879 11:05:17.526987 DramC Write-DBI off
7880 11:05:17.527538
7881 11:05:17.527905 [DATLAT]
7882 11:05:17.528240 Freq=1600, CH0 RK1
7883 11:05:17.528567
7884 11:05:17.529366 DATLAT Default: 0xe
7885 11:05:17.529732 0, 0xFFFF, sum = 0
7886 11:05:17.532985 1, 0xFFFF, sum = 0
7887 11:05:17.536996 2, 0xFFFF, sum = 0
7888 11:05:17.537558 3, 0xFFFF, sum = 0
7889 11:05:17.539792 4, 0xFFFF, sum = 0
7890 11:05:17.540357 5, 0xFFFF, sum = 0
7891 11:05:17.542863 6, 0xFFFF, sum = 0
7892 11:05:17.543380 7, 0xFFFF, sum = 0
7893 11:05:17.545960 8, 0xFFFF, sum = 0
7894 11:05:17.546424 9, 0xFFFF, sum = 0
7895 11:05:17.549227 10, 0xFFFF, sum = 0
7896 11:05:17.549692 11, 0xFFFF, sum = 0
7897 11:05:17.552785 12, 0x8FFF, sum = 0
7898 11:05:17.553356 13, 0x0, sum = 1
7899 11:05:17.556053 14, 0x0, sum = 2
7900 11:05:17.556517 15, 0x0, sum = 3
7901 11:05:17.560405 16, 0x0, sum = 4
7902 11:05:17.561009 best_step = 14
7903 11:05:17.561376
7904 11:05:17.561711 ==
7905 11:05:17.562460 Dram Type= 6, Freq= 0, CH_0, rank 1
7906 11:05:17.569459 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7907 11:05:17.570019 ==
7908 11:05:17.570387 RX Vref Scan: 0
7909 11:05:17.570729
7910 11:05:17.572567 RX Vref 0 -> 0, step: 1
7911 11:05:17.573173
7912 11:05:17.575400 RX Delay 11 -> 252, step: 4
7913 11:05:17.578678 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7914 11:05:17.582601 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7915 11:05:17.585948 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7916 11:05:17.592310 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7917 11:05:17.595336 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7918 11:05:17.598681 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7919 11:05:17.602173 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
7920 11:05:17.605675 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7921 11:05:17.612456 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7922 11:05:17.615357 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7923 11:05:17.618585 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7924 11:05:17.623065 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7925 11:05:17.626129 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7926 11:05:17.632881 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7927 11:05:17.635115 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
7928 11:05:17.639066 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7929 11:05:17.639603 ==
7930 11:05:17.641888 Dram Type= 6, Freq= 0, CH_0, rank 1
7931 11:05:17.645483 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7932 11:05:17.648120 ==
7933 11:05:17.648574 DQS Delay:
7934 11:05:17.649114 DQS0 = 0, DQS1 = 0
7935 11:05:17.652038 DQM Delay:
7936 11:05:17.652497 DQM0 = 128, DQM1 = 120
7937 11:05:17.655064 DQ Delay:
7938 11:05:17.658231 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =122
7939 11:05:17.661522 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =138
7940 11:05:17.664993 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7941 11:05:17.667950 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
7942 11:05:17.668461
7943 11:05:17.668937
7944 11:05:17.669293
7945 11:05:17.671613 [DramC_TX_OE_Calibration] TA2
7946 11:05:17.675108 Original DQ_B0 (3 6) =30, OEN = 27
7947 11:05:17.678281 Original DQ_B1 (3 6) =30, OEN = 27
7948 11:05:17.681421 24, 0x0, End_B0=24 End_B1=24
7949 11:05:17.682079 25, 0x0, End_B0=25 End_B1=25
7950 11:05:17.684631 26, 0x0, End_B0=26 End_B1=26
7951 11:05:17.688630 27, 0x0, End_B0=27 End_B1=27
7952 11:05:17.691731 28, 0x0, End_B0=28 End_B1=28
7953 11:05:17.692239 29, 0x0, End_B0=29 End_B1=29
7954 11:05:17.694858 30, 0x0, End_B0=30 End_B1=30
7955 11:05:17.698279 31, 0x4141, End_B0=30 End_B1=30
7956 11:05:17.701450 Byte0 end_step=30 best_step=27
7957 11:05:17.704805 Byte1 end_step=30 best_step=27
7958 11:05:17.707771 Byte0 TX OE(2T, 0.5T) = (3, 3)
7959 11:05:17.708315 Byte1 TX OE(2T, 0.5T) = (3, 3)
7960 11:05:17.711772
7961 11:05:17.712232
7962 11:05:17.717935 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
7963 11:05:17.721790 CH0 RK1: MR19=303, MR18=2222
7964 11:05:17.727836 CH0_RK1: MR19=0x303, MR18=0x2222, DQSOSC=392, MR23=63, INC=24, DEC=16
7965 11:05:17.731186 [RxdqsGatingPostProcess] freq 1600
7966 11:05:17.734814 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7967 11:05:17.737915 Pre-setting of DQS Precalculation
7968 11:05:17.745430 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7969 11:05:17.745849 ==
7970 11:05:17.748097 Dram Type= 6, Freq= 0, CH_1, rank 0
7971 11:05:17.750899 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7972 11:05:17.751343 ==
7973 11:05:17.759758 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7974 11:05:17.760813 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7975 11:05:17.764655 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7976 11:05:17.770767 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7977 11:05:17.778470 [CA 0] Center 41 (11~71) winsize 61
7978 11:05:17.782435 [CA 1] Center 41 (11~72) winsize 62
7979 11:05:17.785483 [CA 2] Center 37 (8~67) winsize 60
7980 11:05:17.788269 [CA 3] Center 36 (7~66) winsize 60
7981 11:05:17.791624 [CA 4] Center 34 (5~64) winsize 60
7982 11:05:17.795411 [CA 5] Center 34 (5~64) winsize 60
7983 11:05:17.795490
7984 11:05:17.798761 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7985 11:05:17.798841
7986 11:05:17.801979 [CATrainingPosCal] consider 1 rank data
7987 11:05:17.805308 u2DelayCellTimex100 = 275/100 ps
7988 11:05:17.808295 CA0 delay=41 (11~71),Diff = 7 PI (24 cell)
7989 11:05:17.814796 CA1 delay=41 (11~72),Diff = 7 PI (24 cell)
7990 11:05:17.818018 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
7991 11:05:17.821510 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
7992 11:05:17.824658 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
7993 11:05:17.828275 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
7994 11:05:17.828354
7995 11:05:17.831490 CA PerBit enable=1, Macro0, CA PI delay=34
7996 11:05:17.831570
7997 11:05:17.834467 [CBTSetCACLKResult] CA Dly = 34
7998 11:05:17.838087 CS Dly: 8 (0~39)
7999 11:05:17.841457 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8000 11:05:17.844384 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8001 11:05:17.844464 ==
8002 11:05:17.847803 Dram Type= 6, Freq= 0, CH_1, rank 1
8003 11:05:17.854688 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8004 11:05:17.854787 ==
8005 11:05:17.858344 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8006 11:05:17.861875 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8007 11:05:17.868503 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8008 11:05:17.874119 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8009 11:05:17.881322 [CA 0] Center 41 (11~71) winsize 61
8010 11:05:17.884106 [CA 1] Center 41 (10~72) winsize 63
8011 11:05:17.887832 [CA 2] Center 36 (7~66) winsize 60
8012 11:05:17.890959 [CA 3] Center 35 (6~65) winsize 60
8013 11:05:17.894078 [CA 4] Center 34 (5~64) winsize 60
8014 11:05:17.897483 [CA 5] Center 34 (5~64) winsize 60
8015 11:05:17.897563
8016 11:05:17.901076 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8017 11:05:17.901156
8018 11:05:17.905482 [CATrainingPosCal] consider 2 rank data
8019 11:05:17.907321 u2DelayCellTimex100 = 275/100 ps
8020 11:05:17.914390 CA0 delay=41 (11~71),Diff = 7 PI (24 cell)
8021 11:05:17.917631 CA1 delay=41 (11~72),Diff = 7 PI (24 cell)
8022 11:05:17.920493 CA2 delay=37 (8~66),Diff = 3 PI (10 cell)
8023 11:05:17.924257 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8024 11:05:17.927646 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
8025 11:05:17.930601 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8026 11:05:17.930681
8027 11:05:17.934286 CA PerBit enable=1, Macro0, CA PI delay=34
8028 11:05:17.934367
8029 11:05:17.937372 [CBTSetCACLKResult] CA Dly = 34
8030 11:05:17.941535 CS Dly: 9 (0~41)
8031 11:05:17.944621 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8032 11:05:17.947842 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8033 11:05:17.947923
8034 11:05:17.950483 ----->DramcWriteLeveling(PI) begin...
8035 11:05:17.950565 ==
8036 11:05:17.953804 Dram Type= 6, Freq= 0, CH_1, rank 0
8037 11:05:17.960662 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8038 11:05:17.960780 ==
8039 11:05:17.964668 Write leveling (Byte 0): 23 => 23
8040 11:05:17.964761 Write leveling (Byte 1): 22 => 22
8041 11:05:17.967288 DramcWriteLeveling(PI) end<-----
8042 11:05:17.967367
8043 11:05:17.970950 ==
8044 11:05:17.971030 Dram Type= 6, Freq= 0, CH_1, rank 0
8045 11:05:17.977171 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8046 11:05:17.977260 ==
8047 11:05:17.980269 [Gating] SW mode calibration
8048 11:05:17.987244 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8049 11:05:17.990861 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8050 11:05:17.996694 0 12 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8051 11:05:18.000120 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8052 11:05:18.003639 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8053 11:05:18.010453 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8054 11:05:18.013633 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 11:05:18.016557 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8056 11:05:18.023417 0 12 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8057 11:05:18.026774 0 12 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
8058 11:05:18.030174 0 13 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
8059 11:05:18.036666 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8060 11:05:18.040154 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 11:05:18.043726 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 11:05:18.049474 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 11:05:18.052864 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 11:05:18.056360 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 11:05:18.063737 0 13 28 | B1->B0 | 2323 3e3d | 0 1 | (0 0) (0 0)
8066 11:05:18.067165 0 14 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8067 11:05:18.069858 0 14 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8068 11:05:18.075898 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 11:05:18.079387 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 11:05:18.082912 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 11:05:18.089285 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 11:05:18.092905 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8073 11:05:18.096425 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8074 11:05:18.102543 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8075 11:05:18.105926 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8076 11:05:18.109133 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 11:05:18.116316 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 11:05:18.119808 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 11:05:18.122248 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 11:05:18.129124 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 11:05:18.132239 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 11:05:18.135428 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 11:05:18.143228 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 11:05:18.145512 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 11:05:18.148923 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 11:05:18.155532 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 11:05:18.158810 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 11:05:18.162151 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8089 11:05:18.165916 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8090 11:05:18.172482 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8091 11:05:18.175763 Total UI for P1: 0, mck2ui 16
8092 11:05:18.179334 best dqsien dly found for B0: ( 1, 0, 26)
8093 11:05:18.182257 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8094 11:05:18.185468 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8095 11:05:18.188692 Total UI for P1: 0, mck2ui 16
8096 11:05:18.192636 best dqsien dly found for B1: ( 1, 1, 2)
8097 11:05:18.195800 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8098 11:05:18.198525 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8099 11:05:18.201897
8100 11:05:18.205548 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8101 11:05:18.208580 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8102 11:05:18.212182 [Gating] SW calibration Done
8103 11:05:18.212261 ==
8104 11:05:18.216198 Dram Type= 6, Freq= 0, CH_1, rank 0
8105 11:05:18.218629 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8106 11:05:18.218709 ==
8107 11:05:18.218772 RX Vref Scan: 0
8108 11:05:18.218831
8109 11:05:18.221856 RX Vref 0 -> 0, step: 1
8110 11:05:18.221935
8111 11:05:18.225260 RX Delay 0 -> 252, step: 8
8112 11:05:18.228665 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8113 11:05:18.232169 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8114 11:05:18.235590 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8115 11:05:18.242201 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8116 11:05:18.245889 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8117 11:05:18.248650 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8118 11:05:18.251903 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8119 11:05:18.255192 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8120 11:05:18.261869 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8121 11:05:18.265613 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8122 11:05:18.268210 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8123 11:05:18.272105 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8124 11:05:18.275211 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8125 11:05:18.281898 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8126 11:05:18.284913 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8127 11:05:18.288376 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8128 11:05:18.288457 ==
8129 11:05:18.291717 Dram Type= 6, Freq= 0, CH_1, rank 0
8130 11:05:18.295047 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8131 11:05:18.298209 ==
8132 11:05:18.298289 DQS Delay:
8133 11:05:18.298354 DQS0 = 0, DQS1 = 0
8134 11:05:18.301490 DQM Delay:
8135 11:05:18.301570 DQM0 = 130, DQM1 = 125
8136 11:05:18.305352 DQ Delay:
8137 11:05:18.308321 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8138 11:05:18.311507 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8139 11:05:18.315176 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8140 11:05:18.318369 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8141 11:05:18.318448
8142 11:05:18.318512
8143 11:05:18.318570 ==
8144 11:05:18.321570 Dram Type= 6, Freq= 0, CH_1, rank 0
8145 11:05:18.324618 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8146 11:05:18.328105 ==
8147 11:05:18.328184
8148 11:05:18.328247
8149 11:05:18.328306 TX Vref Scan disable
8150 11:05:18.331654 == TX Byte 0 ==
8151 11:05:18.334590 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8152 11:05:18.337590 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8153 11:05:18.341159 == TX Byte 1 ==
8154 11:05:18.344274 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8155 11:05:18.348311 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8156 11:05:18.348391 ==
8157 11:05:18.351026 Dram Type= 6, Freq= 0, CH_1, rank 0
8158 11:05:18.358015 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8159 11:05:18.358120 ==
8160 11:05:18.369677
8161 11:05:18.372330 TX Vref early break, caculate TX vref
8162 11:05:18.375896 TX Vref=16, minBit 0, minWin=22, winSum=368
8163 11:05:18.378780 TX Vref=18, minBit 0, minWin=22, winSum=377
8164 11:05:18.382154 TX Vref=20, minBit 3, minWin=22, winSum=383
8165 11:05:18.385711 TX Vref=22, minBit 3, minWin=23, winSum=393
8166 11:05:18.388676 TX Vref=24, minBit 0, minWin=24, winSum=400
8167 11:05:18.396202 TX Vref=26, minBit 0, minWin=25, winSum=415
8168 11:05:18.398954 TX Vref=28, minBit 0, minWin=25, winSum=413
8169 11:05:18.402036 TX Vref=30, minBit 0, minWin=24, winSum=406
8170 11:05:18.405593 TX Vref=32, minBit 3, minWin=23, winSum=397
8171 11:05:18.409727 TX Vref=34, minBit 2, minWin=23, winSum=387
8172 11:05:18.415259 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 26
8173 11:05:18.415340
8174 11:05:18.419185 Final TX Range 0 Vref 26
8175 11:05:18.419266
8176 11:05:18.419330 ==
8177 11:05:18.422291 Dram Type= 6, Freq= 0, CH_1, rank 0
8178 11:05:18.425491 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8179 11:05:18.425571 ==
8180 11:05:18.425635
8181 11:05:18.425694
8182 11:05:18.428831 TX Vref Scan disable
8183 11:05:18.435728 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8184 11:05:18.435808 == TX Byte 0 ==
8185 11:05:18.438598 u2DelayCellOfst[0]=14 cells (4 PI)
8186 11:05:18.442680 u2DelayCellOfst[1]=10 cells (3 PI)
8187 11:05:18.445144 u2DelayCellOfst[2]=0 cells (0 PI)
8188 11:05:18.448988 u2DelayCellOfst[3]=7 cells (2 PI)
8189 11:05:18.451972 u2DelayCellOfst[4]=7 cells (2 PI)
8190 11:05:18.454906 u2DelayCellOfst[5]=14 cells (4 PI)
8191 11:05:18.458192 u2DelayCellOfst[6]=14 cells (4 PI)
8192 11:05:18.461790 u2DelayCellOfst[7]=7 cells (2 PI)
8193 11:05:18.465679 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8194 11:05:18.468117 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8195 11:05:18.472008 == TX Byte 1 ==
8196 11:05:18.472087 u2DelayCellOfst[8]=0 cells (0 PI)
8197 11:05:18.475072 u2DelayCellOfst[9]=7 cells (2 PI)
8198 11:05:18.478771 u2DelayCellOfst[10]=10 cells (3 PI)
8199 11:05:18.481665 u2DelayCellOfst[11]=3 cells (1 PI)
8200 11:05:18.485750 u2DelayCellOfst[12]=17 cells (5 PI)
8201 11:05:18.488377 u2DelayCellOfst[13]=17 cells (5 PI)
8202 11:05:18.491264 u2DelayCellOfst[14]=21 cells (6 PI)
8203 11:05:18.495309 u2DelayCellOfst[15]=17 cells (5 PI)
8204 11:05:18.497901 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8205 11:05:18.504836 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8206 11:05:18.504909 DramC Write-DBI on
8207 11:05:18.504971 ==
8208 11:05:18.508643 Dram Type= 6, Freq= 0, CH_1, rank 0
8209 11:05:18.514552 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8210 11:05:18.514633 ==
8211 11:05:18.514696
8212 11:05:18.514754
8213 11:05:18.514809 TX Vref Scan disable
8214 11:05:18.518317 == TX Byte 0 ==
8215 11:05:18.521848 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8216 11:05:18.525214 == TX Byte 1 ==
8217 11:05:18.528548 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8218 11:05:18.531363 DramC Write-DBI off
8219 11:05:18.531442
8220 11:05:18.531505 [DATLAT]
8221 11:05:18.531564 Freq=1600, CH1 RK0
8222 11:05:18.531620
8223 11:05:18.535087 DATLAT Default: 0xf
8224 11:05:18.535166 0, 0xFFFF, sum = 0
8225 11:05:18.538449 1, 0xFFFF, sum = 0
8226 11:05:18.541544 2, 0xFFFF, sum = 0
8227 11:05:18.541626 3, 0xFFFF, sum = 0
8228 11:05:18.544663 4, 0xFFFF, sum = 0
8229 11:05:18.544798 5, 0xFFFF, sum = 0
8230 11:05:18.548495 6, 0xFFFF, sum = 0
8231 11:05:18.548576 7, 0xFFFF, sum = 0
8232 11:05:18.551354 8, 0xFFFF, sum = 0
8233 11:05:18.551435 9, 0xFFFF, sum = 0
8234 11:05:18.555725 10, 0xFFFF, sum = 0
8235 11:05:18.555807 11, 0xFFFF, sum = 0
8236 11:05:18.558793 12, 0xFFF, sum = 0
8237 11:05:18.558874 13, 0x0, sum = 1
8238 11:05:18.562068 14, 0x0, sum = 2
8239 11:05:18.562150 15, 0x0, sum = 3
8240 11:05:18.565084 16, 0x0, sum = 4
8241 11:05:18.565165 best_step = 14
8242 11:05:18.565229
8243 11:05:18.565288 ==
8244 11:05:18.567977 Dram Type= 6, Freq= 0, CH_1, rank 0
8245 11:05:18.571415 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8246 11:05:18.574643 ==
8247 11:05:18.574715 RX Vref Scan: 1
8248 11:05:18.574778
8249 11:05:18.577975 Set Vref Range= 24 -> 127
8250 11:05:18.578051
8251 11:05:18.581534 RX Vref 24 -> 127, step: 1
8252 11:05:18.581607
8253 11:05:18.581668 RX Delay 3 -> 252, step: 4
8254 11:05:18.581726
8255 11:05:18.585103 Set Vref, RX VrefLevel [Byte0]: 24
8256 11:05:18.587879 [Byte1]: 24
8257 11:05:18.591997
8258 11:05:18.592076 Set Vref, RX VrefLevel [Byte0]: 25
8259 11:05:18.595021 [Byte1]: 25
8260 11:05:18.599507
8261 11:05:18.599585 Set Vref, RX VrefLevel [Byte0]: 26
8262 11:05:18.602623 [Byte1]: 26
8263 11:05:18.606729
8264 11:05:18.606808 Set Vref, RX VrefLevel [Byte0]: 27
8265 11:05:18.610647 [Byte1]: 27
8266 11:05:18.614502
8267 11:05:18.614580 Set Vref, RX VrefLevel [Byte0]: 28
8268 11:05:18.618443 [Byte1]: 28
8269 11:05:18.622317
8270 11:05:18.622396 Set Vref, RX VrefLevel [Byte0]: 29
8271 11:05:18.626146 [Byte1]: 29
8272 11:05:18.630911
8273 11:05:18.630990 Set Vref, RX VrefLevel [Byte0]: 30
8274 11:05:18.633267 [Byte1]: 30
8275 11:05:18.637630
8276 11:05:18.637710 Set Vref, RX VrefLevel [Byte0]: 31
8277 11:05:18.640440 [Byte1]: 31
8278 11:05:18.645453
8279 11:05:18.645559 Set Vref, RX VrefLevel [Byte0]: 32
8280 11:05:18.648298 [Byte1]: 32
8281 11:05:18.652806
8282 11:05:18.652885 Set Vref, RX VrefLevel [Byte0]: 33
8283 11:05:18.655755 [Byte1]: 33
8284 11:05:18.661940
8285 11:05:18.662019 Set Vref, RX VrefLevel [Byte0]: 34
8286 11:05:18.664444 [Byte1]: 34
8287 11:05:18.668301
8288 11:05:18.668407 Set Vref, RX VrefLevel [Byte0]: 35
8289 11:05:18.672107 [Byte1]: 35
8290 11:05:18.675623
8291 11:05:18.675729 Set Vref, RX VrefLevel [Byte0]: 36
8292 11:05:18.679254 [Byte1]: 36
8293 11:05:18.683614
8294 11:05:18.683696 Set Vref, RX VrefLevel [Byte0]: 37
8295 11:05:18.686440 [Byte1]: 37
8296 11:05:18.691379
8297 11:05:18.691457 Set Vref, RX VrefLevel [Byte0]: 38
8298 11:05:18.694529 [Byte1]: 38
8299 11:05:18.698812
8300 11:05:18.698891 Set Vref, RX VrefLevel [Byte0]: 39
8301 11:05:18.702424 [Byte1]: 39
8302 11:05:18.706487
8303 11:05:18.706581 Set Vref, RX VrefLevel [Byte0]: 40
8304 11:05:18.709438 [Byte1]: 40
8305 11:05:18.715025
8306 11:05:18.715103 Set Vref, RX VrefLevel [Byte0]: 41
8307 11:05:18.717547 [Byte1]: 41
8308 11:05:18.721652
8309 11:05:18.721730 Set Vref, RX VrefLevel [Byte0]: 42
8310 11:05:18.724908 [Byte1]: 42
8311 11:05:18.729292
8312 11:05:18.729369 Set Vref, RX VrefLevel [Byte0]: 43
8313 11:05:18.734150 [Byte1]: 43
8314 11:05:18.736865
8315 11:05:18.736943 Set Vref, RX VrefLevel [Byte0]: 44
8316 11:05:18.740299 [Byte1]: 44
8317 11:05:18.744395
8318 11:05:18.744472 Set Vref, RX VrefLevel [Byte0]: 45
8319 11:05:18.748114 [Byte1]: 45
8320 11:05:18.752586
8321 11:05:18.752664 Set Vref, RX VrefLevel [Byte0]: 46
8322 11:05:18.755847 [Byte1]: 46
8323 11:05:18.759885
8324 11:05:18.759963 Set Vref, RX VrefLevel [Byte0]: 47
8325 11:05:18.763550 [Byte1]: 47
8326 11:05:18.767607
8327 11:05:18.767685 Set Vref, RX VrefLevel [Byte0]: 48
8328 11:05:18.770614 [Byte1]: 48
8329 11:05:18.775250
8330 11:05:18.775328 Set Vref, RX VrefLevel [Byte0]: 49
8331 11:05:18.778557 [Byte1]: 49
8332 11:05:18.783646
8333 11:05:18.783725 Set Vref, RX VrefLevel [Byte0]: 50
8334 11:05:18.786502 [Byte1]: 50
8335 11:05:18.790386
8336 11:05:18.790471 Set Vref, RX VrefLevel [Byte0]: 51
8337 11:05:18.794990 [Byte1]: 51
8338 11:05:18.798191
8339 11:05:18.798270 Set Vref, RX VrefLevel [Byte0]: 52
8340 11:05:18.801538 [Byte1]: 52
8341 11:05:18.806273
8342 11:05:18.806351 Set Vref, RX VrefLevel [Byte0]: 53
8343 11:05:18.809444 [Byte1]: 53
8344 11:05:18.813467
8345 11:05:18.813545 Set Vref, RX VrefLevel [Byte0]: 54
8346 11:05:18.816435 [Byte1]: 54
8347 11:05:18.821248
8348 11:05:18.821327 Set Vref, RX VrefLevel [Byte0]: 55
8349 11:05:18.824985 [Byte1]: 55
8350 11:05:18.829934
8351 11:05:18.830012 Set Vref, RX VrefLevel [Byte0]: 56
8352 11:05:18.832226 [Byte1]: 56
8353 11:05:18.836336
8354 11:05:18.836415 Set Vref, RX VrefLevel [Byte0]: 57
8355 11:05:18.840165 [Byte1]: 57
8356 11:05:18.844280
8357 11:05:18.844363 Set Vref, RX VrefLevel [Byte0]: 58
8358 11:05:18.847196 [Byte1]: 58
8359 11:05:18.852616
8360 11:05:18.852762 Set Vref, RX VrefLevel [Byte0]: 59
8361 11:05:18.855012 [Byte1]: 59
8362 11:05:18.859331
8363 11:05:18.859410 Set Vref, RX VrefLevel [Byte0]: 60
8364 11:05:18.862502 [Byte1]: 60
8365 11:05:18.866790
8366 11:05:18.866896 Set Vref, RX VrefLevel [Byte0]: 61
8367 11:05:18.871242 [Byte1]: 61
8368 11:05:18.874956
8369 11:05:18.875035 Set Vref, RX VrefLevel [Byte0]: 62
8370 11:05:18.877913 [Byte1]: 62
8371 11:05:18.882738
8372 11:05:18.882820 Set Vref, RX VrefLevel [Byte0]: 63
8373 11:05:18.885615 [Byte1]: 63
8374 11:05:18.889628
8375 11:05:18.889709 Set Vref, RX VrefLevel [Byte0]: 64
8376 11:05:18.893136 [Byte1]: 64
8377 11:05:18.897842
8378 11:05:18.897923 Set Vref, RX VrefLevel [Byte0]: 65
8379 11:05:18.900612 [Byte1]: 65
8380 11:05:18.905614
8381 11:05:18.905693 Set Vref, RX VrefLevel [Byte0]: 66
8382 11:05:18.908718 [Byte1]: 66
8383 11:05:18.912810
8384 11:05:18.912916 Set Vref, RX VrefLevel [Byte0]: 67
8385 11:05:18.916561 [Byte1]: 67
8386 11:05:18.920451
8387 11:05:18.920535 Set Vref, RX VrefLevel [Byte0]: 68
8388 11:05:18.924183 [Byte1]: 68
8389 11:05:18.928614
8390 11:05:18.928731 Set Vref, RX VrefLevel [Byte0]: 69
8391 11:05:18.931609 [Byte1]: 69
8392 11:05:18.936404
8393 11:05:18.936483 Set Vref, RX VrefLevel [Byte0]: 70
8394 11:05:18.939095 [Byte1]: 70
8395 11:05:18.943394
8396 11:05:18.943529 Set Vref, RX VrefLevel [Byte0]: 71
8397 11:05:18.946712 [Byte1]: 71
8398 11:05:18.951484
8399 11:05:18.951563 Set Vref, RX VrefLevel [Byte0]: 72
8400 11:05:18.955390 [Byte1]: 72
8401 11:05:18.959307
8402 11:05:18.959386 Set Vref, RX VrefLevel [Byte0]: 73
8403 11:05:18.961990 [Byte1]: 73
8404 11:05:18.966276
8405 11:05:18.966381 Set Vref, RX VrefLevel [Byte0]: 74
8406 11:05:18.969910 [Byte1]: 74
8407 11:05:18.974204
8408 11:05:18.974283 Final RX Vref Byte 0 = 61 to rank0
8409 11:05:18.977371 Final RX Vref Byte 1 = 55 to rank0
8410 11:05:18.980560 Final RX Vref Byte 0 = 61 to rank1
8411 11:05:18.984731 Final RX Vref Byte 1 = 55 to rank1==
8412 11:05:18.987813 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 11:05:18.994147 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8414 11:05:18.994227 ==
8415 11:05:18.994292 DQS Delay:
8416 11:05:18.997663 DQS0 = 0, DQS1 = 0
8417 11:05:18.997742 DQM Delay:
8418 11:05:18.997805 DQM0 = 129, DQM1 = 122
8419 11:05:19.000493 DQ Delay:
8420 11:05:19.003934 DQ0 =132, DQ1 =122, DQ2 =118, DQ3 =126
8421 11:05:19.007163 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =126
8422 11:05:19.011091 DQ8 =104, DQ9 =112, DQ10 =124, DQ11 =112
8423 11:05:19.014515 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =132
8424 11:05:19.014621
8425 11:05:19.014705
8426 11:05:19.014766
8427 11:05:19.017855 [DramC_TX_OE_Calibration] TA2
8428 11:05:19.020463 Original DQ_B0 (3 6) =30, OEN = 27
8429 11:05:19.023691 Original DQ_B1 (3 6) =30, OEN = 27
8430 11:05:19.027617 24, 0x0, End_B0=24 End_B1=24
8431 11:05:19.027698 25, 0x0, End_B0=25 End_B1=25
8432 11:05:19.031573 26, 0x0, End_B0=26 End_B1=26
8433 11:05:19.036552 27, 0x0, End_B0=27 End_B1=27
8434 11:05:19.037304 28, 0x0, End_B0=28 End_B1=28
8435 11:05:19.040500 29, 0x0, End_B0=29 End_B1=29
8436 11:05:19.040580 30, 0x0, End_B0=30 End_B1=30
8437 11:05:19.043608 31, 0x4141, End_B0=30 End_B1=30
8438 11:05:19.047452 Byte0 end_step=30 best_step=27
8439 11:05:19.050477 Byte1 end_step=30 best_step=27
8440 11:05:19.053578 Byte0 TX OE(2T, 0.5T) = (3, 3)
8441 11:05:19.058937 Byte1 TX OE(2T, 0.5T) = (3, 3)
8442 11:05:19.059017
8443 11:05:19.059080
8444 11:05:19.064676 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8445 11:05:19.067343 CH1 RK0: MR19=303, MR18=2525
8446 11:05:19.073252 CH1_RK0: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
8447 11:05:19.073332
8448 11:05:19.077190 ----->DramcWriteLeveling(PI) begin...
8449 11:05:19.077271 ==
8450 11:05:19.080140 Dram Type= 6, Freq= 0, CH_1, rank 1
8451 11:05:19.083570 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8452 11:05:19.083651 ==
8453 11:05:19.086923 Write leveling (Byte 0): 22 => 22
8454 11:05:19.089947 Write leveling (Byte 1): 20 => 20
8455 11:05:19.093085 DramcWriteLeveling(PI) end<-----
8456 11:05:19.093164
8457 11:05:19.093227 ==
8458 11:05:19.096899 Dram Type= 6, Freq= 0, CH_1, rank 1
8459 11:05:19.099878 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8460 11:05:19.099958 ==
8461 11:05:19.103077 [Gating] SW mode calibration
8462 11:05:19.109767 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8463 11:05:19.117481 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8464 11:05:19.119756 0 12 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8465 11:05:19.126537 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8466 11:05:19.129572 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8467 11:05:19.133209 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8468 11:05:19.139909 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8469 11:05:19.143834 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8470 11:05:19.146950 0 12 24 | B1->B0 | 3434 2424 | 1 1 | (1 1) (1 0)
8471 11:05:19.152666 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8472 11:05:19.156136 0 13 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8473 11:05:19.160255 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8474 11:05:19.166453 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8475 11:05:19.169501 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8476 11:05:19.172815 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8477 11:05:19.179742 0 13 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8478 11:05:19.183313 0 13 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
8479 11:05:19.185638 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8480 11:05:19.192167 0 14 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8481 11:05:19.195549 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8482 11:05:19.199400 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8483 11:05:19.205820 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8484 11:05:19.208689 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8485 11:05:19.212507 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8486 11:05:19.219274 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8487 11:05:19.222670 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8488 11:05:19.225471 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8489 11:05:19.229191 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 11:05:19.235544 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 11:05:19.239262 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 11:05:19.241945 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 11:05:19.248644 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 11:05:19.252142 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 11:05:19.255583 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 11:05:19.261989 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 11:05:19.265773 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 11:05:19.268844 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 11:05:19.275634 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 11:05:19.278566 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 11:05:19.281753 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8502 11:05:19.288668 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8503 11:05:19.292373 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8504 11:05:19.294850 Total UI for P1: 0, mck2ui 16
8505 11:05:19.297985 best dqsien dly found for B0: ( 1, 0, 22)
8506 11:05:19.301839 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8507 11:05:19.308568 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8508 11:05:19.311787 Total UI for P1: 0, mck2ui 16
8509 11:05:19.316268 best dqsien dly found for B1: ( 1, 0, 30)
8510 11:05:19.317950 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8511 11:05:19.321866 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8512 11:05:19.321948
8513 11:05:19.325063 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8514 11:05:19.328059 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8515 11:05:19.331571 [Gating] SW calibration Done
8516 11:05:19.331653 ==
8517 11:05:19.335328 Dram Type= 6, Freq= 0, CH_1, rank 1
8518 11:05:19.337714 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8519 11:05:19.337823 ==
8520 11:05:19.341629 RX Vref Scan: 0
8521 11:05:19.341710
8522 11:05:19.341793 RX Vref 0 -> 0, step: 1
8523 11:05:19.344609
8524 11:05:19.344691 RX Delay 0 -> 252, step: 8
8525 11:05:19.351247 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8526 11:05:19.354781 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8527 11:05:19.358139 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8528 11:05:19.361685 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8529 11:05:19.364908 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8530 11:05:19.370888 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8531 11:05:19.374428 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8532 11:05:19.377351 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8533 11:05:19.381195 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8534 11:05:19.384127 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8535 11:05:19.390718 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8536 11:05:19.394455 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8537 11:05:19.397452 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8538 11:05:19.401139 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8539 11:05:19.407455 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8540 11:05:19.410890 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8541 11:05:19.410972 ==
8542 11:05:19.413885 Dram Type= 6, Freq= 0, CH_1, rank 1
8543 11:05:19.416991 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8544 11:05:19.417078 ==
8545 11:05:19.417162 DQS Delay:
8546 11:05:19.420387 DQS0 = 0, DQS1 = 0
8547 11:05:19.420469 DQM Delay:
8548 11:05:19.423492 DQM0 = 130, DQM1 = 125
8549 11:05:19.423575 DQ Delay:
8550 11:05:19.426584 DQ0 =131, DQ1 =123, DQ2 =119, DQ3 =131
8551 11:05:19.430281 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =131
8552 11:05:19.433488 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8553 11:05:19.440114 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8554 11:05:19.440221
8555 11:05:19.440305
8556 11:05:19.440384 ==
8557 11:05:19.443452 Dram Type= 6, Freq= 0, CH_1, rank 1
8558 11:05:19.447238 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8559 11:05:19.447321 ==
8560 11:05:19.447405
8561 11:05:19.447483
8562 11:05:19.449971 TX Vref Scan disable
8563 11:05:19.450053 == TX Byte 0 ==
8564 11:05:19.456677 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8565 11:05:19.460009 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8566 11:05:19.460091 == TX Byte 1 ==
8567 11:05:19.466450 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8568 11:05:19.469555 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8569 11:05:19.469637 ==
8570 11:05:19.473239 Dram Type= 6, Freq= 0, CH_1, rank 1
8571 11:05:19.476979 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8572 11:05:19.477062 ==
8573 11:05:19.491569
8574 11:05:19.494559 TX Vref early break, caculate TX vref
8575 11:05:19.497763 TX Vref=16, minBit 0, minWin=22, winSum=373
8576 11:05:19.501035 TX Vref=18, minBit 0, minWin=23, winSum=385
8577 11:05:19.504958 TX Vref=20, minBit 0, minWin=23, winSum=398
8578 11:05:19.508670 TX Vref=22, minBit 3, minWin=23, winSum=402
8579 11:05:19.510814 TX Vref=24, minBit 1, minWin=24, winSum=411
8580 11:05:19.517442 TX Vref=26, minBit 3, minWin=24, winSum=413
8581 11:05:19.521189 TX Vref=28, minBit 5, minWin=24, winSum=419
8582 11:05:19.524881 TX Vref=30, minBit 0, minWin=24, winSum=415
8583 11:05:19.527772 TX Vref=32, minBit 0, minWin=24, winSum=407
8584 11:05:19.531182 TX Vref=34, minBit 0, minWin=23, winSum=399
8585 11:05:19.534645 TX Vref=36, minBit 0, minWin=22, winSum=389
8586 11:05:19.540740 [TxChooseVref] Worse bit 5, Min win 24, Win sum 419, Final Vref 28
8587 11:05:19.540822
8588 11:05:19.544565 Final TX Range 0 Vref 28
8589 11:05:19.544647
8590 11:05:19.544780 ==
8591 11:05:19.547100 Dram Type= 6, Freq= 0, CH_1, rank 1
8592 11:05:19.551297 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8593 11:05:19.551379 ==
8594 11:05:19.551464
8595 11:05:19.553814
8596 11:05:19.553895 TX Vref Scan disable
8597 11:05:19.560511 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8598 11:05:19.560623 == TX Byte 0 ==
8599 11:05:19.563634 u2DelayCellOfst[0]=14 cells (4 PI)
8600 11:05:19.567396 u2DelayCellOfst[1]=10 cells (3 PI)
8601 11:05:19.570868 u2DelayCellOfst[2]=0 cells (0 PI)
8602 11:05:19.574152 u2DelayCellOfst[3]=3 cells (1 PI)
8603 11:05:19.577821 u2DelayCellOfst[4]=7 cells (2 PI)
8604 11:05:19.580692 u2DelayCellOfst[5]=14 cells (4 PI)
8605 11:05:19.585458 u2DelayCellOfst[6]=14 cells (4 PI)
8606 11:05:19.586865 u2DelayCellOfst[7]=3 cells (1 PI)
8607 11:05:19.591041 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8608 11:05:19.593864 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8609 11:05:19.597440 == TX Byte 1 ==
8610 11:05:19.600186 u2DelayCellOfst[8]=0 cells (0 PI)
8611 11:05:19.603446 u2DelayCellOfst[9]=3 cells (1 PI)
8612 11:05:19.603527 u2DelayCellOfst[10]=7 cells (2 PI)
8613 11:05:19.606822 u2DelayCellOfst[11]=3 cells (1 PI)
8614 11:05:19.610274 u2DelayCellOfst[12]=14 cells (4 PI)
8615 11:05:19.613833 u2DelayCellOfst[13]=17 cells (5 PI)
8616 11:05:19.616861 u2DelayCellOfst[14]=17 cells (5 PI)
8617 11:05:19.620073 u2DelayCellOfst[15]=17 cells (5 PI)
8618 11:05:19.626813 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8619 11:05:19.629812 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8620 11:05:19.629887 DramC Write-DBI on
8621 11:05:19.629950 ==
8622 11:05:19.633317 Dram Type= 6, Freq= 0, CH_1, rank 1
8623 11:05:19.640278 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8624 11:05:19.640376 ==
8625 11:05:19.640465
8626 11:05:19.640556
8627 11:05:19.643030 TX Vref Scan disable
8628 11:05:19.643123 == TX Byte 0 ==
8629 11:05:19.649761 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8630 11:05:19.649865 == TX Byte 1 ==
8631 11:05:19.653259 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8632 11:05:19.656442 DramC Write-DBI off
8633 11:05:19.656544
8634 11:05:19.656636 [DATLAT]
8635 11:05:19.660374 Freq=1600, CH1 RK1
8636 11:05:19.660473
8637 11:05:19.660566 DATLAT Default: 0xe
8638 11:05:19.663162 0, 0xFFFF, sum = 0
8639 11:05:19.663261 1, 0xFFFF, sum = 0
8640 11:05:19.666765 2, 0xFFFF, sum = 0
8641 11:05:19.666868 3, 0xFFFF, sum = 0
8642 11:05:19.669685 4, 0xFFFF, sum = 0
8643 11:05:19.669760 5, 0xFFFF, sum = 0
8644 11:05:19.673519 6, 0xFFFF, sum = 0
8645 11:05:19.673596 7, 0xFFFF, sum = 0
8646 11:05:19.676175 8, 0xFFFF, sum = 0
8647 11:05:19.676272 9, 0xFFFF, sum = 0
8648 11:05:19.680347 10, 0xFFFF, sum = 0
8649 11:05:19.683056 11, 0xFFFF, sum = 0
8650 11:05:19.683159 12, 0xF7F, sum = 0
8651 11:05:19.686294 13, 0x0, sum = 1
8652 11:05:19.686396 14, 0x0, sum = 2
8653 11:05:19.686487 15, 0x0, sum = 3
8654 11:05:19.689850 16, 0x0, sum = 4
8655 11:05:19.689954 best_step = 14
8656 11:05:19.690046
8657 11:05:19.692701 ==
8658 11:05:19.692824 Dram Type= 6, Freq= 0, CH_1, rank 1
8659 11:05:19.699546 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8660 11:05:19.699649 ==
8661 11:05:19.699740 RX Vref Scan: 0
8662 11:05:19.699837
8663 11:05:19.702591 RX Vref 0 -> 0, step: 1
8664 11:05:19.702686
8665 11:05:19.705906 RX Delay 3 -> 252, step: 4
8666 11:05:19.709368 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8667 11:05:19.712695 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8668 11:05:19.719347 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8669 11:05:19.722451 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8670 11:05:19.726172 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8671 11:05:19.729515 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8672 11:05:19.732539 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8673 11:05:19.739016 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8674 11:05:19.742250 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8675 11:05:19.745698 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
8676 11:05:19.749280 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8677 11:05:19.752454 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8678 11:05:19.758867 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8679 11:05:19.762078 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8680 11:05:19.765632 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8681 11:05:19.768926 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8682 11:05:19.769008 ==
8683 11:05:19.772071 Dram Type= 6, Freq= 0, CH_1, rank 1
8684 11:05:19.778894 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8685 11:05:19.778976 ==
8686 11:05:19.779040 DQS Delay:
8687 11:05:19.782105 DQS0 = 0, DQS1 = 0
8688 11:05:19.782210 DQM Delay:
8689 11:05:19.785729 DQM0 = 127, DQM1 = 122
8690 11:05:19.785827 DQ Delay:
8691 11:05:19.788362 DQ0 =128, DQ1 =124, DQ2 =118, DQ3 =124
8692 11:05:19.792713 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8693 11:05:19.794980 DQ8 =104, DQ9 =108, DQ10 =124, DQ11 =114
8694 11:05:19.798527 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8695 11:05:19.798597
8696 11:05:19.798657
8697 11:05:19.798714
8698 11:05:19.801540 [DramC_TX_OE_Calibration] TA2
8699 11:05:19.805287 Original DQ_B0 (3 6) =30, OEN = 27
8700 11:05:19.808302 Original DQ_B1 (3 6) =30, OEN = 27
8701 11:05:19.811700 24, 0x0, End_B0=24 End_B1=24
8702 11:05:19.814781 25, 0x0, End_B0=25 End_B1=25
8703 11:05:19.814857 26, 0x0, End_B0=26 End_B1=26
8704 11:05:19.818234 27, 0x0, End_B0=27 End_B1=27
8705 11:05:19.821493 28, 0x0, End_B0=28 End_B1=28
8706 11:05:19.824828 29, 0x0, End_B0=29 End_B1=29
8707 11:05:19.828587 30, 0x0, End_B0=30 End_B1=30
8708 11:05:19.828697 31, 0x4545, End_B0=30 End_B1=30
8709 11:05:19.831281 Byte0 end_step=30 best_step=27
8710 11:05:19.837388 Byte1 end_step=30 best_step=27
8711 11:05:19.838907 Byte0 TX OE(2T, 0.5T) = (3, 3)
8712 11:05:19.841616 Byte1 TX OE(2T, 0.5T) = (3, 3)
8713 11:05:19.841698
8714 11:05:19.841762
8715 11:05:19.848778 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8716 11:05:19.851231 CH1 RK1: MR19=303, MR18=1D1D
8717 11:05:19.858268 CH1_RK1: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
8718 11:05:19.861688 [RxdqsGatingPostProcess] freq 1600
8719 11:05:19.868012 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8720 11:05:19.868093 Pre-setting of DQS Precalculation
8721 11:05:19.875229 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8722 11:05:19.880995 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8723 11:05:19.888716 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8724 11:05:19.888855
8725 11:05:19.888948
8726 11:05:19.891182 [Calibration Summary] 3200 Mbps
8727 11:05:19.895294 CH 0, Rank 0
8728 11:05:19.895390 SW Impedance : PASS
8729 11:05:19.897984 DUTY Scan : NO K
8730 11:05:19.901164 ZQ Calibration : PASS
8731 11:05:19.901239 Jitter Meter : NO K
8732 11:05:19.904098 CBT Training : PASS
8733 11:05:19.907516 Write leveling : PASS
8734 11:05:19.907612 RX DQS gating : PASS
8735 11:05:19.911720 RX DQ/DQS(RDDQC) : PASS
8736 11:05:19.914680 TX DQ/DQS : PASS
8737 11:05:19.914780 RX DATLAT : PASS
8738 11:05:19.917639 RX DQ/DQS(Engine): PASS
8739 11:05:19.917737 TX OE : PASS
8740 11:05:19.921470 All Pass.
8741 11:05:19.921572
8742 11:05:19.921663 CH 0, Rank 1
8743 11:05:19.925006 SW Impedance : PASS
8744 11:05:19.925093 DUTY Scan : NO K
8745 11:05:19.927725 ZQ Calibration : PASS
8746 11:05:19.931024 Jitter Meter : NO K
8747 11:05:19.931129 CBT Training : PASS
8748 11:05:19.934102 Write leveling : PASS
8749 11:05:19.937866 RX DQS gating : PASS
8750 11:05:19.937972 RX DQ/DQS(RDDQC) : PASS
8751 11:05:19.940832 TX DQ/DQS : PASS
8752 11:05:19.944481 RX DATLAT : PASS
8753 11:05:19.944614 RX DQ/DQS(Engine): PASS
8754 11:05:19.948287 TX OE : PASS
8755 11:05:19.948384 All Pass.
8756 11:05:19.948472
8757 11:05:19.951069 CH 1, Rank 0
8758 11:05:19.951163 SW Impedance : PASS
8759 11:05:19.955140 DUTY Scan : NO K
8760 11:05:19.957479 ZQ Calibration : PASS
8761 11:05:19.957579 Jitter Meter : NO K
8762 11:05:19.960565 CBT Training : PASS
8763 11:05:19.964232 Write leveling : PASS
8764 11:05:19.964335 RX DQS gating : PASS
8765 11:05:19.967913 RX DQ/DQS(RDDQC) : PASS
8766 11:05:19.970848 TX DQ/DQS : PASS
8767 11:05:19.970918 RX DATLAT : PASS
8768 11:05:19.973497 RX DQ/DQS(Engine): PASS
8769 11:05:19.977424 TX OE : PASS
8770 11:05:19.977528 All Pass.
8771 11:05:19.977618
8772 11:05:19.977716 CH 1, Rank 1
8773 11:05:19.980667 SW Impedance : PASS
8774 11:05:19.984037 DUTY Scan : NO K
8775 11:05:19.984146 ZQ Calibration : PASS
8776 11:05:19.986781 Jitter Meter : NO K
8777 11:05:19.986886 CBT Training : PASS
8778 11:05:19.990178 Write leveling : PASS
8779 11:05:19.993993 RX DQS gating : PASS
8780 11:05:19.994072 RX DQ/DQS(RDDQC) : PASS
8781 11:05:19.996817 TX DQ/DQS : PASS
8782 11:05:20.001713 RX DATLAT : PASS
8783 11:05:20.001812 RX DQ/DQS(Engine): PASS
8784 11:05:20.003474 TX OE : PASS
8785 11:05:20.003573 All Pass.
8786 11:05:20.003668
8787 11:05:20.006703 DramC Write-DBI on
8788 11:05:20.010089 PER_BANK_REFRESH: Hybrid Mode
8789 11:05:20.010184 TX_TRACKING: ON
8790 11:05:20.019875 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8791 11:05:20.026472 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8792 11:05:20.033438 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8793 11:05:20.039923 [FAST_K] Save calibration result to emmc
8794 11:05:20.040024 sync common calibartion params.
8795 11:05:20.043499 sync cbt_mode0:0, 1:0
8796 11:05:20.046426 dram_init: ddr_geometry: 0
8797 11:05:20.049645 dram_init: ddr_geometry: 0
8798 11:05:20.049716 dram_init: ddr_geometry: 0
8799 11:05:20.053145 0:dram_rank_size:80000000
8800 11:05:20.056206 1:dram_rank_size:80000000
8801 11:05:20.060116 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8802 11:05:20.063231 DFS_SHUFFLE_HW_MODE: ON
8803 11:05:20.066387 dramc_set_vcore_voltage set vcore to 725000
8804 11:05:20.069434 Read voltage for 1600, 0
8805 11:05:20.069527 Vio18 = 0
8806 11:05:20.072807 Vcore = 725000
8807 11:05:20.072878 Vdram = 0
8808 11:05:20.072938 Vddq = 0
8809 11:05:20.072995 Vmddr = 0
8810 11:05:20.075839 switch to 3200 Mbps bootup
8811 11:05:20.079210 [DramcRunTimeConfig]
8812 11:05:20.079307 PHYPLL
8813 11:05:20.079396 DPM_CONTROL_AFTERK: ON
8814 11:05:20.083003 PER_BANK_REFRESH: ON
8815 11:05:20.086461 REFRESH_OVERHEAD_REDUCTION: ON
8816 11:05:20.086557 CMD_PICG_NEW_MODE: OFF
8817 11:05:20.089231 XRTWTW_NEW_MODE: ON
8818 11:05:20.092598 XRTRTR_NEW_MODE: ON
8819 11:05:20.092695 TX_TRACKING: ON
8820 11:05:20.096436 RDSEL_TRACKING: OFF
8821 11:05:20.096533 DQS Precalculation for DVFS: ON
8822 11:05:20.099478 RX_TRACKING: OFF
8823 11:05:20.099571 HW_GATING DBG: ON
8824 11:05:20.103148 ZQCS_ENABLE_LP4: ON
8825 11:05:20.103247 RX_PICG_NEW_MODE: ON
8826 11:05:20.105997 TX_PICG_NEW_MODE: ON
8827 11:05:20.110141 ENABLE_RX_DCM_DPHY: ON
8828 11:05:20.113014 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8829 11:05:20.113095 DUMMY_READ_FOR_TRACKING: OFF
8830 11:05:20.116577 !!! SPM_CONTROL_AFTERK: OFF
8831 11:05:20.119750 !!! SPM could not control APHY
8832 11:05:20.123312 IMPEDANCE_TRACKING: ON
8833 11:05:20.123393 TEMP_SENSOR: ON
8834 11:05:20.126011 HW_SAVE_FOR_SR: OFF
8835 11:05:20.126093 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8836 11:05:20.133634 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8837 11:05:20.133715 Read ODT Tracking: ON
8838 11:05:20.136075 Refresh Rate DeBounce: ON
8839 11:05:20.139376 DFS_NO_QUEUE_FLUSH: ON
8840 11:05:20.143391 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8841 11:05:20.143472 ENABLE_DFS_RUNTIME_MRW: OFF
8842 11:05:20.145897 DDR_RESERVE_NEW_MODE: ON
8843 11:05:20.149075 MR_CBT_SWITCH_FREQ: ON
8844 11:05:20.149156 =========================
8845 11:05:20.168593 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8846 11:05:20.171803 dram_init: ddr_geometry: 0
8847 11:05:20.190276 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8848 11:05:20.193931 dram_init: dram init end (result: 0)
8849 11:05:20.200491 DRAM-K: Full calibration passed in 23380 msecs
8850 11:05:20.203407 MRC: failed to locate region type 0.
8851 11:05:20.203516 DRAM rank0 size:0x80000000,
8852 11:05:20.206825 DRAM rank1 size=0x80000000
8853 11:05:20.216439 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8854 11:05:20.223573 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8855 11:05:20.230174 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8856 11:05:20.236411 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8857 11:05:20.240168 DRAM rank0 size:0x80000000,
8858 11:05:20.243730 DRAM rank1 size=0x80000000
8859 11:05:20.243816 CBMEM:
8860 11:05:20.246237 IMD: root @ 0xfffff000 254 entries.
8861 11:05:20.249758 IMD: root @ 0xffffec00 62 entries.
8862 11:05:20.252671 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8863 11:05:20.256258 WARNING: RO_VPD is uninitialized or empty.
8864 11:05:20.262412 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8865 11:05:20.269722 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8866 11:05:20.282630 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8867 11:05:20.293700 BS: romstage times (exec / console): total (unknown) / 22922 ms
8868 11:05:20.293792
8869 11:05:20.293858
8870 11:05:20.303561 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8871 11:05:20.306890 ARM64: Exception handlers installed.
8872 11:05:20.310148 ARM64: Testing exception
8873 11:05:20.313478 ARM64: Done test exception
8874 11:05:20.313570 Enumerating buses...
8875 11:05:20.317065 Show all devs... Before device enumeration.
8876 11:05:20.320159 Root Device: enabled 1
8877 11:05:20.323450 CPU_CLUSTER: 0: enabled 1
8878 11:05:20.323557 CPU: 00: enabled 1
8879 11:05:20.326528 Compare with tree...
8880 11:05:20.326624 Root Device: enabled 1
8881 11:05:20.329696 CPU_CLUSTER: 0: enabled 1
8882 11:05:20.333997 CPU: 00: enabled 1
8883 11:05:20.334093 Root Device scanning...
8884 11:05:20.336792 scan_static_bus for Root Device
8885 11:05:20.339594 CPU_CLUSTER: 0 enabled
8886 11:05:20.343475 scan_static_bus for Root Device done
8887 11:05:20.346172 scan_bus: bus Root Device finished in 8 msecs
8888 11:05:20.346272 done
8889 11:05:20.353467 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8890 11:05:20.357232 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8891 11:05:20.363673 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8892 11:05:20.369579 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8893 11:05:20.369680 Allocating resources...
8894 11:05:20.372871 Reading resources...
8895 11:05:20.376062 Root Device read_resources bus 0 link: 0
8896 11:05:20.379344 DRAM rank0 size:0x80000000,
8897 11:05:20.379442 DRAM rank1 size=0x80000000
8898 11:05:20.386305 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8899 11:05:20.386439 CPU: 00 missing read_resources
8900 11:05:20.393125 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8901 11:05:20.395892 Root Device read_resources bus 0 link: 0 done
8902 11:05:20.398978 Done reading resources.
8903 11:05:20.402591 Show resources in subtree (Root Device)...After reading.
8904 11:05:20.406313 Root Device child on link 0 CPU_CLUSTER: 0
8905 11:05:20.409395 CPU_CLUSTER: 0 child on link 0 CPU: 00
8906 11:05:20.418879 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8907 11:05:20.418982 CPU: 00
8908 11:05:20.422304 Root Device assign_resources, bus 0 link: 0
8909 11:05:20.426797 CPU_CLUSTER: 0 missing set_resources
8910 11:05:20.432058 Root Device assign_resources, bus 0 link: 0 done
8911 11:05:20.432159 Done setting resources.
8912 11:05:20.438613 Show resources in subtree (Root Device)...After assigning values.
8913 11:05:20.442406 Root Device child on link 0 CPU_CLUSTER: 0
8914 11:05:20.445465 CPU_CLUSTER: 0 child on link 0 CPU: 00
8915 11:05:20.455711 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8916 11:05:20.455812 CPU: 00
8917 11:05:20.458952 Done allocating resources.
8918 11:05:20.465672 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8919 11:05:20.465777 Enabling resources...
8920 11:05:20.469240 done.
8921 11:05:20.472420 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8922 11:05:20.475033 Initializing devices...
8923 11:05:20.475129 Root Device init
8924 11:05:20.479591 init hardware done!
8925 11:05:20.479696 0x00000018: ctrlr->caps
8926 11:05:20.481928 52.000 MHz: ctrlr->f_max
8927 11:05:20.485306 0.400 MHz: ctrlr->f_min
8928 11:05:20.485381 0x40ff8080: ctrlr->voltages
8929 11:05:20.488885 sclk: 390625
8930 11:05:20.488981 Bus Width = 1
8931 11:05:20.491971 sclk: 390625
8932 11:05:20.492068 Bus Width = 1
8933 11:05:20.494986 Early init status = 3
8934 11:05:20.498221 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8935 11:05:20.501167 in-header: 03 fc 00 00 01 00 00 00
8936 11:05:20.504634 in-data: 00
8937 11:05:20.508904 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8938 11:05:20.512334 in-header: 03 fd 00 00 00 00 00 00
8939 11:05:20.515548 in-data:
8940 11:05:20.518828 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8941 11:05:20.522322 in-header: 03 fc 00 00 01 00 00 00
8942 11:05:20.525444 in-data: 00
8943 11:05:20.529182 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8944 11:05:20.533834 in-header: 03 fd 00 00 00 00 00 00
8945 11:05:20.536982 in-data:
8946 11:05:20.539931 [SSUSB] Setting up USB HOST controller...
8947 11:05:20.543997 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8948 11:05:20.547089 [SSUSB] phy power-on done.
8949 11:05:20.550528 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8950 11:05:20.556984 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8951 11:05:20.560313 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8952 11:05:20.566387 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8953 11:05:20.573027 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8954 11:05:20.579852 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8955 11:05:20.586877 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8956 11:05:20.592874 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
8957 11:05:20.596224 SPM: binary array size = 0x9dc
8958 11:05:20.599458 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8959 11:05:20.606544 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8960 11:05:20.613115 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8961 11:05:20.619249 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8962 11:05:20.622725 configure_display: Starting display init
8963 11:05:20.657582 anx7625_power_on_init: Init interface.
8964 11:05:20.660300 anx7625_disable_pd_protocol: Disabled PD feature.
8965 11:05:20.663560 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8966 11:05:20.691440 anx7625_start_dp_work: Secure OCM version=00
8967 11:05:20.695071 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8968 11:05:20.709154 sp_tx_get_edid_block: EDID Block = 1
8969 11:05:20.811776 Extracted contents:
8970 11:05:20.815051 header: 00 ff ff ff ff ff ff 00
8971 11:05:20.818822 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8972 11:05:20.822396 version: 01 04
8973 11:05:20.825044 basic params: 95 1f 11 78 0a
8974 11:05:20.828444 chroma info: 76 90 94 55 54 90 27 21 50 54
8975 11:05:20.831523 established: 00 00 00
8976 11:05:20.837974 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8977 11:05:20.841729 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8978 11:05:20.847983 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8979 11:05:20.855213 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8980 11:05:20.861396 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8981 11:05:20.864854 extensions: 00
8982 11:05:20.864928 checksum: fb
8983 11:05:20.864995
8984 11:05:20.868380 Manufacturer: IVO Model 57d Serial Number 0
8985 11:05:20.871856 Made week 0 of 2020
8986 11:05:20.871953 EDID version: 1.4
8987 11:05:20.874913 Digital display
8988 11:05:20.878104 6 bits per primary color channel
8989 11:05:20.878203 DisplayPort interface
8990 11:05:20.881347 Maximum image size: 31 cm x 17 cm
8991 11:05:20.885248 Gamma: 220%
8992 11:05:20.885348 Check DPMS levels
8993 11:05:20.888663 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
8994 11:05:20.894824 First detailed timing is preferred timing
8995 11:05:20.894927 Established timings supported:
8996 11:05:20.898835 Standard timings supported:
8997 11:05:20.901345 Detailed timings
8998 11:05:20.904550 Hex of detail: 383680a07038204018303c0035ae10000019
8999 11:05:20.907670 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9000 11:05:20.914441 0780 0798 07c8 0820 hborder 0
9001 11:05:20.917960 0438 043b 0447 0458 vborder 0
9002 11:05:20.921269 -hsync -vsync
9003 11:05:20.921340 Did detailed timing
9004 11:05:20.928332 Hex of detail: 000000000000000000000000000000000000
9005 11:05:20.928434 Manufacturer-specified data, tag 0
9006 11:05:20.934640 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9007 11:05:20.937803 ASCII string: InfoVision
9008 11:05:20.940976 Hex of detail: 000000fe00523134304e574635205248200a
9009 11:05:20.944447 ASCII string: R140NWF5 RH
9010 11:05:20.944546 Checksum
9011 11:05:20.947660 Checksum: 0xfb (valid)
9012 11:05:20.950693 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9013 11:05:20.954427 DSI data_rate: 832800000 bps
9014 11:05:20.960646 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9015 11:05:20.964639 anx7625_parse_edid: pixelclock(138800).
9016 11:05:20.967847 hactive(1920), hsync(48), hfp(24), hbp(88)
9017 11:05:20.970893 vactive(1080), vsync(12), vfp(3), vbp(17)
9018 11:05:20.974468 anx7625_dsi_config: config dsi.
9019 11:05:20.981142 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9020 11:05:20.994870 anx7625_dsi_config: success to config DSI
9021 11:05:20.997325 anx7625_dp_start: MIPI phy setup OK.
9022 11:05:21.000653 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9023 11:05:21.004529 mtk_ddp_mode_set invalid vrefresh 60
9024 11:05:21.007143 main_disp_path_setup
9025 11:05:21.007241 ovl_layer_smi_id_en
9026 11:05:21.011018 ovl_layer_smi_id_en
9027 11:05:21.011113 ccorr_config
9028 11:05:21.011200 aal_config
9029 11:05:21.013674 gamma_config
9030 11:05:21.013743 postmask_config
9031 11:05:21.016995 dither_config
9032 11:05:21.020181 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9033 11:05:21.027412 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9034 11:05:21.030126 Root Device init finished in 551 msecs
9035 11:05:21.033857 CPU_CLUSTER: 0 init
9036 11:05:21.040703 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9037 11:05:21.043385 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9038 11:05:21.047474 APU_MBOX 0x190000b0 = 0x10001
9039 11:05:21.050389 APU_MBOX 0x190001b0 = 0x10001
9040 11:05:21.053565 APU_MBOX 0x190005b0 = 0x10001
9041 11:05:21.056808 APU_MBOX 0x190006b0 = 0x10001
9042 11:05:21.060257 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9043 11:05:21.073186 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9044 11:05:21.085572 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9045 11:05:21.091961 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9046 11:05:21.103369 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9047 11:05:21.113097 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9048 11:05:21.115865 CPU_CLUSTER: 0 init finished in 81 msecs
9049 11:05:21.119619 Devices initialized
9050 11:05:21.122821 Show all devs... After init.
9051 11:05:21.122918 Root Device: enabled 1
9052 11:05:21.125660 CPU_CLUSTER: 0: enabled 1
9053 11:05:21.130031 CPU: 00: enabled 1
9054 11:05:21.132574 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9055 11:05:21.135476 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9056 11:05:21.139221 ELOG: NV offset 0x57f000 size 0x1000
9057 11:05:21.146559 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9058 11:05:21.153672 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9059 11:05:21.155829 ELOG: Event(17) added with size 13 at 2024-03-03 11:05:22 UTC
9060 11:05:21.159517 out: cmd=0x121: 03 db 21 01 00 00 00 00
9061 11:05:21.163290 in-header: 03 29 00 00 2c 00 00 00
9062 11:05:21.176600 in-data: 3a 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9063 11:05:21.182723 ELOG: Event(A1) added with size 10 at 2024-03-03 11:05:22 UTC
9064 11:05:21.189629 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9065 11:05:21.196118 ELOG: Event(A0) added with size 9 at 2024-03-03 11:05:23 UTC
9066 11:05:21.199307 elog_add_boot_reason: Logged dev mode boot
9067 11:05:21.203029 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9068 11:05:21.206081 Finalize devices...
9069 11:05:21.206178 Devices finalized
9070 11:05:21.213226 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9071 11:05:21.216072 Writing coreboot table at 0xffe64000
9072 11:05:21.219098 0. 000000000010a000-0000000000113fff: RAMSTAGE
9073 11:05:21.223674 1. 0000000040000000-00000000400fffff: RAM
9074 11:05:21.229209 2. 0000000040100000-000000004032afff: RAMSTAGE
9075 11:05:21.232801 3. 000000004032b000-00000000545fffff: RAM
9076 11:05:21.236275 4. 0000000054600000-000000005465ffff: BL31
9077 11:05:21.239215 5. 0000000054660000-00000000ffe63fff: RAM
9078 11:05:21.245808 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9079 11:05:21.249229 7. 0000000100000000-000000013fffffff: RAM
9080 11:05:21.249303 Passing 5 GPIOs to payload:
9081 11:05:21.256056 NAME | PORT | POLARITY | VALUE
9082 11:05:21.259732 EC in RW | 0x000000aa | low | undefined
9083 11:05:21.265947 EC interrupt | 0x00000005 | low | undefined
9084 11:05:21.268911 TPM interrupt | 0x000000ab | high | undefined
9085 11:05:21.275322 SD card detect | 0x00000011 | high | undefined
9086 11:05:21.278836 speaker enable | 0x00000093 | high | undefined
9087 11:05:21.282791 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9088 11:05:21.285404 in-header: 03 ef 00 00 02 00 00 00
9089 11:05:21.288997 in-data: 0c 00
9090 11:05:21.289105 ADC[4]: Raw value=668958 ID=5
9091 11:05:21.291857 ADC[3]: Raw value=212549 ID=1
9092 11:05:21.295783 RAM Code: 0x51
9093 11:05:21.295854 ADC[6]: Raw value=74410 ID=0
9094 11:05:21.298500 ADC[5]: Raw value=211444 ID=1
9095 11:05:21.302050 SKU Code: 0x1
9096 11:05:21.305656 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum cf5b
9097 11:05:21.309951 coreboot table: 964 bytes.
9098 11:05:21.311765 IMD ROOT 0. 0xfffff000 0x00001000
9099 11:05:21.314858 IMD SMALL 1. 0xffffe000 0x00001000
9100 11:05:21.319847 RO MCACHE 2. 0xffffc000 0x00001104
9101 11:05:21.321871 CONSOLE 3. 0xfff7c000 0x00080000
9102 11:05:21.325323 FMAP 4. 0xfff7b000 0x00000452
9103 11:05:21.329318 TIME STAMP 5. 0xfff7a000 0x00000910
9104 11:05:21.332035 VBOOT WORK 6. 0xfff66000 0x00014000
9105 11:05:21.335105 RAMOOPS 7. 0xffe66000 0x00100000
9106 11:05:21.338931 COREBOOT 8. 0xffe64000 0x00002000
9107 11:05:21.339028 IMD small region:
9108 11:05:21.341893 IMD ROOT 0. 0xffffec00 0x00000400
9109 11:05:21.344834 VPD 1. 0xffffeb80 0x0000006c
9110 11:05:21.351513 MMC STATUS 2. 0xffffeb60 0x00000004
9111 11:05:21.354737 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9112 11:05:21.359667 Probing TPM: done!
9113 11:05:21.362063 Connected to device vid:did:rid of 1ae0:0028:00
9114 11:05:21.371947 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9115 11:05:21.375029 Initialized TPM device CR50 revision 0
9116 11:05:21.378778 Checking cr50 for pending updates
9117 11:05:21.382314 Reading cr50 TPM mode
9118 11:05:21.391373 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9119 11:05:21.397349 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9120 11:05:21.437885 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9121 11:05:21.441141 Checking segment from ROM address 0x40100000
9122 11:05:21.444971 Checking segment from ROM address 0x4010001c
9123 11:05:21.451236 Loading segment from ROM address 0x40100000
9124 11:05:21.451338 code (compression=0)
9125 11:05:21.461149 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9126 11:05:21.467387 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9127 11:05:21.467489 it's not compressed!
9128 11:05:21.474028 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9129 11:05:21.477371 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9130 11:05:21.498170 Loading segment from ROM address 0x4010001c
9131 11:05:21.498278 Entry Point 0x80000000
9132 11:05:21.501806 Loaded segments
9133 11:05:21.504966 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9134 11:05:21.511745 Jumping to boot code at 0x80000000(0xffe64000)
9135 11:05:21.519092 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9136 11:05:21.524808 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9137 11:05:21.532920 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9138 11:05:21.535947 Checking segment from ROM address 0x40100000
9139 11:05:21.539255 Checking segment from ROM address 0x4010001c
9140 11:05:21.545660 Loading segment from ROM address 0x40100000
9141 11:05:21.545759 code (compression=1)
9142 11:05:21.553183 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9143 11:05:21.562617 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9144 11:05:21.562720 using LZMA
9145 11:05:21.570826 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9146 11:05:21.577832 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9147 11:05:21.580679 Loading segment from ROM address 0x4010001c
9148 11:05:21.580818 Entry Point 0x54601000
9149 11:05:21.584207 Loaded segments
9150 11:05:21.587550 NOTICE: MT8192 bl31_setup
9151 11:05:21.594638 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9152 11:05:21.597700 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9153 11:05:21.601153 WARNING: region 0:
9154 11:05:21.604430 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9155 11:05:21.604540 WARNING: region 1:
9156 11:05:21.611250 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9157 11:05:21.614595 WARNING: region 2:
9158 11:05:21.617445 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9159 11:05:21.621071 WARNING: region 3:
9160 11:05:21.624333 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9161 11:05:21.627706 WARNING: region 4:
9162 11:05:21.634537 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9163 11:05:21.634646 WARNING: region 5:
9164 11:05:21.637600 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9165 11:05:21.641134 WARNING: region 6:
9166 11:05:21.644380 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9167 11:05:21.647632 WARNING: region 7:
9168 11:05:21.651077 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9169 11:05:21.658101 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9170 11:05:21.661551 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9171 11:05:21.664702 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9172 11:05:21.670889 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9173 11:05:21.675101 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9174 11:05:21.677610 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9175 11:05:21.684228 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9176 11:05:21.688124 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9177 11:05:21.695283 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9178 11:05:21.697816 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9179 11:05:21.700623 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9180 11:05:21.707535 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9181 11:05:21.710721 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9182 11:05:21.714476 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9183 11:05:21.721421 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9184 11:05:21.724696 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9185 11:05:21.730928 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9186 11:05:21.734289 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9187 11:05:21.737938 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9188 11:05:21.744506 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9189 11:05:21.747737 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9190 11:05:21.750858 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9191 11:05:21.757476 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9192 11:05:21.761123 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9193 11:05:21.767789 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9194 11:05:21.771369 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9195 11:05:21.774207 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9196 11:05:21.781180 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9197 11:05:21.783972 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9198 11:05:21.791298 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9199 11:05:21.794685 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9200 11:05:21.797751 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9201 11:05:21.804333 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9202 11:05:21.807831 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9203 11:05:21.811536 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9204 11:05:21.814554 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9205 11:05:21.821751 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9206 11:05:21.824213 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9207 11:05:21.827421 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9208 11:05:21.831217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9209 11:05:21.834352 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9210 11:05:21.841113 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9211 11:05:21.844290 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9212 11:05:21.847467 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9213 11:05:21.854011 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9214 11:05:21.857600 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9215 11:05:21.860895 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9216 11:05:21.864018 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9217 11:05:21.871129 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9218 11:05:21.874311 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9219 11:05:21.881264 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9220 11:05:21.884691 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9221 11:05:21.887695 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9222 11:05:21.894127 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9223 11:05:21.897675 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9224 11:05:21.905290 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9225 11:05:21.907815 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9226 11:05:21.914157 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9227 11:05:21.918572 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9228 11:05:21.921097 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9229 11:05:21.927401 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9230 11:05:21.931317 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9231 11:05:21.937498 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9232 11:05:21.940953 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9233 11:05:21.947999 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9234 11:05:21.951146 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9235 11:05:21.957552 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9236 11:05:21.961210 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9237 11:05:21.964278 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9238 11:05:21.971078 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9239 11:05:21.974395 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9240 11:05:21.981370 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9241 11:05:21.984172 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9242 11:05:21.987535 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9243 11:05:21.994307 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9244 11:05:21.997365 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9245 11:05:22.004673 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9246 11:05:22.007752 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9247 11:05:22.014080 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9248 11:05:22.017738 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9249 11:05:22.025043 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9250 11:05:22.027674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9251 11:05:22.031088 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9252 11:05:22.037453 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9253 11:05:22.041067 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9254 11:05:22.047960 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9255 11:05:22.050744 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9256 11:05:22.057862 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9257 11:05:22.061111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9258 11:05:22.063993 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9259 11:05:22.071030 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9260 11:05:22.074343 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9261 11:05:22.081181 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9262 11:05:22.084220 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9263 11:05:22.090851 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9264 11:05:22.094247 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9265 11:05:22.097738 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9266 11:05:22.104132 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9267 11:05:22.107189 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9268 11:05:22.111049 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9269 11:05:22.113965 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9270 11:05:22.120952 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9271 11:05:22.123813 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9272 11:05:22.130860 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9273 11:05:22.133791 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9274 11:05:22.137230 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9275 11:05:22.143667 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9276 11:05:22.147626 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9277 11:05:22.154430 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9278 11:05:22.157212 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9279 11:05:22.160425 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9280 11:05:22.167110 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9281 11:05:22.170723 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9282 11:05:22.177188 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9283 11:05:22.180445 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9284 11:05:22.184201 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9285 11:05:22.187335 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9286 11:05:22.194304 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9287 11:05:22.197558 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9288 11:05:22.200976 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9289 11:05:22.208116 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9290 11:05:22.211148 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9291 11:05:22.213939 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9292 11:05:22.217158 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9293 11:05:22.223624 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9294 11:05:22.227268 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9295 11:05:22.234563 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9296 11:05:22.237293 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9297 11:05:22.241846 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9298 11:05:22.247472 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9299 11:05:22.250457 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9300 11:05:22.257165 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9301 11:05:22.260772 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9302 11:05:22.264029 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9303 11:05:22.270723 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9304 11:05:22.273570 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9305 11:05:22.276868 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9306 11:05:22.284032 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9307 11:05:22.286953 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9308 11:05:22.293658 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9309 11:05:22.297252 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9310 11:05:22.300123 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9311 11:05:22.307226 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9312 11:05:22.310699 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9313 11:05:22.318099 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9314 11:05:22.320549 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9315 11:05:22.324437 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9316 11:05:22.330286 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9317 11:05:22.333514 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9318 11:05:22.341151 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9319 11:05:22.343745 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9320 11:05:22.347243 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9321 11:05:22.353340 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9322 11:05:22.356746 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9323 11:05:22.360286 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9324 11:05:22.366784 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9325 11:05:22.370230 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9326 11:05:22.377085 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9327 11:05:22.380541 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9328 11:05:22.383905 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9329 11:05:22.390573 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9330 11:05:22.393628 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9331 11:05:22.400161 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9332 11:05:22.403426 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9333 11:05:22.406770 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9334 11:05:22.413402 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9335 11:05:22.416549 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9336 11:05:22.423234 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9337 11:05:22.426417 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9338 11:05:22.429640 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9339 11:05:22.436800 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9340 11:05:22.439406 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9341 11:05:22.446674 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9342 11:05:22.449717 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9343 11:05:22.453226 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9344 11:05:22.459791 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9345 11:05:22.462908 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9346 11:05:22.469321 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9347 11:05:22.472883 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9348 11:05:22.476060 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9349 11:05:22.482517 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9350 11:05:22.486706 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9351 11:05:22.492764 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9352 11:05:22.496023 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9353 11:05:22.499450 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9354 11:05:22.505841 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9355 11:05:22.509089 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9356 11:05:22.512332 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9357 11:05:22.519092 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9358 11:05:22.522284 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9359 11:05:22.529212 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9360 11:05:22.532432 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9361 11:05:22.538835 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9362 11:05:22.542196 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9363 11:05:22.545626 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9364 11:05:22.552020 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9365 11:05:22.555389 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9366 11:05:22.562459 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9367 11:05:22.565368 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9368 11:05:22.572088 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9369 11:05:22.575895 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9370 11:05:22.578873 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9371 11:05:22.585231 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9372 11:05:22.588483 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9373 11:05:22.595725 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9374 11:05:22.598656 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9375 11:05:22.605005 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9376 11:05:22.608398 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9377 11:05:22.611962 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9378 11:05:22.618512 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9379 11:05:22.621505 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9380 11:05:22.628802 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9381 11:05:22.632420 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9382 11:05:22.635327 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9383 11:05:22.642023 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9384 11:05:22.645047 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9385 11:05:22.651344 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9386 11:05:22.654689 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9387 11:05:22.661308 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9388 11:05:22.665510 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9389 11:05:22.668610 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9390 11:05:22.674880 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9391 11:05:22.678103 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9392 11:05:22.684996 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9393 11:05:22.688274 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9394 11:05:22.691510 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9395 11:05:22.698278 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9396 11:05:22.701686 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9397 11:05:22.708072 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9398 11:05:22.711742 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9399 11:05:22.714711 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9400 11:05:22.718281 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9401 11:05:22.721555 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9402 11:05:22.728912 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9403 11:05:22.731606 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9404 11:05:22.737805 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9405 11:05:22.740917 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9406 11:05:22.744442 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9407 11:05:22.752226 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9408 11:05:22.754675 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9409 11:05:22.757840 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9410 11:05:22.764375 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9411 11:05:22.767668 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9412 11:05:22.771071 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9413 11:05:22.777583 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9414 11:05:22.781252 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9415 11:05:22.788616 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9416 11:05:22.791103 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9417 11:05:22.794557 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9418 11:05:22.801162 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9419 11:05:22.804610 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9420 11:05:22.808076 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9421 11:05:22.814306 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9422 11:05:22.818177 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9423 11:05:22.820833 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9424 11:05:22.827780 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9425 11:05:22.830816 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9426 11:05:22.837204 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9427 11:05:22.841430 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9428 11:05:22.843814 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9429 11:05:22.850753 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9430 11:05:22.853728 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9431 11:05:22.860374 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9432 11:05:22.863936 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9433 11:05:22.867169 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9434 11:05:22.874121 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9435 11:05:22.877468 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9436 11:05:22.880416 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9437 11:05:22.888046 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9438 11:05:22.890572 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9439 11:05:22.893930 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9440 11:05:22.897518 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9441 11:05:22.904244 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9442 11:05:22.906805 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9443 11:05:22.910664 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9444 11:05:22.914578 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9445 11:05:22.920484 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9446 11:05:22.923816 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9447 11:05:22.926795 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9448 11:05:22.930149 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9449 11:05:22.936689 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9450 11:05:22.940487 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9451 11:05:22.943234 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9452 11:05:22.950237 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9453 11:05:22.953194 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9454 11:05:22.960577 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9455 11:05:22.963258 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9456 11:05:22.966421 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9457 11:05:22.972992 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9458 11:05:22.976349 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9459 11:05:22.984077 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9460 11:05:22.986416 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9461 11:05:22.989816 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9462 11:05:22.996038 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9463 11:05:22.999399 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9464 11:05:23.005965 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9465 11:05:23.010106 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9466 11:05:23.012967 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9467 11:05:23.019404 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9468 11:05:23.022798 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9469 11:05:23.029229 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9470 11:05:23.032631 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9471 11:05:23.039204 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9472 11:05:23.042899 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9473 11:05:23.049110 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9474 11:05:23.052378 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9475 11:05:23.056039 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9476 11:05:23.062443 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9477 11:05:23.066054 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9478 11:05:23.072643 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9479 11:05:23.075851 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9480 11:05:23.078713 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9481 11:05:23.085418 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9482 11:05:23.088558 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9483 11:05:23.095200 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9484 11:05:23.099255 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9485 11:05:23.102429 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9486 11:05:23.108802 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9487 11:05:23.112051 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9488 11:05:23.118411 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9489 11:05:23.122468 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9490 11:05:23.125258 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9491 11:05:23.131851 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9492 11:05:23.134897 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9493 11:05:23.142069 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9494 11:05:23.145098 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9495 11:05:23.151682 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9496 11:05:23.155188 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9497 11:05:23.158363 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9498 11:05:23.165426 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9499 11:05:23.168370 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9500 11:05:23.174881 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9501 11:05:23.178283 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9502 11:05:23.181567 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9503 11:05:23.188065 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9504 11:05:23.192030 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9505 11:05:23.197984 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9506 11:05:23.201764 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9507 11:05:23.204889 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9508 11:05:23.211653 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9509 11:05:23.214295 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9510 11:05:23.221054 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9511 11:05:23.224577 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9512 11:05:23.231267 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9513 11:05:23.234110 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9514 11:05:23.237681 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9515 11:05:23.244172 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9516 11:05:23.247127 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9517 11:05:23.254119 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9518 11:05:23.257011 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9519 11:05:23.264310 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9520 11:05:23.267614 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9521 11:05:23.270395 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9522 11:05:23.277751 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9523 11:05:23.280138 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9524 11:05:23.288156 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9525 11:05:23.290478 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9526 11:05:23.297052 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9527 11:05:23.300181 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9528 11:05:23.304102 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9529 11:05:23.310618 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9530 11:05:23.314002 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9531 11:05:23.320096 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9532 11:05:23.323619 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9533 11:05:23.329981 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9534 11:05:23.333918 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9535 11:05:23.337731 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9536 11:05:23.343756 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9537 11:05:23.346891 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9538 11:05:23.353539 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9539 11:05:23.356310 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9540 11:05:23.363293 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9541 11:05:23.366881 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9542 11:05:23.373157 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9543 11:05:23.376638 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9544 11:05:23.382957 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9545 11:05:23.386207 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9546 11:05:23.389609 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9547 11:05:23.397060 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9548 11:05:23.399236 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9549 11:05:23.406641 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9550 11:05:23.409289 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9551 11:05:23.415947 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9552 11:05:23.419663 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9553 11:05:23.422605 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9554 11:05:23.429807 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9555 11:05:23.433172 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9556 11:05:23.439494 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9557 11:05:23.442629 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9558 11:05:23.448685 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9559 11:05:23.452869 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9560 11:05:23.458976 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9561 11:05:23.462401 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9562 11:05:23.465467 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9563 11:05:23.472374 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9564 11:05:23.475614 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9565 11:05:23.481821 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9566 11:05:23.485370 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9567 11:05:23.492030 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9568 11:05:23.495158 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9569 11:05:23.501757 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9570 11:05:23.505565 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9571 11:05:23.509269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9572 11:05:23.515719 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9573 11:05:23.519027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9574 11:05:23.521958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9575 11:05:23.528897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9576 11:05:23.531797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9577 11:05:23.538275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9578 11:05:23.541535 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9579 11:05:23.549178 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9580 11:05:23.552037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9581 11:05:23.558428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9582 11:05:23.562290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9583 11:05:23.568396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9584 11:05:23.571452 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9585 11:05:23.578485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9586 11:05:23.581320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9587 11:05:23.588268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9588 11:05:23.591523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9589 11:05:23.598076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9590 11:05:23.601945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9591 11:05:23.608765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9592 11:05:23.611283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9593 11:05:23.618643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9594 11:05:23.621713 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9595 11:05:23.628449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9596 11:05:23.631442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9597 11:05:23.638321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9598 11:05:23.641896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9599 11:05:23.648239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9600 11:05:23.651616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9601 11:05:23.658355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9602 11:05:23.661023 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9603 11:05:23.664567 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9604 11:05:23.668343 INFO: [APUAPC] vio 0
9605 11:05:23.674637 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9606 11:05:23.677667 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9607 11:05:23.681145 INFO: [APUAPC] D0_APC_0: 0x400510
9608 11:05:23.685069 INFO: [APUAPC] D0_APC_1: 0x0
9609 11:05:23.687890 INFO: [APUAPC] D0_APC_2: 0x1540
9610 11:05:23.690944 INFO: [APUAPC] D0_APC_3: 0x0
9611 11:05:23.694456 INFO: [APUAPC] D1_APC_0: 0xffffffff
9612 11:05:23.698204 INFO: [APUAPC] D1_APC_1: 0xffffffff
9613 11:05:23.700797 INFO: [APUAPC] D1_APC_2: 0x3fffff
9614 11:05:23.704550 INFO: [APUAPC] D1_APC_3: 0x0
9615 11:05:23.707598 INFO: [APUAPC] D2_APC_0: 0xffffffff
9616 11:05:23.710650 INFO: [APUAPC] D2_APC_1: 0xffffffff
9617 11:05:23.714739 INFO: [APUAPC] D2_APC_2: 0x3fffff
9618 11:05:23.717743 INFO: [APUAPC] D2_APC_3: 0x0
9619 11:05:23.721174 INFO: [APUAPC] D3_APC_0: 0xffffffff
9620 11:05:23.724465 INFO: [APUAPC] D3_APC_1: 0xffffffff
9621 11:05:23.727823 INFO: [APUAPC] D3_APC_2: 0x3fffff
9622 11:05:23.730453 INFO: [APUAPC] D3_APC_3: 0x0
9623 11:05:23.734191 INFO: [APUAPC] D4_APC_0: 0xffffffff
9624 11:05:23.738314 INFO: [APUAPC] D4_APC_1: 0xffffffff
9625 11:05:23.741383 INFO: [APUAPC] D4_APC_2: 0x3fffff
9626 11:05:23.741485 INFO: [APUAPC] D4_APC_3: 0x0
9627 11:05:23.744246 INFO: [APUAPC] D5_APC_0: 0xffffffff
9628 11:05:23.750784 INFO: [APUAPC] D5_APC_1: 0xffffffff
9629 11:05:23.753757 INFO: [APUAPC] D5_APC_2: 0x3fffff
9630 11:05:23.753857 INFO: [APUAPC] D5_APC_3: 0x0
9631 11:05:23.757600 INFO: [APUAPC] D6_APC_0: 0xffffffff
9632 11:05:23.760616 INFO: [APUAPC] D6_APC_1: 0xffffffff
9633 11:05:23.763781 INFO: [APUAPC] D6_APC_2: 0x3fffff
9634 11:05:23.768214 INFO: [APUAPC] D6_APC_3: 0x0
9635 11:05:23.770855 INFO: [APUAPC] D7_APC_0: 0xffffffff
9636 11:05:23.773733 INFO: [APUAPC] D7_APC_1: 0xffffffff
9637 11:05:23.777442 INFO: [APUAPC] D7_APC_2: 0x3fffff
9638 11:05:23.780874 INFO: [APUAPC] D7_APC_3: 0x0
9639 11:05:23.783843 INFO: [APUAPC] D8_APC_0: 0xffffffff
9640 11:05:23.786973 INFO: [APUAPC] D8_APC_1: 0xffffffff
9641 11:05:23.790540 INFO: [APUAPC] D8_APC_2: 0x3fffff
9642 11:05:23.794149 INFO: [APUAPC] D8_APC_3: 0x0
9643 11:05:23.797395 INFO: [APUAPC] D9_APC_0: 0xffffffff
9644 11:05:23.800278 INFO: [APUAPC] D9_APC_1: 0xffffffff
9645 11:05:23.804094 INFO: [APUAPC] D9_APC_2: 0x3fffff
9646 11:05:23.807131 INFO: [APUAPC] D9_APC_3: 0x0
9647 11:05:23.810957 INFO: [APUAPC] D10_APC_0: 0xffffffff
9648 11:05:23.813714 INFO: [APUAPC] D10_APC_1: 0xffffffff
9649 11:05:23.816928 INFO: [APUAPC] D10_APC_2: 0x3fffff
9650 11:05:23.820627 INFO: [APUAPC] D10_APC_3: 0x0
9651 11:05:23.823415 INFO: [APUAPC] D11_APC_0: 0xffffffff
9652 11:05:23.827437 INFO: [APUAPC] D11_APC_1: 0xffffffff
9653 11:05:23.830808 INFO: [APUAPC] D11_APC_2: 0x3fffff
9654 11:05:23.834320 INFO: [APUAPC] D11_APC_3: 0x0
9655 11:05:23.837592 INFO: [APUAPC] D12_APC_0: 0xffffffff
9656 11:05:23.840542 INFO: [APUAPC] D12_APC_1: 0xffffffff
9657 11:05:23.843731 INFO: [APUAPC] D12_APC_2: 0x3fffff
9658 11:05:23.847296 INFO: [APUAPC] D12_APC_3: 0x0
9659 11:05:23.850487 INFO: [APUAPC] D13_APC_0: 0xffffffff
9660 11:05:23.853491 INFO: [APUAPC] D13_APC_1: 0xffffffff
9661 11:05:23.856780 INFO: [APUAPC] D13_APC_2: 0x3fffff
9662 11:05:23.859980 INFO: [APUAPC] D13_APC_3: 0x0
9663 11:05:23.864441 INFO: [APUAPC] D14_APC_0: 0xffffffff
9664 11:05:23.866709 INFO: [APUAPC] D14_APC_1: 0xffffffff
9665 11:05:23.870126 INFO: [APUAPC] D14_APC_2: 0x3fffff
9666 11:05:23.873438 INFO: [APUAPC] D14_APC_3: 0x0
9667 11:05:23.876782 INFO: [APUAPC] D15_APC_0: 0xffffffff
9668 11:05:23.880418 INFO: [APUAPC] D15_APC_1: 0xffffffff
9669 11:05:23.883621 INFO: [APUAPC] D15_APC_2: 0x3fffff
9670 11:05:23.886326 INFO: [APUAPC] D15_APC_3: 0x0
9671 11:05:23.889631 INFO: [APUAPC] APC_CON: 0x4
9672 11:05:23.893583 INFO: [NOCDAPC] D0_APC_0: 0x0
9673 11:05:23.896492 INFO: [NOCDAPC] D0_APC_1: 0x0
9674 11:05:23.899681 INFO: [NOCDAPC] D1_APC_0: 0x0
9675 11:05:23.903094 INFO: [NOCDAPC] D1_APC_1: 0xfff
9676 11:05:23.906430 INFO: [NOCDAPC] D2_APC_0: 0x0
9677 11:05:23.906525 INFO: [NOCDAPC] D2_APC_1: 0xfff
9678 11:05:23.910021 INFO: [NOCDAPC] D3_APC_0: 0x0
9679 11:05:23.913701 INFO: [NOCDAPC] D3_APC_1: 0xfff
9680 11:05:23.916027 INFO: [NOCDAPC] D4_APC_0: 0x0
9681 11:05:23.919330 INFO: [NOCDAPC] D4_APC_1: 0xfff
9682 11:05:23.923081 INFO: [NOCDAPC] D5_APC_0: 0x0
9683 11:05:23.926582 INFO: [NOCDAPC] D5_APC_1: 0xfff
9684 11:05:23.929632 INFO: [NOCDAPC] D6_APC_0: 0x0
9685 11:05:23.933220 INFO: [NOCDAPC] D6_APC_1: 0xfff
9686 11:05:23.936615 INFO: [NOCDAPC] D7_APC_0: 0x0
9687 11:05:23.939672 INFO: [NOCDAPC] D7_APC_1: 0xfff
9688 11:05:23.939767 INFO: [NOCDAPC] D8_APC_0: 0x0
9689 11:05:23.942675 INFO: [NOCDAPC] D8_APC_1: 0xfff
9690 11:05:23.946037 INFO: [NOCDAPC] D9_APC_0: 0x0
9691 11:05:23.949137 INFO: [NOCDAPC] D9_APC_1: 0xfff
9692 11:05:23.952734 INFO: [NOCDAPC] D10_APC_0: 0x0
9693 11:05:23.957277 INFO: [NOCDAPC] D10_APC_1: 0xfff
9694 11:05:23.959877 INFO: [NOCDAPC] D11_APC_0: 0x0
9695 11:05:23.963204 INFO: [NOCDAPC] D11_APC_1: 0xfff
9696 11:05:23.966109 INFO: [NOCDAPC] D12_APC_0: 0x0
9697 11:05:23.969341 INFO: [NOCDAPC] D12_APC_1: 0xfff
9698 11:05:23.972465 INFO: [NOCDAPC] D13_APC_0: 0x0
9699 11:05:23.976328 INFO: [NOCDAPC] D13_APC_1: 0xfff
9700 11:05:23.979010 INFO: [NOCDAPC] D14_APC_0: 0x0
9701 11:05:23.982290 INFO: [NOCDAPC] D14_APC_1: 0xfff
9702 11:05:23.985939 INFO: [NOCDAPC] D15_APC_0: 0x0
9703 11:05:23.986048 INFO: [NOCDAPC] D15_APC_1: 0xfff
9704 11:05:23.989462 INFO: [NOCDAPC] APC_CON: 0x4
9705 11:05:23.992606 INFO: [APUAPC] set_apusys_apc done
9706 11:05:23.995657 INFO: [DEVAPC] devapc_init done
9707 11:05:24.002150 INFO: GICv3 without legacy support detected.
9708 11:05:24.005817 INFO: ARM GICv3 driver initialized in EL3
9709 11:05:24.008948 INFO: Maximum SPI INTID supported: 639
9710 11:05:24.012455 INFO: BL31: Initializing runtime services
9711 11:05:24.019520 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9712 11:05:24.022868 INFO: SPM: enable CPC mode
9713 11:05:24.025621 INFO: mcdi ready for mcusys-off-idle and system suspend
9714 11:05:24.032272 INFO: BL31: Preparing for EL3 exit to normal world
9715 11:05:24.035795 INFO: Entry point address = 0x80000000
9716 11:05:24.035891 INFO: SPSR = 0x8
9717 11:05:24.042758
9718 11:05:24.042856
9719 11:05:24.042947
9720 11:05:24.045342 Starting depthcharge on Spherion...
9721 11:05:24.045436
9722 11:05:24.045526 Wipe memory regions:
9723 11:05:24.045611
9724 11:05:24.046470 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9725 11:05:24.046598 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9726 11:05:24.046709 Setting prompt string to ['asurada:']
9727 11:05:24.046815 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9728 11:05:24.048800 [0x00000040000000, 0x00000054600000)
9729 11:05:24.171621
9730 11:05:24.171758 [0x00000054660000, 0x00000080000000)
9731 11:05:24.431791
9732 11:05:24.435247 [0x000000821a7280, 0x000000ffe64000)
9733 11:05:25.177475
9734 11:05:25.177616 [0x00000100000000, 0x00000140000000)
9735 11:05:25.558722
9736 11:05:25.561352 Initializing XHCI USB controller at 0x11200000.
9737 11:05:26.599602
9738 11:05:26.603064 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9739 11:05:26.603167
9740 11:05:26.603257
9741 11:05:26.603348
9742 11:05:26.603661 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9744 11:05:26.704029 asurada: tftpboot 192.168.201.1 12925608/tftp-deploy-eut2f_1y/kernel/image.itb 12925608/tftp-deploy-eut2f_1y/kernel/cmdline
9745 11:05:26.704154 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9746 11:05:26.704239 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9747 11:05:26.708710 tftpboot 192.168.201.1 12925608/tftp-deploy-eut2f_1y/kernel/image.itp-deploy-eut2f_1y/kernel/cmdline
9748 11:05:26.708806
9749 11:05:26.708872 Waiting for link
9750 11:05:26.866725
9751 11:05:26.866852 R8152: Initializing
9752 11:05:26.866919
9753 11:05:26.869908 Version 9 (ocp_data = 6010)
9754 11:05:26.869989
9755 11:05:26.873410 R8152: Done initializing
9756 11:05:26.873492
9757 11:05:26.873558 Adding net device
9758 11:05:28.908800
9759 11:05:28.908943 done.
9760 11:05:28.909014
9761 11:05:28.909080 MAC: 00:e0:4c:68:03:bd
9762 11:05:28.909140
9763 11:05:28.911200 Sending DHCP discover... done.
9764 11:05:28.911281
9765 11:05:28.915033 Waiting for reply... done.
9766 11:05:28.915147
9767 11:05:28.918563 Sending DHCP request... done.
9768 11:05:28.918647
9769 11:05:28.918711 Waiting for reply... done.
9770 11:05:28.918770
9771 11:05:28.921603 My ip is 192.168.201.16
9772 11:05:28.921683
9773 11:05:28.924666 The DHCP server ip is 192.168.201.1
9774 11:05:28.924786
9775 11:05:28.928532 TFTP server IP predefined by user: 192.168.201.1
9776 11:05:28.928611
9777 11:05:28.934780 Bootfile predefined by user: 12925608/tftp-deploy-eut2f_1y/kernel/image.itb
9778 11:05:28.934859
9779 11:05:28.938324 Sending tftp read request... done.
9780 11:05:28.938507
9781 11:05:28.942356 Waiting for the transfer...
9782 11:05:28.942436
9783 11:05:29.201322 00000000 ################################################################
9784 11:05:29.201467
9785 11:05:29.456353 00080000 ################################################################
9786 11:05:29.456520
9787 11:05:29.707993 00100000 ################################################################
9788 11:05:29.708140
9789 11:05:29.959456 00180000 ################################################################
9790 11:05:29.959611
9791 11:05:30.216150 00200000 ################################################################
9792 11:05:30.216296
9793 11:05:30.471810 00280000 ################################################################
9794 11:05:30.471947
9795 11:05:30.738234 00300000 ################################################################
9796 11:05:30.738396
9797 11:05:30.996965 00380000 ################################################################
9798 11:05:30.997161
9799 11:05:31.259840 00400000 ################################################################
9800 11:05:31.260011
9801 11:05:31.529084 00480000 ################################################################
9802 11:05:31.529265
9803 11:05:31.787722 00500000 ################################################################
9804 11:05:31.787887
9805 11:05:32.056157 00580000 ################################################################
9806 11:05:32.056316
9807 11:05:32.315820 00600000 ################################################################
9808 11:05:32.315976
9809 11:05:32.570617 00680000 ################################################################
9810 11:05:32.570785
9811 11:05:32.828207 00700000 ################################################################
9812 11:05:32.828381
9813 11:05:33.101014 00780000 ################################################################
9814 11:05:33.101177
9815 11:05:33.356016 00800000 ################################################################
9816 11:05:33.356185
9817 11:05:33.646362 00880000 ################################################################
9818 11:05:33.646522
9819 11:05:33.928929 00900000 ################################################################
9820 11:05:33.929060
9821 11:05:34.205651 00980000 ################################################################
9822 11:05:34.205786
9823 11:05:34.490256 00a00000 ################################################################
9824 11:05:34.490396
9825 11:05:34.787940 00a80000 ################################################################
9826 11:05:34.788104
9827 11:05:35.082621 00b00000 ################################################################
9828 11:05:35.082792
9829 11:05:35.464027 00b80000 ################################################################
9830 11:05:35.464625
9831 11:05:35.772075 00c00000 ################################################################
9832 11:05:35.772234
9833 11:05:36.052796 00c80000 ################################################################
9834 11:05:36.052944
9835 11:05:36.342043 00d00000 ################################################################
9836 11:05:36.342169
9837 11:05:36.626004 00d80000 ################################################################
9838 11:05:36.626131
9839 11:05:36.921415 00e00000 ################################################################
9840 11:05:36.921537
9841 11:05:37.208508 00e80000 ################################################################
9842 11:05:37.208661
9843 11:05:37.486031 00f00000 ################################################################
9844 11:05:37.486154
9845 11:05:37.774822 00f80000 ################################################################
9846 11:05:37.774981
9847 11:05:38.075421 01000000 ################################################################
9848 11:05:38.075546
9849 11:05:38.374566 01080000 ################################################################
9850 11:05:38.374694
9851 11:05:38.661912 01100000 ################################################################
9852 11:05:38.662054
9853 11:05:38.962954 01180000 ################################################################
9854 11:05:38.963096
9855 11:05:39.252721 01200000 ################################################################
9856 11:05:39.252856
9857 11:05:39.540986 01280000 ################################################################
9858 11:05:39.541118
9859 11:05:39.830700 01300000 ################################################################
9860 11:05:39.830842
9861 11:05:40.129225 01380000 ################################################################
9862 11:05:40.129366
9863 11:05:40.417250 01400000 ################################################################
9864 11:05:40.417389
9865 11:05:40.716449 01480000 ################################################################
9866 11:05:40.716590
9867 11:05:41.016657 01500000 ################################################################
9868 11:05:41.016840
9869 11:05:41.314668 01580000 ################################################################
9870 11:05:41.314828
9871 11:05:41.610813 01600000 ################################################################
9872 11:05:41.610956
9873 11:05:41.908370 01680000 ################################################################
9874 11:05:41.908514
9875 11:05:42.202752 01700000 ################################################################
9876 11:05:42.202891
9877 11:05:42.505323 01780000 ################################################################
9878 11:05:42.505462
9879 11:05:42.804216 01800000 ################################################################
9880 11:05:42.804390
9881 11:05:43.097584 01880000 ################################################################
9882 11:05:43.097727
9883 11:05:43.400850 01900000 ################################################################
9884 11:05:43.400993
9885 11:05:43.702985 01980000 ################################################################
9886 11:05:43.703125
9887 11:05:43.997857 01a00000 ################################################################
9888 11:05:43.997997
9889 11:05:44.288525 01a80000 ################################################################
9890 11:05:44.288662
9891 11:05:44.590173 01b00000 ################################################################
9892 11:05:44.590319
9893 11:05:44.893047 01b80000 ################################################################
9894 11:05:44.893185
9895 11:05:45.192266 01c00000 ################################################################
9896 11:05:45.192405
9897 11:05:45.490547 01c80000 ################################################################
9898 11:05:45.490681
9899 11:05:45.794467 01d00000 ################################################################
9900 11:05:45.794609
9901 11:05:46.088246 01d80000 ################################################################
9902 11:05:46.088380
9903 11:05:46.374122 01e00000 ################################################################
9904 11:05:46.374262
9905 11:05:46.673319 01e80000 ################################################################
9906 11:05:46.673461
9907 11:05:46.975571 01f00000 ################################################################
9908 11:05:46.975708
9909 11:05:47.271399 01f80000 ################################################################
9910 11:05:47.271563
9911 11:05:47.555497 02000000 ################################################################
9912 11:05:47.555640
9913 11:05:47.842306 02080000 ################################################################
9914 11:05:47.842436
9915 11:05:48.134141 02100000 ################################################################
9916 11:05:48.134302
9917 11:05:48.418805 02180000 ################################################################
9918 11:05:48.418983
9919 11:05:48.712461 02200000 ################################################################
9920 11:05:48.712622
9921 11:05:49.000873 02280000 ################################################################
9922 11:05:49.001031
9923 11:05:49.300649 02300000 ################################################################
9924 11:05:49.300829
9925 11:05:49.597641 02380000 ################################################################
9926 11:05:49.597783
9927 11:05:49.985394 02400000 ################################################################
9928 11:05:49.986126
9929 11:05:50.385699 02480000 ################################################################
9930 11:05:50.386351
9931 11:05:50.719350 02500000 ################################################################
9932 11:05:50.719880
9933 11:05:51.004988 02580000 ################################################################
9934 11:05:51.005126
9935 11:05:51.295876 02600000 ################################################################
9936 11:05:51.296032
9937 11:05:51.591583 02680000 ################################################################
9938 11:05:51.591761
9939 11:05:51.882399 02700000 ################################################################
9940 11:05:51.882554
9941 11:05:52.163283 02780000 ################################################################
9942 11:05:52.163417
9943 11:05:52.452974 02800000 ################################################################
9944 11:05:52.453106
9945 11:05:52.734309 02880000 ################################################################
9946 11:05:52.734473
9947 11:05:53.009335 02900000 ################################################################
9948 11:05:53.009459
9949 11:05:53.306156 02980000 ################################################################
9950 11:05:53.306302
9951 11:05:53.602881 02a00000 ################################################################
9952 11:05:53.603017
9953 11:05:53.898264 02a80000 ################################################################
9954 11:05:53.898403
9955 11:05:54.243888 02b00000 ################################################################
9956 11:05:54.244024
9957 11:05:54.523607 02b80000 ################################################################
9958 11:05:54.523777
9959 11:05:54.814126 02c00000 ################################################################
9960 11:05:54.814295
9961 11:05:55.089600 02c80000 ################################################################
9962 11:05:55.089765
9963 11:05:55.381443 02d00000 ################################################################
9964 11:05:55.381607
9965 11:05:55.650543 02d80000 ################################################################
9966 11:05:55.650706
9967 11:05:55.922697 02e00000 ################################################################
9968 11:05:55.922866
9969 11:05:56.213708 02e80000 ################################################################
9970 11:05:56.213848
9971 11:05:56.493118 02f00000 ################################################################
9972 11:05:56.493245
9973 11:05:56.747284 02f80000 ################################################################
9974 11:05:56.747436
9975 11:05:57.008460 03000000 ################################################################
9976 11:05:57.008617
9977 11:05:57.263577 03080000 ################################################################
9978 11:05:57.263730
9979 11:05:57.520402 03100000 ################################################################
9980 11:05:57.520562
9981 11:05:57.775735 03180000 ################################################################
9982 11:05:57.775900
9983 11:05:58.028924 03200000 ################################################################
9984 11:05:58.029102
9985 11:05:58.301256 03280000 ################################################################
9986 11:05:58.301436
9987 11:05:58.566465 03300000 ################################################################
9988 11:05:58.566633
9989 11:05:58.837660 03380000 ################################################################
9990 11:05:58.837868
9991 11:05:59.101921 03400000 ################################################################
9992 11:05:59.102092
9993 11:05:59.390647 03480000 ################################################################
9994 11:05:59.390806
9995 11:05:59.665121 03500000 ################################################################
9996 11:05:59.665255
9997 11:05:59.960582 03580000 ################################################################
9998 11:05:59.960772
9999 11:06:00.257619 03600000 ################################################################
10000 11:06:00.257795
10001 11:06:00.525297 03680000 ################################################################
10002 11:06:00.525423
10003 11:06:00.779833 03700000 ################################################################
10004 11:06:00.779988
10005 11:06:01.055622 03780000 ################################################################
10006 11:06:01.055763
10007 11:06:01.336453 03800000 ################################################################
10008 11:06:01.336614
10009 11:06:01.635323 03880000 ################################################################
10010 11:06:01.635493
10011 11:06:01.927144 03900000 ################################################################
10012 11:06:01.927277
10013 11:06:02.214186 03980000 ################################################################
10014 11:06:02.214321
10015 11:06:02.512123 03a00000 ################################################################
10016 11:06:02.512272
10017 11:06:02.798128 03a80000 ################################################################
10018 11:06:02.798272
10019 11:06:03.048963 03b00000 ################################################################
10020 11:06:03.049095
10021 11:06:03.303651 03b80000 ################################################################
10022 11:06:03.303790
10023 11:06:03.556674 03c00000 ################################################################
10024 11:06:03.556845
10025 11:06:03.818657 03c80000 ################################################################
10026 11:06:03.818787
10027 11:06:04.079022 03d00000 ################################################################
10028 11:06:04.079149
10029 11:06:04.365666 03d80000 ################################################################
10030 11:06:04.365801
10031 11:06:04.647876 03e00000 ################################################################
10032 11:06:04.648009
10033 11:06:04.919340 03e80000 ################################################################
10034 11:06:04.919470
10035 11:06:05.190515 03f00000 ################################################################
10036 11:06:05.190640
10037 11:06:05.477811 03f80000 ################################################################
10038 11:06:05.477937
10039 11:06:05.737474 04000000 ################################################################
10040 11:06:05.737614
10041 11:06:06.004634 04080000 ################################################################
10042 11:06:06.004827
10043 11:06:06.275956 04100000 ################################################################
10044 11:06:06.276135
10045 11:06:06.548302 04180000 ################################################################
10046 11:06:06.548485
10047 11:06:06.820907 04200000 ################################################################
10048 11:06:06.821056
10049 11:06:07.070315 04280000 ################################################################
10050 11:06:07.070462
10051 11:06:07.345051 04300000 ################################################################
10052 11:06:07.345200
10053 11:06:07.604581 04380000 ################################################################
10054 11:06:07.604731
10055 11:06:07.869191 04400000 ################################################################
10056 11:06:07.869390
10057 11:06:08.137762 04480000 ################################################################
10058 11:06:08.137909
10059 11:06:08.393266 04500000 ################################################################
10060 11:06:08.393413
10061 11:06:08.503524 04580000 ############################# done.
10062 11:06:08.503655
10063 11:06:08.507185 The bootfile was 73108738 bytes long.
10064 11:06:08.507293
10065 11:06:08.510174 Sending tftp read request... done.
10066 11:06:08.510256
10067 11:06:08.514159 Waiting for the transfer...
10068 11:06:08.514241
10069 11:06:08.514304 00000000 # done.
10070 11:06:08.514365
10071 11:06:08.523377 Command line loaded dynamically from TFTP file: 12925608/tftp-deploy-eut2f_1y/kernel/cmdline
10072 11:06:08.523460
10073 11:06:08.536853 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10074 11:06:08.536940
10075 11:06:08.537004 Loading FIT.
10076 11:06:08.537063
10077 11:06:08.540009 Image ramdisk-1 has 61001726 bytes.
10078 11:06:08.540089
10079 11:06:08.543607 Image fdt-1 has 47278 bytes.
10080 11:06:08.543687
10081 11:06:08.546831 Image kernel-1 has 12057697 bytes.
10082 11:06:08.546911
10083 11:06:08.557363 Compat preference: google,spherion-rev12-sku1 google,spherion-rev12 google,spherion-sku1 google,spherion
10084 11:06:08.557445
10085 11:06:08.573883 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion (match) mediatek,mt8192
10086 11:06:08.573969
10087 11:06:08.577399 Choosing best match conf-1 for compat google,spherion.
10088 11:06:08.582566
10089 11:06:08.586565 Connected to device vid:did:rid of 1ae0:0028:00
10090 11:06:08.593820
10091 11:06:08.596958 tpm_get_response: command 0x17b, return code 0x0
10092 11:06:08.597038
10093 11:06:08.600241 ec_init: CrosEC protocol v3 supported (256, 248)
10094 11:06:08.604845
10095 11:06:08.607632 tpm_cleanup: add release locality here.
10096 11:06:08.607713
10097 11:06:08.607777 Shutting down all USB controllers.
10098 11:06:08.611526
10099 11:06:08.611606 Removing current net device
10100 11:06:08.611670
10101 11:06:08.617664 Exiting depthcharge with code 4 at timestamp: 72745023
10102 11:06:08.617745
10103 11:06:08.621371 LZMA decompressing kernel-1 to 0x821a6718
10104 11:06:08.621452
10105 11:06:08.624228 LZMA decompressing kernel-1 to 0x40000000
10106 11:06:10.123701
10107 11:06:10.124259 jumping to kernel
10108 11:06:10.126217 end: 2.2.4 bootloader-commands (duration 00:00:46) [common]
10109 11:06:10.126835 start: 2.2.5 auto-login-action (timeout 00:03:40) [common]
10110 11:06:10.127237 Setting prompt string to ['Linux version [0-9]']
10111 11:06:10.127622 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10112 11:06:10.127997 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10113 11:06:10.174303
10114 11:06:10.177561 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10115 11:06:10.181257 start: 2.2.5.1 login-action (timeout 00:03:40) [common]
10116 11:06:10.181731 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10117 11:06:10.182084 Setting prompt string to []
10118 11:06:10.182465 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10119 11:06:10.182827 Using line separator: #'\n'#
10120 11:06:10.183125 No login prompt set.
10121 11:06:10.183424 Parsing kernel messages
10122 11:06:10.183701 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10123 11:06:10.184189 [login-action] Waiting for messages, (timeout 00:03:40)
10124 11:06:10.184502 Waiting using forced prompt support (timeout 00:01:50)
10125 11:06:10.200192 [ 0.000000] Linux version 6.1.80-cip16 (KernelCI@build-j128891-arm64-gcc-10-defconfig-arm64-chromebook-nrg4h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024
10126 11:06:10.204364 [ 0.000000] random: crng init done
10127 11:06:10.211257 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10128 11:06:10.213750 [ 0.000000] efi: UEFI not found.
10129 11:06:10.220383 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10130 11:06:10.230006 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10131 11:06:10.237167 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10132 11:06:10.246718 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10133 11:06:10.253381 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10134 11:06:10.260009 [ 0.000000] printk: bootconsole [mtk8250] enabled
10135 11:06:10.266321 [ 0.000000] NUMA: No NUMA configuration found
10136 11:06:10.272998 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10137 11:06:10.279465 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10138 11:06:10.279881 [ 0.000000] Zone ranges:
10139 11:06:10.286562 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10140 11:06:10.290529 [ 0.000000] DMA32 empty
10141 11:06:10.295941 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10142 11:06:10.299664 [ 0.000000] Movable zone start for each node
10143 11:06:10.302754 [ 0.000000] Early memory node ranges
10144 11:06:10.309239 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10145 11:06:10.315924 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10146 11:06:10.322470 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10147 11:06:10.328867 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10148 11:06:10.335735 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10149 11:06:10.342416 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10150 11:06:10.372835 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10151 11:06:10.379909 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10152 11:06:10.385888 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10153 11:06:10.389684 [ 0.000000] psci: probing for conduit method from DT.
10154 11:06:10.396397 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10155 11:06:10.400234 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10156 11:06:10.406598 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10157 11:06:10.409471 [ 0.000000] psci: SMC Calling Convention v1.2
10158 11:06:10.415767 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10159 11:06:10.419334 [ 0.000000] Detected VIPT I-cache on CPU0
10160 11:06:10.426408 [ 0.000000] CPU features: detected: GIC system register CPU interface
10161 11:06:10.432787 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10162 11:06:10.438901 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10163 11:06:10.445657 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10164 11:06:10.453135 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10165 11:06:10.462278 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10166 11:06:10.465712 [ 0.000000] alternatives: applying boot alternatives
10167 11:06:10.471845 [ 0.000000] Fallback order for Node 0: 0
10168 11:06:10.478932 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10169 11:06:10.482414 [ 0.000000] Policy zone: Normal
10170 11:06:10.495412 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10171 11:06:10.505565 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10172 11:06:10.516817 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10173 11:06:10.525277 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10174 11:06:10.532004 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10175 11:06:10.535028 <6>[ 0.000000] software IO TLB: area num 8.
10176 11:06:10.591935 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10177 11:06:10.670733 <6>[ 0.000000] Memory: 3793208K/4191232K available (18048K kernel code, 4118K rwdata, 19616K rodata, 8448K init, 616K bss, 365256K reserved, 32768K cma-reserved)
10178 11:06:10.677462 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10179 11:06:10.684224 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10180 11:06:10.687415 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10181 11:06:10.694290 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10182 11:06:10.700428 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10183 11:06:10.704164 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10184 11:06:10.714384 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10185 11:06:10.721652 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10186 11:06:10.727103 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10187 11:06:10.733686 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10188 11:06:10.738469 <6>[ 0.000000] GICv3: 608 SPIs implemented
10189 11:06:10.740484 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10190 11:06:10.747245 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10191 11:06:10.750159 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10192 11:06:10.757169 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10193 11:06:10.770035 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10194 11:06:10.783617 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10195 11:06:10.790224 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10196 11:06:10.797366 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10197 11:06:10.811260 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10198 11:06:10.817429 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10199 11:06:10.824549 <6>[ 0.009173] Console: colour dummy device 80x25
10200 11:06:10.834276 <6>[ 0.013902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10201 11:06:10.840452 <6>[ 0.024355] pid_max: default: 32768 minimum: 301
10202 11:06:10.844740 <6>[ 0.029226] LSM: Security Framework initializing
10203 11:06:10.851435 <6>[ 0.034170] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10204 11:06:10.861664 <6>[ 0.041824] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10205 11:06:10.866817 <6>[ 0.051112] cblist_init_generic: Setting adjustable number of callback queues.
10206 11:06:10.874402 <6>[ 0.058554] cblist_init_generic: Setting shift to 3 and lim to 1.
10207 11:06:10.883227 <6>[ 0.064895] cblist_init_generic: Setting adjustable number of callback queues.
10208 11:06:10.890024 <6>[ 0.072321] cblist_init_generic: Setting shift to 3 and lim to 1.
10209 11:06:10.893345 <6>[ 0.078725] rcu: Hierarchical SRCU implementation.
10210 11:06:10.900067 <6>[ 0.083740] rcu: Max phase no-delay instances is 1000.
10211 11:06:10.906449 <6>[ 0.090766] EFI services will not be available.
10212 11:06:10.909966 <6>[ 0.095724] smp: Bringing up secondary CPUs ...
10213 11:06:10.918173 <6>[ 0.100774] Detected VIPT I-cache on CPU1
10214 11:06:10.924824 <6>[ 0.100841] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10215 11:06:10.931533 <6>[ 0.100873] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10216 11:06:10.934924 <6>[ 0.101205] Detected VIPT I-cache on CPU2
10217 11:06:10.944769 <6>[ 0.101253] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10218 11:06:10.950987 <6>[ 0.101269] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10219 11:06:10.954442 <6>[ 0.101525] Detected VIPT I-cache on CPU3
10220 11:06:10.961435 <6>[ 0.101570] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10221 11:06:10.967523 <6>[ 0.101584] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10222 11:06:10.974210 <6>[ 0.101888] CPU features: detected: Spectre-v4
10223 11:06:10.977722 <6>[ 0.101894] CPU features: detected: Spectre-BHB
10224 11:06:10.981057 <6>[ 0.101900] Detected PIPT I-cache on CPU4
10225 11:06:10.987728 <6>[ 0.101957] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10226 11:06:10.993867 <6>[ 0.101973] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10227 11:06:11.001261 <6>[ 0.102268] Detected PIPT I-cache on CPU5
10228 11:06:11.007330 <6>[ 0.102331] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10229 11:06:11.013959 <6>[ 0.102347] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10230 11:06:11.017098 <6>[ 0.102631] Detected PIPT I-cache on CPU6
10231 11:06:11.023912 <6>[ 0.102693] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10232 11:06:11.030925 <6>[ 0.102710] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10233 11:06:11.037453 <6>[ 0.103011] Detected PIPT I-cache on CPU7
10234 11:06:11.043672 <6>[ 0.103077] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10235 11:06:11.050367 <6>[ 0.103093] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10236 11:06:11.053672 <6>[ 0.103142] smp: Brought up 1 node, 8 CPUs
10237 11:06:11.060465 <6>[ 0.244600] SMP: Total of 8 processors activated.
10238 11:06:11.063616 <6>[ 0.249521] CPU features: detected: 32-bit EL0 Support
10239 11:06:11.073517 <6>[ 0.254884] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10240 11:06:11.080095 <6>[ 0.263684] CPU features: detected: Common not Private translations
10241 11:06:11.086937 <6>[ 0.270160] CPU features: detected: CRC32 instructions
10242 11:06:11.093158 <6>[ 0.275544] CPU features: detected: RCpc load-acquire (LDAPR)
10243 11:06:11.096165 <6>[ 0.281542] CPU features: detected: LSE atomic instructions
10244 11:06:11.103098 <6>[ 0.287323] CPU features: detected: Privileged Access Never
10245 11:06:11.109428 <6>[ 0.293103] CPU features: detected: RAS Extension Support
10246 11:06:11.116084 <6>[ 0.298746] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10247 11:06:11.119655 <6>[ 0.305988] CPU: All CPU(s) started at EL2
10248 11:06:11.126224 <6>[ 0.310332] alternatives: applying system-wide alternatives
10249 11:06:11.135820 <6>[ 0.320339] devtmpfs: initialized
10250 11:06:11.146893 <6>[ 0.328482] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10251 11:06:11.156767 <6>[ 0.338443] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10252 11:06:11.164189 <6>[ 0.346477] pinctrl core: initialized pinctrl subsystem
10253 11:06:11.168054 <6>[ 0.353150] DMI not present or invalid.
10254 11:06:11.173283 <6>[ 0.357554] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10255 11:06:11.183484 <6>[ 0.364404] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10256 11:06:11.189532 <6>[ 0.371852] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10257 11:06:11.197094 <6>[ 0.379946] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10258 11:06:11.204648 <6>[ 0.388103] audit: initializing netlink subsys (disabled)
10259 11:06:11.213526 <5>[ 0.393798] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10260 11:06:11.219561 <6>[ 0.394497] thermal_sys: Registered thermal governor 'step_wise'
10261 11:06:11.226090 <6>[ 0.401763] thermal_sys: Registered thermal governor 'power_allocator'
10262 11:06:11.229820 <6>[ 0.408018] cpuidle: using governor menu
10263 11:06:11.232845 <6>[ 0.418977] NET: Registered PF_QIPCRTR protocol family
10264 11:06:11.242634 <6>[ 0.424456] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10265 11:06:11.246967 <6>[ 0.431559] ASID allocator initialised with 32768 entries
10266 11:06:11.253127 <6>[ 0.438099] Serial: AMBA PL011 UART driver
10267 11:06:11.261615 <4>[ 0.446841] Trying to register duplicate clock ID: 134
10268 11:06:11.316169 <6>[ 0.504332] KASLR enabled
10269 11:06:11.330573 <6>[ 0.512001] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10270 11:06:11.337382 <6>[ 0.519015] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10271 11:06:11.344665 <6>[ 0.525507] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10272 11:06:11.349953 <6>[ 0.532513] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10273 11:06:11.356971 <6>[ 0.539001] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10274 11:06:11.363575 <6>[ 0.546006] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10275 11:06:11.369732 <6>[ 0.552493] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10276 11:06:11.376033 <6>[ 0.559497] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10277 11:06:11.379298 <6>[ 0.566923] ACPI: Interpreter disabled.
10278 11:06:11.388756 <6>[ 0.573322] iommu: Default domain type: Translated
10279 11:06:11.394991 <6>[ 0.578437] iommu: DMA domain TLB invalidation policy: strict mode
10280 11:06:11.398204 <5>[ 0.585099] SCSI subsystem initialized
10281 11:06:11.404840 <6>[ 0.589268] usbcore: registered new interface driver usbfs
10282 11:06:11.411739 <6>[ 0.595000] usbcore: registered new interface driver hub
10283 11:06:11.414421 <6>[ 0.600553] usbcore: registered new device driver usb
10284 11:06:11.421748 <6>[ 0.606643] pps_core: LinuxPPS API ver. 1 registered
10285 11:06:11.431301 <6>[ 0.611836] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10286 11:06:11.434711 <6>[ 0.621183] PTP clock support registered
10287 11:06:11.438321 <6>[ 0.625426] EDAC MC: Ver: 3.0.0
10288 11:06:11.445674 <6>[ 0.630572] FPGA manager framework
10289 11:06:11.451999 <6>[ 0.634252] Advanced Linux Sound Architecture Driver Initialized.
10290 11:06:11.455682 <6>[ 0.641027] vgaarb: loaded
10291 11:06:11.462550 <6>[ 0.644179] clocksource: Switched to clocksource arch_sys_counter
10292 11:06:11.465997 <5>[ 0.650618] VFS: Disk quotas dquot_6.6.0
10293 11:06:11.471934 <6>[ 0.654802] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10294 11:06:11.475586 <6>[ 0.661994] pnp: PnP ACPI: disabled
10295 11:06:11.483330 <6>[ 0.668592] NET: Registered PF_INET protocol family
10296 11:06:11.490102 <6>[ 0.673967] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10297 11:06:11.502340 <6>[ 0.683960] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10298 11:06:11.512074 <6>[ 0.692744] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10299 11:06:11.519188 <6>[ 0.700710] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10300 11:06:11.525907 <6>[ 0.709116] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10301 11:06:11.536686 <6>[ 0.717749] TCP: Hash tables configured (established 32768 bind 32768)
10302 11:06:11.542839 <6>[ 0.724607] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10303 11:06:11.548840 <6>[ 0.731631] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10304 11:06:11.555585 <6>[ 0.739148] NET: Registered PF_UNIX/PF_LOCAL protocol family
10305 11:06:11.562239 <6>[ 0.745292] RPC: Registered named UNIX socket transport module.
10306 11:06:11.565551 <6>[ 0.751443] RPC: Registered udp transport module.
10307 11:06:11.573421 <6>[ 0.756378] RPC: Registered tcp transport module.
10308 11:06:11.579746 <6>[ 0.761310] RPC: Registered tcp NFSv4.1 backchannel transport module.
10309 11:06:11.582250 <6>[ 0.767976] PCI: CLS 0 bytes, default 64
10310 11:06:11.586092 <6>[ 0.772385] Unpacking initramfs...
10311 11:06:11.595394 <6>[ 0.776069] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10312 11:06:11.602115 <6>[ 0.784695] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10313 11:06:11.608688 <6>[ 0.793481] kvm [1]: IPA Size Limit: 40 bits
10314 11:06:11.612383 <6>[ 0.798005] kvm [1]: GICv3: no GICV resource entry
10315 11:06:11.618507 <6>[ 0.803028] kvm [1]: disabling GICv2 emulation
10316 11:06:11.625213 <6>[ 0.807715] kvm [1]: GIC system register CPU interface enabled
10317 11:06:11.628578 <6>[ 0.813872] kvm [1]: vgic interrupt IRQ18
10318 11:06:11.635021 <6>[ 0.818235] kvm [1]: VHE mode initialized successfully
10319 11:06:11.638234 <5>[ 0.824552] Initialise system trusted keyrings
10320 11:06:11.645187 <6>[ 0.829386] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10321 11:06:11.654312 <6>[ 0.839404] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10322 11:06:11.661461 <5>[ 0.845790] NFS: Registering the id_resolver key type
10323 11:06:11.664040 <5>[ 0.851088] Key type id_resolver registered
10324 11:06:11.670675 <5>[ 0.855503] Key type id_legacy registered
10325 11:06:11.677174 <6>[ 0.859783] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10326 11:06:11.684117 <6>[ 0.866705] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10327 11:06:11.690200 <6>[ 0.874449] 9p: Installing v9fs 9p2000 file system support
10328 11:06:11.726289 <5>[ 0.911383] Key type asymmetric registered
10329 11:06:11.729482 <5>[ 0.915712] Asymmetric key parser 'x509' registered
10330 11:06:11.739380 <6>[ 0.920853] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10331 11:06:11.743207 <6>[ 0.928468] io scheduler mq-deadline registered
10332 11:06:11.746186 <6>[ 0.933230] io scheduler kyber registered
10333 11:06:11.765386 <6>[ 0.950470] EINJ: ACPI disabled.
10334 11:06:11.797451 <4>[ 0.975723] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10335 11:06:11.808058 <4>[ 0.986341] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10336 11:06:11.821496 <6>[ 1.006830] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10337 11:06:11.830440 <6>[ 1.014713] printk: console [ttyS0] disabled
10338 11:06:11.857330 <6>[ 1.039339] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10339 11:06:11.864458 <6>[ 1.048810] printk: console [ttyS0] enabled
10340 11:06:11.867731 <6>[ 1.048810] printk: console [ttyS0] enabled
10341 11:06:11.874112 <6>[ 1.057704] printk: bootconsole [mtk8250] disabled
10342 11:06:11.877964 <6>[ 1.057704] printk: bootconsole [mtk8250] disabled
10343 11:06:11.884383 <6>[ 1.068762] SuperH (H)SCI(F) driver initialized
10344 11:06:11.887843 <6>[ 1.074050] msm_serial: driver initialized
10345 11:06:11.902218 <6>[ 1.083035] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10346 11:06:11.911121 <6>[ 1.091582] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10347 11:06:11.918020 <6>[ 1.100125] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10348 11:06:11.928295 <6>[ 1.108755] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10349 11:06:11.937466 <6>[ 1.117464] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10350 11:06:11.944857 <6>[ 1.126184] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10351 11:06:11.954241 <6>[ 1.134723] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10352 11:06:11.961604 <6>[ 1.143535] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10353 11:06:11.971145 <6>[ 1.152076] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10354 11:06:11.983181 <6>[ 1.167660] loop: module loaded
10355 11:06:11.989442 <6>[ 1.173768] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10356 11:06:12.011727 <4>[ 1.196984] mtk-pmic-keys: Failed to locate of_node [id: -1]
10357 11:06:12.019482 <6>[ 1.203650] megasas: 07.719.03.00-rc1
10358 11:06:12.029161 <6>[ 1.213311] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10359 11:06:12.035442 <6>[ 1.219568] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10360 11:06:12.051775 <6>[ 1.236005] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10361 11:06:12.107415 <6>[ 1.285785] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10362 11:06:14.268866 <6>[ 3.453613] Freeing initrd memory: 59568K
10363 11:06:14.280297 <6>[ 3.465358] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10364 11:06:14.291056 <6>[ 3.476562] tun: Universal TUN/TAP device driver, 1.6
10365 11:06:14.295180 <6>[ 3.482626] thunder_xcv, ver 1.0
10366 11:06:14.298847 <6>[ 3.486131] thunder_bgx, ver 1.0
10367 11:06:14.301367 <6>[ 3.489627] nicpf, ver 1.0
10368 11:06:14.311640 <6>[ 3.493676] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10369 11:06:14.314823 <6>[ 3.501153] hns3: Copyright (c) 2017 Huawei Corporation.
10370 11:06:14.321759 <6>[ 3.506740] hclge is initializing
10371 11:06:14.325253 <6>[ 3.510321] e1000: Intel(R) PRO/1000 Network Driver
10372 11:06:14.331712 <6>[ 3.515450] e1000: Copyright (c) 1999-2006 Intel Corporation.
10373 11:06:14.334932 <6>[ 3.521466] e1000e: Intel(R) PRO/1000 Network Driver
10374 11:06:14.341443 <6>[ 3.526681] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10375 11:06:14.349344 <6>[ 3.532865] igb: Intel(R) Gigabit Ethernet Network Driver
10376 11:06:14.355186 <6>[ 3.538514] igb: Copyright (c) 2007-2014 Intel Corporation.
10377 11:06:14.361283 <6>[ 3.544351] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10378 11:06:14.367988 <6>[ 3.550869] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10379 11:06:14.371549 <6>[ 3.557335] sky2: driver version 1.30
10380 11:06:14.377776 <6>[ 3.562334] VFIO - User Level meta-driver version: 0.3
10381 11:06:14.385726 <6>[ 3.570591] usbcore: registered new interface driver usb-storage
10382 11:06:14.391936 <6>[ 3.577036] usbcore: registered new device driver onboard-usb-hub
10383 11:06:14.400789 <6>[ 3.586224] mt6397-rtc mt6359-rtc: registered as rtc0
10384 11:06:14.411538 <6>[ 3.591690] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T11:06:16 UTC (1709463976)
10385 11:06:14.415019 <6>[ 3.601260] i2c_dev: i2c /dev entries driver
10386 11:06:14.430811 <6>[ 3.613062] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10387 11:06:14.452397 <6>[ 3.637031] cpu cpu0: EM: created perf domain
10388 11:06:14.456032 <6>[ 3.641940] cpu cpu4: EM: created perf domain
10389 11:06:14.462678 <6>[ 3.647490] sdhci: Secure Digital Host Controller Interface driver
10390 11:06:14.469129 <6>[ 3.653922] sdhci: Copyright(c) Pierre Ossman
10391 11:06:14.475356 <6>[ 3.658846] Synopsys Designware Multimedia Card Interface Driver
10392 11:06:14.482453 <6>[ 3.665444] sdhci-pltfm: SDHCI platform and OF driver helper
10393 11:06:14.485561 <6>[ 3.665588] mmc0: CQHCI version 5.10
10394 11:06:14.492449 <6>[ 3.675410] ledtrig-cpu: registered to indicate activity on CPUs
10395 11:06:14.498400 <6>[ 3.682330] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10396 11:06:14.505334 <6>[ 3.689351] usbcore: registered new interface driver usbhid
10397 11:06:14.508504 <6>[ 3.695172] usbhid: USB HID core driver
10398 11:06:14.514639 <6>[ 3.699376] spi_master spi0: will run message pump with realtime priority
10399 11:06:14.557032 <6>[ 3.735536] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10400 11:06:14.576918 <6>[ 3.751521] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10401 11:06:14.583325 <6>[ 3.766161] cros-ec-spi spi0.0: Chrome EC device registered
10402 11:06:14.586614 <6>[ 3.772232] mmc0: Command Queue Engine enabled
10403 11:06:14.593192 <6>[ 3.776975] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10404 11:06:14.600387 <6>[ 3.784279] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10405 11:06:14.610159 <6>[ 3.795757] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10406 11:06:14.620515 <6>[ 3.800058] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10407 11:06:14.627069 <6>[ 3.802899] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10408 11:06:14.630153 <6>[ 3.811892] NET: Registered PF_PACKET protocol family
10409 11:06:14.636998 <6>[ 3.816961] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10410 11:06:14.640337 <6>[ 3.821583] 9pnet: Installing 9P2000 support
10411 11:06:14.646545 <6>[ 3.827428] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10412 11:06:14.653179 <5>[ 3.831301] Key type dns_resolver registered
10413 11:06:14.656770 <6>[ 3.842736] registered taskstats version 1
10414 11:06:14.663077 <5>[ 3.847115] Loading compiled-in X.509 certificates
10415 11:06:14.689376 <4>[ 3.867845] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10416 11:06:14.699642 <4>[ 3.878548] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10417 11:06:14.705877 <3>[ 3.889078] debugfs: File 'uA_load' in directory '/' already present!
10418 11:06:14.712769 <3>[ 3.895778] debugfs: File 'min_uV' in directory '/' already present!
10419 11:06:14.719165 <3>[ 3.902448] debugfs: File 'max_uV' in directory '/' already present!
10420 11:06:14.725644 <3>[ 3.909072] debugfs: File 'constraint_flags' in directory '/' already present!
10421 11:06:14.737072 <3>[ 3.918510] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10422 11:06:14.745745 <6>[ 3.930636] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10423 11:06:14.752387 <6>[ 3.937573] xhci-mtk 11200000.usb: xHCI Host Controller
10424 11:06:14.759467 <6>[ 3.943065] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10425 11:06:14.768758 <6>[ 3.950904] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10426 11:06:14.775498 <6>[ 3.960346] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10427 11:06:14.781949 <6>[ 3.966413] xhci-mtk 11200000.usb: xHCI Host Controller
10428 11:06:14.788537 <6>[ 3.971888] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10429 11:06:14.795256 <6>[ 3.979532] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10430 11:06:14.802362 <6>[ 3.987271] hub 1-0:1.0: USB hub found
10431 11:06:14.805465 <6>[ 3.991294] hub 1-0:1.0: 1 port detected
10432 11:06:14.815262 <6>[ 3.995564] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10433 11:06:14.818587 <6>[ 4.004427] hub 2-0:1.0: USB hub found
10434 11:06:14.821999 <6>[ 4.008445] hub 2-0:1.0: 1 port detected
10435 11:06:14.831488 <6>[ 4.016712] mtk-msdc 11f70000.mmc: Got CD GPIO
10436 11:06:14.841313 <6>[ 4.022956] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10437 11:06:14.848350 <6>[ 4.030984] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10438 11:06:14.857759 <4>[ 4.038869] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10439 11:06:14.867619 <6>[ 4.048399] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10440 11:06:14.874075 <6>[ 4.056474] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10441 11:06:14.881073 <6>[ 4.064489] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10442 11:06:14.891366 <6>[ 4.072415] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10443 11:06:14.897855 <6>[ 4.080234] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10444 11:06:14.907784 <6>[ 4.088050] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10445 11:06:14.917249 <6>[ 4.098431] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10446 11:06:14.924812 <6>[ 4.106819] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10447 11:06:14.933951 <6>[ 4.115165] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10448 11:06:14.940069 <6>[ 4.123502] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10449 11:06:14.950681 <6>[ 4.131840] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10450 11:06:14.956766 <6>[ 4.140178] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10451 11:06:14.966647 <6>[ 4.148515] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10452 11:06:14.973313 <6>[ 4.156851] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10453 11:06:14.983577 <6>[ 4.165188] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10454 11:06:14.993170 <6>[ 4.173526] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10455 11:06:14.999626 <6>[ 4.181863] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10456 11:06:15.009700 <6>[ 4.190201] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10457 11:06:15.016424 <6>[ 4.198551] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10458 11:06:15.026424 <6>[ 4.206888] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10459 11:06:15.033291 <6>[ 4.215225] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10460 11:06:15.039889 <6>[ 4.223962] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10461 11:06:15.045954 <6>[ 4.231103] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10462 11:06:15.053008 <6>[ 4.237866] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10463 11:06:15.062955 <6>[ 4.244647] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10464 11:06:15.069323 <6>[ 4.251586] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10465 11:06:15.075875 <6>[ 4.258474] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10466 11:06:15.085326 <6>[ 4.267622] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10467 11:06:15.096108 <6>[ 4.276741] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10468 11:06:15.105626 <6>[ 4.286034] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10469 11:06:15.115558 <6>[ 4.295502] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10470 11:06:15.125271 <6>[ 4.304969] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10471 11:06:15.131885 <6>[ 4.314088] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10472 11:06:15.142183 <6>[ 4.323553] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10473 11:06:15.152315 <6>[ 4.332672] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10474 11:06:15.162359 <6>[ 4.341965] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10475 11:06:15.171541 <6>[ 4.352124] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10476 11:06:15.181616 <6>[ 4.363730] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10477 11:06:15.234610 <6>[ 4.416443] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10478 11:06:15.388812 <6>[ 4.574437] hub 1-1:1.0: USB hub found
10479 11:06:15.392573 <6>[ 4.578965] hub 1-1:1.0: 4 ports detected
10480 11:06:15.402365 <6>[ 4.587548] hub 1-1:1.0: USB hub found
10481 11:06:15.405572 <6>[ 4.591887] hub 1-1:1.0: 4 ports detected
10482 11:06:15.514606 <6>[ 4.696848] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10483 11:06:15.542547 <6>[ 4.727667] hub 2-1:1.0: USB hub found
10484 11:06:15.546195 <6>[ 4.732228] hub 2-1:1.0: 3 ports detected
10485 11:06:15.556044 <6>[ 4.741165] hub 2-1:1.0: USB hub found
10486 11:06:15.559235 <6>[ 4.745695] hub 2-1:1.0: 3 ports detected
10487 11:06:15.726466 <6>[ 4.908492] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10488 11:06:15.858626 <6>[ 5.044061] hub 1-1.4:1.0: USB hub found
10489 11:06:15.861621 <6>[ 5.048656] hub 1-1.4:1.0: 2 ports detected
10490 11:06:15.869928 <6>[ 5.055602] hub 1-1.4:1.0: USB hub found
10491 11:06:15.873988 <6>[ 5.060203] hub 1-1.4:1.0: 2 ports detected
10492 11:06:15.938408 <6>[ 5.120628] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10493 11:06:16.170639 <6>[ 5.352489] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10494 11:06:16.362410 <6>[ 5.544465] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10495 11:06:27.473450 <6>[ 16.661510] ALSA device list:
10496 11:06:27.478002 <6>[ 16.664800] No soundcards found.
10497 11:06:27.485590 <6>[ 16.672694] Freeing unused kernel memory: 8448K
10498 11:06:27.489241 <6>[ 16.678191] Run /init as init process
10499 11:06:27.522631 <6>[ 16.709451] NET: Registered PF_INET6 protocol family
10500 11:06:27.529440 <6>[ 16.715741] Segment Routing with IPv6
10501 11:06:27.532402 <6>[ 16.719697] In-situ OAM (IOAM) with IPv6
10502 11:06:27.591702 <30>[ 16.735023] systemd[1]: systemd 252.19-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10503 11:06:27.592277 <30>[ 16.768241] systemd[1]: Detected architecture arm64.
10504 11:06:27.592647
10505 11:06:27.593090 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10506 11:06:27.593421
10507 11:06:27.601447 <30>[ 16.788527] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10508 11:06:27.723460 <30>[ 16.907301] systemd[1]: Queued start job for default target graphical.target.
10509 11:06:27.766622 <30>[ 16.950265] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10510 11:06:27.772997 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10511 11:06:27.793276 <30>[ 16.977124] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10512 11:06:27.803438 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10513 11:06:27.822125 <30>[ 17.006316] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10514 11:06:27.831989 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10515 11:06:27.850267 <30>[ 17.033758] systemd[1]: Created slice user.slice - User and Session Slice.
10516 11:06:27.856422 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10517 11:06:27.880410 <30>[ 17.061152] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10518 11:06:27.890338 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10519 11:06:27.907802 <30>[ 17.088683] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10520 11:06:27.914691 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10521 11:06:27.943891 <30>[ 17.116587] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10522 11:06:27.952866 <30>[ 17.136509] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10523 11:06:27.959936 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10524 11:06:27.977199 <30>[ 17.160951] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10525 11:06:27.987496 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10526 11:06:28.002431 <30>[ 17.189011] systemd[1]: Reached target paths.target - Path Units.
10527 11:06:28.008383 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10528 11:06:28.028629 <30>[ 17.212915] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10529 11:06:28.035105 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10530 11:06:28.049482 <30>[ 17.236460] systemd[1]: Reached target slices.target - Slice Units.
10531 11:06:28.058901 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10532 11:06:28.074738 <30>[ 17.260965] systemd[1]: Reached target swap.target - Swaps.
10533 11:06:28.080488 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10534 11:06:28.100601 <30>[ 17.284976] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10535 11:06:28.110499 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10536 11:06:28.129233 <30>[ 17.313455] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10537 11:06:28.139285 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10538 11:06:28.159280 <30>[ 17.342721] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10539 11:06:28.168607 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10540 11:06:28.184954 <30>[ 17.369178] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10541 11:06:28.195513 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10542 11:06:28.213307 <30>[ 17.397221] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10543 11:06:28.219556 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10544 11:06:28.237586 <30>[ 17.421111] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10545 11:06:28.247128 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10546 11:06:28.265450 <30>[ 17.448948] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10547 11:06:28.274393 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10548 11:06:28.328934 <30>[ 17.512726] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10549 11:06:28.335416 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10550 11:06:28.356859 <30>[ 17.540587] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10551 11:06:28.364014 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10552 11:06:28.384478 <30>[ 17.568626] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10553 11:06:28.391369 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10554 11:06:28.415664 <30>[ 17.592767] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10555 11:06:28.460937 <30>[ 17.644986] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10556 11:06:28.472936 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10557 11:06:28.493423 <30>[ 17.677289] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10558 11:06:28.502504 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10559 11:06:28.561310 <30>[ 17.744947] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10560 11:06:28.575734 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 17.757735] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10561 11:06:28.578033 Module dm_mod...
10562 11:06:28.602766 <30>[ 17.785652] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10563 11:06:28.608808 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10564 11:06:28.668674 <30>[ 17.853012] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10565 11:06:28.675716 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10566 11:06:28.701798 <30>[ 17.885511] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10567 11:06:28.708577 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10568 11:06:28.754369 <30>[ 17.936818] systemd[1]: Starting systemd-journald.service - Journal Service...
10569 11:06:28.759386 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10570 11:06:28.780149 <30>[ 17.963433] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10571 11:06:28.787694 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10572 11:06:28.811682 <30>[ 17.991383] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10573 11:06:28.817976 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10574 11:06:28.839618 <30>[ 18.023049] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10575 11:06:28.849909 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10576 11:06:28.868668 <30>[ 18.052413] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10577 11:06:28.875683 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10578 11:06:28.904599 <30>[ 18.087621] systemd[1]: Started systemd-journald.service - Journal Service.
10579 11:06:28.911194 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10580 11:06:28.931809 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10581 11:06:28.950434 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10582 11:06:28.970670 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10583 11:06:28.990302 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10584 11:06:29.014995 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10585 11:06:29.036243 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10586 11:06:29.063765 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10587 11:06:29.088785 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10588 11:06:29.109173 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10589 11:06:29.126880 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10590 11:06:29.146980 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10591 11:06:29.171375 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10592 11:06:29.190060 See 'systemctl status systemd-remount-fs.service' for details.
10593 11:06:29.210509 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10594 11:06:29.235816 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10595 11:06:29.290174 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10596 11:06:29.307190 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10597 11:06:29.322163 <46>[ 18.505636] systemd-journald[181]: Received client request to flush runtime journal.
10598 11:06:29.334004 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10599 11:06:29.353643 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10600 11:06:29.373257 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10601 11:06:29.395374 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10602 11:06:29.414364 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10603 11:06:29.433961 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10604 11:06:29.454346 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10605 11:06:29.474043 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10606 11:06:29.521634 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10607 11:06:29.548351 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10608 11:06:29.569507 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10609 11:06:29.585491 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10610 11:06:29.641311 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10611 11:06:29.666428 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10612 11:06:29.693075 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10613 11:06:29.712622 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10614 11:06:29.760068 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10615 11:06:29.922356 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10616 11:06:29.949983 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10617 11:06:29.985591 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10618 11:06:30.015300 [[0;32m OK [0m] Reached targ<3>[ 19.197096] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10619 11:06:30.022448 et [0;1;39mtime<6>[ 19.197109] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10620 11:06:30.035877 -set.target[0m <6>[ 19.197156] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10621 11:06:30.041647 - System Time Se<3>[ 19.208037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10622 11:06:30.051954 <6>[ 19.216953] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10623 11:06:30.052536 t.
10624 11:06:30.061709 <3>[ 19.226770] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10625 11:06:30.071551 <3>[ 19.254925] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10626 11:06:30.078001 <3>[ 19.263418] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10627 11:06:30.088536 <3>[ 19.271749] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10628 11:06:30.094936 <3>[ 19.279844] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10629 11:06:30.104948 <3>[ 19.279849] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10630 11:06:30.117988 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord S<3>[ 19.300897] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10631 11:06:30.125391 ystem Boot/Shutd<6>[ 19.311054] mc: Linux media interface: v0.10
10632 11:06:30.130975 <3>[ 19.312817] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10633 11:06:30.134167 own in UTMP.
10634 11:06:30.141243 <4>[ 19.318377] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10635 11:06:30.147751 <3>[ 19.324237] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10636 11:06:30.157609 <3>[ 19.324243] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10637 11:06:30.164319 <6>[ 19.326195] usbcore: registered new device driver r8152-cfgselector
10638 11:06:30.170412 <3>[ 19.336954] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10639 11:06:30.180806 <4>[ 19.336965] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10640 11:06:30.187341 <6>[ 19.351239] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10641 11:06:30.193831 <3>[ 19.355631] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10642 11:06:30.200794 <6>[ 19.357521] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10643 11:06:30.207700 <6>[ 19.357528] pci_bus 0000:00: root bus resource [bus 00-ff]
10644 11:06:30.214535 <6>[ 19.357534] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10645 11:06:30.224209 <6>[ 19.357539] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10646 11:06:30.231353 <6>[ 19.357570] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10647 11:06:30.237353 <6>[ 19.357590] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10648 11:06:30.244372 <6>[ 19.357668] pci 0000:00:00.0: supports D1 D2
10649 11:06:30.250860 <6>[ 19.357672] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10650 11:06:30.257582 <6>[ 19.359242] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10651 11:06:30.264883 <6>[ 19.359357] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10652 11:06:30.270443 <6>[ 19.359388] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10653 11:06:30.280484 <6>[ 19.359408] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10654 11:06:30.287042 <6>[ 19.359427] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10655 11:06:30.290152 <6>[ 19.359538] pci 0000:01:00.0: supports D1 D2
10656 11:06:30.297287 <6>[ 19.359541] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10657 11:06:30.303466 <6>[ 19.372406] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10658 11:06:30.314414 <3>[ 19.378653] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10659 11:06:30.320898 <3>[ 19.378663] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10660 11:06:30.330163 <3>[ 19.378668] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10661 11:06:30.336764 <4>[ 19.380849] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10662 11:06:30.343556 <4>[ 19.380849] Fallback method does not support PEC.
10663 11:06:30.350060 <6>[ 19.386779] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10664 11:06:30.359882 <3>[ 19.393653] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10665 11:06:30.366687 <3>[ 19.396426] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10666 11:06:30.376201 <6>[ 19.399352] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10667 11:06:30.386051 <6>[ 19.417462] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10668 11:06:30.392756 <6>[ 19.423284] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10669 11:06:30.403182 <6>[ 19.430716] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10670 11:06:30.409809 <6>[ 19.435112] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10671 11:06:30.420342 <6>[ 19.448762] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10672 11:06:30.427539 <6>[ 19.449833] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10673 11:06:30.436889 <6>[ 19.455129] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10674 11:06:30.447103 <4>[ 19.481189] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10675 11:06:30.449558 <6>[ 19.483040] pci 0000:00:00.0: PCI bridge to [bus 01]
10676 11:06:30.453050 <6>[ 19.484228] Bluetooth: Core ver 2.22
10677 11:06:30.459987 <6>[ 19.484304] videodev: Linux video capture interface: v2.00
10678 11:06:30.466912 <6>[ 19.484416] NET: Registered PF_BLUETOOTH protocol family
10679 11:06:30.473369 <6>[ 19.484421] Bluetooth: HCI device and connection manager initialized
10680 11:06:30.476990 <6>[ 19.484454] Bluetooth: HCI socket layer initialized
10681 11:06:30.484019 <6>[ 19.484461] Bluetooth: L2CAP socket layer initialized
10682 11:06:30.487512 <6>[ 19.484472] Bluetooth: SCO socket layer initialized
10683 11:06:30.493790 <6>[ 19.485016] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10684 11:06:30.500802 <6>[ 19.487596] remoteproc remoteproc0: scp is available
10685 11:06:30.507391 <6>[ 19.487636] remoteproc remoteproc0: powering up scp
10686 11:06:30.514214 <6>[ 19.487640] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10687 11:06:30.520466 <6>[ 19.487652] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10688 11:06:30.527659 <4>[ 19.489897] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10689 11:06:30.537300 <6>[ 19.496786] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10690 11:06:30.540541 <6>[ 19.496949] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10691 11:06:30.547128 <6>[ 19.569118] usbcore: registered new interface driver btusb
10692 11:06:30.554809 <6>[ 19.569287] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10693 11:06:30.565045 <4>[ 19.570100] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10694 11:06:30.571488 <3>[ 19.570115] Bluetooth: hci0: Failed to load firmware file (-2)
10695 11:06:30.578531 <3>[ 19.570122] Bluetooth: hci0: Failed to set up firmware (-2)
10696 11:06:30.588318 <4>[ 19.570129] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10697 11:06:30.602401 <6>[ 19.571194] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10698 11:06:30.608846 <6>[ 19.571380] usbcore: registered new interface driver uvcvideo
10699 11:06:30.611800 <6>[ 19.576436] r8152 2-1.3:1.0 eth0: v1.12.13
10700 11:06:30.618477 <6>[ 19.576474] usbcore: registered new interface driver r8152
10701 11:06:30.621647 <6>[ 19.580300] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10702 11:06:30.628679 <6>[ 19.586067] usbcore: registered new interface driver cdc_ether
10703 11:06:30.635383 <6>[ 19.595238] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10704 11:06:30.642558 <6>[ 19.595674] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10705 11:06:30.652804 <3>[ 19.608348] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10706 11:06:30.658735 <3>[ 19.611711] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10707 11:06:30.664783 <6>[ 19.613226] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10708 11:06:30.674740 <6>[ 19.613276] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10709 11:06:30.677968 <6>[ 19.613284] remoteproc remoteproc0: remote processor scp is now up
10710 11:06:30.685215 <6>[ 19.619362] usbcore: registered new interface driver r8153_ecm
10711 11:06:30.695014 <6>[ 19.620567] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10712 11:06:30.701602 <6>[ 19.623146] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10713 11:06:30.711552 <5>[ 19.641464] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10714 11:06:30.715675 <6>[ 19.663705] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10715 11:06:30.722360 <5>[ 19.713666] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10716 11:06:30.732096 <3>[ 19.721316] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10717 11:06:30.739107 <5>[ 19.728416] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10718 11:06:30.749139 <3>[ 19.735049] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10719 11:06:30.759740 <3>[ 19.748947] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10720 11:06:30.766098 <4>[ 19.796840] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10721 11:06:30.776202 <3>[ 19.817411] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10722 11:06:30.779373 <6>[ 19.821049] cfg80211: failed to load regulatory.db
10723 11:06:30.789614 <6>[ 19.853827] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10724 11:06:30.796078 <3>[ 19.880002] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10725 11:06:30.803514 <6>[ 19.886386] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10726 11:06:30.814386 <3>[ 19.913108] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10727 11:06:30.819189 <6>[ 19.932352] mt7921e 0000:01:00.0: ASIC revision: 79610010
10728 11:06:30.825686 <3>[ 19.951961] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10729 11:06:30.836489 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10730 11:06:30.868895 <6>[ 20.052368] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10731 11:06:30.869606 <6>[ 20.052368]
10732 11:06:30.881969 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10733 11:06:30.906171 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10734 11:06:30.965811 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10735 11:06:30.989471 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10736 11:06:31.009562 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10737 11:06:31.028929 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10738 11:06:31.045461 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10739 11:06:31.062572 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10740 11:06:31.081261 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10741 11:06:31.096628 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10742 11:06:31.113527 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10743 11:06:31.139102 <6>[ 20.321950] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10744 11:06:31.182992 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10745 11:06:31.215836 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10746 11:06:31.238909 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10747 11:06:31.259591 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10748 11:06:31.286834 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10749 11:06:31.350826 [[0;32m OK [<46>[ 20.521589] systemd-journald[181]: Data hash table of /var/log/journal/7511cdbeca2141059c257953b873947e/system.journal has a fill level at 75.7 (1549 of 2047 items, 524288 file size, 338 bytes per hash table item), suggesting rotation.
10750 11:06:31.369003 0m] Started [0;<46>[ 20.544210] systemd-journald[181]: /var/log/journal/7511cdbeca2141059c257953b873947e/system.journal: Journal header limits reached or header out-of-date, rotating.
10751 11:06:31.373396 1;39mgetty@tty1.service[0m - Getty on tty1.
10752 11:06:31.414442 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10753 11:06:31.433315 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10754 11:06:31.472768 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10755 11:06:31.490943 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10756 11:06:31.508849 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10757 11:06:31.526698 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10758 11:06:31.545974 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10759 11:06:31.590692 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10760 11:06:31.622821 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10761 11:06:31.669695
10762 11:06:31.670300
10763 11:06:31.672889 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10764 11:06:31.673359
10765 11:06:31.676172 debian-bookworm-arm64 login: root (automatic login)
10766 11:06:31.676879
10767 11:06:31.677260
10768 11:06:31.688561 Linux debian-bookworm-arm64 6.1.80-cip16 #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024 aarch64
10769 11:06:31.689166
10770 11:06:31.695504 The programs included with the Debian GNU/Linux system are free software;
10771 11:06:31.701435 the exact distribution terms for each program are described in the
10772 11:06:31.704936 individual files in /usr/share/doc/*/copyright.
10773 11:06:31.705388
10774 11:06:31.711422 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10775 11:06:31.715246 permitted by applicable law.
10776 11:06:31.716848 Matched prompt #10: / #
10778 11:06:31.717927 Setting prompt string to ['/ #']
10779 11:06:31.718390 end: 2.2.5.1 login-action (duration 00:00:22) [common]
10781 11:06:31.719448 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
10782 11:06:31.719919 start: 2.2.6 expect-shell-connection (timeout 00:03:19) [common]
10783 11:06:31.720313 Setting prompt string to ['/ #']
10784 11:06:31.720644 Forcing a shell prompt, looking for ['/ #']
10786 11:06:31.771595 / #
10787 11:06:31.772256 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10788 11:06:31.772743 Waiting using forced prompt support (timeout 00:02:30)
10789 11:06:31.778548
10790 11:06:31.779487 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10791 11:06:31.780007 start: 2.2.7 export-device-env (timeout 00:03:19) [common]
10792 11:06:31.780503 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10793 11:06:31.781066 end: 2.2 depthcharge-retry (duration 00:01:41) [common]
10794 11:06:31.781545 end: 2 depthcharge-action (duration 00:01:41) [common]
10795 11:06:31.782039 start: 3 lava-test-retry (timeout 00:07:54) [common]
10796 11:06:31.782508 start: 3.1 lava-test-shell (timeout 00:07:54) [common]
10797 11:06:31.782900 Using namespace: common
10799 11:06:31.884053 / # #
10800 11:06:31.884694 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10801 11:06:31.890654 #
10802 11:06:31.891533 Using /lava-12925608
10804 11:06:31.992837 / # export SHELL=/bin/sh
10805 11:06:32.001430 export SHELL=/bin/sh<6>[ 21.188515] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10806 11:06:32.001982
10808 11:06:32.106954 / # . /lava-12925608/environment
10809 11:06:32.114171 . /lava-12925608/environment
10811 11:06:32.215964 / # /lava-12925608/bin/lava-test-runner /lava-12925608/0
10812 11:06:32.216659 Test shell timeout: 10s (minimum of the action and connection timeout)
10813 11:06:32.223793 /lava-12925608/bin/lava-test-runner /lava-12925608/0
10814 11:06:32.249672 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 21.435611] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 12925608_1.5.2.3.1>
10815 11:06:32.250543 Received signal: <STARTRUN> 0_igt-gpu-panfrost 12925608_1.5.2.3.1
10816 11:06:32.250967 Starting test lava.0_igt-gpu-panfrost (12925608_1.5.2.3.1)
10817 11:06:32.251402 Skipping test definition patterns.
10818 11:06:32.252574 nfrost
10819 11:06:32.255978 + cd /lava-12925608/0/tests/0_igt-gpu-panfrost
10820 11:06:32.256439 + cat uuid
10821 11:06:32.260081 + UUID=12925608_1.5.2.3.1
10822 11:06:32.260640 + set +x
10823 11:06:32.277191 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime p<8>[ 21.459813] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
10824 11:06:32.277820 anfrost_submit
10825 11:06:32.278591 Received signal: <TESTSET> START panfrost_gem_new
10826 11:06:32.279017 Starting test_set panfrost_gem_new
10827 11:06:32.295009 <14>[ 21.481949] [IGT] panfrost_gem_new: executing
10828 11:06:32.301441 IGT-Version: 1.28-g0830aa7 (aarc<14>[ 21.488844] [IGT] panfrost_gem_new: exiting, ret=77
10829 11:06:32.304782 h64) (Linux: 6.1.80-cip16 aarch64)
10830 11:06:32.317682 Using IGT_SRANDOM=1709463994 for randomisati<8>[ 21.500554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
10831 11:06:32.318239 on
10832 11:06:32.318929 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
10834 11:06:32.324626 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10835 11:06:32.327717 Test requirement: !(fd<0)
10836 11:06:32.335220 No known gpu found for chipset flags 0x32 (panf<14>[ 21.521968] [IGT] panfrost_gem_new: executing
10837 11:06:32.335788 rost)
10838 11:06:32.343980 Last errno: 2, No such fi<14>[ 21.529559] [IGT] panfrost_gem_new: exiting, ret=77
10839 11:06:32.344443 le or directory
10840 11:06:32.347726 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
10841 11:06:32.357340 IGT-Version: 1.28-<8>[ 21.541196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
10842 11:06:32.358179 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
10844 11:06:32.361433 g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
10845 11:06:32.364219 Using IGT_SRANDOM=1709463994 for randomisation
10846 11:06:32.376457 Test requirement not met in function drm_open_<14>[ 21.561767] [IGT] panfrost_gem_new: executing
10847 11:06:32.381425 driver, file ../lib/drmtest.c:69<14>[ 21.568255] [IGT] panfrost_gem_new: exiting, ret=77
10848 11:06:32.384525 4:
10849 11:06:32.385180 Test requirement: !(fd<0)
10850 11:06:32.397380 No known gpu found for chipset flags 0x32 (panfro<8>[ 21.580288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
10851 11:06:32.397943 st)
10852 11:06:32.398587 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
10854 11:06:32.403817 Last errno: 2, No such file<8>[ 21.590150] <LAVA_SIGNAL_TESTSET STOP>
10855 11:06:32.404375 or directory
10856 11:06:32.405061 Received signal: <TESTSET> STOP
10857 11:06:32.405451 Closing test_set panfrost_gem_new
10858 11:06:32.407684 [1mSubtest gem-new-0: SKIP (0.000s)[0m
10859 11:06:32.413867 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
10860 11:06:32.417245 Using IGT_SRANDOM=1709463994 for randomisation
10861 11:06:32.424044 Tes<8>[ 21.610236] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
10862 11:06:32.424861 Received signal: <TESTSET> START panfrost_get_param
10863 11:06:32.425258 Starting test_set panfrost_get_param
10864 11:06:32.430243 t requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10865 11:06:32.433094 Test requirement: !(fd<0)
10866 11:06:32.443358 No known gpu found for chipset flags 0<14>[ 21.627947] [IGT] panfrost_get_param: executing
10867 11:06:32.444102 x32 (panfrost)
10868 11:06:32.450710 Last errno: 2, N<14>[ 21.635985] [IGT] panfrost_get_param: exiting, ret=77
10869 11:06:32.452948 o such file or directory
10870 11:06:32.463111 [1mSubtest gem-new-zeroed: SKIP (0.00<8>[ 21.647881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
10871 11:06:32.463730 0s)[0m
10872 11:06:32.464388 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
10874 11:06:32.469939 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
10875 11:06:32.473221 Using IGT_SRANDOM=1709463994 for randomisation
10876 11:06:32.483861 Test requirement not met in functio<14>[ 21.667854] [IGT] panfrost_get_param: executing
10877 11:06:32.490317 n drm_open_driver, file ../lib/d<14>[ 21.675597] [IGT] panfrost_get_param: exiting, ret=77
10878 11:06:32.490781 rmtest.c:694:
10879 11:06:32.492971 Test requirement: !(fd<0)
10880 11:06:32.502778 No known gpu found for chipset flags 0<8>[ 21.687718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
10881 11:06:32.503620 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
10883 11:06:32.506128 x32 (panfrost)
10884 11:06:32.509433 Last errno: 2, No such file or directory
10885 11:06:32.512762 [1mSubtest base-params: SKIP (0.000s)[0m
10886 11:06:32.522609 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 <14>[ 21.709130] [IGT] panfrost_get_param: executing
10887 11:06:32.523178 aarch64)
10888 11:06:32.528811 Using IGT_SRANDOM=1709<14>[ 21.716494] [IGT] panfrost_get_param: exiting, ret=77
10889 11:06:32.532587 463994 for randomisation
10890 11:06:32.546400 Test requirement not met in function drm_open_driver, file ../lib/drmt<8>[ 21.730205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
10891 11:06:32.547244 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
10893 11:06:32.548918 est.c:694:
10894 11:06:32.552606 Test requirement: !(<8>[ 21.740642] <LAVA_SIGNAL_TESTSET STOP>
10895 11:06:32.553201 fd<0)
10896 11:06:32.553841 Received signal: <TESTSET> STOP
10897 11:06:32.554204 Closing test_set panfrost_get_param
10898 11:06:32.559427 No known gpu found for chipset flags 0x32 (panfrost)
10899 11:06:32.561998 Last errno: 2, No such file or directory
10900 11:06:32.565045 [1mSubtest get-bad-param: SKIP (0.000s)[0m
10901 11:06:32.574829 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux<8>[ 21.760764] <LAVA_SIGNAL_TESTSET START panfrost_prime>
10902 11:06:32.575676 Received signal: <TESTSET> START panfrost_prime
10903 11:06:32.576085 Starting test_set panfrost_prime
10904 11:06:32.578705 : 6.1.80-cip16 aarch64)
10905 11:06:32.581543 Using IGT_SRANDOM=1709463994 for randomisation
10906 11:06:32.592998 Test requirement not met in function drm_open_driver, file ../lib/drmte<14>[ 21.779363] [IGT] panfrost_prime: executing
10907 11:06:32.593561 st.c:694:
10908 11:06:32.602233 Test requirement: !(f<14>[ 21.786283] [IGT] panfrost_prime: exiting, ret=77
10909 11:06:32.602796 d<0)
10910 11:06:32.604945 No known gpu found for chipset flags 0x32 (panfrost)
10911 11:06:32.611475 Last<8>[ 21.796880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
10912 11:06:32.612309 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
10914 11:06:32.618675 Received signal: <TESTSET> STOP
10915 11:06:32.619204 Closing test_set panfrost_prime
10916 11:06:32.621553 errno: 2, No such file or direc<8>[ 21.806876] <LAVA_SIGNAL_TESTSET STOP>
10917 11:06:32.622106 tory
10918 11:06:32.625391 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
10919 11:06:32.631213 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
10920 11:06:32.638628 Using IGT_SRANDOM=1709463994 for rando<8>[ 21.825903] <LAVA_SIGNAL_TESTSET START panfrost_submit>
10921 11:06:32.639458 Received signal: <TESTSET> START panfrost_submit
10922 11:06:32.639845 Starting test_set panfrost_submit
10923 11:06:32.641239 misation
10924 11:06:32.647544 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10925 11:06:32.650673 Test requirement: !(fd<0)
10926 11:06:32.657613 No known gpu found for chipset flags 0x32<14>[ 21.844790] [IGT] panfrost_submit: executing
10927 11:06:32.658080 (panfrost)
10928 11:06:32.664171 Last errno: 2, No s<14>[ 21.852295] [IGT] panfrost_submit: exiting, ret=77
10929 11:06:32.668234 uch file or directory
10930 11:06:32.677456 [1mSubtest gem-prime-import: SKIP (0.000<8>[ 21.862465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
10931 11:06:32.678001 s)[0m
10932 11:06:32.678646 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
10934 11:06:32.684157 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
10935 11:06:32.691613 Using IGT_SRANDOM=1709463994 for randomisation
10936 11:06:32.698759 Test requirement not<14>[ 21.882516] [IGT] panfrost_submit: executing
10937 11:06:32.706035 met in function drm_open_driver<14>[ 21.890002] [IGT] panfrost_submit: exiting, ret=77
10938 11:06:32.707761 , file ../lib/drmtest.c:694:
10939 11:06:32.708218 Test requirement: !(fd<0)
10940 11:06:32.718249 No know<8>[ 21.901449] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
10941 11:06:32.719090 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
10943 11:06:32.720402 n gpu found for chipset flags 0x32 (panfrost)
10944 11:06:32.723791 Last errno: 2, No such file or directory
10945 11:06:32.727562 [1mSubtest pan-submit: SKIP (0.000s)[0m
10946 11:06:32.737134 IGT-Version: 1.28-g0830aa7 (<14>[ 21.921956] [IGT] panfrost_submit: executing
10947 11:06:32.743605 aarch64) (Linux: 6.1.80-cip16 aa<14>[ 21.929899] [IGT] panfrost_submit: exiting, ret=77
10948 11:06:32.744167 rch64)
10949 11:06:32.749971 Using IGT_SRANDOM=1709463994 for randomisation
10950 11:06:32.756596 Test req<8>[ 21.941297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
10951 11:06:32.757446 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
10953 11:06:32.763881 uirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
10954 11:06:32.767300 Test requirement: !(fd<0)
10955 11:06:32.773717 No known gpu found for chipset flags 0x32 (<14>[ 21.962506] [IGT] panfrost_submit: executing
10956 11:06:32.776358 panfrost)
10957 11:06:32.782963 Last errno: 2, No suc<14>[ 21.969289] [IGT] panfrost_submit: exiting, ret=77
10958 11:06:32.783425 h file or directory
10959 11:06:32.796794 [1mSubtest pan-submit-error-no-jc: SKIP (0<8>[ 21.980468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
10960 11:06:32.797374 .000s)[0m
10961 11:06:32.798025 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
10963 11:06:32.803583 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
10964 11:06:32.809677 Using IGT_SRANDOM=1709463994 for randomisation
10965 11:06:32.817026 Test requirement not met in func<14>[ 22.002060] [IGT] panfrost_submit: executing
10966 11:06:32.823075 tion drm_open_driver, file ../li<14>[ 22.010018] [IGT] panfrost_submit: exiting, ret=77
10967 11:06:32.826347 b/drmtest.c:694:
10968 11:06:32.826904 Test requirement: !(fd<0)
10969 11:06:32.839800 No known gpu found for chipset flag<8>[ 22.022536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
10970 11:06:32.840367 s 0x32 (panfrost)
10971 11:06:32.841051 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
10973 11:06:32.846839 Last errno: 2, No such file or directory
10974 11:06:32.848857 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
10975 11:06:32.859253 IGT-Version: 1.28-g0830aa7 (aarch64) <14>[ 22.044711] [IGT] panfrost_submit: executing
10976 11:06:32.859805 (Linux: 6.1.80-cip16 aarch64)
10977 11:06:32.865911 U<14>[ 22.051856] [IGT] panfrost_submit: exiting, ret=77
10978 11:06:32.868768 sing IGT_SRANDOM=1709463994 for randomisation
10979 11:06:32.879056 Test requirement <8>[ 22.063575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
10980 11:06:32.879980 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
10982 11:06:32.885198 not met in function drm_open_driver, file ../lib/drmtest.c:694:
10983 11:06:32.888825 Test requirement: !(fd<0)
10984 11:06:32.892593 No known gpu found for chipset flags 0x32 (panfrost)
10985 11:06:32.898447 Last errno: 2,<14>[ 22.084998] [IGT] panfrost_submit: executing
10986 11:06:32.901785 No such file or directory
10987 11:06:32.905866 [1m<14>[ 22.092743] [IGT] panfrost_submit: exiting, ret=77
10988 11:06:32.911906 Subtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
10989 11:06:32.918856 IGT-<8>[ 22.104202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
10990 11:06:32.919683 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
10992 11:06:32.925895 Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
10993 11:06:32.928795 Using IGT_SRANDOM=1709463994 for randomisation
10994 11:06:32.938093 Test requirement not met in function drm_open_dr<14>[ 22.123823] [IGT] panfrost_submit: executing
10995 11:06:32.945106 iver, file ../lib/drmtest.c:694:<14>[ 22.131371] [IGT] panfrost_submit: exiting, ret=77
10996 11:06:32.945663
10997 11:06:32.948192 Test requirement: !(fd<0)
10998 11:06:32.957993 No known gpu found for chipset flag<8>[ 22.142994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
10999 11:06:32.958732 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11001 11:06:32.960961 s 0x32 (panfrost)
11002 11:06:32.964336 Last errno: 2, No such file or directory
11003 11:06:32.968066 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11004 11:06:32.977726 IGT-Version: 1.28-g0830aa7 (aarch<14>[ 22.163584] [IGT] panfrost_submit: executing
11005 11:06:32.984753 64) (Linux: 6.1.80-cip16 aarch64<14>[ 22.171203] [IGT] panfrost_submit: exiting, ret=77
11006 11:06:32.985320 )
11007 11:06:32.988098 Using IGT_SRANDOM=1709463994 for randomisation
11008 11:06:32.997883 Test requirem<8>[ 22.182887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11009 11:06:32.998731 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11011 11:06:33.005187 ent not met in f<8>[ 22.192272] <LAVA_SIGNAL_TESTSET STOP>
11012 11:06:33.006020 Received signal: <TESTSET> STOP
11013 11:06:33.006406 Closing test_set panfrost_submit
11014 11:06:33.010763 unction drm_open<8>[ 22.197317] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 12925608_1.5.2.3.1>
11015 11:06:33.011481 Received signal: <ENDRUN> 0_igt-gpu-panfrost 12925608_1.5.2.3.1
11016 11:06:33.011933 Ending use of test pattern.
11017 11:06:33.012286 Ending test lava.0_igt-gpu-panfrost (12925608_1.5.2.3.1), duration 0.76
11019 11:06:33.014185 _driver, file ../lib/drmtest.c:694:
11020 11:06:33.018064 Test requirement: !(fd<0)
11021 11:06:33.020735 No known gpu found for chipset flags 0x32 (panfrost)
11022 11:06:33.028320 Last errno: 2, No such file or directory
11023 11:06:33.031332 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11024 11:06:33.038688 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11025 11:06:33.040666 Using IGT_SRANDOM=1709463994 for randomisation
11026 11:06:33.047156 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11027 11:06:33.051371 Test requirement: !(fd<0)
11028 11:06:33.058392 No known gpu found for chipset flags 0x32 (panfrost)
11029 11:06:33.060674 Last errno: 2, No such file or directory
11030 11:06:33.063995 [1mSubtest pan-reset: SKIP (0.000s)[0m
11031 11:06:33.070236 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11032 11:06:33.073961 Using IGT_SRANDOM=1709463995 for randomisation
11033 11:06:33.080491 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11034 11:06:33.084289 Test requirement: !(fd<0)
11035 11:06:33.086790 No known gpu found for chipset flags 0x32 (panfrost)
11036 11:06:33.091341 Last errno: 2, No such file or directory
11037 11:06:33.097051 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11038 11:06:33.100898 IGT-Version: 1.28-g0830aa7 (aarch64) (Linux: 6.1.80-cip16 aarch64)
11039 11:06:33.106483 Using IGT_SRANDOM=1709463995 for randomisation
11040 11:06:33.113429 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11041 11:06:33.114014 Test requirement: !(fd<0)
11042 11:06:33.119814 No known gpu found for chipset flags 0x32 (panfrost)
11043 11:06:33.123747 Last errno: 2, No such file or directory
11044 11:06:33.127101 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11045 11:06:33.130376 + set +x
11046 11:06:33.130842 <LAVA_TEST_RUNNER EXIT>
11047 11:06:33.131517 ok: lava_test_shell seems to have completed
11048 11:06:33.133266 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11049 11:06:33.133815 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11050 11:06:33.134279 end: 3 lava-test-retry (duration 00:00:01) [common]
11051 11:06:33.134768 start: 4 finalize (timeout 00:07:53) [common]
11052 11:06:33.135267 start: 4.1 power-off (timeout 00:00:30) [common]
11053 11:06:33.136074 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11054 11:06:33.261717 >> Command sent successfully.
11055 11:06:33.266044 Returned 0 in 0 seconds
11056 11:06:33.367029 end: 4.1 power-off (duration 00:00:00) [common]
11058 11:06:33.368561 start: 4.2 read-feedback (timeout 00:07:53) [common]
11059 11:06:33.369919 Listened to connection for namespace 'common' for up to 1s
11060 11:06:34.370586 Finalising connection for namespace 'common'
11061 11:06:34.371296 Disconnecting from shell: Finalise
11062 11:06:34.371710 / #
11063 11:06:34.472758 end: 4.2 read-feedback (duration 00:00:01) [common]
11064 11:06:34.473460 end: 4 finalize (duration 00:00:01) [common]
11065 11:06:34.474110 Cleaning after the job
11066 11:06:34.474621 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925608/tftp-deploy-eut2f_1y/ramdisk
11067 11:06:34.512176 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925608/tftp-deploy-eut2f_1y/kernel
11068 11:06:34.528568 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925608/tftp-deploy-eut2f_1y/dtb
11069 11:06:34.528860 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925608/tftp-deploy-eut2f_1y/modules
11070 11:06:34.538295 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12925608
11071 11:06:34.665318 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12925608
11072 11:06:34.665497 Job finished correctly