Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 36
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 17
1 11:04:54.956322 lava-dispatcher, installed at version: 2024.01
2 11:04:54.956514 start: 0 validate
3 11:04:54.956643 Start time: 2024-03-03 11:04:54.956636+00:00 (UTC)
4 11:04:54.956762 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:04:54.956888 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240221.0%2Farm64%2Finitrd.cpio.gz exists
6 11:04:55.226223 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:04:55.226974 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:04:56.498923 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:04:56.499720 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:04:56.771077 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:04:56.771859 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240221.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:04:57.299278 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:04:57.300036 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:05:01.320221 validate duration: 6.36
16 11:05:01.320490 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:05:01.320585 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:05:01.320668 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:05:01.320794 Not decompressing ramdisk as can be used compressed.
20 11:05:01.320877 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240221.0/arm64/initrd.cpio.gz
21 11:05:01.320940 saving as /var/lib/lava/dispatcher/tmp/12925642/tftp-deploy-c06bihlb/ramdisk/initrd.cpio.gz
22 11:05:01.321005 total size: 5628149 (5 MB)
23 11:05:01.322150 progress 0 % (0 MB)
24 11:05:01.323833 progress 5 % (0 MB)
25 11:05:01.325498 progress 10 % (0 MB)
26 11:05:01.326962 progress 15 % (0 MB)
27 11:05:01.328590 progress 20 % (1 MB)
28 11:05:01.330092 progress 25 % (1 MB)
29 11:05:01.331715 progress 30 % (1 MB)
30 11:05:01.333335 progress 35 % (1 MB)
31 11:05:01.334774 progress 40 % (2 MB)
32 11:05:01.336378 progress 45 % (2 MB)
33 11:05:01.337858 progress 50 % (2 MB)
34 11:05:01.339466 progress 55 % (2 MB)
35 11:05:01.341059 progress 60 % (3 MB)
36 11:05:01.342501 progress 65 % (3 MB)
37 11:05:01.344103 progress 70 % (3 MB)
38 11:05:01.345526 progress 75 % (4 MB)
39 11:05:01.347129 progress 80 % (4 MB)
40 11:05:01.348556 progress 85 % (4 MB)
41 11:05:01.350171 progress 90 % (4 MB)
42 11:05:01.351697 progress 95 % (5 MB)
43 11:05:01.353180 progress 100 % (5 MB)
44 11:05:01.353400 5 MB downloaded in 0.03 s (165.69 MB/s)
45 11:05:01.353556 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:05:01.353790 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:05:01.353875 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:05:01.353988 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:05:01.354132 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:05:01.354200 saving as /var/lib/lava/dispatcher/tmp/12925642/tftp-deploy-c06bihlb/kernel/Image
52 11:05:01.354262 total size: 51599872 (49 MB)
53 11:05:01.354323 No compression specified
54 11:05:01.355407 progress 0 % (0 MB)
55 11:05:01.368163 progress 5 % (2 MB)
56 11:05:01.381015 progress 10 % (4 MB)
57 11:05:01.393838 progress 15 % (7 MB)
58 11:05:01.406784 progress 20 % (9 MB)
59 11:05:01.419770 progress 25 % (12 MB)
60 11:05:01.432782 progress 30 % (14 MB)
61 11:05:01.445717 progress 35 % (17 MB)
62 11:05:01.458521 progress 40 % (19 MB)
63 11:05:01.471326 progress 45 % (22 MB)
64 11:05:01.484214 progress 50 % (24 MB)
65 11:05:01.497048 progress 55 % (27 MB)
66 11:05:01.509942 progress 60 % (29 MB)
67 11:05:01.523122 progress 65 % (32 MB)
68 11:05:01.536222 progress 70 % (34 MB)
69 11:05:01.550945 progress 75 % (36 MB)
70 11:05:01.564213 progress 80 % (39 MB)
71 11:05:01.577206 progress 85 % (41 MB)
72 11:05:01.590187 progress 90 % (44 MB)
73 11:05:01.602903 progress 95 % (46 MB)
74 11:05:01.615831 progress 100 % (49 MB)
75 11:05:01.616072 49 MB downloaded in 0.26 s (187.96 MB/s)
76 11:05:01.616228 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:05:01.616468 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:05:01.616557 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:05:01.616648 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:05:01.616785 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:05:01.616855 saving as /var/lib/lava/dispatcher/tmp/12925642/tftp-deploy-c06bihlb/dtb/mt8192-asurada-spherion-r0.dtb
83 11:05:01.616917 total size: 47278 (0 MB)
84 11:05:01.616981 No compression specified
85 11:05:01.618115 progress 69 % (0 MB)
86 11:05:01.618387 progress 100 % (0 MB)
87 11:05:01.618547 0 MB downloaded in 0.00 s (27.70 MB/s)
88 11:05:01.618673 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:05:01.618896 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:05:01.618982 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:05:01.619066 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:05:01.619179 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240221.0/arm64/full.rootfs.tar.xz
94 11:05:01.619247 saving as /var/lib/lava/dispatcher/tmp/12925642/tftp-deploy-c06bihlb/nfsrootfs/full.rootfs.tar
95 11:05:01.619308 total size: 120336284 (114 MB)
96 11:05:01.619369 Using unxz to decompress xz
97 11:05:01.623071 progress 0 % (0 MB)
98 11:05:01.967039 progress 5 % (5 MB)
99 11:05:02.290012 progress 10 % (11 MB)
100 11:05:02.588401 progress 15 % (17 MB)
101 11:05:02.948922 progress 20 % (22 MB)
102 11:05:03.289862 progress 25 % (28 MB)
103 11:05:03.444760 progress 30 % (34 MB)
104 11:05:03.614246 progress 35 % (40 MB)
105 11:05:03.931005 progress 40 % (45 MB)
106 11:05:04.303847 progress 45 % (51 MB)
107 11:05:04.660993 progress 50 % (57 MB)
108 11:05:05.000777 progress 55 % (63 MB)
109 11:05:05.355728 progress 60 % (68 MB)
110 11:05:05.710131 progress 65 % (74 MB)
111 11:05:06.058916 progress 70 % (80 MB)
112 11:05:06.419302 progress 75 % (86 MB)
113 11:05:06.798962 progress 80 % (91 MB)
114 11:05:07.144787 progress 85 % (97 MB)
115 11:05:07.483296 progress 90 % (103 MB)
116 11:05:07.814210 progress 95 % (109 MB)
117 11:05:08.182331 progress 100 % (114 MB)
118 11:05:08.187726 114 MB downloaded in 6.57 s (17.47 MB/s)
119 11:05:08.187982 end: 1.4.1 http-download (duration 00:00:07) [common]
121 11:05:08.188242 end: 1.4 download-retry (duration 00:00:07) [common]
122 11:05:08.188332 start: 1.5 download-retry (timeout 00:09:53) [common]
123 11:05:08.188420 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 11:05:08.188571 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:05:08.188641 saving as /var/lib/lava/dispatcher/tmp/12925642/tftp-deploy-c06bihlb/modules/modules.tar
126 11:05:08.188702 total size: 8628476 (8 MB)
127 11:05:08.188766 Using unxz to decompress xz
128 11:05:08.455989 progress 0 % (0 MB)
129 11:05:08.476175 progress 5 % (0 MB)
130 11:05:08.500290 progress 10 % (0 MB)
131 11:05:08.524491 progress 15 % (1 MB)
132 11:05:08.547375 progress 20 % (1 MB)
133 11:05:08.571570 progress 25 % (2 MB)
134 11:05:08.595031 progress 30 % (2 MB)
135 11:05:08.623869 progress 35 % (2 MB)
136 11:05:08.649298 progress 40 % (3 MB)
137 11:05:08.673255 progress 45 % (3 MB)
138 11:05:08.697961 progress 50 % (4 MB)
139 11:05:08.723196 progress 55 % (4 MB)
140 11:05:08.747141 progress 60 % (4 MB)
141 11:05:08.773139 progress 65 % (5 MB)
142 11:05:08.797956 progress 70 % (5 MB)
143 11:05:08.823023 progress 75 % (6 MB)
144 11:05:08.849739 progress 80 % (6 MB)
145 11:05:08.874358 progress 85 % (7 MB)
146 11:05:08.898826 progress 90 % (7 MB)
147 11:05:08.928922 progress 95 % (7 MB)
148 11:05:08.957861 progress 100 % (8 MB)
149 11:05:08.963098 8 MB downloaded in 0.77 s (10.63 MB/s)
150 11:05:08.963359 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:05:08.963627 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:05:08.963722 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 11:05:08.963817 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 11:05:12.214893 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12925642/extract-nfsrootfs-iujlsesm
156 11:05:12.215104 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 11:05:12.215208 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 11:05:12.215363 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k
159 11:05:12.215486 makedir: /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin
160 11:05:12.215588 makedir: /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/tests
161 11:05:12.215682 makedir: /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/results
162 11:05:12.215780 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-add-keys
163 11:05:12.215915 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-add-sources
164 11:05:12.216038 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-background-process-start
165 11:05:12.216158 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-background-process-stop
166 11:05:12.216276 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-common-functions
167 11:05:12.216393 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-echo-ipv4
168 11:05:12.216510 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-install-packages
169 11:05:12.216626 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-installed-packages
170 11:05:12.216742 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-os-build
171 11:05:12.216864 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-probe-channel
172 11:05:12.216981 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-probe-ip
173 11:05:12.217098 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-target-ip
174 11:05:12.217213 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-target-mac
175 11:05:12.217328 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-target-storage
176 11:05:12.217446 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-test-case
177 11:05:12.217563 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-test-event
178 11:05:12.217678 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-test-feedback
179 11:05:12.217793 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-test-raise
180 11:05:12.217908 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-test-reference
181 11:05:12.218031 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-test-runner
182 11:05:12.218146 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-test-set
183 11:05:12.218260 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-test-shell
184 11:05:12.218377 Updating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-add-keys (debian)
185 11:05:12.218521 Updating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-add-sources (debian)
186 11:05:12.218664 Updating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-install-packages (debian)
187 11:05:12.218799 Updating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-installed-packages (debian)
188 11:05:12.218934 Updating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/bin/lava-os-build (debian)
189 11:05:12.219053 Creating /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/environment
190 11:05:12.219151 LAVA metadata
191 11:05:12.219220 - LAVA_JOB_ID=12925642
192 11:05:12.219282 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:05:12.219379 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 11:05:12.219444 skipped lava-vland-overlay
195 11:05:12.219515 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:05:12.219592 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 11:05:12.219651 skipped lava-multinode-overlay
198 11:05:12.219720 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:05:12.219797 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 11:05:12.219867 Loading test definitions
201 11:05:12.219955 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 11:05:12.220023 Using /lava-12925642 at stage 0
203 11:05:12.220292 uuid=12925642_1.6.2.3.1 testdef=None
204 11:05:12.220378 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:05:12.220462 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 11:05:12.220896 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:05:12.221114 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 11:05:12.221651 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:05:12.221880 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 11:05:12.222582 runner path: /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/0/tests/0_timesync-off test_uuid 12925642_1.6.2.3.1
213 11:05:12.222734 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:05:12.222953 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 11:05:12.223024 Using /lava-12925642 at stage 0
217 11:05:12.223118 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:05:12.223203 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/0/tests/1_kselftest-alsa'
219 11:05:16.155798 Running '/usr/bin/git checkout kernelci.org
220 11:05:16.264259 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 11:05:16.264981 uuid=12925642_1.6.2.3.5 testdef=None
222 11:05:16.265144 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 11:05:16.265385 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 11:05:16.266165 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:05:16.266395 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 11:05:16.267372 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:05:16.267611 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 11:05:16.268521 runner path: /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/0/tests/1_kselftest-alsa test_uuid 12925642_1.6.2.3.5
232 11:05:16.268615 BOARD='mt8192-asurada-spherion-r0'
233 11:05:16.268683 BRANCH='cip'
234 11:05:16.268743 SKIPFILE='/dev/null'
235 11:05:16.268801 SKIP_INSTALL='True'
236 11:05:16.268892 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:05:16.268952 TST_CASENAME=''
238 11:05:16.269007 TST_CMDFILES='alsa'
239 11:05:16.269149 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:05:16.269367 Creating lava-test-runner.conf files
242 11:05:16.269432 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12925642/lava-overlay-l7fruf7k/lava-12925642/0 for stage 0
243 11:05:16.269526 - 0_timesync-off
244 11:05:16.269596 - 1_kselftest-alsa
245 11:05:16.269693 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 11:05:16.269782 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 11:05:23.683557 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 11:05:23.684076 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 11:05:23.684172 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:05:23.684269 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 11:05:23.684358 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 11:05:23.844275 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:05:23.844650 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 11:05:23.844771 extracting modules file /var/lib/lava/dispatcher/tmp/12925642/tftp-deploy-c06bihlb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925642/extract-nfsrootfs-iujlsesm
255 11:05:24.046284 extracting modules file /var/lib/lava/dispatcher/tmp/12925642/tftp-deploy-c06bihlb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925642/extract-overlay-ramdisk-9kmxqk1q/ramdisk
256 11:05:24.253607 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:05:24.253780 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 11:05:24.253882 [common] Applying overlay to NFS
259 11:05:24.253989 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925642/compress-overlay-z315ux4f/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12925642/extract-nfsrootfs-iujlsesm
260 11:05:25.160179 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:05:25.160362 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 11:05:25.160485 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:05:25.160595 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 11:05:25.160685 Building ramdisk /var/lib/lava/dispatcher/tmp/12925642/extract-overlay-ramdisk-9kmxqk1q/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12925642/extract-overlay-ramdisk-9kmxqk1q/ramdisk
265 11:05:25.485888 >> 130574 blocks
266 11:05:27.607295 rename /var/lib/lava/dispatcher/tmp/12925642/extract-overlay-ramdisk-9kmxqk1q/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12925642/tftp-deploy-c06bihlb/ramdisk/ramdisk.cpio.gz
267 11:05:27.607846 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:05:27.608027 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 11:05:27.608178 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 11:05:27.608330 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12925642/tftp-deploy-c06bihlb/kernel/Image'
271 11:05:40.650215 Returned 0 in 13 seconds
272 11:05:40.750965 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12925642/tftp-deploy-c06bihlb/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12925642/tftp-deploy-c06bihlb/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12925642/tftp-deploy-c06bihlb/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12925642/tftp-deploy-c06bihlb/kernel/image.itb
273 11:05:41.093122 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:05:41.093489 output: Created: Sun Mar 3 11:05:41 2024
275 11:05:41.093568 output: Image 0 (kernel-1)
276 11:05:41.093637 output: Description:
277 11:05:41.093704 output: Created: Sun Mar 3 11:05:41 2024
278 11:05:41.093769 output: Type: Kernel Image
279 11:05:41.093832 output: Compression: lzma compressed
280 11:05:41.093890 output: Data Size: 12057697 Bytes = 11775.09 KiB = 11.50 MiB
281 11:05:41.093954 output: Architecture: AArch64
282 11:05:41.094014 output: OS: Linux
283 11:05:41.094070 output: Load Address: 0x00000000
284 11:05:41.094128 output: Entry Point: 0x00000000
285 11:05:41.094187 output: Hash algo: crc32
286 11:05:41.094246 output: Hash value: cf43f4f3
287 11:05:41.094304 output: Image 1 (fdt-1)
288 11:05:41.094363 output: Description: mt8192-asurada-spherion-r0
289 11:05:41.094421 output: Created: Sun Mar 3 11:05:41 2024
290 11:05:41.094478 output: Type: Flat Device Tree
291 11:05:41.094532 output: Compression: uncompressed
292 11:05:41.094587 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 11:05:41.094642 output: Architecture: AArch64
294 11:05:41.094698 output: Hash algo: crc32
295 11:05:41.094752 output: Hash value: cc4352de
296 11:05:41.094806 output: Image 2 (ramdisk-1)
297 11:05:41.094861 output: Description: unavailable
298 11:05:41.094914 output: Created: Sun Mar 3 11:05:41 2024
299 11:05:41.094969 output: Type: RAMDisk Image
300 11:05:41.095024 output: Compression: Unknown Compression
301 11:05:41.095078 output: Data Size: 18774881 Bytes = 18334.84 KiB = 17.91 MiB
302 11:05:41.095132 output: Architecture: AArch64
303 11:05:41.095186 output: OS: Linux
304 11:05:41.095239 output: Load Address: unavailable
305 11:05:41.095293 output: Entry Point: unavailable
306 11:05:41.095347 output: Hash algo: crc32
307 11:05:41.095401 output: Hash value: e6a2f3b0
308 11:05:41.095455 output: Default Configuration: 'conf-1'
309 11:05:41.095509 output: Configuration 0 (conf-1)
310 11:05:41.095563 output: Description: mt8192-asurada-spherion-r0
311 11:05:41.095617 output: Kernel: kernel-1
312 11:05:41.095671 output: Init Ramdisk: ramdisk-1
313 11:05:41.095725 output: FDT: fdt-1
314 11:05:41.095778 output: Loadables: kernel-1
315 11:05:41.095831 output:
316 11:05:41.096024 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 11:05:41.096128 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 11:05:41.096234 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 11:05:41.096330 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 11:05:41.096413 No LXC device requested
321 11:05:41.096491 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:05:41.096579 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 11:05:41.096656 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:05:41.096725 Checking files for TFTP limit of 4294967296 bytes.
325 11:05:41.097222 end: 1 tftp-deploy (duration 00:00:40) [common]
326 11:05:41.097329 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:05:41.097423 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:05:41.097552 substitutions:
329 11:05:41.097625 - {DTB}: 12925642/tftp-deploy-c06bihlb/dtb/mt8192-asurada-spherion-r0.dtb
330 11:05:41.097692 - {INITRD}: 12925642/tftp-deploy-c06bihlb/ramdisk/ramdisk.cpio.gz
331 11:05:41.097753 - {KERNEL}: 12925642/tftp-deploy-c06bihlb/kernel/Image
332 11:05:41.097812 - {LAVA_MAC}: None
333 11:05:41.097870 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12925642/extract-nfsrootfs-iujlsesm
334 11:05:41.097928 - {NFS_SERVER_IP}: 192.168.201.1
335 11:05:41.097996 - {PRESEED_CONFIG}: None
336 11:05:41.098053 - {PRESEED_LOCAL}: None
337 11:05:41.098109 - {RAMDISK}: 12925642/tftp-deploy-c06bihlb/ramdisk/ramdisk.cpio.gz
338 11:05:41.098165 - {ROOT_PART}: None
339 11:05:41.098220 - {ROOT}: None
340 11:05:41.098274 - {SERVER_IP}: 192.168.201.1
341 11:05:41.098329 - {TEE}: None
342 11:05:41.098384 Parsed boot commands:
343 11:05:41.098438 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:05:41.098614 Parsed boot commands: tftpboot 192.168.201.1 12925642/tftp-deploy-c06bihlb/kernel/image.itb 12925642/tftp-deploy-c06bihlb/kernel/cmdline
345 11:05:41.098709 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:05:41.098796 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:05:41.098892 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:05:41.098978 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:05:41.099052 Not connected, no need to disconnect.
350 11:05:41.099127 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:05:41.099210 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:05:41.099281 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 11:05:41.102669 Setting prompt string to ['lava-test: # ']
354 11:05:41.103014 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:05:41.103127 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:05:41.103229 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:05:41.103325 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:05:41.103518 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 11:05:46.233476 >> Command sent successfully.
360 11:05:46.236596 Returned 0 in 5 seconds
361 11:05:46.336995 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:05:46.337432 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:05:46.337576 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:05:46.337697 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:05:46.337798 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:05:46.337907 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:05:46.338250 [Enter `^Ec?' for help]
369 11:05:46.509609
370 11:05:46.509766
371 11:05:46.509878 F0: 102B 0000
372 11:05:46.510020
373 11:05:46.510091 F3: 1001 0000 [0200]
374 11:05:46.510172
375 11:05:46.513254 F3: 1001 0000
376 11:05:46.513341
377 11:05:46.513411 F7: 102D 0000
378 11:05:46.513475
379 11:05:46.513537 F1: 0000 0000
380 11:05:46.513597
381 11:05:46.517130 V0: 0000 0000 [0001]
382 11:05:46.517216
383 11:05:46.517285 00: 0007 8000
384 11:05:46.517355
385 11:05:46.521356 01: 0000 0000
386 11:05:46.521444
387 11:05:46.521510 BP: 0C00 0209 [0000]
388 11:05:46.521573
389 11:05:46.521632 G0: 1182 0000
390 11:05:46.521690
391 11:05:46.525126 EC: 0000 0021 [4000]
392 11:05:46.525212
393 11:05:46.525279 S7: 0000 0000 [0000]
394 11:05:46.525342
395 11:05:46.528590 CC: 0000 0000 [0001]
396 11:05:46.528675
397 11:05:46.528743 T0: 0000 0040 [010F]
398 11:05:46.531935
399 11:05:46.532020 Jump to BL
400 11:05:46.532087
401 11:05:46.556134
402 11:05:46.556223
403 11:05:46.556291
404 11:05:46.563389 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:05:46.566546 ARM64: Exception handlers installed.
406 11:05:46.570248 ARM64: Testing exception
407 11:05:46.573826 ARM64: Done test exception
408 11:05:46.580996 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:05:46.591570 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:05:46.598465 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:05:46.608353 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:05:46.615121 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:05:46.621528 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:05:46.632980 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:05:46.639930 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:05:46.658970 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:05:46.662401 WDT: Last reset was cold boot
418 11:05:46.665773 SPI1(PAD0) initialized at 2873684 Hz
419 11:05:46.669061 SPI5(PAD0) initialized at 992727 Hz
420 11:05:46.672325 VBOOT: Loading verstage.
421 11:05:46.678917 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:05:46.682241 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:05:46.685604 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:05:46.689041 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:05:46.696595 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:05:46.703276 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:05:46.714055 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 11:05:46.714144
429 11:05:46.714209
430 11:05:46.723917 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:05:46.727862 ARM64: Exception handlers installed.
432 11:05:46.730899 ARM64: Testing exception
433 11:05:46.730985 ARM64: Done test exception
434 11:05:46.737498 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:05:46.740932 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:05:46.755228 Probing TPM: . done!
437 11:05:46.755314 TPM ready after 0 ms
438 11:05:46.761585 Connected to device vid:did:rid of 1ae0:0028:00
439 11:05:46.768898 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 11:05:46.825184 Initialized TPM device CR50 revision 0
441 11:05:46.836624 tlcl_send_startup: Startup return code is 0
442 11:05:46.836714 TPM: setup succeeded
443 11:05:46.848241 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:05:46.857470 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:05:46.867286 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:05:46.876644 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:05:46.879734 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:05:46.887960 in-header: 03 07 00 00 08 00 00 00
449 11:05:46.891876 in-data: aa e4 47 04 13 02 00 00
450 11:05:46.895855 Chrome EC: UHEPI supported
451 11:05:46.902625 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:05:46.906426 in-header: 03 ad 00 00 08 00 00 00
453 11:05:46.910158 in-data: 00 20 20 08 00 00 00 00
454 11:05:46.910246 Phase 1
455 11:05:46.913853 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:05:46.921448 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:05:46.925068 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:05:46.928461 Recovery requested (1009000e)
459 11:05:46.937641 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:05:46.943281 tlcl_extend: response is 0
461 11:05:46.952691 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:05:46.958368 tlcl_extend: response is 0
463 11:05:46.965234 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:05:46.986060 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 11:05:46.992758 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:05:46.992852
467 11:05:46.992919
468 11:05:47.002601 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:05:47.006035 ARM64: Exception handlers installed.
470 11:05:47.006120 ARM64: Testing exception
471 11:05:47.009800 ARM64: Done test exception
472 11:05:47.030979 pmic_efuse_setting: Set efuses in 11 msecs
473 11:05:47.034258 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:05:47.041059 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:05:47.045040 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:05:47.048274 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:05:47.054870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:05:47.059042 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:05:47.066116 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:05:47.070139 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:05:47.073761 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:05:47.077280 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:05:47.084607 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:05:47.088207 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:05:47.092078 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:05:47.095009 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:05:47.102259 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:05:47.109032 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:05:47.116225 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:05:47.119981 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:05:47.127238 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:05:47.131085 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:05:47.137738 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:05:47.141176 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:05:47.148376 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:05:47.154798 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:05:47.158170 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:05:47.164978 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:05:47.171659 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:05:47.175262 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:05:47.178639 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:05:47.185316 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:05:47.188378 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:05:47.195451 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:05:47.198504 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:05:47.205378 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:05:47.208316 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:05:47.215143 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:05:47.218623 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:05:47.225337 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:05:47.228885 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:05:47.235196 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:05:47.238441 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:05:47.242016 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:05:47.248770 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:05:47.252656 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:05:47.256193 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:05:47.259436 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:05:47.266109 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:05:47.269828 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:05:47.272946 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:05:47.276298 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:05:47.283078 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:05:47.286391 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:05:47.293062 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:05:47.303218 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:05:47.306234 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:05:47.316325 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:05:47.323114 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:05:47.326299 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:05:47.333154 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:05:47.336423 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:05:47.343393 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x31
534 11:05:47.350157 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:05:47.353703 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 11:05:47.356888 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:05:47.368767 [RTC]rtc_get_frequency_meter,154: input=15, output=772
538 11:05:47.377690 [RTC]rtc_get_frequency_meter,154: input=23, output=957
539 11:05:47.386930 [RTC]rtc_get_frequency_meter,154: input=19, output=865
540 11:05:47.396613 [RTC]rtc_get_frequency_meter,154: input=17, output=819
541 11:05:47.406371 [RTC]rtc_get_frequency_meter,154: input=16, output=796
542 11:05:47.409465 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 11:05:47.416355 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 11:05:47.419259 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
545 11:05:47.422865 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 11:05:47.426146 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
547 11:05:47.429327 ADC[4]: Raw value=902507 ID=7
548 11:05:47.432928 ADC[3]: Raw value=213179 ID=1
549 11:05:47.433013 RAM Code: 0x71
550 11:05:47.439659 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 11:05:47.442941 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 11:05:47.452876 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 11:05:47.459422 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 11:05:47.462898 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 11:05:47.466318 in-header: 03 07 00 00 08 00 00 00
556 11:05:47.469764 in-data: aa e4 47 04 13 02 00 00
557 11:05:47.473454 Chrome EC: UHEPI supported
558 11:05:47.476562 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 11:05:47.486681 in-header: 03 ed 00 00 08 00 00 00
560 11:05:47.490440 in-data: 80 20 60 08 00 00 00 00
561 11:05:47.494560 MRC: failed to locate region type 0.
562 11:05:47.501957 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 11:05:47.502058 DRAM-K: Running full calibration
564 11:05:47.509259 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 11:05:47.512534 header.status = 0x0
566 11:05:47.516227 header.version = 0x6 (expected: 0x6)
567 11:05:47.520345 header.size = 0xd00 (expected: 0xd00)
568 11:05:47.520423 header.flags = 0x0
569 11:05:47.527005 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 11:05:47.543726 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
571 11:05:47.550319 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 11:05:47.553584 dram_init: ddr_geometry: 2
573 11:05:47.557042 [EMI] MDL number = 2
574 11:05:47.557127 [EMI] Get MDL freq = 0
575 11:05:47.560246 dram_init: ddr_type: 0
576 11:05:47.560331 is_discrete_lpddr4: 1
577 11:05:47.563841 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 11:05:47.563926
579 11:05:47.563994
580 11:05:47.566888 [Bian_co] ETT version 0.0.0.1
581 11:05:47.573747 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 11:05:47.573835
583 11:05:47.577028 dramc_set_vcore_voltage set vcore to 650000
584 11:05:47.577114 Read voltage for 800, 4
585 11:05:47.580254 Vio18 = 0
586 11:05:47.580339 Vcore = 650000
587 11:05:47.580406 Vdram = 0
588 11:05:47.583751 Vddq = 0
589 11:05:47.583836 Vmddr = 0
590 11:05:47.587228 dram_init: config_dvfs: 1
591 11:05:47.590956 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 11:05:47.594678 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 11:05:47.598386 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
594 11:05:47.602661 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
595 11:05:47.606519 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 11:05:47.609864 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 11:05:47.613869 MEM_TYPE=3, freq_sel=18
598 11:05:47.617108 sv_algorithm_assistance_LP4_1600
599 11:05:47.620249 ============ PULL DRAM RESETB DOWN ============
600 11:05:47.623725 ========== PULL DRAM RESETB DOWN end =========
601 11:05:47.630376 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 11:05:47.633785 ===================================
603 11:05:47.637216 LPDDR4 DRAM CONFIGURATION
604 11:05:47.637301 ===================================
605 11:05:47.640565 EX_ROW_EN[0] = 0x0
606 11:05:47.643906 EX_ROW_EN[1] = 0x0
607 11:05:47.643991 LP4Y_EN = 0x0
608 11:05:47.647131 WORK_FSP = 0x0
609 11:05:47.647216 WL = 0x2
610 11:05:47.650442 RL = 0x2
611 11:05:47.650527 BL = 0x2
612 11:05:47.653959 RPST = 0x0
613 11:05:47.654061 RD_PRE = 0x0
614 11:05:47.657293 WR_PRE = 0x1
615 11:05:47.657378 WR_PST = 0x0
616 11:05:47.660875 DBI_WR = 0x0
617 11:05:47.660961 DBI_RD = 0x0
618 11:05:47.663641 OTF = 0x1
619 11:05:47.667104 ===================================
620 11:05:47.670594 ===================================
621 11:05:47.670679 ANA top config
622 11:05:47.673810 ===================================
623 11:05:47.677594 DLL_ASYNC_EN = 0
624 11:05:47.680651 ALL_SLAVE_EN = 1
625 11:05:47.683708 NEW_RANK_MODE = 1
626 11:05:47.683807 DLL_IDLE_MODE = 1
627 11:05:47.687183 LP45_APHY_COMB_EN = 1
628 11:05:47.690724 TX_ODT_DIS = 1
629 11:05:47.694069 NEW_8X_MODE = 1
630 11:05:47.697311 ===================================
631 11:05:47.700309 ===================================
632 11:05:47.704023 data_rate = 1600
633 11:05:47.704100 CKR = 1
634 11:05:47.707441 DQ_P2S_RATIO = 8
635 11:05:47.710335 ===================================
636 11:05:47.714115 CA_P2S_RATIO = 8
637 11:05:47.717580 DQ_CA_OPEN = 0
638 11:05:47.720702 DQ_SEMI_OPEN = 0
639 11:05:47.720786 CA_SEMI_OPEN = 0
640 11:05:47.724188 CA_FULL_RATE = 0
641 11:05:47.727341 DQ_CKDIV4_EN = 1
642 11:05:47.730589 CA_CKDIV4_EN = 1
643 11:05:47.733905 CA_PREDIV_EN = 0
644 11:05:47.737314 PH8_DLY = 0
645 11:05:47.737388 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 11:05:47.740796 DQ_AAMCK_DIV = 4
647 11:05:47.743750 CA_AAMCK_DIV = 4
648 11:05:47.747539 CA_ADMCK_DIV = 4
649 11:05:47.750809 DQ_TRACK_CA_EN = 0
650 11:05:47.754467 CA_PICK = 800
651 11:05:47.754538 CA_MCKIO = 800
652 11:05:47.757188 MCKIO_SEMI = 0
653 11:05:47.760587 PLL_FREQ = 3068
654 11:05:47.764361 DQ_UI_PI_RATIO = 32
655 11:05:47.767202 CA_UI_PI_RATIO = 0
656 11:05:47.771072 ===================================
657 11:05:47.773924 ===================================
658 11:05:47.777677 memory_type:LPDDR4
659 11:05:47.777776 GP_NUM : 10
660 11:05:47.780865 SRAM_EN : 1
661 11:05:47.780967 MD32_EN : 0
662 11:05:47.784777 ===================================
663 11:05:47.788271 [ANA_INIT] >>>>>>>>>>>>>>
664 11:05:47.792329 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 11:05:47.795856 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 11:05:47.795965 ===================================
667 11:05:47.799798 data_rate = 1600,PCW = 0X7600
668 11:05:47.803550 ===================================
669 11:05:47.806904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 11:05:47.814361 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 11:05:47.818214 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 11:05:47.821071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 11:05:47.824762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 11:05:47.828181 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 11:05:47.831190 [ANA_INIT] flow start
676 11:05:47.834905 [ANA_INIT] PLL >>>>>>>>
677 11:05:47.835010 [ANA_INIT] PLL <<<<<<<<
678 11:05:47.838132 [ANA_INIT] MIDPI >>>>>>>>
679 11:05:47.841484 [ANA_INIT] MIDPI <<<<<<<<
680 11:05:47.841594 [ANA_INIT] DLL >>>>>>>>
681 11:05:47.844817 [ANA_INIT] flow end
682 11:05:47.848088 ============ LP4 DIFF to SE enter ============
683 11:05:47.851511 ============ LP4 DIFF to SE exit ============
684 11:05:47.854906 [ANA_INIT] <<<<<<<<<<<<<
685 11:05:47.858172 [Flow] Enable top DCM control >>>>>
686 11:05:47.861435 [Flow] Enable top DCM control <<<<<
687 11:05:47.865152 Enable DLL master slave shuffle
688 11:05:47.871735 ==============================================================
689 11:05:47.871818 Gating Mode config
690 11:05:47.878149 ==============================================================
691 11:05:47.878259 Config description:
692 11:05:47.888580 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 11:05:47.895463 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 11:05:47.901708 SELPH_MODE 0: By rank 1: By Phase
695 11:05:47.905224 ==============================================================
696 11:05:47.908605 GAT_TRACK_EN = 1
697 11:05:47.912160 RX_GATING_MODE = 2
698 11:05:47.915271 RX_GATING_TRACK_MODE = 2
699 11:05:47.918698 SELPH_MODE = 1
700 11:05:47.921848 PICG_EARLY_EN = 1
701 11:05:47.925217 VALID_LAT_VALUE = 1
702 11:05:47.928452 ==============================================================
703 11:05:47.931940 Enter into Gating configuration >>>>
704 11:05:47.935221 Exit from Gating configuration <<<<
705 11:05:47.938849 Enter into DVFS_PRE_config >>>>>
706 11:05:47.952084 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 11:05:47.952177 Exit from DVFS_PRE_config <<<<<
708 11:05:47.955254 Enter into PICG configuration >>>>
709 11:05:47.958681 Exit from PICG configuration <<<<
710 11:05:47.962109 [RX_INPUT] configuration >>>>>
711 11:05:47.965330 [RX_INPUT] configuration <<<<<
712 11:05:47.972033 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 11:05:47.975251 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 11:05:47.982010 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 11:05:47.988841 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 11:05:47.995469 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 11:05:48.002207 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 11:05:48.006304 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 11:05:48.009814 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 11:05:48.013282 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 11:05:48.016740 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 11:05:48.019747 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 11:05:48.026516 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 11:05:48.029552 ===================================
725 11:05:48.029639 LPDDR4 DRAM CONFIGURATION
726 11:05:48.033041 ===================================
727 11:05:48.036551 EX_ROW_EN[0] = 0x0
728 11:05:48.039708 EX_ROW_EN[1] = 0x0
729 11:05:48.039810 LP4Y_EN = 0x0
730 11:05:48.043191 WORK_FSP = 0x0
731 11:05:48.043278 WL = 0x2
732 11:05:48.047074 RL = 0x2
733 11:05:48.047161 BL = 0x2
734 11:05:48.050768 RPST = 0x0
735 11:05:48.050855 RD_PRE = 0x0
736 11:05:48.054474 WR_PRE = 0x1
737 11:05:48.054560 WR_PST = 0x0
738 11:05:48.054628 DBI_WR = 0x0
739 11:05:48.057773 DBI_RD = 0x0
740 11:05:48.057910 OTF = 0x1
741 11:05:48.061483 ===================================
742 11:05:48.065555 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 11:05:48.072252 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 11:05:48.075730 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 11:05:48.079881 ===================================
746 11:05:48.079968 LPDDR4 DRAM CONFIGURATION
747 11:05:48.083231 ===================================
748 11:05:48.086983 EX_ROW_EN[0] = 0x10
749 11:05:48.087070 EX_ROW_EN[1] = 0x0
750 11:05:48.090626 LP4Y_EN = 0x0
751 11:05:48.090729 WORK_FSP = 0x0
752 11:05:48.094004 WL = 0x2
753 11:05:48.094107 RL = 0x2
754 11:05:48.098025 BL = 0x2
755 11:05:48.098106 RPST = 0x0
756 11:05:48.101378 RD_PRE = 0x0
757 11:05:48.101469 WR_PRE = 0x1
758 11:05:48.105304 WR_PST = 0x0
759 11:05:48.105393 DBI_WR = 0x0
760 11:05:48.108695 DBI_RD = 0x0
761 11:05:48.108784 OTF = 0x1
762 11:05:48.112329 ===================================
763 11:05:48.120302 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 11:05:48.123584 nWR fixed to 40
765 11:05:48.123674 [ModeRegInit_LP4] CH0 RK0
766 11:05:48.127702 [ModeRegInit_LP4] CH0 RK1
767 11:05:48.127791 [ModeRegInit_LP4] CH1 RK0
768 11:05:48.130959 [ModeRegInit_LP4] CH1 RK1
769 11:05:48.134544 match AC timing 13
770 11:05:48.138471 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 11:05:48.142108 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 11:05:48.145770 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 11:05:48.149538 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 11:05:48.153431 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 11:05:48.157107 [EMI DOE] emi_dcm 0
776 11:05:48.161075 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 11:05:48.161235 ==
778 11:05:48.164667 Dram Type= 6, Freq= 0, CH_0, rank 0
779 11:05:48.168537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 11:05:48.168625 ==
781 11:05:48.175779 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 11:05:48.179053 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 11:05:48.189910 [CA 0] Center 38 (7~69) winsize 63
784 11:05:48.193430 [CA 1] Center 38 (7~69) winsize 63
785 11:05:48.197281 [CA 2] Center 35 (5~66) winsize 62
786 11:05:48.201063 [CA 3] Center 35 (5~66) winsize 62
787 11:05:48.205230 [CA 4] Center 35 (4~66) winsize 63
788 11:05:48.205316 [CA 5] Center 33 (3~64) winsize 62
789 11:05:48.208812
790 11:05:48.212323 [CmdBusTrainingLP45] Vref(ca) range 1: 32
791 11:05:48.212411
792 11:05:48.216061 [CATrainingPosCal] consider 1 rank data
793 11:05:48.216161 u2DelayCellTimex100 = 270/100 ps
794 11:05:48.219769 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
795 11:05:48.223584 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 11:05:48.227217 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 11:05:48.231091 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
798 11:05:48.234866 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
799 11:05:48.238600 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 11:05:48.238687
801 11:05:48.242055 CA PerBit enable=1, Macro0, CA PI delay=33
802 11:05:48.242141
803 11:05:48.245806 [CBTSetCACLKResult] CA Dly = 33
804 11:05:48.249252 CS Dly: 5 (0~36)
805 11:05:48.249338 ==
806 11:05:48.253238 Dram Type= 6, Freq= 0, CH_0, rank 1
807 11:05:48.257227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 11:05:48.257313 ==
809 11:05:48.260569 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 11:05:48.268142 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 11:05:48.276717 [CA 0] Center 38 (7~69) winsize 63
812 11:05:48.280025 [CA 1] Center 38 (8~69) winsize 62
813 11:05:48.283777 [CA 2] Center 36 (6~67) winsize 62
814 11:05:48.287522 [CA 3] Center 36 (5~67) winsize 63
815 11:05:48.291230 [CA 4] Center 35 (4~66) winsize 63
816 11:05:48.294844 [CA 5] Center 34 (4~65) winsize 62
817 11:05:48.294930
818 11:05:48.298986 [CmdBusTrainingLP45] Vref(ca) range 1: 34
819 11:05:48.299073
820 11:05:48.302364 [CATrainingPosCal] consider 2 rank data
821 11:05:48.302451 u2DelayCellTimex100 = 270/100 ps
822 11:05:48.306194 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
823 11:05:48.309751 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
824 11:05:48.313572 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
825 11:05:48.317790 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 11:05:48.321629 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
827 11:05:48.325448 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 11:05:48.325534
829 11:05:48.329170 CA PerBit enable=1, Macro0, CA PI delay=34
830 11:05:48.329256
831 11:05:48.332969 [CBTSetCACLKResult] CA Dly = 34
832 11:05:48.333075 CS Dly: 6 (0~38)
833 11:05:48.333177
834 11:05:48.336429 ----->DramcWriteLeveling(PI) begin...
835 11:05:48.340261 ==
836 11:05:48.340347 Dram Type= 6, Freq= 0, CH_0, rank 0
837 11:05:48.343596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 11:05:48.347480 ==
839 11:05:48.347596 Write leveling (Byte 0): 32 => 32
840 11:05:48.350776 Write leveling (Byte 1): 31 => 31
841 11:05:48.354134 DramcWriteLeveling(PI) end<-----
842 11:05:48.354212
843 11:05:48.354278 ==
844 11:05:48.357645 Dram Type= 6, Freq= 0, CH_0, rank 0
845 11:05:48.364267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 11:05:48.364375 ==
847 11:05:48.364469 [Gating] SW mode calibration
848 11:05:48.371911 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 11:05:48.379234 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 11:05:48.382984 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
851 11:05:48.385977 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
852 11:05:48.389331 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 11:05:48.396736 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 11:05:48.400135 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 11:05:48.403800 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:05:48.406733 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:05:48.413581 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:05:48.416890 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:05:48.420231 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:05:48.426760 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:05:48.430303 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:05:48.433474 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:05:48.440173 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:05:48.443517 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:05:48.446787 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:05:48.453329 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:05:48.456736 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
868 11:05:48.460267 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:05:48.466963 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:05:48.470134 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 11:05:48.473538 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 11:05:48.480372 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:05:48.483731 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:05:48.487040 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:05:48.490331 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
876 11:05:48.496983 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (1 1) (1 1)
877 11:05:48.500652 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
878 11:05:48.503861 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 11:05:48.510791 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 11:05:48.513845 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 11:05:48.517149 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:05:48.524042 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:05:48.527255 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
884 11:05:48.530745 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
885 11:05:48.537322 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
886 11:05:48.540703 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 11:05:48.544090 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 11:05:48.547468 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 11:05:48.554002 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:05:48.557253 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:05:48.560538 0 11 4 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
892 11:05:48.567404 0 11 8 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
893 11:05:48.571005 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
894 11:05:48.573974 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 11:05:48.580586 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 11:05:48.584066 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 11:05:48.587441 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:05:48.594285 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:05:48.597730 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
900 11:05:48.601003 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
901 11:05:48.607539 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 11:05:48.611275 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 11:05:48.614284 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 11:05:48.620865 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:05:48.624160 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:05:48.627410 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:05:48.634239 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:05:48.637568 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:05:48.640779 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:05:48.644202 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:05:48.650771 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:05:48.654203 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:05:48.657490 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:05:48.664195 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:05:48.667702 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
916 11:05:48.670845 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
917 11:05:48.674273 Total UI for P1: 0, mck2ui 16
918 11:05:48.677765 best dqsien dly found for B0: ( 0, 14, 4)
919 11:05:48.684500 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 11:05:48.684602 Total UI for P1: 0, mck2ui 16
921 11:05:48.691102 best dqsien dly found for B1: ( 0, 14, 6)
922 11:05:48.694235 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
923 11:05:48.697681 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
924 11:05:48.697783
925 11:05:48.700935 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
926 11:05:48.704347 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
927 11:05:48.707563 [Gating] SW calibration Done
928 11:05:48.707663 ==
929 11:05:48.710674 Dram Type= 6, Freq= 0, CH_0, rank 0
930 11:05:48.714121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 11:05:48.714197 ==
932 11:05:48.717399 RX Vref Scan: 0
933 11:05:48.717523
934 11:05:48.717633 RX Vref 0 -> 0, step: 1
935 11:05:48.717725
936 11:05:48.721144 RX Delay -130 -> 252, step: 16
937 11:05:48.724288 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
938 11:05:48.730889 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 11:05:48.734107 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
940 11:05:48.737482 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
941 11:05:48.741222 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
942 11:05:48.744465 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
943 11:05:48.747820 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
944 11:05:48.754468 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 11:05:48.757739 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 11:05:48.761249 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
947 11:05:48.764566 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
948 11:05:48.767841 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
949 11:05:48.774338 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
950 11:05:48.777608 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
951 11:05:48.781199 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 11:05:48.784485 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
953 11:05:48.784572 ==
954 11:05:48.787900 Dram Type= 6, Freq= 0, CH_0, rank 0
955 11:05:48.794700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 11:05:48.794786 ==
957 11:05:48.794855 DQS Delay:
958 11:05:48.797902 DQS0 = 0, DQS1 = 0
959 11:05:48.798009 DQM Delay:
960 11:05:48.798078 DQM0 = 93, DQM1 = 81
961 11:05:48.801143 DQ Delay:
962 11:05:48.804539 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
963 11:05:48.807603 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
964 11:05:48.811359 DQ8 =77, DQ9 =61, DQ10 =85, DQ11 =77
965 11:05:48.814417 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
966 11:05:48.814502
967 11:05:48.814570
968 11:05:48.814635 ==
969 11:05:48.817865 Dram Type= 6, Freq= 0, CH_0, rank 0
970 11:05:48.821038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 11:05:48.821124 ==
972 11:05:48.821191
973 11:05:48.821254
974 11:05:48.824598 TX Vref Scan disable
975 11:05:48.824684 == TX Byte 0 ==
976 11:05:48.831440 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
977 11:05:48.834793 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
978 11:05:48.834878 == TX Byte 1 ==
979 11:05:48.841165 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 11:05:48.844819 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 11:05:48.844905 ==
982 11:05:48.847978 Dram Type= 6, Freq= 0, CH_0, rank 0
983 11:05:48.851195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 11:05:48.851286 ==
985 11:05:48.865565 TX Vref=22, minBit 13, minWin=26, winSum=439
986 11:05:48.868999 TX Vref=24, minBit 8, minWin=27, winSum=444
987 11:05:48.871886 TX Vref=26, minBit 8, minWin=27, winSum=447
988 11:05:48.875589 TX Vref=28, minBit 1, minWin=28, winSum=454
989 11:05:48.878905 TX Vref=30, minBit 3, minWin=28, winSum=455
990 11:05:48.882075 TX Vref=32, minBit 3, minWin=28, winSum=455
991 11:05:48.888830 [TxChooseVref] Worse bit 3, Min win 28, Win sum 455, Final Vref 30
992 11:05:48.888913
993 11:05:48.891978 Final TX Range 1 Vref 30
994 11:05:48.892062
995 11:05:48.892157 ==
996 11:05:48.895165 Dram Type= 6, Freq= 0, CH_0, rank 0
997 11:05:48.899135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 11:05:48.899209 ==
999 11:05:48.899273
1000 11:05:48.901878
1001 11:05:48.902014 TX Vref Scan disable
1002 11:05:48.905137 == TX Byte 0 ==
1003 11:05:48.908776 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1004 11:05:48.912203 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1005 11:05:48.915446 == TX Byte 1 ==
1006 11:05:48.919424 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1007 11:05:48.921840 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1008 11:05:48.925321
1009 11:05:48.925396 [DATLAT]
1010 11:05:48.925459 Freq=800, CH0 RK0
1011 11:05:48.925520
1012 11:05:48.928679 DATLAT Default: 0xa
1013 11:05:48.928780 0, 0xFFFF, sum = 0
1014 11:05:48.931912 1, 0xFFFF, sum = 0
1015 11:05:48.931986 2, 0xFFFF, sum = 0
1016 11:05:48.935583 3, 0xFFFF, sum = 0
1017 11:05:48.935661 4, 0xFFFF, sum = 0
1018 11:05:48.938824 5, 0xFFFF, sum = 0
1019 11:05:48.938899 6, 0xFFFF, sum = 0
1020 11:05:48.942056 7, 0xFFFF, sum = 0
1021 11:05:48.942134 8, 0xFFFF, sum = 0
1022 11:05:48.945329 9, 0x0, sum = 1
1023 11:05:48.945431 10, 0x0, sum = 2
1024 11:05:48.949078 11, 0x0, sum = 3
1025 11:05:48.949186 12, 0x0, sum = 4
1026 11:05:48.952323 best_step = 10
1027 11:05:48.952422
1028 11:05:48.952511 ==
1029 11:05:48.955734 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 11:05:48.958887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 11:05:48.958960 ==
1032 11:05:48.962509 RX Vref Scan: 1
1033 11:05:48.962593
1034 11:05:48.962655 Set Vref Range= 32 -> 127
1035 11:05:48.962713
1036 11:05:48.965765 RX Vref 32 -> 127, step: 1
1037 11:05:48.965867
1038 11:05:48.968760 RX Delay -95 -> 252, step: 8
1039 11:05:48.968863
1040 11:05:48.972028 Set Vref, RX VrefLevel [Byte0]: 32
1041 11:05:48.975553 [Byte1]: 32
1042 11:05:48.975626
1043 11:05:48.978957 Set Vref, RX VrefLevel [Byte0]: 33
1044 11:05:48.982212 [Byte1]: 33
1045 11:05:48.985805
1046 11:05:48.985902 Set Vref, RX VrefLevel [Byte0]: 34
1047 11:05:48.989066 [Byte1]: 34
1048 11:05:48.993279
1049 11:05:48.993388 Set Vref, RX VrefLevel [Byte0]: 35
1050 11:05:48.996330 [Byte1]: 35
1051 11:05:49.000803
1052 11:05:49.000886 Set Vref, RX VrefLevel [Byte0]: 36
1053 11:05:49.004191 [Byte1]: 36
1054 11:05:49.008411
1055 11:05:49.008494 Set Vref, RX VrefLevel [Byte0]: 37
1056 11:05:49.011854 [Byte1]: 37
1057 11:05:49.016264
1058 11:05:49.016380 Set Vref, RX VrefLevel [Byte0]: 38
1059 11:05:49.019278 [Byte1]: 38
1060 11:05:49.023387
1061 11:05:49.023488 Set Vref, RX VrefLevel [Byte0]: 39
1062 11:05:49.027242 [Byte1]: 39
1063 11:05:49.031787
1064 11:05:49.031892 Set Vref, RX VrefLevel [Byte0]: 40
1065 11:05:49.034633 [Byte1]: 40
1066 11:05:49.038923
1067 11:05:49.038999 Set Vref, RX VrefLevel [Byte0]: 41
1068 11:05:49.042471 [Byte1]: 41
1069 11:05:49.047014
1070 11:05:49.047090 Set Vref, RX VrefLevel [Byte0]: 42
1071 11:05:49.050240 [Byte1]: 42
1072 11:05:49.054482
1073 11:05:49.054565 Set Vref, RX VrefLevel [Byte0]: 43
1074 11:05:49.057796 [Byte1]: 43
1075 11:05:49.061556
1076 11:05:49.061639 Set Vref, RX VrefLevel [Byte0]: 44
1077 11:05:49.064908 [Byte1]: 44
1078 11:05:49.069530
1079 11:05:49.069617 Set Vref, RX VrefLevel [Byte0]: 45
1080 11:05:49.072894 [Byte1]: 45
1081 11:05:49.076707
1082 11:05:49.076778 Set Vref, RX VrefLevel [Byte0]: 46
1083 11:05:49.079916 [Byte1]: 46
1084 11:05:49.084144
1085 11:05:49.084213 Set Vref, RX VrefLevel [Byte0]: 47
1086 11:05:49.087814 [Byte1]: 47
1087 11:05:49.092053
1088 11:05:49.092121 Set Vref, RX VrefLevel [Byte0]: 48
1089 11:05:49.095273 [Byte1]: 48
1090 11:05:49.099675
1091 11:05:49.099745 Set Vref, RX VrefLevel [Byte0]: 49
1092 11:05:49.103102 [Byte1]: 49
1093 11:05:49.107120
1094 11:05:49.107193 Set Vref, RX VrefLevel [Byte0]: 50
1095 11:05:49.110453 [Byte1]: 50
1096 11:05:49.114891
1097 11:05:49.114976 Set Vref, RX VrefLevel [Byte0]: 51
1098 11:05:49.117826 [Byte1]: 51
1099 11:05:49.122206
1100 11:05:49.122292 Set Vref, RX VrefLevel [Byte0]: 52
1101 11:05:49.125522 [Byte1]: 52
1102 11:05:49.129743
1103 11:05:49.129828 Set Vref, RX VrefLevel [Byte0]: 53
1104 11:05:49.133319 [Byte1]: 53
1105 11:05:49.137428
1106 11:05:49.137514 Set Vref, RX VrefLevel [Byte0]: 54
1107 11:05:49.140673 [Byte1]: 54
1108 11:05:49.144999
1109 11:05:49.145084 Set Vref, RX VrefLevel [Byte0]: 55
1110 11:05:49.148208 [Byte1]: 55
1111 11:05:49.152719
1112 11:05:49.152804 Set Vref, RX VrefLevel [Byte0]: 56
1113 11:05:49.155838 [Byte1]: 56
1114 11:05:49.160385
1115 11:05:49.160470 Set Vref, RX VrefLevel [Byte0]: 57
1116 11:05:49.163743 [Byte1]: 57
1117 11:05:49.168100
1118 11:05:49.168185 Set Vref, RX VrefLevel [Byte0]: 58
1119 11:05:49.171390 [Byte1]: 58
1120 11:05:49.175544
1121 11:05:49.175629 Set Vref, RX VrefLevel [Byte0]: 59
1122 11:05:49.178673 [Byte1]: 59
1123 11:05:49.183042
1124 11:05:49.183128 Set Vref, RX VrefLevel [Byte0]: 60
1125 11:05:49.186230 [Byte1]: 60
1126 11:05:49.190594
1127 11:05:49.190678 Set Vref, RX VrefLevel [Byte0]: 61
1128 11:05:49.193925 [Byte1]: 61
1129 11:05:49.198221
1130 11:05:49.198305 Set Vref, RX VrefLevel [Byte0]: 62
1131 11:05:49.201389 [Byte1]: 62
1132 11:05:49.206010
1133 11:05:49.206095 Set Vref, RX VrefLevel [Byte0]: 63
1134 11:05:49.209158 [Byte1]: 63
1135 11:05:49.213587
1136 11:05:49.213670 Set Vref, RX VrefLevel [Byte0]: 64
1137 11:05:49.216971 [Byte1]: 64
1138 11:05:49.221549
1139 11:05:49.221634 Set Vref, RX VrefLevel [Byte0]: 65
1140 11:05:49.224304 [Byte1]: 65
1141 11:05:49.228615
1142 11:05:49.228700 Set Vref, RX VrefLevel [Byte0]: 66
1143 11:05:49.231859 [Byte1]: 66
1144 11:05:49.236511
1145 11:05:49.236595 Set Vref, RX VrefLevel [Byte0]: 67
1146 11:05:49.239699 [Byte1]: 67
1147 11:05:49.243791
1148 11:05:49.243874 Set Vref, RX VrefLevel [Byte0]: 68
1149 11:05:49.247232 [Byte1]: 68
1150 11:05:49.251632
1151 11:05:49.251716 Set Vref, RX VrefLevel [Byte0]: 69
1152 11:05:49.254941 [Byte1]: 69
1153 11:05:49.259075
1154 11:05:49.259159 Set Vref, RX VrefLevel [Byte0]: 70
1155 11:05:49.262286 [Byte1]: 70
1156 11:05:49.266578
1157 11:05:49.266662 Set Vref, RX VrefLevel [Byte0]: 71
1158 11:05:49.269860 [Byte1]: 71
1159 11:05:49.274433
1160 11:05:49.274516 Set Vref, RX VrefLevel [Byte0]: 72
1161 11:05:49.277544 [Byte1]: 72
1162 11:05:49.281723
1163 11:05:49.281807 Set Vref, RX VrefLevel [Byte0]: 73
1164 11:05:49.285107 [Byte1]: 73
1165 11:05:49.289343
1166 11:05:49.289429 Set Vref, RX VrefLevel [Byte0]: 74
1167 11:05:49.292750 [Byte1]: 74
1168 11:05:49.297097
1169 11:05:49.297181 Set Vref, RX VrefLevel [Byte0]: 75
1170 11:05:49.300370 [Byte1]: 75
1171 11:05:49.304575
1172 11:05:49.304659 Set Vref, RX VrefLevel [Byte0]: 76
1173 11:05:49.307730 [Byte1]: 76
1174 11:05:49.312416
1175 11:05:49.312500 Set Vref, RX VrefLevel [Byte0]: 77
1176 11:05:49.315332 [Byte1]: 77
1177 11:05:49.320033
1178 11:05:49.320120 Set Vref, RX VrefLevel [Byte0]: 78
1179 11:05:49.322993 [Byte1]: 78
1180 11:05:49.327629
1181 11:05:49.327713 Final RX Vref Byte 0 = 61 to rank0
1182 11:05:49.330831 Final RX Vref Byte 1 = 61 to rank0
1183 11:05:49.334130 Final RX Vref Byte 0 = 61 to rank1
1184 11:05:49.337489 Final RX Vref Byte 1 = 61 to rank1==
1185 11:05:49.340722 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 11:05:49.344069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 11:05:49.347797 ==
1188 11:05:49.347881 DQS Delay:
1189 11:05:49.347948 DQS0 = 0, DQS1 = 0
1190 11:05:49.350784 DQM Delay:
1191 11:05:49.350868 DQM0 = 93, DQM1 = 83
1192 11:05:49.353999 DQ Delay:
1193 11:05:49.354084 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1194 11:05:49.357723 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1195 11:05:49.361033 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1196 11:05:49.364424 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1197 11:05:49.367547
1198 11:05:49.367630
1199 11:05:49.374226 [DQSOSCAuto] RK0, (LSB)MR18= 0x3935, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1200 11:05:49.377720 CH0 RK0: MR19=606, MR18=3935
1201 11:05:49.384437 CH0_RK0: MR19=0x606, MR18=0x3935, DQSOSC=395, MR23=63, INC=94, DEC=63
1202 11:05:49.384522
1203 11:05:49.387754 ----->DramcWriteLeveling(PI) begin...
1204 11:05:49.387840 ==
1205 11:05:49.391037 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 11:05:49.394380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 11:05:49.394466 ==
1208 11:05:49.397784 Write leveling (Byte 0): 34 => 34
1209 11:05:49.401101 Write leveling (Byte 1): 27 => 27
1210 11:05:49.404416 DramcWriteLeveling(PI) end<-----
1211 11:05:49.404500
1212 11:05:49.404567 ==
1213 11:05:49.407592 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 11:05:49.410805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 11:05:49.410889 ==
1216 11:05:49.414472 [Gating] SW mode calibration
1217 11:05:49.421098 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 11:05:49.427586 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 11:05:49.431182 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 11:05:49.434596 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1221 11:05:49.481630 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1222 11:05:49.481723 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:05:49.482070 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:05:49.482362 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:05:49.482462 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:05:49.482578 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:05:49.482678 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:05:49.482780 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:05:49.483137 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:05:49.483427 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:05:49.486496 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:05:49.486581 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:05:49.493489 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:05:49.496827 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:05:49.500009 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1236 11:05:49.506501 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1237 11:05:49.510083 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:05:49.513352 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:05:49.519856 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:05:49.523483 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:05:49.526555 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:05:49.533365 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:05:49.536945 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:05:49.540051 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1245 11:05:49.546716 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1246 11:05:49.549959 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 11:05:49.553318 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 11:05:49.557044 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 11:05:49.563456 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 11:05:49.566858 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 11:05:49.570089 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 11:05:49.577078 0 10 4 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 1)
1253 11:05:49.580166 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1254 11:05:49.583526 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 11:05:49.590366 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 11:05:49.593617 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 11:05:49.596756 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 11:05:49.603360 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 11:05:49.606791 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 11:05:49.610027 0 11 4 | B1->B0 | 2424 3131 | 1 0 | (0 0) (0 0)
1261 11:05:49.617201 0 11 8 | B1->B0 | 3939 4343 | 0 1 | (0 0) (0 0)
1262 11:05:49.620780 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 11:05:49.624326 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 11:05:49.628423 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 11:05:49.631786 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 11:05:49.638367 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 11:05:49.641911 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 11:05:49.645764 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1269 11:05:49.649137 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1270 11:05:49.655864 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:05:49.659181 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:05:49.662298 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:05:49.669293 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:05:49.672486 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:05:49.676162 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:05:49.682549 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:05:49.686202 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:05:49.689509 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:05:49.696210 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:05:49.699618 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:05:49.702923 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 11:05:49.706214 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 11:05:49.712629 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 11:05:49.716910 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1285 11:05:49.719237 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1286 11:05:49.726234 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 11:05:49.729472 Total UI for P1: 0, mck2ui 16
1288 11:05:49.733045 best dqsien dly found for B0: ( 0, 14, 6)
1289 11:05:49.733123 Total UI for P1: 0, mck2ui 16
1290 11:05:49.739745 best dqsien dly found for B1: ( 0, 14, 8)
1291 11:05:49.742997 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1292 11:05:49.746600 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1293 11:05:49.746685
1294 11:05:49.749713 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1295 11:05:49.752843 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1296 11:05:49.756677 [Gating] SW calibration Done
1297 11:05:49.756763 ==
1298 11:05:49.759858 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 11:05:49.763078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 11:05:49.763164 ==
1301 11:05:49.766165 RX Vref Scan: 0
1302 11:05:49.766249
1303 11:05:49.766316 RX Vref 0 -> 0, step: 1
1304 11:05:49.766380
1305 11:05:49.769796 RX Delay -130 -> 252, step: 16
1306 11:05:49.773141 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1307 11:05:49.779911 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1308 11:05:49.783223 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1309 11:05:49.786640 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1310 11:05:49.789812 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1311 11:05:49.793091 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1312 11:05:49.799762 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1313 11:05:49.802962 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1314 11:05:49.806742 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1315 11:05:49.809629 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1316 11:05:49.813030 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1317 11:05:49.819724 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1318 11:05:49.823064 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1319 11:05:49.826492 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1320 11:05:49.830036 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1321 11:05:49.833074 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
1322 11:05:49.833158 ==
1323 11:05:49.836368 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 11:05:49.843041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 11:05:49.843130 ==
1326 11:05:49.843197 DQS Delay:
1327 11:05:49.846402 DQS0 = 0, DQS1 = 0
1328 11:05:49.846486 DQM Delay:
1329 11:05:49.846552 DQM0 = 89, DQM1 = 79
1330 11:05:49.849817 DQ Delay:
1331 11:05:49.853476 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1332 11:05:49.856776 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1333 11:05:49.859914 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1334 11:05:49.863256 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =77
1335 11:05:49.863340
1336 11:05:49.863406
1337 11:05:49.863466 ==
1338 11:05:49.866819 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 11:05:49.869913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 11:05:49.870004 ==
1341 11:05:49.870070
1342 11:05:49.870131
1343 11:05:49.873124 TX Vref Scan disable
1344 11:05:49.876443 == TX Byte 0 ==
1345 11:05:49.880139 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1346 11:05:49.883250 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1347 11:05:49.883335 == TX Byte 1 ==
1348 11:05:49.890286 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1349 11:05:49.893586 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1350 11:05:49.893671 ==
1351 11:05:49.896941 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 11:05:49.900193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 11:05:49.900277 ==
1354 11:05:49.916514 TX Vref=22, minBit 8, minWin=27, winSum=448
1355 11:05:49.918333 TX Vref=24, minBit 8, minWin=27, winSum=451
1356 11:05:49.921737 TX Vref=26, minBit 8, minWin=27, winSum=452
1357 11:05:49.925089 TX Vref=28, minBit 4, minWin=28, winSum=456
1358 11:05:49.928672 TX Vref=30, minBit 8, minWin=27, winSum=457
1359 11:05:49.932010 TX Vref=32, minBit 4, minWin=28, winSum=458
1360 11:05:49.938896 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 32
1361 11:05:49.938983
1362 11:05:49.942157 Final TX Range 1 Vref 32
1363 11:05:49.942251
1364 11:05:49.942314 ==
1365 11:05:49.945149 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 11:05:49.948724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 11:05:49.948804 ==
1368 11:05:49.948867
1369 11:05:49.948926
1370 11:05:49.952035 TX Vref Scan disable
1371 11:05:49.955015 == TX Byte 0 ==
1372 11:05:49.958605 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1373 11:05:49.961844 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1374 11:05:49.965202 == TX Byte 1 ==
1375 11:05:49.968569 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1376 11:05:49.971788 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1377 11:05:49.975462
1378 11:05:49.975544 [DATLAT]
1379 11:05:49.975608 Freq=800, CH0 RK1
1380 11:05:49.975669
1381 11:05:49.978748 DATLAT Default: 0xa
1382 11:05:49.978830 0, 0xFFFF, sum = 0
1383 11:05:49.982136 1, 0xFFFF, sum = 0
1384 11:05:49.982220 2, 0xFFFF, sum = 0
1385 11:05:49.985327 3, 0xFFFF, sum = 0
1386 11:05:49.985411 4, 0xFFFF, sum = 0
1387 11:05:49.988495 5, 0xFFFF, sum = 0
1388 11:05:49.991805 6, 0xFFFF, sum = 0
1389 11:05:49.991888 7, 0xFFFF, sum = 0
1390 11:05:49.995087 8, 0xFFFF, sum = 0
1391 11:05:49.995171 9, 0x0, sum = 1
1392 11:05:49.995238 10, 0x0, sum = 2
1393 11:05:49.998406 11, 0x0, sum = 3
1394 11:05:49.998492 12, 0x0, sum = 4
1395 11:05:50.002152 best_step = 10
1396 11:05:50.002234
1397 11:05:50.002298 ==
1398 11:05:50.005420 Dram Type= 6, Freq= 0, CH_0, rank 1
1399 11:05:50.008664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 11:05:50.008747 ==
1401 11:05:50.011957 RX Vref Scan: 0
1402 11:05:50.012071
1403 11:05:50.012196 RX Vref 0 -> 0, step: 1
1404 11:05:50.012324
1405 11:05:50.015286 RX Delay -79 -> 252, step: 8
1406 11:05:50.021910 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1407 11:05:50.025307 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1408 11:05:50.028671 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1409 11:05:50.031976 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1410 11:05:50.035347 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1411 11:05:50.042050 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1412 11:05:50.045133 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1413 11:05:50.048665 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1414 11:05:50.052123 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1415 11:05:50.055206 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1416 11:05:50.062248 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1417 11:05:50.065578 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1418 11:05:50.068874 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1419 11:05:50.072326 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1420 11:05:50.075579 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1421 11:05:50.081856 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1422 11:05:50.081985 ==
1423 11:05:50.085696 Dram Type= 6, Freq= 0, CH_0, rank 1
1424 11:05:50.088556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 11:05:50.088639 ==
1426 11:05:50.088704 DQS Delay:
1427 11:05:50.092174 DQS0 = 0, DQS1 = 0
1428 11:05:50.092256 DQM Delay:
1429 11:05:50.095396 DQM0 = 90, DQM1 = 81
1430 11:05:50.095478 DQ Delay:
1431 11:05:50.098709 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1432 11:05:50.101881 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1433 11:05:50.105563 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1434 11:05:50.108787 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1435 11:05:50.108870
1436 11:05:50.108934
1437 11:05:50.115222 [DQSOSCAuto] RK1, (LSB)MR18= 0x441d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1438 11:05:50.118634 CH0 RK1: MR19=606, MR18=441D
1439 11:05:50.125314 CH0_RK1: MR19=0x606, MR18=0x441D, DQSOSC=392, MR23=63, INC=96, DEC=64
1440 11:05:50.128665 [RxdqsGatingPostProcess] freq 800
1441 11:05:50.135572 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1442 11:05:50.138914 Pre-setting of DQS Precalculation
1443 11:05:50.142160 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1444 11:05:50.142245 ==
1445 11:05:50.145290 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 11:05:50.148691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 11:05:50.148776 ==
1448 11:05:50.155239 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1449 11:05:50.162468 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1450 11:05:50.170327 [CA 0] Center 36 (6~67) winsize 62
1451 11:05:50.173485 [CA 1] Center 36 (6~67) winsize 62
1452 11:05:50.176844 [CA 2] Center 34 (4~65) winsize 62
1453 11:05:50.180126 [CA 3] Center 34 (3~65) winsize 63
1454 11:05:50.183823 [CA 4] Center 34 (4~65) winsize 62
1455 11:05:50.187114 [CA 5] Center 33 (3~64) winsize 62
1456 11:05:50.187198
1457 11:05:50.190531 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1458 11:05:50.190615
1459 11:05:50.193796 [CATrainingPosCal] consider 1 rank data
1460 11:05:50.197074 u2DelayCellTimex100 = 270/100 ps
1461 11:05:50.200309 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1462 11:05:50.203810 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1463 11:05:50.210317 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1464 11:05:50.213641 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1465 11:05:50.217235 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1466 11:05:50.220483 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1467 11:05:50.220591
1468 11:05:50.223846 CA PerBit enable=1, Macro0, CA PI delay=33
1469 11:05:50.223947
1470 11:05:50.226991 [CBTSetCACLKResult] CA Dly = 33
1471 11:05:50.227075 CS Dly: 5 (0~36)
1472 11:05:50.227142 ==
1473 11:05:50.230247 Dram Type= 6, Freq= 0, CH_1, rank 1
1474 11:05:50.237219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 11:05:50.237305 ==
1476 11:05:50.240370 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1477 11:05:50.247061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1478 11:05:50.256540 [CA 0] Center 37 (6~68) winsize 63
1479 11:05:50.259587 [CA 1] Center 37 (6~68) winsize 63
1480 11:05:50.263431 [CA 2] Center 35 (5~66) winsize 62
1481 11:05:50.266427 [CA 3] Center 34 (4~65) winsize 62
1482 11:05:50.269890 [CA 4] Center 34 (4~65) winsize 62
1483 11:05:50.273216 [CA 5] Center 34 (4~64) winsize 61
1484 11:05:50.273300
1485 11:05:50.276511 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1486 11:05:50.276596
1487 11:05:50.279815 [CATrainingPosCal] consider 2 rank data
1488 11:05:50.283632 u2DelayCellTimex100 = 270/100 ps
1489 11:05:50.287668 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1490 11:05:50.291432 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1491 11:05:50.294767 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1492 11:05:50.298529 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1493 11:05:50.302323 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1494 11:05:50.306106 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1495 11:05:50.306190
1496 11:05:50.309587 CA PerBit enable=1, Macro0, CA PI delay=34
1497 11:05:50.309685
1498 11:05:50.313821 [CBTSetCACLKResult] CA Dly = 34
1499 11:05:50.313921 CS Dly: 6 (0~38)
1500 11:05:50.314028
1501 11:05:50.317599 ----->DramcWriteLeveling(PI) begin...
1502 11:05:50.317685 ==
1503 11:05:50.320799 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 11:05:50.324142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 11:05:50.327543 ==
1506 11:05:50.327628 Write leveling (Byte 0): 26 => 26
1507 11:05:50.330825 Write leveling (Byte 1): 29 => 29
1508 11:05:50.333992 DramcWriteLeveling(PI) end<-----
1509 11:05:50.334092
1510 11:05:50.334188 ==
1511 11:05:50.337615 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 11:05:50.344119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1513 11:05:50.344204 ==
1514 11:05:50.344271 [Gating] SW mode calibration
1515 11:05:50.354076 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1516 11:05:50.357615 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1517 11:05:50.360729 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1518 11:05:50.367722 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1519 11:05:50.371049 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:05:50.374487 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:05:50.381126 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:05:50.384485 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:05:50.387891 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:05:50.394274 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:05:50.397890 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:05:50.401237 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:05:50.407929 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:05:50.411154 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:05:50.414720 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:05:50.418244 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:05:50.424698 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:05:50.428035 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:05:50.430837 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1534 11:05:50.437980 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1535 11:05:50.441420 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1536 11:05:50.444487 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:05:50.451039 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:05:50.454597 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:05:50.457934 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:05:50.464354 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:05:50.467968 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:05:50.471273 0 9 4 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
1543 11:05:50.478008 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 11:05:50.481236 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 11:05:50.484715 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 11:05:50.488081 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 11:05:50.494604 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 11:05:50.498154 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 11:05:50.501328 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1550 11:05:50.508144 0 10 4 | B1->B0 | 2f2f 2d2d | 0 0 | (0 1) (1 1)
1551 11:05:50.511432 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 11:05:50.514581 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 11:05:50.521099 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 11:05:50.525238 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 11:05:50.528163 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 11:05:50.534505 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 11:05:50.538208 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1558 11:05:50.541584 0 11 4 | B1->B0 | 2d2d 3838 | 0 0 | (0 0) (0 0)
1559 11:05:50.548304 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 11:05:50.551508 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 11:05:50.555047 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 11:05:50.561600 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 11:05:50.564788 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 11:05:50.568351 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 11:05:50.571474 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1566 11:05:50.578367 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1567 11:05:50.581571 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:05:50.584746 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:05:50.591349 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:05:50.594700 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:05:50.598226 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:05:50.604593 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:05:50.608253 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:05:50.611533 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:05:50.618420 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:05:50.621535 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:05:50.624898 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:05:50.631473 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:05:50.634841 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:05:50.637934 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 11:05:50.644735 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 11:05:50.648164 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1583 11:05:50.651591 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 11:05:50.654851 Total UI for P1: 0, mck2ui 16
1585 11:05:50.658347 best dqsien dly found for B0: ( 0, 14, 4)
1586 11:05:50.661693 Total UI for P1: 0, mck2ui 16
1587 11:05:50.664846 best dqsien dly found for B1: ( 0, 14, 4)
1588 11:05:50.668298 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1589 11:05:50.671518 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1590 11:05:50.671603
1591 11:05:50.674782 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1592 11:05:50.678256 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1593 11:05:50.681768 [Gating] SW calibration Done
1594 11:05:50.681851 ==
1595 11:05:50.684956 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 11:05:50.691508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 11:05:50.691593 ==
1598 11:05:50.691660 RX Vref Scan: 0
1599 11:05:50.691768
1600 11:05:50.694909 RX Vref 0 -> 0, step: 1
1601 11:05:50.694993
1602 11:05:50.698165 RX Delay -130 -> 252, step: 16
1603 11:05:50.701462 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1604 11:05:50.704934 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1605 11:05:50.708334 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1606 11:05:50.711587 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1607 11:05:50.718391 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1608 11:05:50.721716 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1609 11:05:50.724788 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1610 11:05:50.728204 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1611 11:05:50.731612 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1612 11:05:50.738614 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1613 11:05:50.741925 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1614 11:05:50.745087 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1615 11:05:50.748376 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1616 11:05:50.751867 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1617 11:05:50.758472 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1618 11:05:50.761924 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1619 11:05:50.762029 ==
1620 11:05:50.765419 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 11:05:50.768524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 11:05:50.768609 ==
1623 11:05:50.768707 DQS Delay:
1624 11:05:50.772005 DQS0 = 0, DQS1 = 0
1625 11:05:50.772088 DQM Delay:
1626 11:05:50.775616 DQM0 = 88, DQM1 = 81
1627 11:05:50.775700 DQ Delay:
1628 11:05:50.778791 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1629 11:05:50.782047 DQ4 =93, DQ5 =93, DQ6 =101, DQ7 =85
1630 11:05:50.785888 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1631 11:05:50.788806 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1632 11:05:50.788890
1633 11:05:50.788956
1634 11:05:50.789016 ==
1635 11:05:50.792009 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 11:05:50.795274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 11:05:50.798662 ==
1638 11:05:50.798765
1639 11:05:50.798843
1640 11:05:50.798905 TX Vref Scan disable
1641 11:05:50.802055 == TX Byte 0 ==
1642 11:05:50.805467 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1643 11:05:50.809046 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1644 11:05:50.812420 == TX Byte 1 ==
1645 11:05:50.815686 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1646 11:05:50.818893 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1647 11:05:50.818977 ==
1648 11:05:50.822415 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 11:05:50.828934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 11:05:50.829019 ==
1651 11:05:50.841036 TX Vref=22, minBit 8, minWin=27, winSum=450
1652 11:05:50.844266 TX Vref=24, minBit 10, minWin=27, winSum=455
1653 11:05:50.847641 TX Vref=26, minBit 15, minWin=27, winSum=456
1654 11:05:50.850906 TX Vref=28, minBit 15, minWin=27, winSum=457
1655 11:05:50.854255 TX Vref=30, minBit 15, minWin=27, winSum=457
1656 11:05:50.861247 TX Vref=32, minBit 9, minWin=27, winSum=456
1657 11:05:50.865118 [TxChooseVref] Worse bit 15, Min win 27, Win sum 457, Final Vref 28
1658 11:05:50.865229
1659 11:05:50.868663 Final TX Range 1 Vref 28
1660 11:05:50.868748
1661 11:05:50.868867 ==
1662 11:05:50.871744 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 11:05:50.875378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1664 11:05:50.875463 ==
1665 11:05:50.875529
1666 11:05:50.875589
1667 11:05:50.878502 TX Vref Scan disable
1668 11:05:50.882224 == TX Byte 0 ==
1669 11:05:50.885245 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1670 11:05:50.888486 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1671 11:05:50.892095 == TX Byte 1 ==
1672 11:05:50.895208 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1673 11:05:50.898520 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1674 11:05:50.898605
1675 11:05:50.901717 [DATLAT]
1676 11:05:50.901801 Freq=800, CH1 RK0
1677 11:05:50.901867
1678 11:05:50.905122 DATLAT Default: 0xa
1679 11:05:50.905206 0, 0xFFFF, sum = 0
1680 11:05:50.908784 1, 0xFFFF, sum = 0
1681 11:05:50.908869 2, 0xFFFF, sum = 0
1682 11:05:50.911853 3, 0xFFFF, sum = 0
1683 11:05:50.911965 4, 0xFFFF, sum = 0
1684 11:05:50.915215 5, 0xFFFF, sum = 0
1685 11:05:50.915330 6, 0xFFFF, sum = 0
1686 11:05:50.918563 7, 0xFFFF, sum = 0
1687 11:05:50.918670 8, 0xFFFF, sum = 0
1688 11:05:50.921844 9, 0x0, sum = 1
1689 11:05:50.921977 10, 0x0, sum = 2
1690 11:05:50.925027 11, 0x0, sum = 3
1691 11:05:50.925111 12, 0x0, sum = 4
1692 11:05:50.928711 best_step = 10
1693 11:05:50.928794
1694 11:05:50.928861 ==
1695 11:05:50.932106 Dram Type= 6, Freq= 0, CH_1, rank 0
1696 11:05:50.935213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1697 11:05:50.935323 ==
1698 11:05:50.938564 RX Vref Scan: 1
1699 11:05:50.938664
1700 11:05:50.938746 Set Vref Range= 32 -> 127
1701 11:05:50.938808
1702 11:05:50.941814 RX Vref 32 -> 127, step: 1
1703 11:05:50.941923
1704 11:05:50.945347 RX Delay -95 -> 252, step: 8
1705 11:05:50.945432
1706 11:05:50.948641 Set Vref, RX VrefLevel [Byte0]: 32
1707 11:05:50.952086 [Byte1]: 32
1708 11:05:50.952172
1709 11:05:50.955481 Set Vref, RX VrefLevel [Byte0]: 33
1710 11:05:50.958750 [Byte1]: 33
1711 11:05:50.958844
1712 11:05:50.962078 Set Vref, RX VrefLevel [Byte0]: 34
1713 11:05:50.965547 [Byte1]: 34
1714 11:05:50.969325
1715 11:05:50.969409 Set Vref, RX VrefLevel [Byte0]: 35
1716 11:05:50.972411 [Byte1]: 35
1717 11:05:50.977106
1718 11:05:50.977240 Set Vref, RX VrefLevel [Byte0]: 36
1719 11:05:50.980129 [Byte1]: 36
1720 11:05:50.984513
1721 11:05:50.984604 Set Vref, RX VrefLevel [Byte0]: 37
1722 11:05:50.987638 [Byte1]: 37
1723 11:05:50.991803
1724 11:05:50.991889 Set Vref, RX VrefLevel [Byte0]: 38
1725 11:05:50.995201 [Byte1]: 38
1726 11:05:50.999777
1727 11:05:50.999860 Set Vref, RX VrefLevel [Byte0]: 39
1728 11:05:51.003123 [Byte1]: 39
1729 11:05:51.007240
1730 11:05:51.007341 Set Vref, RX VrefLevel [Byte0]: 40
1731 11:05:51.010475 [Byte1]: 40
1732 11:05:51.015033
1733 11:05:51.015118 Set Vref, RX VrefLevel [Byte0]: 41
1734 11:05:51.018299 [Byte1]: 41
1735 11:05:51.022542
1736 11:05:51.022643 Set Vref, RX VrefLevel [Byte0]: 42
1737 11:05:51.025787 [Byte1]: 42
1738 11:05:51.029812
1739 11:05:51.029898 Set Vref, RX VrefLevel [Byte0]: 43
1740 11:05:51.033181 [Byte1]: 43
1741 11:05:51.037428
1742 11:05:51.037513 Set Vref, RX VrefLevel [Byte0]: 44
1743 11:05:51.041038 [Byte1]: 44
1744 11:05:51.045305
1745 11:05:51.045389 Set Vref, RX VrefLevel [Byte0]: 45
1746 11:05:51.048562 [Byte1]: 45
1747 11:05:51.052729
1748 11:05:51.052816 Set Vref, RX VrefLevel [Byte0]: 46
1749 11:05:51.056261 [Byte1]: 46
1750 11:05:51.060417
1751 11:05:51.060500 Set Vref, RX VrefLevel [Byte0]: 47
1752 11:05:51.063566 [Byte1]: 47
1753 11:05:51.067996
1754 11:05:51.068097 Set Vref, RX VrefLevel [Byte0]: 48
1755 11:05:51.071389 [Byte1]: 48
1756 11:05:51.075436
1757 11:05:51.075522 Set Vref, RX VrefLevel [Byte0]: 49
1758 11:05:51.078787 [Byte1]: 49
1759 11:05:51.083116
1760 11:05:51.083216 Set Vref, RX VrefLevel [Byte0]: 50
1761 11:05:51.086265 [Byte1]: 50
1762 11:05:51.090920
1763 11:05:51.091006 Set Vref, RX VrefLevel [Byte0]: 51
1764 11:05:51.093795 [Byte1]: 51
1765 11:05:51.098281
1766 11:05:51.098382 Set Vref, RX VrefLevel [Byte0]: 52
1767 11:05:51.101543 [Byte1]: 52
1768 11:05:51.105934
1769 11:05:51.106074 Set Vref, RX VrefLevel [Byte0]: 53
1770 11:05:51.109112 [Byte1]: 53
1771 11:05:51.113692
1772 11:05:51.113778 Set Vref, RX VrefLevel [Byte0]: 54
1773 11:05:51.117004 [Byte1]: 54
1774 11:05:51.121086
1775 11:05:51.121170 Set Vref, RX VrefLevel [Byte0]: 55
1776 11:05:51.124530 [Byte1]: 55
1777 11:05:51.128731
1778 11:05:51.128815 Set Vref, RX VrefLevel [Byte0]: 56
1779 11:05:51.132025 [Byte1]: 56
1780 11:05:51.136688
1781 11:05:51.136772 Set Vref, RX VrefLevel [Byte0]: 57
1782 11:05:51.139528 [Byte1]: 57
1783 11:05:51.143970
1784 11:05:51.144071 Set Vref, RX VrefLevel [Byte0]: 58
1785 11:05:51.147266 [Byte1]: 58
1786 11:05:51.151562
1787 11:05:51.151649 Set Vref, RX VrefLevel [Byte0]: 59
1788 11:05:51.154690 [Byte1]: 59
1789 11:05:51.158963
1790 11:05:51.159048 Set Vref, RX VrefLevel [Byte0]: 60
1791 11:05:51.162252 [Byte1]: 60
1792 11:05:51.166820
1793 11:05:51.166904 Set Vref, RX VrefLevel [Byte0]: 61
1794 11:05:51.170147 [Byte1]: 61
1795 11:05:51.174367
1796 11:05:51.174452 Set Vref, RX VrefLevel [Byte0]: 62
1797 11:05:51.177711 [Byte1]: 62
1798 11:05:51.181805
1799 11:05:51.181910 Set Vref, RX VrefLevel [Byte0]: 63
1800 11:05:51.185321 [Byte1]: 63
1801 11:05:51.189714
1802 11:05:51.189802 Set Vref, RX VrefLevel [Byte0]: 64
1803 11:05:51.192829 [Byte1]: 64
1804 11:05:51.197342
1805 11:05:51.197428 Set Vref, RX VrefLevel [Byte0]: 65
1806 11:05:51.200499 [Byte1]: 65
1807 11:05:51.204696
1808 11:05:51.204797 Set Vref, RX VrefLevel [Byte0]: 66
1809 11:05:51.207871 [Byte1]: 66
1810 11:05:51.212267
1811 11:05:51.212377 Set Vref, RX VrefLevel [Byte0]: 67
1812 11:05:51.215530 [Byte1]: 67
1813 11:05:51.219805
1814 11:05:51.219890 Set Vref, RX VrefLevel [Byte0]: 68
1815 11:05:51.223398 [Byte1]: 68
1816 11:05:51.227491
1817 11:05:51.227575 Set Vref, RX VrefLevel [Byte0]: 69
1818 11:05:51.230753 [Byte1]: 69
1819 11:05:51.235093
1820 11:05:51.235178 Set Vref, RX VrefLevel [Byte0]: 70
1821 11:05:51.238662 [Byte1]: 70
1822 11:05:51.242987
1823 11:05:51.243071 Set Vref, RX VrefLevel [Byte0]: 71
1824 11:05:51.246224 [Byte1]: 71
1825 11:05:51.250402
1826 11:05:51.250524 Set Vref, RX VrefLevel [Byte0]: 72
1827 11:05:51.253546 [Byte1]: 72
1828 11:05:51.257798
1829 11:05:51.257884 Set Vref, RX VrefLevel [Byte0]: 73
1830 11:05:51.261400 [Byte1]: 73
1831 11:05:51.265276
1832 11:05:51.265382 Set Vref, RX VrefLevel [Byte0]: 74
1833 11:05:51.268932 [Byte1]: 74
1834 11:05:51.273276
1835 11:05:51.273360 Set Vref, RX VrefLevel [Byte0]: 75
1836 11:05:51.276592 [Byte1]: 75
1837 11:05:51.280833
1838 11:05:51.280917 Set Vref, RX VrefLevel [Byte0]: 76
1839 11:05:51.284052 [Byte1]: 76
1840 11:05:51.288354
1841 11:05:51.288452 Set Vref, RX VrefLevel [Byte0]: 77
1842 11:05:51.291839 [Byte1]: 77
1843 11:05:51.295730
1844 11:05:51.295855 Set Vref, RX VrefLevel [Byte0]: 78
1845 11:05:51.299037 [Byte1]: 78
1846 11:05:51.303929
1847 11:05:51.304040 Final RX Vref Byte 0 = 53 to rank0
1848 11:05:51.306679 Final RX Vref Byte 1 = 62 to rank0
1849 11:05:51.310483 Final RX Vref Byte 0 = 53 to rank1
1850 11:05:51.313696 Final RX Vref Byte 1 = 62 to rank1==
1851 11:05:51.316982 Dram Type= 6, Freq= 0, CH_1, rank 0
1852 11:05:51.323490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1853 11:05:51.323576 ==
1854 11:05:51.323643 DQS Delay:
1855 11:05:51.323743 DQS0 = 0, DQS1 = 0
1856 11:05:51.327100 DQM Delay:
1857 11:05:51.327184 DQM0 = 91, DQM1 = 82
1858 11:05:51.330368 DQ Delay:
1859 11:05:51.333321 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
1860 11:05:51.336803 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
1861 11:05:51.336932 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =80
1862 11:05:51.343761 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1863 11:05:51.343845
1864 11:05:51.343912
1865 11:05:51.350134 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1866 11:05:51.353393 CH1 RK0: MR19=606, MR18=2C49
1867 11:05:51.360088 CH1_RK0: MR19=0x606, MR18=0x2C49, DQSOSC=391, MR23=63, INC=96, DEC=64
1868 11:05:51.360195
1869 11:05:51.363226 ----->DramcWriteLeveling(PI) begin...
1870 11:05:51.363330 ==
1871 11:05:51.367070 Dram Type= 6, Freq= 0, CH_1, rank 1
1872 11:05:51.370136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1873 11:05:51.370225 ==
1874 11:05:51.373394 Write leveling (Byte 0): 27 => 27
1875 11:05:51.376752 Write leveling (Byte 1): 32 => 32
1876 11:05:51.380161 DramcWriteLeveling(PI) end<-----
1877 11:05:51.380269
1878 11:05:51.380372 ==
1879 11:05:51.383140 Dram Type= 6, Freq= 0, CH_1, rank 1
1880 11:05:51.386490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1881 11:05:51.386564 ==
1882 11:05:51.390249 [Gating] SW mode calibration
1883 11:05:51.396862 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1884 11:05:51.403396 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1885 11:05:51.406688 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1886 11:05:51.410150 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1887 11:05:51.416750 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:05:51.420014 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:05:51.423128 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:05:51.429788 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:05:51.433349 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:05:51.436569 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:05:51.443726 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:05:51.446819 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:05:51.450136 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:05:51.456624 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:05:51.459900 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:05:51.463648 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 11:05:51.470161 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 11:05:51.473629 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 11:05:51.476973 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:05:51.480320 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1903 11:05:51.486703 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 11:05:51.490359 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:05:51.493736 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:05:51.500039 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:05:51.503650 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:05:51.506739 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 11:05:51.513509 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 11:05:51.516710 0 9 4 | B1->B0 | 2424 2323 | 1 1 | (1 1) (1 1)
1911 11:05:51.520364 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 11:05:51.526965 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 11:05:51.530239 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 11:05:51.533511 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 11:05:51.540392 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 11:05:51.543686 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 11:05:51.547040 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 11:05:51.553560 0 10 4 | B1->B0 | 2828 2f2f | 1 0 | (1 0) (0 0)
1919 11:05:51.556768 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 11:05:51.560029 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 11:05:51.563308 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 11:05:51.570200 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 11:05:51.573380 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 11:05:51.576901 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 11:05:51.583453 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 11:05:51.586752 0 11 4 | B1->B0 | 3030 3232 | 0 0 | (0 0) (0 0)
1927 11:05:51.590053 0 11 8 | B1->B0 | 4040 4444 | 0 1 | (0 0) (0 0)
1928 11:05:51.597160 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 11:05:51.600535 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 11:05:51.603458 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 11:05:51.610441 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 11:05:51.613503 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 11:05:51.617239 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 11:05:51.623932 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1935 11:05:51.627240 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 11:05:51.630679 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 11:05:51.637365 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 11:05:51.640340 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 11:05:51.643786 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 11:05:51.647129 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 11:05:51.653861 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 11:05:51.657137 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 11:05:51.660772 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 11:05:51.667190 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 11:05:51.670648 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 11:05:51.674027 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 11:05:51.680486 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 11:05:51.683914 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 11:05:51.687133 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 11:05:51.693749 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1951 11:05:51.697077 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1952 11:05:51.700518 Total UI for P1: 0, mck2ui 16
1953 11:05:51.703807 best dqsien dly found for B1: ( 0, 14, 4)
1954 11:05:51.707233 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1955 11:05:51.710548 Total UI for P1: 0, mck2ui 16
1956 11:05:51.714035 best dqsien dly found for B0: ( 0, 14, 8)
1957 11:05:51.717449 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1958 11:05:51.720650 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1959 11:05:51.720762
1960 11:05:51.724074 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1961 11:05:51.730678 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1962 11:05:51.730763 [Gating] SW calibration Done
1963 11:05:51.730829 ==
1964 11:05:51.734203 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 11:05:51.740417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 11:05:51.740499 ==
1967 11:05:51.740576 RX Vref Scan: 0
1968 11:05:51.740677
1969 11:05:51.743737 RX Vref 0 -> 0, step: 1
1970 11:05:51.743836
1971 11:05:51.747267 RX Delay -130 -> 252, step: 16
1972 11:05:51.750624 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1973 11:05:51.753805 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1974 11:05:51.757039 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1975 11:05:51.760851 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1976 11:05:51.767330 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1977 11:05:51.770720 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1978 11:05:51.774062 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1979 11:05:51.777263 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1980 11:05:51.780313 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1981 11:05:51.787241 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1982 11:05:51.790653 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1983 11:05:51.794113 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1984 11:05:51.797457 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1985 11:05:51.800645 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1986 11:05:51.807182 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1987 11:05:51.810407 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1988 11:05:51.810482 ==
1989 11:05:51.813930 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 11:05:51.817484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 11:05:51.817587 ==
1992 11:05:51.820761 DQS Delay:
1993 11:05:51.820868 DQS0 = 0, DQS1 = 0
1994 11:05:51.820995 DQM Delay:
1995 11:05:51.823864 DQM0 = 89, DQM1 = 83
1996 11:05:51.823971 DQ Delay:
1997 11:05:51.827489 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1998 11:05:51.830746 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1999 11:05:51.834045 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
2000 11:05:51.837379 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
2001 11:05:51.837484
2002 11:05:51.837575
2003 11:05:51.837668 ==
2004 11:05:51.840821 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 11:05:51.847514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 11:05:51.847591 ==
2007 11:05:51.847660
2008 11:05:51.847741
2009 11:05:51.847812 TX Vref Scan disable
2010 11:05:51.850705 == TX Byte 0 ==
2011 11:05:51.854145 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2012 11:05:51.857721 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2013 11:05:51.860857 == TX Byte 1 ==
2014 11:05:51.864015 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2015 11:05:51.867694 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2016 11:05:51.870826 ==
2017 11:05:51.874081 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 11:05:51.877279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 11:05:51.877379 ==
2020 11:05:51.890414 TX Vref=22, minBit 8, minWin=27, winSum=449
2021 11:05:51.893593 TX Vref=24, minBit 8, minWin=27, winSum=451
2022 11:05:51.896941 TX Vref=26, minBit 13, minWin=27, winSum=457
2023 11:05:51.900550 TX Vref=28, minBit 13, minWin=27, winSum=456
2024 11:05:51.903780 TX Vref=30, minBit 15, minWin=27, winSum=458
2025 11:05:51.910594 TX Vref=32, minBit 8, minWin=28, winSum=459
2026 11:05:51.913773 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 32
2027 11:05:51.913857
2028 11:05:51.917047 Final TX Range 1 Vref 32
2029 11:05:51.917131
2030 11:05:51.917196 ==
2031 11:05:51.920069 Dram Type= 6, Freq= 0, CH_1, rank 1
2032 11:05:51.923714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2033 11:05:51.923800 ==
2034 11:05:51.926870
2035 11:05:51.926949
2036 11:05:51.927013 TX Vref Scan disable
2037 11:05:51.930634 == TX Byte 0 ==
2038 11:05:51.933539 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2039 11:05:51.937107 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2040 11:05:51.940485 == TX Byte 1 ==
2041 11:05:51.943827 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2042 11:05:51.947072 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2043 11:05:51.950729
2044 11:05:51.950812 [DATLAT]
2045 11:05:51.950880 Freq=800, CH1 RK1
2046 11:05:51.950943
2047 11:05:51.953997 DATLAT Default: 0xa
2048 11:05:51.954072 0, 0xFFFF, sum = 0
2049 11:05:51.957331 1, 0xFFFF, sum = 0
2050 11:05:51.957408 2, 0xFFFF, sum = 0
2051 11:05:51.960668 3, 0xFFFF, sum = 0
2052 11:05:51.960745 4, 0xFFFF, sum = 0
2053 11:05:51.963961 5, 0xFFFF, sum = 0
2054 11:05:51.964072 6, 0xFFFF, sum = 0
2055 11:05:51.967013 7, 0xFFFF, sum = 0
2056 11:05:51.970318 8, 0xFFFF, sum = 0
2057 11:05:51.970400 9, 0x0, sum = 1
2058 11:05:51.970469 10, 0x0, sum = 2
2059 11:05:51.973992 11, 0x0, sum = 3
2060 11:05:51.974072 12, 0x0, sum = 4
2061 11:05:51.977124 best_step = 10
2062 11:05:51.977201
2063 11:05:51.977282 ==
2064 11:05:51.980508 Dram Type= 6, Freq= 0, CH_1, rank 1
2065 11:05:51.983814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2066 11:05:51.983929 ==
2067 11:05:51.987231 RX Vref Scan: 0
2068 11:05:51.987305
2069 11:05:51.987366 RX Vref 0 -> 0, step: 1
2070 11:05:51.987425
2071 11:05:51.990405 RX Delay -79 -> 252, step: 8
2072 11:05:51.997257 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2073 11:05:52.000481 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2074 11:05:52.003844 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2075 11:05:52.007161 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
2076 11:05:52.010427 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2077 11:05:52.013823 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2078 11:05:52.020452 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2079 11:05:52.024021 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2080 11:05:52.027148 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2081 11:05:52.030663 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2082 11:05:52.033887 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2083 11:05:52.040382 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2084 11:05:52.044202 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2085 11:05:52.047238 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2086 11:05:52.050679 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2087 11:05:52.054054 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2088 11:05:52.057300 ==
2089 11:05:52.060545 Dram Type= 6, Freq= 0, CH_1, rank 1
2090 11:05:52.064021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2091 11:05:52.064099 ==
2092 11:05:52.064163 DQS Delay:
2093 11:05:52.067307 DQS0 = 0, DQS1 = 0
2094 11:05:52.067375 DQM Delay:
2095 11:05:52.070501 DQM0 = 92, DQM1 = 83
2096 11:05:52.070584 DQ Delay:
2097 11:05:52.074110 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =92
2098 11:05:52.077368 DQ4 =92, DQ5 =108, DQ6 =96, DQ7 =88
2099 11:05:52.080906 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2100 11:05:52.084214 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2101 11:05:52.084289
2102 11:05:52.084396
2103 11:05:52.090663 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
2104 11:05:52.094042 CH1 RK1: MR19=606, MR18=3E14
2105 11:05:52.100666 CH1_RK1: MR19=0x606, MR18=0x3E14, DQSOSC=394, MR23=63, INC=95, DEC=63
2106 11:05:52.104123 [RxdqsGatingPostProcess] freq 800
2107 11:05:52.107382 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2108 11:05:52.110672 Pre-setting of DQS Precalculation
2109 11:05:52.117749 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2110 11:05:52.124096 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2111 11:05:52.130952 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2112 11:05:52.131059
2113 11:05:52.131140
2114 11:05:52.133952 [Calibration Summary] 1600 Mbps
2115 11:05:52.134061 CH 0, Rank 0
2116 11:05:52.137698 SW Impedance : PASS
2117 11:05:52.140842 DUTY Scan : NO K
2118 11:05:52.140919 ZQ Calibration : PASS
2119 11:05:52.144474 Jitter Meter : NO K
2120 11:05:52.147821 CBT Training : PASS
2121 11:05:52.147894 Write leveling : PASS
2122 11:05:52.150959 RX DQS gating : PASS
2123 11:05:52.154190 RX DQ/DQS(RDDQC) : PASS
2124 11:05:52.154262 TX DQ/DQS : PASS
2125 11:05:52.157463 RX DATLAT : PASS
2126 11:05:52.160765 RX DQ/DQS(Engine): PASS
2127 11:05:52.160836 TX OE : NO K
2128 11:05:52.164226 All Pass.
2129 11:05:52.164315
2130 11:05:52.164414 CH 0, Rank 1
2131 11:05:52.167486 SW Impedance : PASS
2132 11:05:52.167564 DUTY Scan : NO K
2133 11:05:52.170882 ZQ Calibration : PASS
2134 11:05:52.174099 Jitter Meter : NO K
2135 11:05:52.174204 CBT Training : PASS
2136 11:05:52.177876 Write leveling : PASS
2137 11:05:52.178018 RX DQS gating : PASS
2138 11:05:52.180742 RX DQ/DQS(RDDQC) : PASS
2139 11:05:52.184243 TX DQ/DQS : PASS
2140 11:05:52.184352 RX DATLAT : PASS
2141 11:05:52.187647 RX DQ/DQS(Engine): PASS
2142 11:05:52.190787 TX OE : NO K
2143 11:05:52.190860 All Pass.
2144 11:05:52.190929
2145 11:05:52.190987 CH 1, Rank 0
2146 11:05:52.194131 SW Impedance : PASS
2147 11:05:52.197465 DUTY Scan : NO K
2148 11:05:52.197570 ZQ Calibration : PASS
2149 11:05:52.201131 Jitter Meter : NO K
2150 11:05:52.204147 CBT Training : PASS
2151 11:05:52.204222 Write leveling : PASS
2152 11:05:52.207791 RX DQS gating : PASS
2153 11:05:52.210747 RX DQ/DQS(RDDQC) : PASS
2154 11:05:52.210844 TX DQ/DQS : PASS
2155 11:05:52.214496 RX DATLAT : PASS
2156 11:05:52.214607 RX DQ/DQS(Engine): PASS
2157 11:05:52.217568 TX OE : NO K
2158 11:05:52.217686 All Pass.
2159 11:05:52.217799
2160 11:05:52.221242 CH 1, Rank 1
2161 11:05:52.221348 SW Impedance : PASS
2162 11:05:52.224387 DUTY Scan : NO K
2163 11:05:52.227976 ZQ Calibration : PASS
2164 11:05:52.228053 Jitter Meter : NO K
2165 11:05:52.231105 CBT Training : PASS
2166 11:05:52.234344 Write leveling : PASS
2167 11:05:52.234421 RX DQS gating : PASS
2168 11:05:52.237993 RX DQ/DQS(RDDQC) : PASS
2169 11:05:52.240954 TX DQ/DQS : PASS
2170 11:05:52.241036 RX DATLAT : PASS
2171 11:05:52.244346 RX DQ/DQS(Engine): PASS
2172 11:05:52.247950 TX OE : NO K
2173 11:05:52.248025 All Pass.
2174 11:05:52.248088
2175 11:05:52.248146 DramC Write-DBI off
2176 11:05:52.250999 PER_BANK_REFRESH: Hybrid Mode
2177 11:05:52.254631 TX_TRACKING: ON
2178 11:05:52.257631 [GetDramInforAfterCalByMRR] Vendor 6.
2179 11:05:52.260972 [GetDramInforAfterCalByMRR] Revision 606.
2180 11:05:52.264317 [GetDramInforAfterCalByMRR] Revision 2 0.
2181 11:05:52.264384 MR0 0x3b3b
2182 11:05:52.267834 MR8 0x5151
2183 11:05:52.271257 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2184 11:05:52.271335
2185 11:05:52.271401 MR0 0x3b3b
2186 11:05:52.271481 MR8 0x5151
2187 11:05:52.274559 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2188 11:05:52.274649
2189 11:05:52.284342 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2190 11:05:52.288031 [FAST_K] Save calibration result to emmc
2191 11:05:52.291324 [FAST_K] Save calibration result to emmc
2192 11:05:52.294386 dram_init: config_dvfs: 1
2193 11:05:52.298077 dramc_set_vcore_voltage set vcore to 662500
2194 11:05:52.301303 Read voltage for 1200, 2
2195 11:05:52.301387 Vio18 = 0
2196 11:05:52.301454 Vcore = 662500
2197 11:05:52.304584 Vdram = 0
2198 11:05:52.304690 Vddq = 0
2199 11:05:52.304768 Vmddr = 0
2200 11:05:52.311310 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2201 11:05:52.314850 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2202 11:05:52.317869 MEM_TYPE=3, freq_sel=15
2203 11:05:52.321441 sv_algorithm_assistance_LP4_1600
2204 11:05:52.324504 ============ PULL DRAM RESETB DOWN ============
2205 11:05:52.328317 ========== PULL DRAM RESETB DOWN end =========
2206 11:05:52.335161 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2207 11:05:52.338498 ===================================
2208 11:05:52.338583 LPDDR4 DRAM CONFIGURATION
2209 11:05:52.341726 ===================================
2210 11:05:52.344836 EX_ROW_EN[0] = 0x0
2211 11:05:52.348390 EX_ROW_EN[1] = 0x0
2212 11:05:52.348475 LP4Y_EN = 0x0
2213 11:05:52.351690 WORK_FSP = 0x0
2214 11:05:52.351775 WL = 0x4
2215 11:05:52.354944 RL = 0x4
2216 11:05:52.355029 BL = 0x2
2217 11:05:52.358302 RPST = 0x0
2218 11:05:52.358386 RD_PRE = 0x0
2219 11:05:52.361589 WR_PRE = 0x1
2220 11:05:52.361674 WR_PST = 0x0
2221 11:05:52.365020 DBI_WR = 0x0
2222 11:05:52.365105 DBI_RD = 0x0
2223 11:05:52.368296 OTF = 0x1
2224 11:05:52.371506 ===================================
2225 11:05:52.374863 ===================================
2226 11:05:52.374948 ANA top config
2227 11:05:52.378219 ===================================
2228 11:05:52.381475 DLL_ASYNC_EN = 0
2229 11:05:52.384993 ALL_SLAVE_EN = 0
2230 11:05:52.385078 NEW_RANK_MODE = 1
2231 11:05:52.388221 DLL_IDLE_MODE = 1
2232 11:05:52.391547 LP45_APHY_COMB_EN = 1
2233 11:05:52.395117 TX_ODT_DIS = 1
2234 11:05:52.398432 NEW_8X_MODE = 1
2235 11:05:52.401742 ===================================
2236 11:05:52.405142 ===================================
2237 11:05:52.405227 data_rate = 2400
2238 11:05:52.408266 CKR = 1
2239 11:05:52.411611 DQ_P2S_RATIO = 8
2240 11:05:52.415422 ===================================
2241 11:05:52.418742 CA_P2S_RATIO = 8
2242 11:05:52.422059 DQ_CA_OPEN = 0
2243 11:05:52.425558 DQ_SEMI_OPEN = 0
2244 11:05:52.425644 CA_SEMI_OPEN = 0
2245 11:05:52.428833 CA_FULL_RATE = 0
2246 11:05:52.432178 DQ_CKDIV4_EN = 0
2247 11:05:52.435292 CA_CKDIV4_EN = 0
2248 11:05:52.438760 CA_PREDIV_EN = 0
2249 11:05:52.438845 PH8_DLY = 17
2250 11:05:52.441953 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2251 11:05:52.445630 DQ_AAMCK_DIV = 4
2252 11:05:52.448801 CA_AAMCK_DIV = 4
2253 11:05:52.452026 CA_ADMCK_DIV = 4
2254 11:05:52.455200 DQ_TRACK_CA_EN = 0
2255 11:05:52.458617 CA_PICK = 1200
2256 11:05:52.458702 CA_MCKIO = 1200
2257 11:05:52.462388 MCKIO_SEMI = 0
2258 11:05:52.465237 PLL_FREQ = 2366
2259 11:05:52.468885 DQ_UI_PI_RATIO = 32
2260 11:05:52.472198 CA_UI_PI_RATIO = 0
2261 11:05:52.475442 ===================================
2262 11:05:52.478793 ===================================
2263 11:05:52.482189 memory_type:LPDDR4
2264 11:05:52.482274 GP_NUM : 10
2265 11:05:52.485471 SRAM_EN : 1
2266 11:05:52.485555 MD32_EN : 0
2267 11:05:52.488618 ===================================
2268 11:05:52.491928 [ANA_INIT] >>>>>>>>>>>>>>
2269 11:05:52.495454 <<<<<< [CONFIGURE PHASE]: ANA_TX
2270 11:05:52.498598 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2271 11:05:52.501770 ===================================
2272 11:05:52.505090 data_rate = 2400,PCW = 0X5b00
2273 11:05:52.508456 ===================================
2274 11:05:52.511921 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2275 11:05:52.515547 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2276 11:05:52.522094 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2277 11:05:52.525548 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2278 11:05:52.528752 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2279 11:05:52.531899 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2280 11:05:52.535211 [ANA_INIT] flow start
2281 11:05:52.538618 [ANA_INIT] PLL >>>>>>>>
2282 11:05:52.538702 [ANA_INIT] PLL <<<<<<<<
2283 11:05:52.541871 [ANA_INIT] MIDPI >>>>>>>>
2284 11:05:52.545363 [ANA_INIT] MIDPI <<<<<<<<
2285 11:05:52.548839 [ANA_INIT] DLL >>>>>>>>
2286 11:05:52.548924 [ANA_INIT] DLL <<<<<<<<
2287 11:05:52.552183 [ANA_INIT] flow end
2288 11:05:52.555336 ============ LP4 DIFF to SE enter ============
2289 11:05:52.558522 ============ LP4 DIFF to SE exit ============
2290 11:05:52.562169 [ANA_INIT] <<<<<<<<<<<<<
2291 11:05:52.565141 [Flow] Enable top DCM control >>>>>
2292 11:05:52.568872 [Flow] Enable top DCM control <<<<<
2293 11:05:52.572146 Enable DLL master slave shuffle
2294 11:05:52.575484 ==============================================================
2295 11:05:52.578664 Gating Mode config
2296 11:05:52.585479 ==============================================================
2297 11:05:52.585564 Config description:
2298 11:05:52.595742 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2299 11:05:52.602037 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2300 11:05:52.608869 SELPH_MODE 0: By rank 1: By Phase
2301 11:05:52.612031 ==============================================================
2302 11:05:52.615324 GAT_TRACK_EN = 1
2303 11:05:52.618926 RX_GATING_MODE = 2
2304 11:05:52.622004 RX_GATING_TRACK_MODE = 2
2305 11:05:52.625430 SELPH_MODE = 1
2306 11:05:52.628598 PICG_EARLY_EN = 1
2307 11:05:52.632327 VALID_LAT_VALUE = 1
2308 11:05:52.635587 ==============================================================
2309 11:05:52.638981 Enter into Gating configuration >>>>
2310 11:05:52.642484 Exit from Gating configuration <<<<
2311 11:05:52.645594 Enter into DVFS_PRE_config >>>>>
2312 11:05:52.658921 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2313 11:05:52.659008 Exit from DVFS_PRE_config <<<<<
2314 11:05:52.662259 Enter into PICG configuration >>>>
2315 11:05:52.665532 Exit from PICG configuration <<<<
2316 11:05:52.668896 [RX_INPUT] configuration >>>>>
2317 11:05:52.672167 [RX_INPUT] configuration <<<<<
2318 11:05:52.678645 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2319 11:05:52.682453 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2320 11:05:52.688993 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2321 11:05:52.695348 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2322 11:05:52.702034 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2323 11:05:52.708662 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2324 11:05:52.711988 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2325 11:05:52.715688 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2326 11:05:52.718693 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2327 11:05:52.725713 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2328 11:05:52.728650 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2329 11:05:52.732438 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2330 11:05:52.735793 ===================================
2331 11:05:52.739066 LPDDR4 DRAM CONFIGURATION
2332 11:05:52.742386 ===================================
2333 11:05:52.742500 EX_ROW_EN[0] = 0x0
2334 11:05:52.745675 EX_ROW_EN[1] = 0x0
2335 11:05:52.745758 LP4Y_EN = 0x0
2336 11:05:52.748941 WORK_FSP = 0x0
2337 11:05:52.749038 WL = 0x4
2338 11:05:52.752125 RL = 0x4
2339 11:05:52.755720 BL = 0x2
2340 11:05:52.755804 RPST = 0x0
2341 11:05:52.758985 RD_PRE = 0x0
2342 11:05:52.759069 WR_PRE = 0x1
2343 11:05:52.762081 WR_PST = 0x0
2344 11:05:52.762169 DBI_WR = 0x0
2345 11:05:52.765838 DBI_RD = 0x0
2346 11:05:52.765937 OTF = 0x1
2347 11:05:52.768770 ===================================
2348 11:05:52.771978 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2349 11:05:52.778644 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2350 11:05:52.782098 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2351 11:05:52.785456 ===================================
2352 11:05:52.788939 LPDDR4 DRAM CONFIGURATION
2353 11:05:52.792240 ===================================
2354 11:05:52.792325 EX_ROW_EN[0] = 0x10
2355 11:05:52.795736 EX_ROW_EN[1] = 0x0
2356 11:05:52.795820 LP4Y_EN = 0x0
2357 11:05:52.798775 WORK_FSP = 0x0
2358 11:05:52.798860 WL = 0x4
2359 11:05:52.802326 RL = 0x4
2360 11:05:52.802416 BL = 0x2
2361 11:05:52.805528 RPST = 0x0
2362 11:05:52.805610 RD_PRE = 0x0
2363 11:05:52.808687 WR_PRE = 0x1
2364 11:05:52.808768 WR_PST = 0x0
2365 11:05:52.812171 DBI_WR = 0x0
2366 11:05:52.812253 DBI_RD = 0x0
2367 11:05:52.815485 OTF = 0x1
2368 11:05:52.818685 ===================================
2369 11:05:52.825765 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2370 11:05:52.825848 ==
2371 11:05:52.828935 Dram Type= 6, Freq= 0, CH_0, rank 0
2372 11:05:52.832314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2373 11:05:52.832397 ==
2374 11:05:52.835595 [Duty_Offset_Calibration]
2375 11:05:52.835677 B0:2 B1:0 CA:1
2376 11:05:52.835742
2377 11:05:52.838748 [DutyScan_Calibration_Flow] k_type=0
2378 11:05:52.848732
2379 11:05:52.848813 ==CLK 0==
2380 11:05:52.852387 Final CLK duty delay cell = -4
2381 11:05:52.855605 [-4] MAX Duty = 5031%(X100), DQS PI = 26
2382 11:05:52.858794 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2383 11:05:52.862266 [-4] AVG Duty = 4953%(X100)
2384 11:05:52.862348
2385 11:05:52.865527 CH0 CLK Duty spec in!! Max-Min= 156%
2386 11:05:52.869238 [DutyScan_Calibration_Flow] ====Done====
2387 11:05:52.869320
2388 11:05:52.872178 [DutyScan_Calibration_Flow] k_type=1
2389 11:05:52.887378
2390 11:05:52.887460 ==DQS 0 ==
2391 11:05:52.891161 Final DQS duty delay cell = 0
2392 11:05:52.894266 [0] MAX Duty = 5187%(X100), DQS PI = 32
2393 11:05:52.897614 [0] MIN Duty = 4938%(X100), DQS PI = 0
2394 11:05:52.897696 [0] AVG Duty = 5062%(X100)
2395 11:05:52.900879
2396 11:05:52.900961 ==DQS 1 ==
2397 11:05:52.904601 Final DQS duty delay cell = -4
2398 11:05:52.907566 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2399 11:05:52.911171 [-4] MIN Duty = 4938%(X100), DQS PI = 6
2400 11:05:52.914410 [-4] AVG Duty = 5031%(X100)
2401 11:05:52.914508
2402 11:05:52.917495 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2403 11:05:52.917582
2404 11:05:52.920756 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2405 11:05:52.924493 [DutyScan_Calibration_Flow] ====Done====
2406 11:05:52.924575
2407 11:05:52.927805 [DutyScan_Calibration_Flow] k_type=3
2408 11:05:52.944492
2409 11:05:52.944574 ==DQM 0 ==
2410 11:05:52.947799 Final DQM duty delay cell = 0
2411 11:05:52.951152 [0] MAX Duty = 5062%(X100), DQS PI = 24
2412 11:05:52.954306 [0] MIN Duty = 4813%(X100), DQS PI = 2
2413 11:05:52.954387 [0] AVG Duty = 4937%(X100)
2414 11:05:52.957821
2415 11:05:52.957903 ==DQM 1 ==
2416 11:05:52.961013 Final DQM duty delay cell = 0
2417 11:05:52.964513 [0] MAX Duty = 5218%(X100), DQS PI = 48
2418 11:05:52.967678 [0] MIN Duty = 5000%(X100), DQS PI = 22
2419 11:05:52.967762 [0] AVG Duty = 5109%(X100)
2420 11:05:52.967829
2421 11:05:52.974704 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2422 11:05:52.974789
2423 11:05:52.977756 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2424 11:05:52.981407 [DutyScan_Calibration_Flow] ====Done====
2425 11:05:52.981491
2426 11:05:52.984276 [DutyScan_Calibration_Flow] k_type=2
2427 11:05:52.999953
2428 11:05:53.000036 ==DQ 0 ==
2429 11:05:53.003737 Final DQ duty delay cell = -4
2430 11:05:53.006943 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2431 11:05:53.009990 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2432 11:05:53.013576 [-4] AVG Duty = 4968%(X100)
2433 11:05:53.013660
2434 11:05:53.013727 ==DQ 1 ==
2435 11:05:53.016906 Final DQ duty delay cell = 0
2436 11:05:53.020108 [0] MAX Duty = 4969%(X100), DQS PI = 8
2437 11:05:53.023550 [0] MIN Duty = 4907%(X100), DQS PI = 0
2438 11:05:53.023661 [0] AVG Duty = 4938%(X100)
2439 11:05:53.026800
2440 11:05:53.030103 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2441 11:05:53.030220
2442 11:05:53.033386 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2443 11:05:53.037024 [DutyScan_Calibration_Flow] ====Done====
2444 11:05:53.037098 ==
2445 11:05:53.040269 Dram Type= 6, Freq= 0, CH_1, rank 0
2446 11:05:53.043429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2447 11:05:53.043527 ==
2448 11:05:53.046772 [Duty_Offset_Calibration]
2449 11:05:53.046867 B0:0 B1:-1 CA:2
2450 11:05:53.046961
2451 11:05:53.050161 [DutyScan_Calibration_Flow] k_type=0
2452 11:05:53.060188
2453 11:05:53.060282 ==CLK 0==
2454 11:05:53.063454 Final CLK duty delay cell = 0
2455 11:05:53.067030 [0] MAX Duty = 5156%(X100), DQS PI = 16
2456 11:05:53.070196 [0] MIN Duty = 4938%(X100), DQS PI = 44
2457 11:05:53.070276 [0] AVG Duty = 5047%(X100)
2458 11:05:53.073861
2459 11:05:53.076950 CH1 CLK Duty spec in!! Max-Min= 218%
2460 11:05:53.080073 [DutyScan_Calibration_Flow] ====Done====
2461 11:05:53.080172
2462 11:05:53.083267 [DutyScan_Calibration_Flow] k_type=1
2463 11:05:53.099700
2464 11:05:53.099802 ==DQS 0 ==
2465 11:05:53.102929 Final DQS duty delay cell = 0
2466 11:05:53.106189 [0] MAX Duty = 5093%(X100), DQS PI = 24
2467 11:05:53.109769 [0] MIN Duty = 4969%(X100), DQS PI = 0
2468 11:05:53.109869 [0] AVG Duty = 5031%(X100)
2469 11:05:53.113010
2470 11:05:53.113108 ==DQS 1 ==
2471 11:05:53.116313 Final DQS duty delay cell = 0
2472 11:05:53.119827 [0] MAX Duty = 5156%(X100), DQS PI = 0
2473 11:05:53.123087 [0] MIN Duty = 4844%(X100), DQS PI = 36
2474 11:05:53.123192 [0] AVG Duty = 5000%(X100)
2475 11:05:53.126116
2476 11:05:53.129620 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2477 11:05:53.129723
2478 11:05:53.132898 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2479 11:05:53.136129 [DutyScan_Calibration_Flow] ====Done====
2480 11:05:53.136202
2481 11:05:53.139491 [DutyScan_Calibration_Flow] k_type=3
2482 11:05:53.157238
2483 11:05:53.157347 ==DQM 0 ==
2484 11:05:53.160504 Final DQM duty delay cell = 4
2485 11:05:53.163654 [4] MAX Duty = 5093%(X100), DQS PI = 6
2486 11:05:53.167062 [4] MIN Duty = 4969%(X100), DQS PI = 28
2487 11:05:53.167134 [4] AVG Duty = 5031%(X100)
2488 11:05:53.170681
2489 11:05:53.170782 ==DQM 1 ==
2490 11:05:53.173755 Final DQM duty delay cell = 0
2491 11:05:53.177109 [0] MAX Duty = 5249%(X100), DQS PI = 0
2492 11:05:53.180160 [0] MIN Duty = 4875%(X100), DQS PI = 36
2493 11:05:53.180234 [0] AVG Duty = 5062%(X100)
2494 11:05:53.180305
2495 11:05:53.186905 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2496 11:05:53.186984
2497 11:05:53.190166 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2498 11:05:53.193583 [DutyScan_Calibration_Flow] ====Done====
2499 11:05:53.193686
2500 11:05:53.197022 [DutyScan_Calibration_Flow] k_type=2
2501 11:05:53.213392
2502 11:05:53.213503 ==DQ 0 ==
2503 11:05:53.216657 Final DQ duty delay cell = 0
2504 11:05:53.219826 [0] MAX Duty = 5062%(X100), DQS PI = 18
2505 11:05:53.223603 [0] MIN Duty = 4938%(X100), DQS PI = 0
2506 11:05:53.223708 [0] AVG Duty = 5000%(X100)
2507 11:05:53.226741
2508 11:05:53.226847 ==DQ 1 ==
2509 11:05:53.230069 Final DQ duty delay cell = 0
2510 11:05:53.233531 [0] MAX Duty = 5031%(X100), DQS PI = 0
2511 11:05:53.236793 [0] MIN Duty = 4813%(X100), DQS PI = 36
2512 11:05:53.236900 [0] AVG Duty = 4922%(X100)
2513 11:05:53.236992
2514 11:05:53.239966 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2515 11:05:53.243140
2516 11:05:53.246759 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2517 11:05:53.250223 [DutyScan_Calibration_Flow] ====Done====
2518 11:05:53.253154 nWR fixed to 30
2519 11:05:53.253253 [ModeRegInit_LP4] CH0 RK0
2520 11:05:53.256933 [ModeRegInit_LP4] CH0 RK1
2521 11:05:53.260232 [ModeRegInit_LP4] CH1 RK0
2522 11:05:53.260334 [ModeRegInit_LP4] CH1 RK1
2523 11:05:53.263609 match AC timing 7
2524 11:05:53.266756 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2525 11:05:53.270174 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2526 11:05:53.276830 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2527 11:05:53.280223 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2528 11:05:53.286836 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2529 11:05:53.286925 ==
2530 11:05:53.290134 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 11:05:53.293359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 11:05:53.293459 ==
2533 11:05:53.300082 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2534 11:05:53.303697 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2535 11:05:53.313254 [CA 0] Center 38 (8~69) winsize 62
2536 11:05:53.316548 [CA 1] Center 38 (8~69) winsize 62
2537 11:05:53.319897 [CA 2] Center 35 (5~66) winsize 62
2538 11:05:53.323055 [CA 3] Center 35 (4~66) winsize 63
2539 11:05:53.326478 [CA 4] Center 34 (4~65) winsize 62
2540 11:05:53.329838 [CA 5] Center 33 (3~63) winsize 61
2541 11:05:53.329966
2542 11:05:53.333295 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2543 11:05:53.333394
2544 11:05:53.336439 [CATrainingPosCal] consider 1 rank data
2545 11:05:53.339790 u2DelayCellTimex100 = 270/100 ps
2546 11:05:53.343583 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2547 11:05:53.346578 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2548 11:05:53.353104 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2549 11:05:53.356375 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2550 11:05:53.360138 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2551 11:05:53.363318 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2552 11:05:53.363419
2553 11:05:53.366513 CA PerBit enable=1, Macro0, CA PI delay=33
2554 11:05:53.366617
2555 11:05:53.369886 [CBTSetCACLKResult] CA Dly = 33
2556 11:05:53.370020 CS Dly: 6 (0~37)
2557 11:05:53.370112 ==
2558 11:05:53.373214 Dram Type= 6, Freq= 0, CH_0, rank 1
2559 11:05:53.379923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2560 11:05:53.380029 ==
2561 11:05:53.383227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2562 11:05:53.389980 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2563 11:05:53.399156 [CA 0] Center 39 (8~70) winsize 63
2564 11:05:53.402475 [CA 1] Center 38 (8~69) winsize 62
2565 11:05:53.405795 [CA 2] Center 35 (5~66) winsize 62
2566 11:05:53.409090 [CA 3] Center 35 (5~66) winsize 62
2567 11:05:53.412167 [CA 4] Center 34 (4~65) winsize 62
2568 11:05:53.415445 [CA 5] Center 34 (4~64) winsize 61
2569 11:05:53.415542
2570 11:05:53.418773 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2571 11:05:53.418878
2572 11:05:53.422469 [CATrainingPosCal] consider 2 rank data
2573 11:05:53.425692 u2DelayCellTimex100 = 270/100 ps
2574 11:05:53.429422 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2575 11:05:53.432397 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2576 11:05:53.439092 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2577 11:05:53.442206 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2578 11:05:53.445925 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2579 11:05:53.449078 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2580 11:05:53.449150
2581 11:05:53.452602 CA PerBit enable=1, Macro0, CA PI delay=33
2582 11:05:53.452680
2583 11:05:53.455832 [CBTSetCACLKResult] CA Dly = 33
2584 11:05:53.455910 CS Dly: 7 (0~39)
2585 11:05:53.455977
2586 11:05:53.459119 ----->DramcWriteLeveling(PI) begin...
2587 11:05:53.459197 ==
2588 11:05:53.462504 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 11:05:53.469112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 11:05:53.469193 ==
2591 11:05:53.472455 Write leveling (Byte 0): 34 => 34
2592 11:05:53.475619 Write leveling (Byte 1): 31 => 31
2593 11:05:53.475691 DramcWriteLeveling(PI) end<-----
2594 11:05:53.478946
2595 11:05:53.479017 ==
2596 11:05:53.482626 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 11:05:53.485696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 11:05:53.485773 ==
2599 11:05:53.489217 [Gating] SW mode calibration
2600 11:05:53.495507 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2601 11:05:53.499241 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2602 11:05:53.505690 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2603 11:05:53.508971 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2604 11:05:53.512230 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 11:05:53.519361 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 11:05:53.522196 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 11:05:53.525677 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 11:05:53.532594 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2609 11:05:53.535621 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2610 11:05:53.539055 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
2611 11:05:53.546052 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 11:05:53.549292 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 11:05:53.552652 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 11:05:53.559117 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 11:05:53.562496 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 11:05:53.565918 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2617 11:05:53.569267 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2618 11:05:53.575722 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2619 11:05:53.579045 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 11:05:53.582507 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 11:05:53.589341 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 11:05:53.592530 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 11:05:53.595947 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 11:05:53.602694 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2625 11:05:53.606119 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2626 11:05:53.609471 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2627 11:05:53.616127 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 11:05:53.619316 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 11:05:53.622559 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 11:05:53.629769 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 11:05:53.632893 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 11:05:53.636261 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 11:05:53.639720 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 11:05:53.646303 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 11:05:53.649522 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 11:05:53.652844 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 11:05:53.659637 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 11:05:53.662813 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 11:05:53.666109 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 11:05:53.672698 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 11:05:53.676053 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2642 11:05:53.679534 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2643 11:05:53.682752 Total UI for P1: 0, mck2ui 16
2644 11:05:53.685869 best dqsien dly found for B0: ( 1, 3, 28)
2645 11:05:53.692662 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2646 11:05:53.692748 Total UI for P1: 0, mck2ui 16
2647 11:05:53.699699 best dqsien dly found for B1: ( 1, 4, 0)
2648 11:05:53.702849 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2649 11:05:53.706076 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2650 11:05:53.706160
2651 11:05:53.709683 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2652 11:05:53.712685 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2653 11:05:53.716396 [Gating] SW calibration Done
2654 11:05:53.716481 ==
2655 11:05:53.719540 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 11:05:53.722953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 11:05:53.723037 ==
2658 11:05:53.726113 RX Vref Scan: 0
2659 11:05:53.726198
2660 11:05:53.726263 RX Vref 0 -> 0, step: 1
2661 11:05:53.726325
2662 11:05:53.729474 RX Delay -40 -> 252, step: 8
2663 11:05:53.733156 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2664 11:05:53.736121 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2665 11:05:53.742973 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2666 11:05:53.746352 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2667 11:05:53.749664 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2668 11:05:53.752942 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2669 11:05:53.756185 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2670 11:05:53.762911 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2671 11:05:53.766064 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2672 11:05:53.769379 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2673 11:05:53.772745 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2674 11:05:53.776061 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2675 11:05:53.782785 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2676 11:05:53.786105 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2677 11:05:53.789270 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2678 11:05:53.792738 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2679 11:05:53.792824 ==
2680 11:05:53.796359 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 11:05:53.799513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 11:05:53.803033 ==
2683 11:05:53.803179 DQS Delay:
2684 11:05:53.803262 DQS0 = 0, DQS1 = 0
2685 11:05:53.806387 DQM Delay:
2686 11:05:53.806471 DQM0 = 122, DQM1 = 110
2687 11:05:53.809626 DQ Delay:
2688 11:05:53.812810 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2689 11:05:53.816634 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2690 11:05:53.820015 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2691 11:05:53.823291 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2692 11:05:53.823376
2693 11:05:53.823443
2694 11:05:53.823505 ==
2695 11:05:53.826563 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 11:05:53.829769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 11:05:53.829853 ==
2698 11:05:53.829920
2699 11:05:53.830021
2700 11:05:53.833118 TX Vref Scan disable
2701 11:05:53.836361 == TX Byte 0 ==
2702 11:05:53.839638 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2703 11:05:53.842777 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2704 11:05:53.846096 == TX Byte 1 ==
2705 11:05:53.849649 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2706 11:05:53.853014 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2707 11:05:53.853098 ==
2708 11:05:53.856241 Dram Type= 6, Freq= 0, CH_0, rank 0
2709 11:05:53.863026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2710 11:05:53.863111 ==
2711 11:05:53.872944 TX Vref=22, minBit 4, minWin=23, winSum=400
2712 11:05:53.876718 TX Vref=24, minBit 1, minWin=24, winSum=411
2713 11:05:53.880034 TX Vref=26, minBit 3, minWin=24, winSum=411
2714 11:05:53.882895 TX Vref=28, minBit 7, minWin=24, winSum=414
2715 11:05:53.886687 TX Vref=30, minBit 1, minWin=25, winSum=417
2716 11:05:53.893044 TX Vref=32, minBit 0, minWin=25, winSum=414
2717 11:05:53.896196 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 30
2718 11:05:53.896280
2719 11:05:53.899887 Final TX Range 1 Vref 30
2720 11:05:53.899971
2721 11:05:53.900037 ==
2722 11:05:53.903099 Dram Type= 6, Freq= 0, CH_0, rank 0
2723 11:05:53.906203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2724 11:05:53.906288 ==
2725 11:05:53.909791
2726 11:05:53.909875
2727 11:05:53.909964 TX Vref Scan disable
2728 11:05:53.912915 == TX Byte 0 ==
2729 11:05:53.916105 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2730 11:05:53.919899 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2731 11:05:53.923228 == TX Byte 1 ==
2732 11:05:53.926747 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2733 11:05:53.929649 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2734 11:05:53.933456
2735 11:05:53.933540 [DATLAT]
2736 11:05:53.933607 Freq=1200, CH0 RK0
2737 11:05:53.933669
2738 11:05:53.936639 DATLAT Default: 0xd
2739 11:05:53.936722 0, 0xFFFF, sum = 0
2740 11:05:53.939900 1, 0xFFFF, sum = 0
2741 11:05:53.939986 2, 0xFFFF, sum = 0
2742 11:05:53.943082 3, 0xFFFF, sum = 0
2743 11:05:53.943168 4, 0xFFFF, sum = 0
2744 11:05:53.946707 5, 0xFFFF, sum = 0
2745 11:05:53.946792 6, 0xFFFF, sum = 0
2746 11:05:53.950068 7, 0xFFFF, sum = 0
2747 11:05:53.953131 8, 0xFFFF, sum = 0
2748 11:05:53.953216 9, 0xFFFF, sum = 0
2749 11:05:53.956470 10, 0xFFFF, sum = 0
2750 11:05:53.956555 11, 0xFFFF, sum = 0
2751 11:05:53.959761 12, 0x0, sum = 1
2752 11:05:53.959846 13, 0x0, sum = 2
2753 11:05:53.963363 14, 0x0, sum = 3
2754 11:05:53.963448 15, 0x0, sum = 4
2755 11:05:53.963516 best_step = 13
2756 11:05:53.963578
2757 11:05:53.966486 ==
2758 11:05:53.969861 Dram Type= 6, Freq= 0, CH_0, rank 0
2759 11:05:53.973161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2760 11:05:53.973246 ==
2761 11:05:53.973312 RX Vref Scan: 1
2762 11:05:53.973375
2763 11:05:53.976440 Set Vref Range= 32 -> 127
2764 11:05:53.976524
2765 11:05:53.979795 RX Vref 32 -> 127, step: 1
2766 11:05:53.979879
2767 11:05:53.983150 RX Delay -13 -> 252, step: 4
2768 11:05:53.983234
2769 11:05:53.986166 Set Vref, RX VrefLevel [Byte0]: 32
2770 11:05:53.989891 [Byte1]: 32
2771 11:05:53.990018
2772 11:05:53.993155 Set Vref, RX VrefLevel [Byte0]: 33
2773 11:05:53.996256 [Byte1]: 33
2774 11:05:53.996356
2775 11:05:53.999581 Set Vref, RX VrefLevel [Byte0]: 34
2776 11:05:54.002797 [Byte1]: 34
2777 11:05:54.007583
2778 11:05:54.007687 Set Vref, RX VrefLevel [Byte0]: 35
2779 11:05:54.010727 [Byte1]: 35
2780 11:05:54.015121
2781 11:05:54.015222 Set Vref, RX VrefLevel [Byte0]: 36
2782 11:05:54.018689 [Byte1]: 36
2783 11:05:54.022858
2784 11:05:54.022963 Set Vref, RX VrefLevel [Byte0]: 37
2785 11:05:54.026148 [Byte1]: 37
2786 11:05:54.031047
2787 11:05:54.031148 Set Vref, RX VrefLevel [Byte0]: 38
2788 11:05:54.034217 [Byte1]: 38
2789 11:05:54.038702
2790 11:05:54.038780 Set Vref, RX VrefLevel [Byte0]: 39
2791 11:05:54.042543 [Byte1]: 39
2792 11:05:54.046851
2793 11:05:54.046934 Set Vref, RX VrefLevel [Byte0]: 40
2794 11:05:54.050198 [Byte1]: 40
2795 11:05:54.054530
2796 11:05:54.054609 Set Vref, RX VrefLevel [Byte0]: 41
2797 11:05:54.057736 [Byte1]: 41
2798 11:05:54.062486
2799 11:05:54.062588 Set Vref, RX VrefLevel [Byte0]: 42
2800 11:05:54.065709 [Byte1]: 42
2801 11:05:54.070367
2802 11:05:54.070475 Set Vref, RX VrefLevel [Byte0]: 43
2803 11:05:54.073664 [Byte1]: 43
2804 11:05:54.078232
2805 11:05:54.078308 Set Vref, RX VrefLevel [Byte0]: 44
2806 11:05:54.081466 [Byte1]: 44
2807 11:05:54.086198
2808 11:05:54.086274 Set Vref, RX VrefLevel [Byte0]: 45
2809 11:05:54.089485 [Byte1]: 45
2810 11:05:54.094243
2811 11:05:54.094345 Set Vref, RX VrefLevel [Byte0]: 46
2812 11:05:54.097690 [Byte1]: 46
2813 11:05:54.102124
2814 11:05:54.102233 Set Vref, RX VrefLevel [Byte0]: 47
2815 11:05:54.105236 [Byte1]: 47
2816 11:05:54.109893
2817 11:05:54.110039 Set Vref, RX VrefLevel [Byte0]: 48
2818 11:05:54.113003 [Byte1]: 48
2819 11:05:54.117641
2820 11:05:54.117780 Set Vref, RX VrefLevel [Byte0]: 49
2821 11:05:54.121312 [Byte1]: 49
2822 11:05:54.125443
2823 11:05:54.125522 Set Vref, RX VrefLevel [Byte0]: 50
2824 11:05:54.128762 [Byte1]: 50
2825 11:05:54.133391
2826 11:05:54.133472 Set Vref, RX VrefLevel [Byte0]: 51
2827 11:05:54.137043 [Byte1]: 51
2828 11:05:54.141516
2829 11:05:54.141608 Set Vref, RX VrefLevel [Byte0]: 52
2830 11:05:54.147932 [Byte1]: 52
2831 11:05:54.148040
2832 11:05:54.151084 Set Vref, RX VrefLevel [Byte0]: 53
2833 11:05:54.154718 [Byte1]: 53
2834 11:05:54.154801
2835 11:05:54.157891 Set Vref, RX VrefLevel [Byte0]: 54
2836 11:05:54.161029 [Byte1]: 54
2837 11:05:54.165196
2838 11:05:54.165271 Set Vref, RX VrefLevel [Byte0]: 55
2839 11:05:54.168481 [Byte1]: 55
2840 11:05:54.173143
2841 11:05:54.173244 Set Vref, RX VrefLevel [Byte0]: 56
2842 11:05:54.176340 [Byte1]: 56
2843 11:05:54.181073
2844 11:05:54.181148 Set Vref, RX VrefLevel [Byte0]: 57
2845 11:05:54.184183 [Byte1]: 57
2846 11:05:54.188463
2847 11:05:54.188564 Set Vref, RX VrefLevel [Byte0]: 58
2848 11:05:54.192258 [Byte1]: 58
2849 11:05:54.196505
2850 11:05:54.196580 Set Vref, RX VrefLevel [Byte0]: 59
2851 11:05:54.200168 [Byte1]: 59
2852 11:05:54.204442
2853 11:05:54.204545 Set Vref, RX VrefLevel [Byte0]: 60
2854 11:05:54.207702 [Byte1]: 60
2855 11:05:54.212244
2856 11:05:54.212347 Set Vref, RX VrefLevel [Byte0]: 61
2857 11:05:54.215707 [Byte1]: 61
2858 11:05:54.220277
2859 11:05:54.220376 Set Vref, RX VrefLevel [Byte0]: 62
2860 11:05:54.223794 [Byte1]: 62
2861 11:05:54.228135
2862 11:05:54.228235 Set Vref, RX VrefLevel [Byte0]: 63
2863 11:05:54.231493 [Byte1]: 63
2864 11:05:54.236336
2865 11:05:54.236435 Set Vref, RX VrefLevel [Byte0]: 64
2866 11:05:54.239365 [Byte1]: 64
2867 11:05:54.244102
2868 11:05:54.247304 Set Vref, RX VrefLevel [Byte0]: 65
2869 11:05:54.247404 [Byte1]: 65
2870 11:05:54.251982
2871 11:05:54.252081 Set Vref, RX VrefLevel [Byte0]: 66
2872 11:05:54.255152 [Byte1]: 66
2873 11:05:54.259908
2874 11:05:54.260007 Set Vref, RX VrefLevel [Byte0]: 67
2875 11:05:54.263212 [Byte1]: 67
2876 11:05:54.267692
2877 11:05:54.267792 Set Vref, RX VrefLevel [Byte0]: 68
2878 11:05:54.271070 [Byte1]: 68
2879 11:05:54.275477
2880 11:05:54.275555 Set Vref, RX VrefLevel [Byte0]: 69
2881 11:05:54.278744 [Byte1]: 69
2882 11:05:54.283512
2883 11:05:54.283584 Set Vref, RX VrefLevel [Byte0]: 70
2884 11:05:54.286696 [Byte1]: 70
2885 11:05:54.291351
2886 11:05:54.291425 Final RX Vref Byte 0 = 59 to rank0
2887 11:05:54.294652 Final RX Vref Byte 1 = 49 to rank0
2888 11:05:54.298058 Final RX Vref Byte 0 = 59 to rank1
2889 11:05:54.301507 Final RX Vref Byte 1 = 49 to rank1==
2890 11:05:54.304739 Dram Type= 6, Freq= 0, CH_0, rank 0
2891 11:05:54.307936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 11:05:54.311464 ==
2893 11:05:54.311539 DQS Delay:
2894 11:05:54.311601 DQS0 = 0, DQS1 = 0
2895 11:05:54.314461 DQM Delay:
2896 11:05:54.314528 DQM0 = 122, DQM1 = 109
2897 11:05:54.318012 DQ Delay:
2898 11:05:54.321677 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2899 11:05:54.324764 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2900 11:05:54.328286 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2901 11:05:54.331504 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2902 11:05:54.331602
2903 11:05:54.331672
2904 11:05:54.338040 [DQSOSCAuto] RK0, (LSB)MR18= 0xc09, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2905 11:05:54.341420 CH0 RK0: MR19=404, MR18=C09
2906 11:05:54.348026 CH0_RK0: MR19=0x404, MR18=0xC09, DQSOSC=405, MR23=63, INC=39, DEC=26
2907 11:05:54.348105
2908 11:05:54.351506 ----->DramcWriteLeveling(PI) begin...
2909 11:05:54.351582 ==
2910 11:05:54.355268 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 11:05:54.358568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 11:05:54.358646 ==
2913 11:05:54.361866 Write leveling (Byte 0): 34 => 34
2914 11:05:54.365219 Write leveling (Byte 1): 30 => 30
2915 11:05:54.368334 DramcWriteLeveling(PI) end<-----
2916 11:05:54.368417
2917 11:05:54.368483 ==
2918 11:05:54.371737 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 11:05:54.375010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 11:05:54.375094 ==
2921 11:05:54.378510 [Gating] SW mode calibration
2922 11:05:54.385187 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2923 11:05:54.391663 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2924 11:05:54.395110 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
2925 11:05:54.401529 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 11:05:54.405322 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 11:05:54.408694 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 11:05:54.415480 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 11:05:54.418661 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2930 11:05:54.421888 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2931 11:05:54.425092 0 15 28 | B1->B0 | 3333 2c2c | 0 0 | (1 0) (0 0)
2932 11:05:54.431758 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 11:05:54.435095 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 11:05:54.438809 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 11:05:54.445313 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 11:05:54.448635 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 11:05:54.452002 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2938 11:05:54.458494 1 0 24 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
2939 11:05:54.461738 1 0 28 | B1->B0 | 3737 3e3e | 0 1 | (0 0) (0 0)
2940 11:05:54.465027 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 11:05:54.472069 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 11:05:54.475302 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 11:05:54.478582 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 11:05:54.484945 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 11:05:54.488292 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 11:05:54.491841 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 11:05:54.498264 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2948 11:05:54.502059 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2949 11:05:54.505269 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 11:05:54.511649 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 11:05:54.515137 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 11:05:54.518618 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 11:05:54.522046 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 11:05:54.528426 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 11:05:54.532112 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 11:05:54.535260 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 11:05:54.542106 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 11:05:54.545401 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 11:05:54.548710 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 11:05:54.555564 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 11:05:54.558807 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 11:05:54.562138 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 11:05:54.568812 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2964 11:05:54.572190 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2965 11:05:54.575452 Total UI for P1: 0, mck2ui 16
2966 11:05:54.578559 best dqsien dly found for B0: ( 1, 3, 28)
2967 11:05:54.581893 Total UI for P1: 0, mck2ui 16
2968 11:05:54.585637 best dqsien dly found for B1: ( 1, 3, 30)
2969 11:05:54.589032 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2970 11:05:54.592292 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2971 11:05:54.592375
2972 11:05:54.595537 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2973 11:05:54.598754 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2974 11:05:54.602428 [Gating] SW calibration Done
2975 11:05:54.602511 ==
2976 11:05:54.605811 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 11:05:54.608984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 11:05:54.609067 ==
2979 11:05:54.612298 RX Vref Scan: 0
2980 11:05:54.612381
2981 11:05:54.612447 RX Vref 0 -> 0, step: 1
2982 11:05:54.615675
2983 11:05:54.615757 RX Delay -40 -> 252, step: 8
2984 11:05:54.622158 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2985 11:05:54.625722 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2986 11:05:54.628853 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2987 11:05:54.632155 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2988 11:05:54.635689 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2989 11:05:54.642303 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2990 11:05:54.645684 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2991 11:05:54.649024 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2992 11:05:54.652186 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2993 11:05:54.655492 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2994 11:05:54.658892 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2995 11:05:54.665381 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2996 11:05:54.668952 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2997 11:05:54.672127 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2998 11:05:54.675408 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2999 11:05:54.678855 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
3000 11:05:54.682518 ==
3001 11:05:54.685796 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 11:05:54.689189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 11:05:54.689273 ==
3004 11:05:54.689341 DQS Delay:
3005 11:05:54.692354 DQS0 = 0, DQS1 = 0
3006 11:05:54.692438 DQM Delay:
3007 11:05:54.695701 DQM0 = 120, DQM1 = 108
3008 11:05:54.695800 DQ Delay:
3009 11:05:54.699043 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3010 11:05:54.702316 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3011 11:05:54.705685 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3012 11:05:54.709369 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3013 11:05:54.709453
3014 11:05:54.709520
3015 11:05:54.709581 ==
3016 11:05:54.712080 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 11:05:54.719159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 11:05:54.719244 ==
3019 11:05:54.719310
3020 11:05:54.719372
3021 11:05:54.719430 TX Vref Scan disable
3022 11:05:54.722524 == TX Byte 0 ==
3023 11:05:54.725819 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3024 11:05:54.728945 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3025 11:05:54.732167 == TX Byte 1 ==
3026 11:05:54.735726 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3027 11:05:54.738808 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3028 11:05:54.742447 ==
3029 11:05:54.745946 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 11:05:54.749015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 11:05:54.749126 ==
3032 11:05:54.760530 TX Vref=22, minBit 7, minWin=24, winSum=413
3033 11:05:54.763792 TX Vref=24, minBit 0, minWin=24, winSum=413
3034 11:05:54.767173 TX Vref=26, minBit 0, minWin=25, winSum=413
3035 11:05:54.770536 TX Vref=28, minBit 1, minWin=25, winSum=419
3036 11:05:54.773746 TX Vref=30, minBit 1, minWin=24, winSum=420
3037 11:05:54.780335 TX Vref=32, minBit 1, minWin=25, winSum=418
3038 11:05:54.783744 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 28
3039 11:05:54.783845
3040 11:05:54.787226 Final TX Range 1 Vref 28
3041 11:05:54.787329
3042 11:05:54.787395 ==
3043 11:05:54.790647 Dram Type= 6, Freq= 0, CH_0, rank 1
3044 11:05:54.793795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 11:05:54.793894 ==
3046 11:05:54.794035
3047 11:05:54.797049
3048 11:05:54.797148 TX Vref Scan disable
3049 11:05:54.800299 == TX Byte 0 ==
3050 11:05:54.803689 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3051 11:05:54.807294 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3052 11:05:54.810505 == TX Byte 1 ==
3053 11:05:54.813906 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3054 11:05:54.817256 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3055 11:05:54.817354
3056 11:05:54.820615 [DATLAT]
3057 11:05:54.820721 Freq=1200, CH0 RK1
3058 11:05:54.820823
3059 11:05:54.823819 DATLAT Default: 0xd
3060 11:05:54.823924 0, 0xFFFF, sum = 0
3061 11:05:54.827256 1, 0xFFFF, sum = 0
3062 11:05:54.827365 2, 0xFFFF, sum = 0
3063 11:05:54.830679 3, 0xFFFF, sum = 0
3064 11:05:54.830754 4, 0xFFFF, sum = 0
3065 11:05:54.834112 5, 0xFFFF, sum = 0
3066 11:05:54.834192 6, 0xFFFF, sum = 0
3067 11:05:54.837181 7, 0xFFFF, sum = 0
3068 11:05:54.837257 8, 0xFFFF, sum = 0
3069 11:05:54.840896 9, 0xFFFF, sum = 0
3070 11:05:54.843966 10, 0xFFFF, sum = 0
3071 11:05:54.844052 11, 0xFFFF, sum = 0
3072 11:05:54.847426 12, 0x0, sum = 1
3073 11:05:54.847510 13, 0x0, sum = 2
3074 11:05:54.847578 14, 0x0, sum = 3
3075 11:05:54.850693 15, 0x0, sum = 4
3076 11:05:54.850779 best_step = 13
3077 11:05:54.850845
3078 11:05:54.850908 ==
3079 11:05:54.854212 Dram Type= 6, Freq= 0, CH_0, rank 1
3080 11:05:54.860934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 11:05:54.861044 ==
3082 11:05:54.861142 RX Vref Scan: 0
3083 11:05:54.861239
3084 11:05:54.864253 RX Vref 0 -> 0, step: 1
3085 11:05:54.864353
3086 11:05:54.867535 RX Delay -21 -> 252, step: 4
3087 11:05:54.870545 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3088 11:05:54.873908 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3089 11:05:54.880721 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3090 11:05:54.883883 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3091 11:05:54.887205 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3092 11:05:54.890490 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3093 11:05:54.894285 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3094 11:05:54.900494 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3095 11:05:54.904310 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3096 11:05:54.907626 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3097 11:05:54.910873 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3098 11:05:54.914379 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3099 11:05:54.917612 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3100 11:05:54.924200 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3101 11:05:54.927565 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3102 11:05:54.930796 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3103 11:05:54.930873 ==
3104 11:05:54.934238 Dram Type= 6, Freq= 0, CH_0, rank 1
3105 11:05:54.937663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 11:05:54.940785 ==
3107 11:05:54.940890 DQS Delay:
3108 11:05:54.940990 DQS0 = 0, DQS1 = 0
3109 11:05:54.944466 DQM Delay:
3110 11:05:54.944580 DQM0 = 120, DQM1 = 108
3111 11:05:54.947722 DQ Delay:
3112 11:05:54.950664 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =116
3113 11:05:54.954210 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =126
3114 11:05:54.957422 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3115 11:05:54.961088 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3116 11:05:54.961195
3117 11:05:54.961286
3118 11:05:54.967546 [DQSOSCAuto] RK1, (LSB)MR18= 0xff6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3119 11:05:54.970832 CH0 RK1: MR19=403, MR18=FF6
3120 11:05:54.977533 CH0_RK1: MR19=0x403, MR18=0xFF6, DQSOSC=404, MR23=63, INC=40, DEC=26
3121 11:05:54.980815 [RxdqsGatingPostProcess] freq 1200
3122 11:05:54.984047 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3123 11:05:54.987315 best DQS0 dly(2T, 0.5T) = (0, 11)
3124 11:05:54.991049 best DQS1 dly(2T, 0.5T) = (0, 12)
3125 11:05:54.994271 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3126 11:05:54.997503 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3127 11:05:55.000735 best DQS0 dly(2T, 0.5T) = (0, 11)
3128 11:05:55.004408 best DQS1 dly(2T, 0.5T) = (0, 11)
3129 11:05:55.007318 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3130 11:05:55.010781 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3131 11:05:55.014042 Pre-setting of DQS Precalculation
3132 11:05:55.017492 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3133 11:05:55.020673 ==
3134 11:05:55.020772 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 11:05:55.027796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 11:05:55.027923 ==
3137 11:05:55.031066 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3138 11:05:55.037672 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3139 11:05:55.046249 [CA 0] Center 37 (7~68) winsize 62
3140 11:05:55.049805 [CA 1] Center 37 (7~68) winsize 62
3141 11:05:55.052882 [CA 2] Center 35 (5~65) winsize 61
3142 11:05:55.056268 [CA 3] Center 34 (4~65) winsize 62
3143 11:05:55.059552 [CA 4] Center 34 (4~65) winsize 62
3144 11:05:55.062976 [CA 5] Center 33 (3~64) winsize 62
3145 11:05:55.063062
3146 11:05:55.066509 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3147 11:05:55.066595
3148 11:05:55.070062 [CATrainingPosCal] consider 1 rank data
3149 11:05:55.073140 u2DelayCellTimex100 = 270/100 ps
3150 11:05:55.076509 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3151 11:05:55.079994 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3152 11:05:55.086705 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3153 11:05:55.089673 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3154 11:05:55.092995 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3155 11:05:55.096652 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3156 11:05:55.096738
3157 11:05:55.099936 CA PerBit enable=1, Macro0, CA PI delay=33
3158 11:05:55.100022
3159 11:05:55.103288 [CBTSetCACLKResult] CA Dly = 33
3160 11:05:55.103375 CS Dly: 5 (0~36)
3161 11:05:55.103443 ==
3162 11:05:55.106452 Dram Type= 6, Freq= 0, CH_1, rank 1
3163 11:05:55.113119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 11:05:55.113229 ==
3165 11:05:55.116879 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3166 11:05:55.123138 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3167 11:05:55.132108 [CA 0] Center 38 (8~68) winsize 61
3168 11:05:55.135489 [CA 1] Center 38 (7~69) winsize 63
3169 11:05:55.138772 [CA 2] Center 35 (5~66) winsize 62
3170 11:05:55.142182 [CA 3] Center 35 (5~65) winsize 61
3171 11:05:55.145717 [CA 4] Center 35 (5~65) winsize 61
3172 11:05:55.148766 [CA 5] Center 34 (4~64) winsize 61
3173 11:05:55.148880
3174 11:05:55.151982 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3175 11:05:55.152066
3176 11:05:55.155645 [CATrainingPosCal] consider 2 rank data
3177 11:05:55.158876 u2DelayCellTimex100 = 270/100 ps
3178 11:05:55.162179 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3179 11:05:55.165442 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3180 11:05:55.172559 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3181 11:05:55.175517 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3182 11:05:55.178963 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3183 11:05:55.181791 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3184 11:05:55.181875
3185 11:05:55.185736 CA PerBit enable=1, Macro0, CA PI delay=34
3186 11:05:55.185820
3187 11:05:55.188496 [CBTSetCACLKResult] CA Dly = 34
3188 11:05:55.188580 CS Dly: 6 (0~39)
3189 11:05:55.188646
3190 11:05:55.192115 ----->DramcWriteLeveling(PI) begin...
3191 11:05:55.195366 ==
3192 11:05:55.195492 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 11:05:55.201914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 11:05:55.202022 ==
3195 11:05:55.205246 Write leveling (Byte 0): 25 => 25
3196 11:05:55.208913 Write leveling (Byte 1): 28 => 28
3197 11:05:55.211893 DramcWriteLeveling(PI) end<-----
3198 11:05:55.211978
3199 11:05:55.212044 ==
3200 11:05:55.215246 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 11:05:55.218684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 11:05:55.218768 ==
3203 11:05:55.222385 [Gating] SW mode calibration
3204 11:05:55.228759 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3205 11:05:55.232072 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3206 11:05:55.238808 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 11:05:55.242089 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 11:05:55.245500 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 11:05:55.252194 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 11:05:55.255454 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 11:05:55.258903 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3212 11:05:55.265389 0 15 24 | B1->B0 | 2c2c 2525 | 1 1 | (1 1) (1 0)
3213 11:05:55.268929 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 11:05:55.272486 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 11:05:55.278879 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 11:05:55.282230 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 11:05:55.285702 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 11:05:55.289105 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 11:05:55.295928 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 11:05:55.299132 1 0 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3221 11:05:55.302456 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 11:05:55.308985 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 11:05:55.312198 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 11:05:55.315526 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 11:05:55.322480 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 11:05:55.325935 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 11:05:55.329157 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3228 11:05:55.335706 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3229 11:05:55.339087 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3230 11:05:55.342456 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 11:05:55.349181 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 11:05:55.352635 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 11:05:55.355893 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 11:05:55.362299 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 11:05:55.365681 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 11:05:55.369195 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 11:05:55.376030 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 11:05:55.378880 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 11:05:55.382259 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 11:05:55.385685 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 11:05:55.392838 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 11:05:55.395676 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 11:05:55.399107 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3244 11:05:55.405811 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3245 11:05:55.409110 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3246 11:05:55.412660 Total UI for P1: 0, mck2ui 16
3247 11:05:55.415939 best dqsien dly found for B0: ( 1, 3, 22)
3248 11:05:55.419069 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3249 11:05:55.422476 Total UI for P1: 0, mck2ui 16
3250 11:05:55.425750 best dqsien dly found for B1: ( 1, 3, 26)
3251 11:05:55.429484 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3252 11:05:55.432702 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3253 11:05:55.432802
3254 11:05:55.436022 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3255 11:05:55.442722 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3256 11:05:55.442799 [Gating] SW calibration Done
3257 11:05:55.442863 ==
3258 11:05:55.446396 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 11:05:55.452937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 11:05:55.453011 ==
3261 11:05:55.453077 RX Vref Scan: 0
3262 11:05:55.453137
3263 11:05:55.455980 RX Vref 0 -> 0, step: 1
3264 11:05:55.456051
3265 11:05:55.459762 RX Delay -40 -> 252, step: 8
3266 11:05:55.462659 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3267 11:05:55.466206 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3268 11:05:55.469292 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3269 11:05:55.475922 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3270 11:05:55.479529 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3271 11:05:55.482862 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3272 11:05:55.485881 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3273 11:05:55.489121 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3274 11:05:55.492548 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3275 11:05:55.499371 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3276 11:05:55.502989 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3277 11:05:55.506165 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3278 11:05:55.509582 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3279 11:05:55.512884 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3280 11:05:55.519351 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3281 11:05:55.522550 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3282 11:05:55.522637 ==
3283 11:05:55.526218 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 11:05:55.529502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 11:05:55.529588 ==
3286 11:05:55.532904 DQS Delay:
3287 11:05:55.532988 DQS0 = 0, DQS1 = 0
3288 11:05:55.533056 DQM Delay:
3289 11:05:55.535982 DQM0 = 119, DQM1 = 112
3290 11:05:55.536068 DQ Delay:
3291 11:05:55.539667 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3292 11:05:55.542860 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =123
3293 11:05:55.546125 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3294 11:05:55.552696 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3295 11:05:55.552780
3296 11:05:55.552846
3297 11:05:55.552907 ==
3298 11:05:55.556019 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 11:05:55.559768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 11:05:55.559852 ==
3301 11:05:55.559918
3302 11:05:55.559980
3303 11:05:55.562833 TX Vref Scan disable
3304 11:05:55.562917 == TX Byte 0 ==
3305 11:05:55.569679 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3306 11:05:55.572794 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3307 11:05:55.572877 == TX Byte 1 ==
3308 11:05:55.579590 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3309 11:05:55.583346 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3310 11:05:55.583425 ==
3311 11:05:55.586498 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 11:05:55.589579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 11:05:55.589689 ==
3314 11:05:55.601892 TX Vref=22, minBit 11, minWin=24, winSum=409
3315 11:05:55.605166 TX Vref=24, minBit 1, minWin=25, winSum=410
3316 11:05:55.608942 TX Vref=26, minBit 8, minWin=25, winSum=416
3317 11:05:55.611880 TX Vref=28, minBit 10, minWin=25, winSum=421
3318 11:05:55.615713 TX Vref=30, minBit 10, minWin=25, winSum=422
3319 11:05:55.622146 TX Vref=32, minBit 11, minWin=25, winSum=424
3320 11:05:55.625553 [TxChooseVref] Worse bit 11, Min win 25, Win sum 424, Final Vref 32
3321 11:05:55.625638
3322 11:05:55.628729 Final TX Range 1 Vref 32
3323 11:05:55.628814
3324 11:05:55.628881 ==
3325 11:05:55.632200 Dram Type= 6, Freq= 0, CH_1, rank 0
3326 11:05:55.635682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3327 11:05:55.639033 ==
3328 11:05:55.639118
3329 11:05:55.639184
3330 11:05:55.639245 TX Vref Scan disable
3331 11:05:55.642214 == TX Byte 0 ==
3332 11:05:55.645554 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3333 11:05:55.648849 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3334 11:05:55.652199 == TX Byte 1 ==
3335 11:05:55.655504 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3336 11:05:55.658795 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3337 11:05:55.662176
3338 11:05:55.662259 [DATLAT]
3339 11:05:55.662325 Freq=1200, CH1 RK0
3340 11:05:55.662388
3341 11:05:55.665452 DATLAT Default: 0xd
3342 11:05:55.665536 0, 0xFFFF, sum = 0
3343 11:05:55.669062 1, 0xFFFF, sum = 0
3344 11:05:55.669183 2, 0xFFFF, sum = 0
3345 11:05:55.672166 3, 0xFFFF, sum = 0
3346 11:05:55.672251 4, 0xFFFF, sum = 0
3347 11:05:55.675339 5, 0xFFFF, sum = 0
3348 11:05:55.678834 6, 0xFFFF, sum = 0
3349 11:05:55.678919 7, 0xFFFF, sum = 0
3350 11:05:55.682342 8, 0xFFFF, sum = 0
3351 11:05:55.682428 9, 0xFFFF, sum = 0
3352 11:05:55.685660 10, 0xFFFF, sum = 0
3353 11:05:55.685745 11, 0xFFFF, sum = 0
3354 11:05:55.688788 12, 0x0, sum = 1
3355 11:05:55.688873 13, 0x0, sum = 2
3356 11:05:55.692179 14, 0x0, sum = 3
3357 11:05:55.692266 15, 0x0, sum = 4
3358 11:05:55.692335 best_step = 13
3359 11:05:55.692413
3360 11:05:55.695511 ==
3361 11:05:55.698746 Dram Type= 6, Freq= 0, CH_1, rank 0
3362 11:05:55.702515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3363 11:05:55.702597 ==
3364 11:05:55.702661 RX Vref Scan: 1
3365 11:05:55.702721
3366 11:05:55.705334 Set Vref Range= 32 -> 127
3367 11:05:55.705417
3368 11:05:55.708861 RX Vref 32 -> 127, step: 1
3369 11:05:55.708958
3370 11:05:55.712446 RX Delay -13 -> 252, step: 4
3371 11:05:55.712528
3372 11:05:55.715749 Set Vref, RX VrefLevel [Byte0]: 32
3373 11:05:55.719096 [Byte1]: 32
3374 11:05:55.719177
3375 11:05:55.722246 Set Vref, RX VrefLevel [Byte0]: 33
3376 11:05:55.725538 [Byte1]: 33
3377 11:05:55.725649
3378 11:05:55.728831 Set Vref, RX VrefLevel [Byte0]: 34
3379 11:05:55.732376 [Byte1]: 34
3380 11:05:55.736677
3381 11:05:55.736758 Set Vref, RX VrefLevel [Byte0]: 35
3382 11:05:55.740009 [Byte1]: 35
3383 11:05:55.744294
3384 11:05:55.744376 Set Vref, RX VrefLevel [Byte0]: 36
3385 11:05:55.747850 [Byte1]: 36
3386 11:05:55.752204
3387 11:05:55.752286 Set Vref, RX VrefLevel [Byte0]: 37
3388 11:05:55.755493 [Byte1]: 37
3389 11:05:55.760312
3390 11:05:55.760394 Set Vref, RX VrefLevel [Byte0]: 38
3391 11:05:55.763642 [Byte1]: 38
3392 11:05:55.767840
3393 11:05:55.767922 Set Vref, RX VrefLevel [Byte0]: 39
3394 11:05:55.771183 [Byte1]: 39
3395 11:05:55.776049
3396 11:05:55.776131 Set Vref, RX VrefLevel [Byte0]: 40
3397 11:05:55.779178 [Byte1]: 40
3398 11:05:55.783645
3399 11:05:55.783727 Set Vref, RX VrefLevel [Byte0]: 41
3400 11:05:55.786926 [Byte1]: 41
3401 11:05:55.791591
3402 11:05:55.791688 Set Vref, RX VrefLevel [Byte0]: 42
3403 11:05:55.795155 [Byte1]: 42
3404 11:05:55.799746
3405 11:05:55.799827 Set Vref, RX VrefLevel [Byte0]: 43
3406 11:05:55.802656 [Byte1]: 43
3407 11:05:55.807436
3408 11:05:55.807518 Set Vref, RX VrefLevel [Byte0]: 44
3409 11:05:55.810712 [Byte1]: 44
3410 11:05:55.815152
3411 11:05:55.815232 Set Vref, RX VrefLevel [Byte0]: 45
3412 11:05:55.818591 [Byte1]: 45
3413 11:05:55.823251
3414 11:05:55.823334 Set Vref, RX VrefLevel [Byte0]: 46
3415 11:05:55.826383 [Byte1]: 46
3416 11:05:55.831348
3417 11:05:55.831430 Set Vref, RX VrefLevel [Byte0]: 47
3418 11:05:55.834617 [Byte1]: 47
3419 11:05:55.839150
3420 11:05:55.839231 Set Vref, RX VrefLevel [Byte0]: 48
3421 11:05:55.842534 [Byte1]: 48
3422 11:05:55.846763
3423 11:05:55.846844 Set Vref, RX VrefLevel [Byte0]: 49
3424 11:05:55.850379 [Byte1]: 49
3425 11:05:55.854840
3426 11:05:55.854921 Set Vref, RX VrefLevel [Byte0]: 50
3427 11:05:55.858291 [Byte1]: 50
3428 11:05:55.862562
3429 11:05:55.862644 Set Vref, RX VrefLevel [Byte0]: 51
3430 11:05:55.865896 [Byte1]: 51
3431 11:05:55.870649
3432 11:05:55.870745 Set Vref, RX VrefLevel [Byte0]: 52
3433 11:05:55.873839 [Byte1]: 52
3434 11:05:55.878278
3435 11:05:55.878360 Set Vref, RX VrefLevel [Byte0]: 53
3436 11:05:55.881521 [Byte1]: 53
3437 11:05:55.886511
3438 11:05:55.886588 Set Vref, RX VrefLevel [Byte0]: 54
3439 11:05:55.889751 [Byte1]: 54
3440 11:05:55.894028
3441 11:05:55.894109 Set Vref, RX VrefLevel [Byte0]: 55
3442 11:05:55.897699 [Byte1]: 55
3443 11:05:55.901933
3444 11:05:55.902037 Set Vref, RX VrefLevel [Byte0]: 56
3445 11:05:55.905330 [Byte1]: 56
3446 11:05:55.910155
3447 11:05:55.910236 Set Vref, RX VrefLevel [Byte0]: 57
3448 11:05:55.913101 [Byte1]: 57
3449 11:05:55.917918
3450 11:05:55.918010 Set Vref, RX VrefLevel [Byte0]: 58
3451 11:05:55.921160 [Byte1]: 58
3452 11:05:55.925815
3453 11:05:55.925922 Set Vref, RX VrefLevel [Byte0]: 59
3454 11:05:55.929198 [Byte1]: 59
3455 11:05:55.933818
3456 11:05:55.933930 Set Vref, RX VrefLevel [Byte0]: 60
3457 11:05:55.936803 [Byte1]: 60
3458 11:05:55.941680
3459 11:05:55.941783 Set Vref, RX VrefLevel [Byte0]: 61
3460 11:05:55.944550 [Byte1]: 61
3461 11:05:55.949228
3462 11:05:55.949337 Set Vref, RX VrefLevel [Byte0]: 62
3463 11:05:55.952532 [Byte1]: 62
3464 11:05:55.957232
3465 11:05:55.957331 Set Vref, RX VrefLevel [Byte0]: 63
3466 11:05:55.960632 [Byte1]: 63
3467 11:05:55.965202
3468 11:05:55.965308 Set Vref, RX VrefLevel [Byte0]: 64
3469 11:05:55.968241 [Byte1]: 64
3470 11:05:55.972996
3471 11:05:55.973084 Set Vref, RX VrefLevel [Byte0]: 65
3472 11:05:55.976268 [Byte1]: 65
3473 11:05:55.980900
3474 11:05:55.981000 Set Vref, RX VrefLevel [Byte0]: 66
3475 11:05:55.984303 [Byte1]: 66
3476 11:05:55.988836
3477 11:05:55.988936 Set Vref, RX VrefLevel [Byte0]: 67
3478 11:05:55.991960 [Byte1]: 67
3479 11:05:55.996519
3480 11:05:55.996622 Set Vref, RX VrefLevel [Byte0]: 68
3481 11:05:55.999977 [Byte1]: 68
3482 11:05:56.004455
3483 11:05:56.004559 Final RX Vref Byte 0 = 51 to rank0
3484 11:05:56.008257 Final RX Vref Byte 1 = 53 to rank0
3485 11:05:56.011505 Final RX Vref Byte 0 = 51 to rank1
3486 11:05:56.014871 Final RX Vref Byte 1 = 53 to rank1==
3487 11:05:56.018216 Dram Type= 6, Freq= 0, CH_1, rank 0
3488 11:05:56.021474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 11:05:56.024633 ==
3490 11:05:56.024725 DQS Delay:
3491 11:05:56.024816 DQS0 = 0, DQS1 = 0
3492 11:05:56.028055 DQM Delay:
3493 11:05:56.028156 DQM0 = 119, DQM1 = 112
3494 11:05:56.031193 DQ Delay:
3495 11:05:56.034526 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3496 11:05:56.038275 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3497 11:05:56.041648 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3498 11:05:56.044703 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =118
3499 11:05:56.044806
3500 11:05:56.044897
3501 11:05:56.051397 [DQSOSCAuto] RK0, (LSB)MR18= 0x317, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3502 11:05:56.054631 CH1 RK0: MR19=404, MR18=317
3503 11:05:56.061653 CH1_RK0: MR19=0x404, MR18=0x317, DQSOSC=401, MR23=63, INC=40, DEC=27
3504 11:05:56.061730
3505 11:05:56.064891 ----->DramcWriteLeveling(PI) begin...
3506 11:05:56.064968 ==
3507 11:05:56.068229 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 11:05:56.071617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 11:05:56.071706 ==
3510 11:05:56.074869 Write leveling (Byte 0): 25 => 25
3511 11:05:56.078128 Write leveling (Byte 1): 31 => 31
3512 11:05:56.081537 DramcWriteLeveling(PI) end<-----
3513 11:05:56.081612
3514 11:05:56.081675 ==
3515 11:05:56.084832 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 11:05:56.088094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 11:05:56.091732 ==
3518 11:05:56.091823 [Gating] SW mode calibration
3519 11:05:56.098175 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3520 11:05:56.105076 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3521 11:05:56.108208 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3522 11:05:56.114921 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 11:05:56.118182 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 11:05:56.121466 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3525 11:05:56.128564 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3526 11:05:56.131817 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3527 11:05:56.135252 0 15 24 | B1->B0 | 2d2d 3434 | 0 0 | (1 0) (0 1)
3528 11:05:56.141542 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (1 0) (0 1)
3529 11:05:56.145061 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 11:05:56.148696 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 11:05:56.151960 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 11:05:56.158559 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 11:05:56.161812 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3534 11:05:56.165021 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3535 11:05:56.171948 1 0 24 | B1->B0 | 3737 2626 | 1 1 | (0 0) (0 0)
3536 11:05:56.175282 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 11:05:56.178136 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 11:05:56.185177 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 11:05:56.188303 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 11:05:56.191482 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 11:05:56.198345 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 11:05:56.201502 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 11:05:56.204957 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3544 11:05:56.211738 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3545 11:05:56.214974 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 11:05:56.218121 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 11:05:56.224974 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 11:05:56.228085 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 11:05:56.231686 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 11:05:56.238287 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 11:05:56.241468 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 11:05:56.244767 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 11:05:56.251722 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 11:05:56.255109 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 11:05:56.258170 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 11:05:56.261660 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 11:05:56.268126 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 11:05:56.271565 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 11:05:56.274727 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3560 11:05:56.281335 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3561 11:05:56.285017 Total UI for P1: 0, mck2ui 16
3562 11:05:56.288323 best dqsien dly found for B0: ( 1, 3, 24)
3563 11:05:56.288408 Total UI for P1: 0, mck2ui 16
3564 11:05:56.294984 best dqsien dly found for B1: ( 1, 3, 24)
3565 11:05:56.298224 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3566 11:05:56.301386 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3567 11:05:56.301488
3568 11:05:56.304730 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3569 11:05:56.307997 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3570 11:05:56.311269 [Gating] SW calibration Done
3571 11:05:56.311353 ==
3572 11:05:56.314821 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 11:05:56.318080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 11:05:56.318165 ==
3575 11:05:56.321251 RX Vref Scan: 0
3576 11:05:56.321350
3577 11:05:56.321416 RX Vref 0 -> 0, step: 1
3578 11:05:56.321479
3579 11:05:56.324991 RX Delay -40 -> 252, step: 8
3580 11:05:56.328264 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3581 11:05:56.334986 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3582 11:05:56.338106 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3583 11:05:56.341491 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3584 11:05:56.344781 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3585 11:05:56.348342 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3586 11:05:56.354810 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3587 11:05:56.357843 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3588 11:05:56.361266 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3589 11:05:56.365024 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3590 11:05:56.367924 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3591 11:05:56.374827 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3592 11:05:56.378229 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3593 11:05:56.381200 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3594 11:05:56.384880 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3595 11:05:56.388287 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3596 11:05:56.391601 ==
3597 11:05:56.394606 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 11:05:56.397795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 11:05:56.397876 ==
3600 11:05:56.397963 DQS Delay:
3601 11:05:56.401295 DQS0 = 0, DQS1 = 0
3602 11:05:56.401367 DQM Delay:
3603 11:05:56.404640 DQM0 = 121, DQM1 = 113
3604 11:05:56.404711 DQ Delay:
3605 11:05:56.407663 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3606 11:05:56.411314 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3607 11:05:56.414554 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3608 11:05:56.418088 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =123
3609 11:05:56.418171
3610 11:05:56.418233
3611 11:05:56.418292 ==
3612 11:05:56.421245 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 11:05:56.427783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 11:05:56.427882 ==
3615 11:05:56.427946
3616 11:05:56.428012
3617 11:05:56.428075 TX Vref Scan disable
3618 11:05:56.431156 == TX Byte 0 ==
3619 11:05:56.434576 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3620 11:05:56.441391 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3621 11:05:56.441470 == TX Byte 1 ==
3622 11:05:56.444545 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3623 11:05:56.451114 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3624 11:05:56.451190 ==
3625 11:05:56.454631 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 11:05:56.457385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 11:05:56.457456 ==
3628 11:05:56.469640 TX Vref=22, minBit 1, minWin=25, winSum=419
3629 11:05:56.472581 TX Vref=24, minBit 1, minWin=25, winSum=420
3630 11:05:56.476088 TX Vref=26, minBit 3, minWin=25, winSum=426
3631 11:05:56.479600 TX Vref=28, minBit 1, minWin=26, winSum=427
3632 11:05:56.482706 TX Vref=30, minBit 1, minWin=26, winSum=431
3633 11:05:56.486153 TX Vref=32, minBit 2, minWin=26, winSum=429
3634 11:05:56.492887 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3635 11:05:56.492964
3636 11:05:56.496169 Final TX Range 1 Vref 30
3637 11:05:56.496244
3638 11:05:56.496308 ==
3639 11:05:56.499757 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 11:05:56.502796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 11:05:56.502873 ==
3642 11:05:56.505864
3643 11:05:56.505942
3644 11:05:56.506028 TX Vref Scan disable
3645 11:05:56.509444 == TX Byte 0 ==
3646 11:05:56.512597 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3647 11:05:56.519181 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3648 11:05:56.519276 == TX Byte 1 ==
3649 11:05:56.522290 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3650 11:05:56.525876 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3651 11:05:56.529055
3652 11:05:56.529142 [DATLAT]
3653 11:05:56.529210 Freq=1200, CH1 RK1
3654 11:05:56.529271
3655 11:05:56.532395 DATLAT Default: 0xd
3656 11:05:56.532483 0, 0xFFFF, sum = 0
3657 11:05:56.535784 1, 0xFFFF, sum = 0
3658 11:05:56.535871 2, 0xFFFF, sum = 0
3659 11:05:56.539110 3, 0xFFFF, sum = 0
3660 11:05:56.539178 4, 0xFFFF, sum = 0
3661 11:05:56.542339 5, 0xFFFF, sum = 0
3662 11:05:56.545871 6, 0xFFFF, sum = 0
3663 11:05:56.545954 7, 0xFFFF, sum = 0
3664 11:05:56.549186 8, 0xFFFF, sum = 0
3665 11:05:56.549254 9, 0xFFFF, sum = 0
3666 11:05:56.552533 10, 0xFFFF, sum = 0
3667 11:05:56.552603 11, 0xFFFF, sum = 0
3668 11:05:56.556214 12, 0x0, sum = 1
3669 11:05:56.556287 13, 0x0, sum = 2
3670 11:05:56.559087 14, 0x0, sum = 3
3671 11:05:56.559167 15, 0x0, sum = 4
3672 11:05:56.559228 best_step = 13
3673 11:05:56.559285
3674 11:05:56.562461 ==
3675 11:05:56.565625 Dram Type= 6, Freq= 0, CH_1, rank 1
3676 11:05:56.569373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3677 11:05:56.569463 ==
3678 11:05:56.569525 RX Vref Scan: 0
3679 11:05:56.569584
3680 11:05:56.572544 RX Vref 0 -> 0, step: 1
3681 11:05:56.572625
3682 11:05:56.575819 RX Delay -13 -> 252, step: 4
3683 11:05:56.579056 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3684 11:05:56.585706 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3685 11:05:56.588916 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3686 11:05:56.592214 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3687 11:05:56.595451 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3688 11:05:56.598819 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3689 11:05:56.605502 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3690 11:05:56.608702 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3691 11:05:56.612052 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3692 11:05:56.615438 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3693 11:05:56.618964 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3694 11:05:56.625522 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3695 11:05:56.628791 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3696 11:05:56.631884 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3697 11:05:56.635515 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3698 11:05:56.642233 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3699 11:05:56.642340 ==
3700 11:05:56.645428 Dram Type= 6, Freq= 0, CH_1, rank 1
3701 11:05:56.648446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3702 11:05:56.648566 ==
3703 11:05:56.648658 DQS Delay:
3704 11:05:56.651715 DQS0 = 0, DQS1 = 0
3705 11:05:56.651818 DQM Delay:
3706 11:05:56.655145 DQM0 = 119, DQM1 = 113
3707 11:05:56.655249 DQ Delay:
3708 11:05:56.658636 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3709 11:05:56.661750 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3710 11:05:56.665175 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3711 11:05:56.668357 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3712 11:05:56.668464
3713 11:05:56.668556
3714 11:05:56.678622 [DQSOSCAuto] RK1, (LSB)MR18= 0xcef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3715 11:05:56.681844 CH1 RK1: MR19=403, MR18=CEF
3716 11:05:56.685128 CH1_RK1: MR19=0x403, MR18=0xCEF, DQSOSC=405, MR23=63, INC=39, DEC=26
3717 11:05:56.688466 [RxdqsGatingPostProcess] freq 1200
3718 11:05:56.695247 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3719 11:05:56.698563 best DQS0 dly(2T, 0.5T) = (0, 11)
3720 11:05:56.701894 best DQS1 dly(2T, 0.5T) = (0, 11)
3721 11:05:56.705180 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3722 11:05:56.708144 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3723 11:05:56.711478 best DQS0 dly(2T, 0.5T) = (0, 11)
3724 11:05:56.714793 best DQS1 dly(2T, 0.5T) = (0, 11)
3725 11:05:56.718403 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3726 11:05:56.721582 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3727 11:05:56.724857 Pre-setting of DQS Precalculation
3728 11:05:56.728281 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3729 11:05:56.734869 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3730 11:05:56.741596 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3731 11:05:56.741703
3732 11:05:56.744886
3733 11:05:56.744991 [Calibration Summary] 2400 Mbps
3734 11:05:56.747789 CH 0, Rank 0
3735 11:05:56.747892 SW Impedance : PASS
3736 11:05:56.751319 DUTY Scan : NO K
3737 11:05:56.754732 ZQ Calibration : PASS
3738 11:05:56.754816 Jitter Meter : NO K
3739 11:05:56.757858 CBT Training : PASS
3740 11:05:56.761213 Write leveling : PASS
3741 11:05:56.761316 RX DQS gating : PASS
3742 11:05:56.764553 RX DQ/DQS(RDDQC) : PASS
3743 11:05:56.767760 TX DQ/DQS : PASS
3744 11:05:56.767864 RX DATLAT : PASS
3745 11:05:56.771096 RX DQ/DQS(Engine): PASS
3746 11:05:56.774679 TX OE : NO K
3747 11:05:56.774784 All Pass.
3748 11:05:56.774878
3749 11:05:56.774970 CH 0, Rank 1
3750 11:05:56.777913 SW Impedance : PASS
3751 11:05:56.781225 DUTY Scan : NO K
3752 11:05:56.781327 ZQ Calibration : PASS
3753 11:05:56.784705 Jitter Meter : NO K
3754 11:05:56.784807 CBT Training : PASS
3755 11:05:56.787823 Write leveling : PASS
3756 11:05:56.791172 RX DQS gating : PASS
3757 11:05:56.791261 RX DQ/DQS(RDDQC) : PASS
3758 11:05:56.794691 TX DQ/DQS : PASS
3759 11:05:56.798079 RX DATLAT : PASS
3760 11:05:56.798179 RX DQ/DQS(Engine): PASS
3761 11:05:56.801305 TX OE : NO K
3762 11:05:56.801405 All Pass.
3763 11:05:56.801497
3764 11:05:56.804704 CH 1, Rank 0
3765 11:05:56.804805 SW Impedance : PASS
3766 11:05:56.807964 DUTY Scan : NO K
3767 11:05:56.811194 ZQ Calibration : PASS
3768 11:05:56.811295 Jitter Meter : NO K
3769 11:05:56.814652 CBT Training : PASS
3770 11:05:56.817843 Write leveling : PASS
3771 11:05:56.817961 RX DQS gating : PASS
3772 11:05:56.821064 RX DQ/DQS(RDDQC) : PASS
3773 11:05:56.821168 TX DQ/DQS : PASS
3774 11:05:56.824739 RX DATLAT : PASS
3775 11:05:56.827997 RX DQ/DQS(Engine): PASS
3776 11:05:56.828113 TX OE : NO K
3777 11:05:56.831435 All Pass.
3778 11:05:56.831539
3779 11:05:56.831638 CH 1, Rank 1
3780 11:05:56.834377 SW Impedance : PASS
3781 11:05:56.834486 DUTY Scan : NO K
3782 11:05:56.837893 ZQ Calibration : PASS
3783 11:05:56.841462 Jitter Meter : NO K
3784 11:05:56.841554 CBT Training : PASS
3785 11:05:56.844452 Write leveling : PASS
3786 11:05:56.848026 RX DQS gating : PASS
3787 11:05:56.848111 RX DQ/DQS(RDDQC) : PASS
3788 11:05:56.851170 TX DQ/DQS : PASS
3789 11:05:56.854481 RX DATLAT : PASS
3790 11:05:56.854583 RX DQ/DQS(Engine): PASS
3791 11:05:56.857612 TX OE : NO K
3792 11:05:56.857713 All Pass.
3793 11:05:56.857810
3794 11:05:56.861024 DramC Write-DBI off
3795 11:05:56.864262 PER_BANK_REFRESH: Hybrid Mode
3796 11:05:56.864346 TX_TRACKING: ON
3797 11:05:56.874541 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3798 11:05:56.877846 [FAST_K] Save calibration result to emmc
3799 11:05:56.881075 dramc_set_vcore_voltage set vcore to 650000
3800 11:05:56.884522 Read voltage for 600, 5
3801 11:05:56.884628 Vio18 = 0
3802 11:05:56.884696 Vcore = 650000
3803 11:05:56.887790 Vdram = 0
3804 11:05:56.887874 Vddq = 0
3805 11:05:56.887940 Vmddr = 0
3806 11:05:56.894182 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3807 11:05:56.897575 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3808 11:05:56.900965 MEM_TYPE=3, freq_sel=19
3809 11:05:56.904410 sv_algorithm_assistance_LP4_1600
3810 11:05:56.907670 ============ PULL DRAM RESETB DOWN ============
3811 11:05:56.911048 ========== PULL DRAM RESETB DOWN end =========
3812 11:05:56.917552 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3813 11:05:56.920875 ===================================
3814 11:05:56.920960 LPDDR4 DRAM CONFIGURATION
3815 11:05:56.924128 ===================================
3816 11:05:56.927754 EX_ROW_EN[0] = 0x0
3817 11:05:56.930960 EX_ROW_EN[1] = 0x0
3818 11:05:56.931059 LP4Y_EN = 0x0
3819 11:05:56.933928 WORK_FSP = 0x0
3820 11:05:56.934066 WL = 0x2
3821 11:05:56.937562 RL = 0x2
3822 11:05:56.937738 BL = 0x2
3823 11:05:56.940570 RPST = 0x0
3824 11:05:56.940670 RD_PRE = 0x0
3825 11:05:56.944253 WR_PRE = 0x1
3826 11:05:56.944415 WR_PST = 0x0
3827 11:05:56.947331 DBI_WR = 0x0
3828 11:05:56.947478 DBI_RD = 0x0
3829 11:05:56.950875 OTF = 0x1
3830 11:05:56.953923 ===================================
3831 11:05:56.957246 ===================================
3832 11:05:56.957333 ANA top config
3833 11:05:56.960824 ===================================
3834 11:05:56.964017 DLL_ASYNC_EN = 0
3835 11:05:56.967639 ALL_SLAVE_EN = 1
3836 11:05:56.971031 NEW_RANK_MODE = 1
3837 11:05:56.971134 DLL_IDLE_MODE = 1
3838 11:05:56.974183 LP45_APHY_COMB_EN = 1
3839 11:05:56.977422 TX_ODT_DIS = 1
3840 11:05:56.980737 NEW_8X_MODE = 1
3841 11:05:56.984014 ===================================
3842 11:05:56.987443 ===================================
3843 11:05:56.990795 data_rate = 1200
3844 11:05:56.990881 CKR = 1
3845 11:05:56.994143 DQ_P2S_RATIO = 8
3846 11:05:56.997334 ===================================
3847 11:05:57.000618 CA_P2S_RATIO = 8
3848 11:05:57.003959 DQ_CA_OPEN = 0
3849 11:05:57.007279 DQ_SEMI_OPEN = 0
3850 11:05:57.007366 CA_SEMI_OPEN = 0
3851 11:05:57.010646 CA_FULL_RATE = 0
3852 11:05:57.013841 DQ_CKDIV4_EN = 1
3853 11:05:57.017323 CA_CKDIV4_EN = 1
3854 11:05:57.020712 CA_PREDIV_EN = 0
3855 11:05:57.023963 PH8_DLY = 0
3856 11:05:57.024050 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3857 11:05:57.027240 DQ_AAMCK_DIV = 4
3858 11:05:57.030656 CA_AAMCK_DIV = 4
3859 11:05:57.033886 CA_ADMCK_DIV = 4
3860 11:05:57.037213 DQ_TRACK_CA_EN = 0
3861 11:05:57.040439 CA_PICK = 600
3862 11:05:57.043986 CA_MCKIO = 600
3863 11:05:57.044073 MCKIO_SEMI = 0
3864 11:05:57.047178 PLL_FREQ = 2288
3865 11:05:57.050629 DQ_UI_PI_RATIO = 32
3866 11:05:57.054069 CA_UI_PI_RATIO = 0
3867 11:05:57.057071 ===================================
3868 11:05:57.060431 ===================================
3869 11:05:57.063735 memory_type:LPDDR4
3870 11:05:57.063818 GP_NUM : 10
3871 11:05:57.067195 SRAM_EN : 1
3872 11:05:57.067268 MD32_EN : 0
3873 11:05:57.070706 ===================================
3874 11:05:57.073653 [ANA_INIT] >>>>>>>>>>>>>>
3875 11:05:57.077065 <<<<<< [CONFIGURE PHASE]: ANA_TX
3876 11:05:57.080742 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3877 11:05:57.083490 ===================================
3878 11:05:57.087110 data_rate = 1200,PCW = 0X5800
3879 11:05:57.090299 ===================================
3880 11:05:57.093634 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3881 11:05:57.100251 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3882 11:05:57.103523 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3883 11:05:57.110664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3884 11:05:57.113934 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3885 11:05:57.117271 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3886 11:05:57.117384 [ANA_INIT] flow start
3887 11:05:57.120241 [ANA_INIT] PLL >>>>>>>>
3888 11:05:57.123542 [ANA_INIT] PLL <<<<<<<<
3889 11:05:57.123620 [ANA_INIT] MIDPI >>>>>>>>
3890 11:05:57.126901 [ANA_INIT] MIDPI <<<<<<<<
3891 11:05:57.130249 [ANA_INIT] DLL >>>>>>>>
3892 11:05:57.130338 [ANA_INIT] flow end
3893 11:05:57.137003 ============ LP4 DIFF to SE enter ============
3894 11:05:57.140228 ============ LP4 DIFF to SE exit ============
3895 11:05:57.143614 [ANA_INIT] <<<<<<<<<<<<<
3896 11:05:57.146920 [Flow] Enable top DCM control >>>>>
3897 11:05:57.150115 [Flow] Enable top DCM control <<<<<
3898 11:05:57.150191 Enable DLL master slave shuffle
3899 11:05:57.157085 ==============================================================
3900 11:05:57.160578 Gating Mode config
3901 11:05:57.163694 ==============================================================
3902 11:05:57.167097 Config description:
3903 11:05:57.176573 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3904 11:05:57.183244 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3905 11:05:57.186919 SELPH_MODE 0: By rank 1: By Phase
3906 11:05:57.193191 ==============================================================
3907 11:05:57.196470 GAT_TRACK_EN = 1
3908 11:05:57.199892 RX_GATING_MODE = 2
3909 11:05:57.203194 RX_GATING_TRACK_MODE = 2
3910 11:05:57.206595 SELPH_MODE = 1
3911 11:05:57.206668 PICG_EARLY_EN = 1
3912 11:05:57.209737 VALID_LAT_VALUE = 1
3913 11:05:57.216526 ==============================================================
3914 11:05:57.219913 Enter into Gating configuration >>>>
3915 11:05:57.223125 Exit from Gating configuration <<<<
3916 11:05:57.226647 Enter into DVFS_PRE_config >>>>>
3917 11:05:57.236694 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3918 11:05:57.239851 Exit from DVFS_PRE_config <<<<<
3919 11:05:57.243124 Enter into PICG configuration >>>>
3920 11:05:57.246368 Exit from PICG configuration <<<<
3921 11:05:57.249713 [RX_INPUT] configuration >>>>>
3922 11:05:57.252899 [RX_INPUT] configuration <<<<<
3923 11:05:57.256689 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3924 11:05:57.262881 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3925 11:05:57.269801 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3926 11:05:57.276270 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3927 11:05:57.282993 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3928 11:05:57.286476 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3929 11:05:57.293001 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3930 11:05:57.296447 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3931 11:05:57.299831 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3932 11:05:57.303036 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3933 11:05:57.309346 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3934 11:05:57.312766 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3935 11:05:57.316214 ===================================
3936 11:05:57.319688 LPDDR4 DRAM CONFIGURATION
3937 11:05:57.322768 ===================================
3938 11:05:57.322878 EX_ROW_EN[0] = 0x0
3939 11:05:57.326110 EX_ROW_EN[1] = 0x0
3940 11:05:57.326214 LP4Y_EN = 0x0
3941 11:05:57.329641 WORK_FSP = 0x0
3942 11:05:57.329726 WL = 0x2
3943 11:05:57.332964 RL = 0x2
3944 11:05:57.333049 BL = 0x2
3945 11:05:57.336118 RPST = 0x0
3946 11:05:57.336205 RD_PRE = 0x0
3947 11:05:57.339383 WR_PRE = 0x1
3948 11:05:57.339461 WR_PST = 0x0
3949 11:05:57.342725 DBI_WR = 0x0
3950 11:05:57.342806 DBI_RD = 0x0
3951 11:05:57.346424 OTF = 0x1
3952 11:05:57.349317 ===================================
3953 11:05:57.352720 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3954 11:05:57.356224 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3955 11:05:57.362913 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3956 11:05:57.366241 ===================================
3957 11:05:57.366343 LPDDR4 DRAM CONFIGURATION
3958 11:05:57.369560 ===================================
3959 11:05:57.372647 EX_ROW_EN[0] = 0x10
3960 11:05:57.376365 EX_ROW_EN[1] = 0x0
3961 11:05:57.376459 LP4Y_EN = 0x0
3962 11:05:57.379485 WORK_FSP = 0x0
3963 11:05:57.379588 WL = 0x2
3964 11:05:57.382533 RL = 0x2
3965 11:05:57.382601 BL = 0x2
3966 11:05:57.386241 RPST = 0x0
3967 11:05:57.386313 RD_PRE = 0x0
3968 11:05:57.389347 WR_PRE = 0x1
3969 11:05:57.389463 WR_PST = 0x0
3970 11:05:57.392882 DBI_WR = 0x0
3971 11:05:57.392989 DBI_RD = 0x0
3972 11:05:57.395807 OTF = 0x1
3973 11:05:57.399697 ===================================
3974 11:05:57.406190 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3975 11:05:57.409149 nWR fixed to 30
3976 11:05:57.412884 [ModeRegInit_LP4] CH0 RK0
3977 11:05:57.412999 [ModeRegInit_LP4] CH0 RK1
3978 11:05:57.416203 [ModeRegInit_LP4] CH1 RK0
3979 11:05:57.419530 [ModeRegInit_LP4] CH1 RK1
3980 11:05:57.419600 match AC timing 17
3981 11:05:57.426150 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3982 11:05:57.429358 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3983 11:05:57.432637 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3984 11:05:57.439492 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3985 11:05:57.442800 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3986 11:05:57.442877 ==
3987 11:05:57.446107 Dram Type= 6, Freq= 0, CH_0, rank 0
3988 11:05:57.449209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 11:05:57.449286 ==
3990 11:05:57.455876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3991 11:05:57.462324 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3992 11:05:57.465684 [CA 0] Center 36 (5~67) winsize 63
3993 11:05:57.469053 [CA 1] Center 36 (6~67) winsize 62
3994 11:05:57.472409 [CA 2] Center 34 (4~65) winsize 62
3995 11:05:57.475741 [CA 3] Center 34 (4~65) winsize 62
3996 11:05:57.478881 [CA 4] Center 33 (3~64) winsize 62
3997 11:05:57.482537 [CA 5] Center 33 (2~64) winsize 63
3998 11:05:57.482610
3999 11:05:57.485731 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4000 11:05:57.485801
4001 11:05:57.488992 [CATrainingPosCal] consider 1 rank data
4002 11:05:57.492519 u2DelayCellTimex100 = 270/100 ps
4003 11:05:57.495722 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4004 11:05:57.499154 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4005 11:05:57.502303 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4006 11:05:57.505705 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4007 11:05:57.509235 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4008 11:05:57.512574 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4009 11:05:57.512646
4010 11:05:57.518939 CA PerBit enable=1, Macro0, CA PI delay=33
4011 11:05:57.519013
4012 11:05:57.519073 [CBTSetCACLKResult] CA Dly = 33
4013 11:05:57.522198 CS Dly: 5 (0~36)
4014 11:05:57.522270 ==
4015 11:05:57.525528 Dram Type= 6, Freq= 0, CH_0, rank 1
4016 11:05:57.528842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4017 11:05:57.528928 ==
4018 11:05:57.535858 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4019 11:05:57.542315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4020 11:05:57.545710 [CA 0] Center 36 (6~67) winsize 62
4021 11:05:57.549127 [CA 1] Center 36 (6~67) winsize 62
4022 11:05:57.552270 [CA 2] Center 35 (4~66) winsize 63
4023 11:05:57.555638 [CA 3] Center 35 (4~66) winsize 63
4024 11:05:57.558745 [CA 4] Center 34 (3~65) winsize 63
4025 11:05:57.562058 [CA 5] Center 34 (3~65) winsize 63
4026 11:05:57.562136
4027 11:05:57.565275 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4028 11:05:57.565354
4029 11:05:57.569000 [CATrainingPosCal] consider 2 rank data
4030 11:05:57.571927 u2DelayCellTimex100 = 270/100 ps
4031 11:05:57.575620 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4032 11:05:57.578462 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4033 11:05:57.582217 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4034 11:05:57.585440 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4035 11:05:57.588795 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4036 11:05:57.592068 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4037 11:05:57.595655
4038 11:05:57.598511 CA PerBit enable=1, Macro0, CA PI delay=33
4039 11:05:57.598595
4040 11:05:57.602120 [CBTSetCACLKResult] CA Dly = 33
4041 11:05:57.602204 CS Dly: 5 (0~37)
4042 11:05:57.602270
4043 11:05:57.605111 ----->DramcWriteLeveling(PI) begin...
4044 11:05:57.605196 ==
4045 11:05:57.608637 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 11:05:57.612075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 11:05:57.615208 ==
4048 11:05:57.615287 Write leveling (Byte 0): 34 => 34
4049 11:05:57.618778 Write leveling (Byte 1): 30 => 30
4050 11:05:57.622032 DramcWriteLeveling(PI) end<-----
4051 11:05:57.622107
4052 11:05:57.622173 ==
4053 11:05:57.625313 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 11:05:57.632083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 11:05:57.632189 ==
4056 11:05:57.632282 [Gating] SW mode calibration
4057 11:05:57.642049 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4058 11:05:57.645120 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4059 11:05:57.648579 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4060 11:05:57.655101 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4061 11:05:57.658694 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4062 11:05:57.662067 0 9 12 | B1->B0 | 3333 2929 | 0 0 | (0 0) (0 1)
4063 11:05:57.668802 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
4064 11:05:57.672098 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 11:05:57.675442 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 11:05:57.681625 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 11:05:57.685391 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 11:05:57.688724 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 11:05:57.694920 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4070 11:05:57.698319 0 10 12 | B1->B0 | 2d2d 3b3b | 0 1 | (0 0) (1 1)
4071 11:05:57.701697 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4072 11:05:57.708482 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 11:05:57.711933 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 11:05:57.715243 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 11:05:57.721792 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 11:05:57.725184 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 11:05:57.728506 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 11:05:57.735065 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4079 11:05:57.738393 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4080 11:05:57.741661 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 11:05:57.748407 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 11:05:57.751445 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 11:05:57.755134 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 11:05:57.761437 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 11:05:57.764995 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 11:05:57.768496 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 11:05:57.771728 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 11:05:57.778370 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 11:05:57.781647 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 11:05:57.784889 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 11:05:57.791337 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 11:05:57.794747 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 11:05:57.798114 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 11:05:57.805018 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4095 11:05:57.808171 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4096 11:05:57.811337 Total UI for P1: 0, mck2ui 16
4097 11:05:57.814609 best dqsien dly found for B0: ( 0, 13, 12)
4098 11:05:57.818008 Total UI for P1: 0, mck2ui 16
4099 11:05:57.821497 best dqsien dly found for B1: ( 0, 13, 14)
4100 11:05:57.824687 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4101 11:05:57.827876 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4102 11:05:57.827961
4103 11:05:57.831397 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4104 11:05:57.834785 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4105 11:05:57.838097 [Gating] SW calibration Done
4106 11:05:57.838181 ==
4107 11:05:57.841398 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 11:05:57.847980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 11:05:57.848084 ==
4110 11:05:57.848166 RX Vref Scan: 0
4111 11:05:57.848225
4112 11:05:57.851353 RX Vref 0 -> 0, step: 1
4113 11:05:57.851436
4114 11:05:57.854786 RX Delay -230 -> 252, step: 16
4115 11:05:57.858066 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4116 11:05:57.860910 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4117 11:05:57.864660 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4118 11:05:57.871185 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4119 11:05:57.874379 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4120 11:05:57.877530 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4121 11:05:57.880898 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4122 11:05:57.887526 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4123 11:05:57.890782 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4124 11:05:57.894119 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4125 11:05:57.897536 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4126 11:05:57.900802 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4127 11:05:57.907565 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4128 11:05:57.910793 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4129 11:05:57.914070 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4130 11:05:57.917350 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4131 11:05:57.921045 ==
4132 11:05:57.924212 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 11:05:57.927643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 11:05:57.927750 ==
4135 11:05:57.927831 DQS Delay:
4136 11:05:57.930638 DQS0 = 0, DQS1 = 0
4137 11:05:57.930721 DQM Delay:
4138 11:05:57.934130 DQM0 = 47, DQM1 = 39
4139 11:05:57.934212 DQ Delay:
4140 11:05:57.937717 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4141 11:05:57.940736 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4142 11:05:57.944075 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4143 11:05:57.947371 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =41
4144 11:05:57.947480
4145 11:05:57.947547
4146 11:05:57.947607 ==
4147 11:05:57.950706 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 11:05:57.954047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 11:05:57.954130 ==
4150 11:05:57.954196
4151 11:05:57.954255
4152 11:05:57.957275 TX Vref Scan disable
4153 11:05:57.961103 == TX Byte 0 ==
4154 11:05:57.964091 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4155 11:05:57.967411 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4156 11:05:57.970552 == TX Byte 1 ==
4157 11:05:57.973959 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4158 11:05:57.977310 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4159 11:05:57.977410 ==
4160 11:05:57.980534 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 11:05:57.984153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 11:05:57.987136 ==
4163 11:05:57.987218
4164 11:05:57.987282
4165 11:05:57.987341 TX Vref Scan disable
4166 11:05:57.991369 == TX Byte 0 ==
4167 11:05:57.994550 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4168 11:05:58.001645 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4169 11:05:58.001747 == TX Byte 1 ==
4170 11:05:58.004419 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4171 11:05:58.011178 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4172 11:05:58.011278
4173 11:05:58.011367 [DATLAT]
4174 11:05:58.011463 Freq=600, CH0 RK0
4175 11:05:58.011551
4176 11:05:58.014658 DATLAT Default: 0x9
4177 11:05:58.014754 0, 0xFFFF, sum = 0
4178 11:05:58.018035 1, 0xFFFF, sum = 0
4179 11:05:58.018136 2, 0xFFFF, sum = 0
4180 11:05:58.021223 3, 0xFFFF, sum = 0
4181 11:05:58.024344 4, 0xFFFF, sum = 0
4182 11:05:58.024421 5, 0xFFFF, sum = 0
4183 11:05:58.028045 6, 0xFFFF, sum = 0
4184 11:05:58.028147 7, 0xFFFF, sum = 0
4185 11:05:58.031185 8, 0x0, sum = 1
4186 11:05:58.031302 9, 0x0, sum = 2
4187 11:05:58.031384 10, 0x0, sum = 3
4188 11:05:58.034725 11, 0x0, sum = 4
4189 11:05:58.034809 best_step = 9
4190 11:05:58.034925
4191 11:05:58.035018 ==
4192 11:05:58.037971 Dram Type= 6, Freq= 0, CH_0, rank 0
4193 11:05:58.044338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 11:05:58.044422 ==
4195 11:05:58.044488 RX Vref Scan: 1
4196 11:05:58.044547
4197 11:05:58.047803 RX Vref 0 -> 0, step: 1
4198 11:05:58.047887
4199 11:05:58.051155 RX Delay -179 -> 252, step: 8
4200 11:05:58.051249
4201 11:05:58.054574 Set Vref, RX VrefLevel [Byte0]: 59
4202 11:05:58.057814 [Byte1]: 49
4203 11:05:58.057899
4204 11:05:58.061209 Final RX Vref Byte 0 = 59 to rank0
4205 11:05:58.064488 Final RX Vref Byte 1 = 49 to rank0
4206 11:05:58.067793 Final RX Vref Byte 0 = 59 to rank1
4207 11:05:58.071123 Final RX Vref Byte 1 = 49 to rank1==
4208 11:05:58.074355 Dram Type= 6, Freq= 0, CH_0, rank 0
4209 11:05:58.077653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 11:05:58.077729 ==
4211 11:05:58.081205 DQS Delay:
4212 11:05:58.081288 DQS0 = 0, DQS1 = 0
4213 11:05:58.081352 DQM Delay:
4214 11:05:58.084442 DQM0 = 48, DQM1 = 39
4215 11:05:58.084546 DQ Delay:
4216 11:05:58.087760 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4217 11:05:58.091053 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4218 11:05:58.094293 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =36
4219 11:05:58.097632 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4220 11:05:58.097705
4221 11:05:58.097774
4222 11:05:58.107775 [DQSOSCAuto] RK0, (LSB)MR18= 0x5953, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4223 11:05:58.110975 CH0 RK0: MR19=808, MR18=5953
4224 11:05:58.114296 CH0_RK0: MR19=0x808, MR18=0x5953, DQSOSC=393, MR23=63, INC=169, DEC=113
4225 11:05:58.117373
4226 11:05:58.120816 ----->DramcWriteLeveling(PI) begin...
4227 11:05:58.120920 ==
4228 11:05:58.124064 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 11:05:58.127383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 11:05:58.127456 ==
4231 11:05:58.130896 Write leveling (Byte 0): 33 => 33
4232 11:05:58.134200 Write leveling (Byte 1): 29 => 29
4233 11:05:58.137583 DramcWriteLeveling(PI) end<-----
4234 11:05:58.137699
4235 11:05:58.137794 ==
4236 11:05:58.140752 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 11:05:58.144230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 11:05:58.144341 ==
4239 11:05:58.147516 [Gating] SW mode calibration
4240 11:05:58.154042 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4241 11:05:58.160761 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4242 11:05:58.164117 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4243 11:05:58.167520 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4244 11:05:58.173921 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4245 11:05:58.177546 0 9 12 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
4246 11:05:58.180995 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4247 11:05:58.184258 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 11:05:58.190681 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 11:05:58.193843 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 11:05:58.197200 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 11:05:58.204106 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 11:05:58.207234 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 11:05:58.210584 0 10 12 | B1->B0 | 2f2f 3333 | 0 1 | (0 0) (0 0)
4254 11:05:58.217197 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4255 11:05:58.220482 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 11:05:58.223827 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 11:05:58.230455 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 11:05:58.234133 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 11:05:58.237429 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 11:05:58.243923 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 11:05:58.247191 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 11:05:58.250524 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 11:05:58.257272 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 11:05:58.260362 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 11:05:58.263564 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 11:05:58.270677 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 11:05:58.273973 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 11:05:58.277253 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 11:05:58.283807 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 11:05:58.287156 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 11:05:58.290595 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 11:05:58.297025 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 11:05:58.300418 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 11:05:58.303814 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 11:05:58.307159 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 11:05:58.313897 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 11:05:58.317179 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4278 11:05:58.320510 Total UI for P1: 0, mck2ui 16
4279 11:05:58.323840 best dqsien dly found for B0: ( 0, 13, 10)
4280 11:05:58.327201 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4281 11:05:58.330400 Total UI for P1: 0, mck2ui 16
4282 11:05:58.333637 best dqsien dly found for B1: ( 0, 13, 12)
4283 11:05:58.337075 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4284 11:05:58.343606 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4285 11:05:58.343691
4286 11:05:58.347029 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4287 11:05:58.350221 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4288 11:05:58.353440 [Gating] SW calibration Done
4289 11:05:58.353569 ==
4290 11:05:58.357330 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 11:05:58.360173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 11:05:58.360286 ==
4293 11:05:58.360385 RX Vref Scan: 0
4294 11:05:58.363578
4295 11:05:58.363662 RX Vref 0 -> 0, step: 1
4296 11:05:58.363729
4297 11:05:58.366915 RX Delay -230 -> 252, step: 16
4298 11:05:58.370380 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4299 11:05:58.376739 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4300 11:05:58.380089 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4301 11:05:58.383479 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4302 11:05:58.386581 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4303 11:05:58.390079 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4304 11:05:58.396941 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4305 11:05:58.400239 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4306 11:05:58.403615 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4307 11:05:58.406921 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4308 11:05:58.413574 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4309 11:05:58.416753 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4310 11:05:58.420092 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4311 11:05:58.423358 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4312 11:05:58.430071 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4313 11:05:58.433442 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4314 11:05:58.433522 ==
4315 11:05:58.436742 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 11:05:58.440026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 11:05:58.440099 ==
4318 11:05:58.440160 DQS Delay:
4319 11:05:58.443339 DQS0 = 0, DQS1 = 0
4320 11:05:58.443408 DQM Delay:
4321 11:05:58.446579 DQM0 = 48, DQM1 = 42
4322 11:05:58.446647 DQ Delay:
4323 11:05:58.449816 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =41
4324 11:05:58.453351 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4325 11:05:58.457107 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4326 11:05:58.460262 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4327 11:05:58.460340
4328 11:05:58.460428
4329 11:05:58.460491 ==
4330 11:05:58.463373 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 11:05:58.466763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 11:05:58.470098 ==
4333 11:05:58.470182
4334 11:05:58.470249
4335 11:05:58.470311 TX Vref Scan disable
4336 11:05:58.473511 == TX Byte 0 ==
4337 11:05:58.476420 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4338 11:05:58.483139 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4339 11:05:58.483224 == TX Byte 1 ==
4340 11:05:58.486528 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4341 11:05:58.493038 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4342 11:05:58.493123 ==
4343 11:05:58.496295 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 11:05:58.500085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 11:05:58.500169 ==
4346 11:05:58.500237
4347 11:05:58.500299
4348 11:05:58.503333 TX Vref Scan disable
4349 11:05:58.506688 == TX Byte 0 ==
4350 11:05:58.509775 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4351 11:05:58.513076 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4352 11:05:58.516272 == TX Byte 1 ==
4353 11:05:58.519953 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4354 11:05:58.523194 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4355 11:05:58.523279
4356 11:05:58.523346 [DATLAT]
4357 11:05:58.526449 Freq=600, CH0 RK1
4358 11:05:58.526534
4359 11:05:58.526601 DATLAT Default: 0x9
4360 11:05:58.529674 0, 0xFFFF, sum = 0
4361 11:05:58.533048 1, 0xFFFF, sum = 0
4362 11:05:58.533132 2, 0xFFFF, sum = 0
4363 11:05:58.536347 3, 0xFFFF, sum = 0
4364 11:05:58.536431 4, 0xFFFF, sum = 0
4365 11:05:58.539754 5, 0xFFFF, sum = 0
4366 11:05:58.539837 6, 0xFFFF, sum = 0
4367 11:05:58.543024 7, 0xFFFF, sum = 0
4368 11:05:58.543107 8, 0x0, sum = 1
4369 11:05:58.546219 9, 0x0, sum = 2
4370 11:05:58.546303 10, 0x0, sum = 3
4371 11:05:58.546368 11, 0x0, sum = 4
4372 11:05:58.549645 best_step = 9
4373 11:05:58.549727
4374 11:05:58.549791 ==
4375 11:05:58.552881 Dram Type= 6, Freq= 0, CH_0, rank 1
4376 11:05:58.556539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 11:05:58.556623 ==
4378 11:05:58.559471 RX Vref Scan: 0
4379 11:05:58.559553
4380 11:05:58.559617 RX Vref 0 -> 0, step: 1
4381 11:05:58.559677
4382 11:05:58.563143 RX Delay -163 -> 252, step: 8
4383 11:05:58.570168 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4384 11:05:58.573789 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4385 11:05:58.577174 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4386 11:05:58.580378 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4387 11:05:58.583464 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4388 11:05:58.590486 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4389 11:05:58.593479 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4390 11:05:58.596774 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4391 11:05:58.599974 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4392 11:05:58.606892 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4393 11:05:58.609779 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4394 11:05:58.613131 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4395 11:05:58.616513 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4396 11:05:58.619821 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4397 11:05:58.626652 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4398 11:05:58.630145 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4399 11:05:58.630228 ==
4400 11:05:58.633276 Dram Type= 6, Freq= 0, CH_0, rank 1
4401 11:05:58.636462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 11:05:58.636545 ==
4403 11:05:58.639804 DQS Delay:
4404 11:05:58.639886 DQS0 = 0, DQS1 = 0
4405 11:05:58.643174 DQM Delay:
4406 11:05:58.643256 DQM0 = 48, DQM1 = 40
4407 11:05:58.643321 DQ Delay:
4408 11:05:58.646410 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4409 11:05:58.649739 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4410 11:05:58.653027 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4411 11:05:58.656387 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =44
4412 11:05:58.656470
4413 11:05:58.656534
4414 11:05:58.666325 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a36, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
4415 11:05:58.669566 CH0 RK1: MR19=808, MR18=6A36
4416 11:05:58.672888 CH0_RK1: MR19=0x808, MR18=0x6A36, DQSOSC=389, MR23=63, INC=173, DEC=115
4417 11:05:58.676130 [RxdqsGatingPostProcess] freq 600
4418 11:05:58.682771 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4419 11:05:58.686233 Pre-setting of DQS Precalculation
4420 11:05:58.689583 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4421 11:05:58.689665 ==
4422 11:05:58.692932 Dram Type= 6, Freq= 0, CH_1, rank 0
4423 11:05:58.699480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 11:05:58.699565 ==
4425 11:05:58.702906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4426 11:05:58.709463 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4427 11:05:58.712783 [CA 0] Center 35 (5~66) winsize 62
4428 11:05:58.716406 [CA 1] Center 35 (5~66) winsize 62
4429 11:05:58.719266 [CA 2] Center 34 (4~65) winsize 62
4430 11:05:58.722597 [CA 3] Center 33 (3~64) winsize 62
4431 11:05:58.726262 [CA 4] Center 34 (3~65) winsize 63
4432 11:05:58.729636 [CA 5] Center 33 (3~64) winsize 62
4433 11:05:58.729747
4434 11:05:58.733062 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4435 11:05:58.733146
4436 11:05:58.736315 [CATrainingPosCal] consider 1 rank data
4437 11:05:58.739632 u2DelayCellTimex100 = 270/100 ps
4438 11:05:58.742790 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4439 11:05:58.745871 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4440 11:05:58.752679 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4441 11:05:58.755964 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4442 11:05:58.759661 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4443 11:05:58.763017 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4444 11:05:58.763102
4445 11:05:58.766282 CA PerBit enable=1, Macro0, CA PI delay=33
4446 11:05:58.766366
4447 11:05:58.769405 [CBTSetCACLKResult] CA Dly = 33
4448 11:05:58.769490 CS Dly: 3 (0~34)
4449 11:05:58.772598 ==
4450 11:05:58.772682 Dram Type= 6, Freq= 0, CH_1, rank 1
4451 11:05:58.779498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 11:05:58.779583 ==
4453 11:05:58.782884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4454 11:05:58.789209 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4455 11:05:58.793109 [CA 0] Center 35 (5~66) winsize 62
4456 11:05:58.796481 [CA 1] Center 35 (5~66) winsize 62
4457 11:05:58.799517 [CA 2] Center 34 (4~65) winsize 62
4458 11:05:58.802994 [CA 3] Center 34 (4~64) winsize 61
4459 11:05:58.806466 [CA 4] Center 34 (4~65) winsize 62
4460 11:05:58.809418 [CA 5] Center 33 (3~64) winsize 62
4461 11:05:58.809501
4462 11:05:58.813113 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4463 11:05:58.813197
4464 11:05:58.816310 [CATrainingPosCal] consider 2 rank data
4465 11:05:58.819578 u2DelayCellTimex100 = 270/100 ps
4466 11:05:58.822837 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4467 11:05:58.826145 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4468 11:05:58.832666 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4469 11:05:58.836430 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4470 11:05:58.839728 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4471 11:05:58.842639 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4472 11:05:58.842723
4473 11:05:58.846033 CA PerBit enable=1, Macro0, CA PI delay=33
4474 11:05:58.846118
4475 11:05:58.849761 [CBTSetCACLKResult] CA Dly = 33
4476 11:05:58.849845 CS Dly: 4 (0~36)
4477 11:05:58.849912
4478 11:05:58.852684 ----->DramcWriteLeveling(PI) begin...
4479 11:05:58.855970 ==
4480 11:05:58.859369 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 11:05:58.862680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 11:05:58.862768 ==
4483 11:05:58.866107 Write leveling (Byte 0): 31 => 31
4484 11:05:58.869555 Write leveling (Byte 1): 31 => 31
4485 11:05:58.872847 DramcWriteLeveling(PI) end<-----
4486 11:05:58.872931
4487 11:05:58.872997 ==
4488 11:05:58.875877 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 11:05:58.879180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 11:05:58.879265 ==
4491 11:05:58.882606 [Gating] SW mode calibration
4492 11:05:58.889368 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4493 11:05:58.892758 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4494 11:05:58.899460 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4495 11:05:58.902855 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4496 11:05:58.906173 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4497 11:05:58.912835 0 9 12 | B1->B0 | 2d2d 2b2b | 0 0 | (0 0) (1 0)
4498 11:05:58.915735 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 11:05:58.919168 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 11:05:58.925854 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 11:05:58.929106 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 11:05:58.932861 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 11:05:58.939358 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 11:05:58.942932 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4505 11:05:58.945856 0 10 12 | B1->B0 | 3b3b 3f3f | 0 0 | (1 1) (0 0)
4506 11:05:58.952499 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 11:05:58.956195 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 11:05:58.959359 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 11:05:58.965958 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 11:05:58.969306 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 11:05:58.972643 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 11:05:58.979086 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 11:05:58.982794 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4514 11:05:58.985724 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 11:05:58.992891 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 11:05:58.996072 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 11:05:58.999475 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 11:05:59.002433 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 11:05:59.009070 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 11:05:59.012485 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 11:05:59.016011 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 11:05:59.022575 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 11:05:59.026094 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 11:05:59.029080 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 11:05:59.035905 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 11:05:59.039137 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 11:05:59.042396 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 11:05:59.049111 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4529 11:05:59.052642 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 11:05:59.055855 Total UI for P1: 0, mck2ui 16
4531 11:05:59.059257 best dqsien dly found for B0: ( 0, 13, 8)
4532 11:05:59.062629 Total UI for P1: 0, mck2ui 16
4533 11:05:59.065554 best dqsien dly found for B1: ( 0, 13, 10)
4534 11:05:59.069256 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4535 11:05:59.072611 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4536 11:05:59.072696
4537 11:05:59.075754 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4538 11:05:59.079165 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4539 11:05:59.082185 [Gating] SW calibration Done
4540 11:05:59.082269 ==
4541 11:05:59.085483 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 11:05:59.088746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 11:05:59.092092 ==
4544 11:05:59.092177 RX Vref Scan: 0
4545 11:05:59.092257
4546 11:05:59.095708 RX Vref 0 -> 0, step: 1
4547 11:05:59.095791
4548 11:05:59.099153 RX Delay -230 -> 252, step: 16
4549 11:05:59.102213 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4550 11:05:59.105576 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4551 11:05:59.108949 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4552 11:05:59.115699 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4553 11:05:59.118872 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4554 11:05:59.122182 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4555 11:05:59.125536 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4556 11:05:59.128958 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4557 11:05:59.135350 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4558 11:05:59.138767 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4559 11:05:59.141875 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4560 11:05:59.145437 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4561 11:05:59.152195 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4562 11:05:59.155386 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4563 11:05:59.158752 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4564 11:05:59.162321 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4565 11:05:59.162405 ==
4566 11:05:59.165686 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 11:05:59.172143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 11:05:59.172229 ==
4569 11:05:59.172295 DQS Delay:
4570 11:05:59.172372 DQS0 = 0, DQS1 = 0
4571 11:05:59.175533 DQM Delay:
4572 11:05:59.175618 DQM0 = 52, DQM1 = 44
4573 11:05:59.178865 DQ Delay:
4574 11:05:59.182147 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4575 11:05:59.185342 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4576 11:05:59.185448 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4577 11:05:59.192065 DQ12 =57, DQ13 =57, DQ14 =41, DQ15 =57
4578 11:05:59.192149
4579 11:05:59.192215
4580 11:05:59.192277 ==
4581 11:05:59.195707 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 11:05:59.198717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 11:05:59.198802 ==
4584 11:05:59.198869
4585 11:05:59.198930
4586 11:05:59.202189 TX Vref Scan disable
4587 11:05:59.202273 == TX Byte 0 ==
4588 11:05:59.208697 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4589 11:05:59.212032 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4590 11:05:59.212117 == TX Byte 1 ==
4591 11:05:59.218377 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4592 11:05:59.221811 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4593 11:05:59.221895 ==
4594 11:05:59.225313 Dram Type= 6, Freq= 0, CH_1, rank 0
4595 11:05:59.228342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 11:05:59.228476 ==
4597 11:05:59.228573
4598 11:05:59.231696
4599 11:05:59.231780 TX Vref Scan disable
4600 11:05:59.235219 == TX Byte 0 ==
4601 11:05:59.238616 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4602 11:05:59.241759 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4603 11:05:59.245141 == TX Byte 1 ==
4604 11:05:59.248376 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4605 11:05:59.254884 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4606 11:05:59.254968
4607 11:05:59.255034 [DATLAT]
4608 11:05:59.255096 Freq=600, CH1 RK0
4609 11:05:59.255157
4610 11:05:59.258158 DATLAT Default: 0x9
4611 11:05:59.258242 0, 0xFFFF, sum = 0
4612 11:05:59.261506 1, 0xFFFF, sum = 0
4613 11:05:59.261591 2, 0xFFFF, sum = 0
4614 11:05:59.264911 3, 0xFFFF, sum = 0
4615 11:05:59.265000 4, 0xFFFF, sum = 0
4616 11:05:59.268235 5, 0xFFFF, sum = 0
4617 11:05:59.271671 6, 0xFFFF, sum = 0
4618 11:05:59.271756 7, 0xFFFF, sum = 0
4619 11:05:59.271824 8, 0x0, sum = 1
4620 11:05:59.274945 9, 0x0, sum = 2
4621 11:05:59.275030 10, 0x0, sum = 3
4622 11:05:59.278178 11, 0x0, sum = 4
4623 11:05:59.278263 best_step = 9
4624 11:05:59.278330
4625 11:05:59.278391 ==
4626 11:05:59.281502 Dram Type= 6, Freq= 0, CH_1, rank 0
4627 11:05:59.288423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 11:05:59.288508 ==
4629 11:05:59.288574 RX Vref Scan: 1
4630 11:05:59.288637
4631 11:05:59.291670 RX Vref 0 -> 0, step: 1
4632 11:05:59.291755
4633 11:05:59.294888 RX Delay -163 -> 252, step: 8
4634 11:05:59.294972
4635 11:05:59.298170 Set Vref, RX VrefLevel [Byte0]: 51
4636 11:05:59.301376 [Byte1]: 53
4637 11:05:59.301484
4638 11:05:59.304734 Final RX Vref Byte 0 = 51 to rank0
4639 11:05:59.307902 Final RX Vref Byte 1 = 53 to rank0
4640 11:05:59.311481 Final RX Vref Byte 0 = 51 to rank1
4641 11:05:59.314895 Final RX Vref Byte 1 = 53 to rank1==
4642 11:05:59.318212 Dram Type= 6, Freq= 0, CH_1, rank 0
4643 11:05:59.321494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 11:05:59.321597 ==
4645 11:05:59.325111 DQS Delay:
4646 11:05:59.325237 DQS0 = 0, DQS1 = 0
4647 11:05:59.325322 DQM Delay:
4648 11:05:59.328049 DQM0 = 49, DQM1 = 41
4649 11:05:59.328155 DQ Delay:
4650 11:05:59.331586 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4651 11:05:59.334751 DQ4 =52, DQ5 =60, DQ6 =60, DQ7 =44
4652 11:05:59.338200 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =36
4653 11:05:59.341659 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =48
4654 11:05:59.341764
4655 11:05:59.341856
4656 11:05:59.351482 [DQSOSCAuto] RK0, (LSB)MR18= 0x476f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4657 11:05:59.351564 CH1 RK0: MR19=808, MR18=476F
4658 11:05:59.358181 CH1_RK0: MR19=0x808, MR18=0x476F, DQSOSC=389, MR23=63, INC=173, DEC=115
4659 11:05:59.358267
4660 11:05:59.361341 ----->DramcWriteLeveling(PI) begin...
4661 11:05:59.364805 ==
4662 11:05:59.368066 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 11:05:59.371398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 11:05:59.371474 ==
4665 11:05:59.374684 Write leveling (Byte 0): 29 => 29
4666 11:05:59.378107 Write leveling (Byte 1): 28 => 28
4667 11:05:59.381271 DramcWriteLeveling(PI) end<-----
4668 11:05:59.381345
4669 11:05:59.381406 ==
4670 11:05:59.384640 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 11:05:59.387907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 11:05:59.387981 ==
4673 11:05:59.391250 [Gating] SW mode calibration
4674 11:05:59.397932 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4675 11:05:59.401532 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4676 11:05:59.408219 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4677 11:05:59.411067 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4678 11:05:59.414307 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
4679 11:05:59.421138 0 9 12 | B1->B0 | 2e2e 3131 | 0 0 | (0 1) (0 1)
4680 11:05:59.424361 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 11:05:59.427888 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 11:05:59.434553 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 11:05:59.437878 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 11:05:59.441253 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 11:05:59.447572 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 11:05:59.450741 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
4687 11:05:59.454077 0 10 12 | B1->B0 | 3a3a 3030 | 0 0 | (0 0) (1 1)
4688 11:05:59.460791 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 11:05:59.464083 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 11:05:59.467633 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 11:05:59.474310 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 11:05:59.477751 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 11:05:59.480587 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 11:05:59.487423 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 11:05:59.490802 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4696 11:05:59.494191 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 11:05:59.500602 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 11:05:59.504061 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 11:05:59.507444 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 11:05:59.514054 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 11:05:59.517309 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 11:05:59.520665 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 11:05:59.527238 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 11:05:59.530892 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 11:05:59.533724 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 11:05:59.540477 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 11:05:59.543995 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 11:05:59.547372 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 11:05:59.553916 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 11:05:59.557155 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 11:05:59.560660 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4712 11:05:59.563636 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 11:05:59.567308 Total UI for P1: 0, mck2ui 16
4714 11:05:59.570389 best dqsien dly found for B0: ( 0, 13, 12)
4715 11:05:59.574082 Total UI for P1: 0, mck2ui 16
4716 11:05:59.577410 best dqsien dly found for B1: ( 0, 13, 12)
4717 11:05:59.580670 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4718 11:05:59.587245 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4719 11:05:59.587328
4720 11:05:59.590488 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4721 11:05:59.593790 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4722 11:05:59.597146 [Gating] SW calibration Done
4723 11:05:59.597272 ==
4724 11:05:59.600859 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 11:05:59.603824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 11:05:59.603908 ==
4727 11:05:59.603974 RX Vref Scan: 0
4728 11:05:59.604036
4729 11:05:59.607514 RX Vref 0 -> 0, step: 1
4730 11:05:59.607598
4731 11:05:59.610823 RX Delay -230 -> 252, step: 16
4732 11:05:59.614153 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4733 11:05:59.617431 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4734 11:05:59.624076 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4735 11:05:59.627433 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4736 11:05:59.630613 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4737 11:05:59.633863 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4738 11:05:59.637590 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4739 11:05:59.644102 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4740 11:05:59.647315 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4741 11:05:59.650399 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4742 11:05:59.654008 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4743 11:05:59.660277 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4744 11:05:59.663894 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4745 11:05:59.666845 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4746 11:05:59.670251 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4747 11:05:59.677193 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4748 11:05:59.677291 ==
4749 11:05:59.680260 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 11:05:59.683449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 11:05:59.683536 ==
4752 11:05:59.683602 DQS Delay:
4753 11:05:59.686750 DQS0 = 0, DQS1 = 0
4754 11:05:59.686834 DQM Delay:
4755 11:05:59.690110 DQM0 = 53, DQM1 = 50
4756 11:05:59.690192 DQ Delay:
4757 11:05:59.693463 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4758 11:05:59.696817 DQ4 =57, DQ5 =65, DQ6 =65, DQ7 =49
4759 11:05:59.700100 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4760 11:05:59.703376 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4761 11:05:59.703459
4762 11:05:59.703525
4763 11:05:59.703585 ==
4764 11:05:59.706803 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 11:05:59.710163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 11:05:59.710248 ==
4767 11:05:59.710313
4768 11:05:59.710373
4769 11:05:59.713447 TX Vref Scan disable
4770 11:05:59.716853 == TX Byte 0 ==
4771 11:05:59.720120 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4772 11:05:59.723391 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4773 11:05:59.726812 == TX Byte 1 ==
4774 11:05:59.730098 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4775 11:05:59.733442 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4776 11:05:59.733526 ==
4777 11:05:59.736740 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 11:05:59.743349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 11:05:59.743433 ==
4780 11:05:59.743498
4781 11:05:59.743559
4782 11:05:59.743618 TX Vref Scan disable
4783 11:05:59.747679 == TX Byte 0 ==
4784 11:05:59.750894 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4785 11:05:59.757431 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4786 11:05:59.757515 == TX Byte 1 ==
4787 11:05:59.760884 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4788 11:05:59.767701 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4789 11:05:59.767784
4790 11:05:59.767850 [DATLAT]
4791 11:05:59.767911 Freq=600, CH1 RK1
4792 11:05:59.767970
4793 11:05:59.771248 DATLAT Default: 0x9
4794 11:05:59.771331 0, 0xFFFF, sum = 0
4795 11:05:59.774232 1, 0xFFFF, sum = 0
4796 11:05:59.774316 2, 0xFFFF, sum = 0
4797 11:05:59.777590 3, 0xFFFF, sum = 0
4798 11:05:59.780779 4, 0xFFFF, sum = 0
4799 11:05:59.780864 5, 0xFFFF, sum = 0
4800 11:05:59.784207 6, 0xFFFF, sum = 0
4801 11:05:59.784292 7, 0xFFFF, sum = 0
4802 11:05:59.787561 8, 0x0, sum = 1
4803 11:05:59.787646 9, 0x0, sum = 2
4804 11:05:59.787714 10, 0x0, sum = 3
4805 11:05:59.790861 11, 0x0, sum = 4
4806 11:05:59.790947 best_step = 9
4807 11:05:59.791013
4808 11:05:59.791074 ==
4809 11:05:59.794130 Dram Type= 6, Freq= 0, CH_1, rank 1
4810 11:05:59.801162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4811 11:05:59.801274 ==
4812 11:05:59.801374 RX Vref Scan: 0
4813 11:05:59.801464
4814 11:05:59.804646 RX Vref 0 -> 0, step: 1
4815 11:05:59.804729
4816 11:05:59.807474 RX Delay -163 -> 252, step: 8
4817 11:05:59.811229 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4818 11:05:59.814314 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4819 11:05:59.820912 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4820 11:05:59.824269 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4821 11:05:59.827682 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4822 11:05:59.830946 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4823 11:05:59.834304 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4824 11:05:59.840993 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4825 11:05:59.844280 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4826 11:05:59.847395 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4827 11:05:59.850741 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4828 11:05:59.857792 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4829 11:05:59.860709 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4830 11:05:59.864119 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4831 11:05:59.867480 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4832 11:05:59.870625 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4833 11:05:59.874381 ==
4834 11:05:59.877466 Dram Type= 6, Freq= 0, CH_1, rank 1
4835 11:05:59.880679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4836 11:05:59.880764 ==
4837 11:05:59.880831 DQS Delay:
4838 11:05:59.884175 DQS0 = 0, DQS1 = 0
4839 11:05:59.884258 DQM Delay:
4840 11:05:59.887590 DQM0 = 49, DQM1 = 44
4841 11:05:59.887674 DQ Delay:
4842 11:05:59.891095 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =48
4843 11:05:59.894478 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4844 11:05:59.897501 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4845 11:05:59.901249 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =56
4846 11:05:59.901333
4847 11:05:59.901399
4848 11:05:59.907561 [DQSOSCAuto] RK1, (LSB)MR18= 0x551b, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4849 11:05:59.910938 CH1 RK1: MR19=808, MR18=551B
4850 11:05:59.917861 CH1_RK1: MR19=0x808, MR18=0x551B, DQSOSC=393, MR23=63, INC=169, DEC=113
4851 11:05:59.920761 [RxdqsGatingPostProcess] freq 600
4852 11:05:59.924194 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4853 11:05:59.927612 Pre-setting of DQS Precalculation
4854 11:05:59.934077 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4855 11:05:59.940629 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4856 11:05:59.947505 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4857 11:05:59.947590
4858 11:05:59.947656
4859 11:05:59.950771 [Calibration Summary] 1200 Mbps
4860 11:05:59.950855 CH 0, Rank 0
4861 11:05:59.954030 SW Impedance : PASS
4862 11:05:59.957289 DUTY Scan : NO K
4863 11:05:59.957401 ZQ Calibration : PASS
4864 11:05:59.961018 Jitter Meter : NO K
4865 11:05:59.964198 CBT Training : PASS
4866 11:05:59.964302 Write leveling : PASS
4867 11:05:59.967374 RX DQS gating : PASS
4868 11:05:59.971158 RX DQ/DQS(RDDQC) : PASS
4869 11:05:59.971237 TX DQ/DQS : PASS
4870 11:05:59.973999 RX DATLAT : PASS
4871 11:05:59.977700 RX DQ/DQS(Engine): PASS
4872 11:05:59.977806 TX OE : NO K
4873 11:05:59.977898 All Pass.
4874 11:05:59.980803
4875 11:05:59.980901 CH 0, Rank 1
4876 11:05:59.984095 SW Impedance : PASS
4877 11:05:59.984195 DUTY Scan : NO K
4878 11:05:59.987670 ZQ Calibration : PASS
4879 11:05:59.987778 Jitter Meter : NO K
4880 11:05:59.990894 CBT Training : PASS
4881 11:05:59.994052 Write leveling : PASS
4882 11:05:59.994135 RX DQS gating : PASS
4883 11:05:59.997138 RX DQ/DQS(RDDQC) : PASS
4884 11:06:00.000926 TX DQ/DQS : PASS
4885 11:06:00.001030 RX DATLAT : PASS
4886 11:06:00.003932 RX DQ/DQS(Engine): PASS
4887 11:06:00.007526 TX OE : NO K
4888 11:06:00.007627 All Pass.
4889 11:06:00.007717
4890 11:06:00.007814 CH 1, Rank 0
4891 11:06:00.010821 SW Impedance : PASS
4892 11:06:00.014132 DUTY Scan : NO K
4893 11:06:00.014207 ZQ Calibration : PASS
4894 11:06:00.017319 Jitter Meter : NO K
4895 11:06:00.021044 CBT Training : PASS
4896 11:06:00.021145 Write leveling : PASS
4897 11:06:00.024228 RX DQS gating : PASS
4898 11:06:00.024327 RX DQ/DQS(RDDQC) : PASS
4899 11:06:00.027588 TX DQ/DQS : PASS
4900 11:06:00.031058 RX DATLAT : PASS
4901 11:06:00.031134 RX DQ/DQS(Engine): PASS
4902 11:06:00.034381 TX OE : NO K
4903 11:06:00.034455 All Pass.
4904 11:06:00.034526
4905 11:06:00.037814 CH 1, Rank 1
4906 11:06:00.037912 SW Impedance : PASS
4907 11:06:00.040785 DUTY Scan : NO K
4908 11:06:00.044127 ZQ Calibration : PASS
4909 11:06:00.044227 Jitter Meter : NO K
4910 11:06:00.047659 CBT Training : PASS
4911 11:06:00.050896 Write leveling : PASS
4912 11:06:00.050975 RX DQS gating : PASS
4913 11:06:00.054188 RX DQ/DQS(RDDQC) : PASS
4914 11:06:00.057494 TX DQ/DQS : PASS
4915 11:06:00.057601 RX DATLAT : PASS
4916 11:06:00.060807 RX DQ/DQS(Engine): PASS
4917 11:06:00.064084 TX OE : NO K
4918 11:06:00.064184 All Pass.
4919 11:06:00.064281
4920 11:06:00.064371 DramC Write-DBI off
4921 11:06:00.067436 PER_BANK_REFRESH: Hybrid Mode
4922 11:06:00.070758 TX_TRACKING: ON
4923 11:06:00.077295 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4924 11:06:00.080659 [FAST_K] Save calibration result to emmc
4925 11:06:00.087196 dramc_set_vcore_voltage set vcore to 662500
4926 11:06:00.087286 Read voltage for 933, 3
4927 11:06:00.087350 Vio18 = 0
4928 11:06:00.090726 Vcore = 662500
4929 11:06:00.090826 Vdram = 0
4930 11:06:00.090923 Vddq = 0
4931 11:06:00.094048 Vmddr = 0
4932 11:06:00.097362 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4933 11:06:00.103806 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4934 11:06:00.107389 MEM_TYPE=3, freq_sel=17
4935 11:06:00.107553 sv_algorithm_assistance_LP4_1600
4936 11:06:00.114021 ============ PULL DRAM RESETB DOWN ============
4937 11:06:00.117090 ========== PULL DRAM RESETB DOWN end =========
4938 11:06:00.120479 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4939 11:06:00.123689 ===================================
4940 11:06:00.127229 LPDDR4 DRAM CONFIGURATION
4941 11:06:00.130523 ===================================
4942 11:06:00.133769 EX_ROW_EN[0] = 0x0
4943 11:06:00.133874 EX_ROW_EN[1] = 0x0
4944 11:06:00.137111 LP4Y_EN = 0x0
4945 11:06:00.137183 WORK_FSP = 0x0
4946 11:06:00.140452 WL = 0x3
4947 11:06:00.140521 RL = 0x3
4948 11:06:00.144092 BL = 0x2
4949 11:06:00.144176 RPST = 0x0
4950 11:06:00.147373 RD_PRE = 0x0
4951 11:06:00.147457 WR_PRE = 0x1
4952 11:06:00.150682 WR_PST = 0x0
4953 11:06:00.150766 DBI_WR = 0x0
4954 11:06:00.154052 DBI_RD = 0x0
4955 11:06:00.154136 OTF = 0x1
4956 11:06:00.157268 ===================================
4957 11:06:00.160558 ===================================
4958 11:06:00.163997 ANA top config
4959 11:06:00.167099 ===================================
4960 11:06:00.170463 DLL_ASYNC_EN = 0
4961 11:06:00.170568 ALL_SLAVE_EN = 1
4962 11:06:00.173785 NEW_RANK_MODE = 1
4963 11:06:00.176942 DLL_IDLE_MODE = 1
4964 11:06:00.180270 LP45_APHY_COMB_EN = 1
4965 11:06:00.183709 TX_ODT_DIS = 1
4966 11:06:00.183817 NEW_8X_MODE = 1
4967 11:06:00.187014 ===================================
4968 11:06:00.190464 ===================================
4969 11:06:00.193338 data_rate = 1866
4970 11:06:00.197074 CKR = 1
4971 11:06:00.200023 DQ_P2S_RATIO = 8
4972 11:06:00.203706 ===================================
4973 11:06:00.206706 CA_P2S_RATIO = 8
4974 11:06:00.210093 DQ_CA_OPEN = 0
4975 11:06:00.210178 DQ_SEMI_OPEN = 0
4976 11:06:00.213751 CA_SEMI_OPEN = 0
4977 11:06:00.216788 CA_FULL_RATE = 0
4978 11:06:00.220139 DQ_CKDIV4_EN = 1
4979 11:06:00.223307 CA_CKDIV4_EN = 1
4980 11:06:00.226460 CA_PREDIV_EN = 0
4981 11:06:00.226576 PH8_DLY = 0
4982 11:06:00.230341 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4983 11:06:00.233242 DQ_AAMCK_DIV = 4
4984 11:06:00.237042 CA_AAMCK_DIV = 4
4985 11:06:00.239853 CA_ADMCK_DIV = 4
4986 11:06:00.239937 DQ_TRACK_CA_EN = 0
4987 11:06:00.243321 CA_PICK = 933
4988 11:06:00.246766 CA_MCKIO = 933
4989 11:06:00.250113 MCKIO_SEMI = 0
4990 11:06:00.253395 PLL_FREQ = 3732
4991 11:06:00.256654 DQ_UI_PI_RATIO = 32
4992 11:06:00.259826 CA_UI_PI_RATIO = 0
4993 11:06:00.263221 ===================================
4994 11:06:00.266716 ===================================
4995 11:06:00.266800 memory_type:LPDDR4
4996 11:06:00.269837 GP_NUM : 10
4997 11:06:00.273160 SRAM_EN : 1
4998 11:06:00.273245 MD32_EN : 0
4999 11:06:00.276638 ===================================
5000 11:06:00.279952 [ANA_INIT] >>>>>>>>>>>>>>
5001 11:06:00.283164 <<<<<< [CONFIGURE PHASE]: ANA_TX
5002 11:06:00.286546 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5003 11:06:00.289856 ===================================
5004 11:06:00.293024 data_rate = 1866,PCW = 0X8f00
5005 11:06:00.296753 ===================================
5006 11:06:00.299667 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5007 11:06:00.303301 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5008 11:06:00.309845 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5009 11:06:00.312971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5010 11:06:00.316440 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5011 11:06:00.319859 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5012 11:06:00.323166 [ANA_INIT] flow start
5013 11:06:00.326557 [ANA_INIT] PLL >>>>>>>>
5014 11:06:00.326669 [ANA_INIT] PLL <<<<<<<<
5015 11:06:00.329923 [ANA_INIT] MIDPI >>>>>>>>
5016 11:06:00.333084 [ANA_INIT] MIDPI <<<<<<<<
5017 11:06:00.333169 [ANA_INIT] DLL >>>>>>>>
5018 11:06:00.336700 [ANA_INIT] flow end
5019 11:06:00.339941 ============ LP4 DIFF to SE enter ============
5020 11:06:00.346935 ============ LP4 DIFF to SE exit ============
5021 11:06:00.347019 [ANA_INIT] <<<<<<<<<<<<<
5022 11:06:00.349868 [Flow] Enable top DCM control >>>>>
5023 11:06:00.353149 [Flow] Enable top DCM control <<<<<
5024 11:06:00.356482 Enable DLL master slave shuffle
5025 11:06:00.363008 ==============================================================
5026 11:06:00.363092 Gating Mode config
5027 11:06:00.369762 ==============================================================
5028 11:06:00.372882 Config description:
5029 11:06:00.379480 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5030 11:06:00.386439 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5031 11:06:00.392656 SELPH_MODE 0: By rank 1: By Phase
5032 11:06:00.399716 ==============================================================
5033 11:06:00.399826 GAT_TRACK_EN = 1
5034 11:06:00.402970 RX_GATING_MODE = 2
5035 11:06:00.406147 RX_GATING_TRACK_MODE = 2
5036 11:06:00.409429 SELPH_MODE = 1
5037 11:06:00.412741 PICG_EARLY_EN = 1
5038 11:06:00.416203 VALID_LAT_VALUE = 1
5039 11:06:00.422794 ==============================================================
5040 11:06:00.425810 Enter into Gating configuration >>>>
5041 11:06:00.429308 Exit from Gating configuration <<<<
5042 11:06:00.432649 Enter into DVFS_PRE_config >>>>>
5043 11:06:00.442895 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5044 11:06:00.445797 Exit from DVFS_PRE_config <<<<<
5045 11:06:00.449197 Enter into PICG configuration >>>>
5046 11:06:00.452375 Exit from PICG configuration <<<<
5047 11:06:00.456091 [RX_INPUT] configuration >>>>>
5048 11:06:00.456195 [RX_INPUT] configuration <<<<<
5049 11:06:00.462530 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5050 11:06:00.469391 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5051 11:06:00.475966 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5052 11:06:00.479106 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5053 11:06:00.485724 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5054 11:06:00.492673 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5055 11:06:00.495682 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5056 11:06:00.498965 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5057 11:06:00.506050 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5058 11:06:00.508861 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5059 11:06:00.512237 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5060 11:06:00.518894 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5061 11:06:00.522868 ===================================
5062 11:06:00.522946 LPDDR4 DRAM CONFIGURATION
5063 11:06:00.525831 ===================================
5064 11:06:00.529191 EX_ROW_EN[0] = 0x0
5065 11:06:00.529271 EX_ROW_EN[1] = 0x0
5066 11:06:00.532296 LP4Y_EN = 0x0
5067 11:06:00.532401 WORK_FSP = 0x0
5068 11:06:00.535772 WL = 0x3
5069 11:06:00.535844 RL = 0x3
5070 11:06:00.538810 BL = 0x2
5071 11:06:00.542352 RPST = 0x0
5072 11:06:00.542436 RD_PRE = 0x0
5073 11:06:00.545676 WR_PRE = 0x1
5074 11:06:00.545758 WR_PST = 0x0
5075 11:06:00.549225 DBI_WR = 0x0
5076 11:06:00.549308 DBI_RD = 0x0
5077 11:06:00.552366 OTF = 0x1
5078 11:06:00.555562 ===================================
5079 11:06:00.559071 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5080 11:06:00.562156 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5081 11:06:00.565456 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5082 11:06:00.568780 ===================================
5083 11:06:00.572528 LPDDR4 DRAM CONFIGURATION
5084 11:06:00.575624 ===================================
5085 11:06:00.578894 EX_ROW_EN[0] = 0x10
5086 11:06:00.578977 EX_ROW_EN[1] = 0x0
5087 11:06:00.582224 LP4Y_EN = 0x0
5088 11:06:00.582308 WORK_FSP = 0x0
5089 11:06:00.585495 WL = 0x3
5090 11:06:00.585578 RL = 0x3
5091 11:06:00.588808 BL = 0x2
5092 11:06:00.588891 RPST = 0x0
5093 11:06:00.592635 RD_PRE = 0x0
5094 11:06:00.592719 WR_PRE = 0x1
5095 11:06:00.595747 WR_PST = 0x0
5096 11:06:00.598932 DBI_WR = 0x0
5097 11:06:00.599014 DBI_RD = 0x0
5098 11:06:00.602170 OTF = 0x1
5099 11:06:00.605485 ===================================
5100 11:06:00.608684 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5101 11:06:00.613895 nWR fixed to 30
5102 11:06:00.617578 [ModeRegInit_LP4] CH0 RK0
5103 11:06:00.617661 [ModeRegInit_LP4] CH0 RK1
5104 11:06:00.621101 [ModeRegInit_LP4] CH1 RK0
5105 11:06:00.623776 [ModeRegInit_LP4] CH1 RK1
5106 11:06:00.623860 match AC timing 9
5107 11:06:00.630863 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5108 11:06:00.634170 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5109 11:06:00.637510 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5110 11:06:00.643792 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5111 11:06:00.647138 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5112 11:06:00.647218 ==
5113 11:06:00.650263 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 11:06:00.653685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 11:06:00.653791 ==
5116 11:06:00.660366 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5117 11:06:00.667269 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5118 11:06:00.670620 [CA 0] Center 38 (7~69) winsize 63
5119 11:06:00.673713 [CA 1] Center 38 (8~69) winsize 62
5120 11:06:00.676945 [CA 2] Center 35 (5~66) winsize 62
5121 11:06:00.680107 [CA 3] Center 35 (5~65) winsize 61
5122 11:06:00.683461 [CA 4] Center 34 (4~65) winsize 62
5123 11:06:00.686738 [CA 5] Center 33 (3~64) winsize 62
5124 11:06:00.686818
5125 11:06:00.690037 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5126 11:06:00.690121
5127 11:06:00.693363 [CATrainingPosCal] consider 1 rank data
5128 11:06:00.696947 u2DelayCellTimex100 = 270/100 ps
5129 11:06:00.700066 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5130 11:06:00.703455 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5131 11:06:00.706756 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5132 11:06:00.709892 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5133 11:06:00.713320 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5134 11:06:00.720194 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5135 11:06:00.720306
5136 11:06:00.723536 CA PerBit enable=1, Macro0, CA PI delay=33
5137 11:06:00.723638
5138 11:06:00.726826 [CBTSetCACLKResult] CA Dly = 33
5139 11:06:00.726901 CS Dly: 7 (0~38)
5140 11:06:00.726973 ==
5141 11:06:00.730052 Dram Type= 6, Freq= 0, CH_0, rank 1
5142 11:06:00.733691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5143 11:06:00.737050 ==
5144 11:06:00.740400 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5145 11:06:00.746779 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5146 11:06:00.750422 [CA 0] Center 38 (8~69) winsize 62
5147 11:06:00.753253 [CA 1] Center 38 (8~69) winsize 62
5148 11:06:00.756918 [CA 2] Center 36 (6~67) winsize 62
5149 11:06:00.760128 [CA 3] Center 36 (5~67) winsize 63
5150 11:06:00.763650 [CA 4] Center 35 (4~66) winsize 63
5151 11:06:00.766922 [CA 5] Center 34 (4~65) winsize 62
5152 11:06:00.767020
5153 11:06:00.770202 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5154 11:06:00.770292
5155 11:06:00.773679 [CATrainingPosCal] consider 2 rank data
5156 11:06:00.776863 u2DelayCellTimex100 = 270/100 ps
5157 11:06:00.780231 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5158 11:06:00.783592 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5159 11:06:00.786947 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5160 11:06:00.790253 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5161 11:06:00.793677 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5162 11:06:00.800191 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5163 11:06:00.800268
5164 11:06:00.803289 CA PerBit enable=1, Macro0, CA PI delay=34
5165 11:06:00.803367
5166 11:06:00.806449 [CBTSetCACLKResult] CA Dly = 34
5167 11:06:00.806524 CS Dly: 7 (0~39)
5168 11:06:00.806597
5169 11:06:00.809806 ----->DramcWriteLeveling(PI) begin...
5170 11:06:00.809925 ==
5171 11:06:00.813475 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 11:06:00.819992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 11:06:00.820072 ==
5174 11:06:00.823326 Write leveling (Byte 0): 35 => 35
5175 11:06:00.823406 Write leveling (Byte 1): 31 => 31
5176 11:06:00.826649 DramcWriteLeveling(PI) end<-----
5177 11:06:00.826720
5178 11:06:00.829871 ==
5179 11:06:00.830008 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 11:06:00.836433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 11:06:00.836518 ==
5182 11:06:00.839891 [Gating] SW mode calibration
5183 11:06:00.846258 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5184 11:06:00.849731 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5185 11:06:00.856350 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5186 11:06:00.859909 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 11:06:00.862997 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 11:06:00.869539 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 11:06:00.873328 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 11:06:00.876167 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 11:06:00.883026 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
5192 11:06:00.886343 0 14 28 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
5193 11:06:00.889588 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5194 11:06:00.896072 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 11:06:00.899381 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 11:06:00.903089 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 11:06:00.909663 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 11:06:00.912999 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 11:06:00.916192 0 15 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5200 11:06:00.919451 0 15 28 | B1->B0 | 2424 4545 | 0 1 | (0 0) (0 0)
5201 11:06:00.926412 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 11:06:00.929373 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 11:06:00.933061 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 11:06:00.939553 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 11:06:00.942953 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 11:06:00.946314 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 11:06:00.952984 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5208 11:06:00.956026 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5209 11:06:00.959610 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 11:06:00.965895 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 11:06:00.969522 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 11:06:00.972584 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 11:06:00.979596 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 11:06:00.983090 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 11:06:00.986305 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 11:06:00.992845 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 11:06:00.996264 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 11:06:00.999467 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 11:06:01.006141 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 11:06:01.009333 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 11:06:01.012606 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 11:06:01.019192 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 11:06:01.022466 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 11:06:01.025842 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5225 11:06:01.029171 Total UI for P1: 0, mck2ui 16
5226 11:06:01.032581 best dqsien dly found for B0: ( 1, 2, 26)
5227 11:06:01.035938 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5228 11:06:01.039275 Total UI for P1: 0, mck2ui 16
5229 11:06:01.042459 best dqsien dly found for B1: ( 1, 2, 28)
5230 11:06:01.045960 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5231 11:06:01.052577 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5232 11:06:01.052661
5233 11:06:01.056045 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5234 11:06:01.059394 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5235 11:06:01.062581 [Gating] SW calibration Done
5236 11:06:01.062687 ==
5237 11:06:01.065882 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 11:06:01.069204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 11:06:01.069287 ==
5240 11:06:01.072579 RX Vref Scan: 0
5241 11:06:01.072662
5242 11:06:01.072729 RX Vref 0 -> 0, step: 1
5243 11:06:01.072791
5244 11:06:01.075613 RX Delay -80 -> 252, step: 8
5245 11:06:01.079077 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5246 11:06:01.085663 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5247 11:06:01.089001 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5248 11:06:01.092315 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5249 11:06:01.095709 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5250 11:06:01.099055 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5251 11:06:01.102297 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5252 11:06:01.109031 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5253 11:06:01.112773 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5254 11:06:01.115813 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5255 11:06:01.119065 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5256 11:06:01.122142 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5257 11:06:01.125750 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5258 11:06:01.129061 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5259 11:06:01.135856 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5260 11:06:01.139210 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5261 11:06:01.139294 ==
5262 11:06:01.142503 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 11:06:01.145858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 11:06:01.145953 ==
5265 11:06:01.146023 DQS Delay:
5266 11:06:01.149135 DQS0 = 0, DQS1 = 0
5267 11:06:01.149221 DQM Delay:
5268 11:06:01.152516 DQM0 = 105, DQM1 = 90
5269 11:06:01.152602 DQ Delay:
5270 11:06:01.155794 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5271 11:06:01.159171 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5272 11:06:01.162680 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5273 11:06:01.165735 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5274 11:06:01.165836
5275 11:06:01.165936
5276 11:06:01.166067 ==
5277 11:06:01.168997 Dram Type= 6, Freq= 0, CH_0, rank 0
5278 11:06:01.175676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 11:06:01.175786 ==
5280 11:06:01.175878
5281 11:06:01.176022
5282 11:06:01.176144 TX Vref Scan disable
5283 11:06:01.179033 == TX Byte 0 ==
5284 11:06:01.182686 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5285 11:06:01.189217 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5286 11:06:01.189322 == TX Byte 1 ==
5287 11:06:01.192374 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5288 11:06:01.199182 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5289 11:06:01.199262 ==
5290 11:06:01.202795 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 11:06:01.206116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 11:06:01.206202 ==
5293 11:06:01.206268
5294 11:06:01.206329
5295 11:06:01.209135 TX Vref Scan disable
5296 11:06:01.209220 == TX Byte 0 ==
5297 11:06:01.215388 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5298 11:06:01.218975 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5299 11:06:01.222089 == TX Byte 1 ==
5300 11:06:01.225424 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5301 11:06:01.228702 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5302 11:06:01.228830
5303 11:06:01.229002 [DATLAT]
5304 11:06:01.232372 Freq=933, CH0 RK0
5305 11:06:01.232482
5306 11:06:01.232573 DATLAT Default: 0xd
5307 11:06:01.235686 0, 0xFFFF, sum = 0
5308 11:06:01.235773 1, 0xFFFF, sum = 0
5309 11:06:01.238770 2, 0xFFFF, sum = 0
5310 11:06:01.242168 3, 0xFFFF, sum = 0
5311 11:06:01.242270 4, 0xFFFF, sum = 0
5312 11:06:01.245564 5, 0xFFFF, sum = 0
5313 11:06:01.245696 6, 0xFFFF, sum = 0
5314 11:06:01.248856 7, 0xFFFF, sum = 0
5315 11:06:01.248941 8, 0xFFFF, sum = 0
5316 11:06:01.252194 9, 0xFFFF, sum = 0
5317 11:06:01.252280 10, 0x0, sum = 1
5318 11:06:01.255814 11, 0x0, sum = 2
5319 11:06:01.255899 12, 0x0, sum = 3
5320 11:06:01.255966 13, 0x0, sum = 4
5321 11:06:01.259107 best_step = 11
5322 11:06:01.259192
5323 11:06:01.259259 ==
5324 11:06:01.262507 Dram Type= 6, Freq= 0, CH_0, rank 0
5325 11:06:01.265730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 11:06:01.265815 ==
5327 11:06:01.269098 RX Vref Scan: 1
5328 11:06:01.269182
5329 11:06:01.269249 RX Vref 0 -> 0, step: 1
5330 11:06:01.272428
5331 11:06:01.272511 RX Delay -53 -> 252, step: 4
5332 11:06:01.272579
5333 11:06:01.275712 Set Vref, RX VrefLevel [Byte0]: 59
5334 11:06:01.278868 [Byte1]: 49
5335 11:06:01.283258
5336 11:06:01.283342 Final RX Vref Byte 0 = 59 to rank0
5337 11:06:01.286636 Final RX Vref Byte 1 = 49 to rank0
5338 11:06:01.289773 Final RX Vref Byte 0 = 59 to rank1
5339 11:06:01.293188 Final RX Vref Byte 1 = 49 to rank1==
5340 11:06:01.296638 Dram Type= 6, Freq= 0, CH_0, rank 0
5341 11:06:01.303230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 11:06:01.303341 ==
5343 11:06:01.303437 DQS Delay:
5344 11:06:01.303530 DQS0 = 0, DQS1 = 0
5345 11:06:01.306224 DQM Delay:
5346 11:06:01.306309 DQM0 = 108, DQM1 = 91
5347 11:06:01.309651 DQ Delay:
5348 11:06:01.313137 DQ0 =106, DQ1 =108, DQ2 =106, DQ3 =106
5349 11:06:01.316531 DQ4 =108, DQ5 =98, DQ6 =118, DQ7 =114
5350 11:06:01.319836 DQ8 =86, DQ9 =78, DQ10 =90, DQ11 =90
5351 11:06:01.322936 DQ12 =96, DQ13 =92, DQ14 =100, DQ15 =100
5352 11:06:01.323020
5353 11:06:01.323086
5354 11:06:01.329606 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
5355 11:06:01.332910 CH0 RK0: MR19=505, MR18=2622
5356 11:06:01.339560 CH0_RK0: MR19=0x505, MR18=0x2622, DQSOSC=409, MR23=63, INC=64, DEC=43
5357 11:06:01.339663
5358 11:06:01.342845 ----->DramcWriteLeveling(PI) begin...
5359 11:06:01.342931 ==
5360 11:06:01.346187 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 11:06:01.349594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 11:06:01.349677 ==
5363 11:06:01.353115 Write leveling (Byte 0): 33 => 33
5364 11:06:01.356255 Write leveling (Byte 1): 31 => 31
5365 11:06:01.359449 DramcWriteLeveling(PI) end<-----
5366 11:06:01.359531
5367 11:06:01.359595 ==
5368 11:06:01.362713 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 11:06:01.369484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 11:06:01.369567 ==
5371 11:06:01.369631 [Gating] SW mode calibration
5372 11:06:01.379297 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5373 11:06:01.382530 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5374 11:06:01.385862 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 11:06:01.392669 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 11:06:01.395804 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 11:06:01.399216 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 11:06:01.405935 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 11:06:01.409494 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 11:06:01.412342 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5381 11:06:01.419195 0 14 28 | B1->B0 | 2f2f 2525 | 0 0 | (0 1) (0 0)
5382 11:06:01.422650 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 11:06:01.425715 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 11:06:01.432412 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 11:06:01.435700 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 11:06:01.438951 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 11:06:01.445607 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 11:06:01.449250 0 15 24 | B1->B0 | 2323 2c2c | 1 0 | (0 0) (0 0)
5389 11:06:01.452614 0 15 28 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
5390 11:06:01.459204 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 11:06:01.462431 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 11:06:01.465740 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 11:06:01.472108 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 11:06:01.475725 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 11:06:01.478925 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 11:06:01.485467 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 11:06:01.488925 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5398 11:06:01.492130 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5399 11:06:01.499053 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 11:06:01.502311 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 11:06:01.505884 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 11:06:01.509094 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 11:06:01.515893 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 11:06:01.519184 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 11:06:01.522741 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 11:06:01.528902 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 11:06:01.532521 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 11:06:01.535800 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 11:06:01.542385 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 11:06:01.545525 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 11:06:01.548794 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 11:06:01.555739 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 11:06:01.558798 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5414 11:06:01.562050 Total UI for P1: 0, mck2ui 16
5415 11:06:01.565408 best dqsien dly found for B0: ( 1, 2, 26)
5416 11:06:01.568860 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5417 11:06:01.572128 Total UI for P1: 0, mck2ui 16
5418 11:06:01.575592 best dqsien dly found for B1: ( 1, 2, 28)
5419 11:06:01.578774 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5420 11:06:01.582112 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5421 11:06:01.582194
5422 11:06:01.588632 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5423 11:06:01.591950 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5424 11:06:01.592032 [Gating] SW calibration Done
5425 11:06:01.595259 ==
5426 11:06:01.598552 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 11:06:01.601852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 11:06:01.601936 ==
5429 11:06:01.602038 RX Vref Scan: 0
5430 11:06:01.602099
5431 11:06:01.605111 RX Vref 0 -> 0, step: 1
5432 11:06:01.605220
5433 11:06:01.608698 RX Delay -80 -> 252, step: 8
5434 11:06:01.611790 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5435 11:06:01.614961 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5436 11:06:01.618649 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5437 11:06:01.625233 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5438 11:06:01.628805 iDelay=208, Bit 4, Center 111 (24 ~ 199) 176
5439 11:06:01.631735 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5440 11:06:01.635295 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5441 11:06:01.638677 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5442 11:06:01.641582 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5443 11:06:01.648576 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5444 11:06:01.651670 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5445 11:06:01.654940 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5446 11:06:01.658266 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5447 11:06:01.661967 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5448 11:06:01.664994 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5449 11:06:01.671823 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5450 11:06:01.671908 ==
5451 11:06:01.674988 Dram Type= 6, Freq= 0, CH_0, rank 1
5452 11:06:01.678237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5453 11:06:01.678321 ==
5454 11:06:01.678388 DQS Delay:
5455 11:06:01.681505 DQS0 = 0, DQS1 = 0
5456 11:06:01.681621 DQM Delay:
5457 11:06:01.684689 DQM0 = 105, DQM1 = 90
5458 11:06:01.684774 DQ Delay:
5459 11:06:01.688362 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5460 11:06:01.691881 DQ4 =111, DQ5 =95, DQ6 =115, DQ7 =115
5461 11:06:01.694675 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5462 11:06:01.698355 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5463 11:06:01.698439
5464 11:06:01.698505
5465 11:06:01.698566 ==
5466 11:06:01.701548 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 11:06:01.707965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 11:06:01.708051 ==
5469 11:06:01.708117
5470 11:06:01.708177
5471 11:06:01.708235 TX Vref Scan disable
5472 11:06:01.711471 == TX Byte 0 ==
5473 11:06:01.714731 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5474 11:06:01.721587 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5475 11:06:01.721672 == TX Byte 1 ==
5476 11:06:01.724714 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5477 11:06:01.731663 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5478 11:06:01.731751 ==
5479 11:06:01.734869 Dram Type= 6, Freq= 0, CH_0, rank 1
5480 11:06:01.737916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 11:06:01.738041 ==
5482 11:06:01.738109
5483 11:06:01.738168
5484 11:06:01.741245 TX Vref Scan disable
5485 11:06:01.741329 == TX Byte 0 ==
5486 11:06:01.747861 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5487 11:06:01.751079 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5488 11:06:01.751164 == TX Byte 1 ==
5489 11:06:01.758021 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5490 11:06:01.761399 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5491 11:06:01.761483
5492 11:06:01.761550 [DATLAT]
5493 11:06:01.764582 Freq=933, CH0 RK1
5494 11:06:01.764666
5495 11:06:01.764732 DATLAT Default: 0xb
5496 11:06:01.767917 0, 0xFFFF, sum = 0
5497 11:06:01.768004 1, 0xFFFF, sum = 0
5498 11:06:01.771277 2, 0xFFFF, sum = 0
5499 11:06:01.771362 3, 0xFFFF, sum = 0
5500 11:06:01.774484 4, 0xFFFF, sum = 0
5501 11:06:01.774596 5, 0xFFFF, sum = 0
5502 11:06:01.777763 6, 0xFFFF, sum = 0
5503 11:06:01.781061 7, 0xFFFF, sum = 0
5504 11:06:01.781147 8, 0xFFFF, sum = 0
5505 11:06:01.784368 9, 0xFFFF, sum = 0
5506 11:06:01.784454 10, 0x0, sum = 1
5507 11:06:01.784521 11, 0x0, sum = 2
5508 11:06:01.787759 12, 0x0, sum = 3
5509 11:06:01.787844 13, 0x0, sum = 4
5510 11:06:01.790893 best_step = 11
5511 11:06:01.790977
5512 11:06:01.791043 ==
5513 11:06:01.794602 Dram Type= 6, Freq= 0, CH_0, rank 1
5514 11:06:01.797439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 11:06:01.797552 ==
5516 11:06:01.801188 RX Vref Scan: 0
5517 11:06:01.801302
5518 11:06:01.801397 RX Vref 0 -> 0, step: 1
5519 11:06:01.804255
5520 11:06:01.804339 RX Delay -53 -> 252, step: 4
5521 11:06:01.812067 iDelay=203, Bit 0, Center 104 (19 ~ 190) 172
5522 11:06:01.815066 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5523 11:06:01.818188 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5524 11:06:01.821765 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5525 11:06:01.825257 iDelay=203, Bit 4, Center 104 (19 ~ 190) 172
5526 11:06:01.831480 iDelay=203, Bit 5, Center 98 (11 ~ 186) 176
5527 11:06:01.835131 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5528 11:06:01.838649 iDelay=203, Bit 7, Center 110 (23 ~ 198) 176
5529 11:06:01.841917 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5530 11:06:01.844900 iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164
5531 11:06:01.851418 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5532 11:06:01.854788 iDelay=203, Bit 11, Center 90 (7 ~ 174) 168
5533 11:06:01.858132 iDelay=203, Bit 12, Center 98 (15 ~ 182) 168
5534 11:06:01.861969 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5535 11:06:01.864999 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5536 11:06:01.868354 iDelay=203, Bit 15, Center 98 (15 ~ 182) 168
5537 11:06:01.871521 ==
5538 11:06:01.874876 Dram Type= 6, Freq= 0, CH_0, rank 1
5539 11:06:01.878101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5540 11:06:01.878189 ==
5541 11:06:01.878305 DQS Delay:
5542 11:06:01.881767 DQS0 = 0, DQS1 = 0
5543 11:06:01.881875 DQM Delay:
5544 11:06:01.885262 DQM0 = 104, DQM1 = 92
5545 11:06:01.885365 DQ Delay:
5546 11:06:01.888098 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5547 11:06:01.891590 DQ4 =104, DQ5 =98, DQ6 =114, DQ7 =110
5548 11:06:01.894983 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =90
5549 11:06:01.898661 DQ12 =98, DQ13 =94, DQ14 =100, DQ15 =98
5550 11:06:01.898747
5551 11:06:01.898833
5552 11:06:01.904862 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5553 11:06:01.908217 CH0 RK1: MR19=505, MR18=2C0C
5554 11:06:01.914930 CH0_RK1: MR19=0x505, MR18=0x2C0C, DQSOSC=408, MR23=63, INC=65, DEC=43
5555 11:06:01.918182 [RxdqsGatingPostProcess] freq 933
5556 11:06:01.925068 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5557 11:06:01.928135 best DQS0 dly(2T, 0.5T) = (0, 10)
5558 11:06:01.928222 best DQS1 dly(2T, 0.5T) = (0, 10)
5559 11:06:01.931400 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5560 11:06:01.935062 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5561 11:06:01.938286 best DQS0 dly(2T, 0.5T) = (0, 10)
5562 11:06:01.941532 best DQS1 dly(2T, 0.5T) = (0, 10)
5563 11:06:01.945133 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5564 11:06:01.948292 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5565 11:06:01.951444 Pre-setting of DQS Precalculation
5566 11:06:01.958106 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5567 11:06:01.958193 ==
5568 11:06:01.961359 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 11:06:01.964667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 11:06:01.964754 ==
5571 11:06:01.971426 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5572 11:06:01.974728 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5573 11:06:01.979133 [CA 0] Center 37 (7~68) winsize 62
5574 11:06:01.982345 [CA 1] Center 37 (7~68) winsize 62
5575 11:06:01.985613 [CA 2] Center 36 (6~66) winsize 61
5576 11:06:01.988841 [CA 3] Center 34 (4~65) winsize 62
5577 11:06:01.992100 [CA 4] Center 35 (5~65) winsize 61
5578 11:06:01.995578 [CA 5] Center 34 (4~65) winsize 62
5579 11:06:01.995664
5580 11:06:01.999164 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5581 11:06:01.999251
5582 11:06:02.002470 [CATrainingPosCal] consider 1 rank data
5583 11:06:02.005793 u2DelayCellTimex100 = 270/100 ps
5584 11:06:02.009095 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5585 11:06:02.012444 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5586 11:06:02.018980 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5587 11:06:02.022290 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5588 11:06:02.025642 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5589 11:06:02.029153 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5590 11:06:02.029240
5591 11:06:02.032286 CA PerBit enable=1, Macro0, CA PI delay=34
5592 11:06:02.032389
5593 11:06:02.035613 [CBTSetCACLKResult] CA Dly = 34
5594 11:06:02.035700 CS Dly: 6 (0~37)
5595 11:06:02.035786 ==
5596 11:06:02.039165 Dram Type= 6, Freq= 0, CH_1, rank 1
5597 11:06:02.045720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5598 11:06:02.045821 ==
5599 11:06:02.049251 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5600 11:06:02.055343 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5601 11:06:02.058937 [CA 0] Center 38 (8~69) winsize 62
5602 11:06:02.062271 [CA 1] Center 38 (7~69) winsize 63
5603 11:06:02.065602 [CA 2] Center 36 (6~66) winsize 61
5604 11:06:02.068776 [CA 3] Center 36 (6~66) winsize 61
5605 11:06:02.072183 [CA 4] Center 35 (6~65) winsize 60
5606 11:06:02.075515 [CA 5] Center 35 (5~65) winsize 61
5607 11:06:02.075601
5608 11:06:02.078855 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5609 11:06:02.078941
5610 11:06:02.082248 [CATrainingPosCal] consider 2 rank data
5611 11:06:02.085470 u2DelayCellTimex100 = 270/100 ps
5612 11:06:02.089107 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5613 11:06:02.092425 CA1 delay=37 (7~68),Diff = 2 PI (12 cell)
5614 11:06:02.099115 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5615 11:06:02.102469 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
5616 11:06:02.105597 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
5617 11:06:02.108916 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5618 11:06:02.109002
5619 11:06:02.112249 CA PerBit enable=1, Macro0, CA PI delay=35
5620 11:06:02.112338
5621 11:06:02.115589 [CBTSetCACLKResult] CA Dly = 35
5622 11:06:02.115675 CS Dly: 7 (0~39)
5623 11:06:02.115761
5624 11:06:02.118587 ----->DramcWriteLeveling(PI) begin...
5625 11:06:02.121954 ==
5626 11:06:02.125681 Dram Type= 6, Freq= 0, CH_1, rank 0
5627 11:06:02.128573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5628 11:06:02.128660 ==
5629 11:06:02.132310 Write leveling (Byte 0): 25 => 25
5630 11:06:02.135689 Write leveling (Byte 1): 31 => 31
5631 11:06:02.138867 DramcWriteLeveling(PI) end<-----
5632 11:06:02.138951
5633 11:06:02.139017 ==
5634 11:06:02.141899 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 11:06:02.145443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 11:06:02.145528 ==
5637 11:06:02.148738 [Gating] SW mode calibration
5638 11:06:02.155330 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5639 11:06:02.162215 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5640 11:06:02.165290 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 11:06:02.168882 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 11:06:02.172168 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 11:06:02.178797 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5644 11:06:02.182129 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 11:06:02.185559 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 11:06:02.192092 0 14 24 | B1->B0 | 3232 2e2e | 0 1 | (0 1) (1 0)
5647 11:06:02.195449 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 11:06:02.198902 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 11:06:02.205379 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 11:06:02.209043 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 11:06:02.211989 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 11:06:02.218725 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 11:06:02.222080 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 11:06:02.225303 0 15 24 | B1->B0 | 2b2b 2e2e | 0 0 | (0 0) (1 1)
5655 11:06:02.231944 0 15 28 | B1->B0 | 3f3f 4242 | 0 1 | (0 0) (0 0)
5656 11:06:02.235146 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 11:06:02.238723 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 11:06:02.245488 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 11:06:02.248952 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 11:06:02.252069 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 11:06:02.258699 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 11:06:02.261876 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5663 11:06:02.265389 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 11:06:02.271849 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 11:06:02.275260 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 11:06:02.278469 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 11:06:02.285025 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 11:06:02.288388 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 11:06:02.291854 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 11:06:02.295129 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 11:06:02.301704 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 11:06:02.305059 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 11:06:02.308380 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 11:06:02.315289 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 11:06:02.318653 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 11:06:02.321968 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 11:06:02.328577 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 11:06:02.331965 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5679 11:06:02.335070 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 11:06:02.338396 Total UI for P1: 0, mck2ui 16
5681 11:06:02.341826 best dqsien dly found for B0: ( 1, 2, 24)
5682 11:06:02.344861 Total UI for P1: 0, mck2ui 16
5683 11:06:02.348540 best dqsien dly found for B1: ( 1, 2, 26)
5684 11:06:02.351723 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5685 11:06:02.354921 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5686 11:06:02.355006
5687 11:06:02.361397 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5688 11:06:02.364770 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5689 11:06:02.368207 [Gating] SW calibration Done
5690 11:06:02.368291 ==
5691 11:06:02.371412 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 11:06:02.374858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 11:06:02.374943 ==
5694 11:06:02.375010 RX Vref Scan: 0
5695 11:06:02.375071
5696 11:06:02.378103 RX Vref 0 -> 0, step: 1
5697 11:06:02.378187
5698 11:06:02.381193 RX Delay -80 -> 252, step: 8
5699 11:06:02.384507 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5700 11:06:02.388147 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5701 11:06:02.391169 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5702 11:06:02.398057 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5703 11:06:02.401127 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5704 11:06:02.404362 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5705 11:06:02.407728 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5706 11:06:02.411061 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5707 11:06:02.414752 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5708 11:06:02.421082 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5709 11:06:02.424404 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5710 11:06:02.427809 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5711 11:06:02.431060 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5712 11:06:02.434381 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5713 11:06:02.441087 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5714 11:06:02.444418 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5715 11:06:02.444503 ==
5716 11:06:02.447735 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 11:06:02.450942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 11:06:02.451027 ==
5719 11:06:02.451093 DQS Delay:
5720 11:06:02.454520 DQS0 = 0, DQS1 = 0
5721 11:06:02.454604 DQM Delay:
5722 11:06:02.457813 DQM0 = 101, DQM1 = 95
5723 11:06:02.457927 DQ Delay:
5724 11:06:02.460937 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5725 11:06:02.464550 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5726 11:06:02.467518 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5727 11:06:02.470748 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5728 11:06:02.470833
5729 11:06:02.470899
5730 11:06:02.470961 ==
5731 11:06:02.474265 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 11:06:02.480979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 11:06:02.481063 ==
5734 11:06:02.481130
5735 11:06:02.481191
5736 11:06:02.483895 TX Vref Scan disable
5737 11:06:02.483990 == TX Byte 0 ==
5738 11:06:02.487472 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5739 11:06:02.493872 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5740 11:06:02.493964 == TX Byte 1 ==
5741 11:06:02.497243 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5742 11:06:02.503973 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5743 11:06:02.504085 ==
5744 11:06:02.507384 Dram Type= 6, Freq= 0, CH_1, rank 0
5745 11:06:02.510477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 11:06:02.510561 ==
5747 11:06:02.510627
5748 11:06:02.510689
5749 11:06:02.513821 TX Vref Scan disable
5750 11:06:02.517596 == TX Byte 0 ==
5751 11:06:02.520372 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5752 11:06:02.523998 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5753 11:06:02.527288 == TX Byte 1 ==
5754 11:06:02.530668 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5755 11:06:02.533975 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5756 11:06:02.534054
5757 11:06:02.534119 [DATLAT]
5758 11:06:02.536842 Freq=933, CH1 RK0
5759 11:06:02.536949
5760 11:06:02.540213 DATLAT Default: 0xd
5761 11:06:02.540300 0, 0xFFFF, sum = 0
5762 11:06:02.543538 1, 0xFFFF, sum = 0
5763 11:06:02.543624 2, 0xFFFF, sum = 0
5764 11:06:02.547142 3, 0xFFFF, sum = 0
5765 11:06:02.547228 4, 0xFFFF, sum = 0
5766 11:06:02.550358 5, 0xFFFF, sum = 0
5767 11:06:02.550474 6, 0xFFFF, sum = 0
5768 11:06:02.553811 7, 0xFFFF, sum = 0
5769 11:06:02.553896 8, 0xFFFF, sum = 0
5770 11:06:02.556812 9, 0xFFFF, sum = 0
5771 11:06:02.556897 10, 0x0, sum = 1
5772 11:06:02.560278 11, 0x0, sum = 2
5773 11:06:02.560391 12, 0x0, sum = 3
5774 11:06:02.563727 13, 0x0, sum = 4
5775 11:06:02.563812 best_step = 11
5776 11:06:02.563880
5777 11:06:02.563941 ==
5778 11:06:02.566749 Dram Type= 6, Freq= 0, CH_1, rank 0
5779 11:06:02.570276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 11:06:02.573684 ==
5781 11:06:02.573796 RX Vref Scan: 1
5782 11:06:02.573897
5783 11:06:02.577032 RX Vref 0 -> 0, step: 1
5784 11:06:02.577116
5785 11:06:02.577182 RX Delay -53 -> 252, step: 4
5786 11:06:02.580616
5787 11:06:02.580700 Set Vref, RX VrefLevel [Byte0]: 51
5788 11:06:02.583958 [Byte1]: 53
5789 11:06:02.588445
5790 11:06:02.588580 Final RX Vref Byte 0 = 51 to rank0
5791 11:06:02.592024 Final RX Vref Byte 1 = 53 to rank0
5792 11:06:02.594945 Final RX Vref Byte 0 = 51 to rank1
5793 11:06:02.598720 Final RX Vref Byte 1 = 53 to rank1==
5794 11:06:02.602025 Dram Type= 6, Freq= 0, CH_1, rank 0
5795 11:06:02.608536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5796 11:06:02.608623 ==
5797 11:06:02.608689 DQS Delay:
5798 11:06:02.608759 DQS0 = 0, DQS1 = 0
5799 11:06:02.611810 DQM Delay:
5800 11:06:02.611882 DQM0 = 104, DQM1 = 96
5801 11:06:02.615130 DQ Delay:
5802 11:06:02.618506 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5803 11:06:02.621801 DQ4 =104, DQ5 =110, DQ6 =114, DQ7 =100
5804 11:06:02.625126 DQ8 =88, DQ9 =84, DQ10 =100, DQ11 =92
5805 11:06:02.628290 DQ12 =106, DQ13 =100, DQ14 =102, DQ15 =102
5806 11:06:02.628381
5807 11:06:02.628443
5808 11:06:02.634988 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b34, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5809 11:06:02.638390 CH1 RK0: MR19=505, MR18=1B34
5810 11:06:02.644854 CH1_RK0: MR19=0x505, MR18=0x1B34, DQSOSC=405, MR23=63, INC=66, DEC=44
5811 11:06:02.644946
5812 11:06:02.648197 ----->DramcWriteLeveling(PI) begin...
5813 11:06:02.648269 ==
5814 11:06:02.651565 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 11:06:02.654765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 11:06:02.654837 ==
5817 11:06:02.658161 Write leveling (Byte 0): 27 => 27
5818 11:06:02.661780 Write leveling (Byte 1): 26 => 26
5819 11:06:02.665134 DramcWriteLeveling(PI) end<-----
5820 11:06:02.665208
5821 11:06:02.665278 ==
5822 11:06:02.668505 Dram Type= 6, Freq= 0, CH_1, rank 1
5823 11:06:02.675038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5824 11:06:02.675143 ==
5825 11:06:02.675241 [Gating] SW mode calibration
5826 11:06:02.685305 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5827 11:06:02.688421 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5828 11:06:02.691703 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 11:06:02.698294 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 11:06:02.701807 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 11:06:02.704803 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5832 11:06:02.711698 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 11:06:02.715033 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 11:06:02.718158 0 14 24 | B1->B0 | 3030 3232 | 1 1 | (0 0) (1 1)
5835 11:06:02.724778 0 14 28 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
5836 11:06:02.728127 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5837 11:06:02.731290 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 11:06:02.738099 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 11:06:02.741224 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 11:06:02.744447 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 11:06:02.751464 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 11:06:02.754743 0 15 24 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
5843 11:06:02.758128 0 15 28 | B1->B0 | 4242 3a3a | 0 0 | (0 0) (0 0)
5844 11:06:02.764589 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5845 11:06:02.767865 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 11:06:02.771100 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 11:06:02.777898 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 11:06:02.780974 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 11:06:02.784405 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 11:06:02.791142 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 11:06:02.794223 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5852 11:06:02.798049 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 11:06:02.804326 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 11:06:02.807732 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 11:06:02.811194 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 11:06:02.814427 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 11:06:02.821072 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 11:06:02.824441 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 11:06:02.827840 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 11:06:02.834439 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 11:06:02.837867 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 11:06:02.841126 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 11:06:02.847750 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 11:06:02.851103 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 11:06:02.854292 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 11:06:02.860941 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 11:06:02.864326 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5868 11:06:02.867642 Total UI for P1: 0, mck2ui 16
5869 11:06:02.870859 best dqsien dly found for B1: ( 1, 2, 26)
5870 11:06:02.874115 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 11:06:02.877848 Total UI for P1: 0, mck2ui 16
5872 11:06:02.880785 best dqsien dly found for B0: ( 1, 2, 28)
5873 11:06:02.884214 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5874 11:06:02.887763 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5875 11:06:02.887839
5876 11:06:02.894167 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5877 11:06:02.897679 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5878 11:06:02.897789 [Gating] SW calibration Done
5879 11:06:02.900800 ==
5880 11:06:02.900905 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 11:06:02.907737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 11:06:02.907817 ==
5883 11:06:02.907881 RX Vref Scan: 0
5884 11:06:02.907940
5885 11:06:02.910774 RX Vref 0 -> 0, step: 1
5886 11:06:02.910851
5887 11:06:02.914448 RX Delay -80 -> 252, step: 8
5888 11:06:02.917697 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5889 11:06:02.920760 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5890 11:06:02.924089 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5891 11:06:02.931095 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5892 11:06:02.934454 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5893 11:06:02.937795 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5894 11:06:02.941062 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5895 11:06:02.944456 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5896 11:06:02.947673 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5897 11:06:02.954275 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5898 11:06:02.957727 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5899 11:06:02.961118 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5900 11:06:02.964031 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5901 11:06:02.967898 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5902 11:06:02.974622 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5903 11:06:02.977499 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5904 11:06:02.977574 ==
5905 11:06:02.981145 Dram Type= 6, Freq= 0, CH_1, rank 1
5906 11:06:02.984525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5907 11:06:02.984599 ==
5908 11:06:02.984672 DQS Delay:
5909 11:06:02.987344 DQS0 = 0, DQS1 = 0
5910 11:06:02.987415 DQM Delay:
5911 11:06:02.990972 DQM0 = 103, DQM1 = 95
5912 11:06:02.991053 DQ Delay:
5913 11:06:02.994125 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =103
5914 11:06:02.997618 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =103
5915 11:06:03.000819 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5916 11:06:03.004357 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5917 11:06:03.004431
5918 11:06:03.004499
5919 11:06:03.007429 ==
5920 11:06:03.007507 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 11:06:03.014312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 11:06:03.014389 ==
5923 11:06:03.014452
5924 11:06:03.014519
5925 11:06:03.017383 TX Vref Scan disable
5926 11:06:03.017457 == TX Byte 0 ==
5927 11:06:03.020686 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5928 11:06:03.027650 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5929 11:06:03.027727 == TX Byte 1 ==
5930 11:06:03.030590 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5931 11:06:03.037382 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5932 11:06:03.037461 ==
5933 11:06:03.040628 Dram Type= 6, Freq= 0, CH_1, rank 1
5934 11:06:03.043797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5935 11:06:03.043869 ==
5936 11:06:03.043931
5937 11:06:03.043995
5938 11:06:03.047166 TX Vref Scan disable
5939 11:06:03.050905 == TX Byte 0 ==
5940 11:06:03.054064 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5941 11:06:03.057298 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5942 11:06:03.060726 == TX Byte 1 ==
5943 11:06:03.064036 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5944 11:06:03.067391 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5945 11:06:03.067461
5946 11:06:03.067529 [DATLAT]
5947 11:06:03.070619 Freq=933, CH1 RK1
5948 11:06:03.070688
5949 11:06:03.073876 DATLAT Default: 0xb
5950 11:06:03.073974 0, 0xFFFF, sum = 0
5951 11:06:03.077312 1, 0xFFFF, sum = 0
5952 11:06:03.077384 2, 0xFFFF, sum = 0
5953 11:06:03.080668 3, 0xFFFF, sum = 0
5954 11:06:03.080745 4, 0xFFFF, sum = 0
5955 11:06:03.083533 5, 0xFFFF, sum = 0
5956 11:06:03.083607 6, 0xFFFF, sum = 0
5957 11:06:03.087141 7, 0xFFFF, sum = 0
5958 11:06:03.087211 8, 0xFFFF, sum = 0
5959 11:06:03.090418 9, 0xFFFF, sum = 0
5960 11:06:03.090489 10, 0x0, sum = 1
5961 11:06:03.093747 11, 0x0, sum = 2
5962 11:06:03.093817 12, 0x0, sum = 3
5963 11:06:03.097259 13, 0x0, sum = 4
5964 11:06:03.097334 best_step = 11
5965 11:06:03.097402
5966 11:06:03.097460 ==
5967 11:06:03.100194 Dram Type= 6, Freq= 0, CH_1, rank 1
5968 11:06:03.103834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5969 11:06:03.107007 ==
5970 11:06:03.107083 RX Vref Scan: 0
5971 11:06:03.107163
5972 11:06:03.110331 RX Vref 0 -> 0, step: 1
5973 11:06:03.110438
5974 11:06:03.110529 RX Delay -53 -> 252, step: 4
5975 11:06:03.118600 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5976 11:06:03.121632 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5977 11:06:03.125248 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5978 11:06:03.128193 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5979 11:06:03.131319 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5980 11:06:03.138076 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5981 11:06:03.141353 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5982 11:06:03.144893 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5983 11:06:03.148107 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5984 11:06:03.151567 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5985 11:06:03.158253 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5986 11:06:03.161673 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5987 11:06:03.164842 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5988 11:06:03.168014 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5989 11:06:03.171103 iDelay=199, Bit 14, Center 106 (19 ~ 194) 176
5990 11:06:03.178125 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5991 11:06:03.178201 ==
5992 11:06:03.181320 Dram Type= 6, Freq= 0, CH_1, rank 1
5993 11:06:03.184643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5994 11:06:03.184715 ==
5995 11:06:03.184776 DQS Delay:
5996 11:06:03.187943 DQS0 = 0, DQS1 = 0
5997 11:06:03.188017 DQM Delay:
5998 11:06:03.191215 DQM0 = 105, DQM1 = 97
5999 11:06:03.191289 DQ Delay:
6000 11:06:03.194512 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =104
6001 11:06:03.197616 DQ4 =106, DQ5 =116, DQ6 =112, DQ7 =102
6002 11:06:03.200878 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =92
6003 11:06:03.204275 DQ12 =106, DQ13 =102, DQ14 =106, DQ15 =106
6004 11:06:03.204349
6005 11:06:03.204412
6006 11:06:03.214418 [DQSOSCAuto] RK1, (LSB)MR18= 0x2503, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
6007 11:06:03.218044 CH1 RK1: MR19=505, MR18=2503
6008 11:06:03.221154 CH1_RK1: MR19=0x505, MR18=0x2503, DQSOSC=410, MR23=63, INC=64, DEC=42
6009 11:06:03.224455 [RxdqsGatingPostProcess] freq 933
6010 11:06:03.231020 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6011 11:06:03.234013 best DQS0 dly(2T, 0.5T) = (0, 10)
6012 11:06:03.237702 best DQS1 dly(2T, 0.5T) = (0, 10)
6013 11:06:03.240759 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6014 11:06:03.244074 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6015 11:06:03.247473 best DQS0 dly(2T, 0.5T) = (0, 10)
6016 11:06:03.250985 best DQS1 dly(2T, 0.5T) = (0, 10)
6017 11:06:03.254116 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6018 11:06:03.257450 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6019 11:06:03.257535 Pre-setting of DQS Precalculation
6020 11:06:03.264144 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6021 11:06:03.270874 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6022 11:06:03.277352 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6023 11:06:03.277436
6024 11:06:03.277503
6025 11:06:03.280725 [Calibration Summary] 1866 Mbps
6026 11:06:03.284186 CH 0, Rank 0
6027 11:06:03.284269 SW Impedance : PASS
6028 11:06:03.287543 DUTY Scan : NO K
6029 11:06:03.290688 ZQ Calibration : PASS
6030 11:06:03.290773 Jitter Meter : NO K
6031 11:06:03.294133 CBT Training : PASS
6032 11:06:03.294217 Write leveling : PASS
6033 11:06:03.297390 RX DQS gating : PASS
6034 11:06:03.300626 RX DQ/DQS(RDDQC) : PASS
6035 11:06:03.300709 TX DQ/DQS : PASS
6036 11:06:03.304038 RX DATLAT : PASS
6037 11:06:03.307337 RX DQ/DQS(Engine): PASS
6038 11:06:03.307420 TX OE : NO K
6039 11:06:03.310729 All Pass.
6040 11:06:03.310806
6041 11:06:03.310876 CH 0, Rank 1
6042 11:06:03.313981 SW Impedance : PASS
6043 11:06:03.314065 DUTY Scan : NO K
6044 11:06:03.317437 ZQ Calibration : PASS
6045 11:06:03.320626 Jitter Meter : NO K
6046 11:06:03.320713 CBT Training : PASS
6047 11:06:03.324432 Write leveling : PASS
6048 11:06:03.327655 RX DQS gating : PASS
6049 11:06:03.327728 RX DQ/DQS(RDDQC) : PASS
6050 11:06:03.330614 TX DQ/DQS : PASS
6051 11:06:03.333937 RX DATLAT : PASS
6052 11:06:03.334055 RX DQ/DQS(Engine): PASS
6053 11:06:03.337384 TX OE : NO K
6054 11:06:03.337466 All Pass.
6055 11:06:03.337532
6056 11:06:03.340871 CH 1, Rank 0
6057 11:06:03.340945 SW Impedance : PASS
6058 11:06:03.344305 DUTY Scan : NO K
6059 11:06:03.344381 ZQ Calibration : PASS
6060 11:06:03.347363 Jitter Meter : NO K
6061 11:06:03.350577 CBT Training : PASS
6062 11:06:03.350652 Write leveling : PASS
6063 11:06:03.353867 RX DQS gating : PASS
6064 11:06:03.357452 RX DQ/DQS(RDDQC) : PASS
6065 11:06:03.357529 TX DQ/DQS : PASS
6066 11:06:03.360860 RX DATLAT : PASS
6067 11:06:03.364160 RX DQ/DQS(Engine): PASS
6068 11:06:03.364242 TX OE : NO K
6069 11:06:03.367479 All Pass.
6070 11:06:03.367580
6071 11:06:03.367674 CH 1, Rank 1
6072 11:06:03.370860 SW Impedance : PASS
6073 11:06:03.370965 DUTY Scan : NO K
6074 11:06:03.374200 ZQ Calibration : PASS
6075 11:06:03.377083 Jitter Meter : NO K
6076 11:06:03.377159 CBT Training : PASS
6077 11:06:03.380474 Write leveling : PASS
6078 11:06:03.384175 RX DQS gating : PASS
6079 11:06:03.384256 RX DQ/DQS(RDDQC) : PASS
6080 11:06:03.387123 TX DQ/DQS : PASS
6081 11:06:03.390310 RX DATLAT : PASS
6082 11:06:03.390416 RX DQ/DQS(Engine): PASS
6083 11:06:03.393747 TX OE : NO K
6084 11:06:03.393823 All Pass.
6085 11:06:03.393885
6086 11:06:03.397114 DramC Write-DBI off
6087 11:06:03.400377 PER_BANK_REFRESH: Hybrid Mode
6088 11:06:03.400452 TX_TRACKING: ON
6089 11:06:03.410296 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6090 11:06:03.413634 [FAST_K] Save calibration result to emmc
6091 11:06:03.417237 dramc_set_vcore_voltage set vcore to 650000
6092 11:06:03.420343 Read voltage for 400, 6
6093 11:06:03.420419 Vio18 = 0
6094 11:06:03.420489 Vcore = 650000
6095 11:06:03.423952 Vdram = 0
6096 11:06:03.424027 Vddq = 0
6097 11:06:03.424089 Vmddr = 0
6098 11:06:03.430554 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6099 11:06:03.433642 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6100 11:06:03.436831 MEM_TYPE=3, freq_sel=20
6101 11:06:03.440725 sv_algorithm_assistance_LP4_800
6102 11:06:03.443735 ============ PULL DRAM RESETB DOWN ============
6103 11:06:03.446997 ========== PULL DRAM RESETB DOWN end =========
6104 11:06:03.453502 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6105 11:06:03.456661 ===================================
6106 11:06:03.456744 LPDDR4 DRAM CONFIGURATION
6107 11:06:03.460305 ===================================
6108 11:06:03.463508 EX_ROW_EN[0] = 0x0
6109 11:06:03.466839 EX_ROW_EN[1] = 0x0
6110 11:06:03.466923 LP4Y_EN = 0x0
6111 11:06:03.470160 WORK_FSP = 0x0
6112 11:06:03.470236 WL = 0x2
6113 11:06:03.473278 RL = 0x2
6114 11:06:03.473351 BL = 0x2
6115 11:06:03.476689 RPST = 0x0
6116 11:06:03.476765 RD_PRE = 0x0
6117 11:06:03.479931 WR_PRE = 0x1
6118 11:06:03.480006 WR_PST = 0x0
6119 11:06:03.483648 DBI_WR = 0x0
6120 11:06:03.483723 DBI_RD = 0x0
6121 11:06:03.486989 OTF = 0x1
6122 11:06:03.490310 ===================================
6123 11:06:03.493566 ===================================
6124 11:06:03.493642 ANA top config
6125 11:06:03.496750 ===================================
6126 11:06:03.500124 DLL_ASYNC_EN = 0
6127 11:06:03.503490 ALL_SLAVE_EN = 1
6128 11:06:03.503569 NEW_RANK_MODE = 1
6129 11:06:03.506634 DLL_IDLE_MODE = 1
6130 11:06:03.509971 LP45_APHY_COMB_EN = 1
6131 11:06:03.513541 TX_ODT_DIS = 1
6132 11:06:03.516954 NEW_8X_MODE = 1
6133 11:06:03.520030 ===================================
6134 11:06:03.523173 ===================================
6135 11:06:03.523250 data_rate = 800
6136 11:06:03.526557 CKR = 1
6137 11:06:03.530159 DQ_P2S_RATIO = 4
6138 11:06:03.533609 ===================================
6139 11:06:03.536803 CA_P2S_RATIO = 4
6140 11:06:03.539954 DQ_CA_OPEN = 0
6141 11:06:03.543724 DQ_SEMI_OPEN = 1
6142 11:06:03.543827 CA_SEMI_OPEN = 1
6143 11:06:03.546719 CA_FULL_RATE = 0
6144 11:06:03.550040 DQ_CKDIV4_EN = 0
6145 11:06:03.553504 CA_CKDIV4_EN = 1
6146 11:06:03.556696 CA_PREDIV_EN = 0
6147 11:06:03.559791 PH8_DLY = 0
6148 11:06:03.559892 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6149 11:06:03.563157 DQ_AAMCK_DIV = 0
6150 11:06:03.566791 CA_AAMCK_DIV = 0
6151 11:06:03.570370 CA_ADMCK_DIV = 4
6152 11:06:03.573789 DQ_TRACK_CA_EN = 0
6153 11:06:03.573874 CA_PICK = 800
6154 11:06:03.577064 CA_MCKIO = 400
6155 11:06:03.580284 MCKIO_SEMI = 400
6156 11:06:03.583686 PLL_FREQ = 3016
6157 11:06:03.587098 DQ_UI_PI_RATIO = 32
6158 11:06:03.589929 CA_UI_PI_RATIO = 32
6159 11:06:03.593414 ===================================
6160 11:06:03.597065 ===================================
6161 11:06:03.600147 memory_type:LPDDR4
6162 11:06:03.600232 GP_NUM : 10
6163 11:06:03.603476 SRAM_EN : 1
6164 11:06:03.603560 MD32_EN : 0
6165 11:06:03.606842 ===================================
6166 11:06:03.610104 [ANA_INIT] >>>>>>>>>>>>>>
6167 11:06:03.613371 <<<<<< [CONFIGURE PHASE]: ANA_TX
6168 11:06:03.616638 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6169 11:06:03.620167 ===================================
6170 11:06:03.623446 data_rate = 800,PCW = 0X7400
6171 11:06:03.626619 ===================================
6172 11:06:03.630095 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6173 11:06:03.633277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6174 11:06:03.646703 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6175 11:06:03.649650 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6176 11:06:03.653074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6177 11:06:03.656721 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6178 11:06:03.659754 [ANA_INIT] flow start
6179 11:06:03.663238 [ANA_INIT] PLL >>>>>>>>
6180 11:06:03.663323 [ANA_INIT] PLL <<<<<<<<
6181 11:06:03.666775 [ANA_INIT] MIDPI >>>>>>>>
6182 11:06:03.669827 [ANA_INIT] MIDPI <<<<<<<<
6183 11:06:03.669911 [ANA_INIT] DLL >>>>>>>>
6184 11:06:03.673293 [ANA_INIT] flow end
6185 11:06:03.676468 ============ LP4 DIFF to SE enter ============
6186 11:06:03.680158 ============ LP4 DIFF to SE exit ============
6187 11:06:03.683533 [ANA_INIT] <<<<<<<<<<<<<
6188 11:06:03.686435 [Flow] Enable top DCM control >>>>>
6189 11:06:03.689781 [Flow] Enable top DCM control <<<<<
6190 11:06:03.693130 Enable DLL master slave shuffle
6191 11:06:03.699947 ==============================================================
6192 11:06:03.700047 Gating Mode config
6193 11:06:03.706402 ==============================================================
6194 11:06:03.709711 Config description:
6195 11:06:03.716261 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6196 11:06:03.722755 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6197 11:06:03.729428 SELPH_MODE 0: By rank 1: By Phase
6198 11:06:03.736137 ==============================================================
6199 11:06:03.736222 GAT_TRACK_EN = 0
6200 11:06:03.739449 RX_GATING_MODE = 2
6201 11:06:03.742805 RX_GATING_TRACK_MODE = 2
6202 11:06:03.746079 SELPH_MODE = 1
6203 11:06:03.749302 PICG_EARLY_EN = 1
6204 11:06:03.752789 VALID_LAT_VALUE = 1
6205 11:06:03.759143 ==============================================================
6206 11:06:03.762776 Enter into Gating configuration >>>>
6207 11:06:03.765992 Exit from Gating configuration <<<<
6208 11:06:03.769263 Enter into DVFS_PRE_config >>>>>
6209 11:06:03.779168 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6210 11:06:03.782391 Exit from DVFS_PRE_config <<<<<
6211 11:06:03.786089 Enter into PICG configuration >>>>
6212 11:06:03.788910 Exit from PICG configuration <<<<
6213 11:06:03.792242 [RX_INPUT] configuration >>>>>
6214 11:06:03.795575 [RX_INPUT] configuration <<<<<
6215 11:06:03.798969 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6216 11:06:03.805571 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6217 11:06:03.812343 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6218 11:06:03.815796 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6219 11:06:03.822347 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6220 11:06:03.829095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6221 11:06:03.832375 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6222 11:06:03.835457 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6223 11:06:03.842054 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6224 11:06:03.845520 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6225 11:06:03.848698 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6226 11:06:03.855406 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6227 11:06:03.858595 ===================================
6228 11:06:03.858685 LPDDR4 DRAM CONFIGURATION
6229 11:06:03.862279 ===================================
6230 11:06:03.865657 EX_ROW_EN[0] = 0x0
6231 11:06:03.868998 EX_ROW_EN[1] = 0x0
6232 11:06:03.869089 LP4Y_EN = 0x0
6233 11:06:03.872031 WORK_FSP = 0x0
6234 11:06:03.872108 WL = 0x2
6235 11:06:03.875540 RL = 0x2
6236 11:06:03.875636 BL = 0x2
6237 11:06:03.878858 RPST = 0x0
6238 11:06:03.878972 RD_PRE = 0x0
6239 11:06:03.882286 WR_PRE = 0x1
6240 11:06:03.882360 WR_PST = 0x0
6241 11:06:03.885377 DBI_WR = 0x0
6242 11:06:03.885453 DBI_RD = 0x0
6243 11:06:03.888704 OTF = 0x1
6244 11:06:03.892159 ===================================
6245 11:06:03.895341 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6246 11:06:03.898747 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6247 11:06:03.905409 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6248 11:06:03.908633 ===================================
6249 11:06:03.908716 LPDDR4 DRAM CONFIGURATION
6250 11:06:03.911827 ===================================
6251 11:06:03.915235 EX_ROW_EN[0] = 0x10
6252 11:06:03.915315 EX_ROW_EN[1] = 0x0
6253 11:06:03.918508 LP4Y_EN = 0x0
6254 11:06:03.918589 WORK_FSP = 0x0
6255 11:06:03.921761 WL = 0x2
6256 11:06:03.925174 RL = 0x2
6257 11:06:03.925250 BL = 0x2
6258 11:06:03.928776 RPST = 0x0
6259 11:06:03.928883 RD_PRE = 0x0
6260 11:06:03.931830 WR_PRE = 0x1
6261 11:06:03.931937 WR_PST = 0x0
6262 11:06:03.935486 DBI_WR = 0x0
6263 11:06:03.935566 DBI_RD = 0x0
6264 11:06:03.938682 OTF = 0x1
6265 11:06:03.941916 ===================================
6266 11:06:03.948693 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6267 11:06:03.951631 nWR fixed to 30
6268 11:06:03.951711 [ModeRegInit_LP4] CH0 RK0
6269 11:06:03.955110 [ModeRegInit_LP4] CH0 RK1
6270 11:06:03.958618 [ModeRegInit_LP4] CH1 RK0
6271 11:06:03.958697 [ModeRegInit_LP4] CH1 RK1
6272 11:06:03.961886 match AC timing 19
6273 11:06:03.964863 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6274 11:06:03.968402 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6275 11:06:03.974672 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6276 11:06:03.978057 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6277 11:06:03.984642 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6278 11:06:03.984720 ==
6279 11:06:03.988192 Dram Type= 6, Freq= 0, CH_0, rank 0
6280 11:06:03.991214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6281 11:06:03.991321 ==
6282 11:06:03.998376 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6283 11:06:04.004740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6284 11:06:04.004820 [CA 0] Center 36 (8~64) winsize 57
6285 11:06:04.008165 [CA 1] Center 36 (8~64) winsize 57
6286 11:06:04.011587 [CA 2] Center 36 (8~64) winsize 57
6287 11:06:04.014819 [CA 3] Center 36 (8~64) winsize 57
6288 11:06:04.017998 [CA 4] Center 36 (8~64) winsize 57
6289 11:06:04.021245 [CA 5] Center 36 (8~64) winsize 57
6290 11:06:04.021322
6291 11:06:04.024539 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6292 11:06:04.024615
6293 11:06:04.027881 [CATrainingPosCal] consider 1 rank data
6294 11:06:04.031295 u2DelayCellTimex100 = 270/100 ps
6295 11:06:04.034855 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 11:06:04.038141 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 11:06:04.044596 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 11:06:04.048050 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 11:06:04.051286 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 11:06:04.054748 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 11:06:04.054830
6302 11:06:04.057982 CA PerBit enable=1, Macro0, CA PI delay=36
6303 11:06:04.058074
6304 11:06:04.061269 [CBTSetCACLKResult] CA Dly = 36
6305 11:06:04.061386 CS Dly: 1 (0~32)
6306 11:06:04.061477 ==
6307 11:06:04.064696 Dram Type= 6, Freq= 0, CH_0, rank 1
6308 11:06:04.071472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 11:06:04.071559 ==
6310 11:06:04.074592 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6311 11:06:04.081413 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6312 11:06:04.084656 [CA 0] Center 36 (8~64) winsize 57
6313 11:06:04.087884 [CA 1] Center 36 (8~64) winsize 57
6314 11:06:04.091327 [CA 2] Center 36 (8~64) winsize 57
6315 11:06:04.094438 [CA 3] Center 36 (8~64) winsize 57
6316 11:06:04.098089 [CA 4] Center 36 (8~64) winsize 57
6317 11:06:04.101030 [CA 5] Center 36 (8~64) winsize 57
6318 11:06:04.101114
6319 11:06:04.104587 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6320 11:06:04.104672
6321 11:06:04.107856 [CATrainingPosCal] consider 2 rank data
6322 11:06:04.111177 u2DelayCellTimex100 = 270/100 ps
6323 11:06:04.114329 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 11:06:04.117681 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 11:06:04.120918 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 11:06:04.124295 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 11:06:04.127604 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 11:06:04.131276 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 11:06:04.134653
6330 11:06:04.137694 CA PerBit enable=1, Macro0, CA PI delay=36
6331 11:06:04.137778
6332 11:06:04.141399 [CBTSetCACLKResult] CA Dly = 36
6333 11:06:04.141482 CS Dly: 1 (0~32)
6334 11:06:04.141549
6335 11:06:04.144215 ----->DramcWriteLeveling(PI) begin...
6336 11:06:04.144301 ==
6337 11:06:04.147832 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 11:06:04.151002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 11:06:04.151086 ==
6340 11:06:04.154359 Write leveling (Byte 0): 40 => 8
6341 11:06:04.157633 Write leveling (Byte 1): 32 => 0
6342 11:06:04.160943 DramcWriteLeveling(PI) end<-----
6343 11:06:04.161026
6344 11:06:04.161092 ==
6345 11:06:04.164287 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 11:06:04.167565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 11:06:04.170885 ==
6348 11:06:04.170969 [Gating] SW mode calibration
6349 11:06:04.180976 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6350 11:06:04.184735 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6351 11:06:04.187524 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6352 11:06:04.194150 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6353 11:06:04.197805 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6354 11:06:04.200894 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6355 11:06:04.207640 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6356 11:06:04.210638 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6357 11:06:04.214156 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6358 11:06:04.220924 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6359 11:06:04.224398 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6360 11:06:04.227346 Total UI for P1: 0, mck2ui 16
6361 11:06:04.230679 best dqsien dly found for B0: ( 0, 14, 24)
6362 11:06:04.234194 Total UI for P1: 0, mck2ui 16
6363 11:06:04.237150 best dqsien dly found for B1: ( 0, 14, 24)
6364 11:06:04.240331 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6365 11:06:04.243711 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6366 11:06:04.243785
6367 11:06:04.247093 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6368 11:06:04.250503 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6369 11:06:04.254231 [Gating] SW calibration Done
6370 11:06:04.254305 ==
6371 11:06:04.257128 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 11:06:04.263836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 11:06:04.263941 ==
6374 11:06:04.264032 RX Vref Scan: 0
6375 11:06:04.264119
6376 11:06:04.267189 RX Vref 0 -> 0, step: 1
6377 11:06:04.267280
6378 11:06:04.270455 RX Delay -410 -> 252, step: 16
6379 11:06:04.273596 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6380 11:06:04.277106 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6381 11:06:04.280379 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6382 11:06:04.287249 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6383 11:06:04.290588 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6384 11:06:04.293607 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6385 11:06:04.296787 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6386 11:06:04.303537 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6387 11:06:04.306963 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6388 11:06:04.310455 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6389 11:06:04.313532 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6390 11:06:04.320339 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6391 11:06:04.323663 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6392 11:06:04.326993 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6393 11:06:04.333853 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6394 11:06:04.337167 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6395 11:06:04.337252 ==
6396 11:06:04.340255 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 11:06:04.343565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 11:06:04.343649 ==
6399 11:06:04.346806 DQS Delay:
6400 11:06:04.346888 DQS0 = 27, DQS1 = 43
6401 11:06:04.346951 DQM Delay:
6402 11:06:04.350360 DQM0 = 13, DQM1 = 14
6403 11:06:04.350441 DQ Delay:
6404 11:06:04.353620 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =8
6405 11:06:04.357114 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6406 11:06:04.360433 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6407 11:06:04.363862 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6408 11:06:04.363944
6409 11:06:04.364008
6410 11:06:04.364068 ==
6411 11:06:04.367140 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 11:06:04.370424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 11:06:04.370506 ==
6414 11:06:04.373953
6415 11:06:04.374036
6416 11:06:04.374100 TX Vref Scan disable
6417 11:06:04.376832 == TX Byte 0 ==
6418 11:06:04.380068 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 11:06:04.383345 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 11:06:04.386596 == TX Byte 1 ==
6421 11:06:04.390350 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6422 11:06:04.393433 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6423 11:06:04.393517 ==
6424 11:06:04.396609 Dram Type= 6, Freq= 0, CH_0, rank 0
6425 11:06:04.403275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 11:06:04.403360 ==
6427 11:06:04.403425
6428 11:06:04.403487
6429 11:06:04.403546 TX Vref Scan disable
6430 11:06:04.406742 == TX Byte 0 ==
6431 11:06:04.410248 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6432 11:06:04.413171 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6433 11:06:04.416675 == TX Byte 1 ==
6434 11:06:04.419879 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6435 11:06:04.423333 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6436 11:06:04.423418
6437 11:06:04.426394 [DATLAT]
6438 11:06:04.426479 Freq=400, CH0 RK0
6439 11:06:04.426545
6440 11:06:04.430168 DATLAT Default: 0xf
6441 11:06:04.430252 0, 0xFFFF, sum = 0
6442 11:06:04.433450 1, 0xFFFF, sum = 0
6443 11:06:04.433535 2, 0xFFFF, sum = 0
6444 11:06:04.436524 3, 0xFFFF, sum = 0
6445 11:06:04.436609 4, 0xFFFF, sum = 0
6446 11:06:04.439910 5, 0xFFFF, sum = 0
6447 11:06:04.439995 6, 0xFFFF, sum = 0
6448 11:06:04.443155 7, 0xFFFF, sum = 0
6449 11:06:04.443239 8, 0xFFFF, sum = 0
6450 11:06:04.446454 9, 0xFFFF, sum = 0
6451 11:06:04.446538 10, 0xFFFF, sum = 0
6452 11:06:04.449746 11, 0xFFFF, sum = 0
6453 11:06:04.452883 12, 0xFFFF, sum = 0
6454 11:06:04.452968 13, 0x0, sum = 1
6455 11:06:04.456191 14, 0x0, sum = 2
6456 11:06:04.456275 15, 0x0, sum = 3
6457 11:06:04.456342 16, 0x0, sum = 4
6458 11:06:04.459466 best_step = 14
6459 11:06:04.459549
6460 11:06:04.459615 ==
6461 11:06:04.463069 Dram Type= 6, Freq= 0, CH_0, rank 0
6462 11:06:04.466452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 11:06:04.466536 ==
6464 11:06:04.469757 RX Vref Scan: 1
6465 11:06:04.469840
6466 11:06:04.472998 RX Vref 0 -> 0, step: 1
6467 11:06:04.473080
6468 11:06:04.473147 RX Delay -327 -> 252, step: 8
6469 11:06:04.473208
6470 11:06:04.476261 Set Vref, RX VrefLevel [Byte0]: 59
6471 11:06:04.479619 [Byte1]: 49
6472 11:06:04.484706
6473 11:06:04.484788 Final RX Vref Byte 0 = 59 to rank0
6474 11:06:04.487966 Final RX Vref Byte 1 = 49 to rank0
6475 11:06:04.491290 Final RX Vref Byte 0 = 59 to rank1
6476 11:06:04.494883 Final RX Vref Byte 1 = 49 to rank1==
6477 11:06:04.498204 Dram Type= 6, Freq= 0, CH_0, rank 0
6478 11:06:04.504911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 11:06:04.504995 ==
6480 11:06:04.505061 DQS Delay:
6481 11:06:04.507942 DQS0 = 28, DQS1 = 48
6482 11:06:04.508026 DQM Delay:
6483 11:06:04.508092 DQM0 = 12, DQM1 = 15
6484 11:06:04.511329 DQ Delay:
6485 11:06:04.514559 DQ0 =12, DQ1 =12, DQ2 =12, DQ3 =8
6486 11:06:04.518028 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6487 11:06:04.518117 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6488 11:06:04.521067 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6489 11:06:04.524585
6490 11:06:04.524667
6491 11:06:04.531227 [DQSOSCAuto] RK0, (LSB)MR18= 0xaaa2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6492 11:06:04.534338 CH0 RK0: MR19=C0C, MR18=AAA2
6493 11:06:04.541013 CH0_RK0: MR19=0xC0C, MR18=0xAAA2, DQSOSC=388, MR23=63, INC=392, DEC=261
6494 11:06:04.541092 ==
6495 11:06:04.544392 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 11:06:04.547674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 11:06:04.547749 ==
6498 11:06:04.550829 [Gating] SW mode calibration
6499 11:06:04.557832 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6500 11:06:04.564410 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6501 11:06:04.567713 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6502 11:06:04.571111 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6503 11:06:04.577820 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6504 11:06:04.580967 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6505 11:06:04.584228 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 11:06:04.590938 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 11:06:04.594272 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6508 11:06:04.597520 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6509 11:06:04.600756 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6510 11:06:04.604038 Total UI for P1: 0, mck2ui 16
6511 11:06:04.607594 best dqsien dly found for B0: ( 0, 14, 24)
6512 11:06:04.610792 Total UI for P1: 0, mck2ui 16
6513 11:06:04.614036 best dqsien dly found for B1: ( 0, 14, 24)
6514 11:06:04.620802 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6515 11:06:04.623822 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6516 11:06:04.623903
6517 11:06:04.627192 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6518 11:06:04.630710 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6519 11:06:04.633851 [Gating] SW calibration Done
6520 11:06:04.633966 ==
6521 11:06:04.637305 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 11:06:04.640414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 11:06:04.640491 ==
6524 11:06:04.643794 RX Vref Scan: 0
6525 11:06:04.643873
6526 11:06:04.643935 RX Vref 0 -> 0, step: 1
6527 11:06:04.643994
6528 11:06:04.647147 RX Delay -410 -> 252, step: 16
6529 11:06:04.650338 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6530 11:06:04.657033 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6531 11:06:04.660617 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6532 11:06:04.663900 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6533 11:06:04.667038 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6534 11:06:04.673968 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6535 11:06:04.676961 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6536 11:06:04.680521 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6537 11:06:04.683793 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6538 11:06:04.690006 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6539 11:06:04.693805 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6540 11:06:04.697072 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6541 11:06:04.703513 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6542 11:06:04.706799 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6543 11:06:04.710257 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6544 11:06:04.713408 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6545 11:06:04.713483 ==
6546 11:06:04.716807 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 11:06:04.723488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 11:06:04.723566 ==
6549 11:06:04.723630 DQS Delay:
6550 11:06:04.726867 DQS0 = 27, DQS1 = 35
6551 11:06:04.726940 DQM Delay:
6552 11:06:04.727008 DQM0 = 9, DQM1 = 8
6553 11:06:04.730043 DQ Delay:
6554 11:06:04.733337 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6555 11:06:04.733413 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6556 11:06:04.736939 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6557 11:06:04.740112 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6558 11:06:04.740188
6559 11:06:04.740258
6560 11:06:04.743549 ==
6561 11:06:04.747221 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 11:06:04.750182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 11:06:04.750263 ==
6564 11:06:04.750326
6565 11:06:04.750394
6566 11:06:04.753524 TX Vref Scan disable
6567 11:06:04.753599 == TX Byte 0 ==
6568 11:06:04.756971 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6569 11:06:04.760242 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6570 11:06:04.763463 == TX Byte 1 ==
6571 11:06:04.766611 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6572 11:06:04.770361 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6573 11:06:04.773394 ==
6574 11:06:04.776706 Dram Type= 6, Freq= 0, CH_0, rank 1
6575 11:06:04.780044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6576 11:06:04.780119 ==
6577 11:06:04.780180
6578 11:06:04.780245
6579 11:06:04.783456 TX Vref Scan disable
6580 11:06:04.783535 == TX Byte 0 ==
6581 11:06:04.786646 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6582 11:06:04.793465 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6583 11:06:04.793545 == TX Byte 1 ==
6584 11:06:04.796711 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6585 11:06:04.800019 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6586 11:06:04.803378
6587 11:06:04.803449 [DATLAT]
6588 11:06:04.803517 Freq=400, CH0 RK1
6589 11:06:04.803575
6590 11:06:04.806499 DATLAT Default: 0xe
6591 11:06:04.806569 0, 0xFFFF, sum = 0
6592 11:06:04.810220 1, 0xFFFF, sum = 0
6593 11:06:04.810298 2, 0xFFFF, sum = 0
6594 11:06:04.813181 3, 0xFFFF, sum = 0
6595 11:06:04.813259 4, 0xFFFF, sum = 0
6596 11:06:04.816628 5, 0xFFFF, sum = 0
6597 11:06:04.820184 6, 0xFFFF, sum = 0
6598 11:06:04.820264 7, 0xFFFF, sum = 0
6599 11:06:04.823486 8, 0xFFFF, sum = 0
6600 11:06:04.823562 9, 0xFFFF, sum = 0
6601 11:06:04.826722 10, 0xFFFF, sum = 0
6602 11:06:04.826804 11, 0xFFFF, sum = 0
6603 11:06:04.829943 12, 0xFFFF, sum = 0
6604 11:06:04.830022 13, 0x0, sum = 1
6605 11:06:04.833435 14, 0x0, sum = 2
6606 11:06:04.833518 15, 0x0, sum = 3
6607 11:06:04.836440 16, 0x0, sum = 4
6608 11:06:04.836522 best_step = 14
6609 11:06:04.836583
6610 11:06:04.836642 ==
6611 11:06:04.839995 Dram Type= 6, Freq= 0, CH_0, rank 1
6612 11:06:04.843445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 11:06:04.843529 ==
6614 11:06:04.846675 RX Vref Scan: 0
6615 11:06:04.846765
6616 11:06:04.849791 RX Vref 0 -> 0, step: 1
6617 11:06:04.849862
6618 11:06:04.849923 RX Delay -311 -> 252, step: 8
6619 11:06:04.858891 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6620 11:06:04.862135 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6621 11:06:04.865487 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6622 11:06:04.868626 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6623 11:06:04.875090 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6624 11:06:04.878803 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6625 11:06:04.882140 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6626 11:06:04.885036 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6627 11:06:04.891766 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6628 11:06:04.895542 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6629 11:06:04.898355 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6630 11:06:04.901721 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6631 11:06:04.908732 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6632 11:06:04.911784 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6633 11:06:04.915042 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6634 11:06:04.921680 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6635 11:06:04.921755 ==
6636 11:06:04.925222 Dram Type= 6, Freq= 0, CH_0, rank 1
6637 11:06:04.928466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 11:06:04.928543 ==
6639 11:06:04.928606 DQS Delay:
6640 11:06:04.931841 DQS0 = 28, DQS1 = 44
6641 11:06:04.931913 DQM Delay:
6642 11:06:04.935159 DQM0 = 9, DQM1 = 15
6643 11:06:04.935238 DQ Delay:
6644 11:06:04.938464 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6645 11:06:04.941633 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6646 11:06:04.945082 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6647 11:06:04.948577 DQ12 =20, DQ13 =24, DQ14 =24, DQ15 =20
6648 11:06:04.948657
6649 11:06:04.948721
6650 11:06:04.955122 [DQSOSCAuto] RK1, (LSB)MR18= 0xbb6e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6651 11:06:04.958607 CH0 RK1: MR19=C0C, MR18=BB6E
6652 11:06:04.964969 CH0_RK1: MR19=0xC0C, MR18=0xBB6E, DQSOSC=386, MR23=63, INC=396, DEC=264
6653 11:06:04.968308 [RxdqsGatingPostProcess] freq 400
6654 11:06:04.971810 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6655 11:06:04.974997 best DQS0 dly(2T, 0.5T) = (0, 10)
6656 11:06:04.978334 best DQS1 dly(2T, 0.5T) = (0, 10)
6657 11:06:04.981803 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6658 11:06:04.985257 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6659 11:06:04.988193 best DQS0 dly(2T, 0.5T) = (0, 10)
6660 11:06:04.991484 best DQS1 dly(2T, 0.5T) = (0, 10)
6661 11:06:04.994933 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6662 11:06:04.998246 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6663 11:06:05.001518 Pre-setting of DQS Precalculation
6664 11:06:05.004876 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6665 11:06:05.008260 ==
6666 11:06:05.008343 Dram Type= 6, Freq= 0, CH_1, rank 0
6667 11:06:05.014629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 11:06:05.014714 ==
6669 11:06:05.017877 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6670 11:06:05.024961 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6671 11:06:05.028222 [CA 0] Center 36 (8~64) winsize 57
6672 11:06:05.031536 [CA 1] Center 36 (8~64) winsize 57
6673 11:06:05.034649 [CA 2] Center 36 (8~64) winsize 57
6674 11:06:05.038134 [CA 3] Center 36 (8~64) winsize 57
6675 11:06:05.041719 [CA 4] Center 36 (8~64) winsize 57
6676 11:06:05.044845 [CA 5] Center 36 (8~64) winsize 57
6677 11:06:05.044928
6678 11:06:05.048361 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6679 11:06:05.048444
6680 11:06:05.051371 [CATrainingPosCal] consider 1 rank data
6681 11:06:05.054897 u2DelayCellTimex100 = 270/100 ps
6682 11:06:05.058073 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 11:06:05.061540 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 11:06:05.064667 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 11:06:05.068281 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 11:06:05.071550 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 11:06:05.077811 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 11:06:05.077895
6689 11:06:05.081106 CA PerBit enable=1, Macro0, CA PI delay=36
6690 11:06:05.081190
6691 11:06:05.084646 [CBTSetCACLKResult] CA Dly = 36
6692 11:06:05.084730 CS Dly: 1 (0~32)
6693 11:06:05.084795 ==
6694 11:06:05.087817 Dram Type= 6, Freq= 0, CH_1, rank 1
6695 11:06:05.091069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 11:06:05.094533 ==
6697 11:06:05.098046 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6698 11:06:05.104834 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6699 11:06:05.107727 [CA 0] Center 36 (8~64) winsize 57
6700 11:06:05.111178 [CA 1] Center 36 (8~64) winsize 57
6701 11:06:05.114486 [CA 2] Center 36 (8~64) winsize 57
6702 11:06:05.117716 [CA 3] Center 36 (8~64) winsize 57
6703 11:06:05.120880 [CA 4] Center 36 (8~64) winsize 57
6704 11:06:05.124189 [CA 5] Center 36 (8~64) winsize 57
6705 11:06:05.124272
6706 11:06:05.127865 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6707 11:06:05.127948
6708 11:06:05.131207 [CATrainingPosCal] consider 2 rank data
6709 11:06:05.134487 u2DelayCellTimex100 = 270/100 ps
6710 11:06:05.137946 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 11:06:05.141002 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 11:06:05.144549 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 11:06:05.147712 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 11:06:05.150949 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 11:06:05.154521 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 11:06:05.154605
6717 11:06:05.157869 CA PerBit enable=1, Macro0, CA PI delay=36
6718 11:06:05.157993
6719 11:06:05.161311 [CBTSetCACLKResult] CA Dly = 36
6720 11:06:05.164540 CS Dly: 1 (0~32)
6721 11:06:05.164622
6722 11:06:05.167519 ----->DramcWriteLeveling(PI) begin...
6723 11:06:05.167603 ==
6724 11:06:05.171026 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 11:06:05.174419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 11:06:05.174503 ==
6727 11:06:05.177647 Write leveling (Byte 0): 40 => 8
6728 11:06:05.180773 Write leveling (Byte 1): 32 => 0
6729 11:06:05.184482 DramcWriteLeveling(PI) end<-----
6730 11:06:05.184565
6731 11:06:05.184631 ==
6732 11:06:05.187690 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 11:06:05.190906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 11:06:05.190989 ==
6735 11:06:05.194181 [Gating] SW mode calibration
6736 11:06:05.201181 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6737 11:06:05.207404 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6738 11:06:05.210815 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6739 11:06:05.217450 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6740 11:06:05.220945 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6741 11:06:05.224178 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6742 11:06:05.227418 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6743 11:06:05.234067 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6744 11:06:05.237490 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6745 11:06:05.240788 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6746 11:06:05.247333 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6747 11:06:05.250780 Total UI for P1: 0, mck2ui 16
6748 11:06:05.253997 best dqsien dly found for B0: ( 0, 14, 24)
6749 11:06:05.257055 Total UI for P1: 0, mck2ui 16
6750 11:06:05.260617 best dqsien dly found for B1: ( 0, 14, 24)
6751 11:06:05.264000 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6752 11:06:05.267119 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6753 11:06:05.267202
6754 11:06:05.270398 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6755 11:06:05.274115 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6756 11:06:05.277452 [Gating] SW calibration Done
6757 11:06:05.277534 ==
6758 11:06:05.280690 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 11:06:05.283938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 11:06:05.284022 ==
6761 11:06:05.287039 RX Vref Scan: 0
6762 11:06:05.287122
6763 11:06:05.290353 RX Vref 0 -> 0, step: 1
6764 11:06:05.290437
6765 11:06:05.290502 RX Delay -410 -> 252, step: 16
6766 11:06:05.297279 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6767 11:06:05.300441 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6768 11:06:05.303824 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6769 11:06:05.307100 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6770 11:06:05.313807 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6771 11:06:05.317035 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6772 11:06:05.320391 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6773 11:06:05.323784 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6774 11:06:05.330183 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6775 11:06:05.333629 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6776 11:06:05.336868 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6777 11:06:05.340229 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6778 11:06:05.346775 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6779 11:06:05.350455 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6780 11:06:05.353587 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6781 11:06:05.360121 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6782 11:06:05.360205 ==
6783 11:06:05.363497 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 11:06:05.366676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 11:06:05.366759 ==
6786 11:06:05.366825 DQS Delay:
6787 11:06:05.370048 DQS0 = 27, DQS1 = 43
6788 11:06:05.370131 DQM Delay:
6789 11:06:05.373315 DQM0 = 9, DQM1 = 17
6790 11:06:05.373398 DQ Delay:
6791 11:06:05.376863 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6792 11:06:05.379967 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =0
6793 11:06:05.383372 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6794 11:06:05.386696 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6795 11:06:05.386779
6796 11:06:05.386845
6797 11:06:05.386904 ==
6798 11:06:05.390237 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 11:06:05.393470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 11:06:05.393554 ==
6801 11:06:05.393619
6802 11:06:05.393681
6803 11:06:05.396554 TX Vref Scan disable
6804 11:06:05.396637 == TX Byte 0 ==
6805 11:06:05.403209 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 11:06:05.406606 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 11:06:05.406716 == TX Byte 1 ==
6808 11:06:05.413290 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6809 11:06:05.416531 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6810 11:06:05.416614 ==
6811 11:06:05.420005 Dram Type= 6, Freq= 0, CH_1, rank 0
6812 11:06:05.423265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 11:06:05.423348 ==
6814 11:06:05.423414
6815 11:06:05.423476
6816 11:06:05.427036 TX Vref Scan disable
6817 11:06:05.427119 == TX Byte 0 ==
6818 11:06:05.433434 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6819 11:06:05.436788 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6820 11:06:05.436898 == TX Byte 1 ==
6821 11:06:05.443326 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6822 11:06:05.446645 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6823 11:06:05.446729
6824 11:06:05.446795 [DATLAT]
6825 11:06:05.450382 Freq=400, CH1 RK0
6826 11:06:05.450465
6827 11:06:05.450531 DATLAT Default: 0xf
6828 11:06:05.453277 0, 0xFFFF, sum = 0
6829 11:06:05.453361 1, 0xFFFF, sum = 0
6830 11:06:05.456649 2, 0xFFFF, sum = 0
6831 11:06:05.456733 3, 0xFFFF, sum = 0
6832 11:06:05.459903 4, 0xFFFF, sum = 0
6833 11:06:05.459990 5, 0xFFFF, sum = 0
6834 11:06:05.463448 6, 0xFFFF, sum = 0
6835 11:06:05.463536 7, 0xFFFF, sum = 0
6836 11:06:05.466835 8, 0xFFFF, sum = 0
6837 11:06:05.470283 9, 0xFFFF, sum = 0
6838 11:06:05.470368 10, 0xFFFF, sum = 0
6839 11:06:05.473819 11, 0xFFFF, sum = 0
6840 11:06:05.473931 12, 0xFFFF, sum = 0
6841 11:06:05.476742 13, 0x0, sum = 1
6842 11:06:05.476826 14, 0x0, sum = 2
6843 11:06:05.480221 15, 0x0, sum = 3
6844 11:06:05.480306 16, 0x0, sum = 4
6845 11:06:05.480372 best_step = 14
6846 11:06:05.480432
6847 11:06:05.483304 ==
6848 11:06:05.486641 Dram Type= 6, Freq= 0, CH_1, rank 0
6849 11:06:05.490097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 11:06:05.490181 ==
6851 11:06:05.490246 RX Vref Scan: 1
6852 11:06:05.490307
6853 11:06:05.493745 RX Vref 0 -> 0, step: 1
6854 11:06:05.493827
6855 11:06:05.496827 RX Delay -327 -> 252, step: 8
6856 11:06:05.496910
6857 11:06:05.500484 Set Vref, RX VrefLevel [Byte0]: 51
6858 11:06:05.503670 [Byte1]: 53
6859 11:06:05.506877
6860 11:06:05.506973 Final RX Vref Byte 0 = 51 to rank0
6861 11:06:05.510191 Final RX Vref Byte 1 = 53 to rank0
6862 11:06:05.513536 Final RX Vref Byte 0 = 51 to rank1
6863 11:06:05.516910 Final RX Vref Byte 1 = 53 to rank1==
6864 11:06:05.520259 Dram Type= 6, Freq= 0, CH_1, rank 0
6865 11:06:05.526803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 11:06:05.526887 ==
6867 11:06:05.526951 DQS Delay:
6868 11:06:05.530101 DQS0 = 32, DQS1 = 40
6869 11:06:05.530184 DQM Delay:
6870 11:06:05.530249 DQM0 = 11, DQM1 = 14
6871 11:06:05.533281 DQ Delay:
6872 11:06:05.536549 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6873 11:06:05.536632 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6874 11:06:05.540212 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =8
6875 11:06:05.543653 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6876 11:06:05.543736
6877 11:06:05.546840
6878 11:06:05.553591 [DQSOSCAuto] RK0, (LSB)MR18= 0x9cd6, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6879 11:06:05.556861 CH1 RK0: MR19=C0C, MR18=9CD6
6880 11:06:05.563405 CH1_RK0: MR19=0xC0C, MR18=0x9CD6, DQSOSC=383, MR23=63, INC=402, DEC=268
6881 11:06:05.563488 ==
6882 11:06:05.567069 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 11:06:05.569747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 11:06:05.569857 ==
6885 11:06:05.572956 [Gating] SW mode calibration
6886 11:06:05.579747 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6887 11:06:05.586225 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6888 11:06:05.589732 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6889 11:06:05.592803 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6890 11:06:05.599513 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6891 11:06:05.602871 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6892 11:06:05.606181 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6893 11:06:05.613245 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6894 11:06:05.616047 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6895 11:06:05.619438 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6896 11:06:05.622754 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6897 11:06:05.626092 Total UI for P1: 0, mck2ui 16
6898 11:06:05.629476 best dqsien dly found for B0: ( 0, 14, 24)
6899 11:06:05.632611 Total UI for P1: 0, mck2ui 16
6900 11:06:05.636441 best dqsien dly found for B1: ( 0, 14, 24)
6901 11:06:05.639530 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6902 11:06:05.646074 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6903 11:06:05.646157
6904 11:06:05.649381 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6905 11:06:05.652646 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6906 11:06:05.655943 [Gating] SW calibration Done
6907 11:06:05.656025 ==
6908 11:06:05.659650 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 11:06:05.662544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 11:06:05.662628 ==
6911 11:06:05.665894 RX Vref Scan: 0
6912 11:06:05.666013
6913 11:06:05.666078 RX Vref 0 -> 0, step: 1
6914 11:06:05.666139
6915 11:06:05.669570 RX Delay -410 -> 252, step: 16
6916 11:06:05.672777 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6917 11:06:05.679270 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6918 11:06:05.682540 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6919 11:06:05.686061 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6920 11:06:05.689048 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6921 11:06:05.695928 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6922 11:06:05.699419 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6923 11:06:05.702827 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6924 11:06:05.705888 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6925 11:06:05.712428 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6926 11:06:05.715826 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6927 11:06:05.719193 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6928 11:06:05.722397 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6929 11:06:05.729166 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6930 11:06:05.732400 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6931 11:06:05.735835 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6932 11:06:05.735918 ==
6933 11:06:05.739083 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 11:06:05.742822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 11:06:05.745935 ==
6936 11:06:05.746055 DQS Delay:
6937 11:06:05.746121 DQS0 = 35, DQS1 = 35
6938 11:06:05.749190 DQM Delay:
6939 11:06:05.749273 DQM0 = 19, DQM1 = 11
6940 11:06:05.752594 DQ Delay:
6941 11:06:05.756049 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6942 11:06:05.756133 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6943 11:06:05.759361 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6944 11:06:05.762781 DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =24
6945 11:06:05.762864
6946 11:06:05.762929
6947 11:06:05.766123 ==
6948 11:06:05.766206 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 11:06:05.772778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 11:06:05.772861 ==
6951 11:06:05.772927
6952 11:06:05.772987
6953 11:06:05.775681 TX Vref Scan disable
6954 11:06:05.775764 == TX Byte 0 ==
6955 11:06:05.779363 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6956 11:06:05.785714 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6957 11:06:05.785797 == TX Byte 1 ==
6958 11:06:05.789226 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6959 11:06:05.792588 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6960 11:06:05.795745 ==
6961 11:06:05.799211 Dram Type= 6, Freq= 0, CH_1, rank 1
6962 11:06:05.802692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6963 11:06:05.802775 ==
6964 11:06:05.802841
6965 11:06:05.802900
6966 11:06:05.805768 TX Vref Scan disable
6967 11:06:05.805884 == TX Byte 0 ==
6968 11:06:05.809260 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6969 11:06:05.815785 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6970 11:06:05.815872 == TX Byte 1 ==
6971 11:06:05.819372 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6972 11:06:05.822657 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6973 11:06:05.825895
6974 11:06:05.825987 [DATLAT]
6975 11:06:05.826054 Freq=400, CH1 RK1
6976 11:06:05.826116
6977 11:06:05.829124 DATLAT Default: 0xe
6978 11:06:05.829207 0, 0xFFFF, sum = 0
6979 11:06:05.832288 1, 0xFFFF, sum = 0
6980 11:06:05.832373 2, 0xFFFF, sum = 0
6981 11:06:05.835534 3, 0xFFFF, sum = 0
6982 11:06:05.835650 4, 0xFFFF, sum = 0
6983 11:06:05.839249 5, 0xFFFF, sum = 0
6984 11:06:05.842542 6, 0xFFFF, sum = 0
6985 11:06:05.842626 7, 0xFFFF, sum = 0
6986 11:06:05.845788 8, 0xFFFF, sum = 0
6987 11:06:05.845873 9, 0xFFFF, sum = 0
6988 11:06:05.848995 10, 0xFFFF, sum = 0
6989 11:06:05.849078 11, 0xFFFF, sum = 0
6990 11:06:05.852325 12, 0xFFFF, sum = 0
6991 11:06:05.852409 13, 0x0, sum = 1
6992 11:06:05.855658 14, 0x0, sum = 2
6993 11:06:05.855742 15, 0x0, sum = 3
6994 11:06:05.858983 16, 0x0, sum = 4
6995 11:06:05.859067 best_step = 14
6996 11:06:05.859132
6997 11:06:05.859192 ==
6998 11:06:05.862219 Dram Type= 6, Freq= 0, CH_1, rank 1
6999 11:06:05.866077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7000 11:06:05.866161 ==
7001 11:06:05.868931 RX Vref Scan: 0
7002 11:06:05.869014
7003 11:06:05.872668 RX Vref 0 -> 0, step: 1
7004 11:06:05.872752
7005 11:06:05.872817 RX Delay -311 -> 252, step: 8
7006 11:06:05.881274 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
7007 11:06:05.884235 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
7008 11:06:05.887512 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
7009 11:06:05.894178 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
7010 11:06:05.897270 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7011 11:06:05.901006 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
7012 11:06:05.904064 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
7013 11:06:05.907526 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
7014 11:06:05.914142 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7015 11:06:05.917418 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7016 11:06:05.920993 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7017 11:06:05.924306 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7018 11:06:05.930713 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7019 11:06:05.934113 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7020 11:06:05.937564 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7021 11:06:05.944167 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
7022 11:06:05.944251 ==
7023 11:06:05.947490 Dram Type= 6, Freq= 0, CH_1, rank 1
7024 11:06:05.950798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7025 11:06:05.950882 ==
7026 11:06:05.950949 DQS Delay:
7027 11:06:05.954151 DQS0 = 32, DQS1 = 36
7028 11:06:05.954234 DQM Delay:
7029 11:06:05.957487 DQM0 = 11, DQM1 = 12
7030 11:06:05.957570 DQ Delay:
7031 11:06:05.960922 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7032 11:06:05.964161 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =8
7033 11:06:05.967649 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
7034 11:06:05.970808 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =20
7035 11:06:05.970892
7036 11:06:05.970958
7037 11:06:05.977482 [DQSOSCAuto] RK1, (LSB)MR18= 0xab55, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7038 11:06:05.980477 CH1 RK1: MR19=C0C, MR18=AB55
7039 11:06:05.987498 CH1_RK1: MR19=0xC0C, MR18=0xAB55, DQSOSC=388, MR23=63, INC=392, DEC=261
7040 11:06:05.990751 [RxdqsGatingPostProcess] freq 400
7041 11:06:05.997353 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7042 11:06:05.997437 best DQS0 dly(2T, 0.5T) = (0, 10)
7043 11:06:06.000514 best DQS1 dly(2T, 0.5T) = (0, 10)
7044 11:06:06.003994 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7045 11:06:06.007278 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7046 11:06:06.010762 best DQS0 dly(2T, 0.5T) = (0, 10)
7047 11:06:06.013761 best DQS1 dly(2T, 0.5T) = (0, 10)
7048 11:06:06.017510 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7049 11:06:06.020653 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7050 11:06:06.023824 Pre-setting of DQS Precalculation
7051 11:06:06.027391 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7052 11:06:06.037010 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7053 11:06:06.043684 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7054 11:06:06.043769
7055 11:06:06.043835
7056 11:06:06.046895 [Calibration Summary] 800 Mbps
7057 11:06:06.046979 CH 0, Rank 0
7058 11:06:06.050256 SW Impedance : PASS
7059 11:06:06.050339 DUTY Scan : NO K
7060 11:06:06.053870 ZQ Calibration : PASS
7061 11:06:06.056894 Jitter Meter : NO K
7062 11:06:06.056977 CBT Training : PASS
7063 11:06:06.060173 Write leveling : PASS
7064 11:06:06.063576 RX DQS gating : PASS
7065 11:06:06.063659 RX DQ/DQS(RDDQC) : PASS
7066 11:06:06.066962 TX DQ/DQS : PASS
7067 11:06:06.070258 RX DATLAT : PASS
7068 11:06:06.070341 RX DQ/DQS(Engine): PASS
7069 11:06:06.073601 TX OE : NO K
7070 11:06:06.073685 All Pass.
7071 11:06:06.073751
7072 11:06:06.076965 CH 0, Rank 1
7073 11:06:06.077048 SW Impedance : PASS
7074 11:06:06.080198 DUTY Scan : NO K
7075 11:06:06.083545 ZQ Calibration : PASS
7076 11:06:06.083628 Jitter Meter : NO K
7077 11:06:06.086888 CBT Training : PASS
7078 11:06:06.090585 Write leveling : NO K
7079 11:06:06.090668 RX DQS gating : PASS
7080 11:06:06.093760 RX DQ/DQS(RDDQC) : PASS
7081 11:06:06.093871 TX DQ/DQS : PASS
7082 11:06:06.096932 RX DATLAT : PASS
7083 11:06:06.100143 RX DQ/DQS(Engine): PASS
7084 11:06:06.100238 TX OE : NO K
7085 11:06:06.103820 All Pass.
7086 11:06:06.103903
7087 11:06:06.103968 CH 1, Rank 0
7088 11:06:06.106798 SW Impedance : PASS
7089 11:06:06.106881 DUTY Scan : NO K
7090 11:06:06.110279 ZQ Calibration : PASS
7091 11:06:06.113241 Jitter Meter : NO K
7092 11:06:06.113325 CBT Training : PASS
7093 11:06:06.116788 Write leveling : PASS
7094 11:06:06.120123 RX DQS gating : PASS
7095 11:06:06.120206 RX DQ/DQS(RDDQC) : PASS
7096 11:06:06.123536 TX DQ/DQS : PASS
7097 11:06:06.126524 RX DATLAT : PASS
7098 11:06:06.126608 RX DQ/DQS(Engine): PASS
7099 11:06:06.129874 TX OE : NO K
7100 11:06:06.130022 All Pass.
7101 11:06:06.130114
7102 11:06:06.133244 CH 1, Rank 1
7103 11:06:06.133327 SW Impedance : PASS
7104 11:06:06.136466 DUTY Scan : NO K
7105 11:06:06.140201 ZQ Calibration : PASS
7106 11:06:06.140284 Jitter Meter : NO K
7107 11:06:06.143465 CBT Training : PASS
7108 11:06:06.143549 Write leveling : NO K
7109 11:06:06.146837 RX DQS gating : PASS
7110 11:06:06.150011 RX DQ/DQS(RDDQC) : PASS
7111 11:06:06.150122 TX DQ/DQS : PASS
7112 11:06:06.153264 RX DATLAT : PASS
7113 11:06:06.156653 RX DQ/DQS(Engine): PASS
7114 11:06:06.156735 TX OE : NO K
7115 11:06:06.159838 All Pass.
7116 11:06:06.159922
7117 11:06:06.159987 DramC Write-DBI off
7118 11:06:06.163482 PER_BANK_REFRESH: Hybrid Mode
7119 11:06:06.166804 TX_TRACKING: ON
7120 11:06:06.173549 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7121 11:06:06.176780 [FAST_K] Save calibration result to emmc
7122 11:06:06.180147 dramc_set_vcore_voltage set vcore to 725000
7123 11:06:06.183631 Read voltage for 1600, 0
7124 11:06:06.183714 Vio18 = 0
7125 11:06:06.186493 Vcore = 725000
7126 11:06:06.186576 Vdram = 0
7127 11:06:06.186641 Vddq = 0
7128 11:06:06.190354 Vmddr = 0
7129 11:06:06.193500 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7130 11:06:06.200169 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7131 11:06:06.200252 MEM_TYPE=3, freq_sel=13
7132 11:06:06.203419 sv_algorithm_assistance_LP4_3733
7133 11:06:06.210079 ============ PULL DRAM RESETB DOWN ============
7134 11:06:06.213183 ========== PULL DRAM RESETB DOWN end =========
7135 11:06:06.216761 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7136 11:06:06.220002 ===================================
7137 11:06:06.223395 LPDDR4 DRAM CONFIGURATION
7138 11:06:06.226500 ===================================
7139 11:06:06.226583 EX_ROW_EN[0] = 0x0
7140 11:06:06.229937 EX_ROW_EN[1] = 0x0
7141 11:06:06.233425 LP4Y_EN = 0x0
7142 11:06:06.233508 WORK_FSP = 0x1
7143 11:06:06.236539 WL = 0x5
7144 11:06:06.236622 RL = 0x5
7145 11:06:06.240011 BL = 0x2
7146 11:06:06.240095 RPST = 0x0
7147 11:06:06.243322 RD_PRE = 0x0
7148 11:06:06.243437 WR_PRE = 0x1
7149 11:06:06.246767 WR_PST = 0x1
7150 11:06:06.246851 DBI_WR = 0x0
7151 11:06:06.250110 DBI_RD = 0x0
7152 11:06:06.250193 OTF = 0x1
7153 11:06:06.253472 ===================================
7154 11:06:06.256741 ===================================
7155 11:06:06.260081 ANA top config
7156 11:06:06.263212 ===================================
7157 11:06:06.263328 DLL_ASYNC_EN = 0
7158 11:06:06.266494 ALL_SLAVE_EN = 0
7159 11:06:06.269828 NEW_RANK_MODE = 1
7160 11:06:06.273223 DLL_IDLE_MODE = 1
7161 11:06:06.276519 LP45_APHY_COMB_EN = 1
7162 11:06:06.276602 TX_ODT_DIS = 0
7163 11:06:06.279822 NEW_8X_MODE = 1
7164 11:06:06.283134 ===================================
7165 11:06:06.286524 ===================================
7166 11:06:06.289839 data_rate = 3200
7167 11:06:06.293201 CKR = 1
7168 11:06:06.296689 DQ_P2S_RATIO = 8
7169 11:06:06.299511 ===================================
7170 11:06:06.299597 CA_P2S_RATIO = 8
7171 11:06:06.302802 DQ_CA_OPEN = 0
7172 11:06:06.306252 DQ_SEMI_OPEN = 0
7173 11:06:06.309467 CA_SEMI_OPEN = 0
7174 11:06:06.313057 CA_FULL_RATE = 0
7175 11:06:06.316316 DQ_CKDIV4_EN = 0
7176 11:06:06.316400 CA_CKDIV4_EN = 0
7177 11:06:06.319688 CA_PREDIV_EN = 0
7178 11:06:06.322936 PH8_DLY = 12
7179 11:06:06.326213 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7180 11:06:06.329801 DQ_AAMCK_DIV = 4
7181 11:06:06.332758 CA_AAMCK_DIV = 4
7182 11:06:06.332842 CA_ADMCK_DIV = 4
7183 11:06:06.336163 DQ_TRACK_CA_EN = 0
7184 11:06:06.339466 CA_PICK = 1600
7185 11:06:06.342574 CA_MCKIO = 1600
7186 11:06:06.345915 MCKIO_SEMI = 0
7187 11:06:06.349482 PLL_FREQ = 3068
7188 11:06:06.352411 DQ_UI_PI_RATIO = 32
7189 11:06:06.356088 CA_UI_PI_RATIO = 0
7190 11:06:06.359213 ===================================
7191 11:06:06.362506 ===================================
7192 11:06:06.362589 memory_type:LPDDR4
7193 11:06:06.365844 GP_NUM : 10
7194 11:06:06.369354 SRAM_EN : 1
7195 11:06:06.369437 MD32_EN : 0
7196 11:06:06.372684 ===================================
7197 11:06:06.375934 [ANA_INIT] >>>>>>>>>>>>>>
7198 11:06:06.379117 <<<<<< [CONFIGURE PHASE]: ANA_TX
7199 11:06:06.382359 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7200 11:06:06.385765 ===================================
7201 11:06:06.389091 data_rate = 3200,PCW = 0X7600
7202 11:06:06.392400 ===================================
7203 11:06:06.395509 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7204 11:06:06.398738 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7205 11:06:06.405412 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7206 11:06:06.408866 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7207 11:06:06.412257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7208 11:06:06.415540 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7209 11:06:06.418749 [ANA_INIT] flow start
7210 11:06:06.422213 [ANA_INIT] PLL >>>>>>>>
7211 11:06:06.422295 [ANA_INIT] PLL <<<<<<<<
7212 11:06:06.425540 [ANA_INIT] MIDPI >>>>>>>>
7213 11:06:06.429021 [ANA_INIT] MIDPI <<<<<<<<
7214 11:06:06.429098 [ANA_INIT] DLL >>>>>>>>
7215 11:06:06.432316 [ANA_INIT] DLL <<<<<<<<
7216 11:06:06.435362 [ANA_INIT] flow end
7217 11:06:06.438744 ============ LP4 DIFF to SE enter ============
7218 11:06:06.441908 ============ LP4 DIFF to SE exit ============
7219 11:06:06.445380 [ANA_INIT] <<<<<<<<<<<<<
7220 11:06:06.449128 [Flow] Enable top DCM control >>>>>
7221 11:06:06.452049 [Flow] Enable top DCM control <<<<<
7222 11:06:06.455575 Enable DLL master slave shuffle
7223 11:06:06.458683 ==============================================================
7224 11:06:06.462449 Gating Mode config
7225 11:06:06.468970 ==============================================================
7226 11:06:06.469088 Config description:
7227 11:06:06.478800 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7228 11:06:06.485166 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7229 11:06:06.492108 SELPH_MODE 0: By rank 1: By Phase
7230 11:06:06.495467 ==============================================================
7231 11:06:06.498376 GAT_TRACK_EN = 1
7232 11:06:06.501854 RX_GATING_MODE = 2
7233 11:06:06.505305 RX_GATING_TRACK_MODE = 2
7234 11:06:06.508636 SELPH_MODE = 1
7235 11:06:06.511648 PICG_EARLY_EN = 1
7236 11:06:06.514993 VALID_LAT_VALUE = 1
7237 11:06:06.518282 ==============================================================
7238 11:06:06.521651 Enter into Gating configuration >>>>
7239 11:06:06.525056 Exit from Gating configuration <<<<
7240 11:06:06.528446 Enter into DVFS_PRE_config >>>>>
7241 11:06:06.541650 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7242 11:06:06.545138 Exit from DVFS_PRE_config <<<<<
7243 11:06:06.545223 Enter into PICG configuration >>>>
7244 11:06:06.548421 Exit from PICG configuration <<<<
7245 11:06:06.551786 [RX_INPUT] configuration >>>>>
7246 11:06:06.555217 [RX_INPUT] configuration <<<<<
7247 11:06:06.561705 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7248 11:06:06.564895 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7249 11:06:06.571920 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7250 11:06:06.578367 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7251 11:06:06.585230 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7252 11:06:06.591568 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7253 11:06:06.594984 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7254 11:06:06.598365 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7255 11:06:06.601930 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7256 11:06:06.608153 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7257 11:06:06.611518 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7258 11:06:06.614902 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7259 11:06:06.618048 ===================================
7260 11:06:06.621639 LPDDR4 DRAM CONFIGURATION
7261 11:06:06.624836 ===================================
7262 11:06:06.624938 EX_ROW_EN[0] = 0x0
7263 11:06:06.628237 EX_ROW_EN[1] = 0x0
7264 11:06:06.631669 LP4Y_EN = 0x0
7265 11:06:06.631765 WORK_FSP = 0x1
7266 11:06:06.635030 WL = 0x5
7267 11:06:06.635136 RL = 0x5
7268 11:06:06.638034 BL = 0x2
7269 11:06:06.638140 RPST = 0x0
7270 11:06:06.641421 RD_PRE = 0x0
7271 11:06:06.641500 WR_PRE = 0x1
7272 11:06:06.644770 WR_PST = 0x1
7273 11:06:06.644872 DBI_WR = 0x0
7274 11:06:06.648070 DBI_RD = 0x0
7275 11:06:06.648192 OTF = 0x1
7276 11:06:06.651842 ===================================
7277 11:06:06.654674 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7278 11:06:06.661588 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7279 11:06:06.664914 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7280 11:06:06.667770 ===================================
7281 11:06:06.671356 LPDDR4 DRAM CONFIGURATION
7282 11:06:06.674909 ===================================
7283 11:06:06.675017 EX_ROW_EN[0] = 0x10
7284 11:06:06.678177 EX_ROW_EN[1] = 0x0
7285 11:06:06.681568 LP4Y_EN = 0x0
7286 11:06:06.681653 WORK_FSP = 0x1
7287 11:06:06.684728 WL = 0x5
7288 11:06:06.684830 RL = 0x5
7289 11:06:06.688097 BL = 0x2
7290 11:06:06.688183 RPST = 0x0
7291 11:06:06.691285 RD_PRE = 0x0
7292 11:06:06.691418 WR_PRE = 0x1
7293 11:06:06.694666 WR_PST = 0x1
7294 11:06:06.694743 DBI_WR = 0x0
7295 11:06:06.697748 DBI_RD = 0x0
7296 11:06:06.697824 OTF = 0x1
7297 11:06:06.701228 ===================================
7298 11:06:06.707918 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7299 11:06:06.707996 ==
7300 11:06:06.711465 Dram Type= 6, Freq= 0, CH_0, rank 0
7301 11:06:06.714412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7302 11:06:06.714497 ==
7303 11:06:06.717756 [Duty_Offset_Calibration]
7304 11:06:06.720992 B0:2 B1:0 CA:1
7305 11:06:06.721075
7306 11:06:06.724279 [DutyScan_Calibration_Flow] k_type=0
7307 11:06:06.732289
7308 11:06:06.732382 ==CLK 0==
7309 11:06:06.735683 Final CLK duty delay cell = -4
7310 11:06:06.739118 [-4] MAX Duty = 5031%(X100), DQS PI = 28
7311 11:06:06.742181 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7312 11:06:06.745584 [-4] AVG Duty = 4922%(X100)
7313 11:06:06.745669
7314 11:06:06.748940 CH0 CLK Duty spec in!! Max-Min= 218%
7315 11:06:06.752330 [DutyScan_Calibration_Flow] ====Done====
7316 11:06:06.752417
7317 11:06:06.755347 [DutyScan_Calibration_Flow] k_type=1
7318 11:06:06.771901
7319 11:06:06.771987 ==DQS 0 ==
7320 11:06:06.774936 Final DQS duty delay cell = 0
7321 11:06:06.778295 [0] MAX Duty = 5218%(X100), DQS PI = 28
7322 11:06:06.781944 [0] MIN Duty = 4969%(X100), DQS PI = 0
7323 11:06:06.782037 [0] AVG Duty = 5093%(X100)
7324 11:06:06.784873
7325 11:06:06.784958 ==DQS 1 ==
7326 11:06:06.788160 Final DQS duty delay cell = -4
7327 11:06:06.792049 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7328 11:06:06.794976 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7329 11:06:06.798366 [-4] AVG Duty = 5000%(X100)
7330 11:06:06.798453
7331 11:06:06.801859 CH0 DQS 0 Duty spec in!! Max-Min= 249%
7332 11:06:06.801977
7333 11:06:06.804956 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7334 11:06:06.808312 [DutyScan_Calibration_Flow] ====Done====
7335 11:06:06.808410
7336 11:06:06.811748 [DutyScan_Calibration_Flow] k_type=3
7337 11:06:06.829167
7338 11:06:06.829254 ==DQM 0 ==
7339 11:06:06.832455 Final DQM duty delay cell = 0
7340 11:06:06.835846 [0] MAX Duty = 5124%(X100), DQS PI = 26
7341 11:06:06.838865 [0] MIN Duty = 4813%(X100), DQS PI = 52
7342 11:06:06.842568 [0] AVG Duty = 4968%(X100)
7343 11:06:06.842682
7344 11:06:06.842789 ==DQM 1 ==
7345 11:06:06.845738 Final DQM duty delay cell = 0
7346 11:06:06.848867 [0] MAX Duty = 5249%(X100), DQS PI = 28
7347 11:06:06.852594 [0] MIN Duty = 5000%(X100), DQS PI = 20
7348 11:06:06.855403 [0] AVG Duty = 5124%(X100)
7349 11:06:06.855477
7350 11:06:06.858730 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7351 11:06:06.858829
7352 11:06:06.862439 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7353 11:06:06.865588 [DutyScan_Calibration_Flow] ====Done====
7354 11:06:06.865673
7355 11:06:06.868783 [DutyScan_Calibration_Flow] k_type=2
7356 11:06:06.886106
7357 11:06:06.886190 ==DQ 0 ==
7358 11:06:06.889570 Final DQ duty delay cell = 0
7359 11:06:06.892886 [0] MAX Duty = 5156%(X100), DQS PI = 36
7360 11:06:06.896390 [0] MIN Duty = 5000%(X100), DQS PI = 0
7361 11:06:06.896491 [0] AVG Duty = 5078%(X100)
7362 11:06:06.896582
7363 11:06:06.899962 ==DQ 1 ==
7364 11:06:06.902884 Final DQ duty delay cell = 0
7365 11:06:06.906339 [0] MAX Duty = 4969%(X100), DQS PI = 42
7366 11:06:06.909665 [0] MIN Duty = 4875%(X100), DQS PI = 0
7367 11:06:06.909763 [0] AVG Duty = 4922%(X100)
7368 11:06:06.909854
7369 11:06:06.913159 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7370 11:06:06.913255
7371 11:06:06.916649 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7372 11:06:06.919685 [DutyScan_Calibration_Flow] ====Done====
7373 11:06:06.923119 ==
7374 11:06:06.926528 Dram Type= 6, Freq= 0, CH_1, rank 0
7375 11:06:06.929788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7376 11:06:06.929871 ==
7377 11:06:06.933273 [Duty_Offset_Calibration]
7378 11:06:06.933355 B0:0 B1:-1 CA:2
7379 11:06:06.933419
7380 11:06:06.936437 [DutyScan_Calibration_Flow] k_type=0
7381 11:06:06.946709
7382 11:06:06.946792 ==CLK 0==
7383 11:06:06.949683 Final CLK duty delay cell = 0
7384 11:06:06.952820 [0] MAX Duty = 5156%(X100), DQS PI = 10
7385 11:06:06.956338 [0] MIN Duty = 4906%(X100), DQS PI = 46
7386 11:06:06.956420 [0] AVG Duty = 5031%(X100)
7387 11:06:06.959896
7388 11:06:06.962819 CH1 CLK Duty spec in!! Max-Min= 250%
7389 11:06:06.966250 [DutyScan_Calibration_Flow] ====Done====
7390 11:06:06.966332
7391 11:06:06.969553 [DutyScan_Calibration_Flow] k_type=1
7392 11:06:06.986244
7393 11:06:06.986327 ==DQS 0 ==
7394 11:06:06.989207 Final DQS duty delay cell = 0
7395 11:06:06.992752 [0] MAX Duty = 5124%(X100), DQS PI = 26
7396 11:06:06.995880 [0] MIN Duty = 4969%(X100), DQS PI = 2
7397 11:06:06.995953 [0] AVG Duty = 5046%(X100)
7398 11:06:06.999426
7399 11:06:06.999500 ==DQS 1 ==
7400 11:06:07.002610 Final DQS duty delay cell = 0
7401 11:06:07.005891 [0] MAX Duty = 5156%(X100), DQS PI = 0
7402 11:06:07.009581 [0] MIN Duty = 4844%(X100), DQS PI = 34
7403 11:06:07.009660 [0] AVG Duty = 5000%(X100)
7404 11:06:07.012882
7405 11:06:07.016006 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7406 11:06:07.016089
7407 11:06:07.019456 CH1 DQS 1 Duty spec in!! Max-Min= 312%
7408 11:06:07.023043 [DutyScan_Calibration_Flow] ====Done====
7409 11:06:07.023125
7410 11:06:07.025714 [DutyScan_Calibration_Flow] k_type=3
7411 11:06:07.043682
7412 11:06:07.043767 ==DQM 0 ==
7413 11:06:07.047148 Final DQM duty delay cell = 4
7414 11:06:07.050406 [4] MAX Duty = 5125%(X100), DQS PI = 6
7415 11:06:07.053724 [4] MIN Duty = 4969%(X100), DQS PI = 46
7416 11:06:07.053806 [4] AVG Duty = 5047%(X100)
7417 11:06:07.057231
7418 11:06:07.057313 ==DQM 1 ==
7419 11:06:07.060211 Final DQM duty delay cell = 0
7420 11:06:07.063655 [0] MAX Duty = 5281%(X100), DQS PI = 58
7421 11:06:07.067208 [0] MIN Duty = 4844%(X100), DQS PI = 34
7422 11:06:07.070122 [0] AVG Duty = 5062%(X100)
7423 11:06:07.070204
7424 11:06:07.073501 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7425 11:06:07.073583
7426 11:06:07.077016 CH1 DQM 1 Duty spec in!! Max-Min= 437%
7427 11:06:07.080107 [DutyScan_Calibration_Flow] ====Done====
7428 11:06:07.080189
7429 11:06:07.083360 [DutyScan_Calibration_Flow] k_type=2
7430 11:06:07.100458
7431 11:06:07.100568 ==DQ 0 ==
7432 11:06:07.104025 Final DQ duty delay cell = 0
7433 11:06:07.107159 [0] MAX Duty = 5062%(X100), DQS PI = 16
7434 11:06:07.110476 [0] MIN Duty = 4969%(X100), DQS PI = 48
7435 11:06:07.110589 [0] AVG Duty = 5015%(X100)
7436 11:06:07.113955
7437 11:06:07.114050 ==DQ 1 ==
7438 11:06:07.117247 Final DQ duty delay cell = 0
7439 11:06:07.120688 [0] MAX Duty = 5062%(X100), DQS PI = 2
7440 11:06:07.123575 [0] MIN Duty = 4813%(X100), DQS PI = 34
7441 11:06:07.123656 [0] AVG Duty = 4937%(X100)
7442 11:06:07.123756
7443 11:06:07.126851 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7444 11:06:07.130594
7445 11:06:07.133741 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7446 11:06:07.136813 [DutyScan_Calibration_Flow] ====Done====
7447 11:06:07.140335 nWR fixed to 30
7448 11:06:07.140447 [ModeRegInit_LP4] CH0 RK0
7449 11:06:07.143889 [ModeRegInit_LP4] CH0 RK1
7450 11:06:07.147143 [ModeRegInit_LP4] CH1 RK0
7451 11:06:07.147252 [ModeRegInit_LP4] CH1 RK1
7452 11:06:07.150427 match AC timing 5
7453 11:06:07.153877 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7454 11:06:07.156843 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7455 11:06:07.163757 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7456 11:06:07.167118 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7457 11:06:07.173442 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7458 11:06:07.173554 [MiockJmeterHQA]
7459 11:06:07.173623
7460 11:06:07.176734 [DramcMiockJmeter] u1RxGatingPI = 0
7461 11:06:07.180244 0 : 4255, 4027
7462 11:06:07.180329 4 : 4254, 4029
7463 11:06:07.180397 8 : 4253, 4026
7464 11:06:07.183465 12 : 4252, 4027
7465 11:06:07.183578 16 : 4253, 4027
7466 11:06:07.186656 20 : 4254, 4029
7467 11:06:07.186768 24 : 4253, 4026
7468 11:06:07.190081 28 : 4362, 4137
7469 11:06:07.190191 32 : 4252, 4027
7470 11:06:07.193566 36 : 4252, 4027
7471 11:06:07.193679 40 : 4252, 4027
7472 11:06:07.193781 44 : 4255, 4029
7473 11:06:07.196769 48 : 4255, 4029
7474 11:06:07.196886 52 : 4363, 4137
7475 11:06:07.200269 56 : 4362, 4137
7476 11:06:07.200381 60 : 4363, 4140
7477 11:06:07.203747 64 : 4250, 4026
7478 11:06:07.203854 68 : 4252, 4029
7479 11:06:07.203923 72 : 4250, 4026
7480 11:06:07.206933 76 : 4252, 4030
7481 11:06:07.207017 80 : 4361, 4137
7482 11:06:07.210457 84 : 4250, 4027
7483 11:06:07.210570 88 : 4250, 3472
7484 11:06:07.213424 92 : 4250, 0
7485 11:06:07.213507 96 : 4252, 0
7486 11:06:07.213574 100 : 4252, 0
7487 11:06:07.216560 104 : 4255, 0
7488 11:06:07.216644 108 : 4252, 0
7489 11:06:07.220142 112 : 4250, 0
7490 11:06:07.220254 116 : 4253, 0
7491 11:06:07.220351 120 : 4253, 0
7492 11:06:07.223387 124 : 4250, 0
7493 11:06:07.223501 128 : 4253, 0
7494 11:06:07.223600 132 : 4363, 0
7495 11:06:07.226684 136 : 4360, 0
7496 11:06:07.226774 140 : 4250, 0
7497 11:06:07.230086 144 : 4258, 0
7498 11:06:07.230199 148 : 4252, 0
7499 11:06:07.230281 152 : 4249, 0
7500 11:06:07.233673 156 : 4258, 0
7501 11:06:07.233757 160 : 4252, 0
7502 11:06:07.236619 164 : 4250, 0
7503 11:06:07.236735 168 : 4255, 0
7504 11:06:07.236853 172 : 4252, 0
7505 11:06:07.240118 176 : 4360, 0
7506 11:06:07.240235 180 : 4250, 0
7507 11:06:07.240326 184 : 4363, 0
7508 11:06:07.243651 188 : 4361, 0
7509 11:06:07.243765 192 : 4247, 0
7510 11:06:07.246666 196 : 4253, 0
7511 11:06:07.246781 200 : 4252, 7
7512 11:06:07.250032 204 : 4250, 2528
7513 11:06:07.250131 208 : 4361, 4138
7514 11:06:07.250199 212 : 4363, 4138
7515 11:06:07.253579 216 : 4253, 4029
7516 11:06:07.253691 220 : 4250, 4027
7517 11:06:07.256561 224 : 4250, 4027
7518 11:06:07.256674 228 : 4249, 4027
7519 11:06:07.259953 232 : 4255, 4029
7520 11:06:07.260067 236 : 4360, 4138
7521 11:06:07.263368 240 : 4250, 4027
7522 11:06:07.263481 244 : 4249, 4027
7523 11:06:07.266670 248 : 4250, 4027
7524 11:06:07.266792 252 : 4250, 4027
7525 11:06:07.270151 256 : 4250, 4027
7526 11:06:07.270264 260 : 4361, 4138
7527 11:06:07.273676 264 : 4361, 4137
7528 11:06:07.273789 268 : 4250, 4027
7529 11:06:07.273890 272 : 4250, 4027
7530 11:06:07.277088 276 : 4250, 4027
7531 11:06:07.277200 280 : 4250, 4026
7532 11:06:07.280238 284 : 4250, 4026
7533 11:06:07.280351 288 : 4360, 4138
7534 11:06:07.283610 292 : 4250, 4027
7535 11:06:07.283694 296 : 4250, 4026
7536 11:06:07.286755 300 : 4363, 4140
7537 11:06:07.286871 304 : 4250, 4027
7538 11:06:07.290195 308 : 4250, 4027
7539 11:06:07.290278 312 : 4361, 4025
7540 11:06:07.293393 316 : 4361, 1832
7541 11:06:07.293506
7542 11:06:07.293601 MIOCK jitter meter ch=0
7543 11:06:07.293715
7544 11:06:07.296576 1T = (316-92) = 224 dly cells
7545 11:06:07.303514 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7546 11:06:07.303598 ==
7547 11:06:07.306630 Dram Type= 6, Freq= 0, CH_0, rank 0
7548 11:06:07.310169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 11:06:07.310253 ==
7550 11:06:07.316627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7551 11:06:07.320053 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7552 11:06:07.323026 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7553 11:06:07.329682 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7554 11:06:07.339311 [CA 0] Center 43 (13~73) winsize 61
7555 11:06:07.342454 [CA 1] Center 43 (13~73) winsize 61
7556 11:06:07.346081 [CA 2] Center 38 (8~68) winsize 61
7557 11:06:07.349174 [CA 3] Center 37 (8~67) winsize 60
7558 11:06:07.352748 [CA 4] Center 36 (7~66) winsize 60
7559 11:06:07.355818 [CA 5] Center 35 (5~65) winsize 61
7560 11:06:07.355919
7561 11:06:07.359384 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7562 11:06:07.359493
7563 11:06:07.362340 [CATrainingPosCal] consider 1 rank data
7564 11:06:07.366037 u2DelayCellTimex100 = 290/100 ps
7565 11:06:07.369341 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7566 11:06:07.375794 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7567 11:06:07.379091 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7568 11:06:07.382702 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7569 11:06:07.385934 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7570 11:06:07.388959 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7571 11:06:07.389042
7572 11:06:07.392487 CA PerBit enable=1, Macro0, CA PI delay=35
7573 11:06:07.392570
7574 11:06:07.395735 [CBTSetCACLKResult] CA Dly = 35
7575 11:06:07.399284 CS Dly: 9 (0~40)
7576 11:06:07.402685 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7577 11:06:07.405772 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7578 11:06:07.405886 ==
7579 11:06:07.409357 Dram Type= 6, Freq= 0, CH_0, rank 1
7580 11:06:07.412638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7581 11:06:07.412725 ==
7582 11:06:07.419209 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7583 11:06:07.422441 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7584 11:06:07.429189 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7585 11:06:07.432264 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7586 11:06:07.442809 [CA 0] Center 43 (13~74) winsize 62
7587 11:06:07.445685 [CA 1] Center 43 (13~73) winsize 61
7588 11:06:07.449197 [CA 2] Center 38 (9~68) winsize 60
7589 11:06:07.452488 [CA 3] Center 38 (9~68) winsize 60
7590 11:06:07.455867 [CA 4] Center 37 (7~67) winsize 61
7591 11:06:07.459316 [CA 5] Center 36 (6~66) winsize 61
7592 11:06:07.459399
7593 11:06:07.462435 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7594 11:06:07.462518
7595 11:06:07.465771 [CATrainingPosCal] consider 2 rank data
7596 11:06:07.469206 u2DelayCellTimex100 = 290/100 ps
7597 11:06:07.472682 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7598 11:06:07.479121 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7599 11:06:07.482586 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7600 11:06:07.486100 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7601 11:06:07.489457 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7602 11:06:07.492617 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7603 11:06:07.492699
7604 11:06:07.496010 CA PerBit enable=1, Macro0, CA PI delay=35
7605 11:06:07.496094
7606 11:06:07.499165 [CBTSetCACLKResult] CA Dly = 35
7607 11:06:07.502862 CS Dly: 10 (0~43)
7608 11:06:07.505934 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7609 11:06:07.509082 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7610 11:06:07.509191
7611 11:06:07.512685 ----->DramcWriteLeveling(PI) begin...
7612 11:06:07.512770 ==
7613 11:06:07.515872 Dram Type= 6, Freq= 0, CH_0, rank 0
7614 11:06:07.519524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7615 11:06:07.522700 ==
7616 11:06:07.522809 Write leveling (Byte 0): 37 => 37
7617 11:06:07.525815 Write leveling (Byte 1): 29 => 29
7618 11:06:07.529107 DramcWriteLeveling(PI) end<-----
7619 11:06:07.529209
7620 11:06:07.529301 ==
7621 11:06:07.532826 Dram Type= 6, Freq= 0, CH_0, rank 0
7622 11:06:07.539228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 11:06:07.539313 ==
7624 11:06:07.542442 [Gating] SW mode calibration
7625 11:06:07.548941 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7626 11:06:07.552303 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7627 11:06:07.559019 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 11:06:07.562252 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 11:06:07.565534 1 4 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
7630 11:06:07.572585 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7631 11:06:07.575398 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7632 11:06:07.578957 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7633 11:06:07.582614 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7634 11:06:07.589072 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7635 11:06:07.592400 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7636 11:06:07.595656 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7637 11:06:07.602289 1 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
7638 11:06:07.605615 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7639 11:06:07.609572 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7640 11:06:07.615536 1 5 20 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
7641 11:06:07.619152 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7642 11:06:07.622373 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 11:06:07.628830 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 11:06:07.632537 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7645 11:06:07.635541 1 6 8 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7646 11:06:07.642442 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7647 11:06:07.645391 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7648 11:06:07.648800 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7649 11:06:07.655598 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 11:06:07.659014 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 11:06:07.662464 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 11:06:07.668794 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 11:06:07.672068 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 11:06:07.675497 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7655 11:06:07.682255 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7656 11:06:07.685643 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7657 11:06:07.688576 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 11:06:07.692110 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 11:06:07.698849 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 11:06:07.701912 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 11:06:07.705270 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 11:06:07.711999 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 11:06:07.715482 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 11:06:07.718833 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 11:06:07.725413 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 11:06:07.728858 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 11:06:07.732187 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 11:06:07.738943 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 11:06:07.741894 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7670 11:06:07.745182 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7671 11:06:07.748800 Total UI for P1: 0, mck2ui 16
7672 11:06:07.752183 best dqsien dly found for B0: ( 1, 9, 8)
7673 11:06:07.758741 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7674 11:06:07.762119 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7675 11:06:07.765807 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7676 11:06:07.769237 Total UI for P1: 0, mck2ui 16
7677 11:06:07.772078 best dqsien dly found for B1: ( 1, 9, 18)
7678 11:06:07.775570 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7679 11:06:07.779017 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7680 11:06:07.779101
7681 11:06:07.782261 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7682 11:06:07.788573 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7683 11:06:07.788657 [Gating] SW calibration Done
7684 11:06:07.788723 ==
7685 11:06:07.791974 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 11:06:07.798669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 11:06:07.798753 ==
7688 11:06:07.798819 RX Vref Scan: 0
7689 11:06:07.798878
7690 11:06:07.801927 RX Vref 0 -> 0, step: 1
7691 11:06:07.802050
7692 11:06:07.805357 RX Delay 0 -> 252, step: 8
7693 11:06:07.808698 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7694 11:06:07.812374 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7695 11:06:07.815188 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7696 11:06:07.818593 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7697 11:06:07.825150 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7698 11:06:07.828733 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7699 11:06:07.831865 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7700 11:06:07.835663 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7701 11:06:07.838742 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7702 11:06:07.845486 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7703 11:06:07.848648 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7704 11:06:07.851597 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7705 11:06:07.855164 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7706 11:06:07.858320 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7707 11:06:07.865325 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7708 11:06:07.868235 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7709 11:06:07.868323 ==
7710 11:06:07.871963 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 11:06:07.875141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 11:06:07.875226 ==
7713 11:06:07.878337 DQS Delay:
7714 11:06:07.878421 DQS0 = 0, DQS1 = 0
7715 11:06:07.878503 DQM Delay:
7716 11:06:07.881768 DQM0 = 138, DQM1 = 126
7717 11:06:07.881851 DQ Delay:
7718 11:06:07.885133 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7719 11:06:07.888492 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7720 11:06:07.895002 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7721 11:06:07.898369 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7722 11:06:07.898453
7723 11:06:07.898519
7724 11:06:07.898580 ==
7725 11:06:07.901751 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 11:06:07.904981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 11:06:07.905066 ==
7728 11:06:07.905133
7729 11:06:07.905194
7730 11:06:07.908387 TX Vref Scan disable
7731 11:06:07.908498 == TX Byte 0 ==
7732 11:06:07.915153 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7733 11:06:07.918500 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7734 11:06:07.918585 == TX Byte 1 ==
7735 11:06:07.925215 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7736 11:06:07.928264 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7737 11:06:07.928374 ==
7738 11:06:07.931463 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 11:06:07.934992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 11:06:07.935078 ==
7741 11:06:07.949371
7742 11:06:07.953016 TX Vref early break, caculate TX vref
7743 11:06:07.956001 TX Vref=16, minBit 6, minWin=22, winSum=375
7744 11:06:07.959563 TX Vref=18, minBit 7, minWin=23, winSum=386
7745 11:06:07.962617 TX Vref=20, minBit 4, minWin=23, winSum=394
7746 11:06:07.966214 TX Vref=22, minBit 0, minWin=24, winSum=406
7747 11:06:07.969503 TX Vref=24, minBit 4, minWin=24, winSum=414
7748 11:06:07.976193 TX Vref=26, minBit 2, minWin=25, winSum=425
7749 11:06:07.979534 TX Vref=28, minBit 0, minWin=26, winSum=431
7750 11:06:07.982838 TX Vref=30, minBit 0, minWin=25, winSum=423
7751 11:06:07.986649 TX Vref=32, minBit 0, minWin=25, winSum=415
7752 11:06:07.989622 TX Vref=34, minBit 0, minWin=25, winSum=408
7753 11:06:07.996345 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
7754 11:06:07.996445
7755 11:06:07.999688 Final TX Range 0 Vref 28
7756 11:06:07.999760
7757 11:06:07.999821 ==
7758 11:06:08.003017 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 11:06:08.006387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 11:06:08.006457 ==
7761 11:06:08.006517
7762 11:06:08.006575
7763 11:06:08.009525 TX Vref Scan disable
7764 11:06:08.016322 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7765 11:06:08.016433 == TX Byte 0 ==
7766 11:06:08.019610 u2DelayCellOfst[0]=10 cells (3 PI)
7767 11:06:08.022955 u2DelayCellOfst[1]=16 cells (5 PI)
7768 11:06:08.026271 u2DelayCellOfst[2]=10 cells (3 PI)
7769 11:06:08.029752 u2DelayCellOfst[3]=10 cells (3 PI)
7770 11:06:08.032650 u2DelayCellOfst[4]=6 cells (2 PI)
7771 11:06:08.035950 u2DelayCellOfst[5]=0 cells (0 PI)
7772 11:06:08.039641 u2DelayCellOfst[6]=16 cells (5 PI)
7773 11:06:08.039746 u2DelayCellOfst[7]=13 cells (4 PI)
7774 11:06:08.045932 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7775 11:06:08.049076 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7776 11:06:08.052651 == TX Byte 1 ==
7777 11:06:08.052750 u2DelayCellOfst[8]=0 cells (0 PI)
7778 11:06:08.055774 u2DelayCellOfst[9]=0 cells (0 PI)
7779 11:06:08.059322 u2DelayCellOfst[10]=6 cells (2 PI)
7780 11:06:08.062287 u2DelayCellOfst[11]=3 cells (1 PI)
7781 11:06:08.065875 u2DelayCellOfst[12]=13 cells (4 PI)
7782 11:06:08.068938 u2DelayCellOfst[13]=10 cells (3 PI)
7783 11:06:08.072647 u2DelayCellOfst[14]=13 cells (4 PI)
7784 11:06:08.075608 u2DelayCellOfst[15]=10 cells (3 PI)
7785 11:06:08.078965 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7786 11:06:08.085944 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7787 11:06:08.086029 DramC Write-DBI on
7788 11:06:08.086094 ==
7789 11:06:08.088855 Dram Type= 6, Freq= 0, CH_0, rank 0
7790 11:06:08.092115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7791 11:06:08.095391 ==
7792 11:06:08.095474
7793 11:06:08.095539
7794 11:06:08.095599 TX Vref Scan disable
7795 11:06:08.099223 == TX Byte 0 ==
7796 11:06:08.102418 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7797 11:06:08.105835 == TX Byte 1 ==
7798 11:06:08.109048 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7799 11:06:08.109132 DramC Write-DBI off
7800 11:06:08.112281
7801 11:06:08.112363 [DATLAT]
7802 11:06:08.112428 Freq=1600, CH0 RK0
7803 11:06:08.112488
7804 11:06:08.115593 DATLAT Default: 0xf
7805 11:06:08.115676 0, 0xFFFF, sum = 0
7806 11:06:08.119177 1, 0xFFFF, sum = 0
7807 11:06:08.119262 2, 0xFFFF, sum = 0
7808 11:06:08.122540 3, 0xFFFF, sum = 0
7809 11:06:08.125973 4, 0xFFFF, sum = 0
7810 11:06:08.126071 5, 0xFFFF, sum = 0
7811 11:06:08.129113 6, 0xFFFF, sum = 0
7812 11:06:08.129197 7, 0xFFFF, sum = 0
7813 11:06:08.132499 8, 0xFFFF, sum = 0
7814 11:06:08.132583 9, 0xFFFF, sum = 0
7815 11:06:08.135878 10, 0xFFFF, sum = 0
7816 11:06:08.135963 11, 0xFFFF, sum = 0
7817 11:06:08.138785 12, 0xFFFF, sum = 0
7818 11:06:08.138891 13, 0xFFFF, sum = 0
7819 11:06:08.142131 14, 0x0, sum = 1
7820 11:06:08.142215 15, 0x0, sum = 2
7821 11:06:08.145806 16, 0x0, sum = 3
7822 11:06:08.145892 17, 0x0, sum = 4
7823 11:06:08.148713 best_step = 15
7824 11:06:08.148797
7825 11:06:08.148863 ==
7826 11:06:08.152253 Dram Type= 6, Freq= 0, CH_0, rank 0
7827 11:06:08.155818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7828 11:06:08.155902 ==
7829 11:06:08.155969 RX Vref Scan: 1
7830 11:06:08.158808
7831 11:06:08.158891 Set Vref Range= 24 -> 127
7832 11:06:08.158958
7833 11:06:08.162208 RX Vref 24 -> 127, step: 1
7834 11:06:08.162292
7835 11:06:08.165338 RX Delay 19 -> 252, step: 4
7836 11:06:08.165422
7837 11:06:08.168806 Set Vref, RX VrefLevel [Byte0]: 24
7838 11:06:08.172244 [Byte1]: 24
7839 11:06:08.172327
7840 11:06:08.175429 Set Vref, RX VrefLevel [Byte0]: 25
7841 11:06:08.178606 [Byte1]: 25
7842 11:06:08.178690
7843 11:06:08.182028 Set Vref, RX VrefLevel [Byte0]: 26
7844 11:06:08.185356 [Byte1]: 26
7845 11:06:08.189335
7846 11:06:08.189445 Set Vref, RX VrefLevel [Byte0]: 27
7847 11:06:08.192866 [Byte1]: 27
7848 11:06:08.197054
7849 11:06:08.197138 Set Vref, RX VrefLevel [Byte0]: 28
7850 11:06:08.200508 [Byte1]: 28
7851 11:06:08.204370
7852 11:06:08.204483 Set Vref, RX VrefLevel [Byte0]: 29
7853 11:06:08.207660 [Byte1]: 29
7854 11:06:08.212021
7855 11:06:08.212104 Set Vref, RX VrefLevel [Byte0]: 30
7856 11:06:08.215419 [Byte1]: 30
7857 11:06:08.219579
7858 11:06:08.219692 Set Vref, RX VrefLevel [Byte0]: 31
7859 11:06:08.222924 [Byte1]: 31
7860 11:06:08.227155
7861 11:06:08.227269 Set Vref, RX VrefLevel [Byte0]: 32
7862 11:06:08.230570 [Byte1]: 32
7863 11:06:08.234822
7864 11:06:08.234937 Set Vref, RX VrefLevel [Byte0]: 33
7865 11:06:08.238134 [Byte1]: 33
7866 11:06:08.242445
7867 11:06:08.242555 Set Vref, RX VrefLevel [Byte0]: 34
7868 11:06:08.245822 [Byte1]: 34
7869 11:06:08.249842
7870 11:06:08.249926 Set Vref, RX VrefLevel [Byte0]: 35
7871 11:06:08.253460 [Byte1]: 35
7872 11:06:08.257319
7873 11:06:08.257404 Set Vref, RX VrefLevel [Byte0]: 36
7874 11:06:08.260999 [Byte1]: 36
7875 11:06:08.265086
7876 11:06:08.265209 Set Vref, RX VrefLevel [Byte0]: 37
7877 11:06:08.268114 [Byte1]: 37
7878 11:06:08.272910
7879 11:06:08.273010 Set Vref, RX VrefLevel [Byte0]: 38
7880 11:06:08.275751 [Byte1]: 38
7881 11:06:08.280164
7882 11:06:08.280272 Set Vref, RX VrefLevel [Byte0]: 39
7883 11:06:08.283626 [Byte1]: 39
7884 11:06:08.287818
7885 11:06:08.287906 Set Vref, RX VrefLevel [Byte0]: 40
7886 11:06:08.290921 [Byte1]: 40
7887 11:06:08.295132
7888 11:06:08.295210 Set Vref, RX VrefLevel [Byte0]: 41
7889 11:06:08.298455 [Byte1]: 41
7890 11:06:08.302745
7891 11:06:08.302826 Set Vref, RX VrefLevel [Byte0]: 42
7892 11:06:08.306190 [Byte1]: 42
7893 11:06:08.310449
7894 11:06:08.310537 Set Vref, RX VrefLevel [Byte0]: 43
7895 11:06:08.314120 [Byte1]: 43
7896 11:06:08.318252
7897 11:06:08.318328 Set Vref, RX VrefLevel [Byte0]: 44
7898 11:06:08.321613 [Byte1]: 44
7899 11:06:08.325642
7900 11:06:08.325742 Set Vref, RX VrefLevel [Byte0]: 45
7901 11:06:08.328949 [Byte1]: 45
7902 11:06:08.333392
7903 11:06:08.333465 Set Vref, RX VrefLevel [Byte0]: 46
7904 11:06:08.336581 [Byte1]: 46
7905 11:06:08.340828
7906 11:06:08.340941 Set Vref, RX VrefLevel [Byte0]: 47
7907 11:06:08.344186 [Byte1]: 47
7908 11:06:08.348405
7909 11:06:08.348476 Set Vref, RX VrefLevel [Byte0]: 48
7910 11:06:08.351532 [Byte1]: 48
7911 11:06:08.356038
7912 11:06:08.356123 Set Vref, RX VrefLevel [Byte0]: 49
7913 11:06:08.359401 [Byte1]: 49
7914 11:06:08.363359
7915 11:06:08.363436 Set Vref, RX VrefLevel [Byte0]: 50
7916 11:06:08.366858 [Byte1]: 50
7917 11:06:08.370875
7918 11:06:08.370951 Set Vref, RX VrefLevel [Byte0]: 51
7919 11:06:08.374198 [Byte1]: 51
7920 11:06:08.378718
7921 11:06:08.378794 Set Vref, RX VrefLevel [Byte0]: 52
7922 11:06:08.382079 [Byte1]: 52
7923 11:06:08.386407
7924 11:06:08.386483 Set Vref, RX VrefLevel [Byte0]: 53
7925 11:06:08.389357 [Byte1]: 53
7926 11:06:08.393893
7927 11:06:08.393992 Set Vref, RX VrefLevel [Byte0]: 54
7928 11:06:08.396950 [Byte1]: 54
7929 11:06:08.401314
7930 11:06:08.401396 Set Vref, RX VrefLevel [Byte0]: 55
7931 11:06:08.404651 [Byte1]: 55
7932 11:06:08.408890
7933 11:06:08.408964 Set Vref, RX VrefLevel [Byte0]: 56
7934 11:06:08.412265 [Byte1]: 56
7935 11:06:08.416673
7936 11:06:08.416778 Set Vref, RX VrefLevel [Byte0]: 57
7937 11:06:08.419691 [Byte1]: 57
7938 11:06:08.424073
7939 11:06:08.424176 Set Vref, RX VrefLevel [Byte0]: 58
7940 11:06:08.427309 [Byte1]: 58
7941 11:06:08.431508
7942 11:06:08.431579 Set Vref, RX VrefLevel [Byte0]: 59
7943 11:06:08.435010 [Byte1]: 59
7944 11:06:08.439214
7945 11:06:08.439334 Set Vref, RX VrefLevel [Byte0]: 60
7946 11:06:08.442619 [Byte1]: 60
7947 11:06:08.446875
7948 11:06:08.446981 Set Vref, RX VrefLevel [Byte0]: 61
7949 11:06:08.449978 [Byte1]: 61
7950 11:06:08.454105
7951 11:06:08.454219 Set Vref, RX VrefLevel [Byte0]: 62
7952 11:06:08.457738 [Byte1]: 62
7953 11:06:08.461840
7954 11:06:08.461948 Set Vref, RX VrefLevel [Byte0]: 63
7955 11:06:08.465286 [Byte1]: 63
7956 11:06:08.469649
7957 11:06:08.469735 Set Vref, RX VrefLevel [Byte0]: 64
7958 11:06:08.472832 [Byte1]: 64
7959 11:06:08.476914
7960 11:06:08.476990 Set Vref, RX VrefLevel [Byte0]: 65
7961 11:06:08.480630 [Byte1]: 65
7962 11:06:08.484651
7963 11:06:08.484752 Set Vref, RX VrefLevel [Byte0]: 66
7964 11:06:08.488286 [Byte1]: 66
7965 11:06:08.492313
7966 11:06:08.492399 Set Vref, RX VrefLevel [Byte0]: 67
7967 11:06:08.495321 [Byte1]: 67
7968 11:06:08.500050
7969 11:06:08.500126 Set Vref, RX VrefLevel [Byte0]: 68
7970 11:06:08.503092 [Byte1]: 68
7971 11:06:08.507621
7972 11:06:08.507722 Set Vref, RX VrefLevel [Byte0]: 69
7973 11:06:08.511069 [Byte1]: 69
7974 11:06:08.514833
7975 11:06:08.514907 Set Vref, RX VrefLevel [Byte0]: 70
7976 11:06:08.518100 [Byte1]: 70
7977 11:06:08.522709
7978 11:06:08.522783 Set Vref, RX VrefLevel [Byte0]: 71
7979 11:06:08.525890 [Byte1]: 71
7980 11:06:08.530152
7981 11:06:08.530226 Set Vref, RX VrefLevel [Byte0]: 72
7982 11:06:08.533361 [Byte1]: 72
7983 11:06:08.537798
7984 11:06:08.537903 Set Vref, RX VrefLevel [Byte0]: 73
7985 11:06:08.540925 [Byte1]: 73
7986 11:06:08.545109
7987 11:06:08.545195 Set Vref, RX VrefLevel [Byte0]: 74
7988 11:06:08.548697 [Byte1]: 74
7989 11:06:08.552740
7990 11:06:08.552824 Set Vref, RX VrefLevel [Byte0]: 75
7991 11:06:08.556295 [Byte1]: 75
7992 11:06:08.560318
7993 11:06:08.560403 Set Vref, RX VrefLevel [Byte0]: 76
7994 11:06:08.563855 [Byte1]: 76
7995 11:06:08.568029
7996 11:06:08.568113 Set Vref, RX VrefLevel [Byte0]: 77
7997 11:06:08.571426 [Byte1]: 77
7998 11:06:08.575612
7999 11:06:08.575723 Set Vref, RX VrefLevel [Byte0]: 78
8000 11:06:08.578836 [Byte1]: 78
8001 11:06:08.583180
8002 11:06:08.583317 Final RX Vref Byte 0 = 61 to rank0
8003 11:06:08.586374 Final RX Vref Byte 1 = 60 to rank0
8004 11:06:08.589895 Final RX Vref Byte 0 = 61 to rank1
8005 11:06:08.593004 Final RX Vref Byte 1 = 60 to rank1==
8006 11:06:08.596260 Dram Type= 6, Freq= 0, CH_0, rank 0
8007 11:06:08.603072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8008 11:06:08.603152 ==
8009 11:06:08.603232 DQS Delay:
8010 11:06:08.603311 DQS0 = 0, DQS1 = 0
8011 11:06:08.606216 DQM Delay:
8012 11:06:08.606293 DQM0 = 136, DQM1 = 123
8013 11:06:08.609504 DQ Delay:
8014 11:06:08.612928 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =134
8015 11:06:08.616100 DQ4 =138, DQ5 =126, DQ6 =142, DQ7 =142
8016 11:06:08.619982 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8017 11:06:08.622905 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =130
8018 11:06:08.622991
8019 11:06:08.623111
8020 11:06:08.623194
8021 11:06:08.626288 [DramC_TX_OE_Calibration] TA2
8022 11:06:08.629809 Original DQ_B0 (3 6) =30, OEN = 27
8023 11:06:08.633069 Original DQ_B1 (3 6) =30, OEN = 27
8024 11:06:08.636256 24, 0x0, End_B0=24 End_B1=24
8025 11:06:08.636342 25, 0x0, End_B0=25 End_B1=25
8026 11:06:08.639442 26, 0x0, End_B0=26 End_B1=26
8027 11:06:08.642692 27, 0x0, End_B0=27 End_B1=27
8028 11:06:08.646461 28, 0x0, End_B0=28 End_B1=28
8029 11:06:08.646546 29, 0x0, End_B0=29 End_B1=29
8030 11:06:08.649356 30, 0x0, End_B0=30 End_B1=30
8031 11:06:08.652660 31, 0x4141, End_B0=30 End_B1=30
8032 11:06:08.655975 Byte0 end_step=30 best_step=27
8033 11:06:08.659755 Byte1 end_step=30 best_step=27
8034 11:06:08.662985 Byte0 TX OE(2T, 0.5T) = (3, 3)
8035 11:06:08.663074 Byte1 TX OE(2T, 0.5T) = (3, 3)
8036 11:06:08.666257
8037 11:06:08.666354
8038 11:06:08.672835 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
8039 11:06:08.676123 CH0 RK0: MR19=303, MR18=1E1C
8040 11:06:08.683062 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
8041 11:06:08.683148
8042 11:06:08.686242 ----->DramcWriteLeveling(PI) begin...
8043 11:06:08.686327 ==
8044 11:06:08.689495 Dram Type= 6, Freq= 0, CH_0, rank 1
8045 11:06:08.692916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 11:06:08.693000 ==
8047 11:06:08.696203 Write leveling (Byte 0): 41 => 41
8048 11:06:08.699698 Write leveling (Byte 1): 28 => 28
8049 11:06:08.703026 DramcWriteLeveling(PI) end<-----
8050 11:06:08.703111
8051 11:06:08.703177 ==
8052 11:06:08.706403 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 11:06:08.709409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 11:06:08.709494 ==
8055 11:06:08.712928 [Gating] SW mode calibration
8056 11:06:08.719582 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8057 11:06:08.726244 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8058 11:06:08.729706 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 11:06:08.732591 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 11:06:08.739716 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 11:06:08.742657 1 4 12 | B1->B0 | 2424 302f | 0 1 | (0 0) (0 0)
8062 11:06:08.745928 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 11:06:08.752606 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 11:06:08.755965 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 11:06:08.759334 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 11:06:08.765966 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 11:06:08.769512 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 11:06:08.772666 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8069 11:06:08.779273 1 5 12 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 0)
8070 11:06:08.782629 1 5 16 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0)
8071 11:06:08.785746 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 11:06:08.792304 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 11:06:08.795909 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 11:06:08.799027 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 11:06:08.805554 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 11:06:08.808971 1 6 8 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
8077 11:06:08.812484 1 6 12 | B1->B0 | 2d2d 4443 | 0 1 | (1 1) (0 0)
8078 11:06:08.818803 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 11:06:08.822373 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 11:06:08.825658 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 11:06:08.832085 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 11:06:08.835562 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 11:06:08.839007 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 11:06:08.845413 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 11:06:08.848712 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8086 11:06:08.852062 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8087 11:06:08.855408 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 11:06:08.862174 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 11:06:08.865289 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 11:06:08.868654 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 11:06:08.875304 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 11:06:08.878888 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 11:06:08.882224 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 11:06:08.888877 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 11:06:08.891986 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 11:06:08.895276 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 11:06:08.902033 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 11:06:08.905101 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 11:06:08.908607 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 11:06:08.915283 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8101 11:06:08.918232 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8102 11:06:08.921921 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8103 11:06:08.924926 Total UI for P1: 0, mck2ui 16
8104 11:06:08.928160 best dqsien dly found for B0: ( 1, 9, 10)
8105 11:06:08.935011 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8106 11:06:08.935088 Total UI for P1: 0, mck2ui 16
8107 11:06:08.941793 best dqsien dly found for B1: ( 1, 9, 14)
8108 11:06:08.944720 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8109 11:06:08.948589 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8110 11:06:08.948665
8111 11:06:08.951928 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8112 11:06:08.954662 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8113 11:06:08.958103 [Gating] SW calibration Done
8114 11:06:08.958177 ==
8115 11:06:08.961651 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 11:06:08.964961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 11:06:08.965037 ==
8118 11:06:08.968508 RX Vref Scan: 0
8119 11:06:08.968611
8120 11:06:08.968703 RX Vref 0 -> 0, step: 1
8121 11:06:08.968805
8122 11:06:08.971635 RX Delay 0 -> 252, step: 8
8123 11:06:08.974734 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8124 11:06:08.981473 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8125 11:06:08.984834 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8126 11:06:08.988205 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8127 11:06:08.991536 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8128 11:06:08.994596 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8129 11:06:09.001336 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8130 11:06:09.005031 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8131 11:06:09.007844 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8132 11:06:09.011308 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8133 11:06:09.014853 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8134 11:06:09.021433 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8135 11:06:09.024875 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8136 11:06:09.028081 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8137 11:06:09.031260 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8138 11:06:09.034588 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8139 11:06:09.037965 ==
8140 11:06:09.041212 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 11:06:09.044629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 11:06:09.044704 ==
8143 11:06:09.044772 DQS Delay:
8144 11:06:09.047911 DQS0 = 0, DQS1 = 0
8145 11:06:09.047983 DQM Delay:
8146 11:06:09.051359 DQM0 = 136, DQM1 = 125
8147 11:06:09.051430 DQ Delay:
8148 11:06:09.054771 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8149 11:06:09.058145 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8150 11:06:09.061427 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8151 11:06:09.064743 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8152 11:06:09.064815
8153 11:06:09.064876
8154 11:06:09.064938 ==
8155 11:06:09.068185 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 11:06:09.074598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 11:06:09.074677 ==
8158 11:06:09.074740
8159 11:06:09.074798
8160 11:06:09.074854 TX Vref Scan disable
8161 11:06:09.078183 == TX Byte 0 ==
8162 11:06:09.081790 Update DQ dly =996 (3 ,6, 36) DQ OEN =(3 ,3)
8163 11:06:09.088357 Update DQM dly =996 (3 ,6, 36) DQM OEN =(3 ,3)
8164 11:06:09.088443 == TX Byte 1 ==
8165 11:06:09.091415 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8166 11:06:09.098233 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8167 11:06:09.098316 ==
8168 11:06:09.101506 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 11:06:09.104806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 11:06:09.104890 ==
8171 11:06:09.120037
8172 11:06:09.123148 TX Vref early break, caculate TX vref
8173 11:06:09.126742 TX Vref=16, minBit 8, minWin=23, winSum=390
8174 11:06:09.130262 TX Vref=18, minBit 2, minWin=24, winSum=402
8175 11:06:09.133461 TX Vref=20, minBit 8, minWin=24, winSum=412
8176 11:06:09.136685 TX Vref=22, minBit 8, minWin=25, winSum=418
8177 11:06:09.139863 TX Vref=24, minBit 12, minWin=25, winSum=425
8178 11:06:09.146523 TX Vref=26, minBit 0, minWin=26, winSum=429
8179 11:06:09.149860 TX Vref=28, minBit 0, minWin=26, winSum=432
8180 11:06:09.153194 TX Vref=30, minBit 0, minWin=26, winSum=426
8181 11:06:09.156417 TX Vref=32, minBit 11, minWin=25, winSum=418
8182 11:06:09.160046 TX Vref=34, minBit 0, minWin=25, winSum=410
8183 11:06:09.163386 TX Vref=36, minBit 1, minWin=24, winSum=400
8184 11:06:09.170263 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
8185 11:06:09.170348
8186 11:06:09.173361 Final TX Range 0 Vref 28
8187 11:06:09.173461
8188 11:06:09.173557 ==
8189 11:06:09.176835 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 11:06:09.179894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 11:06:09.179978 ==
8192 11:06:09.180045
8193 11:06:09.180106
8194 11:06:09.183450 TX Vref Scan disable
8195 11:06:09.189967 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8196 11:06:09.190071 == TX Byte 0 ==
8197 11:06:09.193017 u2DelayCellOfst[0]=13 cells (4 PI)
8198 11:06:09.196548 u2DelayCellOfst[1]=16 cells (5 PI)
8199 11:06:09.199671 u2DelayCellOfst[2]=13 cells (4 PI)
8200 11:06:09.203041 u2DelayCellOfst[3]=13 cells (4 PI)
8201 11:06:09.206408 u2DelayCellOfst[4]=10 cells (3 PI)
8202 11:06:09.209523 u2DelayCellOfst[5]=0 cells (0 PI)
8203 11:06:09.212970 u2DelayCellOfst[6]=16 cells (5 PI)
8204 11:06:09.216342 u2DelayCellOfst[7]=16 cells (5 PI)
8205 11:06:09.219896 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8206 11:06:09.222884 Update DQM dly =996 (3 ,6, 36) DQM OEN =(3 ,3)
8207 11:06:09.226486 == TX Byte 1 ==
8208 11:06:09.229606 u2DelayCellOfst[8]=0 cells (0 PI)
8209 11:06:09.233166 u2DelayCellOfst[9]=3 cells (1 PI)
8210 11:06:09.233250 u2DelayCellOfst[10]=6 cells (2 PI)
8211 11:06:09.236223 u2DelayCellOfst[11]=3 cells (1 PI)
8212 11:06:09.239565 u2DelayCellOfst[12]=13 cells (4 PI)
8213 11:06:09.243290 u2DelayCellOfst[13]=13 cells (4 PI)
8214 11:06:09.246217 u2DelayCellOfst[14]=13 cells (4 PI)
8215 11:06:09.249812 u2DelayCellOfst[15]=10 cells (3 PI)
8216 11:06:09.256485 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8217 11:06:09.259738 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8218 11:06:09.259847 DramC Write-DBI on
8219 11:06:09.259946 ==
8220 11:06:09.263262 Dram Type= 6, Freq= 0, CH_0, rank 1
8221 11:06:09.269599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8222 11:06:09.269715 ==
8223 11:06:09.269844
8224 11:06:09.269959
8225 11:06:09.270070 TX Vref Scan disable
8226 11:06:09.273762 == TX Byte 0 ==
8227 11:06:09.277074 Update DQM dly =740 (2 ,6, 36) DQM OEN =(3 ,3)
8228 11:06:09.280549 == TX Byte 1 ==
8229 11:06:09.284099 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8230 11:06:09.284183 DramC Write-DBI off
8231 11:06:09.287338
8232 11:06:09.287422 [DATLAT]
8233 11:06:09.287489 Freq=1600, CH0 RK1
8234 11:06:09.287551
8235 11:06:09.290434 DATLAT Default: 0xf
8236 11:06:09.290548 0, 0xFFFF, sum = 0
8237 11:06:09.294166 1, 0xFFFF, sum = 0
8238 11:06:09.294281 2, 0xFFFF, sum = 0
8239 11:06:09.297290 3, 0xFFFF, sum = 0
8240 11:06:09.297375 4, 0xFFFF, sum = 0
8241 11:06:09.300691 5, 0xFFFF, sum = 0
8242 11:06:09.303845 6, 0xFFFF, sum = 0
8243 11:06:09.303930 7, 0xFFFF, sum = 0
8244 11:06:09.307230 8, 0xFFFF, sum = 0
8245 11:06:09.307314 9, 0xFFFF, sum = 0
8246 11:06:09.310666 10, 0xFFFF, sum = 0
8247 11:06:09.310750 11, 0xFFFF, sum = 0
8248 11:06:09.313864 12, 0xFFFF, sum = 0
8249 11:06:09.313969 13, 0xFFFF, sum = 0
8250 11:06:09.317093 14, 0x0, sum = 1
8251 11:06:09.317176 15, 0x0, sum = 2
8252 11:06:09.320651 16, 0x0, sum = 3
8253 11:06:09.320761 17, 0x0, sum = 4
8254 11:06:09.323797 best_step = 15
8255 11:06:09.323895
8256 11:06:09.323990 ==
8257 11:06:09.327375 Dram Type= 6, Freq= 0, CH_0, rank 1
8258 11:06:09.330580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8259 11:06:09.330651 ==
8260 11:06:09.330712 RX Vref Scan: 0
8261 11:06:09.330777
8262 11:06:09.333813 RX Vref 0 -> 0, step: 1
8263 11:06:09.333907
8264 11:06:09.337145 RX Delay 11 -> 252, step: 4
8265 11:06:09.340451 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8266 11:06:09.347240 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8267 11:06:09.350370 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8268 11:06:09.353645 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8269 11:06:09.357203 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8270 11:06:09.360494 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8271 11:06:09.363798 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8272 11:06:09.370339 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8273 11:06:09.373275 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8274 11:06:09.376937 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8275 11:06:09.379938 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8276 11:06:09.387101 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8277 11:06:09.389888 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8278 11:06:09.393206 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8279 11:06:09.396523 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8280 11:06:09.400055 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8281 11:06:09.403115 ==
8282 11:06:09.406499 Dram Type= 6, Freq= 0, CH_0, rank 1
8283 11:06:09.409771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8284 11:06:09.409856 ==
8285 11:06:09.409922 DQS Delay:
8286 11:06:09.413383 DQS0 = 0, DQS1 = 0
8287 11:06:09.413466 DQM Delay:
8288 11:06:09.416664 DQM0 = 133, DQM1 = 123
8289 11:06:09.416748 DQ Delay:
8290 11:06:09.420150 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8291 11:06:09.423271 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =138
8292 11:06:09.426410 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8293 11:06:09.429709 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8294 11:06:09.429793
8295 11:06:09.429858
8296 11:06:09.429920
8297 11:06:09.433485 [DramC_TX_OE_Calibration] TA2
8298 11:06:09.436595 Original DQ_B0 (3 6) =30, OEN = 27
8299 11:06:09.440126 Original DQ_B1 (3 6) =30, OEN = 27
8300 11:06:09.443179 24, 0x0, End_B0=24 End_B1=24
8301 11:06:09.446753 25, 0x0, End_B0=25 End_B1=25
8302 11:06:09.446839 26, 0x0, End_B0=26 End_B1=26
8303 11:06:09.449825 27, 0x0, End_B0=27 End_B1=27
8304 11:06:09.453458 28, 0x0, End_B0=28 End_B1=28
8305 11:06:09.456878 29, 0x0, End_B0=29 End_B1=29
8306 11:06:09.456964 30, 0x0, End_B0=30 End_B1=30
8307 11:06:09.460218 31, 0x4141, End_B0=30 End_B1=30
8308 11:06:09.463337 Byte0 end_step=30 best_step=27
8309 11:06:09.466661 Byte1 end_step=30 best_step=27
8310 11:06:09.470098 Byte0 TX OE(2T, 0.5T) = (3, 3)
8311 11:06:09.473075 Byte1 TX OE(2T, 0.5T) = (3, 3)
8312 11:06:09.473159
8313 11:06:09.473225
8314 11:06:09.479639 [DQSOSCAuto] RK1, (LSB)MR18= 0x230f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8315 11:06:09.482903 CH0 RK1: MR19=303, MR18=230F
8316 11:06:09.489533 CH0_RK1: MR19=0x303, MR18=0x230F, DQSOSC=392, MR23=63, INC=24, DEC=16
8317 11:06:09.493146 [RxdqsGatingPostProcess] freq 1600
8318 11:06:09.496659 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8319 11:06:09.499570 best DQS0 dly(2T, 0.5T) = (1, 1)
8320 11:06:09.503165 best DQS1 dly(2T, 0.5T) = (1, 1)
8321 11:06:09.506434 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8322 11:06:09.509609 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8323 11:06:09.513017 best DQS0 dly(2T, 0.5T) = (1, 1)
8324 11:06:09.516253 best DQS1 dly(2T, 0.5T) = (1, 1)
8325 11:06:09.519712 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8326 11:06:09.522903 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8327 11:06:09.526596 Pre-setting of DQS Precalculation
8328 11:06:09.529371 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8329 11:06:09.529455 ==
8330 11:06:09.532678 Dram Type= 6, Freq= 0, CH_1, rank 0
8331 11:06:09.539367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 11:06:09.539452 ==
8333 11:06:09.542879 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8334 11:06:09.545989 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8335 11:06:09.552690 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8336 11:06:09.559251 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8337 11:06:09.566666 [CA 0] Center 40 (11~70) winsize 60
8338 11:06:09.569900 [CA 1] Center 41 (11~71) winsize 61
8339 11:06:09.573274 [CA 2] Center 37 (7~67) winsize 61
8340 11:06:09.576660 [CA 3] Center 36 (7~66) winsize 60
8341 11:06:09.580035 [CA 4] Center 36 (7~66) winsize 60
8342 11:06:09.583459 [CA 5] Center 36 (6~66) winsize 61
8343 11:06:09.583543
8344 11:06:09.586627 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8345 11:06:09.586711
8346 11:06:09.590096 [CATrainingPosCal] consider 1 rank data
8347 11:06:09.593647 u2DelayCellTimex100 = 290/100 ps
8348 11:06:09.596692 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8349 11:06:09.603421 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8350 11:06:09.606660 CA2 delay=37 (7~67),Diff = 1 PI (3 cell)
8351 11:06:09.609970 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8352 11:06:09.613102 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8353 11:06:09.616883 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8354 11:06:09.616970
8355 11:06:09.619745 CA PerBit enable=1, Macro0, CA PI delay=36
8356 11:06:09.619829
8357 11:06:09.623252 [CBTSetCACLKResult] CA Dly = 36
8358 11:06:09.626807 CS Dly: 9 (0~40)
8359 11:06:09.629769 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8360 11:06:09.633235 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8361 11:06:09.633317 ==
8362 11:06:09.636659 Dram Type= 6, Freq= 0, CH_1, rank 1
8363 11:06:09.640140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8364 11:06:09.640243 ==
8365 11:06:09.646803 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8366 11:06:09.649794 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8367 11:06:09.656728 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8368 11:06:09.660048 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8369 11:06:09.669733 [CA 0] Center 43 (14~72) winsize 59
8370 11:06:09.673193 [CA 1] Center 42 (13~72) winsize 60
8371 11:06:09.676555 [CA 2] Center 38 (9~68) winsize 60
8372 11:06:09.679701 [CA 3] Center 37 (8~67) winsize 60
8373 11:06:09.683153 [CA 4] Center 38 (9~68) winsize 60
8374 11:06:09.686648 [CA 5] Center 37 (8~67) winsize 60
8375 11:06:09.686729
8376 11:06:09.689784 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8377 11:06:09.689891
8378 11:06:09.693207 [CATrainingPosCal] consider 2 rank data
8379 11:06:09.696450 u2DelayCellTimex100 = 290/100 ps
8380 11:06:09.699940 CA0 delay=42 (14~70),Diff = 5 PI (16 cell)
8381 11:06:09.706143 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8382 11:06:09.709668 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8383 11:06:09.713215 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8384 11:06:09.716167 CA4 delay=37 (9~66),Diff = 0 PI (0 cell)
8385 11:06:09.719909 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8386 11:06:09.719991
8387 11:06:09.722795 CA PerBit enable=1, Macro0, CA PI delay=37
8388 11:06:09.722876
8389 11:06:09.726603 [CBTSetCACLKResult] CA Dly = 37
8390 11:06:09.729798 CS Dly: 10 (0~42)
8391 11:06:09.732991 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8392 11:06:09.736309 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8393 11:06:09.736390
8394 11:06:09.739660 ----->DramcWriteLeveling(PI) begin...
8395 11:06:09.739844 ==
8396 11:06:09.743236 Dram Type= 6, Freq= 0, CH_1, rank 0
8397 11:06:09.746593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 11:06:09.749890 ==
8399 11:06:09.750033 Write leveling (Byte 0): 25 => 25
8400 11:06:09.753050 Write leveling (Byte 1): 27 => 27
8401 11:06:09.756478 DramcWriteLeveling(PI) end<-----
8402 11:06:09.756577
8403 11:06:09.756665 ==
8404 11:06:09.759648 Dram Type= 6, Freq= 0, CH_1, rank 0
8405 11:06:09.766207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8406 11:06:09.766291 ==
8407 11:06:09.766355 [Gating] SW mode calibration
8408 11:06:09.776156 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8409 11:06:09.779947 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8410 11:06:09.783114 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 11:06:09.789689 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 11:06:09.793129 1 4 8 | B1->B0 | 2e2e 3232 | 0 0 | (0 0) (0 0)
8413 11:06:09.795952 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 11:06:09.802571 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8415 11:06:09.805828 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 11:06:09.809213 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 11:06:09.815802 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 11:06:09.819108 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 11:06:09.822691 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 11:06:09.829235 1 5 8 | B1->B0 | 2d2d 2b2b | 1 0 | (1 0) (1 0)
8421 11:06:09.832473 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8422 11:06:09.835650 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 11:06:09.842607 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 11:06:09.845989 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 11:06:09.849156 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 11:06:09.855585 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 11:06:09.859272 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8428 11:06:09.862364 1 6 8 | B1->B0 | 3939 3f3f | 1 0 | (0 0) (1 1)
8429 11:06:09.869065 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 11:06:09.872084 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 11:06:09.875567 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 11:06:09.882163 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 11:06:09.885412 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 11:06:09.888862 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 11:06:09.895745 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 11:06:09.898566 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8437 11:06:09.902425 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8438 11:06:09.908635 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 11:06:09.912035 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 11:06:09.915475 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 11:06:09.922236 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 11:06:09.925320 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 11:06:09.928866 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 11:06:09.935306 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 11:06:09.938831 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 11:06:09.941974 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 11:06:09.948558 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 11:06:09.951920 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 11:06:09.955233 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 11:06:09.958572 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 11:06:09.965097 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 11:06:09.968572 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8453 11:06:09.972112 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8454 11:06:09.975221 Total UI for P1: 0, mck2ui 16
8455 11:06:09.978710 best dqsien dly found for B0: ( 1, 9, 8)
8456 11:06:09.982135 Total UI for P1: 0, mck2ui 16
8457 11:06:09.985091 best dqsien dly found for B1: ( 1, 9, 8)
8458 11:06:09.988624 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8459 11:06:09.991944 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8460 11:06:09.992029
8461 11:06:09.998526 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8462 11:06:10.001970 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8463 11:06:10.005326 [Gating] SW calibration Done
8464 11:06:10.005413 ==
8465 11:06:10.008565 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 11:06:10.012041 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 11:06:10.012148 ==
8468 11:06:10.012241 RX Vref Scan: 0
8469 11:06:10.012328
8470 11:06:10.015398 RX Vref 0 -> 0, step: 1
8471 11:06:10.015494
8472 11:06:10.018760 RX Delay 0 -> 252, step: 8
8473 11:06:10.022060 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8474 11:06:10.025415 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8475 11:06:10.028626 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8476 11:06:10.035470 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8477 11:06:10.038740 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8478 11:06:10.042057 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8479 11:06:10.045498 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8480 11:06:10.048742 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8481 11:06:10.052116 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8482 11:06:10.058863 iDelay=200, Bit 9, Center 123 (80 ~ 167) 88
8483 11:06:10.061786 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8484 11:06:10.065030 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8485 11:06:10.068840 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8486 11:06:10.075257 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8487 11:06:10.078435 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8488 11:06:10.081886 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8489 11:06:10.081994 ==
8490 11:06:10.085462 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 11:06:10.088611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 11:06:10.088712 ==
8493 11:06:10.091974 DQS Delay:
8494 11:06:10.092076 DQS0 = 0, DQS1 = 0
8495 11:06:10.092166 DQM Delay:
8496 11:06:10.095458 DQM0 = 138, DQM1 = 130
8497 11:06:10.095542 DQ Delay:
8498 11:06:10.098986 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8499 11:06:10.101836 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8500 11:06:10.108528 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
8501 11:06:10.111859 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8502 11:06:10.111960
8503 11:06:10.112053
8504 11:06:10.112142 ==
8505 11:06:10.115169 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 11:06:10.118402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8507 11:06:10.118475 ==
8508 11:06:10.118541
8509 11:06:10.118625
8510 11:06:10.122071 TX Vref Scan disable
8511 11:06:10.125368 == TX Byte 0 ==
8512 11:06:10.128348 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8513 11:06:10.131735 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8514 11:06:10.135024 == TX Byte 1 ==
8515 11:06:10.138365 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8516 11:06:10.142118 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8517 11:06:10.142222 ==
8518 11:06:10.145050 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 11:06:10.148611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 11:06:10.148713 ==
8521 11:06:10.162519
8522 11:06:10.165857 TX Vref early break, caculate TX vref
8523 11:06:10.169280 TX Vref=16, minBit 10, minWin=22, winSum=375
8524 11:06:10.172637 TX Vref=18, minBit 15, minWin=22, winSum=380
8525 11:06:10.175450 TX Vref=20, minBit 10, minWin=22, winSum=393
8526 11:06:10.179128 TX Vref=22, minBit 0, minWin=24, winSum=402
8527 11:06:10.182055 TX Vref=24, minBit 15, minWin=24, winSum=412
8528 11:06:10.188732 TX Vref=26, minBit 14, minWin=24, winSum=420
8529 11:06:10.192147 TX Vref=28, minBit 10, minWin=25, winSum=426
8530 11:06:10.195336 TX Vref=30, minBit 0, minWin=25, winSum=417
8531 11:06:10.198879 TX Vref=32, minBit 9, minWin=24, winSum=407
8532 11:06:10.202304 TX Vref=34, minBit 5, minWin=24, winSum=399
8533 11:06:10.208661 [TxChooseVref] Worse bit 10, Min win 25, Win sum 426, Final Vref 28
8534 11:06:10.208745
8535 11:06:10.212324 Final TX Range 0 Vref 28
8536 11:06:10.212408
8537 11:06:10.212473 ==
8538 11:06:10.215620 Dram Type= 6, Freq= 0, CH_1, rank 0
8539 11:06:10.218884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8540 11:06:10.218968 ==
8541 11:06:10.219034
8542 11:06:10.221847
8543 11:06:10.221960 TX Vref Scan disable
8544 11:06:10.228658 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8545 11:06:10.228742 == TX Byte 0 ==
8546 11:06:10.232022 u2DelayCellOfst[0]=13 cells (4 PI)
8547 11:06:10.235296 u2DelayCellOfst[1]=10 cells (3 PI)
8548 11:06:10.238686 u2DelayCellOfst[2]=0 cells (0 PI)
8549 11:06:10.241849 u2DelayCellOfst[3]=6 cells (2 PI)
8550 11:06:10.245216 u2DelayCellOfst[4]=6 cells (2 PI)
8551 11:06:10.248463 u2DelayCellOfst[5]=16 cells (5 PI)
8552 11:06:10.251765 u2DelayCellOfst[6]=16 cells (5 PI)
8553 11:06:10.255206 u2DelayCellOfst[7]=3 cells (1 PI)
8554 11:06:10.258864 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8555 11:06:10.261845 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8556 11:06:10.265120 == TX Byte 1 ==
8557 11:06:10.268667 u2DelayCellOfst[8]=0 cells (0 PI)
8558 11:06:10.268753 u2DelayCellOfst[9]=3 cells (1 PI)
8559 11:06:10.271902 u2DelayCellOfst[10]=10 cells (3 PI)
8560 11:06:10.275146 u2DelayCellOfst[11]=3 cells (1 PI)
8561 11:06:10.278534 u2DelayCellOfst[12]=13 cells (4 PI)
8562 11:06:10.281867 u2DelayCellOfst[13]=16 cells (5 PI)
8563 11:06:10.284983 u2DelayCellOfst[14]=20 cells (6 PI)
8564 11:06:10.288319 u2DelayCellOfst[15]=16 cells (5 PI)
8565 11:06:10.291862 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8566 11:06:10.298470 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8567 11:06:10.298556 DramC Write-DBI on
8568 11:06:10.298641 ==
8569 11:06:10.301601 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 11:06:10.308419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 11:06:10.308505 ==
8572 11:06:10.308590
8573 11:06:10.308669
8574 11:06:10.308747 TX Vref Scan disable
8575 11:06:10.312283 == TX Byte 0 ==
8576 11:06:10.315704 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8577 11:06:10.318555 == TX Byte 1 ==
8578 11:06:10.321981 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8579 11:06:10.325674 DramC Write-DBI off
8580 11:06:10.325759
8581 11:06:10.325862 [DATLAT]
8582 11:06:10.325967 Freq=1600, CH1 RK0
8583 11:06:10.326091
8584 11:06:10.328911 DATLAT Default: 0xf
8585 11:06:10.328996 0, 0xFFFF, sum = 0
8586 11:06:10.332090 1, 0xFFFF, sum = 0
8587 11:06:10.332177 2, 0xFFFF, sum = 0
8588 11:06:10.335335 3, 0xFFFF, sum = 0
8589 11:06:10.338804 4, 0xFFFF, sum = 0
8590 11:06:10.338894 5, 0xFFFF, sum = 0
8591 11:06:10.341922 6, 0xFFFF, sum = 0
8592 11:06:10.342050 7, 0xFFFF, sum = 0
8593 11:06:10.345402 8, 0xFFFF, sum = 0
8594 11:06:10.345490 9, 0xFFFF, sum = 0
8595 11:06:10.348692 10, 0xFFFF, sum = 0
8596 11:06:10.348779 11, 0xFFFF, sum = 0
8597 11:06:10.351996 12, 0xFFFF, sum = 0
8598 11:06:10.352083 13, 0xFFFF, sum = 0
8599 11:06:10.355370 14, 0x0, sum = 1
8600 11:06:10.355457 15, 0x0, sum = 2
8601 11:06:10.358579 16, 0x0, sum = 3
8602 11:06:10.358666 17, 0x0, sum = 4
8603 11:06:10.361844 best_step = 15
8604 11:06:10.361930
8605 11:06:10.362020 ==
8606 11:06:10.365138 Dram Type= 6, Freq= 0, CH_1, rank 0
8607 11:06:10.368467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8608 11:06:10.368553 ==
8609 11:06:10.368638 RX Vref Scan: 1
8610 11:06:10.371769
8611 11:06:10.371853 Set Vref Range= 24 -> 127
8612 11:06:10.371939
8613 11:06:10.375055 RX Vref 24 -> 127, step: 1
8614 11:06:10.375140
8615 11:06:10.378451 RX Delay 19 -> 252, step: 4
8616 11:06:10.378536
8617 11:06:10.381869 Set Vref, RX VrefLevel [Byte0]: 24
8618 11:06:10.385166 [Byte1]: 24
8619 11:06:10.385252
8620 11:06:10.388738 Set Vref, RX VrefLevel [Byte0]: 25
8621 11:06:10.391694 [Byte1]: 25
8622 11:06:10.391777
8623 11:06:10.395233 Set Vref, RX VrefLevel [Byte0]: 26
8624 11:06:10.398358 [Byte1]: 26
8625 11:06:10.402287
8626 11:06:10.402368 Set Vref, RX VrefLevel [Byte0]: 27
8627 11:06:10.405698 [Byte1]: 27
8628 11:06:10.409920
8629 11:06:10.410033 Set Vref, RX VrefLevel [Byte0]: 28
8630 11:06:10.413063 [Byte1]: 28
8631 11:06:10.417473
8632 11:06:10.417547 Set Vref, RX VrefLevel [Byte0]: 29
8633 11:06:10.420546 [Byte1]: 29
8634 11:06:10.424940
8635 11:06:10.425010 Set Vref, RX VrefLevel [Byte0]: 30
8636 11:06:10.428330 [Byte1]: 30
8637 11:06:10.432636
8638 11:06:10.432705 Set Vref, RX VrefLevel [Byte0]: 31
8639 11:06:10.435917 [Byte1]: 31
8640 11:06:10.440048
8641 11:06:10.440133 Set Vref, RX VrefLevel [Byte0]: 32
8642 11:06:10.443429 [Byte1]: 32
8643 11:06:10.447804
8644 11:06:10.447879 Set Vref, RX VrefLevel [Byte0]: 33
8645 11:06:10.451090 [Byte1]: 33
8646 11:06:10.455335
8647 11:06:10.455409 Set Vref, RX VrefLevel [Byte0]: 34
8648 11:06:10.458667 [Byte1]: 34
8649 11:06:10.463171
8650 11:06:10.463244 Set Vref, RX VrefLevel [Byte0]: 35
8651 11:06:10.466328 [Byte1]: 35
8652 11:06:10.470343
8653 11:06:10.470417 Set Vref, RX VrefLevel [Byte0]: 36
8654 11:06:10.474065 [Byte1]: 36
8655 11:06:10.478205
8656 11:06:10.478277 Set Vref, RX VrefLevel [Byte0]: 37
8657 11:06:10.481135 [Byte1]: 37
8658 11:06:10.485711
8659 11:06:10.485780 Set Vref, RX VrefLevel [Byte0]: 38
8660 11:06:10.489055 [Byte1]: 38
8661 11:06:10.493336
8662 11:06:10.496392 Set Vref, RX VrefLevel [Byte0]: 39
8663 11:06:10.496468 [Byte1]: 39
8664 11:06:10.500912
8665 11:06:10.500986 Set Vref, RX VrefLevel [Byte0]: 40
8666 11:06:10.504099 [Byte1]: 40
8667 11:06:10.508357
8668 11:06:10.508437 Set Vref, RX VrefLevel [Byte0]: 41
8669 11:06:10.511833 [Byte1]: 41
8670 11:06:10.516109
8671 11:06:10.516183 Set Vref, RX VrefLevel [Byte0]: 42
8672 11:06:10.519137 [Byte1]: 42
8673 11:06:10.523616
8674 11:06:10.523695 Set Vref, RX VrefLevel [Byte0]: 43
8675 11:06:10.526956 [Byte1]: 43
8676 11:06:10.531312
8677 11:06:10.531386 Set Vref, RX VrefLevel [Byte0]: 44
8678 11:06:10.534272 [Byte1]: 44
8679 11:06:10.538919
8680 11:06:10.538990 Set Vref, RX VrefLevel [Byte0]: 45
8681 11:06:10.541801 [Byte1]: 45
8682 11:06:10.546087
8683 11:06:10.546166 Set Vref, RX VrefLevel [Byte0]: 46
8684 11:06:10.549361 [Byte1]: 46
8685 11:06:10.553615
8686 11:06:10.553692 Set Vref, RX VrefLevel [Byte0]: 47
8687 11:06:10.556917 [Byte1]: 47
8688 11:06:10.561632
8689 11:06:10.561703 Set Vref, RX VrefLevel [Byte0]: 48
8690 11:06:10.564979 [Byte1]: 48
8691 11:06:10.569054
8692 11:06:10.569128 Set Vref, RX VrefLevel [Byte0]: 49
8693 11:06:10.572358 [Byte1]: 49
8694 11:06:10.576439
8695 11:06:10.576510 Set Vref, RX VrefLevel [Byte0]: 50
8696 11:06:10.579662 [Byte1]: 50
8697 11:06:10.584395
8698 11:06:10.584466 Set Vref, RX VrefLevel [Byte0]: 51
8699 11:06:10.587259 [Byte1]: 51
8700 11:06:10.591594
8701 11:06:10.591667 Set Vref, RX VrefLevel [Byte0]: 52
8702 11:06:10.595030 [Byte1]: 52
8703 11:06:10.599176
8704 11:06:10.599251 Set Vref, RX VrefLevel [Byte0]: 53
8705 11:06:10.602384 [Byte1]: 53
8706 11:06:10.606799
8707 11:06:10.606873 Set Vref, RX VrefLevel [Byte0]: 54
8708 11:06:10.610274 [Byte1]: 54
8709 11:06:10.614515
8710 11:06:10.614591 Set Vref, RX VrefLevel [Byte0]: 55
8711 11:06:10.617904 [Byte1]: 55
8712 11:06:10.621929
8713 11:06:10.622041 Set Vref, RX VrefLevel [Byte0]: 56
8714 11:06:10.625309 [Byte1]: 56
8715 11:06:10.629468
8716 11:06:10.629543 Set Vref, RX VrefLevel [Byte0]: 57
8717 11:06:10.632888 [Byte1]: 57
8718 11:06:10.636947
8719 11:06:10.637022 Set Vref, RX VrefLevel [Byte0]: 58
8720 11:06:10.640223 [Byte1]: 58
8721 11:06:10.644814
8722 11:06:10.644892 Set Vref, RX VrefLevel [Byte0]: 59
8723 11:06:10.648109 [Byte1]: 59
8724 11:06:10.652319
8725 11:06:10.652391 Set Vref, RX VrefLevel [Byte0]: 60
8726 11:06:10.655736 [Byte1]: 60
8727 11:06:10.660048
8728 11:06:10.660119 Set Vref, RX VrefLevel [Byte0]: 61
8729 11:06:10.662882 [Byte1]: 61
8730 11:06:10.667453
8731 11:06:10.667527 Set Vref, RX VrefLevel [Byte0]: 62
8732 11:06:10.670617 [Byte1]: 62
8733 11:06:10.674816
8734 11:06:10.674886 Set Vref, RX VrefLevel [Byte0]: 63
8735 11:06:10.678078 [Byte1]: 63
8736 11:06:10.682385
8737 11:06:10.682459 Set Vref, RX VrefLevel [Byte0]: 64
8738 11:06:10.685864 [Byte1]: 64
8739 11:06:10.690069
8740 11:06:10.690142 Set Vref, RX VrefLevel [Byte0]: 65
8741 11:06:10.693301 [Byte1]: 65
8742 11:06:10.697699
8743 11:06:10.697775 Set Vref, RX VrefLevel [Byte0]: 66
8744 11:06:10.701011 [Byte1]: 66
8745 11:06:10.705335
8746 11:06:10.705406 Set Vref, RX VrefLevel [Byte0]: 67
8747 11:06:10.708522 [Byte1]: 67
8748 11:06:10.712738
8749 11:06:10.712815 Set Vref, RX VrefLevel [Byte0]: 68
8750 11:06:10.716231 [Byte1]: 68
8751 11:06:10.720441
8752 11:06:10.720521 Set Vref, RX VrefLevel [Byte0]: 69
8753 11:06:10.723664 [Byte1]: 69
8754 11:06:10.728026
8755 11:06:10.728107 Set Vref, RX VrefLevel [Byte0]: 70
8756 11:06:10.731286 [Byte1]: 70
8757 11:06:10.735389
8758 11:06:10.735463 Set Vref, RX VrefLevel [Byte0]: 71
8759 11:06:10.738888 [Byte1]: 71
8760 11:06:10.743332
8761 11:06:10.743410 Set Vref, RX VrefLevel [Byte0]: 72
8762 11:06:10.746683 [Byte1]: 72
8763 11:06:10.750546
8764 11:06:10.750619 Set Vref, RX VrefLevel [Byte0]: 73
8765 11:06:10.754198 [Byte1]: 73
8766 11:06:10.758179
8767 11:06:10.758254 Set Vref, RX VrefLevel [Byte0]: 74
8768 11:06:10.761691 [Byte1]: 74
8769 11:06:10.765872
8770 11:06:10.765959 Set Vref, RX VrefLevel [Byte0]: 75
8771 11:06:10.769397 [Byte1]: 75
8772 11:06:10.773223
8773 11:06:10.773297 Final RX Vref Byte 0 = 51 to rank0
8774 11:06:10.776973 Final RX Vref Byte 1 = 62 to rank0
8775 11:06:10.779915 Final RX Vref Byte 0 = 51 to rank1
8776 11:06:10.783268 Final RX Vref Byte 1 = 62 to rank1==
8777 11:06:10.786964 Dram Type= 6, Freq= 0, CH_1, rank 0
8778 11:06:10.793541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8779 11:06:10.793617 ==
8780 11:06:10.793680 DQS Delay:
8781 11:06:10.793737 DQS0 = 0, DQS1 = 0
8782 11:06:10.796666 DQM Delay:
8783 11:06:10.796734 DQM0 = 133, DQM1 = 129
8784 11:06:10.800168 DQ Delay:
8785 11:06:10.803399 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8786 11:06:10.806680 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8787 11:06:10.810067 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8788 11:06:10.813262 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8789 11:06:10.813332
8790 11:06:10.813393
8791 11:06:10.813467
8792 11:06:10.816735 [DramC_TX_OE_Calibration] TA2
8793 11:06:10.819952 Original DQ_B0 (3 6) =30, OEN = 27
8794 11:06:10.823192 Original DQ_B1 (3 6) =30, OEN = 27
8795 11:06:10.826674 24, 0x0, End_B0=24 End_B1=24
8796 11:06:10.826750 25, 0x0, End_B0=25 End_B1=25
8797 11:06:10.829796 26, 0x0, End_B0=26 End_B1=26
8798 11:06:10.832925 27, 0x0, End_B0=27 End_B1=27
8799 11:06:10.836532 28, 0x0, End_B0=28 End_B1=28
8800 11:06:10.839716 29, 0x0, End_B0=29 End_B1=29
8801 11:06:10.839790 30, 0x0, End_B0=30 End_B1=30
8802 11:06:10.843419 31, 0x4141, End_B0=30 End_B1=30
8803 11:06:10.846671 Byte0 end_step=30 best_step=27
8804 11:06:10.849864 Byte1 end_step=30 best_step=27
8805 11:06:10.853247 Byte0 TX OE(2T, 0.5T) = (3, 3)
8806 11:06:10.856599 Byte1 TX OE(2T, 0.5T) = (3, 3)
8807 11:06:10.856670
8808 11:06:10.856731
8809 11:06:10.863176 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8810 11:06:10.866395 CH1 RK0: MR19=303, MR18=1624
8811 11:06:10.873038 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8812 11:06:10.873110
8813 11:06:10.876371 ----->DramcWriteLeveling(PI) begin...
8814 11:06:10.876441 ==
8815 11:06:10.879633 Dram Type= 6, Freq= 0, CH_1, rank 1
8816 11:06:10.882983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8817 11:06:10.883052 ==
8818 11:06:10.886602 Write leveling (Byte 0): 27 => 27
8819 11:06:10.889806 Write leveling (Byte 1): 29 => 29
8820 11:06:10.893056 DramcWriteLeveling(PI) end<-----
8821 11:06:10.893132
8822 11:06:10.893193 ==
8823 11:06:10.896692 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 11:06:10.899833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 11:06:10.899918 ==
8826 11:06:10.902879 [Gating] SW mode calibration
8827 11:06:10.909505 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8828 11:06:10.916565 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8829 11:06:10.919872 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 11:06:10.923319 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 11:06:10.929379 1 4 8 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
8832 11:06:10.932756 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 11:06:10.936300 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 11:06:10.943060 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 11:06:10.946636 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 11:06:10.949299 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 11:06:10.956008 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 11:06:10.959400 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 11:06:10.962712 1 5 8 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 0)
8840 11:06:10.969290 1 5 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
8841 11:06:10.972655 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 11:06:10.975847 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 11:06:10.982809 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 11:06:10.986061 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 11:06:10.989642 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 11:06:10.995946 1 6 4 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
8847 11:06:10.999260 1 6 8 | B1->B0 | 4545 2323 | 0 0 | (0 0) (0 0)
8848 11:06:11.002868 1 6 12 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
8849 11:06:11.009326 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 11:06:11.012667 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 11:06:11.015980 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 11:06:11.022665 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 11:06:11.025842 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 11:06:11.029050 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8855 11:06:11.032470 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8856 11:06:11.039227 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8857 11:06:11.042422 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 11:06:11.045994 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 11:06:11.052445 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 11:06:11.055579 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 11:06:11.059100 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 11:06:11.065573 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 11:06:11.068775 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 11:06:11.072337 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 11:06:11.079103 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 11:06:11.082341 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 11:06:11.085581 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 11:06:11.092071 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 11:06:11.095229 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 11:06:11.098689 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 11:06:11.105530 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8872 11:06:11.108739 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8873 11:06:11.112044 Total UI for P1: 0, mck2ui 16
8874 11:06:11.115550 best dqsien dly found for B0: ( 1, 9, 8)
8875 11:06:11.118850 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8876 11:06:11.121806 Total UI for P1: 0, mck2ui 16
8877 11:06:11.125559 best dqsien dly found for B1: ( 1, 9, 10)
8878 11:06:11.128811 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8879 11:06:11.131848 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8880 11:06:11.131946
8881 11:06:11.138869 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8882 11:06:11.142037 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8883 11:06:11.142140 [Gating] SW calibration Done
8884 11:06:11.145355 ==
8885 11:06:11.148441 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 11:06:11.151780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 11:06:11.151865 ==
8888 11:06:11.151932 RX Vref Scan: 0
8889 11:06:11.151992
8890 11:06:11.155353 RX Vref 0 -> 0, step: 1
8891 11:06:11.155437
8892 11:06:11.158432 RX Delay 0 -> 252, step: 8
8893 11:06:11.161810 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8894 11:06:11.165216 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8895 11:06:11.168604 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8896 11:06:11.175332 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8897 11:06:11.178577 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8898 11:06:11.181916 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8899 11:06:11.185272 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8900 11:06:11.188546 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8901 11:06:11.191733 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8902 11:06:11.198558 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8903 11:06:11.201697 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8904 11:06:11.205058 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8905 11:06:11.208438 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8906 11:06:11.214882 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8907 11:06:11.218429 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8908 11:06:11.221665 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8909 11:06:11.221749 ==
8910 11:06:11.225070 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 11:06:11.228445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 11:06:11.228529 ==
8913 11:06:11.231922 DQS Delay:
8914 11:06:11.232005 DQS0 = 0, DQS1 = 0
8915 11:06:11.235066 DQM Delay:
8916 11:06:11.235150 DQM0 = 137, DQM1 = 132
8917 11:06:11.235217 DQ Delay:
8918 11:06:11.241406 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135
8919 11:06:11.245112 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =139
8920 11:06:11.248342 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8921 11:06:11.251769 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8922 11:06:11.251854
8923 11:06:11.251919
8924 11:06:11.251980 ==
8925 11:06:11.254887 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 11:06:11.258236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 11:06:11.258320 ==
8928 11:06:11.258386
8929 11:06:11.258447
8930 11:06:11.261541 TX Vref Scan disable
8931 11:06:11.264688 == TX Byte 0 ==
8932 11:06:11.268135 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8933 11:06:11.271380 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8934 11:06:11.274773 == TX Byte 1 ==
8935 11:06:11.278147 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8936 11:06:11.281401 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8937 11:06:11.281485 ==
8938 11:06:11.284653 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 11:06:11.288083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 11:06:11.291339 ==
8941 11:06:11.302574
8942 11:06:11.306118 TX Vref early break, caculate TX vref
8943 11:06:11.309376 TX Vref=16, minBit 9, minWin=21, winSum=377
8944 11:06:11.312620 TX Vref=18, minBit 9, minWin=22, winSum=385
8945 11:06:11.315976 TX Vref=20, minBit 8, minWin=23, winSum=388
8946 11:06:11.318886 TX Vref=22, minBit 9, minWin=23, winSum=405
8947 11:06:11.322620 TX Vref=24, minBit 9, minWin=24, winSum=412
8948 11:06:11.329120 TX Vref=26, minBit 10, minWin=24, winSum=416
8949 11:06:11.332444 TX Vref=28, minBit 8, minWin=24, winSum=416
8950 11:06:11.335646 TX Vref=30, minBit 9, minWin=24, winSum=410
8951 11:06:11.338987 TX Vref=32, minBit 9, minWin=24, winSum=403
8952 11:06:11.342242 TX Vref=34, minBit 9, minWin=23, winSum=394
8953 11:06:11.349075 [TxChooseVref] Worse bit 10, Min win 24, Win sum 416, Final Vref 26
8954 11:06:11.349160
8955 11:06:11.352338 Final TX Range 0 Vref 26
8956 11:06:11.352423
8957 11:06:11.352490 ==
8958 11:06:11.355756 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 11:06:11.358840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 11:06:11.358924 ==
8961 11:06:11.358991
8962 11:06:11.359052
8963 11:06:11.362179 TX Vref Scan disable
8964 11:06:11.368737 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8965 11:06:11.368822 == TX Byte 0 ==
8966 11:06:11.372046 u2DelayCellOfst[0]=16 cells (5 PI)
8967 11:06:11.375589 u2DelayCellOfst[1]=10 cells (3 PI)
8968 11:06:11.378766 u2DelayCellOfst[2]=0 cells (0 PI)
8969 11:06:11.382072 u2DelayCellOfst[3]=6 cells (2 PI)
8970 11:06:11.385425 u2DelayCellOfst[4]=6 cells (2 PI)
8971 11:06:11.388891 u2DelayCellOfst[5]=20 cells (6 PI)
8972 11:06:11.392127 u2DelayCellOfst[6]=16 cells (5 PI)
8973 11:06:11.395452 u2DelayCellOfst[7]=6 cells (2 PI)
8974 11:06:11.398557 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8975 11:06:11.402127 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8976 11:06:11.405393 == TX Byte 1 ==
8977 11:06:11.405476 u2DelayCellOfst[8]=0 cells (0 PI)
8978 11:06:11.408520 u2DelayCellOfst[9]=3 cells (1 PI)
8979 11:06:11.412196 u2DelayCellOfst[10]=6 cells (2 PI)
8980 11:06:11.415182 u2DelayCellOfst[11]=3 cells (1 PI)
8981 11:06:11.418847 u2DelayCellOfst[12]=10 cells (3 PI)
8982 11:06:11.422115 u2DelayCellOfst[13]=16 cells (5 PI)
8983 11:06:11.425375 u2DelayCellOfst[14]=16 cells (5 PI)
8984 11:06:11.429054 u2DelayCellOfst[15]=16 cells (5 PI)
8985 11:06:11.431980 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8986 11:06:11.439011 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8987 11:06:11.439095 DramC Write-DBI on
8988 11:06:11.439161 ==
8989 11:06:11.442320 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 11:06:11.445418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 11:06:11.445503 ==
8992 11:06:11.448676
8993 11:06:11.448760
8994 11:06:11.448827 TX Vref Scan disable
8995 11:06:11.451865 == TX Byte 0 ==
8996 11:06:11.455152 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8997 11:06:11.458469 == TX Byte 1 ==
8998 11:06:11.462045 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8999 11:06:11.462129 DramC Write-DBI off
9000 11:06:11.465277
9001 11:06:11.465360 [DATLAT]
9002 11:06:11.465427 Freq=1600, CH1 RK1
9003 11:06:11.465489
9004 11:06:11.468712 DATLAT Default: 0xf
9005 11:06:11.468796 0, 0xFFFF, sum = 0
9006 11:06:11.472250 1, 0xFFFF, sum = 0
9007 11:06:11.472335 2, 0xFFFF, sum = 0
9008 11:06:11.475235 3, 0xFFFF, sum = 0
9009 11:06:11.475320 4, 0xFFFF, sum = 0
9010 11:06:11.478513 5, 0xFFFF, sum = 0
9011 11:06:11.481843 6, 0xFFFF, sum = 0
9012 11:06:11.481928 7, 0xFFFF, sum = 0
9013 11:06:11.485000 8, 0xFFFF, sum = 0
9014 11:06:11.485085 9, 0xFFFF, sum = 0
9015 11:06:11.488779 10, 0xFFFF, sum = 0
9016 11:06:11.488864 11, 0xFFFF, sum = 0
9017 11:06:11.492136 12, 0xFFFF, sum = 0
9018 11:06:11.492222 13, 0xFFFF, sum = 0
9019 11:06:11.495317 14, 0x0, sum = 1
9020 11:06:11.495402 15, 0x0, sum = 2
9021 11:06:11.498720 16, 0x0, sum = 3
9022 11:06:11.498805 17, 0x0, sum = 4
9023 11:06:11.501951 best_step = 15
9024 11:06:11.502036
9025 11:06:11.502103 ==
9026 11:06:11.505269 Dram Type= 6, Freq= 0, CH_1, rank 1
9027 11:06:11.508680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9028 11:06:11.508765 ==
9029 11:06:11.508831 RX Vref Scan: 0
9030 11:06:11.508893
9031 11:06:11.511938 RX Vref 0 -> 0, step: 1
9032 11:06:11.512022
9033 11:06:11.515350 RX Delay 19 -> 252, step: 4
9034 11:06:11.518566 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
9035 11:06:11.521870 iDelay=195, Bit 1, Center 130 (87 ~ 174) 88
9036 11:06:11.528606 iDelay=195, Bit 2, Center 120 (75 ~ 166) 92
9037 11:06:11.531875 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9038 11:06:11.535416 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9039 11:06:11.538880 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9040 11:06:11.541999 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9041 11:06:11.545421 iDelay=195, Bit 7, Center 132 (87 ~ 178) 92
9042 11:06:11.551790 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9043 11:06:11.555049 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9044 11:06:11.558307 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9045 11:06:11.561674 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9046 11:06:11.565351 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9047 11:06:11.571727 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9048 11:06:11.574984 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9049 11:06:11.578597 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9050 11:06:11.578680 ==
9051 11:06:11.581885 Dram Type= 6, Freq= 0, CH_1, rank 1
9052 11:06:11.584950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9053 11:06:11.588388 ==
9054 11:06:11.588471 DQS Delay:
9055 11:06:11.588536 DQS0 = 0, DQS1 = 0
9056 11:06:11.591922 DQM Delay:
9057 11:06:11.592005 DQM0 = 133, DQM1 = 130
9058 11:06:11.595265 DQ Delay:
9059 11:06:11.598131 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
9060 11:06:11.601576 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =132
9061 11:06:11.604773 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
9062 11:06:11.608389 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9063 11:06:11.608503
9064 11:06:11.608598
9065 11:06:11.608685
9066 11:06:11.611689 [DramC_TX_OE_Calibration] TA2
9067 11:06:11.615045 Original DQ_B0 (3 6) =30, OEN = 27
9068 11:06:11.618061 Original DQ_B1 (3 6) =30, OEN = 27
9069 11:06:11.621671 24, 0x0, End_B0=24 End_B1=24
9070 11:06:11.621755 25, 0x0, End_B0=25 End_B1=25
9071 11:06:11.624906 26, 0x0, End_B0=26 End_B1=26
9072 11:06:11.628243 27, 0x0, End_B0=27 End_B1=27
9073 11:06:11.631510 28, 0x0, End_B0=28 End_B1=28
9074 11:06:11.631601 29, 0x0, End_B0=29 End_B1=29
9075 11:06:11.634835 30, 0x0, End_B0=30 End_B1=30
9076 11:06:11.638138 31, 0x4141, End_B0=30 End_B1=30
9077 11:06:11.641482 Byte0 end_step=30 best_step=27
9078 11:06:11.644473 Byte1 end_step=30 best_step=27
9079 11:06:11.647879 Byte0 TX OE(2T, 0.5T) = (3, 3)
9080 11:06:11.647958 Byte1 TX OE(2T, 0.5T) = (3, 3)
9081 11:06:11.648023
9082 11:06:11.651211
9083 11:06:11.657865 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a05, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
9084 11:06:11.661586 CH1 RK1: MR19=303, MR18=1A05
9085 11:06:11.667862 CH1_RK1: MR19=0x303, MR18=0x1A05, DQSOSC=396, MR23=63, INC=23, DEC=15
9086 11:06:11.671113 [RxdqsGatingPostProcess] freq 1600
9087 11:06:11.674677 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9088 11:06:11.677764 best DQS0 dly(2T, 0.5T) = (1, 1)
9089 11:06:11.681101 best DQS1 dly(2T, 0.5T) = (1, 1)
9090 11:06:11.684686 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9091 11:06:11.687999 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9092 11:06:11.691394 best DQS0 dly(2T, 0.5T) = (1, 1)
9093 11:06:11.694568 best DQS1 dly(2T, 0.5T) = (1, 1)
9094 11:06:11.698258 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9095 11:06:11.701112 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9096 11:06:11.701181 Pre-setting of DQS Precalculation
9097 11:06:11.708001 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9098 11:06:11.714885 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9099 11:06:11.721231 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9100 11:06:11.721307
9101 11:06:11.721371
9102 11:06:11.724790 [Calibration Summary] 3200 Mbps
9103 11:06:11.728102 CH 0, Rank 0
9104 11:06:11.728172 SW Impedance : PASS
9105 11:06:11.731415 DUTY Scan : NO K
9106 11:06:11.734783 ZQ Calibration : PASS
9107 11:06:11.734851 Jitter Meter : NO K
9108 11:06:11.738050 CBT Training : PASS
9109 11:06:11.738138 Write leveling : PASS
9110 11:06:11.741573 RX DQS gating : PASS
9111 11:06:11.744410 RX DQ/DQS(RDDQC) : PASS
9112 11:06:11.744495 TX DQ/DQS : PASS
9113 11:06:11.747788 RX DATLAT : PASS
9114 11:06:11.751304 RX DQ/DQS(Engine): PASS
9115 11:06:11.751403 TX OE : PASS
9116 11:06:11.754536 All Pass.
9117 11:06:11.754646
9118 11:06:11.754748 CH 0, Rank 1
9119 11:06:11.758029 SW Impedance : PASS
9120 11:06:11.758138 DUTY Scan : NO K
9121 11:06:11.761018 ZQ Calibration : PASS
9122 11:06:11.764363 Jitter Meter : NO K
9123 11:06:11.764470 CBT Training : PASS
9124 11:06:11.767633 Write leveling : PASS
9125 11:06:11.771263 RX DQS gating : PASS
9126 11:06:11.771362 RX DQ/DQS(RDDQC) : PASS
9127 11:06:11.774552 TX DQ/DQS : PASS
9128 11:06:11.777734 RX DATLAT : PASS
9129 11:06:11.777832 RX DQ/DQS(Engine): PASS
9130 11:06:11.780932 TX OE : PASS
9131 11:06:11.781028 All Pass.
9132 11:06:11.781094
9133 11:06:11.784186 CH 1, Rank 0
9134 11:06:11.784285 SW Impedance : PASS
9135 11:06:11.787895 DUTY Scan : NO K
9136 11:06:11.791089 ZQ Calibration : PASS
9137 11:06:11.791186 Jitter Meter : NO K
9138 11:06:11.794529 CBT Training : PASS
9139 11:06:11.794598 Write leveling : PASS
9140 11:06:11.797887 RX DQS gating : PASS
9141 11:06:11.801637 RX DQ/DQS(RDDQC) : PASS
9142 11:06:11.801712 TX DQ/DQS : PASS
9143 11:06:11.804205 RX DATLAT : PASS
9144 11:06:11.807566 RX DQ/DQS(Engine): PASS
9145 11:06:11.807660 TX OE : PASS
9146 11:06:11.810949 All Pass.
9147 11:06:11.811018
9148 11:06:11.811079 CH 1, Rank 1
9149 11:06:11.814185 SW Impedance : PASS
9150 11:06:11.814252 DUTY Scan : NO K
9151 11:06:11.817400 ZQ Calibration : PASS
9152 11:06:11.820651 Jitter Meter : NO K
9153 11:06:11.820720 CBT Training : PASS
9154 11:06:11.823903 Write leveling : PASS
9155 11:06:11.827053 RX DQS gating : PASS
9156 11:06:11.827128 RX DQ/DQS(RDDQC) : PASS
9157 11:06:11.830276 TX DQ/DQS : PASS
9158 11:06:11.833682 RX DATLAT : PASS
9159 11:06:11.833776 RX DQ/DQS(Engine): PASS
9160 11:06:11.837009 TX OE : PASS
9161 11:06:11.837103 All Pass.
9162 11:06:11.837190
9163 11:06:11.840617 DramC Write-DBI on
9164 11:06:11.843722 PER_BANK_REFRESH: Hybrid Mode
9165 11:06:11.843810 TX_TRACKING: ON
9166 11:06:11.854225 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9167 11:06:11.860470 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9168 11:06:11.867293 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9169 11:06:11.870584 [FAST_K] Save calibration result to emmc
9170 11:06:11.873655 sync common calibartion params.
9171 11:06:11.876855 sync cbt_mode0:1, 1:1
9172 11:06:11.880677 dram_init: ddr_geometry: 2
9173 11:06:11.880760 dram_init: ddr_geometry: 2
9174 11:06:11.883902 dram_init: ddr_geometry: 2
9175 11:06:11.886991 0:dram_rank_size:100000000
9176 11:06:11.890163 1:dram_rank_size:100000000
9177 11:06:11.893483 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9178 11:06:11.897049 DFS_SHUFFLE_HW_MODE: ON
9179 11:06:11.900074 dramc_set_vcore_voltage set vcore to 725000
9180 11:06:11.903705 Read voltage for 1600, 0
9181 11:06:11.903789 Vio18 = 0
9182 11:06:11.903855 Vcore = 725000
9183 11:06:11.906974 Vdram = 0
9184 11:06:11.907057 Vddq = 0
9185 11:06:11.907122 Vmddr = 0
9186 11:06:11.910025 switch to 3200 Mbps bootup
9187 11:06:11.913472 [DramcRunTimeConfig]
9188 11:06:11.913555 PHYPLL
9189 11:06:11.913620 DPM_CONTROL_AFTERK: ON
9190 11:06:11.916852 PER_BANK_REFRESH: ON
9191 11:06:11.920072 REFRESH_OVERHEAD_REDUCTION: ON
9192 11:06:11.920156 CMD_PICG_NEW_MODE: OFF
9193 11:06:11.923687 XRTWTW_NEW_MODE: ON
9194 11:06:11.923770 XRTRTR_NEW_MODE: ON
9195 11:06:11.927093 TX_TRACKING: ON
9196 11:06:11.927177 RDSEL_TRACKING: OFF
9197 11:06:11.930196 DQS Precalculation for DVFS: ON
9198 11:06:11.933320 RX_TRACKING: OFF
9199 11:06:11.933402 HW_GATING DBG: ON
9200 11:06:11.936685 ZQCS_ENABLE_LP4: ON
9201 11:06:11.936767 RX_PICG_NEW_MODE: ON
9202 11:06:11.940053 TX_PICG_NEW_MODE: ON
9203 11:06:11.943288 ENABLE_RX_DCM_DPHY: ON
9204 11:06:11.943398 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9205 11:06:11.946555 DUMMY_READ_FOR_TRACKING: OFF
9206 11:06:11.950274 !!! SPM_CONTROL_AFTERK: OFF
9207 11:06:11.953599 !!! SPM could not control APHY
9208 11:06:11.953676 IMPEDANCE_TRACKING: ON
9209 11:06:11.956895 TEMP_SENSOR: ON
9210 11:06:11.956978 HW_SAVE_FOR_SR: OFF
9211 11:06:11.960119 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9212 11:06:11.963441 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9213 11:06:11.966766 Read ODT Tracking: ON
9214 11:06:11.970032 Refresh Rate DeBounce: ON
9215 11:06:11.970114 DFS_NO_QUEUE_FLUSH: ON
9216 11:06:11.973788 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9217 11:06:11.976977 ENABLE_DFS_RUNTIME_MRW: OFF
9218 11:06:11.980321 DDR_RESERVE_NEW_MODE: ON
9219 11:06:11.980404 MR_CBT_SWITCH_FREQ: ON
9220 11:06:11.983194 =========================
9221 11:06:12.002427 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9222 11:06:12.005761 dram_init: ddr_geometry: 2
9223 11:06:12.023932 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9224 11:06:12.027508 dram_init: dram init end (result: 0)
9225 11:06:12.034047 DRAM-K: Full calibration passed in 24518 msecs
9226 11:06:12.037349 MRC: failed to locate region type 0.
9227 11:06:12.037431 DRAM rank0 size:0x100000000,
9228 11:06:12.040682 DRAM rank1 size=0x100000000
9229 11:06:12.050656 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9230 11:06:12.057310 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9231 11:06:12.063986 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9232 11:06:12.070544 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9233 11:06:12.074035 DRAM rank0 size:0x100000000,
9234 11:06:12.077392 DRAM rank1 size=0x100000000
9235 11:06:12.077476 CBMEM:
9236 11:06:12.080437 IMD: root @ 0xfffff000 254 entries.
9237 11:06:12.083703 IMD: root @ 0xffffec00 62 entries.
9238 11:06:12.087117 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9239 11:06:12.090508 WARNING: RO_VPD is uninitialized or empty.
9240 11:06:12.097116 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9241 11:06:12.104072 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9242 11:06:12.116813 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9243 11:06:12.128291 BS: romstage times (exec / console): total (unknown) / 24010 ms
9244 11:06:12.128375
9245 11:06:12.128440
9246 11:06:12.138461 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9247 11:06:12.141621 ARM64: Exception handlers installed.
9248 11:06:12.144975 ARM64: Testing exception
9249 11:06:12.148316 ARM64: Done test exception
9250 11:06:12.148399 Enumerating buses...
9251 11:06:12.151716 Show all devs... Before device enumeration.
9252 11:06:12.154978 Root Device: enabled 1
9253 11:06:12.158287 CPU_CLUSTER: 0: enabled 1
9254 11:06:12.158371 CPU: 00: enabled 1
9255 11:06:12.161632 Compare with tree...
9256 11:06:12.161715 Root Device: enabled 1
9257 11:06:12.164655 CPU_CLUSTER: 0: enabled 1
9258 11:06:12.167960 CPU: 00: enabled 1
9259 11:06:12.168043 Root Device scanning...
9260 11:06:12.171240 scan_static_bus for Root Device
9261 11:06:12.174983 CPU_CLUSTER: 0 enabled
9262 11:06:12.178385 scan_static_bus for Root Device done
9263 11:06:12.181421 scan_bus: bus Root Device finished in 8 msecs
9264 11:06:12.181505 done
9265 11:06:12.188296 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9266 11:06:12.191585 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9267 11:06:12.198168 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9268 11:06:12.201367 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9269 11:06:12.204669 Allocating resources...
9270 11:06:12.204752 Reading resources...
9271 11:06:12.211296 Root Device read_resources bus 0 link: 0
9272 11:06:12.211379 DRAM rank0 size:0x100000000,
9273 11:06:12.214812 DRAM rank1 size=0x100000000
9274 11:06:12.217942 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9275 11:06:12.221693 CPU: 00 missing read_resources
9276 11:06:12.224670 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9277 11:06:12.231260 Root Device read_resources bus 0 link: 0 done
9278 11:06:12.231343 Done reading resources.
9279 11:06:12.237912 Show resources in subtree (Root Device)...After reading.
9280 11:06:12.241664 Root Device child on link 0 CPU_CLUSTER: 0
9281 11:06:12.244835 CPU_CLUSTER: 0 child on link 0 CPU: 00
9282 11:06:12.254848 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9283 11:06:12.254932 CPU: 00
9284 11:06:12.258148 Root Device assign_resources, bus 0 link: 0
9285 11:06:12.261398 CPU_CLUSTER: 0 missing set_resources
9286 11:06:12.264775 Root Device assign_resources, bus 0 link: 0 done
9287 11:06:12.267981 Done setting resources.
9288 11:06:12.274737 Show resources in subtree (Root Device)...After assigning values.
9289 11:06:12.278051 Root Device child on link 0 CPU_CLUSTER: 0
9290 11:06:12.281296 CPU_CLUSTER: 0 child on link 0 CPU: 00
9291 11:06:12.290935 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9292 11:06:12.291020 CPU: 00
9293 11:06:12.294508 Done allocating resources.
9294 11:06:12.297896 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9295 11:06:12.301136 Enabling resources...
9296 11:06:12.301219 done.
9297 11:06:12.307889 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9298 11:06:12.307973 Initializing devices...
9299 11:06:12.310996 Root Device init
9300 11:06:12.311079 init hardware done!
9301 11:06:12.314650 0x00000018: ctrlr->caps
9302 11:06:12.317701 52.000 MHz: ctrlr->f_max
9303 11:06:12.317786 0.400 MHz: ctrlr->f_min
9304 11:06:12.320898 0x40ff8080: ctrlr->voltages
9305 11:06:12.320982 sclk: 390625
9306 11:06:12.324534 Bus Width = 1
9307 11:06:12.324617 sclk: 390625
9308 11:06:12.324682 Bus Width = 1
9309 11:06:12.327982 Early init status = 3
9310 11:06:12.334262 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9311 11:06:12.337841 in-header: 03 fc 00 00 01 00 00 00
9312 11:06:12.337924 in-data: 00
9313 11:06:12.344528 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9314 11:06:12.347676 in-header: 03 fd 00 00 00 00 00 00
9315 11:06:12.350959 in-data:
9316 11:06:12.354245 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9317 11:06:12.357808 in-header: 03 fc 00 00 01 00 00 00
9318 11:06:12.361087 in-data: 00
9319 11:06:12.364390 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9320 11:06:12.369041 in-header: 03 fd 00 00 00 00 00 00
9321 11:06:12.372329 in-data:
9322 11:06:12.375627 [SSUSB] Setting up USB HOST controller...
9323 11:06:12.378954 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9324 11:06:12.382309 [SSUSB] phy power-on done.
9325 11:06:12.385712 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9326 11:06:12.392062 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9327 11:06:12.395231 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9328 11:06:12.402014 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9329 11:06:12.408784 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9330 11:06:12.415635 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9331 11:06:12.421948 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9332 11:06:12.428665 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9333 11:06:12.432152 SPM: binary array size = 0x9dc
9334 11:06:12.435447 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9335 11:06:12.441846 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9336 11:06:12.448793 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9337 11:06:12.451879 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9338 11:06:12.458548 configure_display: Starting display init
9339 11:06:12.492266 anx7625_power_on_init: Init interface.
9340 11:06:12.495532 anx7625_disable_pd_protocol: Disabled PD feature.
9341 11:06:12.498912 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9342 11:06:12.526631 anx7625_start_dp_work: Secure OCM version=00
9343 11:06:12.529893 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9344 11:06:12.544627 sp_tx_get_edid_block: EDID Block = 1
9345 11:06:12.647655 Extracted contents:
9346 11:06:12.650892 header: 00 ff ff ff ff ff ff 00
9347 11:06:12.654065 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9348 11:06:12.657125 version: 01 04
9349 11:06:12.660653 basic params: 95 1f 11 78 0a
9350 11:06:12.664145 chroma info: 76 90 94 55 54 90 27 21 50 54
9351 11:06:12.667408 established: 00 00 00
9352 11:06:12.673945 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9353 11:06:12.677011 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9354 11:06:12.684154 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9355 11:06:12.690532 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9356 11:06:12.697073 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9357 11:06:12.700360 extensions: 00
9358 11:06:12.700438 checksum: fb
9359 11:06:12.700501
9360 11:06:12.703846 Manufacturer: IVO Model 57d Serial Number 0
9361 11:06:12.707191 Made week 0 of 2020
9362 11:06:12.707264 EDID version: 1.4
9363 11:06:12.710421 Digital display
9364 11:06:12.713910 6 bits per primary color channel
9365 11:06:12.714043 DisplayPort interface
9366 11:06:12.717249 Maximum image size: 31 cm x 17 cm
9367 11:06:12.720473 Gamma: 220%
9368 11:06:12.720549 Check DPMS levels
9369 11:06:12.723891 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9370 11:06:12.727354 First detailed timing is preferred timing
9371 11:06:12.730348 Established timings supported:
9372 11:06:12.733540 Standard timings supported:
9373 11:06:12.737029 Detailed timings
9374 11:06:12.740424 Hex of detail: 383680a07038204018303c0035ae10000019
9375 11:06:12.743628 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9376 11:06:12.750228 0780 0798 07c8 0820 hborder 0
9377 11:06:12.753676 0438 043b 0447 0458 vborder 0
9378 11:06:12.756833 -hsync -vsync
9379 11:06:12.756913 Did detailed timing
9380 11:06:12.760519 Hex of detail: 000000000000000000000000000000000000
9381 11:06:12.763620 Manufacturer-specified data, tag 0
9382 11:06:12.770283 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9383 11:06:12.770380 ASCII string: InfoVision
9384 11:06:12.777248 Hex of detail: 000000fe00523134304e574635205248200a
9385 11:06:12.780122 ASCII string: R140NWF5 RH
9386 11:06:12.780196 Checksum
9387 11:06:12.780266 Checksum: 0xfb (valid)
9388 11:06:12.787342 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9389 11:06:12.790305 DSI data_rate: 832800000 bps
9390 11:06:12.793888 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9391 11:06:12.796823 anx7625_parse_edid: pixelclock(138800).
9392 11:06:12.803819 hactive(1920), hsync(48), hfp(24), hbp(88)
9393 11:06:12.807070 vactive(1080), vsync(12), vfp(3), vbp(17)
9394 11:06:12.810344 anx7625_dsi_config: config dsi.
9395 11:06:12.817094 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9396 11:06:12.829475 anx7625_dsi_config: success to config DSI
9397 11:06:12.832781 anx7625_dp_start: MIPI phy setup OK.
9398 11:06:12.836015 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9399 11:06:12.839186 mtk_ddp_mode_set invalid vrefresh 60
9400 11:06:12.842616 main_disp_path_setup
9401 11:06:12.842693 ovl_layer_smi_id_en
9402 11:06:12.846029 ovl_layer_smi_id_en
9403 11:06:12.846113 ccorr_config
9404 11:06:12.846177 aal_config
9405 11:06:12.849407 gamma_config
9406 11:06:12.849479 postmask_config
9407 11:06:12.852904 dither_config
9408 11:06:12.855932 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9409 11:06:12.862962 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9410 11:06:12.866140 Root Device init finished in 552 msecs
9411 11:06:12.866213 CPU_CLUSTER: 0 init
9412 11:06:12.875846 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9413 11:06:12.879090 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9414 11:06:12.882413 APU_MBOX 0x190000b0 = 0x10001
9415 11:06:12.885840 APU_MBOX 0x190001b0 = 0x10001
9416 11:06:12.889247 APU_MBOX 0x190005b0 = 0x10001
9417 11:06:12.892617 APU_MBOX 0x190006b0 = 0x10001
9418 11:06:12.895930 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9419 11:06:12.908381 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9420 11:06:12.920630 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9421 11:06:12.927594 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9422 11:06:12.938903 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9423 11:06:12.948352 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9424 11:06:12.951683 CPU_CLUSTER: 0 init finished in 81 msecs
9425 11:06:12.954680 Devices initialized
9426 11:06:12.958360 Show all devs... After init.
9427 11:06:12.958439 Root Device: enabled 1
9428 11:06:12.961447 CPU_CLUSTER: 0: enabled 1
9429 11:06:12.964738 CPU: 00: enabled 1
9430 11:06:12.968234 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9431 11:06:12.971536 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9432 11:06:12.974580 ELOG: NV offset 0x57f000 size 0x1000
9433 11:06:12.981022 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9434 11:06:12.987694 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9435 11:06:12.990992 ELOG: Event(17) added with size 13 at 2024-03-03 11:05:36 UTC
9436 11:06:12.994776 out: cmd=0x121: 03 db 21 01 00 00 00 00
9437 11:06:12.998564 in-header: 03 20 00 00 2c 00 00 00
9438 11:06:13.011580 in-data: 3f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9439 11:06:13.018680 ELOG: Event(A1) added with size 10 at 2024-03-03 11:05:36 UTC
9440 11:06:13.021641 ELOG: Event(16) added with size 11 at 2024-03-03 11:05:36 UTC
9441 11:06:13.103555 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9442 11:06:13.110123 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9443 11:06:13.116951 ELOG: Event(A0) added with size 9 at 2024-03-03 11:05:36 UTC
9444 11:06:13.120113 elog_add_boot_reason: Logged dev mode boot
9445 11:06:13.123434 BS: BS_POST_DEVICE entry times (exec / console): 77 / 74 ms
9446 11:06:13.126707 Finalize devices...
9447 11:06:13.126780 Devices finalized
9448 11:06:13.133196 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9449 11:06:13.136581 Writing coreboot table at 0xffe64000
9450 11:06:13.139960 0. 000000000010a000-0000000000113fff: RAMSTAGE
9451 11:06:13.143155 1. 0000000040000000-00000000400fffff: RAM
9452 11:06:13.150204 2. 0000000040100000-000000004032afff: RAMSTAGE
9453 11:06:13.153579 3. 000000004032b000-00000000545fffff: RAM
9454 11:06:13.156409 4. 0000000054600000-000000005465ffff: BL31
9455 11:06:13.159993 5. 0000000054660000-00000000ffe63fff: RAM
9456 11:06:13.166589 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9457 11:06:13.170155 7. 0000000100000000-000000023fffffff: RAM
9458 11:06:13.173315 Passing 5 GPIOs to payload:
9459 11:06:13.176607 NAME | PORT | POLARITY | VALUE
9460 11:06:13.180012 EC in RW | 0x000000aa | low | undefined
9461 11:06:13.186351 EC interrupt | 0x00000005 | low | undefined
9462 11:06:13.189800 TPM interrupt | 0x000000ab | high | undefined
9463 11:06:13.196466 SD card detect | 0x00000011 | high | undefined
9464 11:06:13.199766 speaker enable | 0x00000093 | high | undefined
9465 11:06:13.202995 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9466 11:06:13.206355 in-header: 03 f9 00 00 02 00 00 00
9467 11:06:13.209597 in-data: 02 00
9468 11:06:13.209680 ADC[4]: Raw value=901032 ID=7
9469 11:06:13.212985 ADC[3]: Raw value=213179 ID=1
9470 11:06:13.216304 RAM Code: 0x71
9471 11:06:13.216413 ADC[6]: Raw value=74870 ID=0
9472 11:06:13.219599 ADC[5]: Raw value=212072 ID=1
9473 11:06:13.223166 SKU Code: 0x1
9474 11:06:13.226726 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d51e
9475 11:06:13.229785 coreboot table: 964 bytes.
9476 11:06:13.233203 IMD ROOT 0. 0xfffff000 0x00001000
9477 11:06:13.236489 IMD SMALL 1. 0xffffe000 0x00001000
9478 11:06:13.239855 RO MCACHE 2. 0xffffc000 0x00001104
9479 11:06:13.243178 CONSOLE 3. 0xfff7c000 0x00080000
9480 11:06:13.246617 FMAP 4. 0xfff7b000 0x00000452
9481 11:06:13.249858 TIME STAMP 5. 0xfff7a000 0x00000910
9482 11:06:13.253070 VBOOT WORK 6. 0xfff66000 0x00014000
9483 11:06:13.256330 RAMOOPS 7. 0xffe66000 0x00100000
9484 11:06:13.259975 COREBOOT 8. 0xffe64000 0x00002000
9485 11:06:13.260058 IMD small region:
9486 11:06:13.263102 IMD ROOT 0. 0xffffec00 0x00000400
9487 11:06:13.266273 VPD 1. 0xffffeb80 0x0000006c
9488 11:06:13.269490 MMC STATUS 2. 0xffffeb60 0x00000004
9489 11:06:13.276471 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9490 11:06:13.279909 Probing TPM: done!
9491 11:06:13.283290 Connected to device vid:did:rid of 1ae0:0028:00
9492 11:06:13.293103 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9493 11:06:13.296565 Initialized TPM device CR50 revision 0
9494 11:06:13.300346 Checking cr50 for pending updates
9495 11:06:13.303965 Reading cr50 TPM mode
9496 11:06:13.312196 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9497 11:06:13.318716 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9498 11:06:13.358911 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9499 11:06:13.362197 Checking segment from ROM address 0x40100000
9500 11:06:13.365482 Checking segment from ROM address 0x4010001c
9501 11:06:13.372177 Loading segment from ROM address 0x40100000
9502 11:06:13.372262 code (compression=0)
9503 11:06:13.382228 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9504 11:06:13.388882 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9505 11:06:13.388970 it's not compressed!
9506 11:06:13.395441 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9507 11:06:13.398726 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9508 11:06:13.419423 Loading segment from ROM address 0x4010001c
9509 11:06:13.419508 Entry Point 0x80000000
9510 11:06:13.422877 Loaded segments
9511 11:06:13.426106 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9512 11:06:13.433124 Jumping to boot code at 0x80000000(0xffe64000)
9513 11:06:13.439742 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9514 11:06:13.446225 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9515 11:06:13.453805 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9516 11:06:13.457117 Checking segment from ROM address 0x40100000
9517 11:06:13.460299 Checking segment from ROM address 0x4010001c
9518 11:06:13.464060 Loading segment from ROM address 0x40100000
9519 11:06:13.467080 code (compression=1)
9520 11:06:13.473907 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9521 11:06:13.484194 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9522 11:06:13.484279 using LZMA
9523 11:06:13.492022 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9524 11:06:13.498594 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9525 11:06:13.501904 Loading segment from ROM address 0x4010001c
9526 11:06:13.502028 Entry Point 0x54601000
9527 11:06:13.505827 Loaded segments
9528 11:06:13.508926 NOTICE: MT8192 bl31_setup
9529 11:06:13.515801 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9530 11:06:13.518901 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9531 11:06:13.522269 WARNING: region 0:
9532 11:06:13.525648 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9533 11:06:13.525732 WARNING: region 1:
9534 11:06:13.532283 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9535 11:06:13.535591 WARNING: region 2:
9536 11:06:13.539432 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9537 11:06:13.542670 WARNING: region 3:
9538 11:06:13.545752 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9539 11:06:13.549127 WARNING: region 4:
9540 11:06:13.552502 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9541 11:06:13.555917 WARNING: region 5:
9542 11:06:13.559173 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 11:06:13.562434 WARNING: region 6:
9544 11:06:13.565798 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9545 11:06:13.565882 WARNING: region 7:
9546 11:06:13.572719 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9547 11:06:13.579421 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9548 11:06:13.582603 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9549 11:06:13.585849 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9550 11:06:13.592869 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9551 11:06:13.596026 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9552 11:06:13.599375 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9553 11:06:13.606073 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9554 11:06:13.609181 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9555 11:06:13.612795 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9556 11:06:13.619454 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9557 11:06:13.622825 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9558 11:06:13.626246 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9559 11:06:13.632536 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9560 11:06:13.635753 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9561 11:06:13.642708 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9562 11:06:13.646008 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9563 11:06:13.649657 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9564 11:06:13.655746 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9565 11:06:13.659500 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9566 11:06:13.662396 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9567 11:06:13.669476 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9568 11:06:13.672400 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9569 11:06:13.679487 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9570 11:06:13.682752 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9571 11:06:13.686076 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9572 11:06:13.692686 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9573 11:06:13.695966 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9574 11:06:13.702741 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9575 11:06:13.705850 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9576 11:06:13.709510 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9577 11:06:13.715830 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9578 11:06:13.719495 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9579 11:06:13.722561 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9580 11:06:13.729485 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9581 11:06:13.732727 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9582 11:06:13.735971 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9583 11:06:13.739157 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9584 11:06:13.746149 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9585 11:06:13.749445 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9586 11:06:13.752706 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9587 11:06:13.755960 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9588 11:06:13.762636 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9589 11:06:13.766046 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9590 11:06:13.769790 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9591 11:06:13.773024 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9592 11:06:13.779746 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9593 11:06:13.783050 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9594 11:06:13.786440 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9595 11:06:13.792963 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9596 11:06:13.796107 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9597 11:06:13.799473 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9598 11:06:13.806180 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9599 11:06:13.809399 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9600 11:06:13.816400 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9601 11:06:13.819646 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9602 11:06:13.826233 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9603 11:06:13.829782 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9604 11:06:13.833206 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9605 11:06:13.839663 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9606 11:06:13.843189 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9607 11:06:13.849553 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9608 11:06:13.852799 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9609 11:06:13.859741 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9610 11:06:13.863017 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9611 11:06:13.866340 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9612 11:06:13.873120 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9613 11:06:13.876486 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9614 11:06:13.883168 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9615 11:06:13.886486 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9616 11:06:13.893142 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9617 11:06:13.896312 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9618 11:06:13.899752 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9619 11:06:13.906415 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9620 11:06:13.909653 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9621 11:06:13.916150 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9622 11:06:13.919952 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9623 11:06:13.926575 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9624 11:06:13.929720 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9625 11:06:13.933236 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9626 11:06:13.939954 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9627 11:06:13.943679 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9628 11:06:13.949899 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9629 11:06:13.953539 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9630 11:06:13.959992 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9631 11:06:13.963091 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9632 11:06:13.966377 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9633 11:06:13.973090 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9634 11:06:13.976815 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9635 11:06:13.983452 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9636 11:06:13.986756 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9637 11:06:13.990068 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9638 11:06:13.996662 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9639 11:06:14.000269 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9640 11:06:14.006973 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9641 11:06:14.009975 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9642 11:06:14.016745 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9643 11:06:14.020182 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9644 11:06:14.023582 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9645 11:06:14.027014 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9646 11:06:14.033614 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9647 11:06:14.037025 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9648 11:06:14.040496 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9649 11:06:14.046926 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9650 11:06:14.050292 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9651 11:06:14.056639 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9652 11:06:14.060201 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9653 11:06:14.063260 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9654 11:06:14.070013 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9655 11:06:14.073299 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9656 11:06:14.079927 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9657 11:06:14.083251 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9658 11:06:14.086902 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9659 11:06:14.093176 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9660 11:06:14.096585 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9661 11:06:14.103550 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9662 11:06:14.106804 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9663 11:06:14.110135 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9664 11:06:14.113550 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9665 11:06:14.120061 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9666 11:06:14.123533 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9667 11:06:14.126804 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9668 11:06:14.130071 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9669 11:06:14.136916 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9670 11:06:14.140167 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9671 11:06:14.143828 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9672 11:06:14.150182 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9673 11:06:14.153625 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9674 11:06:14.156778 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9675 11:06:14.164004 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9676 11:06:14.166672 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9677 11:06:14.173643 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9678 11:06:14.176933 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9679 11:06:14.180101 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9680 11:06:14.186901 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9681 11:06:14.190102 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9682 11:06:14.197064 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9683 11:06:14.200490 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9684 11:06:14.203783 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9685 11:06:14.210488 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9686 11:06:14.213447 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9687 11:06:14.217208 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9688 11:06:14.223635 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9689 11:06:14.226968 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9690 11:06:14.233613 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9691 11:06:14.236994 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9692 11:06:14.240461 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9693 11:06:14.247027 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9694 11:06:14.250471 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9695 11:06:14.253883 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9696 11:06:14.260317 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9697 11:06:14.263631 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9698 11:06:14.270454 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9699 11:06:14.273569 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9700 11:06:14.277191 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9701 11:06:14.283623 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9702 11:06:14.286936 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9703 11:06:14.293796 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9704 11:06:14.297195 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9705 11:06:14.300489 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9706 11:06:14.307061 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9707 11:06:14.310453 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9708 11:06:14.317202 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9709 11:06:14.320089 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9710 11:06:14.323430 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9711 11:06:14.329865 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9712 11:06:14.333178 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9713 11:06:14.340253 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9714 11:06:14.343472 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9715 11:06:14.346806 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9716 11:06:14.353354 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9717 11:06:14.356603 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9718 11:06:14.363198 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9719 11:06:14.366693 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9720 11:06:14.370184 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9721 11:06:14.376401 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9722 11:06:14.379682 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9723 11:06:14.383396 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9724 11:06:14.389871 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9725 11:06:14.393183 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9726 11:06:14.399862 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9727 11:06:14.403009 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9728 11:06:14.406452 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9729 11:06:14.413107 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9730 11:06:14.416177 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9731 11:06:14.422943 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9732 11:06:14.426205 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9733 11:06:14.429722 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9734 11:06:14.436508 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9735 11:06:14.439362 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9736 11:06:14.446109 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9737 11:06:14.449292 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9738 11:06:14.452755 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9739 11:06:14.459372 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9740 11:06:14.462770 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9741 11:06:14.469717 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9742 11:06:14.472750 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9743 11:06:14.479523 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9744 11:06:14.482731 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9745 11:06:14.486034 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9746 11:06:14.492592 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9747 11:06:14.496034 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9748 11:06:14.502672 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9749 11:06:14.506085 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9750 11:06:14.509610 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9751 11:06:14.516179 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9752 11:06:14.519401 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9753 11:06:14.526232 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9754 11:06:14.529444 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9755 11:06:14.532673 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9756 11:06:14.539102 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9757 11:06:14.542548 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9758 11:06:14.549158 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9759 11:06:14.552436 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9760 11:06:14.559006 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9761 11:06:14.562428 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9762 11:06:14.565642 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9763 11:06:14.572573 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9764 11:06:14.575681 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9765 11:06:14.582438 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9766 11:06:14.585644 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9767 11:06:14.592286 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9768 11:06:14.595788 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9769 11:06:14.598941 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9770 11:06:14.605568 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9771 11:06:14.608940 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9772 11:06:14.615528 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9773 11:06:14.618871 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9774 11:06:14.622204 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9775 11:06:14.628895 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9776 11:06:14.632077 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9777 11:06:14.635489 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9778 11:06:14.638770 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9779 11:06:14.645560 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9780 11:06:14.648651 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9781 11:06:14.652044 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9782 11:06:14.658565 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9783 11:06:14.661872 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9784 11:06:14.668462 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9785 11:06:14.671764 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9786 11:06:14.675208 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9787 11:06:14.682137 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9788 11:06:14.685446 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9789 11:06:14.688568 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9790 11:06:14.695574 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9791 11:06:14.698705 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9792 11:06:14.701811 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9793 11:06:14.708347 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9794 11:06:14.711683 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9795 11:06:14.714998 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9796 11:06:14.721677 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9797 11:06:14.725015 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9798 11:06:14.731912 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9799 11:06:14.735133 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9800 11:06:14.738313 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9801 11:06:14.744789 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9802 11:06:14.748485 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9803 11:06:14.751707 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9804 11:06:14.758427 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9805 11:06:14.761590 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9806 11:06:14.764971 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9807 11:06:14.771663 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9808 11:06:14.774938 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9809 11:06:14.781641 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9810 11:06:14.784945 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9811 11:06:14.787966 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9812 11:06:14.794821 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9813 11:06:14.798146 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9814 11:06:14.801557 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9815 11:06:14.807837 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9816 11:06:14.811331 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9817 11:06:14.814815 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9818 11:06:14.818159 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9819 11:06:14.824546 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9820 11:06:14.828259 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9821 11:06:14.831551 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9822 11:06:14.834776 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9823 11:06:14.841567 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9824 11:06:14.844856 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9825 11:06:14.848061 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9826 11:06:14.851112 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9827 11:06:14.857754 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9828 11:06:14.861095 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9829 11:06:14.864581 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9830 11:06:14.871034 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9831 11:06:14.874408 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9832 11:06:14.881382 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9833 11:06:14.884631 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9834 11:06:14.888272 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9835 11:06:14.894674 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9836 11:06:14.897798 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9837 11:06:14.904792 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9838 11:06:14.908024 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9839 11:06:14.911206 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9840 11:06:14.917578 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9841 11:06:14.920861 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9842 11:06:14.927951 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9843 11:06:14.931183 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9844 11:06:14.934671 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9845 11:06:14.940918 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9846 11:06:14.944777 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9847 11:06:14.951164 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9848 11:06:14.954736 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9849 11:06:14.957711 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9850 11:06:14.964339 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9851 11:06:14.967706 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9852 11:06:14.974182 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9853 11:06:14.977557 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9854 11:06:14.980929 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9855 11:06:14.988005 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9856 11:06:14.990895 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9857 11:06:14.997665 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9858 11:06:15.001110 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9859 11:06:15.007737 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9860 11:06:15.010825 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9861 11:06:15.014191 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9862 11:06:15.020753 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9863 11:06:15.024219 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9864 11:06:15.031206 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9865 11:06:15.034461 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9866 11:06:15.037781 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9867 11:06:15.044028 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9868 11:06:15.047273 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9869 11:06:15.054275 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9870 11:06:15.057393 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9871 11:06:15.060741 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9872 11:06:15.067511 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9873 11:06:15.070604 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9874 11:06:15.077289 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9875 11:06:15.080584 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9876 11:06:15.083885 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9877 11:06:15.090520 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9878 11:06:15.094283 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9879 11:06:15.100568 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9880 11:06:15.104129 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9881 11:06:15.107169 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9882 11:06:15.113985 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9883 11:06:15.117440 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9884 11:06:15.124186 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9885 11:06:15.127168 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9886 11:06:15.130639 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9887 11:06:15.137536 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9888 11:06:15.140769 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9889 11:06:15.147155 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9890 11:06:15.150567 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9891 11:06:15.157282 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9892 11:06:15.160596 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9893 11:06:15.164088 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9894 11:06:15.170866 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9895 11:06:15.174123 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9896 11:06:15.180846 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9897 11:06:15.184035 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9898 11:06:15.187234 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9899 11:06:15.193855 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9900 11:06:15.197055 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9901 11:06:15.203711 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9902 11:06:15.207214 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9903 11:06:15.210802 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9904 11:06:15.217210 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9905 11:06:15.220323 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9906 11:06:15.227275 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9907 11:06:15.230728 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9908 11:06:15.237093 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9909 11:06:15.240423 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9910 11:06:15.243637 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9911 11:06:15.250586 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9912 11:06:15.253780 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9913 11:06:15.260529 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9914 11:06:15.263710 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9915 11:06:15.270523 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9916 11:06:15.273845 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9917 11:06:15.277066 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9918 11:06:15.283889 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9919 11:06:15.287106 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9920 11:06:15.293730 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9921 11:06:15.297044 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9922 11:06:15.303965 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9923 11:06:15.307265 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9924 11:06:15.310391 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9925 11:06:15.316963 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9926 11:06:15.320322 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9927 11:06:15.327068 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9928 11:06:15.330689 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9929 11:06:15.337070 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9930 11:06:15.340371 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9931 11:06:15.347080 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9932 11:06:15.350420 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9933 11:06:15.353826 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9934 11:06:15.360340 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9935 11:06:15.363675 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9936 11:06:15.370207 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9937 11:06:15.373731 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9938 11:06:15.380415 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9939 11:06:15.383538 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9940 11:06:15.386867 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9941 11:06:15.393529 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9942 11:06:15.396871 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9943 11:06:15.403414 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9944 11:06:15.406853 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9945 11:06:15.413597 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9946 11:06:15.416774 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9947 11:06:15.420521 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9948 11:06:15.426743 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9949 11:06:15.430374 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9950 11:06:15.433716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9951 11:06:15.440358 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9952 11:06:15.443665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9953 11:06:15.450085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9954 11:06:15.453397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9955 11:06:15.459945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9956 11:06:15.463326 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9957 11:06:15.469932 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9958 11:06:15.473249 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9959 11:06:15.479830 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9960 11:06:15.483160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9961 11:06:15.489804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9962 11:06:15.493132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9963 11:06:15.499556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9964 11:06:15.503372 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9965 11:06:15.509975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9966 11:06:15.512908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9967 11:06:15.519921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9968 11:06:15.522889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9969 11:06:15.529764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9970 11:06:15.532811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9971 11:06:15.539519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9972 11:06:15.542984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9973 11:06:15.549555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9974 11:06:15.552504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9975 11:06:15.559599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9976 11:06:15.562607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9977 11:06:15.569308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9978 11:06:15.572710 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9979 11:06:15.579046 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9980 11:06:15.582384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9981 11:06:15.586120 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9982 11:06:15.588934 INFO: [APUAPC] vio 0
9983 11:06:15.595941 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9984 11:06:15.599314 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9985 11:06:15.602581 INFO: [APUAPC] D0_APC_0: 0x400510
9986 11:06:15.605950 INFO: [APUAPC] D0_APC_1: 0x0
9987 11:06:15.609146 INFO: [APUAPC] D0_APC_2: 0x1540
9988 11:06:15.612419 INFO: [APUAPC] D0_APC_3: 0x0
9989 11:06:15.615766 INFO: [APUAPC] D1_APC_0: 0xffffffff
9990 11:06:15.619110 INFO: [APUAPC] D1_APC_1: 0xffffffff
9991 11:06:15.622446 INFO: [APUAPC] D1_APC_2: 0x3fffff
9992 11:06:15.625900 INFO: [APUAPC] D1_APC_3: 0x0
9993 11:06:15.629026 INFO: [APUAPC] D2_APC_0: 0xffffffff
9994 11:06:15.632353 INFO: [APUAPC] D2_APC_1: 0xffffffff
9995 11:06:15.635894 INFO: [APUAPC] D2_APC_2: 0x3fffff
9996 11:06:15.638887 INFO: [APUAPC] D2_APC_3: 0x0
9997 11:06:15.642521 INFO: [APUAPC] D3_APC_0: 0xffffffff
9998 11:06:15.645655 INFO: [APUAPC] D3_APC_1: 0xffffffff
9999 11:06:15.649060 INFO: [APUAPC] D3_APC_2: 0x3fffff
10000 11:06:15.649145 INFO: [APUAPC] D3_APC_3: 0x0
10001 11:06:15.655330 INFO: [APUAPC] D4_APC_0: 0xffffffff
10002 11:06:15.658794 INFO: [APUAPC] D4_APC_1: 0xffffffff
10003 11:06:15.662146 INFO: [APUAPC] D4_APC_2: 0x3fffff
10004 11:06:15.662230 INFO: [APUAPC] D4_APC_3: 0x0
10005 11:06:15.665635 INFO: [APUAPC] D5_APC_0: 0xffffffff
10006 11:06:15.668779 INFO: [APUAPC] D5_APC_1: 0xffffffff
10007 11:06:15.672161 INFO: [APUAPC] D5_APC_2: 0x3fffff
10008 11:06:15.675468 INFO: [APUAPC] D5_APC_3: 0x0
10009 11:06:15.678794 INFO: [APUAPC] D6_APC_0: 0xffffffff
10010 11:06:15.682032 INFO: [APUAPC] D6_APC_1: 0xffffffff
10011 11:06:15.685340 INFO: [APUAPC] D6_APC_2: 0x3fffff
10012 11:06:15.688668 INFO: [APUAPC] D6_APC_3: 0x0
10013 11:06:15.691972 INFO: [APUAPC] D7_APC_0: 0xffffffff
10014 11:06:15.695542 INFO: [APUAPC] D7_APC_1: 0xffffffff
10015 11:06:15.698906 INFO: [APUAPC] D7_APC_2: 0x3fffff
10016 11:06:15.702003 INFO: [APUAPC] D7_APC_3: 0x0
10017 11:06:15.705391 INFO: [APUAPC] D8_APC_0: 0xffffffff
10018 11:06:15.708822 INFO: [APUAPC] D8_APC_1: 0xffffffff
10019 11:06:15.712016 INFO: [APUAPC] D8_APC_2: 0x3fffff
10020 11:06:15.715434 INFO: [APUAPC] D8_APC_3: 0x0
10021 11:06:15.718788 INFO: [APUAPC] D9_APC_0: 0xffffffff
10022 11:06:15.722103 INFO: [APUAPC] D9_APC_1: 0xffffffff
10023 11:06:15.725340 INFO: [APUAPC] D9_APC_2: 0x3fffff
10024 11:06:15.728733 INFO: [APUAPC] D9_APC_3: 0x0
10025 11:06:15.731920 INFO: [APUAPC] D10_APC_0: 0xffffffff
10026 11:06:15.735215 INFO: [APUAPC] D10_APC_1: 0xffffffff
10027 11:06:15.738663 INFO: [APUAPC] D10_APC_2: 0x3fffff
10028 11:06:15.741885 INFO: [APUAPC] D10_APC_3: 0x0
10029 11:06:15.745206 INFO: [APUAPC] D11_APC_0: 0xffffffff
10030 11:06:15.749071 INFO: [APUAPC] D11_APC_1: 0xffffffff
10031 11:06:15.751720 INFO: [APUAPC] D11_APC_2: 0x3fffff
10032 11:06:15.755279 INFO: [APUAPC] D11_APC_3: 0x0
10033 11:06:15.758764 INFO: [APUAPC] D12_APC_0: 0xffffffff
10034 11:06:15.761875 INFO: [APUAPC] D12_APC_1: 0xffffffff
10035 11:06:15.765270 INFO: [APUAPC] D12_APC_2: 0x3fffff
10036 11:06:15.768405 INFO: [APUAPC] D12_APC_3: 0x0
10037 11:06:15.771675 INFO: [APUAPC] D13_APC_0: 0xffffffff
10038 11:06:15.775066 INFO: [APUAPC] D13_APC_1: 0xffffffff
10039 11:06:15.778666 INFO: [APUAPC] D13_APC_2: 0x3fffff
10040 11:06:15.781824 INFO: [APUAPC] D13_APC_3: 0x0
10041 11:06:15.785077 INFO: [APUAPC] D14_APC_0: 0xffffffff
10042 11:06:15.788646 INFO: [APUAPC] D14_APC_1: 0xffffffff
10043 11:06:15.791860 INFO: [APUAPC] D14_APC_2: 0x3fffff
10044 11:06:15.795212 INFO: [APUAPC] D14_APC_3: 0x0
10045 11:06:15.798552 INFO: [APUAPC] D15_APC_0: 0xffffffff
10046 11:06:15.801909 INFO: [APUAPC] D15_APC_1: 0xffffffff
10047 11:06:15.805293 INFO: [APUAPC] D15_APC_2: 0x3fffff
10048 11:06:15.808429 INFO: [APUAPC] D15_APC_3: 0x0
10049 11:06:15.811794 INFO: [APUAPC] APC_CON: 0x4
10050 11:06:15.815101 INFO: [NOCDAPC] D0_APC_0: 0x0
10051 11:06:15.818386 INFO: [NOCDAPC] D0_APC_1: 0x0
10052 11:06:15.821737 INFO: [NOCDAPC] D1_APC_0: 0x0
10053 11:06:15.821820 INFO: [NOCDAPC] D1_APC_1: 0xfff
10054 11:06:15.825104 INFO: [NOCDAPC] D2_APC_0: 0x0
10055 11:06:15.828446 INFO: [NOCDAPC] D2_APC_1: 0xfff
10056 11:06:15.831842 INFO: [NOCDAPC] D3_APC_0: 0x0
10057 11:06:15.835408 INFO: [NOCDAPC] D3_APC_1: 0xfff
10058 11:06:15.838636 INFO: [NOCDAPC] D4_APC_0: 0x0
10059 11:06:15.841678 INFO: [NOCDAPC] D4_APC_1: 0xfff
10060 11:06:15.844946 INFO: [NOCDAPC] D5_APC_0: 0x0
10061 11:06:15.848674 INFO: [NOCDAPC] D5_APC_1: 0xfff
10062 11:06:15.851539 INFO: [NOCDAPC] D6_APC_0: 0x0
10063 11:06:15.855217 INFO: [NOCDAPC] D6_APC_1: 0xfff
10064 11:06:15.855302 INFO: [NOCDAPC] D7_APC_0: 0x0
10065 11:06:15.858884 INFO: [NOCDAPC] D7_APC_1: 0xfff
10066 11:06:15.862158 INFO: [NOCDAPC] D8_APC_0: 0x0
10067 11:06:15.865152 INFO: [NOCDAPC] D8_APC_1: 0xfff
10068 11:06:15.868273 INFO: [NOCDAPC] D9_APC_0: 0x0
10069 11:06:15.871717 INFO: [NOCDAPC] D9_APC_1: 0xfff
10070 11:06:15.875238 INFO: [NOCDAPC] D10_APC_0: 0x0
10071 11:06:15.878789 INFO: [NOCDAPC] D10_APC_1: 0xfff
10072 11:06:15.881679 INFO: [NOCDAPC] D11_APC_0: 0x0
10073 11:06:15.885141 INFO: [NOCDAPC] D11_APC_1: 0xfff
10074 11:06:15.888379 INFO: [NOCDAPC] D12_APC_0: 0x0
10075 11:06:15.891555 INFO: [NOCDAPC] D12_APC_1: 0xfff
10076 11:06:15.891640 INFO: [NOCDAPC] D13_APC_0: 0x0
10077 11:06:15.894814 INFO: [NOCDAPC] D13_APC_1: 0xfff
10078 11:06:15.898037 INFO: [NOCDAPC] D14_APC_0: 0x0
10079 11:06:15.901834 INFO: [NOCDAPC] D14_APC_1: 0xfff
10080 11:06:15.905133 INFO: [NOCDAPC] D15_APC_0: 0x0
10081 11:06:15.908379 INFO: [NOCDAPC] D15_APC_1: 0xfff
10082 11:06:15.911662 INFO: [NOCDAPC] APC_CON: 0x4
10083 11:06:15.915024 INFO: [APUAPC] set_apusys_apc done
10084 11:06:15.918315 INFO: [DEVAPC] devapc_init done
10085 11:06:15.921436 INFO: GICv3 without legacy support detected.
10086 11:06:15.924850 INFO: ARM GICv3 driver initialized in EL3
10087 11:06:15.931626 INFO: Maximum SPI INTID supported: 639
10088 11:06:15.934909 INFO: BL31: Initializing runtime services
10089 11:06:15.941690 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10090 11:06:15.941774 INFO: SPM: enable CPC mode
10091 11:06:15.948058 INFO: mcdi ready for mcusys-off-idle and system suspend
10092 11:06:15.951259 INFO: BL31: Preparing for EL3 exit to normal world
10093 11:06:15.954840 INFO: Entry point address = 0x80000000
10094 11:06:15.957879 INFO: SPSR = 0x8
10095 11:06:15.963690
10096 11:06:15.963774
10097 11:06:15.963841
10098 11:06:15.967194 Starting depthcharge on Spherion...
10099 11:06:15.967278
10100 11:06:15.967345 Wipe memory regions:
10101 11:06:15.967408
10102 11:06:15.968061 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10103 11:06:15.968169 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10104 11:06:15.968256 Setting prompt string to ['asurada:']
10105 11:06:15.968340 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10106 11:06:15.970469 [0x00000040000000, 0x00000054600000)
10107 11:06:16.092849
10108 11:06:16.092952 [0x00000054660000, 0x00000080000000)
10109 11:06:16.353092
10110 11:06:16.353254 [0x000000821a7280, 0x000000ffe64000)
10111 11:06:17.097936
10112 11:06:17.098082 [0x00000100000000, 0x00000240000000)
10113 11:06:18.988694
10114 11:06:18.991528 Initializing XHCI USB controller at 0x11200000.
10115 11:06:20.030111
10116 11:06:20.033213 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10117 11:06:20.033526
10118 11:06:20.033773
10119 11:06:20.034029
10120 11:06:20.034627 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10122 11:06:20.135764 asurada: tftpboot 192.168.201.1 12925642/tftp-deploy-c06bihlb/kernel/image.itb 12925642/tftp-deploy-c06bihlb/kernel/cmdline
10123 11:06:20.136565 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10124 11:06:20.137018 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10125 11:06:20.141394 tftpboot 192.168.201.1 12925642/tftp-deploy-c06bihlb/kernel/image.itbtp-deploy-c06bihlb/kernel/cmdline
10126 11:06:20.141888
10127 11:06:20.142316 Waiting for link
10128 11:06:20.302143
10129 11:06:20.302721 R8152: Initializing
10130 11:06:20.303104
10131 11:06:20.305473 Version 9 (ocp_data = 6010)
10132 11:06:20.306098
10133 11:06:20.308786 R8152: Done initializing
10134 11:06:20.309371
10135 11:06:20.309749 Adding net device
10136 11:06:22.440425
10137 11:06:22.441009 done.
10138 11:06:22.441384
10139 11:06:22.441727 MAC: 00:e0:4c:72:2d:d6
10140 11:06:22.442113
10141 11:06:22.443480 Sending DHCP discover... done.
10142 11:06:22.443959
10143 11:06:22.446989 Waiting for reply... done.
10144 11:06:22.447466
10145 11:06:22.450068 Sending DHCP request... done.
10146 11:06:22.450547
10147 11:06:22.454572 Waiting for reply... done.
10148 11:06:22.455049
10149 11:06:22.455423 My ip is 192.168.201.21
10150 11:06:22.455770
10151 11:06:22.457787 The DHCP server ip is 192.168.201.1
10152 11:06:22.458298
10153 11:06:22.464432 TFTP server IP predefined by user: 192.168.201.1
10154 11:06:22.464919
10155 11:06:22.471210 Bootfile predefined by user: 12925642/tftp-deploy-c06bihlb/kernel/image.itb
10156 11:06:22.471694
10157 11:06:22.474581 Sending tftp read request... done.
10158 11:06:22.475059
10159 11:06:22.478966 Waiting for the transfer...
10160 11:06:22.479445
10161 11:06:22.788764 00000000 ################################################################
10162 11:06:22.788900
10163 11:06:23.078094 00080000 ################################################################
10164 11:06:23.078258
10165 11:06:23.369058 00100000 ################################################################
10166 11:06:23.369194
10167 11:06:23.627734 00180000 ################################################################
10168 11:06:23.627876
10169 11:06:23.900757 00200000 ################################################################
10170 11:06:23.900892
10171 11:06:24.170541 00280000 ################################################################
10172 11:06:24.170675
10173 11:06:24.461523 00300000 ################################################################
10174 11:06:24.461658
10175 11:06:24.723689 00380000 ################################################################
10176 11:06:24.723818
10177 11:06:25.011829 00400000 ################################################################
10178 11:06:25.011967
10179 11:06:25.334423 00480000 ################################################################
10180 11:06:25.334997
10181 11:06:25.676811 00500000 ################################################################
10182 11:06:25.677387
10183 11:06:26.026029 00580000 ################################################################
10184 11:06:26.026171
10185 11:06:26.294410 00600000 ################################################################
10186 11:06:26.294562
10187 11:06:26.589321 00680000 ################################################################
10188 11:06:26.589457
10189 11:06:26.890988 00700000 ################################################################
10190 11:06:26.891123
10191 11:06:27.171026 00780000 ################################################################
10192 11:06:27.171166
10193 11:06:27.467024 00800000 ################################################################
10194 11:06:27.467160
10195 11:06:27.756497 00880000 ################################################################
10196 11:06:27.756668
10197 11:06:28.018070 00900000 ################################################################
10198 11:06:28.018215
10199 11:06:28.307980 00980000 ################################################################
10200 11:06:28.308129
10201 11:06:28.579452 00a00000 ################################################################
10202 11:06:28.579589
10203 11:06:28.836987 00a80000 ################################################################
10204 11:06:28.837117
10205 11:06:29.122055 00b00000 ################################################################
10206 11:06:29.122204
10207 11:06:29.397636 00b80000 ################################################################
10208 11:06:29.397802
10209 11:06:29.657766 00c00000 ################################################################
10210 11:06:29.657921
10211 11:06:29.918465 00c80000 ################################################################
10212 11:06:29.918600
10213 11:06:30.281324 00d00000 ################################################################
10214 11:06:30.281502
10215 11:06:30.642547 00d80000 ################################################################
10216 11:06:30.642704
10217 11:06:30.988019 00e00000 ################################################################
10218 11:06:30.988172
10219 11:06:31.316475 00e80000 ################################################################
10220 11:06:31.316616
10221 11:06:31.574623 00f00000 ################################################################
10222 11:06:31.574754
10223 11:06:31.862903 00f80000 ################################################################
10224 11:06:31.863042
10225 11:06:32.150426 01000000 ################################################################
10226 11:06:32.150572
10227 11:06:32.418213 01080000 ################################################################
10228 11:06:32.418349
10229 11:06:32.680473 01100000 ################################################################
10230 11:06:32.680640
10231 11:06:32.967484 01180000 ################################################################
10232 11:06:32.967615
10233 11:06:33.239476 01200000 ################################################################
10234 11:06:33.239618
10235 11:06:33.511071 01280000 ################################################################
10236 11:06:33.511215
10237 11:06:33.770889 01300000 ################################################################
10238 11:06:33.771024
10239 11:06:34.033108 01380000 ################################################################
10240 11:06:34.033247
10241 11:06:34.297402 01400000 ################################################################
10242 11:06:34.297542
10243 11:06:34.588736 01480000 ################################################################
10244 11:06:34.588890
10245 11:06:34.879974 01500000 ################################################################
10246 11:06:34.880119
10247 11:06:35.180889 01580000 ################################################################
10248 11:06:35.181026
10249 11:06:35.480238 01600000 ################################################################
10250 11:06:35.480811
10251 11:06:35.896262 01680000 ################################################################
10252 11:06:35.896966
10253 11:06:36.219455 01700000 ################################################################
10254 11:06:36.219598
10255 11:06:36.509656 01780000 ################################################################
10256 11:06:36.509807
10257 11:06:36.779100 01800000 ################################################################
10258 11:06:36.779238
10259 11:06:37.043576 01880000 ################################################################
10260 11:06:37.043721
10261 11:06:37.294938 01900000 ################################################################
10262 11:06:37.295067
10263 11:06:37.572258 01980000 ################################################################
10264 11:06:37.572391
10265 11:06:37.859077 01a00000 ################################################################
10266 11:06:37.859208
10267 11:06:38.164103 01a80000 ################################################################
10268 11:06:38.164243
10269 11:06:38.438613 01b00000 ################################################################
10270 11:06:38.438789
10271 11:06:38.700237 01b80000 ################################################################
10272 11:06:38.700417
10273 11:06:38.956471 01c00000 ################################################################
10274 11:06:38.956646
10275 11:06:39.214371 01c80000 ################################################################
10276 11:06:39.214523
10277 11:06:39.477542 01d00000 ########################################################## done.
10278 11:06:39.477693
10279 11:06:39.480946 The bootfile was 30881894 bytes long.
10280 11:06:39.481033
10281 11:06:39.484288 Sending tftp read request... done.
10282 11:06:39.484373
10283 11:06:39.484440 Waiting for the transfer...
10284 11:06:39.484504
10285 11:06:39.487698 00000000 # done.
10286 11:06:39.487784
10287 11:06:39.494739 Command line loaded dynamically from TFTP file: 12925642/tftp-deploy-c06bihlb/kernel/cmdline
10288 11:06:39.494825
10289 11:06:39.517618 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12925642/extract-nfsrootfs-iujlsesm,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10290 11:06:39.517713
10291 11:06:39.517781 Loading FIT.
10292 11:06:39.517844
10293 11:06:39.520930 Image ramdisk-1 has 18774881 bytes.
10294 11:06:39.521015
10295 11:06:39.524824 Image fdt-1 has 47278 bytes.
10296 11:06:39.524909
10297 11:06:39.527752 Image kernel-1 has 12057697 bytes.
10298 11:06:39.527837
10299 11:06:39.537766 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10300 11:06:39.537877
10301 11:06:39.554396 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10302 11:06:39.554484
10303 11:06:39.557682 Choosing best match conf-1 for compat google,spherion-rev2.
10304 11:06:39.563299
10305 11:06:39.567866 Connected to device vid:did:rid of 1ae0:0028:00
10306 11:06:39.574993
10307 11:06:39.578058 tpm_get_response: command 0x17b, return code 0x0
10308 11:06:39.578141
10309 11:06:39.581319 ec_init: CrosEC protocol v3 supported (256, 248)
10310 11:06:39.585564
10311 11:06:39.589233 tpm_cleanup: add release locality here.
10312 11:06:39.589316
10313 11:06:39.589380 Shutting down all USB controllers.
10314 11:06:39.592083
10315 11:06:39.592167 Removing current net device
10316 11:06:39.592231
10317 11:06:39.599123 Exiting depthcharge with code 4 at timestamp: 53039180
10318 11:06:39.599204
10319 11:06:39.602199 LZMA decompressing kernel-1 to 0x821a6718
10320 11:06:39.602280
10321 11:06:39.605647 LZMA decompressing kernel-1 to 0x40000000
10322 11:06:41.105597
10323 11:06:41.105739 jumping to kernel
10324 11:06:41.106207 end: 2.2.4 bootloader-commands (duration 00:00:25) [common]
10325 11:06:41.106308 start: 2.2.5 auto-login-action (timeout 00:04:00) [common]
10326 11:06:41.106386 Setting prompt string to ['Linux version [0-9]']
10327 11:06:41.106456 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10328 11:06:41.106525 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10329 11:06:41.187338
10330 11:06:41.190910 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10331 11:06:41.193922 start: 2.2.5.1 login-action (timeout 00:04:00) [common]
10332 11:06:41.194057 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10333 11:06:41.194129 Setting prompt string to []
10334 11:06:41.194204 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10335 11:06:41.194277 Using line separator: #'\n'#
10336 11:06:41.194337 No login prompt set.
10337 11:06:41.194399 Parsing kernel messages
10338 11:06:41.194454 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10339 11:06:41.194553 [login-action] Waiting for messages, (timeout 00:04:00)
10340 11:06:41.194616 Waiting using forced prompt support (timeout 00:02:00)
10341 11:06:41.214377 [ 0.000000] Linux version 6.1.80-cip16 (KernelCI@build-j128891-arm64-gcc-10-defconfig-arm64-chromebook-nrg4h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024
10342 11:06:41.217302 [ 0.000000] random: crng init done
10343 11:06:41.224077 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10344 11:06:41.227388 [ 0.000000] efi: UEFI not found.
10345 11:06:41.233826 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10346 11:06:41.240763 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10347 11:06:41.250493 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10348 11:06:41.260366 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10349 11:06:41.267173 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10350 11:06:41.273412 [ 0.000000] printk: bootconsole [mtk8250] enabled
10351 11:06:41.279905 [ 0.000000] NUMA: No NUMA configuration found
10352 11:06:41.287044 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10353 11:06:41.289893 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10354 11:06:41.293620 [ 0.000000] Zone ranges:
10355 11:06:41.299782 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10356 11:06:41.303222 [ 0.000000] DMA32 empty
10357 11:06:41.309611 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10358 11:06:41.313514 [ 0.000000] Movable zone start for each node
10359 11:06:41.316408 [ 0.000000] Early memory node ranges
10360 11:06:41.323073 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10361 11:06:41.329567 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10362 11:06:41.336272 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10363 11:06:41.343189 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10364 11:06:41.349811 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10365 11:06:41.356292 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10366 11:06:41.412312 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10367 11:06:41.419110 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10368 11:06:41.425496 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10369 11:06:41.428410 [ 0.000000] psci: probing for conduit method from DT.
10370 11:06:41.435466 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10371 11:06:41.438857 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10372 11:06:41.445377 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10373 11:06:41.448368 [ 0.000000] psci: SMC Calling Convention v1.2
10374 11:06:41.455316 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10375 11:06:41.458880 [ 0.000000] Detected VIPT I-cache on CPU0
10376 11:06:41.465516 [ 0.000000] CPU features: detected: GIC system register CPU interface
10377 11:06:41.472007 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10378 11:06:41.478410 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10379 11:06:41.484868 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10380 11:06:41.491530 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10381 11:06:41.498397 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10382 11:06:41.504630 [ 0.000000] alternatives: applying boot alternatives
10383 11:06:41.511254 [ 0.000000] Fallback order for Node 0: 0
10384 11:06:41.518342 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10385 11:06:41.521653 [ 0.000000] Policy zone: Normal
10386 11:06:41.544605 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12925642/extract-nfsrootfs-iujlsesm,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10387 11:06:41.554077 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10388 11:06:41.564792 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10389 11:06:41.575014 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10390 11:06:41.581610 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10391 11:06:41.584936 <6>[ 0.000000] software IO TLB: area num 8.
10392 11:06:41.641395 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10393 11:06:41.791203 <6>[ 0.000000] Memory: 7948856K/8385536K available (18048K kernel code, 4118K rwdata, 19616K rodata, 8448K init, 616K bss, 403912K reserved, 32768K cma-reserved)
10394 11:06:41.797785 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10395 11:06:41.804402 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10396 11:06:41.807749 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10397 11:06:41.814715 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10398 11:06:41.821480 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10399 11:06:41.824792 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10400 11:06:41.834893 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10401 11:06:41.841464 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10402 11:06:41.845003 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10403 11:06:41.852535 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10404 11:06:41.855576 <6>[ 0.000000] GICv3: 608 SPIs implemented
10405 11:06:41.862267 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10406 11:06:41.865705 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10407 11:06:41.869269 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10408 11:06:41.878888 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10409 11:06:41.888994 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10410 11:06:41.902240 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10411 11:06:41.908825 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10412 11:06:41.917918 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10413 11:06:41.931272 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10414 11:06:41.937728 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10415 11:06:41.944499 <6>[ 0.009182] Console: colour dummy device 80x25
10416 11:06:41.954023 <6>[ 0.013913] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10417 11:06:41.961152 <6>[ 0.024383] pid_max: default: 32768 minimum: 301
10418 11:06:41.964362 <6>[ 0.029255] LSM: Security Framework initializing
10419 11:06:41.970658 <6>[ 0.034195] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10420 11:06:41.980392 <6>[ 0.042009] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10421 11:06:41.986959 <6>[ 0.051324] cblist_init_generic: Setting adjustable number of callback queues.
10422 11:06:41.993477 <6>[ 0.058767] cblist_init_generic: Setting shift to 3 and lim to 1.
10423 11:06:42.003247 <6>[ 0.065107] cblist_init_generic: Setting adjustable number of callback queues.
10424 11:06:42.009883 <6>[ 0.072534] cblist_init_generic: Setting shift to 3 and lim to 1.
10425 11:06:42.013290 <6>[ 0.078936] rcu: Hierarchical SRCU implementation.
10426 11:06:42.020135 <6>[ 0.083982] rcu: Max phase no-delay instances is 1000.
10427 11:06:42.026865 <6>[ 0.091007] EFI services will not be available.
10428 11:06:42.030114 <6>[ 0.095961] smp: Bringing up secondary CPUs ...
10429 11:06:42.038062 <6>[ 0.100978] Detected VIPT I-cache on CPU1
10430 11:06:42.044696 <6>[ 0.101035] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10431 11:06:42.051629 <6>[ 0.101060] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10432 11:06:42.054612 <6>[ 0.101391] Detected VIPT I-cache on CPU2
10433 11:06:42.061118 <6>[ 0.101441] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10434 11:06:42.068269 <6>[ 0.101457] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10435 11:06:42.074359 <6>[ 0.101717] Detected VIPT I-cache on CPU3
10436 11:06:42.081186 <6>[ 0.101762] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10437 11:06:42.087862 <6>[ 0.101776] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10438 11:06:42.091082 <6>[ 0.102081] CPU features: detected: Spectre-v4
10439 11:06:42.097696 <6>[ 0.102087] CPU features: detected: Spectre-BHB
10440 11:06:42.101163 <6>[ 0.102092] Detected PIPT I-cache on CPU4
10441 11:06:42.107644 <6>[ 0.102149] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10442 11:06:42.114198 <6>[ 0.102165] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10443 11:06:42.120812 <6>[ 0.102462] Detected PIPT I-cache on CPU5
10444 11:06:42.127516 <6>[ 0.102527] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10445 11:06:42.133863 <6>[ 0.102544] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10446 11:06:42.137132 <6>[ 0.102828] Detected PIPT I-cache on CPU6
10447 11:06:42.144097 <6>[ 0.102893] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10448 11:06:42.150591 <6>[ 0.102910] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10449 11:06:42.157015 <6>[ 0.103208] Detected PIPT I-cache on CPU7
10450 11:06:42.163573 <6>[ 0.103274] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10451 11:06:42.170188 <6>[ 0.103290] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10452 11:06:42.173679 <6>[ 0.103336] smp: Brought up 1 node, 8 CPUs
10453 11:06:42.180515 <6>[ 0.244693] SMP: Total of 8 processors activated.
10454 11:06:42.183543 <6>[ 0.249613] CPU features: detected: 32-bit EL0 Support
10455 11:06:42.193421 <6>[ 0.254977] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10456 11:06:42.200434 <6>[ 0.263778] CPU features: detected: Common not Private translations
10457 11:06:42.207329 <6>[ 0.270254] CPU features: detected: CRC32 instructions
10458 11:06:42.210803 <6>[ 0.275605] CPU features: detected: RCpc load-acquire (LDAPR)
10459 11:06:42.217237 <6>[ 0.281565] CPU features: detected: LSE atomic instructions
10460 11:06:42.223976 <6>[ 0.287383] CPU features: detected: Privileged Access Never
10461 11:06:42.230631 <6>[ 0.293162] CPU features: detected: RAS Extension Support
10462 11:06:42.237306 <6>[ 0.298806] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10463 11:06:42.240661 <6>[ 0.306025] CPU: All CPU(s) started at EL2
10464 11:06:42.247403 <6>[ 0.310342] alternatives: applying system-wide alternatives
10465 11:06:42.256059 <6>[ 0.321103] devtmpfs: initialized
10466 11:06:42.268607 <6>[ 0.330088] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10467 11:06:42.278521 <6>[ 0.340048] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10468 11:06:42.285250 <6>[ 0.348071] pinctrl core: initialized pinctrl subsystem
10469 11:06:42.288400 <6>[ 0.354742] DMI not present or invalid.
10470 11:06:42.294893 <6>[ 0.359155] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10471 11:06:42.304673 <6>[ 0.366026] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10472 11:06:42.311371 <6>[ 0.373622] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10473 11:06:42.321593 <6>[ 0.381842] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10474 11:06:42.325039 <6>[ 0.390083] audit: initializing netlink subsys (disabled)
10475 11:06:42.334584 <5>[ 0.395776] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10476 11:06:42.341270 <6>[ 0.396481] thermal_sys: Registered thermal governor 'step_wise'
10477 11:06:42.348024 <6>[ 0.403743] thermal_sys: Registered thermal governor 'power_allocator'
10478 11:06:42.351429 <6>[ 0.409998] cpuidle: using governor menu
10479 11:06:42.357849 <6>[ 0.420960] NET: Registered PF_QIPCRTR protocol family
10480 11:06:42.364888 <6>[ 0.426444] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10481 11:06:42.368216 <6>[ 0.433550] ASID allocator initialised with 32768 entries
10482 11:06:42.375196 <6>[ 0.440124] Serial: AMBA PL011 UART driver
10483 11:06:42.383940 <4>[ 0.448916] Trying to register duplicate clock ID: 134
10484 11:06:42.438611 <6>[ 0.506774] KASLR enabled
10485 11:06:42.452769 <6>[ 0.514475] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10486 11:06:42.459422 <6>[ 0.521491] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10487 11:06:42.466032 <6>[ 0.527982] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10488 11:06:42.472839 <6>[ 0.534987] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10489 11:06:42.479455 <6>[ 0.541474] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10490 11:06:42.486253 <6>[ 0.548478] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10491 11:06:42.492438 <6>[ 0.554963] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10492 11:06:42.499001 <6>[ 0.561970] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10493 11:06:42.502333 <6>[ 0.569500] ACPI: Interpreter disabled.
10494 11:06:42.510765 <6>[ 0.575929] iommu: Default domain type: Translated
10495 11:06:42.517601 <6>[ 0.581041] iommu: DMA domain TLB invalidation policy: strict mode
10496 11:06:42.520756 <5>[ 0.587698] SCSI subsystem initialized
10497 11:06:42.527405 <6>[ 0.591866] usbcore: registered new interface driver usbfs
10498 11:06:42.534271 <6>[ 0.597599] usbcore: registered new interface driver hub
10499 11:06:42.537128 <6>[ 0.603152] usbcore: registered new device driver usb
10500 11:06:42.544358 <6>[ 0.609251] pps_core: LinuxPPS API ver. 1 registered
10501 11:06:42.554304 <6>[ 0.614444] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10502 11:06:42.557714 <6>[ 0.623792] PTP clock support registered
10503 11:06:42.560586 <6>[ 0.628036] EDAC MC: Ver: 3.0.0
10504 11:06:42.568360 <6>[ 0.633199] FPGA manager framework
10505 11:06:42.574752 <6>[ 0.636882] Advanced Linux Sound Architecture Driver Initialized.
10506 11:06:42.578141 <6>[ 0.643658] vgaarb: loaded
10507 11:06:42.584858 <6>[ 0.646822] clocksource: Switched to clocksource arch_sys_counter
10508 11:06:42.588148 <5>[ 0.653257] VFS: Disk quotas dquot_6.6.0
10509 11:06:42.594614 <6>[ 0.657442] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10510 11:06:42.597899 <6>[ 0.664629] pnp: PnP ACPI: disabled
10511 11:06:42.606234 <6>[ 0.671267] NET: Registered PF_INET protocol family
10512 11:06:42.615954 <6>[ 0.676853] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10513 11:06:42.627720 <6>[ 0.689145] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10514 11:06:42.637518 <6>[ 0.697959] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10515 11:06:42.644217 <6>[ 0.705929] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10516 11:06:42.650894 <6>[ 0.714633] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10517 11:06:42.662996 <6>[ 0.724378] TCP: Hash tables configured (established 65536 bind 65536)
10518 11:06:42.669645 <6>[ 0.731241] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10519 11:06:42.676028 <6>[ 0.738438] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10520 11:06:42.682727 <6>[ 0.746136] NET: Registered PF_UNIX/PF_LOCAL protocol family
10521 11:06:42.689218 <6>[ 0.752310] RPC: Registered named UNIX socket transport module.
10522 11:06:42.692519 <6>[ 0.758463] RPC: Registered udp transport module.
10523 11:06:42.699173 <6>[ 0.763397] RPC: Registered tcp transport module.
10524 11:06:42.705632 <6>[ 0.768329] RPC: Registered tcp NFSv4.1 backchannel transport module.
10525 11:06:42.709235 <6>[ 0.774998] PCI: CLS 0 bytes, default 64
10526 11:06:42.712274 <6>[ 0.779407] Unpacking initramfs...
10527 11:06:42.737203 <6>[ 0.798909] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10528 11:06:42.747094 <6>[ 0.807587] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10529 11:06:42.750384 <6>[ 0.816441] kvm [1]: IPA Size Limit: 40 bits
10530 11:06:42.757431 <6>[ 0.820968] kvm [1]: GICv3: no GICV resource entry
10531 11:06:42.760629 <6>[ 0.825988] kvm [1]: disabling GICv2 emulation
10532 11:06:42.767296 <6>[ 0.830674] kvm [1]: GIC system register CPU interface enabled
10533 11:06:42.770584 <6>[ 0.836833] kvm [1]: vgic interrupt IRQ18
10534 11:06:42.777067 <6>[ 0.841184] kvm [1]: VHE mode initialized successfully
10535 11:06:42.783646 <5>[ 0.847680] Initialise system trusted keyrings
10536 11:06:42.789673 <6>[ 0.852518] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10537 11:06:42.797472 <6>[ 0.862493] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10538 11:06:42.804188 <5>[ 0.868909] NFS: Registering the id_resolver key type
10539 11:06:42.807385 <5>[ 0.874211] Key type id_resolver registered
10540 11:06:42.813998 <5>[ 0.878626] Key type id_legacy registered
10541 11:06:42.820749 <6>[ 0.882915] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10542 11:06:42.827536 <6>[ 0.889840] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10543 11:06:42.833781 <6>[ 0.897551] 9p: Installing v9fs 9p2000 file system support
10544 11:06:42.870175 <5>[ 0.934910] Key type asymmetric registered
10545 11:06:42.873316 <5>[ 0.939239] Asymmetric key parser 'x509' registered
10546 11:06:42.883373 <6>[ 0.944379] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10547 11:06:42.886982 <6>[ 0.952000] io scheduler mq-deadline registered
10548 11:06:42.889813 <6>[ 0.956777] io scheduler kyber registered
10549 11:06:42.908790 <6>[ 0.973784] EINJ: ACPI disabled.
10550 11:06:42.941013 <4>[ 0.999332] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10551 11:06:42.950836 <4>[ 1.009972] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10552 11:06:42.966203 <6>[ 1.031222] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10553 11:06:42.974266 <6>[ 1.039398] printk: console [ttyS0] disabled
10554 11:06:43.002691 <6>[ 1.064024] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10555 11:06:43.008880 <6>[ 1.073500] printk: console [ttyS0] enabled
10556 11:06:43.012587 <6>[ 1.073500] printk: console [ttyS0] enabled
10557 11:06:43.018855 <6>[ 1.082394] printk: bootconsole [mtk8250] disabled
10558 11:06:43.022100 <6>[ 1.082394] printk: bootconsole [mtk8250] disabled
10559 11:06:43.028650 <6>[ 1.093679] SuperH (H)SCI(F) driver initialized
10560 11:06:43.031898 <6>[ 1.099006] msm_serial: driver initialized
10561 11:06:43.046574 <6>[ 1.107997] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10562 11:06:43.056326 <6>[ 1.116545] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10563 11:06:43.062956 <6>[ 1.125088] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10564 11:06:43.073308 <6>[ 1.133716] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10565 11:06:43.079489 <6>[ 1.142422] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10566 11:06:43.089580 <6>[ 1.151142] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10567 11:06:43.099322 <6>[ 1.159682] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10568 11:06:43.106427 <6>[ 1.168487] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10569 11:06:43.116145 <6>[ 1.177032] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10570 11:06:43.127497 <6>[ 1.192624] loop: module loaded
10571 11:06:43.134061 <6>[ 1.198669] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10572 11:06:43.157175 <4>[ 1.222226] mtk-pmic-keys: Failed to locate of_node [id: -1]
10573 11:06:43.164181 <6>[ 1.229261] megasas: 07.719.03.00-rc1
10574 11:06:43.173988 <6>[ 1.238947] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10575 11:06:43.185107 <6>[ 1.250203] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10576 11:06:43.202189 <6>[ 1.266978] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10577 11:06:43.258648 <6>[ 1.317031] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10578 11:06:43.506074 <6>[ 1.571588] Freeing initrd memory: 18332K
10579 11:06:43.517901 <6>[ 1.583129] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10580 11:06:43.528866 <6>[ 1.594168] tun: Universal TUN/TAP device driver, 1.6
10581 11:06:43.532198 <6>[ 1.600236] thunder_xcv, ver 1.0
10582 11:06:43.535565 <6>[ 1.603743] thunder_bgx, ver 1.0
10583 11:06:43.538848 <6>[ 1.607239] nicpf, ver 1.0
10584 11:06:43.549699 <6>[ 1.611250] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10585 11:06:43.552886 <6>[ 1.618725] hns3: Copyright (c) 2017 Huawei Corporation.
10586 11:06:43.559468 <6>[ 1.624314] hclge is initializing
10587 11:06:43.562715 <6>[ 1.627897] e1000: Intel(R) PRO/1000 Network Driver
10588 11:06:43.569369 <6>[ 1.633027] e1000: Copyright (c) 1999-2006 Intel Corporation.
10589 11:06:43.572744 <6>[ 1.639039] e1000e: Intel(R) PRO/1000 Network Driver
10590 11:06:43.579503 <6>[ 1.644254] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10591 11:06:43.585899 <6>[ 1.650438] igb: Intel(R) Gigabit Ethernet Network Driver
10592 11:06:43.592799 <6>[ 1.656088] igb: Copyright (c) 2007-2014 Intel Corporation.
10593 11:06:43.599306 <6>[ 1.661924] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10594 11:06:43.606103 <6>[ 1.668442] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10595 11:06:43.609338 <6>[ 1.674913] sky2: driver version 1.30
10596 11:06:43.615687 <6>[ 1.679906] VFIO - User Level meta-driver version: 0.3
10597 11:06:43.623318 <6>[ 1.688164] usbcore: registered new interface driver usb-storage
10598 11:06:43.629651 <6>[ 1.694611] usbcore: registered new device driver onboard-usb-hub
10599 11:06:43.638823 <6>[ 1.703819] mt6397-rtc mt6359-rtc: registered as rtc0
10600 11:06:43.648530 <6>[ 1.709300] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T11:06:06 UTC (1709463966)
10601 11:06:43.652002 <6>[ 1.718901] i2c_dev: i2c /dev entries driver
10602 11:06:43.668478 <6>[ 1.730518] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10603 11:06:43.688137 <6>[ 1.753536] cpu cpu0: EM: created perf domain
10604 11:06:43.691489 <6>[ 1.758460] cpu cpu4: EM: created perf domain
10605 11:06:43.698670 <6>[ 1.764021] sdhci: Secure Digital Host Controller Interface driver
10606 11:06:43.705284 <6>[ 1.770454] sdhci: Copyright(c) Pierre Ossman
10607 11:06:43.712136 <6>[ 1.775415] Synopsys Designware Multimedia Card Interface Driver
10608 11:06:43.719151 <6>[ 1.782043] sdhci-pltfm: SDHCI platform and OF driver helper
10609 11:06:43.722429 <6>[ 1.782059] mmc0: CQHCI version 5.10
10610 11:06:43.729144 <6>[ 1.792287] ledtrig-cpu: registered to indicate activity on CPUs
10611 11:06:43.735736 <6>[ 1.799308] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10612 11:06:43.742347 <6>[ 1.806385] usbcore: registered new interface driver usbhid
10613 11:06:43.746095 <6>[ 1.812206] usbhid: USB HID core driver
10614 11:06:43.752335 <6>[ 1.816399] spi_master spi0: will run message pump with realtime priority
10615 11:06:43.795712 <6>[ 1.854400] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10616 11:06:43.813829 <6>[ 1.869414] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10617 11:06:43.817284 <6>[ 1.882997] mmc0: Command Queue Engine enabled
10618 11:06:43.824797 <6>[ 1.887812] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10619 11:06:43.831635 <6>[ 1.895127] mmcblk0: mmc0:0001 DA4128 116 GiB
10620 11:06:43.834555 <6>[ 1.900088] cros-ec-spi spi0.0: Chrome EC device registered
10621 11:06:43.841320 <6>[ 1.903823] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10622 11:06:43.848852 <6>[ 1.913815] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10623 11:06:43.855730 <6>[ 1.919684] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10624 11:06:43.862016 <6>[ 1.925940] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10625 11:06:43.878690 <6>[ 1.940431] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10626 11:06:43.886390 <6>[ 1.951132] NET: Registered PF_PACKET protocol family
10627 11:06:43.889604 <6>[ 1.956526] 9pnet: Installing 9P2000 support
10628 11:06:43.896273 <5>[ 1.961068] Key type dns_resolver registered
10629 11:06:43.899570 <6>[ 1.966094] registered taskstats version 1
10630 11:06:43.906144 <5>[ 1.970471] Loading compiled-in X.509 certificates
10631 11:06:43.937646 <4>[ 1.995832] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10632 11:06:43.947843 <4>[ 2.006620] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10633 11:06:43.954536 <3>[ 2.017161] debugfs: File 'uA_load' in directory '/' already present!
10634 11:06:43.960676 <3>[ 2.023864] debugfs: File 'min_uV' in directory '/' already present!
10635 11:06:43.967371 <3>[ 2.030473] debugfs: File 'max_uV' in directory '/' already present!
10636 11:06:43.974039 <3>[ 2.037080] debugfs: File 'constraint_flags' in directory '/' already present!
10637 11:06:43.984810 <3>[ 2.046681] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10638 11:06:43.997304 <6>[ 2.062162] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10639 11:06:44.004116 <6>[ 2.068995] xhci-mtk 11200000.usb: xHCI Host Controller
10640 11:06:44.010786 <6>[ 2.074519] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10641 11:06:44.020899 <6>[ 2.082446] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10642 11:06:44.027606 <6>[ 2.091866] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10643 11:06:44.034131 <6>[ 2.097953] xhci-mtk 11200000.usb: xHCI Host Controller
10644 11:06:44.040921 <6>[ 2.103446] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10645 11:06:44.047054 <6>[ 2.111103] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10646 11:06:44.054131 <6>[ 2.118996] hub 1-0:1.0: USB hub found
10647 11:06:44.057636 <6>[ 2.123020] hub 1-0:1.0: 1 port detected
10648 11:06:44.064229 <6>[ 2.127313] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10649 11:06:44.071297 <6>[ 2.136098] hub 2-0:1.0: USB hub found
10650 11:06:44.074390 <6>[ 2.140122] hub 2-0:1.0: 1 port detected
10651 11:06:44.081787 <6>[ 2.146673] mtk-msdc 11f70000.mmc: Got CD GPIO
10652 11:06:44.094105 <6>[ 2.155875] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10653 11:06:44.100882 <6>[ 2.163902] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10654 11:06:44.110563 <4>[ 2.171816] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10655 11:06:44.120409 <6>[ 2.181361] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10656 11:06:44.127190 <6>[ 2.189438] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10657 11:06:44.133658 <6>[ 2.197458] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10658 11:06:44.143675 <6>[ 2.205381] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10659 11:06:44.150211 <6>[ 2.213199] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10660 11:06:44.160354 <6>[ 2.221018] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10661 11:06:44.169937 <6>[ 2.231508] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10662 11:06:44.177248 <6>[ 2.239877] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10663 11:06:44.187233 <6>[ 2.248222] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10664 11:06:44.193911 <6>[ 2.256560] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10665 11:06:44.203982 <6>[ 2.264897] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10666 11:06:44.210449 <6>[ 2.273235] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10667 11:06:44.220560 <6>[ 2.281572] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10668 11:06:44.227508 <6>[ 2.289909] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10669 11:06:44.236824 <6>[ 2.298245] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10670 11:06:44.243622 <6>[ 2.306582] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10671 11:06:44.253591 <6>[ 2.314919] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10672 11:06:44.259923 <6>[ 2.323256] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10673 11:06:44.270119 <6>[ 2.331593] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10674 11:06:44.280163 <6>[ 2.339930] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10675 11:06:44.286814 <6>[ 2.348268] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10676 11:06:44.293401 <6>[ 2.356988] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10677 11:06:44.299745 <6>[ 2.364120] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10678 11:06:44.306381 <6>[ 2.370872] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10679 11:06:44.313223 <6>[ 2.377628] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10680 11:06:44.322590 <6>[ 2.384569] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10681 11:06:44.329578 <6>[ 2.391411] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10682 11:06:44.339225 <6>[ 2.400549] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10683 11:06:44.349474 <6>[ 2.409668] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10684 11:06:44.358964 <6>[ 2.418963] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10685 11:06:44.369622 <6>[ 2.428431] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10686 11:06:44.375872 <6>[ 2.437897] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10687 11:06:44.385936 <6>[ 2.447016] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10688 11:06:44.395304 <6>[ 2.456481] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10689 11:06:44.405600 <6>[ 2.465599] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10690 11:06:44.415078 <6>[ 2.474893] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10691 11:06:44.425305 <6>[ 2.485053] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10692 11:06:44.435428 <6>[ 2.497074] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10693 11:06:44.442195 <6>[ 2.506756] Trying to probe devices needed for running init ...
10694 11:06:44.485165 <6>[ 2.547088] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10695 11:06:44.639919 <6>[ 2.705151] hub 1-1:1.0: USB hub found
10696 11:06:44.643188 <6>[ 2.709662] hub 1-1:1.0: 4 ports detected
10697 11:06:44.653179 <6>[ 2.718297] hub 1-1:1.0: USB hub found
10698 11:06:44.656830 <6>[ 2.722644] hub 1-1:1.0: 4 ports detected
10699 11:06:44.765685 <6>[ 2.827457] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10700 11:06:44.792050 <6>[ 2.857097] hub 2-1:1.0: USB hub found
10701 11:06:44.795000 <6>[ 2.861618] hub 2-1:1.0: 3 ports detected
10702 11:06:44.805054 <6>[ 2.869801] hub 2-1:1.0: USB hub found
10703 11:06:44.808033 <6>[ 2.874324] hub 2-1:1.0: 3 ports detected
10704 11:06:44.981631 <6>[ 3.043139] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10705 11:06:45.113814 <6>[ 3.179010] hub 1-1.4:1.0: USB hub found
10706 11:06:45.116676 <6>[ 3.183677] hub 1-1.4:1.0: 2 ports detected
10707 11:06:45.125838 <6>[ 3.191494] hub 1-1.4:1.0: USB hub found
10708 11:06:45.129198 <6>[ 3.196029] hub 1-1.4:1.0: 2 ports detected
10709 11:06:45.192905 <6>[ 3.255247] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10710 11:06:45.424773 <6>[ 3.487135] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10711 11:06:45.616748 <6>[ 3.679134] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10712 11:06:56.730752 <6>[ 14.800139] ALSA device list:
10713 11:06:56.736972 <6>[ 14.803425] No soundcards found.
10714 11:06:56.745141 <6>[ 14.811371] Freeing unused kernel memory: 8448K
10715 11:06:56.748392 <6>[ 14.816767] Run /init as init process
10716 11:06:56.758241 Loading, please wait...
10717 11:06:56.784362 Starting systemd-udevd version 252.22-1~deb12u1
10718 11:06:56.784959
10719 11:06:57.069875 <6>[ 15.132989] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10720 11:06:57.077023 <6>[ 15.140672] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10721 11:06:57.087090 <6>[ 15.149738] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10722 11:06:57.097852 <6>[ 15.161149] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10723 11:06:57.104519 <6>[ 15.161720] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10724 11:06:57.110921 <3>[ 15.169418] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 11:06:57.118100 <6>[ 15.179042] mc: Linux media interface: v0.10
10726 11:06:57.124212 <3>[ 15.184321] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 11:06:57.135068 <4>[ 15.187955] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10728 11:06:57.138466 <4>[ 15.187955] Fallback method does not support PEC.
10729 11:06:57.145346 <6>[ 15.189203] remoteproc remoteproc0: scp is available
10730 11:06:57.152059 <3>[ 15.196960] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 11:06:57.158587 <4>[ 15.198342] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10732 11:06:57.169055 <3>[ 15.205177] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10733 11:06:57.175870 <6>[ 15.210921] remoteproc remoteproc0: powering up scp
10734 11:06:57.182651 <3>[ 15.215297] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 11:06:57.188742 <3>[ 15.215320] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 11:06:57.198602 <3>[ 15.215324] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10737 11:06:57.205882 <3>[ 15.215333] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10738 11:06:57.214916 <3>[ 15.215338] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 11:06:57.221738 <3>[ 15.224410] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10740 11:06:57.228234 <4>[ 15.224477] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10741 11:06:57.238389 <6>[ 15.231420] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10742 11:06:57.244888 <6>[ 15.231458] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10743 11:06:57.248342 <6>[ 15.232077] videodev: Linux video capture interface: v2.00
10744 11:06:57.258135 <3>[ 15.240664] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 11:06:57.265058 <6>[ 15.241330] usbcore: registered new device driver r8152-cfgselector
10746 11:06:57.271105 <6>[ 15.280183] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10747 11:06:57.278241 <3>[ 15.286001] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 11:06:57.284598 <6>[ 15.294023] pci_bus 0000:00: root bus resource [bus 00-ff]
10749 11:06:57.294729 <3>[ 15.301178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10750 11:06:57.300974 <3>[ 15.301227] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 11:06:57.308072 <6>[ 15.309698] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10752 11:06:57.317738 <3>[ 15.315294] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10753 11:06:57.324243 <3>[ 15.315331] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 11:06:57.334292 <3>[ 15.315343] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 11:06:57.340688 <3>[ 15.315353] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 11:06:57.350829 <3>[ 15.315360] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10757 11:06:57.357192 <3>[ 15.315397] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 11:06:57.367310 <6>[ 15.315822] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10759 11:06:57.377272 <6>[ 15.316158] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10760 11:06:57.387184 <6>[ 15.321008] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10761 11:06:57.394116 <6>[ 15.327261] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10762 11:06:57.403670 <6>[ 15.331267] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10763 11:06:57.410547 <6>[ 15.335884] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10764 11:06:57.420300 <4>[ 15.350141] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10765 11:06:57.426740 <6>[ 15.351493] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10766 11:06:57.436568 <4>[ 15.356486] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10767 11:06:57.439957 <6>[ 15.364625] pci 0000:00:00.0: supports D1 D2
10768 11:06:57.443198 <6>[ 15.365257] Bluetooth: Core ver 2.22
10769 11:06:57.449971 <6>[ 15.365440] NET: Registered PF_BLUETOOTH protocol family
10770 11:06:57.456411 <6>[ 15.365444] Bluetooth: HCI device and connection manager initialized
10771 11:06:57.459754 <6>[ 15.365478] Bluetooth: HCI socket layer initialized
10772 11:06:57.466383 <6>[ 15.365486] Bluetooth: L2CAP socket layer initialized
10773 11:06:57.470222 <6>[ 15.365499] Bluetooth: SCO socket layer initialized
10774 11:06:57.479962 <6>[ 15.370903] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10775 11:06:57.486404 <6>[ 15.372685] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10776 11:06:57.493098 <6>[ 15.379788] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10777 11:06:57.503001 <6>[ 15.381052] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10778 11:06:57.509717 <6>[ 15.381623] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10779 11:06:57.519660 <6>[ 15.383297] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10780 11:06:57.526284 <6>[ 15.388569] remoteproc remoteproc0: remote processor scp is now up
10781 11:06:57.532666 <6>[ 15.413959] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10782 11:06:57.536002 <6>[ 15.414063] usbcore: registered new interface driver btusb
10783 11:06:57.542543 <6>[ 15.421095] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10784 11:06:57.555881 <4>[ 15.429306] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10785 11:06:57.565739 <6>[ 15.430372] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10786 11:06:57.572231 <6>[ 15.430466] usbcore: registered new interface driver uvcvideo
10787 11:06:57.579234 <6>[ 15.439149] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10788 11:06:57.585669 <6>[ 15.439756] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10789 11:06:57.592520 <6>[ 15.447125] r8152 2-1.3:1.0 eth0: v1.12.13
10790 11:06:57.595501 <6>[ 15.447161] usbcore: registered new interface driver r8152
10791 11:06:57.602102 <3>[ 15.448207] Bluetooth: hci0: Failed to load firmware file (-2)
10792 11:06:57.608967 <6>[ 15.458089] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10793 11:06:57.615550 <3>[ 15.466431] Bluetooth: hci0: Failed to set up firmware (-2)
10794 11:06:57.621807 <6>[ 15.475729] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10795 11:06:57.628758 <6>[ 15.475832] usbcore: registered new interface driver cdc_ether
10796 11:06:57.638762 <4>[ 15.481982] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10797 11:06:57.645033 <6>[ 15.482139] usbcore: registered new interface driver r8153_ecm
10798 11:06:57.651907 <6>[ 15.491035] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10799 11:06:57.658826 <6>[ 15.491135] pci 0000:01:00.0: supports D1 D2
10800 11:06:57.665298 <6>[ 15.728236] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10801 11:06:57.683779 <6>[ 15.747134] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10802 11:06:57.690425 <6>[ 15.754043] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10803 11:06:57.697221 <6>[ 15.762129] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10804 11:06:57.707370 <6>[ 15.770125] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10805 11:06:57.713581 <6>[ 15.778126] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10806 11:06:57.723543 <6>[ 15.786127] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10807 11:06:57.726820 <6>[ 15.794127] pci 0000:00:00.0: PCI bridge to [bus 01]
10808 11:06:57.736782 <6>[ 15.799344] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10809 11:06:57.743346 <6>[ 15.807480] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10810 11:06:57.749827 <6>[ 15.814357] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10811 11:06:57.756991 <6>[ 15.821095] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10812 11:06:57.771409 <5>[ 15.834846] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10813 11:06:57.796010 <5>[ 15.858991] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10814 11:06:57.802790 <5>[ 15.866050] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10815 11:06:57.812288 <4>[ 15.874454] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10816 11:06:57.815940 <6>[ 15.883337] cfg80211: failed to load regulatory.db
10817 11:06:57.857356 <6>[ 15.920475] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10818 11:06:57.863997 <6>[ 15.928016] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10819 11:06:57.884740 <6>[ 15.950957] mt7921e 0000:01:00.0: ASIC revision: 79610010
10820 11:06:57.987367 <6>[ 16.050498] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10821 11:06:57.990300 <6>[ 16.050498]
10822 11:06:58.001864 Begin: Loading essential drivers ... done.
10823 11:06:58.005155 Begin: Running /scripts/init-premount ... done.
10824 11:06:58.011574 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10825 11:06:58.021196 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10826 11:06:58.024435 Device /sys/class/net/enx00e04c722dd6 found
10827 11:06:58.024908 done.
10828 11:06:58.048275 Begin: Waiting up to 180 secs for any network device to become available ... done.
10829 11:06:58.083611 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10830 11:06:58.255338 <6>[ 16.318683] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10831 11:06:59.017252 <6>[ 17.083993] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10832 11:06:59.120540 <6>[ 17.187012] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10833 11:06:59.142727 IP-Config: no response after 2 secs - giving up
10834 11:06:59.181035 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:7b mtu 1500 DHCP
10835 11:06:59.871860 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10836 11:06:59.878161 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10837 11:06:59.885198 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10838 11:06:59.891408 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10839 11:06:59.898220 host : mt8192-asurada-spherion-r0-cbg-1
10840 11:06:59.904581 domain : lava-rack
10841 11:06:59.907583 rootserver: 192.168.201.1 rootpath:
10842 11:06:59.908080 filename :
10843 11:07:00.032726 done.
10844 11:07:00.039885 Begin: Running /scripts/nfs-bottom ... done.
10845 11:07:00.056876 Begin: Running /scripts/init-bottom ... done.
10846 11:07:01.411392 <6>[ 19.478225] NET: Registered PF_INET6 protocol family
10847 11:07:01.418963 <6>[ 19.486073] Segment Routing with IPv6
10848 11:07:01.422363 <6>[ 19.490097] In-situ OAM (IOAM) with IPv6
10849 11:07:01.626341 <30>[ 19.666558] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10850 11:07:01.632818 <30>[ 19.699666] systemd[1]: Detected architecture arm64.
10851 11:07:01.641770
10852 11:07:01.645023 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10853 11:07:01.645500
10854 11:07:01.645871
10855 11:07:01.673722 <30>[ 19.741007] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10856 11:07:02.740281 <30>[ 20.804391] systemd[1]: Queued start job for default target graphical.target.
10857 11:07:02.792906 <30>[ 20.856571] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10858 11:07:02.799414 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10859 11:07:02.799972
10860 11:07:02.821288 <30>[ 20.884953] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10861 11:07:02.831270 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10862 11:07:02.831854
10863 11:07:02.849320 <30>[ 20.912949] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10864 11:07:02.859034 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10865 11:07:02.859705
10866 11:07:02.876942 <30>[ 20.940543] systemd[1]: Created slice user.slice - User and Session Slice.
10867 11:07:02.883651 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10868 11:07:02.884227
10869 11:07:02.907084 <30>[ 20.967425] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10870 11:07:02.913234 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10871 11:07:02.916836
10872 11:07:02.934906 <30>[ 20.995356] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10873 11:07:02.941589 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10874 11:07:02.942218
10875 11:07:02.970048 <30>[ 21.023784] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10876 11:07:02.979686 <30>[ 21.043722] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10877 11:07:02.986575 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10878 11:07:02.987146
10879 11:07:03.003589 <30>[ 21.067130] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10880 11:07:03.010181 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10881 11:07:03.010752
10882 11:07:03.027702 <30>[ 21.091176] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10883 11:07:03.037258 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10884 11:07:03.037835
10885 11:07:03.052448 <30>[ 21.119238] systemd[1]: Reached target paths.target - Path Units.
10886 11:07:03.058795 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10887 11:07:03.061699
10888 11:07:03.079893 <30>[ 21.143553] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10889 11:07:03.086147 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10890 11:07:03.086662
10891 11:07:03.100284 <30>[ 21.167107] systemd[1]: Reached target slices.target - Slice Units.
10892 11:07:03.110195 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10893 11:07:03.110760
10894 11:07:03.124495 <30>[ 21.191608] systemd[1]: Reached target swap.target - Swaps.
10895 11:07:03.131039 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10896 11:07:03.131610
10897 11:07:03.152052 <30>[ 21.215620] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10898 11:07:03.161783 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10899 11:07:03.162409
10900 11:07:03.179718 <30>[ 21.243589] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10901 11:07:03.190046 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10902 11:07:03.190600
10903 11:07:03.210512 <30>[ 21.274313] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10904 11:07:03.220216 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10905 11:07:03.220700
10906 11:07:03.237013 <30>[ 21.300673] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10907 11:07:03.246581 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10908 11:07:03.247147
10909 11:07:03.263835 <30>[ 21.327810] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10910 11:07:03.270538 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10911 11:07:03.271102
10912 11:07:03.288741 <30>[ 21.352675] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10913 11:07:03.298695 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10914 11:07:03.299278
10915 11:07:03.317785 <30>[ 21.381901] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10916 11:07:03.328072 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10917 11:07:03.328665
10918 11:07:03.344551 <30>[ 21.408320] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10919 11:07:03.354567 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10920 11:07:03.355163
10921 11:07:03.415790 <30>[ 21.479576] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10922 11:07:03.422076 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10923 11:07:03.422554
10924 11:07:03.442113 <30>[ 21.506075] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10925 11:07:03.448475 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10926 11:07:03.448961
10927 11:07:03.490991 <30>[ 21.555364] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10928 11:07:03.497812 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10929 11:07:03.497900
10930 11:07:03.525930 <30>[ 21.583586] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10931 11:07:03.541114 <30>[ 21.605017] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10932 11:07:03.550894 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10933 11:07:03.551163
10934 11:07:03.576451 <30>[ 21.640662] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10935 11:07:03.583516 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10936 11:07:03.584082
10937 11:07:03.608951 <30>[ 21.672593] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10938 11:07:03.615340 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10939 11:07:03.615945
10940 11:07:03.639317 <30>[ 21.703235] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10941 11:07:03.645736 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10942 11:07:03.655695 <6>[ 21.717466] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10943 11:07:03.655863
10944 11:07:03.715712 <30>[ 21.779658] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10945 11:07:03.722495 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10946 11:07:03.725817
10947 11:07:03.752986 <30>[ 21.816812] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10948 11:07:03.759375 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10949 11:07:03.759859
10950 11:07:03.783519 <30>[ 21.847263] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10951 11:07:03.793090 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop..<6>[ 21.861998] fuse: init (API version 7.37)
10952 11:07:03.793582 .
10953 11:07:03.794011
10954 11:07:03.871896 <30>[ 21.935778] systemd[1]: Starting systemd-journald.service - Journal Service...
10955 11:07:03.878838 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10956 11:07:03.879417
10957 11:07:03.905043 <30>[ 21.969243] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10958 11:07:03.911995 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10959 11:07:03.912483
10960 11:07:03.939441 <30>[ 22.000275] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10961 11:07:03.946050 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10962 11:07:03.946536
10963 11:07:03.970427 <30>[ 22.034263] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10964 11:07:03.980228 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10965 11:07:03.980667
10966 11:07:04.004882 <30>[ 22.068831] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10967 11:07:04.011359 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10968 11:07:04.011802
10969 11:07:04.038101 <30>[ 22.102377] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10970 11:07:04.045244 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10971 11:07:04.045678
10972 11:07:04.063641 <30>[ 22.127497] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10973 11:07:04.073184 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10974 11:07:04.073626
10975 11:07:04.087331 <30>[ 22.151581] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10976 11:07:04.094335 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10977 11:07:04.094876
10978 11:07:04.108583 <3>[ 22.172244] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 11:07:04.118217 <30>[ 22.181933] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10980 11:07:04.128147 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10981 11:07:04.128593
10982 11:07:04.141594 <3>[ 22.205546] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 11:07:04.152309 <30>[ 22.215874] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10984 11:07:04.158629 <30>[ 22.223835] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10985 11:07:04.168594 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10986 11:07:04.169077
10987 11:07:04.192624 <30>[ 22.256112] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10988 11:07:04.199484 <3>[ 22.261053] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 11:07:04.209307 <30>[ 22.263931] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10990 11:07:04.216105 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10991 11:07:04.216712
10992 11:07:04.229286 <3>[ 22.293400] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10993 11:07:04.239466 <30>[ 22.303476] systemd[1]: modprobe@drm.service: Deactivated successfully.
10994 11:07:04.246258 <30>[ 22.311272] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10995 11:07:04.260408 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 22.323041] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10996 11:07:04.263592 rm.service[0m - Load Kernel Module drm.
10997 11:07:04.264164
10998 11:07:04.285072 <30>[ 22.348952] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10999 11:07:04.292030 <3>[ 22.353140] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 11:07:04.301651 <30>[ 22.357056] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11001 11:07:04.308947 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11002 11:07:04.311966
11003 11:07:04.321982 <3>[ 22.385133] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11004 11:07:04.331865 <30>[ 22.396030] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11005 11:07:04.339398 <30>[ 22.403838] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11006 11:07:04.352743 [[0;32m OK [0m] Finished [0<3>[ 22.414549] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 11:07:04.355977 ;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11008 11:07:04.356563
11009 11:07:04.373882 <30>[ 22.440623] systemd[1]: modprobe@loop.service: Deactivated successfully.
11010 11:07:04.384454 <3>[ 22.448275] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11011 11:07:04.390848 <30>[ 22.448490] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11012 11:07:04.400920 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11013 11:07:04.401582
11014 11:07:04.413512 <3>[ 22.477589] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11015 11:07:04.425526 <30>[ 22.489230] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
11016 11:07:04.432271 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11017 11:07:04.432898
11018 11:07:04.456485 <4>[ 22.513444] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11019 11:07:04.463159 <3>[ 22.529092] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
11020 11:07:04.477035 <30>[ 22.530647] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
11021 11:07:04.483748 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11022 11:07:04.484318
11023 11:07:04.504427 <30>[ 22.568053] systemd[1]: Started systemd-journald.service - Journal Service.
11024 11:07:04.510468 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11025 11:07:04.511029
11026 11:07:04.535541 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11027 11:07:04.536111
11028 11:07:04.553185 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11029 11:07:04.553769
11030 11:07:04.574198 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11031 11:07:04.574783
11032 11:07:04.644302 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11033 11:07:04.644869
11034 11:07:04.671498 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11035 11:07:04.672066
11036 11:07:04.694520 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11037 11:07:04.695084
11038 11:07:04.718218 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11039 11:07:04.718738
11040 11:07:04.749388 Starting [0;1;39msyste<46>[ 22.811924] systemd-journald[306]: Received client request to flush runtime journal.
11041 11:07:04.752597 md-sysctl.se…ce[0m - Apply Kernel Variables...
11042 11:07:04.753069
11043 11:07:04.797563 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11044 11:07:04.798114
11045 11:07:05.086092 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11046 11:07:05.086242
11047 11:07:05.103610 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11048 11:07:05.103697
11049 11:07:05.124200 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11050 11:07:05.124288
11051 11:07:05.144435 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11052 11:07:05.144523
11053 11:07:06.161529 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11054 11:07:06.161696
11055 11:07:06.180074 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11056 11:07:06.180254
11057 11:07:06.247832 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11058 11:07:06.248400
11059 11:07:06.372266 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11060 11:07:06.372842
11061 11:07:06.391616 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11062 11:07:06.392199
11063 11:07:06.411326 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11064 11:07:06.411900
11065 11:07:06.455782 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11066 11:07:06.456345
11067 11:07:06.483031 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11068 11:07:06.483640
11069 11:07:06.668740 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11070 11:07:06.668874
11071 11:07:06.741334 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11072 11:07:06.741439
11073 11:07:06.773117 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11074 11:07:06.773349
11075 11:07:06.840688 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11076 11:07:06.841126
11077 11:07:06.989369 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11078 11:07:06.989838
11079 11:07:07.017993 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11080 11:07:07.018081
11081 11:07:07.203967 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11082 11:07:07.204139
11083 11:07:07.245638 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11084 11:07:07.246189
11085 11:07:07.267190 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11086 11:07:07.267288
11087 11:07:07.334483 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11088 11:07:07.334595
11089 11:07:07.355181 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11090 11:07:07.355279
11091 11:07:07.379487 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11092 11:07:07.379578
11093 11:07:07.422642 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11094 11:07:07.422944
11095 11:07:07.433036 <46>[ 25.500918] systemd-journald[306]: Time jumped backwards, rotating.
11096 11:07:07.443500 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11097 11:07:07.443995
11098 11:07:07.463259 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11099 11:07:07.463729
11100 11:07:07.478490 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11101 11:07:07.478601
11102 11:07:07.494376 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11103 11:07:07.494572
11104 11:07:08.220260 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11105 11:07:08.220434
11106 11:07:08.545721 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11107 11:07:08.545891
11108 11:07:08.562661 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11109 11:07:08.562747
11110 11:07:08.909666 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11111 11:07:08.909896
11112 11:07:08.921755 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11113 11:07:08.921959
11114 11:07:08.938540 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11115 11:07:08.938750
11116 11:07:08.957323 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11117 11:07:08.957676
11118 11:07:08.975073 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11119 11:07:08.975656
11120 11:07:08.991434 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11121 11:07:08.992050
11122 11:07:09.012064 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11123 11:07:09.012646
11124 11:07:09.058065 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11125 11:07:09.058632
11126 11:07:09.091683 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11127 11:07:09.092261
11128 11:07:09.207322 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11129 11:07:09.207429
11130 11:07:09.236411 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11131 11:07:09.236506
11132 11:07:09.259187 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11133 11:07:09.259278
11134 11:07:09.389588 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11135 11:07:09.389745
11136 11:07:09.417970 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11137 11:07:09.418211
11138 11:07:09.461749 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11139 11:07:09.461864
11140 11:07:09.520508 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11141 11:07:09.521104
11142 11:07:09.543001 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11143 11:07:09.543155
11144 11:07:09.559743 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11145 11:07:09.559834
11146 11:07:09.578802 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11147 11:07:09.578999
11148 11:07:09.613293 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11149 11:07:09.613704
11150 11:07:09.644238 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11151 11:07:09.644828
11152 11:07:09.664021 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11153 11:07:09.664604
11154 11:07:09.725133 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11155 11:07:09.725718
11156 11:07:09.749892 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11157 11:07:09.750490
11158 11:07:09.797366 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11159 11:07:09.798028
11160 11:07:09.898846 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11161 11:07:09.899533
11162 11:07:09.991932
11163 11:07:09.992097
11164 11:07:09.995330 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11165 11:07:09.995407
11166 11:07:09.998420 debian-bookworm-arm64 login: root (automatic login)
11167 11:07:09.998504
11168 11:07:09.998572
11169 11:07:10.280063 Linux debian-bookworm-arm64 6.1.80-cip16 #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024 aarch64
11170 11:07:10.280214
11171 11:07:10.286667 The programs included with the Debian GNU/Linux system are free software;
11172 11:07:10.293900 the exact distribution terms for each program are described in the
11173 11:07:10.296728 individual files in /usr/share/doc/*/copyright.
11174 11:07:10.296802
11175 11:07:10.303460 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11176 11:07:10.306895 permitted by applicable law.
11177 11:07:11.381657 Matched prompt #10: / #
11179 11:07:11.382994 Setting prompt string to ['/ #']
11180 11:07:11.383476 end: 2.2.5.1 login-action (duration 00:00:30) [common]
11182 11:07:11.384551 end: 2.2.5 auto-login-action (duration 00:00:30) [common]
11183 11:07:11.385243 start: 2.2.6 expect-shell-connection (timeout 00:03:30) [common]
11184 11:07:11.385664 Setting prompt string to ['/ #']
11185 11:07:11.386049 Forcing a shell prompt, looking for ['/ #']
11187 11:07:11.436913 / #
11188 11:07:11.437577 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11189 11:07:11.438031 Waiting using forced prompt support (timeout 00:02:30)
11190 11:07:11.442946
11191 11:07:11.443946 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11192 11:07:11.444500 start: 2.2.7 export-device-env (timeout 00:03:30) [common]
11194 11:07:11.545774 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12925642/extract-nfsrootfs-iujlsesm'
11195 11:07:11.552179 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12925642/extract-nfsrootfs-iujlsesm'
11197 11:07:11.654077 / # export NFS_SERVER_IP='192.168.201.1'
11198 11:07:11.660218 export NFS_SERVER_IP='192.168.201.1'
11199 11:07:11.661195 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11200 11:07:11.661908 end: 2.2 depthcharge-retry (duration 00:01:31) [common]
11201 11:07:11.662509 end: 2 depthcharge-action (duration 00:01:31) [common]
11202 11:07:11.663082 start: 3 lava-test-retry (timeout 00:07:50) [common]
11203 11:07:11.663585 start: 3.1 lava-test-shell (timeout 00:07:50) [common]
11204 11:07:11.664017 Using namespace: common
11206 11:07:11.765342 / # #
11207 11:07:11.766034 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11208 11:07:11.771312 #
11209 11:07:11.772192 Using /lava-12925642
11211 11:07:11.873592 / # export SHELL=/bin/bash
11212 11:07:11.880076 export SHELL=/bin/bash
11214 11:07:11.982003 / # . /lava-12925642/environment
11215 11:07:11.988899 . /lava-12925642/environment
11217 11:07:12.096328 / # /lava-12925642/bin/lava-test-runner /lava-12925642/0
11218 11:07:12.096969 Test shell timeout: 10s (minimum of the action and connection timeout)
11219 11:07:12.102660 /lava-12925642/bin/lava-test-runner /lava-12925642/0
11220 11:07:12.344355 + export TESTRUN_ID=0_timesync-off
11221 11:07:12.347818 + TESTRUN_ID=0_timesync-off
11222 11:07:12.351091 + cd /lava-12925642/0/tests/0_timesync-off
11223 11:07:12.354154 ++ cat uuid
11224 11:07:12.357833 + UUID=12925642_1.6.2.3.1
11225 11:07:12.357954 + set +x
11226 11:07:12.361160 Received signal: <STARTRUN> 0_timesync-off 12925642_1.6.2.3.1
11227 11:07:12.361244 Starting test lava.0_timesync-off (12925642_1.6.2.3.1)
11228 11:07:12.361336 Skipping test definition patterns.
11229 11:07:12.364537 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12925642_1.6.2.3.1>
11230 11:07:12.364623 + systemctl stop systemd-timesyncd
11231 11:07:12.412805 + set +x
11232 11:07:12.415830 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12925642_1.6.2.3.1>
11233 11:07:12.416087 Received signal: <ENDRUN> 0_timesync-off 12925642_1.6.2.3.1
11234 11:07:12.416171 Ending use of test pattern.
11235 11:07:12.416236 Ending test lava.0_timesync-off (12925642_1.6.2.3.1), duration 0.05
11237 11:07:12.472315 + export TESTRUN_ID=1_kselftest-alsa
11238 11:07:12.475934 + TESTRUN_ID=1_kselftest-alsa
11239 11:07:12.478925 + cd /lava-12925642/0/tests/1_kselftest-alsa
11240 11:07:12.482483 ++ cat uuid
11241 11:07:12.485451 + UUID=12925642_1.6.2.3.5
11242 11:07:12.485536 + set +x
11243 11:07:12.492248 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 12925642_1.6.2.3.5>
11244 11:07:12.492503 Received signal: <STARTRUN> 1_kselftest-alsa 12925642_1.6.2.3.5
11245 11:07:12.492573 Starting test lava.1_kselftest-alsa (12925642_1.6.2.3.5)
11246 11:07:12.492653 Skipping test definition patterns.
11247 11:07:12.495609 + cd ./automated/linux/kselftest/
11248 11:07:12.518956 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11249 11:07:12.558041 INFO: install_deps skipped
11250 11:07:13.061738 --2024-03-03 11:06:35-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11251 11:07:13.068599 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11252 11:07:13.199287 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11253 11:07:13.334078 HTTP request sent, awaiting response... 200 OK
11254 11:07:13.337191 Length: 1746012 (1.7M) [application/octet-stream]
11255 11:07:13.340377 Saving to: 'kselftest.tar.xz'
11256 11:07:13.340458
11257 11:07:13.340522
11258 11:07:13.599245 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11259 11:07:13.865491 kselftest.tar.xz 2%[ ] 47.81K 181KB/s
11260 11:07:14.313564 kselftest.tar.xz 12%[=> ] 218.91K 413KB/s
11261 11:07:14.399407 kselftest.tar.xz 47%[========> ] 805.75K 824KB/s
11262 11:07:14.406406 kselftest.tar.xz 100%[===================>] 1.67M 1.56MB/s in 1.1s
11263 11:07:14.406882
11264 11:07:14.558830 2024-03-03 11:06:36 (1.56 MB/s) - 'kselftest.tar.xz' saved [1746012/1746012]
11265 11:07:14.558977
11266 11:07:18.344258 skiplist:
11267 11:07:18.347628 ========================================
11268 11:07:18.350830 ========================================
11269 11:07:18.392514 alsa:mixer-test
11270 11:07:18.410620 ============== Tests to run ===============
11271 11:07:18.410755 alsa:mixer-test
11272 11:07:18.413937 ===========End Tests to run ===============
11273 11:07:18.417276 shardfile-alsa pass
11274 11:07:18.508914 <12>[ 36.578487] kselftest: Running tests in alsa
11275 11:07:18.516883 TAP version 13
11276 11:07:18.529774 1..1
11277 11:07:18.542421 # selftests: alsa: mixer-test
11278 11:07:19.032345 # TAP version 13
11279 11:07:19.032499 # 1..0
11280 11:07:19.038586 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11281 11:07:19.041827 ok 1 selftests: alsa: mixer-test
11282 11:07:20.093647
11283 11:07:20.096887 WARNING: Optional imports not found, TAP 13 output will be
11284 11:07:20.103519 ignored. To parse yaml, see requirements in docs:
11285 11:07:20.106932 https://tappy.readthedocs.io/en/latest/consumers.html#tap-version-13
11286 11:07:20.110146 alsa_mixer-test pass
11287 11:07:20.146407 + ../../utils/send-to-lava.sh ./output/result.txt
11288 11:07:20.193354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11289 11:07:20.193684 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11291 11:07:20.522278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11292 11:07:20.522499 + set +x
11293 11:07:20.522810 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11295 11:07:20.528883 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 12925642_1.6.2.3.5>
11296 11:07:20.529198 Received signal: <ENDRUN> 1_kselftest-alsa 12925642_1.6.2.3.5
11297 11:07:20.529308 Ending use of test pattern.
11298 11:07:20.529398 Ending test lava.1_kselftest-alsa (12925642_1.6.2.3.5), duration 8.04
11300 11:07:20.532306 <LAVA_TEST_RUNNER EXIT>
11301 11:07:20.532560 ok: lava_test_shell seems to have completed
11302 11:07:20.532662 alsa_mixer-test: pass
shardfile-alsa: pass
11303 11:07:20.532752 end: 3.1 lava-test-shell (duration 00:00:09) [common]
11304 11:07:20.532837 end: 3 lava-test-retry (duration 00:00:09) [common]
11305 11:07:20.532959 start: 4 finalize (timeout 00:07:41) [common]
11306 11:07:20.533110 start: 4.1 power-off (timeout 00:00:30) [common]
11307 11:07:20.533397 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11308 11:07:20.609500 >> Command sent successfully.
11309 11:07:20.612244 Returned 0 in 0 seconds
11310 11:07:20.712650 end: 4.1 power-off (duration 00:00:00) [common]
11312 11:07:20.712991 start: 4.2 read-feedback (timeout 00:07:41) [common]
11313 11:07:20.713253 Listened to connection for namespace 'common' for up to 1s
11314 11:07:21.714046 Finalising connection for namespace 'common'
11315 11:07:21.714229 Disconnecting from shell: Finalise
11316 11:07:21.714333 / #
11317 11:07:21.814681 end: 4.2 read-feedback (duration 00:00:01) [common]
11318 11:07:21.814874 end: 4 finalize (duration 00:00:01) [common]
11319 11:07:21.815019 Cleaning after the job
11320 11:07:21.815137 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925642/tftp-deploy-c06bihlb/ramdisk
11321 11:07:21.817545 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925642/tftp-deploy-c06bihlb/kernel
11322 11:07:21.827602 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925642/tftp-deploy-c06bihlb/dtb
11323 11:07:21.827827 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925642/tftp-deploy-c06bihlb/nfsrootfs
11324 11:07:21.890700 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925642/tftp-deploy-c06bihlb/modules
11325 11:07:21.896325 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12925642
11326 11:07:22.437457 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12925642
11327 11:07:22.437631 Job finished correctly