Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 35
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 17
1 11:06:58.530566 lava-dispatcher, installed at version: 2024.01
2 11:06:58.530805 start: 0 validate
3 11:06:58.530978 Start time: 2024-03-03 11:06:58.530970+00:00 (UTC)
4 11:06:58.531112 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:06:58.531265 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20240129.0%2Farm64%2Finitrd.cpio.gz exists
6 11:06:58.794309 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:06:58.795016 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:06:59.065834 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:06:59.066523 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:06:59.336881 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:06:59.337591 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20240129.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:06:59.607797 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:06:59.608545 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:06:59.879051 validate duration: 1.35
16 11:06:59.879308 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:06:59.879401 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:06:59.879484 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:06:59.879607 Not decompressing ramdisk as can be used compressed.
20 11:06:59.879691 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20240129.0/arm64/initrd.cpio.gz
21 11:06:59.879753 saving as /var/lib/lava/dispatcher/tmp/12925646/tftp-deploy-n7u47uue/ramdisk/initrd.cpio.gz
22 11:06:59.879820 total size: 4663047 (4 MB)
23 11:06:59.880909 progress 0 % (0 MB)
24 11:06:59.882388 progress 5 % (0 MB)
25 11:06:59.883649 progress 10 % (0 MB)
26 11:06:59.884974 progress 15 % (0 MB)
27 11:06:59.886215 progress 20 % (0 MB)
28 11:06:59.887442 progress 25 % (1 MB)
29 11:06:59.888678 progress 30 % (1 MB)
30 11:06:59.889946 progress 35 % (1 MB)
31 11:06:59.891179 progress 40 % (1 MB)
32 11:06:59.892565 progress 45 % (2 MB)
33 11:06:59.893828 progress 50 % (2 MB)
34 11:06:59.895056 progress 55 % (2 MB)
35 11:06:59.896277 progress 60 % (2 MB)
36 11:06:59.897552 progress 65 % (2 MB)
37 11:06:59.898783 progress 70 % (3 MB)
38 11:06:59.900010 progress 75 % (3 MB)
39 11:06:59.901249 progress 80 % (3 MB)
40 11:06:59.902488 progress 85 % (3 MB)
41 11:06:59.903931 progress 90 % (4 MB)
42 11:06:59.905205 progress 95 % (4 MB)
43 11:06:59.906472 progress 100 % (4 MB)
44 11:06:59.906617 4 MB downloaded in 0.03 s (165.96 MB/s)
45 11:06:59.906775 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:06:59.907015 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:06:59.907100 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:06:59.907183 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:06:59.907321 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:06:59.907389 saving as /var/lib/lava/dispatcher/tmp/12925646/tftp-deploy-n7u47uue/kernel/Image
52 11:06:59.907452 total size: 51599872 (49 MB)
53 11:06:59.907513 No compression specified
54 11:06:59.908591 progress 0 % (0 MB)
55 11:06:59.921972 progress 5 % (2 MB)
56 11:06:59.935314 progress 10 % (4 MB)
57 11:06:59.949026 progress 15 % (7 MB)
58 11:06:59.962332 progress 20 % (9 MB)
59 11:06:59.975807 progress 25 % (12 MB)
60 11:06:59.989238 progress 30 % (14 MB)
61 11:07:00.002590 progress 35 % (17 MB)
62 11:07:00.015900 progress 40 % (19 MB)
63 11:07:00.029593 progress 45 % (22 MB)
64 11:07:00.043142 progress 50 % (24 MB)
65 11:07:00.056878 progress 55 % (27 MB)
66 11:07:00.070189 progress 60 % (29 MB)
67 11:07:00.083554 progress 65 % (32 MB)
68 11:07:00.096901 progress 70 % (34 MB)
69 11:07:00.110351 progress 75 % (36 MB)
70 11:07:00.123737 progress 80 % (39 MB)
71 11:07:00.137106 progress 85 % (41 MB)
72 11:07:00.150786 progress 90 % (44 MB)
73 11:07:00.163928 progress 95 % (46 MB)
74 11:07:00.177122 progress 100 % (49 MB)
75 11:07:00.177400 49 MB downloaded in 0.27 s (182.30 MB/s)
76 11:07:00.177555 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:07:00.177791 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:07:00.177878 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:07:00.177965 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:07:00.178106 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:07:00.178175 saving as /var/lib/lava/dispatcher/tmp/12925646/tftp-deploy-n7u47uue/dtb/mt8192-asurada-spherion-r0.dtb
83 11:07:00.178235 total size: 47278 (0 MB)
84 11:07:00.178295 No compression specified
85 11:07:00.179401 progress 69 % (0 MB)
86 11:07:00.179674 progress 100 % (0 MB)
87 11:07:00.179831 0 MB downloaded in 0.00 s (28.31 MB/s)
88 11:07:00.179951 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:07:00.180170 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:07:00.180254 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:07:00.180335 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:07:00.180450 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20240129.0/arm64/full.rootfs.tar.xz
94 11:07:00.180516 saving as /var/lib/lava/dispatcher/tmp/12925646/tftp-deploy-n7u47uue/nfsrootfs/full.rootfs.tar
95 11:07:00.180577 total size: 200856304 (191 MB)
96 11:07:00.180637 Using unxz to decompress xz
97 11:07:00.184907 progress 0 % (0 MB)
98 11:07:00.711852 progress 5 % (9 MB)
99 11:07:01.224696 progress 10 % (19 MB)
100 11:07:01.812935 progress 15 % (28 MB)
101 11:07:02.194846 progress 20 % (38 MB)
102 11:07:02.534567 progress 25 % (47 MB)
103 11:07:03.124512 progress 30 % (57 MB)
104 11:07:03.677042 progress 35 % (67 MB)
105 11:07:04.267834 progress 40 % (76 MB)
106 11:07:04.829233 progress 45 % (86 MB)
107 11:07:05.408711 progress 50 % (95 MB)
108 11:07:06.031717 progress 55 % (105 MB)
109 11:07:06.690211 progress 60 % (114 MB)
110 11:07:06.826256 progress 65 % (124 MB)
111 11:07:06.975982 progress 70 % (134 MB)
112 11:07:07.064958 progress 75 % (143 MB)
113 11:07:07.132388 progress 80 % (153 MB)
114 11:07:07.205958 progress 85 % (162 MB)
115 11:07:07.301732 progress 90 % (172 MB)
116 11:07:07.584812 progress 95 % (182 MB)
117 11:07:08.158311 progress 100 % (191 MB)
118 11:07:08.164038 191 MB downloaded in 7.98 s (23.99 MB/s)
119 11:07:08.164291 end: 1.4.1 http-download (duration 00:00:08) [common]
121 11:07:08.164604 end: 1.4 download-retry (duration 00:00:08) [common]
122 11:07:08.164694 start: 1.5 download-retry (timeout 00:09:52) [common]
123 11:07:08.164827 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 11:07:08.164979 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:07:08.165047 saving as /var/lib/lava/dispatcher/tmp/12925646/tftp-deploy-n7u47uue/modules/modules.tar
126 11:07:08.165108 total size: 8628476 (8 MB)
127 11:07:08.165173 Using unxz to decompress xz
128 11:07:08.169608 progress 0 % (0 MB)
129 11:07:08.189657 progress 5 % (0 MB)
130 11:07:08.213494 progress 10 % (0 MB)
131 11:07:08.237458 progress 15 % (1 MB)
132 11:07:08.259932 progress 20 % (1 MB)
133 11:07:08.284370 progress 25 % (2 MB)
134 11:07:08.307907 progress 30 % (2 MB)
135 11:07:08.337768 progress 35 % (2 MB)
136 11:07:08.362850 progress 40 % (3 MB)
137 11:07:08.387124 progress 45 % (3 MB)
138 11:07:08.411531 progress 50 % (4 MB)
139 11:07:08.436389 progress 55 % (4 MB)
140 11:07:08.459960 progress 60 % (4 MB)
141 11:07:08.486298 progress 65 % (5 MB)
142 11:07:08.511554 progress 70 % (5 MB)
143 11:07:08.536568 progress 75 % (6 MB)
144 11:07:08.563150 progress 80 % (6 MB)
145 11:07:08.588089 progress 85 % (7 MB)
146 11:07:08.612568 progress 90 % (7 MB)
147 11:07:08.642857 progress 95 % (7 MB)
148 11:07:08.672194 progress 100 % (8 MB)
149 11:07:08.677422 8 MB downloaded in 0.51 s (16.06 MB/s)
150 11:07:08.677682 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:07:08.677946 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:07:08.678039 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 11:07:08.678133 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 11:07:12.160530 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12925646/extract-nfsrootfs-3abnc__8
156 11:07:12.160795 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 11:07:12.160915 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 11:07:12.161096 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7
159 11:07:12.161245 makedir: /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin
160 11:07:12.161364 makedir: /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/tests
161 11:07:12.161480 makedir: /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/results
162 11:07:12.161599 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-add-keys
163 11:07:12.161788 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-add-sources
164 11:07:12.161964 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-background-process-start
165 11:07:12.162141 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-background-process-stop
166 11:07:12.162346 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-common-functions
167 11:07:12.162577 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-echo-ipv4
168 11:07:12.162728 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-install-packages
169 11:07:12.162876 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-installed-packages
170 11:07:12.163021 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-os-build
171 11:07:12.163168 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-probe-channel
172 11:07:12.163314 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-probe-ip
173 11:07:12.163458 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-target-ip
174 11:07:12.163605 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-target-mac
175 11:07:12.163777 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-target-storage
176 11:07:12.163952 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-test-case
177 11:07:12.164124 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-test-event
178 11:07:12.164275 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-test-feedback
179 11:07:12.164449 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-test-raise
180 11:07:12.164623 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-test-reference
181 11:07:12.164834 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-test-runner
182 11:07:12.164979 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-test-set
183 11:07:12.165125 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-test-shell
184 11:07:12.165272 Updating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-add-keys (debian)
185 11:07:12.165444 Updating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-add-sources (debian)
186 11:07:12.165607 Updating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-install-packages (debian)
187 11:07:12.165770 Updating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-installed-packages (debian)
188 11:07:12.165957 Updating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/bin/lava-os-build (debian)
189 11:07:12.166123 Creating /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/environment
190 11:07:12.166260 LAVA metadata
191 11:07:12.166376 - LAVA_JOB_ID=12925646
192 11:07:12.166479 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:07:12.166629 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 11:07:12.166727 skipped lava-vland-overlay
195 11:07:12.166847 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:07:12.166970 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 11:07:12.167067 skipped lava-multinode-overlay
198 11:07:12.167184 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:07:12.167311 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 11:07:12.167424 Loading test definitions
201 11:07:12.167558 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 11:07:12.167668 Using /lava-12925646 at stage 0
203 11:07:12.168058 uuid=12925646_1.6.2.3.1 testdef=None
204 11:07:12.168182 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:07:12.168308 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 11:07:12.169040 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:07:12.169383 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 11:07:12.170169 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:07:12.170548 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 11:07:12.171310 runner path: /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/0/tests/0_timesync-off test_uuid 12925646_1.6.2.3.1
213 11:07:12.171515 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:07:12.171894 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 11:07:12.171978 Using /lava-12925646 at stage 0
217 11:07:12.172105 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:07:12.172230 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/0/tests/1_kselftest-tpm2'
219 11:07:14.798938 Running '/usr/bin/git checkout kernelci.org
220 11:07:14.948198 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 11:07:14.948977 uuid=12925646_1.6.2.3.5 testdef=None
222 11:07:14.949139 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 11:07:14.949389 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 11:07:14.950140 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:07:14.950366 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 11:07:14.951398 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:07:14.951630 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 11:07:14.952575 runner path: /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/0/tests/1_kselftest-tpm2 test_uuid 12925646_1.6.2.3.5
232 11:07:14.952666 BOARD='mt8192-asurada-spherion-r0'
233 11:07:14.952740 BRANCH='cip'
234 11:07:14.952801 SKIPFILE='/dev/null'
235 11:07:14.952858 SKIP_INSTALL='True'
236 11:07:14.952913 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:07:14.952971 TST_CASENAME=''
238 11:07:14.953025 TST_CMDFILES='tpm2'
239 11:07:14.953167 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:07:14.953375 Creating lava-test-runner.conf files
242 11:07:14.953438 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12925646/lava-overlay-n_e2zqn7/lava-12925646/0 for stage 0
243 11:07:14.953532 - 0_timesync-off
244 11:07:14.953601 - 1_kselftest-tpm2
245 11:07:14.953699 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 11:07:14.953787 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 11:07:22.509354 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:07:22.509517 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 11:07:22.509606 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:07:22.509705 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 11:07:22.509796 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 11:07:22.630707 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:07:22.631095 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 11:07:22.631209 extracting modules file /var/lib/lava/dispatcher/tmp/12925646/tftp-deploy-n7u47uue/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925646/extract-nfsrootfs-3abnc__8
255 11:07:22.853281 extracting modules file /var/lib/lava/dispatcher/tmp/12925646/tftp-deploy-n7u47uue/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925646/extract-overlay-ramdisk-i92w0a2h/ramdisk
256 11:07:23.080835 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:07:23.081013 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 11:07:23.081108 [common] Applying overlay to NFS
259 11:07:23.081179 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925646/compress-overlay-6gey5xtn/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12925646/extract-nfsrootfs-3abnc__8
260 11:07:24.009730 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:07:24.009900 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 11:07:24.009996 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:07:24.010083 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 11:07:24.010164 Building ramdisk /var/lib/lava/dispatcher/tmp/12925646/extract-overlay-ramdisk-i92w0a2h/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12925646/extract-overlay-ramdisk-i92w0a2h/ramdisk
265 11:07:24.350534 >> 119441 blocks
266 11:07:26.272939 rename /var/lib/lava/dispatcher/tmp/12925646/extract-overlay-ramdisk-i92w0a2h/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12925646/tftp-deploy-n7u47uue/ramdisk/ramdisk.cpio.gz
267 11:07:26.273401 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:07:26.273526 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 11:07:26.273627 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 11:07:26.273732 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12925646/tftp-deploy-n7u47uue/kernel/Image'
271 11:07:38.690011 Returned 0 in 12 seconds
272 11:07:38.790634 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12925646/tftp-deploy-n7u47uue/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12925646/tftp-deploy-n7u47uue/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12925646/tftp-deploy-n7u47uue/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12925646/tftp-deploy-n7u47uue/kernel/image.itb
273 11:07:39.177294 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:07:39.177685 output: Created: Sun Mar 3 11:07:39 2024
275 11:07:39.177766 output: Image 0 (kernel-1)
276 11:07:39.177839 output: Description:
277 11:07:39.177904 output: Created: Sun Mar 3 11:07:39 2024
278 11:07:39.177965 output: Type: Kernel Image
279 11:07:39.178025 output: Compression: lzma compressed
280 11:07:39.178080 output: Data Size: 12057697 Bytes = 11775.09 KiB = 11.50 MiB
281 11:07:39.178145 output: Architecture: AArch64
282 11:07:39.178201 output: OS: Linux
283 11:07:39.178255 output: Load Address: 0x00000000
284 11:07:39.178309 output: Entry Point: 0x00000000
285 11:07:39.178366 output: Hash algo: crc32
286 11:07:39.178427 output: Hash value: cf43f4f3
287 11:07:39.178483 output: Image 1 (fdt-1)
288 11:07:39.178537 output: Description: mt8192-asurada-spherion-r0
289 11:07:39.178590 output: Created: Sun Mar 3 11:07:39 2024
290 11:07:39.178643 output: Type: Flat Device Tree
291 11:07:39.178696 output: Compression: uncompressed
292 11:07:39.178755 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 11:07:39.178843 output: Architecture: AArch64
294 11:07:39.178927 output: Hash algo: crc32
295 11:07:39.179012 output: Hash value: cc4352de
296 11:07:39.179095 output: Image 2 (ramdisk-1)
297 11:07:39.179151 output: Description: unavailable
298 11:07:39.179205 output: Created: Sun Mar 3 11:07:39 2024
299 11:07:39.179259 output: Type: RAMDisk Image
300 11:07:39.179311 output: Compression: Unknown Compression
301 11:07:39.179371 output: Data Size: 17804281 Bytes = 17386.99 KiB = 16.98 MiB
302 11:07:39.179425 output: Architecture: AArch64
303 11:07:39.179478 output: OS: Linux
304 11:07:39.179530 output: Load Address: unavailable
305 11:07:39.179582 output: Entry Point: unavailable
306 11:07:39.179634 output: Hash algo: crc32
307 11:07:39.179693 output: Hash value: 2ed13602
308 11:07:39.179745 output: Default Configuration: 'conf-1'
309 11:07:39.179797 output: Configuration 0 (conf-1)
310 11:07:39.179850 output: Description: mt8192-asurada-spherion-r0
311 11:07:39.179902 output: Kernel: kernel-1
312 11:07:39.179960 output: Init Ramdisk: ramdisk-1
313 11:07:39.180013 output: FDT: fdt-1
314 11:07:39.180065 output: Loadables: kernel-1
315 11:07:39.180117 output:
316 11:07:39.180329 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 11:07:39.180429 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 11:07:39.180531 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 11:07:39.180628 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 11:07:39.180719 No LXC device requested
321 11:07:39.180832 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:07:39.180928 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 11:07:39.181004 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:07:39.181071 Checking files for TFTP limit of 4294967296 bytes.
325 11:07:39.181590 end: 1 tftp-deploy (duration 00:00:39) [common]
326 11:07:39.181698 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:07:39.181799 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:07:39.181937 substitutions:
329 11:07:39.182010 - {DTB}: 12925646/tftp-deploy-n7u47uue/dtb/mt8192-asurada-spherion-r0.dtb
330 11:07:39.182083 - {INITRD}: 12925646/tftp-deploy-n7u47uue/ramdisk/ramdisk.cpio.gz
331 11:07:39.182144 - {KERNEL}: 12925646/tftp-deploy-n7u47uue/kernel/Image
332 11:07:39.182202 - {LAVA_MAC}: None
333 11:07:39.182259 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12925646/extract-nfsrootfs-3abnc__8
334 11:07:39.182315 - {NFS_SERVER_IP}: 192.168.201.1
335 11:07:39.182370 - {PRESEED_CONFIG}: None
336 11:07:39.182430 - {PRESEED_LOCAL}: None
337 11:07:39.182484 - {RAMDISK}: 12925646/tftp-deploy-n7u47uue/ramdisk/ramdisk.cpio.gz
338 11:07:39.182539 - {ROOT_PART}: None
339 11:07:39.182592 - {ROOT}: None
340 11:07:39.182646 - {SERVER_IP}: 192.168.201.1
341 11:07:39.182705 - {TEE}: None
342 11:07:39.182762 Parsed boot commands:
343 11:07:39.182815 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:07:39.183006 Parsed boot commands: tftpboot 192.168.201.1 12925646/tftp-deploy-n7u47uue/kernel/image.itb 12925646/tftp-deploy-n7u47uue/kernel/cmdline
345 11:07:39.183095 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:07:39.183181 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:07:39.183271 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:07:39.183363 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:07:39.183435 Not connected, no need to disconnect.
350 11:07:39.183509 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:07:39.183591 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:07:39.183678 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 11:07:39.187873 Setting prompt string to ['lava-test: # ']
354 11:07:39.188262 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:07:39.188380 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:07:39.188490 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:07:39.188635 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:07:39.188905 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 11:07:44.327209 >> Command sent successfully.
360 11:07:44.329689 Returned 0 in 5 seconds
361 11:07:44.430080 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:07:44.430439 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:07:44.430546 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:07:44.430639 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:07:44.430707 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:07:44.430775 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:07:44.431057 [Enter `^Ec?' for help]
369 11:07:44.612537
370 11:07:44.612751
371 11:07:44.612826 F0: 102B 0000
372 11:07:44.612899
373 11:07:44.612963 F3: 1001 0000 [0200]
374 11:07:44.613022
375 11:07:44.616471 F3: 1001 0000
376 11:07:44.616560
377 11:07:44.616624 F7: 102D 0000
378 11:07:44.616684
379 11:07:44.616790 F1: 0000 0000
380 11:07:44.620240
381 11:07:44.620347 V0: 0000 0000 [0001]
382 11:07:44.620414
383 11:07:44.620474 00: 0007 8000
384 11:07:44.620546
385 11:07:44.623944 01: 0000 0000
386 11:07:44.624072
387 11:07:44.624169 BP: 0C00 0209 [0000]
388 11:07:44.624270
389 11:07:44.628177 G0: 1182 0000
390 11:07:44.628280
391 11:07:44.628398 EC: 0000 0021 [4000]
392 11:07:44.628490
393 11:07:44.632672 S7: 0000 0000 [0000]
394 11:07:44.632821
395 11:07:44.632917 CC: 0000 0000 [0001]
396 11:07:44.633013
397 11:07:44.633075 T0: 0000 0040 [010F]
398 11:07:44.633137
399 11:07:44.635291 Jump to BL
400 11:07:44.635359
401 11:07:44.659423
402 11:07:44.659578
403 11:07:44.659695
404 11:07:44.666184 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:07:44.669479 ARM64: Exception handlers installed.
406 11:07:44.673139 ARM64: Testing exception
407 11:07:44.676264 ARM64: Done test exception
408 11:07:44.683063 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:07:44.693203 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:07:44.699796 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:07:44.710512 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:07:44.716389 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:07:44.727892 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:07:44.738029 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:07:44.744023 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:07:44.762226 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:07:44.765477 WDT: Last reset was cold boot
418 11:07:44.768802 SPI1(PAD0) initialized at 2873684 Hz
419 11:07:44.772370 SPI5(PAD0) initialized at 992727 Hz
420 11:07:44.776807 VBOOT: Loading verstage.
421 11:07:44.781883 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:07:44.785806 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:07:44.789706 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:07:44.792399 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:07:44.800578 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:07:44.806129 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:07:44.817402 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
428 11:07:44.817482
429 11:07:44.817547
430 11:07:44.827290 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:07:44.830710 ARM64: Exception handlers installed.
432 11:07:44.834592 ARM64: Testing exception
433 11:07:44.834730 ARM64: Done test exception
434 11:07:44.841665 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:07:44.844137 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:07:44.858160 Probing TPM: . done!
437 11:07:44.858244 TPM ready after 0 ms
438 11:07:44.865245 Connected to device vid:did:rid of 1ae0:0028:00
439 11:07:44.871523 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 11:07:44.915695 Initialized TPM device CR50 revision 0
441 11:07:44.925727 tlcl_send_startup: Startup return code is 0
442 11:07:44.925821 TPM: setup succeeded
443 11:07:44.937139 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:07:44.946106 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:07:44.956169 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:07:44.965376 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:07:44.968901 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:07:44.972049 in-header: 03 07 00 00 08 00 00 00
449 11:07:44.975654 in-data: aa e4 47 04 13 02 00 00
450 11:07:44.978716 Chrome EC: UHEPI supported
451 11:07:44.985129 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:07:44.988928 in-header: 03 9d 00 00 08 00 00 00
453 11:07:44.991931 in-data: 10 20 20 08 00 00 00 00
454 11:07:44.992016 Phase 1
455 11:07:44.995061 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:07:45.001664 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:07:45.008473 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:07:45.011826 Recovery requested (1009000e)
459 11:07:45.016628 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:07:45.024889 tlcl_extend: response is 0
461 11:07:45.032224 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:07:45.037882 tlcl_extend: response is 0
463 11:07:45.044191 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:07:45.065079 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
465 11:07:45.072156 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:07:45.072258
467 11:07:45.072337
468 11:07:45.082094 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:07:45.085095 ARM64: Exception handlers installed.
470 11:07:45.088577 ARM64: Testing exception
471 11:07:45.088686 ARM64: Done test exception
472 11:07:45.110823 pmic_efuse_setting: Set efuses in 11 msecs
473 11:07:45.114280 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:07:45.120961 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:07:45.124544 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:07:45.129264 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:07:45.135742 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:07:45.139890 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:07:45.143044 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:07:45.149304 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:07:45.152866 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:07:45.159216 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:07:45.163085 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:07:45.166243 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:07:45.172978 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:07:45.175841 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:07:45.182705 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:07:45.189004 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:07:45.195843 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:07:45.199842 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:07:45.206985 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:07:45.210674 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:07:45.217293 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:07:45.223574 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:07:45.227066 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:07:45.234773 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:07:45.240608 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:07:45.243361 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:07:45.251046 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:07:45.253842 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:07:45.260063 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:07:45.263325 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:07:45.270072 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:07:45.273595 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:07:45.280522 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:07:45.284756 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:07:45.290805 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:07:45.293471 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:07:45.300676 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:07:45.303258 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:07:45.311456 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:07:45.313489 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:07:45.317573 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:07:45.323668 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:07:45.327901 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:07:45.330005 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:07:45.337055 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:07:45.340189 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:07:45.343922 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:07:45.350356 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:07:45.354210 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:07:45.356756 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:07:45.360097 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:07:45.366948 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:07:45.373683 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:07:45.383543 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:07:45.387229 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:07:45.393686 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:07:45.403195 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:07:45.406563 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:07:45.413726 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:07:45.417450 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:07:45.423273 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x7
534 11:07:45.430322 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:07:45.433835 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 11:07:45.436632 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:07:45.447600 [RTC]rtc_get_frequency_meter,154: input=15, output=764
538 11:07:45.457455 [RTC]rtc_get_frequency_meter,154: input=23, output=949
539 11:07:45.467852 [RTC]rtc_get_frequency_meter,154: input=19, output=856
540 11:07:45.478497 [RTC]rtc_get_frequency_meter,154: input=17, output=810
541 11:07:45.485695 [RTC]rtc_get_frequency_meter,154: input=16, output=787
542 11:07:45.495378 [RTC]rtc_get_frequency_meter,154: input=16, output=787
543 11:07:45.504671 [RTC]rtc_get_frequency_meter,154: input=17, output=810
544 11:07:45.508534 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 11:07:45.515865 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 11:07:45.518878 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:07:45.522137 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 11:07:45.528506 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:07:45.532671 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 11:07:45.535659 ADC[4]: Raw value=670432 ID=5
551 11:07:45.535735 ADC[3]: Raw value=212917 ID=1
552 11:07:45.539062 RAM Code: 0x51
553 11:07:45.542450 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:07:45.549292 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:07:45.555426 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 11:07:45.562015 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 11:07:45.565998 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:07:45.568781 in-header: 03 07 00 00 08 00 00 00
559 11:07:45.572161 in-data: aa e4 47 04 13 02 00 00
560 11:07:45.575063 Chrome EC: UHEPI supported
561 11:07:45.581699 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:07:45.586258 in-header: 03 d5 00 00 08 00 00 00
563 11:07:45.589040 in-data: 98 20 60 08 00 00 00 00
564 11:07:45.591626 MRC: failed to locate region type 0.
565 11:07:45.598161 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:07:45.602445 DRAM-K: Running full calibration
567 11:07:45.605506 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 11:07:45.608344 header.status = 0x0
569 11:07:45.611656 header.version = 0x6 (expected: 0x6)
570 11:07:45.614848 header.size = 0xd00 (expected: 0xd00)
571 11:07:45.614926 header.flags = 0x0
572 11:07:45.621538 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:07:45.640656 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
574 11:07:45.647233 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:07:45.650949 dram_init: ddr_geometry: 0
576 11:07:45.653945 [EMI] MDL number = 0
577 11:07:45.654028 [EMI] Get MDL freq = 0
578 11:07:45.657322 dram_init: ddr_type: 0
579 11:07:45.657404 is_discrete_lpddr4: 1
580 11:07:45.661136 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:07:45.661219
582 11:07:45.661284
583 11:07:45.665355 [Bian_co] ETT version 0.0.0.1
584 11:07:45.669166 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 11:07:45.669250
586 11:07:45.671473 dramc_set_vcore_voltage set vcore to 650000
587 11:07:45.674801 Read voltage for 800, 4
588 11:07:45.674884 Vio18 = 0
589 11:07:45.678260 Vcore = 650000
590 11:07:45.678342 Vdram = 0
591 11:07:45.678409 Vddq = 0
592 11:07:45.682716 Vmddr = 0
593 11:07:45.682799 dram_init: config_dvfs: 1
594 11:07:45.689011 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:07:45.695362 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:07:45.698666 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 11:07:45.701635 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 11:07:45.704907 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 11:07:45.708191 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 11:07:45.711836 MEM_TYPE=3, freq_sel=18
601 11:07:45.714975 sv_algorithm_assistance_LP4_1600
602 11:07:45.718202 ============ PULL DRAM RESETB DOWN ============
603 11:07:45.721396 ========== PULL DRAM RESETB DOWN end =========
604 11:07:45.728637 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:07:45.731721 ===================================
606 11:07:45.731800 LPDDR4 DRAM CONFIGURATION
607 11:07:45.735229 ===================================
608 11:07:45.738759 EX_ROW_EN[0] = 0x0
609 11:07:45.738842 EX_ROW_EN[1] = 0x0
610 11:07:45.741385 LP4Y_EN = 0x0
611 11:07:45.741469 WORK_FSP = 0x0
612 11:07:45.745276 WL = 0x2
613 11:07:45.745359 RL = 0x2
614 11:07:45.748188 BL = 0x2
615 11:07:45.751327 RPST = 0x0
616 11:07:45.751411 RD_PRE = 0x0
617 11:07:45.754913 WR_PRE = 0x1
618 11:07:45.754996 WR_PST = 0x0
619 11:07:45.758171 DBI_WR = 0x0
620 11:07:45.758254 DBI_RD = 0x0
621 11:07:45.761891 OTF = 0x1
622 11:07:45.764694 ===================================
623 11:07:45.767855 ===================================
624 11:07:45.767939 ANA top config
625 11:07:45.771186 ===================================
626 11:07:45.774852 DLL_ASYNC_EN = 0
627 11:07:45.778019 ALL_SLAVE_EN = 1
628 11:07:45.778102 NEW_RANK_MODE = 1
629 11:07:45.781264 DLL_IDLE_MODE = 1
630 11:07:45.784558 LP45_APHY_COMB_EN = 1
631 11:07:45.788891 TX_ODT_DIS = 1
632 11:07:45.788975 NEW_8X_MODE = 1
633 11:07:45.791285 ===================================
634 11:07:45.794924 ===================================
635 11:07:45.797873 data_rate = 1600
636 11:07:45.801069 CKR = 1
637 11:07:45.804689 DQ_P2S_RATIO = 8
638 11:07:45.808145 ===================================
639 11:07:45.811872 CA_P2S_RATIO = 8
640 11:07:45.814519 DQ_CA_OPEN = 0
641 11:07:45.814602 DQ_SEMI_OPEN = 0
642 11:07:45.817622 CA_SEMI_OPEN = 0
643 11:07:45.821389 CA_FULL_RATE = 0
644 11:07:45.824802 DQ_CKDIV4_EN = 1
645 11:07:45.828329 CA_CKDIV4_EN = 1
646 11:07:45.830979 CA_PREDIV_EN = 0
647 11:07:45.831062 PH8_DLY = 0
648 11:07:45.834679 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:07:45.837434 DQ_AAMCK_DIV = 4
650 11:07:45.840830 CA_AAMCK_DIV = 4
651 11:07:45.844423 CA_ADMCK_DIV = 4
652 11:07:45.847728 DQ_TRACK_CA_EN = 0
653 11:07:45.847811 CA_PICK = 800
654 11:07:45.851348 CA_MCKIO = 800
655 11:07:45.854352 MCKIO_SEMI = 0
656 11:07:45.857648 PLL_FREQ = 3068
657 11:07:45.860951 DQ_UI_PI_RATIO = 32
658 11:07:45.864248 CA_UI_PI_RATIO = 0
659 11:07:45.867960 ===================================
660 11:07:45.870952 ===================================
661 11:07:45.875541 memory_type:LPDDR4
662 11:07:45.875625 GP_NUM : 10
663 11:07:45.877652 SRAM_EN : 1
664 11:07:45.877736 MD32_EN : 0
665 11:07:45.881007 ===================================
666 11:07:45.884715 [ANA_INIT] >>>>>>>>>>>>>>
667 11:07:45.887314 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:07:45.890766 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:07:45.894353 ===================================
670 11:07:45.899110 data_rate = 1600,PCW = 0X7600
671 11:07:45.900754 ===================================
672 11:07:45.904213 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:07:45.907600 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:07:45.914159 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:07:45.918358 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:07:45.921135 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:07:45.927860 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:07:45.927944 [ANA_INIT] flow start
679 11:07:45.930712 [ANA_INIT] PLL >>>>>>>>
680 11:07:45.930795 [ANA_INIT] PLL <<<<<<<<
681 11:07:45.934225 [ANA_INIT] MIDPI >>>>>>>>
682 11:07:45.937460 [ANA_INIT] MIDPI <<<<<<<<
683 11:07:45.940934 [ANA_INIT] DLL >>>>>>>>
684 11:07:45.941018 [ANA_INIT] flow end
685 11:07:45.944333 ============ LP4 DIFF to SE enter ============
686 11:07:45.951243 ============ LP4 DIFF to SE exit ============
687 11:07:45.951327 [ANA_INIT] <<<<<<<<<<<<<
688 11:07:45.954040 [Flow] Enable top DCM control >>>>>
689 11:07:45.957370 [Flow] Enable top DCM control <<<<<
690 11:07:45.960742 Enable DLL master slave shuffle
691 11:07:45.967450 ==============================================================
692 11:07:45.967533 Gating Mode config
693 11:07:45.974881 ==============================================================
694 11:07:45.977108 Config description:
695 11:07:45.987507 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:07:45.994144 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:07:45.998443 SELPH_MODE 0: By rank 1: By Phase
698 11:07:46.003581 ==============================================================
699 11:07:46.007016 GAT_TRACK_EN = 1
700 11:07:46.010295 RX_GATING_MODE = 2
701 11:07:46.010378 RX_GATING_TRACK_MODE = 2
702 11:07:46.013901 SELPH_MODE = 1
703 11:07:46.017006 PICG_EARLY_EN = 1
704 11:07:46.020491 VALID_LAT_VALUE = 1
705 11:07:46.027106 ==============================================================
706 11:07:46.030155 Enter into Gating configuration >>>>
707 11:07:46.034261 Exit from Gating configuration <<<<
708 11:07:46.037349 Enter into DVFS_PRE_config >>>>>
709 11:07:46.047241 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:07:46.050617 Exit from DVFS_PRE_config <<<<<
711 11:07:46.053620 Enter into PICG configuration >>>>
712 11:07:46.057578 Exit from PICG configuration <<<<
713 11:07:46.060445 [RX_INPUT] configuration >>>>>
714 11:07:46.063454 [RX_INPUT] configuration <<<<<
715 11:07:46.068330 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:07:46.073326 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:07:46.080349 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:07:46.086688 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:07:46.090285 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:07:46.097000 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:07:46.100159 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:07:46.106951 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:07:46.110413 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:07:46.113225 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:07:46.117153 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:07:46.123525 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:07:46.126934 ===================================
728 11:07:46.127018 LPDDR4 DRAM CONFIGURATION
729 11:07:46.130000 ===================================
730 11:07:46.133341 EX_ROW_EN[0] = 0x0
731 11:07:46.136441 EX_ROW_EN[1] = 0x0
732 11:07:46.136524 LP4Y_EN = 0x0
733 11:07:46.139877 WORK_FSP = 0x0
734 11:07:46.139960 WL = 0x2
735 11:07:46.143712 RL = 0x2
736 11:07:46.143795 BL = 0x2
737 11:07:46.146286 RPST = 0x0
738 11:07:46.146385 RD_PRE = 0x0
739 11:07:46.150642 WR_PRE = 0x1
740 11:07:46.150724 WR_PST = 0x0
741 11:07:46.153099 DBI_WR = 0x0
742 11:07:46.153183 DBI_RD = 0x0
743 11:07:46.156481 OTF = 0x1
744 11:07:46.160457 ===================================
745 11:07:46.163653 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:07:46.166395 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:07:46.173654 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:07:46.176942 ===================================
749 11:07:46.177025 LPDDR4 DRAM CONFIGURATION
750 11:07:46.179591 ===================================
751 11:07:46.183426 EX_ROW_EN[0] = 0x10
752 11:07:46.186567 EX_ROW_EN[1] = 0x0
753 11:07:46.186650 LP4Y_EN = 0x0
754 11:07:46.190273 WORK_FSP = 0x0
755 11:07:46.190356 WL = 0x2
756 11:07:46.193063 RL = 0x2
757 11:07:46.193146 BL = 0x2
758 11:07:46.196669 RPST = 0x0
759 11:07:46.196774 RD_PRE = 0x0
760 11:07:46.199886 WR_PRE = 0x1
761 11:07:46.199973 WR_PST = 0x0
762 11:07:46.203508 DBI_WR = 0x0
763 11:07:46.203591 DBI_RD = 0x0
764 11:07:46.206826 OTF = 0x1
765 11:07:46.210023 ===================================
766 11:07:46.216972 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:07:46.219884 nWR fixed to 40
768 11:07:46.219969 [ModeRegInit_LP4] CH0 RK0
769 11:07:46.223073 [ModeRegInit_LP4] CH0 RK1
770 11:07:46.226401 [ModeRegInit_LP4] CH1 RK0
771 11:07:46.226484 [ModeRegInit_LP4] CH1 RK1
772 11:07:46.229840 match AC timing 12
773 11:07:46.233088 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 11:07:46.236771 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:07:46.243111 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:07:46.246599 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:07:46.253269 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:07:46.253352 [EMI DOE] emi_dcm 0
779 11:07:46.256834 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:07:46.259898 ==
781 11:07:46.262817 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:07:46.266296 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 11:07:46.266379 ==
784 11:07:46.270027 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:07:46.276294 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:07:46.286487 [CA 0] Center 37 (7~68) winsize 62
787 11:07:46.289891 [CA 1] Center 37 (7~68) winsize 62
788 11:07:46.293034 [CA 2] Center 35 (5~66) winsize 62
789 11:07:46.297271 [CA 3] Center 35 (5~66) winsize 62
790 11:07:46.299771 [CA 4] Center 34 (3~65) winsize 63
791 11:07:46.302744 [CA 5] Center 34 (3~65) winsize 63
792 11:07:46.302828
793 11:07:46.306103 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 11:07:46.306186
795 11:07:46.309479 [CATrainingPosCal] consider 1 rank data
796 11:07:46.312672 u2DelayCellTimex100 = 270/100 ps
797 11:07:46.316257 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
798 11:07:46.321068 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
799 11:07:46.326224 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
800 11:07:46.329277 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
801 11:07:46.332825 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
802 11:07:46.336090 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
803 11:07:46.336173
804 11:07:46.339318 CA PerBit enable=1, Macro0, CA PI delay=34
805 11:07:46.339401
806 11:07:46.342861 [CBTSetCACLKResult] CA Dly = 34
807 11:07:46.342945 CS Dly: 6 (0~37)
808 11:07:46.346364 ==
809 11:07:46.346447 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:07:46.352924 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 11:07:46.353007 ==
812 11:07:46.356066 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:07:46.362719 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:07:46.371939 [CA 0] Center 37 (7~68) winsize 62
815 11:07:46.376077 [CA 1] Center 37 (7~68) winsize 62
816 11:07:46.378664 [CA 2] Center 35 (5~66) winsize 62
817 11:07:46.382195 [CA 3] Center 35 (4~66) winsize 63
818 11:07:46.385503 [CA 4] Center 33 (3~64) winsize 62
819 11:07:46.388927 [CA 5] Center 34 (3~65) winsize 63
820 11:07:46.389010
821 11:07:46.391961 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 11:07:46.392044
823 11:07:46.395382 [CATrainingPosCal] consider 2 rank data
824 11:07:46.398373 u2DelayCellTimex100 = 270/100 ps
825 11:07:46.401756 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 11:07:46.409251 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 11:07:46.412534 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 11:07:46.415299 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
829 11:07:46.418248 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 11:07:46.422139 CA5 delay=34 (3~65),Diff = 1 PI (7 cell)
831 11:07:46.422222
832 11:07:46.425322 CA PerBit enable=1, Macro0, CA PI delay=33
833 11:07:46.425406
834 11:07:46.428441 [CBTSetCACLKResult] CA Dly = 33
835 11:07:46.428564 CS Dly: 6 (0~37)
836 11:07:46.432281
837 11:07:46.435240 ----->DramcWriteLeveling(PI) begin...
838 11:07:46.435325 ==
839 11:07:46.438240 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:07:46.442402 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 11:07:46.442486 ==
842 11:07:46.445132 Write leveling (Byte 0): 28 => 28
843 11:07:46.448673 Write leveling (Byte 1): 27 => 27
844 11:07:46.451998 DramcWriteLeveling(PI) end<-----
845 11:07:46.452081
846 11:07:46.452147 ==
847 11:07:46.455226 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:07:46.458375 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 11:07:46.458458 ==
850 11:07:46.461592 [Gating] SW mode calibration
851 11:07:46.468871 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:07:46.475573 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:07:46.478169 0 6 0 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
854 11:07:46.481602 0 6 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
855 11:07:46.488736 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:07:46.491985 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:07:46.495302 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:07:46.499049 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:07:46.505277 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:07:46.508513 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:07:46.511921 0 7 0 | B1->B0 | 2b2b 2928 | 0 1 | (0 0) (0 0)
862 11:07:46.518385 0 7 4 | B1->B0 | 3a3a 4242 | 0 0 | (0 0) (0 0)
863 11:07:46.522255 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 11:07:46.525947 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 11:07:46.531855 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 11:07:46.535239 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 11:07:46.539033 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 11:07:46.545102 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 11:07:46.548674 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 11:07:46.551741 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 11:07:46.559083 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 11:07:46.561687 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 11:07:46.564623 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 11:07:46.571672 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 11:07:46.575424 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 11:07:46.579048 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 11:07:46.585766 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 11:07:46.588185 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 11:07:46.591867 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 11:07:46.596918 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 11:07:46.601511 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 11:07:46.605676 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 11:07:46.607942 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 11:07:46.615104 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 11:07:46.619475 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
886 11:07:46.621896 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 11:07:46.624607 Total UI for P1: 0, mck2ui 16
888 11:07:46.628082 best dqsien dly found for B0: ( 0, 10, 0)
889 11:07:46.632097 Total UI for P1: 0, mck2ui 16
890 11:07:46.635645 best dqsien dly found for B1: ( 0, 10, 2)
891 11:07:46.638035 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
892 11:07:46.642136 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
893 11:07:46.642219
894 11:07:46.648138 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
895 11:07:46.651130 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
896 11:07:46.655249 [Gating] SW calibration Done
897 11:07:46.655331 ==
898 11:07:46.658643 Dram Type= 6, Freq= 0, CH_0, rank 0
899 11:07:46.662703 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 11:07:46.662787 ==
901 11:07:46.662854 RX Vref Scan: 0
902 11:07:46.662915
903 11:07:46.665617 RX Vref 0 -> 0, step: 1
904 11:07:46.665700
905 11:07:46.668665 RX Delay -130 -> 252, step: 16
906 11:07:46.672374 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
907 11:07:46.675486 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 11:07:46.680182 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
909 11:07:46.685229 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 11:07:46.688667 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 11:07:46.692015 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
912 11:07:46.695673 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 11:07:46.699132 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
914 11:07:46.705155 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
915 11:07:46.708590 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
916 11:07:46.711748 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
917 11:07:46.715344 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 11:07:46.719446 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 11:07:46.725350 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
920 11:07:46.728556 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 11:07:46.732688 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 11:07:46.732809 ==
923 11:07:46.736253 Dram Type= 6, Freq= 0, CH_0, rank 0
924 11:07:46.738454 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 11:07:46.738537 ==
926 11:07:46.742623 DQS Delay:
927 11:07:46.742706 DQS0 = 0, DQS1 = 0
928 11:07:46.745844 DQM Delay:
929 11:07:46.745927 DQM0 = 82, DQM1 = 74
930 11:07:46.745993 DQ Delay:
931 11:07:46.749090 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
932 11:07:46.752248 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
933 11:07:46.755455 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
934 11:07:46.758602 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
935 11:07:46.758685
936 11:07:46.758751
937 11:07:46.758811 ==
938 11:07:46.762648 Dram Type= 6, Freq= 0, CH_0, rank 0
939 11:07:46.768634 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 11:07:46.768761 ==
941 11:07:46.768836
942 11:07:46.768899
943 11:07:46.771742 TX Vref Scan disable
944 11:07:46.771824 == TX Byte 0 ==
945 11:07:46.775002 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
946 11:07:46.782097 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
947 11:07:46.782183 == TX Byte 1 ==
948 11:07:46.785091 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
949 11:07:46.791819 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
950 11:07:46.791902 ==
951 11:07:46.795131 Dram Type= 6, Freq= 0, CH_0, rank 0
952 11:07:46.798792 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 11:07:46.798875 ==
954 11:07:46.811265 TX Vref=22, minBit 0, minWin=27, winSum=442
955 11:07:46.815736 TX Vref=24, minBit 0, minWin=27, winSum=442
956 11:07:46.818421 TX Vref=26, minBit 11, minWin=27, winSum=448
957 11:07:46.821434 TX Vref=28, minBit 0, minWin=27, winSum=448
958 11:07:46.825065 TX Vref=30, minBit 0, minWin=28, winSum=452
959 11:07:46.831486 TX Vref=32, minBit 0, minWin=28, winSum=453
960 11:07:46.834670 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 32
961 11:07:46.834765
962 11:07:46.838470 Final TX Range 1 Vref 32
963 11:07:46.838552
964 11:07:46.838617 ==
965 11:07:46.841579 Dram Type= 6, Freq= 0, CH_0, rank 0
966 11:07:46.844593 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 11:07:46.844675 ==
968 11:07:46.844751
969 11:07:46.847892
970 11:07:46.847973 TX Vref Scan disable
971 11:07:46.851936 == TX Byte 0 ==
972 11:07:46.854550 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
973 11:07:46.858547 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
974 11:07:46.861628 == TX Byte 1 ==
975 11:07:46.864735 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
976 11:07:46.868234 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
977 11:07:46.871094
978 11:07:46.871176 [DATLAT]
979 11:07:46.871243 Freq=800, CH0 RK0
980 11:07:46.871306
981 11:07:46.874751 DATLAT Default: 0xa
982 11:07:46.874833 0, 0xFFFF, sum = 0
983 11:07:46.878662 1, 0xFFFF, sum = 0
984 11:07:46.878749 2, 0xFFFF, sum = 0
985 11:07:46.881415 3, 0xFFFF, sum = 0
986 11:07:46.881500 4, 0xFFFF, sum = 0
987 11:07:46.884597 5, 0xFFFF, sum = 0
988 11:07:46.888177 6, 0xFFFF, sum = 0
989 11:07:46.888261 7, 0xFFFF, sum = 0
990 11:07:46.888329 8, 0x0, sum = 1
991 11:07:46.891872 9, 0x0, sum = 2
992 11:07:46.891956 10, 0x0, sum = 3
993 11:07:46.895003 11, 0x0, sum = 4
994 11:07:46.895086 best_step = 9
995 11:07:46.895153
996 11:07:46.895214 ==
997 11:07:46.898045 Dram Type= 6, Freq= 0, CH_0, rank 0
998 11:07:46.905653 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 11:07:46.905735 ==
1000 11:07:46.905802 RX Vref Scan: 1
1001 11:07:46.905863
1002 11:07:46.907903 Set Vref Range= 32 -> 127
1003 11:07:46.907985
1004 11:07:46.911250 RX Vref 32 -> 127, step: 1
1005 11:07:46.911332
1006 11:07:46.911398 RX Delay -111 -> 252, step: 8
1007 11:07:46.914543
1008 11:07:46.914625 Set Vref, RX VrefLevel [Byte0]: 32
1009 11:07:46.917756 [Byte1]: 32
1010 11:07:46.922249
1011 11:07:46.922359 Set Vref, RX VrefLevel [Byte0]: 33
1012 11:07:46.925586 [Byte1]: 33
1013 11:07:46.930167
1014 11:07:46.930249 Set Vref, RX VrefLevel [Byte0]: 34
1015 11:07:46.933960 [Byte1]: 34
1016 11:07:46.937326
1017 11:07:46.937408 Set Vref, RX VrefLevel [Byte0]: 35
1018 11:07:46.940985 [Byte1]: 35
1019 11:07:46.945481
1020 11:07:46.945563 Set Vref, RX VrefLevel [Byte0]: 36
1021 11:07:46.948912 [Byte1]: 36
1022 11:07:46.953357
1023 11:07:46.953439 Set Vref, RX VrefLevel [Byte0]: 37
1024 11:07:46.956780 [Byte1]: 37
1025 11:07:46.960381
1026 11:07:46.960462 Set Vref, RX VrefLevel [Byte0]: 38
1027 11:07:46.963882 [Byte1]: 38
1028 11:07:46.968366
1029 11:07:46.968446 Set Vref, RX VrefLevel [Byte0]: 39
1030 11:07:46.971901 [Byte1]: 39
1031 11:07:46.976023
1032 11:07:46.976131 Set Vref, RX VrefLevel [Byte0]: 40
1033 11:07:46.978888 [Byte1]: 40
1034 11:07:46.983442
1035 11:07:46.983523 Set Vref, RX VrefLevel [Byte0]: 41
1036 11:07:46.986964 [Byte1]: 41
1037 11:07:46.991269
1038 11:07:46.991351 Set Vref, RX VrefLevel [Byte0]: 42
1039 11:07:46.994523 [Byte1]: 42
1040 11:07:46.999260
1041 11:07:46.999340 Set Vref, RX VrefLevel [Byte0]: 43
1042 11:07:47.002884 [Byte1]: 43
1043 11:07:47.006526
1044 11:07:47.006607 Set Vref, RX VrefLevel [Byte0]: 44
1045 11:07:47.010256 [Byte1]: 44
1046 11:07:47.015029
1047 11:07:47.015110 Set Vref, RX VrefLevel [Byte0]: 45
1048 11:07:47.018260 [Byte1]: 45
1049 11:07:47.021979
1050 11:07:47.022059 Set Vref, RX VrefLevel [Byte0]: 46
1051 11:07:47.025050 [Byte1]: 46
1052 11:07:47.029836
1053 11:07:47.029917 Set Vref, RX VrefLevel [Byte0]: 47
1054 11:07:47.032456 [Byte1]: 47
1055 11:07:47.037117
1056 11:07:47.037198 Set Vref, RX VrefLevel [Byte0]: 48
1057 11:07:47.040614 [Byte1]: 48
1058 11:07:47.044836
1059 11:07:47.044917 Set Vref, RX VrefLevel [Byte0]: 49
1060 11:07:47.047748 [Byte1]: 49
1061 11:07:47.052350
1062 11:07:47.052432 Set Vref, RX VrefLevel [Byte0]: 50
1063 11:07:47.055410 [Byte1]: 50
1064 11:07:47.060325
1065 11:07:47.063893 Set Vref, RX VrefLevel [Byte0]: 51
1066 11:07:47.063975 [Byte1]: 51
1067 11:07:47.068427
1068 11:07:47.068509 Set Vref, RX VrefLevel [Byte0]: 52
1069 11:07:47.070638 [Byte1]: 52
1070 11:07:47.076830
1071 11:07:47.076911 Set Vref, RX VrefLevel [Byte0]: 53
1072 11:07:47.078758 [Byte1]: 53
1073 11:07:47.083033
1074 11:07:47.083124 Set Vref, RX VrefLevel [Byte0]: 54
1075 11:07:47.086282 [Byte1]: 54
1076 11:07:47.090792
1077 11:07:47.090873 Set Vref, RX VrefLevel [Byte0]: 55
1078 11:07:47.093910 [Byte1]: 55
1079 11:07:47.098110
1080 11:07:47.098192 Set Vref, RX VrefLevel [Byte0]: 56
1081 11:07:47.101286 [Byte1]: 56
1082 11:07:47.105798
1083 11:07:47.105879 Set Vref, RX VrefLevel [Byte0]: 57
1084 11:07:47.109071 [Byte1]: 57
1085 11:07:47.113698
1086 11:07:47.113779 Set Vref, RX VrefLevel [Byte0]: 58
1087 11:07:47.116617 [Byte1]: 58
1088 11:07:47.121054
1089 11:07:47.121135 Set Vref, RX VrefLevel [Byte0]: 59
1090 11:07:47.124390 [Byte1]: 59
1091 11:07:47.128601
1092 11:07:47.128715 Set Vref, RX VrefLevel [Byte0]: 60
1093 11:07:47.132982 [Byte1]: 60
1094 11:07:47.136332
1095 11:07:47.136412 Set Vref, RX VrefLevel [Byte0]: 61
1096 11:07:47.140118 [Byte1]: 61
1097 11:07:47.144020
1098 11:07:47.144101 Set Vref, RX VrefLevel [Byte0]: 62
1099 11:07:47.147301 [Byte1]: 62
1100 11:07:47.151866
1101 11:07:47.151947 Set Vref, RX VrefLevel [Byte0]: 63
1102 11:07:47.155131 [Byte1]: 63
1103 11:07:47.159483
1104 11:07:47.159564 Set Vref, RX VrefLevel [Byte0]: 64
1105 11:07:47.163741 [Byte1]: 64
1106 11:07:47.167291
1107 11:07:47.167381 Set Vref, RX VrefLevel [Byte0]: 65
1108 11:07:47.170241 [Byte1]: 65
1109 11:07:47.174877
1110 11:07:47.174958 Set Vref, RX VrefLevel [Byte0]: 66
1111 11:07:47.178247 [Byte1]: 66
1112 11:07:47.182723
1113 11:07:47.182805 Set Vref, RX VrefLevel [Byte0]: 67
1114 11:07:47.185410 [Byte1]: 67
1115 11:07:47.189895
1116 11:07:47.189976 Set Vref, RX VrefLevel [Byte0]: 68
1117 11:07:47.193266 [Byte1]: 68
1118 11:07:47.197810
1119 11:07:47.197891 Set Vref, RX VrefLevel [Byte0]: 69
1120 11:07:47.201116 [Byte1]: 69
1121 11:07:47.205303
1122 11:07:47.205383 Set Vref, RX VrefLevel [Byte0]: 70
1123 11:07:47.208503 [Byte1]: 70
1124 11:07:47.212998
1125 11:07:47.213079 Set Vref, RX VrefLevel [Byte0]: 71
1126 11:07:47.215958 [Byte1]: 71
1127 11:07:47.220469
1128 11:07:47.220551 Set Vref, RX VrefLevel [Byte0]: 72
1129 11:07:47.223881 [Byte1]: 72
1130 11:07:47.228384
1131 11:07:47.228465 Set Vref, RX VrefLevel [Byte0]: 73
1132 11:07:47.231469 [Byte1]: 73
1133 11:07:47.235836
1134 11:07:47.235917 Set Vref, RX VrefLevel [Byte0]: 74
1135 11:07:47.240135 [Byte1]: 74
1136 11:07:47.243555
1137 11:07:47.243636 Set Vref, RX VrefLevel [Byte0]: 75
1138 11:07:47.247449 [Byte1]: 75
1139 11:07:47.251178
1140 11:07:47.251259 Set Vref, RX VrefLevel [Byte0]: 76
1141 11:07:47.254895 [Byte1]: 76
1142 11:07:47.258480
1143 11:07:47.258561 Set Vref, RX VrefLevel [Byte0]: 77
1144 11:07:47.261918 [Byte1]: 77
1145 11:07:47.266235
1146 11:07:47.266316 Final RX Vref Byte 0 = 53 to rank0
1147 11:07:47.269656 Final RX Vref Byte 1 = 55 to rank0
1148 11:07:47.272695 Final RX Vref Byte 0 = 53 to rank1
1149 11:07:47.276348 Final RX Vref Byte 1 = 55 to rank1==
1150 11:07:47.280162 Dram Type= 6, Freq= 0, CH_0, rank 0
1151 11:07:47.286593 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1152 11:07:47.286674 ==
1153 11:07:47.286739 DQS Delay:
1154 11:07:47.286799 DQS0 = 0, DQS1 = 0
1155 11:07:47.290219 DQM Delay:
1156 11:07:47.290299 DQM0 = 83, DQM1 = 73
1157 11:07:47.292868 DQ Delay:
1158 11:07:47.296623 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1159 11:07:47.300469 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1160 11:07:47.300550 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1161 11:07:47.305995 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1162 11:07:47.306075
1163 11:07:47.306140
1164 11:07:47.313850 [DQSOSCAuto] RK0, (LSB)MR18= 0x3434, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1165 11:07:47.316035 CH0 RK0: MR19=606, MR18=3434
1166 11:07:47.323399 CH0_RK0: MR19=0x606, MR18=0x3434, DQSOSC=396, MR23=63, INC=94, DEC=62
1167 11:07:47.323481
1168 11:07:47.326271 ----->DramcWriteLeveling(PI) begin...
1169 11:07:47.326353 ==
1170 11:07:47.329826 Dram Type= 6, Freq= 0, CH_0, rank 1
1171 11:07:47.333134 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1172 11:07:47.333215 ==
1173 11:07:47.336904 Write leveling (Byte 0): 28 => 28
1174 11:07:47.339674 Write leveling (Byte 1): 27 => 27
1175 11:07:47.342813 DramcWriteLeveling(PI) end<-----
1176 11:07:47.342893
1177 11:07:47.342958 ==
1178 11:07:47.346210 Dram Type= 6, Freq= 0, CH_0, rank 1
1179 11:07:47.349408 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1180 11:07:47.349489 ==
1181 11:07:47.352678 [Gating] SW mode calibration
1182 11:07:47.360214 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1183 11:07:47.365999 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1184 11:07:47.369392 0 6 0 | B1->B0 | 3333 3030 | 0 1 | (0 1) (1 0)
1185 11:07:47.372656 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 11:07:47.379627 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 11:07:47.382686 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 11:07:47.385763 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 11:07:47.392851 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 11:07:47.395816 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:07:47.399174 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:07:47.406526 0 7 0 | B1->B0 | 2a2a 3030 | 0 1 | (0 0) (0 0)
1193 11:07:47.409838 0 7 4 | B1->B0 | 4040 4040 | 1 0 | (0 0) (0 0)
1194 11:07:47.412677 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 11:07:47.419113 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 11:07:47.422949 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 11:07:47.426310 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 11:07:47.433071 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 11:07:47.436049 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 11:07:47.439710 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 11:07:47.446254 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1202 11:07:47.449761 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 11:07:47.453062 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:07:47.456419 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:07:47.463775 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 11:07:47.466149 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:07:47.469522 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:07:47.476062 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:07:47.479960 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:07:47.482905 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:07:47.489350 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:07:47.492386 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:07:47.495869 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:07:47.502859 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:07:47.506168 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:07:47.510020 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1217 11:07:47.515915 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1218 11:07:47.515997 Total UI for P1: 0, mck2ui 16
1219 11:07:47.523065 best dqsien dly found for B0: ( 0, 10, 0)
1220 11:07:47.526353 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 11:07:47.529575 Total UI for P1: 0, mck2ui 16
1222 11:07:47.532824 best dqsien dly found for B1: ( 0, 10, 2)
1223 11:07:47.536032 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1224 11:07:47.580272 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1225 11:07:47.580376
1226 11:07:47.580744 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1227 11:07:47.580846 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1228 11:07:47.581257 [Gating] SW calibration Done
1229 11:07:47.581368 ==
1230 11:07:47.581450 Dram Type= 6, Freq= 0, CH_0, rank 1
1231 11:07:47.581721 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1232 11:07:47.581827 ==
1233 11:07:47.581907 RX Vref Scan: 0
1234 11:07:47.582028
1235 11:07:47.582125 RX Vref 0 -> 0, step: 1
1236 11:07:47.582214
1237 11:07:47.582317 RX Delay -130 -> 252, step: 16
1238 11:07:47.582412 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1239 11:07:47.583015 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1240 11:07:47.583138 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1241 11:07:47.583424 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1242 11:07:47.610658 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1243 11:07:47.611587 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1244 11:07:47.611810 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1245 11:07:47.612377 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1246 11:07:47.612622 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1247 11:07:47.613127 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1248 11:07:47.613330 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1249 11:07:47.615840 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1250 11:07:47.620073 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1251 11:07:47.620371 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1252 11:07:47.626124 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1253 11:07:47.629737 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1254 11:07:47.630161 ==
1255 11:07:47.632905 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 11:07:47.635765 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1257 11:07:47.636188 ==
1258 11:07:47.639506 DQS Delay:
1259 11:07:47.639924 DQS0 = 0, DQS1 = 0
1260 11:07:47.640262 DQM Delay:
1261 11:07:47.642694 DQM0 = 81, DQM1 = 73
1262 11:07:47.643113 DQ Delay:
1263 11:07:47.645895 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =69
1264 11:07:47.649418 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1265 11:07:47.652419 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1266 11:07:47.656207 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1267 11:07:47.656626
1268 11:07:47.657023
1269 11:07:47.657337 ==
1270 11:07:47.659394 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 11:07:47.662418 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1272 11:07:47.666512 ==
1273 11:07:47.666928
1274 11:07:47.667259
1275 11:07:47.667571 TX Vref Scan disable
1276 11:07:47.669874 == TX Byte 0 ==
1277 11:07:47.672598 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1278 11:07:47.675771 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1279 11:07:47.679140 == TX Byte 1 ==
1280 11:07:47.682300 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1281 11:07:47.685503 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1282 11:07:47.689162 ==
1283 11:07:47.692414 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 11:07:47.695796 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1285 11:07:47.696219 ==
1286 11:07:47.708308 TX Vref=22, minBit 0, minWin=27, winSum=445
1287 11:07:47.711982 TX Vref=24, minBit 0, minWin=27, winSum=448
1288 11:07:47.715167 TX Vref=26, minBit 0, minWin=28, winSum=453
1289 11:07:47.718017 TX Vref=28, minBit 2, minWin=28, winSum=455
1290 11:07:47.721713 TX Vref=30, minBit 2, minWin=28, winSum=459
1291 11:07:47.725112 TX Vref=32, minBit 2, minWin=28, winSum=458
1292 11:07:47.731256 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
1293 11:07:47.731855
1294 11:07:47.734637 Final TX Range 1 Vref 30
1295 11:07:47.735054
1296 11:07:47.735384 ==
1297 11:07:47.738427 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 11:07:47.741572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1299 11:07:47.741990 ==
1300 11:07:47.742327
1301 11:07:47.742636
1302 11:07:47.745295 TX Vref Scan disable
1303 11:07:47.748166 == TX Byte 0 ==
1304 11:07:47.751936 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1305 11:07:47.754915 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1306 11:07:47.758144 == TX Byte 1 ==
1307 11:07:47.761489 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1308 11:07:47.764882 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1309 11:07:47.765303
1310 11:07:47.768782 [DATLAT]
1311 11:07:47.769198 Freq=800, CH0 RK1
1312 11:07:47.769531
1313 11:07:47.771271 DATLAT Default: 0x9
1314 11:07:47.771687 0, 0xFFFF, sum = 0
1315 11:07:47.774689 1, 0xFFFF, sum = 0
1316 11:07:47.775113 2, 0xFFFF, sum = 0
1317 11:07:47.778813 3, 0xFFFF, sum = 0
1318 11:07:47.779237 4, 0xFFFF, sum = 0
1319 11:07:47.781907 5, 0xFFFF, sum = 0
1320 11:07:47.782330 6, 0xFFFF, sum = 0
1321 11:07:47.784571 7, 0xFFFF, sum = 0
1322 11:07:47.785076 8, 0x0, sum = 1
1323 11:07:47.787997 9, 0x0, sum = 2
1324 11:07:47.788435 10, 0x0, sum = 3
1325 11:07:47.791299 11, 0x0, sum = 4
1326 11:07:47.791721 best_step = 9
1327 11:07:47.792054
1328 11:07:47.792362 ==
1329 11:07:47.794528 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 11:07:47.802174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1331 11:07:47.802592 ==
1332 11:07:47.802927 RX Vref Scan: 0
1333 11:07:47.803240
1334 11:07:47.805285 RX Vref 0 -> 0, step: 1
1335 11:07:47.805700
1336 11:07:47.807981 RX Delay -111 -> 252, step: 8
1337 11:07:47.811722 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1338 11:07:47.814443 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1339 11:07:47.821565 iDelay=217, Bit 2, Center 84 (-39 ~ 208) 248
1340 11:07:47.825100 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1341 11:07:47.827915 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1342 11:07:47.831180 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1343 11:07:47.834801 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1344 11:07:47.841200 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1345 11:07:47.844465 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1346 11:07:47.847837 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1347 11:07:47.850966 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1348 11:07:47.854414 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1349 11:07:47.860931 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1350 11:07:47.864687 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1351 11:07:47.867925 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1352 11:07:47.871272 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1353 11:07:47.871720 ==
1354 11:07:47.874420 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 11:07:47.881096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1356 11:07:47.881534 ==
1357 11:07:47.882022 DQS Delay:
1358 11:07:47.882418 DQS0 = 0, DQS1 = 0
1359 11:07:47.885146 DQM Delay:
1360 11:07:47.885562 DQM0 = 85, DQM1 = 73
1361 11:07:47.887522 DQ Delay:
1362 11:07:47.891109 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1363 11:07:47.891527 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1364 11:07:47.894758 DQ8 =64, DQ9 =60, DQ10 =72, DQ11 =64
1365 11:07:47.897526 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1366 11:07:47.902365
1367 11:07:47.902812
1368 11:07:47.907613 [DQSOSCAuto] RK1, (LSB)MR18= 0x4848, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1369 11:07:47.910893 CH0 RK1: MR19=606, MR18=4848
1370 11:07:47.917879 CH0_RK1: MR19=0x606, MR18=0x4848, DQSOSC=391, MR23=63, INC=96, DEC=64
1371 11:07:47.918176 [RxdqsGatingPostProcess] freq 800
1372 11:07:47.924784 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1373 11:07:47.928406 Pre-setting of DQS Precalculation
1374 11:07:47.931500 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1375 11:07:47.934843 ==
1376 11:07:47.937566 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 11:07:47.941179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1378 11:07:47.941478 ==
1379 11:07:47.944175 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 11:07:47.951151 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 11:07:47.960995 [CA 0] Center 37 (6~68) winsize 63
1382 11:07:47.964698 [CA 1] Center 37 (6~68) winsize 63
1383 11:07:47.967749 [CA 2] Center 34 (4~65) winsize 62
1384 11:07:47.971309 [CA 3] Center 34 (4~65) winsize 62
1385 11:07:47.974306 [CA 4] Center 33 (3~64) winsize 62
1386 11:07:47.977448 [CA 5] Center 33 (3~64) winsize 62
1387 11:07:47.977934
1388 11:07:47.980777 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1389 11:07:47.981195
1390 11:07:47.984387 [CATrainingPosCal] consider 1 rank data
1391 11:07:47.987666 u2DelayCellTimex100 = 270/100 ps
1392 11:07:47.991170 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1393 11:07:47.994300 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1394 11:07:48.001438 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1395 11:07:48.004431 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 11:07:48.007236 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 11:07:48.010854 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1398 11:07:48.011325
1399 11:07:48.014654 CA PerBit enable=1, Macro0, CA PI delay=33
1400 11:07:48.015069
1401 11:07:48.017619 [CBTSetCACLKResult] CA Dly = 33
1402 11:07:48.018083 CS Dly: 4 (0~35)
1403 11:07:48.018418 ==
1404 11:07:48.020698 Dram Type= 6, Freq= 0, CH_1, rank 1
1405 11:07:48.027276 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1406 11:07:48.027691 ==
1407 11:07:48.030860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1408 11:07:48.036824 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1409 11:07:48.046504 [CA 0] Center 37 (6~68) winsize 63
1410 11:07:48.049999 [CA 1] Center 37 (6~68) winsize 63
1411 11:07:48.052878 [CA 2] Center 34 (4~65) winsize 62
1412 11:07:48.056319 [CA 3] Center 34 (4~65) winsize 62
1413 11:07:48.060283 [CA 4] Center 33 (3~64) winsize 62
1414 11:07:48.063490 [CA 5] Center 33 (3~64) winsize 62
1415 11:07:48.063916
1416 11:07:48.066645 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1417 11:07:48.067058
1418 11:07:48.069962 [CATrainingPosCal] consider 2 rank data
1419 11:07:48.073469 u2DelayCellTimex100 = 270/100 ps
1420 11:07:48.076444 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1421 11:07:48.080351 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1422 11:07:48.086521 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1423 11:07:48.089929 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1424 11:07:48.093061 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 11:07:48.096634 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1426 11:07:48.097092
1427 11:07:48.100554 CA PerBit enable=1, Macro0, CA PI delay=33
1428 11:07:48.101012
1429 11:07:48.103204 [CBTSetCACLKResult] CA Dly = 33
1430 11:07:48.103614 CS Dly: 5 (0~37)
1431 11:07:48.103938
1432 11:07:48.106493 ----->DramcWriteLeveling(PI) begin...
1433 11:07:48.110083 ==
1434 11:07:48.113377 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 11:07:48.117159 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1436 11:07:48.117572 ==
1437 11:07:48.119692 Write leveling (Byte 0): 27 => 27
1438 11:07:48.123232 Write leveling (Byte 1): 26 => 26
1439 11:07:48.126362 DramcWriteLeveling(PI) end<-----
1440 11:07:48.126773
1441 11:07:48.127098 ==
1442 11:07:48.129969 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 11:07:48.132985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1444 11:07:48.133573 ==
1445 11:07:48.136494 [Gating] SW mode calibration
1446 11:07:48.143416 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1447 11:07:48.146923 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1448 11:07:48.153251 0 6 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
1449 11:07:48.156622 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 11:07:48.160060 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 11:07:48.166247 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 11:07:48.169603 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 11:07:48.173303 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:07:48.180149 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:07:48.182826 0 6 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1456 11:07:48.186359 0 7 0 | B1->B0 | 2a2a 3f3f | 0 0 | (0 0) (0 0)
1457 11:07:48.193506 0 7 4 | B1->B0 | 4544 4646 | 1 0 | (0 0) (0 0)
1458 11:07:48.196141 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1459 11:07:48.200244 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1460 11:07:48.207505 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1461 11:07:48.210078 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1462 11:07:48.213011 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1463 11:07:48.219487 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1464 11:07:48.224441 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1465 11:07:48.226303 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 11:07:48.232890 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 11:07:48.236481 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1468 11:07:48.239423 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1469 11:07:48.246326 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1470 11:07:48.250507 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1471 11:07:48.252825 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1472 11:07:48.256179 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1473 11:07:48.263529 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1474 11:07:48.266224 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1475 11:07:48.269411 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1476 11:07:48.275963 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1477 11:07:48.280087 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1478 11:07:48.282436 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1479 11:07:48.289690 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1480 11:07:48.292378 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1481 11:07:48.296147 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1482 11:07:48.299068 Total UI for P1: 0, mck2ui 16
1483 11:07:48.302186 best dqsien dly found for B0: ( 0, 10, 0)
1484 11:07:48.305775 Total UI for P1: 0, mck2ui 16
1485 11:07:48.309775 best dqsien dly found for B1: ( 0, 10, 0)
1486 11:07:48.312321 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1487 11:07:48.316497 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1488 11:07:48.316968
1489 11:07:48.322312 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1490 11:07:48.325851 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1491 11:07:48.329125 [Gating] SW calibration Done
1492 11:07:48.329562 ==
1493 11:07:48.332198 Dram Type= 6, Freq= 0, CH_1, rank 0
1494 11:07:48.335709 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1495 11:07:48.336151 ==
1496 11:07:48.336491 RX Vref Scan: 0
1497 11:07:48.339037
1498 11:07:48.339456 RX Vref 0 -> 0, step: 1
1499 11:07:48.339877
1500 11:07:48.342186 RX Delay -130 -> 252, step: 16
1501 11:07:48.345321 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1502 11:07:48.348893 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1503 11:07:48.355529 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1504 11:07:48.358605 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1505 11:07:48.363373 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1506 11:07:48.366065 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1507 11:07:48.369102 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1508 11:07:48.375485 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1509 11:07:48.378928 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1510 11:07:48.382014 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1511 11:07:48.385701 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1512 11:07:48.389111 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1513 11:07:48.395427 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1514 11:07:48.398479 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1515 11:07:48.402039 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1516 11:07:48.405436 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1517 11:07:48.405517 ==
1518 11:07:48.408258 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 11:07:48.415356 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1520 11:07:48.415437 ==
1521 11:07:48.415501 DQS Delay:
1522 11:07:48.415561 DQS0 = 0, DQS1 = 0
1523 11:07:48.418484 DQM Delay:
1524 11:07:48.418565 DQM0 = 80, DQM1 = 73
1525 11:07:48.421757 DQ Delay:
1526 11:07:48.425334 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1527 11:07:48.428599 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1528 11:07:48.432674 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1529 11:07:48.435086 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1530 11:07:48.435167
1531 11:07:48.435232
1532 11:07:48.435291 ==
1533 11:07:48.438200 Dram Type= 6, Freq= 0, CH_1, rank 0
1534 11:07:48.441567 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1535 11:07:48.441648 ==
1536 11:07:48.441712
1537 11:07:48.441772
1538 11:07:48.446071 TX Vref Scan disable
1539 11:07:48.446151 == TX Byte 0 ==
1540 11:07:48.451522 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1541 11:07:48.455180 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1542 11:07:48.455262 == TX Byte 1 ==
1543 11:07:48.461875 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1544 11:07:48.465006 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1545 11:07:48.465087 ==
1546 11:07:48.468521 Dram Type= 6, Freq= 0, CH_1, rank 0
1547 11:07:48.471950 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1548 11:07:48.472031 ==
1549 11:07:48.485299 TX Vref=22, minBit 3, minWin=27, winSum=445
1550 11:07:48.488543 TX Vref=24, minBit 0, minWin=28, winSum=451
1551 11:07:48.492944 TX Vref=26, minBit 0, minWin=28, winSum=455
1552 11:07:48.495489 TX Vref=28, minBit 0, minWin=28, winSum=459
1553 11:07:48.498563 TX Vref=30, minBit 0, minWin=28, winSum=459
1554 11:07:48.501970 TX Vref=32, minBit 0, minWin=28, winSum=456
1555 11:07:48.508616 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 28
1556 11:07:48.508697
1557 11:07:48.512524 Final TX Range 1 Vref 28
1558 11:07:48.512606
1559 11:07:48.512670 ==
1560 11:07:48.515218 Dram Type= 6, Freq= 0, CH_1, rank 0
1561 11:07:48.518747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1562 11:07:48.518828 ==
1563 11:07:48.518893
1564 11:07:48.522647
1565 11:07:48.522727 TX Vref Scan disable
1566 11:07:48.525554 == TX Byte 0 ==
1567 11:07:48.528615 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1568 11:07:48.531689 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1569 11:07:48.537624 == TX Byte 1 ==
1570 11:07:48.538311 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1571 11:07:48.542275 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1572 11:07:48.545310
1573 11:07:48.545390 [DATLAT]
1574 11:07:48.545455 Freq=800, CH1 RK0
1575 11:07:48.545516
1576 11:07:48.548519 DATLAT Default: 0xa
1577 11:07:48.548599 0, 0xFFFF, sum = 0
1578 11:07:48.551633 1, 0xFFFF, sum = 0
1579 11:07:48.551715 2, 0xFFFF, sum = 0
1580 11:07:48.555387 3, 0xFFFF, sum = 0
1581 11:07:48.555470 4, 0xFFFF, sum = 0
1582 11:07:48.558740 5, 0xFFFF, sum = 0
1583 11:07:48.562180 6, 0xFFFF, sum = 0
1584 11:07:48.562262 7, 0xFFFF, sum = 0
1585 11:07:48.562328 8, 0x0, sum = 1
1586 11:07:48.565998 9, 0x0, sum = 2
1587 11:07:48.566080 10, 0x0, sum = 3
1588 11:07:48.568404 11, 0x0, sum = 4
1589 11:07:48.568486 best_step = 9
1590 11:07:48.568550
1591 11:07:48.568609 ==
1592 11:07:48.572111 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 11:07:48.579037 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1594 11:07:48.579118 ==
1595 11:07:48.579183 RX Vref Scan: 1
1596 11:07:48.579242
1597 11:07:48.582426 Set Vref Range= 32 -> 127
1598 11:07:48.582507
1599 11:07:48.585010 RX Vref 32 -> 127, step: 1
1600 11:07:48.585091
1601 11:07:48.588548 RX Delay -111 -> 252, step: 8
1602 11:07:48.588629
1603 11:07:48.588694 Set Vref, RX VrefLevel [Byte0]: 32
1604 11:07:48.591945 [Byte1]: 32
1605 11:07:48.596857
1606 11:07:48.596937 Set Vref, RX VrefLevel [Byte0]: 33
1607 11:07:48.599468 [Byte1]: 33
1608 11:07:48.603544
1609 11:07:48.603625 Set Vref, RX VrefLevel [Byte0]: 34
1610 11:07:48.607007 [Byte1]: 34
1611 11:07:48.611553
1612 11:07:48.611634 Set Vref, RX VrefLevel [Byte0]: 35
1613 11:07:48.615217 [Byte1]: 35
1614 11:07:48.619244
1615 11:07:48.619325 Set Vref, RX VrefLevel [Byte0]: 36
1616 11:07:48.622620 [Byte1]: 36
1617 11:07:48.627010
1618 11:07:48.627091 Set Vref, RX VrefLevel [Byte0]: 37
1619 11:07:48.629911 [Byte1]: 37
1620 11:07:48.634353
1621 11:07:48.634433 Set Vref, RX VrefLevel [Byte0]: 38
1622 11:07:48.638877 [Byte1]: 38
1623 11:07:48.641879
1624 11:07:48.641959 Set Vref, RX VrefLevel [Byte0]: 39
1625 11:07:48.645544 [Byte1]: 39
1626 11:07:48.649872
1627 11:07:48.649953 Set Vref, RX VrefLevel [Byte0]: 40
1628 11:07:48.653159 [Byte1]: 40
1629 11:07:48.657100
1630 11:07:48.657180 Set Vref, RX VrefLevel [Byte0]: 41
1631 11:07:48.661329 [Byte1]: 41
1632 11:07:48.665160
1633 11:07:48.665241 Set Vref, RX VrefLevel [Byte0]: 42
1634 11:07:48.668157 [Byte1]: 42
1635 11:07:48.673332
1636 11:07:48.673413 Set Vref, RX VrefLevel [Byte0]: 43
1637 11:07:48.675861 [Byte1]: 43
1638 11:07:48.680523
1639 11:07:48.680604 Set Vref, RX VrefLevel [Byte0]: 44
1640 11:07:48.684518 [Byte1]: 44
1641 11:07:48.688698
1642 11:07:48.688820 Set Vref, RX VrefLevel [Byte0]: 45
1643 11:07:48.691415 [Byte1]: 45
1644 11:07:48.695970
1645 11:07:48.696051 Set Vref, RX VrefLevel [Byte0]: 46
1646 11:07:48.699515 [Byte1]: 46
1647 11:07:48.703197
1648 11:07:48.703277 Set Vref, RX VrefLevel [Byte0]: 47
1649 11:07:48.706276 [Byte1]: 47
1650 11:07:48.711751
1651 11:07:48.711832 Set Vref, RX VrefLevel [Byte0]: 48
1652 11:07:48.714149 [Byte1]: 48
1653 11:07:48.719962
1654 11:07:48.720043 Set Vref, RX VrefLevel [Byte0]: 49
1655 11:07:48.721766 [Byte1]: 49
1656 11:07:48.726531
1657 11:07:48.726611 Set Vref, RX VrefLevel [Byte0]: 50
1658 11:07:48.729367 [Byte1]: 50
1659 11:07:48.734018
1660 11:07:48.734099 Set Vref, RX VrefLevel [Byte0]: 51
1661 11:07:48.737526 [Byte1]: 51
1662 11:07:48.741207
1663 11:07:48.741287 Set Vref, RX VrefLevel [Byte0]: 52
1664 11:07:48.744692 [Byte1]: 52
1665 11:07:48.749142
1666 11:07:48.749222 Set Vref, RX VrefLevel [Byte0]: 53
1667 11:07:48.752287 [Byte1]: 53
1668 11:07:48.756894
1669 11:07:48.756975 Set Vref, RX VrefLevel [Byte0]: 54
1670 11:07:48.759806 [Byte1]: 54
1671 11:07:48.764300
1672 11:07:48.764381 Set Vref, RX VrefLevel [Byte0]: 55
1673 11:07:48.767868 [Byte1]: 55
1674 11:07:48.772300
1675 11:07:48.772380 Set Vref, RX VrefLevel [Byte0]: 56
1676 11:07:48.775656 [Byte1]: 56
1677 11:07:48.780160
1678 11:07:48.780240 Set Vref, RX VrefLevel [Byte0]: 57
1679 11:07:48.783236 [Byte1]: 57
1680 11:07:48.787687
1681 11:07:48.787767 Set Vref, RX VrefLevel [Byte0]: 58
1682 11:07:48.790607 [Byte1]: 58
1683 11:07:48.794957
1684 11:07:48.795037 Set Vref, RX VrefLevel [Byte0]: 59
1685 11:07:48.798664 [Byte1]: 59
1686 11:07:48.803426
1687 11:07:48.803506 Set Vref, RX VrefLevel [Byte0]: 60
1688 11:07:48.805931 [Byte1]: 60
1689 11:07:48.810271
1690 11:07:48.810352 Set Vref, RX VrefLevel [Byte0]: 61
1691 11:07:48.813750 [Byte1]: 61
1692 11:07:48.818133
1693 11:07:48.818213 Set Vref, RX VrefLevel [Byte0]: 62
1694 11:07:48.821073 [Byte1]: 62
1695 11:07:48.826082
1696 11:07:48.826163 Set Vref, RX VrefLevel [Byte0]: 63
1697 11:07:48.829092 [Byte1]: 63
1698 11:07:48.833301
1699 11:07:48.833381 Set Vref, RX VrefLevel [Byte0]: 64
1700 11:07:48.837696 [Byte1]: 64
1701 11:07:48.841091
1702 11:07:48.841171 Set Vref, RX VrefLevel [Byte0]: 65
1703 11:07:48.844128 [Byte1]: 65
1704 11:07:48.848680
1705 11:07:48.848801 Set Vref, RX VrefLevel [Byte0]: 66
1706 11:07:48.851952 [Byte1]: 66
1707 11:07:48.856506
1708 11:07:48.856587 Set Vref, RX VrefLevel [Byte0]: 67
1709 11:07:48.859590 [Byte1]: 67
1710 11:07:48.863906
1711 11:07:48.863987 Set Vref, RX VrefLevel [Byte0]: 68
1712 11:07:48.866925 [Byte1]: 68
1713 11:07:48.871724
1714 11:07:48.871805 Set Vref, RX VrefLevel [Byte0]: 69
1715 11:07:48.874926 [Byte1]: 69
1716 11:07:48.879978
1717 11:07:48.880059 Set Vref, RX VrefLevel [Byte0]: 70
1718 11:07:48.882341 [Byte1]: 70
1719 11:07:48.887557
1720 11:07:48.887637 Set Vref, RX VrefLevel [Byte0]: 71
1721 11:07:48.890156 [Byte1]: 71
1722 11:07:48.894756
1723 11:07:48.894836 Set Vref, RX VrefLevel [Byte0]: 72
1724 11:07:48.897759 [Byte1]: 72
1725 11:07:48.902735
1726 11:07:48.902815 Set Vref, RX VrefLevel [Byte0]: 73
1727 11:07:48.905301 [Byte1]: 73
1728 11:07:48.909776
1729 11:07:48.909856 Set Vref, RX VrefLevel [Byte0]: 74
1730 11:07:48.913876 [Byte1]: 74
1731 11:07:48.917379
1732 11:07:48.917463 Set Vref, RX VrefLevel [Byte0]: 75
1733 11:07:48.920436 [Byte1]: 75
1734 11:07:48.925444
1735 11:07:48.925524 Final RX Vref Byte 0 = 59 to rank0
1736 11:07:48.928167 Final RX Vref Byte 1 = 55 to rank0
1737 11:07:48.931647 Final RX Vref Byte 0 = 59 to rank1
1738 11:07:48.935377 Final RX Vref Byte 1 = 55 to rank1==
1739 11:07:48.938834 Dram Type= 6, Freq= 0, CH_1, rank 0
1740 11:07:48.944865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1741 11:07:48.944947 ==
1742 11:07:48.945011 DQS Delay:
1743 11:07:48.945071 DQS0 = 0, DQS1 = 0
1744 11:07:48.948514 DQM Delay:
1745 11:07:48.948595 DQM0 = 81, DQM1 = 75
1746 11:07:48.952102 DQ Delay:
1747 11:07:48.955294 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1748 11:07:48.958151 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1749 11:07:48.961784 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1750 11:07:48.964865 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1751 11:07:48.964946
1752 11:07:48.965010
1753 11:07:48.971401 [DQSOSCAuto] RK0, (LSB)MR18= 0x4747, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1754 11:07:48.974698 CH1 RK0: MR19=606, MR18=4747
1755 11:07:48.981919 CH1_RK0: MR19=0x606, MR18=0x4747, DQSOSC=392, MR23=63, INC=96, DEC=64
1756 11:07:48.982001
1757 11:07:48.985844 ----->DramcWriteLeveling(PI) begin...
1758 11:07:48.985927 ==
1759 11:07:48.988215 Dram Type= 6, Freq= 0, CH_1, rank 1
1760 11:07:48.991248 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1761 11:07:48.991330 ==
1762 11:07:48.995369 Write leveling (Byte 0): 25 => 25
1763 11:07:48.998285 Write leveling (Byte 1): 24 => 24
1764 11:07:49.001527 DramcWriteLeveling(PI) end<-----
1765 11:07:49.001608
1766 11:07:49.001672 ==
1767 11:07:49.005751 Dram Type= 6, Freq= 0, CH_1, rank 1
1768 11:07:49.008225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1769 11:07:49.008306 ==
1770 11:07:49.011315 [Gating] SW mode calibration
1771 11:07:49.018569 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1772 11:07:49.024575 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1773 11:07:49.027883 0 6 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
1774 11:07:49.031343 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1775 11:07:49.037989 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1776 11:07:49.041290 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1777 11:07:49.044844 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1778 11:07:49.051782 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1779 11:07:49.054801 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1780 11:07:49.058941 0 6 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1781 11:07:49.065087 0 7 0 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
1782 11:07:49.068326 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1783 11:07:49.071836 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1784 11:07:49.078078 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1785 11:07:49.081605 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1786 11:07:49.086238 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1787 11:07:49.091997 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1788 11:07:49.094485 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1789 11:07:49.099540 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1790 11:07:49.101568 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 11:07:49.108173 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 11:07:49.111818 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1793 11:07:49.114670 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1794 11:07:49.121563 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1795 11:07:49.124661 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1796 11:07:49.128175 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1797 11:07:49.134783 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1798 11:07:49.139038 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1799 11:07:49.141876 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1800 11:07:49.148168 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1801 11:07:49.151302 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1802 11:07:49.154606 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1803 11:07:49.161388 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1804 11:07:49.164839 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1805 11:07:49.168153 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1806 11:07:49.171414 Total UI for P1: 0, mck2ui 16
1807 11:07:49.175135 best dqsien dly found for B0: ( 0, 9, 28)
1808 11:07:49.178153 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1809 11:07:49.181582 Total UI for P1: 0, mck2ui 16
1810 11:07:49.184916 best dqsien dly found for B1: ( 0, 10, 0)
1811 11:07:49.188057 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1812 11:07:49.195045 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1813 11:07:49.195127
1814 11:07:49.198062 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1815 11:07:49.201345 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1816 11:07:49.205551 [Gating] SW calibration Done
1817 11:07:49.205632 ==
1818 11:07:49.207904 Dram Type= 6, Freq= 0, CH_1, rank 1
1819 11:07:49.211870 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1820 11:07:49.211951 ==
1821 11:07:49.214682 RX Vref Scan: 0
1822 11:07:49.214763
1823 11:07:49.214828 RX Vref 0 -> 0, step: 1
1824 11:07:49.214888
1825 11:07:49.217832 RX Delay -130 -> 252, step: 16
1826 11:07:49.221167 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1827 11:07:49.228670 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1828 11:07:49.232889 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1829 11:07:49.234488 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1830 11:07:49.237888 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1831 11:07:49.241493 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1832 11:07:49.248403 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1833 11:07:49.251517 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1834 11:07:49.254730 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1835 11:07:49.257697 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1836 11:07:49.261693 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1837 11:07:49.267900 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1838 11:07:49.271689 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1839 11:07:49.274388 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1840 11:07:49.278392 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1841 11:07:49.281017 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1842 11:07:49.284773 ==
1843 11:07:49.284855 Dram Type= 6, Freq= 0, CH_1, rank 1
1844 11:07:49.291348 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1845 11:07:49.291443 ==
1846 11:07:49.291510 DQS Delay:
1847 11:07:49.294396 DQS0 = 0, DQS1 = 0
1848 11:07:49.294478 DQM Delay:
1849 11:07:49.297797 DQM0 = 86, DQM1 = 74
1850 11:07:49.297878 DQ Delay:
1851 11:07:49.300962 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1852 11:07:49.304417 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1853 11:07:49.308021 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1854 11:07:49.311337 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1855 11:07:49.311418
1856 11:07:49.311482
1857 11:07:49.311541 ==
1858 11:07:49.314586 Dram Type= 6, Freq= 0, CH_1, rank 1
1859 11:07:49.317814 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1860 11:07:49.317896 ==
1861 11:07:49.317960
1862 11:07:49.318019
1863 11:07:49.321207 TX Vref Scan disable
1864 11:07:49.324858 == TX Byte 0 ==
1865 11:07:49.328143 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1866 11:07:49.331314 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1867 11:07:49.334628 == TX Byte 1 ==
1868 11:07:49.338314 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1869 11:07:49.341599 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1870 11:07:49.341681 ==
1871 11:07:49.344659 Dram Type= 6, Freq= 0, CH_1, rank 1
1872 11:07:49.347672 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1873 11:07:49.347754 ==
1874 11:07:49.362523 TX Vref=22, minBit 0, minWin=27, winSum=448
1875 11:07:49.365610 TX Vref=24, minBit 8, minWin=27, winSum=454
1876 11:07:49.369340 TX Vref=26, minBit 0, minWin=28, winSum=454
1877 11:07:49.373840 TX Vref=28, minBit 0, minWin=28, winSum=457
1878 11:07:49.375243 TX Vref=30, minBit 0, minWin=28, winSum=455
1879 11:07:49.378553 TX Vref=32, minBit 9, minWin=27, winSum=454
1880 11:07:49.386409 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
1881 11:07:49.386491
1882 11:07:49.389246 Final TX Range 1 Vref 28
1883 11:07:49.389328
1884 11:07:49.389392 ==
1885 11:07:49.392112 Dram Type= 6, Freq= 0, CH_1, rank 1
1886 11:07:49.395299 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1887 11:07:49.395398 ==
1888 11:07:49.395462
1889 11:07:49.398731
1890 11:07:49.398812 TX Vref Scan disable
1891 11:07:49.402148 == TX Byte 0 ==
1892 11:07:49.405338 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1893 11:07:49.409034 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1894 11:07:49.412186 == TX Byte 1 ==
1895 11:07:49.416089 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1896 11:07:49.418748 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1897 11:07:49.422569
1898 11:07:49.422650 [DATLAT]
1899 11:07:49.422714 Freq=800, CH1 RK1
1900 11:07:49.422774
1901 11:07:49.425829 DATLAT Default: 0x9
1902 11:07:49.425909 0, 0xFFFF, sum = 0
1903 11:07:49.428659 1, 0xFFFF, sum = 0
1904 11:07:49.428793 2, 0xFFFF, sum = 0
1905 11:07:49.432315 3, 0xFFFF, sum = 0
1906 11:07:49.432398 4, 0xFFFF, sum = 0
1907 11:07:49.435917 5, 0xFFFF, sum = 0
1908 11:07:49.438801 6, 0xFFFF, sum = 0
1909 11:07:49.438885 7, 0xFFFF, sum = 0
1910 11:07:49.438951 8, 0x0, sum = 1
1911 11:07:49.441827 9, 0x0, sum = 2
1912 11:07:49.441910 10, 0x0, sum = 3
1913 11:07:49.446113 11, 0x0, sum = 4
1914 11:07:49.446196 best_step = 9
1915 11:07:49.446261
1916 11:07:49.446322 ==
1917 11:07:49.448447 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 11:07:49.455490 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1919 11:07:49.455572 ==
1920 11:07:49.455636 RX Vref Scan: 0
1921 11:07:49.455696
1922 11:07:49.458873 RX Vref 0 -> 0, step: 1
1923 11:07:49.458954
1924 11:07:49.462339 RX Delay -111 -> 252, step: 8
1925 11:07:49.465363 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1926 11:07:49.469896 iDelay=217, Bit 1, Center 80 (-39 ~ 200) 240
1927 11:07:49.475679 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1928 11:07:49.478895 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1929 11:07:49.481813 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1930 11:07:49.485464 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1931 11:07:49.489704 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1932 11:07:49.495000 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1933 11:07:49.498343 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1934 11:07:49.501959 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1935 11:07:49.505159 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1936 11:07:49.508830 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1937 11:07:49.515470 iDelay=217, Bit 12, Center 88 (-31 ~ 208) 240
1938 11:07:49.518656 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1939 11:07:49.521661 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1940 11:07:49.524922 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1941 11:07:49.525008 ==
1942 11:07:49.528578 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 11:07:49.534905 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1944 11:07:49.534987 ==
1945 11:07:49.535052 DQS Delay:
1946 11:07:49.535112 DQS0 = 0, DQS1 = 0
1947 11:07:49.538163 DQM Delay:
1948 11:07:49.538245 DQM0 = 84, DQM1 = 75
1949 11:07:49.542302 DQ Delay:
1950 11:07:49.545333 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =80
1951 11:07:49.548730 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1952 11:07:49.552536 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1953 11:07:49.554904 DQ12 =88, DQ13 =84, DQ14 =80, DQ15 =84
1954 11:07:49.554985
1955 11:07:49.555049
1956 11:07:49.561892 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c3c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1957 11:07:49.564861 CH1 RK1: MR19=606, MR18=3C3C
1958 11:07:49.571617 CH1_RK1: MR19=0x606, MR18=0x3C3C, DQSOSC=394, MR23=63, INC=95, DEC=63
1959 11:07:49.575355 [RxdqsGatingPostProcess] freq 800
1960 11:07:49.578375 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1961 11:07:49.581439 Pre-setting of DQS Precalculation
1962 11:07:49.588736 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1963 11:07:49.594724 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1964 11:07:49.602598 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1965 11:07:49.602679
1966 11:07:49.602743
1967 11:07:49.604598 [Calibration Summary] 1600 Mbps
1968 11:07:49.604679 CH 0, Rank 0
1969 11:07:49.608096 SW Impedance : PASS
1970 11:07:49.611513 DUTY Scan : NO K
1971 11:07:49.611594 ZQ Calibration : PASS
1972 11:07:49.614811 Jitter Meter : NO K
1973 11:07:49.617974 CBT Training : PASS
1974 11:07:49.618055 Write leveling : PASS
1975 11:07:49.621061 RX DQS gating : PASS
1976 11:07:49.621141 RX DQ/DQS(RDDQC) : PASS
1977 11:07:49.625050 TX DQ/DQS : PASS
1978 11:07:49.629375 RX DATLAT : PASS
1979 11:07:49.629455 RX DQ/DQS(Engine): PASS
1980 11:07:49.631512 TX OE : NO K
1981 11:07:49.631592 All Pass.
1982 11:07:49.631656
1983 11:07:49.634843 CH 0, Rank 1
1984 11:07:49.634923 SW Impedance : PASS
1985 11:07:49.638019 DUTY Scan : NO K
1986 11:07:49.641401 ZQ Calibration : PASS
1987 11:07:49.641481 Jitter Meter : NO K
1988 11:07:49.644433 CBT Training : PASS
1989 11:07:49.647985 Write leveling : PASS
1990 11:07:49.648066 RX DQS gating : PASS
1991 11:07:49.651774 RX DQ/DQS(RDDQC) : PASS
1992 11:07:49.654978 TX DQ/DQS : PASS
1993 11:07:49.655059 RX DATLAT : PASS
1994 11:07:49.658362 RX DQ/DQS(Engine): PASS
1995 11:07:49.658442 TX OE : NO K
1996 11:07:49.661358 All Pass.
1997 11:07:49.661437
1998 11:07:49.661501 CH 1, Rank 0
1999 11:07:49.664461 SW Impedance : PASS
2000 11:07:49.664541 DUTY Scan : NO K
2001 11:07:49.668637 ZQ Calibration : PASS
2002 11:07:49.671551 Jitter Meter : NO K
2003 11:07:49.671630 CBT Training : PASS
2004 11:07:49.676029 Write leveling : PASS
2005 11:07:49.677933 RX DQS gating : PASS
2006 11:07:49.678014 RX DQ/DQS(RDDQC) : PASS
2007 11:07:49.681880 TX DQ/DQS : PASS
2008 11:07:49.684724 RX DATLAT : PASS
2009 11:07:49.684804 RX DQ/DQS(Engine): PASS
2010 11:07:49.688044 TX OE : NO K
2011 11:07:49.688123 All Pass.
2012 11:07:49.688187
2013 11:07:49.691561 CH 1, Rank 1
2014 11:07:49.691641 SW Impedance : PASS
2015 11:07:49.694457 DUTY Scan : NO K
2016 11:07:49.697815 ZQ Calibration : PASS
2017 11:07:49.697895 Jitter Meter : NO K
2018 11:07:49.701632 CBT Training : PASS
2019 11:07:49.704848 Write leveling : PASS
2020 11:07:49.704928 RX DQS gating : PASS
2021 11:07:49.707996 RX DQ/DQS(RDDQC) : PASS
2022 11:07:49.708076 TX DQ/DQS : PASS
2023 11:07:49.711368 RX DATLAT : PASS
2024 11:07:49.715454 RX DQ/DQS(Engine): PASS
2025 11:07:49.715534 TX OE : NO K
2026 11:07:49.718534 All Pass.
2027 11:07:49.718614
2028 11:07:49.718677 DramC Write-DBI off
2029 11:07:49.721708 PER_BANK_REFRESH: Hybrid Mode
2030 11:07:49.724662 TX_TRACKING: ON
2031 11:07:49.727882 [GetDramInforAfterCalByMRR] Vendor 6.
2032 11:07:49.731125 [GetDramInforAfterCalByMRR] Revision 606.
2033 11:07:49.735925 [GetDramInforAfterCalByMRR] Revision 2 0.
2034 11:07:49.736006 MR0 0x3939
2035 11:07:49.736069 MR8 0x1111
2036 11:07:49.741204 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2037 11:07:49.741284
2038 11:07:49.741347 MR0 0x3939
2039 11:07:49.741406 MR8 0x1111
2040 11:07:49.744595 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2041 11:07:49.744675
2042 11:07:49.754817 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2043 11:07:49.757811 [FAST_K] Save calibration result to emmc
2044 11:07:49.761684 [FAST_K] Save calibration result to emmc
2045 11:07:49.764563 dram_init: config_dvfs: 1
2046 11:07:49.768100 dramc_set_vcore_voltage set vcore to 662500
2047 11:07:49.771326 Read voltage for 1200, 2
2048 11:07:49.771406 Vio18 = 0
2049 11:07:49.771469 Vcore = 662500
2050 11:07:49.775668 Vdram = 0
2051 11:07:49.775748 Vddq = 0
2052 11:07:49.775812 Vmddr = 0
2053 11:07:49.782509 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2054 11:07:49.785414 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2055 11:07:49.788387 MEM_TYPE=3, freq_sel=15
2056 11:07:49.791693 sv_algorithm_assistance_LP4_1600
2057 11:07:49.794755 ============ PULL DRAM RESETB DOWN ============
2058 11:07:49.798127 ========== PULL DRAM RESETB DOWN end =========
2059 11:07:49.804674 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2060 11:07:49.808279 ===================================
2061 11:07:49.808359 LPDDR4 DRAM CONFIGURATION
2062 11:07:49.811591 ===================================
2063 11:07:49.814957 EX_ROW_EN[0] = 0x0
2064 11:07:49.817988 EX_ROW_EN[1] = 0x0
2065 11:07:49.818069 LP4Y_EN = 0x0
2066 11:07:49.821350 WORK_FSP = 0x0
2067 11:07:49.821430 WL = 0x4
2068 11:07:49.824975 RL = 0x4
2069 11:07:49.825055 BL = 0x2
2070 11:07:49.828385 RPST = 0x0
2071 11:07:49.828465 RD_PRE = 0x0
2072 11:07:49.830994 WR_PRE = 0x1
2073 11:07:49.831074 WR_PST = 0x0
2074 11:07:49.834576 DBI_WR = 0x0
2075 11:07:49.834656 DBI_RD = 0x0
2076 11:07:49.838293 OTF = 0x1
2077 11:07:49.841542 ===================================
2078 11:07:49.844452 ===================================
2079 11:07:49.844532 ANA top config
2080 11:07:49.848053 ===================================
2081 11:07:49.851814 DLL_ASYNC_EN = 0
2082 11:07:49.854880 ALL_SLAVE_EN = 0
2083 11:07:49.858101 NEW_RANK_MODE = 1
2084 11:07:49.858182 DLL_IDLE_MODE = 1
2085 11:07:49.861108 LP45_APHY_COMB_EN = 1
2086 11:07:49.864924 TX_ODT_DIS = 1
2087 11:07:49.867953 NEW_8X_MODE = 1
2088 11:07:49.871404 ===================================
2089 11:07:49.874564 ===================================
2090 11:07:49.877794 data_rate = 2400
2091 11:07:49.877875 CKR = 1
2092 11:07:49.882026 DQ_P2S_RATIO = 8
2093 11:07:49.884515 ===================================
2094 11:07:49.887674 CA_P2S_RATIO = 8
2095 11:07:49.891912 DQ_CA_OPEN = 0
2096 11:07:49.894091 DQ_SEMI_OPEN = 0
2097 11:07:49.899154 CA_SEMI_OPEN = 0
2098 11:07:49.899235 CA_FULL_RATE = 0
2099 11:07:49.900947 DQ_CKDIV4_EN = 0
2100 11:07:49.905294 CA_CKDIV4_EN = 0
2101 11:07:49.908023 CA_PREDIV_EN = 0
2102 11:07:49.910936 PH8_DLY = 17
2103 11:07:49.914759 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2104 11:07:49.914839 DQ_AAMCK_DIV = 4
2105 11:07:49.917909 CA_AAMCK_DIV = 4
2106 11:07:49.921121 CA_ADMCK_DIV = 4
2107 11:07:49.924133 DQ_TRACK_CA_EN = 0
2108 11:07:49.927743 CA_PICK = 1200
2109 11:07:49.931471 CA_MCKIO = 1200
2110 11:07:49.931552 MCKIO_SEMI = 0
2111 11:07:49.934268 PLL_FREQ = 2366
2112 11:07:49.938133 DQ_UI_PI_RATIO = 32
2113 11:07:49.941963 CA_UI_PI_RATIO = 0
2114 11:07:49.944633 ===================================
2115 11:07:49.947588 ===================================
2116 11:07:49.951166 memory_type:LPDDR4
2117 11:07:49.951247 GP_NUM : 10
2118 11:07:49.954494 SRAM_EN : 1
2119 11:07:49.957666 MD32_EN : 0
2120 11:07:49.961414 ===================================
2121 11:07:49.961494 [ANA_INIT] >>>>>>>>>>>>>>
2122 11:07:49.964532 <<<<<< [CONFIGURE PHASE]: ANA_TX
2123 11:07:49.967732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2124 11:07:49.971030 ===================================
2125 11:07:49.974088 data_rate = 2400,PCW = 0X5b00
2126 11:07:49.977620 ===================================
2127 11:07:49.980915 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2128 11:07:49.987414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2129 11:07:49.990925 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2130 11:07:49.997468 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2131 11:07:50.000902 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2132 11:07:50.004117 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2133 11:07:50.004197 [ANA_INIT] flow start
2134 11:07:50.007908 [ANA_INIT] PLL >>>>>>>>
2135 11:07:50.011386 [ANA_INIT] PLL <<<<<<<<
2136 11:07:50.011466 [ANA_INIT] MIDPI >>>>>>>>
2137 11:07:50.014804 [ANA_INIT] MIDPI <<<<<<<<
2138 11:07:50.017371 [ANA_INIT] DLL >>>>>>>>
2139 11:07:50.020632 [ANA_INIT] DLL <<<<<<<<
2140 11:07:50.020735 [ANA_INIT] flow end
2141 11:07:50.024174 ============ LP4 DIFF to SE enter ============
2142 11:07:50.030989 ============ LP4 DIFF to SE exit ============
2143 11:07:50.031070 [ANA_INIT] <<<<<<<<<<<<<
2144 11:07:50.034817 [Flow] Enable top DCM control >>>>>
2145 11:07:50.038136 [Flow] Enable top DCM control <<<<<
2146 11:07:50.041326 Enable DLL master slave shuffle
2147 11:07:50.047471 ==============================================================
2148 11:07:50.047552 Gating Mode config
2149 11:07:50.054314 ==============================================================
2150 11:07:50.057597 Config description:
2151 11:07:50.064140 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2152 11:07:50.070644 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2153 11:07:50.079075 SELPH_MODE 0: By rank 1: By Phase
2154 11:07:50.084076 ==============================================================
2155 11:07:50.084157 GAT_TRACK_EN = 1
2156 11:07:50.087236 RX_GATING_MODE = 2
2157 11:07:50.091458 RX_GATING_TRACK_MODE = 2
2158 11:07:50.094297 SELPH_MODE = 1
2159 11:07:50.097771 PICG_EARLY_EN = 1
2160 11:07:50.100517 VALID_LAT_VALUE = 1
2161 11:07:50.107267 ==============================================================
2162 11:07:50.111476 Enter into Gating configuration >>>>
2163 11:07:50.113999 Exit from Gating configuration <<<<
2164 11:07:50.117151 Enter into DVFS_PRE_config >>>>>
2165 11:07:50.127674 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2166 11:07:50.131282 Exit from DVFS_PRE_config <<<<<
2167 11:07:50.133991 Enter into PICG configuration >>>>
2168 11:07:50.137424 Exit from PICG configuration <<<<
2169 11:07:50.140410 [RX_INPUT] configuration >>>>>
2170 11:07:50.140491 [RX_INPUT] configuration <<<<<
2171 11:07:50.146880 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2172 11:07:50.154166 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2173 11:07:50.160594 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2174 11:07:50.164127 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2175 11:07:50.170182 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2176 11:07:50.177138 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2177 11:07:50.180171 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2178 11:07:50.183717 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2179 11:07:50.190191 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2180 11:07:50.197516 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2181 11:07:50.198180 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2182 11:07:50.204754 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2183 11:07:50.206875 ===================================
2184 11:07:50.206955 LPDDR4 DRAM CONFIGURATION
2185 11:07:50.210032 ===================================
2186 11:07:50.213812 EX_ROW_EN[0] = 0x0
2187 11:07:50.213893 EX_ROW_EN[1] = 0x0
2188 11:07:50.217035 LP4Y_EN = 0x0
2189 11:07:50.217114 WORK_FSP = 0x0
2190 11:07:50.220487 WL = 0x4
2191 11:07:50.223986 RL = 0x4
2192 11:07:50.224067 BL = 0x2
2193 11:07:50.227432 RPST = 0x0
2194 11:07:50.227516 RD_PRE = 0x0
2195 11:07:50.230136 WR_PRE = 0x1
2196 11:07:50.230216 WR_PST = 0x0
2197 11:07:50.233478 DBI_WR = 0x0
2198 11:07:50.233558 DBI_RD = 0x0
2199 11:07:50.237123 OTF = 0x1
2200 11:07:50.241224 ===================================
2201 11:07:50.243467 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2202 11:07:50.247195 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2203 11:07:50.250315 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2204 11:07:50.254457 ===================================
2205 11:07:50.256922 LPDDR4 DRAM CONFIGURATION
2206 11:07:50.261097 ===================================
2207 11:07:50.263542 EX_ROW_EN[0] = 0x10
2208 11:07:50.263622 EX_ROW_EN[1] = 0x0
2209 11:07:50.267369 LP4Y_EN = 0x0
2210 11:07:50.267449 WORK_FSP = 0x0
2211 11:07:50.270787 WL = 0x4
2212 11:07:50.270867 RL = 0x4
2213 11:07:50.273620 BL = 0x2
2214 11:07:50.273700 RPST = 0x0
2215 11:07:50.277618 RD_PRE = 0x0
2216 11:07:50.277698 WR_PRE = 0x1
2217 11:07:50.280662 WR_PST = 0x0
2218 11:07:50.280778 DBI_WR = 0x0
2219 11:07:50.284211 DBI_RD = 0x0
2220 11:07:50.286750 OTF = 0x1
2221 11:07:50.290341 ===================================
2222 11:07:50.293854 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2223 11:07:50.293935 ==
2224 11:07:50.297444 Dram Type= 6, Freq= 0, CH_0, rank 0
2225 11:07:50.303494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2226 11:07:50.303575 ==
2227 11:07:50.303639 [Duty_Offset_Calibration]
2228 11:07:50.308656 B0:0 B1:2 CA:1
2229 11:07:50.308744
2230 11:07:50.310960 [DutyScan_Calibration_Flow] k_type=0
2231 11:07:50.319767
2232 11:07:50.319847 ==CLK 0==
2233 11:07:50.323177 Final CLK duty delay cell = 0
2234 11:07:50.326341 [0] MAX Duty = 5093%(X100), DQS PI = 12
2235 11:07:50.329819 [0] MIN Duty = 4938%(X100), DQS PI = 52
2236 11:07:50.329900 [0] AVG Duty = 5015%(X100)
2237 11:07:50.332611
2238 11:07:50.332693 CH0 CLK Duty spec in!! Max-Min= 155%
2239 11:07:50.340018 [DutyScan_Calibration_Flow] ====Done====
2240 11:07:50.340101
2241 11:07:50.343115 [DutyScan_Calibration_Flow] k_type=1
2242 11:07:50.358564
2243 11:07:50.358644 ==DQS 0 ==
2244 11:07:50.362284 Final DQS duty delay cell = 0
2245 11:07:50.365889 [0] MAX Duty = 5125%(X100), DQS PI = 30
2246 11:07:50.368826 [0] MIN Duty = 5031%(X100), DQS PI = 6
2247 11:07:50.368907 [0] AVG Duty = 5078%(X100)
2248 11:07:50.371910
2249 11:07:50.371991 ==DQS 1 ==
2250 11:07:50.375297 Final DQS duty delay cell = 0
2251 11:07:50.378503 [0] MAX Duty = 5062%(X100), DQS PI = 58
2252 11:07:50.382336 [0] MIN Duty = 4906%(X100), DQS PI = 16
2253 11:07:50.382418 [0] AVG Duty = 4984%(X100)
2254 11:07:50.385110
2255 11:07:50.389309 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2256 11:07:50.389394
2257 11:07:50.391724 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2258 11:07:50.395584 [DutyScan_Calibration_Flow] ====Done====
2259 11:07:50.395665
2260 11:07:50.398915 [DutyScan_Calibration_Flow] k_type=3
2261 11:07:50.415837
2262 11:07:50.415918 ==DQM 0 ==
2263 11:07:50.418903 Final DQM duty delay cell = 0
2264 11:07:50.422578 [0] MAX Duty = 5187%(X100), DQS PI = 20
2265 11:07:50.425538 [0] MIN Duty = 4969%(X100), DQS PI = 40
2266 11:07:50.428928 [0] AVG Duty = 5078%(X100)
2267 11:07:50.429008
2268 11:07:50.429071 ==DQM 1 ==
2269 11:07:50.432636 Final DQM duty delay cell = 4
2270 11:07:50.435748 [4] MAX Duty = 5187%(X100), DQS PI = 54
2271 11:07:50.439039 [4] MIN Duty = 5000%(X100), DQS PI = 18
2272 11:07:50.442687 [4] AVG Duty = 5093%(X100)
2273 11:07:50.442768
2274 11:07:50.446083 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2275 11:07:50.446163
2276 11:07:50.449320 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2277 11:07:50.453392 [DutyScan_Calibration_Flow] ====Done====
2278 11:07:50.453473
2279 11:07:50.456013 [DutyScan_Calibration_Flow] k_type=2
2280 11:07:50.470876
2281 11:07:50.470957 ==DQ 0 ==
2282 11:07:50.474309 Final DQ duty delay cell = -4
2283 11:07:50.477117 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2284 11:07:50.481080 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2285 11:07:50.484105 [-4] AVG Duty = 4937%(X100)
2286 11:07:50.484185
2287 11:07:50.484248 ==DQ 1 ==
2288 11:07:50.487488 Final DQ duty delay cell = -4
2289 11:07:50.490748 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2290 11:07:50.493709 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2291 11:07:50.497742 [-4] AVG Duty = 4984%(X100)
2292 11:07:50.497822
2293 11:07:50.500331 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2294 11:07:50.500412
2295 11:07:50.503817 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2296 11:07:50.507139 [DutyScan_Calibration_Flow] ====Done====
2297 11:07:50.507221 ==
2298 11:07:50.510445 Dram Type= 6, Freq= 0, CH_1, rank 0
2299 11:07:50.513736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2300 11:07:50.513818 ==
2301 11:07:50.517658 [Duty_Offset_Calibration]
2302 11:07:50.517754 B0:0 B1:5 CA:-5
2303 11:07:50.517851
2304 11:07:50.520441 [DutyScan_Calibration_Flow] k_type=0
2305 11:07:50.531923
2306 11:07:50.532005 ==CLK 0==
2307 11:07:50.534818 Final CLK duty delay cell = 0
2308 11:07:50.538443 [0] MAX Duty = 5094%(X100), DQS PI = 24
2309 11:07:50.541575 [0] MIN Duty = 4875%(X100), DQS PI = 46
2310 11:07:50.541657 [0] AVG Duty = 4984%(X100)
2311 11:07:50.544613
2312 11:07:50.548238 CH1 CLK Duty spec in!! Max-Min= 219%
2313 11:07:50.551623 [DutyScan_Calibration_Flow] ====Done====
2314 11:07:50.551704
2315 11:07:50.554435 [DutyScan_Calibration_Flow] k_type=1
2316 11:07:50.569696
2317 11:07:50.569776 ==DQS 0 ==
2318 11:07:50.573579 Final DQS duty delay cell = 0
2319 11:07:50.576420 [0] MAX Duty = 5125%(X100), DQS PI = 16
2320 11:07:50.580833 [0] MIN Duty = 4875%(X100), DQS PI = 40
2321 11:07:50.583225 [0] AVG Duty = 5000%(X100)
2322 11:07:50.583305
2323 11:07:50.583368 ==DQS 1 ==
2324 11:07:50.586597 Final DQS duty delay cell = -4
2325 11:07:50.589894 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2326 11:07:50.592903 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2327 11:07:50.596400 [-4] AVG Duty = 4953%(X100)
2328 11:07:50.596481
2329 11:07:50.599446 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2330 11:07:50.599526
2331 11:07:50.603127 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2332 11:07:50.606822 [DutyScan_Calibration_Flow] ====Done====
2333 11:07:50.606903
2334 11:07:50.609507 [DutyScan_Calibration_Flow] k_type=3
2335 11:07:50.626319
2336 11:07:50.626400 ==DQM 0 ==
2337 11:07:50.628418 Final DQM duty delay cell = -4
2338 11:07:50.631928 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2339 11:07:50.635119 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2340 11:07:50.638576 [-4] AVG Duty = 4953%(X100)
2341 11:07:50.638728
2342 11:07:50.638806 ==DQM 1 ==
2343 11:07:50.642562 Final DQM duty delay cell = -4
2344 11:07:50.644634 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2345 11:07:50.650205 [-4] MIN Duty = 4906%(X100), DQS PI = 58
2346 11:07:50.651111 [-4] AVG Duty = 5000%(X100)
2347 11:07:50.651191
2348 11:07:50.655283 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2349 11:07:50.655363
2350 11:07:50.657896 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2351 11:07:50.661520 [DutyScan_Calibration_Flow] ====Done====
2352 11:07:50.661600
2353 11:07:50.665859 [DutyScan_Calibration_Flow] k_type=2
2354 11:07:50.682459
2355 11:07:50.682540 ==DQ 0 ==
2356 11:07:50.687675 Final DQ duty delay cell = 0
2357 11:07:50.688891 [0] MAX Duty = 5062%(X100), DQS PI = 0
2358 11:07:50.692484 [0] MIN Duty = 4938%(X100), DQS PI = 44
2359 11:07:50.692565 [0] AVG Duty = 5000%(X100)
2360 11:07:50.692629
2361 11:07:50.695935 ==DQ 1 ==
2362 11:07:50.698853 Final DQ duty delay cell = 0
2363 11:07:50.701940 [0] MAX Duty = 5000%(X100), DQS PI = 6
2364 11:07:50.705669 [0] MIN Duty = 4907%(X100), DQS PI = 0
2365 11:07:50.705748 [0] AVG Duty = 4953%(X100)
2366 11:07:50.705811
2367 11:07:50.708696 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2368 11:07:50.708782
2369 11:07:50.712470 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2370 11:07:50.716043 [DutyScan_Calibration_Flow] ====Done====
2371 11:07:50.722338 nWR fixed to 30
2372 11:07:50.724945 [ModeRegInit_LP4] CH0 RK0
2373 11:07:50.725025 [ModeRegInit_LP4] CH0 RK1
2374 11:07:50.728345 [ModeRegInit_LP4] CH1 RK0
2375 11:07:50.731163 [ModeRegInit_LP4] CH1 RK1
2376 11:07:50.731242 match AC timing 6
2377 11:07:50.738114 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2378 11:07:50.741035 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2379 11:07:50.744037 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2380 11:07:50.750569 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2381 11:07:50.754241 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2382 11:07:50.754321 ==
2383 11:07:50.757426 Dram Type= 6, Freq= 0, CH_0, rank 0
2384 11:07:50.760842 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2385 11:07:50.760922 ==
2386 11:07:50.767735 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2387 11:07:50.774158 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2388 11:07:50.781773 [CA 0] Center 39 (9~70) winsize 62
2389 11:07:50.784901 [CA 1] Center 39 (8~70) winsize 63
2390 11:07:50.788143 [CA 2] Center 36 (5~67) winsize 63
2391 11:07:50.791911 [CA 3] Center 35 (4~66) winsize 63
2392 11:07:50.795029 [CA 4] Center 34 (3~65) winsize 63
2393 11:07:50.798126 [CA 5] Center 33 (3~64) winsize 62
2394 11:07:50.798206
2395 11:07:50.801932 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2396 11:07:50.802012
2397 11:07:50.805083 [CATrainingPosCal] consider 1 rank data
2398 11:07:50.808650 u2DelayCellTimex100 = 270/100 ps
2399 11:07:50.811417 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2400 11:07:50.815087 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2401 11:07:50.821944 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2402 11:07:50.824932 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2403 11:07:50.828047 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2404 11:07:50.831526 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2405 11:07:50.831606
2406 11:07:50.834844 CA PerBit enable=1, Macro0, CA PI delay=33
2407 11:07:50.834923
2408 11:07:50.838155 [CBTSetCACLKResult] CA Dly = 33
2409 11:07:50.838234 CS Dly: 7 (0~38)
2410 11:07:50.841653 ==
2411 11:07:50.844955 Dram Type= 6, Freq= 0, CH_0, rank 1
2412 11:07:50.848817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2413 11:07:50.848897 ==
2414 11:07:50.851366 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2415 11:07:50.857937 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2416 11:07:50.866865 [CA 0] Center 39 (8~70) winsize 63
2417 11:07:50.871224 [CA 1] Center 39 (8~70) winsize 63
2418 11:07:50.873735 [CA 2] Center 36 (5~67) winsize 63
2419 11:07:50.877205 [CA 3] Center 35 (4~66) winsize 63
2420 11:07:50.880421 [CA 4] Center 33 (3~64) winsize 62
2421 11:07:50.883744 [CA 5] Center 34 (3~65) winsize 63
2422 11:07:50.883824
2423 11:07:50.887195 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2424 11:07:50.887275
2425 11:07:50.890542 [CATrainingPosCal] consider 2 rank data
2426 11:07:50.893648 u2DelayCellTimex100 = 270/100 ps
2427 11:07:50.897355 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2428 11:07:50.900363 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2429 11:07:50.906851 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2430 11:07:50.910771 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2431 11:07:50.913483 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2432 11:07:50.916700 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2433 11:07:50.916801
2434 11:07:50.920764 CA PerBit enable=1, Macro0, CA PI delay=33
2435 11:07:50.920845
2436 11:07:50.924011 [CBTSetCACLKResult] CA Dly = 33
2437 11:07:50.924091 CS Dly: 7 (0~39)
2438 11:07:50.927165
2439 11:07:50.930138 ----->DramcWriteLeveling(PI) begin...
2440 11:07:50.930220 ==
2441 11:07:50.934195 Dram Type= 6, Freq= 0, CH_0, rank 0
2442 11:07:50.936885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2443 11:07:50.936965 ==
2444 11:07:50.940088 Write leveling (Byte 0): 27 => 27
2445 11:07:50.943911 Write leveling (Byte 1): 27 => 27
2446 11:07:50.946739 DramcWriteLeveling(PI) end<-----
2447 11:07:50.946819
2448 11:07:50.946883 ==
2449 11:07:50.950486 Dram Type= 6, Freq= 0, CH_0, rank 0
2450 11:07:50.954059 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2451 11:07:50.954140 ==
2452 11:07:50.956532 [Gating] SW mode calibration
2453 11:07:50.963426 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2454 11:07:50.969868 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2455 11:07:50.973946 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2456 11:07:50.976893 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2457 11:07:50.984151 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2458 11:07:50.986926 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2459 11:07:50.990082 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2460 11:07:50.996477 0 11 20 | B1->B0 | 2f2f 2c2c | 1 1 | (1 0) (1 0)
2461 11:07:51.000256 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2462 11:07:51.003262 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2463 11:07:51.006516 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2464 11:07:51.013238 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2465 11:07:51.016680 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2466 11:07:51.019679 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2467 11:07:51.026786 0 12 16 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2468 11:07:51.030164 0 12 20 | B1->B0 | 3a3a 3c3c | 0 0 | (0 0) (0 0)
2469 11:07:51.033240 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2470 11:07:51.040180 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2471 11:07:51.043632 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2472 11:07:51.047208 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2473 11:07:51.053103 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2474 11:07:51.056481 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2475 11:07:51.059921 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2476 11:07:51.066438 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2477 11:07:51.070543 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2478 11:07:51.073014 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2479 11:07:51.080139 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 11:07:51.083240 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2481 11:07:51.086861 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2482 11:07:51.093744 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2483 11:07:51.096436 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2484 11:07:51.100259 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2485 11:07:51.106333 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2486 11:07:51.109493 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2487 11:07:51.113264 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2488 11:07:51.119573 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2489 11:07:51.123092 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2490 11:07:51.126760 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2491 11:07:51.129944 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2492 11:07:51.136309 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2493 11:07:51.139805 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2494 11:07:51.142979 Total UI for P1: 0, mck2ui 16
2495 11:07:51.145979 best dqsien dly found for B0: ( 0, 15, 18)
2496 11:07:51.149486 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2497 11:07:51.152497 Total UI for P1: 0, mck2ui 16
2498 11:07:51.155870 best dqsien dly found for B1: ( 0, 15, 20)
2499 11:07:51.159880 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2500 11:07:51.166330 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2501 11:07:51.166411
2502 11:07:51.170521 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2503 11:07:51.172906 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2504 11:07:51.176105 [Gating] SW calibration Done
2505 11:07:51.176186 ==
2506 11:07:51.179818 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 11:07:51.183021 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2508 11:07:51.183103 ==
2509 11:07:51.183168 RX Vref Scan: 0
2510 11:07:51.183228
2511 11:07:51.186568 RX Vref 0 -> 0, step: 1
2512 11:07:51.186650
2513 11:07:51.189838 RX Delay -40 -> 252, step: 8
2514 11:07:51.192719 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2515 11:07:51.196509 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2516 11:07:51.203234 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2517 11:07:51.206516 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2518 11:07:51.209100 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2519 11:07:51.212617 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2520 11:07:51.215844 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2521 11:07:51.222626 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2522 11:07:51.225745 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2523 11:07:51.229142 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2524 11:07:51.234093 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2525 11:07:51.236246 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2526 11:07:51.243054 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2527 11:07:51.245946 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2528 11:07:51.249143 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2529 11:07:51.252266 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2530 11:07:51.252348 ==
2531 11:07:51.256527 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 11:07:51.262549 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2533 11:07:51.262630 ==
2534 11:07:51.262694 DQS Delay:
2535 11:07:51.265559 DQS0 = 0, DQS1 = 0
2536 11:07:51.265640 DQM Delay:
2537 11:07:51.265705 DQM0 = 115, DQM1 = 106
2538 11:07:51.269531 DQ Delay:
2539 11:07:51.272639 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2540 11:07:51.276617 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2541 11:07:51.278999 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2542 11:07:51.283119 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2543 11:07:51.283201
2544 11:07:51.283265
2545 11:07:51.283324 ==
2546 11:07:51.285470 Dram Type= 6, Freq= 0, CH_0, rank 0
2547 11:07:51.289043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2548 11:07:51.292192 ==
2549 11:07:51.292273
2550 11:07:51.292337
2551 11:07:51.292396 TX Vref Scan disable
2552 11:07:51.295894 == TX Byte 0 ==
2553 11:07:51.298816 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2554 11:07:51.302505 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2555 11:07:51.305796 == TX Byte 1 ==
2556 11:07:51.309336 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2557 11:07:51.312535 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2558 11:07:51.312643 ==
2559 11:07:51.315757 Dram Type= 6, Freq= 0, CH_0, rank 0
2560 11:07:51.322997 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2561 11:07:51.323078 ==
2562 11:07:51.332624 TX Vref=22, minBit 10, minWin=25, winSum=416
2563 11:07:51.336404 TX Vref=24, minBit 8, minWin=25, winSum=428
2564 11:07:51.339505 TX Vref=26, minBit 8, minWin=26, winSum=433
2565 11:07:51.342553 TX Vref=28, minBit 8, minWin=25, winSum=430
2566 11:07:51.345896 TX Vref=30, minBit 10, minWin=26, winSum=435
2567 11:07:51.352774 TX Vref=32, minBit 8, minWin=26, winSum=435
2568 11:07:51.356452 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 30
2569 11:07:51.356533
2570 11:07:51.359507 Final TX Range 1 Vref 30
2571 11:07:51.359589
2572 11:07:51.359653 ==
2573 11:07:51.362852 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 11:07:51.366707 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2575 11:07:51.369126 ==
2576 11:07:51.369207
2577 11:07:51.369271
2578 11:07:51.369331 TX Vref Scan disable
2579 11:07:51.372578 == TX Byte 0 ==
2580 11:07:51.376071 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2581 11:07:51.382597 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2582 11:07:51.382679 == TX Byte 1 ==
2583 11:07:51.386014 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2584 11:07:51.392717 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2585 11:07:51.392800
2586 11:07:51.392865 [DATLAT]
2587 11:07:51.392926 Freq=1200, CH0 RK0
2588 11:07:51.392983
2589 11:07:51.396123 DATLAT Default: 0xd
2590 11:07:51.396205 0, 0xFFFF, sum = 0
2591 11:07:51.399340 1, 0xFFFF, sum = 0
2592 11:07:51.402600 2, 0xFFFF, sum = 0
2593 11:07:51.402683 3, 0xFFFF, sum = 0
2594 11:07:51.405784 4, 0xFFFF, sum = 0
2595 11:07:51.405867 5, 0xFFFF, sum = 0
2596 11:07:51.409155 6, 0xFFFF, sum = 0
2597 11:07:51.409238 7, 0xFFFF, sum = 0
2598 11:07:51.412985 8, 0xFFFF, sum = 0
2599 11:07:51.413067 9, 0xFFFF, sum = 0
2600 11:07:51.415668 10, 0xFFFF, sum = 0
2601 11:07:51.415754 11, 0x0, sum = 1
2602 11:07:51.419597 12, 0x0, sum = 2
2603 11:07:51.419678 13, 0x0, sum = 3
2604 11:07:51.422410 14, 0x0, sum = 4
2605 11:07:51.422492 best_step = 12
2606 11:07:51.422556
2607 11:07:51.422615 ==
2608 11:07:51.426031 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 11:07:51.429355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2610 11:07:51.429436 ==
2611 11:07:51.432685 RX Vref Scan: 1
2612 11:07:51.432803
2613 11:07:51.436303 Set Vref Range= 32 -> 127
2614 11:07:51.436383
2615 11:07:51.436446 RX Vref 32 -> 127, step: 1
2616 11:07:51.436504
2617 11:07:51.439661 RX Delay -21 -> 252, step: 4
2618 11:07:51.439741
2619 11:07:51.442634 Set Vref, RX VrefLevel [Byte0]: 32
2620 11:07:51.445736 [Byte1]: 32
2621 11:07:51.450063
2622 11:07:51.450142 Set Vref, RX VrefLevel [Byte0]: 33
2623 11:07:51.452552 [Byte1]: 33
2624 11:07:51.457552
2625 11:07:51.457632 Set Vref, RX VrefLevel [Byte0]: 34
2626 11:07:51.461336 [Byte1]: 34
2627 11:07:51.465625
2628 11:07:51.465705 Set Vref, RX VrefLevel [Byte0]: 35
2629 11:07:51.468658 [Byte1]: 35
2630 11:07:51.473544
2631 11:07:51.473624 Set Vref, RX VrefLevel [Byte0]: 36
2632 11:07:51.476316 [Byte1]: 36
2633 11:07:51.481224
2634 11:07:51.481305 Set Vref, RX VrefLevel [Byte0]: 37
2635 11:07:51.485719 [Byte1]: 37
2636 11:07:51.489527
2637 11:07:51.489612 Set Vref, RX VrefLevel [Byte0]: 38
2638 11:07:51.492835 [Byte1]: 38
2639 11:07:51.497234
2640 11:07:51.497318 Set Vref, RX VrefLevel [Byte0]: 39
2641 11:07:51.500232 [Byte1]: 39
2642 11:07:51.504993
2643 11:07:51.505073 Set Vref, RX VrefLevel [Byte0]: 40
2644 11:07:51.508437 [Byte1]: 40
2645 11:07:51.513500
2646 11:07:51.513579 Set Vref, RX VrefLevel [Byte0]: 41
2647 11:07:51.516356 [Byte1]: 41
2648 11:07:51.520919
2649 11:07:51.520998 Set Vref, RX VrefLevel [Byte0]: 42
2650 11:07:51.523931 [Byte1]: 42
2651 11:07:51.528596
2652 11:07:51.528676 Set Vref, RX VrefLevel [Byte0]: 43
2653 11:07:51.532564 [Byte1]: 43
2654 11:07:51.536835
2655 11:07:51.540599 Set Vref, RX VrefLevel [Byte0]: 44
2656 11:07:51.543701 [Byte1]: 44
2657 11:07:51.543781
2658 11:07:51.546487 Set Vref, RX VrefLevel [Byte0]: 45
2659 11:07:51.549694 [Byte1]: 45
2660 11:07:51.549775
2661 11:07:51.553533 Set Vref, RX VrefLevel [Byte0]: 46
2662 11:07:51.556497 [Byte1]: 46
2663 11:07:51.560562
2664 11:07:51.560641 Set Vref, RX VrefLevel [Byte0]: 47
2665 11:07:51.564412 [Byte1]: 47
2666 11:07:51.568046
2667 11:07:51.568126 Set Vref, RX VrefLevel [Byte0]: 48
2668 11:07:51.572651 [Byte1]: 48
2669 11:07:51.577151
2670 11:07:51.577231 Set Vref, RX VrefLevel [Byte0]: 49
2671 11:07:51.579653 [Byte1]: 49
2672 11:07:51.584284
2673 11:07:51.584365 Set Vref, RX VrefLevel [Byte0]: 50
2674 11:07:51.587522 [Byte1]: 50
2675 11:07:51.592331
2676 11:07:51.592411 Set Vref, RX VrefLevel [Byte0]: 51
2677 11:07:51.595513 [Byte1]: 51
2678 11:07:51.599830
2679 11:07:51.599910 Set Vref, RX VrefLevel [Byte0]: 52
2680 11:07:51.603167 [Byte1]: 52
2681 11:07:51.608022
2682 11:07:51.608102 Set Vref, RX VrefLevel [Byte0]: 53
2683 11:07:51.611309 [Byte1]: 53
2684 11:07:51.616483
2685 11:07:51.616563 Set Vref, RX VrefLevel [Byte0]: 54
2686 11:07:51.619089 [Byte1]: 54
2687 11:07:51.624729
2688 11:07:51.624836 Set Vref, RX VrefLevel [Byte0]: 55
2689 11:07:51.627478 [Byte1]: 55
2690 11:07:51.631601
2691 11:07:51.631681 Set Vref, RX VrefLevel [Byte0]: 56
2692 11:07:51.634965 [Byte1]: 56
2693 11:07:51.639316
2694 11:07:51.639396 Set Vref, RX VrefLevel [Byte0]: 57
2695 11:07:51.644050 [Byte1]: 57
2696 11:07:51.647852
2697 11:07:51.647931 Set Vref, RX VrefLevel [Byte0]: 58
2698 11:07:51.651136 [Byte1]: 58
2699 11:07:51.655518
2700 11:07:51.655598 Set Vref, RX VrefLevel [Byte0]: 59
2701 11:07:51.659580 [Byte1]: 59
2702 11:07:51.663283
2703 11:07:51.663362 Set Vref, RX VrefLevel [Byte0]: 60
2704 11:07:51.667005 [Byte1]: 60
2705 11:07:51.671331
2706 11:07:51.671420 Set Vref, RX VrefLevel [Byte0]: 61
2707 11:07:51.674654 [Byte1]: 61
2708 11:07:51.679038
2709 11:07:51.679137 Set Vref, RX VrefLevel [Byte0]: 62
2710 11:07:51.682440 [Byte1]: 62
2711 11:07:51.687302
2712 11:07:51.687421 Set Vref, RX VrefLevel [Byte0]: 63
2713 11:07:51.690465 [Byte1]: 63
2714 11:07:51.695724
2715 11:07:51.695856 Set Vref, RX VrefLevel [Byte0]: 64
2716 11:07:51.698318 [Byte1]: 64
2717 11:07:51.703061
2718 11:07:51.703230 Set Vref, RX VrefLevel [Byte0]: 65
2719 11:07:51.706816 [Byte1]: 65
2720 11:07:51.711148
2721 11:07:51.711343 Final RX Vref Byte 0 = 53 to rank0
2722 11:07:51.714380 Final RX Vref Byte 1 = 48 to rank0
2723 11:07:51.717715 Final RX Vref Byte 0 = 53 to rank1
2724 11:07:51.721318 Final RX Vref Byte 1 = 48 to rank1==
2725 11:07:51.724815 Dram Type= 6, Freq= 0, CH_0, rank 0
2726 11:07:51.731506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2727 11:07:51.731921 ==
2728 11:07:51.732248 DQS Delay:
2729 11:07:51.732553 DQS0 = 0, DQS1 = 0
2730 11:07:51.735504 DQM Delay:
2731 11:07:51.735913 DQM0 = 114, DQM1 = 105
2732 11:07:51.739140 DQ Delay:
2733 11:07:51.741275 DQ0 =112, DQ1 =114, DQ2 =114, DQ3 =110
2734 11:07:51.744880 DQ4 =118, DQ5 =106, DQ6 =122, DQ7 =120
2735 11:07:51.747928 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2736 11:07:51.751836 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2737 11:07:51.752263
2738 11:07:51.752638
2739 11:07:51.757744 [DQSOSCAuto] RK0, (LSB)MR18= 0x707, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2740 11:07:51.761988 CH0 RK0: MR19=404, MR18=707
2741 11:07:51.768114 CH0_RK0: MR19=0x404, MR18=0x707, DQSOSC=407, MR23=63, INC=39, DEC=26
2742 11:07:51.768530
2743 11:07:51.771664 ----->DramcWriteLeveling(PI) begin...
2744 11:07:51.772083 ==
2745 11:07:51.774381 Dram Type= 6, Freq= 0, CH_0, rank 1
2746 11:07:51.778036 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2747 11:07:51.778451 ==
2748 11:07:51.780881 Write leveling (Byte 0): 29 => 29
2749 11:07:51.784827 Write leveling (Byte 1): 24 => 24
2750 11:07:51.787922 DramcWriteLeveling(PI) end<-----
2751 11:07:51.788332
2752 11:07:51.788659 ==
2753 11:07:51.791096 Dram Type= 6, Freq= 0, CH_0, rank 1
2754 11:07:51.797991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2755 11:07:51.798409 ==
2756 11:07:51.798739 [Gating] SW mode calibration
2757 11:07:51.807850 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2758 11:07:51.811099 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2759 11:07:51.814484 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2760 11:07:51.821366 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2761 11:07:51.824468 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2762 11:07:51.827443 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2763 11:07:51.834306 0 11 16 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
2764 11:07:51.837726 0 11 20 | B1->B0 | 2b2b 2424 | 1 0 | (1 0) (0 0)
2765 11:07:51.840827 0 11 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2766 11:07:51.848525 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2767 11:07:51.850731 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2768 11:07:51.855076 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2769 11:07:51.861022 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2770 11:07:51.864325 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2771 11:07:51.867579 0 12 16 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
2772 11:07:51.874316 0 12 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2773 11:07:51.878409 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2774 11:07:51.880916 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2775 11:07:51.888414 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2776 11:07:51.890986 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2777 11:07:51.894047 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2778 11:07:51.901453 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2779 11:07:51.904241 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2780 11:07:51.907731 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2781 11:07:51.910935 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 11:07:51.917490 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2783 11:07:51.921669 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 11:07:51.924068 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 11:07:51.931640 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2786 11:07:51.935047 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2787 11:07:51.937869 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2788 11:07:51.944783 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2789 11:07:51.948499 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2790 11:07:51.950807 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2791 11:07:51.957690 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2792 11:07:51.960814 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2793 11:07:51.964166 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2794 11:07:51.970987 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2795 11:07:51.975766 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2796 11:07:51.978263 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2797 11:07:51.981749 Total UI for P1: 0, mck2ui 16
2798 11:07:51.984463 best dqsien dly found for B0: ( 0, 15, 16)
2799 11:07:51.988399 Total UI for P1: 0, mck2ui 16
2800 11:07:51.991285 best dqsien dly found for B1: ( 0, 15, 18)
2801 11:07:51.994258 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2802 11:07:51.997485 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2803 11:07:51.997904
2804 11:07:52.000974 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2805 11:07:52.007817 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2806 11:07:52.008235 [Gating] SW calibration Done
2807 11:07:52.008568 ==
2808 11:07:52.011389 Dram Type= 6, Freq= 0, CH_0, rank 1
2809 11:07:52.017640 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2810 11:07:52.018060 ==
2811 11:07:52.018394 RX Vref Scan: 0
2812 11:07:52.018705
2813 11:07:52.021174 RX Vref 0 -> 0, step: 1
2814 11:07:52.021595
2815 11:07:52.024264 RX Delay -40 -> 252, step: 8
2816 11:07:52.027593 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2817 11:07:52.030928 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2818 11:07:52.034903 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2819 11:07:52.041217 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2820 11:07:52.044439 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2821 11:07:52.047542 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2822 11:07:52.050849 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2823 11:07:52.054556 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2824 11:07:52.057679 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2825 11:07:52.064755 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2826 11:07:52.068096 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2827 11:07:52.071858 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2828 11:07:52.074366 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2829 11:07:52.077388 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2830 11:07:52.084834 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2831 11:07:52.087433 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2832 11:07:52.088023 ==
2833 11:07:52.091181 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 11:07:52.094080 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2835 11:07:52.094615 ==
2836 11:07:52.097428 DQS Delay:
2837 11:07:52.097924 DQS0 = 0, DQS1 = 0
2838 11:07:52.098361 DQM Delay:
2839 11:07:52.100838 DQM0 = 115, DQM1 = 107
2840 11:07:52.101444 DQ Delay:
2841 11:07:52.104514 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2842 11:07:52.107349 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2843 11:07:52.111031 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2844 11:07:52.117474 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2845 11:07:52.118072
2846 11:07:52.118636
2847 11:07:52.119151 ==
2848 11:07:52.121085 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 11:07:52.124406 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2850 11:07:52.125010 ==
2851 11:07:52.125426
2852 11:07:52.125830
2853 11:07:52.127981 TX Vref Scan disable
2854 11:07:52.128435 == TX Byte 0 ==
2855 11:07:52.134546 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2856 11:07:52.137614 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2857 11:07:52.138033 == TX Byte 1 ==
2858 11:07:52.144837 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2859 11:07:52.147703 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2860 11:07:52.148122 ==
2861 11:07:52.151089 Dram Type= 6, Freq= 0, CH_0, rank 1
2862 11:07:52.154427 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2863 11:07:52.154847 ==
2864 11:07:52.167203 TX Vref=22, minBit 9, minWin=24, winSum=418
2865 11:07:52.170466 TX Vref=24, minBit 8, minWin=25, winSum=425
2866 11:07:52.174804 TX Vref=26, minBit 8, minWin=25, winSum=426
2867 11:07:52.177658 TX Vref=28, minBit 10, minWin=25, winSum=431
2868 11:07:52.181049 TX Vref=30, minBit 10, minWin=25, winSum=432
2869 11:07:52.187557 TX Vref=32, minBit 8, minWin=25, winSum=431
2870 11:07:52.190866 [TxChooseVref] Worse bit 10, Min win 25, Win sum 432, Final Vref 30
2871 11:07:52.191289
2872 11:07:52.193717 Final TX Range 1 Vref 30
2873 11:07:52.194139
2874 11:07:52.194473 ==
2875 11:07:52.196928 Dram Type= 6, Freq= 0, CH_0, rank 1
2876 11:07:52.201171 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2877 11:07:52.203709 ==
2878 11:07:52.204127
2879 11:07:52.204455
2880 11:07:52.204795 TX Vref Scan disable
2881 11:07:52.206837 == TX Byte 0 ==
2882 11:07:52.211118 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2883 11:07:52.216826 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2884 11:07:52.217252 == TX Byte 1 ==
2885 11:07:52.220848 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2886 11:07:52.227148 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2887 11:07:52.227565
2888 11:07:52.227998 [DATLAT]
2889 11:07:52.228321 Freq=1200, CH0 RK1
2890 11:07:52.228627
2891 11:07:52.230197 DATLAT Default: 0xc
2892 11:07:52.230670 0, 0xFFFF, sum = 0
2893 11:07:52.234648 1, 0xFFFF, sum = 0
2894 11:07:52.235078 2, 0xFFFF, sum = 0
2895 11:07:52.237158 3, 0xFFFF, sum = 0
2896 11:07:52.240357 4, 0xFFFF, sum = 0
2897 11:07:52.240854 5, 0xFFFF, sum = 0
2898 11:07:52.243866 6, 0xFFFF, sum = 0
2899 11:07:52.244291 7, 0xFFFF, sum = 0
2900 11:07:52.247209 8, 0xFFFF, sum = 0
2901 11:07:52.247847 9, 0xFFFF, sum = 0
2902 11:07:52.250332 10, 0xFFFF, sum = 0
2903 11:07:52.250918 11, 0x0, sum = 1
2904 11:07:52.253816 12, 0x0, sum = 2
2905 11:07:52.254295 13, 0x0, sum = 3
2906 11:07:52.256800 14, 0x0, sum = 4
2907 11:07:52.257359 best_step = 12
2908 11:07:52.257904
2909 11:07:52.258403 ==
2910 11:07:52.260570 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 11:07:52.263584 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2912 11:07:52.264206 ==
2913 11:07:52.267120 RX Vref Scan: 0
2914 11:07:52.267679
2915 11:07:52.270344 RX Vref 0 -> 0, step: 1
2916 11:07:52.270793
2917 11:07:52.271166 RX Delay -21 -> 252, step: 4
2918 11:07:52.277743 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2919 11:07:52.280772 iDelay=199, Bit 1, Center 114 (43 ~ 186) 144
2920 11:07:52.284673 iDelay=199, Bit 2, Center 112 (43 ~ 182) 140
2921 11:07:52.287987 iDelay=199, Bit 3, Center 110 (39 ~ 182) 144
2922 11:07:52.291111 iDelay=199, Bit 4, Center 120 (47 ~ 194) 148
2923 11:07:52.297591 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2924 11:07:52.302427 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2925 11:07:52.304542 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2926 11:07:52.307872 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2927 11:07:52.311256 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2928 11:07:52.317122 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2929 11:07:52.320925 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2930 11:07:52.325252 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2931 11:07:52.327873 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2932 11:07:52.331188 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2933 11:07:52.337733 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2934 11:07:52.338337 ==
2935 11:07:52.340750 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 11:07:52.344488 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2937 11:07:52.345112 ==
2938 11:07:52.345564 DQS Delay:
2939 11:07:52.347955 DQS0 = 0, DQS1 = 0
2940 11:07:52.348452 DQM Delay:
2941 11:07:52.351003 DQM0 = 115, DQM1 = 105
2942 11:07:52.351513 DQ Delay:
2943 11:07:52.355564 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =110
2944 11:07:52.357379 DQ4 =120, DQ5 =108, DQ6 =122, DQ7 =124
2945 11:07:52.361242 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2946 11:07:52.364115 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2947 11:07:52.364520
2948 11:07:52.364902
2949 11:07:52.374853 [DQSOSCAuto] RK1, (LSB)MR18= 0xa0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2950 11:07:52.377789 CH0 RK1: MR19=404, MR18=A0A
2951 11:07:52.380813 CH0_RK1: MR19=0x404, MR18=0xA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
2952 11:07:52.384411 [RxdqsGatingPostProcess] freq 1200
2953 11:07:52.390963 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2954 11:07:52.394446 Pre-setting of DQS Precalculation
2955 11:07:52.397398 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2956 11:07:52.397843 ==
2957 11:07:52.400620 Dram Type= 6, Freq= 0, CH_1, rank 0
2958 11:07:52.407814 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2959 11:07:52.408440 ==
2960 11:07:52.410684 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2961 11:07:52.417371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2962 11:07:52.426151 [CA 0] Center 37 (7~68) winsize 62
2963 11:07:52.429797 [CA 1] Center 37 (7~68) winsize 62
2964 11:07:52.432738 [CA 2] Center 34 (4~65) winsize 62
2965 11:07:52.435918 [CA 3] Center 33 (3~64) winsize 62
2966 11:07:52.439233 [CA 4] Center 32 (2~63) winsize 62
2967 11:07:52.442393 [CA 5] Center 32 (2~63) winsize 62
2968 11:07:52.443021
2969 11:07:52.445915 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2970 11:07:52.446433
2971 11:07:52.449242 [CATrainingPosCal] consider 1 rank data
2972 11:07:52.453416 u2DelayCellTimex100 = 270/100 ps
2973 11:07:52.455655 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2974 11:07:52.459237 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2975 11:07:52.466021 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2976 11:07:52.469198 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2977 11:07:52.472783 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2978 11:07:52.475675 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2979 11:07:52.476106
2980 11:07:52.479041 CA PerBit enable=1, Macro0, CA PI delay=32
2981 11:07:52.479484
2982 11:07:52.482209 [CBTSetCACLKResult] CA Dly = 32
2983 11:07:52.482702 CS Dly: 5 (0~36)
2984 11:07:52.486163 ==
2985 11:07:52.486597 Dram Type= 6, Freq= 0, CH_1, rank 1
2986 11:07:52.492330 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2987 11:07:52.492969 ==
2988 11:07:52.495775 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2989 11:07:52.502254 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2990 11:07:52.511795 [CA 0] Center 37 (7~68) winsize 62
2991 11:07:52.515628 [CA 1] Center 37 (6~68) winsize 63
2992 11:07:52.518507 [CA 2] Center 34 (3~65) winsize 63
2993 11:07:52.522010 [CA 3] Center 33 (3~64) winsize 62
2994 11:07:52.524524 [CA 4] Center 32 (2~63) winsize 62
2995 11:07:52.527796 [CA 5] Center 32 (2~63) winsize 62
2996 11:07:52.528303
2997 11:07:52.531250 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2998 11:07:52.531750
2999 11:07:52.535495 [CATrainingPosCal] consider 2 rank data
3000 11:07:52.537985 u2DelayCellTimex100 = 270/100 ps
3001 11:07:52.541267 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
3002 11:07:52.545286 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
3003 11:07:52.551044 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
3004 11:07:52.554570 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
3005 11:07:52.557753 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3006 11:07:52.561395 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3007 11:07:52.561998
3008 11:07:52.564122 CA PerBit enable=1, Macro0, CA PI delay=32
3009 11:07:52.564736
3010 11:07:52.567853 [CBTSetCACLKResult] CA Dly = 32
3011 11:07:52.568406 CS Dly: 6 (0~38)
3012 11:07:52.568979
3013 11:07:52.571336 ----->DramcWriteLeveling(PI) begin...
3014 11:07:52.575091 ==
3015 11:07:52.577893 Dram Type= 6, Freq= 0, CH_1, rank 0
3016 11:07:52.581455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3017 11:07:52.581957 ==
3018 11:07:52.584288 Write leveling (Byte 0): 21 => 21
3019 11:07:52.587481 Write leveling (Byte 1): 22 => 22
3020 11:07:52.591678 DramcWriteLeveling(PI) end<-----
3021 11:07:52.592208
3022 11:07:52.592787 ==
3023 11:07:52.595354 Dram Type= 6, Freq= 0, CH_1, rank 0
3024 11:07:52.597971 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3025 11:07:52.598547 ==
3026 11:07:52.601536 [Gating] SW mode calibration
3027 11:07:52.607615 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3028 11:07:52.614473 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3029 11:07:52.617866 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3030 11:07:52.621383 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3031 11:07:52.624086 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3032 11:07:52.630934 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
3033 11:07:52.634956 0 11 16 | B1->B0 | 3333 2d2d | 1 0 | (1 1) (1 0)
3034 11:07:52.637824 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3035 11:07:52.644085 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3036 11:07:52.647637 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3037 11:07:52.651321 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3038 11:07:52.658573 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3039 11:07:52.660814 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3040 11:07:52.664496 0 12 12 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
3041 11:07:52.671387 0 12 16 | B1->B0 | 2e2e 3f3f | 0 0 | (0 0) (0 0)
3042 11:07:52.674588 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3043 11:07:52.677561 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3044 11:07:52.684122 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3045 11:07:52.687454 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3046 11:07:52.690761 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3047 11:07:52.698483 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3048 11:07:52.701121 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3049 11:07:52.703916 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3050 11:07:52.710756 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3051 11:07:52.714688 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3052 11:07:52.717626 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3053 11:07:52.724839 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 11:07:52.727386 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 11:07:52.730749 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 11:07:52.734155 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3057 11:07:52.740691 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3058 11:07:52.744256 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3059 11:07:52.747985 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3060 11:07:52.753895 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3061 11:07:52.758726 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3062 11:07:52.761004 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3063 11:07:52.767932 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3064 11:07:52.770751 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3065 11:07:52.773867 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3066 11:07:52.780822 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3067 11:07:52.781383 Total UI for P1: 0, mck2ui 16
3068 11:07:52.787191 best dqsien dly found for B0: ( 0, 15, 14)
3069 11:07:52.791525 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3070 11:07:52.794312 Total UI for P1: 0, mck2ui 16
3071 11:07:52.797495 best dqsien dly found for B1: ( 0, 15, 20)
3072 11:07:52.800824 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3073 11:07:52.804490 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
3074 11:07:52.805017
3075 11:07:52.807581 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3076 11:07:52.810737 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3077 11:07:52.814520 [Gating] SW calibration Done
3078 11:07:52.814962 ==
3079 11:07:52.817526 Dram Type= 6, Freq= 0, CH_1, rank 0
3080 11:07:52.821838 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3081 11:07:52.824438 ==
3082 11:07:52.824984 RX Vref Scan: 0
3083 11:07:52.825344
3084 11:07:52.827163 RX Vref 0 -> 0, step: 1
3085 11:07:52.827758
3086 11:07:52.830468 RX Delay -40 -> 252, step: 8
3087 11:07:52.833974 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3088 11:07:52.837023 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3089 11:07:52.841038 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3090 11:07:52.844119 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3091 11:07:52.850540 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3092 11:07:52.853999 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3093 11:07:52.857221 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3094 11:07:52.860555 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3095 11:07:52.863753 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3096 11:07:52.870668 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3097 11:07:52.873985 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3098 11:07:52.877477 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3099 11:07:52.880454 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3100 11:07:52.883579 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3101 11:07:52.890465 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3102 11:07:52.893810 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3103 11:07:52.894269 ==
3104 11:07:52.897040 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 11:07:52.900559 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3106 11:07:52.901071 ==
3107 11:07:52.903906 DQS Delay:
3108 11:07:52.904352 DQS0 = 0, DQS1 = 0
3109 11:07:52.904868 DQM Delay:
3110 11:07:52.907064 DQM0 = 116, DQM1 = 108
3111 11:07:52.907495 DQ Delay:
3112 11:07:52.910147 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3113 11:07:52.914019 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3114 11:07:52.917164 DQ8 =87, DQ9 =99, DQ10 =111, DQ11 =103
3115 11:07:52.924652 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3116 11:07:52.925236
3117 11:07:52.925648
3118 11:07:52.926040 ==
3119 11:07:52.926799 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 11:07:52.930981 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3121 11:07:52.931488 ==
3122 11:07:52.932032
3123 11:07:52.932429
3124 11:07:52.933222 TX Vref Scan disable
3125 11:07:52.933661 == TX Byte 0 ==
3126 11:07:52.940367 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3127 11:07:52.943388 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3128 11:07:52.944013 == TX Byte 1 ==
3129 11:07:52.950485 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3130 11:07:52.953575 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3131 11:07:52.954169 ==
3132 11:07:52.956803 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 11:07:52.960658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3134 11:07:52.961321 ==
3135 11:07:52.972487 TX Vref=22, minBit 1, minWin=25, winSum=412
3136 11:07:52.975858 TX Vref=24, minBit 0, minWin=25, winSum=419
3137 11:07:52.979581 TX Vref=26, minBit 0, minWin=26, winSum=426
3138 11:07:52.982947 TX Vref=28, minBit 15, minWin=25, winSum=430
3139 11:07:52.986072 TX Vref=30, minBit 9, minWin=25, winSum=430
3140 11:07:52.992455 TX Vref=32, minBit 3, minWin=26, winSum=430
3141 11:07:52.995616 [TxChooseVref] Worse bit 3, Min win 26, Win sum 430, Final Vref 32
3142 11:07:52.996135
3143 11:07:52.999260 Final TX Range 1 Vref 32
3144 11:07:52.999865
3145 11:07:53.000417 ==
3146 11:07:53.003033 Dram Type= 6, Freq= 0, CH_1, rank 0
3147 11:07:53.006514 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3148 11:07:53.007141 ==
3149 11:07:53.007709
3150 11:07:53.009117
3151 11:07:53.009663 TX Vref Scan disable
3152 11:07:53.012883 == TX Byte 0 ==
3153 11:07:53.015717 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3154 11:07:53.019258 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3155 11:07:53.022526 == TX Byte 1 ==
3156 11:07:53.026919 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3157 11:07:53.028953 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3158 11:07:53.032808
3159 11:07:53.033324 [DATLAT]
3160 11:07:53.033892 Freq=1200, CH1 RK0
3161 11:07:53.034412
3162 11:07:53.035557 DATLAT Default: 0xd
3163 11:07:53.036123 0, 0xFFFF, sum = 0
3164 11:07:53.039314 1, 0xFFFF, sum = 0
3165 11:07:53.039897 2, 0xFFFF, sum = 0
3166 11:07:53.042034 3, 0xFFFF, sum = 0
3167 11:07:53.045493 4, 0xFFFF, sum = 0
3168 11:07:53.046008 5, 0xFFFF, sum = 0
3169 11:07:53.048747 6, 0xFFFF, sum = 0
3170 11:07:53.049218 7, 0xFFFF, sum = 0
3171 11:07:53.052207 8, 0xFFFF, sum = 0
3172 11:07:53.052834 9, 0xFFFF, sum = 0
3173 11:07:53.055616 10, 0xFFFF, sum = 0
3174 11:07:53.056250 11, 0x0, sum = 1
3175 11:07:53.058637 12, 0x0, sum = 2
3176 11:07:53.059206 13, 0x0, sum = 3
3177 11:07:53.062157 14, 0x0, sum = 4
3178 11:07:53.062739 best_step = 12
3179 11:07:53.063261
3180 11:07:53.063782 ==
3181 11:07:53.065308 Dram Type= 6, Freq= 0, CH_1, rank 0
3182 11:07:53.068496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3183 11:07:53.068983 ==
3184 11:07:53.072374 RX Vref Scan: 1
3185 11:07:53.072841
3186 11:07:53.075315 Set Vref Range= 32 -> 127
3187 11:07:53.075745
3188 11:07:53.076097 RX Vref 32 -> 127, step: 1
3189 11:07:53.076411
3190 11:07:53.078572 RX Delay -29 -> 252, step: 4
3191 11:07:53.079005
3192 11:07:53.081785 Set Vref, RX VrefLevel [Byte0]: 32
3193 11:07:53.086163 [Byte1]: 32
3194 11:07:53.089495
3195 11:07:53.089990 Set Vref, RX VrefLevel [Byte0]: 33
3196 11:07:53.092366 [Byte1]: 33
3197 11:07:53.097352
3198 11:07:53.097802 Set Vref, RX VrefLevel [Byte0]: 34
3199 11:07:53.100353 [Byte1]: 34
3200 11:07:53.105022
3201 11:07:53.105556 Set Vref, RX VrefLevel [Byte0]: 35
3202 11:07:53.108417 [Byte1]: 35
3203 11:07:53.112976
3204 11:07:53.113421 Set Vref, RX VrefLevel [Byte0]: 36
3205 11:07:53.116342 [Byte1]: 36
3206 11:07:53.120938
3207 11:07:53.121377 Set Vref, RX VrefLevel [Byte0]: 37
3208 11:07:53.124174 [Byte1]: 37
3209 11:07:53.129119
3210 11:07:53.129634 Set Vref, RX VrefLevel [Byte0]: 38
3211 11:07:53.131804 [Byte1]: 38
3212 11:07:53.136552
3213 11:07:53.137000 Set Vref, RX VrefLevel [Byte0]: 39
3214 11:07:53.140141 [Byte1]: 39
3215 11:07:53.144948
3216 11:07:53.145397 Set Vref, RX VrefLevel [Byte0]: 40
3217 11:07:53.147886 [Byte1]: 40
3218 11:07:53.152564
3219 11:07:53.153139 Set Vref, RX VrefLevel [Byte0]: 41
3220 11:07:53.155892 [Byte1]: 41
3221 11:07:53.161027
3222 11:07:53.161490 Set Vref, RX VrefLevel [Byte0]: 42
3223 11:07:53.163912 [Byte1]: 42
3224 11:07:53.168762
3225 11:07:53.169180 Set Vref, RX VrefLevel [Byte0]: 43
3226 11:07:53.171932 [Byte1]: 43
3227 11:07:53.176761
3228 11:07:53.177327 Set Vref, RX VrefLevel [Byte0]: 44
3229 11:07:53.180204 [Byte1]: 44
3230 11:07:53.184655
3231 11:07:53.185171 Set Vref, RX VrefLevel [Byte0]: 45
3232 11:07:53.191114 [Byte1]: 45
3233 11:07:53.191529
3234 11:07:53.194376 Set Vref, RX VrefLevel [Byte0]: 46
3235 11:07:53.197378 [Byte1]: 46
3236 11:07:53.197794
3237 11:07:53.201060 Set Vref, RX VrefLevel [Byte0]: 47
3238 11:07:53.204672 [Byte1]: 47
3239 11:07:53.209068
3240 11:07:53.209483 Set Vref, RX VrefLevel [Byte0]: 48
3241 11:07:53.212288 [Byte1]: 48
3242 11:07:53.217956
3243 11:07:53.218368 Set Vref, RX VrefLevel [Byte0]: 49
3244 11:07:53.219556 [Byte1]: 49
3245 11:07:53.225136
3246 11:07:53.225663 Set Vref, RX VrefLevel [Byte0]: 50
3247 11:07:53.227842 [Byte1]: 50
3248 11:07:53.234545
3249 11:07:53.234956 Set Vref, RX VrefLevel [Byte0]: 51
3250 11:07:53.235738 [Byte1]: 51
3251 11:07:53.240189
3252 11:07:53.240675 Set Vref, RX VrefLevel [Byte0]: 52
3253 11:07:53.243926 [Byte1]: 52
3254 11:07:53.248096
3255 11:07:53.248508 Set Vref, RX VrefLevel [Byte0]: 53
3256 11:07:53.251323 [Byte1]: 53
3257 11:07:53.256349
3258 11:07:53.256802 Set Vref, RX VrefLevel [Byte0]: 54
3259 11:07:53.259201 [Byte1]: 54
3260 11:07:53.264349
3261 11:07:53.264803 Set Vref, RX VrefLevel [Byte0]: 55
3262 11:07:53.267848 [Byte1]: 55
3263 11:07:53.272537
3264 11:07:53.273000 Set Vref, RX VrefLevel [Byte0]: 56
3265 11:07:53.275767 [Byte1]: 56
3266 11:07:53.280361
3267 11:07:53.280848 Set Vref, RX VrefLevel [Byte0]: 57
3268 11:07:53.283401 [Byte1]: 57
3269 11:07:53.288027
3270 11:07:53.288442 Set Vref, RX VrefLevel [Byte0]: 58
3271 11:07:53.292031 [Byte1]: 58
3272 11:07:53.296330
3273 11:07:53.296785 Set Vref, RX VrefLevel [Byte0]: 59
3274 11:07:53.299362 [Byte1]: 59
3275 11:07:53.304174
3276 11:07:53.304685 Set Vref, RX VrefLevel [Byte0]: 60
3277 11:07:53.307472 [Byte1]: 60
3278 11:07:53.311935
3279 11:07:53.312440 Set Vref, RX VrefLevel [Byte0]: 61
3280 11:07:53.315498 [Byte1]: 61
3281 11:07:53.321397
3282 11:07:53.321907 Set Vref, RX VrefLevel [Byte0]: 62
3283 11:07:53.323473 [Byte1]: 62
3284 11:07:53.327777
3285 11:07:53.328287 Set Vref, RX VrefLevel [Byte0]: 63
3286 11:07:53.331172 [Byte1]: 63
3287 11:07:53.335975
3288 11:07:53.336486 Set Vref, RX VrefLevel [Byte0]: 64
3289 11:07:53.339700 [Byte1]: 64
3290 11:07:53.343464
3291 11:07:53.343878 Set Vref, RX VrefLevel [Byte0]: 65
3292 11:07:53.347111 [Byte1]: 65
3293 11:07:53.351552
3294 11:07:53.352013 Set Vref, RX VrefLevel [Byte0]: 66
3295 11:07:53.355644 [Byte1]: 66
3296 11:07:53.359733
3297 11:07:53.360286 Set Vref, RX VrefLevel [Byte0]: 67
3298 11:07:53.363125 [Byte1]: 67
3299 11:07:53.367996
3300 11:07:53.368555 Final RX Vref Byte 0 = 54 to rank0
3301 11:07:53.370957 Final RX Vref Byte 1 = 49 to rank0
3302 11:07:53.375176 Final RX Vref Byte 0 = 54 to rank1
3303 11:07:53.377681 Final RX Vref Byte 1 = 49 to rank1==
3304 11:07:53.381075 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 11:07:53.387824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3306 11:07:53.388404 ==
3307 11:07:53.388816 DQS Delay:
3308 11:07:53.389159 DQS0 = 0, DQS1 = 0
3309 11:07:53.390951 DQM Delay:
3310 11:07:53.391407 DQM0 = 115, DQM1 = 105
3311 11:07:53.394678 DQ Delay:
3312 11:07:53.397932 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3313 11:07:53.401195 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3314 11:07:53.404606 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3315 11:07:53.407408 DQ12 =114, DQ13 =118, DQ14 =112, DQ15 =116
3316 11:07:53.407873
3317 11:07:53.408285
3318 11:07:53.414181 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3319 11:07:53.417626 CH1 RK0: MR19=404, MR18=1717
3320 11:07:53.424365 CH1_RK0: MR19=0x404, MR18=0x1717, DQSOSC=401, MR23=63, INC=40, DEC=27
3321 11:07:53.425087
3322 11:07:53.427699 ----->DramcWriteLeveling(PI) begin...
3323 11:07:53.428256 ==
3324 11:07:53.431286 Dram Type= 6, Freq= 0, CH_1, rank 1
3325 11:07:53.433743 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3326 11:07:53.437673 ==
3327 11:07:53.438232 Write leveling (Byte 0): 21 => 21
3328 11:07:53.440887 Write leveling (Byte 1): 21 => 21
3329 11:07:53.445294 DramcWriteLeveling(PI) end<-----
3330 11:07:53.445876
3331 11:07:53.446241 ==
3332 11:07:53.447734 Dram Type= 6, Freq= 0, CH_1, rank 1
3333 11:07:53.454662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3334 11:07:53.455225 ==
3335 11:07:53.457550 [Gating] SW mode calibration
3336 11:07:53.464149 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3337 11:07:53.467674 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3338 11:07:53.473977 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3339 11:07:53.477773 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3340 11:07:53.480495 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3341 11:07:53.487672 0 11 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 0)
3342 11:07:53.490389 0 11 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
3343 11:07:53.494137 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3344 11:07:53.497362 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3345 11:07:53.505146 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3346 11:07:53.508017 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3347 11:07:53.511188 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3348 11:07:53.518071 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3349 11:07:53.520357 0 12 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
3350 11:07:53.523598 0 12 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
3351 11:07:53.530431 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3352 11:07:53.534118 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3353 11:07:53.537267 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3354 11:07:53.544044 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3355 11:07:53.547010 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3356 11:07:53.550477 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3357 11:07:53.556885 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3358 11:07:53.560604 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3359 11:07:53.564129 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3360 11:07:53.570184 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3361 11:07:53.573567 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3362 11:07:53.577404 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3363 11:07:53.583140 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3364 11:07:53.586583 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3365 11:07:53.590225 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3366 11:07:53.596500 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3367 11:07:53.600653 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3368 11:07:53.603184 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3369 11:07:53.610250 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3370 11:07:53.614229 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3371 11:07:53.616756 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3372 11:07:53.623694 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3373 11:07:53.626417 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3374 11:07:53.630280 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3375 11:07:53.633757 Total UI for P1: 0, mck2ui 16
3376 11:07:53.636909 best dqsien dly found for B0: ( 0, 15, 12)
3377 11:07:53.640211 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3378 11:07:53.647983 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3379 11:07:53.650364 Total UI for P1: 0, mck2ui 16
3380 11:07:53.652858 best dqsien dly found for B1: ( 0, 15, 18)
3381 11:07:53.657017 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3382 11:07:53.659677 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3383 11:07:53.660130
3384 11:07:53.664215 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3385 11:07:53.666796 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3386 11:07:53.669988 [Gating] SW calibration Done
3387 11:07:53.670551 ==
3388 11:07:53.673045 Dram Type= 6, Freq= 0, CH_1, rank 1
3389 11:07:53.676928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3390 11:07:53.677485 ==
3391 11:07:53.681706 RX Vref Scan: 0
3392 11:07:53.682253
3393 11:07:53.683280 RX Vref 0 -> 0, step: 1
3394 11:07:53.683733
3395 11:07:53.684122 RX Delay -40 -> 252, step: 8
3396 11:07:53.690160 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3397 11:07:53.693019 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3398 11:07:53.696525 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3399 11:07:53.699948 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3400 11:07:53.704233 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3401 11:07:53.710210 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3402 11:07:53.713335 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3403 11:07:53.717077 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3404 11:07:53.720511 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3405 11:07:53.723531 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3406 11:07:53.729532 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3407 11:07:53.733398 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3408 11:07:53.736808 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3409 11:07:53.739906 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3410 11:07:53.743149 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3411 11:07:53.749448 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3412 11:07:53.749906 ==
3413 11:07:53.754179 Dram Type= 6, Freq= 0, CH_1, rank 1
3414 11:07:53.757308 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3415 11:07:53.757917 ==
3416 11:07:53.758438 DQS Delay:
3417 11:07:53.760038 DQS0 = 0, DQS1 = 0
3418 11:07:53.760591 DQM Delay:
3419 11:07:53.763153 DQM0 = 116, DQM1 = 105
3420 11:07:53.763602 DQ Delay:
3421 11:07:53.767022 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3422 11:07:53.769450 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3423 11:07:53.772905 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3424 11:07:53.775812 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3425 11:07:53.776265
3426 11:07:53.776834
3427 11:07:53.777201 ==
3428 11:07:53.779351 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 11:07:53.786026 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3430 11:07:53.786566 ==
3431 11:07:53.786929
3432 11:07:53.787262
3433 11:07:53.789266 TX Vref Scan disable
3434 11:07:53.789718 == TX Byte 0 ==
3435 11:07:53.793270 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3436 11:07:53.799424 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3437 11:07:53.800114 == TX Byte 1 ==
3438 11:07:53.802967 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3439 11:07:53.810096 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3440 11:07:53.810646 ==
3441 11:07:53.813152 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 11:07:53.816318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3443 11:07:53.816896 ==
3444 11:07:53.827600 TX Vref=22, minBit 9, minWin=25, winSum=422
3445 11:07:53.831465 TX Vref=24, minBit 0, minWin=26, winSum=425
3446 11:07:53.835023 TX Vref=26, minBit 3, minWin=26, winSum=430
3447 11:07:53.837414 TX Vref=28, minBit 3, minWin=26, winSum=429
3448 11:07:53.840867 TX Vref=30, minBit 0, minWin=26, winSum=429
3449 11:07:53.844953 TX Vref=32, minBit 0, minWin=26, winSum=435
3450 11:07:53.850700 [TxChooseVref] Worse bit 0, Min win 26, Win sum 435, Final Vref 32
3451 11:07:53.851158
3452 11:07:53.854390 Final TX Range 1 Vref 32
3453 11:07:53.854844
3454 11:07:53.855205 ==
3455 11:07:53.857239 Dram Type= 6, Freq= 0, CH_1, rank 1
3456 11:07:53.860754 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3457 11:07:53.861323 ==
3458 11:07:53.864142
3459 11:07:53.864671
3460 11:07:53.865105 TX Vref Scan disable
3461 11:07:53.867272 == TX Byte 0 ==
3462 11:07:53.871107 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3463 11:07:53.874159 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3464 11:07:53.877372 == TX Byte 1 ==
3465 11:07:53.880977 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3466 11:07:53.884310 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3467 11:07:53.884903
3468 11:07:53.887471 [DATLAT]
3469 11:07:53.888029 Freq=1200, CH1 RK1
3470 11:07:53.888398
3471 11:07:53.890708 DATLAT Default: 0xc
3472 11:07:53.891269 0, 0xFFFF, sum = 0
3473 11:07:53.894148 1, 0xFFFF, sum = 0
3474 11:07:53.894613 2, 0xFFFF, sum = 0
3475 11:07:53.897335 3, 0xFFFF, sum = 0
3476 11:07:53.897799 4, 0xFFFF, sum = 0
3477 11:07:53.900393 5, 0xFFFF, sum = 0
3478 11:07:53.905290 6, 0xFFFF, sum = 0
3479 11:07:53.905860 7, 0xFFFF, sum = 0
3480 11:07:53.907752 8, 0xFFFF, sum = 0
3481 11:07:53.908317 9, 0xFFFF, sum = 0
3482 11:07:53.910712 10, 0xFFFF, sum = 0
3483 11:07:53.911175 11, 0x0, sum = 1
3484 11:07:53.914041 12, 0x0, sum = 2
3485 11:07:53.914608 13, 0x0, sum = 3
3486 11:07:53.917269 14, 0x0, sum = 4
3487 11:07:53.917838 best_step = 12
3488 11:07:53.918207
3489 11:07:53.918543 ==
3490 11:07:53.921068 Dram Type= 6, Freq= 0, CH_1, rank 1
3491 11:07:53.924284 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3492 11:07:53.924883 ==
3493 11:07:53.927121 RX Vref Scan: 0
3494 11:07:53.927577
3495 11:07:53.927940 RX Vref 0 -> 0, step: 1
3496 11:07:53.930482
3497 11:07:53.931041 RX Delay -29 -> 252, step: 4
3498 11:07:53.937928 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3499 11:07:53.942047 iDelay=199, Bit 1, Center 112 (43 ~ 182) 140
3500 11:07:53.944665 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3501 11:07:53.947442 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3502 11:07:53.950835 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3503 11:07:53.957481 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3504 11:07:53.961837 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3505 11:07:53.964218 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3506 11:07:53.967715 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3507 11:07:53.971444 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3508 11:07:53.977685 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3509 11:07:53.981376 iDelay=199, Bit 11, Center 96 (31 ~ 162) 132
3510 11:07:53.984277 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3511 11:07:53.987452 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3512 11:07:53.990993 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3513 11:07:53.997752 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3514 11:07:53.998319 ==
3515 11:07:54.000858 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 11:07:54.004100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3517 11:07:54.004665 ==
3518 11:07:54.005100 DQS Delay:
3519 11:07:54.008000 DQS0 = 0, DQS1 = 0
3520 11:07:54.008565 DQM Delay:
3521 11:07:54.010818 DQM0 = 115, DQM1 = 103
3522 11:07:54.011379 DQ Delay:
3523 11:07:54.014650 DQ0 =116, DQ1 =112, DQ2 =108, DQ3 =112
3524 11:07:54.017243 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3525 11:07:54.021263 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =96
3526 11:07:54.024610 DQ12 =112, DQ13 =110, DQ14 =112, DQ15 =110
3527 11:07:54.025103
3528 11:07:54.025469
3529 11:07:54.034200 [DQSOSCAuto] RK1, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
3530 11:07:54.037704 CH1 RK1: MR19=404, MR18=606
3531 11:07:54.041117 CH1_RK1: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
3532 11:07:54.044305 [RxdqsGatingPostProcess] freq 1200
3533 11:07:54.050824 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3534 11:07:54.053737 Pre-setting of DQS Precalculation
3535 11:07:54.057219 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3536 11:07:54.067446 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3537 11:07:54.074506 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3538 11:07:54.074969
3539 11:07:54.075436
3540 11:07:54.077260 [Calibration Summary] 2400 Mbps
3541 11:07:54.077717 CH 0, Rank 0
3542 11:07:54.080511 SW Impedance : PASS
3543 11:07:54.081020 DUTY Scan : NO K
3544 11:07:54.083864 ZQ Calibration : PASS
3545 11:07:54.087237 Jitter Meter : NO K
3546 11:07:54.087785 CBT Training : PASS
3547 11:07:54.090638 Write leveling : PASS
3548 11:07:54.093847 RX DQS gating : PASS
3549 11:07:54.094263 RX DQ/DQS(RDDQC) : PASS
3550 11:07:54.098136 TX DQ/DQS : PASS
3551 11:07:54.100562 RX DATLAT : PASS
3552 11:07:54.101080 RX DQ/DQS(Engine): PASS
3553 11:07:54.104183 TX OE : NO K
3554 11:07:54.104704 All Pass.
3555 11:07:54.105098
3556 11:07:54.107405 CH 0, Rank 1
3557 11:07:54.107817 SW Impedance : PASS
3558 11:07:54.110686 DUTY Scan : NO K
3559 11:07:54.113762 ZQ Calibration : PASS
3560 11:07:54.114196 Jitter Meter : NO K
3561 11:07:54.117632 CBT Training : PASS
3562 11:07:54.118153 Write leveling : PASS
3563 11:07:54.120701 RX DQS gating : PASS
3564 11:07:54.124470 RX DQ/DQS(RDDQC) : PASS
3565 11:07:54.125032 TX DQ/DQS : PASS
3566 11:07:54.127373 RX DATLAT : PASS
3567 11:07:54.130804 RX DQ/DQS(Engine): PASS
3568 11:07:54.131222 TX OE : NO K
3569 11:07:54.134264 All Pass.
3570 11:07:54.134681
3571 11:07:54.135010 CH 1, Rank 0
3572 11:07:54.137551 SW Impedance : PASS
3573 11:07:54.138073 DUTY Scan : NO K
3574 11:07:54.141372 ZQ Calibration : PASS
3575 11:07:54.143516 Jitter Meter : NO K
3576 11:07:54.143931 CBT Training : PASS
3577 11:07:54.147385 Write leveling : PASS
3578 11:07:54.150658 RX DQS gating : PASS
3579 11:07:54.151078 RX DQ/DQS(RDDQC) : PASS
3580 11:07:54.153868 TX DQ/DQS : PASS
3581 11:07:54.156904 RX DATLAT : PASS
3582 11:07:54.157333 RX DQ/DQS(Engine): PASS
3583 11:07:54.160690 TX OE : NO K
3584 11:07:54.161152 All Pass.
3585 11:07:54.161484
3586 11:07:54.164013 CH 1, Rank 1
3587 11:07:54.164425 SW Impedance : PASS
3588 11:07:54.167595 DUTY Scan : NO K
3589 11:07:54.168114 ZQ Calibration : PASS
3590 11:07:54.170795 Jitter Meter : NO K
3591 11:07:54.174278 CBT Training : PASS
3592 11:07:54.174801 Write leveling : PASS
3593 11:07:54.177207 RX DQS gating : PASS
3594 11:07:54.180537 RX DQ/DQS(RDDQC) : PASS
3595 11:07:54.180979 TX DQ/DQS : PASS
3596 11:07:54.183958 RX DATLAT : PASS
3597 11:07:54.187744 RX DQ/DQS(Engine): PASS
3598 11:07:54.188272 TX OE : NO K
3599 11:07:54.190142 All Pass.
3600 11:07:54.190556
3601 11:07:54.190886 DramC Write-DBI off
3602 11:07:54.193823 PER_BANK_REFRESH: Hybrid Mode
3603 11:07:54.194237 TX_TRACKING: ON
3604 11:07:54.203977 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3605 11:07:54.207309 [FAST_K] Save calibration result to emmc
3606 11:07:54.211714 dramc_set_vcore_voltage set vcore to 650000
3607 11:07:54.213989 Read voltage for 600, 5
3608 11:07:54.214409 Vio18 = 0
3609 11:07:54.217234 Vcore = 650000
3610 11:07:54.217776 Vdram = 0
3611 11:07:54.218292 Vddq = 0
3612 11:07:54.218639 Vmddr = 0
3613 11:07:54.223999 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3614 11:07:54.230978 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3615 11:07:54.231546 MEM_TYPE=3, freq_sel=19
3616 11:07:54.233640 sv_algorithm_assistance_LP4_1600
3617 11:07:54.237554 ============ PULL DRAM RESETB DOWN ============
3618 11:07:54.244313 ========== PULL DRAM RESETB DOWN end =========
3619 11:07:54.247311 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3620 11:07:54.250120 ===================================
3621 11:07:54.253521 LPDDR4 DRAM CONFIGURATION
3622 11:07:54.256929 ===================================
3623 11:07:54.257398 EX_ROW_EN[0] = 0x0
3624 11:07:54.260964 EX_ROW_EN[1] = 0x0
3625 11:07:54.261426 LP4Y_EN = 0x0
3626 11:07:54.264056 WORK_FSP = 0x0
3627 11:07:54.267420 WL = 0x2
3628 11:07:54.267986 RL = 0x2
3629 11:07:54.271596 BL = 0x2
3630 11:07:54.272160 RPST = 0x0
3631 11:07:54.274526 RD_PRE = 0x0
3632 11:07:54.275090 WR_PRE = 0x1
3633 11:07:54.276803 WR_PST = 0x0
3634 11:07:54.277267 DBI_WR = 0x0
3635 11:07:54.280621 DBI_RD = 0x0
3636 11:07:54.281241 OTF = 0x1
3637 11:07:54.283389 ===================================
3638 11:07:54.287570 ===================================
3639 11:07:54.291448 ANA top config
3640 11:07:54.293260 ===================================
3641 11:07:54.293802 DLL_ASYNC_EN = 0
3642 11:07:54.296648 ALL_SLAVE_EN = 1
3643 11:07:54.300173 NEW_RANK_MODE = 1
3644 11:07:54.303241 DLL_IDLE_MODE = 1
3645 11:07:54.306371 LP45_APHY_COMB_EN = 1
3646 11:07:54.306836 TX_ODT_DIS = 1
3647 11:07:54.309385 NEW_8X_MODE = 1
3648 11:07:54.312648 ===================================
3649 11:07:54.316298 ===================================
3650 11:07:54.319653 data_rate = 1200
3651 11:07:54.323053 CKR = 1
3652 11:07:54.325808 DQ_P2S_RATIO = 8
3653 11:07:54.329186 ===================================
3654 11:07:54.332599 CA_P2S_RATIO = 8
3655 11:07:54.333300 DQ_CA_OPEN = 0
3656 11:07:54.336392 DQ_SEMI_OPEN = 0
3657 11:07:54.339630 CA_SEMI_OPEN = 0
3658 11:07:54.342848 CA_FULL_RATE = 0
3659 11:07:54.347584 DQ_CKDIV4_EN = 1
3660 11:07:54.349457 CA_CKDIV4_EN = 1
3661 11:07:54.349915 CA_PREDIV_EN = 0
3662 11:07:54.353145 PH8_DLY = 0
3663 11:07:54.355791 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3664 11:07:54.359503 DQ_AAMCK_DIV = 4
3665 11:07:54.363219 CA_AAMCK_DIV = 4
3666 11:07:54.365845 CA_ADMCK_DIV = 4
3667 11:07:54.366306 DQ_TRACK_CA_EN = 0
3668 11:07:54.369045 CA_PICK = 600
3669 11:07:54.372256 CA_MCKIO = 600
3670 11:07:54.375427 MCKIO_SEMI = 0
3671 11:07:54.378803 PLL_FREQ = 2288
3672 11:07:54.382200 DQ_UI_PI_RATIO = 32
3673 11:07:54.385457 CA_UI_PI_RATIO = 0
3674 11:07:54.389189 ===================================
3675 11:07:54.392883 ===================================
3676 11:07:54.393436 memory_type:LPDDR4
3677 11:07:54.395696 GP_NUM : 10
3678 11:07:54.399155 SRAM_EN : 1
3679 11:07:54.399711 MD32_EN : 0
3680 11:07:54.402808 ===================================
3681 11:07:54.405581 [ANA_INIT] >>>>>>>>>>>>>>
3682 11:07:54.408663 <<<<<< [CONFIGURE PHASE]: ANA_TX
3683 11:07:54.412483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3684 11:07:54.415084 ===================================
3685 11:07:54.418632 data_rate = 1200,PCW = 0X5800
3686 11:07:54.421455 ===================================
3687 11:07:54.425340 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3688 11:07:54.428953 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3689 11:07:54.435403 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3690 11:07:54.438229 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3691 11:07:54.445476 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3692 11:07:54.448020 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3693 11:07:54.448486 [ANA_INIT] flow start
3694 11:07:54.451725 [ANA_INIT] PLL >>>>>>>>
3695 11:07:54.454514 [ANA_INIT] PLL <<<<<<<<
3696 11:07:54.455100 [ANA_INIT] MIDPI >>>>>>>>
3697 11:07:54.457980 [ANA_INIT] MIDPI <<<<<<<<
3698 11:07:54.461150 [ANA_INIT] DLL >>>>>>>>
3699 11:07:54.461642 [ANA_INIT] flow end
3700 11:07:54.464259 ============ LP4 DIFF to SE enter ============
3701 11:07:54.471532 ============ LP4 DIFF to SE exit ============
3702 11:07:54.472104 [ANA_INIT] <<<<<<<<<<<<<
3703 11:07:54.474702 [Flow] Enable top DCM control >>>>>
3704 11:07:54.478260 [Flow] Enable top DCM control <<<<<
3705 11:07:54.481003 Enable DLL master slave shuffle
3706 11:07:54.488194 ==============================================================
3707 11:07:54.490914 Gating Mode config
3708 11:07:54.494578 ==============================================================
3709 11:07:54.497541 Config description:
3710 11:07:54.507579 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3711 11:07:54.514067 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3712 11:07:54.518678 SELPH_MODE 0: By rank 1: By Phase
3713 11:07:54.524460 ==============================================================
3714 11:07:54.527635 GAT_TRACK_EN = 1
3715 11:07:54.530869 RX_GATING_MODE = 2
3716 11:07:54.533623 RX_GATING_TRACK_MODE = 2
3717 11:07:54.537159 SELPH_MODE = 1
3718 11:07:54.537772 PICG_EARLY_EN = 1
3719 11:07:54.540147 VALID_LAT_VALUE = 1
3720 11:07:54.546751 ==============================================================
3721 11:07:54.550398 Enter into Gating configuration >>>>
3722 11:07:54.553629 Exit from Gating configuration <<<<
3723 11:07:54.556763 Enter into DVFS_PRE_config >>>>>
3724 11:07:54.567126 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3725 11:07:54.570261 Exit from DVFS_PRE_config <<<<<
3726 11:07:54.573394 Enter into PICG configuration >>>>
3727 11:07:54.576777 Exit from PICG configuration <<<<
3728 11:07:54.579999 [RX_INPUT] configuration >>>>>
3729 11:07:54.583155 [RX_INPUT] configuration <<<<<
3730 11:07:54.590124 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3731 11:07:54.593382 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3732 11:07:54.599673 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3733 11:07:54.606966 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3734 11:07:54.613084 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3735 11:07:54.620132 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3736 11:07:54.622876 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3737 11:07:54.626609 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3738 11:07:54.629795 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3739 11:07:54.636141 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3740 11:07:54.640429 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3741 11:07:54.643361 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3742 11:07:54.646235 ===================================
3743 11:07:54.649336 LPDDR4 DRAM CONFIGURATION
3744 11:07:54.652865 ===================================
3745 11:07:54.653327 EX_ROW_EN[0] = 0x0
3746 11:07:54.655878 EX_ROW_EN[1] = 0x0
3747 11:07:54.658964 LP4Y_EN = 0x0
3748 11:07:54.659421 WORK_FSP = 0x0
3749 11:07:54.662637 WL = 0x2
3750 11:07:54.663190 RL = 0x2
3751 11:07:54.666291 BL = 0x2
3752 11:07:54.666865 RPST = 0x0
3753 11:07:54.668900 RD_PRE = 0x0
3754 11:07:54.669362 WR_PRE = 0x1
3755 11:07:54.672401 WR_PST = 0x0
3756 11:07:54.673035 DBI_WR = 0x0
3757 11:07:54.675859 DBI_RD = 0x0
3758 11:07:54.676409 OTF = 0x1
3759 11:07:54.678933 ===================================
3760 11:07:54.682893 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3761 11:07:54.688816 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3762 11:07:54.693099 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3763 11:07:54.695716 ===================================
3764 11:07:54.698946 LPDDR4 DRAM CONFIGURATION
3765 11:07:54.702330 ===================================
3766 11:07:54.702788 EX_ROW_EN[0] = 0x10
3767 11:07:54.706115 EX_ROW_EN[1] = 0x0
3768 11:07:54.709273 LP4Y_EN = 0x0
3769 11:07:54.709827 WORK_FSP = 0x0
3770 11:07:54.713352 WL = 0x2
3771 11:07:54.713923 RL = 0x2
3772 11:07:54.715696 BL = 0x2
3773 11:07:54.716152 RPST = 0x0
3774 11:07:54.718810 RD_PRE = 0x0
3775 11:07:54.719363 WR_PRE = 0x1
3776 11:07:54.721654 WR_PST = 0x0
3777 11:07:54.722110 DBI_WR = 0x0
3778 11:07:54.725912 DBI_RD = 0x0
3779 11:07:54.726469 OTF = 0x1
3780 11:07:54.729951 ===================================
3781 11:07:54.734881 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3782 11:07:54.740156 nWR fixed to 30
3783 11:07:54.742867 [ModeRegInit_LP4] CH0 RK0
3784 11:07:54.743424 [ModeRegInit_LP4] CH0 RK1
3785 11:07:54.746366 [ModeRegInit_LP4] CH1 RK0
3786 11:07:54.749420 [ModeRegInit_LP4] CH1 RK1
3787 11:07:54.749875 match AC timing 16
3788 11:07:54.757102 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3789 11:07:54.759815 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3790 11:07:54.762966 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3791 11:07:54.769174 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3792 11:07:54.772436 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3793 11:07:54.772950 ==
3794 11:07:54.776221 Dram Type= 6, Freq= 0, CH_0, rank 0
3795 11:07:54.779200 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3796 11:07:54.779757 ==
3797 11:07:54.786067 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3798 11:07:54.792495 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3799 11:07:54.795851 [CA 0] Center 36 (6~66) winsize 61
3800 11:07:54.798820 [CA 1] Center 35 (5~66) winsize 62
3801 11:07:54.802160 [CA 2] Center 34 (4~65) winsize 62
3802 11:07:54.806218 [CA 3] Center 34 (3~65) winsize 63
3803 11:07:54.808953 [CA 4] Center 33 (3~64) winsize 62
3804 11:07:54.812560 [CA 5] Center 33 (3~64) winsize 62
3805 11:07:54.813455
3806 11:07:54.815578 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3807 11:07:54.816131
3808 11:07:54.818793 [CATrainingPosCal] consider 1 rank data
3809 11:07:54.822888 u2DelayCellTimex100 = 270/100 ps
3810 11:07:54.825566 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3811 11:07:54.828883 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3812 11:07:54.831873 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3813 11:07:54.835210 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3814 11:07:54.841687 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3815 11:07:54.845096 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3816 11:07:54.845552
3817 11:07:54.848371 CA PerBit enable=1, Macro0, CA PI delay=33
3818 11:07:54.848948
3819 11:07:54.852130 [CBTSetCACLKResult] CA Dly = 33
3820 11:07:54.852587 CS Dly: 4 (0~35)
3821 11:07:54.853113 ==
3822 11:07:54.855441 Dram Type= 6, Freq= 0, CH_0, rank 1
3823 11:07:54.861556 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3824 11:07:54.862017 ==
3825 11:07:54.864925 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3826 11:07:54.871755 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3827 11:07:54.874841 [CA 0] Center 35 (5~66) winsize 62
3828 11:07:54.878286 [CA 1] Center 35 (5~66) winsize 62
3829 11:07:54.881942 [CA 2] Center 34 (4~65) winsize 62
3830 11:07:54.884354 [CA 3] Center 34 (4~65) winsize 62
3831 11:07:54.888833 [CA 4] Center 33 (3~64) winsize 62
3832 11:07:54.891881 [CA 5] Center 33 (3~64) winsize 62
3833 11:07:54.892431
3834 11:07:54.894489 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3835 11:07:54.894993
3836 11:07:54.898101 [CATrainingPosCal] consider 2 rank data
3837 11:07:54.901268 u2DelayCellTimex100 = 270/100 ps
3838 11:07:54.905129 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3839 11:07:54.911211 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3840 11:07:54.914845 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3841 11:07:54.917620 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3842 11:07:54.921288 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3843 11:07:54.924702 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3844 11:07:54.925296
3845 11:07:54.928247 CA PerBit enable=1, Macro0, CA PI delay=33
3846 11:07:54.928844
3847 11:07:54.930939 [CBTSetCACLKResult] CA Dly = 33
3848 11:07:54.934431 CS Dly: 4 (0~36)
3849 11:07:54.934884
3850 11:07:54.937609 ----->DramcWriteLeveling(PI) begin...
3851 11:07:54.938072 ==
3852 11:07:54.940594 Dram Type= 6, Freq= 0, CH_0, rank 0
3853 11:07:54.944511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3854 11:07:54.945111 ==
3855 11:07:54.947428 Write leveling (Byte 0): 28 => 28
3856 11:07:54.950866 Write leveling (Byte 1): 32 => 32
3857 11:07:54.954196 DramcWriteLeveling(PI) end<-----
3858 11:07:54.954778
3859 11:07:54.955143 ==
3860 11:07:54.957367 Dram Type= 6, Freq= 0, CH_0, rank 0
3861 11:07:54.961506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3862 11:07:54.962019 ==
3863 11:07:54.965039 [Gating] SW mode calibration
3864 11:07:54.971429 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3865 11:07:54.977231 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3866 11:07:54.980785 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3867 11:07:54.984116 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3868 11:07:54.990327 0 5 8 | B1->B0 | 3232 3030 | 0 0 | (0 0) (0 1)
3869 11:07:54.993497 0 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3870 11:07:54.997790 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3871 11:07:55.003275 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3872 11:07:55.007343 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3873 11:07:55.010556 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3874 11:07:55.016984 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3875 11:07:55.020015 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3876 11:07:55.023657 0 6 8 | B1->B0 | 2929 2f2f | 0 0 | (0 0) (0 0)
3877 11:07:55.030170 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3878 11:07:55.034030 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3879 11:07:55.036527 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3880 11:07:55.043383 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3881 11:07:55.046330 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3882 11:07:55.050706 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3883 11:07:55.056312 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3884 11:07:55.059940 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3885 11:07:55.063448 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3886 11:07:55.069595 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3887 11:07:55.073117 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3888 11:07:55.076498 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3889 11:07:55.083297 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3890 11:07:55.086278 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3891 11:07:55.089884 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3892 11:07:55.096465 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3893 11:07:55.099758 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3894 11:07:55.102967 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3895 11:07:55.109081 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3896 11:07:55.113237 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3897 11:07:55.116561 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3898 11:07:55.122687 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3899 11:07:55.126091 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3900 11:07:55.129367 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3901 11:07:55.132332 Total UI for P1: 0, mck2ui 16
3902 11:07:55.135624 best dqsien dly found for B0: ( 0, 9, 6)
3903 11:07:55.142061 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3904 11:07:55.142608 Total UI for P1: 0, mck2ui 16
3905 11:07:55.145335 best dqsien dly found for B1: ( 0, 9, 8)
3906 11:07:55.152286 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3907 11:07:55.155164 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3908 11:07:55.155647
3909 11:07:55.159081 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3910 11:07:55.162870 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3911 11:07:55.165418 [Gating] SW calibration Done
3912 11:07:55.165874 ==
3913 11:07:55.170666 Dram Type= 6, Freq= 0, CH_0, rank 0
3914 11:07:55.172900 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3915 11:07:55.173364 ==
3916 11:07:55.175808 RX Vref Scan: 0
3917 11:07:55.176358
3918 11:07:55.176766 RX Vref 0 -> 0, step: 1
3919 11:07:55.177119
3920 11:07:55.178303 RX Delay -230 -> 252, step: 16
3921 11:07:55.181820 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
3922 11:07:55.188534 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3923 11:07:55.191659 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3924 11:07:55.195309 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
3925 11:07:55.198629 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3926 11:07:55.204818 iDelay=218, Bit 5, Center 33 (-118 ~ 185) 304
3927 11:07:55.208738 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3928 11:07:55.212121 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3929 11:07:55.214964 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3930 11:07:55.218857 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3931 11:07:55.224898 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
3932 11:07:55.228495 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3933 11:07:55.232897 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3934 11:07:55.234851 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3935 11:07:55.241653 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3936 11:07:55.244984 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3937 11:07:55.245530 ==
3938 11:07:55.248415 Dram Type= 6, Freq= 0, CH_0, rank 0
3939 11:07:55.251410 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3940 11:07:55.251889 ==
3941 11:07:55.254435 DQS Delay:
3942 11:07:55.254891 DQS0 = 0, DQS1 = 0
3943 11:07:55.257719 DQM Delay:
3944 11:07:55.258179 DQM0 = 43, DQM1 = 34
3945 11:07:55.258545 DQ Delay:
3946 11:07:55.262299 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
3947 11:07:55.265132 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3948 11:07:55.267996 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
3949 11:07:55.271633 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3950 11:07:55.272092
3951 11:07:55.272451
3952 11:07:55.273051 ==
3953 11:07:55.274867 Dram Type= 6, Freq= 0, CH_0, rank 0
3954 11:07:55.281332 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3955 11:07:55.281794 ==
3956 11:07:55.282157
3957 11:07:55.282488
3958 11:07:55.284569 TX Vref Scan disable
3959 11:07:55.285075 == TX Byte 0 ==
3960 11:07:55.287553 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3961 11:07:55.294481 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3962 11:07:55.294994 == TX Byte 1 ==
3963 11:07:55.297842 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3964 11:07:55.304351 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3965 11:07:55.304809 ==
3966 11:07:55.308485 Dram Type= 6, Freq= 0, CH_0, rank 0
3967 11:07:55.311000 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3968 11:07:55.311418 ==
3969 11:07:55.311748
3970 11:07:55.312054
3971 11:07:55.314644 TX Vref Scan disable
3972 11:07:55.318992 == TX Byte 0 ==
3973 11:07:55.320792 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3974 11:07:55.324061 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3975 11:07:55.327774 == TX Byte 1 ==
3976 11:07:55.330838 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3977 11:07:55.334459 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3978 11:07:55.334956
3979 11:07:55.337760 [DATLAT]
3980 11:07:55.338219 Freq=600, CH0 RK0
3981 11:07:55.338587
3982 11:07:55.340673 DATLAT Default: 0x9
3983 11:07:55.341202 0, 0xFFFF, sum = 0
3984 11:07:55.343903 1, 0xFFFF, sum = 0
3985 11:07:55.344436 2, 0xFFFF, sum = 0
3986 11:07:55.347203 3, 0xFFFF, sum = 0
3987 11:07:55.347689 4, 0xFFFF, sum = 0
3988 11:07:55.350922 5, 0xFFFF, sum = 0
3989 11:07:55.351388 6, 0xFFFF, sum = 0
3990 11:07:55.353953 7, 0x0, sum = 1
3991 11:07:55.354417 8, 0x0, sum = 2
3992 11:07:55.357264 9, 0x0, sum = 3
3993 11:07:55.357687 10, 0x0, sum = 4
3994 11:07:55.361067 best_step = 8
3995 11:07:55.361485
3996 11:07:55.361819 ==
3997 11:07:55.363379 Dram Type= 6, Freq= 0, CH_0, rank 0
3998 11:07:55.366829 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3999 11:07:55.367333 ==
4000 11:07:55.370313 RX Vref Scan: 1
4001 11:07:55.370729
4002 11:07:55.371063 RX Vref 0 -> 0, step: 1
4003 11:07:55.371372
4004 11:07:55.373872 RX Delay -195 -> 252, step: 8
4005 11:07:55.374290
4006 11:07:55.376700 Set Vref, RX VrefLevel [Byte0]: 53
4007 11:07:55.380552 [Byte1]: 48
4008 11:07:55.384306
4009 11:07:55.384759 Final RX Vref Byte 0 = 53 to rank0
4010 11:07:55.387255 Final RX Vref Byte 1 = 48 to rank0
4011 11:07:55.390182 Final RX Vref Byte 0 = 53 to rank1
4012 11:07:55.393824 Final RX Vref Byte 1 = 48 to rank1==
4013 11:07:55.396769 Dram Type= 6, Freq= 0, CH_0, rank 0
4014 11:07:55.403380 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4015 11:07:55.404014 ==
4016 11:07:55.404459 DQS Delay:
4017 11:07:55.406988 DQS0 = 0, DQS1 = 0
4018 11:07:55.407404 DQM Delay:
4019 11:07:55.407738 DQM0 = 39, DQM1 = 30
4020 11:07:55.410230 DQ Delay:
4021 11:07:55.413291 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4022 11:07:55.417258 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4023 11:07:55.420317 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4024 11:07:55.423821 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4025 11:07:55.424239
4026 11:07:55.424569
4027 11:07:55.429888 [DQSOSCAuto] RK0, (LSB)MR18= 0x5353, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
4028 11:07:55.433208 CH0 RK0: MR19=808, MR18=5353
4029 11:07:55.439870 CH0_RK0: MR19=0x808, MR18=0x5353, DQSOSC=394, MR23=63, INC=168, DEC=112
4030 11:07:55.440230
4031 11:07:55.443335 ----->DramcWriteLeveling(PI) begin...
4032 11:07:55.443563 ==
4033 11:07:55.447108 Dram Type= 6, Freq= 0, CH_0, rank 1
4034 11:07:55.449479 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4035 11:07:55.449705 ==
4036 11:07:55.453237 Write leveling (Byte 0): 31 => 31
4037 11:07:55.456541 Write leveling (Byte 1): 30 => 30
4038 11:07:55.459475 DramcWriteLeveling(PI) end<-----
4039 11:07:55.459701
4040 11:07:55.459881 ==
4041 11:07:55.462933 Dram Type= 6, Freq= 0, CH_0, rank 1
4042 11:07:55.466342 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4043 11:07:55.466569 ==
4044 11:07:55.469508 [Gating] SW mode calibration
4045 11:07:55.476466 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4046 11:07:55.483376 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4047 11:07:55.486351 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4048 11:07:55.493646 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4049 11:07:55.496005 0 5 8 | B1->B0 | 3333 3232 | 1 1 | (1 0) (0 1)
4050 11:07:55.499752 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4051 11:07:55.505932 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 11:07:55.509900 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 11:07:55.512645 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 11:07:55.519431 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 11:07:55.522366 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 11:07:55.525579 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 11:07:55.533015 0 6 8 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (0 0)
4058 11:07:55.535353 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4059 11:07:55.539488 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 11:07:55.545665 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 11:07:55.548637 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 11:07:55.552484 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 11:07:55.558815 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 11:07:55.562453 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 11:07:55.565604 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4066 11:07:55.572044 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 11:07:55.575485 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 11:07:55.579306 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 11:07:55.585639 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 11:07:55.588776 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 11:07:55.591611 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 11:07:55.598870 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 11:07:55.601836 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 11:07:55.605542 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 11:07:55.611434 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 11:07:55.615231 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 11:07:55.618117 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 11:07:55.625345 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 11:07:55.628898 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 11:07:55.631723 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 11:07:55.638013 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4082 11:07:55.638424 Total UI for P1: 0, mck2ui 16
4083 11:07:55.645564 best dqsien dly found for B1: ( 0, 9, 6)
4084 11:07:55.648118 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 11:07:55.651620 Total UI for P1: 0, mck2ui 16
4086 11:07:55.654862 best dqsien dly found for B0: ( 0, 9, 8)
4087 11:07:55.658649 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4088 11:07:55.661375 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4089 11:07:55.661958
4090 11:07:55.665687 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4091 11:07:55.668087 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4092 11:07:55.671654 [Gating] SW calibration Done
4093 11:07:55.672338 ==
4094 11:07:55.674757 Dram Type= 6, Freq= 0, CH_0, rank 1
4095 11:07:55.677780 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4096 11:07:55.678418 ==
4097 11:07:55.681760 RX Vref Scan: 0
4098 11:07:55.682303
4099 11:07:55.684420 RX Vref 0 -> 0, step: 1
4100 11:07:55.684927
4101 11:07:55.685300 RX Delay -230 -> 252, step: 16
4102 11:07:55.691957 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4103 11:07:55.694666 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4104 11:07:55.698442 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4105 11:07:55.701175 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4106 11:07:55.708089 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4107 11:07:55.711613 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4108 11:07:55.715074 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4109 11:07:55.718207 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4110 11:07:55.721096 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4111 11:07:55.729478 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4112 11:07:55.730900 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4113 11:07:55.734190 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4114 11:07:55.738275 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4115 11:07:55.744496 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4116 11:07:55.747623 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4117 11:07:55.751013 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4118 11:07:55.751473 ==
4119 11:07:55.754434 Dram Type= 6, Freq= 0, CH_0, rank 1
4120 11:07:55.761203 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4121 11:07:55.761834 ==
4122 11:07:55.762432 DQS Delay:
4123 11:07:55.762956 DQS0 = 0, DQS1 = 0
4124 11:07:55.764584 DQM Delay:
4125 11:07:55.765258 DQM0 = 40, DQM1 = 33
4126 11:07:55.768057 DQ Delay:
4127 11:07:55.770877 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4128 11:07:55.774444 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4129 11:07:55.775007 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4130 11:07:55.780817 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4131 11:07:55.781279
4132 11:07:55.781644
4133 11:07:55.782019 ==
4134 11:07:55.784146 Dram Type= 6, Freq= 0, CH_0, rank 1
4135 11:07:55.787636 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4136 11:07:55.788099 ==
4137 11:07:55.788592
4138 11:07:55.789003
4139 11:07:55.791228 TX Vref Scan disable
4140 11:07:55.791687 == TX Byte 0 ==
4141 11:07:55.797930 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4142 11:07:55.801670 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4143 11:07:55.802281 == TX Byte 1 ==
4144 11:07:55.807017 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4145 11:07:55.811209 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4146 11:07:55.811777 ==
4147 11:07:55.813736 Dram Type= 6, Freq= 0, CH_0, rank 1
4148 11:07:55.816799 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4149 11:07:55.817261 ==
4150 11:07:55.817623
4151 11:07:55.820136
4152 11:07:55.820590 TX Vref Scan disable
4153 11:07:55.823891 == TX Byte 0 ==
4154 11:07:55.826967 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4155 11:07:55.830617 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4156 11:07:55.834533 == TX Byte 1 ==
4157 11:07:55.837576 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4158 11:07:55.844254 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4159 11:07:55.844844
4160 11:07:55.845363 [DATLAT]
4161 11:07:55.845880 Freq=600, CH0 RK1
4162 11:07:55.846344
4163 11:07:55.847042 DATLAT Default: 0x8
4164 11:07:55.847386 0, 0xFFFF, sum = 0
4165 11:07:55.850536 1, 0xFFFF, sum = 0
4166 11:07:55.850952 2, 0xFFFF, sum = 0
4167 11:07:55.853827 3, 0xFFFF, sum = 0
4168 11:07:55.857278 4, 0xFFFF, sum = 0
4169 11:07:55.857695 5, 0xFFFF, sum = 0
4170 11:07:55.860619 6, 0xFFFF, sum = 0
4171 11:07:55.861083 7, 0x0, sum = 1
4172 11:07:55.861420 8, 0x0, sum = 2
4173 11:07:55.863588 9, 0x0, sum = 3
4174 11:07:55.864006 10, 0x0, sum = 4
4175 11:07:55.866728 best_step = 8
4176 11:07:55.867139
4177 11:07:55.867466 ==
4178 11:07:55.869966 Dram Type= 6, Freq= 0, CH_0, rank 1
4179 11:07:55.874112 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4180 11:07:55.874628 ==
4181 11:07:55.876897 RX Vref Scan: 0
4182 11:07:55.877317
4183 11:07:55.877648 RX Vref 0 -> 0, step: 1
4184 11:07:55.877962
4185 11:07:55.880119 RX Delay -195 -> 252, step: 8
4186 11:07:55.887397 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4187 11:07:55.890906 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4188 11:07:55.894338 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4189 11:07:55.897736 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4190 11:07:55.905096 iDelay=205, Bit 4, Center 44 (-115 ~ 204) 320
4191 11:07:55.906794 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4192 11:07:55.911222 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4193 11:07:55.914615 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4194 11:07:55.920295 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4195 11:07:55.924226 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4196 11:07:55.927257 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4197 11:07:55.931056 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4198 11:07:55.937378 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4199 11:07:55.939940 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4200 11:07:55.943183 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4201 11:07:55.947623 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4202 11:07:55.948138 ==
4203 11:07:55.950631 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 11:07:55.956905 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4205 11:07:55.957332 ==
4206 11:07:55.957666 DQS Delay:
4207 11:07:55.960884 DQS0 = 0, DQS1 = 0
4208 11:07:55.961299 DQM Delay:
4209 11:07:55.961725 DQM0 = 41, DQM1 = 33
4210 11:07:55.963432 DQ Delay:
4211 11:07:55.967147 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4212 11:07:55.970005 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4213 11:07:55.973216 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4214 11:07:55.976594 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4215 11:07:55.977067
4216 11:07:55.977399
4217 11:07:55.983418 [DQSOSCAuto] RK1, (LSB)MR18= 0x6060, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4218 11:07:55.987481 CH0 RK1: MR19=808, MR18=6060
4219 11:07:55.993426 CH0_RK1: MR19=0x808, MR18=0x6060, DQSOSC=391, MR23=63, INC=171, DEC=114
4220 11:07:55.996372 [RxdqsGatingPostProcess] freq 600
4221 11:07:55.999665 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4222 11:07:56.003225 Pre-setting of DQS Precalculation
4223 11:07:56.009430 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4224 11:07:56.009834 ==
4225 11:07:56.013131 Dram Type= 6, Freq= 0, CH_1, rank 0
4226 11:07:56.016477 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4227 11:07:56.016934 ==
4228 11:07:56.023120 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4229 11:07:56.029745 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4230 11:07:56.032666 [CA 0] Center 35 (5~66) winsize 62
4231 11:07:56.035999 [CA 1] Center 35 (5~66) winsize 62
4232 11:07:56.039710 [CA 2] Center 33 (3~64) winsize 62
4233 11:07:56.042967 [CA 3] Center 33 (3~64) winsize 62
4234 11:07:56.045836 [CA 4] Center 33 (2~64) winsize 63
4235 11:07:56.049265 [CA 5] Center 33 (2~64) winsize 63
4236 11:07:56.049678
4237 11:07:56.053244 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4238 11:07:56.053923
4239 11:07:56.056666 [CATrainingPosCal] consider 1 rank data
4240 11:07:56.059313 u2DelayCellTimex100 = 270/100 ps
4241 11:07:56.062527 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4242 11:07:56.066063 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4243 11:07:56.068994 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4244 11:07:56.072304 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4245 11:07:56.075660 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4246 11:07:56.079098 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4247 11:07:56.079620
4248 11:07:56.085778 CA PerBit enable=1, Macro0, CA PI delay=33
4249 11:07:56.086211
4250 11:07:56.088865 [CBTSetCACLKResult] CA Dly = 33
4251 11:07:56.089348 CS Dly: 4 (0~35)
4252 11:07:56.089784 ==
4253 11:07:56.091999 Dram Type= 6, Freq= 0, CH_1, rank 1
4254 11:07:56.095735 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4255 11:07:56.096239 ==
4256 11:07:56.102577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4257 11:07:56.109510 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4258 11:07:56.112201 [CA 0] Center 35 (5~66) winsize 62
4259 11:07:56.115496 [CA 1] Center 34 (4~65) winsize 62
4260 11:07:56.118342 [CA 2] Center 33 (3~64) winsize 62
4261 11:07:56.122032 [CA 3] Center 33 (3~64) winsize 62
4262 11:07:56.125380 [CA 4] Center 32 (2~63) winsize 62
4263 11:07:56.128534 [CA 5] Center 32 (2~63) winsize 62
4264 11:07:56.129135
4265 11:07:56.131834 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4266 11:07:56.132337
4267 11:07:56.134869 [CATrainingPosCal] consider 2 rank data
4268 11:07:56.138067 u2DelayCellTimex100 = 270/100 ps
4269 11:07:56.142021 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4270 11:07:56.145138 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4271 11:07:56.148315 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4272 11:07:56.151399 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4273 11:07:56.158304 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4274 11:07:56.161354 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4275 11:07:56.161787
4276 11:07:56.164325 CA PerBit enable=1, Macro0, CA PI delay=32
4277 11:07:56.164893
4278 11:07:56.167858 [CBTSetCACLKResult] CA Dly = 32
4279 11:07:56.168271 CS Dly: 4 (0~36)
4280 11:07:56.168597
4281 11:07:56.171606 ----->DramcWriteLeveling(PI) begin...
4282 11:07:56.172023 ==
4283 11:07:56.174641 Dram Type= 6, Freq= 0, CH_1, rank 0
4284 11:07:56.181106 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4285 11:07:56.181518 ==
4286 11:07:56.184441 Write leveling (Byte 0): 27 => 27
4287 11:07:56.187806 Write leveling (Byte 1): 26 => 26
4288 11:07:56.188318 DramcWriteLeveling(PI) end<-----
4289 11:07:56.191842
4290 11:07:56.192354 ==
4291 11:07:56.194476 Dram Type= 6, Freq= 0, CH_1, rank 0
4292 11:07:56.197584 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4293 11:07:56.198042 ==
4294 11:07:56.201516 [Gating] SW mode calibration
4295 11:07:56.208110 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4296 11:07:56.211195 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4297 11:07:56.218560 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4298 11:07:56.221326 0 5 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4299 11:07:56.224645 0 5 8 | B1->B0 | 3131 2727 | 1 1 | (1 0) (1 0)
4300 11:07:56.231125 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4301 11:07:56.234029 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4302 11:07:56.237122 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4303 11:07:56.244801 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4304 11:07:56.247367 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4305 11:07:56.250461 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4306 11:07:56.257949 0 6 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4307 11:07:56.261547 0 6 8 | B1->B0 | 3737 4343 | 0 0 | (0 0) (0 0)
4308 11:07:56.263851 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4309 11:07:56.270541 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4310 11:07:56.273954 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4311 11:07:56.277508 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4312 11:07:56.283775 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4313 11:07:56.287493 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4314 11:07:56.290518 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4315 11:07:56.297236 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4316 11:07:56.300946 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 11:07:56.304620 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 11:07:56.310345 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 11:07:56.313527 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4320 11:07:56.317061 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4321 11:07:56.323726 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4322 11:07:56.326360 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4323 11:07:56.331077 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4324 11:07:56.336818 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4325 11:07:56.340208 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4326 11:07:56.343683 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4327 11:07:56.350017 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4328 11:07:56.352897 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4329 11:07:56.356793 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4330 11:07:56.362804 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4331 11:07:56.366231 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4332 11:07:56.370333 Total UI for P1: 0, mck2ui 16
4333 11:07:56.373885 best dqsien dly found for B0: ( 0, 9, 6)
4334 11:07:56.376409 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4335 11:07:56.380982 Total UI for P1: 0, mck2ui 16
4336 11:07:56.383306 best dqsien dly found for B1: ( 0, 9, 8)
4337 11:07:56.386469 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4338 11:07:56.389221 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4339 11:07:56.389740
4340 11:07:56.392941 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4341 11:07:56.400111 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4342 11:07:56.400655 [Gating] SW calibration Done
4343 11:07:56.401167 ==
4344 11:07:56.403858 Dram Type= 6, Freq= 0, CH_1, rank 0
4345 11:07:56.409202 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4346 11:07:56.409702 ==
4347 11:07:56.410056 RX Vref Scan: 0
4348 11:07:56.410372
4349 11:07:56.413450 RX Vref 0 -> 0, step: 1
4350 11:07:56.413976
4351 11:07:56.416618 RX Delay -230 -> 252, step: 16
4352 11:07:56.419632 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4353 11:07:56.422709 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4354 11:07:56.429310 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4355 11:07:56.432876 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4356 11:07:56.435786 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4357 11:07:56.439610 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4358 11:07:56.442931 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4359 11:07:56.448884 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4360 11:07:56.452989 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4361 11:07:56.455313 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4362 11:07:56.459127 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4363 11:07:56.465387 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4364 11:07:56.468394 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4365 11:07:56.471980 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4366 11:07:56.475295 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4367 11:07:56.482634 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4368 11:07:56.483147 ==
4369 11:07:56.485576 Dram Type= 6, Freq= 0, CH_1, rank 0
4370 11:07:56.488526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4371 11:07:56.488986 ==
4372 11:07:56.489322 DQS Delay:
4373 11:07:56.492016 DQS0 = 0, DQS1 = 0
4374 11:07:56.492428 DQM Delay:
4375 11:07:56.495606 DQM0 = 39, DQM1 = 32
4376 11:07:56.496166 DQ Delay:
4377 11:07:56.499078 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4378 11:07:56.501864 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4379 11:07:56.505551 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4380 11:07:56.508473 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4381 11:07:56.508919
4382 11:07:56.509248
4383 11:07:56.509553 ==
4384 11:07:56.512183 Dram Type= 6, Freq= 0, CH_1, rank 0
4385 11:07:56.514879 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4386 11:07:56.519188 ==
4387 11:07:56.519809
4388 11:07:56.520151
4389 11:07:56.520459 TX Vref Scan disable
4390 11:07:56.522097 == TX Byte 0 ==
4391 11:07:56.525369 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4392 11:07:56.529142 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4393 11:07:56.532191 == TX Byte 1 ==
4394 11:07:56.534999 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4395 11:07:56.539704 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4396 11:07:56.541543 ==
4397 11:07:56.544596 Dram Type= 6, Freq= 0, CH_1, rank 0
4398 11:07:56.548494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4399 11:07:56.549039 ==
4400 11:07:56.549376
4401 11:07:56.549690
4402 11:07:56.551947 TX Vref Scan disable
4403 11:07:56.552353 == TX Byte 0 ==
4404 11:07:56.558389 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4405 11:07:56.561160 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4406 11:07:56.561659 == TX Byte 1 ==
4407 11:07:56.567872 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4408 11:07:56.571826 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4409 11:07:56.572355
4410 11:07:56.572687 [DATLAT]
4411 11:07:56.575405 Freq=600, CH1 RK0
4412 11:07:56.575811
4413 11:07:56.576148 DATLAT Default: 0x9
4414 11:07:56.578529 0, 0xFFFF, sum = 0
4415 11:07:56.579070 1, 0xFFFF, sum = 0
4416 11:07:56.581734 2, 0xFFFF, sum = 0
4417 11:07:56.584531 3, 0xFFFF, sum = 0
4418 11:07:56.585006 4, 0xFFFF, sum = 0
4419 11:07:56.587908 5, 0xFFFF, sum = 0
4420 11:07:56.588328 6, 0xFFFF, sum = 0
4421 11:07:56.591360 7, 0x0, sum = 1
4422 11:07:56.591781 8, 0x0, sum = 2
4423 11:07:56.592162 9, 0x0, sum = 3
4424 11:07:56.594388 10, 0x0, sum = 4
4425 11:07:56.594811 best_step = 8
4426 11:07:56.595140
4427 11:07:56.595441 ==
4428 11:07:56.597431 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 11:07:56.604782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4430 11:07:56.605203 ==
4431 11:07:56.605534 RX Vref Scan: 1
4432 11:07:56.605840
4433 11:07:56.607553 RX Vref 0 -> 0, step: 1
4434 11:07:56.607968
4435 11:07:56.610985 RX Delay -195 -> 252, step: 8
4436 11:07:56.611400
4437 11:07:56.614670 Set Vref, RX VrefLevel [Byte0]: 54
4438 11:07:56.618778 [Byte1]: 49
4439 11:07:56.619312
4440 11:07:56.621088 Final RX Vref Byte 0 = 54 to rank0
4441 11:07:56.625080 Final RX Vref Byte 1 = 49 to rank0
4442 11:07:56.627702 Final RX Vref Byte 0 = 54 to rank1
4443 11:07:56.630921 Final RX Vref Byte 1 = 49 to rank1==
4444 11:07:56.634637 Dram Type= 6, Freq= 0, CH_1, rank 0
4445 11:07:56.637745 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4446 11:07:56.638241 ==
4447 11:07:56.641255 DQS Delay:
4448 11:07:56.641672 DQS0 = 0, DQS1 = 0
4449 11:07:56.643703 DQM Delay:
4450 11:07:56.644118 DQM0 = 38, DQM1 = 30
4451 11:07:56.644447 DQ Delay:
4452 11:07:56.647248 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4453 11:07:56.651836 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4454 11:07:56.653717 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4455 11:07:56.657635 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
4456 11:07:56.658158
4457 11:07:56.658497
4458 11:07:56.667793 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d6d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4459 11:07:56.670469 CH1 RK0: MR19=808, MR18=6D6D
4460 11:07:56.678245 CH1_RK0: MR19=0x808, MR18=0x6D6D, DQSOSC=389, MR23=63, INC=173, DEC=115
4461 11:07:56.678781
4462 11:07:56.681664 ----->DramcWriteLeveling(PI) begin...
4463 11:07:56.682091 ==
4464 11:07:56.683604 Dram Type= 6, Freq= 0, CH_1, rank 1
4465 11:07:56.687296 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4466 11:07:56.687824 ==
4467 11:07:56.690614 Write leveling (Byte 0): 27 => 27
4468 11:07:56.693365 Write leveling (Byte 1): 28 => 28
4469 11:07:56.696873 DramcWriteLeveling(PI) end<-----
4470 11:07:56.697395
4471 11:07:56.697732 ==
4472 11:07:56.700464 Dram Type= 6, Freq= 0, CH_1, rank 1
4473 11:07:56.703537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4474 11:07:56.703960 ==
4475 11:07:56.706795 [Gating] SW mode calibration
4476 11:07:56.713973 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4477 11:07:56.719881 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4478 11:07:56.723497 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4479 11:07:56.727623 0 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 0) (0 0)
4480 11:07:56.733297 0 5 8 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
4481 11:07:56.736689 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 11:07:56.740166 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 11:07:56.747186 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 11:07:56.749962 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 11:07:56.753178 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 11:07:56.760307 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 11:07:56.763499 0 6 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
4488 11:07:56.766238 0 6 8 | B1->B0 | 3434 4444 | 1 0 | (0 0) (0 0)
4489 11:07:56.773544 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 11:07:56.777076 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 11:07:56.780292 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 11:07:56.786517 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 11:07:56.790116 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 11:07:56.793505 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 11:07:56.799595 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4496 11:07:56.802703 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4497 11:07:56.805649 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 11:07:56.812696 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 11:07:56.815624 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 11:07:56.819467 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 11:07:56.826391 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 11:07:56.829216 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 11:07:56.832835 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 11:07:56.840075 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 11:07:56.842703 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 11:07:56.845316 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 11:07:56.851816 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 11:07:56.855722 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 11:07:56.858846 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 11:07:56.865786 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 11:07:56.869066 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4512 11:07:56.872576 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 11:07:56.875287 Total UI for P1: 0, mck2ui 16
4514 11:07:56.879062 best dqsien dly found for B0: ( 0, 9, 4)
4515 11:07:56.882269 Total UI for P1: 0, mck2ui 16
4516 11:07:56.885738 best dqsien dly found for B1: ( 0, 9, 6)
4517 11:07:56.888251 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4518 11:07:56.891603 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4519 11:07:56.892066
4520 11:07:56.898974 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4521 11:07:56.901728 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4522 11:07:56.902191 [Gating] SW calibration Done
4523 11:07:56.904806 ==
4524 11:07:56.908893 Dram Type= 6, Freq= 0, CH_1, rank 1
4525 11:07:56.911845 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4526 11:07:56.912310 ==
4527 11:07:56.912681 RX Vref Scan: 0
4528 11:07:56.913091
4529 11:07:56.914845 RX Vref 0 -> 0, step: 1
4530 11:07:56.915308
4531 11:07:56.918351 RX Delay -230 -> 252, step: 16
4532 11:07:56.921579 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4533 11:07:56.924592 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4534 11:07:56.932262 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4535 11:07:56.934806 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4536 11:07:56.938055 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4537 11:07:56.941703 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4538 11:07:56.948367 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4539 11:07:56.951562 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4540 11:07:56.954892 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4541 11:07:56.958114 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4542 11:07:56.961190 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4543 11:07:56.968081 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4544 11:07:56.971406 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4545 11:07:56.974399 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4546 11:07:56.977563 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4547 11:07:56.984368 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4548 11:07:56.984863 ==
4549 11:07:56.987326 Dram Type= 6, Freq= 0, CH_1, rank 1
4550 11:07:56.990913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4551 11:07:56.991374 ==
4552 11:07:56.991738 DQS Delay:
4553 11:07:56.993831 DQS0 = 0, DQS1 = 0
4554 11:07:56.994289 DQM Delay:
4555 11:07:56.998079 DQM0 = 40, DQM1 = 33
4556 11:07:56.998974 DQ Delay:
4557 11:07:57.000851 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4558 11:07:57.004904 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4559 11:07:57.008092 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4560 11:07:57.011160 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4561 11:07:57.011721
4562 11:07:57.012084
4563 11:07:57.012419 ==
4564 11:07:57.013989 Dram Type= 6, Freq= 0, CH_1, rank 1
4565 11:07:57.020905 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4566 11:07:57.021463 ==
4567 11:07:57.021832
4568 11:07:57.022170
4569 11:07:57.022492 TX Vref Scan disable
4570 11:07:57.023711 == TX Byte 0 ==
4571 11:07:57.027701 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4572 11:07:57.034336 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4573 11:07:57.034898 == TX Byte 1 ==
4574 11:07:57.037598 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4575 11:07:57.043567 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4576 11:07:57.044089 ==
4577 11:07:57.047353 Dram Type= 6, Freq= 0, CH_1, rank 1
4578 11:07:57.050354 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4579 11:07:57.050816 ==
4580 11:07:57.051184
4581 11:07:57.051613
4582 11:07:57.053696 TX Vref Scan disable
4583 11:07:57.058380 == TX Byte 0 ==
4584 11:07:57.060199 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4585 11:07:57.063544 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4586 11:07:57.067115 == TX Byte 1 ==
4587 11:07:57.070153 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4588 11:07:57.074014 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4589 11:07:57.074438
4590 11:07:57.074773 [DATLAT]
4591 11:07:57.076760 Freq=600, CH1 RK1
4592 11:07:57.077182
4593 11:07:57.080008 DATLAT Default: 0x8
4594 11:07:57.080426 0, 0xFFFF, sum = 0
4595 11:07:57.083352 1, 0xFFFF, sum = 0
4596 11:07:57.083882 2, 0xFFFF, sum = 0
4597 11:07:57.086999 3, 0xFFFF, sum = 0
4598 11:07:57.087540 4, 0xFFFF, sum = 0
4599 11:07:57.089727 5, 0xFFFF, sum = 0
4600 11:07:57.090202 6, 0xFFFF, sum = 0
4601 11:07:57.093142 7, 0x0, sum = 1
4602 11:07:57.093589 8, 0x0, sum = 2
4603 11:07:57.096338 9, 0x0, sum = 3
4604 11:07:57.096818 10, 0x0, sum = 4
4605 11:07:57.097170 best_step = 8
4606 11:07:57.097488
4607 11:07:57.100788 ==
4608 11:07:57.103424 Dram Type= 6, Freq= 0, CH_1, rank 1
4609 11:07:57.106929 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4610 11:07:57.107353 ==
4611 11:07:57.107682 RX Vref Scan: 0
4612 11:07:57.107997
4613 11:07:57.109433 RX Vref 0 -> 0, step: 1
4614 11:07:57.109850
4615 11:07:57.112810 RX Delay -195 -> 252, step: 8
4616 11:07:57.119826 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4617 11:07:57.123079 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4618 11:07:57.126697 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4619 11:07:57.129455 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4620 11:07:57.133004 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4621 11:07:57.140079 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4622 11:07:57.143308 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4623 11:07:57.146020 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4624 11:07:57.149732 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4625 11:07:57.156548 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4626 11:07:57.161248 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4627 11:07:57.162794 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4628 11:07:57.166219 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4629 11:07:57.172939 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4630 11:07:57.175706 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4631 11:07:57.180344 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4632 11:07:57.180912 ==
4633 11:07:57.182304 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 11:07:57.185641 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4635 11:07:57.189184 ==
4636 11:07:57.189600 DQS Delay:
4637 11:07:57.190046 DQS0 = 0, DQS1 = 0
4638 11:07:57.193189 DQM Delay:
4639 11:07:57.193619 DQM0 = 37, DQM1 = 29
4640 11:07:57.195744 DQ Delay:
4641 11:07:57.196176 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4642 11:07:57.199145 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4643 11:07:57.202631 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4644 11:07:57.205971 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4645 11:07:57.209441
4646 11:07:57.209940
4647 11:07:57.216091 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4648 11:07:57.219617 CH1 RK1: MR19=808, MR18=5F5F
4649 11:07:57.225570 CH1_RK1: MR19=0x808, MR18=0x5F5F, DQSOSC=391, MR23=63, INC=171, DEC=114
4650 11:07:57.228857 [RxdqsGatingPostProcess] freq 600
4651 11:07:57.231851 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4652 11:07:57.235250 Pre-setting of DQS Precalculation
4653 11:07:57.242082 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4654 11:07:57.248593 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4655 11:07:57.255984 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4656 11:07:57.256504
4657 11:07:57.256910
4658 11:07:57.258940 [Calibration Summary] 1200 Mbps
4659 11:07:57.259453 CH 0, Rank 0
4660 11:07:57.262007 SW Impedance : PASS
4661 11:07:57.265215 DUTY Scan : NO K
4662 11:07:57.265645 ZQ Calibration : PASS
4663 11:07:57.268536 Jitter Meter : NO K
4664 11:07:57.269067 CBT Training : PASS
4665 11:07:57.272065 Write leveling : PASS
4666 11:07:57.275600 RX DQS gating : PASS
4667 11:07:57.276010 RX DQ/DQS(RDDQC) : PASS
4668 11:07:57.278469 TX DQ/DQS : PASS
4669 11:07:57.281714 RX DATLAT : PASS
4670 11:07:57.282124 RX DQ/DQS(Engine): PASS
4671 11:07:57.285914 TX OE : NO K
4672 11:07:57.286424 All Pass.
4673 11:07:57.286756
4674 11:07:57.288623 CH 0, Rank 1
4675 11:07:57.289086 SW Impedance : PASS
4676 11:07:57.292448 DUTY Scan : NO K
4677 11:07:57.296283 ZQ Calibration : PASS
4678 11:07:57.296878 Jitter Meter : NO K
4679 11:07:57.298690 CBT Training : PASS
4680 11:07:57.302045 Write leveling : PASS
4681 11:07:57.302460 RX DQS gating : PASS
4682 11:07:57.305794 RX DQ/DQS(RDDQC) : PASS
4683 11:07:57.308871 TX DQ/DQS : PASS
4684 11:07:57.309380 RX DATLAT : PASS
4685 11:07:57.311697 RX DQ/DQS(Engine): PASS
4686 11:07:57.314896 TX OE : NO K
4687 11:07:57.315314 All Pass.
4688 11:07:57.315644
4689 11:07:57.315949 CH 1, Rank 0
4690 11:07:57.318391 SW Impedance : PASS
4691 11:07:57.321898 DUTY Scan : NO K
4692 11:07:57.322404 ZQ Calibration : PASS
4693 11:07:57.325675 Jitter Meter : NO K
4694 11:07:57.328447 CBT Training : PASS
4695 11:07:57.329056 Write leveling : PASS
4696 11:07:57.331770 RX DQS gating : PASS
4697 11:07:57.332304 RX DQ/DQS(RDDQC) : PASS
4698 11:07:57.336026 TX DQ/DQS : PASS
4699 11:07:57.338503 RX DATLAT : PASS
4700 11:07:57.338943 RX DQ/DQS(Engine): PASS
4701 11:07:57.341485 TX OE : NO K
4702 11:07:57.341919 All Pass.
4703 11:07:57.342359
4704 11:07:57.344992 CH 1, Rank 1
4705 11:07:57.345422 SW Impedance : PASS
4706 11:07:57.348451 DUTY Scan : NO K
4707 11:07:57.352031 ZQ Calibration : PASS
4708 11:07:57.352578 Jitter Meter : NO K
4709 11:07:57.354910 CBT Training : PASS
4710 11:07:57.357917 Write leveling : PASS
4711 11:07:57.358352 RX DQS gating : PASS
4712 11:07:57.361494 RX DQ/DQS(RDDQC) : PASS
4713 11:07:57.364523 TX DQ/DQS : PASS
4714 11:07:57.364972 RX DATLAT : PASS
4715 11:07:57.367795 RX DQ/DQS(Engine): PASS
4716 11:07:57.371657 TX OE : NO K
4717 11:07:57.372069 All Pass.
4718 11:07:57.372566
4719 11:07:57.372996 DramC Write-DBI off
4720 11:07:57.374316 PER_BANK_REFRESH: Hybrid Mode
4721 11:07:57.377770 TX_TRACKING: ON
4722 11:07:57.384248 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4723 11:07:57.387669 [FAST_K] Save calibration result to emmc
4724 11:07:57.394453 dramc_set_vcore_voltage set vcore to 662500
4725 11:07:57.394870 Read voltage for 933, 3
4726 11:07:57.398113 Vio18 = 0
4727 11:07:57.398523 Vcore = 662500
4728 11:07:57.398885 Vdram = 0
4729 11:07:57.400922 Vddq = 0
4730 11:07:57.401347 Vmddr = 0
4731 11:07:57.404385 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4732 11:07:57.412098 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4733 11:07:57.414698 MEM_TYPE=3, freq_sel=17
4734 11:07:57.417620 sv_algorithm_assistance_LP4_1600
4735 11:07:57.421273 ============ PULL DRAM RESETB DOWN ============
4736 11:07:57.423964 ========== PULL DRAM RESETB DOWN end =========
4737 11:07:57.428233 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4738 11:07:57.431110 ===================================
4739 11:07:57.434151 LPDDR4 DRAM CONFIGURATION
4740 11:07:57.436948 ===================================
4741 11:07:57.441031 EX_ROW_EN[0] = 0x0
4742 11:07:57.441442 EX_ROW_EN[1] = 0x0
4743 11:07:57.444595 LP4Y_EN = 0x0
4744 11:07:57.445172 WORK_FSP = 0x0
4745 11:07:57.447876 WL = 0x3
4746 11:07:57.448373 RL = 0x3
4747 11:07:57.451109 BL = 0x2
4748 11:07:57.451544 RPST = 0x0
4749 11:07:57.454339 RD_PRE = 0x0
4750 11:07:57.457757 WR_PRE = 0x1
4751 11:07:57.458174 WR_PST = 0x0
4752 11:07:57.460753 DBI_WR = 0x0
4753 11:07:57.461279 DBI_RD = 0x0
4754 11:07:57.463856 OTF = 0x1
4755 11:07:57.466753 ===================================
4756 11:07:57.470471 ===================================
4757 11:07:57.470911 ANA top config
4758 11:07:57.473528 ===================================
4759 11:07:57.476896 DLL_ASYNC_EN = 0
4760 11:07:57.481059 ALL_SLAVE_EN = 1
4761 11:07:57.481501 NEW_RANK_MODE = 1
4762 11:07:57.484470 DLL_IDLE_MODE = 1
4763 11:07:57.487328 LP45_APHY_COMB_EN = 1
4764 11:07:57.490698 TX_ODT_DIS = 1
4765 11:07:57.491118 NEW_8X_MODE = 1
4766 11:07:57.494273 ===================================
4767 11:07:57.497457 ===================================
4768 11:07:57.500065 data_rate = 1866
4769 11:07:57.503900 CKR = 1
4770 11:07:57.507892 DQ_P2S_RATIO = 8
4771 11:07:57.510630 ===================================
4772 11:07:57.514528 CA_P2S_RATIO = 8
4773 11:07:57.516629 DQ_CA_OPEN = 0
4774 11:07:57.517141 DQ_SEMI_OPEN = 0
4775 11:07:57.520841 CA_SEMI_OPEN = 0
4776 11:07:57.523761 CA_FULL_RATE = 0
4777 11:07:57.527023 DQ_CKDIV4_EN = 1
4778 11:07:57.531404 CA_CKDIV4_EN = 1
4779 11:07:57.533649 CA_PREDIV_EN = 0
4780 11:07:57.534067 PH8_DLY = 0
4781 11:07:57.537275 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4782 11:07:57.540076 DQ_AAMCK_DIV = 4
4783 11:07:57.544385 CA_AAMCK_DIV = 4
4784 11:07:57.546917 CA_ADMCK_DIV = 4
4785 11:07:57.550325 DQ_TRACK_CA_EN = 0
4786 11:07:57.553207 CA_PICK = 933
4787 11:07:57.553659 CA_MCKIO = 933
4788 11:07:57.557031 MCKIO_SEMI = 0
4789 11:07:57.560243 PLL_FREQ = 3732
4790 11:07:57.563536 DQ_UI_PI_RATIO = 32
4791 11:07:57.566278 CA_UI_PI_RATIO = 0
4792 11:07:57.569821 ===================================
4793 11:07:57.573038 ===================================
4794 11:07:57.576467 memory_type:LPDDR4
4795 11:07:57.577066 GP_NUM : 10
4796 11:07:57.579809 SRAM_EN : 1
4797 11:07:57.580360 MD32_EN : 0
4798 11:07:57.583080 ===================================
4799 11:07:57.586661 [ANA_INIT] >>>>>>>>>>>>>>
4800 11:07:57.589663 <<<<<< [CONFIGURE PHASE]: ANA_TX
4801 11:07:57.593016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4802 11:07:57.596907 ===================================
4803 11:07:57.599906 data_rate = 1866,PCW = 0X8f00
4804 11:07:57.603058 ===================================
4805 11:07:57.606621 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4806 11:07:57.612882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4807 11:07:57.616121 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4808 11:07:57.622815 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4809 11:07:57.626938 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4810 11:07:57.629574 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4811 11:07:57.630190 [ANA_INIT] flow start
4812 11:07:57.632655 [ANA_INIT] PLL >>>>>>>>
4813 11:07:57.635895 [ANA_INIT] PLL <<<<<<<<
4814 11:07:57.636358 [ANA_INIT] MIDPI >>>>>>>>
4815 11:07:57.640619 [ANA_INIT] MIDPI <<<<<<<<
4816 11:07:57.642591 [ANA_INIT] DLL >>>>>>>>
4817 11:07:57.643067 [ANA_INIT] flow end
4818 11:07:57.650110 ============ LP4 DIFF to SE enter ============
4819 11:07:57.652891 ============ LP4 DIFF to SE exit ============
4820 11:07:57.656018 [ANA_INIT] <<<<<<<<<<<<<
4821 11:07:57.659523 [Flow] Enable top DCM control >>>>>
4822 11:07:57.662510 [Flow] Enable top DCM control <<<<<
4823 11:07:57.662994 Enable DLL master slave shuffle
4824 11:07:57.669305 ==============================================================
4825 11:07:57.672465 Gating Mode config
4826 11:07:57.676306 ==============================================================
4827 11:07:57.679351 Config description:
4828 11:07:57.689391 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4829 11:07:57.695641 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4830 11:07:57.699056 SELPH_MODE 0: By rank 1: By Phase
4831 11:07:57.705214 ==============================================================
4832 11:07:57.709214 GAT_TRACK_EN = 1
4833 11:07:57.712069 RX_GATING_MODE = 2
4834 11:07:57.715245 RX_GATING_TRACK_MODE = 2
4835 11:07:57.718706 SELPH_MODE = 1
4836 11:07:57.719168 PICG_EARLY_EN = 1
4837 11:07:57.724015 VALID_LAT_VALUE = 1
4838 11:07:57.728496 ==============================================================
4839 11:07:57.733210 Enter into Gating configuration >>>>
4840 11:07:57.735168 Exit from Gating configuration <<<<
4841 11:07:57.738504 Enter into DVFS_PRE_config >>>>>
4842 11:07:57.748789 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4843 11:07:57.751690 Exit from DVFS_PRE_config <<<<<
4844 11:07:57.754965 Enter into PICG configuration >>>>
4845 11:07:57.758989 Exit from PICG configuration <<<<
4846 11:07:57.761737 [RX_INPUT] configuration >>>>>
4847 11:07:57.764732 [RX_INPUT] configuration <<<<<
4848 11:07:57.771667 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4849 11:07:57.774525 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4850 11:07:57.780995 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4851 11:07:57.787703 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4852 11:07:57.794868 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4853 11:07:57.800597 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4854 11:07:57.803685 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4855 11:07:57.807304 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4856 11:07:57.811462 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4857 11:07:57.818082 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4858 11:07:57.820638 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4859 11:07:57.824023 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4860 11:07:57.827332 ===================================
4861 11:07:57.830168 LPDDR4 DRAM CONFIGURATION
4862 11:07:57.833608 ===================================
4863 11:07:57.836957 EX_ROW_EN[0] = 0x0
4864 11:07:57.837503 EX_ROW_EN[1] = 0x0
4865 11:07:57.840594 LP4Y_EN = 0x0
4866 11:07:57.841249 WORK_FSP = 0x0
4867 11:07:57.844015 WL = 0x3
4868 11:07:57.844478 RL = 0x3
4869 11:07:57.847021 BL = 0x2
4870 11:07:57.847545 RPST = 0x0
4871 11:07:57.850450 RD_PRE = 0x0
4872 11:07:57.850975 WR_PRE = 0x1
4873 11:07:57.854320 WR_PST = 0x0
4874 11:07:57.854785 DBI_WR = 0x0
4875 11:07:57.857426 DBI_RD = 0x0
4876 11:07:57.860954 OTF = 0x1
4877 11:07:57.861498 ===================================
4878 11:07:57.866994 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4879 11:07:57.870324 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4880 11:07:57.873493 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4881 11:07:57.876619 ===================================
4882 11:07:57.879901 LPDDR4 DRAM CONFIGURATION
4883 11:07:57.883570 ===================================
4884 11:07:57.886679 EX_ROW_EN[0] = 0x10
4885 11:07:57.887223 EX_ROW_EN[1] = 0x0
4886 11:07:57.889913 LP4Y_EN = 0x0
4887 11:07:57.890461 WORK_FSP = 0x0
4888 11:07:57.893196 WL = 0x3
4889 11:07:57.893656 RL = 0x3
4890 11:07:57.896765 BL = 0x2
4891 11:07:57.897230 RPST = 0x0
4892 11:07:57.899965 RD_PRE = 0x0
4893 11:07:57.900522 WR_PRE = 0x1
4894 11:07:57.903468 WR_PST = 0x0
4895 11:07:57.904003 DBI_WR = 0x0
4896 11:07:57.907187 DBI_RD = 0x0
4897 11:07:57.909659 OTF = 0x1
4898 11:07:57.912580 ===================================
4899 11:07:57.915768 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4900 11:07:57.921380 nWR fixed to 30
4901 11:07:57.925020 [ModeRegInit_LP4] CH0 RK0
4902 11:07:57.925586 [ModeRegInit_LP4] CH0 RK1
4903 11:07:57.927941 [ModeRegInit_LP4] CH1 RK0
4904 11:07:57.931583 [ModeRegInit_LP4] CH1 RK1
4905 11:07:57.932139 match AC timing 8
4906 11:07:57.937787 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4907 11:07:57.941128 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4908 11:07:57.944621 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4909 11:07:57.951106 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4910 11:07:57.955212 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4911 11:07:57.955769 ==
4912 11:07:57.958435 Dram Type= 6, Freq= 0, CH_0, rank 0
4913 11:07:57.962345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4914 11:07:57.962934 ==
4915 11:07:57.967800 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4916 11:07:57.974611 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4917 11:07:57.977437 [CA 0] Center 39 (8~70) winsize 63
4918 11:07:57.980927 [CA 1] Center 38 (8~69) winsize 62
4919 11:07:57.984028 [CA 2] Center 36 (6~67) winsize 62
4920 11:07:57.987293 [CA 3] Center 36 (6~67) winsize 62
4921 11:07:57.990535 [CA 4] Center 34 (4~65) winsize 62
4922 11:07:57.993644 [CA 5] Center 34 (4~65) winsize 62
4923 11:07:57.994161
4924 11:07:57.997509 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4925 11:07:57.997967
4926 11:07:58.000667 [CATrainingPosCal] consider 1 rank data
4927 11:07:58.003987 u2DelayCellTimex100 = 270/100 ps
4928 11:07:58.006683 CA0 delay=39 (8~70),Diff = 5 PI (31 cell)
4929 11:07:58.010654 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4930 11:07:58.014026 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4931 11:07:58.017147 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4932 11:07:58.024047 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4933 11:07:58.027256 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4934 11:07:58.027815
4935 11:07:58.030040 CA PerBit enable=1, Macro0, CA PI delay=34
4936 11:07:58.030495
4937 11:07:58.034196 [CBTSetCACLKResult] CA Dly = 34
4938 11:07:58.034757 CS Dly: 7 (0~38)
4939 11:07:58.035121 ==
4940 11:07:58.036962 Dram Type= 6, Freq= 0, CH_0, rank 1
4941 11:07:58.043797 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4942 11:07:58.044387 ==
4943 11:07:58.047020 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4944 11:07:58.053212 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4945 11:07:58.058395 [CA 0] Center 38 (8~69) winsize 62
4946 11:07:58.059971 [CA 1] Center 38 (8~69) winsize 62
4947 11:07:58.063244 [CA 2] Center 36 (5~67) winsize 63
4948 11:07:58.066467 [CA 3] Center 35 (5~66) winsize 62
4949 11:07:58.070027 [CA 4] Center 34 (4~65) winsize 62
4950 11:07:58.074091 [CA 5] Center 34 (4~65) winsize 62
4951 11:07:58.074548
4952 11:07:58.076678 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4953 11:07:58.077204
4954 11:07:58.080170 [CATrainingPosCal] consider 2 rank data
4955 11:07:58.083038 u2DelayCellTimex100 = 270/100 ps
4956 11:07:58.086298 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4957 11:07:58.089321 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4958 11:07:58.096694 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4959 11:07:58.100052 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4960 11:07:58.103123 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4961 11:07:58.106233 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4962 11:07:58.106691
4963 11:07:58.109584 CA PerBit enable=1, Macro0, CA PI delay=34
4964 11:07:58.110039
4965 11:07:58.112985 [CBTSetCACLKResult] CA Dly = 34
4966 11:07:58.113535 CS Dly: 7 (0~39)
4967 11:07:58.116117
4968 11:07:58.119416 ----->DramcWriteLeveling(PI) begin...
4969 11:07:58.119877 ==
4970 11:07:58.122793 Dram Type= 6, Freq= 0, CH_0, rank 0
4971 11:07:58.125895 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4972 11:07:58.126451 ==
4973 11:07:58.129627 Write leveling (Byte 0): 28 => 28
4974 11:07:58.132533 Write leveling (Byte 1): 28 => 28
4975 11:07:58.136069 DramcWriteLeveling(PI) end<-----
4976 11:07:58.136521
4977 11:07:58.136942 ==
4978 11:07:58.139032 Dram Type= 6, Freq= 0, CH_0, rank 0
4979 11:07:58.142684 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4980 11:07:58.143143 ==
4981 11:07:58.146140 [Gating] SW mode calibration
4982 11:07:58.152755 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4983 11:07:58.159144 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4984 11:07:58.162532 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4985 11:07:58.165873 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4986 11:07:58.172419 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4987 11:07:58.175732 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4988 11:07:58.179359 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4989 11:07:58.185520 0 10 20 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4990 11:07:58.189410 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
4991 11:07:58.191845 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4992 11:07:58.198540 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4993 11:07:58.202048 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4994 11:07:58.205293 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4995 11:07:58.211958 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4996 11:07:58.215387 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4997 11:07:58.218648 0 11 20 | B1->B0 | 2727 3131 | 1 1 | (0 0) (0 0)
4998 11:07:58.225150 0 11 24 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4999 11:07:58.228376 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5000 11:07:58.232076 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5001 11:07:58.238449 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5002 11:07:58.242464 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5003 11:07:58.245105 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5004 11:07:58.251900 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5005 11:07:58.254571 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5006 11:07:58.259368 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5007 11:07:58.264824 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5008 11:07:58.268383 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5009 11:07:58.271645 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5010 11:07:58.278751 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5011 11:07:58.281248 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5012 11:07:58.284692 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5013 11:07:58.291531 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5014 11:07:58.294787 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5015 11:07:58.298798 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5016 11:07:58.304970 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5017 11:07:58.307653 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5018 11:07:58.311190 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5019 11:07:58.317586 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5020 11:07:58.321021 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5021 11:07:58.324263 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5022 11:07:58.330968 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5023 11:07:58.334341 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5024 11:07:58.337539 Total UI for P1: 0, mck2ui 16
5025 11:07:58.342086 best dqsien dly found for B0: ( 0, 14, 22)
5026 11:07:58.344289 Total UI for P1: 0, mck2ui 16
5027 11:07:58.347465 best dqsien dly found for B1: ( 0, 14, 22)
5028 11:07:58.350524 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5029 11:07:58.353547 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5030 11:07:58.354055
5031 11:07:58.357493 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5032 11:07:58.360419 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5033 11:07:58.363841 [Gating] SW calibration Done
5034 11:07:58.364358 ==
5035 11:07:58.367227 Dram Type= 6, Freq= 0, CH_0, rank 0
5036 11:07:58.370219 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5037 11:07:58.373408 ==
5038 11:07:58.373953 RX Vref Scan: 0
5039 11:07:58.374292
5040 11:07:58.376928 RX Vref 0 -> 0, step: 1
5041 11:07:58.377568
5042 11:07:58.380964 RX Delay -80 -> 252, step: 8
5043 11:07:58.383536 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5044 11:07:58.387345 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5045 11:07:58.390033 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5046 11:07:58.393677 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5047 11:07:58.396482 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5048 11:07:58.403576 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5049 11:07:58.406494 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5050 11:07:58.409855 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5051 11:07:58.413391 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5052 11:07:58.416643 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5053 11:07:58.423069 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5054 11:07:58.426594 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5055 11:07:58.430107 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5056 11:07:58.432982 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5057 11:07:58.436333 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5058 11:07:58.442763 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5059 11:07:58.443346 ==
5060 11:07:58.446693 Dram Type= 6, Freq= 0, CH_0, rank 0
5061 11:07:58.449916 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5062 11:07:58.450486 ==
5063 11:07:58.450854 DQS Delay:
5064 11:07:58.453288 DQS0 = 0, DQS1 = 0
5065 11:07:58.453860 DQM Delay:
5066 11:07:58.456221 DQM0 = 95, DQM1 = 84
5067 11:07:58.456756 DQ Delay:
5068 11:07:58.459893 DQ0 =91, DQ1 =95, DQ2 =95, DQ3 =87
5069 11:07:58.463251 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5070 11:07:58.466248 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5071 11:07:58.469292 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5072 11:07:58.469848
5073 11:07:58.470215
5074 11:07:58.470553 ==
5075 11:07:58.472899 Dram Type= 6, Freq= 0, CH_0, rank 0
5076 11:07:58.475678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5077 11:07:58.479353 ==
5078 11:07:58.479812
5079 11:07:58.480174
5080 11:07:58.480512 TX Vref Scan disable
5081 11:07:58.483031 == TX Byte 0 ==
5082 11:07:58.486161 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5083 11:07:58.489084 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5084 11:07:58.492301 == TX Byte 1 ==
5085 11:07:58.495846 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5086 11:07:58.498846 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5087 11:07:58.502283 ==
5088 11:07:58.502769 Dram Type= 6, Freq= 0, CH_0, rank 0
5089 11:07:58.509722 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5090 11:07:58.510283 ==
5091 11:07:58.510657
5092 11:07:58.510995
5093 11:07:58.512459 TX Vref Scan disable
5094 11:07:58.512972 == TX Byte 0 ==
5095 11:07:58.519642 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5096 11:07:58.522168 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5097 11:07:58.522723 == TX Byte 1 ==
5098 11:07:58.528997 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5099 11:07:58.533434 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5100 11:07:58.534173
5101 11:07:58.534777 [DATLAT]
5102 11:07:58.535651 Freq=933, CH0 RK0
5103 11:07:58.536048
5104 11:07:58.536393 DATLAT Default: 0xd
5105 11:07:58.538709 0, 0xFFFF, sum = 0
5106 11:07:58.539178 1, 0xFFFF, sum = 0
5107 11:07:58.542494 2, 0xFFFF, sum = 0
5108 11:07:58.543076 3, 0xFFFF, sum = 0
5109 11:07:58.545254 4, 0xFFFF, sum = 0
5110 11:07:58.545757 5, 0xFFFF, sum = 0
5111 11:07:58.549194 6, 0xFFFF, sum = 0
5112 11:07:58.549761 7, 0xFFFF, sum = 0
5113 11:07:58.551942 8, 0xFFFF, sum = 0
5114 11:07:58.552513 9, 0xFFFF, sum = 0
5115 11:07:58.555666 10, 0x0, sum = 1
5116 11:07:58.556135 11, 0x0, sum = 2
5117 11:07:58.558338 12, 0x0, sum = 3
5118 11:07:58.558800 13, 0x0, sum = 4
5119 11:07:58.562391 best_step = 11
5120 11:07:58.562946
5121 11:07:58.563310 ==
5122 11:07:58.564924 Dram Type= 6, Freq= 0, CH_0, rank 0
5123 11:07:58.568621 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5124 11:07:58.569247 ==
5125 11:07:58.572480 RX Vref Scan: 1
5126 11:07:58.573101
5127 11:07:58.573475 RX Vref 0 -> 0, step: 1
5128 11:07:58.573818
5129 11:07:58.575064 RX Delay -77 -> 252, step: 4
5130 11:07:58.575521
5131 11:07:58.578438 Set Vref, RX VrefLevel [Byte0]: 53
5132 11:07:58.582429 [Byte1]: 48
5133 11:07:58.586219
5134 11:07:58.586678 Final RX Vref Byte 0 = 53 to rank0
5135 11:07:58.590585 Final RX Vref Byte 1 = 48 to rank0
5136 11:07:58.592841 Final RX Vref Byte 0 = 53 to rank1
5137 11:07:58.595814 Final RX Vref Byte 1 = 48 to rank1==
5138 11:07:58.600111 Dram Type= 6, Freq= 0, CH_0, rank 0
5139 11:07:58.606080 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5140 11:07:58.606628 ==
5141 11:07:58.606995 DQS Delay:
5142 11:07:58.609043 DQS0 = 0, DQS1 = 0
5143 11:07:58.609500 DQM Delay:
5144 11:07:58.609866 DQM0 = 97, DQM1 = 87
5145 11:07:58.613012 DQ Delay:
5146 11:07:58.615931 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =94
5147 11:07:58.619991 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =102
5148 11:07:58.622560 DQ8 =76, DQ9 =72, DQ10 =86, DQ11 =78
5149 11:07:58.625883 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =98
5150 11:07:58.626446
5151 11:07:58.626813
5152 11:07:58.632202 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5153 11:07:58.635756 CH0 RK0: MR19=505, MR18=1E1E
5154 11:07:58.641813 CH0_RK0: MR19=0x505, MR18=0x1E1E, DQSOSC=412, MR23=63, INC=63, DEC=42
5155 11:07:58.642377
5156 11:07:58.645034 ----->DramcWriteLeveling(PI) begin...
5157 11:07:58.645503 ==
5158 11:07:58.649659 Dram Type= 6, Freq= 0, CH_0, rank 1
5159 11:07:58.652580 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5160 11:07:58.653190 ==
5161 11:07:58.655211 Write leveling (Byte 0): 30 => 30
5162 11:07:58.658582 Write leveling (Byte 1): 25 => 25
5163 11:07:58.662069 DramcWriteLeveling(PI) end<-----
5164 11:07:58.662647
5165 11:07:58.663011 ==
5166 11:07:58.665734 Dram Type= 6, Freq= 0, CH_0, rank 1
5167 11:07:58.672009 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5168 11:07:58.672572 ==
5169 11:07:58.673009 [Gating] SW mode calibration
5170 11:07:58.681793 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5171 11:07:58.684953 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5172 11:07:58.688209 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 11:07:58.695168 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 11:07:58.698092 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 11:07:58.701618 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 11:07:58.708329 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 11:07:58.711661 0 10 20 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 1)
5178 11:07:58.715349 0 10 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5179 11:07:58.721680 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 11:07:58.725928 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 11:07:58.728584 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 11:07:58.735272 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 11:07:58.738403 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 11:07:58.741257 0 11 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5185 11:07:58.748309 0 11 20 | B1->B0 | 3232 3535 | 0 0 | (0 0) (0 0)
5186 11:07:58.751713 0 11 24 | B1->B0 | 3a3a 4343 | 0 0 | (0 0) (0 0)
5187 11:07:58.755537 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 11:07:58.761630 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 11:07:58.764358 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 11:07:58.767995 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 11:07:58.773981 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 11:07:58.777362 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5193 11:07:58.780904 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5194 11:07:58.787475 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 11:07:58.791692 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 11:07:58.794131 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 11:07:58.800822 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 11:07:58.803696 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 11:07:58.807656 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 11:07:58.814104 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 11:07:58.817605 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 11:07:58.820247 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 11:07:58.827893 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 11:07:58.830676 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 11:07:58.833590 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 11:07:58.840545 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 11:07:58.844277 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 11:07:58.847580 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 11:07:58.853581 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5210 11:07:58.856901 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 11:07:58.861054 Total UI for P1: 0, mck2ui 16
5212 11:07:58.864004 best dqsien dly found for B0: ( 0, 14, 20)
5213 11:07:58.866872 Total UI for P1: 0, mck2ui 16
5214 11:07:58.870053 best dqsien dly found for B1: ( 0, 14, 20)
5215 11:07:58.873851 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5216 11:07:58.876580 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5217 11:07:58.877081
5218 11:07:58.881105 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5219 11:07:58.883471 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5220 11:07:58.887056 [Gating] SW calibration Done
5221 11:07:58.887630 ==
5222 11:07:58.889681 Dram Type= 6, Freq= 0, CH_0, rank 1
5223 11:07:58.896149 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5224 11:07:58.896611 ==
5225 11:07:58.897035 RX Vref Scan: 0
5226 11:07:58.897383
5227 11:07:58.900232 RX Vref 0 -> 0, step: 1
5228 11:07:58.900845
5229 11:07:58.903444 RX Delay -80 -> 252, step: 8
5230 11:07:58.906193 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5231 11:07:58.910116 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5232 11:07:58.913156 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5233 11:07:58.916474 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5234 11:07:58.923011 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5235 11:07:58.927801 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5236 11:07:58.930135 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5237 11:07:58.932889 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5238 11:07:58.936403 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5239 11:07:58.939392 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5240 11:07:58.945981 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5241 11:07:58.949514 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5242 11:07:58.952781 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5243 11:07:58.956054 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5244 11:07:58.959352 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5245 11:07:58.965660 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5246 11:07:58.966224 ==
5247 11:07:58.968826 Dram Type= 6, Freq= 0, CH_0, rank 1
5248 11:07:58.972587 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5249 11:07:58.973191 ==
5250 11:07:58.973559 DQS Delay:
5251 11:07:58.975752 DQS0 = 0, DQS1 = 0
5252 11:07:58.976218 DQM Delay:
5253 11:07:58.978768 DQM0 = 96, DQM1 = 85
5254 11:07:58.979223 DQ Delay:
5255 11:07:58.982251 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5256 11:07:58.985120 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5257 11:07:58.988514 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5258 11:07:58.992580 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =95
5259 11:07:58.993195
5260 11:07:58.993572
5261 11:07:58.993908 ==
5262 11:07:58.994985 Dram Type= 6, Freq= 0, CH_0, rank 1
5263 11:07:59.001880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5264 11:07:59.002445 ==
5265 11:07:59.002881
5266 11:07:59.003360
5267 11:07:59.003768 TX Vref Scan disable
5268 11:07:59.005213 == TX Byte 0 ==
5269 11:07:59.008838 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5270 11:07:59.015506 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5271 11:07:59.016068 == TX Byte 1 ==
5272 11:07:59.018979 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5273 11:07:59.025382 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5274 11:07:59.025945 ==
5275 11:07:59.029817 Dram Type= 6, Freq= 0, CH_0, rank 1
5276 11:07:59.031263 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5277 11:07:59.031722 ==
5278 11:07:59.032085
5279 11:07:59.032420
5280 11:07:59.034776 TX Vref Scan disable
5281 11:07:59.038383 == TX Byte 0 ==
5282 11:07:59.041346 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5283 11:07:59.044749 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5284 11:07:59.048825 == TX Byte 1 ==
5285 11:07:59.051773 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5286 11:07:59.054674 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5287 11:07:59.055131
5288 11:07:59.055493 [DATLAT]
5289 11:07:59.057847 Freq=933, CH0 RK1
5290 11:07:59.058306
5291 11:07:59.060894 DATLAT Default: 0xb
5292 11:07:59.061351 0, 0xFFFF, sum = 0
5293 11:07:59.064408 1, 0xFFFF, sum = 0
5294 11:07:59.064904 2, 0xFFFF, sum = 0
5295 11:07:59.068776 3, 0xFFFF, sum = 0
5296 11:07:59.069350 4, 0xFFFF, sum = 0
5297 11:07:59.071518 5, 0xFFFF, sum = 0
5298 11:07:59.072087 6, 0xFFFF, sum = 0
5299 11:07:59.074441 7, 0xFFFF, sum = 0
5300 11:07:59.074909 8, 0xFFFF, sum = 0
5301 11:07:59.077510 9, 0xFFFF, sum = 0
5302 11:07:59.077979 10, 0x0, sum = 1
5303 11:07:59.081432 11, 0x0, sum = 2
5304 11:07:59.081898 12, 0x0, sum = 3
5305 11:07:59.085419 13, 0x0, sum = 4
5306 11:07:59.085889 best_step = 11
5307 11:07:59.086217
5308 11:07:59.086521 ==
5309 11:07:59.089282 Dram Type= 6, Freq= 0, CH_0, rank 1
5310 11:07:59.091192 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5311 11:07:59.094539 ==
5312 11:07:59.094953 RX Vref Scan: 0
5313 11:07:59.095413
5314 11:07:59.097394 RX Vref 0 -> 0, step: 1
5315 11:07:59.097808
5316 11:07:59.100683 RX Delay -69 -> 252, step: 4
5317 11:07:59.105052 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5318 11:07:59.107211 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5319 11:07:59.110817 iDelay=203, Bit 2, Center 98 (7 ~ 190) 184
5320 11:07:59.117207 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5321 11:07:59.120483 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5322 11:07:59.124525 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5323 11:07:59.127833 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5324 11:07:59.130472 iDelay=203, Bit 7, Center 106 (11 ~ 202) 192
5325 11:07:59.137478 iDelay=203, Bit 8, Center 76 (-9 ~ 162) 172
5326 11:07:59.140435 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5327 11:07:59.143530 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5328 11:07:59.147289 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5329 11:07:59.150248 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5330 11:07:59.157486 iDelay=203, Bit 13, Center 92 (3 ~ 182) 180
5331 11:07:59.160299 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5332 11:07:59.163500 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5333 11:07:59.163914 ==
5334 11:07:59.166644 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 11:07:59.170844 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5336 11:07:59.171372 ==
5337 11:07:59.173175 DQS Delay:
5338 11:07:59.173587 DQS0 = 0, DQS1 = 0
5339 11:07:59.173917 DQM Delay:
5340 11:07:59.176811 DQM0 = 97, DQM1 = 86
5341 11:07:59.177465 DQ Delay:
5342 11:07:59.179641 DQ0 =92, DQ1 =96, DQ2 =98, DQ3 =92
5343 11:07:59.183140 DQ4 =102, DQ5 =90, DQ6 =104, DQ7 =106
5344 11:07:59.186621 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5345 11:07:59.189669 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =94
5346 11:07:59.190088
5347 11:07:59.190414
5348 11:07:59.200909 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c2c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5349 11:07:59.202956 CH0 RK1: MR19=505, MR18=2C2C
5350 11:07:59.209927 CH0_RK1: MR19=0x505, MR18=0x2C2C, DQSOSC=408, MR23=63, INC=65, DEC=43
5351 11:07:59.210456 [RxdqsGatingPostProcess] freq 933
5352 11:07:59.216968 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5353 11:07:59.219671 Pre-setting of DQS Precalculation
5354 11:07:59.226679 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5355 11:07:59.227213 ==
5356 11:07:59.229865 Dram Type= 6, Freq= 0, CH_1, rank 0
5357 11:07:59.233460 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5358 11:07:59.233983 ==
5359 11:07:59.238956 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5360 11:07:59.242502 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5361 11:07:59.246400 [CA 0] Center 37 (7~68) winsize 62
5362 11:07:59.249655 [CA 1] Center 37 (6~68) winsize 63
5363 11:07:59.252977 [CA 2] Center 34 (4~65) winsize 62
5364 11:07:59.256082 [CA 3] Center 34 (4~65) winsize 62
5365 11:07:59.260441 [CA 4] Center 33 (3~64) winsize 62
5366 11:07:59.263136 [CA 5] Center 33 (3~64) winsize 62
5367 11:07:59.263646
5368 11:07:59.266586 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5369 11:07:59.266999
5370 11:07:59.270090 [CATrainingPosCal] consider 1 rank data
5371 11:07:59.273182 u2DelayCellTimex100 = 270/100 ps
5372 11:07:59.276593 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5373 11:07:59.282736 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5374 11:07:59.285968 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5375 11:07:59.289420 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5376 11:07:59.292669 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5377 11:07:59.296167 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5378 11:07:59.296579
5379 11:07:59.300142 CA PerBit enable=1, Macro0, CA PI delay=33
5380 11:07:59.300552
5381 11:07:59.303082 [CBTSetCACLKResult] CA Dly = 33
5382 11:07:59.303493 CS Dly: 5 (0~36)
5383 11:07:59.306276 ==
5384 11:07:59.309388 Dram Type= 6, Freq= 0, CH_1, rank 1
5385 11:07:59.313161 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5386 11:07:59.313574 ==
5387 11:07:59.315935 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5388 11:07:59.323344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5389 11:07:59.326430 [CA 0] Center 37 (6~68) winsize 63
5390 11:07:59.330619 [CA 1] Center 37 (6~68) winsize 63
5391 11:07:59.333357 [CA 2] Center 34 (4~65) winsize 62
5392 11:07:59.336630 [CA 3] Center 34 (4~64) winsize 61
5393 11:07:59.339947 [CA 4] Center 33 (2~64) winsize 63
5394 11:07:59.343436 [CA 5] Center 33 (2~64) winsize 63
5395 11:07:59.343990
5396 11:07:59.346799 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5397 11:07:59.347365
5398 11:07:59.349704 [CATrainingPosCal] consider 2 rank data
5399 11:07:59.353729 u2DelayCellTimex100 = 270/100 ps
5400 11:07:59.356258 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5401 11:07:59.362804 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5402 11:07:59.366369 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5403 11:07:59.369752 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5404 11:07:59.373039 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5405 11:07:59.376217 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5406 11:07:59.376672
5407 11:07:59.378958 CA PerBit enable=1, Macro0, CA PI delay=33
5408 11:07:59.379414
5409 11:07:59.382952 [CBTSetCACLKResult] CA Dly = 33
5410 11:07:59.385713 CS Dly: 5 (0~37)
5411 11:07:59.386167
5412 11:07:59.388830 ----->DramcWriteLeveling(PI) begin...
5413 11:07:59.389289 ==
5414 11:07:59.393473 Dram Type= 6, Freq= 0, CH_1, rank 0
5415 11:07:59.395701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5416 11:07:59.396180 ==
5417 11:07:59.399094 Write leveling (Byte 0): 23 => 23
5418 11:07:59.402589 Write leveling (Byte 1): 24 => 24
5419 11:07:59.405690 DramcWriteLeveling(PI) end<-----
5420 11:07:59.406142
5421 11:07:59.406497 ==
5422 11:07:59.409273 Dram Type= 6, Freq= 0, CH_1, rank 0
5423 11:07:59.412754 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5424 11:07:59.413330 ==
5425 11:07:59.415644 [Gating] SW mode calibration
5426 11:07:59.422486 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5427 11:07:59.428849 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5428 11:07:59.432158 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5429 11:07:59.435687 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5430 11:07:59.444059 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5431 11:07:59.445486 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5432 11:07:59.449238 0 10 16 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
5433 11:07:59.455814 0 10 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (1 0)
5434 11:07:59.459197 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5435 11:07:59.462466 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5436 11:07:59.469660 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5437 11:07:59.472866 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5438 11:07:59.475253 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5439 11:07:59.482265 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5440 11:07:59.486348 0 11 16 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
5441 11:07:59.488836 0 11 20 | B1->B0 | 2727 3e3e | 1 0 | (0 0) (0 0)
5442 11:07:59.495121 0 11 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5443 11:07:59.499863 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5444 11:07:59.502387 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5445 11:07:59.509180 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5446 11:07:59.511857 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5447 11:07:59.515289 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5448 11:07:59.521918 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5449 11:07:59.524540 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5450 11:07:59.528548 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 11:07:59.535514 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 11:07:59.538912 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 11:07:59.541763 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 11:07:59.547837 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 11:07:59.551310 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 11:07:59.554926 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 11:07:59.561795 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5458 11:07:59.564756 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5459 11:07:59.567901 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5460 11:07:59.571672 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5461 11:07:59.577841 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5462 11:07:59.582049 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5463 11:07:59.585250 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5464 11:07:59.591689 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5465 11:07:59.594972 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5466 11:07:59.597360 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5467 11:07:59.601528 Total UI for P1: 0, mck2ui 16
5468 11:07:59.604616 best dqsien dly found for B0: ( 0, 14, 20)
5469 11:07:59.607714 Total UI for P1: 0, mck2ui 16
5470 11:07:59.611722 best dqsien dly found for B1: ( 0, 14, 20)
5471 11:07:59.614097 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5472 11:07:59.620517 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5473 11:07:59.621132
5474 11:07:59.624297 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5475 11:07:59.627963 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5476 11:07:59.631137 [Gating] SW calibration Done
5477 11:07:59.631692 ==
5478 11:07:59.634157 Dram Type= 6, Freq= 0, CH_1, rank 0
5479 11:07:59.638137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5480 11:07:59.638594 ==
5481 11:07:59.640642 RX Vref Scan: 0
5482 11:07:59.641257
5483 11:07:59.641622 RX Vref 0 -> 0, step: 1
5484 11:07:59.641960
5485 11:07:59.644138 RX Delay -80 -> 252, step: 8
5486 11:07:59.648943 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5487 11:07:59.655073 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5488 11:07:59.657321 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5489 11:07:59.660405 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5490 11:07:59.663937 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5491 11:07:59.667145 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5492 11:07:59.670446 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5493 11:07:59.677006 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5494 11:07:59.680550 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5495 11:07:59.683365 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5496 11:07:59.688061 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5497 11:07:59.690839 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5498 11:07:59.693998 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5499 11:07:59.700872 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5500 11:07:59.704429 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5501 11:07:59.706841 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5502 11:07:59.707411 ==
5503 11:07:59.710337 Dram Type= 6, Freq= 0, CH_1, rank 0
5504 11:07:59.713245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5505 11:07:59.713723 ==
5506 11:07:59.717473 DQS Delay:
5507 11:07:59.718037 DQS0 = 0, DQS1 = 0
5508 11:07:59.720006 DQM Delay:
5509 11:07:59.720476 DQM0 = 94, DQM1 = 87
5510 11:07:59.721030 DQ Delay:
5511 11:07:59.723153 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5512 11:07:59.726711 DQ4 =91, DQ5 =107, DQ6 =99, DQ7 =91
5513 11:07:59.730220 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =79
5514 11:07:59.733155 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =95
5515 11:07:59.733631
5516 11:07:59.736788
5517 11:07:59.737258 ==
5518 11:07:59.739971 Dram Type= 6, Freq= 0, CH_1, rank 0
5519 11:07:59.742885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5520 11:07:59.743370 ==
5521 11:07:59.743854
5522 11:07:59.744352
5523 11:07:59.746297 TX Vref Scan disable
5524 11:07:59.746772 == TX Byte 0 ==
5525 11:07:59.754293 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5526 11:07:59.755932 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5527 11:07:59.756406 == TX Byte 1 ==
5528 11:07:59.762739 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5529 11:07:59.766347 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5530 11:07:59.766821 ==
5531 11:07:59.769635 Dram Type= 6, Freq= 0, CH_1, rank 0
5532 11:07:59.773038 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5533 11:07:59.773605 ==
5534 11:07:59.774095
5535 11:07:59.774548
5536 11:07:59.776561 TX Vref Scan disable
5537 11:07:59.779895 == TX Byte 0 ==
5538 11:07:59.782699 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5539 11:07:59.785973 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5540 11:07:59.789285 == TX Byte 1 ==
5541 11:07:59.792835 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5542 11:07:59.796396 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5543 11:07:59.797144
5544 11:07:59.799293 [DATLAT]
5545 11:07:59.799748 Freq=933, CH1 RK0
5546 11:07:59.800117
5547 11:07:59.803812 DATLAT Default: 0xd
5548 11:07:59.804363 0, 0xFFFF, sum = 0
5549 11:07:59.805606 1, 0xFFFF, sum = 0
5550 11:07:59.806071 2, 0xFFFF, sum = 0
5551 11:07:59.809177 3, 0xFFFF, sum = 0
5552 11:07:59.809645 4, 0xFFFF, sum = 0
5553 11:07:59.812611 5, 0xFFFF, sum = 0
5554 11:07:59.813116 6, 0xFFFF, sum = 0
5555 11:07:59.815947 7, 0xFFFF, sum = 0
5556 11:07:59.816506 8, 0xFFFF, sum = 0
5557 11:07:59.819041 9, 0xFFFF, sum = 0
5558 11:07:59.819504 10, 0x0, sum = 1
5559 11:07:59.822664 11, 0x0, sum = 2
5560 11:07:59.823226 12, 0x0, sum = 3
5561 11:07:59.825623 13, 0x0, sum = 4
5562 11:07:59.826183 best_step = 11
5563 11:07:59.826550
5564 11:07:59.826886 ==
5565 11:07:59.829118 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 11:07:59.835460 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5567 11:07:59.835999 ==
5568 11:07:59.836366 RX Vref Scan: 1
5569 11:07:59.836742
5570 11:07:59.838977 RX Vref 0 -> 0, step: 1
5571 11:07:59.839533
5572 11:07:59.842012 RX Delay -69 -> 252, step: 4
5573 11:07:59.842468
5574 11:07:59.845567 Set Vref, RX VrefLevel [Byte0]: 54
5575 11:07:59.848941 [Byte1]: 49
5576 11:07:59.849489
5577 11:07:59.852440 Final RX Vref Byte 0 = 54 to rank0
5578 11:07:59.855790 Final RX Vref Byte 1 = 49 to rank0
5579 11:07:59.858972 Final RX Vref Byte 0 = 54 to rank1
5580 11:07:59.862799 Final RX Vref Byte 1 = 49 to rank1==
5581 11:07:59.865420 Dram Type= 6, Freq= 0, CH_1, rank 0
5582 11:07:59.869203 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5583 11:07:59.869793 ==
5584 11:07:59.872201 DQS Delay:
5585 11:07:59.872789 DQS0 = 0, DQS1 = 0
5586 11:07:59.875426 DQM Delay:
5587 11:07:59.875982 DQM0 = 94, DQM1 = 88
5588 11:07:59.876353 DQ Delay:
5589 11:07:59.878989 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =92
5590 11:07:59.882595 DQ4 =92, DQ5 =104, DQ6 =102, DQ7 =92
5591 11:07:59.885979 DQ8 =72, DQ9 =78, DQ10 =90, DQ11 =80
5592 11:07:59.888639 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =98
5593 11:07:59.889140
5594 11:07:59.892110
5595 11:07:59.898347 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e2e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5596 11:07:59.901625 CH1 RK0: MR19=505, MR18=2E2E
5597 11:07:59.908228 CH1_RK0: MR19=0x505, MR18=0x2E2E, DQSOSC=407, MR23=63, INC=65, DEC=43
5598 11:07:59.908843
5599 11:07:59.911987 ----->DramcWriteLeveling(PI) begin...
5600 11:07:59.912508 ==
5601 11:07:59.915367 Dram Type= 6, Freq= 0, CH_1, rank 1
5602 11:07:59.918411 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5603 11:07:59.918965 ==
5604 11:07:59.921617 Write leveling (Byte 0): 27 => 27
5605 11:07:59.925181 Write leveling (Byte 1): 22 => 22
5606 11:07:59.928280 DramcWriteLeveling(PI) end<-----
5607 11:07:59.928874
5608 11:07:59.929246 ==
5609 11:07:59.931655 Dram Type= 6, Freq= 0, CH_1, rank 1
5610 11:07:59.934706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5611 11:07:59.935266 ==
5612 11:07:59.937926 [Gating] SW mode calibration
5613 11:07:59.944606 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5614 11:07:59.951942 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5615 11:07:59.954479 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 11:07:59.960856 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 11:07:59.964531 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 11:07:59.967765 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 11:07:59.974563 0 10 16 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
5620 11:07:59.977466 0 10 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (1 0)
5621 11:07:59.980883 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 11:07:59.984387 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 11:07:59.991175 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 11:07:59.994353 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 11:07:59.997708 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 11:08:00.005479 0 11 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5627 11:08:00.007719 0 11 16 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
5628 11:08:00.010877 0 11 20 | B1->B0 | 2f2f 4646 | 0 0 | (1 1) (0 0)
5629 11:08:00.017650 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 11:08:00.020693 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 11:08:00.024124 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 11:08:00.030614 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 11:08:00.033412 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 11:08:00.037363 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 11:08:00.043837 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5636 11:08:00.047219 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5637 11:08:00.050722 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 11:08:00.057413 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 11:08:00.060638 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 11:08:00.064071 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 11:08:00.070766 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 11:08:00.073843 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 11:08:00.076961 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 11:08:00.083481 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 11:08:00.087002 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 11:08:00.090384 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 11:08:00.097354 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 11:08:00.100583 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 11:08:00.103770 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 11:08:00.110201 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 11:08:00.114046 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5652 11:08:00.117161 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5653 11:08:00.120265 Total UI for P1: 0, mck2ui 16
5654 11:08:00.123649 best dqsien dly found for B0: ( 0, 14, 16)
5655 11:08:00.130448 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5656 11:08:00.133560 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 11:08:00.136880 Total UI for P1: 0, mck2ui 16
5658 11:08:00.139712 best dqsien dly found for B1: ( 0, 14, 20)
5659 11:08:00.143386 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5660 11:08:00.146271 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5661 11:08:00.146857
5662 11:08:00.149912 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5663 11:08:00.153736 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5664 11:08:00.157098 [Gating] SW calibration Done
5665 11:08:00.157655 ==
5666 11:08:00.159666 Dram Type= 6, Freq= 0, CH_1, rank 1
5667 11:08:00.163446 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5668 11:08:00.167053 ==
5669 11:08:00.167608 RX Vref Scan: 0
5670 11:08:00.167977
5671 11:08:00.170272 RX Vref 0 -> 0, step: 1
5672 11:08:00.170828
5673 11:08:00.172875 RX Delay -80 -> 252, step: 8
5674 11:08:00.176518 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5675 11:08:00.180160 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5676 11:08:00.182886 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5677 11:08:00.186102 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5678 11:08:00.189185 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5679 11:08:00.196284 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5680 11:08:00.199651 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5681 11:08:00.203295 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5682 11:08:00.206004 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5683 11:08:00.209110 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5684 11:08:00.216409 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5685 11:08:00.219456 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5686 11:08:00.222577 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5687 11:08:00.225934 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5688 11:08:00.229204 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5689 11:08:00.235955 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5690 11:08:00.236515 ==
5691 11:08:00.239090 Dram Type= 6, Freq= 0, CH_1, rank 1
5692 11:08:00.242309 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5693 11:08:00.242865 ==
5694 11:08:00.243231 DQS Delay:
5695 11:08:00.245473 DQS0 = 0, DQS1 = 0
5696 11:08:00.245926 DQM Delay:
5697 11:08:00.249114 DQM0 = 96, DQM1 = 85
5698 11:08:00.249664 DQ Delay:
5699 11:08:00.252170 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =91
5700 11:08:00.255574 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =91
5701 11:08:00.259109 DQ8 =75, DQ9 =75, DQ10 =83, DQ11 =75
5702 11:08:00.262767 DQ12 =91, DQ13 =95, DQ14 =91, DQ15 =95
5703 11:08:00.263330
5704 11:08:00.263697
5705 11:08:00.264031 ==
5706 11:08:00.265382 Dram Type= 6, Freq= 0, CH_1, rank 1
5707 11:08:00.268855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5708 11:08:00.272418 ==
5709 11:08:00.273022
5710 11:08:00.273387
5711 11:08:00.273719 TX Vref Scan disable
5712 11:08:00.275360 == TX Byte 0 ==
5713 11:08:00.278532 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5714 11:08:00.283287 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5715 11:08:00.285179 == TX Byte 1 ==
5716 11:08:00.288340 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5717 11:08:00.292395 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5718 11:08:00.295106 ==
5719 11:08:00.298184 Dram Type= 6, Freq= 0, CH_1, rank 1
5720 11:08:00.303142 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5721 11:08:00.303705 ==
5722 11:08:00.304073
5723 11:08:00.304461
5724 11:08:00.305318 TX Vref Scan disable
5725 11:08:00.305678 == TX Byte 0 ==
5726 11:08:00.311809 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5727 11:08:00.314840 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5728 11:08:00.315297 == TX Byte 1 ==
5729 11:08:00.322013 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5730 11:08:00.326276 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5731 11:08:00.326828
5732 11:08:00.327189 [DATLAT]
5733 11:08:00.327931 Freq=933, CH1 RK1
5734 11:08:00.328293
5735 11:08:00.328619 DATLAT Default: 0xb
5736 11:08:00.331914 0, 0xFFFF, sum = 0
5737 11:08:00.332473 1, 0xFFFF, sum = 0
5738 11:08:00.335037 2, 0xFFFF, sum = 0
5739 11:08:00.337662 3, 0xFFFF, sum = 0
5740 11:08:00.338126 4, 0xFFFF, sum = 0
5741 11:08:00.341902 5, 0xFFFF, sum = 0
5742 11:08:00.342468 6, 0xFFFF, sum = 0
5743 11:08:00.345395 7, 0xFFFF, sum = 0
5744 11:08:00.345852 8, 0xFFFF, sum = 0
5745 11:08:00.347942 9, 0xFFFF, sum = 0
5746 11:08:00.348402 10, 0x0, sum = 1
5747 11:08:00.351347 11, 0x0, sum = 2
5748 11:08:00.351919 12, 0x0, sum = 3
5749 11:08:00.355037 13, 0x0, sum = 4
5750 11:08:00.355625 best_step = 11
5751 11:08:00.355999
5752 11:08:00.356336 ==
5753 11:08:00.358179 Dram Type= 6, Freq= 0, CH_1, rank 1
5754 11:08:00.360881 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5755 11:08:00.361370 ==
5756 11:08:00.364601 RX Vref Scan: 0
5757 11:08:00.365139
5758 11:08:00.368150 RX Vref 0 -> 0, step: 1
5759 11:08:00.368702
5760 11:08:00.369126 RX Delay -69 -> 252, step: 4
5761 11:08:00.375532 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5762 11:08:00.378712 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5763 11:08:00.382459 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5764 11:08:00.385339 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5765 11:08:00.389166 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5766 11:08:00.392226 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5767 11:08:00.398386 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5768 11:08:00.401692 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5769 11:08:00.405364 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5770 11:08:00.408367 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5771 11:08:00.412328 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5772 11:08:00.418408 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5773 11:08:00.422041 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5774 11:08:00.424854 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5775 11:08:00.428625 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5776 11:08:00.431636 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5777 11:08:00.432189 ==
5778 11:08:00.435062 Dram Type= 6, Freq= 0, CH_1, rank 1
5779 11:08:00.441771 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5780 11:08:00.442321 ==
5781 11:08:00.442686 DQS Delay:
5782 11:08:00.445417 DQS0 = 0, DQS1 = 0
5783 11:08:00.445986 DQM Delay:
5784 11:08:00.448119 DQM0 = 96, DQM1 = 88
5785 11:08:00.448571 DQ Delay:
5786 11:08:00.451856 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =94
5787 11:08:00.455204 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5788 11:08:00.458417 DQ8 =74, DQ9 =78, DQ10 =88, DQ11 =80
5789 11:08:00.461687 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5790 11:08:00.462238
5791 11:08:00.462597
5792 11:08:00.468093 [DQSOSCAuto] RK1, (LSB)MR18= 0x2424, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5793 11:08:00.471710 CH1 RK1: MR19=505, MR18=2424
5794 11:08:00.478871 CH1_RK1: MR19=0x505, MR18=0x2424, DQSOSC=410, MR23=63, INC=64, DEC=42
5795 11:08:00.481819 [RxdqsGatingPostProcess] freq 933
5796 11:08:00.488080 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5797 11:08:00.488537 Pre-setting of DQS Precalculation
5798 11:08:00.494856 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5799 11:08:00.501836 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5800 11:08:00.507912 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5801 11:08:00.508474
5802 11:08:00.508899
5803 11:08:00.511606 [Calibration Summary] 1866 Mbps
5804 11:08:00.514399 CH 0, Rank 0
5805 11:08:00.514860 SW Impedance : PASS
5806 11:08:00.518683 DUTY Scan : NO K
5807 11:08:00.520821 ZQ Calibration : PASS
5808 11:08:00.521286 Jitter Meter : NO K
5809 11:08:00.524362 CBT Training : PASS
5810 11:08:00.528033 Write leveling : PASS
5811 11:08:00.528598 RX DQS gating : PASS
5812 11:08:00.530848 RX DQ/DQS(RDDQC) : PASS
5813 11:08:00.534031 TX DQ/DQS : PASS
5814 11:08:00.534589 RX DATLAT : PASS
5815 11:08:00.538357 RX DQ/DQS(Engine): PASS
5816 11:08:00.538912 TX OE : NO K
5817 11:08:00.541098 All Pass.
5818 11:08:00.541653
5819 11:08:00.542022 CH 0, Rank 1
5820 11:08:00.544372 SW Impedance : PASS
5821 11:08:00.544882 DUTY Scan : NO K
5822 11:08:00.547622 ZQ Calibration : PASS
5823 11:08:00.551144 Jitter Meter : NO K
5824 11:08:00.551609 CBT Training : PASS
5825 11:08:00.554498 Write leveling : PASS
5826 11:08:00.556977 RX DQS gating : PASS
5827 11:08:00.557436 RX DQ/DQS(RDDQC) : PASS
5828 11:08:00.560297 TX DQ/DQS : PASS
5829 11:08:00.564488 RX DATLAT : PASS
5830 11:08:00.565095 RX DQ/DQS(Engine): PASS
5831 11:08:00.567987 TX OE : NO K
5832 11:08:00.568544 All Pass.
5833 11:08:00.569052
5834 11:08:00.570305 CH 1, Rank 0
5835 11:08:00.570764 SW Impedance : PASS
5836 11:08:00.573508 DUTY Scan : NO K
5837 11:08:00.577893 ZQ Calibration : PASS
5838 11:08:00.578450 Jitter Meter : NO K
5839 11:08:00.581018 CBT Training : PASS
5840 11:08:00.584316 Write leveling : PASS
5841 11:08:00.584838 RX DQS gating : PASS
5842 11:08:00.587857 RX DQ/DQS(RDDQC) : PASS
5843 11:08:00.590735 TX DQ/DQS : PASS
5844 11:08:00.591294 RX DATLAT : PASS
5845 11:08:00.594115 RX DQ/DQS(Engine): PASS
5846 11:08:00.594673 TX OE : NO K
5847 11:08:00.596832 All Pass.
5848 11:08:00.597294
5849 11:08:00.597660 CH 1, Rank 1
5850 11:08:00.600055 SW Impedance : PASS
5851 11:08:00.600530 DUTY Scan : NO K
5852 11:08:00.603827 ZQ Calibration : PASS
5853 11:08:00.606722 Jitter Meter : NO K
5854 11:08:00.607196 CBT Training : PASS
5855 11:08:00.610425 Write leveling : PASS
5856 11:08:00.614918 RX DQS gating : PASS
5857 11:08:00.615472 RX DQ/DQS(RDDQC) : PASS
5858 11:08:00.617002 TX DQ/DQS : PASS
5859 11:08:00.620592 RX DATLAT : PASS
5860 11:08:00.621222 RX DQ/DQS(Engine): PASS
5861 11:08:00.623850 TX OE : NO K
5862 11:08:00.624408 All Pass.
5863 11:08:00.624835
5864 11:08:00.628194 DramC Write-DBI off
5865 11:08:00.631350 PER_BANK_REFRESH: Hybrid Mode
5866 11:08:00.631926 TX_TRACKING: ON
5867 11:08:00.640561 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5868 11:08:00.643883 [FAST_K] Save calibration result to emmc
5869 11:08:00.648097 dramc_set_vcore_voltage set vcore to 650000
5870 11:08:00.650544 Read voltage for 400, 6
5871 11:08:00.651123 Vio18 = 0
5872 11:08:00.651772 Vcore = 650000
5873 11:08:00.652998 Vdram = 0
5874 11:08:00.653458 Vddq = 0
5875 11:08:00.653822 Vmddr = 0
5876 11:08:00.659918 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5877 11:08:00.663502 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5878 11:08:00.666063 MEM_TYPE=3, freq_sel=20
5879 11:08:00.670334 sv_algorithm_assistance_LP4_800
5880 11:08:00.673256 ============ PULL DRAM RESETB DOWN ============
5881 11:08:00.676983 ========== PULL DRAM RESETB DOWN end =========
5882 11:08:00.683320 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5883 11:08:00.686204 ===================================
5884 11:08:00.689334 LPDDR4 DRAM CONFIGURATION
5885 11:08:00.693191 ===================================
5886 11:08:00.693748 EX_ROW_EN[0] = 0x0
5887 11:08:00.696554 EX_ROW_EN[1] = 0x0
5888 11:08:00.697158 LP4Y_EN = 0x0
5889 11:08:00.699338 WORK_FSP = 0x0
5890 11:08:00.699798 WL = 0x2
5891 11:08:00.702961 RL = 0x2
5892 11:08:00.703521 BL = 0x2
5893 11:08:00.707185 RPST = 0x0
5894 11:08:00.707796 RD_PRE = 0x0
5895 11:08:00.709351 WR_PRE = 0x1
5896 11:08:00.709963 WR_PST = 0x0
5897 11:08:00.712778 DBI_WR = 0x0
5898 11:08:00.713243 DBI_RD = 0x0
5899 11:08:00.716217 OTF = 0x1
5900 11:08:00.719972 ===================================
5901 11:08:00.723058 ===================================
5902 11:08:00.723620 ANA top config
5903 11:08:00.726099 ===================================
5904 11:08:00.729792 DLL_ASYNC_EN = 0
5905 11:08:00.732935 ALL_SLAVE_EN = 1
5906 11:08:00.737021 NEW_RANK_MODE = 1
5907 11:08:00.737657 DLL_IDLE_MODE = 1
5908 11:08:00.740428 LP45_APHY_COMB_EN = 1
5909 11:08:00.743264 TX_ODT_DIS = 1
5910 11:08:00.746377 NEW_8X_MODE = 1
5911 11:08:00.749328 ===================================
5912 11:08:00.752909 ===================================
5913 11:08:00.756425 data_rate = 800
5914 11:08:00.760070 CKR = 1
5915 11:08:00.760626 DQ_P2S_RATIO = 4
5916 11:08:00.763069 ===================================
5917 11:08:00.765701 CA_P2S_RATIO = 4
5918 11:08:00.769375 DQ_CA_OPEN = 0
5919 11:08:00.772749 DQ_SEMI_OPEN = 1
5920 11:08:00.775757 CA_SEMI_OPEN = 1
5921 11:08:00.779114 CA_FULL_RATE = 0
5922 11:08:00.779671 DQ_CKDIV4_EN = 0
5923 11:08:00.782364 CA_CKDIV4_EN = 1
5924 11:08:00.785760 CA_PREDIV_EN = 0
5925 11:08:00.788677 PH8_DLY = 0
5926 11:08:00.792425 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5927 11:08:00.795308 DQ_AAMCK_DIV = 0
5928 11:08:00.795864 CA_AAMCK_DIV = 0
5929 11:08:00.799550 CA_ADMCK_DIV = 4
5930 11:08:00.802552 DQ_TRACK_CA_EN = 0
5931 11:08:00.805343 CA_PICK = 800
5932 11:08:00.808759 CA_MCKIO = 400
5933 11:08:00.812027 MCKIO_SEMI = 400
5934 11:08:00.815324 PLL_FREQ = 3016
5935 11:08:00.818868 DQ_UI_PI_RATIO = 32
5936 11:08:00.819413 CA_UI_PI_RATIO = 32
5937 11:08:00.822262 ===================================
5938 11:08:00.825103 ===================================
5939 11:08:00.828840 memory_type:LPDDR4
5940 11:08:00.832819 GP_NUM : 10
5941 11:08:00.833364 SRAM_EN : 1
5942 11:08:00.835398 MD32_EN : 0
5943 11:08:00.838671 ===================================
5944 11:08:00.841802 [ANA_INIT] >>>>>>>>>>>>>>
5945 11:08:00.845248 <<<<<< [CONFIGURE PHASE]: ANA_TX
5946 11:08:00.848857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5947 11:08:00.851893 ===================================
5948 11:08:00.852462 data_rate = 800,PCW = 0X7400
5949 11:08:00.855043 ===================================
5950 11:08:00.858521 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5951 11:08:00.865424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5952 11:08:00.877928 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5953 11:08:00.881478 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5954 11:08:00.885343 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5955 11:08:00.887832 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5956 11:08:00.891493 [ANA_INIT] flow start
5957 11:08:00.892044 [ANA_INIT] PLL >>>>>>>>
5958 11:08:00.894647 [ANA_INIT] PLL <<<<<<<<
5959 11:08:00.897719 [ANA_INIT] MIDPI >>>>>>>>
5960 11:08:00.898183 [ANA_INIT] MIDPI <<<<<<<<
5961 11:08:00.901717 [ANA_INIT] DLL >>>>>>>>
5962 11:08:00.904597 [ANA_INIT] flow end
5963 11:08:00.908061 ============ LP4 DIFF to SE enter ============
5964 11:08:00.911607 ============ LP4 DIFF to SE exit ============
5965 11:08:00.914830 [ANA_INIT] <<<<<<<<<<<<<
5966 11:08:00.917736 [Flow] Enable top DCM control >>>>>
5967 11:08:00.921357 [Flow] Enable top DCM control <<<<<
5968 11:08:00.924499 Enable DLL master slave shuffle
5969 11:08:00.931297 ==============================================================
5970 11:08:00.931854 Gating Mode config
5971 11:08:00.937311 ==============================================================
5972 11:08:00.937866 Config description:
5973 11:08:00.947895 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5974 11:08:00.956071 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5975 11:08:00.960466 SELPH_MODE 0: By rank 1: By Phase
5976 11:08:00.963815 ==============================================================
5977 11:08:00.967508 GAT_TRACK_EN = 0
5978 11:08:00.970898 RX_GATING_MODE = 2
5979 11:08:00.973910 RX_GATING_TRACK_MODE = 2
5980 11:08:00.977342 SELPH_MODE = 1
5981 11:08:00.980332 PICG_EARLY_EN = 1
5982 11:08:00.983811 VALID_LAT_VALUE = 1
5983 11:08:00.990623 ==============================================================
5984 11:08:00.995548 Enter into Gating configuration >>>>
5985 11:08:00.996805 Exit from Gating configuration <<<<
5986 11:08:00.997272 Enter into DVFS_PRE_config >>>>>
5987 11:08:01.010204 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5988 11:08:01.013306 Exit from DVFS_PRE_config <<<<<
5989 11:08:01.016977 Enter into PICG configuration >>>>
5990 11:08:01.020661 Exit from PICG configuration <<<<
5991 11:08:01.021268 [RX_INPUT] configuration >>>>>
5992 11:08:01.024651 [RX_INPUT] configuration <<<<<
5993 11:08:01.029735 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5994 11:08:01.033955 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5995 11:08:01.039808 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5996 11:08:01.047437 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5997 11:08:01.053459 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5998 11:08:01.059994 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5999 11:08:01.064746 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6000 11:08:01.067374 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6001 11:08:01.073735 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6002 11:08:01.076849 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6003 11:08:01.079938 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6004 11:08:01.086509 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6005 11:08:01.087064 ===================================
6006 11:08:01.089298 LPDDR4 DRAM CONFIGURATION
6007 11:08:01.093096 ===================================
6008 11:08:01.096226 EX_ROW_EN[0] = 0x0
6009 11:08:01.096819 EX_ROW_EN[1] = 0x0
6010 11:08:01.099145 LP4Y_EN = 0x0
6011 11:08:01.099676 WORK_FSP = 0x0
6012 11:08:01.103334 WL = 0x2
6013 11:08:01.103884 RL = 0x2
6014 11:08:01.106198 BL = 0x2
6015 11:08:01.109840 RPST = 0x0
6016 11:08:01.110299 RD_PRE = 0x0
6017 11:08:01.112498 WR_PRE = 0x1
6018 11:08:01.112993 WR_PST = 0x0
6019 11:08:01.116066 DBI_WR = 0x0
6020 11:08:01.116638 DBI_RD = 0x0
6021 11:08:01.119294 OTF = 0x1
6022 11:08:01.122316 ===================================
6023 11:08:01.125542 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6024 11:08:01.129346 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6025 11:08:01.132822 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6026 11:08:01.135926 ===================================
6027 11:08:01.139472 LPDDR4 DRAM CONFIGURATION
6028 11:08:01.142833 ===================================
6029 11:08:01.145759 EX_ROW_EN[0] = 0x10
6030 11:08:01.146313 EX_ROW_EN[1] = 0x0
6031 11:08:01.148907 LP4Y_EN = 0x0
6032 11:08:01.149458 WORK_FSP = 0x0
6033 11:08:01.152911 WL = 0x2
6034 11:08:01.153465 RL = 0x2
6035 11:08:01.155909 BL = 0x2
6036 11:08:01.159568 RPST = 0x0
6037 11:08:01.160121 RD_PRE = 0x0
6038 11:08:01.162968 WR_PRE = 0x1
6039 11:08:01.163517 WR_PST = 0x0
6040 11:08:01.166168 DBI_WR = 0x0
6041 11:08:01.166720 DBI_RD = 0x0
6042 11:08:01.168914 OTF = 0x1
6043 11:08:01.172472 ===================================
6044 11:08:01.176152 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6045 11:08:01.181559 nWR fixed to 30
6046 11:08:01.184560 [ModeRegInit_LP4] CH0 RK0
6047 11:08:01.185204 [ModeRegInit_LP4] CH0 RK1
6048 11:08:01.187287 [ModeRegInit_LP4] CH1 RK0
6049 11:08:01.190822 [ModeRegInit_LP4] CH1 RK1
6050 11:08:01.191275 match AC timing 18
6051 11:08:01.197290 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6052 11:08:01.200807 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6053 11:08:01.204127 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6054 11:08:01.210701 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6055 11:08:01.214657 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6056 11:08:01.215216 ==
6057 11:08:01.217275 Dram Type= 6, Freq= 0, CH_0, rank 0
6058 11:08:01.221507 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6059 11:08:01.222060 ==
6060 11:08:01.227725 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6061 11:08:01.234308 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6062 11:08:01.237619 [CA 0] Center 36 (8~64) winsize 57
6063 11:08:01.240144 [CA 1] Center 36 (8~64) winsize 57
6064 11:08:01.244334 [CA 2] Center 36 (8~64) winsize 57
6065 11:08:01.246944 [CA 3] Center 36 (8~64) winsize 57
6066 11:08:01.250603 [CA 4] Center 36 (8~64) winsize 57
6067 11:08:01.251057 [CA 5] Center 36 (8~64) winsize 57
6068 11:08:01.253590
6069 11:08:01.257591 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6070 11:08:01.258192
6071 11:08:01.260992 [CATrainingPosCal] consider 1 rank data
6072 11:08:01.264473 u2DelayCellTimex100 = 270/100 ps
6073 11:08:01.267387 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6074 11:08:01.270345 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6075 11:08:01.273893 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6076 11:08:01.276952 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6077 11:08:01.280400 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6078 11:08:01.284102 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6079 11:08:01.284681
6080 11:08:01.287714 CA PerBit enable=1, Macro0, CA PI delay=36
6081 11:08:01.288269
6082 11:08:01.289728 [CBTSetCACLKResult] CA Dly = 36
6083 11:08:01.293209 CS Dly: 1 (0~32)
6084 11:08:01.293661 ==
6085 11:08:01.296660 Dram Type= 6, Freq= 0, CH_0, rank 1
6086 11:08:01.299921 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6087 11:08:01.300438 ==
6088 11:08:01.306529 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6089 11:08:01.313191 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6090 11:08:01.316376 [CA 0] Center 36 (8~64) winsize 57
6091 11:08:01.320172 [CA 1] Center 36 (8~64) winsize 57
6092 11:08:01.320784 [CA 2] Center 36 (8~64) winsize 57
6093 11:08:01.323905 [CA 3] Center 36 (8~64) winsize 57
6094 11:08:01.326700 [CA 4] Center 36 (8~64) winsize 57
6095 11:08:01.329411 [CA 5] Center 36 (8~64) winsize 57
6096 11:08:01.329919
6097 11:08:01.333012 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6098 11:08:01.336452
6099 11:08:01.339329 [CATrainingPosCal] consider 2 rank data
6100 11:08:01.339894 u2DelayCellTimex100 = 270/100 ps
6101 11:08:01.347242 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6102 11:08:01.349597 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6103 11:08:01.352935 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6104 11:08:01.356083 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6105 11:08:01.359138 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6106 11:08:01.364040 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6107 11:08:01.364593
6108 11:08:01.365773 CA PerBit enable=1, Macro0, CA PI delay=36
6109 11:08:01.366224
6110 11:08:01.369639 [CBTSetCACLKResult] CA Dly = 36
6111 11:08:01.372164 CS Dly: 1 (0~32)
6112 11:08:01.372749
6113 11:08:01.375995 ----->DramcWriteLeveling(PI) begin...
6114 11:08:01.376576 ==
6115 11:08:01.379299 Dram Type= 6, Freq= 0, CH_0, rank 0
6116 11:08:01.382352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6117 11:08:01.382907 ==
6118 11:08:01.385673 Write leveling (Byte 0): 32 => 0
6119 11:08:01.389006 Write leveling (Byte 1): 32 => 0
6120 11:08:01.392914 DramcWriteLeveling(PI) end<-----
6121 11:08:01.393383
6122 11:08:01.393751 ==
6123 11:08:01.395817 Dram Type= 6, Freq= 0, CH_0, rank 0
6124 11:08:01.399466 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6125 11:08:01.400089 ==
6126 11:08:01.402048 [Gating] SW mode calibration
6127 11:08:01.408992 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6128 11:08:01.415598 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6129 11:08:01.419045 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6130 11:08:01.422402 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6131 11:08:01.429186 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6132 11:08:01.432845 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6133 11:08:01.435582 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6134 11:08:01.442463 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6135 11:08:01.445225 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6136 11:08:01.448910 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6137 11:08:01.455218 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6138 11:08:01.458764 Total UI for P1: 0, mck2ui 16
6139 11:08:01.462054 best dqsien dly found for B0: ( 0, 10, 16)
6140 11:08:01.462524 Total UI for P1: 0, mck2ui 16
6141 11:08:01.468592 best dqsien dly found for B1: ( 0, 10, 24)
6142 11:08:01.472192 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6143 11:08:01.475503 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6144 11:08:01.476061
6145 11:08:01.478765 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6146 11:08:01.481224 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6147 11:08:01.484689 [Gating] SW calibration Done
6148 11:08:01.485195 ==
6149 11:08:01.488613 Dram Type= 6, Freq= 0, CH_0, rank 0
6150 11:08:01.491484 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6151 11:08:01.491944 ==
6152 11:08:01.496607 RX Vref Scan: 0
6153 11:08:01.497162
6154 11:08:01.498375 RX Vref 0 -> 0, step: 1
6155 11:08:01.498816
6156 11:08:01.499168 RX Delay -410 -> 252, step: 16
6157 11:08:01.504871 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6158 11:08:01.508599 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6159 11:08:01.511270 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6160 11:08:01.517644 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6161 11:08:01.521434 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6162 11:08:01.524545 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6163 11:08:01.528031 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6164 11:08:01.534652 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6165 11:08:01.537658 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6166 11:08:01.541944 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6167 11:08:01.544925 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6168 11:08:01.550994 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6169 11:08:01.554360 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6170 11:08:01.557497 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6171 11:08:01.561064 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6172 11:08:01.568064 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6173 11:08:01.568579 ==
6174 11:08:01.571263 Dram Type= 6, Freq= 0, CH_0, rank 0
6175 11:08:01.574190 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6176 11:08:01.574727 ==
6177 11:08:01.575073 DQS Delay:
6178 11:08:01.578190 DQS0 = 51, DQS1 = 59
6179 11:08:01.578695 DQM Delay:
6180 11:08:01.581120 DQM0 = 12, DQM1 = 13
6181 11:08:01.581630 DQ Delay:
6182 11:08:01.584779 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6183 11:08:01.587622 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6184 11:08:01.590840 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6185 11:08:01.594160 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6186 11:08:01.594576
6187 11:08:01.594907
6188 11:08:01.595210 ==
6189 11:08:01.597026 Dram Type= 6, Freq= 0, CH_0, rank 0
6190 11:08:01.601028 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6191 11:08:01.601449 ==
6192 11:08:01.601783
6193 11:08:01.602089
6194 11:08:01.604660 TX Vref Scan disable
6195 11:08:01.607811 == TX Byte 0 ==
6196 11:08:01.610831 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6197 11:08:01.613855 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6198 11:08:01.616828 == TX Byte 1 ==
6199 11:08:01.620771 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6200 11:08:01.623639 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6201 11:08:01.624103 ==
6202 11:08:01.627012 Dram Type= 6, Freq= 0, CH_0, rank 0
6203 11:08:01.630237 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6204 11:08:01.634082 ==
6205 11:08:01.634594
6206 11:08:01.634929
6207 11:08:01.635239 TX Vref Scan disable
6208 11:08:01.637296 == TX Byte 0 ==
6209 11:08:01.641412 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6210 11:08:01.643999 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6211 11:08:01.647447 == TX Byte 1 ==
6212 11:08:01.650203 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6213 11:08:01.653805 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6214 11:08:01.654324
6215 11:08:01.657437 [DATLAT]
6216 11:08:01.657954 Freq=400, CH0 RK0
6217 11:08:01.658330
6218 11:08:01.660473 DATLAT Default: 0xf
6219 11:08:01.661133 0, 0xFFFF, sum = 0
6220 11:08:01.663690 1, 0xFFFF, sum = 0
6221 11:08:01.664213 2, 0xFFFF, sum = 0
6222 11:08:01.667277 3, 0xFFFF, sum = 0
6223 11:08:01.667795 4, 0xFFFF, sum = 0
6224 11:08:01.670361 5, 0xFFFF, sum = 0
6225 11:08:01.670882 6, 0xFFFF, sum = 0
6226 11:08:01.673871 7, 0xFFFF, sum = 0
6227 11:08:01.674388 8, 0xFFFF, sum = 0
6228 11:08:01.677322 9, 0xFFFF, sum = 0
6229 11:08:01.677863 10, 0xFFFF, sum = 0
6230 11:08:01.680078 11, 0xFFFF, sum = 0
6231 11:08:01.680640 12, 0x0, sum = 1
6232 11:08:01.683696 13, 0x0, sum = 2
6233 11:08:01.684253 14, 0x0, sum = 3
6234 11:08:01.687320 15, 0x0, sum = 4
6235 11:08:01.687880 best_step = 13
6236 11:08:01.688247
6237 11:08:01.688580 ==
6238 11:08:01.690451 Dram Type= 6, Freq= 0, CH_0, rank 0
6239 11:08:01.696936 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6240 11:08:01.697507 ==
6241 11:08:01.697875 RX Vref Scan: 1
6242 11:08:01.698208
6243 11:08:01.699907 RX Vref 0 -> 0, step: 1
6244 11:08:01.700360
6245 11:08:01.703013 RX Delay -359 -> 252, step: 8
6246 11:08:01.703463
6247 11:08:01.707336 Set Vref, RX VrefLevel [Byte0]: 53
6248 11:08:01.710111 [Byte1]: 48
6249 11:08:01.713253
6250 11:08:01.713708 Final RX Vref Byte 0 = 53 to rank0
6251 11:08:01.717448 Final RX Vref Byte 1 = 48 to rank0
6252 11:08:01.720101 Final RX Vref Byte 0 = 53 to rank1
6253 11:08:01.724869 Final RX Vref Byte 1 = 48 to rank1==
6254 11:08:01.726994 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 11:08:01.733590 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6256 11:08:01.734379 ==
6257 11:08:01.734827 DQS Delay:
6258 11:08:01.736364 DQS0 = 52, DQS1 = 68
6259 11:08:01.736860 DQM Delay:
6260 11:08:01.737233 DQM0 = 9, DQM1 = 16
6261 11:08:01.740361 DQ Delay:
6262 11:08:01.743413 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6263 11:08:01.743868 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =20
6264 11:08:01.746383 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6265 11:08:01.749567 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6266 11:08:01.750029
6267 11:08:01.753461
6268 11:08:01.759862 [DQSOSCAuto] RK0, (LSB)MR18= 0xa9a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6269 11:08:01.763065 CH0 RK0: MR19=C0C, MR18=A9A9
6270 11:08:01.769404 CH0_RK0: MR19=0xC0C, MR18=0xA9A9, DQSOSC=388, MR23=63, INC=392, DEC=261
6271 11:08:01.769958 ==
6272 11:08:01.773210 Dram Type= 6, Freq= 0, CH_0, rank 1
6273 11:08:01.778354 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6274 11:08:01.778921 ==
6275 11:08:01.780283 [Gating] SW mode calibration
6276 11:08:01.786550 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6277 11:08:01.793397 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6278 11:08:01.796395 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6279 11:08:01.799756 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6280 11:08:01.806776 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 11:08:01.809926 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6282 11:08:01.813129 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 11:08:01.819243 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 11:08:01.822437 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 11:08:01.825665 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6286 11:08:01.832287 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 11:08:01.832883 Total UI for P1: 0, mck2ui 16
6288 11:08:01.839119 best dqsien dly found for B0: ( 0, 10, 16)
6289 11:08:01.839685 Total UI for P1: 0, mck2ui 16
6290 11:08:01.842295 best dqsien dly found for B1: ( 0, 10, 24)
6291 11:08:01.849082 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6292 11:08:01.851800 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6293 11:08:01.852258
6294 11:08:01.855692 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6295 11:08:01.859013 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6296 11:08:01.862176 [Gating] SW calibration Done
6297 11:08:01.862652 ==
6298 11:08:01.865124 Dram Type= 6, Freq= 0, CH_0, rank 1
6299 11:08:01.868977 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6300 11:08:01.869766 ==
6301 11:08:01.872396 RX Vref Scan: 0
6302 11:08:01.872884
6303 11:08:01.873255 RX Vref 0 -> 0, step: 1
6304 11:08:01.873600
6305 11:08:01.875719 RX Delay -410 -> 252, step: 16
6306 11:08:01.881547 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6307 11:08:01.885109 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6308 11:08:01.889090 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6309 11:08:01.892100 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6310 11:08:01.898826 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6311 11:08:01.901784 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6312 11:08:01.904821 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6313 11:08:01.909048 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6314 11:08:01.915008 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6315 11:08:01.918645 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6316 11:08:01.921351 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6317 11:08:01.924985 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6318 11:08:01.931948 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6319 11:08:01.935876 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6320 11:08:01.939848 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6321 11:08:01.945020 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6322 11:08:01.945593 ==
6323 11:08:01.948490 Dram Type= 6, Freq= 0, CH_0, rank 1
6324 11:08:01.951034 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6325 11:08:01.951716 ==
6326 11:08:01.952193 DQS Delay:
6327 11:08:01.954741 DQS0 = 43, DQS1 = 59
6328 11:08:01.955231 DQM Delay:
6329 11:08:01.957999 DQM0 = 6, DQM1 = 15
6330 11:08:01.958615 DQ Delay:
6331 11:08:01.961030 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6332 11:08:01.964979 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6333 11:08:01.968077 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6334 11:08:01.971025 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6335 11:08:01.971495
6336 11:08:01.971991
6337 11:08:01.972438 ==
6338 11:08:01.974297 Dram Type= 6, Freq= 0, CH_0, rank 1
6339 11:08:01.977675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6340 11:08:01.978187 ==
6341 11:08:01.978659
6342 11:08:01.979104
6343 11:08:01.981591 TX Vref Scan disable
6344 11:08:01.982205 == TX Byte 0 ==
6345 11:08:01.988911 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6346 11:08:01.991380 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6347 11:08:01.991866 == TX Byte 1 ==
6348 11:08:01.998151 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6349 11:08:02.000894 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6350 11:08:02.001458 ==
6351 11:08:02.004579 Dram Type= 6, Freq= 0, CH_0, rank 1
6352 11:08:02.007665 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6353 11:08:02.008232 ==
6354 11:08:02.008838
6355 11:08:02.009293
6356 11:08:02.011196 TX Vref Scan disable
6357 11:08:02.011662 == TX Byte 0 ==
6358 11:08:02.017292 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6359 11:08:02.021023 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6360 11:08:02.021648 == TX Byte 1 ==
6361 11:08:02.027057 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6362 11:08:02.030547 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6363 11:08:02.031059
6364 11:08:02.031515 [DATLAT]
6365 11:08:02.033572 Freq=400, CH0 RK1
6366 11:08:02.033926
6367 11:08:02.034245 DATLAT Default: 0xd
6368 11:08:02.036840 0, 0xFFFF, sum = 0
6369 11:08:02.037203 1, 0xFFFF, sum = 0
6370 11:08:02.041577 2, 0xFFFF, sum = 0
6371 11:08:02.041812 3, 0xFFFF, sum = 0
6372 11:08:02.043595 4, 0xFFFF, sum = 0
6373 11:08:02.043855 5, 0xFFFF, sum = 0
6374 11:08:02.047613 6, 0xFFFF, sum = 0
6375 11:08:02.047872 7, 0xFFFF, sum = 0
6376 11:08:02.050519 8, 0xFFFF, sum = 0
6377 11:08:02.053382 9, 0xFFFF, sum = 0
6378 11:08:02.053615 10, 0xFFFF, sum = 0
6379 11:08:02.057250 11, 0xFFFF, sum = 0
6380 11:08:02.057485 12, 0x0, sum = 1
6381 11:08:02.060593 13, 0x0, sum = 2
6382 11:08:02.060852 14, 0x0, sum = 3
6383 11:08:02.060984 15, 0x0, sum = 4
6384 11:08:02.063649 best_step = 13
6385 11:08:02.063916
6386 11:08:02.064059 ==
6387 11:08:02.066813 Dram Type= 6, Freq= 0, CH_0, rank 1
6388 11:08:02.070104 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6389 11:08:02.070354 ==
6390 11:08:02.073656 RX Vref Scan: 0
6391 11:08:02.073887
6392 11:08:02.076535 RX Vref 0 -> 0, step: 1
6393 11:08:02.076739
6394 11:08:02.076876 RX Delay -359 -> 252, step: 8
6395 11:08:02.085286 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6396 11:08:02.088963 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6397 11:08:02.092260 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6398 11:08:02.098972 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6399 11:08:02.101764 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6400 11:08:02.105261 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6401 11:08:02.109314 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6402 11:08:02.116353 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6403 11:08:02.118706 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6404 11:08:02.122811 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6405 11:08:02.126083 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6406 11:08:02.132003 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6407 11:08:02.134893 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6408 11:08:02.138900 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6409 11:08:02.142213 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6410 11:08:02.148135 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6411 11:08:02.148681 ==
6412 11:08:02.151364 Dram Type= 6, Freq= 0, CH_0, rank 1
6413 11:08:02.155284 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6414 11:08:02.155834 ==
6415 11:08:02.158421 DQS Delay:
6416 11:08:02.158973 DQS0 = 52, DQS1 = 64
6417 11:08:02.159331 DQM Delay:
6418 11:08:02.161443 DQM0 = 10, DQM1 = 13
6419 11:08:02.161892 DQ Delay:
6420 11:08:02.164847 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6421 11:08:02.168570 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6422 11:08:02.171500 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6423 11:08:02.174685 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6424 11:08:02.175239
6425 11:08:02.175600
6426 11:08:02.185194 [DQSOSCAuto] RK1, (LSB)MR18= 0xb9b9, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6427 11:08:02.185815 CH0 RK1: MR19=C0C, MR18=B9B9
6428 11:08:02.191356 CH0_RK1: MR19=0xC0C, MR18=0xB9B9, DQSOSC=386, MR23=63, INC=396, DEC=264
6429 11:08:02.195178 [RxdqsGatingPostProcess] freq 400
6430 11:08:02.200696 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6431 11:08:02.205623 Pre-setting of DQS Precalculation
6432 11:08:02.207646 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6433 11:08:02.208204 ==
6434 11:08:02.211294 Dram Type= 6, Freq= 0, CH_1, rank 0
6435 11:08:02.217692 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6436 11:08:02.218190 ==
6437 11:08:02.220805 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6438 11:08:02.228263 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6439 11:08:02.231689 [CA 0] Center 36 (8~64) winsize 57
6440 11:08:02.236011 [CA 1] Center 36 (8~64) winsize 57
6441 11:08:02.237175 [CA 2] Center 36 (8~64) winsize 57
6442 11:08:02.241345 [CA 3] Center 36 (8~64) winsize 57
6443 11:08:02.245026 [CA 4] Center 36 (8~64) winsize 57
6444 11:08:02.247864 [CA 5] Center 36 (8~64) winsize 57
6445 11:08:02.248413
6446 11:08:02.251208 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6447 11:08:02.251752
6448 11:08:02.254033 [CATrainingPosCal] consider 1 rank data
6449 11:08:02.257320 u2DelayCellTimex100 = 270/100 ps
6450 11:08:02.260814 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6451 11:08:02.263819 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6452 11:08:02.267565 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6453 11:08:02.271059 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6454 11:08:02.274221 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6455 11:08:02.277243 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6456 11:08:02.277968
6457 11:08:02.284536 CA PerBit enable=1, Macro0, CA PI delay=36
6458 11:08:02.285265
6459 11:08:02.285642 [CBTSetCACLKResult] CA Dly = 36
6460 11:08:02.288067 CS Dly: 1 (0~32)
6461 11:08:02.288624 ==
6462 11:08:02.290531 Dram Type= 6, Freq= 0, CH_1, rank 1
6463 11:08:02.293405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6464 11:08:02.294106 ==
6465 11:08:02.300570 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6466 11:08:02.306906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6467 11:08:02.310413 [CA 0] Center 36 (8~64) winsize 57
6468 11:08:02.313348 [CA 1] Center 36 (8~64) winsize 57
6469 11:08:02.318093 [CA 2] Center 36 (8~64) winsize 57
6470 11:08:02.320526 [CA 3] Center 36 (8~64) winsize 57
6471 11:08:02.324345 [CA 4] Center 36 (8~64) winsize 57
6472 11:08:02.324944 [CA 5] Center 36 (8~64) winsize 57
6473 11:08:02.327213
6474 11:08:02.330365 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6475 11:08:02.330925
6476 11:08:02.333300 [CATrainingPosCal] consider 2 rank data
6477 11:08:02.337120 u2DelayCellTimex100 = 270/100 ps
6478 11:08:02.340401 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6479 11:08:02.343870 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6480 11:08:02.347186 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6481 11:08:02.349972 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6482 11:08:02.353112 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6483 11:08:02.357078 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6484 11:08:02.357640
6485 11:08:02.359630 CA PerBit enable=1, Macro0, CA PI delay=36
6486 11:08:02.360197
6487 11:08:02.363735 [CBTSetCACLKResult] CA Dly = 36
6488 11:08:02.366555 CS Dly: 1 (0~32)
6489 11:08:02.367014
6490 11:08:02.370131 ----->DramcWriteLeveling(PI) begin...
6491 11:08:02.370774 ==
6492 11:08:02.373226 Dram Type= 6, Freq= 0, CH_1, rank 0
6493 11:08:02.376576 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6494 11:08:02.377192 ==
6495 11:08:02.380806 Write leveling (Byte 0): 32 => 0
6496 11:08:02.383902 Write leveling (Byte 1): 32 => 0
6497 11:08:02.386419 DramcWriteLeveling(PI) end<-----
6498 11:08:02.386878
6499 11:08:02.387242 ==
6500 11:08:02.389501 Dram Type= 6, Freq= 0, CH_1, rank 0
6501 11:08:02.392593 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6502 11:08:02.393097 ==
6503 11:08:02.395781 [Gating] SW mode calibration
6504 11:08:02.402672 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6505 11:08:02.409608 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6506 11:08:02.412567 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6507 11:08:02.419488 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6508 11:08:02.423390 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6509 11:08:02.425622 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6510 11:08:02.432847 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6511 11:08:02.436187 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6512 11:08:02.439264 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6513 11:08:02.446684 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6514 11:08:02.450826 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6515 11:08:02.454998 Total UI for P1: 0, mck2ui 16
6516 11:08:02.455928 best dqsien dly found for B0: ( 0, 10, 16)
6517 11:08:02.459230 Total UI for P1: 0, mck2ui 16
6518 11:08:02.462489 best dqsien dly found for B1: ( 0, 10, 16)
6519 11:08:02.465530 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6520 11:08:02.468788 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6521 11:08:02.469256
6522 11:08:02.472327 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6523 11:08:02.475732 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6524 11:08:02.478920 [Gating] SW calibration Done
6525 11:08:02.479487 ==
6526 11:08:02.481840 Dram Type= 6, Freq= 0, CH_1, rank 0
6527 11:08:02.485280 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6528 11:08:02.488510 ==
6529 11:08:02.489117 RX Vref Scan: 0
6530 11:08:02.489492
6531 11:08:02.491968 RX Vref 0 -> 0, step: 1
6532 11:08:02.492430
6533 11:08:02.495173 RX Delay -410 -> 252, step: 16
6534 11:08:02.499045 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6535 11:08:02.502639 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6536 11:08:02.504827 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6537 11:08:02.511940 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6538 11:08:02.515192 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6539 11:08:02.518400 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6540 11:08:02.521356 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6541 11:08:02.528293 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6542 11:08:02.531756 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6543 11:08:02.534592 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6544 11:08:02.538316 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6545 11:08:02.544843 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6546 11:08:02.548378 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6547 11:08:02.551128 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6548 11:08:02.558238 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6549 11:08:02.563751 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6550 11:08:02.564315 ==
6551 11:08:02.565056 Dram Type= 6, Freq= 0, CH_1, rank 0
6552 11:08:02.569042 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6553 11:08:02.569505 ==
6554 11:08:02.571431 DQS Delay:
6555 11:08:02.571890 DQS0 = 43, DQS1 = 59
6556 11:08:02.572256 DQM Delay:
6557 11:08:02.574686 DQM0 = 10, DQM1 = 16
6558 11:08:02.575242 DQ Delay:
6559 11:08:02.577632 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6560 11:08:02.580991 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6561 11:08:02.584283 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6562 11:08:02.587457 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6563 11:08:02.587874
6564 11:08:02.588206
6565 11:08:02.588514 ==
6566 11:08:02.591027 Dram Type= 6, Freq= 0, CH_1, rank 0
6567 11:08:02.597488 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6568 11:08:02.597987 ==
6569 11:08:02.598323
6570 11:08:02.598632
6571 11:08:02.598928 TX Vref Scan disable
6572 11:08:02.601292 == TX Byte 0 ==
6573 11:08:02.604351 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6574 11:08:02.608051 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6575 11:08:02.610716 == TX Byte 1 ==
6576 11:08:02.613987 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6577 11:08:02.617840 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6578 11:08:02.620776 ==
6579 11:08:02.621306 Dram Type= 6, Freq= 0, CH_1, rank 0
6580 11:08:02.627403 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6581 11:08:02.627967 ==
6582 11:08:02.628340
6583 11:08:02.628679
6584 11:08:02.630907 TX Vref Scan disable
6585 11:08:02.631468 == TX Byte 0 ==
6586 11:08:02.634403 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6587 11:08:02.641114 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6588 11:08:02.641677 == TX Byte 1 ==
6589 11:08:02.644307 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6590 11:08:02.651236 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6591 11:08:02.651799
6592 11:08:02.652169 [DATLAT]
6593 11:08:02.652692 Freq=400, CH1 RK0
6594 11:08:02.653352
6595 11:08:02.654067 DATLAT Default: 0xf
6596 11:08:02.654431 0, 0xFFFF, sum = 0
6597 11:08:02.658016 1, 0xFFFF, sum = 0
6598 11:08:02.660603 2, 0xFFFF, sum = 0
6599 11:08:02.661227 3, 0xFFFF, sum = 0
6600 11:08:02.663931 4, 0xFFFF, sum = 0
6601 11:08:02.664532 5, 0xFFFF, sum = 0
6602 11:08:02.667279 6, 0xFFFF, sum = 0
6603 11:08:02.667747 7, 0xFFFF, sum = 0
6604 11:08:02.670559 8, 0xFFFF, sum = 0
6605 11:08:02.671133 9, 0xFFFF, sum = 0
6606 11:08:02.674659 10, 0xFFFF, sum = 0
6607 11:08:02.675233 11, 0xFFFF, sum = 0
6608 11:08:02.678255 12, 0x0, sum = 1
6609 11:08:02.678841 13, 0x0, sum = 2
6610 11:08:02.681904 14, 0x0, sum = 3
6611 11:08:02.682497 15, 0x0, sum = 4
6612 11:08:02.684027 best_step = 13
6613 11:08:02.684484
6614 11:08:02.684882 ==
6615 11:08:02.687983 Dram Type= 6, Freq= 0, CH_1, rank 0
6616 11:08:02.690856 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6617 11:08:02.691420 ==
6618 11:08:02.691789 RX Vref Scan: 1
6619 11:08:02.694012
6620 11:08:02.694570 RX Vref 0 -> 0, step: 1
6621 11:08:02.694945
6622 11:08:02.697311 RX Delay -359 -> 252, step: 8
6623 11:08:02.697792
6624 11:08:02.700292 Set Vref, RX VrefLevel [Byte0]: 54
6625 11:08:02.703424 [Byte1]: 49
6626 11:08:02.708101
6627 11:08:02.708655 Final RX Vref Byte 0 = 54 to rank0
6628 11:08:02.711145 Final RX Vref Byte 1 = 49 to rank0
6629 11:08:02.714206 Final RX Vref Byte 0 = 54 to rank1
6630 11:08:02.717607 Final RX Vref Byte 1 = 49 to rank1==
6631 11:08:02.721069 Dram Type= 6, Freq= 0, CH_1, rank 0
6632 11:08:02.727792 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6633 11:08:02.728346 ==
6634 11:08:02.728763 DQS Delay:
6635 11:08:02.729132 DQS0 = 48, DQS1 = 64
6636 11:08:02.731053 DQM Delay:
6637 11:08:02.731608 DQM0 = 7, DQM1 = 16
6638 11:08:02.734539 DQ Delay:
6639 11:08:02.735120 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6640 11:08:02.737874 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6641 11:08:02.741432 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6642 11:08:02.744835 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6643 11:08:02.745386
6644 11:08:02.745756
6645 11:08:02.754924 [DQSOSCAuto] RK0, (LSB)MR18= 0xd5d5, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6646 11:08:02.757412 CH1 RK0: MR19=C0C, MR18=D5D5
6647 11:08:02.764344 CH1_RK0: MR19=0xC0C, MR18=0xD5D5, DQSOSC=383, MR23=63, INC=402, DEC=268
6648 11:08:02.764947 ==
6649 11:08:02.767363 Dram Type= 6, Freq= 0, CH_1, rank 1
6650 11:08:02.770769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6651 11:08:02.771326 ==
6652 11:08:02.774409 [Gating] SW mode calibration
6653 11:08:02.780816 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6654 11:08:02.783832 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6655 11:08:02.791783 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 11:08:02.794246 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6657 11:08:02.798679 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 11:08:02.804352 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6659 11:08:02.807169 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 11:08:02.810581 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 11:08:02.816901 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 11:08:02.820565 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6663 11:08:02.823707 Total UI for P1: 0, mck2ui 16
6664 11:08:02.827196 best dqsien dly found for B0: ( 0, 10, 8)
6665 11:08:02.829748 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 11:08:02.833387 Total UI for P1: 0, mck2ui 16
6667 11:08:02.837143 best dqsien dly found for B1: ( 0, 10, 16)
6668 11:08:02.843650 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6669 11:08:02.847059 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6670 11:08:02.847621
6671 11:08:02.850058 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6672 11:08:02.853763 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6673 11:08:02.856442 [Gating] SW calibration Done
6674 11:08:02.857040 ==
6675 11:08:02.860379 Dram Type= 6, Freq= 0, CH_1, rank 1
6676 11:08:02.863847 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6677 11:08:02.864428 ==
6678 11:08:02.866492 RX Vref Scan: 0
6679 11:08:02.866951
6680 11:08:02.867319 RX Vref 0 -> 0, step: 1
6681 11:08:02.867661
6682 11:08:02.869279 RX Delay -410 -> 252, step: 16
6683 11:08:02.876929 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6684 11:08:02.879523 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6685 11:08:02.882918 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6686 11:08:02.886132 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6687 11:08:02.893375 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6688 11:08:02.896530 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6689 11:08:02.899304 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6690 11:08:02.902488 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6691 11:08:02.909499 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6692 11:08:02.912241 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6693 11:08:02.917029 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6694 11:08:02.919401 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6695 11:08:02.926047 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6696 11:08:02.929433 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6697 11:08:02.933135 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6698 11:08:02.935992 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6699 11:08:02.939599 ==
6700 11:08:02.942307 Dram Type= 6, Freq= 0, CH_1, rank 1
6701 11:08:02.945959 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6702 11:08:02.946516 ==
6703 11:08:02.946885 DQS Delay:
6704 11:08:02.949068 DQS0 = 35, DQS1 = 59
6705 11:08:02.949608 DQM Delay:
6706 11:08:02.952512 DQM0 = 2, DQM1 = 18
6707 11:08:02.953125 DQ Delay:
6708 11:08:02.955751 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6709 11:08:02.959089 DQ4 =0, DQ5 =8, DQ6 =8, DQ7 =0
6710 11:08:02.962678 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6711 11:08:02.965163 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6712 11:08:02.965627
6713 11:08:02.965990
6714 11:08:02.966331 ==
6715 11:08:02.969112 Dram Type= 6, Freq= 0, CH_1, rank 1
6716 11:08:02.971828 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6717 11:08:02.972367 ==
6718 11:08:02.972789
6719 11:08:02.973141
6720 11:08:02.976215 TX Vref Scan disable
6721 11:08:02.976824 == TX Byte 0 ==
6722 11:08:02.981925 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6723 11:08:02.985755 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6724 11:08:02.986323 == TX Byte 1 ==
6725 11:08:02.992420 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6726 11:08:02.994942 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6727 11:08:02.995508 ==
6728 11:08:02.997927 Dram Type= 6, Freq= 0, CH_1, rank 1
6729 11:08:03.001339 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6730 11:08:03.001817 ==
6731 11:08:03.002183
6732 11:08:03.002518
6733 11:08:03.004811 TX Vref Scan disable
6734 11:08:03.005272 == TX Byte 0 ==
6735 11:08:03.011669 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6736 11:08:03.014725 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6737 11:08:03.015188 == TX Byte 1 ==
6738 11:08:03.021996 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6739 11:08:03.025172 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6740 11:08:03.025727
6741 11:08:03.026148 [DATLAT]
6742 11:08:03.028421 Freq=400, CH1 RK1
6743 11:08:03.029030
6744 11:08:03.029404 DATLAT Default: 0xd
6745 11:08:03.031322 0, 0xFFFF, sum = 0
6746 11:08:03.031791 1, 0xFFFF, sum = 0
6747 11:08:03.034692 2, 0xFFFF, sum = 0
6748 11:08:03.035273 3, 0xFFFF, sum = 0
6749 11:08:03.038134 4, 0xFFFF, sum = 0
6750 11:08:03.038731 5, 0xFFFF, sum = 0
6751 11:08:03.041279 6, 0xFFFF, sum = 0
6752 11:08:03.041754 7, 0xFFFF, sum = 0
6753 11:08:03.045217 8, 0xFFFF, sum = 0
6754 11:08:03.045783 9, 0xFFFF, sum = 0
6755 11:08:03.047783 10, 0xFFFF, sum = 0
6756 11:08:03.052182 11, 0xFFFF, sum = 0
6757 11:08:03.052785 12, 0x0, sum = 1
6758 11:08:03.053172 13, 0x0, sum = 2
6759 11:08:03.054634 14, 0x0, sum = 3
6760 11:08:03.055100 15, 0x0, sum = 4
6761 11:08:03.058321 best_step = 13
6762 11:08:03.058877
6763 11:08:03.059246 ==
6764 11:08:03.061373 Dram Type= 6, Freq= 0, CH_1, rank 1
6765 11:08:03.064640 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6766 11:08:03.065240 ==
6767 11:08:03.067502 RX Vref Scan: 0
6768 11:08:03.067963
6769 11:08:03.068330 RX Vref 0 -> 0, step: 1
6770 11:08:03.071398
6771 11:08:03.071966 RX Delay -359 -> 252, step: 8
6772 11:08:03.080241 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6773 11:08:03.083477 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6774 11:08:03.086582 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6775 11:08:03.089263 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6776 11:08:03.096548 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6777 11:08:03.100775 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6778 11:08:03.102560 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6779 11:08:03.106645 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6780 11:08:03.112827 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6781 11:08:03.116638 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6782 11:08:03.119222 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6783 11:08:03.125682 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6784 11:08:03.129722 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6785 11:08:03.132659 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6786 11:08:03.135750 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6787 11:08:03.142682 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6788 11:08:03.143251 ==
6789 11:08:03.146837 Dram Type= 6, Freq= 0, CH_1, rank 1
6790 11:08:03.149598 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6791 11:08:03.150064 ==
6792 11:08:03.150457 DQS Delay:
6793 11:08:03.152639 DQS0 = 48, DQS1 = 64
6794 11:08:03.153366 DQM Delay:
6795 11:08:03.155117 DQM0 = 9, DQM1 = 15
6796 11:08:03.155579 DQ Delay:
6797 11:08:03.158750 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6798 11:08:03.162056 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6799 11:08:03.165668 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6800 11:08:03.169256 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6801 11:08:03.169940
6802 11:08:03.170465
6803 11:08:03.175472 [DQSOSCAuto] RK1, (LSB)MR18= 0x9f9f, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6804 11:08:03.179342 CH1 RK1: MR19=C0C, MR18=9F9F
6805 11:08:03.185590 CH1_RK1: MR19=0xC0C, MR18=0x9F9F, DQSOSC=389, MR23=63, INC=390, DEC=260
6806 11:08:03.188240 [RxdqsGatingPostProcess] freq 400
6807 11:08:03.195142 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6808 11:08:03.198269 Pre-setting of DQS Precalculation
6809 11:08:03.202343 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6810 11:08:03.208528 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6811 11:08:03.214809 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6812 11:08:03.215379
6813 11:08:03.218003
6814 11:08:03.218478 [Calibration Summary] 800 Mbps
6815 11:08:03.221834 CH 0, Rank 0
6816 11:08:03.222416 SW Impedance : PASS
6817 11:08:03.224778 DUTY Scan : NO K
6818 11:08:03.228698 ZQ Calibration : PASS
6819 11:08:03.229313 Jitter Meter : NO K
6820 11:08:03.232405 CBT Training : PASS
6821 11:08:03.234776 Write leveling : PASS
6822 11:08:03.235343 RX DQS gating : PASS
6823 11:08:03.237805 RX DQ/DQS(RDDQC) : PASS
6824 11:08:03.241900 TX DQ/DQS : PASS
6825 11:08:03.242466 RX DATLAT : PASS
6826 11:08:03.245656 RX DQ/DQS(Engine): PASS
6827 11:08:03.247906 TX OE : NO K
6828 11:08:03.248478 All Pass.
6829 11:08:03.248903
6830 11:08:03.249348 CH 0, Rank 1
6831 11:08:03.251577 SW Impedance : PASS
6832 11:08:03.254781 DUTY Scan : NO K
6833 11:08:03.255241 ZQ Calibration : PASS
6834 11:08:03.257767 Jitter Meter : NO K
6835 11:08:03.261620 CBT Training : PASS
6836 11:08:03.262187 Write leveling : NO K
6837 11:08:03.264236 RX DQS gating : PASS
6838 11:08:03.264697 RX DQ/DQS(RDDQC) : PASS
6839 11:08:03.267659 TX DQ/DQS : PASS
6840 11:08:03.271632 RX DATLAT : PASS
6841 11:08:03.272092 RX DQ/DQS(Engine): PASS
6842 11:08:03.274262 TX OE : NO K
6843 11:08:03.274729 All Pass.
6844 11:08:03.275099
6845 11:08:03.277578 CH 1, Rank 0
6846 11:08:03.278145 SW Impedance : PASS
6847 11:08:03.281497 DUTY Scan : NO K
6848 11:08:03.284360 ZQ Calibration : PASS
6849 11:08:03.284857 Jitter Meter : NO K
6850 11:08:03.287417 CBT Training : PASS
6851 11:08:03.290850 Write leveling : PASS
6852 11:08:03.291441 RX DQS gating : PASS
6853 11:08:03.295603 RX DQ/DQS(RDDQC) : PASS
6854 11:08:03.297272 TX DQ/DQS : PASS
6855 11:08:03.297738 RX DATLAT : PASS
6856 11:08:03.300992 RX DQ/DQS(Engine): PASS
6857 11:08:03.303745 TX OE : NO K
6858 11:08:03.304280 All Pass.
6859 11:08:03.304653
6860 11:08:03.305054 CH 1, Rank 1
6861 11:08:03.307267 SW Impedance : PASS
6862 11:08:03.310886 DUTY Scan : NO K
6863 11:08:03.311345 ZQ Calibration : PASS
6864 11:08:03.313998 Jitter Meter : NO K
6865 11:08:03.317730 CBT Training : PASS
6866 11:08:03.318192 Write leveling : NO K
6867 11:08:03.320354 RX DQS gating : PASS
6868 11:08:03.324311 RX DQ/DQS(RDDQC) : PASS
6869 11:08:03.324911 TX DQ/DQS : PASS
6870 11:08:03.327542 RX DATLAT : PASS
6871 11:08:03.328091 RX DQ/DQS(Engine): PASS
6872 11:08:03.330680 TX OE : NO K
6873 11:08:03.331236 All Pass.
6874 11:08:03.331608
6875 11:08:03.334619 DramC Write-DBI off
6876 11:08:03.337632 PER_BANK_REFRESH: Hybrid Mode
6877 11:08:03.338192 TX_TRACKING: ON
6878 11:08:03.347381 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6879 11:08:03.350867 [FAST_K] Save calibration result to emmc
6880 11:08:03.353611 dramc_set_vcore_voltage set vcore to 725000
6881 11:08:03.358123 Read voltage for 1600, 0
6882 11:08:03.358802 Vio18 = 0
6883 11:08:03.360356 Vcore = 725000
6884 11:08:03.360862 Vdram = 0
6885 11:08:03.361241 Vddq = 0
6886 11:08:03.361586 Vmddr = 0
6887 11:08:03.366792 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6888 11:08:03.373493 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6889 11:08:03.374074 MEM_TYPE=3, freq_sel=13
6890 11:08:03.376986 sv_algorithm_assistance_LP4_3733
6891 11:08:03.380485 ============ PULL DRAM RESETB DOWN ============
6892 11:08:03.386954 ========== PULL DRAM RESETB DOWN end =========
6893 11:08:03.390582 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6894 11:08:03.393708 ===================================
6895 11:08:03.397178 LPDDR4 DRAM CONFIGURATION
6896 11:08:03.400140 ===================================
6897 11:08:03.400744 EX_ROW_EN[0] = 0x0
6898 11:08:03.403189 EX_ROW_EN[1] = 0x0
6899 11:08:03.406737 LP4Y_EN = 0x0
6900 11:08:03.407217 WORK_FSP = 0x1
6901 11:08:03.409497 WL = 0x5
6902 11:08:03.409955 RL = 0x5
6903 11:08:03.413129 BL = 0x2
6904 11:08:03.413692 RPST = 0x0
6905 11:08:03.416250 RD_PRE = 0x0
6906 11:08:03.416756 WR_PRE = 0x1
6907 11:08:03.419851 WR_PST = 0x1
6908 11:08:03.420416 DBI_WR = 0x0
6909 11:08:03.423528 DBI_RD = 0x0
6910 11:08:03.424100 OTF = 0x1
6911 11:08:03.426707 ===================================
6912 11:08:03.429683 ===================================
6913 11:08:03.432789 ANA top config
6914 11:08:03.436109 ===================================
6915 11:08:03.436666 DLL_ASYNC_EN = 0
6916 11:08:03.440021 ALL_SLAVE_EN = 0
6917 11:08:03.442743 NEW_RANK_MODE = 1
6918 11:08:03.446213 DLL_IDLE_MODE = 1
6919 11:08:03.449560 LP45_APHY_COMB_EN = 1
6920 11:08:03.450114 TX_ODT_DIS = 0
6921 11:08:03.453647 NEW_8X_MODE = 1
6922 11:08:03.456379 ===================================
6923 11:08:03.460448 ===================================
6924 11:08:03.464532 data_rate = 3200
6925 11:08:03.466343 CKR = 1
6926 11:08:03.469543 DQ_P2S_RATIO = 8
6927 11:08:03.474599 ===================================
6928 11:08:03.475188 CA_P2S_RATIO = 8
6929 11:08:03.476761 DQ_CA_OPEN = 0
6930 11:08:03.480190 DQ_SEMI_OPEN = 0
6931 11:08:03.482991 CA_SEMI_OPEN = 0
6932 11:08:03.486291 CA_FULL_RATE = 0
6933 11:08:03.489369 DQ_CKDIV4_EN = 0
6934 11:08:03.492336 CA_CKDIV4_EN = 0
6935 11:08:03.492849 CA_PREDIV_EN = 0
6936 11:08:03.497013 PH8_DLY = 12
6937 11:08:03.498754 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6938 11:08:03.502447 DQ_AAMCK_DIV = 4
6939 11:08:03.505431 CA_AAMCK_DIV = 4
6940 11:08:03.509250 CA_ADMCK_DIV = 4
6941 11:08:03.509828 DQ_TRACK_CA_EN = 0
6942 11:08:03.512086 CA_PICK = 1600
6943 11:08:03.517189 CA_MCKIO = 1600
6944 11:08:03.519888 MCKIO_SEMI = 0
6945 11:08:03.522602 PLL_FREQ = 3068
6946 11:08:03.525387 DQ_UI_PI_RATIO = 32
6947 11:08:03.529241 CA_UI_PI_RATIO = 0
6948 11:08:03.532236 ===================================
6949 11:08:03.535448 ===================================
6950 11:08:03.536018 memory_type:LPDDR4
6951 11:08:03.538948 GP_NUM : 10
6952 11:08:03.542725 SRAM_EN : 1
6953 11:08:03.543289 MD32_EN : 0
6954 11:08:03.545230 ===================================
6955 11:08:03.548892 [ANA_INIT] >>>>>>>>>>>>>>
6956 11:08:03.552335 <<<<<< [CONFIGURE PHASE]: ANA_TX
6957 11:08:03.555029 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6958 11:08:03.558634 ===================================
6959 11:08:03.562269 data_rate = 3200,PCW = 0X7600
6960 11:08:03.565963 ===================================
6961 11:08:03.568686 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6962 11:08:03.572178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6963 11:08:03.578616 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6964 11:08:03.582449 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6965 11:08:03.585619 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6966 11:08:03.588880 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6967 11:08:03.592002 [ANA_INIT] flow start
6968 11:08:03.595645 [ANA_INIT] PLL >>>>>>>>
6969 11:08:03.596211 [ANA_INIT] PLL <<<<<<<<
6970 11:08:03.598530 [ANA_INIT] MIDPI >>>>>>>>
6971 11:08:03.601569 [ANA_INIT] MIDPI <<<<<<<<
6972 11:08:03.605106 [ANA_INIT] DLL >>>>>>>>
6973 11:08:03.605566 [ANA_INIT] DLL <<<<<<<<
6974 11:08:03.607997 [ANA_INIT] flow end
6975 11:08:03.612041 ============ LP4 DIFF to SE enter ============
6976 11:08:03.614495 ============ LP4 DIFF to SE exit ============
6977 11:08:03.618508 [ANA_INIT] <<<<<<<<<<<<<
6978 11:08:03.621399 [Flow] Enable top DCM control >>>>>
6979 11:08:03.624888 [Flow] Enable top DCM control <<<<<
6980 11:08:03.628279 Enable DLL master slave shuffle
6981 11:08:03.634862 ==============================================================
6982 11:08:03.635422 Gating Mode config
6983 11:08:03.641638 ==============================================================
6984 11:08:03.642303 Config description:
6985 11:08:03.651312 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6986 11:08:03.658257 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6987 11:08:03.665393 SELPH_MODE 0: By rank 1: By Phase
6988 11:08:03.668069 ==============================================================
6989 11:08:03.671035 GAT_TRACK_EN = 1
6990 11:08:03.674716 RX_GATING_MODE = 2
6991 11:08:03.678071 RX_GATING_TRACK_MODE = 2
6992 11:08:03.680830 SELPH_MODE = 1
6993 11:08:03.685005 PICG_EARLY_EN = 1
6994 11:08:03.688060 VALID_LAT_VALUE = 1
6995 11:08:03.694750 ==============================================================
6996 11:08:03.698301 Enter into Gating configuration >>>>
6997 11:08:03.701000 Exit from Gating configuration <<<<
6998 11:08:03.701460 Enter into DVFS_PRE_config >>>>>
6999 11:08:03.714073 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7000 11:08:03.717316 Exit from DVFS_PRE_config <<<<<
7001 11:08:03.720981 Enter into PICG configuration >>>>
7002 11:08:03.724407 Exit from PICG configuration <<<<
7003 11:08:03.727779 [RX_INPUT] configuration >>>>>
7004 11:08:03.728340 [RX_INPUT] configuration <<<<<
7005 11:08:03.734442 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7006 11:08:03.740831 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7007 11:08:03.744320 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7008 11:08:03.750475 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7009 11:08:03.757108 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7010 11:08:03.763493 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7011 11:08:03.767121 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7012 11:08:03.770129 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7013 11:08:03.777099 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7014 11:08:03.780386 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7015 11:08:03.783469 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7016 11:08:03.790294 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7017 11:08:03.793678 ===================================
7018 11:08:03.794233 LPDDR4 DRAM CONFIGURATION
7019 11:08:03.796879 ===================================
7020 11:08:03.799924 EX_ROW_EN[0] = 0x0
7021 11:08:03.803414 EX_ROW_EN[1] = 0x0
7022 11:08:03.804096 LP4Y_EN = 0x0
7023 11:08:03.807473 WORK_FSP = 0x1
7024 11:08:03.808024 WL = 0x5
7025 11:08:03.810272 RL = 0x5
7026 11:08:03.810827 BL = 0x2
7027 11:08:03.813341 RPST = 0x0
7028 11:08:03.813947 RD_PRE = 0x0
7029 11:08:03.817424 WR_PRE = 0x1
7030 11:08:03.817971 WR_PST = 0x1
7031 11:08:03.820122 DBI_WR = 0x0
7032 11:08:03.820804 DBI_RD = 0x0
7033 11:08:03.823436 OTF = 0x1
7034 11:08:03.826417 ===================================
7035 11:08:03.829964 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7036 11:08:03.833118 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7037 11:08:03.839536 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7038 11:08:03.843824 ===================================
7039 11:08:03.844380 LPDDR4 DRAM CONFIGURATION
7040 11:08:03.846342 ===================================
7041 11:08:03.849584 EX_ROW_EN[0] = 0x10
7042 11:08:03.852851 EX_ROW_EN[1] = 0x0
7043 11:08:03.853412 LP4Y_EN = 0x0
7044 11:08:03.855974 WORK_FSP = 0x1
7045 11:08:03.856543 WL = 0x5
7046 11:08:03.859252 RL = 0x5
7047 11:08:03.859797 BL = 0x2
7048 11:08:03.862524 RPST = 0x0
7049 11:08:03.862978 RD_PRE = 0x0
7050 11:08:03.865955 WR_PRE = 0x1
7051 11:08:03.866504 WR_PST = 0x1
7052 11:08:03.869466 DBI_WR = 0x0
7053 11:08:03.870022 DBI_RD = 0x0
7054 11:08:03.873306 OTF = 0x1
7055 11:08:03.875673 ===================================
7056 11:08:03.882597 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7057 11:08:03.883177 ==
7058 11:08:03.885601 Dram Type= 6, Freq= 0, CH_0, rank 0
7059 11:08:03.889314 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7060 11:08:03.890028 ==
7061 11:08:03.892449 [Duty_Offset_Calibration]
7062 11:08:03.892968 B0:0 B1:2 CA:1
7063 11:08:03.893457
7064 11:08:03.896437 [DutyScan_Calibration_Flow] k_type=0
7065 11:08:03.906379
7066 11:08:03.906856 ==CLK 0==
7067 11:08:03.909609 Final CLK duty delay cell = 0
7068 11:08:03.913347 [0] MAX Duty = 5187%(X100), DQS PI = 24
7069 11:08:03.916294 [0] MIN Duty = 4938%(X100), DQS PI = 54
7070 11:08:03.920002 [0] AVG Duty = 5062%(X100)
7071 11:08:03.920581
7072 11:08:03.922671 CH0 CLK Duty spec in!! Max-Min= 249%
7073 11:08:03.926232 [DutyScan_Calibration_Flow] ====Done====
7074 11:08:03.926811
7075 11:08:03.929128 [DutyScan_Calibration_Flow] k_type=1
7076 11:08:03.946503
7077 11:08:03.947081 ==DQS 0 ==
7078 11:08:03.950294 Final DQS duty delay cell = 0
7079 11:08:03.953605 [0] MAX Duty = 5156%(X100), DQS PI = 34
7080 11:08:03.956081 [0] MIN Duty = 5000%(X100), DQS PI = 8
7081 11:08:03.959693 [0] AVG Duty = 5078%(X100)
7082 11:08:03.960271
7083 11:08:03.960809 ==DQS 1 ==
7084 11:08:03.962976 Final DQS duty delay cell = 0
7085 11:08:03.966207 [0] MAX Duty = 5031%(X100), DQS PI = 6
7086 11:08:03.971704 [0] MIN Duty = 4875%(X100), DQS PI = 18
7087 11:08:03.972680 [0] AVG Duty = 4953%(X100)
7088 11:08:03.973170
7089 11:08:03.976199 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7090 11:08:03.976829
7091 11:08:03.979340 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7092 11:08:03.983300 [DutyScan_Calibration_Flow] ====Done====
7093 11:08:03.983873
7094 11:08:03.986780 [DutyScan_Calibration_Flow] k_type=3
7095 11:08:04.004937
7096 11:08:04.005747 ==DQM 0 ==
7097 11:08:04.007183 Final DQM duty delay cell = 0
7098 11:08:04.011055 [0] MAX Duty = 5187%(X100), DQS PI = 22
7099 11:08:04.014100 [0] MIN Duty = 4907%(X100), DQS PI = 42
7100 11:08:04.017133 [0] AVG Duty = 5047%(X100)
7101 11:08:04.017592
7102 11:08:04.017954 ==DQM 1 ==
7103 11:08:04.020302 Final DQM duty delay cell = 0
7104 11:08:04.023168 [0] MAX Duty = 5031%(X100), DQS PI = 50
7105 11:08:04.026761 [0] MIN Duty = 4782%(X100), DQS PI = 16
7106 11:08:04.030300 [0] AVG Duty = 4906%(X100)
7107 11:08:04.030852
7108 11:08:04.033199 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7109 11:08:04.033757
7110 11:08:04.036283 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7111 11:08:04.039437 [DutyScan_Calibration_Flow] ====Done====
7112 11:08:04.039898
7113 11:08:04.043614 [DutyScan_Calibration_Flow] k_type=2
7114 11:08:04.060242
7115 11:08:04.060843 ==DQ 0 ==
7116 11:08:04.063616 Final DQ duty delay cell = 0
7117 11:08:04.066715 [0] MAX Duty = 5218%(X100), DQS PI = 18
7118 11:08:04.069522 [0] MIN Duty = 4938%(X100), DQS PI = 56
7119 11:08:04.069994 [0] AVG Duty = 5078%(X100)
7120 11:08:04.073392
7121 11:08:04.073944 ==DQ 1 ==
7122 11:08:04.076293 Final DQ duty delay cell = -4
7123 11:08:04.079459 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7124 11:08:04.082888 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7125 11:08:04.087446 [-4] AVG Duty = 4953%(X100)
7126 11:08:04.087999
7127 11:08:04.089088 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7128 11:08:04.089720
7129 11:08:04.092989 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7130 11:08:04.096514 [DutyScan_Calibration_Flow] ====Done====
7131 11:08:04.096945 ==
7132 11:08:04.099195 Dram Type= 6, Freq= 0, CH_1, rank 0
7133 11:08:04.102803 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7134 11:08:04.103362 ==
7135 11:08:04.105931 [Duty_Offset_Calibration]
7136 11:08:04.106463 B0:0 B1:4 CA:-5
7137 11:08:04.106830
7138 11:08:04.109225 [DutyScan_Calibration_Flow] k_type=0
7139 11:08:04.120514
7140 11:08:04.121121 ==CLK 0==
7141 11:08:04.124683 Final CLK duty delay cell = 0
7142 11:08:04.127520 [0] MAX Duty = 5156%(X100), DQS PI = 20
7143 11:08:04.130608 [0] MIN Duty = 4906%(X100), DQS PI = 52
7144 11:08:04.134871 [0] AVG Duty = 5031%(X100)
7145 11:08:04.135430
7146 11:08:04.136824 CH1 CLK Duty spec in!! Max-Min= 250%
7147 11:08:04.140868 [DutyScan_Calibration_Flow] ====Done====
7148 11:08:04.141502
7149 11:08:04.143062 [DutyScan_Calibration_Flow] k_type=1
7150 11:08:04.159330
7151 11:08:04.159875 ==DQS 0 ==
7152 11:08:04.162694 Final DQS duty delay cell = 0
7153 11:08:04.165905 [0] MAX Duty = 5156%(X100), DQS PI = 18
7154 11:08:04.169312 [0] MIN Duty = 4876%(X100), DQS PI = 42
7155 11:08:04.172590 [0] AVG Duty = 5016%(X100)
7156 11:08:04.173100
7157 11:08:04.173460 ==DQS 1 ==
7158 11:08:04.175767 Final DQS duty delay cell = -4
7159 11:08:04.179555 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7160 11:08:04.182623 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7161 11:08:04.185668 [-4] AVG Duty = 4922%(X100)
7162 11:08:04.186219
7163 11:08:04.190190 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7164 11:08:04.190743
7165 11:08:04.192261 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7166 11:08:04.196066 [DutyScan_Calibration_Flow] ====Done====
7167 11:08:04.196618
7168 11:08:04.198997 [DutyScan_Calibration_Flow] k_type=3
7169 11:08:04.215742
7170 11:08:04.216293 ==DQM 0 ==
7171 11:08:04.218002 Final DQM duty delay cell = -4
7172 11:08:04.222718 [-4] MAX Duty = 5062%(X100), DQS PI = 32
7173 11:08:04.224954 [-4] MIN Duty = 4782%(X100), DQS PI = 46
7174 11:08:04.228385 [-4] AVG Duty = 4922%(X100)
7175 11:08:04.228998
7176 11:08:04.229372 ==DQM 1 ==
7177 11:08:04.231667 Final DQM duty delay cell = -4
7178 11:08:04.235397 [-4] MAX Duty = 5062%(X100), DQS PI = 16
7179 11:08:04.238145 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7180 11:08:04.242062 [-4] AVG Duty = 4984%(X100)
7181 11:08:04.242618
7182 11:08:04.246153 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7183 11:08:04.246717
7184 11:08:04.248528 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7185 11:08:04.252743 [DutyScan_Calibration_Flow] ====Done====
7186 11:08:04.253314
7187 11:08:04.254461 [DutyScan_Calibration_Flow] k_type=2
7188 11:08:04.272628
7189 11:08:04.273220 ==DQ 0 ==
7190 11:08:04.275874 Final DQ duty delay cell = 0
7191 11:08:04.280156 [0] MAX Duty = 5093%(X100), DQS PI = 4
7192 11:08:04.282211 [0] MIN Duty = 4969%(X100), DQS PI = 44
7193 11:08:04.282671 [0] AVG Duty = 5031%(X100)
7194 11:08:04.286619
7195 11:08:04.287171 ==DQ 1 ==
7196 11:08:04.289569 Final DQ duty delay cell = 0
7197 11:08:04.292256 [0] MAX Duty = 5062%(X100), DQS PI = 6
7198 11:08:04.296047 [0] MIN Duty = 4876%(X100), DQS PI = 28
7199 11:08:04.296603 [0] AVG Duty = 4969%(X100)
7200 11:08:04.297049
7201 11:08:04.298988 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7202 11:08:04.302069
7203 11:08:04.305704 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7204 11:08:04.309177 [DutyScan_Calibration_Flow] ====Done====
7205 11:08:04.312651 nWR fixed to 30
7206 11:08:04.313269 [ModeRegInit_LP4] CH0 RK0
7207 11:08:04.315618 [ModeRegInit_LP4] CH0 RK1
7208 11:08:04.319481 [ModeRegInit_LP4] CH1 RK0
7209 11:08:04.322316 [ModeRegInit_LP4] CH1 RK1
7210 11:08:04.322773 match AC timing 4
7211 11:08:04.325251 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7212 11:08:04.332155 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7213 11:08:04.335298 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7214 11:08:04.342540 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7215 11:08:04.345616 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7216 11:08:04.346177 [MiockJmeterHQA]
7217 11:08:04.346543
7218 11:08:04.348825 [DramcMiockJmeter] u1RxGatingPI = 0
7219 11:08:04.352025 0 : 4368, 4140
7220 11:08:04.352590 4 : 4253, 4027
7221 11:08:04.355334 8 : 4255, 4029
7222 11:08:04.355890 12 : 4253, 4027
7223 11:08:04.356264 16 : 4252, 4026
7224 11:08:04.358868 20 : 4253, 4026
7225 11:08:04.359428 24 : 4252, 4027
7226 11:08:04.362877 28 : 4253, 4027
7227 11:08:04.363437 32 : 4249, 4027
7228 11:08:04.364809 36 : 4255, 4029
7229 11:08:04.365270 40 : 4253, 4026
7230 11:08:04.368649 44 : 4250, 4027
7231 11:08:04.369284 48 : 4252, 4027
7232 11:08:04.369660 52 : 4253, 4029
7233 11:08:04.372177 56 : 4250, 4027
7234 11:08:04.372639 60 : 4252, 4029
7235 11:08:04.375809 64 : 4252, 4029
7236 11:08:04.376391 68 : 4249, 4027
7237 11:08:04.378260 72 : 4250, 4027
7238 11:08:04.378722 76 : 4361, 4138
7239 11:08:04.379090 80 : 4252, 4027
7240 11:08:04.382106 84 : 4252, 4029
7241 11:08:04.382571 88 : 4250, 4027
7242 11:08:04.384924 92 : 4363, 4138
7243 11:08:04.385390 96 : 4365, 4140
7244 11:08:04.388123 100 : 4360, 2045
7245 11:08:04.388589 104 : 4360, 0
7246 11:08:04.392046 108 : 4249, 0
7247 11:08:04.392628 112 : 4250, 0
7248 11:08:04.393055 116 : 4361, 0
7249 11:08:04.395072 120 : 4250, 0
7250 11:08:04.395632 124 : 4361, 0
7251 11:08:04.396008 128 : 4250, 0
7252 11:08:04.398039 132 : 4250, 0
7253 11:08:04.398554 136 : 4250, 0
7254 11:08:04.401570 140 : 4250, 0
7255 11:08:04.402037 144 : 4250, 0
7256 11:08:04.402411 148 : 4250, 0
7257 11:08:04.405084 152 : 4250, 0
7258 11:08:04.405654 156 : 4250, 0
7259 11:08:04.408288 160 : 4361, 0
7260 11:08:04.408784 164 : 4250, 0
7261 11:08:04.409165 168 : 4363, 0
7262 11:08:04.411563 172 : 4360, 0
7263 11:08:04.412126 176 : 4250, 0
7264 11:08:04.414964 180 : 4255, 0
7265 11:08:04.415584 184 : 4250, 0
7266 11:08:04.415965 188 : 4250, 0
7267 11:08:04.418038 192 : 4255, 0
7268 11:08:04.418502 196 : 4250, 0
7269 11:08:04.418872 200 : 4250, 0
7270 11:08:04.421304 204 : 4250, 0
7271 11:08:04.421786 208 : 4250, 0
7272 11:08:04.424905 212 : 4249, 0
7273 11:08:04.425370 216 : 4363, 0
7274 11:08:04.425750 220 : 4250, 668
7275 11:08:04.428324 224 : 4250, 4011
7276 11:08:04.428929 228 : 4252, 4029
7277 11:08:04.431749 232 : 4250, 4026
7278 11:08:04.432311 236 : 4250, 4027
7279 11:08:04.435931 240 : 4362, 4140
7280 11:08:04.436490 244 : 4252, 4029
7281 11:08:04.438017 248 : 4250, 4026
7282 11:08:04.438481 252 : 4255, 4030
7283 11:08:04.441649 256 : 4252, 4030
7284 11:08:04.442214 260 : 4250, 4026
7285 11:08:04.445066 264 : 4250, 4027
7286 11:08:04.445649 268 : 4252, 4029
7287 11:08:04.448484 272 : 4252, 4029
7288 11:08:04.449084 276 : 4250, 4026
7289 11:08:04.449461 280 : 4253, 4029
7290 11:08:04.451623 284 : 4250, 4026
7291 11:08:04.452181 288 : 4250, 4027
7292 11:08:04.455013 292 : 4255, 4032
7293 11:08:04.455476 296 : 4250, 4027
7294 11:08:04.458327 300 : 4250, 4027
7295 11:08:04.458793 304 : 4250, 4026
7296 11:08:04.461359 308 : 4250, 4026
7297 11:08:04.461824 312 : 4250, 4027
7298 11:08:04.465086 316 : 4360, 4137
7299 11:08:04.465644 320 : 4363, 4138
7300 11:08:04.468234 324 : 4247, 4024
7301 11:08:04.468824 328 : 4250, 4027
7302 11:08:04.471744 332 : 4252, 4029
7303 11:08:04.472209 336 : 4252, 3846
7304 11:08:04.472583 340 : 4253, 2062
7305 11:08:04.474847
7306 11:08:04.475396 MIOCK jitter meter ch=0
7307 11:08:04.475763
7308 11:08:04.477652 1T = (340-100) = 240 dly cells
7309 11:08:04.484465 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7310 11:08:04.485050 ==
7311 11:08:04.488978 Dram Type= 6, Freq= 0, CH_0, rank 0
7312 11:08:04.490800 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7313 11:08:04.491259 ==
7314 11:08:04.497983 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7315 11:08:04.501435 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7316 11:08:04.504020 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7317 11:08:04.511447 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7318 11:08:04.520167 [CA 0] Center 41 (11~72) winsize 62
7319 11:08:04.522995 [CA 1] Center 41 (11~72) winsize 62
7320 11:08:04.526285 [CA 2] Center 37 (7~68) winsize 62
7321 11:08:04.529539 [CA 3] Center 37 (7~67) winsize 61
7322 11:08:04.532909 [CA 4] Center 35 (5~66) winsize 62
7323 11:08:04.536080 [CA 5] Center 35 (5~65) winsize 61
7324 11:08:04.536638
7325 11:08:04.539649 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7326 11:08:04.540206
7327 11:08:04.542748 [CATrainingPosCal] consider 1 rank data
7328 11:08:04.546262 u2DelayCellTimex100 = 271/100 ps
7329 11:08:04.549303 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7330 11:08:04.555834 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7331 11:08:04.559328 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7332 11:08:04.563142 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7333 11:08:04.566167 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7334 11:08:04.569613 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7335 11:08:04.570182
7336 11:08:04.572895 CA PerBit enable=1, Macro0, CA PI delay=35
7337 11:08:04.573450
7338 11:08:04.576905 [CBTSetCACLKResult] CA Dly = 35
7339 11:08:04.579185 CS Dly: 11 (0~42)
7340 11:08:04.582707 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7341 11:08:04.585982 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7342 11:08:04.586534 ==
7343 11:08:04.589114 Dram Type= 6, Freq= 0, CH_0, rank 1
7344 11:08:04.592495 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7345 11:08:04.596169 ==
7346 11:08:04.599439 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7347 11:08:04.602136 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7348 11:08:04.608920 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7349 11:08:04.615844 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7350 11:08:04.621992 [CA 0] Center 42 (12~73) winsize 62
7351 11:08:04.625379 [CA 1] Center 41 (11~72) winsize 62
7352 11:08:04.628966 [CA 2] Center 38 (9~68) winsize 60
7353 11:08:04.632857 [CA 3] Center 37 (8~67) winsize 60
7354 11:08:04.635545 [CA 4] Center 35 (5~65) winsize 61
7355 11:08:04.638657 [CA 5] Center 35 (5~66) winsize 62
7356 11:08:04.639217
7357 11:08:04.642147 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7358 11:08:04.642601
7359 11:08:04.645448 [CATrainingPosCal] consider 2 rank data
7360 11:08:04.648535 u2DelayCellTimex100 = 271/100 ps
7361 11:08:04.651871 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7362 11:08:04.659431 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7363 11:08:04.661712 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7364 11:08:04.665236 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7365 11:08:04.668504 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
7366 11:08:04.671448 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7367 11:08:04.671898
7368 11:08:04.674904 CA PerBit enable=1, Macro0, CA PI delay=35
7369 11:08:04.675459
7370 11:08:04.678184 [CBTSetCACLKResult] CA Dly = 35
7371 11:08:04.681252 CS Dly: 11 (0~43)
7372 11:08:04.684823 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7373 11:08:04.689064 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7374 11:08:04.689770
7375 11:08:04.691684 ----->DramcWriteLeveling(PI) begin...
7376 11:08:04.692243 ==
7377 11:08:04.695004 Dram Type= 6, Freq= 0, CH_0, rank 0
7378 11:08:04.701115 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7379 11:08:04.701574 ==
7380 11:08:04.705163 Write leveling (Byte 0): 30 => 30
7381 11:08:04.707843 Write leveling (Byte 1): 27 => 27
7382 11:08:04.708579 DramcWriteLeveling(PI) end<-----
7383 11:08:04.711239
7384 11:08:04.711690 ==
7385 11:08:04.714187 Dram Type= 6, Freq= 0, CH_0, rank 0
7386 11:08:04.717898 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7387 11:08:04.718353 ==
7388 11:08:04.721641 [Gating] SW mode calibration
7389 11:08:04.728495 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7390 11:08:04.732073 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7391 11:08:04.738118 0 12 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7392 11:08:04.741323 0 12 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7393 11:08:04.744194 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7394 11:08:04.751739 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7395 11:08:04.754271 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7396 11:08:04.758543 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7397 11:08:04.764375 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7398 11:08:04.767595 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7399 11:08:04.770833 0 13 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7400 11:08:04.777587 0 13 4 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
7401 11:08:04.781097 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7402 11:08:04.784125 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7403 11:08:04.790828 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7404 11:08:04.793866 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7405 11:08:04.797372 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7406 11:08:04.804298 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7407 11:08:04.807888 0 14 0 | B1->B0 | 2323 3838 | 0 0 | (0 0) (1 1)
7408 11:08:04.810430 0 14 4 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
7409 11:08:04.817849 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7410 11:08:04.820401 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7411 11:08:04.823471 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7412 11:08:04.830189 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7413 11:08:04.833755 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7414 11:08:04.837266 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7415 11:08:04.843528 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7416 11:08:04.847042 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7417 11:08:04.850965 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7418 11:08:04.857656 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7419 11:08:04.860021 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7420 11:08:04.863976 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7421 11:08:04.870325 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7422 11:08:04.873351 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7423 11:08:04.877100 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7424 11:08:04.883357 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7425 11:08:04.886625 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7426 11:08:04.890257 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7427 11:08:04.896649 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7428 11:08:04.900492 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7429 11:08:04.903161 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7430 11:08:04.909545 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7431 11:08:04.912800 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7432 11:08:04.916493 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7433 11:08:04.924392 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7434 11:08:04.925002 Total UI for P1: 0, mck2ui 16
7435 11:08:04.929438 best dqsien dly found for B0: ( 1, 1, 4)
7436 11:08:04.932820 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7437 11:08:04.936379 Total UI for P1: 0, mck2ui 16
7438 11:08:04.939632 best dqsien dly found for B1: ( 1, 1, 6)
7439 11:08:04.942813 best DQS0 dly(MCK, UI, PI) = (1, 1, 4)
7440 11:08:04.946778 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7441 11:08:04.947329
7442 11:08:04.949111 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 4)
7443 11:08:04.952807 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7444 11:08:04.955955 [Gating] SW calibration Done
7445 11:08:04.956519 ==
7446 11:08:04.959461 Dram Type= 6, Freq= 0, CH_0, rank 0
7447 11:08:04.963130 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7448 11:08:04.963687 ==
7449 11:08:04.966197 RX Vref Scan: 0
7450 11:08:04.966656
7451 11:08:04.970139 RX Vref 0 -> 0, step: 1
7452 11:08:04.970688
7453 11:08:04.971057 RX Delay 0 -> 252, step: 8
7454 11:08:04.976108 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7455 11:08:04.979266 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7456 11:08:04.982320 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7457 11:08:04.985698 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7458 11:08:04.988796 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7459 11:08:04.995901 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7460 11:08:04.999600 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7461 11:08:05.002109 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7462 11:08:05.005411 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7463 11:08:05.009005 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7464 11:08:05.015860 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7465 11:08:05.019080 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7466 11:08:05.021794 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7467 11:08:05.025428 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7468 11:08:05.032343 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7469 11:08:05.035928 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7470 11:08:05.036480 ==
7471 11:08:05.038275 Dram Type= 6, Freq= 0, CH_0, rank 0
7472 11:08:05.042056 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7473 11:08:05.042616 ==
7474 11:08:05.042985 DQS Delay:
7475 11:08:05.045935 DQS0 = 0, DQS1 = 0
7476 11:08:05.046663 DQM Delay:
7477 11:08:05.048937 DQM0 = 130, DQM1 = 124
7478 11:08:05.049487 DQ Delay:
7479 11:08:05.051961 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7480 11:08:05.055609 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7481 11:08:05.057971 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7482 11:08:05.065390 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7483 11:08:05.065946
7484 11:08:05.066317
7485 11:08:05.066658 ==
7486 11:08:05.068005 Dram Type= 6, Freq= 0, CH_0, rank 0
7487 11:08:05.071640 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7488 11:08:05.072102 ==
7489 11:08:05.072467
7490 11:08:05.072861
7491 11:08:05.075375 TX Vref Scan disable
7492 11:08:05.075929 == TX Byte 0 ==
7493 11:08:05.082080 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7494 11:08:05.085071 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7495 11:08:05.085630 == TX Byte 1 ==
7496 11:08:05.092071 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7497 11:08:05.094792 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7498 11:08:05.095363 ==
7499 11:08:05.098223 Dram Type= 6, Freq= 0, CH_0, rank 0
7500 11:08:05.101188 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7501 11:08:05.101652 ==
7502 11:08:05.115403
7503 11:08:05.118545 TX Vref early break, caculate TX vref
7504 11:08:05.122132 TX Vref=16, minBit 9, minWin=21, winSum=370
7505 11:08:05.124943 TX Vref=18, minBit 9, minWin=22, winSum=381
7506 11:08:05.128812 TX Vref=20, minBit 8, minWin=23, winSum=386
7507 11:08:05.131832 TX Vref=22, minBit 8, minWin=23, winSum=397
7508 11:08:05.134930 TX Vref=24, minBit 8, minWin=24, winSum=406
7509 11:08:05.141550 TX Vref=26, minBit 4, minWin=25, winSum=413
7510 11:08:05.144703 TX Vref=28, minBit 3, minWin=25, winSum=418
7511 11:08:05.148167 TX Vref=30, minBit 0, minWin=25, winSum=413
7512 11:08:05.151225 TX Vref=32, minBit 2, minWin=24, winSum=400
7513 11:08:05.155023 TX Vref=34, minBit 0, minWin=24, winSum=394
7514 11:08:05.160980 [TxChooseVref] Worse bit 3, Min win 25, Win sum 418, Final Vref 28
7515 11:08:05.161440
7516 11:08:05.164636 Final TX Range 0 Vref 28
7517 11:08:05.165421
7518 11:08:05.165805 ==
7519 11:08:05.168021 Dram Type= 6, Freq= 0, CH_0, rank 0
7520 11:08:05.171295 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7521 11:08:05.171757 ==
7522 11:08:05.172123
7523 11:08:05.172456
7524 11:08:05.174564 TX Vref Scan disable
7525 11:08:05.181097 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7526 11:08:05.181658 == TX Byte 0 ==
7527 11:08:05.184152 u2DelayCellOfst[0]=14 cells (4 PI)
7528 11:08:05.187788 u2DelayCellOfst[1]=18 cells (5 PI)
7529 11:08:05.190945 u2DelayCellOfst[2]=14 cells (4 PI)
7530 11:08:05.194437 u2DelayCellOfst[3]=14 cells (4 PI)
7531 11:08:05.197430 u2DelayCellOfst[4]=7 cells (2 PI)
7532 11:08:05.201100 u2DelayCellOfst[5]=0 cells (0 PI)
7533 11:08:05.204174 u2DelayCellOfst[6]=18 cells (5 PI)
7534 11:08:05.207089 u2DelayCellOfst[7]=18 cells (5 PI)
7535 11:08:05.210700 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7536 11:08:05.213933 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7537 11:08:05.217619 == TX Byte 1 ==
7538 11:08:05.220391 u2DelayCellOfst[8]=3 cells (1 PI)
7539 11:08:05.223862 u2DelayCellOfst[9]=0 cells (0 PI)
7540 11:08:05.227313 u2DelayCellOfst[10]=10 cells (3 PI)
7541 11:08:05.227767 u2DelayCellOfst[11]=7 cells (2 PI)
7542 11:08:05.230540 u2DelayCellOfst[12]=18 cells (5 PI)
7543 11:08:05.234049 u2DelayCellOfst[13]=18 cells (5 PI)
7544 11:08:05.236986 u2DelayCellOfst[14]=21 cells (6 PI)
7545 11:08:05.240634 u2DelayCellOfst[15]=18 cells (5 PI)
7546 11:08:05.247605 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7547 11:08:05.251839 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7548 11:08:05.252302 DramC Write-DBI on
7549 11:08:05.254244 ==
7550 11:08:05.254798 Dram Type= 6, Freq= 0, CH_0, rank 0
7551 11:08:05.260539 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7552 11:08:05.261077 ==
7553 11:08:05.261446
7554 11:08:05.261783
7555 11:08:05.263173 TX Vref Scan disable
7556 11:08:05.263643 == TX Byte 0 ==
7557 11:08:05.270537 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7558 11:08:05.271098 == TX Byte 1 ==
7559 11:08:05.273350 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7560 11:08:05.277089 DramC Write-DBI off
7561 11:08:05.277655
7562 11:08:05.278104 [DATLAT]
7563 11:08:05.280187 Freq=1600, CH0 RK0
7564 11:08:05.280647
7565 11:08:05.281051 DATLAT Default: 0xf
7566 11:08:05.283577 0, 0xFFFF, sum = 0
7567 11:08:05.284136 1, 0xFFFF, sum = 0
7568 11:08:05.287113 2, 0xFFFF, sum = 0
7569 11:08:05.287664 3, 0xFFFF, sum = 0
7570 11:08:05.290234 4, 0xFFFF, sum = 0
7571 11:08:05.290694 5, 0xFFFF, sum = 0
7572 11:08:05.294227 6, 0xFFFF, sum = 0
7573 11:08:05.294789 7, 0xFFFF, sum = 0
7574 11:08:05.297012 8, 0xFFFF, sum = 0
7575 11:08:05.297596 9, 0xFFFF, sum = 0
7576 11:08:05.300180 10, 0xFFFF, sum = 0
7577 11:08:05.303541 11, 0xFFFF, sum = 0
7578 11:08:05.304109 12, 0xFFF, sum = 0
7579 11:08:05.306457 13, 0x0, sum = 1
7580 11:08:05.306919 14, 0x0, sum = 2
7581 11:08:05.310639 15, 0x0, sum = 3
7582 11:08:05.311244 16, 0x0, sum = 4
7583 11:08:05.311882 best_step = 14
7584 11:08:05.312255
7585 11:08:05.313213 ==
7586 11:08:05.316757 Dram Type= 6, Freq= 0, CH_0, rank 0
7587 11:08:05.319812 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7588 11:08:05.320268 ==
7589 11:08:05.320627 RX Vref Scan: 1
7590 11:08:05.321026
7591 11:08:05.322738 Set Vref Range= 24 -> 127
7592 11:08:05.323191
7593 11:08:05.326505 RX Vref 24 -> 127, step: 1
7594 11:08:05.327059
7595 11:08:05.330121 RX Delay 11 -> 252, step: 4
7596 11:08:05.330728
7597 11:08:05.332876 Set Vref, RX VrefLevel [Byte0]: 24
7598 11:08:05.336692 [Byte1]: 24
7599 11:08:05.337294
7600 11:08:05.339376 Set Vref, RX VrefLevel [Byte0]: 25
7601 11:08:05.343471 [Byte1]: 25
7602 11:08:05.344046
7603 11:08:05.346469 Set Vref, RX VrefLevel [Byte0]: 26
7604 11:08:05.349241 [Byte1]: 26
7605 11:08:05.353387
7606 11:08:05.353840 Set Vref, RX VrefLevel [Byte0]: 27
7607 11:08:05.356412 [Byte1]: 27
7608 11:08:05.360933
7609 11:08:05.361385 Set Vref, RX VrefLevel [Byte0]: 28
7610 11:08:05.364362 [Byte1]: 28
7611 11:08:05.368210
7612 11:08:05.368809 Set Vref, RX VrefLevel [Byte0]: 29
7613 11:08:05.371872 [Byte1]: 29
7614 11:08:05.376452
7615 11:08:05.376960 Set Vref, RX VrefLevel [Byte0]: 30
7616 11:08:05.379300 [Byte1]: 30
7617 11:08:05.383674
7618 11:08:05.384227 Set Vref, RX VrefLevel [Byte0]: 31
7619 11:08:05.386666 [Byte1]: 31
7620 11:08:05.391157
7621 11:08:05.391609 Set Vref, RX VrefLevel [Byte0]: 32
7622 11:08:05.396651 [Byte1]: 32
7623 11:08:05.399200
7624 11:08:05.399769 Set Vref, RX VrefLevel [Byte0]: 33
7625 11:08:05.402592 [Byte1]: 33
7626 11:08:05.406932
7627 11:08:05.407386 Set Vref, RX VrefLevel [Byte0]: 34
7628 11:08:05.409466 [Byte1]: 34
7629 11:08:05.413989
7630 11:08:05.414441 Set Vref, RX VrefLevel [Byte0]: 35
7631 11:08:05.417316 [Byte1]: 35
7632 11:08:05.421521
7633 11:08:05.421971 Set Vref, RX VrefLevel [Byte0]: 36
7634 11:08:05.425071 [Byte1]: 36
7635 11:08:05.429329
7636 11:08:05.429883 Set Vref, RX VrefLevel [Byte0]: 37
7637 11:08:05.432829 [Byte1]: 37
7638 11:08:05.436796
7639 11:08:05.437350 Set Vref, RX VrefLevel [Byte0]: 38
7640 11:08:05.439999 [Byte1]: 38
7641 11:08:05.444051
7642 11:08:05.444507 Set Vref, RX VrefLevel [Byte0]: 39
7643 11:08:05.447397 [Byte1]: 39
7644 11:08:05.452046
7645 11:08:05.452497 Set Vref, RX VrefLevel [Byte0]: 40
7646 11:08:05.455315 [Byte1]: 40
7647 11:08:05.459735
7648 11:08:05.460468 Set Vref, RX VrefLevel [Byte0]: 41
7649 11:08:05.463704 [Byte1]: 41
7650 11:08:05.467477
7651 11:08:05.468027 Set Vref, RX VrefLevel [Byte0]: 42
7652 11:08:05.470606 [Byte1]: 42
7653 11:08:05.475251
7654 11:08:05.475708 Set Vref, RX VrefLevel [Byte0]: 43
7655 11:08:05.478027 [Byte1]: 43
7656 11:08:05.482365
7657 11:08:05.482919 Set Vref, RX VrefLevel [Byte0]: 44
7658 11:08:05.485880 [Byte1]: 44
7659 11:08:05.490947
7660 11:08:05.491509 Set Vref, RX VrefLevel [Byte0]: 45
7661 11:08:05.493335 [Byte1]: 45
7662 11:08:05.497628
7663 11:08:05.498209 Set Vref, RX VrefLevel [Byte0]: 46
7664 11:08:05.501070 [Byte1]: 46
7665 11:08:05.505897
7666 11:08:05.506449 Set Vref, RX VrefLevel [Byte0]: 47
7667 11:08:05.509247 [Byte1]: 47
7668 11:08:05.513577
7669 11:08:05.514155 Set Vref, RX VrefLevel [Byte0]: 48
7670 11:08:05.517349 [Byte1]: 48
7671 11:08:05.520766
7672 11:08:05.521225 Set Vref, RX VrefLevel [Byte0]: 49
7673 11:08:05.524179 [Byte1]: 49
7674 11:08:05.528466
7675 11:08:05.528976 Set Vref, RX VrefLevel [Byte0]: 50
7676 11:08:05.531638 [Byte1]: 50
7677 11:08:05.536541
7678 11:08:05.537176 Set Vref, RX VrefLevel [Byte0]: 51
7679 11:08:05.540760 [Byte1]: 51
7680 11:08:05.544100
7681 11:08:05.544651 Set Vref, RX VrefLevel [Byte0]: 52
7682 11:08:05.546818 [Byte1]: 52
7683 11:08:05.551573
7684 11:08:05.552129 Set Vref, RX VrefLevel [Byte0]: 53
7685 11:08:05.554690 [Byte1]: 53
7686 11:08:05.558345
7687 11:08:05.558857 Set Vref, RX VrefLevel [Byte0]: 54
7688 11:08:05.561772 [Byte1]: 54
7689 11:08:05.566475
7690 11:08:05.567050 Set Vref, RX VrefLevel [Byte0]: 55
7691 11:08:05.569456 [Byte1]: 55
7692 11:08:05.574682
7693 11:08:05.575239 Set Vref, RX VrefLevel [Byte0]: 56
7694 11:08:05.577168 [Byte1]: 56
7695 11:08:05.581389
7696 11:08:05.581845 Set Vref, RX VrefLevel [Byte0]: 57
7697 11:08:05.584863 [Byte1]: 57
7698 11:08:05.590373
7699 11:08:05.590927 Set Vref, RX VrefLevel [Byte0]: 58
7700 11:08:05.592395 [Byte1]: 58
7701 11:08:05.597467
7702 11:08:05.597923 Set Vref, RX VrefLevel [Byte0]: 59
7703 11:08:05.599816 [Byte1]: 59
7704 11:08:05.604537
7705 11:08:05.605153 Set Vref, RX VrefLevel [Byte0]: 60
7706 11:08:05.607505 [Byte1]: 60
7707 11:08:05.611966
7708 11:08:05.612556 Set Vref, RX VrefLevel [Byte0]: 61
7709 11:08:05.615296 [Byte1]: 61
7710 11:08:05.619435
7711 11:08:05.619988 Set Vref, RX VrefLevel [Byte0]: 62
7712 11:08:05.623668 [Byte1]: 62
7713 11:08:05.627419
7714 11:08:05.627995 Set Vref, RX VrefLevel [Byte0]: 63
7715 11:08:05.630398 [Byte1]: 63
7716 11:08:05.634639
7717 11:08:05.635141 Set Vref, RX VrefLevel [Byte0]: 64
7718 11:08:05.638300 [Byte1]: 64
7719 11:08:05.642678
7720 11:08:05.643238 Set Vref, RX VrefLevel [Byte0]: 65
7721 11:08:05.645906 [Byte1]: 65
7722 11:08:05.649935
7723 11:08:05.650494 Set Vref, RX VrefLevel [Byte0]: 66
7724 11:08:05.653508 [Byte1]: 66
7725 11:08:05.657904
7726 11:08:05.658459 Set Vref, RX VrefLevel [Byte0]: 67
7727 11:08:05.661064 [Byte1]: 67
7728 11:08:05.665189
7729 11:08:05.665737 Set Vref, RX VrefLevel [Byte0]: 68
7730 11:08:05.669579 [Byte1]: 68
7731 11:08:05.673296
7732 11:08:05.673914 Set Vref, RX VrefLevel [Byte0]: 69
7733 11:08:05.676029 [Byte1]: 69
7734 11:08:05.680430
7735 11:08:05.681018 Set Vref, RX VrefLevel [Byte0]: 70
7736 11:08:05.683634 [Byte1]: 70
7737 11:08:05.688271
7738 11:08:05.688868 Set Vref, RX VrefLevel [Byte0]: 71
7739 11:08:05.691569 [Byte1]: 71
7740 11:08:05.695607
7741 11:08:05.696160 Set Vref, RX VrefLevel [Byte0]: 72
7742 11:08:05.699077 [Byte1]: 72
7743 11:08:05.704074
7744 11:08:05.704629 Set Vref, RX VrefLevel [Byte0]: 73
7745 11:08:05.706457 [Byte1]: 73
7746 11:08:05.710897
7747 11:08:05.711354 Final RX Vref Byte 0 = 52 to rank0
7748 11:08:05.713920 Final RX Vref Byte 1 = 55 to rank0
7749 11:08:05.717101 Final RX Vref Byte 0 = 52 to rank1
7750 11:08:05.720855 Final RX Vref Byte 1 = 55 to rank1==
7751 11:08:05.723916 Dram Type= 6, Freq= 0, CH_0, rank 0
7752 11:08:05.732780 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7753 11:08:05.733346 ==
7754 11:08:05.733719 DQS Delay:
7755 11:08:05.734649 DQS0 = 0, DQS1 = 0
7756 11:08:05.735128 DQM Delay:
7757 11:08:05.735497 DQM0 = 126, DQM1 = 121
7758 11:08:05.737988 DQ Delay:
7759 11:08:05.740853 DQ0 =122, DQ1 =126, DQ2 =124, DQ3 =122
7760 11:08:05.744049 DQ4 =130, DQ5 =116, DQ6 =136, DQ7 =134
7761 11:08:05.747108 DQ8 =112, DQ9 =104, DQ10 =122, DQ11 =112
7762 11:08:05.750457 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7763 11:08:05.750920
7764 11:08:05.751291
7765 11:08:05.751630
7766 11:08:05.754013 [DramC_TX_OE_Calibration] TA2
7767 11:08:05.757249 Original DQ_B0 (3 6) =30, OEN = 27
7768 11:08:05.760673 Original DQ_B1 (3 6) =30, OEN = 27
7769 11:08:05.763830 24, 0x0, End_B0=24 End_B1=24
7770 11:08:05.766799 25, 0x0, End_B0=25 End_B1=25
7771 11:08:05.767359 26, 0x0, End_B0=26 End_B1=26
7772 11:08:05.770413 27, 0x0, End_B0=27 End_B1=27
7773 11:08:05.773766 28, 0x0, End_B0=28 End_B1=28
7774 11:08:05.776743 29, 0x0, End_B0=29 End_B1=29
7775 11:08:05.777218 30, 0x0, End_B0=30 End_B1=30
7776 11:08:05.780029 31, 0x4141, End_B0=30 End_B1=30
7777 11:08:05.783650 Byte0 end_step=30 best_step=27
7778 11:08:05.786895 Byte1 end_step=30 best_step=27
7779 11:08:05.790053 Byte0 TX OE(2T, 0.5T) = (3, 3)
7780 11:08:05.793373 Byte1 TX OE(2T, 0.5T) = (3, 3)
7781 11:08:05.794053
7782 11:08:05.794438
7783 11:08:05.799745 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
7784 11:08:05.803481 CH0 RK0: MR19=303, MR18=1717
7785 11:08:05.810182 CH0_RK0: MR19=0x303, MR18=0x1717, DQSOSC=398, MR23=63, INC=23, DEC=15
7786 11:08:05.810645
7787 11:08:05.813321 ----->DramcWriteLeveling(PI) begin...
7788 11:08:05.813801 ==
7789 11:08:05.817635 Dram Type= 6, Freq= 0, CH_0, rank 1
7790 11:08:05.819689 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7791 11:08:05.820147 ==
7792 11:08:05.823811 Write leveling (Byte 0): 31 => 31
7793 11:08:05.827007 Write leveling (Byte 1): 28 => 28
7794 11:08:05.829940 DramcWriteLeveling(PI) end<-----
7795 11:08:05.830500
7796 11:08:05.830869 ==
7797 11:08:05.833874 Dram Type= 6, Freq= 0, CH_0, rank 1
7798 11:08:05.837284 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7799 11:08:05.839448 ==
7800 11:08:05.840000 [Gating] SW mode calibration
7801 11:08:05.849445 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7802 11:08:05.852656 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7803 11:08:05.856652 0 12 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7804 11:08:05.862621 0 12 4 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7805 11:08:05.866948 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7806 11:08:05.869551 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7807 11:08:05.876542 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7808 11:08:05.879111 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7809 11:08:05.882569 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7810 11:08:05.889300 0 12 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7811 11:08:05.893032 0 13 0 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)
7812 11:08:05.895327 0 13 4 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
7813 11:08:05.902111 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7814 11:08:05.905629 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7815 11:08:05.909740 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7816 11:08:05.915084 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7817 11:08:05.918667 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7818 11:08:05.921647 0 13 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7819 11:08:05.928926 0 14 0 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7820 11:08:05.932386 0 14 4 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
7821 11:08:05.935285 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7822 11:08:05.942424 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7823 11:08:05.944891 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7824 11:08:05.949563 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7825 11:08:05.955809 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7826 11:08:05.959059 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7827 11:08:05.962374 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7828 11:08:05.968272 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7829 11:08:05.971901 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7830 11:08:05.975553 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7831 11:08:05.982489 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7832 11:08:05.985029 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7833 11:08:05.988916 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7834 11:08:05.995037 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7835 11:08:05.998307 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7836 11:08:06.001420 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7837 11:08:06.008296 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7838 11:08:06.011926 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7839 11:08:06.015012 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7840 11:08:06.021496 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7841 11:08:06.024402 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7842 11:08:06.028941 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7843 11:08:06.034307 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7844 11:08:06.037426 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7845 11:08:06.041458 Total UI for P1: 0, mck2ui 16
7846 11:08:06.044195 best dqsien dly found for B0: ( 1, 0, 30)
7847 11:08:06.047592 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7848 11:08:06.051287 Total UI for P1: 0, mck2ui 16
7849 11:08:06.054283 best dqsien dly found for B1: ( 1, 1, 2)
7850 11:08:06.057715 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7851 11:08:06.061380 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7852 11:08:06.062002
7853 11:08:06.064857 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7854 11:08:06.070897 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7855 11:08:06.071456 [Gating] SW calibration Done
7856 11:08:06.071830 ==
7857 11:08:06.074187 Dram Type= 6, Freq= 0, CH_0, rank 1
7858 11:08:06.080896 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7859 11:08:06.081428 ==
7860 11:08:06.081799 RX Vref Scan: 0
7861 11:08:06.082146
7862 11:08:06.084168 RX Vref 0 -> 0, step: 1
7863 11:08:06.084622
7864 11:08:06.088038 RX Delay 0 -> 252, step: 8
7865 11:08:06.091119 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7866 11:08:06.094657 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7867 11:08:06.097636 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7868 11:08:06.105178 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7869 11:08:06.107520 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7870 11:08:06.110920 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7871 11:08:06.114090 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7872 11:08:06.117367 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7873 11:08:06.124371 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7874 11:08:06.127557 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7875 11:08:06.131311 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7876 11:08:06.134411 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7877 11:08:06.137022 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7878 11:08:06.144323 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7879 11:08:06.147616 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7880 11:08:06.150170 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7881 11:08:06.150632 ==
7882 11:08:06.153882 Dram Type= 6, Freq= 0, CH_0, rank 1
7883 11:08:06.157101 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7884 11:08:06.157660 ==
7885 11:08:06.160154 DQS Delay:
7886 11:08:06.160742 DQS0 = 0, DQS1 = 0
7887 11:08:06.163992 DQM Delay:
7888 11:08:06.164450 DQM0 = 131, DQM1 = 124
7889 11:08:06.166660 DQ Delay:
7890 11:08:06.170612 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7891 11:08:06.173437 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =143
7892 11:08:06.177082 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7893 11:08:06.180090 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7894 11:08:06.180784
7895 11:08:06.181326
7896 11:08:06.181690 ==
7897 11:08:06.185027 Dram Type= 6, Freq= 0, CH_0, rank 1
7898 11:08:06.186968 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7899 11:08:06.187528 ==
7900 11:08:06.187896
7901 11:08:06.189650
7902 11:08:06.190105 TX Vref Scan disable
7903 11:08:06.193934 == TX Byte 0 ==
7904 11:08:06.196538 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7905 11:08:06.199784 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7906 11:08:06.203243 == TX Byte 1 ==
7907 11:08:06.206341 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7908 11:08:06.209394 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7909 11:08:06.209945 ==
7910 11:08:06.213591 Dram Type= 6, Freq= 0, CH_0, rank 1
7911 11:08:06.219765 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7912 11:08:06.220329 ==
7913 11:08:06.233400
7914 11:08:06.235789 TX Vref early break, caculate TX vref
7915 11:08:06.239613 TX Vref=16, minBit 1, minWin=21, winSum=375
7916 11:08:06.243187 TX Vref=18, minBit 1, minWin=22, winSum=385
7917 11:08:06.245412 TX Vref=20, minBit 1, minWin=24, winSum=399
7918 11:08:06.249177 TX Vref=22, minBit 1, minWin=24, winSum=403
7919 11:08:06.252651 TX Vref=24, minBit 1, minWin=23, winSum=407
7920 11:08:06.259467 TX Vref=26, minBit 1, minWin=25, winSum=414
7921 11:08:06.262451 TX Vref=28, minBit 8, minWin=25, winSum=421
7922 11:08:06.265415 TX Vref=30, minBit 1, minWin=25, winSum=416
7923 11:08:06.268869 TX Vref=32, minBit 0, minWin=24, winSum=407
7924 11:08:06.274709 TX Vref=34, minBit 7, minWin=23, winSum=400
7925 11:08:06.278635 TX Vref=36, minBit 1, minWin=23, winSum=391
7926 11:08:06.282028 [TxChooseVref] Worse bit 8, Min win 25, Win sum 421, Final Vref 28
7927 11:08:06.282494
7928 11:08:06.285500 Final TX Range 0 Vref 28
7929 11:08:06.286069
7930 11:08:06.286441 ==
7931 11:08:06.288394 Dram Type= 6, Freq= 0, CH_0, rank 1
7932 11:08:06.291742 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7933 11:08:06.294886 ==
7934 11:08:06.295456
7935 11:08:06.296014
7936 11:08:06.296392 TX Vref Scan disable
7937 11:08:06.301754 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7938 11:08:06.302218 == TX Byte 0 ==
7939 11:08:06.305047 u2DelayCellOfst[0]=14 cells (4 PI)
7940 11:08:06.308406 u2DelayCellOfst[1]=18 cells (5 PI)
7941 11:08:06.311631 u2DelayCellOfst[2]=14 cells (4 PI)
7942 11:08:06.315439 u2DelayCellOfst[3]=14 cells (4 PI)
7943 11:08:06.318388 u2DelayCellOfst[4]=10 cells (3 PI)
7944 11:08:06.321456 u2DelayCellOfst[5]=0 cells (0 PI)
7945 11:08:06.324885 u2DelayCellOfst[6]=21 cells (6 PI)
7946 11:08:06.328077 u2DelayCellOfst[7]=21 cells (6 PI)
7947 11:08:06.332153 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7948 11:08:06.335163 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7949 11:08:06.338335 == TX Byte 1 ==
7950 11:08:06.341413 u2DelayCellOfst[8]=3 cells (1 PI)
7951 11:08:06.345264 u2DelayCellOfst[9]=0 cells (0 PI)
7952 11:08:06.347973 u2DelayCellOfst[10]=10 cells (3 PI)
7953 11:08:06.351306 u2DelayCellOfst[11]=7 cells (2 PI)
7954 11:08:06.355061 u2DelayCellOfst[12]=14 cells (4 PI)
7955 11:08:06.358769 u2DelayCellOfst[13]=14 cells (4 PI)
7956 11:08:06.361317 u2DelayCellOfst[14]=18 cells (5 PI)
7957 11:08:06.361779 u2DelayCellOfst[15]=14 cells (4 PI)
7958 11:08:06.368368 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7959 11:08:06.371363 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7960 11:08:06.374563 DramC Write-DBI on
7961 11:08:06.375142 ==
7962 11:08:06.378557 Dram Type= 6, Freq= 0, CH_0, rank 1
7963 11:08:06.381281 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7964 11:08:06.381746 ==
7965 11:08:06.382117
7966 11:08:06.382456
7967 11:08:06.384806 TX Vref Scan disable
7968 11:08:06.385360 == TX Byte 0 ==
7969 11:08:06.391410 Update DQM dly =731 (2 ,6, 27) DQM OEN =(3 ,3)
7970 11:08:06.391970 == TX Byte 1 ==
7971 11:08:06.394430 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7972 11:08:06.397919 DramC Write-DBI off
7973 11:08:06.398381
7974 11:08:06.398750 [DATLAT]
7975 11:08:06.400650 Freq=1600, CH0 RK1
7976 11:08:06.401143
7977 11:08:06.401515 DATLAT Default: 0xe
7978 11:08:06.404310 0, 0xFFFF, sum = 0
7979 11:08:06.404929 1, 0xFFFF, sum = 0
7980 11:08:06.408057 2, 0xFFFF, sum = 0
7981 11:08:06.410708 3, 0xFFFF, sum = 0
7982 11:08:06.411176 4, 0xFFFF, sum = 0
7983 11:08:06.414684 5, 0xFFFF, sum = 0
7984 11:08:06.415257 6, 0xFFFF, sum = 0
7985 11:08:06.417323 7, 0xFFFF, sum = 0
7986 11:08:06.417922 8, 0xFFFF, sum = 0
7987 11:08:06.420994 9, 0xFFFF, sum = 0
7988 11:08:06.421481 10, 0xFFFF, sum = 0
7989 11:08:06.424868 11, 0xFFFF, sum = 0
7990 11:08:06.425447 12, 0x8FFF, sum = 0
7991 11:08:06.428142 13, 0x0, sum = 1
7992 11:08:06.428758 14, 0x0, sum = 2
7993 11:08:06.431287 15, 0x0, sum = 3
7994 11:08:06.431854 16, 0x0, sum = 4
7995 11:08:06.434552 best_step = 14
7996 11:08:06.435114
7997 11:08:06.435484 ==
7998 11:08:06.437294 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 11:08:06.441388 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8000 11:08:06.441859 ==
8001 11:08:06.442233 RX Vref Scan: 0
8002 11:08:06.444032
8003 11:08:06.444495 RX Vref 0 -> 0, step: 1
8004 11:08:06.444926
8005 11:08:06.447414 RX Delay 11 -> 252, step: 4
8006 11:08:06.450724 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
8007 11:08:06.457620 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8008 11:08:06.460471 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
8009 11:08:06.463792 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8010 11:08:06.467648 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8011 11:08:06.470715 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8012 11:08:06.477294 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8013 11:08:06.481076 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
8014 11:08:06.483887 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
8015 11:08:06.487176 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
8016 11:08:06.490432 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8017 11:08:06.497173 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8018 11:08:06.500019 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8019 11:08:06.503573 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8020 11:08:06.506740 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8021 11:08:06.513292 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8022 11:08:06.513753 ==
8023 11:08:06.517792 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 11:08:06.519946 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8025 11:08:06.520413 ==
8026 11:08:06.520837 DQS Delay:
8027 11:08:06.523081 DQS0 = 0, DQS1 = 0
8028 11:08:06.523541 DQM Delay:
8029 11:08:06.526554 DQM0 = 128, DQM1 = 120
8030 11:08:06.527013 DQ Delay:
8031 11:08:06.530006 DQ0 =122, DQ1 =130, DQ2 =126, DQ3 =124
8032 11:08:06.534775 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =138
8033 11:08:06.536613 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
8034 11:08:06.540112 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
8035 11:08:06.540671
8036 11:08:06.541088
8037 11:08:06.541428
8038 11:08:06.543878 [DramC_TX_OE_Calibration] TA2
8039 11:08:06.547105 Original DQ_B0 (3 6) =30, OEN = 27
8040 11:08:06.549627 Original DQ_B1 (3 6) =30, OEN = 27
8041 11:08:06.553449 24, 0x0, End_B0=24 End_B1=24
8042 11:08:06.557049 25, 0x0, End_B0=25 End_B1=25
8043 11:08:06.560051 26, 0x0, End_B0=26 End_B1=26
8044 11:08:06.560516 27, 0x0, End_B0=27 End_B1=27
8045 11:08:06.563164 28, 0x0, End_B0=28 End_B1=28
8046 11:08:06.566829 29, 0x0, End_B0=29 End_B1=29
8047 11:08:06.569744 30, 0x0, End_B0=30 End_B1=30
8048 11:08:06.573352 31, 0x4141, End_B0=30 End_B1=30
8049 11:08:06.573917 Byte0 end_step=30 best_step=27
8050 11:08:06.576980 Byte1 end_step=30 best_step=27
8051 11:08:06.579830 Byte0 TX OE(2T, 0.5T) = (3, 3)
8052 11:08:06.582950 Byte1 TX OE(2T, 0.5T) = (3, 3)
8053 11:08:06.583506
8054 11:08:06.583876
8055 11:08:06.590239 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8056 11:08:06.592945 CH0 RK1: MR19=303, MR18=1E1E
8057 11:08:06.599954 CH0_RK1: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
8058 11:08:06.602782 [RxdqsGatingPostProcess] freq 1600
8059 11:08:06.609635 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8060 11:08:06.612632 Pre-setting of DQS Precalculation
8061 11:08:06.616086 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8062 11:08:06.616647 ==
8063 11:08:06.619141 Dram Type= 6, Freq= 0, CH_1, rank 0
8064 11:08:06.622730 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8065 11:08:06.625638 ==
8066 11:08:06.629590 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8067 11:08:06.632561 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8068 11:08:06.639067 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8069 11:08:06.642304 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8070 11:08:06.652890 [CA 0] Center 41 (11~72) winsize 62
8071 11:08:06.655607 [CA 1] Center 41 (11~72) winsize 62
8072 11:08:06.658769 [CA 2] Center 37 (8~67) winsize 60
8073 11:08:06.661844 [CA 3] Center 36 (7~66) winsize 60
8074 11:08:06.664927 [CA 4] Center 34 (5~64) winsize 60
8075 11:08:06.668571 [CA 5] Center 34 (4~64) winsize 61
8076 11:08:06.669068
8077 11:08:06.671937 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8078 11:08:06.672399
8079 11:08:06.675568 [CATrainingPosCal] consider 1 rank data
8080 11:08:06.678683 u2DelayCellTimex100 = 271/100 ps
8081 11:08:06.684874 CA0 delay=41 (11~72),Diff = 7 PI (25 cell)
8082 11:08:06.688515 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
8083 11:08:06.692281 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8084 11:08:06.696603 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8085 11:08:06.698865 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
8086 11:08:06.702725 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8087 11:08:06.703280
8088 11:08:06.705113 CA PerBit enable=1, Macro0, CA PI delay=34
8089 11:08:06.705574
8090 11:08:06.708184 [CBTSetCACLKResult] CA Dly = 34
8091 11:08:06.711301 CS Dly: 8 (0~39)
8092 11:08:06.715258 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8093 11:08:06.718159 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8094 11:08:06.718626 ==
8095 11:08:06.721757 Dram Type= 6, Freq= 0, CH_1, rank 1
8096 11:08:06.725450 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8097 11:08:06.728422 ==
8098 11:08:06.732594 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8099 11:08:06.735102 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8100 11:08:06.741992 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8101 11:08:06.747823 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8102 11:08:06.754416 [CA 0] Center 40 (10~70) winsize 61
8103 11:08:06.757950 [CA 1] Center 39 (9~70) winsize 62
8104 11:08:06.761111 [CA 2] Center 35 (6~65) winsize 60
8105 11:08:06.764156 [CA 3] Center 35 (6~65) winsize 60
8106 11:08:06.767984 [CA 4] Center 33 (4~63) winsize 60
8107 11:08:06.770933 [CA 5] Center 33 (3~63) winsize 61
8108 11:08:06.771503
8109 11:08:06.774387 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8110 11:08:06.774861
8111 11:08:06.777531 [CATrainingPosCal] consider 2 rank data
8112 11:08:06.780674 u2DelayCellTimex100 = 271/100 ps
8113 11:08:06.784787 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8114 11:08:06.790729 CA1 delay=40 (11~70),Diff = 7 PI (25 cell)
8115 11:08:06.795060 CA2 delay=36 (8~65),Diff = 3 PI (10 cell)
8116 11:08:06.797683 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8117 11:08:06.801741 CA4 delay=34 (5~63),Diff = 1 PI (3 cell)
8118 11:08:06.804547 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8119 11:08:06.805035
8120 11:08:06.807357 CA PerBit enable=1, Macro0, CA PI delay=33
8121 11:08:06.807916
8122 11:08:06.810231 [CBTSetCACLKResult] CA Dly = 33
8123 11:08:06.814099 CS Dly: 9 (0~41)
8124 11:08:06.817689 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8125 11:08:06.820796 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8126 11:08:06.821260
8127 11:08:06.824016 ----->DramcWriteLeveling(PI) begin...
8128 11:08:06.824476 ==
8129 11:08:06.826854 Dram Type= 6, Freq= 0, CH_1, rank 0
8130 11:08:06.833612 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8131 11:08:06.834161 ==
8132 11:08:06.836920 Write leveling (Byte 0): 24 => 24
8133 11:08:06.840366 Write leveling (Byte 1): 22 => 22
8134 11:08:06.840999 DramcWriteLeveling(PI) end<-----
8135 11:08:06.841497
8136 11:08:06.844039 ==
8137 11:08:06.846943 Dram Type= 6, Freq= 0, CH_1, rank 0
8138 11:08:06.851404 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8139 11:08:06.851980 ==
8140 11:08:06.853888 [Gating] SW mode calibration
8141 11:08:06.860008 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8142 11:08:06.863412 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8143 11:08:06.869629 0 12 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
8144 11:08:06.874197 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8145 11:08:06.876406 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8146 11:08:06.883163 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8147 11:08:06.886582 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8148 11:08:06.889753 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8149 11:08:06.896243 0 12 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8150 11:08:06.900010 0 12 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8151 11:08:06.903310 0 13 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
8152 11:08:06.909483 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8153 11:08:06.913314 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8154 11:08:06.916240 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8155 11:08:06.922857 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8156 11:08:06.926513 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8157 11:08:06.930524 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8158 11:08:06.936578 0 13 28 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8159 11:08:06.939490 0 14 0 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
8160 11:08:06.943031 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8161 11:08:06.949221 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8162 11:08:06.953151 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8163 11:08:06.956451 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8164 11:08:06.963482 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8165 11:08:06.966078 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8166 11:08:06.969203 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8167 11:08:06.975843 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8168 11:08:06.979585 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8169 11:08:06.982740 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8170 11:08:06.990587 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8171 11:08:06.993650 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8172 11:08:06.995840 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8173 11:08:07.002159 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8174 11:08:07.006006 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8175 11:08:07.009568 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8176 11:08:07.016247 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8177 11:08:07.019181 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8178 11:08:07.022014 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8179 11:08:07.029088 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8180 11:08:07.031991 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8181 11:08:07.035316 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8182 11:08:07.042377 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8183 11:08:07.047473 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8184 11:08:07.048701 Total UI for P1: 0, mck2ui 16
8185 11:08:07.052162 best dqsien dly found for B0: ( 1, 0, 26)
8186 11:08:07.055804 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8187 11:08:07.059039 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8188 11:08:07.063065 Total UI for P1: 0, mck2ui 16
8189 11:08:07.065036 best dqsien dly found for B1: ( 1, 1, 2)
8190 11:08:07.072132 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8191 11:08:07.074996 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8192 11:08:07.075570
8193 11:08:07.078678 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8194 11:08:07.081428 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8195 11:08:07.085146 [Gating] SW calibration Done
8196 11:08:07.085784 ==
8197 11:08:07.089081 Dram Type= 6, Freq= 0, CH_1, rank 0
8198 11:08:07.091661 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8199 11:08:07.092218 ==
8200 11:08:07.095511 RX Vref Scan: 0
8201 11:08:07.096068
8202 11:08:07.096435 RX Vref 0 -> 0, step: 1
8203 11:08:07.096830
8204 11:08:07.097846 RX Delay 0 -> 252, step: 8
8205 11:08:07.101435 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8206 11:08:07.105498 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8207 11:08:07.111734 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8208 11:08:07.115106 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8209 11:08:07.118268 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8210 11:08:07.121817 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8211 11:08:07.124601 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8212 11:08:07.132119 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8213 11:08:07.135031 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8214 11:08:07.138152 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8215 11:08:07.141304 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8216 11:08:07.144653 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8217 11:08:07.150954 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8218 11:08:07.154961 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8219 11:08:07.158334 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8220 11:08:07.161540 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8221 11:08:07.162000 ==
8222 11:08:07.164240 Dram Type= 6, Freq= 0, CH_1, rank 0
8223 11:08:07.171208 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8224 11:08:07.171774 ==
8225 11:08:07.172145 DQS Delay:
8226 11:08:07.174761 DQS0 = 0, DQS1 = 0
8227 11:08:07.175323 DQM Delay:
8228 11:08:07.177796 DQM0 = 130, DQM1 = 125
8229 11:08:07.178255 DQ Delay:
8230 11:08:07.180816 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8231 11:08:07.184258 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8232 11:08:07.187924 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8233 11:08:07.190796 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8234 11:08:07.191360
8235 11:08:07.191725
8236 11:08:07.192062 ==
8237 11:08:07.194165 Dram Type= 6, Freq= 0, CH_1, rank 0
8238 11:08:07.201296 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8239 11:08:07.201859 ==
8240 11:08:07.202231
8241 11:08:07.202568
8242 11:08:07.202892 TX Vref Scan disable
8243 11:08:07.205010 == TX Byte 0 ==
8244 11:08:07.209001 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8245 11:08:07.213851 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8246 11:08:07.214313 == TX Byte 1 ==
8247 11:08:07.218134 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8248 11:08:07.223948 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8249 11:08:07.224411 ==
8250 11:08:07.227002 Dram Type= 6, Freq= 0, CH_1, rank 0
8251 11:08:07.230437 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8252 11:08:07.231018 ==
8253 11:08:07.244068
8254 11:08:07.246913 TX Vref early break, caculate TX vref
8255 11:08:07.251021 TX Vref=16, minBit 3, minWin=21, winSum=368
8256 11:08:07.253721 TX Vref=18, minBit 0, minWin=22, winSum=376
8257 11:08:07.257023 TX Vref=20, minBit 0, minWin=23, winSum=389
8258 11:08:07.260256 TX Vref=22, minBit 0, minWin=24, winSum=394
8259 11:08:07.263740 TX Vref=24, minBit 0, minWin=24, winSum=406
8260 11:08:07.270475 TX Vref=26, minBit 0, minWin=25, winSum=414
8261 11:08:07.273837 TX Vref=28, minBit 3, minWin=25, winSum=412
8262 11:08:07.277702 TX Vref=30, minBit 1, minWin=24, winSum=409
8263 11:08:07.280086 TX Vref=32, minBit 0, minWin=24, winSum=400
8264 11:08:07.283441 TX Vref=34, minBit 0, minWin=24, winSum=393
8265 11:08:07.287042 TX Vref=36, minBit 0, minWin=22, winSum=383
8266 11:08:07.293331 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 26
8267 11:08:07.293899
8268 11:08:07.296462 Final TX Range 0 Vref 26
8269 11:08:07.297176
8270 11:08:07.297557 ==
8271 11:08:07.299863 Dram Type= 6, Freq= 0, CH_1, rank 0
8272 11:08:07.303840 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8273 11:08:07.304407 ==
8274 11:08:07.306474
8275 11:08:07.306929
8276 11:08:07.307294 TX Vref Scan disable
8277 11:08:07.313220 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8278 11:08:07.313769 == TX Byte 0 ==
8279 11:08:07.316582 u2DelayCellOfst[0]=18 cells (5 PI)
8280 11:08:07.319789 u2DelayCellOfst[1]=10 cells (3 PI)
8281 11:08:07.322717 u2DelayCellOfst[2]=0 cells (0 PI)
8282 11:08:07.326254 u2DelayCellOfst[3]=7 cells (2 PI)
8283 11:08:07.329487 u2DelayCellOfst[4]=7 cells (2 PI)
8284 11:08:07.333005 u2DelayCellOfst[5]=14 cells (4 PI)
8285 11:08:07.336764 u2DelayCellOfst[6]=14 cells (4 PI)
8286 11:08:07.340226 u2DelayCellOfst[7]=7 cells (2 PI)
8287 11:08:07.342905 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8288 11:08:07.347140 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8289 11:08:07.349336 == TX Byte 1 ==
8290 11:08:07.352367 u2DelayCellOfst[8]=0 cells (0 PI)
8291 11:08:07.356627 u2DelayCellOfst[9]=3 cells (1 PI)
8292 11:08:07.359216 u2DelayCellOfst[10]=7 cells (2 PI)
8293 11:08:07.362467 u2DelayCellOfst[11]=0 cells (0 PI)
8294 11:08:07.362929 u2DelayCellOfst[12]=14 cells (4 PI)
8295 11:08:07.365772 u2DelayCellOfst[13]=18 cells (5 PI)
8296 11:08:07.369027 u2DelayCellOfst[14]=18 cells (5 PI)
8297 11:08:07.372390 u2DelayCellOfst[15]=18 cells (5 PI)
8298 11:08:07.379499 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8299 11:08:07.382231 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8300 11:08:07.382709 DramC Write-DBI on
8301 11:08:07.385950 ==
8302 11:08:07.389150 Dram Type= 6, Freq= 0, CH_1, rank 0
8303 11:08:07.392643 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8304 11:08:07.393259 ==
8305 11:08:07.393630
8306 11:08:07.393971
8307 11:08:07.395297 TX Vref Scan disable
8308 11:08:07.395695 == TX Byte 0 ==
8309 11:08:07.402669 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8310 11:08:07.403231 == TX Byte 1 ==
8311 11:08:07.405749 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8312 11:08:07.409122 DramC Write-DBI off
8313 11:08:07.409683
8314 11:08:07.410129 [DATLAT]
8315 11:08:07.412425 Freq=1600, CH1 RK0
8316 11:08:07.412932
8317 11:08:07.413305 DATLAT Default: 0xf
8318 11:08:07.415387 0, 0xFFFF, sum = 0
8319 11:08:07.415851 1, 0xFFFF, sum = 0
8320 11:08:07.418920 2, 0xFFFF, sum = 0
8321 11:08:07.419485 3, 0xFFFF, sum = 0
8322 11:08:07.422024 4, 0xFFFF, sum = 0
8323 11:08:07.422683 5, 0xFFFF, sum = 0
8324 11:08:07.425285 6, 0xFFFF, sum = 0
8325 11:08:07.425751 7, 0xFFFF, sum = 0
8326 11:08:07.428815 8, 0xFFFF, sum = 0
8327 11:08:07.432053 9, 0xFFFF, sum = 0
8328 11:08:07.432521 10, 0xFFFF, sum = 0
8329 11:08:07.435130 11, 0xFFFF, sum = 0
8330 11:08:07.435597 12, 0x8FFF, sum = 0
8331 11:08:07.438855 13, 0x0, sum = 1
8332 11:08:07.439420 14, 0x0, sum = 2
8333 11:08:07.442771 15, 0x0, sum = 3
8334 11:08:07.443340 16, 0x0, sum = 4
8335 11:08:07.443720 best_step = 14
8336 11:08:07.445063
8337 11:08:07.445532 ==
8338 11:08:07.449154 Dram Type= 6, Freq= 0, CH_1, rank 0
8339 11:08:07.451296 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8340 11:08:07.451782 ==
8341 11:08:07.452149 RX Vref Scan: 1
8342 11:08:07.452490
8343 11:08:07.455427 Set Vref Range= 24 -> 127
8344 11:08:07.455989
8345 11:08:07.458818 RX Vref 24 -> 127, step: 1
8346 11:08:07.459382
8347 11:08:07.462127 RX Delay 3 -> 252, step: 4
8348 11:08:07.462698
8349 11:08:07.464849 Set Vref, RX VrefLevel [Byte0]: 24
8350 11:08:07.468910 [Byte1]: 24
8351 11:08:07.469474
8352 11:08:07.471467 Set Vref, RX VrefLevel [Byte0]: 25
8353 11:08:07.475233 [Byte1]: 25
8354 11:08:07.475793
8355 11:08:07.477899 Set Vref, RX VrefLevel [Byte0]: 26
8356 11:08:07.481095 [Byte1]: 26
8357 11:08:07.485513
8358 11:08:07.485970 Set Vref, RX VrefLevel [Byte0]: 27
8359 11:08:07.488408 [Byte1]: 27
8360 11:08:07.493047
8361 11:08:07.493635 Set Vref, RX VrefLevel [Byte0]: 28
8362 11:08:07.496088 [Byte1]: 28
8363 11:08:07.500740
8364 11:08:07.501196 Set Vref, RX VrefLevel [Byte0]: 29
8365 11:08:07.504246 [Byte1]: 29
8366 11:08:07.507966
8367 11:08:07.511261 Set Vref, RX VrefLevel [Byte0]: 30
8368 11:08:07.515678 [Byte1]: 30
8369 11:08:07.516232
8370 11:08:07.518666 Set Vref, RX VrefLevel [Byte0]: 31
8371 11:08:07.521997 [Byte1]: 31
8372 11:08:07.522571
8373 11:08:07.524854 Set Vref, RX VrefLevel [Byte0]: 32
8374 11:08:07.527919 [Byte1]: 32
8375 11:08:07.531677
8376 11:08:07.532232 Set Vref, RX VrefLevel [Byte0]: 33
8377 11:08:07.534364 [Byte1]: 33
8378 11:08:07.539059
8379 11:08:07.539611 Set Vref, RX VrefLevel [Byte0]: 34
8380 11:08:07.541954 [Byte1]: 34
8381 11:08:07.546498
8382 11:08:07.546948 Set Vref, RX VrefLevel [Byte0]: 35
8383 11:08:07.549576 [Byte1]: 35
8384 11:08:07.554723
8385 11:08:07.555274 Set Vref, RX VrefLevel [Byte0]: 36
8386 11:08:07.557239 [Byte1]: 36
8387 11:08:07.562207
8388 11:08:07.562764 Set Vref, RX VrefLevel [Byte0]: 37
8389 11:08:07.565392 [Byte1]: 37
8390 11:08:07.570311
8391 11:08:07.570859 Set Vref, RX VrefLevel [Byte0]: 38
8392 11:08:07.573103 [Byte1]: 38
8393 11:08:07.577367
8394 11:08:07.578132 Set Vref, RX VrefLevel [Byte0]: 39
8395 11:08:07.580523 [Byte1]: 39
8396 11:08:07.585050
8397 11:08:07.585497 Set Vref, RX VrefLevel [Byte0]: 40
8398 11:08:07.588497 [Byte1]: 40
8399 11:08:07.593116
8400 11:08:07.593664 Set Vref, RX VrefLevel [Byte0]: 41
8401 11:08:07.596128 [Byte1]: 41
8402 11:08:07.600514
8403 11:08:07.601110 Set Vref, RX VrefLevel [Byte0]: 42
8404 11:08:07.604068 [Byte1]: 42
8405 11:08:07.607642
8406 11:08:07.608216 Set Vref, RX VrefLevel [Byte0]: 43
8407 11:08:07.611260 [Byte1]: 43
8408 11:08:07.615667
8409 11:08:07.616228 Set Vref, RX VrefLevel [Byte0]: 44
8410 11:08:07.619810 [Byte1]: 44
8411 11:08:07.623179
8412 11:08:07.623748 Set Vref, RX VrefLevel [Byte0]: 45
8413 11:08:07.626763 [Byte1]: 45
8414 11:08:07.630712
8415 11:08:07.631257 Set Vref, RX VrefLevel [Byte0]: 46
8416 11:08:07.634280 [Byte1]: 46
8417 11:08:07.638582
8418 11:08:07.639147 Set Vref, RX VrefLevel [Byte0]: 47
8419 11:08:07.641345 [Byte1]: 47
8420 11:08:07.646243
8421 11:08:07.646787 Set Vref, RX VrefLevel [Byte0]: 48
8422 11:08:07.649165 [Byte1]: 48
8423 11:08:07.653580
8424 11:08:07.654124 Set Vref, RX VrefLevel [Byte0]: 49
8425 11:08:07.657407 [Byte1]: 49
8426 11:08:07.661652
8427 11:08:07.662198 Set Vref, RX VrefLevel [Byte0]: 50
8428 11:08:07.665431 [Byte1]: 50
8429 11:08:07.669071
8430 11:08:07.669618 Set Vref, RX VrefLevel [Byte0]: 51
8431 11:08:07.672386 [Byte1]: 51
8432 11:08:07.676964
8433 11:08:07.677504 Set Vref, RX VrefLevel [Byte0]: 52
8434 11:08:07.681427 [Byte1]: 52
8435 11:08:07.684280
8436 11:08:07.684795 Set Vref, RX VrefLevel [Byte0]: 53
8437 11:08:07.687744 [Byte1]: 53
8438 11:08:07.692293
8439 11:08:07.692889 Set Vref, RX VrefLevel [Byte0]: 54
8440 11:08:07.695086 [Byte1]: 54
8441 11:08:07.699462
8442 11:08:07.700008 Set Vref, RX VrefLevel [Byte0]: 55
8443 11:08:07.702758 [Byte1]: 55
8444 11:08:07.707455
8445 11:08:07.707989 Set Vref, RX VrefLevel [Byte0]: 56
8446 11:08:07.710754 [Byte1]: 56
8447 11:08:07.715102
8448 11:08:07.715647 Set Vref, RX VrefLevel [Byte0]: 57
8449 11:08:07.718403 [Byte1]: 57
8450 11:08:07.723017
8451 11:08:07.723469 Set Vref, RX VrefLevel [Byte0]: 58
8452 11:08:07.725957 [Byte1]: 58
8453 11:08:07.730378
8454 11:08:07.730933 Set Vref, RX VrefLevel [Byte0]: 59
8455 11:08:07.733336 [Byte1]: 59
8456 11:08:07.738115
8457 11:08:07.738668 Set Vref, RX VrefLevel [Byte0]: 60
8458 11:08:07.740917 [Byte1]: 60
8459 11:08:07.746144
8460 11:08:07.746694 Set Vref, RX VrefLevel [Byte0]: 61
8461 11:08:07.749165 [Byte1]: 61
8462 11:08:07.753346
8463 11:08:07.753943 Set Vref, RX VrefLevel [Byte0]: 62
8464 11:08:07.756171 [Byte1]: 62
8465 11:08:07.760973
8466 11:08:07.761530 Set Vref, RX VrefLevel [Byte0]: 63
8467 11:08:07.764492 [Byte1]: 63
8468 11:08:07.768642
8469 11:08:07.769242 Set Vref, RX VrefLevel [Byte0]: 64
8470 11:08:07.772030 [Byte1]: 64
8471 11:08:07.776054
8472 11:08:07.776627 Set Vref, RX VrefLevel [Byte0]: 65
8473 11:08:07.780091 [Byte1]: 65
8474 11:08:07.784005
8475 11:08:07.784564 Set Vref, RX VrefLevel [Byte0]: 66
8476 11:08:07.787797 [Byte1]: 66
8477 11:08:07.791802
8478 11:08:07.792356 Set Vref, RX VrefLevel [Byte0]: 67
8479 11:08:07.794912 [Byte1]: 67
8480 11:08:07.799828
8481 11:08:07.800382 Set Vref, RX VrefLevel [Byte0]: 68
8482 11:08:07.802190 [Byte1]: 68
8483 11:08:07.806648
8484 11:08:07.807203 Set Vref, RX VrefLevel [Byte0]: 69
8485 11:08:07.809987 [Byte1]: 69
8486 11:08:07.814080
8487 11:08:07.814530 Set Vref, RX VrefLevel [Byte0]: 70
8488 11:08:07.817840 [Byte1]: 70
8489 11:08:07.821803
8490 11:08:07.822264 Set Vref, RX VrefLevel [Byte0]: 71
8491 11:08:07.824953 [Byte1]: 71
8492 11:08:07.830293
8493 11:08:07.830747 Set Vref, RX VrefLevel [Byte0]: 72
8494 11:08:07.834043 [Byte1]: 72
8495 11:08:07.837636
8496 11:08:07.838198 Set Vref, RX VrefLevel [Byte0]: 73
8497 11:08:07.840842 [Byte1]: 73
8498 11:08:07.845693
8499 11:08:07.846253 Set Vref, RX VrefLevel [Byte0]: 74
8500 11:08:07.849640 [Byte1]: 74
8501 11:08:07.853704
8502 11:08:07.854265 Set Vref, RX VrefLevel [Byte0]: 75
8503 11:08:07.856623 [Byte1]: 75
8504 11:08:07.860168
8505 11:08:07.860763 Set Vref, RX VrefLevel [Byte0]: 76
8506 11:08:07.864017 [Byte1]: 76
8507 11:08:07.867798
8508 11:08:07.868282 Final RX Vref Byte 0 = 57 to rank0
8509 11:08:07.870945 Final RX Vref Byte 1 = 56 to rank0
8510 11:08:07.875089 Final RX Vref Byte 0 = 57 to rank1
8511 11:08:07.877927 Final RX Vref Byte 1 = 56 to rank1==
8512 11:08:07.881354 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 11:08:07.887923 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8514 11:08:07.888491 ==
8515 11:08:07.888908 DQS Delay:
8516 11:08:07.892089 DQS0 = 0, DQS1 = 0
8517 11:08:07.892645 DQM Delay:
8518 11:08:07.893063 DQM0 = 128, DQM1 = 123
8519 11:08:07.894352 DQ Delay:
8520 11:08:07.897765 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =128
8521 11:08:07.901078 DQ4 =128, DQ5 =140, DQ6 =136, DQ7 =124
8522 11:08:07.905239 DQ8 =104, DQ9 =112, DQ10 =124, DQ11 =112
8523 11:08:07.908812 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =132
8524 11:08:07.909381
8525 11:08:07.909748
8526 11:08:07.910107
8527 11:08:07.911383 [DramC_TX_OE_Calibration] TA2
8528 11:08:07.914357 Original DQ_B0 (3 6) =30, OEN = 27
8529 11:08:07.917955 Original DQ_B1 (3 6) =30, OEN = 27
8530 11:08:07.921214 24, 0x0, End_B0=24 End_B1=24
8531 11:08:07.921784 25, 0x0, End_B0=25 End_B1=25
8532 11:08:07.925189 26, 0x0, End_B0=26 End_B1=26
8533 11:08:07.927408 27, 0x0, End_B0=27 End_B1=27
8534 11:08:07.930688 28, 0x0, End_B0=28 End_B1=28
8535 11:08:07.933871 29, 0x0, End_B0=29 End_B1=29
8536 11:08:07.934460 30, 0x0, End_B0=30 End_B1=30
8537 11:08:07.937747 31, 0x4141, End_B0=30 End_B1=30
8538 11:08:07.941335 Byte0 end_step=30 best_step=27
8539 11:08:07.944209 Byte1 end_step=30 best_step=27
8540 11:08:07.947477 Byte0 TX OE(2T, 0.5T) = (3, 3)
8541 11:08:07.951098 Byte1 TX OE(2T, 0.5T) = (3, 3)
8542 11:08:07.951560
8543 11:08:07.951921
8544 11:08:07.957827 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8545 11:08:07.961009 CH1 RK0: MR19=303, MR18=2424
8546 11:08:07.967788 CH1_RK0: MR19=0x303, MR18=0x2424, DQSOSC=391, MR23=63, INC=24, DEC=16
8547 11:08:07.968339
8548 11:08:07.970438 ----->DramcWriteLeveling(PI) begin...
8549 11:08:07.970904 ==
8550 11:08:07.974613 Dram Type= 6, Freq= 0, CH_1, rank 1
8551 11:08:07.979260 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8552 11:08:07.979722 ==
8553 11:08:07.980439 Write leveling (Byte 0): 24 => 24
8554 11:08:07.983863 Write leveling (Byte 1): 21 => 21
8555 11:08:07.987465 DramcWriteLeveling(PI) end<-----
8556 11:08:07.988030
8557 11:08:07.988398 ==
8558 11:08:07.990875 Dram Type= 6, Freq= 0, CH_1, rank 1
8559 11:08:07.993730 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8560 11:08:07.994459 ==
8561 11:08:07.997282 [Gating] SW mode calibration
8562 11:08:08.003428 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8563 11:08:08.010101 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8564 11:08:08.013250 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8565 11:08:08.020125 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8566 11:08:08.023137 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8567 11:08:08.026746 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8568 11:08:08.033371 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8569 11:08:08.037465 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8570 11:08:08.039807 0 12 24 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
8571 11:08:08.046309 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8572 11:08:08.050148 0 13 0 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
8573 11:08:08.053198 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8574 11:08:08.060377 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8575 11:08:08.063073 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8576 11:08:08.066988 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8577 11:08:08.073927 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8578 11:08:08.076095 0 13 24 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8579 11:08:08.079869 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8580 11:08:08.086025 0 14 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8581 11:08:08.089657 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8582 11:08:08.092918 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8583 11:08:08.099295 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8584 11:08:08.103055 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8585 11:08:08.106332 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8586 11:08:08.109562 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8587 11:08:08.116310 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8588 11:08:08.119653 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8589 11:08:08.123517 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8590 11:08:08.129605 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8591 11:08:08.133082 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8592 11:08:08.136185 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8593 11:08:08.142609 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8594 11:08:08.145681 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8595 11:08:08.149895 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8596 11:08:08.156172 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8597 11:08:08.158925 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8598 11:08:08.162535 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8599 11:08:08.169322 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8600 11:08:08.172669 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8601 11:08:08.175563 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8602 11:08:08.182586 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8603 11:08:08.185369 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8604 11:08:08.188600 Total UI for P1: 0, mck2ui 16
8605 11:08:08.192384 best dqsien dly found for B0: ( 1, 0, 24)
8606 11:08:08.195253 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8607 11:08:08.202253 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8608 11:08:08.205482 Total UI for P1: 0, mck2ui 16
8609 11:08:08.208598 best dqsien dly found for B1: ( 1, 0, 30)
8610 11:08:08.211773 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8611 11:08:08.214984 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8612 11:08:08.215451
8613 11:08:08.219029 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8614 11:08:08.222411 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8615 11:08:08.225297 [Gating] SW calibration Done
8616 11:08:08.225751 ==
8617 11:08:08.228796 Dram Type= 6, Freq= 0, CH_1, rank 1
8618 11:08:08.232177 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8619 11:08:08.232795 ==
8620 11:08:08.235138 RX Vref Scan: 0
8621 11:08:08.235691
8622 11:08:08.236058 RX Vref 0 -> 0, step: 1
8623 11:08:08.239124
8624 11:08:08.239579 RX Delay 0 -> 252, step: 8
8625 11:08:08.245403 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8626 11:08:08.248979 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8627 11:08:08.252308 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8628 11:08:08.254866 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8629 11:08:08.259262 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8630 11:08:08.261366 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8631 11:08:08.268342 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8632 11:08:08.271551 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8633 11:08:08.274932 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8634 11:08:08.278195 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8635 11:08:08.285311 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8636 11:08:08.288256 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8637 11:08:08.291756 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8638 11:08:08.294937 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8639 11:08:08.298410 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8640 11:08:08.305093 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8641 11:08:08.305646 ==
8642 11:08:08.308069 Dram Type= 6, Freq= 0, CH_1, rank 1
8643 11:08:08.311406 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8644 11:08:08.311967 ==
8645 11:08:08.312342 DQS Delay:
8646 11:08:08.314721 DQS0 = 0, DQS1 = 0
8647 11:08:08.315174 DQM Delay:
8648 11:08:08.318491 DQM0 = 131, DQM1 = 124
8649 11:08:08.319041 DQ Delay:
8650 11:08:08.321666 DQ0 =131, DQ1 =123, DQ2 =119, DQ3 =131
8651 11:08:08.324923 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8652 11:08:08.328253 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8653 11:08:08.331580 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8654 11:08:08.332336
8655 11:08:08.334966
8656 11:08:08.335515 ==
8657 11:08:08.337857 Dram Type= 6, Freq= 0, CH_1, rank 1
8658 11:08:08.342547 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8659 11:08:08.343172 ==
8660 11:08:08.343557
8661 11:08:08.343897
8662 11:08:08.344669 TX Vref Scan disable
8663 11:08:08.345109 == TX Byte 0 ==
8664 11:08:08.351594 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8665 11:08:08.354649 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8666 11:08:08.355211 == TX Byte 1 ==
8667 11:08:08.361532 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8668 11:08:08.364487 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8669 11:08:08.365097 ==
8670 11:08:08.367435 Dram Type= 6, Freq= 0, CH_1, rank 1
8671 11:08:08.370452 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8672 11:08:08.370910 ==
8673 11:08:08.384356
8674 11:08:08.387453 TX Vref early break, caculate TX vref
8675 11:08:08.392054 TX Vref=16, minBit 0, minWin=22, winSum=378
8676 11:08:08.393846 TX Vref=18, minBit 0, minWin=23, winSum=388
8677 11:08:08.397210 TX Vref=20, minBit 0, minWin=23, winSum=395
8678 11:08:08.400549 TX Vref=22, minBit 0, minWin=23, winSum=404
8679 11:08:08.404007 TX Vref=24, minBit 0, minWin=25, winSum=415
8680 11:08:08.410757 TX Vref=26, minBit 5, minWin=24, winSum=417
8681 11:08:08.413750 TX Vref=28, minBit 0, minWin=23, winSum=415
8682 11:08:08.416981 TX Vref=30, minBit 0, minWin=24, winSum=415
8683 11:08:08.420538 TX Vref=32, minBit 0, minWin=22, winSum=405
8684 11:08:08.423756 TX Vref=34, minBit 0, minWin=22, winSum=395
8685 11:08:08.431053 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 24
8686 11:08:08.431605
8687 11:08:08.433318 Final TX Range 0 Vref 24
8688 11:08:08.433775
8689 11:08:08.434156 ==
8690 11:08:08.437239 Dram Type= 6, Freq= 0, CH_1, rank 1
8691 11:08:08.440131 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8692 11:08:08.440696 ==
8693 11:08:08.441117
8694 11:08:08.443330
8695 11:08:08.443884 TX Vref Scan disable
8696 11:08:08.449533 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8697 11:08:08.449988 == TX Byte 0 ==
8698 11:08:08.454016 u2DelayCellOfst[0]=14 cells (4 PI)
8699 11:08:08.457201 u2DelayCellOfst[1]=10 cells (3 PI)
8700 11:08:08.459842 u2DelayCellOfst[2]=0 cells (0 PI)
8701 11:08:08.464265 u2DelayCellOfst[3]=7 cells (2 PI)
8702 11:08:08.466144 u2DelayCellOfst[4]=7 cells (2 PI)
8703 11:08:08.469899 u2DelayCellOfst[5]=18 cells (5 PI)
8704 11:08:08.472888 u2DelayCellOfst[6]=18 cells (5 PI)
8705 11:08:08.476684 u2DelayCellOfst[7]=7 cells (2 PI)
8706 11:08:08.479331 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8707 11:08:08.483309 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8708 11:08:08.486215 == TX Byte 1 ==
8709 11:08:08.489975 u2DelayCellOfst[8]=0 cells (0 PI)
8710 11:08:08.492942 u2DelayCellOfst[9]=7 cells (2 PI)
8711 11:08:08.496164 u2DelayCellOfst[10]=14 cells (4 PI)
8712 11:08:08.496624 u2DelayCellOfst[11]=7 cells (2 PI)
8713 11:08:08.499710 u2DelayCellOfst[12]=18 cells (5 PI)
8714 11:08:08.503242 u2DelayCellOfst[13]=18 cells (5 PI)
8715 11:08:08.506462 u2DelayCellOfst[14]=21 cells (6 PI)
8716 11:08:08.508998 u2DelayCellOfst[15]=18 cells (5 PI)
8717 11:08:08.515930 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8718 11:08:08.519454 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8719 11:08:08.520019 DramC Write-DBI on
8720 11:08:08.520389 ==
8721 11:08:08.522471 Dram Type= 6, Freq= 0, CH_1, rank 1
8722 11:08:08.529526 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8723 11:08:08.530304 ==
8724 11:08:08.530699
8725 11:08:08.531036
8726 11:08:08.532824 TX Vref Scan disable
8727 11:08:08.533285 == TX Byte 0 ==
8728 11:08:08.539651 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8729 11:08:08.540207 == TX Byte 1 ==
8730 11:08:08.543129 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8731 11:08:08.546015 DramC Write-DBI off
8732 11:08:08.546567
8733 11:08:08.546968 [DATLAT]
8734 11:08:08.548870 Freq=1600, CH1 RK1
8735 11:08:08.549448
8736 11:08:08.549816 DATLAT Default: 0xe
8737 11:08:08.552355 0, 0xFFFF, sum = 0
8738 11:08:08.553009 1, 0xFFFF, sum = 0
8739 11:08:08.555479 2, 0xFFFF, sum = 0
8740 11:08:08.555942 3, 0xFFFF, sum = 0
8741 11:08:08.558956 4, 0xFFFF, sum = 0
8742 11:08:08.559514 5, 0xFFFF, sum = 0
8743 11:08:08.562551 6, 0xFFFF, sum = 0
8744 11:08:08.563174 7, 0xFFFF, sum = 0
8745 11:08:08.565864 8, 0xFFFF, sum = 0
8746 11:08:08.566324 9, 0xFFFF, sum = 0
8747 11:08:08.569056 10, 0xFFFF, sum = 0
8748 11:08:08.572809 11, 0xFFFF, sum = 0
8749 11:08:08.573401 12, 0xFFF, sum = 0
8750 11:08:08.575356 13, 0x0, sum = 1
8751 11:08:08.575918 14, 0x0, sum = 2
8752 11:08:08.578731 15, 0x0, sum = 3
8753 11:08:08.579293 16, 0x0, sum = 4
8754 11:08:08.579669 best_step = 14
8755 11:08:08.580007
8756 11:08:08.581656 ==
8757 11:08:08.585224 Dram Type= 6, Freq= 0, CH_1, rank 1
8758 11:08:08.588810 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8759 11:08:08.589231 ==
8760 11:08:08.589579 RX Vref Scan: 0
8761 11:08:08.589907
8762 11:08:08.591595 RX Vref 0 -> 0, step: 1
8763 11:08:08.592046
8764 11:08:08.595331 RX Delay 3 -> 252, step: 4
8765 11:08:08.598011 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8766 11:08:08.601600 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8767 11:08:08.607952 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8768 11:08:08.611483 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8769 11:08:08.614589 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8770 11:08:08.618197 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8771 11:08:08.621474 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8772 11:08:08.628330 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8773 11:08:08.631830 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8774 11:08:08.634782 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8775 11:08:08.637885 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8776 11:08:08.645021 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8777 11:08:08.649122 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8778 11:08:08.651508 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8779 11:08:08.655066 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8780 11:08:08.657880 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8781 11:08:08.661208 ==
8782 11:08:08.665099 Dram Type= 6, Freq= 0, CH_1, rank 1
8783 11:08:08.668354 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8784 11:08:08.668918 ==
8785 11:08:08.669296 DQS Delay:
8786 11:08:08.670798 DQS0 = 0, DQS1 = 0
8787 11:08:08.671280 DQM Delay:
8788 11:08:08.674538 DQM0 = 126, DQM1 = 122
8789 11:08:08.675089 DQ Delay:
8790 11:08:08.678650 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8791 11:08:08.681071 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8792 11:08:08.684517 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =114
8793 11:08:08.687611 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8794 11:08:08.688071
8795 11:08:08.688664
8796 11:08:08.689104
8797 11:08:08.692218 [DramC_TX_OE_Calibration] TA2
8798 11:08:08.694854 Original DQ_B0 (3 6) =30, OEN = 27
8799 11:08:08.698101 Original DQ_B1 (3 6) =30, OEN = 27
8800 11:08:08.700859 24, 0x0, End_B0=24 End_B1=24
8801 11:08:08.704063 25, 0x0, End_B0=25 End_B1=25
8802 11:08:08.704697 26, 0x0, End_B0=26 End_B1=26
8803 11:08:08.707611 27, 0x0, End_B0=27 End_B1=27
8804 11:08:08.710739 28, 0x0, End_B0=28 End_B1=28
8805 11:08:08.713836 29, 0x0, End_B0=29 End_B1=29
8806 11:08:08.717050 30, 0x0, End_B0=30 End_B1=30
8807 11:08:08.717513 31, 0x4141, End_B0=30 End_B1=30
8808 11:08:08.721296 Byte0 end_step=30 best_step=27
8809 11:08:08.724696 Byte1 end_step=30 best_step=27
8810 11:08:08.727685 Byte0 TX OE(2T, 0.5T) = (3, 3)
8811 11:08:08.730868 Byte1 TX OE(2T, 0.5T) = (3, 3)
8812 11:08:08.731514
8813 11:08:08.731885
8814 11:08:08.737453 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8815 11:08:08.741442 CH1 RK1: MR19=303, MR18=1D1D
8816 11:08:08.747561 CH1_RK1: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
8817 11:08:08.751183 [RxdqsGatingPostProcess] freq 1600
8818 11:08:08.757284 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8819 11:08:08.760687 Pre-setting of DQS Precalculation
8820 11:08:08.763670 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8821 11:08:08.770070 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8822 11:08:08.776794 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8823 11:08:08.777357
8824 11:08:08.780571
8825 11:08:08.781273 [Calibration Summary] 3200 Mbps
8826 11:08:08.783734 CH 0, Rank 0
8827 11:08:08.784285 SW Impedance : PASS
8828 11:08:08.786541 DUTY Scan : NO K
8829 11:08:08.791619 ZQ Calibration : PASS
8830 11:08:08.792171 Jitter Meter : NO K
8831 11:08:08.793395 CBT Training : PASS
8832 11:08:08.797605 Write leveling : PASS
8833 11:08:08.798162 RX DQS gating : PASS
8834 11:08:08.800073 RX DQ/DQS(RDDQC) : PASS
8835 11:08:08.804052 TX DQ/DQS : PASS
8836 11:08:08.804612 RX DATLAT : PASS
8837 11:08:08.806641 RX DQ/DQS(Engine): PASS
8838 11:08:08.809642 TX OE : PASS
8839 11:08:08.810102 All Pass.
8840 11:08:08.810505
8841 11:08:08.811038 CH 0, Rank 1
8842 11:08:08.813332 SW Impedance : PASS
8843 11:08:08.816267 DUTY Scan : NO K
8844 11:08:08.816800 ZQ Calibration : PASS
8845 11:08:08.819861 Jitter Meter : NO K
8846 11:08:08.823155 CBT Training : PASS
8847 11:08:08.823709 Write leveling : PASS
8848 11:08:08.827121 RX DQS gating : PASS
8849 11:08:08.829925 RX DQ/DQS(RDDQC) : PASS
8850 11:08:08.830394 TX DQ/DQS : PASS
8851 11:08:08.833117 RX DATLAT : PASS
8852 11:08:08.833570 RX DQ/DQS(Engine): PASS
8853 11:08:08.836070 TX OE : PASS
8854 11:08:08.836622 All Pass.
8855 11:08:08.837088
8856 11:08:08.839879 CH 1, Rank 0
8857 11:08:08.840424 SW Impedance : PASS
8858 11:08:08.843687 DUTY Scan : NO K
8859 11:08:08.846611 ZQ Calibration : PASS
8860 11:08:08.847162 Jitter Meter : NO K
8861 11:08:08.850514 CBT Training : PASS
8862 11:08:08.852341 Write leveling : PASS
8863 11:08:08.852848 RX DQS gating : PASS
8864 11:08:08.855896 RX DQ/DQS(RDDQC) : PASS
8865 11:08:08.860132 TX DQ/DQS : PASS
8866 11:08:08.860684 RX DATLAT : PASS
8867 11:08:08.862643 RX DQ/DQS(Engine): PASS
8868 11:08:08.865844 TX OE : PASS
8869 11:08:08.866402 All Pass.
8870 11:08:08.866771
8871 11:08:08.867106 CH 1, Rank 1
8872 11:08:08.869064 SW Impedance : PASS
8873 11:08:08.872614 DUTY Scan : NO K
8874 11:08:08.873230 ZQ Calibration : PASS
8875 11:08:08.876249 Jitter Meter : NO K
8876 11:08:08.879490 CBT Training : PASS
8877 11:08:08.880060 Write leveling : PASS
8878 11:08:08.882604 RX DQS gating : PASS
8879 11:08:08.885847 RX DQ/DQS(RDDQC) : PASS
8880 11:08:08.886301 TX DQ/DQS : PASS
8881 11:08:08.889241 RX DATLAT : PASS
8882 11:08:08.893055 RX DQ/DQS(Engine): PASS
8883 11:08:08.893605 TX OE : PASS
8884 11:08:08.893974 All Pass.
8885 11:08:08.896282
8886 11:08:08.896861 DramC Write-DBI on
8887 11:08:08.898647 PER_BANK_REFRESH: Hybrid Mode
8888 11:08:08.899105 TX_TRACKING: ON
8889 11:08:08.909330 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8890 11:08:08.915871 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8891 11:08:08.925360 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8892 11:08:08.928889 [FAST_K] Save calibration result to emmc
8893 11:08:08.932417 sync common calibartion params.
8894 11:08:08.932948 sync cbt_mode0:0, 1:0
8895 11:08:08.935784 dram_init: ddr_geometry: 0
8896 11:08:08.938451 dram_init: ddr_geometry: 0
8897 11:08:08.939014 dram_init: ddr_geometry: 0
8898 11:08:08.942769 0:dram_rank_size:80000000
8899 11:08:08.946664 1:dram_rank_size:80000000
8900 11:08:08.948583 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8901 11:08:08.952815 DFS_SHUFFLE_HW_MODE: ON
8902 11:08:08.955532 dramc_set_vcore_voltage set vcore to 725000
8903 11:08:08.959011 Read voltage for 1600, 0
8904 11:08:08.959573 Vio18 = 0
8905 11:08:08.961884 Vcore = 725000
8906 11:08:08.962448 Vdram = 0
8907 11:08:08.962817 Vddq = 0
8908 11:08:08.963156 Vmddr = 0
8909 11:08:08.965428 switch to 3200 Mbps bootup
8910 11:08:08.968958 [DramcRunTimeConfig]
8911 11:08:08.969657 PHYPLL
8912 11:08:08.973172 DPM_CONTROL_AFTERK: ON
8913 11:08:08.973757 PER_BANK_REFRESH: ON
8914 11:08:08.975030 REFRESH_OVERHEAD_REDUCTION: ON
8915 11:08:08.978444 CMD_PICG_NEW_MODE: OFF
8916 11:08:08.979010 XRTWTW_NEW_MODE: ON
8917 11:08:08.982345 XRTRTR_NEW_MODE: ON
8918 11:08:08.982800 TX_TRACKING: ON
8919 11:08:08.984771 RDSEL_TRACKING: OFF
8920 11:08:08.988883 DQS Precalculation for DVFS: ON
8921 11:08:08.989442 RX_TRACKING: OFF
8922 11:08:08.989814 HW_GATING DBG: ON
8923 11:08:08.991464 ZQCS_ENABLE_LP4: ON
8924 11:08:08.995359 RX_PICG_NEW_MODE: ON
8925 11:08:08.995917 TX_PICG_NEW_MODE: ON
8926 11:08:08.998989 ENABLE_RX_DCM_DPHY: ON
8927 11:08:09.001546 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8928 11:08:09.002005 DUMMY_READ_FOR_TRACKING: OFF
8929 11:08:09.005472 !!! SPM_CONTROL_AFTERK: OFF
8930 11:08:09.008907 !!! SPM could not control APHY
8931 11:08:09.011683 IMPEDANCE_TRACKING: ON
8932 11:08:09.012245 TEMP_SENSOR: ON
8933 11:08:09.015422 HW_SAVE_FOR_SR: OFF
8934 11:08:09.017970 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8935 11:08:09.022535 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8936 11:08:09.023095 Read ODT Tracking: ON
8937 11:08:09.025230 Refresh Rate DeBounce: ON
8938 11:08:09.028216 DFS_NO_QUEUE_FLUSH: ON
8939 11:08:09.031438 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8940 11:08:09.032033 ENABLE_DFS_RUNTIME_MRW: OFF
8941 11:08:09.035405 DDR_RESERVE_NEW_MODE: ON
8942 11:08:09.038532 MR_CBT_SWITCH_FREQ: ON
8943 11:08:09.038992 =========================
8944 11:08:09.058250 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8945 11:08:09.061222 dram_init: ddr_geometry: 0
8946 11:08:09.079247 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8947 11:08:09.083714 dram_init: dram init end (result: 0)
8948 11:08:09.089031 DRAM-K: Full calibration passed in 23476 msecs
8949 11:08:09.092625 MRC: failed to locate region type 0.
8950 11:08:09.093223 DRAM rank0 size:0x80000000,
8951 11:08:09.096085 DRAM rank1 size=0x80000000
8952 11:08:09.105959 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8953 11:08:09.112657 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8954 11:08:09.119801 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8955 11:08:09.126011 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8956 11:08:09.129423 DRAM rank0 size:0x80000000,
8957 11:08:09.133082 DRAM rank1 size=0x80000000
8958 11:08:09.133558 CBMEM:
8959 11:08:09.135213 IMD: root @ 0xfffff000 254 entries.
8960 11:08:09.138783 IMD: root @ 0xffffec00 62 entries.
8961 11:08:09.141706 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8962 11:08:09.145062 WARNING: RO_VPD is uninitialized or empty.
8963 11:08:09.151763 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8964 11:08:09.158754 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8965 11:08:09.171553 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8966 11:08:09.182856 BS: romstage times (exec / console): total (unknown) / 23006 ms
8967 11:08:09.183335
8968 11:08:09.183697
8969 11:08:09.193144 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8970 11:08:09.195850 ARM64: Exception handlers installed.
8971 11:08:09.200070 ARM64: Testing exception
8972 11:08:09.203307 ARM64: Done test exception
8973 11:08:09.203768 Enumerating buses...
8974 11:08:09.206362 Show all devs... Before device enumeration.
8975 11:08:09.210442 Root Device: enabled 1
8976 11:08:09.213108 CPU_CLUSTER: 0: enabled 1
8977 11:08:09.213582 CPU: 00: enabled 1
8978 11:08:09.215814 Compare with tree...
8979 11:08:09.216269 Root Device: enabled 1
8980 11:08:09.219746 CPU_CLUSTER: 0: enabled 1
8981 11:08:09.223424 CPU: 00: enabled 1
8982 11:08:09.223979 Root Device scanning...
8983 11:08:09.226237 scan_static_bus for Root Device
8984 11:08:09.229358 CPU_CLUSTER: 0 enabled
8985 11:08:09.232605 scan_static_bus for Root Device done
8986 11:08:09.235786 scan_bus: bus Root Device finished in 8 msecs
8987 11:08:09.236341 done
8988 11:08:09.243752 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8989 11:08:09.245577 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8990 11:08:09.252316 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8991 11:08:09.256327 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8992 11:08:09.258922 Allocating resources...
8993 11:08:09.261860 Reading resources...
8994 11:08:09.265289 Root Device read_resources bus 0 link: 0
8995 11:08:09.269277 DRAM rank0 size:0x80000000,
8996 11:08:09.269749 DRAM rank1 size=0x80000000
8997 11:08:09.271915 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8998 11:08:09.275801 CPU: 00 missing read_resources
8999 11:08:09.281780 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9000 11:08:09.285391 Root Device read_resources bus 0 link: 0 done
9001 11:08:09.286020 Done reading resources.
9002 11:08:09.292752 Show resources in subtree (Root Device)...After reading.
9003 11:08:09.296025 Root Device child on link 0 CPU_CLUSTER: 0
9004 11:08:09.298835 CPU_CLUSTER: 0 child on link 0 CPU: 00
9005 11:08:09.308939 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9006 11:08:09.309495 CPU: 00
9007 11:08:09.311819 Root Device assign_resources, bus 0 link: 0
9008 11:08:09.315051 CPU_CLUSTER: 0 missing set_resources
9009 11:08:09.322323 Root Device assign_resources, bus 0 link: 0 done
9010 11:08:09.322873 Done setting resources.
9011 11:08:09.328412 Show resources in subtree (Root Device)...After assigning values.
9012 11:08:09.331882 Root Device child on link 0 CPU_CLUSTER: 0
9013 11:08:09.335000 CPU_CLUSTER: 0 child on link 0 CPU: 00
9014 11:08:09.345454 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9015 11:08:09.346016 CPU: 00
9016 11:08:09.348993 Done allocating resources.
9017 11:08:09.355018 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9018 11:08:09.355576 Enabling resources...
9019 11:08:09.355949 done.
9020 11:08:09.361476 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9021 11:08:09.362016 Initializing devices...
9022 11:08:09.364913 Root Device init
9023 11:08:09.365464 init hardware done!
9024 11:08:09.368122 0x00000018: ctrlr->caps
9025 11:08:09.371561 52.000 MHz: ctrlr->f_max
9026 11:08:09.372033 0.400 MHz: ctrlr->f_min
9027 11:08:09.375062 0x40ff8080: ctrlr->voltages
9028 11:08:09.378699 sclk: 390625
9029 11:08:09.379251 Bus Width = 1
9030 11:08:09.379626 sclk: 390625
9031 11:08:09.382357 Bus Width = 1
9032 11:08:09.382831 Early init status = 3
9033 11:08:09.388534 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9034 11:08:09.391406 in-header: 03 fc 00 00 01 00 00 00
9035 11:08:09.394466 in-data: 00
9036 11:08:09.398006 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9037 11:08:09.401586 in-header: 03 fd 00 00 00 00 00 00
9038 11:08:09.405021 in-data:
9039 11:08:09.408424 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9040 11:08:09.412339 in-header: 03 fc 00 00 01 00 00 00
9041 11:08:09.415206 in-data: 00
9042 11:08:09.418652 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9043 11:08:09.424804 in-header: 03 fd 00 00 00 00 00 00
9044 11:08:09.426651 in-data:
9045 11:08:09.429914 [SSUSB] Setting up USB HOST controller...
9046 11:08:09.435024 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9047 11:08:09.436522 [SSUSB] phy power-on done.
9048 11:08:09.440479 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9049 11:08:09.446704 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9050 11:08:09.449994 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9051 11:08:09.457108 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9052 11:08:09.463765 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9053 11:08:09.470138 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9054 11:08:09.476071 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9055 11:08:09.483121 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9056 11:08:09.486032 SPM: binary array size = 0x9dc
9057 11:08:09.489885 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9058 11:08:09.496460 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9059 11:08:09.503326 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9060 11:08:09.509394 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9061 11:08:09.512853 configure_display: Starting display init
9062 11:08:09.547566 anx7625_power_on_init: Init interface.
9063 11:08:09.550128 anx7625_disable_pd_protocol: Disabled PD feature.
9064 11:08:09.554215 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9065 11:08:09.581594 anx7625_start_dp_work: Secure OCM version=00
9066 11:08:09.584250 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9067 11:08:09.601668 sp_tx_get_edid_block: EDID Block = 1
9068 11:08:09.702144 Extracted contents:
9069 11:08:09.705326 header: 00 ff ff ff ff ff ff 00
9070 11:08:09.708663 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9071 11:08:09.712532 version: 01 04
9072 11:08:09.715349 basic params: 95 1f 11 78 0a
9073 11:08:09.717939 chroma info: 76 90 94 55 54 90 27 21 50 54
9074 11:08:09.721268 established: 00 00 00
9075 11:08:09.728763 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9076 11:08:09.734516 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9077 11:08:09.738223 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9078 11:08:09.745025 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9079 11:08:09.751623 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9080 11:08:09.755348 extensions: 00
9081 11:08:09.755806 checksum: fb
9082 11:08:09.756172
9083 11:08:09.761033 Manufacturer: IVO Model 57d Serial Number 0
9084 11:08:09.761492 Made week 0 of 2020
9085 11:08:09.764593 EDID version: 1.4
9086 11:08:09.765188 Digital display
9087 11:08:09.768296 6 bits per primary color channel
9088 11:08:09.768799 DisplayPort interface
9089 11:08:09.771116 Maximum image size: 31 cm x 17 cm
9090 11:08:09.773934 Gamma: 220%
9091 11:08:09.774389 Check DPMS levels
9092 11:08:09.781355 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9093 11:08:09.784062 First detailed timing is preferred timing
9094 11:08:09.784524 Established timings supported:
9095 11:08:09.787763 Standard timings supported:
9096 11:08:09.791020 Detailed timings
9097 11:08:09.793908 Hex of detail: 383680a07038204018303c0035ae10000019
9098 11:08:09.800760 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9099 11:08:09.804617 0780 0798 07c8 0820 hborder 0
9100 11:08:09.807412 0438 043b 0447 0458 vborder 0
9101 11:08:09.811249 -hsync -vsync
9102 11:08:09.811800 Did detailed timing
9103 11:08:09.816936 Hex of detail: 000000000000000000000000000000000000
9104 11:08:09.820592 Manufacturer-specified data, tag 0
9105 11:08:09.823963 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9106 11:08:09.827024 ASCII string: InfoVision
9107 11:08:09.830296 Hex of detail: 000000fe00523134304e574635205248200a
9108 11:08:09.833980 ASCII string: R140NWF5 RH
9109 11:08:09.834548 Checksum
9110 11:08:09.836825 Checksum: 0xfb (valid)
9111 11:08:09.840628 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9112 11:08:09.843984 DSI data_rate: 832800000 bps
9113 11:08:09.850262 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9114 11:08:09.853278 anx7625_parse_edid: pixelclock(138800).
9115 11:08:09.857130 hactive(1920), hsync(48), hfp(24), hbp(88)
9116 11:08:09.860809 vactive(1080), vsync(12), vfp(3), vbp(17)
9117 11:08:09.864360 anx7625_dsi_config: config dsi.
9118 11:08:09.869746 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9119 11:08:09.884997 anx7625_dsi_config: success to config DSI
9120 11:08:09.886973 anx7625_dp_start: MIPI phy setup OK.
9121 11:08:09.890301 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9122 11:08:09.893747 mtk_ddp_mode_set invalid vrefresh 60
9123 11:08:09.897626 main_disp_path_setup
9124 11:08:09.898207 ovl_layer_smi_id_en
9125 11:08:09.900362 ovl_layer_smi_id_en
9126 11:08:09.900996 ccorr_config
9127 11:08:09.901486 aal_config
9128 11:08:09.903784 gamma_config
9129 11:08:09.904369 postmask_config
9130 11:08:09.907586 dither_config
9131 11:08:09.910372 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9132 11:08:09.917629 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9133 11:08:09.920237 Root Device init finished in 552 msecs
9134 11:08:09.923638 CPU_CLUSTER: 0 init
9135 11:08:09.930119 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9136 11:08:09.936754 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9137 11:08:09.937384 APU_MBOX 0x190000b0 = 0x10001
9138 11:08:09.939998 APU_MBOX 0x190001b0 = 0x10001
9139 11:08:09.943459 APU_MBOX 0x190005b0 = 0x10001
9140 11:08:09.947288 APU_MBOX 0x190006b0 = 0x10001
9141 11:08:09.952998 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9142 11:08:09.962834 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9143 11:08:09.975556 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9144 11:08:09.981503 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9145 11:08:09.993642 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9146 11:08:10.003091 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9147 11:08:10.006476 CPU_CLUSTER: 0 init finished in 81 msecs
9148 11:08:10.009467 Devices initialized
9149 11:08:10.012313 Show all devs... After init.
9150 11:08:10.012903 Root Device: enabled 1
9151 11:08:10.015717 CPU_CLUSTER: 0: enabled 1
9152 11:08:10.018774 CPU: 00: enabled 1
9153 11:08:10.022435 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9154 11:08:10.026204 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9155 11:08:10.028999 ELOG: NV offset 0x57f000 size 0x1000
9156 11:08:10.036061 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9157 11:08:10.042928 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9158 11:08:10.045540 ELOG: Event(17) added with size 13 at 2024-03-03 11:08:11 UTC
9159 11:08:10.052464 out: cmd=0x121: 03 db 21 01 00 00 00 00
9160 11:08:10.055312 in-header: 03 c5 00 00 2c 00 00 00
9161 11:08:10.064997 in-data: 9e 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9162 11:08:10.072192 ELOG: Event(A1) added with size 10 at 2024-03-03 11:08:11 UTC
9163 11:08:10.078994 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9164 11:08:10.085824 ELOG: Event(A0) added with size 9 at 2024-03-03 11:08:11 UTC
9165 11:08:10.089353 elog_add_boot_reason: Logged dev mode boot
9166 11:08:10.094793 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9167 11:08:10.095337 Finalize devices...
9168 11:08:10.099046 Devices finalized
9169 11:08:10.102339 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9170 11:08:10.105059 Writing coreboot table at 0xffe64000
9171 11:08:10.108186 0. 000000000010a000-0000000000113fff: RAMSTAGE
9172 11:08:10.115756 1. 0000000040000000-00000000400fffff: RAM
9173 11:08:10.119253 2. 0000000040100000-000000004032afff: RAMSTAGE
9174 11:08:10.121433 3. 000000004032b000-00000000545fffff: RAM
9175 11:08:10.125311 4. 0000000054600000-000000005465ffff: BL31
9176 11:08:10.128028 5. 0000000054660000-00000000ffe63fff: RAM
9177 11:08:10.135626 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9178 11:08:10.137721 7. 0000000100000000-000000013fffffff: RAM
9179 11:08:10.141148 Passing 5 GPIOs to payload:
9180 11:08:10.144844 NAME | PORT | POLARITY | VALUE
9181 11:08:10.151234 EC in RW | 0x000000aa | low | undefined
9182 11:08:10.154625 EC interrupt | 0x00000005 | low | undefined
9183 11:08:10.158130 TPM interrupt | 0x000000ab | high | undefined
9184 11:08:10.164149 SD card detect | 0x00000011 | high | undefined
9185 11:08:10.167417 speaker enable | 0x00000093 | high | undefined
9186 11:08:10.170537 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9187 11:08:10.174727 in-header: 03 f8 00 00 02 00 00 00
9188 11:08:10.178294 in-data: 03 00
9189 11:08:10.182212 ADC[4]: Raw value=669327 ID=5
9190 11:08:10.184920 ADC[3]: Raw value=212549 ID=1
9191 11:08:10.185381 RAM Code: 0x51
9192 11:08:10.189338 ADC[6]: Raw value=74410 ID=0
9193 11:08:10.191031 ADC[5]: Raw value=211444 ID=1
9194 11:08:10.191488 SKU Code: 0x1
9195 11:08:10.198166 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum cf64
9196 11:08:10.198721 coreboot table: 964 bytes.
9197 11:08:10.200967 IMD ROOT 0. 0xfffff000 0x00001000
9198 11:08:10.204785 IMD SMALL 1. 0xffffe000 0x00001000
9199 11:08:10.208639 RO MCACHE 2. 0xffffc000 0x00001104
9200 11:08:10.211632 CONSOLE 3. 0xfff7c000 0x00080000
9201 11:08:10.214656 FMAP 4. 0xfff7b000 0x00000452
9202 11:08:10.217797 TIME STAMP 5. 0xfff7a000 0x00000910
9203 11:08:10.221275 VBOOT WORK 6. 0xfff66000 0x00014000
9204 11:08:10.224643 RAMOOPS 7. 0xffe66000 0x00100000
9205 11:08:10.229386 COREBOOT 8. 0xffe64000 0x00002000
9206 11:08:10.230921 IMD small region:
9207 11:08:10.234424 IMD ROOT 0. 0xffffec00 0x00000400
9208 11:08:10.237283 VPD 1. 0xffffeb80 0x0000006c
9209 11:08:10.241429 MMC STATUS 2. 0xffffeb60 0x00000004
9210 11:08:10.247021 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9211 11:08:10.247609 Probing TPM: done!
9212 11:08:10.250671 Connected to device vid:did:rid of 1ae0:0028:00
9213 11:08:10.262313 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9214 11:08:10.265553 Initialized TPM device CR50 revision 0
9215 11:08:10.269602 Checking cr50 for pending updates
9216 11:08:10.272575 Reading cr50 TPM mode
9217 11:08:10.281879 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9218 11:08:10.288269 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9219 11:08:10.327992 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9220 11:08:10.331388 Checking segment from ROM address 0x40100000
9221 11:08:10.334953 Checking segment from ROM address 0x4010001c
9222 11:08:10.341559 Loading segment from ROM address 0x40100000
9223 11:08:10.342099 code (compression=0)
9224 11:08:10.351303 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9225 11:08:10.357612 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9226 11:08:10.358156 it's not compressed!
9227 11:08:10.364880 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9228 11:08:10.372329 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9229 11:08:10.388553 Loading segment from ROM address 0x4010001c
9230 11:08:10.389160 Entry Point 0x80000000
9231 11:08:10.392217 Loaded segments
9232 11:08:10.395127 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9233 11:08:10.401646 Jumping to boot code at 0x80000000(0xffe64000)
9234 11:08:10.408442 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9235 11:08:10.415213 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9236 11:08:10.423634 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9237 11:08:10.426350 Checking segment from ROM address 0x40100000
9238 11:08:10.429678 Checking segment from ROM address 0x4010001c
9239 11:08:10.436575 Loading segment from ROM address 0x40100000
9240 11:08:10.437196 code (compression=1)
9241 11:08:10.443390 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9242 11:08:10.452989 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9243 11:08:10.453553 using LZMA
9244 11:08:10.461812 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9245 11:08:10.468255 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9246 11:08:10.472084 Loading segment from ROM address 0x4010001c
9247 11:08:10.472648 Entry Point 0x54601000
9248 11:08:10.474221 Loaded segments
9249 11:08:10.477821 NOTICE: MT8192 bl31_setup
9250 11:08:10.484961 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9251 11:08:10.488574 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9252 11:08:10.491257 WARNING: region 0:
9253 11:08:10.494917 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9254 11:08:10.495476 WARNING: region 1:
9255 11:08:10.501392 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9256 11:08:10.505032 WARNING: region 2:
9257 11:08:10.508623 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9258 11:08:10.512093 WARNING: region 3:
9259 11:08:10.515551 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9260 11:08:10.518460 WARNING: region 4:
9261 11:08:10.525923 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9262 11:08:10.526477 WARNING: region 5:
9263 11:08:10.527969 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9264 11:08:10.531814 WARNING: region 6:
9265 11:08:10.534737 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9266 11:08:10.539074 WARNING: region 7:
9267 11:08:10.543071 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9268 11:08:10.548541 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9269 11:08:10.551793 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9270 11:08:10.554774 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9271 11:08:10.561372 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9272 11:08:10.564935 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9273 11:08:10.568112 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9274 11:08:10.575001 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9275 11:08:10.578507 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9276 11:08:10.584981 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9277 11:08:10.587928 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9278 11:08:10.591700 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9279 11:08:10.598092 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9280 11:08:10.601222 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9281 11:08:10.604902 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9282 11:08:10.611923 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9283 11:08:10.614978 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9284 11:08:10.621410 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9285 11:08:10.625641 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9286 11:08:10.628195 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9287 11:08:10.634911 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9288 11:08:10.638863 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9289 11:08:10.641772 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9290 11:08:10.648640 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9291 11:08:10.651373 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9292 11:08:10.658452 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9293 11:08:10.662195 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9294 11:08:10.666110 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9295 11:08:10.671569 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9296 11:08:10.674362 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9297 11:08:10.681119 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9298 11:08:10.684768 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9299 11:08:10.687695 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9300 11:08:10.695576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9301 11:08:10.698630 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9302 11:08:10.701191 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9303 11:08:10.704653 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9304 11:08:10.711526 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9305 11:08:10.714783 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9306 11:08:10.718046 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9307 11:08:10.721483 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9308 11:08:10.728435 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9309 11:08:10.731211 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9310 11:08:10.734155 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9311 11:08:10.738524 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9312 11:08:10.745427 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9313 11:08:10.747991 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9314 11:08:10.751484 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9315 11:08:10.757567 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9316 11:08:10.761035 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9317 11:08:10.764234 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9318 11:08:10.770750 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9319 11:08:10.774590 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9320 11:08:10.780643 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9321 11:08:10.784517 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9322 11:08:10.787566 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9323 11:08:10.794056 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9324 11:08:10.797398 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9325 11:08:10.804497 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9326 11:08:10.807915 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9327 11:08:10.814326 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9328 11:08:10.817687 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9329 11:08:10.824223 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9330 11:08:10.828000 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9331 11:08:10.830924 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9332 11:08:10.837980 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9333 11:08:10.840883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9334 11:08:10.847279 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9335 11:08:10.852235 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9336 11:08:10.858148 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9337 11:08:10.861076 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9338 11:08:10.864011 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9339 11:08:10.870918 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9340 11:08:10.874110 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9341 11:08:10.881677 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9342 11:08:10.883755 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9343 11:08:10.891163 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9344 11:08:10.893682 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9345 11:08:10.901182 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9346 11:08:10.903680 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9347 11:08:10.906877 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9348 11:08:10.913928 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9349 11:08:10.917676 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9350 11:08:10.923834 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9351 11:08:10.927195 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9352 11:08:10.934000 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9353 11:08:10.937699 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9354 11:08:10.940340 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9355 11:08:10.947143 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9356 11:08:10.950041 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9357 11:08:10.958816 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9358 11:08:10.959959 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9359 11:08:10.967328 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9360 11:08:10.970315 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9361 11:08:10.977826 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9362 11:08:10.979982 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9363 11:08:10.984017 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9364 11:08:10.990097 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9365 11:08:10.993679 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9366 11:08:10.997360 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9367 11:08:10.999921 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9368 11:08:11.007721 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9369 11:08:11.011310 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9370 11:08:11.016547 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9371 11:08:11.019892 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9372 11:08:11.024052 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9373 11:08:11.030142 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9374 11:08:11.033290 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9375 11:08:11.039957 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9376 11:08:11.043353 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9377 11:08:11.046276 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9378 11:08:11.053433 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9379 11:08:11.056263 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9380 11:08:11.063082 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9381 11:08:11.066149 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9382 11:08:11.070177 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9383 11:08:11.076676 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9384 11:08:11.079914 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9385 11:08:11.083166 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9386 11:08:11.089694 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9387 11:08:11.093672 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9388 11:08:11.097123 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9389 11:08:11.100025 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9390 11:08:11.106607 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9391 11:08:11.109388 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9392 11:08:11.113045 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9393 11:08:11.119096 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9394 11:08:11.123623 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9395 11:08:11.126422 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9396 11:08:11.133097 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9397 11:08:11.136603 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9398 11:08:11.142980 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9399 11:08:11.146132 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9400 11:08:11.149259 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9401 11:08:11.155891 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9402 11:08:11.159761 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9403 11:08:11.166020 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9404 11:08:11.169223 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9405 11:08:11.172478 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9406 11:08:11.178918 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9407 11:08:11.182552 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9408 11:08:11.190292 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9409 11:08:11.192440 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9410 11:08:11.195613 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9411 11:08:11.202825 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9412 11:08:11.205615 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9413 11:08:11.212052 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9414 11:08:11.215689 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9415 11:08:11.219245 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9416 11:08:11.226305 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9417 11:08:11.229625 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9418 11:08:11.235225 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9419 11:08:11.238620 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9420 11:08:11.241752 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9421 11:08:11.248693 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9422 11:08:11.252133 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9423 11:08:11.258638 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9424 11:08:11.261982 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9425 11:08:11.265408 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9426 11:08:11.271728 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9427 11:08:11.274589 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9428 11:08:11.281978 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9429 11:08:11.284884 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9430 11:08:11.287809 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9431 11:08:11.294684 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9432 11:08:11.297907 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9433 11:08:11.305071 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9434 11:08:11.307755 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9435 11:08:11.311133 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9436 11:08:11.317354 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9437 11:08:11.321263 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9438 11:08:11.327679 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9439 11:08:11.331787 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9440 11:08:11.334349 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9441 11:08:11.341594 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9442 11:08:11.344480 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9443 11:08:11.350738 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9444 11:08:11.354027 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9445 11:08:11.357144 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9446 11:08:11.364112 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9447 11:08:11.366988 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9448 11:08:11.373427 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9449 11:08:11.376895 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9450 11:08:11.380840 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9451 11:08:11.387289 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9452 11:08:11.390046 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9453 11:08:11.396772 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9454 11:08:11.400661 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9455 11:08:11.403644 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9456 11:08:11.410179 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9457 11:08:11.413447 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9458 11:08:11.421456 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9459 11:08:11.424059 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9460 11:08:11.429882 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9461 11:08:11.432952 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9462 11:08:11.436671 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9463 11:08:11.442942 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9464 11:08:11.446471 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9465 11:08:11.453251 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9466 11:08:11.456267 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9467 11:08:11.462832 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9468 11:08:11.466182 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9469 11:08:11.470261 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9470 11:08:11.476213 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9471 11:08:11.479722 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9472 11:08:11.485833 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9473 11:08:11.490816 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9474 11:08:11.493109 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9475 11:08:11.499176 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9476 11:08:11.503187 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9477 11:08:11.508967 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9478 11:08:11.512831 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9479 11:08:11.520176 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9480 11:08:11.522598 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9481 11:08:11.527579 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9482 11:08:11.532314 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9483 11:08:11.535852 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9484 11:08:11.541913 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9485 11:08:11.545463 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9486 11:08:11.552437 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9487 11:08:11.555610 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9488 11:08:11.558677 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9489 11:08:11.565700 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9490 11:08:11.568841 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9491 11:08:11.575633 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9492 11:08:11.578457 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9493 11:08:11.585178 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9494 11:08:11.588323 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9495 11:08:11.591274 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9496 11:08:11.598335 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9497 11:08:11.601235 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9498 11:08:11.604401 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9499 11:08:11.611431 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9500 11:08:11.614846 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9501 11:08:11.617741 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9502 11:08:11.621896 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9503 11:08:11.627650 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9504 11:08:11.631848 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9505 11:08:11.638081 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9506 11:08:11.640324 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9507 11:08:11.644455 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9508 11:08:11.650862 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9509 11:08:11.653960 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9510 11:08:11.660460 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9511 11:08:11.663964 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9512 11:08:11.666817 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9513 11:08:11.673689 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9514 11:08:11.678782 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9515 11:08:11.680375 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9516 11:08:11.686957 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9517 11:08:11.690406 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9518 11:08:11.693439 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9519 11:08:11.700208 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9520 11:08:11.703875 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9521 11:08:11.710216 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9522 11:08:11.713312 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9523 11:08:11.716596 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9524 11:08:11.723823 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9525 11:08:11.726880 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9526 11:08:11.729581 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9527 11:08:11.737107 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9528 11:08:11.739641 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9529 11:08:11.746080 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9530 11:08:11.749263 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9531 11:08:11.752836 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9532 11:08:11.759670 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9533 11:08:11.762684 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9534 11:08:11.769169 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9535 11:08:11.773000 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9536 11:08:11.775923 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9537 11:08:11.779407 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9538 11:08:11.786005 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9539 11:08:11.789448 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9540 11:08:11.792829 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9541 11:08:11.795346 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9542 11:08:11.803383 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9543 11:08:11.806050 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9544 11:08:11.808817 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9545 11:08:11.812255 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9546 11:08:11.818484 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9547 11:08:11.822595 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9548 11:08:11.824980 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9549 11:08:11.831649 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9550 11:08:11.834625 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9551 11:08:11.838072 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9552 11:08:11.845296 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9553 11:08:11.848275 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9554 11:08:11.854568 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9555 11:08:11.858091 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9556 11:08:11.864853 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9557 11:08:11.867890 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9558 11:08:11.871751 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9559 11:08:11.877898 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9560 11:08:11.880801 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9561 11:08:11.887946 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9562 11:08:11.890619 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9563 11:08:11.897341 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9564 11:08:11.901462 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9565 11:08:11.904326 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9566 11:08:11.910894 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9567 11:08:11.913990 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9568 11:08:11.920643 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9569 11:08:11.923936 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9570 11:08:11.927789 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9571 11:08:11.933815 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9572 11:08:11.937286 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9573 11:08:11.944018 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9574 11:08:11.947345 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9575 11:08:11.950784 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9576 11:08:11.956598 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9577 11:08:11.960170 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9578 11:08:11.966899 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9579 11:08:11.969953 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9580 11:08:11.978016 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9581 11:08:11.981724 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9582 11:08:11.983670 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9583 11:08:11.989638 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9584 11:08:11.993032 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9585 11:08:12.000586 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9586 11:08:12.003482 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9587 11:08:12.009640 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9588 11:08:12.012835 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9589 11:08:12.016522 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9590 11:08:12.022637 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9591 11:08:12.026640 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9592 11:08:12.033036 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9593 11:08:12.036518 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9594 11:08:12.039648 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9595 11:08:12.046005 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9596 11:08:12.049443 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9597 11:08:12.056309 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9598 11:08:12.059943 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9599 11:08:12.063113 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9600 11:08:12.069294 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9601 11:08:12.072252 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9602 11:08:12.079360 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9603 11:08:12.081926 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9604 11:08:12.088991 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9605 11:08:12.091890 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9606 11:08:12.095756 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9607 11:08:12.102140 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9608 11:08:12.105500 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9609 11:08:12.111504 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9610 11:08:12.115310 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9611 11:08:12.122135 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9612 11:08:12.125169 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9613 11:08:12.128288 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9614 11:08:12.134605 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9615 11:08:12.138482 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9616 11:08:12.145583 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9617 11:08:12.148352 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9618 11:08:12.151725 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9619 11:08:12.158283 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9620 11:08:12.161102 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9621 11:08:12.167547 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9622 11:08:12.171040 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9623 11:08:12.177863 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9624 11:08:12.180806 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9625 11:08:12.187728 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9626 11:08:12.190907 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9627 11:08:12.193863 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9628 11:08:12.201221 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9629 11:08:12.204085 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9630 11:08:12.210234 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9631 11:08:12.214352 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9632 11:08:12.220603 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9633 11:08:12.223768 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9634 11:08:12.230372 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9635 11:08:12.233585 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9636 11:08:12.237017 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9637 11:08:12.243875 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9638 11:08:12.247527 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9639 11:08:12.253880 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9640 11:08:12.256813 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9641 11:08:12.263893 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9642 11:08:12.267013 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9643 11:08:12.273289 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9644 11:08:12.276804 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9645 11:08:12.279850 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9646 11:08:12.286511 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9647 11:08:12.289739 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9648 11:08:12.296543 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9649 11:08:12.299633 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9650 11:08:12.306505 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9651 11:08:12.309649 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9652 11:08:12.316143 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9653 11:08:12.320080 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9654 11:08:12.322708 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9655 11:08:12.329516 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9656 11:08:12.333026 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9657 11:08:12.339510 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9658 11:08:12.342466 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9659 11:08:12.349705 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9660 11:08:12.352241 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9661 11:08:12.355895 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9662 11:08:12.362432 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9663 11:08:12.365963 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9664 11:08:12.372007 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9665 11:08:12.376564 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9666 11:08:12.382791 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9667 11:08:12.385074 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9668 11:08:12.391915 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9669 11:08:12.395429 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9670 11:08:12.398516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9671 11:08:12.405882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9672 11:08:12.409129 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9673 11:08:12.414823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9674 11:08:12.418380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9675 11:08:12.424815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9676 11:08:12.429307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9677 11:08:12.435371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9678 11:08:12.438049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9679 11:08:12.444553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9680 11:08:12.448094 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9681 11:08:12.454556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9682 11:08:12.458523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9683 11:08:12.464914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9684 11:08:12.468128 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9685 11:08:12.474961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9686 11:08:12.478079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9687 11:08:12.484898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9688 11:08:12.487306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9689 11:08:12.494623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9690 11:08:12.498140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9691 11:08:12.503968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9692 11:08:12.507422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9693 11:08:12.513752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9694 11:08:12.517210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9695 11:08:12.523914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9696 11:08:12.528103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9697 11:08:12.533465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9698 11:08:12.536615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9699 11:08:12.543763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9700 11:08:12.547031 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9701 11:08:12.553464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9702 11:08:12.556549 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9703 11:08:12.559966 INFO: [APUAPC] vio 0
9704 11:08:12.563232 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9705 11:08:12.570347 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9706 11:08:12.573055 INFO: [APUAPC] D0_APC_0: 0x400510
9707 11:08:12.573475 INFO: [APUAPC] D0_APC_1: 0x0
9708 11:08:12.577369 INFO: [APUAPC] D0_APC_2: 0x1540
9709 11:08:12.580841 INFO: [APUAPC] D0_APC_3: 0x0
9710 11:08:12.583963 INFO: [APUAPC] D1_APC_0: 0xffffffff
9711 11:08:12.586318 INFO: [APUAPC] D1_APC_1: 0xffffffff
9712 11:08:12.590412 INFO: [APUAPC] D1_APC_2: 0x3fffff
9713 11:08:12.592894 INFO: [APUAPC] D1_APC_3: 0x0
9714 11:08:12.597049 INFO: [APUAPC] D2_APC_0: 0xffffffff
9715 11:08:12.599642 INFO: [APUAPC] D2_APC_1: 0xffffffff
9716 11:08:12.603377 INFO: [APUAPC] D2_APC_2: 0x3fffff
9717 11:08:12.606686 INFO: [APUAPC] D2_APC_3: 0x0
9718 11:08:12.610886 INFO: [APUAPC] D3_APC_0: 0xffffffff
9719 11:08:12.613763 INFO: [APUAPC] D3_APC_1: 0xffffffff
9720 11:08:12.616355 INFO: [APUAPC] D3_APC_2: 0x3fffff
9721 11:08:12.619948 INFO: [APUAPC] D3_APC_3: 0x0
9722 11:08:12.622776 INFO: [APUAPC] D4_APC_0: 0xffffffff
9723 11:08:12.625704 INFO: [APUAPC] D4_APC_1: 0xffffffff
9724 11:08:12.630167 INFO: [APUAPC] D4_APC_2: 0x3fffff
9725 11:08:12.632437 INFO: [APUAPC] D4_APC_3: 0x0
9726 11:08:12.636234 INFO: [APUAPC] D5_APC_0: 0xffffffff
9727 11:08:12.639350 INFO: [APUAPC] D5_APC_1: 0xffffffff
9728 11:08:12.642368 INFO: [APUAPC] D5_APC_2: 0x3fffff
9729 11:08:12.645414 INFO: [APUAPC] D5_APC_3: 0x0
9730 11:08:12.648766 INFO: [APUAPC] D6_APC_0: 0xffffffff
9731 11:08:12.652620 INFO: [APUAPC] D6_APC_1: 0xffffffff
9732 11:08:12.656393 INFO: [APUAPC] D6_APC_2: 0x3fffff
9733 11:08:12.659045 INFO: [APUAPC] D6_APC_3: 0x0
9734 11:08:12.662714 INFO: [APUAPC] D7_APC_0: 0xffffffff
9735 11:08:12.665527 INFO: [APUAPC] D7_APC_1: 0xffffffff
9736 11:08:12.668546 INFO: [APUAPC] D7_APC_2: 0x3fffff
9737 11:08:12.672610 INFO: [APUAPC] D7_APC_3: 0x0
9738 11:08:12.675306 INFO: [APUAPC] D8_APC_0: 0xffffffff
9739 11:08:12.678670 INFO: [APUAPC] D8_APC_1: 0xffffffff
9740 11:08:12.681723 INFO: [APUAPC] D8_APC_2: 0x3fffff
9741 11:08:12.684983 INFO: [APUAPC] D8_APC_3: 0x0
9742 11:08:12.688491 INFO: [APUAPC] D9_APC_0: 0xffffffff
9743 11:08:12.691870 INFO: [APUAPC] D9_APC_1: 0xffffffff
9744 11:08:12.695784 INFO: [APUAPC] D9_APC_2: 0x3fffff
9745 11:08:12.698495 INFO: [APUAPC] D9_APC_3: 0x0
9746 11:08:12.702743 INFO: [APUAPC] D10_APC_0: 0xffffffff
9747 11:08:12.704630 INFO: [APUAPC] D10_APC_1: 0xffffffff
9748 11:08:12.708468 INFO: [APUAPC] D10_APC_2: 0x3fffff
9749 11:08:12.712304 INFO: [APUAPC] D10_APC_3: 0x0
9750 11:08:12.714876 INFO: [APUAPC] D11_APC_0: 0xffffffff
9751 11:08:12.718710 INFO: [APUAPC] D11_APC_1: 0xffffffff
9752 11:08:12.721875 INFO: [APUAPC] D11_APC_2: 0x3fffff
9753 11:08:12.724540 INFO: [APUAPC] D11_APC_3: 0x0
9754 11:08:12.728057 INFO: [APUAPC] D12_APC_0: 0xffffffff
9755 11:08:12.731849 INFO: [APUAPC] D12_APC_1: 0xffffffff
9756 11:08:12.734668 INFO: [APUAPC] D12_APC_2: 0x3fffff
9757 11:08:12.738169 INFO: [APUAPC] D12_APC_3: 0x0
9758 11:08:12.741976 INFO: [APUAPC] D13_APC_0: 0xffffffff
9759 11:08:12.746483 INFO: [APUAPC] D13_APC_1: 0xffffffff
9760 11:08:12.747909 INFO: [APUAPC] D13_APC_2: 0x3fffff
9761 11:08:12.750698 INFO: [APUAPC] D13_APC_3: 0x0
9762 11:08:12.754293 INFO: [APUAPC] D14_APC_0: 0xffffffff
9763 11:08:12.757499 INFO: [APUAPC] D14_APC_1: 0xffffffff
9764 11:08:12.760650 INFO: [APUAPC] D14_APC_2: 0x3fffff
9765 11:08:12.764750 INFO: [APUAPC] D14_APC_3: 0x0
9766 11:08:12.767525 INFO: [APUAPC] D15_APC_0: 0xffffffff
9767 11:08:12.770976 INFO: [APUAPC] D15_APC_1: 0xffffffff
9768 11:08:12.774130 INFO: [APUAPC] D15_APC_2: 0x3fffff
9769 11:08:12.777340 INFO: [APUAPC] D15_APC_3: 0x0
9770 11:08:12.780662 INFO: [APUAPC] APC_CON: 0x4
9771 11:08:12.784511 INFO: [NOCDAPC] D0_APC_0: 0x0
9772 11:08:12.788047 INFO: [NOCDAPC] D0_APC_1: 0x0
9773 11:08:12.790495 INFO: [NOCDAPC] D1_APC_0: 0x0
9774 11:08:12.794549 INFO: [NOCDAPC] D1_APC_1: 0xfff
9775 11:08:12.795010 INFO: [NOCDAPC] D2_APC_0: 0x0
9776 11:08:12.797174 INFO: [NOCDAPC] D2_APC_1: 0xfff
9777 11:08:12.800862 INFO: [NOCDAPC] D3_APC_0: 0x0
9778 11:08:12.804005 INFO: [NOCDAPC] D3_APC_1: 0xfff
9779 11:08:12.807831 INFO: [NOCDAPC] D4_APC_0: 0x0
9780 11:08:12.810516 INFO: [NOCDAPC] D4_APC_1: 0xfff
9781 11:08:12.813544 INFO: [NOCDAPC] D5_APC_0: 0x0
9782 11:08:12.817727 INFO: [NOCDAPC] D5_APC_1: 0xfff
9783 11:08:12.820345 INFO: [NOCDAPC] D6_APC_0: 0x0
9784 11:08:12.823764 INFO: [NOCDAPC] D6_APC_1: 0xfff
9785 11:08:12.827595 INFO: [NOCDAPC] D7_APC_0: 0x0
9786 11:08:12.830706 INFO: [NOCDAPC] D7_APC_1: 0xfff
9787 11:08:12.831266 INFO: [NOCDAPC] D8_APC_0: 0x0
9788 11:08:12.833732 INFO: [NOCDAPC] D8_APC_1: 0xfff
9789 11:08:12.836651 INFO: [NOCDAPC] D9_APC_0: 0x0
9790 11:08:12.841169 INFO: [NOCDAPC] D9_APC_1: 0xfff
9791 11:08:12.843888 INFO: [NOCDAPC] D10_APC_0: 0x0
9792 11:08:12.846837 INFO: [NOCDAPC] D10_APC_1: 0xfff
9793 11:08:12.850233 INFO: [NOCDAPC] D11_APC_0: 0x0
9794 11:08:12.853408 INFO: [NOCDAPC] D11_APC_1: 0xfff
9795 11:08:12.856791 INFO: [NOCDAPC] D12_APC_0: 0x0
9796 11:08:12.859968 INFO: [NOCDAPC] D12_APC_1: 0xfff
9797 11:08:12.863746 INFO: [NOCDAPC] D13_APC_0: 0x0
9798 11:08:12.867053 INFO: [NOCDAPC] D13_APC_1: 0xfff
9799 11:08:12.869817 INFO: [NOCDAPC] D14_APC_0: 0x0
9800 11:08:12.873968 INFO: [NOCDAPC] D14_APC_1: 0xfff
9801 11:08:12.877330 INFO: [NOCDAPC] D15_APC_0: 0x0
9802 11:08:12.877886 INFO: [NOCDAPC] D15_APC_1: 0xfff
9803 11:08:12.880794 INFO: [NOCDAPC] APC_CON: 0x4
9804 11:08:12.883201 INFO: [APUAPC] set_apusys_apc done
9805 11:08:12.886598 INFO: [DEVAPC] devapc_init done
9806 11:08:12.892623 INFO: GICv3 without legacy support detected.
9807 11:08:12.896154 INFO: ARM GICv3 driver initialized in EL3
9808 11:08:12.899280 INFO: Maximum SPI INTID supported: 639
9809 11:08:12.902850 INFO: BL31: Initializing runtime services
9810 11:08:12.909796 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9811 11:08:12.912763 INFO: SPM: enable CPC mode
9812 11:08:12.916112 INFO: mcdi ready for mcusys-off-idle and system suspend
9813 11:08:12.922461 INFO: BL31: Preparing for EL3 exit to normal world
9814 11:08:12.925943 INFO: Entry point address = 0x80000000
9815 11:08:12.926499 INFO: SPSR = 0x8
9816 11:08:12.933204
9817 11:08:12.933756
9818 11:08:12.934122
9819 11:08:12.936385 Starting depthcharge on Spherion...
9820 11:08:12.936980
9821 11:08:12.937353 Wipe memory regions:
9822 11:08:12.937698
9823 11:08:12.940351 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9824 11:08:12.940938 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9825 11:08:12.941393 Setting prompt string to ['asurada:']
9826 11:08:12.941837 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9827 11:08:12.942555 [0x00000040000000, 0x00000054600000)
9828 11:08:13.061799
9829 11:08:13.062346 [0x00000054660000, 0x00000080000000)
9830 11:08:13.322583
9831 11:08:13.323135 [0x000000821a7280, 0x000000ffe64000)
9832 11:08:14.067389
9833 11:08:14.067947 [0x00000100000000, 0x00000140000000)
9834 11:08:14.447791
9835 11:08:14.451192 Initializing XHCI USB controller at 0x11200000.
9836 11:08:15.489279
9837 11:08:15.492146 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9838 11:08:15.492569
9839 11:08:15.492972
9840 11:08:15.493289
9841 11:08:15.494070 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9843 11:08:15.595181 asurada: tftpboot 192.168.201.1 12925646/tftp-deploy-n7u47uue/kernel/image.itb 12925646/tftp-deploy-n7u47uue/kernel/cmdline
9844 11:08:15.595787 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9845 11:08:15.596176 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9846 11:08:15.600386 tftpboot 192.168.201.1 12925646/tftp-deploy-n7u47uue/kernel/image.itp-deploy-n7u47uue/kernel/cmdline
9847 11:08:15.600876
9848 11:08:15.601227 Waiting for link
9849 11:08:15.761182
9850 11:08:15.761745 R8152: Initializing
9851 11:08:15.762170
9852 11:08:15.764473 Version 9 (ocp_data = 6010)
9853 11:08:15.764989
9854 11:08:15.767561 R8152: Done initializing
9855 11:08:15.768018
9856 11:08:15.768382 Adding net device
9857 11:08:17.777440
9858 11:08:17.777994 done.
9859 11:08:17.778355
9860 11:08:17.778691 MAC: 00:e0:4c:68:03:bd
9861 11:08:17.779071
9862 11:08:17.779994 Sending DHCP discover... done.
9863 11:08:17.780375
9864 11:08:21.117020 Waiting for reply... done.
9865 11:08:21.117524
9866 11:08:21.117874 Sending DHCP request... done.
9867 11:08:21.119671
9868 11:08:21.123888 Waiting for reply... done.
9869 11:08:21.124307
9870 11:08:21.124653 My ip is 192.168.201.16
9871 11:08:21.125025
9872 11:08:21.127487 The DHCP server ip is 192.168.201.1
9873 11:08:21.127909
9874 11:08:21.133739 TFTP server IP predefined by user: 192.168.201.1
9875 11:08:21.134167
9876 11:08:21.140593 Bootfile predefined by user: 12925646/tftp-deploy-n7u47uue/kernel/image.itb
9877 11:08:21.141087
9878 11:08:21.143825 Sending tftp read request... done.
9879 11:08:21.144287
9880 11:08:21.150605 Waiting for the transfer...
9881 11:08:21.151026
9882 11:08:21.470201 00000000 ################################################################
9883 11:08:21.470351
9884 11:08:21.747569 00080000 ################################################################
9885 11:08:21.747721
9886 11:08:22.023452 00100000 ################################################################
9887 11:08:22.023580
9888 11:08:22.307334 00180000 ################################################################
9889 11:08:22.307482
9890 11:08:22.560867 00200000 ################################################################
9891 11:08:22.561001
9892 11:08:22.810469 00280000 ################################################################
9893 11:08:22.810620
9894 11:08:23.060986 00300000 ################################################################
9895 11:08:23.061119
9896 11:08:23.317105 00380000 ################################################################
9897 11:08:23.317249
9898 11:08:23.565923 00400000 ################################################################
9899 11:08:23.566055
9900 11:08:23.815219 00480000 ################################################################
9901 11:08:23.815353
9902 11:08:24.066115 00500000 ################################################################
9903 11:08:24.066246
9904 11:08:24.323364 00580000 ################################################################
9905 11:08:24.323502
9906 11:08:24.571213 00600000 ################################################################
9907 11:08:24.571346
9908 11:08:24.818749 00680000 ################################################################
9909 11:08:24.818880
9910 11:08:25.066989 00700000 ################################################################
9911 11:08:25.067124
9912 11:08:25.316482 00780000 ################################################################
9913 11:08:25.316618
9914 11:08:25.564348 00800000 ################################################################
9915 11:08:25.564493
9916 11:08:25.812055 00880000 ################################################################
9917 11:08:25.812181
9918 11:08:26.059197 00900000 ################################################################
9919 11:08:26.059328
9920 11:08:26.307008 00980000 ################################################################
9921 11:08:26.307139
9922 11:08:26.555811 00a00000 ################################################################
9923 11:08:26.555943
9924 11:08:26.810857 00a80000 ################################################################
9925 11:08:26.811015
9926 11:08:27.059236 00b00000 ################################################################
9927 11:08:27.059362
9928 11:08:27.306172 00b80000 ################################################################
9929 11:08:27.306302
9930 11:08:27.554555 00c00000 ################################################################
9931 11:08:27.554695
9932 11:08:27.810606 00c80000 ################################################################
9933 11:08:27.810735
9934 11:08:28.065724 00d00000 ################################################################
9935 11:08:28.065857
9936 11:08:28.323793 00d80000 ################################################################
9937 11:08:28.323924
9938 11:08:28.576253 00e00000 ################################################################
9939 11:08:28.576380
9940 11:08:28.824569 00e80000 ################################################################
9941 11:08:28.824768
9942 11:08:29.073303 00f00000 ################################################################
9943 11:08:29.073436
9944 11:08:29.321901 00f80000 ################################################################
9945 11:08:29.322027
9946 11:08:29.570345 01000000 ################################################################
9947 11:08:29.570479
9948 11:08:29.818426 01080000 ################################################################
9949 11:08:29.818558
9950 11:08:30.066448 01100000 ################################################################
9951 11:08:30.066579
9952 11:08:30.314859 01180000 ################################################################
9953 11:08:30.314992
9954 11:08:30.562866 01200000 ################################################################
9955 11:08:30.562996
9956 11:08:30.820148 01280000 ################################################################
9957 11:08:30.820282
9958 11:08:31.074551 01300000 ################################################################
9959 11:08:31.074686
9960 11:08:31.323545 01380000 ################################################################
9961 11:08:31.323680
9962 11:08:31.572737 01400000 ################################################################
9963 11:08:31.572875
9964 11:08:31.822902 01480000 ################################################################
9965 11:08:31.823041
9966 11:08:32.073865 01500000 ################################################################
9967 11:08:32.074003
9968 11:08:32.325508 01580000 ################################################################
9969 11:08:32.325647
9970 11:08:32.575873 01600000 ################################################################
9971 11:08:32.576020
9972 11:08:32.825596 01680000 ################################################################
9973 11:08:32.825738
9974 11:08:33.076609 01700000 ################################################################
9975 11:08:33.076754
9976 11:08:33.327528 01780000 ################################################################
9977 11:08:33.327671
9978 11:08:33.578093 01800000 ################################################################
9979 11:08:33.578244
9980 11:08:33.829046 01880000 ################################################################
9981 11:08:33.829184
9982 11:08:34.079480 01900000 ################################################################
9983 11:08:34.079614
9984 11:08:34.333596 01980000 ################################################################
9985 11:08:34.333737
9986 11:08:34.585463 01a00000 ################################################################
9987 11:08:34.585617
9988 11:08:34.835799 01a80000 ################################################################
9989 11:08:34.835933
9990 11:08:35.087182 01b00000 ################################################################
9991 11:08:35.087316
9992 11:08:35.337957 01b80000 ################################################################
9993 11:08:35.338095
9994 11:08:35.589322 01c00000 ################################################################
9995 11:08:35.589466
9996 11:08:35.601708 01c80000 #### done.
9997 11:08:35.601792
9998 11:08:35.607364 The bootfile was 29911294 bytes long.
9999 11:08:35.607507
10000 11:08:35.608400 Sending tftp read request... done.
10001 11:08:35.608488
10002 11:08:35.611522 Waiting for the transfer...
10003 11:08:35.611631
10004 11:08:35.611747 00000000 # done.
10005 11:08:35.611867
10006 11:08:35.621062 Command line loaded dynamically from TFTP file: 12925646/tftp-deploy-n7u47uue/kernel/cmdline
10007 11:08:35.621179
10008 11:08:35.641355 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12925646/extract-nfsrootfs-3abnc__8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10009 11:08:35.641629
10010 11:08:35.645292 Loading FIT.
10011 11:08:35.645586
10012 11:08:35.648217 Image ramdisk-1 has 17804281 bytes.
10013 11:08:35.648510
10014 11:08:35.648790 Image fdt-1 has 47278 bytes.
10015 11:08:35.649010
10016 11:08:35.651039 Image kernel-1 has 12057697 bytes.
10017 11:08:35.651382
10018 11:08:35.661175 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10019 11:08:35.661579
10020 11:08:35.678912 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10021 11:08:35.679554
10022 11:08:35.685073 Choosing best match conf-1 for compat google,spherion-rev3.
10023 11:08:35.688928
10024 11:08:35.693895 Connected to device vid:did:rid of 1ae0:0028:00
10025 11:08:35.700103
10026 11:08:35.703935 tpm_get_response: command 0x17b, return code 0x0
10027 11:08:35.704653
10028 11:08:35.706523 ec_init: CrosEC protocol v3 supported (256, 248)
10029 11:08:35.712212
10030 11:08:35.714076 tpm_cleanup: add release locality here.
10031 11:08:35.714543
10032 11:08:35.714915 Shutting down all USB controllers.
10033 11:08:35.717187
10034 11:08:35.717668 Removing current net device
10035 11:08:35.718050
10036 11:08:35.723962 Exiting depthcharge with code 4 at timestamp: 51060544
10037 11:08:35.724427
10038 11:08:35.726956 LZMA decompressing kernel-1 to 0x821a6718
10039 11:08:35.727421
10040 11:08:35.730216 LZMA decompressing kernel-1 to 0x40000000
10041 11:08:37.229740
10042 11:08:37.229904 jumping to kernel
10043 11:08:37.230387 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10044 11:08:37.230494 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10045 11:08:37.230582 Setting prompt string to ['Linux version [0-9]']
10046 11:08:37.230665 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10047 11:08:37.230796 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10048 11:08:37.279746
10049 11:08:37.283911 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10050 11:08:37.286840 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10051 11:08:37.287231 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10052 11:08:37.287476 Setting prompt string to []
10053 11:08:37.287732 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10054 11:08:37.287978 Using line separator: #'\n'#
10055 11:08:37.288178 No login prompt set.
10056 11:08:37.288391 Parsing kernel messages
10057 11:08:37.288583 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10058 11:08:37.288960 [login-action] Waiting for messages, (timeout 00:04:02)
10059 11:08:37.289185 Waiting using forced prompt support (timeout 00:02:01)
10060 11:08:37.308176 [ 0.000000] Linux version 6.1.80-cip16 (KernelCI@build-j128891-arm64-gcc-10-defconfig-arm64-chromebook-nrg4h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024
10061 11:08:37.309531 [ 0.000000] random: crng init done
10062 11:08:37.317672 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10063 11:08:37.319308 [ 0.000000] efi: UEFI not found.
10064 11:08:37.325872 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10065 11:08:37.333327 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10066 11:08:37.343550 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10067 11:08:37.352975 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10068 11:08:37.359239 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10069 11:08:37.365990 [ 0.000000] printk: bootconsole [mtk8250] enabled
10070 11:08:37.372951 [ 0.000000] NUMA: No NUMA configuration found
10071 11:08:37.379517 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10072 11:08:37.382475 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10073 11:08:37.386055 [ 0.000000] Zone ranges:
10074 11:08:37.392690 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10075 11:08:37.396253 [ 0.000000] DMA32 empty
10076 11:08:37.402231 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10077 11:08:37.405670 [ 0.000000] Movable zone start for each node
10078 11:08:37.409164 [ 0.000000] Early memory node ranges
10079 11:08:37.416314 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10080 11:08:37.423235 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10081 11:08:37.428556 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10082 11:08:37.435413 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10083 11:08:37.442120 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10084 11:08:37.449392 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10085 11:08:37.479292 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10086 11:08:37.485635 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10087 11:08:37.492509 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10088 11:08:37.495418 [ 0.000000] psci: probing for conduit method from DT.
10089 11:08:37.501776 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10090 11:08:37.505533 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10091 11:08:37.512294 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10092 11:08:37.515337 [ 0.000000] psci: SMC Calling Convention v1.2
10093 11:08:37.521821 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10094 11:08:37.525009 [ 0.000000] Detected VIPT I-cache on CPU0
10095 11:08:37.532332 [ 0.000000] CPU features: detected: GIC system register CPU interface
10096 11:08:37.538274 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10097 11:08:37.544683 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10098 11:08:37.551966 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10099 11:08:37.563255 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10100 11:08:37.567933 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10101 11:08:37.572138 [ 0.000000] alternatives: applying boot alternatives
10102 11:08:37.578130 [ 0.000000] Fallback order for Node 0: 0
10103 11:08:37.585238 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10104 11:08:37.587647 [ 0.000000] Policy zone: Normal
10105 11:08:37.610826 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12925646/extract-nfsrootfs-3abnc__8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10106 11:08:37.620475 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10107 11:08:37.631370 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10108 11:08:37.637594 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10109 11:08:37.643964 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10110 11:08:37.650610 <6>[ 0.000000] software IO TLB: area num 8.
10111 11:08:37.705446 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10112 11:08:37.785829 <6>[ 0.000000] Memory: 3835392K/4191232K available (18048K kernel code, 4118K rwdata, 19616K rodata, 8448K init, 616K bss, 323072K reserved, 32768K cma-reserved)
10113 11:08:37.793316 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10114 11:08:37.799839 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10115 11:08:37.802443 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10116 11:08:37.809447 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10117 11:08:37.816310 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10118 11:08:37.818874 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10119 11:08:37.828759 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10120 11:08:37.835331 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10121 11:08:37.841699 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10122 11:08:37.849036 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10123 11:08:37.851738 <6>[ 0.000000] GICv3: 608 SPIs implemented
10124 11:08:37.855258 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10125 11:08:37.861524 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10126 11:08:37.865096 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10127 11:08:37.872058 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10128 11:08:37.885154 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10129 11:08:37.897929 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10130 11:08:37.904750 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10131 11:08:37.912168 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10132 11:08:37.925496 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10133 11:08:37.933024 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10134 11:08:37.939059 <6>[ 0.009229] Console: colour dummy device 80x25
10135 11:08:37.948834 <6>[ 0.013957] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10136 11:08:37.955113 <6>[ 0.024399] pid_max: default: 32768 minimum: 301
10137 11:08:37.959171 <6>[ 0.029302] LSM: Security Framework initializing
10138 11:08:37.965748 <6>[ 0.034248] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10139 11:08:37.976684 <6>[ 0.041902] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10140 11:08:37.982013 <6>[ 0.051136] cblist_init_generic: Setting adjustable number of callback queues.
10141 11:08:37.988892 <6>[ 0.058625] cblist_init_generic: Setting shift to 3 and lim to 1.
10142 11:08:37.998558 <6>[ 0.064963] cblist_init_generic: Setting adjustable number of callback queues.
10143 11:08:38.002175 <6>[ 0.072390] cblist_init_generic: Setting shift to 3 and lim to 1.
10144 11:08:38.008335 <6>[ 0.078793] rcu: Hierarchical SRCU implementation.
10145 11:08:38.015020 <6>[ 0.083839] rcu: Max phase no-delay instances is 1000.
10146 11:08:38.021411 <6>[ 0.090863] EFI services will not be available.
10147 11:08:38.025444 <6>[ 0.095820] smp: Bringing up secondary CPUs ...
10148 11:08:38.032688 <6>[ 0.100874] Detected VIPT I-cache on CPU1
10149 11:08:38.040587 <6>[ 0.100944] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10150 11:08:38.046985 <6>[ 0.100976] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10151 11:08:38.049990 <6>[ 0.101307] Detected VIPT I-cache on CPU2
10152 11:08:38.056331 <6>[ 0.101354] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10153 11:08:38.065875 <6>[ 0.101369] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10154 11:08:38.069399 <6>[ 0.101627] Detected VIPT I-cache on CPU3
10155 11:08:38.075726 <6>[ 0.101673] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10156 11:08:38.082485 <6>[ 0.101687] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10157 11:08:38.086523 <6>[ 0.101993] CPU features: detected: Spectre-v4
10158 11:08:38.092424 <6>[ 0.102000] CPU features: detected: Spectre-BHB
10159 11:08:38.095485 <6>[ 0.102005] Detected PIPT I-cache on CPU4
10160 11:08:38.103042 <6>[ 0.102061] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10161 11:08:38.108510 <6>[ 0.102078] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10162 11:08:38.115328 <6>[ 0.102371] Detected PIPT I-cache on CPU5
10163 11:08:38.121675 <6>[ 0.102432] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10164 11:08:38.128311 <6>[ 0.102448] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10165 11:08:38.131721 <6>[ 0.102728] Detected PIPT I-cache on CPU6
10166 11:08:38.138742 <6>[ 0.102791] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10167 11:08:38.146280 <6>[ 0.102806] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10168 11:08:38.151658 <6>[ 0.103103] Detected PIPT I-cache on CPU7
10169 11:08:38.158406 <6>[ 0.103168] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10170 11:08:38.164785 <6>[ 0.103184] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10171 11:08:38.168339 <6>[ 0.103231] smp: Brought up 1 node, 8 CPUs
10172 11:08:38.175411 <6>[ 0.244620] SMP: Total of 8 processors activated.
10173 11:08:38.177671 <6>[ 0.249541] CPU features: detected: 32-bit EL0 Support
10174 11:08:38.187873 <6>[ 0.254904] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10175 11:08:38.195166 <6>[ 0.263704] CPU features: detected: Common not Private translations
10176 11:08:38.201281 <6>[ 0.270180] CPU features: detected: CRC32 instructions
10177 11:08:38.207552 <6>[ 0.275564] CPU features: detected: RCpc load-acquire (LDAPR)
10178 11:08:38.210837 <6>[ 0.281561] CPU features: detected: LSE atomic instructions
10179 11:08:38.217378 <6>[ 0.287343] CPU features: detected: Privileged Access Never
10180 11:08:38.224165 <6>[ 0.293122] CPU features: detected: RAS Extension Support
10181 11:08:38.230695 <6>[ 0.298730] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10182 11:08:38.234051 <6>[ 0.305943] CPU: All CPU(s) started at EL2
10183 11:08:38.240871 <6>[ 0.310286] alternatives: applying system-wide alternatives
10184 11:08:38.250834 <6>[ 0.320247] devtmpfs: initialized
10185 11:08:38.264701 <6>[ 0.328616] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10186 11:08:38.271661 <6>[ 0.338578] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10187 11:08:38.278437 <6>[ 0.346612] pinctrl core: initialized pinctrl subsystem
10188 11:08:38.280957 <6>[ 0.353299] DMI not present or invalid.
10189 11:08:38.288177 <6>[ 0.357702] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10190 11:08:38.297722 <6>[ 0.364542] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10191 11:08:38.304439 <6>[ 0.371992] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10192 11:08:38.315008 <6>[ 0.380081] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10193 11:08:38.317757 <6>[ 0.388238] audit: initializing netlink subsys (disabled)
10194 11:08:38.328660 <5>[ 0.393936] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10195 11:08:38.334687 <6>[ 0.394647] thermal_sys: Registered thermal governor 'step_wise'
10196 11:08:38.340946 <6>[ 0.401902] thermal_sys: Registered thermal governor 'power_allocator'
10197 11:08:38.344393 <6>[ 0.408158] cpuidle: using governor menu
10198 11:08:38.350625 <6>[ 0.419118] NET: Registered PF_QIPCRTR protocol family
10199 11:08:38.357582 <6>[ 0.424612] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10200 11:08:38.360402 <6>[ 0.431713] ASID allocator initialised with 32768 entries
10201 11:08:38.368820 <6>[ 0.438264] Serial: AMBA PL011 UART driver
10202 11:08:38.379527 <4>[ 0.447047] Trying to register duplicate clock ID: 134
10203 11:08:38.433561 <6>[ 0.506735] KASLR enabled
10204 11:08:38.448155 <6>[ 0.514615] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10205 11:08:38.454730 <6>[ 0.521629] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10206 11:08:38.460695 <6>[ 0.528118] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10207 11:08:38.467089 <6>[ 0.535125] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10208 11:08:38.475641 <6>[ 0.541613] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10209 11:08:38.480415 <6>[ 0.548617] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10210 11:08:38.486953 <6>[ 0.555103] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10211 11:08:38.493446 <6>[ 0.562108] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10212 11:08:38.497551 <6>[ 0.569622] ACPI: Interpreter disabled.
10213 11:08:38.505837 <6>[ 0.576026] iommu: Default domain type: Translated
10214 11:08:38.511764 <6>[ 0.581140] iommu: DMA domain TLB invalidation policy: strict mode
10215 11:08:38.515214 <5>[ 0.587804] SCSI subsystem initialized
10216 11:08:38.521312 <6>[ 0.591972] usbcore: registered new interface driver usbfs
10217 11:08:38.528048 <6>[ 0.597706] usbcore: registered new interface driver hub
10218 11:08:38.531756 <6>[ 0.603259] usbcore: registered new device driver usb
10219 11:08:38.539536 <6>[ 0.609364] pps_core: LinuxPPS API ver. 1 registered
10220 11:08:38.549187 <6>[ 0.614559] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10221 11:08:38.551358 <6>[ 0.623908] PTP clock support registered
10222 11:08:38.554728 <6>[ 0.628148] EDAC MC: Ver: 3.0.0
10223 11:08:38.562479 <6>[ 0.633293] FPGA manager framework
10224 11:08:38.568940 <6>[ 0.636976] Advanced Linux Sound Architecture Driver Initialized.
10225 11:08:38.572135 <6>[ 0.643755] vgaarb: loaded
10226 11:08:38.579564 <6>[ 0.646907] clocksource: Switched to clocksource arch_sys_counter
10227 11:08:38.582403 <5>[ 0.653346] VFS: Disk quotas dquot_6.6.0
10228 11:08:38.589198 <6>[ 0.657531] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10229 11:08:38.591947 <6>[ 0.664722] pnp: PnP ACPI: disabled
10230 11:08:38.600883 <6>[ 0.671402] NET: Registered PF_INET protocol family
10231 11:08:38.607387 <6>[ 0.676784] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10232 11:08:38.619491 <6>[ 0.686801] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10233 11:08:38.629277 <6>[ 0.695591] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10234 11:08:38.635803 <6>[ 0.703558] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10235 11:08:38.642178 <6>[ 0.711961] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10236 11:08:38.652830 <6>[ 0.720618] TCP: Hash tables configured (established 32768 bind 32768)
10237 11:08:38.659872 <6>[ 0.727479] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10238 11:08:38.666262 <6>[ 0.734496] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10239 11:08:38.672484 <6>[ 0.741994] NET: Registered PF_UNIX/PF_LOCAL protocol family
10240 11:08:38.679264 <6>[ 0.748142] RPC: Registered named UNIX socket transport module.
10241 11:08:38.682815 <6>[ 0.754295] RPC: Registered udp transport module.
10242 11:08:38.688927 <6>[ 0.759227] RPC: Registered tcp transport module.
10243 11:08:38.696551 <6>[ 0.764156] RPC: Registered tcp NFSv4.1 backchannel transport module.
10244 11:08:38.699081 <6>[ 0.770821] PCI: CLS 0 bytes, default 64
10245 11:08:38.702131 <6>[ 0.775132] Unpacking initramfs...
10246 11:08:38.726961 <6>[ 0.794997] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10247 11:08:38.736983 <6>[ 0.803655] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10248 11:08:38.740334 <6>[ 0.812497] kvm [1]: IPA Size Limit: 40 bits
10249 11:08:38.746767 <6>[ 0.817023] kvm [1]: GICv3: no GICV resource entry
10250 11:08:38.749996 <6>[ 0.822046] kvm [1]: disabling GICv2 emulation
10251 11:08:38.757135 <6>[ 0.826731] kvm [1]: GIC system register CPU interface enabled
10252 11:08:38.760021 <6>[ 0.832888] kvm [1]: vgic interrupt IRQ18
10253 11:08:38.767029 <6>[ 0.837238] kvm [1]: VHE mode initialized successfully
10254 11:08:38.773689 <5>[ 0.843747] Initialise system trusted keyrings
10255 11:08:38.779861 <6>[ 0.848570] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10256 11:08:38.788236 <6>[ 0.858772] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10257 11:08:38.794162 <5>[ 0.865165] NFS: Registering the id_resolver key type
10258 11:08:38.797501 <5>[ 0.870482] Key type id_resolver registered
10259 11:08:38.804508 <5>[ 0.874899] Key type id_legacy registered
10260 11:08:38.810763 <6>[ 0.879180] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10261 11:08:38.817594 <6>[ 0.886099] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10262 11:08:38.823777 <6>[ 0.893824] 9p: Installing v9fs 9p2000 file system support
10263 11:08:38.860375 <5>[ 0.931389] Key type asymmetric registered
10264 11:08:38.863391 <5>[ 0.935720] Asymmetric key parser 'x509' registered
10265 11:08:38.873346 <6>[ 0.940887] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10266 11:08:38.876523 <6>[ 0.948503] io scheduler mq-deadline registered
10267 11:08:38.879765 <6>[ 0.953279] io scheduler kyber registered
10268 11:08:38.899294 <6>[ 0.970188] EINJ: ACPI disabled.
10269 11:08:38.931670 <4>[ 0.995826] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10270 11:08:38.941061 <4>[ 1.006468] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10271 11:08:38.956125 <6>[ 1.027573] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10272 11:08:38.964330 <6>[ 1.035696] printk: console [ttyS0] disabled
10273 11:08:38.992980 <6>[ 1.060324] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10274 11:08:38.999315 <6>[ 1.069799] printk: console [ttyS0] enabled
10275 11:08:39.004369 <6>[ 1.069799] printk: console [ttyS0] enabled
10276 11:08:39.009875 <6>[ 1.078691] printk: bootconsole [mtk8250] disabled
10277 11:08:39.012680 <6>[ 1.078691] printk: bootconsole [mtk8250] disabled
10278 11:08:39.019553 <6>[ 1.090058] SuperH (H)SCI(F) driver initialized
10279 11:08:39.022942 <6>[ 1.095372] msm_serial: driver initialized
10280 11:08:39.036870 <6>[ 1.104412] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10281 11:08:39.047107 <6>[ 1.112959] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10282 11:08:39.053500 <6>[ 1.121502] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10283 11:08:39.063528 <6>[ 1.130131] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10284 11:08:39.073388 <6>[ 1.138837] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10285 11:08:39.080395 <6>[ 1.147559] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10286 11:08:39.089688 <6>[ 1.156099] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10287 11:08:39.096617 <6>[ 1.164901] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10288 11:08:39.106533 <6>[ 1.173449] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10289 11:08:39.115178 <6>[ 1.189286] loop: module loaded
10290 11:08:39.124015 <6>[ 1.195220] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10291 11:08:39.148345 <4>[ 1.218851] mtk-pmic-keys: Failed to locate of_node [id: -1]
10292 11:08:39.155538 <6>[ 1.226051] megasas: 07.719.03.00-rc1
10293 11:08:39.165583 <6>[ 1.235953] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10294 11:08:39.171957 <6>[ 1.242292] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10295 11:08:39.189767 <6>[ 1.258800] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10296 11:08:39.245916 <6>[ 1.308470] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10297 11:08:39.443667 <6>[ 1.514021] Freeing initrd memory: 17384K
10298 11:08:39.454656 <6>[ 1.524385] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10299 11:08:39.465731 <6>[ 1.535508] tun: Universal TUN/TAP device driver, 1.6
10300 11:08:39.468952 <6>[ 1.541573] thunder_xcv, ver 1.0
10301 11:08:39.472240 <6>[ 1.545081] thunder_bgx, ver 1.0
10302 11:08:39.475866 <6>[ 1.548581] nicpf, ver 1.0
10303 11:08:39.487332 <6>[ 1.552608] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10304 11:08:39.489429 <6>[ 1.560085] hns3: Copyright (c) 2017 Huawei Corporation.
10305 11:08:39.495356 <6>[ 1.565678] hclge is initializing
10306 11:08:39.498393 <6>[ 1.569265] e1000: Intel(R) PRO/1000 Network Driver
10307 11:08:39.505417 <6>[ 1.574396] e1000: Copyright (c) 1999-2006 Intel Corporation.
10308 11:08:39.508664 <6>[ 1.580410] e1000e: Intel(R) PRO/1000 Network Driver
10309 11:08:39.516321 <6>[ 1.585625] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10310 11:08:39.521811 <6>[ 1.591810] igb: Intel(R) Gigabit Ethernet Network Driver
10311 11:08:39.528551 <6>[ 1.597461] igb: Copyright (c) 2007-2014 Intel Corporation.
10312 11:08:39.535227 <6>[ 1.603299] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10313 11:08:39.542045 <6>[ 1.609817] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10314 11:08:39.544935 <6>[ 1.616282] sky2: driver version 1.30
10315 11:08:39.552942 <6>[ 1.621288] VFIO - User Level meta-driver version: 0.3
10316 11:08:39.560319 <6>[ 1.629516] usbcore: registered new interface driver usb-storage
10317 11:08:39.565405 <6>[ 1.635960] usbcore: registered new device driver onboard-usb-hub
10318 11:08:39.575587 <6>[ 1.645145] mt6397-rtc mt6359-rtc: registered as rtc0
10319 11:08:39.584485 <6>[ 1.650613] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T11:08:41 UTC (1709464121)
10320 11:08:39.588854 <6>[ 1.660182] i2c_dev: i2c /dev entries driver
10321 11:08:39.606136 <6>[ 1.672024] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10322 11:08:39.625625 <6>[ 1.696000] cpu cpu0: EM: created perf domain
10323 11:08:39.628447 <6>[ 1.700900] cpu cpu4: EM: created perf domain
10324 11:08:39.636569 <6>[ 1.706432] sdhci: Secure Digital Host Controller Interface driver
10325 11:08:39.642671 <6>[ 1.712864] sdhci: Copyright(c) Pierre Ossman
10326 11:08:39.649203 <6>[ 1.717782] Synopsys Designware Multimedia Card Interface Driver
10327 11:08:39.655751 <6>[ 1.724377] sdhci-pltfm: SDHCI platform and OF driver helper
10328 11:08:39.659312 <6>[ 1.724538] mmc0: CQHCI version 5.10
10329 11:08:39.666039 <6>[ 1.734372] ledtrig-cpu: registered to indicate activity on CPUs
10330 11:08:39.673141 <6>[ 1.741250] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10331 11:08:39.679579 <6>[ 1.748273] usbcore: registered new interface driver usbhid
10332 11:08:39.682619 <6>[ 1.754095] usbhid: USB HID core driver
10333 11:08:39.689865 <6>[ 1.758296] spi_master spi0: will run message pump with realtime priority
10334 11:08:39.730615 <6>[ 1.794350] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10335 11:08:39.749046 <6>[ 1.809668] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10336 11:08:39.753317 <6>[ 1.823292] mmc0: Command Queue Engine enabled
10337 11:08:39.759609 <6>[ 1.828069] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10338 11:08:39.766120 <6>[ 1.834983] cros-ec-spi spi0.0: Chrome EC device registered
10339 11:08:39.769206 <6>[ 1.835244] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10340 11:08:39.780186 <6>[ 1.850581] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10341 11:08:39.787596 <6>[ 1.857843] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10342 11:08:39.794437 <6>[ 1.863886] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10343 11:08:39.804507 <6>[ 1.867379] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10344 11:08:39.810538 <6>[ 1.869768] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10345 11:08:39.813995 <6>[ 1.879453] NET: Registered PF_PACKET protocol family
10346 11:08:39.820375 <6>[ 1.890319] 9pnet: Installing 9P2000 support
10347 11:08:39.823689 <5>[ 1.894879] Key type dns_resolver registered
10348 11:08:39.826737 <6>[ 1.899823] registered taskstats version 1
10349 11:08:39.834628 <5>[ 1.904218] Loading compiled-in X.509 certificates
10350 11:08:39.861257 <4>[ 1.925518] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10351 11:08:39.871366 <4>[ 1.936231] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10352 11:08:39.877824 <3>[ 1.946784] debugfs: File 'uA_load' in directory '/' already present!
10353 11:08:39.885676 <3>[ 1.953532] debugfs: File 'min_uV' in directory '/' already present!
10354 11:08:39.891263 <3>[ 1.960143] debugfs: File 'max_uV' in directory '/' already present!
10355 11:08:39.898005 <3>[ 1.966749] debugfs: File 'constraint_flags' in directory '/' already present!
10356 11:08:39.910939 <3>[ 1.978074] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10357 11:08:39.923997 <6>[ 1.994055] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10358 11:08:39.930482 <6>[ 2.000790] xhci-mtk 11200000.usb: xHCI Host Controller
10359 11:08:39.936530 <6>[ 2.006291] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10360 11:08:39.947083 <6>[ 2.014229] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10361 11:08:39.953444 <6>[ 2.023671] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10362 11:08:39.960910 <6>[ 2.029741] xhci-mtk 11200000.usb: xHCI Host Controller
10363 11:08:39.966708 <6>[ 2.035220] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10364 11:08:39.973620 <6>[ 2.042867] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10365 11:08:39.979931 <6>[ 2.050637] hub 1-0:1.0: USB hub found
10366 11:08:39.983326 <6>[ 2.054659] hub 1-0:1.0: 1 port detected
10367 11:08:39.990478 <6>[ 2.058931] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10368 11:08:39.997281 <6>[ 2.067626] hub 2-0:1.0: USB hub found
10369 11:08:40.000577 <6>[ 2.071644] hub 2-0:1.0: 1 port detected
10370 11:08:40.007783 <6>[ 2.078364] mtk-msdc 11f70000.mmc: Got CD GPIO
10371 11:08:40.018133 <6>[ 2.085306] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10372 11:08:40.025384 <6>[ 2.093343] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10373 11:08:40.035161 <4>[ 2.101237] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10374 11:08:40.045306 <6>[ 2.110760] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10375 11:08:40.051931 <6>[ 2.118838] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10376 11:08:40.058926 <6>[ 2.126961] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10377 11:08:40.067914 <6>[ 2.134881] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10378 11:08:40.074318 <6>[ 2.142756] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10379 11:08:40.084388 <6>[ 2.150577] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10380 11:08:40.094397 <6>[ 2.161123] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10381 11:08:40.102483 <6>[ 2.169487] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10382 11:08:40.110752 <6>[ 2.177865] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10383 11:08:40.117794 <6>[ 2.186205] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10384 11:08:40.127786 <6>[ 2.194554] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10385 11:08:40.134037 <6>[ 2.202891] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10386 11:08:40.143930 <6>[ 2.211238] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10387 11:08:40.154764 <6>[ 2.219576] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10388 11:08:40.160777 <6>[ 2.227926] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10389 11:08:40.170491 <6>[ 2.236264] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10390 11:08:40.177253 <6>[ 2.244609] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10391 11:08:40.187503 <6>[ 2.252948] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10392 11:08:40.193944 <6>[ 2.261285] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10393 11:08:40.203894 <6>[ 2.269621] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10394 11:08:40.210035 <6>[ 2.277958] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10395 11:08:40.217348 <6>[ 2.286716] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10396 11:08:40.224323 <6>[ 2.293864] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10397 11:08:40.229732 <6>[ 2.300573] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10398 11:08:40.239366 <6>[ 2.307304] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10399 11:08:40.246872 <6>[ 2.314215] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10400 11:08:40.253501 <6>[ 2.321071] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10401 11:08:40.264165 <6>[ 2.330198] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10402 11:08:40.273397 <6>[ 2.339318] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10403 11:08:40.283295 <6>[ 2.348611] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10404 11:08:40.293194 <6>[ 2.358114] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10405 11:08:40.299996 <6>[ 2.367659] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10406 11:08:40.310736 <6>[ 2.376783] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10407 11:08:40.319666 <6>[ 2.386249] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10408 11:08:40.329995 <6>[ 2.395367] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10409 11:08:40.339834 <6>[ 2.404661] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10410 11:08:40.348969 <6>[ 2.414821] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10411 11:08:40.359067 <6>[ 2.426302] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10412 11:08:40.365334 <6>[ 2.435670] Trying to probe devices needed for running init ...
10413 11:08:40.427469 <6>[ 2.495182] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10414 11:08:40.582330 <6>[ 2.652904] hub 1-1:1.0: USB hub found
10415 11:08:40.585830 <6>[ 2.657417] hub 1-1:1.0: 4 ports detected
10416 11:08:40.595751 <6>[ 2.666094] hub 1-1:1.0: USB hub found
10417 11:08:40.599581 <6>[ 2.670551] hub 1-1:1.0: 4 ports detected
10418 11:08:40.708476 <6>[ 2.775528] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10419 11:08:40.734210 <6>[ 2.804812] hub 2-1:1.0: USB hub found
10420 11:08:40.737087 <6>[ 2.809308] hub 2-1:1.0: 3 ports detected
10421 11:08:40.746356 <6>[ 2.817315] hub 2-1:1.0: USB hub found
10422 11:08:40.750676 <6>[ 2.821754] hub 2-1:1.0: 3 ports detected
10423 11:08:40.923690 <6>[ 2.991184] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10424 11:08:41.056597 <6>[ 3.126629] hub 1-1.4:1.0: USB hub found
10425 11:08:41.059355 <6>[ 3.131280] hub 1-1.4:1.0: 2 ports detected
10426 11:08:41.067878 <6>[ 3.138562] hub 1-1.4:1.0: USB hub found
10427 11:08:41.071022 <6>[ 3.143181] hub 1-1.4:1.0: 2 ports detected
10428 11:08:41.135866 <6>[ 3.203409] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10429 11:08:41.367492 <6>[ 3.435223] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10430 11:08:41.559919 <6>[ 3.627195] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10431 11:08:52.662336 <6>[ 14.736471] ALSA device list:
10432 11:08:52.667658 <6>[ 14.739751] No soundcards found.
10433 11:08:52.673979 <6>[ 14.745420] Freeing unused kernel memory: 8448K
10434 11:08:52.677855 <6>[ 14.750385] Run /init as init process
10435 11:08:52.685357 Loading, please wait...
10436 11:08:52.700860 Starting version 247.3-7+deb11u4
10437 11:08:52.834737 <6>[ 14.903532] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10438 11:08:52.844832 <3>[ 14.912533] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10439 11:08:52.847917 <6>[ 14.913818] remoteproc remoteproc0: scp is available
10440 11:08:52.858047 <3>[ 14.921684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10441 11:08:52.861276 <6>[ 14.926014] remoteproc remoteproc0: powering up scp
10442 11:08:52.868462 <6>[ 14.926068] usbcore: registered new device driver r8152-cfgselector
10443 11:08:52.877440 <6>[ 14.929261] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10444 11:08:52.884118 <6>[ 14.929272] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10445 11:08:52.893825 <6>[ 14.929276] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10446 11:08:52.900357 <3>[ 14.934297] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10447 11:08:52.910809 <6>[ 14.940234] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10448 11:08:52.916832 <3>[ 14.956004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10449 11:08:52.924057 <6>[ 14.959770] mc: Linux media interface: v0.10
10450 11:08:52.926995 <6>[ 14.961884] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10451 11:08:52.938809 <3>[ 14.970572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10452 11:08:52.943370 <6>[ 14.971146] videodev: Linux video capture interface: v2.00
10453 11:08:52.951261 <6>[ 14.982730] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10454 11:08:52.958640 <3>[ 14.987373] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10455 11:08:52.964322 <4>[ 14.988055] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10456 11:08:52.971027 <4>[ 14.988890] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10457 11:08:52.980643 <4>[ 15.005146] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10458 11:08:52.987611 <4>[ 15.005146] Fallback method does not support PEC.
10459 11:08:52.995062 <3>[ 15.005427] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10460 11:08:53.003763 <3>[ 15.027600] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10461 11:08:53.011280 <3>[ 15.034947] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10462 11:08:53.020686 <3>[ 15.034979] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10463 11:08:53.027600 <6>[ 15.052204] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10464 11:08:53.034670 <3>[ 15.063193] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10465 11:08:53.041097 <6>[ 15.071290] pci_bus 0000:00: root bus resource [bus 00-ff]
10466 11:08:53.047527 <3>[ 15.080037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10467 11:08:53.057427 <3>[ 15.080040] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10468 11:08:53.064944 <3>[ 15.080064] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10469 11:08:53.071194 <6>[ 15.080108] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10470 11:08:53.081018 <6>[ 15.088134] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10471 11:08:53.087916 <3>[ 15.096204] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10472 11:08:53.097122 <3>[ 15.096206] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10473 11:08:53.105053 <3>[ 15.096209] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10474 11:08:53.110927 <3>[ 15.096211] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10475 11:08:53.120373 <3>[ 15.096222] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10476 11:08:53.130464 <6>[ 15.103107] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10477 11:08:53.137041 <6>[ 15.104314] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10478 11:08:53.146913 <6>[ 15.104351] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10479 11:08:53.153196 <6>[ 15.104356] remoteproc remoteproc0: remote processor scp is now up
10480 11:08:53.160410 <6>[ 15.107150] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10481 11:08:53.169622 <4>[ 15.109874] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10482 11:08:53.179834 <4>[ 15.109879] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10483 11:08:53.186654 <3>[ 15.110017] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10484 11:08:53.196553 <6>[ 15.112117] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10485 11:08:53.206427 <6>[ 15.115555] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10486 11:08:53.213373 <6>[ 15.115852] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10487 11:08:53.220476 <6>[ 15.119034] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10488 11:08:53.228799 <6>[ 15.126697] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10489 11:08:53.236088 <6>[ 15.133081] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10490 11:08:53.242473 <6>[ 15.133138] pci 0000:00:00.0: supports D1 D2
10491 11:08:53.246369 <6>[ 15.165256] Bluetooth: Core ver 2.22
10492 11:08:53.253028 <6>[ 15.165765] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10493 11:08:53.265822 <6>[ 15.166914] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10494 11:08:53.268581 <6>[ 15.167062] usbcore: registered new interface driver uvcvideo
10495 11:08:53.275945 <6>[ 15.172796] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10496 11:08:53.281885 <6>[ 15.180883] NET: Registered PF_BLUETOOTH protocol family
10497 11:08:53.291725 <6>[ 15.189554] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10498 11:08:53.298476 <6>[ 15.197017] Bluetooth: HCI device and connection manager initialized
10499 11:08:53.301510 <6>[ 15.197024] Bluetooth: HCI socket layer initialized
10500 11:08:53.308819 <6>[ 15.197252] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10501 11:08:53.312194 <6>[ 15.203072] r8152 2-1.3:1.0 eth0: v1.12.13
10502 11:08:53.318073 <6>[ 15.203122] usbcore: registered new interface driver r8152
10503 11:08:53.325425 <6>[ 15.206993] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10504 11:08:53.332498 <6>[ 15.213958] Bluetooth: L2CAP socket layer initialized
10505 11:08:53.335627 <6>[ 15.213964] Bluetooth: SCO socket layer initialized
10506 11:08:53.341330 <6>[ 15.229175] usbcore: registered new interface driver cdc_ether
10507 11:08:53.348310 <6>[ 15.238233] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10508 11:08:53.354637 <6>[ 15.255602] usbcore: registered new interface driver r8153_ecm
10509 11:08:53.361248 <6>[ 15.264115] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10510 11:08:53.368194 <6>[ 15.282675] usbcore: registered new interface driver btusb
10511 11:08:53.377760 <4>[ 15.283385] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10512 11:08:53.384917 <3>[ 15.283389] Bluetooth: hci0: Failed to load firmware file (-2)
10513 11:08:53.390961 <3>[ 15.283391] Bluetooth: hci0: Failed to set up firmware (-2)
10514 11:08:53.401184 <4>[ 15.283392] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10515 11:08:53.408149 <6>[ 15.283827] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10516 11:08:53.414337 <6>[ 15.291469] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10517 11:08:53.421138 <6>[ 15.492141] pci 0000:01:00.0: supports D1 D2
10518 11:08:53.427284 <6>[ 15.496662] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10519 11:08:53.446403 <6>[ 15.515069] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10520 11:08:53.452805 <6>[ 15.521949] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10521 11:08:53.459691 <6>[ 15.530028] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10522 11:08:53.469366 <6>[ 15.538026] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10523 11:08:53.476220 <6>[ 15.546026] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10524 11:08:53.488354 <6>[ 15.554027] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10525 11:08:53.489642 <6>[ 15.562026] pci 0000:00:00.0: PCI bridge to [bus 01]
10526 11:08:53.498800 <6>[ 15.567242] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10527 11:08:53.505745 <6>[ 15.575304] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10528 11:08:53.512280 <6>[ 15.581978] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10529 11:08:53.515961 <6>[ 15.588486] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10530 11:08:53.536462 <5>[ 15.605395] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10531 11:08:53.557868 <5>[ 15.626512] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10532 11:08:53.564298 <5>[ 15.634516] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10533 11:08:53.574064 <4>[ 15.642982] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10534 11:08:53.580991 <6>[ 15.651878] cfg80211: failed to load regulatory.db
10535 11:08:53.618800 <6>[ 15.687894] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10536 11:08:53.625858 <6>[ 15.695442] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10537 11:08:53.650198 <6>[ 15.722143] mt7921e 0000:01:00.0: ASIC revision: 79610010
10538 11:08:53.747828 <6>[ 15.816827] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10539 11:08:53.751170 <6>[ 15.816827]
10540 11:08:53.761113 Begin: Loading essential drivers ... done.
10541 11:08:53.764169 Begin: Running /scripts/init-premount ... done.
10542 11:08:53.771153 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10543 11:08:53.781079 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10544 11:08:53.783634 Device /sys/class/net/enx00e04c6803bd found
10545 11:08:53.784157 done.
10546 11:08:53.821937 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10547 11:08:54.017891 <6>[ 16.086691] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10548 11:08:54.686934 <6>[ 16.759638] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10549 11:08:54.859285 <6>[ 16.931432] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10550 11:08:55.078453 IP-Config: no response after 2 secs - giving up
10551 11:08:55.109970 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10552 11:08:55.131919 IP-Config: wlp1s0 hardware address 74:4c:a1:92:35:3b mtu 1500 DHCP
10553 11:08:55.832137 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10554 11:08:55.838813 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10555 11:08:55.845334 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10556 11:08:55.853083 host : mt8192-asurada-spherion-r0-cbg-4
10557 11:08:55.861165 domain : lava-rack
10558 11:08:55.864787 rootserver: 192.168.201.1 rootpath:
10559 11:08:55.865269 filename :
10560 11:08:55.952985 done.
10561 11:08:55.961403 Begin: Running /scripts/nfs-bottom ... done.
10562 11:08:55.969129 Begin: Running /scripts/init-bottom ... done.
10563 11:08:57.170029 <6>[ 19.242808] NET: Registered PF_INET6 protocol family
10564 11:08:57.179578 <6>[ 19.250419] Segment Routing with IPv6
10565 11:08:57.181713 <6>[ 19.254428] In-situ OAM (IOAM) with IPv6
10566 11:08:57.300925 <30>[ 19.353526] systemd[1]: systemd 247.3-7+deb11u4 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10567 11:08:57.303745 <30>[ 19.377900] systemd[1]: Detected architecture arm64.
10568 11:08:57.327438
10569 11:08:57.329824 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10570 11:08:57.330114
10571 11:08:57.344574 <30>[ 19.417257] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10572 11:08:58.254154 <30>[ 20.323477] systemd[1]: Queued start job for default target Graphical Interface.
10573 11:08:58.284962 <30>[ 20.357688] systemd[1]: Created slice system-getty.slice.
10574 11:08:58.291447 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10575 11:08:58.307809 <30>[ 20.380543] systemd[1]: Created slice system-modprobe.slice.
10576 11:08:58.315111 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10577 11:08:58.333584 <30>[ 20.405111] systemd[1]: Created slice system-serial\x2dgetty.slice.
10578 11:08:58.342947 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10579 11:08:58.355369 <30>[ 20.428265] systemd[1]: Created slice User and Session Slice.
10580 11:08:58.362766 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10581 11:08:58.382289 <30>[ 20.451932] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10582 11:08:58.391937 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10583 11:08:58.411184 <30>[ 20.479846] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10584 11:08:58.416870 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10585 11:08:58.441606 <30>[ 20.507652] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10586 11:08:58.448567 <30>[ 20.519881] systemd[1]: Reached target Local Encrypted Volumes.
10587 11:08:58.454885 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10588 11:08:58.470950 <30>[ 20.543719] systemd[1]: Reached target Paths.
10589 11:08:58.473934 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10590 11:08:58.491671 <30>[ 20.563198] systemd[1]: Reached target Remote File Systems.
10591 11:08:58.496576 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10592 11:08:58.515394 <30>[ 20.587494] systemd[1]: Reached target Slices.
10593 11:08:58.521715 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10594 11:08:58.535052 <30>[ 20.607282] systemd[1]: Reached target Swap.
10595 11:08:58.538201 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10596 11:08:58.558490 <30>[ 20.627625] systemd[1]: Listening on initctl Compatibility Named Pipe.
10597 11:08:58.564296 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10598 11:08:58.571779 <30>[ 20.643802] systemd[1]: Listening on Journal Audit Socket.
10599 11:08:58.578117 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10600 11:08:58.596194 <30>[ 20.668544] systemd[1]: Listening on Journal Socket (/dev/log).
10601 11:08:58.601986 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10602 11:08:58.619000 <30>[ 20.691757] systemd[1]: Listening on Journal Socket.
10603 11:08:58.625689 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10604 11:08:58.643045 <30>[ 20.712820] systemd[1]: Listening on Network Service Netlink Socket.
10605 11:08:58.649729 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10606 11:08:58.665465 <30>[ 20.738338] systemd[1]: Listening on udev Control Socket.
10607 11:08:58.672658 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10608 11:08:58.687016 <30>[ 20.759637] systemd[1]: Listening on udev Kernel Socket.
10609 11:08:58.693490 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10610 11:08:58.743412 <30>[ 20.815503] systemd[1]: Mounting Huge Pages File System...
10611 11:08:58.749329 Mounting [0;1;39mHuge Pages File System[0m...
10612 11:08:58.767294 <30>[ 20.839427] systemd[1]: Mounting POSIX Message Queue File System...
10613 11:08:58.773543 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10614 11:08:58.792981 <30>[ 20.866088] systemd[1]: Mounting Kernel Debug File System...
10615 11:08:58.799753 Mounting [0;1;39mKernel Debug File System[0m...
10616 11:08:58.817852 <30>[ 20.887521] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10617 11:08:58.865748 <30>[ 20.935375] systemd[1]: Starting Create list of static device nodes for the current kernel...
10618 11:08:58.872099 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10619 11:08:58.894684 <30>[ 20.967772] systemd[1]: Starting Load Kernel Module configfs...
10620 11:08:58.901732 Starting [0;1;39mLoad Kernel Module configfs[0m...
10621 11:08:58.918589 <30>[ 20.991312] systemd[1]: Starting Load Kernel Module drm...
10622 11:08:58.925073 Starting [0;1;39mLoad Kernel Module drm[0m...
10623 11:08:58.942925 <30>[ 21.015384] systemd[1]: Starting Load Kernel Module fuse...
10624 11:08:58.949016 Starting [0;1;39mLoad Kernel Module fuse[0m...
10625 11:08:58.977445 <6>[ 21.050670] fuse: init (API version 7.37)
10626 11:08:58.987388 <30>[ 21.052154] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10627 11:08:59.030913 <30>[ 21.103676] systemd[1]: Starting Journal Service...
10628 11:08:59.034803 Starting [0;1;39mJournal Service[0m...
10629 11:08:59.061719 <30>[ 21.133800] systemd[1]: Starting Load Kernel Modules...
10630 11:08:59.067755 Starting [0;1;39mLoad Kernel Modules[0m...
10631 11:08:59.088474 <30>[ 21.158279] systemd[1]: Starting Remount Root and Kernel File Systems...
10632 11:08:59.094615 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10633 11:08:59.112983 <30>[ 21.186408] systemd[1]: Starting Coldplug All udev Devices...
10634 11:08:59.119612 Starting [0;1;39mColdplug All udev Devices[0m...
10635 11:08:59.137239 <30>[ 21.209984] systemd[1]: Mounted Huge Pages File System.
10636 11:08:59.147410 <3>[ 21.213738] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10637 11:08:59.153102 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10638 11:08:59.166879 <30>[ 21.239492] systemd[1]: Mounted POSIX Message Queue File System.
10639 11:08:59.177574 <3>[ 21.245276] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10640 11:08:59.183333 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10641 11:08:59.198536 <30>[ 21.271333] systemd[1]: Mounted Kernel Debug File System.
10642 11:08:59.205537 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10643 11:08:59.216631 <3>[ 21.285574] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10644 11:08:59.226446 <30>[ 21.295988] systemd[1]: Finished Create list of static device nodes for the current kernel.
10645 11:08:59.237229 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10646 11:08:59.247201 <3>[ 21.315508] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10647 11:08:59.252952 <30>[ 21.325960] systemd[1]: modprobe@configfs.service: Succeeded.
10648 11:08:59.261365 <30>[ 21.333086] systemd[1]: Finished Load Kernel Module configfs.
10649 11:08:59.266903 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10650 11:08:59.286222 <3>[ 21.355492] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10651 11:08:59.293918 <30>[ 21.365220] systemd[1]: modprobe@drm.service: Succeeded.
10652 11:08:59.299742 <30>[ 21.371792] systemd[1]: Finished Load Kernel Module drm.
10653 11:08:59.305967 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10654 11:08:59.321373 <3>[ 21.390816] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10655 11:08:59.328379 <30>[ 21.400935] systemd[1]: modprobe@fuse.service: Succeeded.
10656 11:08:59.334809 <30>[ 21.407701] systemd[1]: Finished Load Kernel Module fuse.
10657 11:08:59.348984 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0<3>[ 21.419262] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10658 11:08:59.352609 m.
10659 11:08:59.367826 <30>[ 21.440221] systemd[1]: Finished Load Kernel Modules.
10660 11:08:59.381215 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 21.449049] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10661 11:08:59.381766 l Modules[0m.
10662 11:08:59.400224 <30>[ 21.471834] systemd[1]: Finished Remount Root and Kernel File Systems.
10663 11:08:59.413268 [[0;32m OK [0m] Finished [0<3>[ 21.480903] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10664 11:08:59.417031 ;1;39mRemount Root and Kernel File Systems[0m.
10665 11:08:59.442047 <3>[ 21.511523] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10666 11:08:59.476908 <30>[ 21.549953] systemd[1]: Mounting FUSE Control File System...
10667 11:08:59.483982 Mounting [0;1;39mFUSE Control File System[0m...
10668 11:08:59.507182 <30>[ 21.577212] systemd[1]: Mounting Kernel Configuration File System...
10669 11:08:59.510203 Mounting [0;1;39mKernel Configuration File System[0m...
10670 11:08:59.540269 <30>[ 21.609839] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10671 11:08:59.550091 <30>[ 21.619045] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10672 11:08:59.579433 <30>[ 21.651684] systemd[1]: Starting Load/Save Random Seed...
10673 11:08:59.585245 Starting [0;1;39mLoad/Save Random Seed[0m...
10674 11:08:59.604617 <30>[ 21.677295] systemd[1]: Starting Apply Kernel Variables...
10675 11:08:59.621387 <4>[ 21.680769] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10676 11:08:59.627814 <3>[ 21.698786] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10677 11:08:59.634812 Starting [0;1;39mApply Kernel Variables[0m...
10678 11:08:59.710804 <30>[ 21.783807] systemd[1]: Starting Create System Users...
10679 11:08:59.717434 Starting [0;1;39mCreate System Users[0m...
10680 11:08:59.736042 <30>[ 21.808976] systemd[1]: Started Journal Service.
10681 11:08:59.743330 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10682 11:08:59.768590 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10683 11:08:59.782646 See 'systemctl status systemd-udev-trigger.service' for details.
10684 11:08:59.802443 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10685 11:08:59.818207 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10686 11:08:59.839213 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10687 11:08:59.856325 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10688 11:08:59.871988 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10689 11:08:59.939350 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10690 11:08:59.958707 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10691 11:08:59.998522 <46>[ 22.068720] systemd-journald[288]: Received client request to flush runtime journal.
10692 11:09:00.029221 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10693 11:09:00.042430 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10694 11:09:00.058765 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10695 11:09:00.122813 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10696 11:09:01.409431 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10697 11:09:01.449901 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10698 11:09:01.474104 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10699 11:09:01.491384 Starting [0;1;39mNetwork Service[0m...
10700 11:09:01.631665 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10701 11:09:01.684974 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10702 11:09:01.712405 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10703 11:09:02.082378 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10704 11:09:02.101169 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10705 11:09:02.142487 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10706 11:09:02.164299 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10707 11:09:02.211658 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10708 11:09:02.227118 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10709 11:09:02.242708 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10710 11:09:02.299152 Starting [0;1;39mNetwork Name Resolution[0m...
10711 11:09:02.326556 Starting [0;1;39mNetwork Time Synchronization[0m...
10712 11:09:02.344321 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10713 11:09:02.403259 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10714 11:09:02.505642 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10715 11:09:02.526098 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10716 11:09:02.545314 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10717 11:09:02.557752 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10718 11:09:02.573574 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10719 11:09:02.726050 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10720 11:09:02.770131 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10721 11:09:03.408589 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10722 11:09:03.509115 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10723 11:09:03.526416 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10724 11:09:03.867915 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10725 11:09:03.881032 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10726 11:09:03.909987 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10727 11:09:03.970141 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10728 11:09:04.023444 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10729 11:09:04.093710 Starting [0;1;39mUser Login Management[0m...
10730 11:09:04.112698 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10731 11:09:04.132700 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10732 11:09:04.150996 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10733 11:09:04.187174 Starting [0;1;39mPermit User Sessions[0m...
10734 11:09:04.334120 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10735 11:09:04.356425 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10736 11:09:04.401587 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10737 11:09:04.470567 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10738 11:09:04.487527 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10739 11:09:04.504501 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10740 11:09:04.522849 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10741 11:09:04.537654 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10742 11:09:04.589904 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10743 11:09:04.637400 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10744 11:09:04.708474
10745 11:09:04.709075
10746 11:09:04.711652 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10747 11:09:04.712122
10748 11:09:04.714837 debian-bullseye-arm64 login: root (automatic login)
10749 11:09:04.715307
10750 11:09:04.715786
10751 11:09:05.083048 Linux debian-bullseye-arm64 6.1.80-cip16 #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024 aarch64
10752 11:09:05.083257
10753 11:09:05.089493 The programs included with the Debian GNU/Linux system are free software;
10754 11:09:05.096116 the exact distribution terms for each program are described in the
10755 11:09:05.099566 individual files in /usr/share/doc/*/copyright.
10756 11:09:05.099770
10757 11:09:05.106304 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10758 11:09:05.109440 permitted by applicable law.
10759 11:09:05.933080 Matched prompt #10: / #
10761 11:09:05.933469 Setting prompt string to ['/ #']
10762 11:09:05.933616 end: 2.2.5.1 login-action (duration 00:00:29) [common]
10764 11:09:05.933917 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
10765 11:09:05.934047 start: 2.2.6 expect-shell-connection (timeout 00:03:33) [common]
10766 11:09:05.934156 Setting prompt string to ['/ #']
10767 11:09:05.934282 Forcing a shell prompt, looking for ['/ #']
10769 11:09:05.984769 / #
10770 11:09:05.985454 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10771 11:09:05.985969 Waiting using forced prompt support (timeout 00:02:30)
10772 11:09:05.992345
10773 11:09:05.993228 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10774 11:09:05.993842 start: 2.2.7 export-device-env (timeout 00:03:33) [common]
10776 11:09:06.095218 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12925646/extract-nfsrootfs-3abnc__8'
10777 11:09:06.102574 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12925646/extract-nfsrootfs-3abnc__8'
10779 11:09:06.204165 / # export NFS_SERVER_IP='192.168.201.1'
10780 11:09:06.210653 export NFS_SERVER_IP='192.168.201.1'
10781 11:09:06.211596 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10782 11:09:06.212144 end: 2.2 depthcharge-retry (duration 00:01:27) [common]
10783 11:09:06.212646 end: 2 depthcharge-action (duration 00:01:27) [common]
10784 11:09:06.213222 start: 3 lava-test-retry (timeout 00:07:54) [common]
10785 11:09:06.213703 start: 3.1 lava-test-shell (timeout 00:07:54) [common]
10786 11:09:06.214131 Using namespace: common
10788 11:09:06.315245 / # #
10789 11:09:06.315890 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10790 11:09:06.322324 #
10791 11:09:06.323205 Using /lava-12925646
10793 11:09:06.424410 / # export SHELL=/bin/bash
10794 11:09:06.431285 export SHELL=/bin/bash
10796 11:09:06.533014 / # . /lava-12925646/environment
10797 11:09:06.539809 . /lava-12925646/environment
10799 11:09:06.646797 / # /lava-12925646/bin/lava-test-runner /lava-12925646/0
10800 11:09:06.647438 Test shell timeout: 10s (minimum of the action and connection timeout)
10801 11:09:06.653649 /lava-12925646/bin/lava-test-runner /lava-12925646/0
10802 11:09:06.914562 + export TESTRUN_ID=0_timesync-off
10803 11:09:06.917257 + TESTRUN_ID=0_timesync-off
10804 11:09:06.921060 + cd /lava-12925646/0/tests/0_timesync-off
10805 11:09:06.923712 ++ cat uuid
10806 11:09:06.928244 + UUID=12925646_1.6.2.3.1
10807 11:09:06.928664 + set +x
10808 11:09:06.935089 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12925646_1.6.2.3.1>
10809 11:09:06.935755 Received signal: <STARTRUN> 0_timesync-off 12925646_1.6.2.3.1
10810 11:09:06.936143 Starting test lava.0_timesync-off (12925646_1.6.2.3.1)
10811 11:09:06.936582 Skipping test definition patterns.
10812 11:09:06.937828 + systemctl stop systemd-timesyncd
10813 11:09:06.981173 + set +x
10814 11:09:06.984125 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12925646_1.6.2.3.1>
10815 11:09:06.984840 Received signal: <ENDRUN> 0_timesync-off 12925646_1.6.2.3.1
10816 11:09:06.985254 Ending use of test pattern.
10817 11:09:06.985608 Ending test lava.0_timesync-off (12925646_1.6.2.3.1), duration 0.05
10819 11:09:07.060109 + export TESTRUN_ID=1_kselftest-tpm2
10820 11:09:07.063375 + TESTRUN_ID=1_kselftest-tpm2
10821 11:09:07.069904 + cd /lava-12925646/0/tests/1_kselftest-tpm2
10822 11:09:07.070328 ++ cat uuid
10823 11:09:07.075658 + UUID=12925646_1.6.2.3.5
10824 11:09:07.076135 + set +x
10825 11:09:07.081274 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 12925646_1.6.2.3.5>
10826 11:09:07.082018 Received signal: <STARTRUN> 1_kselftest-tpm2 12925646_1.6.2.3.5
10827 11:09:07.082418 Starting test lava.1_kselftest-tpm2 (12925646_1.6.2.3.5)
10828 11:09:07.082843 Skipping test definition patterns.
10829 11:09:07.085434 + cd ./automated/linux/kselftest/
10830 11:09:07.111356 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10831 11:09:07.147389 INFO: install_deps skipped
10832 11:09:07.260181 --2024-03-03 11:09:07-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10833 11:09:07.275796 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10834 11:09:07.405180 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10835 11:09:07.534631 HTTP request sent, awaiting response... 200 OK
10836 11:09:07.537290 Length: 1746012 (1.7M) [application/octet-stream]
10837 11:09:07.540890 Saving to: 'kselftest.tar.xz'
10838 11:09:07.541454
10839 11:09:07.541892
10840 11:09:07.793335 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10841 11:09:08.054351 kselftest.tar.xz 2%[ ] 46.39K 180KB/s
10842 11:09:08.406614 kselftest.tar.xz 12%[=> ] 217.50K 419KB/s
10843 11:09:08.705789 kselftest.tar.xz 29%[====> ] 508.79K 585KB/s
10844 11:09:08.711386 kselftest.tar.xz 100%[===================>] 1.67M 1.42MB/s
10845 11:09:08.718400 kselftest.tar.xz 100%[===================>] 1.67M 1.42MB/s in 1.2s
10846 11:09:08.718960
10847 11:09:08.865216 2024-03-03 11:09:08 (1.42 MB/s) - 'kselftest.tar.xz' saved [1746012/1746012]
10848 11:09:08.865387
10849 11:09:13.065897 skiplist:
10850 11:09:13.068734 ========================================
10851 11:09:13.072585 ========================================
10852 11:09:13.116991 tpm2:test_smoke.sh
10853 11:09:13.119464 tpm2:test_space.sh
10854 11:09:13.136230 ============== Tests to run ===============
10855 11:09:13.136790 tpm2:test_smoke.sh
10856 11:09:13.139079 tpm2:test_space.sh
10857 11:09:13.142497 ===========End Tests to run ===============
10858 11:09:13.145647 shardfile-tpm2 pass
10859 11:09:13.249478 <12>[ 35.324327] kselftest: Running tests in tpm2
10860 11:09:13.259567 TAP version 13
10861 11:09:13.271044 1..2
10862 11:09:13.300346 # selftests: tpm2: test_smoke.sh
10863 11:09:14.795457 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
10864 11:09:14.798842 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
10865 11:09:14.805387 # Exception ignored in: <function Client.__del__ at 0xffff8b6bcd30>
10866 11:09:14.808633 # Traceback (most recent call last):
10867 11:09:14.819004 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10868 11:09:14.819540 # if self.tpm:
10869 11:09:14.825596 # AttributeError: 'Client' object has no attribute 'tpm'
10870 11:09:14.828927 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
10871 11:09:14.836076 # Exception ignored in: <function Client.__del__ at 0xffff8b6bcd30>
10872 11:09:14.838496 # Traceback (most recent call last):
10873 11:09:14.849673 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10874 11:09:14.851825 # if self.tpm:
10875 11:09:14.855504 # AttributeError: 'Client' object has no attribute 'tpm'
10876 11:09:14.862032 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
10877 11:09:14.868759 # Exception ignored in: <function Client.__del__ at 0xffff8b6bcd30>
10878 11:09:14.872100 # Traceback (most recent call last):
10879 11:09:14.881717 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10880 11:09:14.882260 # if self.tpm:
10881 11:09:14.888175 # AttributeError: 'Client' object has no attribute 'tpm'
10882 11:09:14.891420 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
10883 11:09:14.897829 # Exception ignored in: <function Client.__del__ at 0xffff8b6bcd30>
10884 11:09:14.901363 # Traceback (most recent call last):
10885 11:09:14.911814 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10886 11:09:14.914598 # if self.tpm:
10887 11:09:14.917677 # AttributeError: 'Client' object has no attribute 'tpm'
10888 11:09:14.924831 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
10889 11:09:14.928569 # Exception ignored in: <function Client.__del__ at 0xffff8b6bcd30>
10890 11:09:14.931181 # Traceback (most recent call last):
10891 11:09:14.940962 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10892 11:09:14.944493 # if self.tpm:
10893 11:09:14.954411 # AttributeError: 'Client' object has no attribute 'tpm'
10894 11:09:14.955282 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
10895 11:09:14.961000 # Exception ignored in: <function Client.__del__ at 0xffff8b6bcd30>
10896 11:09:14.964375 # Traceback (most recent call last):
10897 11:09:14.974208 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10898 11:09:14.974739 # if self.tpm:
10899 11:09:14.981402 # AttributeError: 'Client' object has no attribute 'tpm'
10900 11:09:14.984293 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
10901 11:09:14.990551 # Exception ignored in: <function Client.__del__ at 0xffff8b6bcd30>
10902 11:09:14.994077 # Traceback (most recent call last):
10903 11:09:15.003865 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10904 11:09:15.007368 # if self.tpm:
10905 11:09:15.010849 # AttributeError: 'Client' object has no attribute 'tpm'
10906 11:09:15.017815 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
10907 11:09:15.023473 # Exception ignored in: <function Client.__del__ at 0xffff8b6bcd30>
10908 11:09:15.027188 # Traceback (most recent call last):
10909 11:09:15.039428 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10910 11:09:15.040048 # if self.tpm:
10911 11:09:15.044213 # AttributeError: 'Client' object has no attribute 'tpm'
10912 11:09:15.044769 #
10913 11:09:15.051262 # ======================================================================
10914 11:09:15.054063 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
10915 11:09:15.060509 # ----------------------------------------------------------------------
10916 11:09:15.063548 # Traceback (most recent call last):
10917 11:09:15.077102 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
10918 11:09:15.080251 # self.root_key = self.client.create_root_key()
10919 11:09:15.090343 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
10920 11:09:15.096565 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
10921 11:09:15.106317 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
10922 11:09:15.109630 # raise ProtocolError(cc, rc)
10923 11:09:15.112569 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
10924 11:09:15.117056 #
10925 11:09:15.120242 # ======================================================================
10926 11:09:15.126563 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
10927 11:09:15.133262 # ----------------------------------------------------------------------
10928 11:09:15.136111 # Traceback (most recent call last):
10929 11:09:15.146407 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10930 11:09:15.149638 # self.client = tpm2.Client()
10931 11:09:15.158674 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10932 11:09:15.162912 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10933 11:09:15.169349 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10934 11:09:15.169774 #
10935 11:09:15.175616 # ======================================================================
10936 11:09:15.179707 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
10937 11:09:15.185946 # ----------------------------------------------------------------------
10938 11:09:15.188808 # Traceback (most recent call last):
10939 11:09:15.199494 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10940 11:09:15.202242 # self.client = tpm2.Client()
10941 11:09:15.212372 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10942 11:09:15.218461 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10943 11:09:15.222523 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10944 11:09:15.223044 #
10945 11:09:15.228913 # ======================================================================
10946 11:09:15.235699 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
10947 11:09:15.243538 # ----------------------------------------------------------------------
10948 11:09:15.245707 # Traceback (most recent call last):
10949 11:09:15.255188 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10950 11:09:15.259226 # self.client = tpm2.Client()
10951 11:09:15.268499 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10952 11:09:15.271760 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10953 11:09:15.278655 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10954 11:09:15.279221 #
10955 11:09:15.285976 # ======================================================================
10956 11:09:15.288325 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
10957 11:09:15.295308 # ----------------------------------------------------------------------
10958 11:09:15.298812 # Traceback (most recent call last):
10959 11:09:15.308932 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10960 11:09:15.311195 # self.client = tpm2.Client()
10961 11:09:15.321455 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10962 11:09:15.328136 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10963 11:09:15.331535 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10964 11:09:15.332073 #
10965 11:09:15.338364 # ======================================================================
10966 11:09:15.345443 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
10967 11:09:15.351887 # ----------------------------------------------------------------------
10968 11:09:15.354865 # Traceback (most recent call last):
10969 11:09:15.366058 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10970 11:09:15.366623 # self.client = tpm2.Client()
10971 11:09:15.376692 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10972 11:09:15.380914 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10973 11:09:15.387320 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10974 11:09:15.387881 #
10975 11:09:15.394793 # ======================================================================
10976 11:09:15.398832 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
10977 11:09:15.405838 # ----------------------------------------------------------------------
10978 11:09:15.409451 # Traceback (most recent call last):
10979 11:09:15.417724 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10980 11:09:15.421121 # self.client = tpm2.Client()
10981 11:09:15.431366 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10982 11:09:15.437186 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10983 11:09:15.440478 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10984 11:09:15.441119 #
10985 11:09:15.447070 # ======================================================================
10986 11:09:15.453565 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
10987 11:09:15.460128 # ----------------------------------------------------------------------
10988 11:09:15.464320 # Traceback (most recent call last):
10989 11:09:15.473509 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10990 11:09:15.474060 # self.client = tpm2.Client()
10991 11:09:15.484627 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10992 11:09:15.490826 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10993 11:09:15.496864 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10994 11:09:15.497433 #
10995 11:09:15.503095 # ======================================================================
10996 11:09:15.507032 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
10997 11:09:15.513521 # ----------------------------------------------------------------------
10998 11:09:15.517564 # Traceback (most recent call last):
10999 11:09:15.526209 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11000 11:09:15.529367 # self.client = tpm2.Client()
11001 11:09:15.539922 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11002 11:09:15.546774 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11003 11:09:15.549664 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11004 11:09:15.550127 #
11005 11:09:15.556599 # ----------------------------------------------------------------------
11006 11:09:15.559457 # Ran 9 tests in 0.049s
11007 11:09:15.559919 #
11008 11:09:15.564063 # FAILED (errors=9)
11009 11:09:15.566788 # test_async (tpm2_tests.AsyncTest) ... ok
11010 11:09:15.569124 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11011 11:09:15.569646 #
11012 11:09:15.576953 # ----------------------------------------------------------------------
11013 11:09:15.579323 # Ran 2 tests in 0.034s
11014 11:09:15.579880 #
11015 11:09:15.580363 # OK
11016 11:09:15.582818 ok 1 selftests: tpm2: test_smoke.sh
11017 11:09:15.587067 # selftests: tpm2: test_space.sh
11018 11:09:15.594749 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11019 11:09:15.595778 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11020 11:09:15.599486 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11021 11:09:15.605264 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11022 11:09:15.605734 #
11023 11:09:15.612883 # ======================================================================
11024 11:09:15.616198 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11025 11:09:15.622855 # ----------------------------------------------------------------------
11026 11:09:15.625582 # Traceback (most recent call last):
11027 11:09:15.638842 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11028 11:09:15.642088 # root1 = space1.create_root_key()
11029 11:09:15.651798 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11030 11:09:15.655838 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11031 11:09:15.665782 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11032 11:09:15.668825 # raise ProtocolError(cc, rc)
11033 11:09:15.675060 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11034 11:09:15.675620 #
11035 11:09:15.681869 # ======================================================================
11036 11:09:15.688887 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11037 11:09:15.691533 # ----------------------------------------------------------------------
11038 11:09:15.695486 # Traceback (most recent call last):
11039 11:09:15.708017 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11040 11:09:15.712316 # space1.create_root_key()
11041 11:09:15.721222 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11042 11:09:15.727928 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11043 11:09:15.738357 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11044 11:09:15.738940 # raise ProtocolError(cc, rc)
11045 11:09:15.745100 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11046 11:09:15.745673 #
11047 11:09:15.751885 # ======================================================================
11048 11:09:15.759305 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11049 11:09:15.761019 # ----------------------------------------------------------------------
11050 11:09:15.765167 # Traceback (most recent call last):
11051 11:09:15.778570 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11052 11:09:15.781285 # root1 = space1.create_root_key()
11053 11:09:15.791734 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11054 11:09:15.797841 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11055 11:09:15.808090 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11056 11:09:15.810761 # raise ProtocolError(cc, rc)
11057 11:09:15.814449 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11058 11:09:15.817884 #
11059 11:09:15.820753 # ======================================================================
11060 11:09:15.827889 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11061 11:09:15.833700 # ----------------------------------------------------------------------
11062 11:09:15.837191 # Traceback (most recent call last):
11063 11:09:15.847585 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11064 11:09:15.850179 # root1 = space1.create_root_key()
11065 11:09:15.863736 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11066 11:09:15.867410 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11067 11:09:15.878117 # File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11068 11:09:15.879761 # raise ProtocolError(cc, rc)
11069 11:09:15.886970 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11070 11:09:15.887483 #
11071 11:09:15.893183 # ----------------------------------------------------------------------
11072 11:09:15.896671 # Ran 4 tests in 0.092s
11073 11:09:15.897136 #
11074 11:09:15.897476 # FAILED (errors=4)
11075 11:09:15.903024 not ok 2 selftests: tpm2: test_space.sh # exit=1
11076 11:09:15.920862 Traceback (most recent call last):
11077 11:09:15.931066 File "/lava-12925646/0/tests/1_kselftest-tpm2/automated/linux/kselftest/./parse-output.py", line 4, in <module>
11078 11:09:15.934135 from tap import parser
11079 11:09:15.938635 ModuleNotFoundError: No module named 'tap'
11080 11:09:15.944035 + ../../utils/send-to-lava.sh ./output/result.txt
11081 11:09:16.006967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11082 11:09:16.007399 + set +x
11083 11:09:16.008115 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11085 11:09:16.013763 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 12925646_1.6.2.3.5>
11086 11:09:16.014443 Received signal: <ENDRUN> 1_kselftest-tpm2 12925646_1.6.2.3.5
11087 11:09:16.014819 Ending use of test pattern.
11088 11:09:16.015139 Ending test lava.1_kselftest-tpm2 (12925646_1.6.2.3.5), duration 8.93
11090 11:09:16.016375 <LAVA_TEST_RUNNER EXIT>
11091 11:09:16.017016 ok: lava_test_shell seems to have completed
11092 11:09:16.017479 shardfile-tpm2: pass
11093 11:09:16.017884 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11094 11:09:16.018304 end: 3 lava-test-retry (duration 00:00:10) [common]
11095 11:09:16.018734 start: 4 finalize (timeout 00:07:44) [common]
11096 11:09:16.019187 start: 4.1 power-off (timeout 00:00:30) [common]
11097 11:09:16.019919 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11098 11:09:16.141739 >> Command sent successfully.
11099 11:09:16.146347 Returned 0 in 0 seconds
11100 11:09:16.247249 end: 4.1 power-off (duration 00:00:00) [common]
11102 11:09:16.248824 start: 4.2 read-feedback (timeout 00:07:44) [common]
11103 11:09:16.250233 Listened to connection for namespace 'common' for up to 1s
11104 11:09:17.250804 Finalising connection for namespace 'common'
11105 11:09:17.251482 Disconnecting from shell: Finalise
11106 11:09:17.251913 / #
11107 11:09:17.352965 end: 4.2 read-feedback (duration 00:00:01) [common]
11108 11:09:17.353761 end: 4 finalize (duration 00:00:01) [common]
11109 11:09:17.354383 Cleaning after the job
11110 11:09:17.354913 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925646/tftp-deploy-n7u47uue/ramdisk
11111 11:09:17.369294 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925646/tftp-deploy-n7u47uue/kernel
11112 11:09:17.404008 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925646/tftp-deploy-n7u47uue/dtb
11113 11:09:17.404294 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925646/tftp-deploy-n7u47uue/nfsrootfs
11114 11:09:17.498745 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925646/tftp-deploy-n7u47uue/modules
11115 11:09:17.506226 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12925646
11116 11:09:18.144050 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12925646
11117 11:09:18.144222 Job finished correctly