Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 31
- Boot result: PASS
- Errors: 0
- Warnings: 1
- Kernel Warnings: 37
1 11:10:53.705738 lava-dispatcher, installed at version: 2024.01
2 11:10:53.705973 start: 0 validate
3 11:10:53.706123 Start time: 2024-03-03 11:10:53.706111+00:00 (UTC)
4 11:10:53.706256 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:10:53.706402 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20240129.0%2Farm64%2Frootfs.cpio.gz exists
6 11:10:53.973639 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:10:53.973805 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:10:54.238425 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:10:54.238617 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:10:54.504010 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:10:54.504209 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:10:54.770949 validate duration: 1.06
14 11:10:54.771369 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:10:54.771499 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:10:54.771601 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:10:54.771770 Not decompressing ramdisk as can be used compressed.
18 11:10:54.771899 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20240129.0/arm64/rootfs.cpio.gz
19 11:10:54.771975 saving as /var/lib/lava/dispatcher/tmp/12925665/tftp-deploy-qak9d4qr/ramdisk/rootfs.cpio.gz
20 11:10:54.772060 total size: 84944419 (81 MB)
21 11:10:54.773261 progress 0 % (0 MB)
22 11:10:54.795835 progress 5 % (4 MB)
23 11:10:54.818200 progress 10 % (8 MB)
24 11:10:54.840780 progress 15 % (12 MB)
25 11:10:54.863435 progress 20 % (16 MB)
26 11:10:54.886250 progress 25 % (20 MB)
27 11:10:54.908882 progress 30 % (24 MB)
28 11:10:54.931181 progress 35 % (28 MB)
29 11:10:54.953711 progress 40 % (32 MB)
30 11:10:54.976148 progress 45 % (36 MB)
31 11:10:54.999066 progress 50 % (40 MB)
32 11:10:55.021638 progress 55 % (44 MB)
33 11:10:55.043953 progress 60 % (48 MB)
34 11:10:55.066361 progress 65 % (52 MB)
35 11:10:55.088898 progress 70 % (56 MB)
36 11:10:55.112441 progress 75 % (60 MB)
37 11:10:55.135106 progress 80 % (64 MB)
38 11:10:55.157466 progress 85 % (68 MB)
39 11:10:55.180196 progress 90 % (72 MB)
40 11:10:55.202503 progress 95 % (76 MB)
41 11:10:55.224569 progress 100 % (81 MB)
42 11:10:55.224805 81 MB downloaded in 0.45 s (178.93 MB/s)
43 11:10:55.224993 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:10:55.225264 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:10:55.225370 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:10:55.225471 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:10:55.225629 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:10:55.225730 saving as /var/lib/lava/dispatcher/tmp/12925665/tftp-deploy-qak9d4qr/kernel/Image
50 11:10:55.225830 total size: 51599872 (49 MB)
51 11:10:55.225931 No compression specified
52 11:10:55.227567 progress 0 % (0 MB)
53 11:10:55.241282 progress 5 % (2 MB)
54 11:10:55.255082 progress 10 % (4 MB)
55 11:10:55.269072 progress 15 % (7 MB)
56 11:10:55.282684 progress 20 % (9 MB)
57 11:10:55.296722 progress 25 % (12 MB)
58 11:10:55.310809 progress 30 % (14 MB)
59 11:10:55.325056 progress 35 % (17 MB)
60 11:10:55.339078 progress 40 % (19 MB)
61 11:10:55.353314 progress 45 % (22 MB)
62 11:10:55.368169 progress 50 % (24 MB)
63 11:10:55.382352 progress 55 % (27 MB)
64 11:10:55.396054 progress 60 % (29 MB)
65 11:10:55.409808 progress 65 % (32 MB)
66 11:10:55.423657 progress 70 % (34 MB)
67 11:10:55.437429 progress 75 % (36 MB)
68 11:10:55.451020 progress 80 % (39 MB)
69 11:10:55.464871 progress 85 % (41 MB)
70 11:10:55.478645 progress 90 % (44 MB)
71 11:10:55.492184 progress 95 % (46 MB)
72 11:10:55.505634 progress 100 % (49 MB)
73 11:10:55.505886 49 MB downloaded in 0.28 s (175.71 MB/s)
74 11:10:55.506059 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:10:55.506326 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:10:55.506437 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:10:55.506546 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:10:55.506704 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:10:55.506779 saving as /var/lib/lava/dispatcher/tmp/12925665/tftp-deploy-qak9d4qr/dtb/mt8192-asurada-spherion-r0.dtb
81 11:10:55.506881 total size: 47278 (0 MB)
82 11:10:55.506985 No compression specified
83 11:10:55.508661 progress 69 % (0 MB)
84 11:10:55.508981 progress 100 % (0 MB)
85 11:10:55.509168 0 MB downloaded in 0.00 s (19.74 MB/s)
86 11:10:55.509311 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:10:55.509570 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:10:55.509674 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:10:55.509780 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:10:55.509942 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:10:55.510041 saving as /var/lib/lava/dispatcher/tmp/12925665/tftp-deploy-qak9d4qr/modules/modules.tar
93 11:10:55.510142 total size: 8628476 (8 MB)
94 11:10:55.510245 Using unxz to decompress xz
95 11:10:55.514556 progress 0 % (0 MB)
96 11:10:55.541355 progress 5 % (0 MB)
97 11:10:55.571600 progress 10 % (0 MB)
98 11:10:55.597428 progress 15 % (1 MB)
99 11:10:55.621634 progress 20 % (1 MB)
100 11:10:55.646598 progress 25 % (2 MB)
101 11:10:55.672016 progress 30 % (2 MB)
102 11:10:55.702300 progress 35 % (2 MB)
103 11:10:55.729217 progress 40 % (3 MB)
104 11:10:55.755172 progress 45 % (3 MB)
105 11:10:55.781445 progress 50 % (4 MB)
106 11:10:55.808236 progress 55 % (4 MB)
107 11:10:55.832748 progress 60 % (4 MB)
108 11:10:55.860800 progress 65 % (5 MB)
109 11:10:55.887719 progress 70 % (5 MB)
110 11:10:55.914352 progress 75 % (6 MB)
111 11:10:55.942301 progress 80 % (6 MB)
112 11:10:55.967679 progress 85 % (7 MB)
113 11:10:55.993723 progress 90 % (7 MB)
114 11:10:56.025985 progress 95 % (7 MB)
115 11:10:56.056809 progress 100 % (8 MB)
116 11:10:56.062153 8 MB downloaded in 0.55 s (14.91 MB/s)
117 11:10:56.062410 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:10:56.062760 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:10:56.062858 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:10:56.062972 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:10:56.063066 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:10:56.063158 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:10:56.063387 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo
125 11:10:56.063531 makedir: /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin
126 11:10:56.063638 makedir: /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/tests
127 11:10:56.063751 makedir: /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/results
128 11:10:56.063875 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-add-keys
129 11:10:56.064029 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-add-sources
130 11:10:56.064163 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-background-process-start
131 11:10:56.064306 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-background-process-stop
132 11:10:56.064438 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-common-functions
133 11:10:56.064567 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-echo-ipv4
134 11:10:56.064697 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-install-packages
135 11:10:56.064825 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-installed-packages
136 11:10:56.064953 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-os-build
137 11:10:56.065083 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-probe-channel
138 11:10:56.065213 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-probe-ip
139 11:10:56.065344 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-target-ip
140 11:10:56.065471 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-target-mac
141 11:10:56.065596 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-target-storage
142 11:10:56.065727 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-test-case
143 11:10:56.065856 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-test-event
144 11:10:56.065983 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-test-feedback
145 11:10:56.066110 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-test-raise
146 11:10:56.066240 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-test-reference
147 11:10:56.066366 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-test-runner
148 11:10:56.066493 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-test-set
149 11:10:56.066622 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-test-shell
150 11:10:56.066752 Updating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-install-packages (oe)
151 11:10:56.066913 Updating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/bin/lava-installed-packages (oe)
152 11:10:56.067048 Creating /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/environment
153 11:10:56.067155 LAVA metadata
154 11:10:56.067232 - LAVA_JOB_ID=12925665
155 11:10:56.067298 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:10:56.067405 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:10:56.067475 skipped lava-vland-overlay
158 11:10:56.067551 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:10:56.067632 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:10:56.067695 skipped lava-multinode-overlay
161 11:10:56.067772 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:10:56.067864 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:10:56.067943 Loading test definitions
164 11:10:56.068033 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 11:10:56.068108 Using /lava-12925665 at stage 0
166 11:10:56.068206 Fetching tests from https://github.com/kernelci/kernelci-core
167 11:10:56.068305 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/0/tests/0_sleep'
168 11:10:56.750377 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/0/tests/0_sleep
169 11:10:56.751769 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 11:10:56.752182 uuid=12925665_1.5.2.3.1 testdef=None
171 11:10:56.752406 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 11:10:56.752676 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 11:10:56.753229 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 11:10:56.753455 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 11:10:56.754168 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 11:10:56.754405 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 11:10:56.755148 runner path: /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/0/tests/0_sleep test_uuid 12925665_1.5.2.3.1
181 11:10:56.755234 sleep_params='mem'
182 11:10:56.755407 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 11:10:56.755625 Creating lava-test-runner.conf files
185 11:10:56.755690 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12925665/lava-overlay-4b1vbtqo/lava-12925665/0 for stage 0
186 11:10:56.755785 - 0_sleep
187 11:10:56.755890 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 11:10:56.755982 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 11:10:56.899910 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 11:10:56.900064 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 11:10:56.900162 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 11:10:56.900264 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 11:10:56.900374 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 11:10:59.438182 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:03) [common]
195 11:10:59.438593 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 11:10:59.438714 extracting modules file /var/lib/lava/dispatcher/tmp/12925665/tftp-deploy-qak9d4qr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925665/extract-overlay-ramdisk-_hi2cjb_/ramdisk
197 11:10:59.675089 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 11:10:59.675263 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 11:10:59.675362 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925665/compress-overlay-a2rf7e8e/overlay-1.5.2.4.tar.gz to ramdisk
200 11:10:59.675436 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925665/compress-overlay-a2rf7e8e/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12925665/extract-overlay-ramdisk-_hi2cjb_/ramdisk
201 11:10:59.780134 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 11:10:59.780291 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 11:10:59.780388 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 11:10:59.780475 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 11:10:59.780557 Building ramdisk /var/lib/lava/dispatcher/tmp/12925665/extract-overlay-ramdisk-_hi2cjb_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12925665/extract-overlay-ramdisk-_hi2cjb_/ramdisk
206 11:11:01.398297 >> 563785 blocks
207 11:11:11.675092 rename /var/lib/lava/dispatcher/tmp/12925665/extract-overlay-ramdisk-_hi2cjb_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12925665/tftp-deploy-qak9d4qr/ramdisk/ramdisk.cpio.gz
208 11:11:11.675583 end: 1.5.7 compress-ramdisk (duration 00:00:12) [common]
209 11:11:11.675742 start: 1.5.8 prepare-kernel (timeout 00:09:43) [common]
210 11:11:11.675877 start: 1.5.8.1 prepare-fit (timeout 00:09:43) [common]
211 11:11:11.676027 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12925665/tftp-deploy-qak9d4qr/kernel/Image'
212 11:11:24.946732 Returned 0 in 13 seconds
213 11:11:25.047358 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12925665/tftp-deploy-qak9d4qr/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12925665/tftp-deploy-qak9d4qr/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12925665/tftp-deploy-qak9d4qr/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12925665/tftp-deploy-qak9d4qr/kernel/image.itb
214 11:11:26.445662 output: FIT description: Kernel Image image with one or more FDT blobs
215 11:11:26.446038 output: Created: Sun Mar 3 11:11:26 2024
216 11:11:26.446113 output: Image 0 (kernel-1)
217 11:11:26.446180 output: Description:
218 11:11:26.446241 output: Created: Sun Mar 3 11:11:26 2024
219 11:11:26.446300 output: Type: Kernel Image
220 11:11:26.446356 output: Compression: lzma compressed
221 11:11:26.446413 output: Data Size: 12057697 Bytes = 11775.09 KiB = 11.50 MiB
222 11:11:26.446472 output: Architecture: AArch64
223 11:11:26.446537 output: OS: Linux
224 11:11:26.446598 output: Load Address: 0x00000000
225 11:11:26.446662 output: Entry Point: 0x00000000
226 11:11:26.446721 output: Hash algo: crc32
227 11:11:26.446781 output: Hash value: cf43f4f3
228 11:11:26.446842 output: Image 1 (fdt-1)
229 11:11:26.446901 output: Description: mt8192-asurada-spherion-r0
230 11:11:26.446957 output: Created: Sun Mar 3 11:11:26 2024
231 11:11:26.447011 output: Type: Flat Device Tree
232 11:11:26.447065 output: Compression: uncompressed
233 11:11:26.447119 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 11:11:26.447173 output: Architecture: AArch64
235 11:11:26.447226 output: Hash algo: crc32
236 11:11:26.447280 output: Hash value: cc4352de
237 11:11:26.447333 output: Image 2 (ramdisk-1)
238 11:11:26.447386 output: Description: unavailable
239 11:11:26.447439 output: Created: Sun Mar 3 11:11:26 2024
240 11:11:26.447492 output: Type: RAMDisk Image
241 11:11:26.447546 output: Compression: Unknown Compression
242 11:11:26.447599 output: Data Size: 98363817 Bytes = 96058.42 KiB = 93.81 MiB
243 11:11:26.447653 output: Architecture: AArch64
244 11:11:26.447706 output: OS: Linux
245 11:11:26.447759 output: Load Address: unavailable
246 11:11:26.447812 output: Entry Point: unavailable
247 11:11:26.447865 output: Hash algo: crc32
248 11:11:26.447919 output: Hash value: 1fee4137
249 11:11:26.447972 output: Default Configuration: 'conf-1'
250 11:11:26.448025 output: Configuration 0 (conf-1)
251 11:11:26.448078 output: Description: mt8192-asurada-spherion-r0
252 11:11:26.448132 output: Kernel: kernel-1
253 11:11:26.448185 output: Init Ramdisk: ramdisk-1
254 11:11:26.448239 output: FDT: fdt-1
255 11:11:26.448303 output: Loadables: kernel-1
256 11:11:26.448359 output:
257 11:11:26.448563 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
258 11:11:26.448666 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
259 11:11:26.448774 end: 1.5 prepare-tftp-overlay (duration 00:00:30) [common]
260 11:11:26.448871 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:28) [common]
261 11:11:26.448960 No LXC device requested
262 11:11:26.449040 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 11:11:26.449128 start: 1.7 deploy-device-env (timeout 00:09:28) [common]
264 11:11:26.449206 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 11:11:26.449274 Checking files for TFTP limit of 4294967296 bytes.
266 11:11:26.449773 end: 1 tftp-deploy (duration 00:00:32) [common]
267 11:11:26.449883 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 11:11:26.449981 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 11:11:26.450112 substitutions:
270 11:11:26.450187 - {DTB}: 12925665/tftp-deploy-qak9d4qr/dtb/mt8192-asurada-spherion-r0.dtb
271 11:11:26.450254 - {INITRD}: 12925665/tftp-deploy-qak9d4qr/ramdisk/ramdisk.cpio.gz
272 11:11:26.450317 - {KERNEL}: 12925665/tftp-deploy-qak9d4qr/kernel/Image
273 11:11:26.450376 - {LAVA_MAC}: None
274 11:11:26.450435 - {PRESEED_CONFIG}: None
275 11:11:26.450493 - {PRESEED_LOCAL}: None
276 11:11:26.450576 - {RAMDISK}: 12925665/tftp-deploy-qak9d4qr/ramdisk/ramdisk.cpio.gz
277 11:11:26.450670 - {ROOT_PART}: None
278 11:11:26.450730 - {ROOT}: None
279 11:11:26.450787 - {SERVER_IP}: 192.168.201.1
280 11:11:26.450843 - {TEE}: None
281 11:11:26.450900 Parsed boot commands:
282 11:11:26.450955 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 11:11:26.451140 Parsed boot commands: tftpboot 192.168.201.1 12925665/tftp-deploy-qak9d4qr/kernel/image.itb 12925665/tftp-deploy-qak9d4qr/kernel/cmdline
284 11:11:26.451236 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 11:11:26.451320 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 11:11:26.451414 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 11:11:26.451505 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 11:11:26.451579 Not connected, no need to disconnect.
289 11:11:26.451654 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 11:11:26.451737 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 11:11:26.451806 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
292 11:11:26.455984 Setting prompt string to ['lava-test: # ']
293 11:11:26.456386 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 11:11:26.456508 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 11:11:26.456652 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 11:11:26.456790 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 11:11:26.457009 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
298 11:11:31.591160 >> Command sent successfully.
299 11:11:31.594524 Returned 0 in 5 seconds
300 11:11:31.694915 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 11:11:31.695264 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 11:11:31.695364 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 11:11:31.695452 Setting prompt string to 'Starting depthcharge on Spherion...'
305 11:11:31.695519 Changing prompt to 'Starting depthcharge on Spherion...'
306 11:11:31.695588 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 11:11:31.695858 [Enter `^Ec?' for help]
308 11:11:31.865890
309 11:11:31.866033
310 11:11:31.866131 F0: 102B 0000
311 11:11:31.866220
312 11:11:31.866303 F3: 1001 0000 [0200]
313 11:11:31.866385
314 11:11:31.869715 F3: 1001 0000
315 11:11:31.869935
316 11:11:31.870083 F7: 102D 0000
317 11:11:31.870229
318 11:11:31.870391 F1: 0000 0000
319 11:11:31.870470
320 11:11:31.873671 V0: 0000 0000 [0001]
321 11:11:31.873805
322 11:11:31.873921 00: 0007 8000
323 11:11:31.874039
324 11:11:31.877628 01: 0000 0000
325 11:11:31.877756
326 11:11:31.877874 BP: 0C00 0209 [0000]
327 11:11:31.877986
328 11:11:31.881323 G0: 1182 0000
329 11:11:31.881449
330 11:11:31.881562 EC: 0000 0021 [4000]
331 11:11:31.881670
332 11:11:31.885016 S7: 0000 0000 [0000]
333 11:11:31.885138
334 11:11:31.885249 CC: 0000 0000 [0001]
335 11:11:31.885361
336 11:11:31.888323 T0: 0000 0040 [010F]
337 11:11:31.888458
338 11:11:31.888570 Jump to BL
339 11:11:31.888681
340 11:11:31.912626
341 11:11:31.912755
342 11:11:31.912868
343 11:11:31.920627 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 11:11:31.924088 ARM64: Exception handlers installed.
345 11:11:31.927598 ARM64: Testing exception
346 11:11:31.931292 ARM64: Done test exception
347 11:11:31.938529 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 11:11:31.945612 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 11:11:31.952759 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 11:11:31.963837 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 11:11:31.970012 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 11:11:31.980760 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 11:11:31.991411 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 11:11:31.997831 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 11:11:32.015989 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 11:11:32.018641 WDT: Last reset was cold boot
357 11:11:32.022453 SPI1(PAD0) initialized at 2873684 Hz
358 11:11:32.025445 SPI5(PAD0) initialized at 992727 Hz
359 11:11:32.028980 VBOOT: Loading verstage.
360 11:11:32.035698 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 11:11:32.040132 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 11:11:32.043096 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 11:11:32.046582 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 11:11:32.053419 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 11:11:32.059567 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 11:11:32.070842 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 11:11:32.070926
368 11:11:32.070992
369 11:11:32.081592 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 11:11:32.084767 ARM64: Exception handlers installed.
371 11:11:32.084851 ARM64: Testing exception
372 11:11:32.088033 ARM64: Done test exception
373 11:11:32.091258 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 11:11:32.098166 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 11:11:32.111624 Probing TPM: . done!
376 11:11:32.111707 TPM ready after 0 ms
377 11:11:32.119655 Connected to device vid:did:rid of 1ae0:0028:00
378 11:11:32.126508 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 11:11:32.186798 Initialized TPM device CR50 revision 0
380 11:11:32.196061 tlcl_send_startup: Startup return code is 0
381 11:11:32.196175 TPM: setup succeeded
382 11:11:32.207958 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 11:11:32.216465 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 11:11:32.228945 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 11:11:32.238376 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 11:11:32.242602 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 11:11:32.246317 in-header: 03 07 00 00 08 00 00 00
388 11:11:32.250017 in-data: aa e4 47 04 13 02 00 00
389 11:11:32.250101 Chrome EC: UHEPI supported
390 11:11:32.257196 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 11:11:32.260988 in-header: 03 95 00 00 08 00 00 00
392 11:11:32.264018 in-data: 18 20 20 08 00 00 00 00
393 11:11:32.264122 Phase 1
394 11:11:32.267825 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 11:11:32.275258 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 11:11:32.282834 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 11:11:32.282919 Recovery requested (1009000e)
398 11:11:32.294639 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 11:11:32.299377 tlcl_extend: response is 0
400 11:11:32.308680 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 11:11:32.314057 tlcl_extend: response is 0
402 11:11:32.321510 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 11:11:32.340957 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 11:11:32.347228 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 11:11:32.347315
406 11:11:32.347380
407 11:11:32.357787 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 11:11:32.360757 ARM64: Exception handlers installed.
409 11:11:32.364240 ARM64: Testing exception
410 11:11:32.364348 ARM64: Done test exception
411 11:11:32.386538 pmic_efuse_setting: Set efuses in 11 msecs
412 11:11:32.389686 pmwrap_interface_init: Select PMIF_VLD_RDY
413 11:11:32.396143 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 11:11:32.399724 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 11:11:32.406705 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 11:11:32.410553 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 11:11:32.414200 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 11:11:32.421179 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 11:11:32.424791 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 11:11:32.428769 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 11:11:32.432475 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 11:11:32.439993 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 11:11:32.443581 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 11:11:32.447865 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 11:11:32.450880 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 11:11:32.458977 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 11:11:32.466251 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 11:11:32.469560 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 11:11:32.477664 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 11:11:32.481203 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 11:11:32.488578 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 11:11:32.492331 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 11:11:32.499354 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 11:11:32.503151 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 11:11:32.510480 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 11:11:32.514374 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 11:11:32.521879 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 11:11:32.525675 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 11:11:32.528828 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 11:11:32.536254 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 11:11:32.540091 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 11:11:32.543736 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 11:11:32.550635 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 11:11:32.554809 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 11:11:32.561949 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 11:11:32.565567 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 11:11:32.569111 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 11:11:32.576636 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 11:11:32.580042 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 11:11:32.584502 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 11:11:32.588224 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 11:11:32.595708 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 11:11:32.599432 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 11:11:32.603219 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 11:11:32.606335 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 11:11:32.610675 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 11:11:32.617870 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 11:11:32.621645 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 11:11:32.625325 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 11:11:32.629031 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 11:11:32.632880 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 11:11:32.636004 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 11:11:32.640245 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 11:11:32.651049 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 11:11:32.658697 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 11:11:32.662582 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 11:11:32.669704 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 11:11:32.680670 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 11:11:32.684572 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 11:11:32.688089 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 11:11:32.691195 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 11:11:32.699663 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2c
473 11:11:32.703062 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 11:11:32.711231 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 11:11:32.714622 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 11:11:32.723941 [RTC]rtc_get_frequency_meter,154: input=15, output=760
477 11:11:32.733799 [RTC]rtc_get_frequency_meter,154: input=23, output=941
478 11:11:32.742738 [RTC]rtc_get_frequency_meter,154: input=19, output=850
479 11:11:32.752349 [RTC]rtc_get_frequency_meter,154: input=17, output=804
480 11:11:32.762247 [RTC]rtc_get_frequency_meter,154: input=16, output=782
481 11:11:32.771109 [RTC]rtc_get_frequency_meter,154: input=16, output=782
482 11:11:32.781021 [RTC]rtc_get_frequency_meter,154: input=17, output=803
483 11:11:32.783919 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
484 11:11:32.791969 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
485 11:11:32.795709 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 11:11:32.799580 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
487 11:11:32.803375 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 11:11:32.806485 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
489 11:11:32.810559 ADC[4]: Raw value=906573 ID=7
490 11:11:32.814191 ADC[3]: Raw value=213810 ID=1
491 11:11:32.814274 RAM Code: 0x71
492 11:11:32.817227 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 11:11:32.825279 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 11:11:32.832623 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 11:11:32.840122 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 11:11:32.843804 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 11:11:32.847055 in-header: 03 07 00 00 08 00 00 00
498 11:11:32.850790 in-data: aa e4 47 04 13 02 00 00
499 11:11:32.850872 Chrome EC: UHEPI supported
500 11:11:32.858519 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 11:11:32.862193 in-header: 03 95 00 00 08 00 00 00
502 11:11:32.866011 in-data: 18 20 20 08 00 00 00 00
503 11:11:32.869759 MRC: failed to locate region type 0.
504 11:11:32.876603 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 11:11:32.876691 DRAM-K: Running full calibration
506 11:11:32.884024 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 11:11:32.887578 header.status = 0x0
508 11:11:32.887691 header.version = 0x6 (expected: 0x6)
509 11:11:32.891878 header.size = 0xd00 (expected: 0xd00)
510 11:11:32.895063 header.flags = 0x0
511 11:11:32.902466 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 11:11:32.918872 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
513 11:11:32.926854 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 11:11:32.926960 dram_init: ddr_geometry: 2
515 11:11:32.930311 [EMI] MDL number = 2
516 11:11:32.934071 [EMI] Get MDL freq = 0
517 11:11:32.934174 dram_init: ddr_type: 0
518 11:11:32.937943 is_discrete_lpddr4: 1
519 11:11:32.938027 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 11:11:32.941653
521 11:11:32.941762
522 11:11:32.941856 [Bian_co] ETT version 0.0.0.1
523 11:11:32.949164 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 11:11:32.949303
525 11:11:32.953006 dramc_set_vcore_voltage set vcore to 650000
526 11:11:32.953110 Read voltage for 800, 4
527 11:11:32.953205 Vio18 = 0
528 11:11:32.956620 Vcore = 650000
529 11:11:32.956723 Vdram = 0
530 11:11:32.956816 Vddq = 0
531 11:11:32.960132 Vmddr = 0
532 11:11:32.960246 dram_init: config_dvfs: 1
533 11:11:32.963696 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 11:11:32.970221 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 11:11:32.974158 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
536 11:11:32.977275 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
537 11:11:32.984220 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
538 11:11:32.987642 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
539 11:11:32.987790 MEM_TYPE=3, freq_sel=18
540 11:11:32.991365 sv_algorithm_assistance_LP4_1600
541 11:11:32.995157 ============ PULL DRAM RESETB DOWN ============
542 11:11:32.999175 ========== PULL DRAM RESETB DOWN end =========
543 11:11:33.006144 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 11:11:33.009344 ===================================
545 11:11:33.009459 LPDDR4 DRAM CONFIGURATION
546 11:11:33.012609 ===================================
547 11:11:33.015713 EX_ROW_EN[0] = 0x0
548 11:11:33.015830 EX_ROW_EN[1] = 0x0
549 11:11:33.019419 LP4Y_EN = 0x0
550 11:11:33.019526 WORK_FSP = 0x0
551 11:11:33.022553 WL = 0x2
552 11:11:33.022638 RL = 0x2
553 11:11:33.026229 BL = 0x2
554 11:11:33.026316 RPST = 0x0
555 11:11:33.029770 RD_PRE = 0x0
556 11:11:33.029858 WR_PRE = 0x1
557 11:11:33.033299 WR_PST = 0x0
558 11:11:33.033399 DBI_WR = 0x0
559 11:11:33.036560 DBI_RD = 0x0
560 11:11:33.036684 OTF = 0x1
561 11:11:33.040238 ===================================
562 11:11:33.043804 ===================================
563 11:11:33.047202 ANA top config
564 11:11:33.050399 ===================================
565 11:11:33.050510 DLL_ASYNC_EN = 0
566 11:11:33.053804 ALL_SLAVE_EN = 1
567 11:11:33.057645 NEW_RANK_MODE = 1
568 11:11:33.060336 DLL_IDLE_MODE = 1
569 11:11:33.060424 LP45_APHY_COMB_EN = 1
570 11:11:33.064111 TX_ODT_DIS = 1
571 11:11:33.067247 NEW_8X_MODE = 1
572 11:11:33.071446 ===================================
573 11:11:33.074349 ===================================
574 11:11:33.078124 data_rate = 1600
575 11:11:33.081367 CKR = 1
576 11:11:33.081460 DQ_P2S_RATIO = 8
577 11:11:33.084458 ===================================
578 11:11:33.088316 CA_P2S_RATIO = 8
579 11:11:33.091339 DQ_CA_OPEN = 0
580 11:11:33.094341 DQ_SEMI_OPEN = 0
581 11:11:33.098011 CA_SEMI_OPEN = 0
582 11:11:33.098097 CA_FULL_RATE = 0
583 11:11:33.101080 DQ_CKDIV4_EN = 1
584 11:11:33.104398 CA_CKDIV4_EN = 1
585 11:11:33.108191 CA_PREDIV_EN = 0
586 11:11:33.111451 PH8_DLY = 0
587 11:11:33.114563 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 11:11:33.114648 DQ_AAMCK_DIV = 4
589 11:11:33.118257 CA_AAMCK_DIV = 4
590 11:11:33.121312 CA_ADMCK_DIV = 4
591 11:11:33.125064 DQ_TRACK_CA_EN = 0
592 11:11:33.128220 CA_PICK = 800
593 11:11:33.131987 CA_MCKIO = 800
594 11:11:33.132120 MCKIO_SEMI = 0
595 11:11:33.135069 PLL_FREQ = 3068
596 11:11:33.138749 DQ_UI_PI_RATIO = 32
597 11:11:33.142283 CA_UI_PI_RATIO = 0
598 11:11:33.145804 ===================================
599 11:11:33.149883 ===================================
600 11:11:33.150010 memory_type:LPDDR4
601 11:11:33.153736 GP_NUM : 10
602 11:11:33.153863 SRAM_EN : 1
603 11:11:33.157393 MD32_EN : 0
604 11:11:33.160697 ===================================
605 11:11:33.160824 [ANA_INIT] >>>>>>>>>>>>>>
606 11:11:33.164832 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 11:11:33.168199 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 11:11:33.171981 ===================================
609 11:11:33.175205 data_rate = 1600,PCW = 0X7600
610 11:11:33.178831 ===================================
611 11:11:33.182055 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 11:11:33.185550 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 11:11:33.192296 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 11:11:33.195410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 11:11:33.198505 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 11:11:33.202131 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 11:11:33.205250 [ANA_INIT] flow start
618 11:11:33.209126 [ANA_INIT] PLL >>>>>>>>
619 11:11:33.209214 [ANA_INIT] PLL <<<<<<<<
620 11:11:33.212279 [ANA_INIT] MIDPI >>>>>>>>
621 11:11:33.215395 [ANA_INIT] MIDPI <<<<<<<<
622 11:11:33.219305 [ANA_INIT] DLL >>>>>>>>
623 11:11:33.219394 [ANA_INIT] flow end
624 11:11:33.222527 ============ LP4 DIFF to SE enter ============
625 11:11:33.228787 ============ LP4 DIFF to SE exit ============
626 11:11:33.228876 [ANA_INIT] <<<<<<<<<<<<<
627 11:11:33.232610 [Flow] Enable top DCM control >>>>>
628 11:11:33.235880 [Flow] Enable top DCM control <<<<<
629 11:11:33.238881 Enable DLL master slave shuffle
630 11:11:33.245705 ==============================================================
631 11:11:33.245793 Gating Mode config
632 11:11:33.252232 ==============================================================
633 11:11:33.255922 Config description:
634 11:11:33.262786 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 11:11:33.269274 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 11:11:33.275508 SELPH_MODE 0: By rank 1: By Phase
637 11:11:33.282546 ==============================================================
638 11:11:33.282634 GAT_TRACK_EN = 1
639 11:11:33.285488 RX_GATING_MODE = 2
640 11:11:33.289180 RX_GATING_TRACK_MODE = 2
641 11:11:33.292465 SELPH_MODE = 1
642 11:11:33.295855 PICG_EARLY_EN = 1
643 11:11:33.298927 VALID_LAT_VALUE = 1
644 11:11:33.305574 ==============================================================
645 11:11:33.309179 Enter into Gating configuration >>>>
646 11:11:33.312256 Exit from Gating configuration <<<<
647 11:11:33.315979 Enter into DVFS_PRE_config >>>>>
648 11:11:33.326091 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 11:11:33.329221 Exit from DVFS_PRE_config <<<<<
650 11:11:33.332525 Enter into PICG configuration >>>>
651 11:11:33.336084 Exit from PICG configuration <<<<
652 11:11:33.336170 [RX_INPUT] configuration >>>>>
653 11:11:33.339266 [RX_INPUT] configuration <<<<<
654 11:11:33.346247 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 11:11:33.349463 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 11:11:33.356189 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 11:11:33.363041 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 11:11:33.369554 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 11:11:33.375835 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 11:11:33.379560 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 11:11:33.382580 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 11:11:33.386126 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 11:11:33.393006 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 11:11:33.396017 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 11:11:33.399739 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 11:11:33.402771 ===================================
667 11:11:33.405964 LPDDR4 DRAM CONFIGURATION
668 11:11:33.409525 ===================================
669 11:11:33.412942 EX_ROW_EN[0] = 0x0
670 11:11:33.413029 EX_ROW_EN[1] = 0x0
671 11:11:33.415977 LP4Y_EN = 0x0
672 11:11:33.416063 WORK_FSP = 0x0
673 11:11:33.419330 WL = 0x2
674 11:11:33.419416 RL = 0x2
675 11:11:33.422643 BL = 0x2
676 11:11:33.422730 RPST = 0x0
677 11:11:33.426105 RD_PRE = 0x0
678 11:11:33.426191 WR_PRE = 0x1
679 11:11:33.429447 WR_PST = 0x0
680 11:11:33.429533 DBI_WR = 0x0
681 11:11:33.432531 DBI_RD = 0x0
682 11:11:33.432617 OTF = 0x1
683 11:11:33.435990 ===================================
684 11:11:33.439493 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 11:11:33.446016 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 11:11:33.449356 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 11:11:33.453043 ===================================
688 11:11:33.456127 LPDDR4 DRAM CONFIGURATION
689 11:11:33.459922 ===================================
690 11:11:33.460009 EX_ROW_EN[0] = 0x10
691 11:11:33.462859 EX_ROW_EN[1] = 0x0
692 11:11:33.466427 LP4Y_EN = 0x0
693 11:11:33.466513 WORK_FSP = 0x0
694 11:11:33.469567 WL = 0x2
695 11:11:33.469653 RL = 0x2
696 11:11:33.472602 BL = 0x2
697 11:11:33.472688 RPST = 0x0
698 11:11:33.476139 RD_PRE = 0x0
699 11:11:33.476225 WR_PRE = 0x1
700 11:11:33.479872 WR_PST = 0x0
701 11:11:33.479958 DBI_WR = 0x0
702 11:11:33.482791 DBI_RD = 0x0
703 11:11:33.482877 OTF = 0x1
704 11:11:33.486324 ===================================
705 11:11:33.493011 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 11:11:33.496804 nWR fixed to 40
707 11:11:33.499933 [ModeRegInit_LP4] CH0 RK0
708 11:11:33.500019 [ModeRegInit_LP4] CH0 RK1
709 11:11:33.503638 [ModeRegInit_LP4] CH1 RK0
710 11:11:33.506775 [ModeRegInit_LP4] CH1 RK1
711 11:11:33.506861 match AC timing 13
712 11:11:33.513649 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 11:11:33.516729 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 11:11:33.519951 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 11:11:33.526674 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 11:11:33.530178 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 11:11:33.530265 [EMI DOE] emi_dcm 0
718 11:11:33.537049 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 11:11:33.537136 ==
720 11:11:33.540035 Dram Type= 6, Freq= 0, CH_0, rank 0
721 11:11:33.543658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 11:11:33.543746 ==
723 11:11:33.549937 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 11:11:33.556969 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 11:11:33.563981 [CA 0] Center 36 (6~67) winsize 62
726 11:11:33.567600 [CA 1] Center 36 (6~67) winsize 62
727 11:11:33.570538 [CA 2] Center 34 (4~65) winsize 62
728 11:11:33.574132 [CA 3] Center 33 (3~64) winsize 62
729 11:11:33.577305 [CA 4] Center 33 (3~64) winsize 62
730 11:11:33.580981 [CA 5] Center 32 (3~62) winsize 60
731 11:11:33.581108
732 11:11:33.584414 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 11:11:33.584534
734 11:11:33.587464 [CATrainingPosCal] consider 1 rank data
735 11:11:33.590984 u2DelayCellTimex100 = 270/100 ps
736 11:11:33.594508 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
737 11:11:33.597336 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
738 11:11:33.604009 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
739 11:11:33.607955 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
740 11:11:33.610912 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
741 11:11:33.614155 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
742 11:11:33.614277
743 11:11:33.617305 CA PerBit enable=1, Macro0, CA PI delay=32
744 11:11:33.617428
745 11:11:33.621046 [CBTSetCACLKResult] CA Dly = 32
746 11:11:33.621170 CS Dly: 4 (0~35)
747 11:11:33.621282 ==
748 11:11:33.624196 Dram Type= 6, Freq= 0, CH_0, rank 1
749 11:11:33.631090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 11:11:33.631217 ==
751 11:11:33.634105 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 11:11:33.640908 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 11:11:33.650078 [CA 0] Center 36 (6~67) winsize 62
754 11:11:33.653974 [CA 1] Center 36 (6~67) winsize 62
755 11:11:33.657062 [CA 2] Center 34 (4~65) winsize 62
756 11:11:33.660189 [CA 3] Center 33 (3~64) winsize 62
757 11:11:33.663864 [CA 4] Center 33 (3~63) winsize 61
758 11:11:33.667031 [CA 5] Center 32 (2~63) winsize 62
759 11:11:33.667153
760 11:11:33.670494 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 11:11:33.670650
762 11:11:33.673671 [CATrainingPosCal] consider 2 rank data
763 11:11:33.676844 u2DelayCellTimex100 = 270/100 ps
764 11:11:33.679987 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
765 11:11:33.683401 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
766 11:11:33.690433 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
767 11:11:33.693666 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
768 11:11:33.697163 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
769 11:11:33.700240 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
770 11:11:33.700370
771 11:11:33.703940 CA PerBit enable=1, Macro0, CA PI delay=32
772 11:11:33.704026
773 11:11:33.707356 [CBTSetCACLKResult] CA Dly = 32
774 11:11:33.707442 CS Dly: 5 (0~37)
775 11:11:33.707531
776 11:11:33.710381 ----->DramcWriteLeveling(PI) begin...
777 11:11:33.713550 ==
778 11:11:33.713637 Dram Type= 6, Freq= 0, CH_0, rank 0
779 11:11:33.721838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 11:11:33.721921 ==
781 11:11:33.721987 Write leveling (Byte 0): 31 => 31
782 11:11:33.725579 Write leveling (Byte 1): 31 => 31
783 11:11:33.729411 DramcWriteLeveling(PI) end<-----
784 11:11:33.729493
785 11:11:33.729558 ==
786 11:11:33.732595 Dram Type= 6, Freq= 0, CH_0, rank 0
787 11:11:33.735777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 11:11:33.735899 ==
789 11:11:33.739477 [Gating] SW mode calibration
790 11:11:33.746826 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 11:11:33.753583 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 11:11:33.756770 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 11:11:33.759797 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
794 11:11:33.763523 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
795 11:11:33.770379 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
796 11:11:33.773524 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:11:33.776947 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:11:33.783565 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:11:33.786660 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:11:33.790128 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:11:33.796797 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:11:33.800132 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:11:33.803349 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:11:33.810035 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 11:11:33.813438 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:11:33.816864 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:11:33.823385 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:11:33.826980 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
809 11:11:33.830018 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
810 11:11:33.836980 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
811 11:11:33.840133 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:11:33.843911 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 11:11:33.846953 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 11:11:33.853835 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 11:11:33.856891 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 11:11:33.860645 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 11:11:33.867518 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 11:11:33.870832 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
819 11:11:33.873370 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
820 11:11:33.880300 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 11:11:33.883554 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 11:11:33.886780 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 11:11:33.893714 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 11:11:33.896965 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 11:11:33.900411 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
826 11:11:33.907549 0 10 8 | B1->B0 | 2f2f 2626 | 1 0 | (1 1) (1 0)
827 11:11:33.910516 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
828 11:11:33.913983 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 11:11:33.917356 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 11:11:33.923960 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 11:11:33.927107 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 11:11:33.930589 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 11:11:33.937063 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
834 11:11:33.940430 0 11 8 | B1->B0 | 2f2f 3939 | 0 0 | (0 0) (1 1)
835 11:11:33.943715 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
836 11:11:33.950830 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 11:11:33.953834 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 11:11:33.957848 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 11:11:33.963740 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 11:11:33.967229 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 11:11:33.970412 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 11:11:33.977279 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
843 11:11:33.980452 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
844 11:11:33.983708 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:11:33.990486 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:11:33.994055 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:11:33.997378 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:11:34.000618 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:11:34.007502 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:11:34.010727 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:11:34.013964 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 11:11:34.020743 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 11:11:34.023992 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 11:11:34.027500 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 11:11:34.033730 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 11:11:34.037442 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 11:11:34.040590 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
858 11:11:34.047216 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
859 11:11:34.047303 Total UI for P1: 0, mck2ui 16
860 11:11:34.053988 best dqsien dly found for B0: ( 0, 14, 4)
861 11:11:34.057268 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 11:11:34.060993 Total UI for P1: 0, mck2ui 16
863 11:11:34.064323 best dqsien dly found for B1: ( 0, 14, 8)
864 11:11:34.068227 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
865 11:11:34.071685 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 11:11:34.071772
867 11:11:34.074699 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
868 11:11:34.078296 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 11:11:34.081422 [Gating] SW calibration Done
870 11:11:34.081552 ==
871 11:11:34.085178 Dram Type= 6, Freq= 0, CH_0, rank 0
872 11:11:34.088516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 11:11:34.088645 ==
874 11:11:34.091602 RX Vref Scan: 0
875 11:11:34.091728
876 11:11:34.091844 RX Vref 0 -> 0, step: 1
877 11:11:34.091959
878 11:11:34.095307 RX Delay -130 -> 252, step: 16
879 11:11:34.098319 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
880 11:11:34.104748 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
881 11:11:34.108545 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
882 11:11:34.112087 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
883 11:11:34.115211 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
884 11:11:34.118334 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
885 11:11:34.122165 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
886 11:11:34.128335 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
887 11:11:34.131511 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
888 11:11:34.135352 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
889 11:11:34.138327 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
890 11:11:34.142039 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
891 11:11:34.148203 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
892 11:11:34.152071 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
893 11:11:34.155267 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
894 11:11:34.158360 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
895 11:11:34.158444 ==
896 11:11:34.161764 Dram Type= 6, Freq= 0, CH_0, rank 0
897 11:11:34.168923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 11:11:34.169006 ==
899 11:11:34.169071 DQS Delay:
900 11:11:34.171951 DQS0 = 0, DQS1 = 0
901 11:11:34.172033 DQM Delay:
902 11:11:34.172097 DQM0 = 92, DQM1 = 86
903 11:11:34.175508 DQ Delay:
904 11:11:34.178760 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
905 11:11:34.182002 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
906 11:11:34.185609 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
907 11:11:34.188521 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
908 11:11:34.188603
909 11:11:34.188668
910 11:11:34.188728 ==
911 11:11:34.192083 Dram Type= 6, Freq= 0, CH_0, rank 0
912 11:11:34.195090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 11:11:34.195172 ==
914 11:11:34.195237
915 11:11:34.195297
916 11:11:34.198907 TX Vref Scan disable
917 11:11:34.199000 == TX Byte 0 ==
918 11:11:34.205652 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
919 11:11:34.208591 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
920 11:11:34.208675 == TX Byte 1 ==
921 11:11:34.215552 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
922 11:11:34.218746 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
923 11:11:34.218824 ==
924 11:11:34.222442 Dram Type= 6, Freq= 0, CH_0, rank 0
925 11:11:34.225725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 11:11:34.225808 ==
927 11:11:34.239036 TX Vref=22, minBit 1, minWin=27, winSum=442
928 11:11:34.242170 TX Vref=24, minBit 8, minWin=27, winSum=451
929 11:11:34.245888 TX Vref=26, minBit 1, minWin=28, winSum=455
930 11:11:34.249319 TX Vref=28, minBit 7, minWin=28, winSum=458
931 11:11:34.252196 TX Vref=30, minBit 8, minWin=28, winSum=457
932 11:11:34.255987 TX Vref=32, minBit 10, minWin=27, winSum=453
933 11:11:34.262380 [TxChooseVref] Worse bit 7, Min win 28, Win sum 458, Final Vref 28
934 11:11:34.262463
935 11:11:34.265839 Final TX Range 1 Vref 28
936 11:11:34.265922
937 11:11:34.265987 ==
938 11:11:34.269343 Dram Type= 6, Freq= 0, CH_0, rank 0
939 11:11:34.272901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 11:11:34.272984 ==
941 11:11:34.273053
942 11:11:34.276014
943 11:11:34.276122 TX Vref Scan disable
944 11:11:34.279656 == TX Byte 0 ==
945 11:11:34.282563 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
946 11:11:34.285736 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
947 11:11:34.289430 == TX Byte 1 ==
948 11:11:34.292608 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
949 11:11:34.296087 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
950 11:11:34.296170
951 11:11:34.299048 [DATLAT]
952 11:11:34.299129 Freq=800, CH0 RK0
953 11:11:34.299194
954 11:11:34.302285 DATLAT Default: 0xa
955 11:11:34.302366 0, 0xFFFF, sum = 0
956 11:11:34.305997 1, 0xFFFF, sum = 0
957 11:11:34.306082 2, 0xFFFF, sum = 0
958 11:11:34.309241 3, 0xFFFF, sum = 0
959 11:11:34.309323 4, 0xFFFF, sum = 0
960 11:11:34.312498 5, 0xFFFF, sum = 0
961 11:11:34.312581 6, 0xFFFF, sum = 0
962 11:11:34.315868 7, 0xFFFF, sum = 0
963 11:11:34.315977 8, 0xFFFF, sum = 0
964 11:11:34.319634 9, 0x0, sum = 1
965 11:11:34.319716 10, 0x0, sum = 2
966 11:11:34.322710 11, 0x0, sum = 3
967 11:11:34.322793 12, 0x0, sum = 4
968 11:11:34.326195 best_step = 10
969 11:11:34.326277
970 11:11:34.326341 ==
971 11:11:34.329218 Dram Type= 6, Freq= 0, CH_0, rank 0
972 11:11:34.333090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 11:11:34.333173 ==
974 11:11:34.336159 RX Vref Scan: 1
975 11:11:34.336281
976 11:11:34.336405 Set Vref Range= 32 -> 127
977 11:11:34.336504
978 11:11:34.339377 RX Vref 32 -> 127, step: 1
979 11:11:34.339473
980 11:11:34.342637 RX Delay -79 -> 252, step: 8
981 11:11:34.342718
982 11:11:34.346419 Set Vref, RX VrefLevel [Byte0]: 32
983 11:11:34.349590 [Byte1]: 32
984 11:11:34.349671
985 11:11:34.352716 Set Vref, RX VrefLevel [Byte0]: 33
986 11:11:34.355980 [Byte1]: 33
987 11:11:34.359647
988 11:11:34.359728 Set Vref, RX VrefLevel [Byte0]: 34
989 11:11:34.362453 [Byte1]: 34
990 11:11:34.366850
991 11:11:34.366931 Set Vref, RX VrefLevel [Byte0]: 35
992 11:11:34.370567 [Byte1]: 35
993 11:11:34.374450
994 11:11:34.374557 Set Vref, RX VrefLevel [Byte0]: 36
995 11:11:34.377713 [Byte1]: 36
996 11:11:34.381999
997 11:11:34.382083 Set Vref, RX VrefLevel [Byte0]: 37
998 11:11:34.385140 [Byte1]: 37
999 11:11:34.389295
1000 11:11:34.389378 Set Vref, RX VrefLevel [Byte0]: 38
1001 11:11:34.392993 [Byte1]: 38
1002 11:11:34.397295
1003 11:11:34.397378 Set Vref, RX VrefLevel [Byte0]: 39
1004 11:11:34.401138 [Byte1]: 39
1005 11:11:34.404646
1006 11:11:34.404729 Set Vref, RX VrefLevel [Byte0]: 40
1007 11:11:34.407895 [Byte1]: 40
1008 11:11:34.412029
1009 11:11:34.412113 Set Vref, RX VrefLevel [Byte0]: 41
1010 11:11:34.415526 [Byte1]: 41
1011 11:11:34.419444
1012 11:11:34.419540 Set Vref, RX VrefLevel [Byte0]: 42
1013 11:11:34.423185 [Byte1]: 42
1014 11:11:34.427103
1015 11:11:34.427186 Set Vref, RX VrefLevel [Byte0]: 43
1016 11:11:34.430520 [Byte1]: 43
1017 11:11:34.434777
1018 11:11:34.434861 Set Vref, RX VrefLevel [Byte0]: 44
1019 11:11:34.437831 [Byte1]: 44
1020 11:11:34.442093
1021 11:11:34.442176 Set Vref, RX VrefLevel [Byte0]: 45
1022 11:11:34.445966 [Byte1]: 45
1023 11:11:34.449687
1024 11:11:34.449770 Set Vref, RX VrefLevel [Byte0]: 46
1025 11:11:34.453371 [Byte1]: 46
1026 11:11:34.457369
1027 11:11:34.457451 Set Vref, RX VrefLevel [Byte0]: 47
1028 11:11:34.460561 [Byte1]: 47
1029 11:11:34.464933
1030 11:11:34.465015 Set Vref, RX VrefLevel [Byte0]: 48
1031 11:11:34.468081 [Byte1]: 48
1032 11:11:34.472260
1033 11:11:34.472383 Set Vref, RX VrefLevel [Byte0]: 49
1034 11:11:34.475557 [Byte1]: 49
1035 11:11:34.479785
1036 11:11:34.479866 Set Vref, RX VrefLevel [Byte0]: 50
1037 11:11:34.483325 [Byte1]: 50
1038 11:11:34.487672
1039 11:11:34.487754 Set Vref, RX VrefLevel [Byte0]: 51
1040 11:11:34.490883 [Byte1]: 51
1041 11:11:34.495018
1042 11:11:34.495100 Set Vref, RX VrefLevel [Byte0]: 52
1043 11:11:34.498523 [Byte1]: 52
1044 11:11:34.502849
1045 11:11:34.502931 Set Vref, RX VrefLevel [Byte0]: 53
1046 11:11:34.505937 [Byte1]: 53
1047 11:11:34.510162
1048 11:11:34.510244 Set Vref, RX VrefLevel [Byte0]: 54
1049 11:11:34.513303 [Byte1]: 54
1050 11:11:34.517590
1051 11:11:34.517673 Set Vref, RX VrefLevel [Byte0]: 55
1052 11:11:34.521296 [Byte1]: 55
1053 11:11:34.525614
1054 11:11:34.525695 Set Vref, RX VrefLevel [Byte0]: 56
1055 11:11:34.528552 [Byte1]: 56
1056 11:11:34.533049
1057 11:11:34.533131 Set Vref, RX VrefLevel [Byte0]: 57
1058 11:11:34.536087 [Byte1]: 57
1059 11:11:34.540282
1060 11:11:34.540406 Set Vref, RX VrefLevel [Byte0]: 58
1061 11:11:34.543767 [Byte1]: 58
1062 11:11:34.547679
1063 11:11:34.547775 Set Vref, RX VrefLevel [Byte0]: 59
1064 11:11:34.551277 [Byte1]: 59
1065 11:11:34.555663
1066 11:11:34.555744 Set Vref, RX VrefLevel [Byte0]: 60
1067 11:11:34.558814 [Byte1]: 60
1068 11:11:34.563272
1069 11:11:34.563353 Set Vref, RX VrefLevel [Byte0]: 61
1070 11:11:34.566335 [Byte1]: 61
1071 11:11:34.570676
1072 11:11:34.570757 Set Vref, RX VrefLevel [Byte0]: 62
1073 11:11:34.573904 [Byte1]: 62
1074 11:11:34.578166
1075 11:11:34.578247 Set Vref, RX VrefLevel [Byte0]: 63
1076 11:11:34.581676 [Byte1]: 63
1077 11:11:34.585725
1078 11:11:34.585806 Set Vref, RX VrefLevel [Byte0]: 64
1079 11:11:34.588942 [Byte1]: 64
1080 11:11:34.593295
1081 11:11:34.593376 Set Vref, RX VrefLevel [Byte0]: 65
1082 11:11:34.596376 [Byte1]: 65
1083 11:11:34.600904
1084 11:11:34.600985 Set Vref, RX VrefLevel [Byte0]: 66
1085 11:11:34.604093 [Byte1]: 66
1086 11:11:34.608341
1087 11:11:34.608436 Set Vref, RX VrefLevel [Byte0]: 67
1088 11:11:34.611613 [Byte1]: 67
1089 11:11:34.615804
1090 11:11:34.615882 Set Vref, RX VrefLevel [Byte0]: 68
1091 11:11:34.618970 [Byte1]: 68
1092 11:11:34.623335
1093 11:11:34.623466 Set Vref, RX VrefLevel [Byte0]: 69
1094 11:11:34.626992 [Byte1]: 69
1095 11:11:34.630750
1096 11:11:34.630877 Set Vref, RX VrefLevel [Byte0]: 70
1097 11:11:34.634508 [Byte1]: 70
1098 11:11:34.638861
1099 11:11:34.638986 Set Vref, RX VrefLevel [Byte0]: 71
1100 11:11:34.641645 [Byte1]: 71
1101 11:11:34.646261
1102 11:11:34.646385 Set Vref, RX VrefLevel [Byte0]: 72
1103 11:11:34.649173 [Byte1]: 72
1104 11:11:34.653483
1105 11:11:34.653609 Set Vref, RX VrefLevel [Byte0]: 73
1106 11:11:34.656795 [Byte1]: 73
1107 11:11:34.661327
1108 11:11:34.661498 Set Vref, RX VrefLevel [Byte0]: 74
1109 11:11:34.664697 [Byte1]: 74
1110 11:11:34.668599
1111 11:11:34.668722 Set Vref, RX VrefLevel [Byte0]: 75
1112 11:11:34.672197 [Byte1]: 75
1113 11:11:34.676085
1114 11:11:34.676205 Set Vref, RX VrefLevel [Byte0]: 76
1115 11:11:34.679893 [Byte1]: 76
1116 11:11:34.683722
1117 11:11:34.683843 Final RX Vref Byte 0 = 60 to rank0
1118 11:11:34.687249 Final RX Vref Byte 1 = 61 to rank0
1119 11:11:34.690630 Final RX Vref Byte 0 = 60 to rank1
1120 11:11:34.693619 Final RX Vref Byte 1 = 61 to rank1==
1121 11:11:34.697389 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 11:11:34.700563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 11:11:34.704368 ==
1124 11:11:34.704486 DQS Delay:
1125 11:11:34.704601 DQS0 = 0, DQS1 = 0
1126 11:11:34.707364 DQM Delay:
1127 11:11:34.707487 DQM0 = 91, DQM1 = 85
1128 11:11:34.710395 DQ Delay:
1129 11:11:34.710517 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1130 11:11:34.713796 DQ4 =96, DQ5 =80, DQ6 =96, DQ7 =100
1131 11:11:34.717250 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1132 11:11:34.720596 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1133 11:11:34.720678
1134 11:11:34.724266
1135 11:11:34.731024 [DQSOSCAuto] RK0, (LSB)MR18= 0x4940, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1136 11:11:34.734040 CH0 RK0: MR19=606, MR18=4940
1137 11:11:34.740577 CH0_RK0: MR19=0x606, MR18=0x4940, DQSOSC=391, MR23=63, INC=96, DEC=64
1138 11:11:34.740660
1139 11:11:34.744172 ----->DramcWriteLeveling(PI) begin...
1140 11:11:34.744257 ==
1141 11:11:34.747147 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 11:11:34.751011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 11:11:34.751093 ==
1144 11:11:34.753881 Write leveling (Byte 0): 35 => 35
1145 11:11:34.757631 Write leveling (Byte 1): 30 => 30
1146 11:11:34.760673 DramcWriteLeveling(PI) end<-----
1147 11:11:34.760754
1148 11:11:34.760818 ==
1149 11:11:34.764200 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 11:11:34.767809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 11:11:34.767891 ==
1152 11:11:34.771119 [Gating] SW mode calibration
1153 11:11:34.777634 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 11:11:34.783995 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 11:11:34.828544 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 11:11:34.828832 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 11:11:34.828903 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1158 11:11:34.828966 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:11:34.829026 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:11:34.829117 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:11:34.829842 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:11:34.829920 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:11:34.830447 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:11:34.831079 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:11:34.872388 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:11:34.872751 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:11:34.872846 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:11:34.872922 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:11:34.873009 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:11:34.873067 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:11:34.873123 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:11:34.873204 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:11:34.873546 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1174 11:11:34.873825 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1175 11:11:34.876696 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:11:34.880007 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:11:34.883340 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:11:34.890157 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:11:34.893336 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:11:34.896549 0 9 4 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
1181 11:11:34.899663 0 9 8 | B1->B0 | 2f2f 2a2a | 1 0 | (1 1) (0 0)
1182 11:11:34.906301 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 11:11:34.909668 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 11:11:34.913453 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 11:11:34.919637 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 11:11:34.923460 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 11:11:34.926600 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 11:11:34.932945 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1189 11:11:34.936539 0 10 8 | B1->B0 | 2828 2828 | 1 1 | (0 0) (0 0)
1190 11:11:34.939608 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:11:34.946709 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:11:34.949805 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 11:11:34.953365 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 11:11:34.960040 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 11:11:34.963952 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 11:11:34.967316 0 11 4 | B1->B0 | 2a2a 2626 | 0 0 | (0 0) (0 0)
1197 11:11:34.971284 0 11 8 | B1->B0 | 3a3a 3b3b | 1 0 | (0 0) (0 0)
1198 11:11:34.975273 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 11:11:34.982156 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 11:11:34.985165 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 11:11:34.989045 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 11:11:34.992819 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 11:11:34.999817 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 11:11:35.002986 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 11:11:35.006094 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1206 11:11:35.013066 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:11:35.016308 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:11:35.019247 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:11:35.022990 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:11:35.029290 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:11:35.033067 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:11:35.036038 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:11:35.043184 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:11:35.046368 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:11:35.049631 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:11:35.055895 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:11:35.059371 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 11:11:35.063015 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 11:11:35.069690 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 11:11:35.072689 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 11:11:35.076175 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1222 11:11:35.082645 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 11:11:35.082769 Total UI for P1: 0, mck2ui 16
1224 11:11:35.090047 best dqsien dly found for B0: ( 0, 14, 8)
1225 11:11:35.090134 Total UI for P1: 0, mck2ui 16
1226 11:11:35.093190 best dqsien dly found for B1: ( 0, 14, 10)
1227 11:11:35.099754 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1228 11:11:35.102931 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1229 11:11:35.103016
1230 11:11:35.106243 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 11:11:35.109986 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1232 11:11:35.112967 [Gating] SW calibration Done
1233 11:11:35.113052 ==
1234 11:11:35.116220 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 11:11:35.119788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 11:11:35.119891 ==
1237 11:11:35.122929 RX Vref Scan: 0
1238 11:11:35.123011
1239 11:11:35.123077 RX Vref 0 -> 0, step: 1
1240 11:11:35.123137
1241 11:11:35.126284 RX Delay -130 -> 252, step: 16
1242 11:11:35.130041 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1243 11:11:35.133156 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1244 11:11:35.140025 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1245 11:11:35.143125 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1246 11:11:35.146648 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1247 11:11:35.149533 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1248 11:11:35.153333 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1249 11:11:35.159592 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1250 11:11:35.163104 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1251 11:11:35.166232 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1252 11:11:35.169482 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1253 11:11:35.173329 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1254 11:11:35.179840 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1255 11:11:35.183271 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1256 11:11:35.186178 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1257 11:11:35.189982 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1258 11:11:35.190068 ==
1259 11:11:35.193129 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 11:11:35.199954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 11:11:35.200039 ==
1262 11:11:35.200141 DQS Delay:
1263 11:11:35.200240 DQS0 = 0, DQS1 = 0
1264 11:11:35.203564 DQM Delay:
1265 11:11:35.203649 DQM0 = 95, DQM1 = 82
1266 11:11:35.206515 DQ Delay:
1267 11:11:35.209978 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1268 11:11:35.213266 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =109
1269 11:11:35.216283 DQ8 =69, DQ9 =77, DQ10 =77, DQ11 =77
1270 11:11:35.219816 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1271 11:11:35.219900
1272 11:11:35.220001
1273 11:11:35.220100 ==
1274 11:11:35.223162 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 11:11:35.226368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 11:11:35.226484 ==
1277 11:11:35.226570
1278 11:11:35.226650
1279 11:11:35.229915 TX Vref Scan disable
1280 11:11:35.230000 == TX Byte 0 ==
1281 11:11:35.236769 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1282 11:11:35.239940 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1283 11:11:35.240026 == TX Byte 1 ==
1284 11:11:35.246464 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1285 11:11:35.250216 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1286 11:11:35.250301 ==
1287 11:11:35.253251 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 11:11:35.256824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 11:11:35.256956 ==
1290 11:11:35.270981 TX Vref=22, minBit 11, minWin=27, winSum=448
1291 11:11:35.274210 TX Vref=24, minBit 8, minWin=27, winSum=448
1292 11:11:35.277978 TX Vref=26, minBit 1, minWin=28, winSum=454
1293 11:11:35.281198 TX Vref=28, minBit 1, minWin=28, winSum=457
1294 11:11:35.284487 TX Vref=30, minBit 2, minWin=28, winSum=459
1295 11:11:35.290901 TX Vref=32, minBit 2, minWin=28, winSum=456
1296 11:11:35.294339 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
1297 11:11:35.294444
1298 11:11:35.297461 Final TX Range 1 Vref 30
1299 11:11:35.297570
1300 11:11:35.297695 ==
1301 11:11:35.300690 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 11:11:35.304383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 11:11:35.304466 ==
1304 11:11:35.304529
1305 11:11:35.307392
1306 11:11:35.307473 TX Vref Scan disable
1307 11:11:35.311271 == TX Byte 0 ==
1308 11:11:35.314350 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1309 11:11:35.317757 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1310 11:11:35.321272 == TX Byte 1 ==
1311 11:11:35.324334 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1312 11:11:35.327915 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1313 11:11:35.331074
1314 11:11:35.331155 [DATLAT]
1315 11:11:35.331219 Freq=800, CH0 RK1
1316 11:11:35.331279
1317 11:11:35.334627 DATLAT Default: 0xa
1318 11:11:35.334708 0, 0xFFFF, sum = 0
1319 11:11:35.337743 1, 0xFFFF, sum = 0
1320 11:11:35.337825 2, 0xFFFF, sum = 0
1321 11:11:35.341232 3, 0xFFFF, sum = 0
1322 11:11:35.341315 4, 0xFFFF, sum = 0
1323 11:11:35.344555 5, 0xFFFF, sum = 0
1324 11:11:35.344638 6, 0xFFFF, sum = 0
1325 11:11:35.348143 7, 0xFFFF, sum = 0
1326 11:11:35.348226 8, 0xFFFF, sum = 0
1327 11:11:35.351410 9, 0x0, sum = 1
1328 11:11:35.351492 10, 0x0, sum = 2
1329 11:11:35.354488 11, 0x0, sum = 3
1330 11:11:35.354643 12, 0x0, sum = 4
1331 11:11:35.357893 best_step = 10
1332 11:11:35.357975
1333 11:11:35.358038 ==
1334 11:11:35.361010 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 11:11:35.364503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 11:11:35.364586 ==
1337 11:11:35.367918 RX Vref Scan: 0
1338 11:11:35.368000
1339 11:11:35.368063 RX Vref 0 -> 0, step: 1
1340 11:11:35.368123
1341 11:11:35.370754 RX Delay -95 -> 252, step: 8
1342 11:11:35.377789 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1343 11:11:35.380888 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1344 11:11:35.384693 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1345 11:11:35.388073 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1346 11:11:35.390987 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1347 11:11:35.397595 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1348 11:11:35.401074 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1349 11:11:35.404519 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1350 11:11:35.407667 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1351 11:11:35.410959 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1352 11:11:35.418326 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1353 11:11:35.421435 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1354 11:11:35.424523 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1355 11:11:35.428024 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1356 11:11:35.431044 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1357 11:11:35.437705 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1358 11:11:35.437787 ==
1359 11:11:35.441220 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 11:11:35.444237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 11:11:35.444362 ==
1362 11:11:35.444427 DQS Delay:
1363 11:11:35.448089 DQS0 = 0, DQS1 = 0
1364 11:11:35.448171 DQM Delay:
1365 11:11:35.451097 DQM0 = 92, DQM1 = 83
1366 11:11:35.451178 DQ Delay:
1367 11:11:35.454713 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1368 11:11:35.457662 DQ4 =92, DQ5 =84, DQ6 =96, DQ7 =100
1369 11:11:35.461152 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1370 11:11:35.464412 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1371 11:11:35.464497
1372 11:11:35.464583
1373 11:11:35.471406 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1374 11:11:35.474734 CH0 RK1: MR19=606, MR18=3F10
1375 11:11:35.481285 CH0_RK1: MR19=0x606, MR18=0x3F10, DQSOSC=393, MR23=63, INC=95, DEC=63
1376 11:11:35.484884 [RxdqsGatingPostProcess] freq 800
1377 11:11:35.491231 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 11:11:35.491317 Pre-setting of DQS Precalculation
1379 11:11:35.498060 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 11:11:35.498154 ==
1381 11:11:35.501183 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 11:11:35.504932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 11:11:35.505018 ==
1384 11:11:35.511538 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 11:11:35.518124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 11:11:35.525779 [CA 0] Center 36 (6~67) winsize 62
1387 11:11:35.529617 [CA 1] Center 36 (6~67) winsize 62
1388 11:11:35.532601 [CA 2] Center 34 (4~65) winsize 62
1389 11:11:35.535997 [CA 3] Center 34 (4~65) winsize 62
1390 11:11:35.539372 [CA 4] Center 34 (4~65) winsize 62
1391 11:11:35.543011 [CA 5] Center 34 (4~64) winsize 61
1392 11:11:35.543096
1393 11:11:35.546429 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1394 11:11:35.546515
1395 11:11:35.549558 [CATrainingPosCal] consider 1 rank data
1396 11:11:35.552688 u2DelayCellTimex100 = 270/100 ps
1397 11:11:35.556554 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 11:11:35.559563 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 11:11:35.563136 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 11:11:35.569504 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 11:11:35.572883 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1402 11:11:35.576441 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1403 11:11:35.576526
1404 11:11:35.579402 CA PerBit enable=1, Macro0, CA PI delay=34
1405 11:11:35.579488
1406 11:11:35.583069 [CBTSetCACLKResult] CA Dly = 34
1407 11:11:35.583155 CS Dly: 6 (0~37)
1408 11:11:35.583244 ==
1409 11:11:35.586505 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 11:11:35.592660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 11:11:35.592745 ==
1412 11:11:35.596313 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 11:11:35.603119 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 11:11:35.612163 [CA 0] Center 36 (6~67) winsize 62
1415 11:11:35.615470 [CA 1] Center 36 (6~67) winsize 62
1416 11:11:35.618897 [CA 2] Center 35 (4~66) winsize 63
1417 11:11:35.622370 [CA 3] Center 35 (5~65) winsize 61
1418 11:11:35.625701 [CA 4] Center 35 (5~66) winsize 62
1419 11:11:35.629478 [CA 5] Center 34 (4~65) winsize 62
1420 11:11:35.629566
1421 11:11:35.633353 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1422 11:11:35.633439
1423 11:11:35.637175 [CATrainingPosCal] consider 2 rank data
1424 11:11:35.641077 u2DelayCellTimex100 = 270/100 ps
1425 11:11:35.644633 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 11:11:35.648752 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 11:11:35.652211 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 11:11:35.655975 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1429 11:11:35.656060 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1430 11:11:35.659796 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1431 11:11:35.663723
1432 11:11:35.666515 CA PerBit enable=1, Macro0, CA PI delay=34
1433 11:11:35.666601
1434 11:11:35.670434 [CBTSetCACLKResult] CA Dly = 34
1435 11:11:35.670519 CS Dly: 6 (0~38)
1436 11:11:35.670608
1437 11:11:35.673482 ----->DramcWriteLeveling(PI) begin...
1438 11:11:35.673598 ==
1439 11:11:35.676511 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 11:11:35.679988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 11:11:35.680074 ==
1442 11:11:35.683679 Write leveling (Byte 0): 29 => 29
1443 11:11:35.686927 Write leveling (Byte 1): 30 => 30
1444 11:11:35.690153 DramcWriteLeveling(PI) end<-----
1445 11:11:35.690237
1446 11:11:35.690323 ==
1447 11:11:35.693422 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 11:11:35.697064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 11:11:35.700633 ==
1450 11:11:35.700718 [Gating] SW mode calibration
1451 11:11:35.707185 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 11:11:35.713961 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 11:11:35.717380 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 11:11:35.724049 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 11:11:35.727185 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:11:35.730729 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:11:35.736950 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:11:35.740839 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:11:35.743968 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:11:35.747082 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:11:35.753962 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:11:35.756940 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:11:35.760363 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:11:35.767220 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:11:35.770213 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:11:35.774044 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:11:35.780529 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:11:35.783585 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:11:35.786984 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1470 11:11:35.793790 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1471 11:11:35.797136 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1472 11:11:35.800253 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:11:35.806958 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:11:35.810661 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:11:35.813653 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:11:35.820378 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:11:35.823935 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:11:35.826964 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1479 11:11:35.833583 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1480 11:11:35.837040 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 11:11:35.840579 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 11:11:35.843716 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 11:11:35.850501 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 11:11:35.853722 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 11:11:35.857020 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1486 11:11:35.863815 0 10 4 | B1->B0 | 3232 2e2e | 1 1 | (1 0) (0 0)
1487 11:11:35.866948 0 10 8 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (1 0)
1488 11:11:35.870391 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 11:11:35.877302 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 11:11:35.880363 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 11:11:35.883709 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 11:11:35.890692 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 11:11:35.893631 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 11:11:35.897303 0 11 4 | B1->B0 | 2b2b 3737 | 0 0 | (1 1) (1 1)
1495 11:11:35.903883 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1496 11:11:35.907265 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 11:11:35.910354 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 11:11:35.917165 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 11:11:35.920290 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 11:11:35.923948 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 11:11:35.930701 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 11:11:35.933624 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1503 11:11:35.937005 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:11:35.940638 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:11:35.947054 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:11:35.950275 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:11:35.953735 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:11:35.960478 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:11:35.963660 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:11:35.966907 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:11:35.973420 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:11:35.977039 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:11:35.980657 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:11:35.986941 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:11:35.990665 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 11:11:35.993995 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 11:11:36.000563 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1518 11:11:36.004187 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1519 11:11:36.007496 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 11:11:36.010697 Total UI for P1: 0, mck2ui 16
1521 11:11:36.014025 best dqsien dly found for B0: ( 0, 14, 2)
1522 11:11:36.017125 Total UI for P1: 0, mck2ui 16
1523 11:11:36.020481 best dqsien dly found for B1: ( 0, 14, 4)
1524 11:11:36.024487 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1525 11:11:36.027518 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1526 11:11:36.027601
1527 11:11:36.030082 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1528 11:11:36.037025 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1529 11:11:36.037132 [Gating] SW calibration Done
1530 11:11:36.037222 ==
1531 11:11:36.040091 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 11:11:36.047030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 11:11:36.047115 ==
1534 11:11:36.047181 RX Vref Scan: 0
1535 11:11:36.047242
1536 11:11:36.050708 RX Vref 0 -> 0, step: 1
1537 11:11:36.050790
1538 11:11:36.053876 RX Delay -130 -> 252, step: 16
1539 11:11:36.057454 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1540 11:11:36.060634 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1541 11:11:36.063616 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1542 11:11:36.070612 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1543 11:11:36.073925 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1544 11:11:36.077030 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1545 11:11:36.080741 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1546 11:11:36.083526 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1547 11:11:36.087190 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1548 11:11:36.094219 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1549 11:11:36.097318 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1550 11:11:36.100570 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1551 11:11:36.103979 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1552 11:11:36.106915 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1553 11:11:36.113953 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1554 11:11:36.117014 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1555 11:11:36.117140 ==
1556 11:11:36.120774 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 11:11:36.123726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 11:11:36.123857 ==
1559 11:11:36.126987 DQS Delay:
1560 11:11:36.127113 DQS0 = 0, DQS1 = 0
1561 11:11:36.127228 DQM Delay:
1562 11:11:36.130618 DQM0 = 93, DQM1 = 89
1563 11:11:36.130745 DQ Delay:
1564 11:11:36.133604 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1565 11:11:36.137454 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1566 11:11:36.140493 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1567 11:11:36.143920 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1568 11:11:36.144047
1569 11:11:36.144161
1570 11:11:36.144275 ==
1571 11:11:36.146816 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 11:11:36.153783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 11:11:36.153910 ==
1574 11:11:36.154027
1575 11:11:36.154138
1576 11:11:36.154252 TX Vref Scan disable
1577 11:11:36.157269 == TX Byte 0 ==
1578 11:11:36.160970 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1579 11:11:36.164016 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1580 11:11:36.167819 == TX Byte 1 ==
1581 11:11:36.170617 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1582 11:11:36.173802 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1583 11:11:36.177709 ==
1584 11:11:36.180963 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 11:11:36.184098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 11:11:36.184182 ==
1587 11:11:36.196249 TX Vref=22, minBit 7, minWin=26, winSum=437
1588 11:11:36.199678 TX Vref=24, minBit 7, minWin=26, winSum=439
1589 11:11:36.203283 TX Vref=26, minBit 1, minWin=27, winSum=445
1590 11:11:36.206897 TX Vref=28, minBit 1, minWin=27, winSum=448
1591 11:11:36.210551 TX Vref=30, minBit 2, minWin=26, winSum=445
1592 11:11:36.214175 TX Vref=32, minBit 2, minWin=26, winSum=444
1593 11:11:36.220466 [TxChooseVref] Worse bit 1, Min win 27, Win sum 448, Final Vref 28
1594 11:11:36.220551
1595 11:11:36.223677 Final TX Range 1 Vref 28
1596 11:11:36.223760
1597 11:11:36.223826 ==
1598 11:11:36.226963 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 11:11:36.230744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 11:11:36.230869 ==
1601 11:11:36.230986
1602 11:11:36.231098
1603 11:11:36.233758 TX Vref Scan disable
1604 11:11:36.237600 == TX Byte 0 ==
1605 11:11:36.240740 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1606 11:11:36.243766 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1607 11:11:36.246972 == TX Byte 1 ==
1608 11:11:36.250694 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1609 11:11:36.253763 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1610 11:11:36.253850
1611 11:11:36.253917 [DATLAT]
1612 11:11:36.257011 Freq=800, CH1 RK0
1613 11:11:36.257116
1614 11:11:36.260697 DATLAT Default: 0xa
1615 11:11:36.260775 0, 0xFFFF, sum = 0
1616 11:11:36.264319 1, 0xFFFF, sum = 0
1617 11:11:36.264417 2, 0xFFFF, sum = 0
1618 11:11:36.267494 3, 0xFFFF, sum = 0
1619 11:11:36.267607 4, 0xFFFF, sum = 0
1620 11:11:36.270640 5, 0xFFFF, sum = 0
1621 11:11:36.270770 6, 0xFFFF, sum = 0
1622 11:11:36.274254 7, 0xFFFF, sum = 0
1623 11:11:36.274377 8, 0xFFFF, sum = 0
1624 11:11:36.277456 9, 0x0, sum = 1
1625 11:11:36.277577 10, 0x0, sum = 2
1626 11:11:36.280451 11, 0x0, sum = 3
1627 11:11:36.280624 12, 0x0, sum = 4
1628 11:11:36.280785 best_step = 10
1629 11:11:36.280895
1630 11:11:36.284268 ==
1631 11:11:36.287605 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 11:11:36.290642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 11:11:36.290767 ==
1634 11:11:36.290881 RX Vref Scan: 1
1635 11:11:36.290991
1636 11:11:36.293899 Set Vref Range= 32 -> 127
1637 11:11:36.294020
1638 11:11:36.297296 RX Vref 32 -> 127, step: 1
1639 11:11:36.297420
1640 11:11:36.300500 RX Delay -63 -> 252, step: 8
1641 11:11:36.300663
1642 11:11:36.303742 Set Vref, RX VrefLevel [Byte0]: 32
1643 11:11:36.307232 [Byte1]: 32
1644 11:11:36.307357
1645 11:11:36.310765 Set Vref, RX VrefLevel [Byte0]: 33
1646 11:11:36.313670 [Byte1]: 33
1647 11:11:36.313839
1648 11:11:36.317066 Set Vref, RX VrefLevel [Byte0]: 34
1649 11:11:36.320472 [Byte1]: 34
1650 11:11:36.324043
1651 11:11:36.324165 Set Vref, RX VrefLevel [Byte0]: 35
1652 11:11:36.327017 [Byte1]: 35
1653 11:11:36.331361
1654 11:11:36.331481 Set Vref, RX VrefLevel [Byte0]: 36
1655 11:11:36.334684 [Byte1]: 36
1656 11:11:36.338959
1657 11:11:36.339080 Set Vref, RX VrefLevel [Byte0]: 37
1658 11:11:36.342100 [Byte1]: 37
1659 11:11:36.346093
1660 11:11:36.346241 Set Vref, RX VrefLevel [Byte0]: 38
1661 11:11:36.349976 [Byte1]: 38
1662 11:11:36.353736
1663 11:11:36.353856 Set Vref, RX VrefLevel [Byte0]: 39
1664 11:11:36.357507 [Byte1]: 39
1665 11:11:36.361222
1666 11:11:36.361349 Set Vref, RX VrefLevel [Byte0]: 40
1667 11:11:36.364970 [Byte1]: 40
1668 11:11:36.368634
1669 11:11:36.368760 Set Vref, RX VrefLevel [Byte0]: 41
1670 11:11:36.372416 [Byte1]: 41
1671 11:11:36.376209
1672 11:11:36.376343 Set Vref, RX VrefLevel [Byte0]: 42
1673 11:11:36.379906 [Byte1]: 42
1674 11:11:36.383618
1675 11:11:36.383746 Set Vref, RX VrefLevel [Byte0]: 43
1676 11:11:36.387100 [Byte1]: 43
1677 11:11:36.391442
1678 11:11:36.391568 Set Vref, RX VrefLevel [Byte0]: 44
1679 11:11:36.394707 [Byte1]: 44
1680 11:11:36.399076
1681 11:11:36.399201 Set Vref, RX VrefLevel [Byte0]: 45
1682 11:11:36.402190 [Byte1]: 45
1683 11:11:36.406344
1684 11:11:36.406469 Set Vref, RX VrefLevel [Byte0]: 46
1685 11:11:36.409480 [Byte1]: 46
1686 11:11:36.413651
1687 11:11:36.413765 Set Vref, RX VrefLevel [Byte0]: 47
1688 11:11:36.416997 [Byte1]: 47
1689 11:11:36.421486
1690 11:11:36.421570 Set Vref, RX VrefLevel [Byte0]: 48
1691 11:11:36.425005 [Byte1]: 48
1692 11:11:36.428831
1693 11:11:36.428914 Set Vref, RX VrefLevel [Byte0]: 49
1694 11:11:36.432263 [Byte1]: 49
1695 11:11:36.436079
1696 11:11:36.436188 Set Vref, RX VrefLevel [Byte0]: 50
1697 11:11:36.439765 [Byte1]: 50
1698 11:11:36.444176
1699 11:11:36.444297 Set Vref, RX VrefLevel [Byte0]: 51
1700 11:11:36.447460 [Byte1]: 51
1701 11:11:36.451151
1702 11:11:36.451234 Set Vref, RX VrefLevel [Byte0]: 52
1703 11:11:36.454852 [Byte1]: 52
1704 11:11:36.458708
1705 11:11:36.458829 Set Vref, RX VrefLevel [Byte0]: 53
1706 11:11:36.462340 [Byte1]: 53
1707 11:11:36.466028
1708 11:11:36.466134 Set Vref, RX VrefLevel [Byte0]: 54
1709 11:11:36.469458 [Byte1]: 54
1710 11:11:36.473798
1711 11:11:36.473919 Set Vref, RX VrefLevel [Byte0]: 55
1712 11:11:36.477459 [Byte1]: 55
1713 11:11:36.481328
1714 11:11:36.481409 Set Vref, RX VrefLevel [Byte0]: 56
1715 11:11:36.484395 [Byte1]: 56
1716 11:11:36.488823
1717 11:11:36.488904 Set Vref, RX VrefLevel [Byte0]: 57
1718 11:11:36.492153 [Byte1]: 57
1719 11:11:36.496104
1720 11:11:36.496186 Set Vref, RX VrefLevel [Byte0]: 58
1721 11:11:36.499441 [Byte1]: 58
1722 11:11:36.503936
1723 11:11:36.504018 Set Vref, RX VrefLevel [Byte0]: 59
1724 11:11:36.507061 [Byte1]: 59
1725 11:11:36.511417
1726 11:11:36.511548 Set Vref, RX VrefLevel [Byte0]: 60
1727 11:11:36.514593 [Byte1]: 60
1728 11:11:36.518815
1729 11:11:36.518912 Set Vref, RX VrefLevel [Byte0]: 61
1730 11:11:36.521939 [Byte1]: 61
1731 11:11:36.526229
1732 11:11:36.526352 Set Vref, RX VrefLevel [Byte0]: 62
1733 11:11:36.529466 [Byte1]: 62
1734 11:11:36.533829
1735 11:11:36.533952 Set Vref, RX VrefLevel [Byte0]: 63
1736 11:11:36.537392 [Byte1]: 63
1737 11:11:36.541491
1738 11:11:36.541613 Set Vref, RX VrefLevel [Byte0]: 64
1739 11:11:36.544972 [Byte1]: 64
1740 11:11:36.548555
1741 11:11:36.548678 Set Vref, RX VrefLevel [Byte0]: 65
1742 11:11:36.552242 [Byte1]: 65
1743 11:11:36.556479
1744 11:11:36.556602 Set Vref, RX VrefLevel [Byte0]: 66
1745 11:11:36.559504 [Byte1]: 66
1746 11:11:36.563882
1747 11:11:36.564000 Set Vref, RX VrefLevel [Byte0]: 67
1748 11:11:36.566988 [Byte1]: 67
1749 11:11:36.571369
1750 11:11:36.571491 Set Vref, RX VrefLevel [Byte0]: 68
1751 11:11:36.574577 [Byte1]: 68
1752 11:11:36.578970
1753 11:11:36.579092 Set Vref, RX VrefLevel [Byte0]: 69
1754 11:11:36.581984 [Byte1]: 69
1755 11:11:36.586398
1756 11:11:36.586519 Set Vref, RX VrefLevel [Byte0]: 70
1757 11:11:36.589572 [Byte1]: 70
1758 11:11:36.593462
1759 11:11:36.593584 Set Vref, RX VrefLevel [Byte0]: 71
1760 11:11:36.597157 [Byte1]: 71
1761 11:11:36.601537
1762 11:11:36.601660 Final RX Vref Byte 0 = 57 to rank0
1763 11:11:36.604463 Final RX Vref Byte 1 = 56 to rank0
1764 11:11:36.608118 Final RX Vref Byte 0 = 57 to rank1
1765 11:11:36.611428 Final RX Vref Byte 1 = 56 to rank1==
1766 11:11:36.614472 Dram Type= 6, Freq= 0, CH_1, rank 0
1767 11:11:36.621437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1768 11:11:36.621563 ==
1769 11:11:36.621678 DQS Delay:
1770 11:11:36.621786 DQS0 = 0, DQS1 = 0
1771 11:11:36.624422 DQM Delay:
1772 11:11:36.624543 DQM0 = 94, DQM1 = 90
1773 11:11:36.627984 DQ Delay:
1774 11:11:36.631079 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =96
1775 11:11:36.634332 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =92
1776 11:11:36.638132 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1777 11:11:36.641321 DQ12 =96, DQ13 =100, DQ14 =96, DQ15 =96
1778 11:11:36.641442
1779 11:11:36.641552
1780 11:11:36.647916 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1781 11:11:36.651611 CH1 RK0: MR19=606, MR18=2D49
1782 11:11:36.658092 CH1_RK0: MR19=0x606, MR18=0x2D49, DQSOSC=391, MR23=63, INC=96, DEC=64
1783 11:11:36.658197
1784 11:11:36.661554 ----->DramcWriteLeveling(PI) begin...
1785 11:11:36.661668 ==
1786 11:11:36.664837 Dram Type= 6, Freq= 0, CH_1, rank 1
1787 11:11:36.667968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 11:11:36.668089 ==
1789 11:11:36.671398 Write leveling (Byte 0): 26 => 26
1790 11:11:36.674905 Write leveling (Byte 1): 26 => 26
1791 11:11:36.678074 DramcWriteLeveling(PI) end<-----
1792 11:11:36.678216
1793 11:11:36.678358 ==
1794 11:11:36.681328 Dram Type= 6, Freq= 0, CH_1, rank 1
1795 11:11:36.684582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 11:11:36.684704 ==
1797 11:11:36.688211 [Gating] SW mode calibration
1798 11:11:36.695095 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1799 11:11:36.701636 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1800 11:11:36.704823 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1801 11:11:36.708165 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1802 11:11:36.714757 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 11:11:36.717975 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 11:11:36.721306 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 11:11:36.728054 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 11:11:36.731832 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 11:11:36.735344 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 11:11:36.741688 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 11:11:36.744925 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 11:11:36.748086 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 11:11:36.751676 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 11:11:36.758496 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 11:11:36.761380 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 11:11:36.765298 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 11:11:36.771870 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:11:36.774756 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1817 11:11:36.778128 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1818 11:11:36.784946 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:11:36.788155 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:11:36.791428 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:11:36.798056 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:11:36.801390 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:11:36.805059 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:11:36.811458 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:11:36.815021 0 9 4 | B1->B0 | 2d2d 2323 | 1 0 | (1 1) (0 0)
1826 11:11:36.818458 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1827 11:11:36.825162 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 11:11:36.828767 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 11:11:36.831684 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 11:11:36.838354 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 11:11:36.841907 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 11:11:36.844995 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 11:11:36.848373 0 10 4 | B1->B0 | 2e2e 3030 | 1 0 | (1 0) (0 1)
1834 11:11:36.855211 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 11:11:36.858242 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 11:11:36.861901 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 11:11:36.868190 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 11:11:36.872009 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 11:11:36.875064 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 11:11:36.881772 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 11:11:36.885483 0 11 4 | B1->B0 | 3b3b 2b2b | 1 0 | (0 0) (1 1)
1842 11:11:36.888482 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1843 11:11:36.895289 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 11:11:36.898667 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 11:11:36.902248 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 11:11:36.908495 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 11:11:36.912203 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 11:11:36.915222 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1849 11:11:36.918891 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1850 11:11:36.925134 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 11:11:36.928442 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 11:11:36.931759 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 11:11:36.938599 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 11:11:36.942052 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 11:11:36.945058 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 11:11:36.951707 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 11:11:36.955382 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 11:11:36.958723 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 11:11:36.965384 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 11:11:36.968721 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 11:11:36.971923 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 11:11:36.978390 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 11:11:36.982025 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:11:36.985658 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:11:36.991943 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1866 11:11:36.995507 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 11:11:36.998612 Total UI for P1: 0, mck2ui 16
1868 11:11:37.002228 best dqsien dly found for B0: ( 0, 14, 4)
1869 11:11:37.005211 Total UI for P1: 0, mck2ui 16
1870 11:11:37.008805 best dqsien dly found for B1: ( 0, 14, 6)
1871 11:11:37.012381 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1872 11:11:37.015484 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1873 11:11:37.015568
1874 11:11:37.018615 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1875 11:11:37.022432 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1876 11:11:37.025730 [Gating] SW calibration Done
1877 11:11:37.025813 ==
1878 11:11:37.029041 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 11:11:37.032149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 11:11:37.032233 ==
1881 11:11:37.035317 RX Vref Scan: 0
1882 11:11:37.035401
1883 11:11:37.035467 RX Vref 0 -> 0, step: 1
1884 11:11:37.035528
1885 11:11:37.038991 RX Delay -130 -> 252, step: 16
1886 11:11:37.041888 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1887 11:11:37.048598 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1888 11:11:37.052198 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1889 11:11:37.055646 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1890 11:11:37.058964 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1891 11:11:37.062549 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1892 11:11:37.069066 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1893 11:11:37.072636 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1894 11:11:37.075645 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1895 11:11:37.079081 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1896 11:11:37.082036 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1897 11:11:37.088868 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1898 11:11:37.092443 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1899 11:11:37.095553 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1900 11:11:37.099146 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1901 11:11:37.102201 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1902 11:11:37.106059 ==
1903 11:11:37.106142 Dram Type= 6, Freq= 0, CH_1, rank 1
1904 11:11:37.112196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1905 11:11:37.112313 ==
1906 11:11:37.112410 DQS Delay:
1907 11:11:37.115754 DQS0 = 0, DQS1 = 0
1908 11:11:37.115851 DQM Delay:
1909 11:11:37.119174 DQM0 = 92, DQM1 = 87
1910 11:11:37.119257 DQ Delay:
1911 11:11:37.122316 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1912 11:11:37.125680 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1913 11:11:37.128927 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1914 11:11:37.132071 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1915 11:11:37.132154
1916 11:11:37.132220
1917 11:11:37.132280 ==
1918 11:11:37.135924 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 11:11:37.139009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 11:11:37.139093 ==
1921 11:11:37.139159
1922 11:11:37.139220
1923 11:11:37.142128 TX Vref Scan disable
1924 11:11:37.145778 == TX Byte 0 ==
1925 11:11:37.149393 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1926 11:11:37.152325 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1927 11:11:37.156028 == TX Byte 1 ==
1928 11:11:37.159223 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1929 11:11:37.162231 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1930 11:11:37.162314 ==
1931 11:11:37.165913 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 11:11:37.169179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 11:11:37.172642 ==
1934 11:11:37.183901 TX Vref=22, minBit 0, minWin=27, winSum=437
1935 11:11:37.187394 TX Vref=24, minBit 0, minWin=27, winSum=438
1936 11:11:37.190281 TX Vref=26, minBit 1, minWin=27, winSum=444
1937 11:11:37.193609 TX Vref=28, minBit 2, minWin=27, winSum=444
1938 11:11:37.197104 TX Vref=30, minBit 2, minWin=27, winSum=449
1939 11:11:37.200585 TX Vref=32, minBit 0, minWin=27, winSum=444
1940 11:11:37.207267 [TxChooseVref] Worse bit 2, Min win 27, Win sum 449, Final Vref 30
1941 11:11:37.207393
1942 11:11:37.210368 Final TX Range 1 Vref 30
1943 11:11:37.210492
1944 11:11:37.210603 ==
1945 11:11:37.214111 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 11:11:37.217228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 11:11:37.217353 ==
1948 11:11:37.217464
1949 11:11:37.217573
1950 11:11:37.220235 TX Vref Scan disable
1951 11:11:37.223436 == TX Byte 0 ==
1952 11:11:37.226864 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1953 11:11:37.230094 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1954 11:11:37.233991 == TX Byte 1 ==
1955 11:11:37.237070 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1956 11:11:37.240300 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1957 11:11:37.240414
1958 11:11:37.244108 [DATLAT]
1959 11:11:37.244191 Freq=800, CH1 RK1
1960 11:11:37.244257
1961 11:11:37.247146 DATLAT Default: 0xa
1962 11:11:37.247277 0, 0xFFFF, sum = 0
1963 11:11:37.250382 1, 0xFFFF, sum = 0
1964 11:11:37.250465 2, 0xFFFF, sum = 0
1965 11:11:37.253999 3, 0xFFFF, sum = 0
1966 11:11:37.254110 4, 0xFFFF, sum = 0
1967 11:11:37.256990 5, 0xFFFF, sum = 0
1968 11:11:37.257073 6, 0xFFFF, sum = 0
1969 11:11:37.260438 7, 0xFFFF, sum = 0
1970 11:11:37.260552 8, 0xFFFF, sum = 0
1971 11:11:37.263579 9, 0x0, sum = 1
1972 11:11:37.263676 10, 0x0, sum = 2
1973 11:11:37.267355 11, 0x0, sum = 3
1974 11:11:37.267466 12, 0x0, sum = 4
1975 11:11:37.270382 best_step = 10
1976 11:11:37.270478
1977 11:11:37.270543 ==
1978 11:11:37.273448 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 11:11:37.276967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 11:11:37.277050 ==
1981 11:11:37.280343 RX Vref Scan: 0
1982 11:11:37.280438
1983 11:11:37.280502 RX Vref 0 -> 0, step: 1
1984 11:11:37.280560
1985 11:11:37.283963 RX Delay -79 -> 252, step: 8
1986 11:11:37.290214 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1987 11:11:37.293890 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1988 11:11:37.297137 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1989 11:11:37.300546 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1990 11:11:37.304101 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1991 11:11:37.307309 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1992 11:11:37.310740 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1993 11:11:37.317342 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1994 11:11:37.321122 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1995 11:11:37.324221 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1996 11:11:37.327204 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
1997 11:11:37.330983 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
1998 11:11:37.337812 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1999 11:11:37.340700 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2000 11:11:37.344016 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2001 11:11:37.347534 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2002 11:11:37.347642 ==
2003 11:11:37.351050 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 11:11:37.354165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 11:11:37.357958 ==
2006 11:11:37.358039 DQS Delay:
2007 11:11:37.358101 DQS0 = 0, DQS1 = 0
2008 11:11:37.360959 DQM Delay:
2009 11:11:37.361061 DQM0 = 97, DQM1 = 91
2010 11:11:37.364237 DQ Delay:
2011 11:11:37.364336 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2012 11:11:37.367739 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2013 11:11:37.370675 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2014 11:11:37.374512 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2015 11:11:37.377686
2016 11:11:37.377758
2017 11:11:37.384507 [DQSOSCAuto] RK1, (LSB)MR18= 0x4913, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2018 11:11:37.387927 CH1 RK1: MR19=606, MR18=4913
2019 11:11:37.394068 CH1_RK1: MR19=0x606, MR18=0x4913, DQSOSC=391, MR23=63, INC=96, DEC=64
2020 11:11:37.397648 [RxdqsGatingPostProcess] freq 800
2021 11:11:37.400773 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2022 11:11:37.404478 Pre-setting of DQS Precalculation
2023 11:11:37.411342 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2024 11:11:37.417746 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2025 11:11:37.424385 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2026 11:11:37.424472
2027 11:11:37.424538
2028 11:11:37.428034 [Calibration Summary] 1600 Mbps
2029 11:11:37.428137 CH 0, Rank 0
2030 11:11:37.431321 SW Impedance : PASS
2031 11:11:37.431421 DUTY Scan : NO K
2032 11:11:37.434586 ZQ Calibration : PASS
2033 11:11:37.438417 Jitter Meter : NO K
2034 11:11:37.438500 CBT Training : PASS
2035 11:11:37.441528 Write leveling : PASS
2036 11:11:37.444547 RX DQS gating : PASS
2037 11:11:37.444630 RX DQ/DQS(RDDQC) : PASS
2038 11:11:37.448194 TX DQ/DQS : PASS
2039 11:11:37.451053 RX DATLAT : PASS
2040 11:11:37.451135 RX DQ/DQS(Engine): PASS
2041 11:11:37.454430 TX OE : NO K
2042 11:11:37.454513 All Pass.
2043 11:11:37.454578
2044 11:11:37.457852 CH 0, Rank 1
2045 11:11:37.457934 SW Impedance : PASS
2046 11:11:37.461419 DUTY Scan : NO K
2047 11:11:37.464553 ZQ Calibration : PASS
2048 11:11:37.464633 Jitter Meter : NO K
2049 11:11:37.468138 CBT Training : PASS
2050 11:11:37.468219 Write leveling : PASS
2051 11:11:37.471634 RX DQS gating : PASS
2052 11:11:37.475022 RX DQ/DQS(RDDQC) : PASS
2053 11:11:37.475103 TX DQ/DQS : PASS
2054 11:11:37.478032 RX DATLAT : PASS
2055 11:11:37.481254 RX DQ/DQS(Engine): PASS
2056 11:11:37.481348 TX OE : NO K
2057 11:11:37.484968 All Pass.
2058 11:11:37.485048
2059 11:11:37.485111 CH 1, Rank 0
2060 11:11:37.487971 SW Impedance : PASS
2061 11:11:37.488082 DUTY Scan : NO K
2062 11:11:37.491193 ZQ Calibration : PASS
2063 11:11:37.494795 Jitter Meter : NO K
2064 11:11:37.494875 CBT Training : PASS
2065 11:11:37.497884 Write leveling : PASS
2066 11:11:37.501262 RX DQS gating : PASS
2067 11:11:37.501343 RX DQ/DQS(RDDQC) : PASS
2068 11:11:37.504951 TX DQ/DQS : PASS
2069 11:11:37.505031 RX DATLAT : PASS
2070 11:11:37.508085 RX DQ/DQS(Engine): PASS
2071 11:11:37.511690 TX OE : NO K
2072 11:11:37.511772 All Pass.
2073 11:11:37.511835
2074 11:11:37.511894 CH 1, Rank 1
2075 11:11:37.514703 SW Impedance : PASS
2076 11:11:37.517923 DUTY Scan : NO K
2077 11:11:37.518019 ZQ Calibration : PASS
2078 11:11:37.521781 Jitter Meter : NO K
2079 11:11:37.524752 CBT Training : PASS
2080 11:11:37.524833 Write leveling : PASS
2081 11:11:37.528508 RX DQS gating : PASS
2082 11:11:37.531388 RX DQ/DQS(RDDQC) : PASS
2083 11:11:37.531485 TX DQ/DQS : PASS
2084 11:11:37.534918 RX DATLAT : PASS
2085 11:11:37.538283 RX DQ/DQS(Engine): PASS
2086 11:11:37.538379 TX OE : NO K
2087 11:11:37.538474 All Pass.
2088 11:11:37.541219
2089 11:11:37.541316 DramC Write-DBI off
2090 11:11:37.544927 PER_BANK_REFRESH: Hybrid Mode
2091 11:11:37.545024 TX_TRACKING: ON
2092 11:11:37.548035 [GetDramInforAfterCalByMRR] Vendor 6.
2093 11:11:37.551261 [GetDramInforAfterCalByMRR] Revision 606.
2094 11:11:37.558082 [GetDramInforAfterCalByMRR] Revision 2 0.
2095 11:11:37.558180 MR0 0x3b3b
2096 11:11:37.558258 MR8 0x5151
2097 11:11:37.561639 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 11:11:37.561738
2099 11:11:37.564902 MR0 0x3b3b
2100 11:11:37.564998 MR8 0x5151
2101 11:11:37.568292 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2102 11:11:37.568404
2103 11:11:37.578102 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2104 11:11:37.581582 [FAST_K] Save calibration result to emmc
2105 11:11:37.585006 [FAST_K] Save calibration result to emmc
2106 11:11:37.588042 dram_init: config_dvfs: 1
2107 11:11:37.591893 dramc_set_vcore_voltage set vcore to 662500
2108 11:11:37.591974 Read voltage for 1200, 2
2109 11:11:37.595098 Vio18 = 0
2110 11:11:37.595178 Vcore = 662500
2111 11:11:37.595241 Vdram = 0
2112 11:11:37.598153 Vddq = 0
2113 11:11:37.598233 Vmddr = 0
2114 11:11:37.602012 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2115 11:11:37.608204 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2116 11:11:37.611847 MEM_TYPE=3, freq_sel=15
2117 11:11:37.614788 sv_algorithm_assistance_LP4_1600
2118 11:11:37.618641 ============ PULL DRAM RESETB DOWN ============
2119 11:11:37.621852 ========== PULL DRAM RESETB DOWN end =========
2120 11:11:37.628441 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2121 11:11:37.628568 ===================================
2122 11:11:37.631373 LPDDR4 DRAM CONFIGURATION
2123 11:11:37.635138 ===================================
2124 11:11:37.638332 EX_ROW_EN[0] = 0x0
2125 11:11:37.638454 EX_ROW_EN[1] = 0x0
2126 11:11:37.642017 LP4Y_EN = 0x0
2127 11:11:37.642137 WORK_FSP = 0x0
2128 11:11:37.645285 WL = 0x4
2129 11:11:37.645407 RL = 0x4
2130 11:11:37.648788 BL = 0x2
2131 11:11:37.648907 RPST = 0x0
2132 11:11:37.651617 RD_PRE = 0x0
2133 11:11:37.651736 WR_PRE = 0x1
2134 11:11:37.655459 WR_PST = 0x0
2135 11:11:37.655581 DBI_WR = 0x0
2136 11:11:37.658691 DBI_RD = 0x0
2137 11:11:37.661979 OTF = 0x1
2138 11:11:37.665106 ===================================
2139 11:11:37.665230 ===================================
2140 11:11:37.668517 ANA top config
2141 11:11:37.672082 ===================================
2142 11:11:37.674921 DLL_ASYNC_EN = 0
2143 11:11:37.675045 ALL_SLAVE_EN = 0
2144 11:11:37.678435 NEW_RANK_MODE = 1
2145 11:11:37.681930 DLL_IDLE_MODE = 1
2146 11:11:37.684907 LP45_APHY_COMB_EN = 1
2147 11:11:37.688705 TX_ODT_DIS = 1
2148 11:11:37.688825 NEW_8X_MODE = 1
2149 11:11:37.691628 ===================================
2150 11:11:37.695224 ===================================
2151 11:11:37.698381 data_rate = 2400
2152 11:11:37.702112 CKR = 1
2153 11:11:37.705360 DQ_P2S_RATIO = 8
2154 11:11:37.708540 ===================================
2155 11:11:37.711646 CA_P2S_RATIO = 8
2156 11:11:37.711743 DQ_CA_OPEN = 0
2157 11:11:37.715343 DQ_SEMI_OPEN = 0
2158 11:11:37.718417 CA_SEMI_OPEN = 0
2159 11:11:37.721659 CA_FULL_RATE = 0
2160 11:11:37.725172 DQ_CKDIV4_EN = 0
2161 11:11:37.728808 CA_CKDIV4_EN = 0
2162 11:11:37.728890 CA_PREDIV_EN = 0
2163 11:11:37.731671 PH8_DLY = 17
2164 11:11:37.735042 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2165 11:11:37.738354 DQ_AAMCK_DIV = 4
2166 11:11:37.742075 CA_AAMCK_DIV = 4
2167 11:11:37.745090 CA_ADMCK_DIV = 4
2168 11:11:37.745172 DQ_TRACK_CA_EN = 0
2169 11:11:37.748695 CA_PICK = 1200
2170 11:11:37.751659 CA_MCKIO = 1200
2171 11:11:37.755297 MCKIO_SEMI = 0
2172 11:11:37.758439 PLL_FREQ = 2366
2173 11:11:37.762027 DQ_UI_PI_RATIO = 32
2174 11:11:37.765107 CA_UI_PI_RATIO = 0
2175 11:11:37.768374 ===================================
2176 11:11:37.771917 ===================================
2177 11:11:37.771999 memory_type:LPDDR4
2178 11:11:37.775033 GP_NUM : 10
2179 11:11:37.778576 SRAM_EN : 1
2180 11:11:37.778659 MD32_EN : 0
2181 11:11:37.782131 ===================================
2182 11:11:37.785131 [ANA_INIT] >>>>>>>>>>>>>>
2183 11:11:37.788749 <<<<<< [CONFIGURE PHASE]: ANA_TX
2184 11:11:37.791951 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2185 11:11:37.795567 ===================================
2186 11:11:37.798999 data_rate = 2400,PCW = 0X5b00
2187 11:11:37.799082 ===================================
2188 11:11:37.805467 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2189 11:11:37.809080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2190 11:11:37.815453 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2191 11:11:37.818615 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2192 11:11:37.822421 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2193 11:11:37.825590 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2194 11:11:37.829093 [ANA_INIT] flow start
2195 11:11:37.832231 [ANA_INIT] PLL >>>>>>>>
2196 11:11:37.832363 [ANA_INIT] PLL <<<<<<<<
2197 11:11:37.835379 [ANA_INIT] MIDPI >>>>>>>>
2198 11:11:37.839127 [ANA_INIT] MIDPI <<<<<<<<
2199 11:11:37.839209 [ANA_INIT] DLL >>>>>>>>
2200 11:11:37.842185 [ANA_INIT] DLL <<<<<<<<
2201 11:11:37.845706 [ANA_INIT] flow end
2202 11:11:37.848519 ============ LP4 DIFF to SE enter ============
2203 11:11:37.852100 ============ LP4 DIFF to SE exit ============
2204 11:11:37.855311 [ANA_INIT] <<<<<<<<<<<<<
2205 11:11:37.859016 [Flow] Enable top DCM control >>>>>
2206 11:11:37.862159 [Flow] Enable top DCM control <<<<<
2207 11:11:37.865969 Enable DLL master slave shuffle
2208 11:11:37.868710 ==============================================================
2209 11:11:37.872107 Gating Mode config
2210 11:11:37.875577 ==============================================================
2211 11:11:37.879285 Config description:
2212 11:11:37.889013 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2213 11:11:37.895956 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2214 11:11:37.898985 SELPH_MODE 0: By rank 1: By Phase
2215 11:11:37.906199 ==============================================================
2216 11:11:37.908952 GAT_TRACK_EN = 1
2217 11:11:37.912270 RX_GATING_MODE = 2
2218 11:11:37.915633 RX_GATING_TRACK_MODE = 2
2219 11:11:37.915732 SELPH_MODE = 1
2220 11:11:37.919425 PICG_EARLY_EN = 1
2221 11:11:37.922704 VALID_LAT_VALUE = 1
2222 11:11:37.929563 ==============================================================
2223 11:11:37.932508 Enter into Gating configuration >>>>
2224 11:11:37.936054 Exit from Gating configuration <<<<
2225 11:11:37.939330 Enter into DVFS_PRE_config >>>>>
2226 11:11:37.949386 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2227 11:11:37.952949 Exit from DVFS_PRE_config <<<<<
2228 11:11:37.956132 Enter into PICG configuration >>>>
2229 11:11:37.959345 Exit from PICG configuration <<<<
2230 11:11:37.963033 [RX_INPUT] configuration >>>>>
2231 11:11:37.966051 [RX_INPUT] configuration <<<<<
2232 11:11:37.969461 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2233 11:11:37.975946 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2234 11:11:37.982951 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2235 11:11:37.989660 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2236 11:11:37.992738 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 11:11:37.999721 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 11:11:38.002974 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2239 11:11:38.009511 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2240 11:11:38.012674 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2241 11:11:38.016142 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2242 11:11:38.019961 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2243 11:11:38.025945 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2244 11:11:38.029183 ===================================
2245 11:11:38.029266 LPDDR4 DRAM CONFIGURATION
2246 11:11:38.033028 ===================================
2247 11:11:38.036113 EX_ROW_EN[0] = 0x0
2248 11:11:38.039491 EX_ROW_EN[1] = 0x0
2249 11:11:38.039573 LP4Y_EN = 0x0
2250 11:11:38.042683 WORK_FSP = 0x0
2251 11:11:38.042765 WL = 0x4
2252 11:11:38.045985 RL = 0x4
2253 11:11:38.046067 BL = 0x2
2254 11:11:38.049738 RPST = 0x0
2255 11:11:38.049820 RD_PRE = 0x0
2256 11:11:38.052933 WR_PRE = 0x1
2257 11:11:38.053014 WR_PST = 0x0
2258 11:11:38.055919 DBI_WR = 0x0
2259 11:11:38.056001 DBI_RD = 0x0
2260 11:11:38.059633 OTF = 0x1
2261 11:11:38.062810 ===================================
2262 11:11:38.066001 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2263 11:11:38.069727 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2264 11:11:38.076098 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 11:11:38.076181 ===================================
2266 11:11:38.079867 LPDDR4 DRAM CONFIGURATION
2267 11:11:38.083010 ===================================
2268 11:11:38.086385 EX_ROW_EN[0] = 0x10
2269 11:11:38.086469 EX_ROW_EN[1] = 0x0
2270 11:11:38.089755 LP4Y_EN = 0x0
2271 11:11:38.089837 WORK_FSP = 0x0
2272 11:11:38.093155 WL = 0x4
2273 11:11:38.093237 RL = 0x4
2274 11:11:38.096027 BL = 0x2
2275 11:11:38.096109 RPST = 0x0
2276 11:11:38.099532 RD_PRE = 0x0
2277 11:11:38.099614 WR_PRE = 0x1
2278 11:11:38.102932 WR_PST = 0x0
2279 11:11:38.106849 DBI_WR = 0x0
2280 11:11:38.106931 DBI_RD = 0x0
2281 11:11:38.109713 OTF = 0x1
2282 11:11:38.109795 ===================================
2283 11:11:38.116631 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2284 11:11:38.116716 ==
2285 11:11:38.119981 Dram Type= 6, Freq= 0, CH_0, rank 0
2286 11:11:38.126378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2287 11:11:38.126460 ==
2288 11:11:38.126524 [Duty_Offset_Calibration]
2289 11:11:38.129852 B0:2 B1:1 CA:1
2290 11:11:38.129957
2291 11:11:38.133293 [DutyScan_Calibration_Flow] k_type=0
2292 11:11:38.142080
2293 11:11:38.142161 ==CLK 0==
2294 11:11:38.145681 Final CLK duty delay cell = 0
2295 11:11:38.148781 [0] MAX Duty = 5218%(X100), DQS PI = 24
2296 11:11:38.152482 [0] MIN Duty = 4875%(X100), DQS PI = 0
2297 11:11:38.152563 [0] AVG Duty = 5046%(X100)
2298 11:11:38.155678
2299 11:11:38.158933 CH0 CLK Duty spec in!! Max-Min= 343%
2300 11:11:38.161998 [DutyScan_Calibration_Flow] ====Done====
2301 11:11:38.162095
2302 11:11:38.165574 [DutyScan_Calibration_Flow] k_type=1
2303 11:11:38.180824
2304 11:11:38.180905 ==DQS 0 ==
2305 11:11:38.183979 Final DQS duty delay cell = -4
2306 11:11:38.187226 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2307 11:11:38.191038 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2308 11:11:38.194034 [-4] AVG Duty = 4937%(X100)
2309 11:11:38.194158
2310 11:11:38.194220 ==DQS 1 ==
2311 11:11:38.197666 Final DQS duty delay cell = 0
2312 11:11:38.200645 [0] MAX Duty = 5156%(X100), DQS PI = 0
2313 11:11:38.204280 [0] MIN Duty = 5031%(X100), DQS PI = 32
2314 11:11:38.207435 [0] AVG Duty = 5093%(X100)
2315 11:11:38.207516
2316 11:11:38.210497 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2317 11:11:38.210580
2318 11:11:38.214013 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2319 11:11:38.217580 [DutyScan_Calibration_Flow] ====Done====
2320 11:11:38.217660
2321 11:11:38.220579 [DutyScan_Calibration_Flow] k_type=3
2322 11:11:38.237763
2323 11:11:38.237845 ==DQM 0 ==
2324 11:11:38.241199 Final DQM duty delay cell = 0
2325 11:11:38.244535 [0] MAX Duty = 5156%(X100), DQS PI = 30
2326 11:11:38.247580 [0] MIN Duty = 4875%(X100), DQS PI = 58
2327 11:11:38.247662 [0] AVG Duty = 5015%(X100)
2328 11:11:38.250965
2329 11:11:38.251046 ==DQM 1 ==
2330 11:11:38.254323 Final DQM duty delay cell = 0
2331 11:11:38.257447 [0] MAX Duty = 5093%(X100), DQS PI = 0
2332 11:11:38.260719 [0] MIN Duty = 5000%(X100), DQS PI = 16
2333 11:11:38.260802 [0] AVG Duty = 5046%(X100)
2334 11:11:38.260866
2335 11:11:38.267803 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2336 11:11:38.267886
2337 11:11:38.270946 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2338 11:11:38.274050 [DutyScan_Calibration_Flow] ====Done====
2339 11:11:38.274133
2340 11:11:38.277284 [DutyScan_Calibration_Flow] k_type=2
2341 11:11:38.293808
2342 11:11:38.293892 ==DQ 0 ==
2343 11:11:38.297484 Final DQ duty delay cell = 0
2344 11:11:38.300672 [0] MAX Duty = 5031%(X100), DQS PI = 26
2345 11:11:38.304298 [0] MIN Duty = 4875%(X100), DQS PI = 62
2346 11:11:38.304408 [0] AVG Duty = 4953%(X100)
2347 11:11:38.304501
2348 11:11:38.307198 ==DQ 1 ==
2349 11:11:38.310535 Final DQ duty delay cell = 0
2350 11:11:38.313942 [0] MAX Duty = 5093%(X100), DQS PI = 24
2351 11:11:38.317589 [0] MIN Duty = 4938%(X100), DQS PI = 34
2352 11:11:38.317672 [0] AVG Duty = 5015%(X100)
2353 11:11:38.317736
2354 11:11:38.320630 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2355 11:11:38.324243
2356 11:11:38.324344 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2357 11:11:38.330778 [DutyScan_Calibration_Flow] ====Done====
2358 11:11:38.330868 ==
2359 11:11:38.334411 Dram Type= 6, Freq= 0, CH_1, rank 0
2360 11:11:38.337372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2361 11:11:38.337454 ==
2362 11:11:38.341157 [Duty_Offset_Calibration]
2363 11:11:38.341239 B0:1 B1:0 CA:0
2364 11:11:38.341303
2365 11:11:38.344098 [DutyScan_Calibration_Flow] k_type=0
2366 11:11:38.353118
2367 11:11:38.353219 ==CLK 0==
2368 11:11:38.356198 Final CLK duty delay cell = -4
2369 11:11:38.359957 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2370 11:11:38.363284 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2371 11:11:38.366331 [-4] AVG Duty = 4953%(X100)
2372 11:11:38.366432
2373 11:11:38.369887 CH1 CLK Duty spec in!! Max-Min= 156%
2374 11:11:38.373327 [DutyScan_Calibration_Flow] ====Done====
2375 11:11:38.373426
2376 11:11:38.376477 [DutyScan_Calibration_Flow] k_type=1
2377 11:11:38.393030
2378 11:11:38.393112 ==DQS 0 ==
2379 11:11:38.396129 Final DQS duty delay cell = 0
2380 11:11:38.400003 [0] MAX Duty = 5094%(X100), DQS PI = 26
2381 11:11:38.403081 [0] MIN Duty = 4875%(X100), DQS PI = 0
2382 11:11:38.403162 [0] AVG Duty = 4984%(X100)
2383 11:11:38.406097
2384 11:11:38.406178 ==DQS 1 ==
2385 11:11:38.409883 Final DQS duty delay cell = 0
2386 11:11:38.412897 [0] MAX Duty = 5218%(X100), DQS PI = 20
2387 11:11:38.416205 [0] MIN Duty = 4969%(X100), DQS PI = 10
2388 11:11:38.416318 [0] AVG Duty = 5093%(X100)
2389 11:11:38.419738
2390 11:11:38.423089 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2391 11:11:38.423171
2392 11:11:38.426225 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2393 11:11:38.429672 [DutyScan_Calibration_Flow] ====Done====
2394 11:11:38.429755
2395 11:11:38.433180 [DutyScan_Calibration_Flow] k_type=3
2396 11:11:38.449564
2397 11:11:38.449646 ==DQM 0 ==
2398 11:11:38.453065 Final DQM duty delay cell = 0
2399 11:11:38.456007 [0] MAX Duty = 5156%(X100), DQS PI = 6
2400 11:11:38.459630 [0] MIN Duty = 5031%(X100), DQS PI = 0
2401 11:11:38.459710 [0] AVG Duty = 5093%(X100)
2402 11:11:38.459773
2403 11:11:38.462701 ==DQM 1 ==
2404 11:11:38.466529 Final DQM duty delay cell = 0
2405 11:11:38.469639 [0] MAX Duty = 5031%(X100), DQS PI = 26
2406 11:11:38.473160 [0] MIN Duty = 4907%(X100), DQS PI = 36
2407 11:11:38.473240 [0] AVG Duty = 4969%(X100)
2408 11:11:38.473302
2409 11:11:38.476243 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2410 11:11:38.479762
2411 11:11:38.482802 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2412 11:11:38.486095 [DutyScan_Calibration_Flow] ====Done====
2413 11:11:38.486176
2414 11:11:38.489475 [DutyScan_Calibration_Flow] k_type=2
2415 11:11:38.505246
2416 11:11:38.505339 ==DQ 0 ==
2417 11:11:38.509042 Final DQ duty delay cell = -4
2418 11:11:38.512183 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2419 11:11:38.515438 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2420 11:11:38.519020 [-4] AVG Duty = 4984%(X100)
2421 11:11:38.519121
2422 11:11:38.519186 ==DQ 1 ==
2423 11:11:38.522190 Final DQ duty delay cell = 0
2424 11:11:38.525241 [0] MAX Duty = 5125%(X100), DQS PI = 20
2425 11:11:38.528896 [0] MIN Duty = 4969%(X100), DQS PI = 12
2426 11:11:38.529027 [0] AVG Duty = 5047%(X100)
2427 11:11:38.529092
2428 11:11:38.535622 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2429 11:11:38.535702
2430 11:11:38.539071 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2431 11:11:38.541880 [DutyScan_Calibration_Flow] ====Done====
2432 11:11:38.545376 nWR fixed to 30
2433 11:11:38.545483 [ModeRegInit_LP4] CH0 RK0
2434 11:11:38.549079 [ModeRegInit_LP4] CH0 RK1
2435 11:11:38.552496 [ModeRegInit_LP4] CH1 RK0
2436 11:11:38.552577 [ModeRegInit_LP4] CH1 RK1
2437 11:11:38.555441 match AC timing 7
2438 11:11:38.559114 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2439 11:11:38.561995 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2440 11:11:38.569117 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2441 11:11:38.572299 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2442 11:11:38.578790 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2443 11:11:38.578871 ==
2444 11:11:38.582415 Dram Type= 6, Freq= 0, CH_0, rank 0
2445 11:11:38.585569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2446 11:11:38.585662 ==
2447 11:11:38.592484 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2448 11:11:38.595510 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2449 11:11:38.605449 [CA 0] Center 39 (8~70) winsize 63
2450 11:11:38.608977 [CA 1] Center 39 (8~70) winsize 63
2451 11:11:38.611978 [CA 2] Center 35 (5~66) winsize 62
2452 11:11:38.615713 [CA 3] Center 34 (4~65) winsize 62
2453 11:11:38.618864 [CA 4] Center 33 (3~64) winsize 62
2454 11:11:38.622033 [CA 5] Center 32 (3~62) winsize 60
2455 11:11:38.622113
2456 11:11:38.625861 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2457 11:11:38.625944
2458 11:11:38.629057 [CATrainingPosCal] consider 1 rank data
2459 11:11:38.632450 u2DelayCellTimex100 = 270/100 ps
2460 11:11:38.635689 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2461 11:11:38.639251 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2462 11:11:38.645795 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2463 11:11:38.649098 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2464 11:11:38.652722 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2465 11:11:38.655479 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2466 11:11:38.655560
2467 11:11:38.658960 CA PerBit enable=1, Macro0, CA PI delay=32
2468 11:11:38.659040
2469 11:11:38.662226 [CBTSetCACLKResult] CA Dly = 32
2470 11:11:38.662306 CS Dly: 6 (0~37)
2471 11:11:38.662370 ==
2472 11:11:38.665419 Dram Type= 6, Freq= 0, CH_0, rank 1
2473 11:11:38.672581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2474 11:11:38.672691 ==
2475 11:11:38.675484 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2476 11:11:38.682178 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2477 11:11:38.691307 [CA 0] Center 38 (8~69) winsize 62
2478 11:11:38.694499 [CA 1] Center 38 (8~69) winsize 62
2479 11:11:38.698162 [CA 2] Center 35 (5~66) winsize 62
2480 11:11:38.701427 [CA 3] Center 34 (4~65) winsize 62
2481 11:11:38.704328 [CA 4] Center 33 (3~64) winsize 62
2482 11:11:38.708159 [CA 5] Center 32 (3~62) winsize 60
2483 11:11:38.708265
2484 11:11:38.710999 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2485 11:11:38.711109
2486 11:11:38.714883 [CATrainingPosCal] consider 2 rank data
2487 11:11:38.717993 u2DelayCellTimex100 = 270/100 ps
2488 11:11:38.721175 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2489 11:11:38.724740 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2490 11:11:38.731074 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2491 11:11:38.734828 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2492 11:11:38.738180 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2493 11:11:38.741239 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2494 11:11:38.741349
2495 11:11:38.744551 CA PerBit enable=1, Macro0, CA PI delay=32
2496 11:11:38.744632
2497 11:11:38.748116 [CBTSetCACLKResult] CA Dly = 32
2498 11:11:38.748222 CS Dly: 6 (0~38)
2499 11:11:38.748349
2500 11:11:38.751217 ----->DramcWriteLeveling(PI) begin...
2501 11:11:38.754339 ==
2502 11:11:38.758007 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 11:11:38.761066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2504 11:11:38.761148 ==
2505 11:11:38.765027 Write leveling (Byte 0): 32 => 32
2506 11:11:38.767976 Write leveling (Byte 1): 29 => 29
2507 11:11:38.771094 DramcWriteLeveling(PI) end<-----
2508 11:11:38.771175
2509 11:11:38.771244 ==
2510 11:11:38.774887 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 11:11:38.778415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 11:11:38.778497 ==
2513 11:11:38.781212 [Gating] SW mode calibration
2514 11:11:38.788099 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2515 11:11:38.791521 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2516 11:11:38.798050 0 15 0 | B1->B0 | 2524 3333 | 1 1 | (0 0) (1 1)
2517 11:11:38.801558 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2518 11:11:38.805166 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 11:11:38.811300 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 11:11:38.815283 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 11:11:38.818366 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 11:11:38.825201 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
2523 11:11:38.828626 0 15 28 | B1->B0 | 3434 2727 | 0 0 | (0 0) (0 0)
2524 11:11:38.831348 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2525 11:11:38.838037 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 11:11:38.841804 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 11:11:38.844975 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 11:11:38.848713 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 11:11:38.854861 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 11:11:38.858459 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2531 11:11:38.861647 1 0 28 | B1->B0 | 2525 4444 | 0 0 | (0 0) (1 1)
2532 11:11:38.868370 1 1 0 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
2533 11:11:38.871516 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 11:11:38.875332 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 11:11:38.881527 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 11:11:38.885372 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 11:11:38.888187 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 11:11:38.894982 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 11:11:38.898579 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2540 11:11:38.901601 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2541 11:11:38.908346 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 11:11:38.911694 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 11:11:38.915013 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 11:11:38.921743 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 11:11:38.925044 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 11:11:38.928158 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 11:11:38.934654 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 11:11:38.938373 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 11:11:38.941781 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 11:11:38.945131 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 11:11:38.951509 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 11:11:38.955319 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 11:11:38.958421 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 11:11:38.965031 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 11:11:38.968612 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2556 11:11:38.971640 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2557 11:11:38.974843 Total UI for P1: 0, mck2ui 16
2558 11:11:38.978217 best dqsien dly found for B0: ( 1, 3, 28)
2559 11:11:38.984971 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 11:11:38.985058 Total UI for P1: 0, mck2ui 16
2561 11:11:38.991648 best dqsien dly found for B1: ( 1, 4, 0)
2562 11:11:38.995300 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2563 11:11:38.998288 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2564 11:11:38.998366
2565 11:11:39.001792 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2566 11:11:39.004932 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2567 11:11:39.008707 [Gating] SW calibration Done
2568 11:11:39.008786 ==
2569 11:11:39.011870 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 11:11:39.014944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 11:11:39.015017 ==
2572 11:11:39.018506 RX Vref Scan: 0
2573 11:11:39.018617
2574 11:11:39.018683 RX Vref 0 -> 0, step: 1
2575 11:11:39.018741
2576 11:11:39.021504 RX Delay -40 -> 252, step: 8
2577 11:11:39.024952 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2578 11:11:39.028576 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2579 11:11:39.035424 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2580 11:11:39.038525 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2581 11:11:39.041659 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2582 11:11:39.044884 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2583 11:11:39.048568 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2584 11:11:39.055159 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2585 11:11:39.058410 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2586 11:11:39.061576 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2587 11:11:39.065211 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2588 11:11:39.068298 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2589 11:11:39.075460 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2590 11:11:39.078773 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2591 11:11:39.082008 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2592 11:11:39.085142 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2593 11:11:39.085264 ==
2594 11:11:39.088202 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 11:11:39.095572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 11:11:39.095655 ==
2597 11:11:39.095718 DQS Delay:
2598 11:11:39.098675 DQS0 = 0, DQS1 = 0
2599 11:11:39.098772 DQM Delay:
2600 11:11:39.098867 DQM0 = 121, DQM1 = 113
2601 11:11:39.101816 DQ Delay:
2602 11:11:39.105347 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2603 11:11:39.108485 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2604 11:11:39.112182 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2605 11:11:39.115548 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2606 11:11:39.115702
2607 11:11:39.115810
2608 11:11:39.115874 ==
2609 11:11:39.118759 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 11:11:39.122036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 11:11:39.122118 ==
2612 11:11:39.125087
2613 11:11:39.125168
2614 11:11:39.125231 TX Vref Scan disable
2615 11:11:39.128821 == TX Byte 0 ==
2616 11:11:39.131949 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2617 11:11:39.135508 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2618 11:11:39.138387 == TX Byte 1 ==
2619 11:11:39.141845 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2620 11:11:39.145285 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2621 11:11:39.145366 ==
2622 11:11:39.148627 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 11:11:39.155095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 11:11:39.155177 ==
2625 11:11:39.165931 TX Vref=22, minBit 0, minWin=24, winSum=407
2626 11:11:39.169466 TX Vref=24, minBit 0, minWin=25, winSum=411
2627 11:11:39.172604 TX Vref=26, minBit 1, minWin=25, winSum=416
2628 11:11:39.176052 TX Vref=28, minBit 0, minWin=26, winSum=425
2629 11:11:39.179313 TX Vref=30, minBit 0, minWin=26, winSum=428
2630 11:11:39.182931 TX Vref=32, minBit 10, minWin=25, winSum=419
2631 11:11:39.189242 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 30
2632 11:11:39.189341
2633 11:11:39.192583 Final TX Range 1 Vref 30
2634 11:11:39.192665
2635 11:11:39.192728 ==
2636 11:11:39.196181 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 11:11:39.199579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 11:11:39.199661 ==
2639 11:11:39.199725
2640 11:11:39.202511
2641 11:11:39.202591 TX Vref Scan disable
2642 11:11:39.206162 == TX Byte 0 ==
2643 11:11:39.209084 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2644 11:11:39.212732 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2645 11:11:39.216005 == TX Byte 1 ==
2646 11:11:39.219764 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2647 11:11:39.222949 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2648 11:11:39.223034
2649 11:11:39.225987 [DATLAT]
2650 11:11:39.226068 Freq=1200, CH0 RK0
2651 11:11:39.226132
2652 11:11:39.229757 DATLAT Default: 0xd
2653 11:11:39.229838 0, 0xFFFF, sum = 0
2654 11:11:39.233019 1, 0xFFFF, sum = 0
2655 11:11:39.233101 2, 0xFFFF, sum = 0
2656 11:11:39.236180 3, 0xFFFF, sum = 0
2657 11:11:39.236311 4, 0xFFFF, sum = 0
2658 11:11:39.239221 5, 0xFFFF, sum = 0
2659 11:11:39.239304 6, 0xFFFF, sum = 0
2660 11:11:39.242761 7, 0xFFFF, sum = 0
2661 11:11:39.242843 8, 0xFFFF, sum = 0
2662 11:11:39.245951 9, 0xFFFF, sum = 0
2663 11:11:39.249468 10, 0xFFFF, sum = 0
2664 11:11:39.249550 11, 0xFFFF, sum = 0
2665 11:11:39.253068 12, 0x0, sum = 1
2666 11:11:39.253151 13, 0x0, sum = 2
2667 11:11:39.253216 14, 0x0, sum = 3
2668 11:11:39.255925 15, 0x0, sum = 4
2669 11:11:39.256034 best_step = 13
2670 11:11:39.256130
2671 11:11:39.256218 ==
2672 11:11:39.259666 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 11:11:39.265992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 11:11:39.266077 ==
2675 11:11:39.266156 RX Vref Scan: 1
2676 11:11:39.266228
2677 11:11:39.269223 Set Vref Range= 32 -> 127
2678 11:11:39.269304
2679 11:11:39.273053 RX Vref 32 -> 127, step: 1
2680 11:11:39.273134
2681 11:11:39.276010 RX Delay -13 -> 252, step: 4
2682 11:11:39.276117
2683 11:11:39.279641 Set Vref, RX VrefLevel [Byte0]: 32
2684 11:11:39.282776 [Byte1]: 32
2685 11:11:39.282858
2686 11:11:39.285974 Set Vref, RX VrefLevel [Byte0]: 33
2687 11:11:39.289869 [Byte1]: 33
2688 11:11:39.289953
2689 11:11:39.292907 Set Vref, RX VrefLevel [Byte0]: 34
2690 11:11:39.295926 [Byte1]: 34
2691 11:11:39.300056
2692 11:11:39.300162 Set Vref, RX VrefLevel [Byte0]: 35
2693 11:11:39.303462 [Byte1]: 35
2694 11:11:39.307663
2695 11:11:39.307784 Set Vref, RX VrefLevel [Byte0]: 36
2696 11:11:39.310968 [Byte1]: 36
2697 11:11:39.315695
2698 11:11:39.315771 Set Vref, RX VrefLevel [Byte0]: 37
2699 11:11:39.319462 [Byte1]: 37
2700 11:11:39.323441
2701 11:11:39.323533 Set Vref, RX VrefLevel [Byte0]: 38
2702 11:11:39.327153 [Byte1]: 38
2703 11:11:39.331468
2704 11:11:39.331543 Set Vref, RX VrefLevel [Byte0]: 39
2705 11:11:39.334581 [Byte1]: 39
2706 11:11:39.339600
2707 11:11:39.339672 Set Vref, RX VrefLevel [Byte0]: 40
2708 11:11:39.342831 [Byte1]: 40
2709 11:11:39.347065
2710 11:11:39.347141 Set Vref, RX VrefLevel [Byte0]: 41
2711 11:11:39.350677 [Byte1]: 41
2712 11:11:39.355595
2713 11:11:39.355676 Set Vref, RX VrefLevel [Byte0]: 42
2714 11:11:39.358183 [Byte1]: 42
2715 11:11:39.362982
2716 11:11:39.363055 Set Vref, RX VrefLevel [Byte0]: 43
2717 11:11:39.366307 [Byte1]: 43
2718 11:11:39.370950
2719 11:11:39.371056 Set Vref, RX VrefLevel [Byte0]: 44
2720 11:11:39.374318 [Byte1]: 44
2721 11:11:39.378742
2722 11:11:39.378818 Set Vref, RX VrefLevel [Byte0]: 45
2723 11:11:39.382266 [Byte1]: 45
2724 11:11:39.386756
2725 11:11:39.386864 Set Vref, RX VrefLevel [Byte0]: 46
2726 11:11:39.389956 [Byte1]: 46
2727 11:11:39.394502
2728 11:11:39.394611 Set Vref, RX VrefLevel [Byte0]: 47
2729 11:11:39.398267 [Byte1]: 47
2730 11:11:39.402781
2731 11:11:39.402855 Set Vref, RX VrefLevel [Byte0]: 48
2732 11:11:39.405759 [Byte1]: 48
2733 11:11:39.410495
2734 11:11:39.410576 Set Vref, RX VrefLevel [Byte0]: 49
2735 11:11:39.413504 [Byte1]: 49
2736 11:11:39.418122
2737 11:11:39.418231 Set Vref, RX VrefLevel [Byte0]: 50
2738 11:11:39.421944 [Byte1]: 50
2739 11:11:39.426492
2740 11:11:39.426590 Set Vref, RX VrefLevel [Byte0]: 51
2741 11:11:39.429681 [Byte1]: 51
2742 11:11:39.433995
2743 11:11:39.434129 Set Vref, RX VrefLevel [Byte0]: 52
2744 11:11:39.437253 [Byte1]: 52
2745 11:11:39.441992
2746 11:11:39.442072 Set Vref, RX VrefLevel [Byte0]: 53
2747 11:11:39.445080 [Byte1]: 53
2748 11:11:39.450162
2749 11:11:39.450243 Set Vref, RX VrefLevel [Byte0]: 54
2750 11:11:39.453199 [Byte1]: 54
2751 11:11:39.457994
2752 11:11:39.458093 Set Vref, RX VrefLevel [Byte0]: 55
2753 11:11:39.461120 [Byte1]: 55
2754 11:11:39.465529
2755 11:11:39.465611 Set Vref, RX VrefLevel [Byte0]: 56
2756 11:11:39.469154 [Byte1]: 56
2757 11:11:39.473699
2758 11:11:39.473780 Set Vref, RX VrefLevel [Byte0]: 57
2759 11:11:39.476772 [Byte1]: 57
2760 11:11:39.481449
2761 11:11:39.481530 Set Vref, RX VrefLevel [Byte0]: 58
2762 11:11:39.484627 [Byte1]: 58
2763 11:11:39.489365
2764 11:11:39.489447 Set Vref, RX VrefLevel [Byte0]: 59
2765 11:11:39.492664 [Byte1]: 59
2766 11:11:39.496979
2767 11:11:39.497061 Set Vref, RX VrefLevel [Byte0]: 60
2768 11:11:39.500955 [Byte1]: 60
2769 11:11:39.505248
2770 11:11:39.505330 Set Vref, RX VrefLevel [Byte0]: 61
2771 11:11:39.508421 [Byte1]: 61
2772 11:11:39.513187
2773 11:11:39.513272 Set Vref, RX VrefLevel [Byte0]: 62
2774 11:11:39.516192 [Byte1]: 62
2775 11:11:39.520756
2776 11:11:39.520838 Set Vref, RX VrefLevel [Byte0]: 63
2777 11:11:39.524235 [Byte1]: 63
2778 11:11:39.528877
2779 11:11:39.528959 Set Vref, RX VrefLevel [Byte0]: 64
2780 11:11:39.531904 [Byte1]: 64
2781 11:11:39.536867
2782 11:11:39.536948 Set Vref, RX VrefLevel [Byte0]: 65
2783 11:11:39.540367 [Byte1]: 65
2784 11:11:39.544529
2785 11:11:39.544637 Set Vref, RX VrefLevel [Byte0]: 66
2786 11:11:39.548065 [Byte1]: 66
2787 11:11:39.552218
2788 11:11:39.552330 Set Vref, RX VrefLevel [Byte0]: 67
2789 11:11:39.555875 [Byte1]: 67
2790 11:11:39.560351
2791 11:11:39.560451 Set Vref, RX VrefLevel [Byte0]: 68
2792 11:11:39.563884 [Byte1]: 68
2793 11:11:39.568393
2794 11:11:39.568474 Set Vref, RX VrefLevel [Byte0]: 69
2795 11:11:39.571658 [Byte1]: 69
2796 11:11:39.576056
2797 11:11:39.576139 Final RX Vref Byte 0 = 55 to rank0
2798 11:11:39.579421 Final RX Vref Byte 1 = 51 to rank0
2799 11:11:39.583014 Final RX Vref Byte 0 = 55 to rank1
2800 11:11:39.585962 Final RX Vref Byte 1 = 51 to rank1==
2801 11:11:39.589058 Dram Type= 6, Freq= 0, CH_0, rank 0
2802 11:11:39.595900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2803 11:11:39.596010 ==
2804 11:11:39.596103 DQS Delay:
2805 11:11:39.596191 DQS0 = 0, DQS1 = 0
2806 11:11:39.599806 DQM Delay:
2807 11:11:39.599901 DQM0 = 120, DQM1 = 112
2808 11:11:39.603050 DQ Delay:
2809 11:11:39.606199 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2810 11:11:39.609319 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2811 11:11:39.613172 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2812 11:11:39.616508 DQ12 =120, DQ13 =116, DQ14 =124, DQ15 =122
2813 11:11:39.616590
2814 11:11:39.616653
2815 11:11:39.626131 [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2816 11:11:39.626213 CH0 RK0: MR19=404, MR18=140D
2817 11:11:39.632774 CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27
2818 11:11:39.632855
2819 11:11:39.636001 ----->DramcWriteLeveling(PI) begin...
2820 11:11:39.636108 ==
2821 11:11:39.639616 Dram Type= 6, Freq= 0, CH_0, rank 1
2822 11:11:39.642637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 11:11:39.646180 ==
2824 11:11:39.646261 Write leveling (Byte 0): 33 => 33
2825 11:11:39.649402 Write leveling (Byte 1): 28 => 28
2826 11:11:39.652616 DramcWriteLeveling(PI) end<-----
2827 11:11:39.652698
2828 11:11:39.652778 ==
2829 11:11:39.656199 Dram Type= 6, Freq= 0, CH_0, rank 1
2830 11:11:39.663013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2831 11:11:39.663132 ==
2832 11:11:39.663228 [Gating] SW mode calibration
2833 11:11:39.672760 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2834 11:11:39.675997 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2835 11:11:39.682704 0 15 0 | B1->B0 | 3131 2d2d | 1 1 | (1 1) (1 1)
2836 11:11:39.686240 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 11:11:39.689685 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 11:11:39.692659 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 11:11:39.699435 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 11:11:39.702489 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 11:11:39.706345 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2842 11:11:39.712603 0 15 28 | B1->B0 | 3232 2d2d | 0 0 | (0 1) (0 0)
2843 11:11:39.716489 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2844 11:11:39.719550 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 11:11:39.726647 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 11:11:39.729708 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 11:11:39.732656 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 11:11:39.739307 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 11:11:39.742778 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 11:11:39.746045 1 0 28 | B1->B0 | 3b3b 3c3b | 0 1 | (0 0) (0 0)
2851 11:11:39.752993 1 1 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
2852 11:11:39.756261 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 11:11:39.759418 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 11:11:39.766579 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 11:11:39.769786 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 11:11:39.772702 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 11:11:39.776531 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 11:11:39.782683 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2859 11:11:39.786428 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2860 11:11:39.790054 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 11:11:39.796613 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 11:11:39.799512 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 11:11:39.803179 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 11:11:39.809983 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 11:11:39.813067 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 11:11:39.816250 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 11:11:39.823262 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 11:11:39.826509 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 11:11:39.829701 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 11:11:39.833387 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 11:11:39.839808 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 11:11:39.843460 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 11:11:39.846479 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 11:11:39.853142 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2875 11:11:39.856801 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 11:11:39.860065 Total UI for P1: 0, mck2ui 16
2877 11:11:39.863470 best dqsien dly found for B0: ( 1, 3, 28)
2878 11:11:39.866285 Total UI for P1: 0, mck2ui 16
2879 11:11:39.870146 best dqsien dly found for B1: ( 1, 3, 28)
2880 11:11:39.872830 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2881 11:11:39.876722 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2882 11:11:39.876847
2883 11:11:39.879924 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2884 11:11:39.882862 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2885 11:11:39.886386 [Gating] SW calibration Done
2886 11:11:39.886508 ==
2887 11:11:39.890101 Dram Type= 6, Freq= 0, CH_0, rank 1
2888 11:11:39.893530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 11:11:39.896784 ==
2890 11:11:39.896909 RX Vref Scan: 0
2891 11:11:39.897020
2892 11:11:39.899870 RX Vref 0 -> 0, step: 1
2893 11:11:39.899992
2894 11:11:39.903569 RX Delay -40 -> 252, step: 8
2895 11:11:39.906550 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2896 11:11:39.910114 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2897 11:11:39.913115 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2898 11:11:39.916560 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2899 11:11:39.923577 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2900 11:11:39.926764 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2901 11:11:39.930030 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2902 11:11:39.933754 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2903 11:11:39.937029 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2904 11:11:39.940224 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2905 11:11:39.947140 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2906 11:11:39.950218 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2907 11:11:39.953195 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2908 11:11:39.957181 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2909 11:11:39.960155 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2910 11:11:39.966741 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2911 11:11:39.966849 ==
2912 11:11:39.969972 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 11:11:39.973350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 11:11:39.973498 ==
2915 11:11:39.973598 DQS Delay:
2916 11:11:39.976717 DQS0 = 0, DQS1 = 0
2917 11:11:39.976798 DQM Delay:
2918 11:11:39.979821 DQM0 = 122, DQM1 = 114
2919 11:11:39.979902 DQ Delay:
2920 11:11:39.983664 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2921 11:11:39.986956 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2922 11:11:39.990028 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =107
2923 11:11:39.993173 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2924 11:11:39.996893
2925 11:11:39.996974
2926 11:11:39.997038 ==
2927 11:11:39.999999 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 11:11:40.003587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2929 11:11:40.003669 ==
2930 11:11:40.003733
2931 11:11:40.003792
2932 11:11:40.006935 TX Vref Scan disable
2933 11:11:40.007017 == TX Byte 0 ==
2934 11:11:40.013717 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2935 11:11:40.017219 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2936 11:11:40.017301 == TX Byte 1 ==
2937 11:11:40.020190 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2938 11:11:40.027395 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2939 11:11:40.027477 ==
2940 11:11:40.030244 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 11:11:40.033843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 11:11:40.033942 ==
2943 11:11:40.046445 TX Vref=22, minBit 1, minWin=25, winSum=407
2944 11:11:40.049713 TX Vref=24, minBit 3, minWin=25, winSum=415
2945 11:11:40.052877 TX Vref=26, minBit 3, minWin=25, winSum=419
2946 11:11:40.056116 TX Vref=28, minBit 4, minWin=25, winSum=422
2947 11:11:40.059808 TX Vref=30, minBit 3, minWin=26, winSum=426
2948 11:11:40.062827 TX Vref=32, minBit 0, minWin=26, winSum=423
2949 11:11:40.069849 [TxChooseVref] Worse bit 3, Min win 26, Win sum 426, Final Vref 30
2950 11:11:40.069932
2951 11:11:40.072967 Final TX Range 1 Vref 30
2952 11:11:40.073050
2953 11:11:40.073115 ==
2954 11:11:40.076455 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 11:11:40.079894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 11:11:40.079977 ==
2957 11:11:40.080042
2958 11:11:40.080102
2959 11:11:40.082918 TX Vref Scan disable
2960 11:11:40.086011 == TX Byte 0 ==
2961 11:11:40.089962 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2962 11:11:40.093013 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2963 11:11:40.096075 == TX Byte 1 ==
2964 11:11:40.099874 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2965 11:11:40.102863 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2966 11:11:40.102985
2967 11:11:40.106631 [DATLAT]
2968 11:11:40.106706 Freq=1200, CH0 RK1
2969 11:11:40.106774
2970 11:11:40.109819 DATLAT Default: 0xd
2971 11:11:40.109891 0, 0xFFFF, sum = 0
2972 11:11:40.113050 1, 0xFFFF, sum = 0
2973 11:11:40.113149 2, 0xFFFF, sum = 0
2974 11:11:40.116181 3, 0xFFFF, sum = 0
2975 11:11:40.116278 4, 0xFFFF, sum = 0
2976 11:11:40.119802 5, 0xFFFF, sum = 0
2977 11:11:40.119919 6, 0xFFFF, sum = 0
2978 11:11:40.122780 7, 0xFFFF, sum = 0
2979 11:11:40.122888 8, 0xFFFF, sum = 0
2980 11:11:40.126285 9, 0xFFFF, sum = 0
2981 11:11:40.129722 10, 0xFFFF, sum = 0
2982 11:11:40.129833 11, 0xFFFF, sum = 0
2983 11:11:40.133032 12, 0x0, sum = 1
2984 11:11:40.133146 13, 0x0, sum = 2
2985 11:11:40.133246 14, 0x0, sum = 3
2986 11:11:40.136521 15, 0x0, sum = 4
2987 11:11:40.136627 best_step = 13
2988 11:11:40.136696
2989 11:11:40.136763 ==
2990 11:11:40.139705 Dram Type= 6, Freq= 0, CH_0, rank 1
2991 11:11:40.146149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2992 11:11:40.146259 ==
2993 11:11:40.146346 RX Vref Scan: 0
2994 11:11:40.146409
2995 11:11:40.149516 RX Vref 0 -> 0, step: 1
2996 11:11:40.149599
2997 11:11:40.153324 RX Delay -13 -> 252, step: 4
2998 11:11:40.156309 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
2999 11:11:40.159506 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3000 11:11:40.166577 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3001 11:11:40.169624 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3002 11:11:40.172934 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3003 11:11:40.176563 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3004 11:11:40.179607 iDelay=195, Bit 6, Center 124 (59 ~ 190) 132
3005 11:11:40.186384 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3006 11:11:40.189943 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3007 11:11:40.193147 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3008 11:11:40.196453 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3009 11:11:40.200015 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3010 11:11:40.206322 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3011 11:11:40.209741 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3012 11:11:40.212837 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3013 11:11:40.216745 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3014 11:11:40.216826 ==
3015 11:11:40.219899 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 11:11:40.226344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 11:11:40.226427 ==
3018 11:11:40.226492 DQS Delay:
3019 11:11:40.226551 DQS0 = 0, DQS1 = 0
3020 11:11:40.230084 DQM Delay:
3021 11:11:40.230164 DQM0 = 120, DQM1 = 110
3022 11:11:40.233064 DQ Delay:
3023 11:11:40.236215 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3024 11:11:40.239836 DQ4 =122, DQ5 =116, DQ6 =124, DQ7 =126
3025 11:11:40.243389 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =102
3026 11:11:40.246410 DQ12 =116, DQ13 =116, DQ14 =122, DQ15 =120
3027 11:11:40.246491
3028 11:11:40.246556
3029 11:11:40.253230 [DQSOSCAuto] RK1, (LSB)MR18= 0xff1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 404 ps
3030 11:11:40.256572 CH0 RK1: MR19=403, MR18=FF1
3031 11:11:40.263115 CH0_RK1: MR19=0x403, MR18=0xFF1, DQSOSC=404, MR23=63, INC=40, DEC=26
3032 11:11:40.266945 [RxdqsGatingPostProcess] freq 1200
3033 11:11:40.273304 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3034 11:11:40.273430 best DQS0 dly(2T, 0.5T) = (0, 11)
3035 11:11:40.276441 best DQS1 dly(2T, 0.5T) = (0, 12)
3036 11:11:40.279571 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3037 11:11:40.282883 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3038 11:11:40.286545 best DQS0 dly(2T, 0.5T) = (0, 11)
3039 11:11:40.290013 best DQS1 dly(2T, 0.5T) = (0, 11)
3040 11:11:40.293196 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3041 11:11:40.296399 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3042 11:11:40.300020 Pre-setting of DQS Precalculation
3043 11:11:40.303346 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3044 11:11:40.306466 ==
3045 11:11:40.309752 Dram Type= 6, Freq= 0, CH_1, rank 0
3046 11:11:40.313270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 11:11:40.313393 ==
3048 11:11:40.316911 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3049 11:11:40.323258 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3050 11:11:40.332616 [CA 0] Center 37 (7~68) winsize 62
3051 11:11:40.335579 [CA 1] Center 37 (7~68) winsize 62
3052 11:11:40.339086 [CA 2] Center 35 (5~65) winsize 61
3053 11:11:40.342181 [CA 3] Center 34 (4~64) winsize 61
3054 11:11:40.345875 [CA 4] Center 34 (4~64) winsize 61
3055 11:11:40.349005 [CA 5] Center 33 (3~63) winsize 61
3056 11:11:40.349126
3057 11:11:40.352598 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3058 11:11:40.352719
3059 11:11:40.355542 [CATrainingPosCal] consider 1 rank data
3060 11:11:40.359367 u2DelayCellTimex100 = 270/100 ps
3061 11:11:40.362399 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3062 11:11:40.365544 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3063 11:11:40.372236 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3064 11:11:40.375626 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3065 11:11:40.379480 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3066 11:11:40.382523 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3067 11:11:40.382645
3068 11:11:40.386384 CA PerBit enable=1, Macro0, CA PI delay=33
3069 11:11:40.386505
3070 11:11:40.389522 [CBTSetCACLKResult] CA Dly = 33
3071 11:11:40.389639 CS Dly: 8 (0~39)
3072 11:11:40.389746 ==
3073 11:11:40.392478 Dram Type= 6, Freq= 0, CH_1, rank 1
3074 11:11:40.399367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 11:11:40.399491 ==
3076 11:11:40.402503 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3077 11:11:40.409303 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3078 11:11:40.417797 [CA 0] Center 37 (7~68) winsize 62
3079 11:11:40.421199 [CA 1] Center 38 (8~68) winsize 61
3080 11:11:40.424459 [CA 2] Center 35 (5~65) winsize 61
3081 11:11:40.427834 [CA 3] Center 34 (4~65) winsize 62
3082 11:11:40.431422 [CA 4] Center 34 (4~65) winsize 62
3083 11:11:40.434408 [CA 5] Center 34 (4~64) winsize 61
3084 11:11:40.434531
3085 11:11:40.438173 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3086 11:11:40.438295
3087 11:11:40.441297 [CATrainingPosCal] consider 2 rank data
3088 11:11:40.444865 u2DelayCellTimex100 = 270/100 ps
3089 11:11:40.447789 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3090 11:11:40.451329 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3091 11:11:40.458046 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3092 11:11:40.461190 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3093 11:11:40.464714 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3094 11:11:40.467803 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3095 11:11:40.467924
3096 11:11:40.471000 CA PerBit enable=1, Macro0, CA PI delay=33
3097 11:11:40.471122
3098 11:11:40.474971 [CBTSetCACLKResult] CA Dly = 33
3099 11:11:40.475093 CS Dly: 8 (0~40)
3100 11:11:40.475206
3101 11:11:40.477992 ----->DramcWriteLeveling(PI) begin...
3102 11:11:40.481085 ==
3103 11:11:40.481208 Dram Type= 6, Freq= 0, CH_1, rank 0
3104 11:11:40.488261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 11:11:40.488419 ==
3106 11:11:40.491186 Write leveling (Byte 0): 26 => 26
3107 11:11:40.494556 Write leveling (Byte 1): 28 => 28
3108 11:11:40.494680 DramcWriteLeveling(PI) end<-----
3109 11:11:40.498517
3110 11:11:40.498637 ==
3111 11:11:40.501636 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 11:11:40.505003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 11:11:40.505125 ==
3114 11:11:40.508142 [Gating] SW mode calibration
3115 11:11:40.515046 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3116 11:11:40.518067 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3117 11:11:40.524753 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 11:11:40.528340 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 11:11:40.531711 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 11:11:40.538036 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 11:11:40.541437 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 11:11:40.545174 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 11:11:40.551648 0 15 24 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
3124 11:11:40.555238 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 11:11:40.558385 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 11:11:40.561970 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 11:11:40.568724 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 11:11:40.571858 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 11:11:40.574989 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 11:11:40.581816 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 11:11:40.584933 1 0 24 | B1->B0 | 3231 4040 | 1 0 | (0 0) (0 0)
3132 11:11:40.588701 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 11:11:40.594984 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 11:11:40.598503 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 11:11:40.601909 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 11:11:40.608518 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 11:11:40.611779 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 11:11:40.614884 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 11:11:40.621653 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3140 11:11:40.625196 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3141 11:11:40.628419 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 11:11:40.635125 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 11:11:40.638754 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 11:11:40.641651 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 11:11:40.648647 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 11:11:40.652059 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 11:11:40.654859 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 11:11:40.658639 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 11:11:40.665388 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 11:11:40.668246 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 11:11:40.671937 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 11:11:40.678958 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 11:11:40.681996 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 11:11:40.685179 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 11:11:40.692139 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3156 11:11:40.695297 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 11:11:40.698501 Total UI for P1: 0, mck2ui 16
3158 11:11:40.702141 best dqsien dly found for B0: ( 1, 3, 24)
3159 11:11:40.705329 Total UI for P1: 0, mck2ui 16
3160 11:11:40.708920 best dqsien dly found for B1: ( 1, 3, 24)
3161 11:11:40.711975 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3162 11:11:40.715677 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3163 11:11:40.715762
3164 11:11:40.718920 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3165 11:11:40.722372 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3166 11:11:40.725679 [Gating] SW calibration Done
3167 11:11:40.725763 ==
3168 11:11:40.728854 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 11:11:40.731946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 11:11:40.732032 ==
3171 11:11:40.735940 RX Vref Scan: 0
3172 11:11:40.736024
3173 11:11:40.739073 RX Vref 0 -> 0, step: 1
3174 11:11:40.739157
3175 11:11:40.739243 RX Delay -40 -> 252, step: 8
3176 11:11:40.745859 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3177 11:11:40.749049 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3178 11:11:40.752074 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3179 11:11:40.755425 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3180 11:11:40.758549 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3181 11:11:40.765880 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3182 11:11:40.768916 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3183 11:11:40.772432 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3184 11:11:40.775282 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3185 11:11:40.778918 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3186 11:11:40.785510 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3187 11:11:40.789268 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3188 11:11:40.792564 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3189 11:11:40.795636 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3190 11:11:40.798772 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3191 11:11:40.805741 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3192 11:11:40.805824 ==
3193 11:11:40.808804 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 11:11:40.812703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 11:11:40.812785 ==
3196 11:11:40.812850 DQS Delay:
3197 11:11:40.815919 DQS0 = 0, DQS1 = 0
3198 11:11:40.816000 DQM Delay:
3199 11:11:40.819020 DQM0 = 119, DQM1 = 116
3200 11:11:40.819136 DQ Delay:
3201 11:11:40.822404 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3202 11:11:40.825602 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3203 11:11:40.829269 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3204 11:11:40.832342 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3205 11:11:40.832424
3206 11:11:40.832489
3207 11:11:40.832548 ==
3208 11:11:40.836064 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 11:11:40.842806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 11:11:40.842889 ==
3211 11:11:40.842953
3212 11:11:40.843013
3213 11:11:40.845749 TX Vref Scan disable
3214 11:11:40.845831 == TX Byte 0 ==
3215 11:11:40.849081 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3216 11:11:40.855771 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3217 11:11:40.855854 == TX Byte 1 ==
3218 11:11:40.858848 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3219 11:11:40.865902 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3220 11:11:40.865984 ==
3221 11:11:40.868824 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 11:11:40.872504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 11:11:40.872589 ==
3224 11:11:40.884060 TX Vref=22, minBit 11, minWin=24, winSum=411
3225 11:11:40.887288 TX Vref=24, minBit 9, minWin=25, winSum=419
3226 11:11:40.890604 TX Vref=26, minBit 9, minWin=25, winSum=421
3227 11:11:40.894182 TX Vref=28, minBit 0, minWin=26, winSum=424
3228 11:11:40.897504 TX Vref=30, minBit 1, minWin=26, winSum=432
3229 11:11:40.903844 TX Vref=32, minBit 10, minWin=26, winSum=433
3230 11:11:40.907066 [TxChooseVref] Worse bit 10, Min win 26, Win sum 433, Final Vref 32
3231 11:11:40.907151
3232 11:11:40.910651 Final TX Range 1 Vref 32
3233 11:11:40.910733
3234 11:11:40.910797 ==
3235 11:11:40.913725 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 11:11:40.917150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 11:11:40.917231 ==
3238 11:11:40.920822
3239 11:11:40.920932
3240 11:11:40.921012 TX Vref Scan disable
3241 11:11:40.923925 == TX Byte 0 ==
3242 11:11:40.927140 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3243 11:11:40.930369 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3244 11:11:40.934258 == TX Byte 1 ==
3245 11:11:40.937351 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3246 11:11:40.940522 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3247 11:11:40.944139
3248 11:11:40.944239 [DATLAT]
3249 11:11:40.944371 Freq=1200, CH1 RK0
3250 11:11:40.944464
3251 11:11:40.946954 DATLAT Default: 0xd
3252 11:11:40.947065 0, 0xFFFF, sum = 0
3253 11:11:40.950631 1, 0xFFFF, sum = 0
3254 11:11:40.950747 2, 0xFFFF, sum = 0
3255 11:11:40.953732 3, 0xFFFF, sum = 0
3256 11:11:40.953836 4, 0xFFFF, sum = 0
3257 11:11:40.957478 5, 0xFFFF, sum = 0
3258 11:11:40.960377 6, 0xFFFF, sum = 0
3259 11:11:40.960452 7, 0xFFFF, sum = 0
3260 11:11:40.963784 8, 0xFFFF, sum = 0
3261 11:11:40.963857 9, 0xFFFF, sum = 0
3262 11:11:40.967652 10, 0xFFFF, sum = 0
3263 11:11:40.967786 11, 0xFFFF, sum = 0
3264 11:11:40.970517 12, 0x0, sum = 1
3265 11:11:40.970600 13, 0x0, sum = 2
3266 11:11:40.974070 14, 0x0, sum = 3
3267 11:11:40.974204 15, 0x0, sum = 4
3268 11:11:40.974324 best_step = 13
3269 11:11:40.974415
3270 11:11:40.978535 ==
3271 11:11:40.980474 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 11:11:40.984240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 11:11:40.984361 ==
3274 11:11:40.984427 RX Vref Scan: 1
3275 11:11:40.984487
3276 11:11:40.987431 Set Vref Range= 32 -> 127
3277 11:11:40.987519
3278 11:11:40.990455 RX Vref 32 -> 127, step: 1
3279 11:11:40.990538
3280 11:11:40.994184 RX Delay -5 -> 252, step: 4
3281 11:11:40.994265
3282 11:11:40.997053 Set Vref, RX VrefLevel [Byte0]: 32
3283 11:11:41.000400 [Byte1]: 32
3284 11:11:41.000482
3285 11:11:41.003998 Set Vref, RX VrefLevel [Byte0]: 33
3286 11:11:41.007316 [Byte1]: 33
3287 11:11:41.007398
3288 11:11:41.010384 Set Vref, RX VrefLevel [Byte0]: 34
3289 11:11:41.014049 [Byte1]: 34
3290 11:11:41.017700
3291 11:11:41.017781 Set Vref, RX VrefLevel [Byte0]: 35
3292 11:11:41.021439 [Byte1]: 35
3293 11:11:41.025890
3294 11:11:41.025975 Set Vref, RX VrefLevel [Byte0]: 36
3295 11:11:41.029090 [Byte1]: 36
3296 11:11:41.033553
3297 11:11:41.033637 Set Vref, RX VrefLevel [Byte0]: 37
3298 11:11:41.037272 [Byte1]: 37
3299 11:11:41.041448
3300 11:11:41.041529 Set Vref, RX VrefLevel [Byte0]: 38
3301 11:11:41.044792 [Byte1]: 38
3302 11:11:41.049270
3303 11:11:41.049356 Set Vref, RX VrefLevel [Byte0]: 39
3304 11:11:41.052934 [Byte1]: 39
3305 11:11:41.057189
3306 11:11:41.057302 Set Vref, RX VrefLevel [Byte0]: 40
3307 11:11:41.060228 [Byte1]: 40
3308 11:11:41.065164
3309 11:11:41.065259 Set Vref, RX VrefLevel [Byte0]: 41
3310 11:11:41.068459 [Byte1]: 41
3311 11:11:41.072733
3312 11:11:41.072814 Set Vref, RX VrefLevel [Byte0]: 42
3313 11:11:41.076263 [Byte1]: 42
3314 11:11:41.080649
3315 11:11:41.080731 Set Vref, RX VrefLevel [Byte0]: 43
3316 11:11:41.084078 [Byte1]: 43
3317 11:11:41.088770
3318 11:11:41.088853 Set Vref, RX VrefLevel [Byte0]: 44
3319 11:11:41.092035 [Byte1]: 44
3320 11:11:41.096136
3321 11:11:41.096218 Set Vref, RX VrefLevel [Byte0]: 45
3322 11:11:41.099723 [Byte1]: 45
3323 11:11:41.104166
3324 11:11:41.104274 Set Vref, RX VrefLevel [Byte0]: 46
3325 11:11:41.107543 [Byte1]: 46
3326 11:11:41.112392
3327 11:11:41.112474 Set Vref, RX VrefLevel [Byte0]: 47
3328 11:11:41.115227 [Byte1]: 47
3329 11:11:41.119628
3330 11:11:41.119709 Set Vref, RX VrefLevel [Byte0]: 48
3331 11:11:41.123156 [Byte1]: 48
3332 11:11:41.128205
3333 11:11:41.128352 Set Vref, RX VrefLevel [Byte0]: 49
3334 11:11:41.131410 [Byte1]: 49
3335 11:11:41.135842
3336 11:11:41.135926 Set Vref, RX VrefLevel [Byte0]: 50
3337 11:11:41.138936 [Byte1]: 50
3338 11:11:41.143267
3339 11:11:41.143374 Set Vref, RX VrefLevel [Byte0]: 51
3340 11:11:41.147051 [Byte1]: 51
3341 11:11:41.151610
3342 11:11:41.151692 Set Vref, RX VrefLevel [Byte0]: 52
3343 11:11:41.154642 [Byte1]: 52
3344 11:11:41.159583
3345 11:11:41.159665 Set Vref, RX VrefLevel [Byte0]: 53
3346 11:11:41.162608 [Byte1]: 53
3347 11:11:41.167257
3348 11:11:41.167340 Set Vref, RX VrefLevel [Byte0]: 54
3349 11:11:41.170266 [Byte1]: 54
3350 11:11:41.175353
3351 11:11:41.175436 Set Vref, RX VrefLevel [Byte0]: 55
3352 11:11:41.178408 [Byte1]: 55
3353 11:11:41.182708
3354 11:11:41.182791 Set Vref, RX VrefLevel [Byte0]: 56
3355 11:11:41.185937 [Byte1]: 56
3356 11:11:41.191003
3357 11:11:41.191086 Set Vref, RX VrefLevel [Byte0]: 57
3358 11:11:41.193701 [Byte1]: 57
3359 11:11:41.198610
3360 11:11:41.198691 Set Vref, RX VrefLevel [Byte0]: 58
3361 11:11:41.201648 [Byte1]: 58
3362 11:11:41.206460
3363 11:11:41.206541 Set Vref, RX VrefLevel [Byte0]: 59
3364 11:11:41.209619 [Byte1]: 59
3365 11:11:41.214256
3366 11:11:41.214336 Set Vref, RX VrefLevel [Byte0]: 60
3367 11:11:41.217614 [Byte1]: 60
3368 11:11:41.222020
3369 11:11:41.222101 Set Vref, RX VrefLevel [Byte0]: 61
3370 11:11:41.225557 [Byte1]: 61
3371 11:11:41.229767
3372 11:11:41.229848 Set Vref, RX VrefLevel [Byte0]: 62
3373 11:11:41.233097 [Byte1]: 62
3374 11:11:41.237793
3375 11:11:41.237873 Set Vref, RX VrefLevel [Byte0]: 63
3376 11:11:41.240906 [Byte1]: 63
3377 11:11:41.245746
3378 11:11:41.245843 Set Vref, RX VrefLevel [Byte0]: 64
3379 11:11:41.248794 [Byte1]: 64
3380 11:11:41.253368
3381 11:11:41.253479 Set Vref, RX VrefLevel [Byte0]: 65
3382 11:11:41.256987 [Byte1]: 65
3383 11:11:41.261443
3384 11:11:41.261524 Set Vref, RX VrefLevel [Byte0]: 66
3385 11:11:41.264604 [Byte1]: 66
3386 11:11:41.268878
3387 11:11:41.272228 Set Vref, RX VrefLevel [Byte0]: 67
3388 11:11:41.272436 [Byte1]: 67
3389 11:11:41.276998
3390 11:11:41.277080 Set Vref, RX VrefLevel [Byte0]: 68
3391 11:11:41.280147 [Byte1]: 68
3392 11:11:41.285142
3393 11:11:41.285223 Final RX Vref Byte 0 = 55 to rank0
3394 11:11:41.288171 Final RX Vref Byte 1 = 55 to rank0
3395 11:11:41.291414 Final RX Vref Byte 0 = 55 to rank1
3396 11:11:41.295132 Final RX Vref Byte 1 = 55 to rank1==
3397 11:11:41.298290 Dram Type= 6, Freq= 0, CH_1, rank 0
3398 11:11:41.301487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3399 11:11:41.305188 ==
3400 11:11:41.305271 DQS Delay:
3401 11:11:41.305335 DQS0 = 0, DQS1 = 0
3402 11:11:41.308305 DQM Delay:
3403 11:11:41.308402 DQM0 = 120, DQM1 = 117
3404 11:11:41.312065 DQ Delay:
3405 11:11:41.315285 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3406 11:11:41.318860 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3407 11:11:41.321842 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3408 11:11:41.325174 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3409 11:11:41.325257
3410 11:11:41.325322
3411 11:11:41.331994 [DQSOSCAuto] RK0, (LSB)MR18= 0xff12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3412 11:11:41.335086 CH1 RK0: MR19=304, MR18=FF12
3413 11:11:41.342086 CH1_RK0: MR19=0x304, MR18=0xFF12, DQSOSC=403, MR23=63, INC=40, DEC=26
3414 11:11:41.342171
3415 11:11:41.345524 ----->DramcWriteLeveling(PI) begin...
3416 11:11:41.345599 ==
3417 11:11:41.348488 Dram Type= 6, Freq= 0, CH_1, rank 1
3418 11:11:41.351879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 11:11:41.351961 ==
3420 11:11:41.355315 Write leveling (Byte 0): 25 => 25
3421 11:11:41.358530 Write leveling (Byte 1): 28 => 28
3422 11:11:41.362211 DramcWriteLeveling(PI) end<-----
3423 11:11:41.362309
3424 11:11:41.362374 ==
3425 11:11:41.365823 Dram Type= 6, Freq= 0, CH_1, rank 1
3426 11:11:41.369042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 11:11:41.372162 ==
3428 11:11:41.372270 [Gating] SW mode calibration
3429 11:11:41.378865 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3430 11:11:41.385714 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3431 11:11:41.388688 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 11:11:41.395635 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3433 11:11:41.398748 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 11:11:41.402432 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 11:11:41.408777 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 11:11:41.412449 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 11:11:41.415600 0 15 24 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
3438 11:11:41.419516 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 11:11:41.425698 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 11:11:41.429236 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 11:11:41.432131 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 11:11:41.438942 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 11:11:41.442086 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 11:11:41.445652 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3445 11:11:41.452033 1 0 24 | B1->B0 | 4545 2e2e | 0 0 | (0 0) (0 0)
3446 11:11:41.455527 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3447 11:11:41.458860 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 11:11:41.465513 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 11:11:41.468845 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 11:11:41.472184 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 11:11:41.478767 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 11:11:41.482518 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 11:11:41.485698 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3454 11:11:41.492027 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3455 11:11:41.495599 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 11:11:41.498709 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 11:11:41.505855 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 11:11:41.508959 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 11:11:41.512006 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 11:11:41.518624 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 11:11:41.522329 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 11:11:41.525528 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 11:11:41.528615 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 11:11:41.535523 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 11:11:41.539095 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 11:11:41.542364 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 11:11:41.548900 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 11:11:41.552339 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3469 11:11:41.555409 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3470 11:11:41.558977 Total UI for P1: 0, mck2ui 16
3471 11:11:41.562359 best dqsien dly found for B1: ( 1, 3, 20)
3472 11:11:41.568690 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3473 11:11:41.571879 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 11:11:41.575682 Total UI for P1: 0, mck2ui 16
3475 11:11:41.578762 best dqsien dly found for B0: ( 1, 3, 26)
3476 11:11:41.581834 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3477 11:11:41.585258 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3478 11:11:41.585340
3479 11:11:41.588337 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3480 11:11:41.591957 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3481 11:11:41.595242 [Gating] SW calibration Done
3482 11:11:41.595340 ==
3483 11:11:41.598467 Dram Type= 6, Freq= 0, CH_1, rank 1
3484 11:11:41.605384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 11:11:41.605502 ==
3486 11:11:41.605597 RX Vref Scan: 0
3487 11:11:41.605701
3488 11:11:41.608584 RX Vref 0 -> 0, step: 1
3489 11:11:41.608679
3490 11:11:41.611390 RX Delay -40 -> 252, step: 8
3491 11:11:41.615225 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3492 11:11:41.618256 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3493 11:11:41.621420 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3494 11:11:41.625047 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3495 11:11:41.631387 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3496 11:11:41.635131 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3497 11:11:41.638209 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3498 11:11:41.641375 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3499 11:11:41.645209 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3500 11:11:41.651677 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3501 11:11:41.655028 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3502 11:11:41.658406 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3503 11:11:41.661791 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3504 11:11:41.664986 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3505 11:11:41.671602 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3506 11:11:41.674843 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3507 11:11:41.674928 ==
3508 11:11:41.677825 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 11:11:41.681644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 11:11:41.681729 ==
3511 11:11:41.684616 DQS Delay:
3512 11:11:41.684700 DQS0 = 0, DQS1 = 0
3513 11:11:41.687893 DQM Delay:
3514 11:11:41.687979 DQM0 = 120, DQM1 = 117
3515 11:11:41.688045 DQ Delay:
3516 11:11:41.691022 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3517 11:11:41.698061 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3518 11:11:41.700985 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3519 11:11:41.704528 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3520 11:11:41.704612
3521 11:11:41.704677
3522 11:11:41.704737 ==
3523 11:11:41.707995 Dram Type= 6, Freq= 0, CH_1, rank 1
3524 11:11:41.711564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3525 11:11:41.711648 ==
3526 11:11:41.711713
3527 11:11:41.711773
3528 11:11:41.714790 TX Vref Scan disable
3529 11:11:41.718134 == TX Byte 0 ==
3530 11:11:41.720937 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3531 11:11:41.724674 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3532 11:11:41.728154 == TX Byte 1 ==
3533 11:11:41.731371 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3534 11:11:41.734590 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3535 11:11:41.734675 ==
3536 11:11:41.738286 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 11:11:41.741515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 11:11:41.741600 ==
3539 11:11:41.754134 TX Vref=22, minBit 9, minWin=25, winSum=420
3540 11:11:41.757983 TX Vref=24, minBit 10, minWin=25, winSum=426
3541 11:11:41.760797 TX Vref=26, minBit 2, minWin=26, winSum=428
3542 11:11:41.764444 TX Vref=28, minBit 9, minWin=26, winSum=432
3543 11:11:41.767388 TX Vref=30, minBit 9, minWin=26, winSum=434
3544 11:11:41.774450 TX Vref=32, minBit 0, minWin=27, winSum=436
3545 11:11:41.777818 [TxChooseVref] Worse bit 0, Min win 27, Win sum 436, Final Vref 32
3546 11:11:41.777900
3547 11:11:41.781177 Final TX Range 1 Vref 32
3548 11:11:41.781259
3549 11:11:41.781336 ==
3550 11:11:41.784404 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 11:11:41.787471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 11:11:41.787553 ==
3553 11:11:41.790695
3554 11:11:41.790777
3555 11:11:41.790841 TX Vref Scan disable
3556 11:11:41.794486 == TX Byte 0 ==
3557 11:11:41.797639 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3558 11:11:41.800708 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3559 11:11:41.804320 == TX Byte 1 ==
3560 11:11:41.807753 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3561 11:11:41.810674 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3562 11:11:41.814330
3563 11:11:41.814411 [DATLAT]
3564 11:11:41.814475 Freq=1200, CH1 RK1
3565 11:11:41.814535
3566 11:11:41.817599 DATLAT Default: 0xd
3567 11:11:41.817681 0, 0xFFFF, sum = 0
3568 11:11:41.820651 1, 0xFFFF, sum = 0
3569 11:11:41.820735 2, 0xFFFF, sum = 0
3570 11:11:41.824146 3, 0xFFFF, sum = 0
3571 11:11:41.827595 4, 0xFFFF, sum = 0
3572 11:11:41.827679 5, 0xFFFF, sum = 0
3573 11:11:41.831239 6, 0xFFFF, sum = 0
3574 11:11:41.831322 7, 0xFFFF, sum = 0
3575 11:11:41.833884 8, 0xFFFF, sum = 0
3576 11:11:41.833968 9, 0xFFFF, sum = 0
3577 11:11:41.837269 10, 0xFFFF, sum = 0
3578 11:11:41.837353 11, 0xFFFF, sum = 0
3579 11:11:41.840589 12, 0x0, sum = 1
3580 11:11:41.840696 13, 0x0, sum = 2
3581 11:11:41.844331 14, 0x0, sum = 3
3582 11:11:41.844430 15, 0x0, sum = 4
3583 11:11:41.844528 best_step = 13
3584 11:11:41.844605
3585 11:11:41.847532 ==
3586 11:11:41.850782 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 11:11:41.854554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 11:11:41.854636 ==
3589 11:11:41.854701 RX Vref Scan: 0
3590 11:11:41.854761
3591 11:11:41.857663 RX Vref 0 -> 0, step: 1
3592 11:11:41.857745
3593 11:11:41.860901 RX Delay -5 -> 252, step: 4
3594 11:11:41.863874 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3595 11:11:41.870977 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3596 11:11:41.873863 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3597 11:11:41.877601 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3598 11:11:41.880531 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3599 11:11:41.884121 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3600 11:11:41.887263 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3601 11:11:41.894076 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3602 11:11:41.897200 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3603 11:11:41.900471 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3604 11:11:41.904221 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3605 11:11:41.910881 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3606 11:11:41.913894 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3607 11:11:41.917300 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3608 11:11:41.920803 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3609 11:11:41.923917 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3610 11:11:41.923999 ==
3611 11:11:41.927082 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 11:11:41.933709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 11:11:41.933793 ==
3614 11:11:41.933857 DQS Delay:
3615 11:11:41.937423 DQS0 = 0, DQS1 = 0
3616 11:11:41.937505 DQM Delay:
3617 11:11:41.940275 DQM0 = 120, DQM1 = 117
3618 11:11:41.940382 DQ Delay:
3619 11:11:41.943892 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3620 11:11:41.947385 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3621 11:11:41.950521 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3622 11:11:41.954104 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3623 11:11:41.954186
3624 11:11:41.954251
3625 11:11:41.964090 [DQSOSCAuto] RK1, (LSB)MR18= 0xeeb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3626 11:11:41.964172 CH1 RK1: MR19=403, MR18=EEB
3627 11:11:41.970957 CH1_RK1: MR19=0x403, MR18=0xEEB, DQSOSC=404, MR23=63, INC=40, DEC=26
3628 11:11:41.974073 [RxdqsGatingPostProcess] freq 1200
3629 11:11:41.980484 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3630 11:11:41.984195 best DQS0 dly(2T, 0.5T) = (0, 11)
3631 11:11:41.987430 best DQS1 dly(2T, 0.5T) = (0, 11)
3632 11:11:41.990589 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3633 11:11:41.993951 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3634 11:11:41.997405 best DQS0 dly(2T, 0.5T) = (0, 11)
3635 11:11:41.997487 best DQS1 dly(2T, 0.5T) = (0, 11)
3636 11:11:42.000458 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3637 11:11:42.003409 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3638 11:11:42.007106 Pre-setting of DQS Precalculation
3639 11:11:42.013368 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3640 11:11:42.020089 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3641 11:11:42.027143 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3642 11:11:42.027227
3643 11:11:42.027291
3644 11:11:42.030129 [Calibration Summary] 2400 Mbps
3645 11:11:42.030213 CH 0, Rank 0
3646 11:11:42.033968 SW Impedance : PASS
3647 11:11:42.037043 DUTY Scan : NO K
3648 11:11:42.037149 ZQ Calibration : PASS
3649 11:11:42.040125 Jitter Meter : NO K
3650 11:11:42.043889 CBT Training : PASS
3651 11:11:42.043971 Write leveling : PASS
3652 11:11:42.047022 RX DQS gating : PASS
3653 11:11:42.050198 RX DQ/DQS(RDDQC) : PASS
3654 11:11:42.050280 TX DQ/DQS : PASS
3655 11:11:42.053315 RX DATLAT : PASS
3656 11:11:42.056792 RX DQ/DQS(Engine): PASS
3657 11:11:42.056873 TX OE : NO K
3658 11:11:42.060250 All Pass.
3659 11:11:42.060371
3660 11:11:42.060435 CH 0, Rank 1
3661 11:11:42.063484 SW Impedance : PASS
3662 11:11:42.063566 DUTY Scan : NO K
3663 11:11:42.067087 ZQ Calibration : PASS
3664 11:11:42.070276 Jitter Meter : NO K
3665 11:11:42.070358 CBT Training : PASS
3666 11:11:42.073465 Write leveling : PASS
3667 11:11:42.073547 RX DQS gating : PASS
3668 11:11:42.076619 RX DQ/DQS(RDDQC) : PASS
3669 11:11:42.080322 TX DQ/DQS : PASS
3670 11:11:42.080418 RX DATLAT : PASS
3671 11:11:42.083454 RX DQ/DQS(Engine): PASS
3672 11:11:42.086991 TX OE : NO K
3673 11:11:42.087073 All Pass.
3674 11:11:42.087139
3675 11:11:42.087198 CH 1, Rank 0
3676 11:11:42.090414 SW Impedance : PASS
3677 11:11:42.093230 DUTY Scan : NO K
3678 11:11:42.093368 ZQ Calibration : PASS
3679 11:11:42.096459 Jitter Meter : NO K
3680 11:11:42.100090 CBT Training : PASS
3681 11:11:42.100172 Write leveling : PASS
3682 11:11:42.103354 RX DQS gating : PASS
3683 11:11:42.106815 RX DQ/DQS(RDDQC) : PASS
3684 11:11:42.106897 TX DQ/DQS : PASS
3685 11:11:42.110072 RX DATLAT : PASS
3686 11:11:42.113177 RX DQ/DQS(Engine): PASS
3687 11:11:42.113260 TX OE : NO K
3688 11:11:42.116754 All Pass.
3689 11:11:42.116836
3690 11:11:42.116902 CH 1, Rank 1
3691 11:11:42.119622 SW Impedance : PASS
3692 11:11:42.119704 DUTY Scan : NO K
3693 11:11:42.123255 ZQ Calibration : PASS
3694 11:11:42.126274 Jitter Meter : NO K
3695 11:11:42.126373 CBT Training : PASS
3696 11:11:42.129993 Write leveling : PASS
3697 11:11:42.130075 RX DQS gating : PASS
3698 11:11:42.132992 RX DQ/DQS(RDDQC) : PASS
3699 11:11:42.136377 TX DQ/DQS : PASS
3700 11:11:42.136460 RX DATLAT : PASS
3701 11:11:42.140022 RX DQ/DQS(Engine): PASS
3702 11:11:42.143015 TX OE : NO K
3703 11:11:42.143097 All Pass.
3704 11:11:42.143161
3705 11:11:42.146379 DramC Write-DBI off
3706 11:11:42.146462 PER_BANK_REFRESH: Hybrid Mode
3707 11:11:42.149439 TX_TRACKING: ON
3708 11:11:42.159563 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3709 11:11:42.162795 [FAST_K] Save calibration result to emmc
3710 11:11:42.166465 dramc_set_vcore_voltage set vcore to 650000
3711 11:11:42.166548 Read voltage for 600, 5
3712 11:11:42.169390 Vio18 = 0
3713 11:11:42.169472 Vcore = 650000
3714 11:11:42.169537 Vdram = 0
3715 11:11:42.173313 Vddq = 0
3716 11:11:42.173409 Vmddr = 0
3717 11:11:42.176471 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3718 11:11:42.183103 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3719 11:11:42.186233 MEM_TYPE=3, freq_sel=19
3720 11:11:42.189465 sv_algorithm_assistance_LP4_1600
3721 11:11:42.192973 ============ PULL DRAM RESETB DOWN ============
3722 11:11:42.196041 ========== PULL DRAM RESETB DOWN end =========
3723 11:11:42.202738 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3724 11:11:42.205954 ===================================
3725 11:11:42.206037 LPDDR4 DRAM CONFIGURATION
3726 11:11:42.209191 ===================================
3727 11:11:42.212928 EX_ROW_EN[0] = 0x0
3728 11:11:42.213010 EX_ROW_EN[1] = 0x0
3729 11:11:42.215984 LP4Y_EN = 0x0
3730 11:11:42.219601 WORK_FSP = 0x0
3731 11:11:42.219684 WL = 0x2
3732 11:11:42.222571 RL = 0x2
3733 11:11:42.222654 BL = 0x2
3734 11:11:42.226020 RPST = 0x0
3735 11:11:42.226103 RD_PRE = 0x0
3736 11:11:42.229480 WR_PRE = 0x1
3737 11:11:42.229577 WR_PST = 0x0
3738 11:11:42.232756 DBI_WR = 0x0
3739 11:11:42.232839 DBI_RD = 0x0
3740 11:11:42.235941 OTF = 0x1
3741 11:11:42.239755 ===================================
3742 11:11:42.242617 ===================================
3743 11:11:42.242700 ANA top config
3744 11:11:42.246159 ===================================
3745 11:11:42.249488 DLL_ASYNC_EN = 0
3746 11:11:42.252661 ALL_SLAVE_EN = 1
3747 11:11:42.252743 NEW_RANK_MODE = 1
3748 11:11:42.256042 DLL_IDLE_MODE = 1
3749 11:11:42.259718 LP45_APHY_COMB_EN = 1
3750 11:11:42.262931 TX_ODT_DIS = 1
3751 11:11:42.263013 NEW_8X_MODE = 1
3752 11:11:42.265982 ===================================
3753 11:11:42.269245 ===================================
3754 11:11:42.272911 data_rate = 1200
3755 11:11:42.275964 CKR = 1
3756 11:11:42.279721 DQ_P2S_RATIO = 8
3757 11:11:42.282606 ===================================
3758 11:11:42.286066 CA_P2S_RATIO = 8
3759 11:11:42.289350 DQ_CA_OPEN = 0
3760 11:11:42.289449 DQ_SEMI_OPEN = 0
3761 11:11:42.292985 CA_SEMI_OPEN = 0
3762 11:11:42.295951 CA_FULL_RATE = 0
3763 11:11:42.299487 DQ_CKDIV4_EN = 1
3764 11:11:42.302767 CA_CKDIV4_EN = 1
3765 11:11:42.305791 CA_PREDIV_EN = 0
3766 11:11:42.305873 PH8_DLY = 0
3767 11:11:42.309187 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3768 11:11:42.313001 DQ_AAMCK_DIV = 4
3769 11:11:42.316159 CA_AAMCK_DIV = 4
3770 11:11:42.319203 CA_ADMCK_DIV = 4
3771 11:11:42.322864 DQ_TRACK_CA_EN = 0
3772 11:11:42.325968 CA_PICK = 600
3773 11:11:42.326051 CA_MCKIO = 600
3774 11:11:42.328952 MCKIO_SEMI = 0
3775 11:11:42.332222 PLL_FREQ = 2288
3776 11:11:42.335441 DQ_UI_PI_RATIO = 32
3777 11:11:42.338919 CA_UI_PI_RATIO = 0
3778 11:11:42.342439 ===================================
3779 11:11:42.345493 ===================================
3780 11:11:42.349102 memory_type:LPDDR4
3781 11:11:42.349210 GP_NUM : 10
3782 11:11:42.352084 SRAM_EN : 1
3783 11:11:42.352166 MD32_EN : 0
3784 11:11:42.355500 ===================================
3785 11:11:42.358759 [ANA_INIT] >>>>>>>>>>>>>>
3786 11:11:42.362507 <<<<<< [CONFIGURE PHASE]: ANA_TX
3787 11:11:42.365668 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3788 11:11:42.368737 ===================================
3789 11:11:42.372225 data_rate = 1200,PCW = 0X5800
3790 11:11:42.375283 ===================================
3791 11:11:42.379079 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3792 11:11:42.382191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3793 11:11:42.388602 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3794 11:11:42.395289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3795 11:11:42.398722 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3796 11:11:42.401952 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3797 11:11:42.402054 [ANA_INIT] flow start
3798 11:11:42.405828 [ANA_INIT] PLL >>>>>>>>
3799 11:11:42.408738 [ANA_INIT] PLL <<<<<<<<
3800 11:11:42.408820 [ANA_INIT] MIDPI >>>>>>>>
3801 11:11:42.412254 [ANA_INIT] MIDPI <<<<<<<<
3802 11:11:42.415302 [ANA_INIT] DLL >>>>>>>>
3803 11:11:42.415384 [ANA_INIT] flow end
3804 11:11:42.419035 ============ LP4 DIFF to SE enter ============
3805 11:11:42.425247 ============ LP4 DIFF to SE exit ============
3806 11:11:42.425330 [ANA_INIT] <<<<<<<<<<<<<
3807 11:11:42.428649 [Flow] Enable top DCM control >>>>>
3808 11:11:42.431783 [Flow] Enable top DCM control <<<<<
3809 11:11:42.435718 Enable DLL master slave shuffle
3810 11:11:42.442164 ==============================================================
3811 11:11:42.445214 Gating Mode config
3812 11:11:42.448854 ==============================================================
3813 11:11:42.451951 Config description:
3814 11:11:42.461995 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3815 11:11:42.468631 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3816 11:11:42.471953 SELPH_MODE 0: By rank 1: By Phase
3817 11:11:42.478773 ==============================================================
3818 11:11:42.481819 GAT_TRACK_EN = 1
3819 11:11:42.484916 RX_GATING_MODE = 2
3820 11:11:42.484999 RX_GATING_TRACK_MODE = 2
3821 11:11:42.489139 SELPH_MODE = 1
3822 11:11:42.491821 PICG_EARLY_EN = 1
3823 11:11:42.495074 VALID_LAT_VALUE = 1
3824 11:11:42.501978 ==============================================================
3825 11:11:42.504988 Enter into Gating configuration >>>>
3826 11:11:42.508643 Exit from Gating configuration <<<<
3827 11:11:42.511918 Enter into DVFS_PRE_config >>>>>
3828 11:11:42.521728 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3829 11:11:42.525162 Exit from DVFS_PRE_config <<<<<
3830 11:11:42.527969 Enter into PICG configuration >>>>
3831 11:11:42.531396 Exit from PICG configuration <<<<
3832 11:11:42.534618 [RX_INPUT] configuration >>>>>
3833 11:11:42.538484 [RX_INPUT] configuration <<<<<
3834 11:11:42.541754 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3835 11:11:42.548066 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3836 11:11:42.554775 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3837 11:11:42.561811 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3838 11:11:42.564935 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3839 11:11:42.571750 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3840 11:11:42.574780 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3841 11:11:42.581836 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3842 11:11:42.584805 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3843 11:11:42.587942 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3844 11:11:42.591564 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3845 11:11:42.597862 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3846 11:11:42.601642 ===================================
3847 11:11:42.604937 LPDDR4 DRAM CONFIGURATION
3848 11:11:42.608316 ===================================
3849 11:11:42.608412 EX_ROW_EN[0] = 0x0
3850 11:11:42.611389 EX_ROW_EN[1] = 0x0
3851 11:11:42.611471 LP4Y_EN = 0x0
3852 11:11:42.614543 WORK_FSP = 0x0
3853 11:11:42.614624 WL = 0x2
3854 11:11:42.617588 RL = 0x2
3855 11:11:42.617668 BL = 0x2
3856 11:11:42.621252 RPST = 0x0
3857 11:11:42.621332 RD_PRE = 0x0
3858 11:11:42.624729 WR_PRE = 0x1
3859 11:11:42.624811 WR_PST = 0x0
3860 11:11:42.627486 DBI_WR = 0x0
3861 11:11:42.627593 DBI_RD = 0x0
3862 11:11:42.631167 OTF = 0x1
3863 11:11:42.634675 ===================================
3864 11:11:42.638104 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3865 11:11:42.641339 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3866 11:11:42.647574 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3867 11:11:42.651355 ===================================
3868 11:11:42.651437 LPDDR4 DRAM CONFIGURATION
3869 11:11:42.654544 ===================================
3870 11:11:42.657618 EX_ROW_EN[0] = 0x10
3871 11:11:42.661340 EX_ROW_EN[1] = 0x0
3872 11:11:42.661421 LP4Y_EN = 0x0
3873 11:11:42.664578 WORK_FSP = 0x0
3874 11:11:42.664660 WL = 0x2
3875 11:11:42.667632 RL = 0x2
3876 11:11:42.667713 BL = 0x2
3877 11:11:42.670694 RPST = 0x0
3878 11:11:42.670775 RD_PRE = 0x0
3879 11:11:42.674418 WR_PRE = 0x1
3880 11:11:42.674500 WR_PST = 0x0
3881 11:11:42.677714 DBI_WR = 0x0
3882 11:11:42.677796 DBI_RD = 0x0
3883 11:11:42.680849 OTF = 0x1
3884 11:11:42.684076 ===================================
3885 11:11:42.691012 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3886 11:11:42.693979 nWR fixed to 30
3887 11:11:42.697645 [ModeRegInit_LP4] CH0 RK0
3888 11:11:42.697726 [ModeRegInit_LP4] CH0 RK1
3889 11:11:42.700800 [ModeRegInit_LP4] CH1 RK0
3890 11:11:42.703943 [ModeRegInit_LP4] CH1 RK1
3891 11:11:42.704024 match AC timing 17
3892 11:11:42.710809 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3893 11:11:42.714006 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3894 11:11:42.717668 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3895 11:11:42.724160 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3896 11:11:42.727415 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3897 11:11:42.727530 ==
3898 11:11:42.730457 Dram Type= 6, Freq= 0, CH_0, rank 0
3899 11:11:42.734455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3900 11:11:42.734537 ==
3901 11:11:42.740851 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3902 11:11:42.747423 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3903 11:11:42.750359 [CA 0] Center 35 (5~66) winsize 62
3904 11:11:42.753733 [CA 1] Center 36 (5~67) winsize 63
3905 11:11:42.757541 [CA 2] Center 33 (3~64) winsize 62
3906 11:11:42.760914 [CA 3] Center 33 (2~64) winsize 63
3907 11:11:42.763809 [CA 4] Center 33 (2~64) winsize 63
3908 11:11:42.767552 [CA 5] Center 32 (2~63) winsize 62
3909 11:11:42.767634
3910 11:11:42.770757 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3911 11:11:42.770838
3912 11:11:42.773859 [CATrainingPosCal] consider 1 rank data
3913 11:11:42.777030 u2DelayCellTimex100 = 270/100 ps
3914 11:11:42.780635 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3915 11:11:42.783747 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3916 11:11:42.787564 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3917 11:11:42.790671 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3918 11:11:42.794328 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3919 11:11:42.797565 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3920 11:11:42.797647
3921 11:11:42.803943 CA PerBit enable=1, Macro0, CA PI delay=32
3922 11:11:42.804025
3923 11:11:42.804089 [CBTSetCACLKResult] CA Dly = 32
3924 11:11:42.807064 CS Dly: 4 (0~35)
3925 11:11:42.807145 ==
3926 11:11:42.810503 Dram Type= 6, Freq= 0, CH_0, rank 1
3927 11:11:42.813677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3928 11:11:42.813759 ==
3929 11:11:42.820696 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3930 11:11:42.827015 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3931 11:11:42.830182 [CA 0] Center 36 (5~67) winsize 63
3932 11:11:42.833691 [CA 1] Center 35 (5~66) winsize 62
3933 11:11:42.837077 [CA 2] Center 34 (3~65) winsize 63
3934 11:11:42.840483 [CA 3] Center 34 (3~65) winsize 63
3935 11:11:42.843924 [CA 4] Center 33 (2~64) winsize 63
3936 11:11:42.847304 [CA 5] Center 32 (2~63) winsize 62
3937 11:11:42.847386
3938 11:11:42.850561 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3939 11:11:42.850643
3940 11:11:42.853703 [CATrainingPosCal] consider 2 rank data
3941 11:11:42.857430 u2DelayCellTimex100 = 270/100 ps
3942 11:11:42.860419 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3943 11:11:42.863679 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3944 11:11:42.867121 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3945 11:11:42.870331 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3946 11:11:42.873626 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3947 11:11:42.876780 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3948 11:11:42.880472
3949 11:11:42.883523 CA PerBit enable=1, Macro0, CA PI delay=32
3950 11:11:42.883603
3951 11:11:42.886763 [CBTSetCACLKResult] CA Dly = 32
3952 11:11:42.886873 CS Dly: 4 (0~36)
3953 11:11:42.886990
3954 11:11:42.889972 ----->DramcWriteLeveling(PI) begin...
3955 11:11:42.890080 ==
3956 11:11:42.893318 Dram Type= 6, Freq= 0, CH_0, rank 0
3957 11:11:42.896984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3958 11:11:42.899864 ==
3959 11:11:42.899992 Write leveling (Byte 0): 33 => 33
3960 11:11:42.903544 Write leveling (Byte 1): 30 => 30
3961 11:11:42.906760 DramcWriteLeveling(PI) end<-----
3962 11:11:42.906841
3963 11:11:42.906906 ==
3964 11:11:42.909841 Dram Type= 6, Freq= 0, CH_0, rank 0
3965 11:11:42.916548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 11:11:42.916630 ==
3967 11:11:42.919683 [Gating] SW mode calibration
3968 11:11:42.926558 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3969 11:11:42.930322 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3970 11:11:42.936760 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3971 11:11:42.939940 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3972 11:11:42.943166 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3973 11:11:42.946901 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 0) (0 0)
3974 11:11:42.953215 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
3975 11:11:42.956198 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 11:11:42.959711 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 11:11:42.966520 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 11:11:42.969996 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 11:11:42.972872 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 11:11:42.979695 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 11:11:42.982837 0 10 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
3982 11:11:42.986374 0 10 16 | B1->B0 | 3636 4545 | 0 0 | (1 1) (0 0)
3983 11:11:42.992798 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 11:11:42.996147 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 11:11:42.999364 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 11:11:43.006455 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 11:11:43.009357 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 11:11:43.013068 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 11:11:43.019951 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3990 11:11:43.023133 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3991 11:11:43.026316 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 11:11:43.033306 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 11:11:43.036453 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 11:11:43.039638 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 11:11:43.046195 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 11:11:43.049416 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 11:11:43.052602 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 11:11:43.059685 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 11:11:43.062739 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 11:11:43.066001 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 11:11:43.072737 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 11:11:43.076209 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 11:11:43.079613 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 11:11:43.085982 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 11:11:43.089551 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 11:11:43.092702 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4007 11:11:43.095685 Total UI for P1: 0, mck2ui 16
4008 11:11:43.099397 best dqsien dly found for B0: ( 0, 13, 14)
4009 11:11:43.102720 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 11:11:43.106063 Total UI for P1: 0, mck2ui 16
4011 11:11:43.108916 best dqsien dly found for B1: ( 0, 13, 16)
4012 11:11:43.112279 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4013 11:11:43.119049 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4014 11:11:43.119131
4015 11:11:43.122680 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4016 11:11:43.125709 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4017 11:11:43.129458 [Gating] SW calibration Done
4018 11:11:43.129541 ==
4019 11:11:43.132497 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 11:11:43.135719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 11:11:43.135805 ==
4022 11:11:43.139517 RX Vref Scan: 0
4023 11:11:43.139599
4024 11:11:43.139664 RX Vref 0 -> 0, step: 1
4025 11:11:43.139725
4026 11:11:43.142814 RX Delay -230 -> 252, step: 16
4027 11:11:43.145927 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4028 11:11:43.152207 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4029 11:11:43.156056 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4030 11:11:43.159189 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4031 11:11:43.162343 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4032 11:11:43.165945 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4033 11:11:43.172600 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4034 11:11:43.175756 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4035 11:11:43.178853 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4036 11:11:43.182610 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4037 11:11:43.188973 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4038 11:11:43.192488 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4039 11:11:43.195656 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4040 11:11:43.199117 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4041 11:11:43.205553 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4042 11:11:43.208737 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4043 11:11:43.208818 ==
4044 11:11:43.212115 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 11:11:43.215401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 11:11:43.215482 ==
4047 11:11:43.218693 DQS Delay:
4048 11:11:43.218773 DQS0 = 0, DQS1 = 0
4049 11:11:43.218836 DQM Delay:
4050 11:11:43.221888 DQM0 = 49, DQM1 = 45
4051 11:11:43.221968 DQ Delay:
4052 11:11:43.225343 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4053 11:11:43.228922 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4054 11:11:43.232214 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4055 11:11:43.235573 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4056 11:11:43.235653
4057 11:11:43.235715
4058 11:11:43.235774 ==
4059 11:11:43.238938 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 11:11:43.245548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 11:11:43.245629 ==
4062 11:11:43.245692
4063 11:11:43.245751
4064 11:11:43.245806 TX Vref Scan disable
4065 11:11:43.248631 == TX Byte 0 ==
4066 11:11:43.252412 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4067 11:11:43.258753 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4068 11:11:43.258834 == TX Byte 1 ==
4069 11:11:43.261959 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4070 11:11:43.268723 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4071 11:11:43.268804 ==
4072 11:11:43.271839 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 11:11:43.275360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 11:11:43.275441 ==
4075 11:11:43.275505
4076 11:11:43.275563
4077 11:11:43.278424 TX Vref Scan disable
4078 11:11:43.282265 == TX Byte 0 ==
4079 11:11:43.285442 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4080 11:11:43.288441 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4081 11:11:43.292271 == TX Byte 1 ==
4082 11:11:43.295458 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4083 11:11:43.298675 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4084 11:11:43.298757
4085 11:11:43.298821 [DATLAT]
4086 11:11:43.302245 Freq=600, CH0 RK0
4087 11:11:43.302327
4088 11:11:43.302391 DATLAT Default: 0x9
4089 11:11:43.305586 0, 0xFFFF, sum = 0
4090 11:11:43.308799 1, 0xFFFF, sum = 0
4091 11:11:43.308882 2, 0xFFFF, sum = 0
4092 11:11:43.312420 3, 0xFFFF, sum = 0
4093 11:11:43.312503 4, 0xFFFF, sum = 0
4094 11:11:43.315180 5, 0xFFFF, sum = 0
4095 11:11:43.315263 6, 0xFFFF, sum = 0
4096 11:11:43.318505 7, 0xFFFF, sum = 0
4097 11:11:43.318608 8, 0x0, sum = 1
4098 11:11:43.318704 9, 0x0, sum = 2
4099 11:11:43.322042 10, 0x0, sum = 3
4100 11:11:43.322140 11, 0x0, sum = 4
4101 11:11:43.325028 best_step = 9
4102 11:11:43.325113
4103 11:11:43.325177 ==
4104 11:11:43.328557 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 11:11:43.331936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 11:11:43.332043 ==
4107 11:11:43.335246 RX Vref Scan: 1
4108 11:11:43.335354
4109 11:11:43.335444 RX Vref 0 -> 0, step: 1
4110 11:11:43.335507
4111 11:11:43.338826 RX Delay -163 -> 252, step: 8
4112 11:11:43.338929
4113 11:11:43.341703 Set Vref, RX VrefLevel [Byte0]: 55
4114 11:11:43.345054 [Byte1]: 51
4115 11:11:43.349147
4116 11:11:43.349229 Final RX Vref Byte 0 = 55 to rank0
4117 11:11:43.352575 Final RX Vref Byte 1 = 51 to rank0
4118 11:11:43.356013 Final RX Vref Byte 0 = 55 to rank1
4119 11:11:43.359274 Final RX Vref Byte 1 = 51 to rank1==
4120 11:11:43.362415 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 11:11:43.369489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 11:11:43.369615 ==
4123 11:11:43.369731 DQS Delay:
4124 11:11:43.369843 DQS0 = 0, DQS1 = 0
4125 11:11:43.372750 DQM Delay:
4126 11:11:43.372875 DQM0 = 52, DQM1 = 47
4127 11:11:43.376189 DQ Delay:
4128 11:11:43.379036 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =52
4129 11:11:43.379158 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4130 11:11:43.382703 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4131 11:11:43.388947 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =52
4132 11:11:43.389069
4133 11:11:43.389181
4134 11:11:43.395823 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
4135 11:11:43.399093 CH0 RK0: MR19=808, MR18=6A5E
4136 11:11:43.405604 CH0_RK0: MR19=0x808, MR18=0x6A5E, DQSOSC=389, MR23=63, INC=173, DEC=115
4137 11:11:43.405728
4138 11:11:43.409281 ----->DramcWriteLeveling(PI) begin...
4139 11:11:43.409407 ==
4140 11:11:43.412250 Dram Type= 6, Freq= 0, CH_0, rank 1
4141 11:11:43.415360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 11:11:43.415484 ==
4143 11:11:43.418721 Write leveling (Byte 0): 33 => 33
4144 11:11:43.422388 Write leveling (Byte 1): 30 => 30
4145 11:11:43.425616 DramcWriteLeveling(PI) end<-----
4146 11:11:43.425741
4147 11:11:43.425858 ==
4148 11:11:43.429001 Dram Type= 6, Freq= 0, CH_0, rank 1
4149 11:11:43.432509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 11:11:43.432679 ==
4151 11:11:43.435631 [Gating] SW mode calibration
4152 11:11:43.442084 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4153 11:11:43.448758 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4154 11:11:43.452250 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4155 11:11:43.455499 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4156 11:11:43.462294 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4157 11:11:43.465518 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
4158 11:11:43.468794 0 9 16 | B1->B0 | 2b2b 2626 | 0 0 | (0 0) (0 0)
4159 11:11:43.475732 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 11:11:43.478933 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 11:11:43.482098 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 11:11:43.488963 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 11:11:43.491990 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 11:11:43.495668 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 11:11:43.502092 0 10 12 | B1->B0 | 2828 2525 | 0 0 | (0 0) (0 0)
4166 11:11:43.505310 0 10 16 | B1->B0 | 3b3b 3f3f | 0 1 | (0 0) (0 0)
4167 11:11:43.508548 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 11:11:43.515363 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 11:11:43.518925 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 11:11:43.522071 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 11:11:43.529039 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 11:11:43.531904 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 11:11:43.535723 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4174 11:11:43.539244 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 11:11:43.545927 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 11:11:43.548641 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 11:11:43.552347 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 11:11:43.558706 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 11:11:43.562139 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 11:11:43.565474 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 11:11:43.572195 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 11:11:43.575349 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 11:11:43.578891 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 11:11:43.585287 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 11:11:43.588832 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 11:11:43.591788 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 11:11:43.598614 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 11:11:43.601613 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 11:11:43.605469 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4190 11:11:43.608050 Total UI for P1: 0, mck2ui 16
4191 11:11:43.611804 best dqsien dly found for B0: ( 0, 13, 10)
4192 11:11:43.618213 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 11:11:43.618338 Total UI for P1: 0, mck2ui 16
4194 11:11:43.624782 best dqsien dly found for B1: ( 0, 13, 12)
4195 11:11:43.628036 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4196 11:11:43.631898 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4197 11:11:43.632026
4198 11:11:43.635110 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4199 11:11:43.638116 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4200 11:11:43.641472 [Gating] SW calibration Done
4201 11:11:43.641594 ==
4202 11:11:43.644664 Dram Type= 6, Freq= 0, CH_0, rank 1
4203 11:11:43.648445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4204 11:11:43.648572 ==
4205 11:11:43.652083 RX Vref Scan: 0
4206 11:11:43.652206
4207 11:11:43.652327 RX Vref 0 -> 0, step: 1
4208 11:11:43.654885
4209 11:11:43.654972 RX Delay -230 -> 252, step: 16
4210 11:11:43.661463 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4211 11:11:43.664916 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4212 11:11:43.668393 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4213 11:11:43.671715 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4214 11:11:43.678115 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4215 11:11:43.681872 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4216 11:11:43.685043 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4217 11:11:43.688083 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4218 11:11:43.691243 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4219 11:11:43.698060 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4220 11:11:43.701265 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4221 11:11:43.705008 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4222 11:11:43.708374 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4223 11:11:43.714582 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4224 11:11:43.717722 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4225 11:11:43.721607 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4226 11:11:43.721734 ==
4227 11:11:43.724914 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 11:11:43.727908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 11:11:43.728034 ==
4230 11:11:43.731386 DQS Delay:
4231 11:11:43.731510 DQS0 = 0, DQS1 = 0
4232 11:11:43.734718 DQM Delay:
4233 11:11:43.734843 DQM0 = 52, DQM1 = 44
4234 11:11:43.734959 DQ Delay:
4235 11:11:43.737822 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4236 11:11:43.741491 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4237 11:11:43.744800 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4238 11:11:43.747873 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4239 11:11:43.747996
4240 11:11:43.751176
4241 11:11:43.751298 ==
4242 11:11:43.754202 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 11:11:43.757996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 11:11:43.758120 ==
4245 11:11:43.758237
4246 11:11:43.758349
4247 11:11:43.761084 TX Vref Scan disable
4248 11:11:43.761210 == TX Byte 0 ==
4249 11:11:43.767658 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4250 11:11:43.771100 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4251 11:11:43.771207 == TX Byte 1 ==
4252 11:11:43.777574 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4253 11:11:43.781174 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4254 11:11:43.781267 ==
4255 11:11:43.784818 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 11:11:43.787623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 11:11:43.787704 ==
4258 11:11:43.787770
4259 11:11:43.787873
4260 11:11:43.791278 TX Vref Scan disable
4261 11:11:43.794202 == TX Byte 0 ==
4262 11:11:43.797505 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4263 11:11:43.800746 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4264 11:11:43.804541 == TX Byte 1 ==
4265 11:11:43.807544 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4266 11:11:43.811183 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4267 11:11:43.811265
4268 11:11:43.814508 [DATLAT]
4269 11:11:43.814583 Freq=600, CH0 RK1
4270 11:11:43.814647
4271 11:11:43.817554 DATLAT Default: 0x9
4272 11:11:43.817655 0, 0xFFFF, sum = 0
4273 11:11:43.820726 1, 0xFFFF, sum = 0
4274 11:11:43.820839 2, 0xFFFF, sum = 0
4275 11:11:43.824132 3, 0xFFFF, sum = 0
4276 11:11:43.824218 4, 0xFFFF, sum = 0
4277 11:11:43.827208 5, 0xFFFF, sum = 0
4278 11:11:43.827294 6, 0xFFFF, sum = 0
4279 11:11:43.831102 7, 0xFFFF, sum = 0
4280 11:11:43.831187 8, 0x0, sum = 1
4281 11:11:43.834181 9, 0x0, sum = 2
4282 11:11:43.834266 10, 0x0, sum = 3
4283 11:11:43.837622 11, 0x0, sum = 4
4284 11:11:43.837707 best_step = 9
4285 11:11:43.837773
4286 11:11:43.837833 ==
4287 11:11:43.840805 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 11:11:43.847168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 11:11:43.847294 ==
4290 11:11:43.847364 RX Vref Scan: 0
4291 11:11:43.847426
4292 11:11:43.850490 RX Vref 0 -> 0, step: 1
4293 11:11:43.850582
4294 11:11:43.853787 RX Delay -163 -> 252, step: 8
4295 11:11:43.857595 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4296 11:11:43.860757 iDelay=197, Bit 1, Center 52 (-91 ~ 196) 288
4297 11:11:43.867699 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4298 11:11:43.870701 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4299 11:11:43.873987 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4300 11:11:43.877568 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4301 11:11:43.880615 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4302 11:11:43.887715 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4303 11:11:43.890742 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4304 11:11:43.894180 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4305 11:11:43.897545 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4306 11:11:43.900552 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4307 11:11:43.907258 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4308 11:11:43.910509 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4309 11:11:43.913900 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4310 11:11:43.917035 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4311 11:11:43.917117 ==
4312 11:11:43.920243 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 11:11:43.926974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 11:11:43.927058 ==
4315 11:11:43.927123 DQS Delay:
4316 11:11:43.930299 DQS0 = 0, DQS1 = 0
4317 11:11:43.930432 DQM Delay:
4318 11:11:43.930551 DQM0 = 52, DQM1 = 46
4319 11:11:43.933884 DQ Delay:
4320 11:11:43.937648 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4321 11:11:43.940686 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =56
4322 11:11:43.943959 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4323 11:11:43.947242 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4324 11:11:43.947344
4325 11:11:43.947434
4326 11:11:43.953900 [DQSOSCAuto] RK1, (LSB)MR18= 0x6223, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4327 11:11:43.957237 CH0 RK1: MR19=808, MR18=6223
4328 11:11:43.963881 CH0_RK1: MR19=0x808, MR18=0x6223, DQSOSC=391, MR23=63, INC=171, DEC=114
4329 11:11:43.966941 [RxdqsGatingPostProcess] freq 600
4330 11:11:43.970768 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4331 11:11:43.973904 Pre-setting of DQS Precalculation
4332 11:11:43.980361 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4333 11:11:43.980465 ==
4334 11:11:43.983579 Dram Type= 6, Freq= 0, CH_1, rank 0
4335 11:11:43.987171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 11:11:43.987300 ==
4337 11:11:43.993302 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4338 11:11:44.000169 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4339 11:11:44.003304 [CA 0] Center 36 (5~67) winsize 63
4340 11:11:44.006971 [CA 1] Center 36 (5~67) winsize 63
4341 11:11:44.009903 [CA 2] Center 34 (4~65) winsize 62
4342 11:11:44.013531 [CA 3] Center 34 (3~65) winsize 63
4343 11:11:44.016837 [CA 4] Center 34 (4~65) winsize 62
4344 11:11:44.019856 [CA 5] Center 34 (3~65) winsize 63
4345 11:11:44.019938
4346 11:11:44.023571 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4347 11:11:44.023703
4348 11:11:44.026729 [CATrainingPosCal] consider 1 rank data
4349 11:11:44.029794 u2DelayCellTimex100 = 270/100 ps
4350 11:11:44.033472 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4351 11:11:44.036720 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4352 11:11:44.039925 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4353 11:11:44.042964 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4354 11:11:44.046470 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4355 11:11:44.049801 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4356 11:11:44.049927
4357 11:11:44.056821 CA PerBit enable=1, Macro0, CA PI delay=34
4358 11:11:44.056907
4359 11:11:44.056974 [CBTSetCACLKResult] CA Dly = 34
4360 11:11:44.059821 CS Dly: 6 (0~37)
4361 11:11:44.059905 ==
4362 11:11:44.062953 Dram Type= 6, Freq= 0, CH_1, rank 1
4363 11:11:44.066138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 11:11:44.066223 ==
4365 11:11:44.072728 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4366 11:11:44.079697 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4367 11:11:44.082818 [CA 0] Center 36 (5~67) winsize 63
4368 11:11:44.086553 [CA 1] Center 36 (5~67) winsize 63
4369 11:11:44.089539 [CA 2] Center 35 (4~66) winsize 63
4370 11:11:44.093293 [CA 3] Center 34 (4~65) winsize 62
4371 11:11:44.096424 [CA 4] Center 35 (4~66) winsize 63
4372 11:11:44.099478 [CA 5] Center 34 (3~65) winsize 63
4373 11:11:44.099604
4374 11:11:44.102886 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4375 11:11:44.103012
4376 11:11:44.106291 [CATrainingPosCal] consider 2 rank data
4377 11:11:44.109693 u2DelayCellTimex100 = 270/100 ps
4378 11:11:44.112899 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4379 11:11:44.115841 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4380 11:11:44.119314 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4381 11:11:44.122922 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4382 11:11:44.126029 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4383 11:11:44.133037 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4384 11:11:44.133121
4385 11:11:44.136227 CA PerBit enable=1, Macro0, CA PI delay=34
4386 11:11:44.136317
4387 11:11:44.139384 [CBTSetCACLKResult] CA Dly = 34
4388 11:11:44.139467 CS Dly: 6 (0~37)
4389 11:11:44.139533
4390 11:11:44.142581 ----->DramcWriteLeveling(PI) begin...
4391 11:11:44.142666 ==
4392 11:11:44.145792 Dram Type= 6, Freq= 0, CH_1, rank 0
4393 11:11:44.149066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 11:11:44.152705 ==
4395 11:11:44.152811 Write leveling (Byte 0): 29 => 29
4396 11:11:44.155964 Write leveling (Byte 1): 30 => 30
4397 11:11:44.159213 DramcWriteLeveling(PI) end<-----
4398 11:11:44.159286
4399 11:11:44.159347 ==
4400 11:11:44.163025 Dram Type= 6, Freq= 0, CH_1, rank 0
4401 11:11:44.169378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 11:11:44.169459 ==
4403 11:11:44.169523 [Gating] SW mode calibration
4404 11:11:44.179120 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4405 11:11:44.182564 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4406 11:11:44.186082 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4407 11:11:44.192804 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4408 11:11:44.196074 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4409 11:11:44.199093 0 9 12 | B1->B0 | 2e2e 2e2e | 0 0 | (0 0) (0 0)
4410 11:11:44.205977 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 11:11:44.209750 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 11:11:44.212735 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 11:11:44.219434 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 11:11:44.222958 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 11:11:44.226315 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 11:11:44.233206 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4417 11:11:44.236215 0 10 12 | B1->B0 | 3939 3838 | 0 1 | (0 0) (0 0)
4418 11:11:44.239348 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 11:11:44.246232 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 11:11:44.249335 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 11:11:44.252504 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 11:11:44.259169 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 11:11:44.262973 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 11:11:44.266119 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 11:11:44.272453 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4426 11:11:44.276251 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4427 11:11:44.279126 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 11:11:44.282323 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 11:11:44.289102 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 11:11:44.292616 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 11:11:44.295987 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 11:11:44.302349 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 11:11:44.305310 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 11:11:44.308810 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 11:11:44.315352 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 11:11:44.318630 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 11:11:44.322260 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 11:11:44.328860 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 11:11:44.332507 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 11:11:44.335947 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4441 11:11:44.342346 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4442 11:11:44.345612 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 11:11:44.349129 Total UI for P1: 0, mck2ui 16
4444 11:11:44.352461 best dqsien dly found for B0: ( 0, 13, 12)
4445 11:11:44.355629 Total UI for P1: 0, mck2ui 16
4446 11:11:44.358693 best dqsien dly found for B1: ( 0, 13, 14)
4447 11:11:44.362355 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4448 11:11:44.365919 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4449 11:11:44.366041
4450 11:11:44.369111 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4451 11:11:44.372249 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4452 11:11:44.375404 [Gating] SW calibration Done
4453 11:11:44.375526 ==
4454 11:11:44.378656 Dram Type= 6, Freq= 0, CH_1, rank 0
4455 11:11:44.385580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4456 11:11:44.385704 ==
4457 11:11:44.385817 RX Vref Scan: 0
4458 11:11:44.385926
4459 11:11:44.388724 RX Vref 0 -> 0, step: 1
4460 11:11:44.388843
4461 11:11:44.391877 RX Delay -230 -> 252, step: 16
4462 11:11:44.395623 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4463 11:11:44.398794 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4464 11:11:44.401915 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4465 11:11:44.408961 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4466 11:11:44.412027 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4467 11:11:44.415161 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4468 11:11:44.418678 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4469 11:11:44.421911 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4470 11:11:44.428820 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4471 11:11:44.432058 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4472 11:11:44.435092 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4473 11:11:44.438445 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4474 11:11:44.445382 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4475 11:11:44.448524 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4476 11:11:44.451777 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4477 11:11:44.455172 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4478 11:11:44.455254 ==
4479 11:11:44.458382 Dram Type= 6, Freq= 0, CH_1, rank 0
4480 11:11:44.465534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 11:11:44.465643 ==
4482 11:11:44.465736 DQS Delay:
4483 11:11:44.468923 DQS0 = 0, DQS1 = 0
4484 11:11:44.469005 DQM Delay:
4485 11:11:44.469071 DQM0 = 48, DQM1 = 46
4486 11:11:44.471967 DQ Delay:
4487 11:11:44.475283 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4488 11:11:44.478476 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =49
4489 11:11:44.481718 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4490 11:11:44.485532 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4491 11:11:44.485614
4492 11:11:44.485678
4493 11:11:44.485737 ==
4494 11:11:44.488767 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 11:11:44.491944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 11:11:44.492026 ==
4497 11:11:44.492090
4498 11:11:44.492150
4499 11:11:44.495049 TX Vref Scan disable
4500 11:11:44.498254 == TX Byte 0 ==
4501 11:11:44.501969 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4502 11:11:44.505188 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4503 11:11:44.508491 == TX Byte 1 ==
4504 11:11:44.511631 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4505 11:11:44.515250 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4506 11:11:44.515335 ==
4507 11:11:44.518440 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 11:11:44.521642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 11:11:44.521724 ==
4510 11:11:44.525430
4511 11:11:44.525511
4512 11:11:44.525575 TX Vref Scan disable
4513 11:11:44.528597 == TX Byte 0 ==
4514 11:11:44.532073 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4515 11:11:44.535252 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4516 11:11:44.538514 == TX Byte 1 ==
4517 11:11:44.542212 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4518 11:11:44.548239 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4519 11:11:44.548357
4520 11:11:44.548423 [DATLAT]
4521 11:11:44.548483 Freq=600, CH1 RK0
4522 11:11:44.548541
4523 11:11:44.551717 DATLAT Default: 0x9
4524 11:11:44.551798 0, 0xFFFF, sum = 0
4525 11:11:44.554956 1, 0xFFFF, sum = 0
4526 11:11:44.555039 2, 0xFFFF, sum = 0
4527 11:11:44.558621 3, 0xFFFF, sum = 0
4528 11:11:44.558704 4, 0xFFFF, sum = 0
4529 11:11:44.561732 5, 0xFFFF, sum = 0
4530 11:11:44.565455 6, 0xFFFF, sum = 0
4531 11:11:44.565538 7, 0xFFFF, sum = 0
4532 11:11:44.565604 8, 0x0, sum = 1
4533 11:11:44.568411 9, 0x0, sum = 2
4534 11:11:44.568494 10, 0x0, sum = 3
4535 11:11:44.572340 11, 0x0, sum = 4
4536 11:11:44.572443 best_step = 9
4537 11:11:44.572509
4538 11:11:44.572571 ==
4539 11:11:44.575415 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 11:11:44.581946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 11:11:44.582029 ==
4542 11:11:44.582094 RX Vref Scan: 1
4543 11:11:44.582153
4544 11:11:44.585201 RX Vref 0 -> 0, step: 1
4545 11:11:44.585283
4546 11:11:44.588563 RX Delay -163 -> 252, step: 8
4547 11:11:44.588645
4548 11:11:44.591699 Set Vref, RX VrefLevel [Byte0]: 55
4549 11:11:44.595337 [Byte1]: 55
4550 11:11:44.595460
4551 11:11:44.598308 Final RX Vref Byte 0 = 55 to rank0
4552 11:11:44.601788 Final RX Vref Byte 1 = 55 to rank0
4553 11:11:44.604923 Final RX Vref Byte 0 = 55 to rank1
4554 11:11:44.608546 Final RX Vref Byte 1 = 55 to rank1==
4555 11:11:44.611666 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 11:11:44.614834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 11:11:44.614917 ==
4558 11:11:44.618017 DQS Delay:
4559 11:11:44.618099 DQS0 = 0, DQS1 = 0
4560 11:11:44.618163 DQM Delay:
4561 11:11:44.621935 DQM0 = 48, DQM1 = 45
4562 11:11:44.622017 DQ Delay:
4563 11:11:44.625030 DQ0 =48, DQ1 =40, DQ2 =40, DQ3 =48
4564 11:11:44.628137 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4565 11:11:44.631312 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4566 11:11:44.635120 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4567 11:11:44.635202
4568 11:11:44.635265
4569 11:11:44.644722 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b70, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4570 11:11:44.648414 CH1 RK0: MR19=808, MR18=4B70
4571 11:11:44.651463 CH1_RK0: MR19=0x808, MR18=0x4B70, DQSOSC=388, MR23=63, INC=174, DEC=116
4572 11:11:44.655166
4573 11:11:44.657946 ----->DramcWriteLeveling(PI) begin...
4574 11:11:44.658048 ==
4575 11:11:44.660997 Dram Type= 6, Freq= 0, CH_1, rank 1
4576 11:11:44.664767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 11:11:44.664849 ==
4578 11:11:44.668030 Write leveling (Byte 0): 29 => 29
4579 11:11:44.671245 Write leveling (Byte 1): 32 => 32
4580 11:11:44.674539 DramcWriteLeveling(PI) end<-----
4581 11:11:44.674620
4582 11:11:44.674684 ==
4583 11:11:44.677646 Dram Type= 6, Freq= 0, CH_1, rank 1
4584 11:11:44.681440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 11:11:44.681522 ==
4586 11:11:44.684330 [Gating] SW mode calibration
4587 11:11:44.691082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4588 11:11:44.698048 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4589 11:11:44.701232 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4590 11:11:44.704175 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4591 11:11:44.710895 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4592 11:11:44.714261 0 9 12 | B1->B0 | 3030 2f2f | 0 1 | (0 0) (1 0)
4593 11:11:44.717565 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4594 11:11:44.724509 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 11:11:44.727976 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 11:11:44.730711 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 11:11:44.737716 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 11:11:44.740770 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 11:11:44.744009 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 11:11:44.747594 0 10 12 | B1->B0 | 3636 3737 | 1 1 | (0 0) (0 0)
4601 11:11:44.754259 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4602 11:11:44.757875 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 11:11:44.760869 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 11:11:44.767425 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 11:11:44.770601 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 11:11:44.774447 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 11:11:44.780742 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 11:11:44.783945 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4609 11:11:44.787691 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 11:11:44.793993 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 11:11:44.797190 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 11:11:44.800906 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 11:11:44.807336 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 11:11:44.810416 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 11:11:44.814254 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 11:11:44.820390 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 11:11:44.824074 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 11:11:44.827126 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 11:11:44.833981 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 11:11:44.837247 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 11:11:44.840407 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 11:11:44.847380 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 11:11:44.850447 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 11:11:44.853453 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4625 11:11:44.860166 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 11:11:44.860248 Total UI for P1: 0, mck2ui 16
4627 11:11:44.866820 best dqsien dly found for B0: ( 0, 13, 12)
4628 11:11:44.866902 Total UI for P1: 0, mck2ui 16
4629 11:11:44.870177 best dqsien dly found for B1: ( 0, 13, 12)
4630 11:11:44.876829 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4631 11:11:44.880034 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4632 11:11:44.880115
4633 11:11:44.883789 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4634 11:11:44.886889 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4635 11:11:44.890171 [Gating] SW calibration Done
4636 11:11:44.890252 ==
4637 11:11:44.893337 Dram Type= 6, Freq= 0, CH_1, rank 1
4638 11:11:44.897052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4639 11:11:44.897133 ==
4640 11:11:44.899969 RX Vref Scan: 0
4641 11:11:44.900050
4642 11:11:44.900114 RX Vref 0 -> 0, step: 1
4643 11:11:44.900174
4644 11:11:44.903349 RX Delay -230 -> 252, step: 16
4645 11:11:44.906817 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4646 11:11:44.913165 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4647 11:11:44.916969 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4648 11:11:44.920005 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4649 11:11:44.923266 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4650 11:11:44.930076 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4651 11:11:44.933211 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4652 11:11:44.936334 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4653 11:11:44.940105 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4654 11:11:44.943202 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4655 11:11:44.949811 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4656 11:11:44.953315 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4657 11:11:44.956564 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4658 11:11:44.960069 iDelay=218, Bit 13, Center 65 (-86 ~ 217) 304
4659 11:11:44.966216 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4660 11:11:44.969317 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4661 11:11:44.969399 ==
4662 11:11:44.973048 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 11:11:44.976438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 11:11:44.976546 ==
4665 11:11:44.979379 DQS Delay:
4666 11:11:44.979485 DQS0 = 0, DQS1 = 0
4667 11:11:44.979575 DQM Delay:
4668 11:11:44.982768 DQM0 = 53, DQM1 = 49
4669 11:11:44.982850 DQ Delay:
4670 11:11:44.986378 DQ0 =65, DQ1 =49, DQ2 =33, DQ3 =49
4671 11:11:44.989342 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4672 11:11:44.993248 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4673 11:11:44.996117 DQ12 =57, DQ13 =65, DQ14 =49, DQ15 =57
4674 11:11:44.996225
4675 11:11:44.996352
4676 11:11:44.996416 ==
4677 11:11:44.999955 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 11:11:45.006035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 11:11:45.006117 ==
4680 11:11:45.006182
4681 11:11:45.006242
4682 11:11:45.006300 TX Vref Scan disable
4683 11:11:45.009973 == TX Byte 0 ==
4684 11:11:45.013473 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4685 11:11:45.016598 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4686 11:11:45.019693 == TX Byte 1 ==
4687 11:11:45.023436 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4688 11:11:45.026551 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4689 11:11:45.029615 ==
4690 11:11:45.033263 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 11:11:45.036449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 11:11:45.036532 ==
4693 11:11:45.036596
4694 11:11:45.036655
4695 11:11:45.039716 TX Vref Scan disable
4696 11:11:45.039798 == TX Byte 0 ==
4697 11:11:45.046708 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4698 11:11:45.049790 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4699 11:11:45.049873 == TX Byte 1 ==
4700 11:11:45.056694 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4701 11:11:45.059899 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4702 11:11:45.059981
4703 11:11:45.060046 [DATLAT]
4704 11:11:45.062912 Freq=600, CH1 RK1
4705 11:11:45.062993
4706 11:11:45.063058 DATLAT Default: 0x9
4707 11:11:45.066620 0, 0xFFFF, sum = 0
4708 11:11:45.066704 1, 0xFFFF, sum = 0
4709 11:11:45.069638 2, 0xFFFF, sum = 0
4710 11:11:45.069748 3, 0xFFFF, sum = 0
4711 11:11:45.073279 4, 0xFFFF, sum = 0
4712 11:11:45.076221 5, 0xFFFF, sum = 0
4713 11:11:45.076363 6, 0xFFFF, sum = 0
4714 11:11:45.079824 7, 0xFFFF, sum = 0
4715 11:11:45.079907 8, 0x0, sum = 1
4716 11:11:45.079973 9, 0x0, sum = 2
4717 11:11:45.083036 10, 0x0, sum = 3
4718 11:11:45.083119 11, 0x0, sum = 4
4719 11:11:45.086471 best_step = 9
4720 11:11:45.086553
4721 11:11:45.086617 ==
4722 11:11:45.089925 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 11:11:45.093022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 11:11:45.093105 ==
4725 11:11:45.096181 RX Vref Scan: 0
4726 11:11:45.096297
4727 11:11:45.096379 RX Vref 0 -> 0, step: 1
4728 11:11:45.096440
4729 11:11:45.099512 RX Delay -163 -> 252, step: 8
4730 11:11:45.106619 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4731 11:11:45.110605 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4732 11:11:45.113744 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4733 11:11:45.117249 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4734 11:11:45.120222 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4735 11:11:45.127073 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4736 11:11:45.129945 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4737 11:11:45.133675 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4738 11:11:45.136962 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4739 11:11:45.140124 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4740 11:11:45.146595 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4741 11:11:45.149868 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4742 11:11:45.153710 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4743 11:11:45.156953 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4744 11:11:45.163869 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4745 11:11:45.167100 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4746 11:11:45.167224 ==
4747 11:11:45.170189 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 11:11:45.173644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 11:11:45.173765 ==
4750 11:11:45.177184 DQS Delay:
4751 11:11:45.177307 DQS0 = 0, DQS1 = 0
4752 11:11:45.177420 DQM Delay:
4753 11:11:45.180258 DQM0 = 48, DQM1 = 45
4754 11:11:45.180385 DQ Delay:
4755 11:11:45.183414 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4756 11:11:45.186930 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4757 11:11:45.190093 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4758 11:11:45.193243 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4759 11:11:45.193324
4760 11:11:45.193388
4761 11:11:45.203247 [DQSOSCAuto] RK1, (LSB)MR18= 0x651d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4762 11:11:45.203330 CH1 RK1: MR19=808, MR18=651D
4763 11:11:45.209996 CH1_RK1: MR19=0x808, MR18=0x651D, DQSOSC=390, MR23=63, INC=172, DEC=114
4764 11:11:45.213645 [RxdqsGatingPostProcess] freq 600
4765 11:11:45.219988 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4766 11:11:45.223496 Pre-setting of DQS Precalculation
4767 11:11:45.226759 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4768 11:11:45.233673 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4769 11:11:45.243143 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4770 11:11:45.243226
4771 11:11:45.243290
4772 11:11:45.246471 [Calibration Summary] 1200 Mbps
4773 11:11:45.246604 CH 0, Rank 0
4774 11:11:45.250027 SW Impedance : PASS
4775 11:11:45.250123 DUTY Scan : NO K
4776 11:11:45.253189 ZQ Calibration : PASS
4777 11:11:45.253271 Jitter Meter : NO K
4778 11:11:45.256208 CBT Training : PASS
4779 11:11:45.260016 Write leveling : PASS
4780 11:11:45.260130 RX DQS gating : PASS
4781 11:11:45.263209 RX DQ/DQS(RDDQC) : PASS
4782 11:11:45.266883 TX DQ/DQS : PASS
4783 11:11:45.266964 RX DATLAT : PASS
4784 11:11:45.270061 RX DQ/DQS(Engine): PASS
4785 11:11:45.273346 TX OE : NO K
4786 11:11:45.273427 All Pass.
4787 11:11:45.273492
4788 11:11:45.273551 CH 0, Rank 1
4789 11:11:45.276283 SW Impedance : PASS
4790 11:11:45.280073 DUTY Scan : NO K
4791 11:11:45.280186 ZQ Calibration : PASS
4792 11:11:45.283101 Jitter Meter : NO K
4793 11:11:45.286815 CBT Training : PASS
4794 11:11:45.286896 Write leveling : PASS
4795 11:11:45.289825 RX DQS gating : PASS
4796 11:11:45.293428 RX DQ/DQS(RDDQC) : PASS
4797 11:11:45.293509 TX DQ/DQS : PASS
4798 11:11:45.296432 RX DATLAT : PASS
4799 11:11:45.296541 RX DQ/DQS(Engine): PASS
4800 11:11:45.300047 TX OE : NO K
4801 11:11:45.300127 All Pass.
4802 11:11:45.300192
4803 11:11:45.303192 CH 1, Rank 0
4804 11:11:45.303273 SW Impedance : PASS
4805 11:11:45.306453 DUTY Scan : NO K
4806 11:11:45.309726 ZQ Calibration : PASS
4807 11:11:45.309808 Jitter Meter : NO K
4808 11:11:45.313335 CBT Training : PASS
4809 11:11:45.316439 Write leveling : PASS
4810 11:11:45.316521 RX DQS gating : PASS
4811 11:11:45.319987 RX DQ/DQS(RDDQC) : PASS
4812 11:11:45.322850 TX DQ/DQS : PASS
4813 11:11:45.322928 RX DATLAT : PASS
4814 11:11:45.326171 RX DQ/DQS(Engine): PASS
4815 11:11:45.329945 TX OE : NO K
4816 11:11:45.330027 All Pass.
4817 11:11:45.330091
4818 11:11:45.330150 CH 1, Rank 1
4819 11:11:45.333461 SW Impedance : PASS
4820 11:11:45.336709 DUTY Scan : NO K
4821 11:11:45.336790 ZQ Calibration : PASS
4822 11:11:45.339884 Jitter Meter : NO K
4823 11:11:45.343108 CBT Training : PASS
4824 11:11:45.343190 Write leveling : PASS
4825 11:11:45.346686 RX DQS gating : PASS
4826 11:11:45.346767 RX DQ/DQS(RDDQC) : PASS
4827 11:11:45.349773 TX DQ/DQS : PASS
4828 11:11:45.353388 RX DATLAT : PASS
4829 11:11:45.353470 RX DQ/DQS(Engine): PASS
4830 11:11:45.356553 TX OE : NO K
4831 11:11:45.356638 All Pass.
4832 11:11:45.356739
4833 11:11:45.360011 DramC Write-DBI off
4834 11:11:45.363248 PER_BANK_REFRESH: Hybrid Mode
4835 11:11:45.363332 TX_TRACKING: ON
4836 11:11:45.372764 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4837 11:11:45.376249 [FAST_K] Save calibration result to emmc
4838 11:11:45.379323 dramc_set_vcore_voltage set vcore to 662500
4839 11:11:45.383052 Read voltage for 933, 3
4840 11:11:45.383133 Vio18 = 0
4841 11:11:45.383197 Vcore = 662500
4842 11:11:45.385937 Vdram = 0
4843 11:11:45.386017 Vddq = 0
4844 11:11:45.386081 Vmddr = 0
4845 11:11:45.392568 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4846 11:11:45.396214 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4847 11:11:45.399360 MEM_TYPE=3, freq_sel=17
4848 11:11:45.402788 sv_algorithm_assistance_LP4_1600
4849 11:11:45.406189 ============ PULL DRAM RESETB DOWN ============
4850 11:11:45.409298 ========== PULL DRAM RESETB DOWN end =========
4851 11:11:45.416134 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4852 11:11:45.419131 ===================================
4853 11:11:45.422799 LPDDR4 DRAM CONFIGURATION
4854 11:11:45.426506 ===================================
4855 11:11:45.426588 EX_ROW_EN[0] = 0x0
4856 11:11:45.429438 EX_ROW_EN[1] = 0x0
4857 11:11:45.429519 LP4Y_EN = 0x0
4858 11:11:45.433159 WORK_FSP = 0x0
4859 11:11:45.433241 WL = 0x3
4860 11:11:45.436157 RL = 0x3
4861 11:11:45.436238 BL = 0x2
4862 11:11:45.439750 RPST = 0x0
4863 11:11:45.439831 RD_PRE = 0x0
4864 11:11:45.442938 WR_PRE = 0x1
4865 11:11:45.443019 WR_PST = 0x0
4866 11:11:45.446090 DBI_WR = 0x0
4867 11:11:45.446171 DBI_RD = 0x0
4868 11:11:45.449810 OTF = 0x1
4869 11:11:45.452833 ===================================
4870 11:11:45.456423 ===================================
4871 11:11:45.456504 ANA top config
4872 11:11:45.459467 ===================================
4873 11:11:45.462617 DLL_ASYNC_EN = 0
4874 11:11:45.466418 ALL_SLAVE_EN = 1
4875 11:11:45.469693 NEW_RANK_MODE = 1
4876 11:11:45.469776 DLL_IDLE_MODE = 1
4877 11:11:45.472763 LP45_APHY_COMB_EN = 1
4878 11:11:45.476438 TX_ODT_DIS = 1
4879 11:11:45.479340 NEW_8X_MODE = 1
4880 11:11:45.482615 ===================================
4881 11:11:45.485726 ===================================
4882 11:11:45.488961 data_rate = 1866
4883 11:11:45.489043 CKR = 1
4884 11:11:45.492819 DQ_P2S_RATIO = 8
4885 11:11:45.495977 ===================================
4886 11:11:45.499320 CA_P2S_RATIO = 8
4887 11:11:45.502824 DQ_CA_OPEN = 0
4888 11:11:45.505932 DQ_SEMI_OPEN = 0
4889 11:11:45.509459 CA_SEMI_OPEN = 0
4890 11:11:45.509542 CA_FULL_RATE = 0
4891 11:11:45.512193 DQ_CKDIV4_EN = 1
4892 11:11:45.515706 CA_CKDIV4_EN = 1
4893 11:11:45.519308 CA_PREDIV_EN = 0
4894 11:11:45.522328 PH8_DLY = 0
4895 11:11:45.526088 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4896 11:11:45.526170 DQ_AAMCK_DIV = 4
4897 11:11:45.529173 CA_AAMCK_DIV = 4
4898 11:11:45.532393 CA_ADMCK_DIV = 4
4899 11:11:45.535941 DQ_TRACK_CA_EN = 0
4900 11:11:45.539091 CA_PICK = 933
4901 11:11:45.542661 CA_MCKIO = 933
4902 11:11:45.542743 MCKIO_SEMI = 0
4903 11:11:45.545647 PLL_FREQ = 3732
4904 11:11:45.548810 DQ_UI_PI_RATIO = 32
4905 11:11:45.552625 CA_UI_PI_RATIO = 0
4906 11:11:45.555831 ===================================
4907 11:11:45.559341 ===================================
4908 11:11:45.562593 memory_type:LPDDR4
4909 11:11:45.562675 GP_NUM : 10
4910 11:11:45.565743 SRAM_EN : 1
4911 11:11:45.568761 MD32_EN : 0
4912 11:11:45.572105 ===================================
4913 11:11:45.572186 [ANA_INIT] >>>>>>>>>>>>>>
4914 11:11:45.575210 <<<<<< [CONFIGURE PHASE]: ANA_TX
4915 11:11:45.579055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4916 11:11:45.582205 ===================================
4917 11:11:45.585296 data_rate = 1866,PCW = 0X8f00
4918 11:11:45.589077 ===================================
4919 11:11:45.592030 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4920 11:11:45.598591 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4921 11:11:45.602063 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4922 11:11:45.608263 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4923 11:11:45.612321 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4924 11:11:45.615153 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4925 11:11:45.618696 [ANA_INIT] flow start
4926 11:11:45.618777 [ANA_INIT] PLL >>>>>>>>
4927 11:11:45.622007 [ANA_INIT] PLL <<<<<<<<
4928 11:11:45.625284 [ANA_INIT] MIDPI >>>>>>>>
4929 11:11:45.625365 [ANA_INIT] MIDPI <<<<<<<<
4930 11:11:45.628326 [ANA_INIT] DLL >>>>>>>>
4931 11:11:45.631966 [ANA_INIT] flow end
4932 11:11:45.634978 ============ LP4 DIFF to SE enter ============
4933 11:11:45.638293 ============ LP4 DIFF to SE exit ============
4934 11:11:45.641733 [ANA_INIT] <<<<<<<<<<<<<
4935 11:11:45.645165 [Flow] Enable top DCM control >>>>>
4936 11:11:45.648169 [Flow] Enable top DCM control <<<<<
4937 11:11:45.651838 Enable DLL master slave shuffle
4938 11:11:45.654725 ==============================================================
4939 11:11:45.658550 Gating Mode config
4940 11:11:45.665262 ==============================================================
4941 11:11:45.665344 Config description:
4942 11:11:45.675265 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4943 11:11:45.681608 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4944 11:11:45.684750 SELPH_MODE 0: By rank 1: By Phase
4945 11:11:45.691610 ==============================================================
4946 11:11:45.694611 GAT_TRACK_EN = 1
4947 11:11:45.698199 RX_GATING_MODE = 2
4948 11:11:45.701338 RX_GATING_TRACK_MODE = 2
4949 11:11:45.704987 SELPH_MODE = 1
4950 11:11:45.708032 PICG_EARLY_EN = 1
4951 11:11:45.711883 VALID_LAT_VALUE = 1
4952 11:11:45.715047 ==============================================================
4953 11:11:45.718133 Enter into Gating configuration >>>>
4954 11:11:45.721865 Exit from Gating configuration <<<<
4955 11:11:45.725081 Enter into DVFS_PRE_config >>>>>
4956 11:11:45.735087 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4957 11:11:45.737924 Exit from DVFS_PRE_config <<<<<
4958 11:11:45.741404 Enter into PICG configuration >>>>
4959 11:11:45.744674 Exit from PICG configuration <<<<
4960 11:11:45.748272 [RX_INPUT] configuration >>>>>
4961 11:11:45.751529 [RX_INPUT] configuration <<<<<
4962 11:11:45.757899 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4963 11:11:45.761253 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4964 11:11:45.767853 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4965 11:11:45.774974 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4966 11:11:45.781769 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4967 11:11:45.788119 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4968 11:11:45.791280 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4969 11:11:45.794552 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4970 11:11:45.798094 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4971 11:11:45.804968 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4972 11:11:45.808492 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4973 11:11:45.811331 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4974 11:11:45.814509 ===================================
4975 11:11:45.818304 LPDDR4 DRAM CONFIGURATION
4976 11:11:45.821390 ===================================
4977 11:11:45.821498 EX_ROW_EN[0] = 0x0
4978 11:11:45.824406 EX_ROW_EN[1] = 0x0
4979 11:11:45.824504 LP4Y_EN = 0x0
4980 11:11:45.827672 WORK_FSP = 0x0
4981 11:11:45.827766 WL = 0x3
4982 11:11:45.831343 RL = 0x3
4983 11:11:45.834909 BL = 0x2
4984 11:11:45.834990 RPST = 0x0
4985 11:11:45.837775 RD_PRE = 0x0
4986 11:11:45.837856 WR_PRE = 0x1
4987 11:11:45.841144 WR_PST = 0x0
4988 11:11:45.841225 DBI_WR = 0x0
4989 11:11:45.844631 DBI_RD = 0x0
4990 11:11:45.844713 OTF = 0x1
4991 11:11:45.847833 ===================================
4992 11:11:45.851564 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4993 11:11:45.858128 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4994 11:11:45.861716 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4995 11:11:45.864608 ===================================
4996 11:11:45.868083 LPDDR4 DRAM CONFIGURATION
4997 11:11:45.871310 ===================================
4998 11:11:45.871391 EX_ROW_EN[0] = 0x10
4999 11:11:45.874395 EX_ROW_EN[1] = 0x0
5000 11:11:45.874476 LP4Y_EN = 0x0
5001 11:11:45.877890 WORK_FSP = 0x0
5002 11:11:45.877971 WL = 0x3
5003 11:11:45.881310 RL = 0x3
5004 11:11:45.881416 BL = 0x2
5005 11:11:45.884655 RPST = 0x0
5006 11:11:45.884735 RD_PRE = 0x0
5007 11:11:45.887859 WR_PRE = 0x1
5008 11:11:45.887940 WR_PST = 0x0
5009 11:11:45.891400 DBI_WR = 0x0
5010 11:11:45.894425 DBI_RD = 0x0
5011 11:11:45.894506 OTF = 0x1
5012 11:11:45.898286 ===================================
5013 11:11:45.904405 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5014 11:11:45.908060 nWR fixed to 30
5015 11:11:45.911207 [ModeRegInit_LP4] CH0 RK0
5016 11:11:45.911288 [ModeRegInit_LP4] CH0 RK1
5017 11:11:45.914827 [ModeRegInit_LP4] CH1 RK0
5018 11:11:45.918312 [ModeRegInit_LP4] CH1 RK1
5019 11:11:45.918394 match AC timing 9
5020 11:11:45.924460 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5021 11:11:45.928250 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5022 11:11:45.931363 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5023 11:11:45.938227 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5024 11:11:45.941366 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5025 11:11:45.941448 ==
5026 11:11:45.944319 Dram Type= 6, Freq= 0, CH_0, rank 0
5027 11:11:45.947879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5028 11:11:45.947961 ==
5029 11:11:45.954679 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5030 11:11:45.961530 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5031 11:11:45.964529 [CA 0] Center 37 (7~68) winsize 62
5032 11:11:45.967716 [CA 1] Center 37 (7~68) winsize 62
5033 11:11:45.971164 [CA 2] Center 34 (4~65) winsize 62
5034 11:11:45.974638 [CA 3] Center 33 (3~64) winsize 62
5035 11:11:45.981732 [CA 4] Center 33 (3~64) winsize 62
5036 11:11:45.981804 [CA 5] Center 32 (2~62) winsize 61
5037 11:11:45.981866
5038 11:11:45.984759 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5039 11:11:45.984840
5040 11:11:45.987875 [CATrainingPosCal] consider 1 rank data
5041 11:11:45.990816 u2DelayCellTimex100 = 270/100 ps
5042 11:11:45.994474 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5043 11:11:45.997901 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5044 11:11:46.001153 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5045 11:11:46.004499 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5046 11:11:46.007353 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5047 11:11:46.011035 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5048 11:11:46.011106
5049 11:11:46.017464 CA PerBit enable=1, Macro0, CA PI delay=32
5050 11:11:46.017546
5051 11:11:46.020608 [CBTSetCACLKResult] CA Dly = 32
5052 11:11:46.020735 CS Dly: 5 (0~36)
5053 11:11:46.020848 ==
5054 11:11:46.024122 Dram Type= 6, Freq= 0, CH_0, rank 1
5055 11:11:46.027548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5056 11:11:46.027661 ==
5057 11:11:46.033777 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5058 11:11:46.041010 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5059 11:11:46.043984 [CA 0] Center 37 (6~68) winsize 63
5060 11:11:46.047241 [CA 1] Center 37 (7~68) winsize 62
5061 11:11:46.050426 [CA 2] Center 34 (4~65) winsize 62
5062 11:11:46.054102 [CA 3] Center 34 (3~65) winsize 63
5063 11:11:46.057039 [CA 4] Center 33 (3~63) winsize 61
5064 11:11:46.060633 [CA 5] Center 32 (2~62) winsize 61
5065 11:11:46.060717
5066 11:11:46.063984 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5067 11:11:46.064065
5068 11:11:46.067500 [CATrainingPosCal] consider 2 rank data
5069 11:11:46.070426 u2DelayCellTimex100 = 270/100 ps
5070 11:11:46.074072 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5071 11:11:46.077092 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5072 11:11:46.080067 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5073 11:11:46.083718 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5074 11:11:46.090134 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5075 11:11:46.093994 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5076 11:11:46.094117
5077 11:11:46.097121 CA PerBit enable=1, Macro0, CA PI delay=32
5078 11:11:46.097242
5079 11:11:46.100292 [CBTSetCACLKResult] CA Dly = 32
5080 11:11:46.100444 CS Dly: 5 (0~37)
5081 11:11:46.100555
5082 11:11:46.103480 ----->DramcWriteLeveling(PI) begin...
5083 11:11:46.103606 ==
5084 11:11:46.106633 Dram Type= 6, Freq= 0, CH_0, rank 0
5085 11:11:46.113188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5086 11:11:46.113295 ==
5087 11:11:46.116988 Write leveling (Byte 0): 30 => 30
5088 11:11:46.120068 Write leveling (Byte 1): 29 => 29
5089 11:11:46.120189 DramcWriteLeveling(PI) end<-----
5090 11:11:46.120326
5091 11:11:46.123401 ==
5092 11:11:46.126809 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 11:11:46.129632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 11:11:46.129791 ==
5095 11:11:46.133526 [Gating] SW mode calibration
5096 11:11:46.140108 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5097 11:11:46.143085 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5098 11:11:46.150119 0 14 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5099 11:11:46.153216 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 11:11:46.156487 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 11:11:46.163406 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 11:11:46.166437 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 11:11:46.169516 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 11:11:46.176575 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5105 11:11:46.179874 0 14 28 | B1->B0 | 3232 2525 | 1 0 | (1 1) (1 0)
5106 11:11:46.182780 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
5107 11:11:46.189760 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 11:11:46.192942 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 11:11:46.196065 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 11:11:46.202932 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 11:11:46.206135 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 11:11:46.209897 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5113 11:11:46.216404 0 15 28 | B1->B0 | 2626 3c3c | 0 0 | (0 0) (0 0)
5114 11:11:46.219554 1 0 0 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
5115 11:11:46.223268 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 11:11:46.229477 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 11:11:46.232915 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 11:11:46.236484 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 11:11:46.239618 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 11:11:46.246422 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 11:11:46.249376 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5122 11:11:46.252722 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 11:11:46.259245 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 11:11:46.262714 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 11:11:46.265975 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 11:11:46.272924 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 11:11:46.275885 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 11:11:46.279386 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 11:11:46.286341 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 11:11:46.289277 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 11:11:46.292654 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 11:11:46.299416 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 11:11:46.302546 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 11:11:46.306219 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 11:11:46.312662 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 11:11:46.315724 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 11:11:46.319305 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5138 11:11:46.322395 Total UI for P1: 0, mck2ui 16
5139 11:11:46.326230 best dqsien dly found for B0: ( 1, 2, 26)
5140 11:11:46.332542 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5141 11:11:46.335770 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 11:11:46.339335 Total UI for P1: 0, mck2ui 16
5143 11:11:46.342151 best dqsien dly found for B1: ( 1, 2, 30)
5144 11:11:46.345826 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5145 11:11:46.348889 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5146 11:11:46.349012
5147 11:11:46.352662 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5148 11:11:46.355917 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5149 11:11:46.358980 [Gating] SW calibration Done
5150 11:11:46.359099 ==
5151 11:11:46.362088 Dram Type= 6, Freq= 0, CH_0, rank 0
5152 11:11:46.365692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5153 11:11:46.368663 ==
5154 11:11:46.368785 RX Vref Scan: 0
5155 11:11:46.368896
5156 11:11:46.371984 RX Vref 0 -> 0, step: 1
5157 11:11:46.372115
5158 11:11:46.375597 RX Delay -80 -> 252, step: 8
5159 11:11:46.378547 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5160 11:11:46.381963 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5161 11:11:46.385456 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5162 11:11:46.388811 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5163 11:11:46.392045 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5164 11:11:46.399018 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5165 11:11:46.401927 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5166 11:11:46.405348 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5167 11:11:46.408570 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5168 11:11:46.412003 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5169 11:11:46.415293 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5170 11:11:46.422278 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5171 11:11:46.425179 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5172 11:11:46.428480 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5173 11:11:46.432155 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5174 11:11:46.435341 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5175 11:11:46.435464 ==
5176 11:11:46.438489 Dram Type= 6, Freq= 0, CH_0, rank 0
5177 11:11:46.445316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5178 11:11:46.445439 ==
5179 11:11:46.445554 DQS Delay:
5180 11:11:46.448816 DQS0 = 0, DQS1 = 0
5181 11:11:46.448939 DQM Delay:
5182 11:11:46.451933 DQM0 = 104, DQM1 = 95
5183 11:11:46.452054 DQ Delay:
5184 11:11:46.455040 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5185 11:11:46.458868 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5186 11:11:46.461948 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5187 11:11:46.465083 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5188 11:11:46.465205
5189 11:11:46.465318
5190 11:11:46.465425 ==
5191 11:11:46.468236 Dram Type= 6, Freq= 0, CH_0, rank 0
5192 11:11:46.471745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5193 11:11:46.471866 ==
5194 11:11:46.471978
5195 11:11:46.475362
5196 11:11:46.475482 TX Vref Scan disable
5197 11:11:46.478310 == TX Byte 0 ==
5198 11:11:46.481532 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5199 11:11:46.485434 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5200 11:11:46.488473 == TX Byte 1 ==
5201 11:11:46.491520 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5202 11:11:46.495184 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5203 11:11:46.495307 ==
5204 11:11:46.498214 Dram Type= 6, Freq= 0, CH_0, rank 0
5205 11:11:46.505259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5206 11:11:46.505382 ==
5207 11:11:46.505495
5208 11:11:46.505605
5209 11:11:46.505711 TX Vref Scan disable
5210 11:11:46.509071 == TX Byte 0 ==
5211 11:11:46.512511 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5212 11:11:46.515680 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5213 11:11:46.518901 == TX Byte 1 ==
5214 11:11:46.522619 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5215 11:11:46.528842 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5216 11:11:46.528964
5217 11:11:46.529076 [DATLAT]
5218 11:11:46.529188 Freq=933, CH0 RK0
5219 11:11:46.529296
5220 11:11:46.532441 DATLAT Default: 0xd
5221 11:11:46.532564 0, 0xFFFF, sum = 0
5222 11:11:46.535513 1, 0xFFFF, sum = 0
5223 11:11:46.535636 2, 0xFFFF, sum = 0
5224 11:11:46.539011 3, 0xFFFF, sum = 0
5225 11:11:46.542232 4, 0xFFFF, sum = 0
5226 11:11:46.542357 5, 0xFFFF, sum = 0
5227 11:11:46.545404 6, 0xFFFF, sum = 0
5228 11:11:46.545529 7, 0xFFFF, sum = 0
5229 11:11:46.549395 8, 0xFFFF, sum = 0
5230 11:11:46.549522 9, 0xFFFF, sum = 0
5231 11:11:46.552265 10, 0x0, sum = 1
5232 11:11:46.552423 11, 0x0, sum = 2
5233 11:11:46.552538 12, 0x0, sum = 3
5234 11:11:46.555769 13, 0x0, sum = 4
5235 11:11:46.555893 best_step = 11
5236 11:11:46.556006
5237 11:11:46.559309 ==
5238 11:11:46.559433 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 11:11:46.565647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 11:11:46.565772 ==
5241 11:11:46.565886 RX Vref Scan: 1
5242 11:11:46.565998
5243 11:11:46.568802 RX Vref 0 -> 0, step: 1
5244 11:11:46.568921
5245 11:11:46.571982 RX Delay -53 -> 252, step: 4
5246 11:11:46.572101
5247 11:11:46.575846 Set Vref, RX VrefLevel [Byte0]: 55
5248 11:11:46.578725 [Byte1]: 51
5249 11:11:46.578848
5250 11:11:46.582402 Final RX Vref Byte 0 = 55 to rank0
5251 11:11:46.585363 Final RX Vref Byte 1 = 51 to rank0
5252 11:11:46.589146 Final RX Vref Byte 0 = 55 to rank1
5253 11:11:46.592419 Final RX Vref Byte 1 = 51 to rank1==
5254 11:11:46.595635 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 11:11:46.598727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 11:11:46.598851 ==
5257 11:11:46.602493 DQS Delay:
5258 11:11:46.602614 DQS0 = 0, DQS1 = 0
5259 11:11:46.605544 DQM Delay:
5260 11:11:46.605664 DQM0 = 104, DQM1 = 96
5261 11:11:46.605776 DQ Delay:
5262 11:11:46.609163 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5263 11:11:46.612360 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5264 11:11:46.615383 DQ8 =86, DQ9 =86, DQ10 =96, DQ11 =92
5265 11:11:46.622076 DQ12 =100, DQ13 =100, DQ14 =108, DQ15 =102
5266 11:11:46.622216
5267 11:11:46.622329
5268 11:11:46.629088 [DQSOSCAuto] RK0, (LSB)MR18= 0x3028, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5269 11:11:46.632146 CH0 RK0: MR19=505, MR18=3028
5270 11:11:46.638861 CH0_RK0: MR19=0x505, MR18=0x3028, DQSOSC=406, MR23=63, INC=65, DEC=43
5271 11:11:46.638987
5272 11:11:46.642216 ----->DramcWriteLeveling(PI) begin...
5273 11:11:46.642340 ==
5274 11:11:46.645378 Dram Type= 6, Freq= 0, CH_0, rank 1
5275 11:11:46.648561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 11:11:46.648685 ==
5277 11:11:46.652147 Write leveling (Byte 0): 36 => 36
5278 11:11:46.655462 Write leveling (Byte 1): 29 => 29
5279 11:11:46.658443 DramcWriteLeveling(PI) end<-----
5280 11:11:46.658565
5281 11:11:46.658676 ==
5282 11:11:46.662478 Dram Type= 6, Freq= 0, CH_0, rank 1
5283 11:11:46.665475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 11:11:46.665597 ==
5285 11:11:46.669051 [Gating] SW mode calibration
5286 11:11:46.675094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5287 11:11:46.682065 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5288 11:11:46.685245 0 14 0 | B1->B0 | 3333 3232 | 0 0 | (0 0) (0 0)
5289 11:11:46.691608 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5290 11:11:46.695166 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 11:11:46.698400 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 11:11:46.705342 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 11:11:46.708487 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 11:11:46.711664 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 11:11:46.718639 0 14 28 | B1->B0 | 2c2c 2e2e | 1 1 | (1 1) (1 0)
5296 11:11:46.721511 0 15 0 | B1->B0 | 2626 2727 | 0 0 | (0 0) (1 1)
5297 11:11:46.724743 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5298 11:11:46.728524 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 11:11:46.734851 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 11:11:46.738565 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 11:11:46.741541 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 11:11:46.748692 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5303 11:11:46.751427 0 15 28 | B1->B0 | 4343 3a3a | 0 1 | (0 0) (0 0)
5304 11:11:46.755302 1 0 0 | B1->B0 | 4646 4242 | 0 0 | (0 0) (1 1)
5305 11:11:46.761788 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5306 11:11:46.764622 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 11:11:46.768039 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 11:11:46.774943 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 11:11:46.777942 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 11:11:46.781174 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 11:11:46.788044 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5312 11:11:46.791895 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5313 11:11:46.794834 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 11:11:46.801798 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 11:11:46.805083 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 11:11:46.808173 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 11:11:46.815261 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 11:11:46.818435 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 11:11:46.821542 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 11:11:46.828293 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 11:11:46.831597 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 11:11:46.834786 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 11:11:46.841673 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 11:11:46.844738 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 11:11:46.847722 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 11:11:46.854828 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 11:11:46.858322 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5328 11:11:46.861276 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5329 11:11:46.864633 Total UI for P1: 0, mck2ui 16
5330 11:11:46.867680 best dqsien dly found for B1: ( 1, 2, 30)
5331 11:11:46.871513 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 11:11:46.874451 Total UI for P1: 0, mck2ui 16
5333 11:11:46.878236 best dqsien dly found for B0: ( 1, 2, 30)
5334 11:11:46.881279 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5335 11:11:46.887879 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5336 11:11:46.887961
5337 11:11:46.890785 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5338 11:11:46.894262 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5339 11:11:46.897388 [Gating] SW calibration Done
5340 11:11:46.897469 ==
5341 11:11:46.901163 Dram Type= 6, Freq= 0, CH_0, rank 1
5342 11:11:46.904007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 11:11:46.904089 ==
5344 11:11:46.907511 RX Vref Scan: 0
5345 11:11:46.907592
5346 11:11:46.907656 RX Vref 0 -> 0, step: 1
5347 11:11:46.907716
5348 11:11:46.911326 RX Delay -80 -> 252, step: 8
5349 11:11:46.914173 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5350 11:11:46.921071 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5351 11:11:46.924054 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5352 11:11:46.927787 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5353 11:11:46.930881 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5354 11:11:46.934073 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5355 11:11:46.937792 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5356 11:11:46.944002 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5357 11:11:46.947221 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5358 11:11:46.950564 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5359 11:11:46.954144 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5360 11:11:46.957342 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5361 11:11:46.961002 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5362 11:11:46.967533 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5363 11:11:46.970963 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5364 11:11:46.974179 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5365 11:11:46.974262 ==
5366 11:11:46.977222 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 11:11:46.980824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 11:11:46.980932 ==
5369 11:11:46.983875 DQS Delay:
5370 11:11:46.983957 DQS0 = 0, DQS1 = 0
5371 11:11:46.984021 DQM Delay:
5372 11:11:46.987627 DQM0 = 105, DQM1 = 93
5373 11:11:46.987709 DQ Delay:
5374 11:11:46.990723 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =103
5375 11:11:46.993895 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5376 11:11:46.997012 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5377 11:11:47.003975 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5378 11:11:47.004057
5379 11:11:47.004121
5380 11:11:47.004180 ==
5381 11:11:47.007455 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 11:11:47.010701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 11:11:47.010879 ==
5384 11:11:47.010967
5385 11:11:47.011027
5386 11:11:47.013725 TX Vref Scan disable
5387 11:11:47.013807 == TX Byte 0 ==
5388 11:11:47.020694 Update DQ dly =721 (2 ,6, 17) DQ OEN =(2 ,3)
5389 11:11:47.023642 Update DQM dly =721 (2 ,6, 17) DQM OEN =(2 ,3)
5390 11:11:47.023724 == TX Byte 1 ==
5391 11:11:47.030447 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5392 11:11:47.033730 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5393 11:11:47.033812 ==
5394 11:11:47.037182 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 11:11:47.040412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 11:11:47.040543 ==
5397 11:11:47.040623
5398 11:11:47.040682
5399 11:11:47.043902 TX Vref Scan disable
5400 11:11:47.047312 == TX Byte 0 ==
5401 11:11:47.050353 Update DQ dly =720 (2 ,6, 16) DQ OEN =(2 ,3)
5402 11:11:47.053657 Update DQM dly =720 (2 ,6, 16) DQM OEN =(2 ,3)
5403 11:11:47.057380 == TX Byte 1 ==
5404 11:11:47.060423 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5405 11:11:47.063572 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5406 11:11:47.063655
5407 11:11:47.067180 [DATLAT]
5408 11:11:47.067262 Freq=933, CH0 RK1
5409 11:11:47.067327
5410 11:11:47.070177 DATLAT Default: 0xb
5411 11:11:47.070259 0, 0xFFFF, sum = 0
5412 11:11:47.073721 1, 0xFFFF, sum = 0
5413 11:11:47.073805 2, 0xFFFF, sum = 0
5414 11:11:47.077000 3, 0xFFFF, sum = 0
5415 11:11:47.077084 4, 0xFFFF, sum = 0
5416 11:11:47.080450 5, 0xFFFF, sum = 0
5417 11:11:47.080560 6, 0xFFFF, sum = 0
5418 11:11:47.083519 7, 0xFFFF, sum = 0
5419 11:11:47.083602 8, 0xFFFF, sum = 0
5420 11:11:47.087326 9, 0xFFFF, sum = 0
5421 11:11:47.087409 10, 0x0, sum = 1
5422 11:11:47.090531 11, 0x0, sum = 2
5423 11:11:47.090614 12, 0x0, sum = 3
5424 11:11:47.093671 13, 0x0, sum = 4
5425 11:11:47.093754 best_step = 11
5426 11:11:47.093819
5427 11:11:47.093879 ==
5428 11:11:47.097292 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 11:11:47.103503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 11:11:47.103589 ==
5431 11:11:47.103654 RX Vref Scan: 0
5432 11:11:47.103713
5433 11:11:47.106711 RX Vref 0 -> 0, step: 1
5434 11:11:47.106793
5435 11:11:47.110086 RX Delay -53 -> 252, step: 4
5436 11:11:47.113774 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5437 11:11:47.117284 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5438 11:11:47.123669 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5439 11:11:47.127380 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5440 11:11:47.130691 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5441 11:11:47.133686 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5442 11:11:47.136892 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5443 11:11:47.143768 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5444 11:11:47.146742 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5445 11:11:47.150346 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5446 11:11:47.153847 iDelay=199, Bit 10, Center 96 (15 ~ 178) 164
5447 11:11:47.156869 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5448 11:11:47.160709 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5449 11:11:47.166757 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5450 11:11:47.169978 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5451 11:11:47.173633 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5452 11:11:47.173747 ==
5453 11:11:47.176724 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 11:11:47.179836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 11:11:47.183427 ==
5456 11:11:47.183508 DQS Delay:
5457 11:11:47.183572 DQS0 = 0, DQS1 = 0
5458 11:11:47.186964 DQM Delay:
5459 11:11:47.187071 DQM0 = 104, DQM1 = 95
5460 11:11:47.189839 DQ Delay:
5461 11:11:47.193572 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5462 11:11:47.196583 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5463 11:11:47.199873 DQ8 =88, DQ9 =86, DQ10 =96, DQ11 =88
5464 11:11:47.203584 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102
5465 11:11:47.203665
5466 11:11:47.203729
5467 11:11:47.209847 [DQSOSCAuto] RK1, (LSB)MR18= 0x2600, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5468 11:11:47.213757 CH0 RK1: MR19=505, MR18=2600
5469 11:11:47.219937 CH0_RK1: MR19=0x505, MR18=0x2600, DQSOSC=409, MR23=63, INC=64, DEC=43
5470 11:11:47.223690 [RxdqsGatingPostProcess] freq 933
5471 11:11:47.226595 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5472 11:11:47.229812 best DQS0 dly(2T, 0.5T) = (0, 10)
5473 11:11:47.233461 best DQS1 dly(2T, 0.5T) = (0, 10)
5474 11:11:47.236570 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5475 11:11:47.240252 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5476 11:11:47.243576 best DQS0 dly(2T, 0.5T) = (0, 10)
5477 11:11:47.246793 best DQS1 dly(2T, 0.5T) = (0, 10)
5478 11:11:47.249858 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5479 11:11:47.253105 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5480 11:11:47.256770 Pre-setting of DQS Precalculation
5481 11:11:47.259768 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5482 11:11:47.263469 ==
5483 11:11:47.263592 Dram Type= 6, Freq= 0, CH_1, rank 0
5484 11:11:47.270055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 11:11:47.270178 ==
5486 11:11:47.272953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5487 11:11:47.279607 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5488 11:11:47.283467 [CA 0] Center 36 (6~67) winsize 62
5489 11:11:47.286570 [CA 1] Center 36 (6~67) winsize 62
5490 11:11:47.290156 [CA 2] Center 35 (5~65) winsize 61
5491 11:11:47.293193 [CA 3] Center 34 (4~65) winsize 62
5492 11:11:47.296234 [CA 4] Center 34 (4~64) winsize 61
5493 11:11:47.299902 [CA 5] Center 33 (3~64) winsize 62
5494 11:11:47.300025
5495 11:11:47.303423 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5496 11:11:47.303545
5497 11:11:47.306223 [CATrainingPosCal] consider 1 rank data
5498 11:11:47.310044 u2DelayCellTimex100 = 270/100 ps
5499 11:11:47.312997 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5500 11:11:47.319759 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5501 11:11:47.322963 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5502 11:11:47.326232 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5503 11:11:47.330014 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5504 11:11:47.332900 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5505 11:11:47.333006
5506 11:11:47.336315 CA PerBit enable=1, Macro0, CA PI delay=33
5507 11:11:47.336429
5508 11:11:47.339892 [CBTSetCACLKResult] CA Dly = 33
5509 11:11:47.342753 CS Dly: 6 (0~37)
5510 11:11:47.342834 ==
5511 11:11:47.346520 Dram Type= 6, Freq= 0, CH_1, rank 1
5512 11:11:47.349738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 11:11:47.349819 ==
5514 11:11:47.352891 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5515 11:11:47.359363 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5516 11:11:47.363512 [CA 0] Center 36 (6~67) winsize 62
5517 11:11:47.366639 [CA 1] Center 37 (6~68) winsize 63
5518 11:11:47.370439 [CA 2] Center 34 (4~65) winsize 62
5519 11:11:47.373568 [CA 3] Center 34 (4~65) winsize 62
5520 11:11:47.377162 [CA 4] Center 34 (4~65) winsize 62
5521 11:11:47.380413 [CA 5] Center 34 (4~64) winsize 61
5522 11:11:47.380534
5523 11:11:47.383301 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5524 11:11:47.383419
5525 11:11:47.386774 [CATrainingPosCal] consider 2 rank data
5526 11:11:47.389953 u2DelayCellTimex100 = 270/100 ps
5527 11:11:47.393617 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5528 11:11:47.396586 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5529 11:11:47.403324 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5530 11:11:47.406604 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5531 11:11:47.409797 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5532 11:11:47.413370 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5533 11:11:47.413455
5534 11:11:47.416802 CA PerBit enable=1, Macro0, CA PI delay=34
5535 11:11:47.416905
5536 11:11:47.419939 [CBTSetCACLKResult] CA Dly = 34
5537 11:11:47.420037 CS Dly: 7 (0~39)
5538 11:11:47.420132
5539 11:11:47.423205 ----->DramcWriteLeveling(PI) begin...
5540 11:11:47.426511 ==
5541 11:11:47.429661 Dram Type= 6, Freq= 0, CH_1, rank 0
5542 11:11:47.433384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 11:11:47.433482 ==
5544 11:11:47.436650 Write leveling (Byte 0): 27 => 27
5545 11:11:47.439818 Write leveling (Byte 1): 27 => 27
5546 11:11:47.443302 DramcWriteLeveling(PI) end<-----
5547 11:11:47.443451
5548 11:11:47.443535 ==
5549 11:11:47.446284 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 11:11:47.449894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 11:11:47.449977 ==
5552 11:11:47.452890 [Gating] SW mode calibration
5553 11:11:47.459668 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5554 11:11:47.466617 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5555 11:11:47.469620 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 11:11:47.473419 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 11:11:47.479718 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 11:11:47.483094 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 11:11:47.486228 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 11:11:47.489724 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 11:11:47.496384 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 1)
5562 11:11:47.499637 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5563 11:11:47.502671 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 11:11:47.509520 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 11:11:47.512659 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 11:11:47.516124 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 11:11:47.522567 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 11:11:47.525958 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 11:11:47.529475 0 15 24 | B1->B0 | 2626 3333 | 1 0 | (0 0) (0 0)
5570 11:11:47.535857 0 15 28 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5571 11:11:47.539915 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 11:11:47.542747 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 11:11:47.549710 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 11:11:47.552743 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 11:11:47.555784 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 11:11:47.562665 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 11:11:47.565781 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5578 11:11:47.569467 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 11:11:47.576113 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 11:11:47.579359 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 11:11:47.582547 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 11:11:47.589335 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 11:11:47.592396 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 11:11:47.596107 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 11:11:47.602582 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 11:11:47.606012 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 11:11:47.609258 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 11:11:47.615575 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 11:11:47.619288 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 11:11:47.622428 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 11:11:47.628932 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 11:11:47.632223 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 11:11:47.635734 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5594 11:11:47.638821 Total UI for P1: 0, mck2ui 16
5595 11:11:47.642031 best dqsien dly found for B0: ( 1, 2, 22)
5596 11:11:47.645608 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 11:11:47.649071 Total UI for P1: 0, mck2ui 16
5598 11:11:47.652513 best dqsien dly found for B1: ( 1, 2, 24)
5599 11:11:47.655651 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5600 11:11:47.662264 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5601 11:11:47.662348
5602 11:11:47.665722 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5603 11:11:47.668955 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5604 11:11:47.672133 [Gating] SW calibration Done
5605 11:11:47.672215 ==
5606 11:11:47.675706 Dram Type= 6, Freq= 0, CH_1, rank 0
5607 11:11:47.678789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5608 11:11:47.678873 ==
5609 11:11:47.682026 RX Vref Scan: 0
5610 11:11:47.682109
5611 11:11:47.682173 RX Vref 0 -> 0, step: 1
5612 11:11:47.682232
5613 11:11:47.685023 RX Delay -80 -> 252, step: 8
5614 11:11:47.688730 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5615 11:11:47.691749 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5616 11:11:47.698620 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5617 11:11:47.701653 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5618 11:11:47.705491 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5619 11:11:47.708452 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5620 11:11:47.712115 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5621 11:11:47.714979 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5622 11:11:47.721734 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5623 11:11:47.725001 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5624 11:11:47.728593 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5625 11:11:47.731688 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5626 11:11:47.735407 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5627 11:11:47.741405 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5628 11:11:47.744860 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5629 11:11:47.748158 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5630 11:11:47.748241 ==
5631 11:11:47.751795 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 11:11:47.755318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 11:11:47.755402 ==
5634 11:11:47.758327 DQS Delay:
5635 11:11:47.758409 DQS0 = 0, DQS1 = 0
5636 11:11:47.758474 DQM Delay:
5637 11:11:47.761569 DQM0 = 103, DQM1 = 98
5638 11:11:47.761651 DQ Delay:
5639 11:11:47.765058 DQ0 =111, DQ1 =95, DQ2 =91, DQ3 =99
5640 11:11:47.768205 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5641 11:11:47.771013 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5642 11:11:47.777842 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5643 11:11:47.777926
5644 11:11:47.777990
5645 11:11:47.778050 ==
5646 11:11:47.781521 Dram Type= 6, Freq= 0, CH_1, rank 0
5647 11:11:47.784296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5648 11:11:47.784394 ==
5649 11:11:47.784458
5650 11:11:47.784518
5651 11:11:47.787640 TX Vref Scan disable
5652 11:11:47.787723 == TX Byte 0 ==
5653 11:11:47.794625 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5654 11:11:47.797506 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5655 11:11:47.797589 == TX Byte 1 ==
5656 11:11:47.804481 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5657 11:11:47.807501 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5658 11:11:47.807587 ==
5659 11:11:47.811320 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 11:11:47.814461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 11:11:47.814544 ==
5662 11:11:47.814608
5663 11:11:47.814667
5664 11:11:47.817515 TX Vref Scan disable
5665 11:11:47.820952 == TX Byte 0 ==
5666 11:11:47.824197 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5667 11:11:47.827973 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5668 11:11:47.831222 == TX Byte 1 ==
5669 11:11:47.834379 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5670 11:11:47.837547 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5671 11:11:47.837630
5672 11:11:47.841361 [DATLAT]
5673 11:11:47.841443 Freq=933, CH1 RK0
5674 11:11:47.841507
5675 11:11:47.844565 DATLAT Default: 0xd
5676 11:11:47.844647 0, 0xFFFF, sum = 0
5677 11:11:47.847503 1, 0xFFFF, sum = 0
5678 11:11:47.847586 2, 0xFFFF, sum = 0
5679 11:11:47.850927 3, 0xFFFF, sum = 0
5680 11:11:47.851012 4, 0xFFFF, sum = 0
5681 11:11:47.854585 5, 0xFFFF, sum = 0
5682 11:11:47.854668 6, 0xFFFF, sum = 0
5683 11:11:47.857560 7, 0xFFFF, sum = 0
5684 11:11:47.857643 8, 0xFFFF, sum = 0
5685 11:11:47.860733 9, 0xFFFF, sum = 0
5686 11:11:47.860816 10, 0x0, sum = 1
5687 11:11:47.864223 11, 0x0, sum = 2
5688 11:11:47.864344 12, 0x0, sum = 3
5689 11:11:47.867827 13, 0x0, sum = 4
5690 11:11:47.867910 best_step = 11
5691 11:11:47.867974
5692 11:11:47.868034 ==
5693 11:11:47.870750 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 11:11:47.877332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 11:11:47.877448 ==
5696 11:11:47.877513 RX Vref Scan: 1
5697 11:11:47.877573
5698 11:11:47.880682 RX Vref 0 -> 0, step: 1
5699 11:11:47.880765
5700 11:11:47.883943 RX Delay -45 -> 252, step: 4
5701 11:11:47.884025
5702 11:11:47.887210 Set Vref, RX VrefLevel [Byte0]: 55
5703 11:11:47.890551 [Byte1]: 55
5704 11:11:47.890633
5705 11:11:47.894304 Final RX Vref Byte 0 = 55 to rank0
5706 11:11:47.897468 Final RX Vref Byte 1 = 55 to rank0
5707 11:11:47.900607 Final RX Vref Byte 0 = 55 to rank1
5708 11:11:47.903752 Final RX Vref Byte 1 = 55 to rank1==
5709 11:11:47.907361 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 11:11:47.910273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 11:11:47.910355 ==
5712 11:11:47.914139 DQS Delay:
5713 11:11:47.914221 DQS0 = 0, DQS1 = 0
5714 11:11:47.914286 DQM Delay:
5715 11:11:47.917292 DQM0 = 103, DQM1 = 99
5716 11:11:47.917374 DQ Delay:
5717 11:11:47.920456 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5718 11:11:47.923650 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =104
5719 11:11:47.927382 DQ8 =88, DQ9 =90, DQ10 =102, DQ11 =94
5720 11:11:47.933873 DQ12 =104, DQ13 =106, DQ14 =106, DQ15 =106
5721 11:11:47.933956
5722 11:11:47.934020
5723 11:11:47.940193 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5724 11:11:47.943978 CH1 RK0: MR19=505, MR18=1B32
5725 11:11:47.950220 CH1_RK0: MR19=0x505, MR18=0x1B32, DQSOSC=406, MR23=63, INC=65, DEC=43
5726 11:11:47.950303
5727 11:11:47.953879 ----->DramcWriteLeveling(PI) begin...
5728 11:11:47.953962 ==
5729 11:11:47.956930 Dram Type= 6, Freq= 0, CH_1, rank 1
5730 11:11:47.960599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 11:11:47.960682 ==
5732 11:11:47.963642 Write leveling (Byte 0): 29 => 29
5733 11:11:47.967061 Write leveling (Byte 1): 30 => 30
5734 11:11:47.970379 DramcWriteLeveling(PI) end<-----
5735 11:11:47.970461
5736 11:11:47.970526 ==
5737 11:11:47.973671 Dram Type= 6, Freq= 0, CH_1, rank 1
5738 11:11:47.977077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 11:11:47.977161 ==
5740 11:11:47.979997 [Gating] SW mode calibration
5741 11:11:47.986768 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5742 11:11:47.993319 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5743 11:11:47.996753 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 11:11:48.003344 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 11:11:48.006704 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 11:11:48.010151 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 11:11:48.016425 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 11:11:48.020168 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5749 11:11:48.023440 0 14 24 | B1->B0 | 2f2f 3131 | 0 1 | (1 0) (1 0)
5750 11:11:48.026587 0 14 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5751 11:11:48.033343 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 11:11:48.036265 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 11:11:48.039699 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 11:11:48.046672 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 11:11:48.049754 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 11:11:48.053034 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 11:11:48.059864 0 15 24 | B1->B0 | 3535 2d2d | 0 0 | (0 0) (0 0)
5758 11:11:48.062896 0 15 28 | B1->B0 | 4646 3d3d | 0 0 | (0 0) (0 0)
5759 11:11:48.066557 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 11:11:48.072863 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 11:11:48.076505 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 11:11:48.079459 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 11:11:48.086538 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 11:11:48.089719 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 11:11:48.093023 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 11:11:48.099736 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5767 11:11:48.102772 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 11:11:48.105882 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 11:11:48.112860 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 11:11:48.116198 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 11:11:48.119581 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 11:11:48.126313 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 11:11:48.129600 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 11:11:48.133123 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 11:11:48.139277 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 11:11:48.142990 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 11:11:48.146047 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 11:11:48.153010 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 11:11:48.156095 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 11:11:48.159148 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 11:11:48.166053 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5782 11:11:48.169053 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 11:11:48.172765 Total UI for P1: 0, mck2ui 16
5784 11:11:48.176022 best dqsien dly found for B0: ( 1, 2, 24)
5785 11:11:48.179229 Total UI for P1: 0, mck2ui 16
5786 11:11:48.182305 best dqsien dly found for B1: ( 1, 2, 24)
5787 11:11:48.186076 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5788 11:11:48.189222 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5789 11:11:48.189304
5790 11:11:48.192801 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5791 11:11:48.196266 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5792 11:11:48.199384 [Gating] SW calibration Done
5793 11:11:48.199466 ==
5794 11:11:48.202538 Dram Type= 6, Freq= 0, CH_1, rank 1
5795 11:11:48.205697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5796 11:11:48.205785 ==
5797 11:11:48.209520 RX Vref Scan: 0
5798 11:11:48.209602
5799 11:11:48.209666 RX Vref 0 -> 0, step: 1
5800 11:11:48.212968
5801 11:11:48.213048 RX Delay -80 -> 252, step: 8
5802 11:11:48.219625 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5803 11:11:48.222844 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5804 11:11:48.225850 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5805 11:11:48.228999 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5806 11:11:48.232663 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5807 11:11:48.236021 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5808 11:11:48.242401 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5809 11:11:48.245890 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5810 11:11:48.249299 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5811 11:11:48.252446 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5812 11:11:48.256242 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5813 11:11:48.259003 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5814 11:11:48.265877 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5815 11:11:48.269097 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5816 11:11:48.272573 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5817 11:11:48.275837 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5818 11:11:48.275910 ==
5819 11:11:48.279013 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 11:11:48.282655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 11:11:48.285755 ==
5822 11:11:48.285837 DQS Delay:
5823 11:11:48.285902 DQS0 = 0, DQS1 = 0
5824 11:11:48.288949 DQM Delay:
5825 11:11:48.289031 DQM0 = 102, DQM1 = 98
5826 11:11:48.292152 DQ Delay:
5827 11:11:48.295942 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5828 11:11:48.299060 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5829 11:11:48.302332 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5830 11:11:48.305425 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5831 11:11:48.305513
5832 11:11:48.305578
5833 11:11:48.305638 ==
5834 11:11:48.309028 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 11:11:48.311938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 11:11:48.312021 ==
5837 11:11:48.312086
5838 11:11:48.312146
5839 11:11:48.315383 TX Vref Scan disable
5840 11:11:48.315465 == TX Byte 0 ==
5841 11:11:48.322017 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5842 11:11:48.325282 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5843 11:11:48.325365 == TX Byte 1 ==
5844 11:11:48.332182 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5845 11:11:48.335232 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5846 11:11:48.335316 ==
5847 11:11:48.338864 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 11:11:48.342113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 11:11:48.342195 ==
5850 11:11:48.342264
5851 11:11:48.345293
5852 11:11:48.345375 TX Vref Scan disable
5853 11:11:48.348830 == TX Byte 0 ==
5854 11:11:48.352153 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5855 11:11:48.355173 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5856 11:11:48.358853 == TX Byte 1 ==
5857 11:11:48.362274 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5858 11:11:48.365670 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5859 11:11:48.368654
5860 11:11:48.368735 [DATLAT]
5861 11:11:48.368801 Freq=933, CH1 RK1
5862 11:11:48.368862
5863 11:11:48.371834 DATLAT Default: 0xb
5864 11:11:48.371950 0, 0xFFFF, sum = 0
5865 11:11:48.375225 1, 0xFFFF, sum = 0
5866 11:11:48.375309 2, 0xFFFF, sum = 0
5867 11:11:48.378475 3, 0xFFFF, sum = 0
5868 11:11:48.378561 4, 0xFFFF, sum = 0
5869 11:11:48.382134 5, 0xFFFF, sum = 0
5870 11:11:48.385285 6, 0xFFFF, sum = 0
5871 11:11:48.385367 7, 0xFFFF, sum = 0
5872 11:11:48.388466 8, 0xFFFF, sum = 0
5873 11:11:48.388548 9, 0xFFFF, sum = 0
5874 11:11:48.391993 10, 0x0, sum = 1
5875 11:11:48.392100 11, 0x0, sum = 2
5876 11:11:48.392168 12, 0x0, sum = 3
5877 11:11:48.395382 13, 0x0, sum = 4
5878 11:11:48.395464 best_step = 11
5879 11:11:48.395527
5880 11:11:48.398536 ==
5881 11:11:48.398617 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 11:11:48.405498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 11:11:48.405579 ==
5884 11:11:48.405643 RX Vref Scan: 0
5885 11:11:48.405703
5886 11:11:48.408624 RX Vref 0 -> 0, step: 1
5887 11:11:48.408705
5888 11:11:48.411780 RX Delay -45 -> 252, step: 4
5889 11:11:48.415421 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5890 11:11:48.422081 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5891 11:11:48.425027 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5892 11:11:48.428779 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5893 11:11:48.431850 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5894 11:11:48.435312 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5895 11:11:48.438362 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5896 11:11:48.445438 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5897 11:11:48.448695 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5898 11:11:48.451606 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5899 11:11:48.455243 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5900 11:11:48.458156 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5901 11:11:48.464732 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5902 11:11:48.468627 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5903 11:11:48.471547 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5904 11:11:48.475161 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5905 11:11:48.475263 ==
5906 11:11:48.478198 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 11:11:48.484722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 11:11:48.484804 ==
5909 11:11:48.484868 DQS Delay:
5910 11:11:48.488087 DQS0 = 0, DQS1 = 0
5911 11:11:48.488201 DQM Delay:
5912 11:11:48.488315 DQM0 = 105, DQM1 = 100
5913 11:11:48.491491 DQ Delay:
5914 11:11:48.495167 DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =100
5915 11:11:48.498223 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5916 11:11:48.501427 DQ8 =92, DQ9 =90, DQ10 =100, DQ11 =94
5917 11:11:48.505208 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5918 11:11:48.505336
5919 11:11:48.505407
5920 11:11:48.511656 [DQSOSCAuto] RK1, (LSB)MR18= 0x2afe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5921 11:11:48.514660 CH1 RK1: MR19=504, MR18=2AFE
5922 11:11:48.521473 CH1_RK1: MR19=0x504, MR18=0x2AFE, DQSOSC=408, MR23=63, INC=65, DEC=43
5923 11:11:48.525205 [RxdqsGatingPostProcess] freq 933
5924 11:11:48.531735 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5925 11:11:48.534810 best DQS0 dly(2T, 0.5T) = (0, 10)
5926 11:11:48.534909 best DQS1 dly(2T, 0.5T) = (0, 10)
5927 11:11:48.538075 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5928 11:11:48.541786 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5929 11:11:48.544774 best DQS0 dly(2T, 0.5T) = (0, 10)
5930 11:11:48.548507 best DQS1 dly(2T, 0.5T) = (0, 10)
5931 11:11:48.552015 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5932 11:11:48.554751 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5933 11:11:48.558295 Pre-setting of DQS Precalculation
5934 11:11:48.565218 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5935 11:11:48.571656 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5936 11:11:48.578464 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5937 11:11:48.578579
5938 11:11:48.578647
5939 11:11:48.581590 [Calibration Summary] 1866 Mbps
5940 11:11:48.581674 CH 0, Rank 0
5941 11:11:48.584827 SW Impedance : PASS
5942 11:11:48.588489 DUTY Scan : NO K
5943 11:11:48.588572 ZQ Calibration : PASS
5944 11:11:48.591427 Jitter Meter : NO K
5945 11:11:48.594825 CBT Training : PASS
5946 11:11:48.594908 Write leveling : PASS
5947 11:11:48.598393 RX DQS gating : PASS
5948 11:11:48.601148 RX DQ/DQS(RDDQC) : PASS
5949 11:11:48.601230 TX DQ/DQS : PASS
5950 11:11:48.604514 RX DATLAT : PASS
5951 11:11:48.604596 RX DQ/DQS(Engine): PASS
5952 11:11:48.608089 TX OE : NO K
5953 11:11:48.608202 All Pass.
5954 11:11:48.608340
5955 11:11:48.611272 CH 0, Rank 1
5956 11:11:48.611380 SW Impedance : PASS
5957 11:11:48.614371 DUTY Scan : NO K
5958 11:11:48.618116 ZQ Calibration : PASS
5959 11:11:48.618199 Jitter Meter : NO K
5960 11:11:48.621178 CBT Training : PASS
5961 11:11:48.624150 Write leveling : PASS
5962 11:11:48.624262 RX DQS gating : PASS
5963 11:11:48.627933 RX DQ/DQS(RDDQC) : PASS
5964 11:11:48.630988 TX DQ/DQS : PASS
5965 11:11:48.631071 RX DATLAT : PASS
5966 11:11:48.634157 RX DQ/DQS(Engine): PASS
5967 11:11:48.637545 TX OE : NO K
5968 11:11:48.637669 All Pass.
5969 11:11:48.637779
5970 11:11:48.637887 CH 1, Rank 0
5971 11:11:48.641044 SW Impedance : PASS
5972 11:11:48.644129 DUTY Scan : NO K
5973 11:11:48.644249 ZQ Calibration : PASS
5974 11:11:48.647338 Jitter Meter : NO K
5975 11:11:48.651387 CBT Training : PASS
5976 11:11:48.651508 Write leveling : PASS
5977 11:11:48.654388 RX DQS gating : PASS
5978 11:11:48.657504 RX DQ/DQS(RDDQC) : PASS
5979 11:11:48.657624 TX DQ/DQS : PASS
5980 11:11:48.660648 RX DATLAT : PASS
5981 11:11:48.664350 RX DQ/DQS(Engine): PASS
5982 11:11:48.664446 TX OE : NO K
5983 11:11:48.664512 All Pass.
5984 11:11:48.667293
5985 11:11:48.667390 CH 1, Rank 1
5986 11:11:48.670675 SW Impedance : PASS
5987 11:11:48.670758 DUTY Scan : NO K
5988 11:11:48.674112 ZQ Calibration : PASS
5989 11:11:48.674221 Jitter Meter : NO K
5990 11:11:48.677370 CBT Training : PASS
5991 11:11:48.680603 Write leveling : PASS
5992 11:11:48.680687 RX DQS gating : PASS
5993 11:11:48.684120 RX DQ/DQS(RDDQC) : PASS
5994 11:11:48.687630 TX DQ/DQS : PASS
5995 11:11:48.687716 RX DATLAT : PASS
5996 11:11:48.690715 RX DQ/DQS(Engine): PASS
5997 11:11:48.693752 TX OE : NO K
5998 11:11:48.693868 All Pass.
5999 11:11:48.693958
6000 11:11:48.697472 DramC Write-DBI off
6001 11:11:48.697570 PER_BANK_REFRESH: Hybrid Mode
6002 11:11:48.700409 TX_TRACKING: ON
6003 11:11:48.707247 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6004 11:11:48.713628 [FAST_K] Save calibration result to emmc
6005 11:11:48.716782 dramc_set_vcore_voltage set vcore to 650000
6006 11:11:48.716886 Read voltage for 400, 6
6007 11:11:48.720013 Vio18 = 0
6008 11:11:48.720113 Vcore = 650000
6009 11:11:48.720204 Vdram = 0
6010 11:11:48.723922 Vddq = 0
6011 11:11:48.724023 Vmddr = 0
6012 11:11:48.727055 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6013 11:11:48.733857 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6014 11:11:48.736999 MEM_TYPE=3, freq_sel=20
6015 11:11:48.740161 sv_algorithm_assistance_LP4_800
6016 11:11:48.743745 ============ PULL DRAM RESETB DOWN ============
6017 11:11:48.746618 ========== PULL DRAM RESETB DOWN end =========
6018 11:11:48.753258 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6019 11:11:48.756930 ===================================
6020 11:11:48.757053 LPDDR4 DRAM CONFIGURATION
6021 11:11:48.759945 ===================================
6022 11:11:48.763704 EX_ROW_EN[0] = 0x0
6023 11:11:48.763806 EX_ROW_EN[1] = 0x0
6024 11:11:48.766796 LP4Y_EN = 0x0
6025 11:11:48.766897 WORK_FSP = 0x0
6026 11:11:48.770035 WL = 0x2
6027 11:11:48.770143 RL = 0x2
6028 11:11:48.773685 BL = 0x2
6029 11:11:48.777028 RPST = 0x0
6030 11:11:48.777106 RD_PRE = 0x0
6031 11:11:48.780113 WR_PRE = 0x1
6032 11:11:48.780226 WR_PST = 0x0
6033 11:11:48.783155 DBI_WR = 0x0
6034 11:11:48.783254 DBI_RD = 0x0
6035 11:11:48.786769 OTF = 0x1
6036 11:11:48.790220 ===================================
6037 11:11:48.793089 ===================================
6038 11:11:48.793165 ANA top config
6039 11:11:48.796520 ===================================
6040 11:11:48.799969 DLL_ASYNC_EN = 0
6041 11:11:48.802978 ALL_SLAVE_EN = 1
6042 11:11:48.803082 NEW_RANK_MODE = 1
6043 11:11:48.806648 DLL_IDLE_MODE = 1
6044 11:11:48.810009 LP45_APHY_COMB_EN = 1
6045 11:11:48.812969 TX_ODT_DIS = 1
6046 11:11:48.813047 NEW_8X_MODE = 1
6047 11:11:48.816618 ===================================
6048 11:11:48.820096 ===================================
6049 11:11:48.822910 data_rate = 800
6050 11:11:48.826548 CKR = 1
6051 11:11:48.829768 DQ_P2S_RATIO = 4
6052 11:11:48.832998 ===================================
6053 11:11:48.836145 CA_P2S_RATIO = 4
6054 11:11:48.839988 DQ_CA_OPEN = 0
6055 11:11:48.840097 DQ_SEMI_OPEN = 1
6056 11:11:48.843080 CA_SEMI_OPEN = 1
6057 11:11:48.846219 CA_FULL_RATE = 0
6058 11:11:48.849508 DQ_CKDIV4_EN = 0
6059 11:11:48.853140 CA_CKDIV4_EN = 1
6060 11:11:48.856203 CA_PREDIV_EN = 0
6061 11:11:48.856307 PH8_DLY = 0
6062 11:11:48.859644 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6063 11:11:48.863106 DQ_AAMCK_DIV = 0
6064 11:11:48.866113 CA_AAMCK_DIV = 0
6065 11:11:48.869796 CA_ADMCK_DIV = 4
6066 11:11:48.872956 DQ_TRACK_CA_EN = 0
6067 11:11:48.873038 CA_PICK = 800
6068 11:11:48.876741 CA_MCKIO = 400
6069 11:11:48.879837 MCKIO_SEMI = 400
6070 11:11:48.883234 PLL_FREQ = 3016
6071 11:11:48.886326 DQ_UI_PI_RATIO = 32
6072 11:11:48.889416 CA_UI_PI_RATIO = 32
6073 11:11:48.893090 ===================================
6074 11:11:48.896153 ===================================
6075 11:11:48.899722 memory_type:LPDDR4
6076 11:11:48.899848 GP_NUM : 10
6077 11:11:48.903044 SRAM_EN : 1
6078 11:11:48.903166 MD32_EN : 0
6079 11:11:48.906145 ===================================
6080 11:11:48.909456 [ANA_INIT] >>>>>>>>>>>>>>
6081 11:11:48.912715 <<<<<< [CONFIGURE PHASE]: ANA_TX
6082 11:11:48.916012 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6083 11:11:48.919667 ===================================
6084 11:11:48.922811 data_rate = 800,PCW = 0X7400
6085 11:11:48.926026 ===================================
6086 11:11:48.929557 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6087 11:11:48.932853 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6088 11:11:48.946222 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6089 11:11:48.949426 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6090 11:11:48.952672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6091 11:11:48.956421 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6092 11:11:48.959588 [ANA_INIT] flow start
6093 11:11:48.962709 [ANA_INIT] PLL >>>>>>>>
6094 11:11:48.962790 [ANA_INIT] PLL <<<<<<<<
6095 11:11:48.966343 [ANA_INIT] MIDPI >>>>>>>>
6096 11:11:48.969447 [ANA_INIT] MIDPI <<<<<<<<
6097 11:11:48.969528 [ANA_INIT] DLL >>>>>>>>
6098 11:11:48.972960 [ANA_INIT] flow end
6099 11:11:48.975737 ============ LP4 DIFF to SE enter ============
6100 11:11:48.982656 ============ LP4 DIFF to SE exit ============
6101 11:11:48.982781 [ANA_INIT] <<<<<<<<<<<<<
6102 11:11:48.985754 [Flow] Enable top DCM control >>>>>
6103 11:11:48.989282 [Flow] Enable top DCM control <<<<<
6104 11:11:48.992512 Enable DLL master slave shuffle
6105 11:11:48.999332 ==============================================================
6106 11:11:48.999459 Gating Mode config
6107 11:11:49.006056 ==============================================================
6108 11:11:49.009124 Config description:
6109 11:11:49.015656 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6110 11:11:49.022629 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6111 11:11:49.029037 SELPH_MODE 0: By rank 1: By Phase
6112 11:11:49.035986 ==============================================================
6113 11:11:49.036069 GAT_TRACK_EN = 0
6114 11:11:49.038980 RX_GATING_MODE = 2
6115 11:11:49.042472 RX_GATING_TRACK_MODE = 2
6116 11:11:49.045387 SELPH_MODE = 1
6117 11:11:49.048965 PICG_EARLY_EN = 1
6118 11:11:49.052281 VALID_LAT_VALUE = 1
6119 11:11:49.059118 ==============================================================
6120 11:11:49.062230 Enter into Gating configuration >>>>
6121 11:11:49.065839 Exit from Gating configuration <<<<
6122 11:11:49.068774 Enter into DVFS_PRE_config >>>>>
6123 11:11:49.078638 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6124 11:11:49.082181 Exit from DVFS_PRE_config <<<<<
6125 11:11:49.085103 Enter into PICG configuration >>>>
6126 11:11:49.088893 Exit from PICG configuration <<<<
6127 11:11:49.091833 [RX_INPUT] configuration >>>>>
6128 11:11:49.095312 [RX_INPUT] configuration <<<<<
6129 11:11:49.098818 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6130 11:11:49.105111 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6131 11:11:49.112020 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6132 11:11:49.115140 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6133 11:11:49.122068 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6134 11:11:49.128593 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6135 11:11:49.132077 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6136 11:11:49.135586 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6137 11:11:49.141584 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6138 11:11:49.144862 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6139 11:11:49.148558 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6140 11:11:49.155126 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6141 11:11:49.158265 ===================================
6142 11:11:49.158349 LPDDR4 DRAM CONFIGURATION
6143 11:11:49.161414 ===================================
6144 11:11:49.164585 EX_ROW_EN[0] = 0x0
6145 11:11:49.168206 EX_ROW_EN[1] = 0x0
6146 11:11:49.168352 LP4Y_EN = 0x0
6147 11:11:49.171213 WORK_FSP = 0x0
6148 11:11:49.171326 WL = 0x2
6149 11:11:49.174783 RL = 0x2
6150 11:11:49.174865 BL = 0x2
6151 11:11:49.177973 RPST = 0x0
6152 11:11:49.178056 RD_PRE = 0x0
6153 11:11:49.181157 WR_PRE = 0x1
6154 11:11:49.181239 WR_PST = 0x0
6155 11:11:49.184698 DBI_WR = 0x0
6156 11:11:49.184780 DBI_RD = 0x0
6157 11:11:49.187660 OTF = 0x1
6158 11:11:49.191565 ===================================
6159 11:11:49.194401 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6160 11:11:49.198120 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6161 11:11:49.204437 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6162 11:11:49.207787 ===================================
6163 11:11:49.207869 LPDDR4 DRAM CONFIGURATION
6164 11:11:49.210913 ===================================
6165 11:11:49.214075 EX_ROW_EN[0] = 0x10
6166 11:11:49.217918 EX_ROW_EN[1] = 0x0
6167 11:11:49.218040 LP4Y_EN = 0x0
6168 11:11:49.221179 WORK_FSP = 0x0
6169 11:11:49.221284 WL = 0x2
6170 11:11:49.224065 RL = 0x2
6171 11:11:49.224171 BL = 0x2
6172 11:11:49.227574 RPST = 0x0
6173 11:11:49.227659 RD_PRE = 0x0
6174 11:11:49.230489 WR_PRE = 0x1
6175 11:11:49.230602 WR_PST = 0x0
6176 11:11:49.234204 DBI_WR = 0x0
6177 11:11:49.234306 DBI_RD = 0x0
6178 11:11:49.237324 OTF = 0x1
6179 11:11:49.240851 ===================================
6180 11:11:49.247079 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6181 11:11:49.250287 nWR fixed to 30
6182 11:11:49.253630 [ModeRegInit_LP4] CH0 RK0
6183 11:11:49.253747 [ModeRegInit_LP4] CH0 RK1
6184 11:11:49.257307 [ModeRegInit_LP4] CH1 RK0
6185 11:11:49.260723 [ModeRegInit_LP4] CH1 RK1
6186 11:11:49.260871 match AC timing 19
6187 11:11:49.267151 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6188 11:11:49.270255 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6189 11:11:49.273884 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6190 11:11:49.280100 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6191 11:11:49.283719 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6192 11:11:49.283832 ==
6193 11:11:49.286982 Dram Type= 6, Freq= 0, CH_0, rank 0
6194 11:11:49.289911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6195 11:11:49.290027 ==
6196 11:11:49.296745 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6197 11:11:49.303529 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6198 11:11:49.306648 [CA 0] Center 36 (8~64) winsize 57
6199 11:11:49.310209 [CA 1] Center 36 (8~64) winsize 57
6200 11:11:49.313309 [CA 2] Center 36 (8~64) winsize 57
6201 11:11:49.316763 [CA 3] Center 36 (8~64) winsize 57
6202 11:11:49.316876 [CA 4] Center 36 (8~64) winsize 57
6203 11:11:49.319960 [CA 5] Center 36 (8~64) winsize 57
6204 11:11:49.320077
6205 11:11:49.326909 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6206 11:11:49.327019
6207 11:11:49.329860 [CATrainingPosCal] consider 1 rank data
6208 11:11:49.333395 u2DelayCellTimex100 = 270/100 ps
6209 11:11:49.336737 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 11:11:49.339725 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 11:11:49.343345 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 11:11:49.346332 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 11:11:49.349516 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 11:11:49.353143 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 11:11:49.353265
6216 11:11:49.356194 CA PerBit enable=1, Macro0, CA PI delay=36
6217 11:11:49.356325
6218 11:11:49.359655 [CBTSetCACLKResult] CA Dly = 36
6219 11:11:49.363059 CS Dly: 1 (0~32)
6220 11:11:49.363137 ==
6221 11:11:49.366179 Dram Type= 6, Freq= 0, CH_0, rank 1
6222 11:11:49.369675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6223 11:11:49.369760 ==
6224 11:11:49.376535 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6225 11:11:49.379935 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6226 11:11:49.382975 [CA 0] Center 36 (8~64) winsize 57
6227 11:11:49.386084 [CA 1] Center 36 (8~64) winsize 57
6228 11:11:49.389915 [CA 2] Center 36 (8~64) winsize 57
6229 11:11:49.392909 [CA 3] Center 36 (8~64) winsize 57
6230 11:11:49.395965 [CA 4] Center 36 (8~64) winsize 57
6231 11:11:49.399678 [CA 5] Center 36 (8~64) winsize 57
6232 11:11:49.399792
6233 11:11:49.402695 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6234 11:11:49.402811
6235 11:11:49.406515 [CATrainingPosCal] consider 2 rank data
6236 11:11:49.409593 u2DelayCellTimex100 = 270/100 ps
6237 11:11:49.412679 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 11:11:49.415984 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 11:11:49.422892 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 11:11:49.426382 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 11:11:49.429464 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 11:11:49.432672 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 11:11:49.432756
6244 11:11:49.435935 CA PerBit enable=1, Macro0, CA PI delay=36
6245 11:11:49.436045
6246 11:11:49.439663 [CBTSetCACLKResult] CA Dly = 36
6247 11:11:49.439747 CS Dly: 1 (0~32)
6248 11:11:49.439813
6249 11:11:49.442677 ----->DramcWriteLeveling(PI) begin...
6250 11:11:49.446106 ==
6251 11:11:49.449410 Dram Type= 6, Freq= 0, CH_0, rank 0
6252 11:11:49.452641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6253 11:11:49.452745 ==
6254 11:11:49.456272 Write leveling (Byte 0): 40 => 8
6255 11:11:49.459472 Write leveling (Byte 1): 40 => 8
6256 11:11:49.459581 DramcWriteLeveling(PI) end<-----
6257 11:11:49.462635
6258 11:11:49.462716 ==
6259 11:11:49.465733 Dram Type= 6, Freq= 0, CH_0, rank 0
6260 11:11:49.469543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 11:11:49.469635 ==
6262 11:11:49.472459 [Gating] SW mode calibration
6263 11:11:49.479526 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6264 11:11:49.482611 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6265 11:11:49.489048 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6266 11:11:49.492782 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6267 11:11:49.495758 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6268 11:11:49.502897 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6269 11:11:49.506102 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 11:11:49.509050 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 11:11:49.515972 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 11:11:49.519019 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 11:11:49.522792 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 11:11:49.525801 Total UI for P1: 0, mck2ui 16
6275 11:11:49.528978 best dqsien dly found for B0: ( 0, 14, 24)
6276 11:11:49.532507 Total UI for P1: 0, mck2ui 16
6277 11:11:49.535540 best dqsien dly found for B1: ( 0, 14, 24)
6278 11:11:49.539335 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6279 11:11:49.542527 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6280 11:11:49.545690
6281 11:11:49.548939 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6282 11:11:49.552057 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6283 11:11:49.555675 [Gating] SW calibration Done
6284 11:11:49.555757 ==
6285 11:11:49.558616 Dram Type= 6, Freq= 0, CH_0, rank 0
6286 11:11:49.562633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 11:11:49.562715 ==
6288 11:11:49.562780 RX Vref Scan: 0
6289 11:11:49.562870
6290 11:11:49.565414 RX Vref 0 -> 0, step: 1
6291 11:11:49.565496
6292 11:11:49.568935 RX Delay -410 -> 252, step: 16
6293 11:11:49.572072 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6294 11:11:49.579066 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6295 11:11:49.582148 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6296 11:11:49.585179 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6297 11:11:49.588779 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6298 11:11:49.595642 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6299 11:11:49.598590 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6300 11:11:49.602143 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6301 11:11:49.605643 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6302 11:11:49.612411 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6303 11:11:49.615435 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6304 11:11:49.618817 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6305 11:11:49.621813 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6306 11:11:49.628665 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6307 11:11:49.632209 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6308 11:11:49.635150 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6309 11:11:49.635233 ==
6310 11:11:49.638724 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 11:11:49.641810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 11:11:49.645564 ==
6313 11:11:49.645648 DQS Delay:
6314 11:11:49.645715 DQS0 = 27, DQS1 = 35
6315 11:11:49.648841 DQM Delay:
6316 11:11:49.648936 DQM0 = 9, DQM1 = 12
6317 11:11:49.651866 DQ Delay:
6318 11:11:49.651985 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6319 11:11:49.655173 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6320 11:11:49.659000 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6321 11:11:49.662078 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6322 11:11:49.662159
6323 11:11:49.662222
6324 11:11:49.662280 ==
6325 11:11:49.665268 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 11:11:49.672377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 11:11:49.672458 ==
6328 11:11:49.672521
6329 11:11:49.672579
6330 11:11:49.672636 TX Vref Scan disable
6331 11:11:49.675364 == TX Byte 0 ==
6332 11:11:49.678485 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6333 11:11:49.682431 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6334 11:11:49.685467 == TX Byte 1 ==
6335 11:11:49.688589 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6336 11:11:49.692212 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6337 11:11:49.695376 ==
6338 11:11:49.695463 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 11:11:49.701488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 11:11:49.701607 ==
6341 11:11:49.701670
6342 11:11:49.701727
6343 11:11:49.705244 TX Vref Scan disable
6344 11:11:49.705331 == TX Byte 0 ==
6345 11:11:49.708217 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 11:11:49.714902 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 11:11:49.715013 == TX Byte 1 ==
6348 11:11:49.718486 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6349 11:11:49.725039 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6350 11:11:49.725113
6351 11:11:49.725174 [DATLAT]
6352 11:11:49.725231 Freq=400, CH0 RK0
6353 11:11:49.725287
6354 11:11:49.728007 DATLAT Default: 0xf
6355 11:11:49.728103 0, 0xFFFF, sum = 0
6356 11:11:49.731502 1, 0xFFFF, sum = 0
6357 11:11:49.731576 2, 0xFFFF, sum = 0
6358 11:11:49.735249 3, 0xFFFF, sum = 0
6359 11:11:49.738251 4, 0xFFFF, sum = 0
6360 11:11:49.738334 5, 0xFFFF, sum = 0
6361 11:11:49.741454 6, 0xFFFF, sum = 0
6362 11:11:49.741536 7, 0xFFFF, sum = 0
6363 11:11:49.745077 8, 0xFFFF, sum = 0
6364 11:11:49.745158 9, 0xFFFF, sum = 0
6365 11:11:49.748099 10, 0xFFFF, sum = 0
6366 11:11:49.748194 11, 0xFFFF, sum = 0
6367 11:11:49.751218 12, 0xFFFF, sum = 0
6368 11:11:49.751299 13, 0x0, sum = 1
6369 11:11:49.754516 14, 0x0, sum = 2
6370 11:11:49.754597 15, 0x0, sum = 3
6371 11:11:49.757785 16, 0x0, sum = 4
6372 11:11:49.757866 best_step = 14
6373 11:11:49.757929
6374 11:11:49.757987 ==
6375 11:11:49.761370 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 11:11:49.764564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 11:11:49.768306 ==
6378 11:11:49.768400 RX Vref Scan: 1
6379 11:11:49.768463
6380 11:11:49.771480 RX Vref 0 -> 0, step: 1
6381 11:11:49.771560
6382 11:11:49.774543 RX Delay -311 -> 252, step: 8
6383 11:11:49.774623
6384 11:11:49.777973 Set Vref, RX VrefLevel [Byte0]: 55
6385 11:11:49.780936 [Byte1]: 51
6386 11:11:49.781016
6387 11:11:49.784648 Final RX Vref Byte 0 = 55 to rank0
6388 11:11:49.787746 Final RX Vref Byte 1 = 51 to rank0
6389 11:11:49.790957 Final RX Vref Byte 0 = 55 to rank1
6390 11:11:49.794670 Final RX Vref Byte 1 = 51 to rank1==
6391 11:11:49.797682 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 11:11:49.801431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 11:11:49.801512 ==
6394 11:11:49.804360 DQS Delay:
6395 11:11:49.804440 DQS0 = 28, DQS1 = 36
6396 11:11:49.807474 DQM Delay:
6397 11:11:49.807554 DQM0 = 11, DQM1 = 13
6398 11:11:49.807617 DQ Delay:
6399 11:11:49.811258 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6400 11:11:49.814362 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6401 11:11:49.818028 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6402 11:11:49.821125 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6403 11:11:49.821206
6404 11:11:49.821269
6405 11:11:49.831009 [DQSOSCAuto] RK0, (LSB)MR18= 0xcebc, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6406 11:11:49.831090 CH0 RK0: MR19=C0C, MR18=CEBC
6407 11:11:49.837653 CH0_RK0: MR19=0xC0C, MR18=0xCEBC, DQSOSC=384, MR23=63, INC=400, DEC=267
6408 11:11:49.837734 ==
6409 11:11:49.841136 Dram Type= 6, Freq= 0, CH_0, rank 1
6410 11:11:49.847406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 11:11:49.847504 ==
6412 11:11:49.851144 [Gating] SW mode calibration
6413 11:11:49.857639 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6414 11:11:49.860667 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6415 11:11:49.867255 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6416 11:11:49.871099 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6417 11:11:49.873788 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6418 11:11:49.880655 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6419 11:11:49.884144 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6420 11:11:49.887742 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6421 11:11:49.894414 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 11:11:49.897507 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 11:11:49.901075 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6424 11:11:49.904173 Total UI for P1: 0, mck2ui 16
6425 11:11:49.907240 best dqsien dly found for B0: ( 0, 14, 24)
6426 11:11:49.910987 Total UI for P1: 0, mck2ui 16
6427 11:11:49.914021 best dqsien dly found for B1: ( 0, 14, 24)
6428 11:11:49.917297 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6429 11:11:49.920393 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6430 11:11:49.920482
6431 11:11:49.923992 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6432 11:11:49.930393 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6433 11:11:49.930475 [Gating] SW calibration Done
6434 11:11:49.930539 ==
6435 11:11:49.933991 Dram Type= 6, Freq= 0, CH_0, rank 1
6436 11:11:49.940354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 11:11:49.940435 ==
6438 11:11:49.940498 RX Vref Scan: 0
6439 11:11:49.940557
6440 11:11:49.944061 RX Vref 0 -> 0, step: 1
6441 11:11:49.944144
6442 11:11:49.947083 RX Delay -410 -> 252, step: 16
6443 11:11:49.950707 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6444 11:11:49.953536 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6445 11:11:49.960178 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6446 11:11:49.963502 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6447 11:11:49.966735 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6448 11:11:49.970576 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6449 11:11:49.976615 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6450 11:11:49.980411 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6451 11:11:49.983521 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6452 11:11:49.986706 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6453 11:11:49.993428 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6454 11:11:49.997059 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6455 11:11:50.000118 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6456 11:11:50.003791 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6457 11:11:50.010369 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6458 11:11:50.013505 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6459 11:11:50.013586 ==
6460 11:11:50.016715 Dram Type= 6, Freq= 0, CH_0, rank 1
6461 11:11:50.020546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 11:11:50.020627 ==
6463 11:11:50.023763 DQS Delay:
6464 11:11:50.023844 DQS0 = 27, DQS1 = 35
6465 11:11:50.026813 DQM Delay:
6466 11:11:50.026893 DQM0 = 11, DQM1 = 11
6467 11:11:50.026957 DQ Delay:
6468 11:11:50.029944 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6469 11:11:50.033475 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6470 11:11:50.036762 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6471 11:11:50.040164 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6472 11:11:50.040292
6473 11:11:50.040375
6474 11:11:50.040435 ==
6475 11:11:50.043297 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 11:11:50.050212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 11:11:50.050294 ==
6478 11:11:50.050357
6479 11:11:50.050416
6480 11:11:50.050472 TX Vref Scan disable
6481 11:11:50.053354 == TX Byte 0 ==
6482 11:11:50.056457 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6483 11:11:50.060004 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6484 11:11:50.063174 == TX Byte 1 ==
6485 11:11:50.066956 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6486 11:11:50.070119 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6487 11:11:50.070200 ==
6488 11:11:50.073196 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 11:11:50.079994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 11:11:50.080075 ==
6491 11:11:50.080139
6492 11:11:50.080202
6493 11:11:50.080334 TX Vref Scan disable
6494 11:11:50.083196 == TX Byte 0 ==
6495 11:11:50.086510 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6496 11:11:50.089916 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6497 11:11:50.093426 == TX Byte 1 ==
6498 11:11:50.096447 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6499 11:11:50.100104 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6500 11:11:50.100208
6501 11:11:50.103216 [DATLAT]
6502 11:11:50.103296 Freq=400, CH0 RK1
6503 11:11:50.103361
6504 11:11:50.106844 DATLAT Default: 0xe
6505 11:11:50.106924 0, 0xFFFF, sum = 0
6506 11:11:50.109813 1, 0xFFFF, sum = 0
6507 11:11:50.109895 2, 0xFFFF, sum = 0
6508 11:11:50.113472 3, 0xFFFF, sum = 0
6509 11:11:50.113555 4, 0xFFFF, sum = 0
6510 11:11:50.116580 5, 0xFFFF, sum = 0
6511 11:11:50.116662 6, 0xFFFF, sum = 0
6512 11:11:50.119671 7, 0xFFFF, sum = 0
6513 11:11:50.119752 8, 0xFFFF, sum = 0
6514 11:11:50.122850 9, 0xFFFF, sum = 0
6515 11:11:50.122932 10, 0xFFFF, sum = 0
6516 11:11:50.126650 11, 0xFFFF, sum = 0
6517 11:11:50.129724 12, 0xFFFF, sum = 0
6518 11:11:50.129805 13, 0x0, sum = 1
6519 11:11:50.129870 14, 0x0, sum = 2
6520 11:11:50.132678 15, 0x0, sum = 3
6521 11:11:50.132760 16, 0x0, sum = 4
6522 11:11:50.136051 best_step = 14
6523 11:11:50.136131
6524 11:11:50.136195 ==
6525 11:11:50.139687 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 11:11:50.143101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 11:11:50.143182 ==
6528 11:11:50.146574 RX Vref Scan: 0
6529 11:11:50.146660
6530 11:11:50.146799 RX Vref 0 -> 0, step: 1
6531 11:11:50.146924
6532 11:11:50.149403 RX Delay -311 -> 252, step: 8
6533 11:11:50.157809 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6534 11:11:50.160930 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6535 11:11:50.164541 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6536 11:11:50.167556 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6537 11:11:50.174265 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6538 11:11:50.177451 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6539 11:11:50.181154 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6540 11:11:50.184201 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6541 11:11:50.191229 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6542 11:11:50.194591 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6543 11:11:50.197382 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6544 11:11:50.201268 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6545 11:11:50.207643 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6546 11:11:50.211084 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6547 11:11:50.214283 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6548 11:11:50.221227 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6549 11:11:50.221352 ==
6550 11:11:50.224364 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 11:11:50.227570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 11:11:50.227693 ==
6553 11:11:50.227805 DQS Delay:
6554 11:11:50.230729 DQS0 = 24, DQS1 = 32
6555 11:11:50.230852 DQM Delay:
6556 11:11:50.234150 DQM0 = 7, DQM1 = 9
6557 11:11:50.234272 DQ Delay:
6558 11:11:50.237953 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6559 11:11:50.241070 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6560 11:11:50.244302 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6561 11:11:50.247951 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6562 11:11:50.248055
6563 11:11:50.248148
6564 11:11:50.254014 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6565 11:11:50.257424 CH0 RK1: MR19=C0C, MR18=BD5D
6566 11:11:50.263918 CH0_RK1: MR19=0xC0C, MR18=0xBD5D, DQSOSC=386, MR23=63, INC=396, DEC=264
6567 11:11:50.267603 [RxdqsGatingPostProcess] freq 400
6568 11:11:50.270633 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6569 11:11:50.274433 best DQS0 dly(2T, 0.5T) = (0, 10)
6570 11:11:50.277211 best DQS1 dly(2T, 0.5T) = (0, 10)
6571 11:11:50.280981 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6572 11:11:50.284085 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6573 11:11:50.287349 best DQS0 dly(2T, 0.5T) = (0, 10)
6574 11:11:50.290629 best DQS1 dly(2T, 0.5T) = (0, 10)
6575 11:11:50.293740 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6576 11:11:50.296999 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6577 11:11:50.300694 Pre-setting of DQS Precalculation
6578 11:11:50.303944 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6579 11:11:50.304065 ==
6580 11:11:50.306977 Dram Type= 6, Freq= 0, CH_1, rank 0
6581 11:11:50.313791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 11:11:50.313917 ==
6583 11:11:50.317375 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6584 11:11:50.323813 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6585 11:11:50.327032 [CA 0] Center 36 (8~64) winsize 57
6586 11:11:50.330359 [CA 1] Center 36 (8~64) winsize 57
6587 11:11:50.333645 [CA 2] Center 36 (8~64) winsize 57
6588 11:11:50.336977 [CA 3] Center 36 (8~64) winsize 57
6589 11:11:50.340487 [CA 4] Center 36 (8~64) winsize 57
6590 11:11:50.343918 [CA 5] Center 36 (8~64) winsize 57
6591 11:11:50.344048
6592 11:11:50.347047 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6593 11:11:50.347165
6594 11:11:50.350052 [CATrainingPosCal] consider 1 rank data
6595 11:11:50.353905 u2DelayCellTimex100 = 270/100 ps
6596 11:11:50.356997 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 11:11:50.360168 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 11:11:50.363691 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 11:11:50.366674 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 11:11:50.370255 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 11:11:50.376466 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 11:11:50.376592
6603 11:11:50.380166 CA PerBit enable=1, Macro0, CA PI delay=36
6604 11:11:50.380293
6605 11:11:50.383287 [CBTSetCACLKResult] CA Dly = 36
6606 11:11:50.383437 CS Dly: 1 (0~32)
6607 11:11:50.383544 ==
6608 11:11:50.386772 Dram Type= 6, Freq= 0, CH_1, rank 1
6609 11:11:50.390087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6610 11:11:50.393221 ==
6611 11:11:50.397039 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6612 11:11:50.403332 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6613 11:11:50.406651 [CA 0] Center 36 (8~64) winsize 57
6614 11:11:50.409752 [CA 1] Center 36 (8~64) winsize 57
6615 11:11:50.413432 [CA 2] Center 36 (8~64) winsize 57
6616 11:11:50.416496 [CA 3] Center 36 (8~64) winsize 57
6617 11:11:50.419695 [CA 4] Center 36 (8~64) winsize 57
6618 11:11:50.423426 [CA 5] Center 36 (8~64) winsize 57
6619 11:11:50.423552
6620 11:11:50.426356 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6621 11:11:50.426480
6622 11:11:50.429774 [CATrainingPosCal] consider 2 rank data
6623 11:11:50.433279 u2DelayCellTimex100 = 270/100 ps
6624 11:11:50.436368 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 11:11:50.439741 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 11:11:50.443228 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 11:11:50.446637 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 11:11:50.449516 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 11:11:50.453110 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 11:11:50.453230
6631 11:11:50.456382 CA PerBit enable=1, Macro0, CA PI delay=36
6632 11:11:50.459719
6633 11:11:50.459841 [CBTSetCACLKResult] CA Dly = 36
6634 11:11:50.463281 CS Dly: 1 (0~32)
6635 11:11:50.463405
6636 11:11:50.466290 ----->DramcWriteLeveling(PI) begin...
6637 11:11:50.466416 ==
6638 11:11:50.469939 Dram Type= 6, Freq= 0, CH_1, rank 0
6639 11:11:50.473020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 11:11:50.473145 ==
6641 11:11:50.476709 Write leveling (Byte 0): 40 => 8
6642 11:11:50.479886 Write leveling (Byte 1): 40 => 8
6643 11:11:50.483078 DramcWriteLeveling(PI) end<-----
6644 11:11:50.483207
6645 11:11:50.483321 ==
6646 11:11:50.486075 Dram Type= 6, Freq= 0, CH_1, rank 0
6647 11:11:50.489579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 11:11:50.489705 ==
6649 11:11:50.493129 [Gating] SW mode calibration
6650 11:11:50.499237 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6651 11:11:50.506064 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6652 11:11:50.509189 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6653 11:11:50.516079 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6654 11:11:50.519094 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6655 11:11:50.522355 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6656 11:11:50.529158 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6657 11:11:50.532242 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6658 11:11:50.535821 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 11:11:50.542208 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 11:11:50.545538 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6661 11:11:50.549169 Total UI for P1: 0, mck2ui 16
6662 11:11:50.552787 best dqsien dly found for B0: ( 0, 14, 24)
6663 11:11:50.555794 Total UI for P1: 0, mck2ui 16
6664 11:11:50.558713 best dqsien dly found for B1: ( 0, 14, 24)
6665 11:11:50.562042 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6666 11:11:50.565565 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6667 11:11:50.565689
6668 11:11:50.569027 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6669 11:11:50.572388 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6670 11:11:50.575724 [Gating] SW calibration Done
6671 11:11:50.575845 ==
6672 11:11:50.579062 Dram Type= 6, Freq= 0, CH_1, rank 0
6673 11:11:50.582275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 11:11:50.585890 ==
6675 11:11:50.586012 RX Vref Scan: 0
6676 11:11:50.586125
6677 11:11:50.589091 RX Vref 0 -> 0, step: 1
6678 11:11:50.589215
6679 11:11:50.592224 RX Delay -410 -> 252, step: 16
6680 11:11:50.595331 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6681 11:11:50.598981 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6682 11:11:50.602564 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6683 11:11:50.608976 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6684 11:11:50.612064 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6685 11:11:50.615878 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6686 11:11:50.618869 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6687 11:11:50.625589 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6688 11:11:50.628588 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6689 11:11:50.632493 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6690 11:11:50.635706 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6691 11:11:50.642301 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6692 11:11:50.645435 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6693 11:11:50.648989 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6694 11:11:50.651940 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6695 11:11:50.658520 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6696 11:11:50.658608 ==
6697 11:11:50.661919 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 11:11:50.665418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 11:11:50.665495 ==
6700 11:11:50.665577 DQS Delay:
6701 11:11:50.668649 DQS0 = 27, DQS1 = 35
6702 11:11:50.668750 DQM Delay:
6703 11:11:50.672198 DQM0 = 11, DQM1 = 13
6704 11:11:50.672282 DQ Delay:
6705 11:11:50.675278 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6706 11:11:50.678937 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6707 11:11:50.681970 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6708 11:11:50.685240 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6709 11:11:50.685324
6710 11:11:50.685411
6711 11:11:50.685473 ==
6712 11:11:50.688693 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 11:11:50.692009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 11:11:50.692100 ==
6715 11:11:50.692198
6716 11:11:50.692316
6717 11:11:50.695588 TX Vref Scan disable
6718 11:11:50.698483 == TX Byte 0 ==
6719 11:11:50.701985 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6720 11:11:50.705617 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6721 11:11:50.705699 == TX Byte 1 ==
6722 11:11:50.712158 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6723 11:11:50.715275 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6724 11:11:50.715356 ==
6725 11:11:50.718564 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 11:11:50.721626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 11:11:50.721720 ==
6728 11:11:50.721805
6729 11:11:50.721882
6730 11:11:50.725413 TX Vref Scan disable
6731 11:11:50.728424 == TX Byte 0 ==
6732 11:11:50.731527 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 11:11:50.735269 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 11:11:50.738525 == TX Byte 1 ==
6735 11:11:50.741714 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6736 11:11:50.744779 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6737 11:11:50.744861
6738 11:11:50.744926 [DATLAT]
6739 11:11:50.748330 Freq=400, CH1 RK0
6740 11:11:50.748413
6741 11:11:50.748477 DATLAT Default: 0xf
6742 11:11:50.752218 0, 0xFFFF, sum = 0
6743 11:11:50.752352 1, 0xFFFF, sum = 0
6744 11:11:50.754954 2, 0xFFFF, sum = 0
6745 11:11:50.755036 3, 0xFFFF, sum = 0
6746 11:11:50.758448 4, 0xFFFF, sum = 0
6747 11:11:50.761391 5, 0xFFFF, sum = 0
6748 11:11:50.761474 6, 0xFFFF, sum = 0
6749 11:11:50.765042 7, 0xFFFF, sum = 0
6750 11:11:50.765151 8, 0xFFFF, sum = 0
6751 11:11:50.768010 9, 0xFFFF, sum = 0
6752 11:11:50.768125 10, 0xFFFF, sum = 0
6753 11:11:50.771739 11, 0xFFFF, sum = 0
6754 11:11:50.771822 12, 0xFFFF, sum = 0
6755 11:11:50.774885 13, 0x0, sum = 1
6756 11:11:50.774967 14, 0x0, sum = 2
6757 11:11:50.778486 15, 0x0, sum = 3
6758 11:11:50.778568 16, 0x0, sum = 4
6759 11:11:50.781536 best_step = 14
6760 11:11:50.781617
6761 11:11:50.781681 ==
6762 11:11:50.785199 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 11:11:50.788325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 11:11:50.788447 ==
6765 11:11:50.788561 RX Vref Scan: 1
6766 11:11:50.788667
6767 11:11:50.791586 RX Vref 0 -> 0, step: 1
6768 11:11:50.791703
6769 11:11:50.795180 RX Delay -311 -> 252, step: 8
6770 11:11:50.795303
6771 11:11:50.798167 Set Vref, RX VrefLevel [Byte0]: 55
6772 11:11:50.801609 [Byte1]: 55
6773 11:11:50.805573
6774 11:11:50.805687 Final RX Vref Byte 0 = 55 to rank0
6775 11:11:50.808843 Final RX Vref Byte 1 = 55 to rank0
6776 11:11:50.812383 Final RX Vref Byte 0 = 55 to rank1
6777 11:11:50.815594 Final RX Vref Byte 1 = 55 to rank1==
6778 11:11:50.818572 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 11:11:50.825319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 11:11:50.825474 ==
6781 11:11:50.825586 DQS Delay:
6782 11:11:50.825695 DQS0 = 28, DQS1 = 32
6783 11:11:50.828524 DQM Delay:
6784 11:11:50.828646 DQM0 = 9, DQM1 = 9
6785 11:11:50.832159 DQ Delay:
6786 11:11:50.832278 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6787 11:11:50.835314 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6788 11:11:50.838550 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6789 11:11:50.842189 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6790 11:11:50.842312
6791 11:11:50.842425
6792 11:11:50.851930 [DQSOSCAuto] RK0, (LSB)MR18= 0x8ac2, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6793 11:11:50.855691 CH1 RK0: MR19=C0C, MR18=8AC2
6794 11:11:50.858961 CH1_RK0: MR19=0xC0C, MR18=0x8AC2, DQSOSC=385, MR23=63, INC=398, DEC=265
6795 11:11:50.862043 ==
6796 11:11:50.865527 Dram Type= 6, Freq= 0, CH_1, rank 1
6797 11:11:50.868555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 11:11:50.868676 ==
6799 11:11:50.871951 [Gating] SW mode calibration
6800 11:11:50.878758 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6801 11:11:50.882310 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6802 11:11:50.889131 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6803 11:11:50.891705 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6804 11:11:50.895458 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6805 11:11:50.902137 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6806 11:11:50.905360 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6807 11:11:50.908590 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6808 11:11:50.915149 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 11:11:50.918674 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 11:11:50.921629 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6811 11:11:50.925093 Total UI for P1: 0, mck2ui 16
6812 11:11:50.928511 best dqsien dly found for B0: ( 0, 14, 24)
6813 11:11:50.931834 Total UI for P1: 0, mck2ui 16
6814 11:11:50.935206 best dqsien dly found for B1: ( 0, 14, 24)
6815 11:11:50.938710 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6816 11:11:50.942015 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6817 11:11:50.942135
6818 11:11:50.945035 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6819 11:11:50.951934 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6820 11:11:50.952059 [Gating] SW calibration Done
6821 11:11:50.954958 ==
6822 11:11:50.955078 Dram Type= 6, Freq= 0, CH_1, rank 1
6823 11:11:50.961758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 11:11:50.961881 ==
6825 11:11:50.961992 RX Vref Scan: 0
6826 11:11:50.962099
6827 11:11:50.964906 RX Vref 0 -> 0, step: 1
6828 11:11:50.965028
6829 11:11:50.968661 RX Delay -410 -> 252, step: 16
6830 11:11:50.971596 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6831 11:11:50.975300 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6832 11:11:50.983064 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6833 11:11:50.985425 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6834 11:11:50.988571 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6835 11:11:50.992098 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6836 11:11:50.998669 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6837 11:11:51.001753 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6838 11:11:51.004925 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6839 11:11:51.008488 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6840 11:11:51.015362 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6841 11:11:51.018376 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6842 11:11:51.021495 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6843 11:11:51.025270 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6844 11:11:51.031466 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6845 11:11:51.035002 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6846 11:11:51.035123 ==
6847 11:11:51.038028 Dram Type= 6, Freq= 0, CH_1, rank 1
6848 11:11:51.041408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 11:11:51.041490 ==
6850 11:11:51.044861 DQS Delay:
6851 11:11:51.044948 DQS0 = 35, DQS1 = 35
6852 11:11:51.048351 DQM Delay:
6853 11:11:51.048466 DQM0 = 18, DQM1 = 15
6854 11:11:51.048573 DQ Delay:
6855 11:11:51.051536 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6856 11:11:51.054625 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6857 11:11:51.058306 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6858 11:11:51.061408 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6859 11:11:51.061531
6860 11:11:51.061642
6861 11:11:51.061750 ==
6862 11:11:51.065091 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 11:11:51.071445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 11:11:51.071568 ==
6865 11:11:51.071696
6866 11:11:51.071819
6867 11:11:51.071925 TX Vref Scan disable
6868 11:11:51.074502 == TX Byte 0 ==
6869 11:11:51.078173 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6870 11:11:51.081426 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6871 11:11:51.084644 == TX Byte 1 ==
6872 11:11:51.088171 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6873 11:11:51.091494 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6874 11:11:51.091614 ==
6875 11:11:51.094539 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 11:11:51.101358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 11:11:51.101480 ==
6878 11:11:51.101594
6879 11:11:51.101701
6880 11:11:51.101806 TX Vref Scan disable
6881 11:11:51.104999 == TX Byte 0 ==
6882 11:11:51.107974 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6883 11:11:51.111097 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6884 11:11:51.114304 == TX Byte 1 ==
6885 11:11:51.118102 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6886 11:11:51.121147 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6887 11:11:51.121268
6888 11:11:51.124898 [DATLAT]
6889 11:11:51.125017 Freq=400, CH1 RK1
6890 11:11:51.125128
6891 11:11:51.127913 DATLAT Default: 0xe
6892 11:11:51.128035 0, 0xFFFF, sum = 0
6893 11:11:51.131084 1, 0xFFFF, sum = 0
6894 11:11:51.131205 2, 0xFFFF, sum = 0
6895 11:11:51.134363 3, 0xFFFF, sum = 0
6896 11:11:51.134485 4, 0xFFFF, sum = 0
6897 11:11:51.138026 5, 0xFFFF, sum = 0
6898 11:11:51.138131 6, 0xFFFF, sum = 0
6899 11:11:51.141098 7, 0xFFFF, sum = 0
6900 11:11:51.141200 8, 0xFFFF, sum = 0
6901 11:11:51.144807 9, 0xFFFF, sum = 0
6902 11:11:51.144889 10, 0xFFFF, sum = 0
6903 11:11:51.147981 11, 0xFFFF, sum = 0
6904 11:11:51.151105 12, 0xFFFF, sum = 0
6905 11:11:51.151232 13, 0x0, sum = 1
6906 11:11:51.151349 14, 0x0, sum = 2
6907 11:11:51.154713 15, 0x0, sum = 3
6908 11:11:51.154837 16, 0x0, sum = 4
6909 11:11:51.158126 best_step = 14
6910 11:11:51.158210
6911 11:11:51.158275 ==
6912 11:11:51.161420 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 11:11:51.164568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 11:11:51.164693 ==
6915 11:11:51.167975 RX Vref Scan: 0
6916 11:11:51.168098
6917 11:11:51.168214 RX Vref 0 -> 0, step: 1
6918 11:11:51.171049
6919 11:11:51.171170 RX Delay -311 -> 252, step: 8
6920 11:11:51.179428 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6921 11:11:51.182415 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6922 11:11:51.186192 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6923 11:11:51.189383 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6924 11:11:51.196030 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6925 11:11:51.199017 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6926 11:11:51.202666 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6927 11:11:51.206037 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6928 11:11:51.212577 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6929 11:11:51.215833 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6930 11:11:51.219259 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6931 11:11:51.222433 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6932 11:11:51.229493 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6933 11:11:51.232282 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6934 11:11:51.236137 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6935 11:11:51.242515 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6936 11:11:51.242640 ==
6937 11:11:51.245964 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 11:11:51.249132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 11:11:51.249254 ==
6940 11:11:51.249369 DQS Delay:
6941 11:11:51.252270 DQS0 = 28, DQS1 = 32
6942 11:11:51.252423 DQM Delay:
6943 11:11:51.255483 DQM0 = 10, DQM1 = 11
6944 11:11:51.255603 DQ Delay:
6945 11:11:51.259214 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6946 11:11:51.262385 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6947 11:11:51.265675 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6948 11:11:51.269349 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6949 11:11:51.269470
6950 11:11:51.269580
6951 11:11:51.276008 [DQSOSCAuto] RK1, (LSB)MR18= 0xc758, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6952 11:11:51.278935 CH1 RK1: MR19=C0C, MR18=C758
6953 11:11:51.285694 CH1_RK1: MR19=0xC0C, MR18=0xC758, DQSOSC=385, MR23=63, INC=398, DEC=265
6954 11:11:51.289091 [RxdqsGatingPostProcess] freq 400
6955 11:11:51.292396 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6956 11:11:51.295336 best DQS0 dly(2T, 0.5T) = (0, 10)
6957 11:11:51.299123 best DQS1 dly(2T, 0.5T) = (0, 10)
6958 11:11:51.302657 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6959 11:11:51.305716 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6960 11:11:51.309012 best DQS0 dly(2T, 0.5T) = (0, 10)
6961 11:11:51.312062 best DQS1 dly(2T, 0.5T) = (0, 10)
6962 11:11:51.315550 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6963 11:11:51.319185 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6964 11:11:51.322540 Pre-setting of DQS Precalculation
6965 11:11:51.325384 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6966 11:11:51.335376 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6967 11:11:51.341973 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6968 11:11:51.342083
6969 11:11:51.342176
6970 11:11:51.345280 [Calibration Summary] 800 Mbps
6971 11:11:51.345363 CH 0, Rank 0
6972 11:11:51.348993 SW Impedance : PASS
6973 11:11:51.349069 DUTY Scan : NO K
6974 11:11:51.352188 ZQ Calibration : PASS
6975 11:11:51.355372 Jitter Meter : NO K
6976 11:11:51.355471 CBT Training : PASS
6977 11:11:51.359225 Write leveling : PASS
6978 11:11:51.362186 RX DQS gating : PASS
6979 11:11:51.362268 RX DQ/DQS(RDDQC) : PASS
6980 11:11:51.365945 TX DQ/DQS : PASS
6981 11:11:51.369129 RX DATLAT : PASS
6982 11:11:51.369212 RX DQ/DQS(Engine): PASS
6983 11:11:51.372140 TX OE : NO K
6984 11:11:51.372222 All Pass.
6985 11:11:51.372317
6986 11:11:51.375703 CH 0, Rank 1
6987 11:11:51.375785 SW Impedance : PASS
6988 11:11:51.378806 DUTY Scan : NO K
6989 11:11:51.378888 ZQ Calibration : PASS
6990 11:11:51.381925 Jitter Meter : NO K
6991 11:11:51.385511 CBT Training : PASS
6992 11:11:51.385593 Write leveling : NO K
6993 11:11:51.388612 RX DQS gating : PASS
6994 11:11:51.392083 RX DQ/DQS(RDDQC) : PASS
6995 11:11:51.392166 TX DQ/DQS : PASS
6996 11:11:51.395727 RX DATLAT : PASS
6997 11:11:51.398659 RX DQ/DQS(Engine): PASS
6998 11:11:51.398742 TX OE : NO K
6999 11:11:51.401968 All Pass.
7000 11:11:51.402050
7001 11:11:51.402115 CH 1, Rank 0
7002 11:11:51.405327 SW Impedance : PASS
7003 11:11:51.405409 DUTY Scan : NO K
7004 11:11:51.408399 ZQ Calibration : PASS
7005 11:11:51.411816 Jitter Meter : NO K
7006 11:11:51.411897 CBT Training : PASS
7007 11:11:51.414974 Write leveling : PASS
7008 11:11:51.418975 RX DQS gating : PASS
7009 11:11:51.419057 RX DQ/DQS(RDDQC) : PASS
7010 11:11:51.422081 TX DQ/DQS : PASS
7011 11:11:51.425186 RX DATLAT : PASS
7012 11:11:51.425311 RX DQ/DQS(Engine): PASS
7013 11:11:51.428281 TX OE : NO K
7014 11:11:51.428424 All Pass.
7015 11:11:51.428533
7016 11:11:51.431947 CH 1, Rank 1
7017 11:11:51.432066 SW Impedance : PASS
7018 11:11:51.435074 DUTY Scan : NO K
7019 11:11:51.438566 ZQ Calibration : PASS
7020 11:11:51.438687 Jitter Meter : NO K
7021 11:11:51.441974 CBT Training : PASS
7022 11:11:51.442093 Write leveling : NO K
7023 11:11:51.445213 RX DQS gating : PASS
7024 11:11:51.448500 RX DQ/DQS(RDDQC) : PASS
7025 11:11:51.448621 TX DQ/DQS : PASS
7026 11:11:51.451761 RX DATLAT : PASS
7027 11:11:51.455074 RX DQ/DQS(Engine): PASS
7028 11:11:51.455173 TX OE : NO K
7029 11:11:51.458630 All Pass.
7030 11:11:51.458729
7031 11:11:51.458818 DramC Write-DBI off
7032 11:11:51.461693 PER_BANK_REFRESH: Hybrid Mode
7033 11:11:51.461775 TX_TRACKING: ON
7034 11:11:51.471736 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7035 11:11:51.475050 [FAST_K] Save calibration result to emmc
7036 11:11:51.478761 dramc_set_vcore_voltage set vcore to 725000
7037 11:11:51.481789 Read voltage for 1600, 0
7038 11:11:51.481871 Vio18 = 0
7039 11:11:51.484980 Vcore = 725000
7040 11:11:51.485062 Vdram = 0
7041 11:11:51.485127 Vddq = 0
7042 11:11:51.488741 Vmddr = 0
7043 11:11:51.491806 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7044 11:11:51.498499 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7045 11:11:51.498581 MEM_TYPE=3, freq_sel=13
7046 11:11:51.501579 sv_algorithm_assistance_LP4_3733
7047 11:11:51.508599 ============ PULL DRAM RESETB DOWN ============
7048 11:11:51.511640 ========== PULL DRAM RESETB DOWN end =========
7049 11:11:51.515115 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7050 11:11:51.518146 ===================================
7051 11:11:51.521583 LPDDR4 DRAM CONFIGURATION
7052 11:11:51.525146 ===================================
7053 11:11:51.525229 EX_ROW_EN[0] = 0x0
7054 11:11:51.528211 EX_ROW_EN[1] = 0x0
7055 11:11:51.531684 LP4Y_EN = 0x0
7056 11:11:51.531766 WORK_FSP = 0x1
7057 11:11:51.534798 WL = 0x5
7058 11:11:51.534880 RL = 0x5
7059 11:11:51.538280 BL = 0x2
7060 11:11:51.538363 RPST = 0x0
7061 11:11:51.541930 RD_PRE = 0x0
7062 11:11:51.542011 WR_PRE = 0x1
7063 11:11:51.545068 WR_PST = 0x1
7064 11:11:51.545150 DBI_WR = 0x0
7065 11:11:51.548002 DBI_RD = 0x0
7066 11:11:51.548084 OTF = 0x1
7067 11:11:51.551719 ===================================
7068 11:11:51.554727 ===================================
7069 11:11:51.558259 ANA top config
7070 11:11:51.561921 ===================================
7071 11:11:51.562006 DLL_ASYNC_EN = 0
7072 11:11:51.565290 ALL_SLAVE_EN = 0
7073 11:11:51.568576 NEW_RANK_MODE = 1
7074 11:11:51.571516 DLL_IDLE_MODE = 1
7075 11:11:51.571598 LP45_APHY_COMB_EN = 1
7076 11:11:51.574708 TX_ODT_DIS = 0
7077 11:11:51.578482 NEW_8X_MODE = 1
7078 11:11:51.581565 ===================================
7079 11:11:51.584562 ===================================
7080 11:11:51.588398 data_rate = 3200
7081 11:11:51.591590 CKR = 1
7082 11:11:51.594768 DQ_P2S_RATIO = 8
7083 11:11:51.597972 ===================================
7084 11:11:51.598053 CA_P2S_RATIO = 8
7085 11:11:51.601564 DQ_CA_OPEN = 0
7086 11:11:51.604751 DQ_SEMI_OPEN = 0
7087 11:11:51.608470 CA_SEMI_OPEN = 0
7088 11:11:51.611619 CA_FULL_RATE = 0
7089 11:11:51.614680 DQ_CKDIV4_EN = 0
7090 11:11:51.614764 CA_CKDIV4_EN = 0
7091 11:11:51.617948 CA_PREDIV_EN = 0
7092 11:11:51.621101 PH8_DLY = 12
7093 11:11:51.624968 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7094 11:11:51.628115 DQ_AAMCK_DIV = 4
7095 11:11:51.631102 CA_AAMCK_DIV = 4
7096 11:11:51.631186 CA_ADMCK_DIV = 4
7097 11:11:51.634717 DQ_TRACK_CA_EN = 0
7098 11:11:51.638191 CA_PICK = 1600
7099 11:11:51.641130 CA_MCKIO = 1600
7100 11:11:51.644521 MCKIO_SEMI = 0
7101 11:11:51.647848 PLL_FREQ = 3068
7102 11:11:51.650898 DQ_UI_PI_RATIO = 32
7103 11:11:51.650981 CA_UI_PI_RATIO = 0
7104 11:11:51.654331 ===================================
7105 11:11:51.658123 ===================================
7106 11:11:51.661070 memory_type:LPDDR4
7107 11:11:51.664760 GP_NUM : 10
7108 11:11:51.664884 SRAM_EN : 1
7109 11:11:51.668150 MD32_EN : 0
7110 11:11:51.671317 ===================================
7111 11:11:51.674376 [ANA_INIT] >>>>>>>>>>>>>>
7112 11:11:51.677839 <<<<<< [CONFIGURE PHASE]: ANA_TX
7113 11:11:51.681137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7114 11:11:51.684278 ===================================
7115 11:11:51.684404 data_rate = 3200,PCW = 0X7600
7116 11:11:51.687768 ===================================
7117 11:11:51.691112 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7118 11:11:51.697714 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7119 11:11:51.704507 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7120 11:11:51.707592 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7121 11:11:51.711419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7122 11:11:51.714476 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7123 11:11:51.717572 [ANA_INIT] flow start
7124 11:11:51.720750 [ANA_INIT] PLL >>>>>>>>
7125 11:11:51.720831 [ANA_INIT] PLL <<<<<<<<
7126 11:11:51.724528 [ANA_INIT] MIDPI >>>>>>>>
7127 11:11:51.727738 [ANA_INIT] MIDPI <<<<<<<<
7128 11:11:51.727818 [ANA_INIT] DLL >>>>>>>>
7129 11:11:51.730885 [ANA_INIT] DLL <<<<<<<<
7130 11:11:51.734027 [ANA_INIT] flow end
7131 11:11:51.737692 ============ LP4 DIFF to SE enter ============
7132 11:11:51.740675 ============ LP4 DIFF to SE exit ============
7133 11:11:51.744438 [ANA_INIT] <<<<<<<<<<<<<
7134 11:11:51.747551 [Flow] Enable top DCM control >>>>>
7135 11:11:51.750743 [Flow] Enable top DCM control <<<<<
7136 11:11:51.753966 Enable DLL master slave shuffle
7137 11:11:51.757605 ==============================================================
7138 11:11:51.760687 Gating Mode config
7139 11:11:51.767158 ==============================================================
7140 11:11:51.767240 Config description:
7141 11:11:51.777427 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7142 11:11:51.784309 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7143 11:11:51.787494 SELPH_MODE 0: By rank 1: By Phase
7144 11:11:51.793871 ==============================================================
7145 11:11:51.797479 GAT_TRACK_EN = 1
7146 11:11:51.800980 RX_GATING_MODE = 2
7147 11:11:51.803954 RX_GATING_TRACK_MODE = 2
7148 11:11:51.807122 SELPH_MODE = 1
7149 11:11:51.810693 PICG_EARLY_EN = 1
7150 11:11:51.814008 VALID_LAT_VALUE = 1
7151 11:11:51.817422 ==============================================================
7152 11:11:51.820907 Enter into Gating configuration >>>>
7153 11:11:51.824065 Exit from Gating configuration <<<<
7154 11:11:51.827173 Enter into DVFS_PRE_config >>>>>
7155 11:11:51.837173 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7156 11:11:51.840877 Exit from DVFS_PRE_config <<<<<
7157 11:11:51.844005 Enter into PICG configuration >>>>
7158 11:11:51.846999 Exit from PICG configuration <<<<
7159 11:11:51.850162 [RX_INPUT] configuration >>>>>
7160 11:11:51.853874 [RX_INPUT] configuration <<<<<
7161 11:11:51.860176 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7162 11:11:51.863965 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7163 11:11:51.870253 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7164 11:11:51.877002 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7165 11:11:51.883170 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7166 11:11:51.890063 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7167 11:11:51.893130 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7168 11:11:51.897103 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7169 11:11:51.899830 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7170 11:11:51.906949 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7171 11:11:51.910080 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7172 11:11:51.913362 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7173 11:11:51.917030 ===================================
7174 11:11:51.919918 LPDDR4 DRAM CONFIGURATION
7175 11:11:51.923563 ===================================
7176 11:11:51.923646 EX_ROW_EN[0] = 0x0
7177 11:11:51.927000 EX_ROW_EN[1] = 0x0
7178 11:11:51.930115 LP4Y_EN = 0x0
7179 11:11:51.930196 WORK_FSP = 0x1
7180 11:11:51.933329 WL = 0x5
7181 11:11:51.933411 RL = 0x5
7182 11:11:51.936824 BL = 0x2
7183 11:11:51.936905 RPST = 0x0
7184 11:11:51.940062 RD_PRE = 0x0
7185 11:11:51.940145 WR_PRE = 0x1
7186 11:11:51.943454 WR_PST = 0x1
7187 11:11:51.943561 DBI_WR = 0x0
7188 11:11:51.946959 DBI_RD = 0x0
7189 11:11:51.947042 OTF = 0x1
7190 11:11:51.949791 ===================================
7191 11:11:51.953604 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7192 11:11:51.959882 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7193 11:11:51.963021 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7194 11:11:51.966733 ===================================
7195 11:11:51.969938 LPDDR4 DRAM CONFIGURATION
7196 11:11:51.972884 ===================================
7197 11:11:51.972968 EX_ROW_EN[0] = 0x10
7198 11:11:51.976161 EX_ROW_EN[1] = 0x0
7199 11:11:51.976244 LP4Y_EN = 0x0
7200 11:11:51.979864 WORK_FSP = 0x1
7201 11:11:51.979945 WL = 0x5
7202 11:11:51.983073 RL = 0x5
7203 11:11:51.986748 BL = 0x2
7204 11:11:51.986830 RPST = 0x0
7205 11:11:51.989965 RD_PRE = 0x0
7206 11:11:51.990047 WR_PRE = 0x1
7207 11:11:51.993104 WR_PST = 0x1
7208 11:11:51.993186 DBI_WR = 0x0
7209 11:11:51.996833 DBI_RD = 0x0
7210 11:11:51.996915 OTF = 0x1
7211 11:11:51.999999 ===================================
7212 11:11:52.006831 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7213 11:11:52.006914 ==
7214 11:11:52.010107 Dram Type= 6, Freq= 0, CH_0, rank 0
7215 11:11:52.013270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7216 11:11:52.013353 ==
7217 11:11:52.016789 [Duty_Offset_Calibration]
7218 11:11:52.016872 B0:2 B1:1 CA:1
7219 11:11:52.019610
7220 11:11:52.023340 [DutyScan_Calibration_Flow] k_type=0
7221 11:11:52.031523
7222 11:11:52.031605 ==CLK 0==
7223 11:11:52.034689 Final CLK duty delay cell = 0
7224 11:11:52.038130 [0] MAX Duty = 5156%(X100), DQS PI = 22
7225 11:11:52.041642 [0] MIN Duty = 4876%(X100), DQS PI = 48
7226 11:11:52.041725 [0] AVG Duty = 5016%(X100)
7227 11:11:52.045048
7228 11:11:52.045130 CH0 CLK Duty spec in!! Max-Min= 280%
7229 11:11:52.051765 [DutyScan_Calibration_Flow] ====Done====
7230 11:11:52.051848
7231 11:11:52.055029 [DutyScan_Calibration_Flow] k_type=1
7232 11:11:52.070746
7233 11:11:52.070828 ==DQS 0 ==
7234 11:11:52.073707 Final DQS duty delay cell = -4
7235 11:11:52.077384 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7236 11:11:52.080479 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7237 11:11:52.083602 [-4] AVG Duty = 4906%(X100)
7238 11:11:52.083684
7239 11:11:52.083749 ==DQS 1 ==
7240 11:11:52.087319 Final DQS duty delay cell = 0
7241 11:11:52.090418 [0] MAX Duty = 5187%(X100), DQS PI = 2
7242 11:11:52.093611 [0] MIN Duty = 5031%(X100), DQS PI = 54
7243 11:11:52.096794 [0] AVG Duty = 5109%(X100)
7244 11:11:52.096876
7245 11:11:52.100596 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7246 11:11:52.100679
7247 11:11:52.103690 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7248 11:11:52.106882 [DutyScan_Calibration_Flow] ====Done====
7249 11:11:52.106964
7250 11:11:52.110538 [DutyScan_Calibration_Flow] k_type=3
7251 11:11:52.128046
7252 11:11:52.128128 ==DQM 0 ==
7253 11:11:52.130989 Final DQM duty delay cell = 0
7254 11:11:52.134476 [0] MAX Duty = 5187%(X100), DQS PI = 26
7255 11:11:52.137896 [0] MIN Duty = 4907%(X100), DQS PI = 56
7256 11:11:52.141384 [0] AVG Duty = 5047%(X100)
7257 11:11:52.141482
7258 11:11:52.141562 ==DQM 1 ==
7259 11:11:52.144961 Final DQM duty delay cell = 0
7260 11:11:52.147964 [0] MAX Duty = 5187%(X100), DQS PI = 4
7261 11:11:52.151049 [0] MIN Duty = 5031%(X100), DQS PI = 50
7262 11:11:52.151132 [0] AVG Duty = 5109%(X100)
7263 11:11:52.154772
7264 11:11:52.157725 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7265 11:11:52.157808
7266 11:11:52.161566 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7267 11:11:52.164488 [DutyScan_Calibration_Flow] ====Done====
7268 11:11:52.164570
7269 11:11:52.167659 [DutyScan_Calibration_Flow] k_type=2
7270 11:11:52.184884
7271 11:11:52.184969 ==DQ 0 ==
7272 11:11:52.188795 Final DQ duty delay cell = 0
7273 11:11:52.191534 [0] MAX Duty = 5062%(X100), DQS PI = 26
7274 11:11:52.195069 [0] MIN Duty = 4907%(X100), DQS PI = 0
7275 11:11:52.195152 [0] AVG Duty = 4984%(X100)
7276 11:11:52.195216
7277 11:11:52.198541 ==DQ 1 ==
7278 11:11:52.201644 Final DQ duty delay cell = 0
7279 11:11:52.204891 [0] MAX Duty = 5125%(X100), DQS PI = 6
7280 11:11:52.208718 [0] MIN Duty = 4938%(X100), DQS PI = 32
7281 11:11:52.208827 [0] AVG Duty = 5031%(X100)
7282 11:11:52.208908
7283 11:11:52.211945 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7284 11:11:52.212027
7285 11:11:52.214989 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7286 11:11:52.221998 [DutyScan_Calibration_Flow] ====Done====
7287 11:11:52.222081 ==
7288 11:11:52.225081 Dram Type= 6, Freq= 0, CH_1, rank 0
7289 11:11:52.228238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7290 11:11:52.228347 ==
7291 11:11:52.231296 [Duty_Offset_Calibration]
7292 11:11:52.231378 B0:1 B1:0 CA:0
7293 11:11:52.231442
7294 11:11:52.234690 [DutyScan_Calibration_Flow] k_type=0
7295 11:11:52.244363
7296 11:11:52.244444 ==CLK 0==
7297 11:11:52.247545 Final CLK duty delay cell = -4
7298 11:11:52.251082 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7299 11:11:52.254468 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7300 11:11:52.257470 [-4] AVG Duty = 4906%(X100)
7301 11:11:52.257560
7302 11:11:52.260976 CH1 CLK Duty spec in!! Max-Min= 125%
7303 11:11:52.264480 [DutyScan_Calibration_Flow] ====Done====
7304 11:11:52.264562
7305 11:11:52.267377 [DutyScan_Calibration_Flow] k_type=1
7306 11:11:52.284634
7307 11:11:52.284715 ==DQS 0 ==
7308 11:11:52.287652 Final DQS duty delay cell = 0
7309 11:11:52.290753 [0] MAX Duty = 5094%(X100), DQS PI = 28
7310 11:11:52.294560 [0] MIN Duty = 4844%(X100), DQS PI = 50
7311 11:11:52.297863 [0] AVG Duty = 4969%(X100)
7312 11:11:52.297944
7313 11:11:52.298007 ==DQS 1 ==
7314 11:11:52.300831 Final DQS duty delay cell = 0
7315 11:11:52.304082 [0] MAX Duty = 5249%(X100), DQS PI = 16
7316 11:11:52.307892 [0] MIN Duty = 4969%(X100), DQS PI = 6
7317 11:11:52.311156 [0] AVG Duty = 5109%(X100)
7318 11:11:52.311237
7319 11:11:52.313981 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7320 11:11:52.314063
7321 11:11:52.317680 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7322 11:11:52.320791 [DutyScan_Calibration_Flow] ====Done====
7323 11:11:52.320873
7324 11:11:52.323903 [DutyScan_Calibration_Flow] k_type=3
7325 11:11:52.341244
7326 11:11:52.341325 ==DQM 0 ==
7327 11:11:52.344684 Final DQM duty delay cell = 0
7328 11:11:52.347825 [0] MAX Duty = 5218%(X100), DQS PI = 18
7329 11:11:52.350951 [0] MIN Duty = 4969%(X100), DQS PI = 48
7330 11:11:52.354527 [0] AVG Duty = 5093%(X100)
7331 11:11:52.354608
7332 11:11:52.354672 ==DQM 1 ==
7333 11:11:52.357692 Final DQM duty delay cell = 0
7334 11:11:52.361067 [0] MAX Duty = 5093%(X100), DQS PI = 16
7335 11:11:52.364604 [0] MIN Duty = 4907%(X100), DQS PI = 34
7336 11:11:52.367568 [0] AVG Duty = 5000%(X100)
7337 11:11:52.367649
7338 11:11:52.371224 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7339 11:11:52.371306
7340 11:11:52.374310 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7341 11:11:52.377828 [DutyScan_Calibration_Flow] ====Done====
7342 11:11:52.377910
7343 11:11:52.380687 [DutyScan_Calibration_Flow] k_type=2
7344 11:11:52.397786
7345 11:11:52.397866 ==DQ 0 ==
7346 11:11:52.401038 Final DQ duty delay cell = -4
7347 11:11:52.404155 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7348 11:11:52.407315 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7349 11:11:52.410448 [-4] AVG Duty = 4968%(X100)
7350 11:11:52.410529
7351 11:11:52.410592 ==DQ 1 ==
7352 11:11:52.414168 Final DQ duty delay cell = 0
7353 11:11:52.417513 [0] MAX Duty = 5125%(X100), DQS PI = 18
7354 11:11:52.420518 [0] MIN Duty = 4938%(X100), DQS PI = 10
7355 11:11:52.423755 [0] AVG Duty = 5031%(X100)
7356 11:11:52.423835
7357 11:11:52.427044 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7358 11:11:52.427124
7359 11:11:52.430873 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7360 11:11:52.434067 [DutyScan_Calibration_Flow] ====Done====
7361 11:11:52.437242 nWR fixed to 30
7362 11:11:52.440407 [ModeRegInit_LP4] CH0 RK0
7363 11:11:52.440513 [ModeRegInit_LP4] CH0 RK1
7364 11:11:52.444189 [ModeRegInit_LP4] CH1 RK0
7365 11:11:52.447190 [ModeRegInit_LP4] CH1 RK1
7366 11:11:52.447269 match AC timing 5
7367 11:11:52.453815 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7368 11:11:52.457297 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7369 11:11:52.460946 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7370 11:11:52.467160 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7371 11:11:52.470580 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7372 11:11:52.470701 [MiockJmeterHQA]
7373 11:11:52.470810
7374 11:11:52.474096 [DramcMiockJmeter] u1RxGatingPI = 0
7375 11:11:52.477024 0 : 4252, 4027
7376 11:11:52.477146 4 : 4253, 4026
7377 11:11:52.480742 8 : 4252, 4027
7378 11:11:52.480864 12 : 4253, 4026
7379 11:11:52.480978 16 : 4363, 4138
7380 11:11:52.483897 20 : 4363, 4137
7381 11:11:52.484018 24 : 4252, 4027
7382 11:11:52.487334 28 : 4252, 4027
7383 11:11:52.487459 32 : 4253, 4026
7384 11:11:52.490252 36 : 4363, 4138
7385 11:11:52.490372 40 : 4252, 4027
7386 11:11:52.493664 44 : 4363, 4138
7387 11:11:52.493801 48 : 4252, 4027
7388 11:11:52.493913 52 : 4252, 4027
7389 11:11:52.497137 56 : 4255, 4029
7390 11:11:52.497257 60 : 4252, 4029
7391 11:11:52.500168 64 : 4250, 4026
7392 11:11:52.500292 68 : 4252, 4030
7393 11:11:52.503352 72 : 4363, 4140
7394 11:11:52.503473 76 : 4250, 4027
7395 11:11:52.507077 80 : 4252, 4029
7396 11:11:52.507197 84 : 4250, 4026
7397 11:11:52.507310 88 : 4363, 125
7398 11:11:52.510155 92 : 4250, 0
7399 11:11:52.510276 96 : 4250, 0
7400 11:11:52.510387 100 : 4360, 0
7401 11:11:52.513969 104 : 4252, 0
7402 11:11:52.514088 108 : 4250, 0
7403 11:11:52.517099 112 : 4252, 0
7404 11:11:52.517222 116 : 4363, 0
7405 11:11:52.517334 120 : 4250, 0
7406 11:11:52.520146 124 : 4250, 0
7407 11:11:52.520268 128 : 4250, 0
7408 11:11:52.523907 132 : 4361, 0
7409 11:11:52.524028 136 : 4360, 0
7410 11:11:52.524138 140 : 4250, 0
7411 11:11:52.526933 144 : 4250, 0
7412 11:11:52.527054 148 : 4361, 0
7413 11:11:52.530507 152 : 4250, 0
7414 11:11:52.530627 156 : 4250, 0
7415 11:11:52.530738 160 : 4250, 0
7416 11:11:52.533969 164 : 4253, 0
7417 11:11:52.534090 168 : 4250, 0
7418 11:11:52.534203 172 : 4252, 0
7419 11:11:52.537096 176 : 4250, 0
7420 11:11:52.537218 180 : 4249, 0
7421 11:11:52.539966 184 : 4253, 0
7422 11:11:52.540089 188 : 4250, 0
7423 11:11:52.540202 192 : 4252, 0
7424 11:11:52.543907 196 : 4250, 0
7425 11:11:52.544028 200 : 4361, 0
7426 11:11:52.547047 204 : 4360, 1106
7427 11:11:52.547168 208 : 4363, 4110
7428 11:11:52.550221 212 : 4250, 4026
7429 11:11:52.550342 216 : 4250, 4027
7430 11:11:52.553279 220 : 4250, 4027
7431 11:11:52.553400 224 : 4252, 4029
7432 11:11:52.553513 228 : 4250, 4026
7433 11:11:52.557009 232 : 4250, 4027
7434 11:11:52.557130 236 : 4249, 4027
7435 11:11:52.560027 240 : 4252, 4029
7436 11:11:52.560149 244 : 4250, 4026
7437 11:11:52.563498 248 : 4361, 4137
7438 11:11:52.563618 252 : 4360, 4138
7439 11:11:52.566766 256 : 4250, 4027
7440 11:11:52.566871 260 : 4363, 4140
7441 11:11:52.570396 264 : 4250, 4026
7442 11:11:52.570496 268 : 4250, 4027
7443 11:11:52.573322 272 : 4249, 4027
7444 11:11:52.573404 276 : 4252, 4029
7445 11:11:52.576956 280 : 4250, 4026
7446 11:11:52.577037 284 : 4250, 4027
7447 11:11:52.577101 288 : 4249, 4027
7448 11:11:52.579980 292 : 4252, 4029
7449 11:11:52.580061 296 : 4250, 4026
7450 11:11:52.583588 300 : 4361, 4137
7451 11:11:52.583670 304 : 4360, 4138
7452 11:11:52.586682 308 : 4250, 3997
7453 11:11:52.586764 312 : 4363, 2142
7454 11:11:52.586828
7455 11:11:52.590143 MIOCK jitter meter ch=0
7456 11:11:52.590224
7457 11:11:52.593802 1T = (312-88) = 224 dly cells
7458 11:11:52.599905 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7459 11:11:52.600030 ==
7460 11:11:52.603164 Dram Type= 6, Freq= 0, CH_0, rank 0
7461 11:11:52.606668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7462 11:11:52.606790 ==
7463 11:11:52.613677 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7464 11:11:52.616953 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7465 11:11:52.620012 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7466 11:11:52.626868 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7467 11:11:52.635171 [CA 0] Center 42 (12~73) winsize 62
7468 11:11:52.638244 [CA 1] Center 42 (12~73) winsize 62
7469 11:11:52.641890 [CA 2] Center 37 (7~67) winsize 61
7470 11:11:52.645248 [CA 3] Center 37 (7~67) winsize 61
7471 11:11:52.648703 [CA 4] Center 36 (6~66) winsize 61
7472 11:11:52.651514 [CA 5] Center 35 (6~64) winsize 59
7473 11:11:52.651633
7474 11:11:52.655164 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7475 11:11:52.655283
7476 11:11:52.658381 [CATrainingPosCal] consider 1 rank data
7477 11:11:52.661608 u2DelayCellTimex100 = 290/100 ps
7478 11:11:52.665250 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7479 11:11:52.671375 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7480 11:11:52.674741 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7481 11:11:52.678121 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7482 11:11:52.681558 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7483 11:11:52.685117 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7484 11:11:52.685200
7485 11:11:52.688122 CA PerBit enable=1, Macro0, CA PI delay=35
7486 11:11:52.688255
7487 11:11:52.691874 [CBTSetCACLKResult] CA Dly = 35
7488 11:11:52.695008 CS Dly: 9 (0~40)
7489 11:11:52.697952 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7490 11:11:52.701606 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7491 11:11:52.701687 ==
7492 11:11:52.704979 Dram Type= 6, Freq= 0, CH_0, rank 1
7493 11:11:52.708007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7494 11:11:52.708112 ==
7495 11:11:52.715016 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7496 11:11:52.718291 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7497 11:11:52.725003 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7498 11:11:52.728156 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7499 11:11:52.738690 [CA 0] Center 42 (12~73) winsize 62
7500 11:11:52.741972 [CA 1] Center 42 (12~73) winsize 62
7501 11:11:52.745182 [CA 2] Center 38 (8~68) winsize 61
7502 11:11:52.748464 [CA 3] Center 37 (7~68) winsize 62
7503 11:11:52.751495 [CA 4] Center 35 (5~65) winsize 61
7504 11:11:52.755148 [CA 5] Center 35 (5~65) winsize 61
7505 11:11:52.755229
7506 11:11:52.757919 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7507 11:11:52.758000
7508 11:11:52.764523 [CATrainingPosCal] consider 2 rank data
7509 11:11:52.764604 u2DelayCellTimex100 = 290/100 ps
7510 11:11:52.771212 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7511 11:11:52.774430 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7512 11:11:52.777641 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7513 11:11:52.781221 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7514 11:11:52.784601 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7515 11:11:52.787594 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7516 11:11:52.787718
7517 11:11:52.791244 CA PerBit enable=1, Macro0, CA PI delay=35
7518 11:11:52.791364
7519 11:11:52.794748 [CBTSetCACLKResult] CA Dly = 35
7520 11:11:52.797624 CS Dly: 10 (0~42)
7521 11:11:52.801297 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7522 11:11:52.804592 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7523 11:11:52.804696
7524 11:11:52.807939 ----->DramcWriteLeveling(PI) begin...
7525 11:11:52.808021 ==
7526 11:11:52.810898 Dram Type= 6, Freq= 0, CH_0, rank 0
7527 11:11:52.817758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 11:11:52.817840 ==
7529 11:11:52.821385 Write leveling (Byte 0): 37 => 37
7530 11:11:52.821467 Write leveling (Byte 1): 29 => 29
7531 11:11:52.824523 DramcWriteLeveling(PI) end<-----
7532 11:11:52.824631
7533 11:11:52.827657 ==
7534 11:11:52.827737 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 11:11:52.834389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 11:11:52.834470 ==
7537 11:11:52.837831 [Gating] SW mode calibration
7538 11:11:52.844195 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7539 11:11:52.848047 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7540 11:11:52.854431 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7541 11:11:52.857539 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7542 11:11:52.861278 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7543 11:11:52.867416 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7544 11:11:52.870845 1 4 16 | B1->B0 | 2424 3636 | 1 0 | (1 1) (0 0)
7545 11:11:52.874236 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7546 11:11:52.880779 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7547 11:11:52.884053 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7548 11:11:52.887639 1 5 0 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7549 11:11:52.894480 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7550 11:11:52.897707 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7551 11:11:52.900816 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
7552 11:11:52.904419 1 5 16 | B1->B0 | 3333 2827 | 0 1 | (0 1) (0 0)
7553 11:11:52.911196 1 5 20 | B1->B0 | 2525 2525 | 0 0 | (1 0) (0 0)
7554 11:11:52.914413 1 5 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7555 11:11:52.917375 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7556 11:11:52.924401 1 6 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7557 11:11:52.927514 1 6 4 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7558 11:11:52.930684 1 6 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
7559 11:11:52.937399 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7560 11:11:52.940449 1 6 16 | B1->B0 | 2929 4646 | 0 0 | (1 1) (0 0)
7561 11:11:52.943964 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7562 11:11:52.950387 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 11:11:52.954161 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 11:11:52.957319 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 11:11:52.963602 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 11:11:52.967359 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7567 11:11:52.970486 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7568 11:11:52.976782 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7569 11:11:52.980437 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7570 11:11:52.983741 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 11:11:52.990552 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 11:11:52.993544 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 11:11:52.997208 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 11:11:53.003641 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 11:11:53.007199 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 11:11:53.010390 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 11:11:53.017192 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 11:11:53.020221 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 11:11:53.023467 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 11:11:53.030400 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 11:11:53.033441 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7582 11:11:53.037057 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 11:11:53.043831 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7584 11:11:53.047074 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7585 11:11:53.050492 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7586 11:11:53.053415 Total UI for P1: 0, mck2ui 16
7587 11:11:53.057030 best dqsien dly found for B0: ( 1, 9, 14)
7588 11:11:53.059998 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 11:11:53.063724 Total UI for P1: 0, mck2ui 16
7590 11:11:53.067045 best dqsien dly found for B1: ( 1, 9, 20)
7591 11:11:53.070128 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7592 11:11:53.077058 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7593 11:11:53.077141
7594 11:11:53.080054 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7595 11:11:53.083231 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7596 11:11:53.087032 [Gating] SW calibration Done
7597 11:11:53.087113 ==
7598 11:11:53.090179 Dram Type= 6, Freq= 0, CH_0, rank 0
7599 11:11:53.093593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7600 11:11:53.093675 ==
7601 11:11:53.097100 RX Vref Scan: 0
7602 11:11:53.097180
7603 11:11:53.097243 RX Vref 0 -> 0, step: 1
7604 11:11:53.097302
7605 11:11:53.100127 RX Delay 0 -> 252, step: 8
7606 11:11:53.103440 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7607 11:11:53.106728 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7608 11:11:53.113611 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7609 11:11:53.116859 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7610 11:11:53.119975 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7611 11:11:53.123082 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7612 11:11:53.126901 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7613 11:11:53.133584 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7614 11:11:53.136863 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7615 11:11:53.140011 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7616 11:11:53.143462 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7617 11:11:53.146652 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7618 11:11:53.153019 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7619 11:11:53.156618 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7620 11:11:53.159539 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7621 11:11:53.163178 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7622 11:11:53.163259 ==
7623 11:11:53.166226 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 11:11:53.173024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 11:11:53.173105 ==
7626 11:11:53.173169 DQS Delay:
7627 11:11:53.173227 DQS0 = 0, DQS1 = 0
7628 11:11:53.176714 DQM Delay:
7629 11:11:53.176820 DQM0 = 137, DQM1 = 129
7630 11:11:53.179833 DQ Delay:
7631 11:11:53.183087 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7632 11:11:53.186696 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7633 11:11:53.189836 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7634 11:11:53.193068 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7635 11:11:53.193149
7636 11:11:53.193212
7637 11:11:53.193270 ==
7638 11:11:53.196136 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 11:11:53.199746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 11:11:53.202980 ==
7641 11:11:53.203060
7642 11:11:53.203123
7643 11:11:53.203182 TX Vref Scan disable
7644 11:11:53.206100 == TX Byte 0 ==
7645 11:11:53.209771 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7646 11:11:53.213139 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7647 11:11:53.216475 == TX Byte 1 ==
7648 11:11:53.219910 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7649 11:11:53.223067 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7650 11:11:53.226347 ==
7651 11:11:53.226454 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 11:11:53.232754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 11:11:53.232838 ==
7654 11:11:53.244237
7655 11:11:53.247505 TX Vref early break, caculate TX vref
7656 11:11:53.251131 TX Vref=16, minBit 8, minWin=22, winSum=379
7657 11:11:53.254652 TX Vref=18, minBit 0, minWin=23, winSum=382
7658 11:11:53.257573 TX Vref=20, minBit 0, minWin=24, winSum=399
7659 11:11:53.261007 TX Vref=22, minBit 0, minWin=24, winSum=407
7660 11:11:53.264510 TX Vref=24, minBit 0, minWin=24, winSum=414
7661 11:11:53.270932 TX Vref=26, minBit 2, minWin=25, winSum=425
7662 11:11:53.274121 TX Vref=28, minBit 1, minWin=25, winSum=423
7663 11:11:53.277483 TX Vref=30, minBit 0, minWin=25, winSum=414
7664 11:11:53.281123 TX Vref=32, minBit 0, minWin=24, winSum=402
7665 11:11:53.287306 [TxChooseVref] Worse bit 2, Min win 25, Win sum 425, Final Vref 26
7666 11:11:53.287391
7667 11:11:53.291078 Final TX Range 0 Vref 26
7668 11:11:53.291162
7669 11:11:53.291246 ==
7670 11:11:53.294216 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 11:11:53.297426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 11:11:53.297510 ==
7673 11:11:53.297594
7674 11:11:53.297674
7675 11:11:53.301193 TX Vref Scan disable
7676 11:11:53.304314 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7677 11:11:53.307478 == TX Byte 0 ==
7678 11:11:53.310635 u2DelayCellOfst[0]=10 cells (3 PI)
7679 11:11:53.314476 u2DelayCellOfst[1]=13 cells (4 PI)
7680 11:11:53.317622 u2DelayCellOfst[2]=6 cells (2 PI)
7681 11:11:53.321318 u2DelayCellOfst[3]=6 cells (2 PI)
7682 11:11:53.321401 u2DelayCellOfst[4]=6 cells (2 PI)
7683 11:11:53.324092 u2DelayCellOfst[5]=0 cells (0 PI)
7684 11:11:53.327605 u2DelayCellOfst[6]=16 cells (5 PI)
7685 11:11:53.331038 u2DelayCellOfst[7]=13 cells (4 PI)
7686 11:11:53.334427 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7687 11:11:53.340784 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7688 11:11:53.340867 == TX Byte 1 ==
7689 11:11:53.344422 u2DelayCellOfst[8]=3 cells (1 PI)
7690 11:11:53.347487 u2DelayCellOfst[9]=0 cells (0 PI)
7691 11:11:53.351101 u2DelayCellOfst[10]=6 cells (2 PI)
7692 11:11:53.354612 u2DelayCellOfst[11]=3 cells (1 PI)
7693 11:11:53.357684 u2DelayCellOfst[12]=10 cells (3 PI)
7694 11:11:53.361240 u2DelayCellOfst[13]=10 cells (3 PI)
7695 11:11:53.364497 u2DelayCellOfst[14]=13 cells (4 PI)
7696 11:11:53.367378 u2DelayCellOfst[15]=10 cells (3 PI)
7697 11:11:53.371194 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7698 11:11:53.374344 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7699 11:11:53.377972 DramC Write-DBI on
7700 11:11:53.378055 ==
7701 11:11:53.380855 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 11:11:53.384069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 11:11:53.384152 ==
7704 11:11:53.384252
7705 11:11:53.384391
7706 11:11:53.387522 TX Vref Scan disable
7707 11:11:53.390967 == TX Byte 0 ==
7708 11:11:53.394500 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7709 11:11:53.394583 == TX Byte 1 ==
7710 11:11:53.400815 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7711 11:11:53.400917 DramC Write-DBI off
7712 11:11:53.401001
7713 11:11:53.401079 [DATLAT]
7714 11:11:53.403955 Freq=1600, CH0 RK0
7715 11:11:53.404056
7716 11:11:53.407764 DATLAT Default: 0xf
7717 11:11:53.407847 0, 0xFFFF, sum = 0
7718 11:11:53.411016 1, 0xFFFF, sum = 0
7719 11:11:53.411103 2, 0xFFFF, sum = 0
7720 11:11:53.414209 3, 0xFFFF, sum = 0
7721 11:11:53.414319 4, 0xFFFF, sum = 0
7722 11:11:53.417358 5, 0xFFFF, sum = 0
7723 11:11:53.417443 6, 0xFFFF, sum = 0
7724 11:11:53.421109 7, 0xFFFF, sum = 0
7725 11:11:53.421193 8, 0xFFFF, sum = 0
7726 11:11:53.424231 9, 0xFFFF, sum = 0
7727 11:11:53.424368 10, 0xFFFF, sum = 0
7728 11:11:53.427417 11, 0xFFFF, sum = 0
7729 11:11:53.427500 12, 0xFFFF, sum = 0
7730 11:11:53.430960 13, 0xFFFF, sum = 0
7731 11:11:53.431044 14, 0x0, sum = 1
7732 11:11:53.434129 15, 0x0, sum = 2
7733 11:11:53.434214 16, 0x0, sum = 3
7734 11:11:53.437731 17, 0x0, sum = 4
7735 11:11:53.437813 best_step = 15
7736 11:11:53.437876
7737 11:11:53.437934 ==
7738 11:11:53.440737 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 11:11:53.447390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 11:11:53.447486 ==
7741 11:11:53.447599 RX Vref Scan: 1
7742 11:11:53.447658
7743 11:11:53.450677 Set Vref Range= 24 -> 127
7744 11:11:53.450757
7745 11:11:53.453951 RX Vref 24 -> 127, step: 1
7746 11:11:53.454032
7747 11:11:53.457374 RX Delay 19 -> 252, step: 4
7748 11:11:53.457460
7749 11:11:53.460902 Set Vref, RX VrefLevel [Byte0]: 24
7750 11:11:53.461027 [Byte1]: 24
7751 11:11:53.464897
7752 11:11:53.465017 Set Vref, RX VrefLevel [Byte0]: 25
7753 11:11:53.468041 [Byte1]: 25
7754 11:11:53.472213
7755 11:11:53.472373 Set Vref, RX VrefLevel [Byte0]: 26
7756 11:11:53.475966 [Byte1]: 26
7757 11:11:53.480371
7758 11:11:53.480491 Set Vref, RX VrefLevel [Byte0]: 27
7759 11:11:53.483566 [Byte1]: 27
7760 11:11:53.487390
7761 11:11:53.487511 Set Vref, RX VrefLevel [Byte0]: 28
7762 11:11:53.490924 [Byte1]: 28
7763 11:11:53.495349
7764 11:11:53.495467 Set Vref, RX VrefLevel [Byte0]: 29
7765 11:11:53.498394 [Byte1]: 29
7766 11:11:53.502626
7767 11:11:53.502746 Set Vref, RX VrefLevel [Byte0]: 30
7768 11:11:53.505921 [Byte1]: 30
7769 11:11:53.510294
7770 11:11:53.510396 Set Vref, RX VrefLevel [Byte0]: 31
7771 11:11:53.513621 [Byte1]: 31
7772 11:11:53.518039
7773 11:11:53.518120 Set Vref, RX VrefLevel [Byte0]: 32
7774 11:11:53.521036 [Byte1]: 32
7775 11:11:53.525507
7776 11:11:53.525587 Set Vref, RX VrefLevel [Byte0]: 33
7777 11:11:53.528644 [Byte1]: 33
7778 11:11:53.532997
7779 11:11:53.533086 Set Vref, RX VrefLevel [Byte0]: 34
7780 11:11:53.536575 [Byte1]: 34
7781 11:11:53.540972
7782 11:11:53.541069 Set Vref, RX VrefLevel [Byte0]: 35
7783 11:11:53.544033 [Byte1]: 35
7784 11:11:53.548589
7785 11:11:53.548695 Set Vref, RX VrefLevel [Byte0]: 36
7786 11:11:53.551763 [Byte1]: 36
7787 11:11:53.556063
7788 11:11:53.556162 Set Vref, RX VrefLevel [Byte0]: 37
7789 11:11:53.559122 [Byte1]: 37
7790 11:11:53.563493
7791 11:11:53.563579 Set Vref, RX VrefLevel [Byte0]: 38
7792 11:11:53.566679 [Byte1]: 38
7793 11:11:53.571134
7794 11:11:53.571261 Set Vref, RX VrefLevel [Byte0]: 39
7795 11:11:53.574375 [Byte1]: 39
7796 11:11:53.578733
7797 11:11:53.578866 Set Vref, RX VrefLevel [Byte0]: 40
7798 11:11:53.582258 [Byte1]: 40
7799 11:11:53.585966
7800 11:11:53.586087 Set Vref, RX VrefLevel [Byte0]: 41
7801 11:11:53.589141 [Byte1]: 41
7802 11:11:53.593474
7803 11:11:53.593604 Set Vref, RX VrefLevel [Byte0]: 42
7804 11:11:53.597236 [Byte1]: 42
7805 11:11:53.600987
7806 11:11:53.601085 Set Vref, RX VrefLevel [Byte0]: 43
7807 11:11:53.604200 [Byte1]: 43
7808 11:11:53.608621
7809 11:11:53.608706 Set Vref, RX VrefLevel [Byte0]: 44
7810 11:11:53.612506 [Byte1]: 44
7811 11:11:53.616666
7812 11:11:53.616757 Set Vref, RX VrefLevel [Byte0]: 45
7813 11:11:53.619476 [Byte1]: 45
7814 11:11:53.624019
7815 11:11:53.624111 Set Vref, RX VrefLevel [Byte0]: 46
7816 11:11:53.627424 [Byte1]: 46
7817 11:11:53.631798
7818 11:11:53.631892 Set Vref, RX VrefLevel [Byte0]: 47
7819 11:11:53.635056 [Byte1]: 47
7820 11:11:53.639401
7821 11:11:53.639493 Set Vref, RX VrefLevel [Byte0]: 48
7822 11:11:53.642354 [Byte1]: 48
7823 11:11:53.646731
7824 11:11:53.646818 Set Vref, RX VrefLevel [Byte0]: 49
7825 11:11:53.649837 [Byte1]: 49
7826 11:11:53.654488
7827 11:11:53.654582 Set Vref, RX VrefLevel [Byte0]: 50
7828 11:11:53.657699 [Byte1]: 50
7829 11:11:53.661592
7830 11:11:53.661676 Set Vref, RX VrefLevel [Byte0]: 51
7831 11:11:53.665355 [Byte1]: 51
7832 11:11:53.669718
7833 11:11:53.669844 Set Vref, RX VrefLevel [Byte0]: 52
7834 11:11:53.672991 [Byte1]: 52
7835 11:11:53.677135
7836 11:11:53.677233 Set Vref, RX VrefLevel [Byte0]: 53
7837 11:11:53.680540 [Byte1]: 53
7838 11:11:53.684506
7839 11:11:53.684611 Set Vref, RX VrefLevel [Byte0]: 54
7840 11:11:53.687980 [Byte1]: 54
7841 11:11:53.692051
7842 11:11:53.692168 Set Vref, RX VrefLevel [Byte0]: 55
7843 11:11:53.695404 [Byte1]: 55
7844 11:11:53.699494
7845 11:11:53.699577 Set Vref, RX VrefLevel [Byte0]: 56
7846 11:11:53.703381 [Byte1]: 56
7847 11:11:53.707279
7848 11:11:53.707367 Set Vref, RX VrefLevel [Byte0]: 57
7849 11:11:53.710517 [Byte1]: 57
7850 11:11:53.714845
7851 11:11:53.714934 Set Vref, RX VrefLevel [Byte0]: 58
7852 11:11:53.718000 [Byte1]: 58
7853 11:11:53.722401
7854 11:11:53.722524 Set Vref, RX VrefLevel [Byte0]: 59
7855 11:11:53.726121 [Byte1]: 59
7856 11:11:53.730450
7857 11:11:53.730535 Set Vref, RX VrefLevel [Byte0]: 60
7858 11:11:53.733107 [Byte1]: 60
7859 11:11:53.737753
7860 11:11:53.737877 Set Vref, RX VrefLevel [Byte0]: 61
7861 11:11:53.740758 [Byte1]: 61
7862 11:11:53.745060
7863 11:11:53.745182 Set Vref, RX VrefLevel [Byte0]: 62
7864 11:11:53.748748 [Byte1]: 62
7865 11:11:53.753032
7866 11:11:53.753157 Set Vref, RX VrefLevel [Byte0]: 63
7867 11:11:53.755981 [Byte1]: 63
7868 11:11:53.760196
7869 11:11:53.760350 Set Vref, RX VrefLevel [Byte0]: 64
7870 11:11:53.763333 [Byte1]: 64
7871 11:11:53.767680
7872 11:11:53.767800 Set Vref, RX VrefLevel [Byte0]: 65
7873 11:11:53.771417 [Byte1]: 65
7874 11:11:53.775150
7875 11:11:53.775272 Set Vref, RX VrefLevel [Byte0]: 66
7876 11:11:53.778955 [Byte1]: 66
7877 11:11:53.783253
7878 11:11:53.783372 Set Vref, RX VrefLevel [Byte0]: 67
7879 11:11:53.786356 [Byte1]: 67
7880 11:11:53.790969
7881 11:11:53.791050 Set Vref, RX VrefLevel [Byte0]: 68
7882 11:11:53.794042 [Byte1]: 68
7883 11:11:53.798086
7884 11:11:53.798166 Set Vref, RX VrefLevel [Byte0]: 69
7885 11:11:53.801411 [Byte1]: 69
7886 11:11:53.805901
7887 11:11:53.806018 Set Vref, RX VrefLevel [Byte0]: 70
7888 11:11:53.808882 [Byte1]: 70
7889 11:11:53.813276
7890 11:11:53.813366 Set Vref, RX VrefLevel [Byte0]: 71
7891 11:11:53.816543 [Byte1]: 71
7892 11:11:53.820978
7893 11:11:53.821132 Set Vref, RX VrefLevel [Byte0]: 72
7894 11:11:53.824038 [Byte1]: 72
7895 11:11:53.828751
7896 11:11:53.828835 Set Vref, RX VrefLevel [Byte0]: 73
7897 11:11:53.831674 [Byte1]: 73
7898 11:11:53.836191
7899 11:11:53.836275 Set Vref, RX VrefLevel [Byte0]: 74
7900 11:11:53.839181 [Byte1]: 74
7901 11:11:53.843992
7902 11:11:53.844074 Set Vref, RX VrefLevel [Byte0]: 75
7903 11:11:53.846933 [Byte1]: 75
7904 11:11:53.851079
7905 11:11:53.851160 Set Vref, RX VrefLevel [Byte0]: 76
7906 11:11:53.854695 [Byte1]: 76
7907 11:11:53.858961
7908 11:11:53.859043 Final RX Vref Byte 0 = 56 to rank0
7909 11:11:53.861990 Final RX Vref Byte 1 = 59 to rank0
7910 11:11:53.865464 Final RX Vref Byte 0 = 56 to rank1
7911 11:11:53.868471 Final RX Vref Byte 1 = 59 to rank1==
7912 11:11:53.872339 Dram Type= 6, Freq= 0, CH_0, rank 0
7913 11:11:53.878679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7914 11:11:53.878762 ==
7915 11:11:53.878828 DQS Delay:
7916 11:11:53.878888 DQS0 = 0, DQS1 = 0
7917 11:11:53.881729 DQM Delay:
7918 11:11:53.881810 DQM0 = 133, DQM1 = 127
7919 11:11:53.885552 DQ Delay:
7920 11:11:53.888686 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =132
7921 11:11:53.891804 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7922 11:11:53.895397 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7923 11:11:53.898642 DQ12 =130, DQ13 =134, DQ14 =138, DQ15 =134
7924 11:11:53.898723
7925 11:11:53.898786
7926 11:11:53.898844
7927 11:11:53.901764 [DramC_TX_OE_Calibration] TA2
7928 11:11:53.905500 Original DQ_B0 (3 6) =30, OEN = 27
7929 11:11:53.908435 Original DQ_B1 (3 6) =30, OEN = 27
7930 11:11:53.911978 24, 0x0, End_B0=24 End_B1=24
7931 11:11:53.912060 25, 0x0, End_B0=25 End_B1=25
7932 11:11:53.915045 26, 0x0, End_B0=26 End_B1=26
7933 11:11:53.918158 27, 0x0, End_B0=27 End_B1=27
7934 11:11:53.921660 28, 0x0, End_B0=28 End_B1=28
7935 11:11:53.925032 29, 0x0, End_B0=29 End_B1=29
7936 11:11:53.925115 30, 0x0, End_B0=30 End_B1=30
7937 11:11:53.928649 31, 0x4141, End_B0=30 End_B1=30
7938 11:11:53.931798 Byte0 end_step=30 best_step=27
7939 11:11:53.934849 Byte1 end_step=30 best_step=27
7940 11:11:53.938799 Byte0 TX OE(2T, 0.5T) = (3, 3)
7941 11:11:53.941483 Byte1 TX OE(2T, 0.5T) = (3, 3)
7942 11:11:53.941564
7943 11:11:53.941627
7944 11:11:53.948247 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7945 11:11:53.951724 CH0 RK0: MR19=303, MR18=2420
7946 11:11:53.958576 CH0_RK0: MR19=0x303, MR18=0x2420, DQSOSC=391, MR23=63, INC=24, DEC=16
7947 11:11:53.958657
7948 11:11:53.961785 ----->DramcWriteLeveling(PI) begin...
7949 11:11:53.961868 ==
7950 11:11:53.965144 Dram Type= 6, Freq= 0, CH_0, rank 1
7951 11:11:53.968090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7952 11:11:53.968172 ==
7953 11:11:53.971682 Write leveling (Byte 0): 36 => 36
7954 11:11:53.974722 Write leveling (Byte 1): 27 => 27
7955 11:11:53.978432 DramcWriteLeveling(PI) end<-----
7956 11:11:53.978513
7957 11:11:53.978576 ==
7958 11:11:53.981729 Dram Type= 6, Freq= 0, CH_0, rank 1
7959 11:11:53.984875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7960 11:11:53.984957 ==
7961 11:11:53.987932 [Gating] SW mode calibration
7962 11:11:53.994877 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7963 11:11:54.001237 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7964 11:11:54.005010 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7965 11:11:54.008149 1 4 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7966 11:11:54.014704 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7967 11:11:54.018202 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7968 11:11:54.021338 1 4 16 | B1->B0 | 302f 3535 | 1 1 | (0 0) (0 0)
7969 11:11:54.028294 1 4 20 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7970 11:11:54.031421 1 4 24 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7971 11:11:54.034437 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7972 11:11:54.041182 1 5 0 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)
7973 11:11:54.045051 1 5 4 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7974 11:11:54.048012 1 5 8 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
7975 11:11:54.054570 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
7976 11:11:54.057977 1 5 16 | B1->B0 | 3131 2727 | 0 0 | (0 1) (1 0)
7977 11:11:54.061133 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7978 11:11:54.067783 1 5 24 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7979 11:11:54.071064 1 5 28 | B1->B0 | 2323 2726 | 0 1 | (0 0) (1 1)
7980 11:11:54.074353 1 6 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7981 11:11:54.081394 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 11:11:54.084828 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7983 11:11:54.087726 1 6 12 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
7984 11:11:54.094586 1 6 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7985 11:11:54.097792 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7986 11:11:54.101565 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 11:11:54.107742 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7988 11:11:54.111433 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 11:11:54.114408 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7990 11:11:54.121213 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 11:11:54.124708 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7992 11:11:54.127583 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7993 11:11:54.131294 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 11:11:54.137550 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 11:11:54.141108 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 11:11:54.144535 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 11:11:54.151436 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 11:11:54.154741 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 11:11:54.157722 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 11:11:54.164468 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 11:11:54.167434 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 11:11:54.171106 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 11:11:54.177318 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 11:11:54.181041 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 11:11:54.184000 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 11:11:54.190820 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 11:11:54.194001 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8008 11:11:54.197354 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8009 11:11:54.203989 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 11:11:54.204071 Total UI for P1: 0, mck2ui 16
8011 11:11:54.210633 best dqsien dly found for B0: ( 1, 9, 16)
8012 11:11:54.210715 Total UI for P1: 0, mck2ui 16
8013 11:11:54.217506 best dqsien dly found for B1: ( 1, 9, 14)
8014 11:11:54.220480 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8015 11:11:54.224179 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8016 11:11:54.224292
8017 11:11:54.227485 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8018 11:11:54.230610 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8019 11:11:54.234088 [Gating] SW calibration Done
8020 11:11:54.234168 ==
8021 11:11:54.237470 Dram Type= 6, Freq= 0, CH_0, rank 1
8022 11:11:54.240536 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8023 11:11:54.240618 ==
8024 11:11:54.243756 RX Vref Scan: 0
8025 11:11:54.243837
8026 11:11:54.243901 RX Vref 0 -> 0, step: 1
8027 11:11:54.243960
8028 11:11:54.247434 RX Delay 0 -> 252, step: 8
8029 11:11:54.250954 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8030 11:11:54.257415 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8031 11:11:54.261062 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8032 11:11:54.264263 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8033 11:11:54.267405 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8034 11:11:54.270463 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8035 11:11:54.277372 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8036 11:11:54.280756 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8037 11:11:54.283842 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8038 11:11:54.286993 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8039 11:11:54.290707 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8040 11:11:54.296977 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8041 11:11:54.300698 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8042 11:11:54.303995 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8043 11:11:54.307307 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8044 11:11:54.310211 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8045 11:11:54.313655 ==
8046 11:11:54.316831 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 11:11:54.320551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 11:11:54.320632 ==
8049 11:11:54.320695 DQS Delay:
8050 11:11:54.323523 DQS0 = 0, DQS1 = 0
8051 11:11:54.323604 DQM Delay:
8052 11:11:54.327209 DQM0 = 137, DQM1 = 128
8053 11:11:54.327289 DQ Delay:
8054 11:11:54.330260 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8055 11:11:54.333463 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8056 11:11:54.337250 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8057 11:11:54.340214 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8058 11:11:54.340360
8059 11:11:54.340452
8060 11:11:54.340538 ==
8061 11:11:54.343889 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 11:11:54.350458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 11:11:54.350539 ==
8064 11:11:54.350603
8065 11:11:54.350661
8066 11:11:54.350721 TX Vref Scan disable
8067 11:11:54.354100 == TX Byte 0 ==
8068 11:11:54.357248 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8069 11:11:54.363844 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8070 11:11:54.363925 == TX Byte 1 ==
8071 11:11:54.367161 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8072 11:11:54.370351 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8073 11:11:54.374186 ==
8074 11:11:54.377263 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 11:11:54.380427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 11:11:54.380510 ==
8077 11:11:54.394063
8078 11:11:54.397108 TX Vref early break, caculate TX vref
8079 11:11:54.400293 TX Vref=16, minBit 3, minWin=22, winSum=383
8080 11:11:54.403515 TX Vref=18, minBit 0, minWin=24, winSum=401
8081 11:11:54.407115 TX Vref=20, minBit 0, minWin=24, winSum=403
8082 11:11:54.410263 TX Vref=22, minBit 3, minWin=24, winSum=411
8083 11:11:54.413805 TX Vref=24, minBit 1, minWin=24, winSum=417
8084 11:11:54.420241 TX Vref=26, minBit 3, minWin=25, winSum=428
8085 11:11:54.423374 TX Vref=28, minBit 4, minWin=25, winSum=422
8086 11:11:54.426663 TX Vref=30, minBit 0, minWin=25, winSum=414
8087 11:11:54.430051 TX Vref=32, minBit 1, minWin=25, winSum=407
8088 11:11:54.433384 TX Vref=34, minBit 0, minWin=24, winSum=399
8089 11:11:54.440023 [TxChooseVref] Worse bit 3, Min win 25, Win sum 428, Final Vref 26
8090 11:11:54.440106
8091 11:11:54.443424 Final TX Range 0 Vref 26
8092 11:11:54.443506
8093 11:11:54.443569 ==
8094 11:11:54.446944 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 11:11:54.450487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 11:11:54.450569 ==
8097 11:11:54.450634
8098 11:11:54.450693
8099 11:11:54.453669 TX Vref Scan disable
8100 11:11:54.460024 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8101 11:11:54.460192 == TX Byte 0 ==
8102 11:11:54.463661 u2DelayCellOfst[0]=16 cells (5 PI)
8103 11:11:54.466732 u2DelayCellOfst[1]=16 cells (5 PI)
8104 11:11:54.470279 u2DelayCellOfst[2]=13 cells (4 PI)
8105 11:11:54.473640 u2DelayCellOfst[3]=13 cells (4 PI)
8106 11:11:54.477111 u2DelayCellOfst[4]=10 cells (3 PI)
8107 11:11:54.480233 u2DelayCellOfst[5]=0 cells (0 PI)
8108 11:11:54.483355 u2DelayCellOfst[6]=16 cells (5 PI)
8109 11:11:54.487268 u2DelayCellOfst[7]=16 cells (5 PI)
8110 11:11:54.490385 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8111 11:11:54.493445 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8112 11:11:54.497005 == TX Byte 1 ==
8113 11:11:54.497086 u2DelayCellOfst[8]=3 cells (1 PI)
8114 11:11:54.500498 u2DelayCellOfst[9]=0 cells (0 PI)
8115 11:11:54.503688 u2DelayCellOfst[10]=6 cells (2 PI)
8116 11:11:54.506901 u2DelayCellOfst[11]=6 cells (2 PI)
8117 11:11:54.510063 u2DelayCellOfst[12]=10 cells (3 PI)
8118 11:11:54.513739 u2DelayCellOfst[13]=10 cells (3 PI)
8119 11:11:54.516887 u2DelayCellOfst[14]=13 cells (4 PI)
8120 11:11:54.520427 u2DelayCellOfst[15]=10 cells (3 PI)
8121 11:11:54.523615 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8122 11:11:54.529916 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8123 11:11:54.529997 DramC Write-DBI on
8124 11:11:54.530060 ==
8125 11:11:54.533778 Dram Type= 6, Freq= 0, CH_0, rank 1
8126 11:11:54.536919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8127 11:11:54.540156 ==
8128 11:11:54.540237
8129 11:11:54.540329
8130 11:11:54.540402 TX Vref Scan disable
8131 11:11:54.543989 == TX Byte 0 ==
8132 11:11:54.546991 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8133 11:11:54.550068 == TX Byte 1 ==
8134 11:11:54.553324 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8135 11:11:54.556772 DramC Write-DBI off
8136 11:11:54.556891
8137 11:11:54.557003 [DATLAT]
8138 11:11:54.557105 Freq=1600, CH0 RK1
8139 11:11:54.557209
8140 11:11:54.560110 DATLAT Default: 0xf
8141 11:11:54.560230 0, 0xFFFF, sum = 0
8142 11:11:54.563205 1, 0xFFFF, sum = 0
8143 11:11:54.566332 2, 0xFFFF, sum = 0
8144 11:11:54.566468 3, 0xFFFF, sum = 0
8145 11:11:54.569903 4, 0xFFFF, sum = 0
8146 11:11:54.570025 5, 0xFFFF, sum = 0
8147 11:11:54.573431 6, 0xFFFF, sum = 0
8148 11:11:54.573553 7, 0xFFFF, sum = 0
8149 11:11:54.576894 8, 0xFFFF, sum = 0
8150 11:11:54.577016 9, 0xFFFF, sum = 0
8151 11:11:54.580074 10, 0xFFFF, sum = 0
8152 11:11:54.580199 11, 0xFFFF, sum = 0
8153 11:11:54.583177 12, 0xFFFF, sum = 0
8154 11:11:54.583301 13, 0xFFFF, sum = 0
8155 11:11:54.586584 14, 0x0, sum = 1
8156 11:11:54.586720 15, 0x0, sum = 2
8157 11:11:54.589917 16, 0x0, sum = 3
8158 11:11:54.589998 17, 0x0, sum = 4
8159 11:11:54.593414 best_step = 15
8160 11:11:54.593494
8161 11:11:54.593557 ==
8162 11:11:54.596600 Dram Type= 6, Freq= 0, CH_0, rank 1
8163 11:11:54.599650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8164 11:11:54.599731 ==
8165 11:11:54.603370 RX Vref Scan: 0
8166 11:11:54.603449
8167 11:11:54.603512 RX Vref 0 -> 0, step: 1
8168 11:11:54.603570
8169 11:11:54.606823 RX Delay 19 -> 252, step: 4
8170 11:11:54.609657 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8171 11:11:54.616602 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8172 11:11:54.619655 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8173 11:11:54.623127 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8174 11:11:54.626113 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8175 11:11:54.630033 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8176 11:11:54.636134 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8177 11:11:54.639942 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8178 11:11:54.643129 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8179 11:11:54.646229 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8180 11:11:54.649333 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8181 11:11:54.656304 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8182 11:11:54.659386 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8183 11:11:54.662605 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8184 11:11:54.666273 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8185 11:11:54.669805 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8186 11:11:54.672638 ==
8187 11:11:54.676249 Dram Type= 6, Freq= 0, CH_0, rank 1
8188 11:11:54.679368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8189 11:11:54.679449 ==
8190 11:11:54.679513 DQS Delay:
8191 11:11:54.683083 DQS0 = 0, DQS1 = 0
8192 11:11:54.683165 DQM Delay:
8193 11:11:54.686191 DQM0 = 134, DQM1 = 127
8194 11:11:54.686272 DQ Delay:
8195 11:11:54.689740 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8196 11:11:54.692740 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =142
8197 11:11:54.696004 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8198 11:11:54.699634 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8199 11:11:54.699714
8200 11:11:54.699777
8201 11:11:54.699835
8202 11:11:54.702621 [DramC_TX_OE_Calibration] TA2
8203 11:11:54.706237 Original DQ_B0 (3 6) =30, OEN = 27
8204 11:11:54.709592 Original DQ_B1 (3 6) =30, OEN = 27
8205 11:11:54.712704 24, 0x0, End_B0=24 End_B1=24
8206 11:11:54.716219 25, 0x0, End_B0=25 End_B1=25
8207 11:11:54.716312 26, 0x0, End_B0=26 End_B1=26
8208 11:11:54.719406 27, 0x0, End_B0=27 End_B1=27
8209 11:11:54.722788 28, 0x0, End_B0=28 End_B1=28
8210 11:11:54.726612 29, 0x0, End_B0=29 End_B1=29
8211 11:11:54.726696 30, 0x0, End_B0=30 End_B1=30
8212 11:11:54.729110 31, 0x4141, End_B0=30 End_B1=30
8213 11:11:54.732795 Byte0 end_step=30 best_step=27
8214 11:11:54.736084 Byte1 end_step=30 best_step=27
8215 11:11:54.739142 Byte0 TX OE(2T, 0.5T) = (3, 3)
8216 11:11:54.743012 Byte1 TX OE(2T, 0.5T) = (3, 3)
8217 11:11:54.743093
8218 11:11:54.743156
8219 11:11:54.749236 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8220 11:11:54.752421 CH0 RK1: MR19=303, MR18=2008
8221 11:11:54.759321 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8222 11:11:54.762469 [RxdqsGatingPostProcess] freq 1600
8223 11:11:54.769389 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8224 11:11:54.769473 best DQS0 dly(2T, 0.5T) = (1, 1)
8225 11:11:54.772558 best DQS1 dly(2T, 0.5T) = (1, 1)
8226 11:11:54.775634 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8227 11:11:54.779195 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8228 11:11:54.782136 best DQS0 dly(2T, 0.5T) = (1, 1)
8229 11:11:54.785630 best DQS1 dly(2T, 0.5T) = (1, 1)
8230 11:11:54.789341 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8231 11:11:54.792344 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8232 11:11:54.795553 Pre-setting of DQS Precalculation
8233 11:11:54.799286 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8234 11:11:54.799368 ==
8235 11:11:54.802556 Dram Type= 6, Freq= 0, CH_1, rank 0
8236 11:11:54.808891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8237 11:11:54.808974 ==
8238 11:11:54.812455 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8239 11:11:54.819065 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8240 11:11:54.822055 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8241 11:11:54.828796 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8242 11:11:54.836200 [CA 0] Center 42 (13~72) winsize 60
8243 11:11:54.839483 [CA 1] Center 42 (13~72) winsize 60
8244 11:11:54.843265 [CA 2] Center 39 (10~69) winsize 60
8245 11:11:54.846487 [CA 3] Center 38 (9~67) winsize 59
8246 11:11:54.849713 [CA 4] Center 38 (9~68) winsize 60
8247 11:11:54.852844 [CA 5] Center 37 (8~67) winsize 60
8248 11:11:54.852942
8249 11:11:54.856155 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8250 11:11:54.856241
8251 11:11:54.859911 [CATrainingPosCal] consider 1 rank data
8252 11:11:54.862832 u2DelayCellTimex100 = 290/100 ps
8253 11:11:54.866562 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8254 11:11:54.873011 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8255 11:11:54.875972 CA2 delay=39 (10~69),Diff = 2 PI (6 cell)
8256 11:11:54.879796 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8257 11:11:54.882919 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8258 11:11:54.886040 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8259 11:11:54.886124
8260 11:11:54.889627 CA PerBit enable=1, Macro0, CA PI delay=37
8261 11:11:54.889711
8262 11:11:54.892523 [CBTSetCACLKResult] CA Dly = 37
8263 11:11:54.896410 CS Dly: 11 (0~42)
8264 11:11:54.899405 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8265 11:11:54.902431 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8266 11:11:54.902515 ==
8267 11:11:54.906275 Dram Type= 6, Freq= 0, CH_1, rank 1
8268 11:11:54.912609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8269 11:11:54.912725 ==
8270 11:11:54.915592 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8271 11:11:54.919252 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8272 11:11:54.925549 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8273 11:11:54.932460 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8274 11:11:54.939598 [CA 0] Center 42 (12~72) winsize 61
8275 11:11:54.943366 [CA 1] Center 42 (12~72) winsize 61
8276 11:11:54.946576 [CA 2] Center 38 (9~68) winsize 60
8277 11:11:54.949794 [CA 3] Center 38 (8~68) winsize 61
8278 11:11:54.953405 [CA 4] Center 38 (8~69) winsize 62
8279 11:11:54.956220 [CA 5] Center 37 (8~67) winsize 60
8280 11:11:54.956342
8281 11:11:54.959718 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8282 11:11:54.959801
8283 11:11:54.963144 [CATrainingPosCal] consider 2 rank data
8284 11:11:54.966366 u2DelayCellTimex100 = 290/100 ps
8285 11:11:54.969535 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8286 11:11:54.976283 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8287 11:11:54.979502 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8288 11:11:54.983044 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8289 11:11:54.986469 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8290 11:11:54.989661 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8291 11:11:54.989789
8292 11:11:54.993485 CA PerBit enable=1, Macro0, CA PI delay=37
8293 11:11:54.993608
8294 11:11:54.996633 [CBTSetCACLKResult] CA Dly = 37
8295 11:11:54.999588 CS Dly: 12 (0~45)
8296 11:11:55.003106 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8297 11:11:55.006528 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8298 11:11:55.006652
8299 11:11:55.010061 ----->DramcWriteLeveling(PI) begin...
8300 11:11:55.010160 ==
8301 11:11:55.013186 Dram Type= 6, Freq= 0, CH_1, rank 0
8302 11:11:55.016228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8303 11:11:55.019832 ==
8304 11:11:55.019913 Write leveling (Byte 0): 24 => 24
8305 11:11:55.023083 Write leveling (Byte 1): 27 => 27
8306 11:11:55.026502 DramcWriteLeveling(PI) end<-----
8307 11:11:55.026584
8308 11:11:55.026648 ==
8309 11:11:55.029689 Dram Type= 6, Freq= 0, CH_1, rank 0
8310 11:11:55.036039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 11:11:55.036147 ==
8312 11:11:55.039740 [Gating] SW mode calibration
8313 11:11:55.046111 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8314 11:11:55.049811 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8315 11:11:55.056032 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8316 11:11:55.059089 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8317 11:11:55.062385 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8318 11:11:55.069215 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8319 11:11:55.072382 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 11:11:55.075980 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 11:11:55.082540 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 11:11:55.085573 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 11:11:55.089215 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 11:11:55.095759 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 11:11:55.099198 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
8326 11:11:55.102258 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
8327 11:11:55.105536 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 11:11:55.112570 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 11:11:55.115630 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 11:11:55.119243 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 11:11:55.125659 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 11:11:55.128924 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 11:11:55.132710 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
8334 11:11:55.139185 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8335 11:11:55.142306 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 11:11:55.145489 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 11:11:55.152567 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 11:11:55.155473 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 11:11:55.159279 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 11:11:55.165557 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 11:11:55.169392 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8342 11:11:55.172535 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8343 11:11:55.178848 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8344 11:11:55.182580 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 11:11:55.185754 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 11:11:55.191983 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 11:11:55.195736 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 11:11:55.198851 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 11:11:55.205508 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 11:11:55.208900 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 11:11:55.212228 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 11:11:55.218823 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 11:11:55.222486 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 11:11:55.225299 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 11:11:55.229084 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 11:11:55.235378 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 11:11:55.238653 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8358 11:11:55.242434 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8359 11:11:55.249029 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 11:11:55.252242 Total UI for P1: 0, mck2ui 16
8361 11:11:55.255233 best dqsien dly found for B0: ( 1, 9, 10)
8362 11:11:55.255344 Total UI for P1: 0, mck2ui 16
8363 11:11:55.262232 best dqsien dly found for B1: ( 1, 9, 10)
8364 11:11:55.265246 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8365 11:11:55.268978 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8366 11:11:55.269086
8367 11:11:55.272179 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8368 11:11:55.275302 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8369 11:11:55.278517 [Gating] SW calibration Done
8370 11:11:55.278600 ==
8371 11:11:55.282330 Dram Type= 6, Freq= 0, CH_1, rank 0
8372 11:11:55.285474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 11:11:55.285558 ==
8374 11:11:55.288525 RX Vref Scan: 0
8375 11:11:55.288620
8376 11:11:55.288685 RX Vref 0 -> 0, step: 1
8377 11:11:55.292362
8378 11:11:55.292445 RX Delay 0 -> 252, step: 8
8379 11:11:55.295542 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8380 11:11:55.302330 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8381 11:11:55.305504 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8382 11:11:55.308730 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8383 11:11:55.311763 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8384 11:11:55.315353 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8385 11:11:55.321834 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8386 11:11:55.325490 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8387 11:11:55.328593 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8388 11:11:55.331675 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8389 11:11:55.335543 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8390 11:11:55.341763 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8391 11:11:55.345552 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8392 11:11:55.348524 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8393 11:11:55.352109 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8394 11:11:55.354946 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8395 11:11:55.358350 ==
8396 11:11:55.361781 Dram Type= 6, Freq= 0, CH_1, rank 0
8397 11:11:55.365119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 11:11:55.365270 ==
8399 11:11:55.365423 DQS Delay:
8400 11:11:55.368255 DQS0 = 0, DQS1 = 0
8401 11:11:55.368412 DQM Delay:
8402 11:11:55.371988 DQM0 = 137, DQM1 = 133
8403 11:11:55.372106 DQ Delay:
8404 11:11:55.375413 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8405 11:11:55.378285 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8406 11:11:55.382040 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8407 11:11:55.385160 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8408 11:11:55.385253
8409 11:11:55.385317
8410 11:11:55.385376 ==
8411 11:11:55.388485 Dram Type= 6, Freq= 0, CH_1, rank 0
8412 11:11:55.395323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 11:11:55.395414 ==
8414 11:11:55.395480
8415 11:11:55.395539
8416 11:11:55.395595 TX Vref Scan disable
8417 11:11:55.398676 == TX Byte 0 ==
8418 11:11:55.401652 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8419 11:11:55.408693 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8420 11:11:55.408775 == TX Byte 1 ==
8421 11:11:55.412012 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8422 11:11:55.415167 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8423 11:11:55.418312 ==
8424 11:11:55.421989 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 11:11:55.424910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 11:11:55.424996 ==
8427 11:11:55.437446
8428 11:11:55.440490 TX Vref early break, caculate TX vref
8429 11:11:55.444085 TX Vref=16, minBit 1, minWin=22, winSum=377
8430 11:11:55.447137 TX Vref=18, minBit 1, minWin=23, winSum=390
8431 11:11:55.450912 TX Vref=20, minBit 0, minWin=23, winSum=395
8432 11:11:55.454069 TX Vref=22, minBit 0, minWin=24, winSum=405
8433 11:11:55.457181 TX Vref=24, minBit 0, minWin=25, winSum=419
8434 11:11:55.464146 TX Vref=26, minBit 0, minWin=26, winSum=429
8435 11:11:55.467206 TX Vref=28, minBit 0, minWin=26, winSum=432
8436 11:11:55.470974 TX Vref=30, minBit 0, minWin=25, winSum=418
8437 11:11:55.474230 TX Vref=32, minBit 0, minWin=24, winSum=412
8438 11:11:55.477297 TX Vref=34, minBit 0, minWin=24, winSum=403
8439 11:11:55.483951 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
8440 11:11:55.484061
8441 11:11:55.487387 Final TX Range 0 Vref 28
8442 11:11:55.487488
8443 11:11:55.487620 ==
8444 11:11:55.490571 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 11:11:55.493904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 11:11:55.493989 ==
8447 11:11:55.494075
8448 11:11:55.494156
8449 11:11:55.497340 TX Vref Scan disable
8450 11:11:55.503643 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8451 11:11:55.503827 == TX Byte 0 ==
8452 11:11:55.507094 u2DelayCellOfst[0]=16 cells (5 PI)
8453 11:11:55.510515 u2DelayCellOfst[1]=10 cells (3 PI)
8454 11:11:55.513653 u2DelayCellOfst[2]=0 cells (0 PI)
8455 11:11:55.516911 u2DelayCellOfst[3]=6 cells (2 PI)
8456 11:11:55.520119 u2DelayCellOfst[4]=10 cells (3 PI)
8457 11:11:55.523257 u2DelayCellOfst[5]=20 cells (6 PI)
8458 11:11:55.527018 u2DelayCellOfst[6]=20 cells (6 PI)
8459 11:11:55.530258 u2DelayCellOfst[7]=6 cells (2 PI)
8460 11:11:55.533343 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8461 11:11:55.536994 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8462 11:11:55.539793 == TX Byte 1 ==
8463 11:11:55.539872 u2DelayCellOfst[8]=0 cells (0 PI)
8464 11:11:55.543237 u2DelayCellOfst[9]=3 cells (1 PI)
8465 11:11:55.546553 u2DelayCellOfst[10]=13 cells (4 PI)
8466 11:11:55.550288 u2DelayCellOfst[11]=3 cells (1 PI)
8467 11:11:55.553304 u2DelayCellOfst[12]=16 cells (5 PI)
8468 11:11:55.557120 u2DelayCellOfst[13]=16 cells (5 PI)
8469 11:11:55.560243 u2DelayCellOfst[14]=16 cells (5 PI)
8470 11:11:55.563339 u2DelayCellOfst[15]=16 cells (5 PI)
8471 11:11:55.566460 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8472 11:11:55.573329 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8473 11:11:55.573416 DramC Write-DBI on
8474 11:11:55.573487 ==
8475 11:11:55.576532 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 11:11:55.580134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 11:11:55.583268 ==
8478 11:11:55.583390
8479 11:11:55.583503
8480 11:11:55.583611 TX Vref Scan disable
8481 11:11:55.586587 == TX Byte 0 ==
8482 11:11:55.590306 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8483 11:11:55.593344 == TX Byte 1 ==
8484 11:11:55.596442 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8485 11:11:55.599944 DramC Write-DBI off
8486 11:11:55.600066
8487 11:11:55.600176 [DATLAT]
8488 11:11:55.600308 Freq=1600, CH1 RK0
8489 11:11:55.600434
8490 11:11:55.603041 DATLAT Default: 0xf
8491 11:11:55.603125 0, 0xFFFF, sum = 0
8492 11:11:55.606310 1, 0xFFFF, sum = 0
8493 11:11:55.609898 2, 0xFFFF, sum = 0
8494 11:11:55.609981 3, 0xFFFF, sum = 0
8495 11:11:55.613039 4, 0xFFFF, sum = 0
8496 11:11:55.613122 5, 0xFFFF, sum = 0
8497 11:11:55.616226 6, 0xFFFF, sum = 0
8498 11:11:55.616347 7, 0xFFFF, sum = 0
8499 11:11:55.619934 8, 0xFFFF, sum = 0
8500 11:11:55.620017 9, 0xFFFF, sum = 0
8501 11:11:55.623133 10, 0xFFFF, sum = 0
8502 11:11:55.623259 11, 0xFFFF, sum = 0
8503 11:11:55.626458 12, 0xFFFF, sum = 0
8504 11:11:55.626582 13, 0xFFFF, sum = 0
8505 11:11:55.630022 14, 0x0, sum = 1
8506 11:11:55.630145 15, 0x0, sum = 2
8507 11:11:55.633155 16, 0x0, sum = 3
8508 11:11:55.633280 17, 0x0, sum = 4
8509 11:11:55.636239 best_step = 15
8510 11:11:55.636371
8511 11:11:55.636466 ==
8512 11:11:55.640119 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 11:11:55.643033 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 11:11:55.643110 ==
8515 11:11:55.646549 RX Vref Scan: 1
8516 11:11:55.646658
8517 11:11:55.646753 Set Vref Range= 24 -> 127
8518 11:11:55.646828
8519 11:11:55.649547 RX Vref 24 -> 127, step: 1
8520 11:11:55.649660
8521 11:11:55.653310 RX Delay 27 -> 252, step: 4
8522 11:11:55.653421
8523 11:11:55.656219 Set Vref, RX VrefLevel [Byte0]: 24
8524 11:11:55.659588 [Byte1]: 24
8525 11:11:55.659700
8526 11:11:55.662898 Set Vref, RX VrefLevel [Byte0]: 25
8527 11:11:55.666332 [Byte1]: 25
8528 11:11:55.666441
8529 11:11:55.669520 Set Vref, RX VrefLevel [Byte0]: 26
8530 11:11:55.673368 [Byte1]: 26
8531 11:11:55.677110
8532 11:11:55.677195 Set Vref, RX VrefLevel [Byte0]: 27
8533 11:11:55.680157 [Byte1]: 27
8534 11:11:55.684525
8535 11:11:55.684607 Set Vref, RX VrefLevel [Byte0]: 28
8536 11:11:55.687592 [Byte1]: 28
8537 11:11:55.692080
8538 11:11:55.692177 Set Vref, RX VrefLevel [Byte0]: 29
8539 11:11:55.695201 [Byte1]: 29
8540 11:11:55.699499
8541 11:11:55.699596 Set Vref, RX VrefLevel [Byte0]: 30
8542 11:11:55.702578 [Byte1]: 30
8543 11:11:55.706938
8544 11:11:55.707031 Set Vref, RX VrefLevel [Byte0]: 31
8545 11:11:55.710194 [Byte1]: 31
8546 11:11:55.714574
8547 11:11:55.714653 Set Vref, RX VrefLevel [Byte0]: 32
8548 11:11:55.717750 [Byte1]: 32
8549 11:11:55.722165
8550 11:11:55.722267 Set Vref, RX VrefLevel [Byte0]: 33
8551 11:11:55.725264 [Byte1]: 33
8552 11:11:55.729568
8553 11:11:55.729671 Set Vref, RX VrefLevel [Byte0]: 34
8554 11:11:55.732688 [Byte1]: 34
8555 11:11:55.736980
8556 11:11:55.737062 Set Vref, RX VrefLevel [Byte0]: 35
8557 11:11:55.740482 [Byte1]: 35
8558 11:11:55.744673
8559 11:11:55.744799 Set Vref, RX VrefLevel [Byte0]: 36
8560 11:11:55.747659 [Byte1]: 36
8561 11:11:55.751967
8562 11:11:55.752105 Set Vref, RX VrefLevel [Byte0]: 37
8563 11:11:55.755412 [Byte1]: 37
8564 11:11:55.759663
8565 11:11:55.759785 Set Vref, RX VrefLevel [Byte0]: 38
8566 11:11:55.762890 [Byte1]: 38
8567 11:11:55.767352
8568 11:11:55.767474 Set Vref, RX VrefLevel [Byte0]: 39
8569 11:11:55.770432 [Byte1]: 39
8570 11:11:55.774513
8571 11:11:55.774605 Set Vref, RX VrefLevel [Byte0]: 40
8572 11:11:55.777888 [Byte1]: 40
8573 11:11:55.782657
8574 11:11:55.782757 Set Vref, RX VrefLevel [Byte0]: 41
8575 11:11:55.785418 [Byte1]: 41
8576 11:11:55.789613
8577 11:11:55.789697 Set Vref, RX VrefLevel [Byte0]: 42
8578 11:11:55.793202 [Byte1]: 42
8579 11:11:55.797547
8580 11:11:55.797678 Set Vref, RX VrefLevel [Byte0]: 43
8581 11:11:55.800572 [Byte1]: 43
8582 11:11:55.804762
8583 11:11:55.804884 Set Vref, RX VrefLevel [Byte0]: 44
8584 11:11:55.808368 [Byte1]: 44
8585 11:11:55.812194
8586 11:11:55.812343 Set Vref, RX VrefLevel [Byte0]: 45
8587 11:11:55.815491 [Byte1]: 45
8588 11:11:55.820001
8589 11:11:55.820082 Set Vref, RX VrefLevel [Byte0]: 46
8590 11:11:55.822983 [Byte1]: 46
8591 11:11:55.827538
8592 11:11:55.827644 Set Vref, RX VrefLevel [Byte0]: 47
8593 11:11:55.830605 [Byte1]: 47
8594 11:11:55.834928
8595 11:11:55.835052 Set Vref, RX VrefLevel [Byte0]: 48
8596 11:11:55.838116 [Byte1]: 48
8597 11:11:55.842404
8598 11:11:55.842502 Set Vref, RX VrefLevel [Byte0]: 49
8599 11:11:55.846035 [Byte1]: 49
8600 11:11:55.849763
8601 11:11:55.849847 Set Vref, RX VrefLevel [Byte0]: 50
8602 11:11:55.853537 [Byte1]: 50
8603 11:11:55.857439
8604 11:11:55.857521 Set Vref, RX VrefLevel [Byte0]: 51
8605 11:11:55.860662 [Byte1]: 51
8606 11:11:55.865082
8607 11:11:55.865171 Set Vref, RX VrefLevel [Byte0]: 52
8608 11:11:55.868659 [Byte1]: 52
8609 11:11:55.872679
8610 11:11:55.872811 Set Vref, RX VrefLevel [Byte0]: 53
8611 11:11:55.876264 [Byte1]: 53
8612 11:11:55.880120
8613 11:11:55.880203 Set Vref, RX VrefLevel [Byte0]: 54
8614 11:11:55.883311 [Byte1]: 54
8615 11:11:55.887673
8616 11:11:55.887759 Set Vref, RX VrefLevel [Byte0]: 55
8617 11:11:55.890832 [Byte1]: 55
8618 11:11:55.895384
8619 11:11:55.895526 Set Vref, RX VrefLevel [Byte0]: 56
8620 11:11:55.898436 [Byte1]: 56
8621 11:11:55.902670
8622 11:11:55.902773 Set Vref, RX VrefLevel [Byte0]: 57
8623 11:11:55.905812 [Byte1]: 57
8624 11:11:55.910175
8625 11:11:55.910257 Set Vref, RX VrefLevel [Byte0]: 58
8626 11:11:55.913416 [Byte1]: 58
8627 11:11:55.917707
8628 11:11:55.917807 Set Vref, RX VrefLevel [Byte0]: 59
8629 11:11:55.921148 [Byte1]: 59
8630 11:11:55.925414
8631 11:11:55.925526 Set Vref, RX VrefLevel [Byte0]: 60
8632 11:11:55.928558 [Byte1]: 60
8633 11:11:55.932880
8634 11:11:55.932992 Set Vref, RX VrefLevel [Byte0]: 61
8635 11:11:55.935999 [Byte1]: 61
8636 11:11:55.940568
8637 11:11:55.940684 Set Vref, RX VrefLevel [Byte0]: 62
8638 11:11:55.943690 [Byte1]: 62
8639 11:11:55.948095
8640 11:11:55.948217 Set Vref, RX VrefLevel [Byte0]: 63
8641 11:11:55.951184 [Byte1]: 63
8642 11:11:55.955287
8643 11:11:55.955370 Set Vref, RX VrefLevel [Byte0]: 64
8644 11:11:55.958623 [Byte1]: 64
8645 11:11:55.963064
8646 11:11:55.963147 Set Vref, RX VrefLevel [Byte0]: 65
8647 11:11:55.966219 [Byte1]: 65
8648 11:11:55.970676
8649 11:11:55.970760 Set Vref, RX VrefLevel [Byte0]: 66
8650 11:11:55.973897 [Byte1]: 66
8651 11:11:55.978008
8652 11:11:55.978092 Set Vref, RX VrefLevel [Byte0]: 67
8653 11:11:55.981252 [Byte1]: 67
8654 11:11:55.985586
8655 11:11:55.985670 Set Vref, RX VrefLevel [Byte0]: 68
8656 11:11:55.988732 [Byte1]: 68
8657 11:11:55.993104
8658 11:11:55.993187 Set Vref, RX VrefLevel [Byte0]: 69
8659 11:11:55.996551 [Byte1]: 69
8660 11:11:56.000803
8661 11:11:56.000887 Set Vref, RX VrefLevel [Byte0]: 70
8662 11:11:56.004224 [Byte1]: 70
8663 11:11:56.007945
8664 11:11:56.008028 Set Vref, RX VrefLevel [Byte0]: 71
8665 11:11:56.011696 [Byte1]: 71
8666 11:11:56.015955
8667 11:11:56.016038 Set Vref, RX VrefLevel [Byte0]: 72
8668 11:11:56.018819 [Byte1]: 72
8669 11:11:56.023139
8670 11:11:56.023222 Set Vref, RX VrefLevel [Byte0]: 73
8671 11:11:56.026549 [Byte1]: 73
8672 11:11:56.030609
8673 11:11:56.030691 Set Vref, RX VrefLevel [Byte0]: 74
8674 11:11:56.033878 [Byte1]: 74
8675 11:11:56.038405
8676 11:11:56.038514 Set Vref, RX VrefLevel [Byte0]: 75
8677 11:11:56.041678 [Byte1]: 75
8678 11:11:56.045594
8679 11:11:56.045723 Set Vref, RX VrefLevel [Byte0]: 76
8680 11:11:56.049437 [Byte1]: 76
8681 11:11:56.053170
8682 11:11:56.053294 Set Vref, RX VrefLevel [Byte0]: 77
8683 11:11:56.056836 [Byte1]: 77
8684 11:11:56.061030
8685 11:11:56.061151 Final RX Vref Byte 0 = 57 to rank0
8686 11:11:56.064111 Final RX Vref Byte 1 = 57 to rank0
8687 11:11:56.067495 Final RX Vref Byte 0 = 57 to rank1
8688 11:11:56.071296 Final RX Vref Byte 1 = 57 to rank1==
8689 11:11:56.074384 Dram Type= 6, Freq= 0, CH_1, rank 0
8690 11:11:56.080725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8691 11:11:56.080846 ==
8692 11:11:56.080957 DQS Delay:
8693 11:11:56.081066 DQS0 = 0, DQS1 = 0
8694 11:11:56.084352 DQM Delay:
8695 11:11:56.084470 DQM0 = 134, DQM1 = 131
8696 11:11:56.087633 DQ Delay:
8697 11:11:56.090545 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8698 11:11:56.094310 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =134
8699 11:11:56.097466 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8700 11:11:56.100627 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8701 11:11:56.100709
8702 11:11:56.100772
8703 11:11:56.100830
8704 11:11:56.104423 [DramC_TX_OE_Calibration] TA2
8705 11:11:56.107553 Original DQ_B0 (3 6) =30, OEN = 27
8706 11:11:56.110670 Original DQ_B1 (3 6) =30, OEN = 27
8707 11:11:56.114372 24, 0x0, End_B0=24 End_B1=24
8708 11:11:56.114494 25, 0x0, End_B0=25 End_B1=25
8709 11:11:56.117358 26, 0x0, End_B0=26 End_B1=26
8710 11:11:56.120630 27, 0x0, End_B0=27 End_B1=27
8711 11:11:56.123866 28, 0x0, End_B0=28 End_B1=28
8712 11:11:56.127392 29, 0x0, End_B0=29 End_B1=29
8713 11:11:56.127508 30, 0x0, End_B0=30 End_B1=30
8714 11:11:56.130432 31, 0x4545, End_B0=30 End_B1=30
8715 11:11:56.133786 Byte0 end_step=30 best_step=27
8716 11:11:56.137364 Byte1 end_step=30 best_step=27
8717 11:11:56.140277 Byte0 TX OE(2T, 0.5T) = (3, 3)
8718 11:11:56.144141 Byte1 TX OE(2T, 0.5T) = (3, 3)
8719 11:11:56.144279
8720 11:11:56.144407
8721 11:11:56.150383 [DQSOSCAuto] RK0, (LSB)MR18= 0x1623, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
8722 11:11:56.153857 CH1 RK0: MR19=303, MR18=1623
8723 11:11:56.160525 CH1_RK0: MR19=0x303, MR18=0x1623, DQSOSC=392, MR23=63, INC=24, DEC=16
8724 11:11:56.160612
8725 11:11:56.163693 ----->DramcWriteLeveling(PI) begin...
8726 11:11:56.163779 ==
8727 11:11:56.167334 Dram Type= 6, Freq= 0, CH_1, rank 1
8728 11:11:56.170437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8729 11:11:56.170519 ==
8730 11:11:56.173784 Write leveling (Byte 0): 28 => 28
8731 11:11:56.176819 Write leveling (Byte 1): 27 => 27
8732 11:11:56.180016 DramcWriteLeveling(PI) end<-----
8733 11:11:56.180089
8734 11:11:56.180151 ==
8735 11:11:56.183800 Dram Type= 6, Freq= 0, CH_1, rank 1
8736 11:11:56.186996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8737 11:11:56.187079 ==
8738 11:11:56.189970 [Gating] SW mode calibration
8739 11:11:56.197003 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8740 11:11:56.203980 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8741 11:11:56.207130 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 11:11:56.210383 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 11:11:56.217178 1 4 8 | B1->B0 | 2a2a 2323 | 1 0 | (1 1) (0 0)
8744 11:11:56.220443 1 4 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
8745 11:11:56.223375 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 11:11:56.230280 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 11:11:56.233829 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 11:11:56.237323 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 11:11:56.243584 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 11:11:56.246876 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8751 11:11:56.250399 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8752 11:11:56.256720 1 5 12 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
8753 11:11:56.260156 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8754 11:11:56.263656 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 11:11:56.270024 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 11:11:56.273537 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 11:11:56.276881 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 11:11:56.283450 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8759 11:11:56.286959 1 6 8 | B1->B0 | 3737 2323 | 1 0 | (0 0) (0 0)
8760 11:11:56.290203 1 6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8761 11:11:56.296646 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 11:11:56.299969 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 11:11:56.303770 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 11:11:56.309991 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 11:11:56.313723 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 11:11:56.316947 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8767 11:11:56.323420 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8768 11:11:56.326704 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8769 11:11:56.329828 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8770 11:11:56.333768 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 11:11:56.339961 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 11:11:56.343554 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 11:11:56.346717 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 11:11:56.353283 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 11:11:56.356394 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 11:11:56.359923 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 11:11:56.366680 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 11:11:56.370382 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 11:11:56.373319 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 11:11:56.380102 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 11:11:56.383227 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 11:11:56.386888 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8783 11:11:56.393050 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8784 11:11:56.396798 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8785 11:11:56.399792 Total UI for P1: 0, mck2ui 16
8786 11:11:56.403257 best dqsien dly found for B1: ( 1, 9, 6)
8787 11:11:56.406750 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8788 11:11:56.413366 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 11:11:56.413453 Total UI for P1: 0, mck2ui 16
8790 11:11:56.416511 best dqsien dly found for B0: ( 1, 9, 14)
8791 11:11:56.423460 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8792 11:11:56.426616 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8793 11:11:56.426698
8794 11:11:56.429744 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8795 11:11:56.432973 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8796 11:11:56.436741 [Gating] SW calibration Done
8797 11:11:56.436823 ==
8798 11:11:56.439833 Dram Type= 6, Freq= 0, CH_1, rank 1
8799 11:11:56.443120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8800 11:11:56.443203 ==
8801 11:11:56.446883 RX Vref Scan: 0
8802 11:11:56.446966
8803 11:11:56.447031 RX Vref 0 -> 0, step: 1
8804 11:11:56.447091
8805 11:11:56.450406 RX Delay 0 -> 252, step: 8
8806 11:11:56.452985 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8807 11:11:56.456620 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8808 11:11:56.463358 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8809 11:11:56.466346 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8810 11:11:56.470034 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8811 11:11:56.473083 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8812 11:11:56.476590 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8813 11:11:56.483127 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8814 11:11:56.485944 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8815 11:11:56.489531 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8816 11:11:56.492802 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8817 11:11:56.496035 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8818 11:11:56.503195 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8819 11:11:56.506205 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8820 11:11:56.509647 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8821 11:11:56.513166 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8822 11:11:56.513248 ==
8823 11:11:56.516462 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 11:11:56.523080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 11:11:56.523198 ==
8826 11:11:56.523298 DQS Delay:
8827 11:11:56.526056 DQS0 = 0, DQS1 = 0
8828 11:11:56.526139 DQM Delay:
8829 11:11:56.526205 DQM0 = 136, DQM1 = 133
8830 11:11:56.529514 DQ Delay:
8831 11:11:56.532829 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8832 11:11:56.536464 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8833 11:11:56.539518 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8834 11:11:56.542776 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8835 11:11:56.542859
8836 11:11:56.542924
8837 11:11:56.543008 ==
8838 11:11:56.545973 Dram Type= 6, Freq= 0, CH_1, rank 1
8839 11:11:56.549266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8840 11:11:56.552902 ==
8841 11:11:56.552984
8842 11:11:56.553049
8843 11:11:56.553108 TX Vref Scan disable
8844 11:11:56.556059 == TX Byte 0 ==
8845 11:11:56.559751 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8846 11:11:56.562729 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8847 11:11:56.565847 == TX Byte 1 ==
8848 11:11:56.569508 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8849 11:11:56.572656 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8850 11:11:56.575772 ==
8851 11:11:56.579461 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 11:11:56.582532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 11:11:56.582615 ==
8854 11:11:56.596138
8855 11:11:56.599074 TX Vref early break, caculate TX vref
8856 11:11:56.602293 TX Vref=16, minBit 5, minWin=22, winSum=384
8857 11:11:56.605705 TX Vref=18, minBit 0, minWin=23, winSum=389
8858 11:11:56.608748 TX Vref=20, minBit 1, minWin=24, winSum=405
8859 11:11:56.612664 TX Vref=22, minBit 0, minWin=24, winSum=408
8860 11:11:56.615793 TX Vref=24, minBit 0, minWin=25, winSum=417
8861 11:11:56.622021 TX Vref=26, minBit 0, minWin=26, winSum=424
8862 11:11:56.625624 TX Vref=28, minBit 0, minWin=25, winSum=424
8863 11:11:56.628757 TX Vref=30, minBit 0, minWin=26, winSum=423
8864 11:11:56.632412 TX Vref=32, minBit 1, minWin=25, winSum=416
8865 11:11:56.635295 TX Vref=34, minBit 0, minWin=24, winSum=403
8866 11:11:56.638635 TX Vref=36, minBit 0, minWin=24, winSum=398
8867 11:11:56.645773 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 26
8868 11:11:56.645858
8869 11:11:56.648914 Final TX Range 0 Vref 26
8870 11:11:56.648997
8871 11:11:56.649061 ==
8872 11:11:56.652183 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 11:11:56.655375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 11:11:56.655459 ==
8875 11:11:56.655525
8876 11:11:56.655585
8877 11:11:56.659103 TX Vref Scan disable
8878 11:11:56.665693 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8879 11:11:56.665779 == TX Byte 0 ==
8880 11:11:56.669036 u2DelayCellOfst[0]=16 cells (5 PI)
8881 11:11:56.672115 u2DelayCellOfst[1]=10 cells (3 PI)
8882 11:11:56.675727 u2DelayCellOfst[2]=0 cells (0 PI)
8883 11:11:56.679095 u2DelayCellOfst[3]=6 cells (2 PI)
8884 11:11:56.682030 u2DelayCellOfst[4]=10 cells (3 PI)
8885 11:11:56.686043 u2DelayCellOfst[5]=16 cells (5 PI)
8886 11:11:56.688977 u2DelayCellOfst[6]=16 cells (5 PI)
8887 11:11:56.692583 u2DelayCellOfst[7]=6 cells (2 PI)
8888 11:11:56.695749 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8889 11:11:56.698890 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8890 11:11:56.702106 == TX Byte 1 ==
8891 11:11:56.705170 u2DelayCellOfst[8]=0 cells (0 PI)
8892 11:11:56.705267 u2DelayCellOfst[9]=3 cells (1 PI)
8893 11:11:56.708872 u2DelayCellOfst[10]=10 cells (3 PI)
8894 11:11:56.712157 u2DelayCellOfst[11]=3 cells (1 PI)
8895 11:11:56.715338 u2DelayCellOfst[12]=13 cells (4 PI)
8896 11:11:56.718570 u2DelayCellOfst[13]=13 cells (4 PI)
8897 11:11:56.722172 u2DelayCellOfst[14]=16 cells (5 PI)
8898 11:11:56.725204 u2DelayCellOfst[15]=16 cells (5 PI)
8899 11:11:56.728919 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8900 11:11:56.735149 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8901 11:11:56.735275 DramC Write-DBI on
8902 11:11:56.735390 ==
8903 11:11:56.738746 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 11:11:56.744970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 11:11:56.745096 ==
8906 11:11:56.745210
8907 11:11:56.745318
8908 11:11:56.745424 TX Vref Scan disable
8909 11:11:56.749278 == TX Byte 0 ==
8910 11:11:56.752277 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8911 11:11:56.755702 == TX Byte 1 ==
8912 11:11:56.758932 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8913 11:11:56.762347 DramC Write-DBI off
8914 11:11:56.762467
8915 11:11:56.762575 [DATLAT]
8916 11:11:56.762680 Freq=1600, CH1 RK1
8917 11:11:56.762791
8918 11:11:56.765479 DATLAT Default: 0xf
8919 11:11:56.768948 0, 0xFFFF, sum = 0
8920 11:11:56.769072 1, 0xFFFF, sum = 0
8921 11:11:56.771808 2, 0xFFFF, sum = 0
8922 11:11:56.771931 3, 0xFFFF, sum = 0
8923 11:11:56.775229 4, 0xFFFF, sum = 0
8924 11:11:56.775355 5, 0xFFFF, sum = 0
8925 11:11:56.778857 6, 0xFFFF, sum = 0
8926 11:11:56.778982 7, 0xFFFF, sum = 0
8927 11:11:56.782003 8, 0xFFFF, sum = 0
8928 11:11:56.782127 9, 0xFFFF, sum = 0
8929 11:11:56.785633 10, 0xFFFF, sum = 0
8930 11:11:56.785758 11, 0xFFFF, sum = 0
8931 11:11:56.788801 12, 0xFFFF, sum = 0
8932 11:11:56.788926 13, 0xFFFF, sum = 0
8933 11:11:56.791986 14, 0x0, sum = 1
8934 11:11:56.792137 15, 0x0, sum = 2
8935 11:11:56.795145 16, 0x0, sum = 3
8936 11:11:56.795272 17, 0x0, sum = 4
8937 11:11:56.798671 best_step = 15
8938 11:11:56.798794
8939 11:11:56.798907 ==
8940 11:11:56.801902 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 11:11:56.805709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 11:11:56.805833 ==
8943 11:11:56.805945 RX Vref Scan: 0
8944 11:11:56.808921
8945 11:11:56.809043 RX Vref 0 -> 0, step: 1
8946 11:11:56.809151
8947 11:11:56.812102 RX Delay 19 -> 252, step: 4
8948 11:11:56.815439 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8949 11:11:56.822208 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8950 11:11:56.825690 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8951 11:11:56.829120 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8952 11:11:56.831979 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8953 11:11:56.835488 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8954 11:11:56.838929 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8955 11:11:56.845307 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8956 11:11:56.849051 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8957 11:11:56.852073 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8958 11:11:56.855367 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8959 11:11:56.858527 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8960 11:11:56.865267 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8961 11:11:56.869215 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8962 11:11:56.872113 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8963 11:11:56.875373 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8964 11:11:56.875496 ==
8965 11:11:56.878332 Dram Type= 6, Freq= 0, CH_1, rank 1
8966 11:11:56.885343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8967 11:11:56.885471 ==
8968 11:11:56.885586 DQS Delay:
8969 11:11:56.888814 DQS0 = 0, DQS1 = 0
8970 11:11:56.888937 DQM Delay:
8971 11:11:56.889050 DQM0 = 134, DQM1 = 130
8972 11:11:56.892175 DQ Delay:
8973 11:11:56.895179 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8974 11:11:56.898873 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8975 11:11:56.901927 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8976 11:11:56.904988 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8977 11:11:56.905069
8978 11:11:56.905133
8979 11:11:56.905192
8980 11:11:56.908697 [DramC_TX_OE_Calibration] TA2
8981 11:11:56.911870 Original DQ_B0 (3 6) =30, OEN = 27
8982 11:11:56.915024 Original DQ_B1 (3 6) =30, OEN = 27
8983 11:11:56.918260 24, 0x0, End_B0=24 End_B1=24
8984 11:11:56.918382 25, 0x0, End_B0=25 End_B1=25
8985 11:11:56.922151 26, 0x0, End_B0=26 End_B1=26
8986 11:11:56.925368 27, 0x0, End_B0=27 End_B1=27
8987 11:11:56.928465 28, 0x0, End_B0=28 End_B1=28
8988 11:11:56.932062 29, 0x0, End_B0=29 End_B1=29
8989 11:11:56.932145 30, 0x0, End_B0=30 End_B1=30
8990 11:11:56.935089 31, 0x4141, End_B0=30 End_B1=30
8991 11:11:56.938414 Byte0 end_step=30 best_step=27
8992 11:11:56.941788 Byte1 end_step=30 best_step=27
8993 11:11:56.945130 Byte0 TX OE(2T, 0.5T) = (3, 3)
8994 11:11:56.948024 Byte1 TX OE(2T, 0.5T) = (3, 3)
8995 11:11:56.948107
8996 11:11:56.948172
8997 11:11:56.955080 [DQSOSCAuto] RK1, (LSB)MR18= 0x2105, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
8998 11:11:56.958171 CH1 RK1: MR19=303, MR18=2105
8999 11:11:56.965151 CH1_RK1: MR19=0x303, MR18=0x2105, DQSOSC=393, MR23=63, INC=23, DEC=15
9000 11:11:56.968262 [RxdqsGatingPostProcess] freq 1600
9001 11:11:56.971300 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9002 11:11:56.974887 best DQS0 dly(2T, 0.5T) = (1, 1)
9003 11:11:56.978124 best DQS1 dly(2T, 0.5T) = (1, 1)
9004 11:11:56.981087 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9005 11:11:56.984969 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9006 11:11:56.988179 best DQS0 dly(2T, 0.5T) = (1, 1)
9007 11:11:56.991359 best DQS1 dly(2T, 0.5T) = (1, 1)
9008 11:11:56.995003 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9009 11:11:56.997945 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9010 11:11:57.001291 Pre-setting of DQS Precalculation
9011 11:11:57.005208 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9012 11:11:57.011746 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9013 11:11:57.017910 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9014 11:11:57.021655
9015 11:11:57.021780
9016 11:11:57.021894 [Calibration Summary] 3200 Mbps
9017 11:11:57.024785 CH 0, Rank 0
9018 11:11:57.024912 SW Impedance : PASS
9019 11:11:57.028577 DUTY Scan : NO K
9020 11:11:57.031644 ZQ Calibration : PASS
9021 11:11:57.031768 Jitter Meter : NO K
9022 11:11:57.034882 CBT Training : PASS
9023 11:11:57.038108 Write leveling : PASS
9024 11:11:57.038232 RX DQS gating : PASS
9025 11:11:57.041780 RX DQ/DQS(RDDQC) : PASS
9026 11:11:57.044856 TX DQ/DQS : PASS
9027 11:11:57.044980 RX DATLAT : PASS
9028 11:11:57.048432 RX DQ/DQS(Engine): PASS
9029 11:11:57.051712 TX OE : PASS
9030 11:11:57.051875 All Pass.
9031 11:11:57.051980
9032 11:11:57.052087 CH 0, Rank 1
9033 11:11:57.054568 SW Impedance : PASS
9034 11:11:57.057971 DUTY Scan : NO K
9035 11:11:57.058093 ZQ Calibration : PASS
9036 11:11:57.061379 Jitter Meter : NO K
9037 11:11:57.064906 CBT Training : PASS
9038 11:11:57.065032 Write leveling : PASS
9039 11:11:57.068010 RX DQS gating : PASS
9040 11:11:57.068135 RX DQ/DQS(RDDQC) : PASS
9041 11:11:57.071234 TX DQ/DQS : PASS
9042 11:11:57.074452 RX DATLAT : PASS
9043 11:11:57.074578 RX DQ/DQS(Engine): PASS
9044 11:11:57.078010 TX OE : PASS
9045 11:11:57.078134 All Pass.
9046 11:11:57.078247
9047 11:11:57.081119 CH 1, Rank 0
9048 11:11:57.081243 SW Impedance : PASS
9049 11:11:57.084719 DUTY Scan : NO K
9050 11:11:57.087988 ZQ Calibration : PASS
9051 11:11:57.088113 Jitter Meter : NO K
9052 11:11:57.091362 CBT Training : PASS
9053 11:11:57.094961 Write leveling : PASS
9054 11:11:57.095067 RX DQS gating : PASS
9055 11:11:57.098466 RX DQ/DQS(RDDQC) : PASS
9056 11:11:57.101552 TX DQ/DQS : PASS
9057 11:11:57.101637 RX DATLAT : PASS
9058 11:11:57.104631 RX DQ/DQS(Engine): PASS
9059 11:11:57.104715 TX OE : PASS
9060 11:11:57.108129 All Pass.
9061 11:11:57.108214
9062 11:11:57.108281 CH 1, Rank 1
9063 11:11:57.111466 SW Impedance : PASS
9064 11:11:57.114951 DUTY Scan : NO K
9065 11:11:57.115036 ZQ Calibration : PASS
9066 11:11:57.117772 Jitter Meter : NO K
9067 11:11:57.117857 CBT Training : PASS
9068 11:11:57.121151 Write leveling : PASS
9069 11:11:57.124778 RX DQS gating : PASS
9070 11:11:57.124862 RX DQ/DQS(RDDQC) : PASS
9071 11:11:57.127868 TX DQ/DQS : PASS
9072 11:11:57.131515 RX DATLAT : PASS
9073 11:11:57.131599 RX DQ/DQS(Engine): PASS
9074 11:11:57.134793 TX OE : PASS
9075 11:11:57.134878 All Pass.
9076 11:11:57.134945
9077 11:11:57.137953 DramC Write-DBI on
9078 11:11:57.141039 PER_BANK_REFRESH: Hybrid Mode
9079 11:11:57.141123 TX_TRACKING: ON
9080 11:11:57.151362 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9081 11:11:57.157666 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9082 11:11:57.164820 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9083 11:11:57.167742 [FAST_K] Save calibration result to emmc
9084 11:11:57.171486 sync common calibartion params.
9085 11:11:57.174361 sync cbt_mode0:1, 1:1
9086 11:11:57.177617 dram_init: ddr_geometry: 2
9087 11:11:57.177726 dram_init: ddr_geometry: 2
9088 11:11:57.181457 dram_init: ddr_geometry: 2
9089 11:11:57.184505 0:dram_rank_size:100000000
9090 11:11:57.187862 1:dram_rank_size:100000000
9091 11:11:57.190880 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9092 11:11:57.194588 DFS_SHUFFLE_HW_MODE: ON
9093 11:11:57.197616 dramc_set_vcore_voltage set vcore to 725000
9094 11:11:57.201150 Read voltage for 1600, 0
9095 11:11:57.201233 Vio18 = 0
9096 11:11:57.201298 Vcore = 725000
9097 11:11:57.204292 Vdram = 0
9098 11:11:57.204390 Vddq = 0
9099 11:11:57.204455 Vmddr = 0
9100 11:11:57.207949 switch to 3200 Mbps bootup
9101 11:11:57.211129 [DramcRunTimeConfig]
9102 11:11:57.211211 PHYPLL
9103 11:11:57.211275 DPM_CONTROL_AFTERK: ON
9104 11:11:57.214188 PER_BANK_REFRESH: ON
9105 11:11:57.217915 REFRESH_OVERHEAD_REDUCTION: ON
9106 11:11:57.218000 CMD_PICG_NEW_MODE: OFF
9107 11:11:57.221011 XRTWTW_NEW_MODE: ON
9108 11:11:57.221094 XRTRTR_NEW_MODE: ON
9109 11:11:57.224674 TX_TRACKING: ON
9110 11:11:57.224756 RDSEL_TRACKING: OFF
9111 11:11:57.227975 DQS Precalculation for DVFS: ON
9112 11:11:57.231426 RX_TRACKING: OFF
9113 11:11:57.231508 HW_GATING DBG: ON
9114 11:11:57.234655 ZQCS_ENABLE_LP4: ON
9115 11:11:57.234738 RX_PICG_NEW_MODE: ON
9116 11:11:57.237921 TX_PICG_NEW_MODE: ON
9117 11:11:57.240961 ENABLE_RX_DCM_DPHY: ON
9118 11:11:57.241095 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9119 11:11:57.244653 DUMMY_READ_FOR_TRACKING: OFF
9120 11:11:57.247867 !!! SPM_CONTROL_AFTERK: OFF
9121 11:11:57.251033 !!! SPM could not control APHY
9122 11:11:57.251159 IMPEDANCE_TRACKING: ON
9123 11:11:57.254785 TEMP_SENSOR: ON
9124 11:11:57.254908 HW_SAVE_FOR_SR: OFF
9125 11:11:57.257768 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9126 11:11:57.261483 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9127 11:11:57.264237 Read ODT Tracking: ON
9128 11:11:57.267511 Refresh Rate DeBounce: ON
9129 11:11:57.267634 DFS_NO_QUEUE_FLUSH: ON
9130 11:11:57.270921 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9131 11:11:57.274388 ENABLE_DFS_RUNTIME_MRW: OFF
9132 11:11:57.277922 DDR_RESERVE_NEW_MODE: ON
9133 11:11:57.278061 MR_CBT_SWITCH_FREQ: ON
9134 11:11:57.280824 =========================
9135 11:11:57.300435 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9136 11:11:57.303592 dram_init: ddr_geometry: 2
9137 11:11:57.321670 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9138 11:11:57.325248 dram_init: dram init end (result: 0)
9139 11:11:57.331526 DRAM-K: Full calibration passed in 24441 msecs
9140 11:11:57.335346 MRC: failed to locate region type 0.
9141 11:11:57.335470 DRAM rank0 size:0x100000000,
9142 11:11:57.338398 DRAM rank1 size=0x100000000
9143 11:11:57.348171 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9144 11:11:57.355219 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9145 11:11:57.361508 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9146 11:11:57.368545 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9147 11:11:57.371516 DRAM rank0 size:0x100000000,
9148 11:11:57.374994 DRAM rank1 size=0x100000000
9149 11:11:57.375120 CBMEM:
9150 11:11:57.378405 IMD: root @ 0xfffff000 254 entries.
9151 11:11:57.381926 IMD: root @ 0xffffec00 62 entries.
9152 11:11:57.384819 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9153 11:11:57.388274 WARNING: RO_VPD is uninitialized or empty.
9154 11:11:57.394869 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9155 11:11:57.401624 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9156 11:11:57.414688 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9157 11:11:57.425984 BS: romstage times (exec / console): total (unknown) / 23976 ms
9158 11:11:57.426123
9159 11:11:57.426241
9160 11:11:57.435524 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9161 11:11:57.439272 ARM64: Exception handlers installed.
9162 11:11:57.442334 ARM64: Testing exception
9163 11:11:57.445451 ARM64: Done test exception
9164 11:11:57.445595 Enumerating buses...
9165 11:11:57.449206 Show all devs... Before device enumeration.
9166 11:11:57.452226 Root Device: enabled 1
9167 11:11:57.455483 CPU_CLUSTER: 0: enabled 1
9168 11:11:57.455608 CPU: 00: enabled 1
9169 11:11:57.458809 Compare with tree...
9170 11:11:57.458965 Root Device: enabled 1
9171 11:11:57.462036 CPU_CLUSTER: 0: enabled 1
9172 11:11:57.465706 CPU: 00: enabled 1
9173 11:11:57.465831 Root Device scanning...
9174 11:11:57.468886 scan_static_bus for Root Device
9175 11:11:57.471967 CPU_CLUSTER: 0 enabled
9176 11:11:57.475660 scan_static_bus for Root Device done
9177 11:11:57.478725 scan_bus: bus Root Device finished in 8 msecs
9178 11:11:57.478847 done
9179 11:11:57.485359 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9180 11:11:57.488809 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9181 11:11:57.495087 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9182 11:11:57.498684 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9183 11:11:57.502343 Allocating resources...
9184 11:11:57.505427 Reading resources...
9185 11:11:57.508509 Root Device read_resources bus 0 link: 0
9186 11:11:57.508605 DRAM rank0 size:0x100000000,
9187 11:11:57.512142 DRAM rank1 size=0x100000000
9188 11:11:57.515317 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9189 11:11:57.518554 CPU: 00 missing read_resources
9190 11:11:57.522276 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9191 11:11:57.529021 Root Device read_resources bus 0 link: 0 done
9192 11:11:57.529107 Done reading resources.
9193 11:11:57.535650 Show resources in subtree (Root Device)...After reading.
9194 11:11:57.539039 Root Device child on link 0 CPU_CLUSTER: 0
9195 11:11:57.541906 CPU_CLUSTER: 0 child on link 0 CPU: 00
9196 11:11:57.552258 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9197 11:11:57.552428 CPU: 00
9198 11:11:57.555490 Root Device assign_resources, bus 0 link: 0
9199 11:11:57.558648 CPU_CLUSTER: 0 missing set_resources
9200 11:11:57.562381 Root Device assign_resources, bus 0 link: 0 done
9201 11:11:57.565221 Done setting resources.
9202 11:11:57.571987 Show resources in subtree (Root Device)...After assigning values.
9203 11:11:57.575559 Root Device child on link 0 CPU_CLUSTER: 0
9204 11:11:57.578523 CPU_CLUSTER: 0 child on link 0 CPU: 00
9205 11:11:57.588721 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9206 11:11:57.588809 CPU: 00
9207 11:11:57.591713 Done allocating resources.
9208 11:11:57.595415 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9209 11:11:57.598893 Enabling resources...
9210 11:11:57.598975 done.
9211 11:11:57.605463 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9212 11:11:57.605547 Initializing devices...
9213 11:11:57.608477 Root Device init
9214 11:11:57.608597 init hardware done!
9215 11:11:57.612175 0x00000018: ctrlr->caps
9216 11:11:57.615218 52.000 MHz: ctrlr->f_max
9217 11:11:57.615302 0.400 MHz: ctrlr->f_min
9218 11:11:57.618649 0x40ff8080: ctrlr->voltages
9219 11:11:57.618770 sclk: 390625
9220 11:11:57.621890 Bus Width = 1
9221 11:11:57.621972 sclk: 390625
9222 11:11:57.625125 Bus Width = 1
9223 11:11:57.625207 Early init status = 3
9224 11:11:57.631703 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9225 11:11:57.634963 in-header: 03 fc 00 00 01 00 00 00
9226 11:11:57.635046 in-data: 00
9227 11:11:57.641633 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9228 11:11:57.645015 in-header: 03 fd 00 00 00 00 00 00
9229 11:11:57.648400 in-data:
9230 11:11:57.651759 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9231 11:11:57.654919 in-header: 03 fc 00 00 01 00 00 00
9232 11:11:57.658020 in-data: 00
9233 11:11:57.661162 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9234 11:11:57.665604 in-header: 03 fd 00 00 00 00 00 00
9235 11:11:57.669390 in-data:
9236 11:11:57.672619 [SSUSB] Setting up USB HOST controller...
9237 11:11:57.675617 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9238 11:11:57.679239 [SSUSB] phy power-on done.
9239 11:11:57.682546 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9240 11:11:57.689338 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9241 11:11:57.692573 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9242 11:11:57.699041 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9243 11:11:57.705799 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9244 11:11:57.712507 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9245 11:11:57.719134 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9246 11:11:57.725772 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9247 11:11:57.725898 SPM: binary array size = 0x9dc
9248 11:11:57.732569 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9249 11:11:57.739245 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9250 11:11:57.745482 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9251 11:11:57.749345 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9252 11:11:57.752229 configure_display: Starting display init
9253 11:11:57.788998 anx7625_power_on_init: Init interface.
9254 11:11:57.792589 anx7625_disable_pd_protocol: Disabled PD feature.
9255 11:11:57.795662 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9256 11:11:57.823820 anx7625_start_dp_work: Secure OCM version=00
9257 11:11:57.826787 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9258 11:11:57.841264 sp_tx_get_edid_block: EDID Block = 1
9259 11:11:57.943874 Extracted contents:
9260 11:11:57.947092 header: 00 ff ff ff ff ff ff 00
9261 11:11:57.950556 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9262 11:11:57.954269 version: 01 04
9263 11:11:57.957134 basic params: 95 1f 11 78 0a
9264 11:11:57.960520 chroma info: 76 90 94 55 54 90 27 21 50 54
9265 11:11:57.964077 established: 00 00 00
9266 11:11:57.970716 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9267 11:11:57.977325 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9268 11:11:57.980406 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9269 11:11:57.986712 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9270 11:11:57.993555 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9271 11:11:57.996660 extensions: 00
9272 11:11:57.996758 checksum: fb
9273 11:11:57.996824
9274 11:11:57.999930 Manufacturer: IVO Model 57d Serial Number 0
9275 11:11:58.003659 Made week 0 of 2020
9276 11:11:58.006697 EDID version: 1.4
9277 11:11:58.006782 Digital display
9278 11:11:58.010138 6 bits per primary color channel
9279 11:11:58.010261 DisplayPort interface
9280 11:11:58.013230 Maximum image size: 31 cm x 17 cm
9281 11:11:58.016439 Gamma: 220%
9282 11:11:58.016524 Check DPMS levels
9283 11:11:58.020223 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9284 11:11:58.026873 First detailed timing is preferred timing
9285 11:11:58.026973 Established timings supported:
9286 11:11:58.029976 Standard timings supported:
9287 11:11:58.033235 Detailed timings
9288 11:11:58.036909 Hex of detail: 383680a07038204018303c0035ae10000019
9289 11:11:58.043504 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9290 11:11:58.046777 0780 0798 07c8 0820 hborder 0
9291 11:11:58.049762 0438 043b 0447 0458 vborder 0
9292 11:11:58.053229 -hsync -vsync
9293 11:11:58.053317 Did detailed timing
9294 11:11:58.059842 Hex of detail: 000000000000000000000000000000000000
9295 11:11:58.063480 Manufacturer-specified data, tag 0
9296 11:11:58.066500 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9297 11:11:58.069845 ASCII string: InfoVision
9298 11:11:58.073021 Hex of detail: 000000fe00523134304e574635205248200a
9299 11:11:58.076255 ASCII string: R140NWF5 RH
9300 11:11:58.076418 Checksum
9301 11:11:58.080173 Checksum: 0xfb (valid)
9302 11:11:58.083389 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9303 11:11:58.086255 DSI data_rate: 832800000 bps
9304 11:11:58.093053 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9305 11:11:58.096720 anx7625_parse_edid: pixelclock(138800).
9306 11:11:58.100070 hactive(1920), hsync(48), hfp(24), hbp(88)
9307 11:11:58.103235 vactive(1080), vsync(12), vfp(3), vbp(17)
9308 11:11:58.106195 anx7625_dsi_config: config dsi.
9309 11:11:58.113253 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9310 11:11:58.126145 anx7625_dsi_config: success to config DSI
9311 11:11:58.129400 anx7625_dp_start: MIPI phy setup OK.
9312 11:11:58.132496 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9313 11:11:58.136223 mtk_ddp_mode_set invalid vrefresh 60
9314 11:11:58.139387 main_disp_path_setup
9315 11:11:58.139499 ovl_layer_smi_id_en
9316 11:11:58.142481 ovl_layer_smi_id_en
9317 11:11:58.142563 ccorr_config
9318 11:11:58.142627 aal_config
9319 11:11:58.145755 gamma_config
9320 11:11:58.145837 postmask_config
9321 11:11:58.149559 dither_config
9322 11:11:58.152409 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9323 11:11:58.159212 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9324 11:11:58.162644 Root Device init finished in 551 msecs
9325 11:11:58.165636 CPU_CLUSTER: 0 init
9326 11:11:58.172605 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9327 11:11:58.178730 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9328 11:11:58.178858 APU_MBOX 0x190000b0 = 0x10001
9329 11:11:58.182476 APU_MBOX 0x190001b0 = 0x10001
9330 11:11:58.185875 APU_MBOX 0x190005b0 = 0x10001
9331 11:11:58.189022 APU_MBOX 0x190006b0 = 0x10001
9332 11:11:58.195314 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9333 11:11:58.204761 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9334 11:11:58.217618 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9335 11:11:58.224275 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9336 11:11:58.235470 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9337 11:11:58.245028 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9338 11:11:58.248187 CPU_CLUSTER: 0 init finished in 81 msecs
9339 11:11:58.251944 Devices initialized
9340 11:11:58.254676 Show all devs... After init.
9341 11:11:58.254761 Root Device: enabled 1
9342 11:11:58.258128 CPU_CLUSTER: 0: enabled 1
9343 11:11:58.261600 CPU: 00: enabled 1
9344 11:11:58.264681 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9345 11:11:58.268158 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9346 11:11:58.271608 ELOG: NV offset 0x57f000 size 0x1000
9347 11:11:58.278489 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9348 11:11:58.284664 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9349 11:11:58.288397 ELOG: Event(17) added with size 13 at 2024-03-03 11:09:09 UTC
9350 11:11:58.291579 out: cmd=0x121: 03 db 21 01 00 00 00 00
9351 11:11:58.295434 in-header: 03 ef 00 00 2c 00 00 00
9352 11:11:58.308645 in-data: 70 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9353 11:11:58.315144 ELOG: Event(A1) added with size 10 at 2024-03-03 11:09:09 UTC
9354 11:11:58.321875 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9355 11:11:58.328344 ELOG: Event(A0) added with size 9 at 2024-03-03 11:09:09 UTC
9356 11:11:58.331598 elog_add_boot_reason: Logged dev mode boot
9357 11:11:58.335062 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9358 11:11:58.338055 Finalize devices...
9359 11:11:58.338185 Devices finalized
9360 11:11:58.345057 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9361 11:11:58.348140 Writing coreboot table at 0xffe64000
9362 11:11:58.351364 0. 000000000010a000-0000000000113fff: RAMSTAGE
9363 11:11:58.355060 1. 0000000040000000-00000000400fffff: RAM
9364 11:11:58.358352 2. 0000000040100000-000000004032afff: RAMSTAGE
9365 11:11:58.365018 3. 000000004032b000-00000000545fffff: RAM
9366 11:11:58.368082 4. 0000000054600000-000000005465ffff: BL31
9367 11:11:58.371740 5. 0000000054660000-00000000ffe63fff: RAM
9368 11:11:58.378207 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9369 11:11:58.381625 7. 0000000100000000-000000023fffffff: RAM
9370 11:11:58.381752 Passing 5 GPIOs to payload:
9371 11:11:58.388164 NAME | PORT | POLARITY | VALUE
9372 11:11:58.391348 EC in RW | 0x000000aa | low | undefined
9373 11:11:58.398261 EC interrupt | 0x00000005 | low | undefined
9374 11:11:58.401442 TPM interrupt | 0x000000ab | high | undefined
9375 11:11:58.404439 SD card detect | 0x00000011 | high | undefined
9376 11:11:58.411589 speaker enable | 0x00000093 | high | undefined
9377 11:11:58.414750 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9378 11:11:58.417983 in-header: 03 f9 00 00 02 00 00 00
9379 11:11:58.418108 in-data: 02 00
9380 11:11:58.421103 ADC[4]: Raw value=904357 ID=7
9381 11:11:58.424771 ADC[3]: Raw value=213441 ID=1
9382 11:11:58.424895 RAM Code: 0x71
9383 11:11:58.427916 ADC[6]: Raw value=75701 ID=0
9384 11:11:58.431717 ADC[5]: Raw value=213072 ID=1
9385 11:11:58.431826 SKU Code: 0x1
9386 11:11:58.437775 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 8707
9387 11:11:58.441111 coreboot table: 964 bytes.
9388 11:11:58.444752 IMD ROOT 0. 0xfffff000 0x00001000
9389 11:11:58.447836 IMD SMALL 1. 0xffffe000 0x00001000
9390 11:11:58.451403 RO MCACHE 2. 0xffffc000 0x00001104
9391 11:11:58.454739 CONSOLE 3. 0xfff7c000 0x00080000
9392 11:11:58.457760 FMAP 4. 0xfff7b000 0x00000452
9393 11:11:58.461432 TIME STAMP 5. 0xfff7a000 0x00000910
9394 11:11:58.464691 VBOOT WORK 6. 0xfff66000 0x00014000
9395 11:11:58.467760 RAMOOPS 7. 0xffe66000 0x00100000
9396 11:11:58.470818 COREBOOT 8. 0xffe64000 0x00002000
9397 11:11:58.470945 IMD small region:
9398 11:11:58.474281 IMD ROOT 0. 0xffffec00 0x00000400
9399 11:11:58.477658 VPD 1. 0xffffeb80 0x0000006c
9400 11:11:58.481337 MMC STATUS 2. 0xffffeb60 0x00000004
9401 11:11:58.487987 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9402 11:11:58.488112 Probing TPM: done!
9403 11:11:58.495150 Connected to device vid:did:rid of 1ae0:0028:00
9404 11:11:58.501748 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9405 11:11:58.505098 Initialized TPM device CR50 revision 0
9406 11:11:58.508976 Checking cr50 for pending updates
9407 11:11:58.514681 Reading cr50 TPM mode
9408 11:11:58.522944 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9409 11:11:58.529636 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9410 11:11:58.570002 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9411 11:11:58.573157 Checking segment from ROM address 0x40100000
9412 11:11:58.576533 Checking segment from ROM address 0x4010001c
9413 11:11:58.583458 Loading segment from ROM address 0x40100000
9414 11:11:58.583549 code (compression=0)
9415 11:11:58.590119 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9416 11:11:58.600169 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9417 11:11:58.600318 it's not compressed!
9418 11:11:58.606926 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9419 11:11:58.609712 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9420 11:11:58.630274 Loading segment from ROM address 0x4010001c
9421 11:11:58.630398 Entry Point 0x80000000
9422 11:11:58.634045 Loaded segments
9423 11:11:58.637250 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9424 11:11:58.643694 Jumping to boot code at 0x80000000(0xffe64000)
9425 11:11:58.650188 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9426 11:11:58.657124 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9427 11:11:58.664624 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9428 11:11:58.667993 Checking segment from ROM address 0x40100000
9429 11:11:58.671099 Checking segment from ROM address 0x4010001c
9430 11:11:58.678099 Loading segment from ROM address 0x40100000
9431 11:11:58.678207 code (compression=1)
9432 11:11:58.685018 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9433 11:11:58.694767 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9434 11:11:58.694865 using LZMA
9435 11:11:58.703447 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9436 11:11:58.709699 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9437 11:11:58.713524 Loading segment from ROM address 0x4010001c
9438 11:11:58.713612 Entry Point 0x54601000
9439 11:11:58.716220 Loaded segments
9440 11:11:58.719699 NOTICE: MT8192 bl31_setup
9441 11:11:58.726586 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9442 11:11:58.729895 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9443 11:11:58.733362 WARNING: region 0:
9444 11:11:58.737155 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9445 11:11:58.737278 WARNING: region 1:
9446 11:11:58.743171 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9447 11:11:58.746857 WARNING: region 2:
9448 11:11:58.750043 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9449 11:11:58.753328 WARNING: region 3:
9450 11:11:58.756913 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9451 11:11:58.760247 WARNING: region 4:
9452 11:11:58.763344 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9453 11:11:58.766958 WARNING: region 5:
9454 11:11:58.770079 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9455 11:11:58.773193 WARNING: region 6:
9456 11:11:58.777001 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9457 11:11:58.777087 WARNING: region 7:
9458 11:11:58.783504 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9459 11:11:58.789929 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9460 11:11:58.793615 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9461 11:11:58.796625 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9462 11:11:58.803663 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9463 11:11:58.806797 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9464 11:11:58.810412 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9465 11:11:58.816712 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9466 11:11:58.820199 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9467 11:11:58.823943 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9468 11:11:58.830179 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9469 11:11:58.833587 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9470 11:11:58.837076 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9471 11:11:58.843928 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9472 11:11:58.846782 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9473 11:11:58.853828 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9474 11:11:58.857143 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9475 11:11:58.860344 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9476 11:11:58.867167 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9477 11:11:58.870383 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9478 11:11:58.873563 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9479 11:11:58.880579 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9480 11:11:58.883658 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9481 11:11:58.890413 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9482 11:11:58.893721 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9483 11:11:58.900452 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9484 11:11:58.903631 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9485 11:11:58.907086 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9486 11:11:58.913884 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9487 11:11:58.917014 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9488 11:11:58.920036 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9489 11:11:58.926709 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9490 11:11:58.930321 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9491 11:11:58.933875 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9492 11:11:58.940334 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9493 11:11:58.943626 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9494 11:11:58.946756 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9495 11:11:58.950046 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9496 11:11:58.956659 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9497 11:11:58.960154 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9498 11:11:58.963454 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9499 11:11:58.966970 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9500 11:11:58.973961 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9501 11:11:58.977197 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9502 11:11:58.980418 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9503 11:11:58.983383 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9504 11:11:58.990699 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9505 11:11:58.993539 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9506 11:11:58.996761 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9507 11:11:59.003585 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9508 11:11:59.006708 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9509 11:11:59.010307 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9510 11:11:59.016894 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9511 11:11:59.020214 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9512 11:11:59.026814 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9513 11:11:59.030448 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9514 11:11:59.037006 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9515 11:11:59.040086 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9516 11:11:59.043597 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9517 11:11:59.050507 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9518 11:11:59.053589 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9519 11:11:59.060252 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9520 11:11:59.063394 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9521 11:11:59.070318 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9522 11:11:59.073296 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9523 11:11:59.080114 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9524 11:11:59.083723 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9525 11:11:59.087184 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9526 11:11:59.093819 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9527 11:11:59.096756 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9528 11:11:59.103676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9529 11:11:59.107028 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9530 11:11:59.110158 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9531 11:11:59.117094 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9532 11:11:59.119987 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9533 11:11:59.127029 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9534 11:11:59.130201 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9535 11:11:59.137349 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9536 11:11:59.140121 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9537 11:11:59.147342 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9538 11:11:59.150242 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9539 11:11:59.153929 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9540 11:11:59.160367 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9541 11:11:59.163406 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9542 11:11:59.170466 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9543 11:11:59.173650 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9544 11:11:59.180257 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9545 11:11:59.183541 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9546 11:11:59.187312 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9547 11:11:59.193661 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9548 11:11:59.196916 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9549 11:11:59.203365 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9550 11:11:59.206677 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9551 11:11:59.213746 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9552 11:11:59.217081 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9553 11:11:59.220198 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9554 11:11:59.227105 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9555 11:11:59.230658 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9556 11:11:59.233676 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9557 11:11:59.240276 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9558 11:11:59.243717 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9559 11:11:59.247150 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9560 11:11:59.253959 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9561 11:11:59.256814 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9562 11:11:59.260428 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9563 11:11:59.267183 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9564 11:11:59.270381 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9565 11:11:59.273676 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9566 11:11:59.280147 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9567 11:11:59.283714 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9568 11:11:59.290094 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9569 11:11:59.293719 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9570 11:11:59.296852 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9571 11:11:59.303822 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9572 11:11:59.306988 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9573 11:11:59.313753 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9574 11:11:59.317325 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9575 11:11:59.320428 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9576 11:11:59.326953 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9577 11:11:59.330227 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9578 11:11:59.333908 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9579 11:11:59.336922 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9580 11:11:59.343492 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9581 11:11:59.347228 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9582 11:11:59.350637 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9583 11:11:59.357094 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9584 11:11:59.360366 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9585 11:11:59.363792 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9586 11:11:59.370489 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9587 11:11:59.373607 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9588 11:11:59.380505 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9589 11:11:59.383683 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9590 11:11:59.387372 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9591 11:11:59.394140 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9592 11:11:59.397265 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9593 11:11:59.400445 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9594 11:11:59.407268 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9595 11:11:59.410394 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9596 11:11:59.416895 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9597 11:11:59.420574 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9598 11:11:59.423923 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9599 11:11:59.430458 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9600 11:11:59.433632 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9601 11:11:59.437288 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9602 11:11:59.443787 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9603 11:11:59.447027 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9604 11:11:59.454165 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9605 11:11:59.457090 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9606 11:11:59.460424 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9607 11:11:59.467137 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9608 11:11:59.470302 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9609 11:11:59.477650 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9610 11:11:59.480305 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9611 11:11:59.484040 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9612 11:11:59.490536 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9613 11:11:59.493810 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9614 11:11:59.497615 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9615 11:11:59.504022 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9616 11:11:59.507689 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9617 11:11:59.510806 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9618 11:11:59.517222 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9619 11:11:59.520523 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9620 11:11:59.527382 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9621 11:11:59.530325 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9622 11:11:59.537014 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9623 11:11:59.540912 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9624 11:11:59.544009 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9625 11:11:59.550343 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9626 11:11:59.553867 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9627 11:11:59.557279 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9628 11:11:59.563523 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9629 11:11:59.567113 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9630 11:11:59.573891 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9631 11:11:59.576764 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9632 11:11:59.580263 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9633 11:11:59.586879 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9634 11:11:59.590174 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9635 11:11:59.597238 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9636 11:11:59.600248 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9637 11:11:59.603601 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9638 11:11:59.610297 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9639 11:11:59.613436 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9640 11:11:59.619813 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9641 11:11:59.623682 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9642 11:11:59.626838 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9643 11:11:59.633147 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9644 11:11:59.636694 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9645 11:11:59.640159 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9646 11:11:59.646726 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9647 11:11:59.649863 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9648 11:11:59.656578 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9649 11:11:59.660195 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9650 11:11:59.666761 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9651 11:11:59.669584 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9652 11:11:59.673296 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9653 11:11:59.679634 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9654 11:11:59.682812 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9655 11:11:59.689529 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9656 11:11:59.693222 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9657 11:11:59.699908 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9658 11:11:59.703454 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9659 11:11:59.706183 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9660 11:11:59.712973 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9661 11:11:59.716215 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9662 11:11:59.723137 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9663 11:11:59.726322 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9664 11:11:59.729469 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9665 11:11:59.736385 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9666 11:11:59.739398 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9667 11:11:59.746196 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9668 11:11:59.749328 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9669 11:11:59.755772 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9670 11:11:59.759597 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9671 11:11:59.762615 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9672 11:11:59.769201 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9673 11:11:59.772766 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9674 11:11:59.779076 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9675 11:11:59.782968 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9676 11:11:59.786056 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9677 11:11:59.792962 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9678 11:11:59.795860 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9679 11:11:59.802516 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9680 11:11:59.806207 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9681 11:11:59.809138 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9682 11:11:59.815752 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9683 11:11:59.819432 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9684 11:11:59.826116 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9685 11:11:59.829305 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9686 11:11:59.836129 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9687 11:11:59.839418 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9688 11:11:59.842650 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9689 11:11:59.845761 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9690 11:11:59.852622 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9691 11:11:59.855565 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9692 11:11:59.859375 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9693 11:11:59.862711 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9694 11:11:59.869401 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9695 11:11:59.872679 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9696 11:11:59.878761 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9697 11:11:59.882262 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9698 11:11:59.885627 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9699 11:11:59.892464 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9700 11:11:59.895645 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9701 11:11:59.902331 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9702 11:11:59.905770 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9703 11:11:59.908668 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9704 11:11:59.915484 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9705 11:11:59.919086 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9706 11:11:59.922110 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9707 11:11:59.929027 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9708 11:11:59.932145 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9709 11:11:59.935747 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9710 11:11:59.941957 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9711 11:11:59.945722 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9712 11:11:59.948645 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9713 11:11:59.955556 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9714 11:11:59.958720 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9715 11:11:59.965553 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9716 11:11:59.968507 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9717 11:11:59.971978 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9718 11:11:59.978362 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9719 11:11:59.982199 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9720 11:11:59.985505 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9721 11:11:59.991881 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9722 11:11:59.995527 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9723 11:11:59.998611 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9724 11:12:00.004939 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9725 11:12:00.008767 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9726 11:12:00.015162 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9727 11:12:00.018816 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9728 11:12:00.021748 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9729 11:12:00.025177 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9730 11:12:00.028427 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9731 11:12:00.035475 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9732 11:12:00.038457 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9733 11:12:00.041813 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9734 11:12:00.045362 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9735 11:12:00.051852 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9736 11:12:00.055198 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9737 11:12:00.058816 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9738 11:12:00.061627 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9739 11:12:00.068339 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9740 11:12:00.071536 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9741 11:12:00.074991 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9742 11:12:00.081652 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9743 11:12:00.085255 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9744 11:12:00.092046 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9745 11:12:00.095001 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9746 11:12:00.101614 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9747 11:12:00.104734 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9748 11:12:00.108475 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9749 11:12:00.114670 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9750 11:12:00.118474 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9751 11:12:00.125129 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9752 11:12:00.128271 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9753 11:12:00.131467 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9754 11:12:00.138387 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9755 11:12:00.141368 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9756 11:12:00.148206 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9757 11:12:00.151974 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9758 11:12:00.155048 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9759 11:12:00.161968 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9760 11:12:00.165043 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9761 11:12:00.171794 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9762 11:12:00.174999 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9763 11:12:00.177946 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9764 11:12:00.184813 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9765 11:12:00.188027 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9766 11:12:00.194563 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9767 11:12:00.198260 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9768 11:12:00.201221 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9769 11:12:00.207769 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9770 11:12:00.211495 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9771 11:12:00.217830 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9772 11:12:00.220963 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9773 11:12:00.224650 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9774 11:12:00.231193 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9775 11:12:00.234287 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9776 11:12:00.240999 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9777 11:12:00.244582 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9778 11:12:00.251152 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9779 11:12:00.254051 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9780 11:12:00.257911 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9781 11:12:00.264155 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9782 11:12:00.267315 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9783 11:12:00.274175 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9784 11:12:00.277204 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9785 11:12:00.284298 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9786 11:12:00.287205 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9787 11:12:00.291107 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9788 11:12:00.297395 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9789 11:12:00.300979 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9790 11:12:00.303849 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9791 11:12:00.310592 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9792 11:12:00.314157 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9793 11:12:00.320613 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9794 11:12:00.323923 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9795 11:12:00.330780 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9796 11:12:00.333824 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9797 11:12:00.337433 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9798 11:12:00.344031 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9799 11:12:00.347256 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9800 11:12:00.353781 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9801 11:12:00.357330 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9802 11:12:00.360587 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9803 11:12:00.366896 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9804 11:12:00.370613 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9805 11:12:00.376993 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9806 11:12:00.380146 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9807 11:12:00.383767 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9808 11:12:00.390569 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9809 11:12:00.393678 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9810 11:12:00.400411 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9811 11:12:00.403648 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9812 11:12:00.406846 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9813 11:12:00.413418 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9814 11:12:00.417013 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9815 11:12:00.423505 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9816 11:12:00.426770 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9817 11:12:00.433299 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9818 11:12:00.437092 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9819 11:12:00.443181 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9820 11:12:00.446691 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9821 11:12:00.449916 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9822 11:12:00.456743 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9823 11:12:00.459949 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9824 11:12:00.466516 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9825 11:12:00.469949 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9826 11:12:00.476790 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9827 11:12:00.479986 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9828 11:12:00.483641 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9829 11:12:00.489797 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9830 11:12:00.493649 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9831 11:12:00.499951 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9832 11:12:00.503218 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9833 11:12:00.509767 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9834 11:12:00.513035 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9835 11:12:00.519987 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9836 11:12:00.523468 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9837 11:12:00.526497 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9838 11:12:00.533158 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9839 11:12:00.536858 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9840 11:12:00.543271 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9841 11:12:00.546449 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9842 11:12:00.549619 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9843 11:12:00.556664 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9844 11:12:00.559894 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9845 11:12:00.566455 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9846 11:12:00.570156 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9847 11:12:00.576542 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9848 11:12:00.580116 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9849 11:12:00.586266 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9850 11:12:00.589466 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9851 11:12:00.593193 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9852 11:12:00.600016 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9853 11:12:00.603178 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9854 11:12:00.609389 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9855 11:12:00.613127 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9856 11:12:00.619493 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9857 11:12:00.622624 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9858 11:12:00.626529 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9859 11:12:00.632859 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9860 11:12:00.635928 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9861 11:12:00.642868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9862 11:12:00.646361 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9863 11:12:00.649363 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9864 11:12:00.656173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9865 11:12:00.659471 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9866 11:12:00.665724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9867 11:12:00.669096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9868 11:12:00.675933 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9869 11:12:00.679342 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9870 11:12:00.685648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9871 11:12:00.689203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9872 11:12:00.695856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9873 11:12:00.698889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9874 11:12:00.705915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9875 11:12:00.709101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9876 11:12:00.716089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9877 11:12:00.719192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9878 11:12:00.726104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9879 11:12:00.729200 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9880 11:12:00.736168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9881 11:12:00.739230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9882 11:12:00.745532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9883 11:12:00.749053 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9884 11:12:00.755785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9885 11:12:00.758963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9886 11:12:00.765587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9887 11:12:00.768954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9888 11:12:00.775676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9889 11:12:00.778679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9890 11:12:00.785430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9891 11:12:00.788736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9892 11:12:00.795405 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9893 11:12:00.798914 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9894 11:12:00.801871 INFO: [APUAPC] vio 0
9895 11:12:00.805490 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9896 11:12:00.808973 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9897 11:12:00.812047 INFO: [APUAPC] D0_APC_0: 0x400510
9898 11:12:00.815403 INFO: [APUAPC] D0_APC_1: 0x0
9899 11:12:00.818985 INFO: [APUAPC] D0_APC_2: 0x1540
9900 11:12:00.822108 INFO: [APUAPC] D0_APC_3: 0x0
9901 11:12:00.825150 INFO: [APUAPC] D1_APC_0: 0xffffffff
9902 11:12:00.828529 INFO: [APUAPC] D1_APC_1: 0xffffffff
9903 11:12:00.832049 INFO: [APUAPC] D1_APC_2: 0x3fffff
9904 11:12:00.835171 INFO: [APUAPC] D1_APC_3: 0x0
9905 11:12:00.838353 INFO: [APUAPC] D2_APC_0: 0xffffffff
9906 11:12:00.842149 INFO: [APUAPC] D2_APC_1: 0xffffffff
9907 11:12:00.845263 INFO: [APUAPC] D2_APC_2: 0x3fffff
9908 11:12:00.848420 INFO: [APUAPC] D2_APC_3: 0x0
9909 11:12:00.852013 INFO: [APUAPC] D3_APC_0: 0xffffffff
9910 11:12:00.855328 INFO: [APUAPC] D3_APC_1: 0xffffffff
9911 11:12:00.858970 INFO: [APUAPC] D3_APC_2: 0x3fffff
9912 11:12:00.861939 INFO: [APUAPC] D3_APC_3: 0x0
9913 11:12:00.865062 INFO: [APUAPC] D4_APC_0: 0xffffffff
9914 11:12:00.868711 INFO: [APUAPC] D4_APC_1: 0xffffffff
9915 11:12:00.871832 INFO: [APUAPC] D4_APC_2: 0x3fffff
9916 11:12:00.875463 INFO: [APUAPC] D4_APC_3: 0x0
9917 11:12:00.878459 INFO: [APUAPC] D5_APC_0: 0xffffffff
9918 11:12:00.882069 INFO: [APUAPC] D5_APC_1: 0xffffffff
9919 11:12:00.885117 INFO: [APUAPC] D5_APC_2: 0x3fffff
9920 11:12:00.888327 INFO: [APUAPC] D5_APC_3: 0x0
9921 11:12:00.892011 INFO: [APUAPC] D6_APC_0: 0xffffffff
9922 11:12:00.895128 INFO: [APUAPC] D6_APC_1: 0xffffffff
9923 11:12:00.898701 INFO: [APUAPC] D6_APC_2: 0x3fffff
9924 11:12:00.901968 INFO: [APUAPC] D6_APC_3: 0x0
9925 11:12:00.905043 INFO: [APUAPC] D7_APC_0: 0xffffffff
9926 11:12:00.908604 INFO: [APUAPC] D7_APC_1: 0xffffffff
9927 11:12:00.911688 INFO: [APUAPC] D7_APC_2: 0x3fffff
9928 11:12:00.911774 INFO: [APUAPC] D7_APC_3: 0x0
9929 11:12:00.915233 INFO: [APUAPC] D8_APC_0: 0xffffffff
9930 11:12:00.921976 INFO: [APUAPC] D8_APC_1: 0xffffffff
9931 11:12:00.922060 INFO: [APUAPC] D8_APC_2: 0x3fffff
9932 11:12:00.925309 INFO: [APUAPC] D8_APC_3: 0x0
9933 11:12:00.928519 INFO: [APUAPC] D9_APC_0: 0xffffffff
9934 11:12:00.932232 INFO: [APUAPC] D9_APC_1: 0xffffffff
9935 11:12:00.935282 INFO: [APUAPC] D9_APC_2: 0x3fffff
9936 11:12:00.938558 INFO: [APUAPC] D9_APC_3: 0x0
9937 11:12:00.941645 INFO: [APUAPC] D10_APC_0: 0xffffffff
9938 11:12:00.945055 INFO: [APUAPC] D10_APC_1: 0xffffffff
9939 11:12:00.948653 INFO: [APUAPC] D10_APC_2: 0x3fffff
9940 11:12:00.951774 INFO: [APUAPC] D10_APC_3: 0x0
9941 11:12:00.955516 INFO: [APUAPC] D11_APC_0: 0xffffffff
9942 11:12:00.958616 INFO: [APUAPC] D11_APC_1: 0xffffffff
9943 11:12:00.961583 INFO: [APUAPC] D11_APC_2: 0x3fffff
9944 11:12:00.965094 INFO: [APUAPC] D11_APC_3: 0x0
9945 11:12:00.968683 INFO: [APUAPC] D12_APC_0: 0xffffffff
9946 11:12:00.971823 INFO: [APUAPC] D12_APC_1: 0xffffffff
9947 11:12:00.975119 INFO: [APUAPC] D12_APC_2: 0x3fffff
9948 11:12:00.978404 INFO: [APUAPC] D12_APC_3: 0x0
9949 11:12:00.981462 INFO: [APUAPC] D13_APC_0: 0xffffffff
9950 11:12:00.985141 INFO: [APUAPC] D13_APC_1: 0xffffffff
9951 11:12:00.988461 INFO: [APUAPC] D13_APC_2: 0x3fffff
9952 11:12:00.991853 INFO: [APUAPC] D13_APC_3: 0x0
9953 11:12:00.994858 INFO: [APUAPC] D14_APC_0: 0xffffffff
9954 11:12:00.998400 INFO: [APUAPC] D14_APC_1: 0xffffffff
9955 11:12:01.004496 INFO: [APUAPC] D14_APC_2: 0x3fffff
9956 11:12:01.004600 INFO: [APUAPC] D14_APC_3: 0x0
9957 11:12:01.008321 INFO: [APUAPC] D15_APC_0: 0xffffffff
9958 11:12:01.014502 INFO: [APUAPC] D15_APC_1: 0xffffffff
9959 11:12:01.018206 INFO: [APUAPC] D15_APC_2: 0x3fffff
9960 11:12:01.018291 INFO: [APUAPC] D15_APC_3: 0x0
9961 11:12:01.021391 INFO: [APUAPC] APC_CON: 0x4
9962 11:12:01.025007 INFO: [NOCDAPC] D0_APC_0: 0x0
9963 11:12:01.028149 INFO: [NOCDAPC] D0_APC_1: 0x0
9964 11:12:01.031393 INFO: [NOCDAPC] D1_APC_0: 0x0
9965 11:12:01.034391 INFO: [NOCDAPC] D1_APC_1: 0xfff
9966 11:12:01.038063 INFO: [NOCDAPC] D2_APC_0: 0x0
9967 11:12:01.041178 INFO: [NOCDAPC] D2_APC_1: 0xfff
9968 11:12:01.044558 INFO: [NOCDAPC] D3_APC_0: 0x0
9969 11:12:01.044686 INFO: [NOCDAPC] D3_APC_1: 0xfff
9970 11:12:01.048145 INFO: [NOCDAPC] D4_APC_0: 0x0
9971 11:12:01.051319 INFO: [NOCDAPC] D4_APC_1: 0xfff
9972 11:12:01.054363 INFO: [NOCDAPC] D5_APC_0: 0x0
9973 11:12:01.058053 INFO: [NOCDAPC] D5_APC_1: 0xfff
9974 11:12:01.061199 INFO: [NOCDAPC] D6_APC_0: 0x0
9975 11:12:01.065036 INFO: [NOCDAPC] D6_APC_1: 0xfff
9976 11:12:01.067943 INFO: [NOCDAPC] D7_APC_0: 0x0
9977 11:12:01.071644 INFO: [NOCDAPC] D7_APC_1: 0xfff
9978 11:12:01.074465 INFO: [NOCDAPC] D8_APC_0: 0x0
9979 11:12:01.077679 INFO: [NOCDAPC] D8_APC_1: 0xfff
9980 11:12:01.077806 INFO: [NOCDAPC] D9_APC_0: 0x0
9981 11:12:01.081525 INFO: [NOCDAPC] D9_APC_1: 0xfff
9982 11:12:01.084536 INFO: [NOCDAPC] D10_APC_0: 0x0
9983 11:12:01.087594 INFO: [NOCDAPC] D10_APC_1: 0xfff
9984 11:12:01.090888 INFO: [NOCDAPC] D11_APC_0: 0x0
9985 11:12:01.094321 INFO: [NOCDAPC] D11_APC_1: 0xfff
9986 11:12:01.097702 INFO: [NOCDAPC] D12_APC_0: 0x0
9987 11:12:01.100621 INFO: [NOCDAPC] D12_APC_1: 0xfff
9988 11:12:01.104222 INFO: [NOCDAPC] D13_APC_0: 0x0
9989 11:12:01.107431 INFO: [NOCDAPC] D13_APC_1: 0xfff
9990 11:12:01.111086 INFO: [NOCDAPC] D14_APC_0: 0x0
9991 11:12:01.114274 INFO: [NOCDAPC] D14_APC_1: 0xfff
9992 11:12:01.117456 INFO: [NOCDAPC] D15_APC_0: 0x0
9993 11:12:01.121110 INFO: [NOCDAPC] D15_APC_1: 0xfff
9994 11:12:01.123997 INFO: [NOCDAPC] APC_CON: 0x4
9995 11:12:01.127678 INFO: [APUAPC] set_apusys_apc done
9996 11:12:01.127761 INFO: [DEVAPC] devapc_init done
9997 11:12:01.134425 INFO: GICv3 without legacy support detected.
9998 11:12:01.137502 INFO: ARM GICv3 driver initialized in EL3
9999 11:12:01.140523 INFO: Maximum SPI INTID supported: 639
10000 11:12:01.144402 INFO: BL31: Initializing runtime services
10001 11:12:01.150555 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10002 11:12:01.154019 INFO: SPM: enable CPC mode
10003 11:12:01.157218 INFO: mcdi ready for mcusys-off-idle and system suspend
10004 11:12:01.163771 INFO: BL31: Preparing for EL3 exit to normal world
10005 11:12:01.167175 INFO: Entry point address = 0x80000000
10006 11:12:01.170075 INFO: SPSR = 0x8
10007 11:12:01.174580
10008 11:12:01.174718
10009 11:12:01.174843
10010 11:12:01.178151 Starting depthcharge on Spherion...
10011 11:12:01.178271
10012 11:12:01.178382 Wipe memory regions:
10013 11:12:01.178492
10014 11:12:01.179348 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10015 11:12:01.179507 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10016 11:12:01.179644 Setting prompt string to ['asurada:']
10017 11:12:01.179784 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10018 11:12:01.181096 [0x00000040000000, 0x00000054600000)
10019 11:12:01.303453
10020 11:12:01.303591 [0x00000054660000, 0x00000080000000)
10021 11:12:01.564189
10022 11:12:01.564436 [0x000000821a7280, 0x000000ffe64000)
10023 11:12:02.308967
10024 11:12:02.309161 [0x00000100000000, 0x00000240000000)
10025 11:12:04.199673
10026 11:12:04.202871 Initializing XHCI USB controller at 0x11200000.
10027 11:12:05.240700
10028 11:12:05.243651 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10029 11:12:05.243729
10030 11:12:05.243813
10031 11:12:05.243877
10032 11:12:05.244156 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10034 11:12:05.344502 asurada: tftpboot 192.168.201.1 12925665/tftp-deploy-qak9d4qr/kernel/image.itb 12925665/tftp-deploy-qak9d4qr/kernel/cmdline
10035 11:12:05.344636 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10036 11:12:05.344746 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10037 11:12:05.348543 tftpboot 192.168.201.1 12925665/tftp-deploy-qak9d4qr/kernel/image.itp-deploy-qak9d4qr/kernel/cmdline
10038 11:12:05.348659
10039 11:12:05.348734 Waiting for link
10040 11:12:05.509001
10041 11:12:05.509127 R8152: Initializing
10042 11:12:05.509194
10043 11:12:05.512750 Version 9 (ocp_data = 6010)
10044 11:12:05.512833
10045 11:12:05.515583 R8152: Done initializing
10046 11:12:05.515664
10047 11:12:05.515730 Adding net device
10048 11:12:07.388761
10049 11:12:07.388914 done.
10050 11:12:07.388982
10051 11:12:07.389044 MAC: 00:e0:4c:78:7a:aa
10052 11:12:07.389103
10053 11:12:07.391944 Sending DHCP discover... done.
10054 11:12:07.392055
10055 11:12:07.395155 Waiting for reply... done.
10056 11:12:07.395267
10057 11:12:07.399132 Sending DHCP request... done.
10058 11:12:07.399221
10059 11:12:07.404075 Waiting for reply... done.
10060 11:12:07.404165
10061 11:12:07.404231 My ip is 192.168.201.12
10062 11:12:07.404315
10063 11:12:07.407275 The DHCP server ip is 192.168.201.1
10064 11:12:07.407358
10065 11:12:07.414228 TFTP server IP predefined by user: 192.168.201.1
10066 11:12:07.414321
10067 11:12:07.420700 Bootfile predefined by user: 12925665/tftp-deploy-qak9d4qr/kernel/image.itb
10068 11:12:07.420799
10069 11:12:07.420864 Sending tftp read request... done.
10070 11:12:07.423951
10071 11:12:07.427413 Waiting for the transfer...
10072 11:12:07.427504
10073 11:12:07.696842 00000000 ################################################################
10074 11:12:07.697032
10075 11:12:07.966520 00080000 ################################################################
10076 11:12:07.966747
10077 11:12:08.228946 00100000 ################################################################
10078 11:12:08.229099
10079 11:12:08.493851 00180000 ################################################################
10080 11:12:08.494032
10081 11:12:08.767911 00200000 ################################################################
10082 11:12:08.768093
10083 11:12:09.037698 00280000 ################################################################
10084 11:12:09.037920
10085 11:12:09.297591 00300000 ################################################################
10086 11:12:09.297816
10087 11:12:09.578133 00380000 ################################################################
10088 11:12:09.578293
10089 11:12:09.841654 00400000 ################################################################
10090 11:12:09.841874
10091 11:12:10.104979 00480000 ################################################################
10092 11:12:10.105133
10093 11:12:10.363595 00500000 ################################################################
10094 11:12:10.363865
10095 11:12:10.628741 00580000 ################################################################
10096 11:12:10.628970
10097 11:12:10.892864 00600000 ################################################################
10098 11:12:10.893028
10099 11:12:11.157781 00680000 ################################################################
10100 11:12:11.157993
10101 11:12:11.432613 00700000 ################################################################
10102 11:12:11.432838
10103 11:12:11.700634 00780000 ################################################################
10104 11:12:11.700787
10105 11:12:11.960390 00800000 ################################################################
10106 11:12:11.960573
10107 11:12:12.229505 00880000 ################################################################
10108 11:12:12.229716
10109 11:12:12.496106 00900000 ################################################################
10110 11:12:12.496334
10111 11:12:12.771256 00980000 ################################################################
10112 11:12:12.771420
10113 11:12:13.044952 00a00000 ################################################################
10114 11:12:13.045171
10115 11:12:13.301519 00a80000 ################################################################
10116 11:12:13.301649
10117 11:12:13.566227 00b00000 ################################################################
10118 11:12:13.566460
10119 11:12:13.831912 00b80000 ################################################################
10120 11:12:13.832061
10121 11:12:14.097120 00c00000 ################################################################
10122 11:12:14.097264
10123 11:12:14.360592 00c80000 ################################################################
10124 11:12:14.360755
10125 11:12:14.624239 00d00000 ################################################################
10126 11:12:14.624443
10127 11:12:14.895316 00d80000 ################################################################
10128 11:12:14.895468
10129 11:12:15.171661 00e00000 ################################################################
10130 11:12:15.171814
10131 11:12:15.429033 00e80000 ################################################################
10132 11:12:15.429171
10133 11:12:15.698589 00f00000 ################################################################
10134 11:12:15.698740
10135 11:12:15.965363 00f80000 ################################################################
10136 11:12:15.965510
10137 11:12:16.233403 01000000 ################################################################
10138 11:12:16.233555
10139 11:12:16.492584 01080000 ################################################################
10140 11:12:16.492790
10141 11:12:16.762314 01100000 ################################################################
10142 11:12:16.762463
10143 11:12:17.027542 01180000 ################################################################
10144 11:12:17.027720
10145 11:12:17.294890 01200000 ################################################################
10146 11:12:17.295065
10147 11:12:17.555840 01280000 ################################################################
10148 11:12:17.556017
10149 11:12:17.818149 01300000 ################################################################
10150 11:12:17.818327
10151 11:12:18.081048 01380000 ################################################################
10152 11:12:18.081237
10153 11:12:18.368061 01400000 ################################################################
10154 11:12:18.368254
10155 11:12:18.635380 01480000 ################################################################
10156 11:12:18.635532
10157 11:12:18.909751 01500000 ################################################################
10158 11:12:18.909966
10159 11:12:19.198067 01580000 ################################################################
10160 11:12:19.198215
10161 11:12:19.486296 01600000 ################################################################
10162 11:12:19.486467
10163 11:12:19.781813 01680000 ################################################################
10164 11:12:19.781989
10165 11:12:20.085275 01700000 ################################################################
10166 11:12:20.085452
10167 11:12:20.369066 01780000 ################################################################
10168 11:12:20.369237
10169 11:12:20.653125 01800000 ################################################################
10170 11:12:20.653301
10171 11:12:20.951216 01880000 ################################################################
10172 11:12:20.951386
10173 11:12:21.245445 01900000 ################################################################
10174 11:12:21.245601
10175 11:12:21.543797 01980000 ################################################################
10176 11:12:21.543968
10177 11:12:21.833970 01a00000 ################################################################
10178 11:12:21.834115
10179 11:12:22.129032 01a80000 ################################################################
10180 11:12:22.129178
10181 11:12:22.416725 01b00000 ################################################################
10182 11:12:22.416874
10183 11:12:22.698961 01b80000 ################################################################
10184 11:12:22.699133
10185 11:12:22.976816 01c00000 ################################################################
10186 11:12:22.976983
10187 11:12:23.267211 01c80000 ################################################################
10188 11:12:23.267380
10189 11:12:23.534972 01d00000 ################################################################
10190 11:12:23.535154
10191 11:12:23.825082 01d80000 ################################################################
10192 11:12:23.825287
10193 11:12:24.124383 01e00000 ################################################################
10194 11:12:24.124532
10195 11:12:24.423159 01e80000 ################################################################
10196 11:12:24.423304
10197 11:12:24.720906 01f00000 ################################################################
10198 11:12:24.721050
10199 11:12:25.017150 01f80000 ################################################################
10200 11:12:25.017289
10201 11:12:25.300156 02000000 ################################################################
10202 11:12:25.300325
10203 11:12:25.563736 02080000 ################################################################
10204 11:12:25.563876
10205 11:12:25.833501 02100000 ################################################################
10206 11:12:25.833647
10207 11:12:26.120683 02180000 ################################################################
10208 11:12:26.120807
10209 11:12:26.394821 02200000 ################################################################
10210 11:12:26.394984
10211 11:12:26.661299 02280000 ################################################################
10212 11:12:26.661447
10213 11:12:26.925859 02300000 ################################################################
10214 11:12:26.926021
10215 11:12:27.186235 02380000 ################################################################
10216 11:12:27.186397
10217 11:12:27.446935 02400000 ################################################################
10218 11:12:27.447110
10219 11:12:27.721096 02480000 ################################################################
10220 11:12:27.721286
10221 11:12:27.977917 02500000 ################################################################
10222 11:12:27.978054
10223 11:12:28.252130 02580000 ################################################################
10224 11:12:28.252270
10225 11:12:28.521469 02600000 ################################################################
10226 11:12:28.521606
10227 11:12:28.784065 02680000 ################################################################
10228 11:12:28.784233
10229 11:12:29.060994 02700000 ################################################################
10230 11:12:29.061125
10231 11:12:29.325264 02780000 ################################################################
10232 11:12:29.325413
10233 11:12:29.599747 02800000 ################################################################
10234 11:12:29.599921
10235 11:12:29.843470 02880000 ################################################################
10236 11:12:29.843622
10237 11:12:30.092979 02900000 ################################################################
10238 11:12:30.093111
10239 11:12:30.353074 02980000 ################################################################
10240 11:12:30.353281
10241 11:12:30.612025 02a00000 ################################################################
10242 11:12:30.612173
10243 11:12:30.868667 02a80000 ################################################################
10244 11:12:30.868818
10245 11:12:31.131526 02b00000 ################################################################
10246 11:12:31.131702
10247 11:12:31.386229 02b80000 ################################################################
10248 11:12:31.386365
10249 11:12:31.643594 02c00000 ################################################################
10250 11:12:31.643729
10251 11:12:31.898397 02c80000 ################################################################
10252 11:12:31.898586
10253 11:12:32.158824 02d00000 ################################################################
10254 11:12:32.159001
10255 11:12:32.413492 02d80000 ################################################################
10256 11:12:32.413641
10257 11:12:32.667294 02e00000 ################################################################
10258 11:12:32.667438
10259 11:12:32.922803 02e80000 ################################################################
10260 11:12:32.922962
10261 11:12:33.176098 02f00000 ################################################################
10262 11:12:33.176243
10263 11:12:33.424444 02f80000 ################################################################
10264 11:12:33.424614
10265 11:12:33.675452 03000000 ################################################################
10266 11:12:33.675627
10267 11:12:33.937242 03080000 ################################################################
10268 11:12:33.937448
10269 11:12:34.187246 03100000 ################################################################
10270 11:12:34.187411
10271 11:12:34.443125 03180000 ################################################################
10272 11:12:34.443259
10273 11:12:34.709297 03200000 ################################################################
10274 11:12:34.709471
10275 11:12:34.977943 03280000 ################################################################
10276 11:12:34.978111
10277 11:12:35.225772 03300000 ################################################################
10278 11:12:35.225956
10279 11:12:35.476085 03380000 ################################################################
10280 11:12:35.476253
10281 11:12:35.728379 03400000 ################################################################
10282 11:12:35.728520
10283 11:12:35.982552 03480000 ################################################################
10284 11:12:35.982726
10285 11:12:36.234713 03500000 ################################################################
10286 11:12:36.234880
10287 11:12:36.487647 03580000 ################################################################
10288 11:12:36.487817
10289 11:12:36.741832 03600000 ################################################################
10290 11:12:36.742008
10291 11:12:36.993166 03680000 ################################################################
10292 11:12:36.993336
10293 11:12:37.248618 03700000 ################################################################
10294 11:12:37.248767
10295 11:12:37.506075 03780000 ################################################################
10296 11:12:37.506244
10297 11:12:37.768018 03800000 ################################################################
10298 11:12:37.768205
10299 11:12:38.042589 03880000 ################################################################
10300 11:12:38.042757
10301 11:12:38.307267 03900000 ################################################################
10302 11:12:38.307505
10303 11:12:38.560537 03980000 ################################################################
10304 11:12:38.560703
10305 11:12:38.809350 03a00000 ################################################################
10306 11:12:38.809523
10307 11:12:39.063294 03a80000 ################################################################
10308 11:12:39.063438
10309 11:12:39.315981 03b00000 ################################################################
10310 11:12:39.316130
10311 11:12:39.573503 03b80000 ################################################################
10312 11:12:39.573643
10313 11:12:39.833851 03c00000 ################################################################
10314 11:12:39.833988
10315 11:12:40.096742 03c80000 ################################################################
10316 11:12:40.096886
10317 11:12:40.359333 03d00000 ################################################################
10318 11:12:40.359544
10319 11:12:40.620011 03d80000 ################################################################
10320 11:12:40.620179
10321 11:12:40.874688 03e00000 ################################################################
10322 11:12:40.874827
10323 11:12:41.128306 03e80000 ################################################################
10324 11:12:41.128511
10325 11:12:41.385870 03f00000 ################################################################
10326 11:12:41.386083
10327 11:12:41.659247 03f80000 ################################################################
10328 11:12:41.659451
10329 11:12:41.916722 04000000 ################################################################
10330 11:12:41.916930
10331 11:12:42.175312 04080000 ################################################################
10332 11:12:42.175471
10333 11:12:42.426301 04100000 ################################################################
10334 11:12:42.426513
10335 11:12:42.676365 04180000 ################################################################
10336 11:12:42.676575
10337 11:12:42.936696 04200000 ################################################################
10338 11:12:42.936842
10339 11:12:43.192556 04280000 ################################################################
10340 11:12:43.192700
10341 11:12:43.458066 04300000 ################################################################
10342 11:12:43.458208
10343 11:12:43.717251 04380000 ################################################################
10344 11:12:43.717457
10345 11:12:43.970738 04400000 ################################################################
10346 11:12:43.970888
10347 11:12:44.225809 04480000 ################################################################
10348 11:12:44.225949
10349 11:12:44.476987 04500000 ################################################################
10350 11:12:44.477133
10351 11:12:44.730356 04580000 ################################################################
10352 11:12:44.730505
10353 11:12:44.987418 04600000 ################################################################
10354 11:12:44.987564
10355 11:12:45.250794 04680000 ################################################################
10356 11:12:45.250944
10357 11:12:45.510972 04700000 ################################################################
10358 11:12:45.511146
10359 11:12:45.775057 04780000 ################################################################
10360 11:12:45.775273
10361 11:12:46.033296 04800000 ################################################################
10362 11:12:46.033509
10363 11:12:46.286995 04880000 ################################################################
10364 11:12:46.287192
10365 11:12:46.542502 04900000 ################################################################
10366 11:12:46.542663
10367 11:12:46.802366 04980000 ################################################################
10368 11:12:46.802515
10369 11:12:47.054036 04a00000 ################################################################
10370 11:12:47.054197
10371 11:12:47.318069 04a80000 ################################################################
10372 11:12:47.318217
10373 11:12:47.571850 04b00000 ################################################################
10374 11:12:47.572010
10375 11:12:47.839027 04b80000 ################################################################
10376 11:12:47.839220
10377 11:12:48.095950 04c00000 ################################################################
10378 11:12:48.096139
10379 11:12:48.352331 04c80000 ################################################################
10380 11:12:48.352462
10381 11:12:48.614333 04d00000 ################################################################
10382 11:12:48.614472
10383 11:12:48.873200 04d80000 ################################################################
10384 11:12:48.873333
10385 11:12:49.144537 04e00000 ################################################################
10386 11:12:49.144670
10387 11:12:49.405455 04e80000 ################################################################
10388 11:12:49.405595
10389 11:12:49.660945 04f00000 ################################################################
10390 11:12:49.661099
10391 11:12:49.907994 04f80000 ################################################################
10392 11:12:49.908131
10393 11:12:50.163890 05000000 ################################################################
10394 11:12:50.164028
10395 11:12:50.415916 05080000 ################################################################
10396 11:12:50.416090
10397 11:12:50.678895 05100000 ################################################################
10398 11:12:50.679048
10399 11:12:50.934378 05180000 ################################################################
10400 11:12:50.934547
10401 11:12:51.187287 05200000 ################################################################
10402 11:12:51.187416
10403 11:12:51.442717 05280000 ################################################################
10404 11:12:51.442901
10405 11:12:51.699745 05300000 ################################################################
10406 11:12:51.699922
10407 11:12:51.957756 05380000 ################################################################
10408 11:12:51.957929
10409 11:12:52.207991 05400000 ################################################################
10410 11:12:52.208126
10411 11:12:52.463080 05480000 ################################################################
10412 11:12:52.463222
10413 11:12:52.731540 05500000 ################################################################
10414 11:12:52.731707
10415 11:12:52.984725 05580000 ################################################################
10416 11:12:52.984866
10417 11:12:53.235669 05600000 ################################################################
10418 11:12:53.235853
10419 11:12:53.495350 05680000 ################################################################
10420 11:12:53.495550
10421 11:12:53.763400 05700000 ################################################################
10422 11:12:53.763541
10423 11:12:54.029541 05780000 ################################################################
10424 11:12:54.029707
10425 11:12:54.278519 05800000 ################################################################
10426 11:12:54.278667
10427 11:12:54.529366 05880000 ################################################################
10428 11:12:54.529511
10429 11:12:54.788596 05900000 ################################################################
10430 11:12:54.788768
10431 11:12:55.049165 05980000 ################################################################
10432 11:12:55.049334
10433 11:12:55.297516 05a00000 ################################################################
10434 11:12:55.297684
10435 11:12:55.551244 05a80000 ################################################################
10436 11:12:55.551416
10437 11:12:55.801505 05b00000 ################################################################
10438 11:12:55.801654
10439 11:12:56.060414 05b80000 ################################################################
10440 11:12:56.060553
10441 11:12:56.316278 05c00000 ################################################################
10442 11:12:56.316438
10443 11:12:56.567568 05c80000 ################################################################
10444 11:12:56.567714
10445 11:12:56.813700 05d00000 ################################################################
10446 11:12:56.813853
10447 11:12:57.065047 05d80000 ################################################################
10448 11:12:57.065189
10449 11:12:57.319575 05e00000 ################################################################
10450 11:12:57.319720
10451 11:12:57.584422 05e80000 ################################################################
10452 11:12:57.584581
10453 11:12:57.847547 05f00000 ################################################################
10454 11:12:57.847691
10455 11:12:58.099369 05f80000 ################################################################
10456 11:12:58.099514
10457 11:12:58.353522 06000000 ################################################################
10458 11:12:58.353726
10459 11:12:58.605521 06080000 ################################################################
10460 11:12:58.605672
10461 11:12:58.861659 06100000 ################################################################
10462 11:12:58.861800
10463 11:12:59.116683 06180000 ################################################################
10464 11:12:59.116885
10465 11:12:59.375412 06200000 ################################################################
10466 11:12:59.375556
10467 11:12:59.637062 06280000 ################################################################
10468 11:12:59.637203
10469 11:12:59.905482 06300000 ################################################################
10470 11:12:59.905650
10471 11:13:00.178899 06380000 ################################################################
10472 11:13:00.179107
10473 11:13:00.435761 06400000 ################################################################
10474 11:13:00.435905
10475 11:13:00.687345 06480000 ################################################################
10476 11:13:00.687495
10477 11:13:00.945804 06500000 ################################################################
10478 11:13:00.945977
10479 11:13:01.209975 06580000 ################################################################
10480 11:13:01.210120
10481 11:13:01.462678 06600000 ################################################################
10482 11:13:01.462850
10483 11:13:01.713282 06680000 ################################################################
10484 11:13:01.713429
10485 11:13:01.972456 06700000 ################################################################
10486 11:13:01.972633
10487 11:13:02.222526 06780000 ################################################################
10488 11:13:02.222670
10489 11:13:02.476620 06800000 ################################################################
10490 11:13:02.476765
10491 11:13:02.734166 06880000 ################################################################
10492 11:13:02.734341
10493 11:13:02.927586 06900000 ############################################## done.
10494 11:13:02.927754
10495 11:13:02.931216 The bootfile was 110470830 bytes long.
10496 11:13:02.931324
10497 11:13:02.934370 Sending tftp read request... done.
10498 11:13:02.934478
10499 11:13:02.938021 Waiting for the transfer...
10500 11:13:02.938101
10501 11:13:02.938166 00000000 # done.
10502 11:13:02.938235
10503 11:13:02.947418 Command line loaded dynamically from TFTP file: 12925665/tftp-deploy-qak9d4qr/kernel/cmdline
10504 11:13:02.947512
10505 11:13:02.960607 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10506 11:13:02.960695
10507 11:13:02.960761 Loading FIT.
10508 11:13:02.960822
10509 11:13:02.964466 Image ramdisk-1 has 98363817 bytes.
10510 11:13:02.964548
10511 11:13:02.967534 Image fdt-1 has 47278 bytes.
10512 11:13:02.967618
10513 11:13:02.970608 Image kernel-1 has 12057697 bytes.
10514 11:13:02.970691
10515 11:13:02.977378 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10516 11:13:02.977462
10517 11:13:02.997194 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10518 11:13:02.997283
10519 11:13:03.000525 Choosing best match conf-1 for compat google,spherion-rev2.
10520 11:13:03.005954
10521 11:13:03.010509 Connected to device vid:did:rid of 1ae0:0028:00
10522 11:13:03.018617
10523 11:13:03.022303 tpm_get_response: command 0x17b, return code 0x0
10524 11:13:03.022386
10525 11:13:03.025037 ec_init: CrosEC protocol v3 supported (256, 248)
10526 11:13:03.029217
10527 11:13:03.032274 tpm_cleanup: add release locality here.
10528 11:13:03.032365
10529 11:13:03.032431 Shutting down all USB controllers.
10530 11:13:03.035933
10531 11:13:03.036016 Removing current net device
10532 11:13:03.036081
10533 11:13:03.042709 Exiting depthcharge with code 4 at timestamp: 91125790
10534 11:13:03.042793
10535 11:13:03.045834 LZMA decompressing kernel-1 to 0x821a6718
10536 11:13:03.045935
10537 11:13:03.049333 LZMA decompressing kernel-1 to 0x40000000
10538 11:13:04.550163
10539 11:13:04.550304 jumping to kernel
10540 11:13:04.550896 end: 2.2.4 bootloader-commands (duration 00:01:03) [common]
10541 11:13:04.551000 start: 2.2.5 auto-login-action (timeout 00:03:22) [common]
10542 11:13:04.551076 Setting prompt string to ['Linux version [0-9]']
10543 11:13:04.551143 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10544 11:13:04.551209 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10545 11:13:04.631637
10546 11:13:04.634832 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10547 11:13:04.638769 start: 2.2.5.1 login-action (timeout 00:03:22) [common]
10548 11:13:04.638860 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10549 11:13:04.638931 Setting prompt string to []
10550 11:13:04.639011 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10551 11:13:04.639083 Using line separator: #'\n'#
10552 11:13:04.639143 No login prompt set.
10553 11:13:04.639203 Parsing kernel messages
10554 11:13:04.639257 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10555 11:13:04.639394 [login-action] Waiting for messages, (timeout 00:03:22)
10556 11:13:04.639458 Waiting using forced prompt support (timeout 00:01:41)
10557 11:13:04.658312 [ 0.000000] Linux version 6.1.80-cip16 (KernelCI@build-j128891-arm64-gcc-10-defconfig-arm64-chromebook-nrg4h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024
10558 11:13:04.661875 [ 0.000000] random: crng init done
10559 11:13:04.668214 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10560 11:13:04.671828 [ 0.000000] efi: UEFI not found.
10561 11:13:04.678253 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10562 11:13:04.685182 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10563 11:13:04.694947 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10564 11:13:04.705248 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10565 11:13:04.711972 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10566 11:13:04.715033 [ 0.000000] printk: bootconsole [mtk8250] enabled
10567 11:13:04.723705 [ 0.000000] NUMA: No NUMA configuration found
10568 11:13:04.730607 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10569 11:13:04.737425 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10570 11:13:04.737509 [ 0.000000] Zone ranges:
10571 11:13:04.743931 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10572 11:13:04.746832 [ 0.000000] DMA32 empty
10573 11:13:04.753543 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10574 11:13:04.756807 [ 0.000000] Movable zone start for each node
10575 11:13:04.760368 [ 0.000000] Early memory node ranges
10576 11:13:04.767003 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10577 11:13:04.773576 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10578 11:13:04.780177 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10579 11:13:04.786655 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10580 11:13:04.793505 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10581 11:13:04.799601 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10582 11:13:04.856300 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10583 11:13:04.863567 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10584 11:13:04.869819 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10585 11:13:04.872968 [ 0.000000] psci: probing for conduit method from DT.
10586 11:13:04.879853 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10587 11:13:04.883462 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10588 11:13:04.889888 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10589 11:13:04.893067 [ 0.000000] psci: SMC Calling Convention v1.2
10590 11:13:04.900212 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10591 11:13:04.903408 [ 0.000000] Detected VIPT I-cache on CPU0
10592 11:13:04.909545 [ 0.000000] CPU features: detected: GIC system register CPU interface
10593 11:13:04.916422 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10594 11:13:04.923173 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10595 11:13:04.929948 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10596 11:13:04.936144 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10597 11:13:04.942955 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10598 11:13:04.949859 [ 0.000000] alternatives: applying boot alternatives
10599 11:13:04.952927 [ 0.000000] Fallback order for Node 0: 0
10600 11:13:04.962914 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10601 11:13:04.963020 [ 0.000000] Policy zone: Normal
10602 11:13:04.979382 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10603 11:13:04.989529 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10604 11:13:05.000719 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10605 11:13:05.011229 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10606 11:13:05.017468 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10607 11:13:05.020462 <6>[ 0.000000] software IO TLB: area num 8.
10608 11:13:05.077426 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10609 11:13:05.226572 <6>[ 0.000000] Memory: 7871136K/8385536K available (18048K kernel code, 4118K rwdata, 19616K rodata, 8448K init, 616K bss, 481632K reserved, 32768K cma-reserved)
10610 11:13:05.233531 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10611 11:13:05.240117 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10612 11:13:05.243253 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10613 11:13:05.250117 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10614 11:13:05.256735 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10615 11:13:05.259791 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10616 11:13:05.269440 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10617 11:13:05.276228 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10618 11:13:05.282975 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10619 11:13:05.289311 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10620 11:13:05.293127 <6>[ 0.000000] GICv3: 608 SPIs implemented
10621 11:13:05.296218 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10622 11:13:05.302977 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10623 11:13:05.305866 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10624 11:13:05.313064 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10625 11:13:05.325924 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10626 11:13:05.335941 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10627 11:13:05.345848 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10628 11:13:05.353547 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10629 11:13:05.366395 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10630 11:13:05.373406 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10631 11:13:05.379873 <6>[ 0.009182] Console: colour dummy device 80x25
10632 11:13:05.389710 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10633 11:13:05.396083 <6>[ 0.024352] pid_max: default: 32768 minimum: 301
10634 11:13:05.399820 <6>[ 0.029223] LSM: Security Framework initializing
10635 11:13:05.406060 <6>[ 0.034192] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10636 11:13:05.416345 <6>[ 0.042012] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10637 11:13:05.422605 <6>[ 0.051390] cblist_init_generic: Setting adjustable number of callback queues.
10638 11:13:05.429873 <6>[ 0.058879] cblist_init_generic: Setting shift to 3 and lim to 1.
10639 11:13:05.439515 <6>[ 0.065219] cblist_init_generic: Setting adjustable number of callback queues.
10640 11:13:05.443028 <6>[ 0.072646] cblist_init_generic: Setting shift to 3 and lim to 1.
10641 11:13:05.449712 <6>[ 0.079046] rcu: Hierarchical SRCU implementation.
10642 11:13:05.456529 <6>[ 0.084061] rcu: Max phase no-delay instances is 1000.
10643 11:13:05.462954 <6>[ 0.091119] EFI services will not be available.
10644 11:13:05.466014 <6>[ 0.096076] smp: Bringing up secondary CPUs ...
10645 11:13:05.474122 <6>[ 0.101128] Detected VIPT I-cache on CPU1
10646 11:13:05.480539 <6>[ 0.101197] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10647 11:13:05.487059 <6>[ 0.101230] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10648 11:13:05.490290 <6>[ 0.101569] Detected VIPT I-cache on CPU2
10649 11:13:05.497248 <6>[ 0.101618] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10650 11:13:05.507341 <6>[ 0.101634] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10651 11:13:05.510520 <6>[ 0.101892] Detected VIPT I-cache on CPU3
10652 11:13:05.517182 <6>[ 0.101938] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10653 11:13:05.523997 <6>[ 0.101952] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10654 11:13:05.527059 <6>[ 0.102257] CPU features: detected: Spectre-v4
10655 11:13:05.533685 <6>[ 0.102264] CPU features: detected: Spectre-BHB
10656 11:13:05.536956 <6>[ 0.102269] Detected PIPT I-cache on CPU4
10657 11:13:05.543502 <6>[ 0.102325] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10658 11:13:05.550425 <6>[ 0.102342] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10659 11:13:05.557003 <6>[ 0.102638] Detected PIPT I-cache on CPU5
10660 11:13:05.563760 <6>[ 0.102701] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10661 11:13:05.569813 <6>[ 0.102717] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10662 11:13:05.573637 <6>[ 0.103002] Detected PIPT I-cache on CPU6
10663 11:13:05.580155 <6>[ 0.103067] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10664 11:13:05.586647 <6>[ 0.103084] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10665 11:13:05.593527 <6>[ 0.103384] Detected PIPT I-cache on CPU7
10666 11:13:05.600049 <6>[ 0.103449] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10667 11:13:05.606636 <6>[ 0.103465] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10668 11:13:05.609851 <6>[ 0.103513] smp: Brought up 1 node, 8 CPUs
10669 11:13:05.616646 <6>[ 0.244883] SMP: Total of 8 processors activated.
10670 11:13:05.619768 <6>[ 0.249804] CPU features: detected: 32-bit EL0 Support
10671 11:13:05.629926 <6>[ 0.255168] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10672 11:13:05.636056 <6>[ 0.264023] CPU features: detected: Common not Private translations
10673 11:13:05.642781 <6>[ 0.270499] CPU features: detected: CRC32 instructions
10674 11:13:05.645958 <6>[ 0.275851] CPU features: detected: RCpc load-acquire (LDAPR)
10675 11:13:05.652863 <6>[ 0.281848] CPU features: detected: LSE atomic instructions
10676 11:13:05.659479 <6>[ 0.287665] CPU features: detected: Privileged Access Never
10677 11:13:05.666303 <6>[ 0.293445] CPU features: detected: RAS Extension Support
10678 11:13:05.672695 <6>[ 0.299054] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10679 11:13:05.676527 <6>[ 0.306272] CPU: All CPU(s) started at EL2
10680 11:13:05.682966 <6>[ 0.310589] alternatives: applying system-wide alternatives
10681 11:13:05.692029 <6>[ 0.321383] devtmpfs: initialized
10682 11:13:05.707195 <6>[ 0.330287] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10683 11:13:05.714254 <6>[ 0.340252] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10684 11:13:05.720378 <6>[ 0.348296] pinctrl core: initialized pinctrl subsystem
10685 11:13:05.724114 <6>[ 0.354969] DMI not present or invalid.
10686 11:13:05.730623 <6>[ 0.359385] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10687 11:13:05.740513 <6>[ 0.366251] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10688 11:13:05.746747 <6>[ 0.373844] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10689 11:13:05.756655 <6>[ 0.382067] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10690 11:13:05.760308 <6>[ 0.390309] audit: initializing netlink subsys (disabled)
10691 11:13:05.769788 <5>[ 0.396002] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10692 11:13:05.776708 <6>[ 0.396713] thermal_sys: Registered thermal governor 'step_wise'
10693 11:13:05.783305 <6>[ 0.403970] thermal_sys: Registered thermal governor 'power_allocator'
10694 11:13:05.786733 <6>[ 0.410228] cpuidle: using governor menu
10695 11:13:05.793290 <6>[ 0.421188] NET: Registered PF_QIPCRTR protocol family
10696 11:13:05.799950 <6>[ 0.426665] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10697 11:13:05.803321 <6>[ 0.433771] ASID allocator initialised with 32768 entries
10698 11:13:05.810609 <6>[ 0.440345] Serial: AMBA PL011 UART driver
10699 11:13:05.819827 <4>[ 0.449128] Trying to register duplicate clock ID: 134
10700 11:13:05.874208 <6>[ 0.506898] KASLR enabled
10701 11:13:05.888563 <6>[ 0.514601] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10702 11:13:05.894929 <6>[ 0.521615] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10703 11:13:05.901976 <6>[ 0.528107] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10704 11:13:05.908587 <6>[ 0.535111] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10705 11:13:05.915105 <6>[ 0.541601] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10706 11:13:05.921851 <6>[ 0.548605] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10707 11:13:05.928039 <6>[ 0.555092] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10708 11:13:05.934815 <6>[ 0.562099] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10709 11:13:05.938148 <6>[ 0.569618] ACPI: Interpreter disabled.
10710 11:13:05.946664 <6>[ 0.576040] iommu: Default domain type: Translated
10711 11:13:05.953364 <6>[ 0.581153] iommu: DMA domain TLB invalidation policy: strict mode
10712 11:13:05.956556 <5>[ 0.587817] SCSI subsystem initialized
10713 11:13:05.963321 <6>[ 0.591978] usbcore: registered new interface driver usbfs
10714 11:13:05.969559 <6>[ 0.597711] usbcore: registered new interface driver hub
10715 11:13:05.972738 <6>[ 0.603260] usbcore: registered new device driver usb
10716 11:13:05.980203 <6>[ 0.609368] pps_core: LinuxPPS API ver. 1 registered
10717 11:13:05.990071 <6>[ 0.614561] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10718 11:13:05.993114 <6>[ 0.623909] PTP clock support registered
10719 11:13:05.996684 <6>[ 0.628152] EDAC MC: Ver: 3.0.0
10720 11:13:06.003676 <6>[ 0.633318] FPGA manager framework
10721 11:13:06.010613 <6>[ 0.636994] Advanced Linux Sound Architecture Driver Initialized.
10722 11:13:06.013451 <6>[ 0.643779] vgaarb: loaded
10723 11:13:06.020406 <6>[ 0.646949] clocksource: Switched to clocksource arch_sys_counter
10724 11:13:06.023421 <5>[ 0.653379] VFS: Disk quotas dquot_6.6.0
10725 11:13:06.030137 <6>[ 0.657564] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10726 11:13:06.033699 <6>[ 0.664751] pnp: PnP ACPI: disabled
10727 11:13:06.042076 <6>[ 0.671418] NET: Registered PF_INET protocol family
10728 11:13:06.052421 <6>[ 0.677025] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10729 11:13:06.063407 <6>[ 0.689365] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10730 11:13:06.073261 <6>[ 0.698182] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10731 11:13:06.079628 <6>[ 0.706153] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10732 11:13:06.086485 <6>[ 0.714851] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10733 11:13:06.095398 <6>[ 0.724592] TCP: Hash tables configured (established 65536 bind 65536)
10734 11:13:06.105183 <6>[ 0.731455] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10735 11:13:06.112141 <6>[ 0.738653] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10736 11:13:06.118534 <6>[ 0.746356] NET: Registered PF_UNIX/PF_LOCAL protocol family
10737 11:13:06.124962 <6>[ 0.752447] RPC: Registered named UNIX socket transport module.
10738 11:13:06.128512 <6>[ 0.758593] RPC: Registered udp transport module.
10739 11:13:06.135219 <6>[ 0.763525] RPC: Registered tcp transport module.
10740 11:13:06.142032 <6>[ 0.768458] RPC: Registered tcp NFSv4.1 backchannel transport module.
10741 11:13:06.145111 <6>[ 0.775124] PCI: CLS 0 bytes, default 64
10742 11:13:06.148249 <6>[ 0.779525] Unpacking initramfs...
10743 11:13:06.165153 <6>[ 0.791576] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10744 11:13:06.175240 <6>[ 0.800239] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10745 11:13:06.178740 <6>[ 0.809122] kvm [1]: IPA Size Limit: 40 bits
10746 11:13:06.185201 <6>[ 0.813648] kvm [1]: GICv3: no GICV resource entry
10747 11:13:06.188323 <6>[ 0.818668] kvm [1]: disabling GICv2 emulation
10748 11:13:06.195311 <6>[ 0.823356] kvm [1]: GIC system register CPU interface enabled
10749 11:13:06.201710 <6>[ 0.830988] kvm [1]: vgic interrupt IRQ18
10750 11:13:06.205275 <6>[ 0.835370] kvm [1]: VHE mode initialized successfully
10751 11:13:06.212051 <5>[ 0.841769] Initialise system trusted keyrings
10752 11:13:06.218866 <6>[ 0.846542] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10753 11:13:06.226649 <6>[ 0.856522] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10754 11:13:06.233723 <5>[ 0.862905] NFS: Registering the id_resolver key type
10755 11:13:06.237073 <5>[ 0.868204] Key type id_resolver registered
10756 11:13:06.243450 <5>[ 0.872620] Key type id_legacy registered
10757 11:13:06.250370 <6>[ 0.876896] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10758 11:13:06.256719 <6>[ 0.883817] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10759 11:13:06.263592 <6>[ 0.891532] 9p: Installing v9fs 9p2000 file system support
10760 11:13:06.300521 <5>[ 0.930086] Key type asymmetric registered
10761 11:13:06.304175 <5>[ 0.934415] Asymmetric key parser 'x509' registered
10762 11:13:06.313728 <6>[ 0.939554] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10763 11:13:06.316982 <6>[ 0.947168] io scheduler mq-deadline registered
10764 11:13:06.320714 <6>[ 0.951928] io scheduler kyber registered
10765 11:13:06.339307 <6>[ 0.968785] EINJ: ACPI disabled.
10766 11:13:06.371303 <4>[ 0.993910] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10767 11:13:06.381153 <4>[ 1.004514] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10768 11:13:06.395566 <6>[ 1.024838] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10769 11:13:06.403361 <6>[ 1.032774] printk: console [ttyS0] disabled
10770 11:13:06.430945 <6>[ 1.057407] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10771 11:13:06.437446 <6>[ 1.066906] printk: console [ttyS0] enabled
10772 11:13:06.440934 <6>[ 1.066906] printk: console [ttyS0] enabled
10773 11:13:06.447421 <6>[ 1.075821] printk: bootconsole [mtk8250] disabled
10774 11:13:06.450954 <6>[ 1.075821] printk: bootconsole [mtk8250] disabled
10775 11:13:06.457570 <6>[ 1.086875] SuperH (H)SCI(F) driver initialized
10776 11:13:06.460764 <6>[ 1.092149] msm_serial: driver initialized
10777 11:13:06.475046 <6>[ 1.101069] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10778 11:13:06.485114 <6>[ 1.109619] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10779 11:13:06.491196 <6>[ 1.118162] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10780 11:13:06.501767 <6>[ 1.126791] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10781 11:13:06.508087 <6>[ 1.135497] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10782 11:13:06.517863 <6>[ 1.144210] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10783 11:13:06.528100 <6>[ 1.152749] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10784 11:13:06.534966 <6>[ 1.161545] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10785 11:13:06.544789 <6>[ 1.170088] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10786 11:13:06.556221 <6>[ 1.185670] loop: module loaded
10787 11:13:06.562587 <6>[ 1.191321] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10788 11:13:06.585206 <4>[ 1.214435] mtk-pmic-keys: Failed to locate of_node [id: -1]
10789 11:13:06.591343 <6>[ 1.221203] megasas: 07.719.03.00-rc1
10790 11:13:06.601221 <6>[ 1.230685] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10791 11:13:06.608651 <6>[ 1.238338] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10792 11:13:06.625190 <6>[ 1.254936] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10793 11:13:06.681695 <6>[ 1.304367] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10794 11:13:10.146669 <6>[ 4.776807] Freeing initrd memory: 96056K
10795 11:13:10.157054 <6>[ 4.787188] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10796 11:13:10.168137 <6>[ 4.798089] tun: Universal TUN/TAP device driver, 1.6
10797 11:13:10.171609 <6>[ 4.804150] thunder_xcv, ver 1.0
10798 11:13:10.174653 <6>[ 4.807653] thunder_bgx, ver 1.0
10799 11:13:10.178463 <6>[ 4.811146] nicpf, ver 1.0
10800 11:13:10.188499 <6>[ 4.815158] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10801 11:13:10.192207 <6>[ 4.822634] hns3: Copyright (c) 2017 Huawei Corporation.
10802 11:13:10.198274 <6>[ 4.828221] hclge is initializing
10803 11:13:10.202018 <6>[ 4.831803] e1000: Intel(R) PRO/1000 Network Driver
10804 11:13:10.208207 <6>[ 4.836932] e1000: Copyright (c) 1999-2006 Intel Corporation.
10805 11:13:10.211944 <6>[ 4.842952] e1000e: Intel(R) PRO/1000 Network Driver
10806 11:13:10.218127 <6>[ 4.848168] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10807 11:13:10.224877 <6>[ 4.854359] igb: Intel(R) Gigabit Ethernet Network Driver
10808 11:13:10.231516 <6>[ 4.860010] igb: Copyright (c) 2007-2014 Intel Corporation.
10809 11:13:10.238212 <6>[ 4.865846] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10810 11:13:10.244678 <6>[ 4.872364] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10811 11:13:10.248092 <6>[ 4.878829] sky2: driver version 1.30
10812 11:13:10.254556 <6>[ 4.883822] VFIO - User Level meta-driver version: 0.3
10813 11:13:10.262401 <6>[ 4.892064] usbcore: registered new interface driver usb-storage
10814 11:13:10.268741 <6>[ 4.898505] usbcore: registered new device driver onboard-usb-hub
10815 11:13:10.277847 <6>[ 4.907665] mt6397-rtc mt6359-rtc: registered as rtc0
10816 11:13:10.287868 <6>[ 4.913130] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T11:10:21 UTC (1709464221)
10817 11:13:10.291023 <6>[ 4.922686] i2c_dev: i2c /dev entries driver
10818 11:13:10.307596 <6>[ 4.934382] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10819 11:13:10.327567 <6>[ 4.957386] cpu cpu0: EM: created perf domain
10820 11:13:10.330486 <6>[ 4.962329] cpu cpu4: EM: created perf domain
10821 11:13:10.337805 <6>[ 4.967898] sdhci: Secure Digital Host Controller Interface driver
10822 11:13:10.344849 <6>[ 4.974331] sdhci: Copyright(c) Pierre Ossman
10823 11:13:10.351095 <6>[ 4.979286] Synopsys Designware Multimedia Card Interface Driver
10824 11:13:10.357749 <6>[ 4.985928] sdhci-pltfm: SDHCI platform and OF driver helper
10825 11:13:10.361302 <6>[ 4.986039] mmc0: CQHCI version 5.10
10826 11:13:10.367800 <6>[ 4.996284] ledtrig-cpu: registered to indicate activity on CPUs
10827 11:13:10.374834 <6>[ 5.003403] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10828 11:13:10.381455 <6>[ 5.010469] usbcore: registered new interface driver usbhid
10829 11:13:10.384493 <6>[ 5.016291] usbhid: USB HID core driver
10830 11:13:10.391298 <6>[ 5.020482] spi_master spi0: will run message pump with realtime priority
10831 11:13:10.435871 <6>[ 5.058999] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10832 11:13:10.454477 <6>[ 5.074471] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10833 11:13:10.462031 <6>[ 5.089346] cros-ec-spi spi0.0: Chrome EC device registered
10834 11:13:10.465141 <6>[ 5.089456] mmc0: Command Queue Engine enabled
10835 11:13:10.472006 <6>[ 5.099920] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10836 11:13:10.478403 <6>[ 5.107270] mmcblk0: mmc0:0001 DA4128 116 GiB
10837 11:13:10.485144 <6>[ 5.108468] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10838 11:13:10.491749 <6>[ 5.117492] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10839 11:13:10.498608 <6>[ 5.122378] NET: Registered PF_PACKET protocol family
10840 11:13:10.501928 <6>[ 5.128664] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10841 11:13:10.508124 <6>[ 5.132559] 9pnet: Installing 9P2000 support
10842 11:13:10.511650 <6>[ 5.138433] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10843 11:13:10.518584 <5>[ 5.142260] Key type dns_resolver registered
10844 11:13:10.524937 <6>[ 5.148137] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10845 11:13:10.528082 <6>[ 5.152428] registered taskstats version 1
10846 11:13:10.531818 <5>[ 5.162857] Loading compiled-in X.509 certificates
10847 11:13:10.561985 <4>[ 5.185404] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10848 11:13:10.571852 <4>[ 5.196094] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10849 11:13:10.578632 <3>[ 5.206621] debugfs: File 'uA_load' in directory '/' already present!
10850 11:13:10.585269 <3>[ 5.213319] debugfs: File 'min_uV' in directory '/' already present!
10851 11:13:10.592113 <3>[ 5.219990] debugfs: File 'max_uV' in directory '/' already present!
10852 11:13:10.598305 <3>[ 5.226603] debugfs: File 'constraint_flags' in directory '/' already present!
10853 11:13:10.610410 <3>[ 5.237325] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10854 11:13:10.622754 <6>[ 5.252978] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10855 11:13:10.630120 <6>[ 5.259957] xhci-mtk 11200000.usb: xHCI Host Controller
10856 11:13:10.636661 <6>[ 5.265481] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10857 11:13:10.647005 <6>[ 5.273419] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10858 11:13:10.653505 <6>[ 5.282861] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10859 11:13:10.659657 <6>[ 5.288955] xhci-mtk 11200000.usb: xHCI Host Controller
10860 11:13:10.666400 <6>[ 5.294436] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10861 11:13:10.673122 <6>[ 5.302091] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10862 11:13:10.679975 <6>[ 5.309913] hub 1-0:1.0: USB hub found
10863 11:13:10.683066 <6>[ 5.313940] hub 1-0:1.0: 1 port detected
10864 11:13:10.689697 <6>[ 5.318241] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10865 11:13:10.697277 <6>[ 5.326964] hub 2-0:1.0: USB hub found
10866 11:13:10.700236 <6>[ 5.330991] hub 2-0:1.0: 1 port detected
10867 11:13:10.707601 <6>[ 5.337715] mtk-msdc 11f70000.mmc: Got CD GPIO
10868 11:13:10.721080 <6>[ 5.347543] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10869 11:13:10.727211 <6>[ 5.355564] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10870 11:13:10.737153 <4>[ 5.363490] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10871 11:13:10.747118 <6>[ 5.373053] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10872 11:13:10.754303 <6>[ 5.381131] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10873 11:13:10.760492 <6>[ 5.389151] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10874 11:13:10.770325 <6>[ 5.397071] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10875 11:13:10.776897 <6>[ 5.404888] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10876 11:13:10.786973 <6>[ 5.412704] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10877 11:13:10.796915 <6>[ 5.423159] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10878 11:13:10.803872 <6>[ 5.431525] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10879 11:13:10.813953 <6>[ 5.439869] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10880 11:13:10.820382 <6>[ 5.448208] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10881 11:13:10.830021 <6>[ 5.456546] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10882 11:13:10.837018 <6>[ 5.464884] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10883 11:13:10.846431 <6>[ 5.473221] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10884 11:13:10.853187 <6>[ 5.481565] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10885 11:13:10.863579 <6>[ 5.489902] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10886 11:13:10.870119 <6>[ 5.498239] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10887 11:13:10.879761 <6>[ 5.506576] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10888 11:13:10.889848 <6>[ 5.514914] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10889 11:13:10.896552 <6>[ 5.523252] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10890 11:13:10.906386 <6>[ 5.531592] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10891 11:13:10.913199 <6>[ 5.539929] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10892 11:13:10.919559 <6>[ 5.548651] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10893 11:13:10.926369 <6>[ 5.555815] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10894 11:13:10.933059 <6>[ 5.562573] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10895 11:13:10.939321 <6>[ 5.569328] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10896 11:13:10.950005 <6>[ 5.576261] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10897 11:13:10.956241 <6>[ 5.583110] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10898 11:13:10.966306 <6>[ 5.592247] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10899 11:13:10.975958 <6>[ 5.601367] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10900 11:13:10.986108 <6>[ 5.610661] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10901 11:13:10.995605 <6>[ 5.620128] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10902 11:13:11.002376 <6>[ 5.629596] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10903 11:13:11.012229 <6>[ 5.638716] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10904 11:13:11.022480 <6>[ 5.648182] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10905 11:13:11.032259 <6>[ 5.657300] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10906 11:13:11.042483 <6>[ 5.666595] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10907 11:13:11.052169 <6>[ 5.676755] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10908 11:13:11.062188 <6>[ 5.688398] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10909 11:13:11.112307 <6>[ 5.739152] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10910 11:13:11.267120 <6>[ 5.897171] hub 1-1:1.0: USB hub found
10911 11:13:11.270683 <6>[ 5.901710] hub 1-1:1.0: 4 ports detected
10912 11:13:11.280542 <6>[ 5.910340] hub 1-1:1.0: USB hub found
10913 11:13:11.283628 <6>[ 5.914679] hub 1-1:1.0: 4 ports detected
10914 11:13:11.392700 <6>[ 6.019556] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10915 11:13:11.419207 <6>[ 6.049425] hub 2-1:1.0: USB hub found
10916 11:13:11.423021 <6>[ 6.053953] hub 2-1:1.0: 3 ports detected
10917 11:13:11.432571 <6>[ 6.062351] hub 2-1:1.0: USB hub found
10918 11:13:11.435679 <6>[ 6.066813] hub 2-1:1.0: 3 ports detected
10919 11:13:11.608475 <6>[ 6.235267] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10920 11:13:11.740965 <6>[ 6.371086] hub 1-1.4:1.0: USB hub found
10921 11:13:11.744197 <6>[ 6.375752] hub 1-1.4:1.0: 2 ports detected
10922 11:13:11.753968 <6>[ 6.383841] hub 1-1.4:1.0: USB hub found
10923 11:13:11.756971 <6>[ 6.388394] hub 1-1.4:1.0: 2 ports detected
10924 11:13:11.820702 <6>[ 6.447455] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10925 11:13:12.052547 <6>[ 6.679266] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10926 11:13:12.244279 <6>[ 6.871201] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10927 11:13:23.333645 <6>[ 17.968267] ALSA device list:
10928 11:13:23.339872 <6>[ 17.971561] No soundcards found.
10929 11:13:23.348263 <6>[ 17.979619] Freeing unused kernel memory: 8448K
10930 11:13:23.351687 <6>[ 17.985004] Run /init as init process
10931 11:13:23.397228 <6>[ 18.028380] NET: Registered PF_INET6 protocol family
10932 11:13:23.403361 <6>[ 18.034597] Segment Routing with IPv6
10933 11:13:23.406948 <6>[ 18.038550] In-situ OAM (IOAM) with IPv6
10934 11:13:23.437714 <30>[ 18.052387] systemd[1]: systemd 247.3-7+deb11u4 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10935 11:13:23.444837 <30>[ 18.076120] systemd[1]: Detected architecture arm64.
10936 11:13:23.444961
10937 11:13:23.451145 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10938 11:13:23.451265
10939 11:13:23.463708 <30>[ 18.095282] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10940 11:13:23.587480 <30>[ 18.215413] systemd[1]: Queued start job for default target Graphical Interface.
10941 11:13:23.628912 <30>[ 18.260289] systemd[1]: Created slice system-getty.slice.
10942 11:13:23.635075 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10943 11:13:23.656678 <30>[ 18.288448] systemd[1]: Created slice system-modprobe.slice.
10944 11:13:23.663742 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10945 11:13:23.680059 <30>[ 18.311734] systemd[1]: Created slice system-serial\x2dgetty.slice.
10946 11:13:23.690174 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10947 11:13:23.704989 <30>[ 18.336498] systemd[1]: Created slice User and Session Slice.
10948 11:13:23.711357 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10949 11:13:23.731548 <30>[ 18.359920] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10950 11:13:23.741765 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10951 11:13:23.759662 <30>[ 18.387984] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10952 11:13:23.766321 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10953 11:13:23.790974 <30>[ 18.415732] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10954 11:13:23.797630 <30>[ 18.427985] systemd[1]: Reached target Local Encrypted Volumes.
10955 11:13:23.803901 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10956 11:13:23.819883 <30>[ 18.451565] systemd[1]: Reached target Paths.
10957 11:13:23.823439 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10958 11:13:23.839612 <30>[ 18.471221] systemd[1]: Reached target Remote File Systems.
10959 11:13:23.846008 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10960 11:13:23.859806 <30>[ 18.491210] systemd[1]: Reached target Slices.
10961 11:13:23.863103 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10962 11:13:23.879431 <30>[ 18.511254] systemd[1]: Reached target Swap.
10963 11:13:23.883213 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10964 11:13:23.903868 <30>[ 18.531739] systemd[1]: Listening on initctl Compatibility Named Pipe.
10965 11:13:23.910048 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10966 11:13:23.924877 <30>[ 18.556659] systemd[1]: Listening on Journal Audit Socket.
10967 11:13:23.931361 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10968 11:13:23.948896 <30>[ 18.580380] systemd[1]: Listening on Journal Socket (/dev/log).
10969 11:13:23.955205 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10970 11:13:23.972914 <30>[ 18.604453] systemd[1]: Listening on Journal Socket.
10971 11:13:23.979723 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10972 11:13:23.992442 <30>[ 18.623796] systemd[1]: Listening on udev Control Socket.
10973 11:13:23.998565 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10974 11:13:24.017004 <30>[ 18.648280] systemd[1]: Listening on udev Kernel Socket.
10975 11:13:24.023271 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10976 11:13:24.063829 <30>[ 18.695413] systemd[1]: Mounting Huge Pages File System...
10977 11:13:24.070507 Mounting [0;1;39mHuge Pages File System[0m...
10978 11:13:24.087731 <30>[ 18.719094] systemd[1]: Mounting POSIX Message Queue File System...
10979 11:13:24.094095 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10980 11:13:24.131731 <30>[ 18.763294] systemd[1]: Mounting Kernel Debug File System...
10981 11:13:24.138195 Mounting [0;1;39mKernel Debug File System[0m...
10982 11:13:24.155461 <30>[ 18.783613] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10983 11:13:24.167955 <30>[ 18.796458] systemd[1]: Starting Create list of static device nodes for the current kernel...
10984 11:13:24.174818 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10985 11:13:24.195646 <30>[ 18.827327] systemd[1]: Starting Load Kernel Module configfs...
10986 11:13:24.202311 Starting [0;1;39mLoad Kernel Module configfs[0m...
10987 11:13:24.219746 <30>[ 18.851246] systemd[1]: Starting Load Kernel Module drm...
10988 11:13:24.226538 Starting [0;1;39mLoad Kernel Module drm[0m...
10989 11:13:24.242915 <30>[ 18.871411] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10990 11:13:24.275890 <30>[ 18.907630] systemd[1]: Starting Journal Service...
10991 11:13:24.279405 Starting [0;1;39mJournal Service[0m...
10992 11:13:24.298266 <30>[ 18.929911] systemd[1]: Starting Load Kernel Modules...
10993 11:13:24.304595 Starting [0;1;39mLoad Kernel Modules[0m...
10994 11:13:24.327625 <30>[ 18.955738] systemd[1]: Starting Remount Root and Kernel File Systems...
10995 11:13:24.333822 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10996 11:13:24.351006 <30>[ 18.982716] systemd[1]: Starting Coldplug All udev Devices...
10997 11:13:24.357930 Starting [0;1;39mColdplug All udev Devices[0m...
10998 11:13:24.374838 <30>[ 19.006379] systemd[1]: Started Journal Service.
10999 11:13:24.381778 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11000 11:13:24.398021 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11001 11:13:24.417204 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11002 11:13:24.433431 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11003 11:13:24.453360 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11004 11:13:24.469197 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11005 11:13:24.485514 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11006 11:13:24.501762 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11007 11:13:24.521511 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11008 11:13:24.536155 See 'systemctl status systemd-remount-fs.service' for details.
11009 11:13:24.576836 Mounting [0;1;39mKernel Configuration File System[0m...
11010 11:13:24.597512 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11011 11:13:24.610258 <46>[ 19.238299] systemd-journald[183]: Received client request to flush runtime journal.
11012 11:13:24.621174 Starting [0;1;39mLoad/Save Random Seed[0m...
11013 11:13:24.641123 Starting [0;1;39mApply Kernel Variables[0m...
11014 11:13:24.661503 Starting [0;1;39mCreate System Users[0m...
11015 11:13:24.680305 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11016 11:13:24.696844 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11017 11:13:24.716896 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11018 11:13:24.733503 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11019 11:13:24.749732 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11020 11:13:24.766013 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11021 11:13:24.803949 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11022 11:13:24.831312 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11023 11:13:24.844352 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11024 11:13:24.859673 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11025 11:13:24.921042 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11026 11:13:24.947962 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11027 11:13:24.973903 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11028 11:13:24.992949 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11029 11:13:25.046866 Starting [0;1;39mNetwork Time Synchronization[0m...
11030 11:13:25.070566 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11031 11:13:25.105107 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11032 11:13:25.128948 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11033 11:13:25.135702 <6>[ 19.764932] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11034 11:13:25.149431 [[0;32m OK [<6>[ 19.778018] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11035 11:13:25.159912 0m] Started [0;<3>[ 19.779165] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11036 11:13:25.169399 1;39mNetwork Tim<6>[ 19.787177] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11037 11:13:25.179789 <3>[ 19.796977] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11038 11:13:25.186191 e Synchronizatio<6>[ 19.806037] remoteproc remoteproc0: scp is available
11039 11:13:25.186280 n[0m.
11040 11:13:25.189565 <6>[ 19.806090] remoteproc remoteproc0: powering up scp
11041 11:13:25.199649 <6>[ 19.806095] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11042 11:13:25.202753 <6>[ 19.806115] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11043 11:13:25.212414 <6>[ 19.809209] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11044 11:13:25.222811 <3>[ 19.815043] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11045 11:13:25.232504 [[0;32m OK [0m] Finished [0<4>[ 19.859793] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11046 11:13:25.242324 ;1;39mLoad/Save <3>[ 19.863202] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11047 11:13:25.249060 <3>[ 19.877776] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11048 11:13:25.259083 Screen …s of l<3>[ 19.885931] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11049 11:13:25.265805 <4>[ 19.886624] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11050 11:13:25.275920 <3>[ 19.895327] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11051 11:13:25.282154 eds:white:kbd_ba<3>[ 19.895331] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11052 11:13:25.292365 <3>[ 19.901690] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11053 11:13:25.295377 <6>[ 19.923205] mc: Linux media interface: v0.10
11054 11:13:25.299062 cklight[0m.
11055 11:13:25.305367 <6>[ 19.931824] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11056 11:13:25.312094 <6>[ 19.932824] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11057 11:13:25.322224 <3>[ 19.941488] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11058 11:13:25.328562 <6>[ 19.942542] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11059 11:13:25.335721 <6>[ 19.949756] remoteproc remoteproc0: remote processor scp is now up
11060 11:13:25.341724 <3>[ 19.957749] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11061 11:13:25.348563 <6>[ 19.971846] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11062 11:13:25.358446 <3>[ 19.979848] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11063 11:13:25.368782 <4>[ 19.981173] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11064 11:13:25.371847 <4>[ 19.981173] Fallback method does not support PEC.
11065 11:13:25.374971 <6>[ 19.983587] Bluetooth: Core ver 2.22
11066 11:13:25.381839 <6>[ 19.983644] videodev: Linux video capture interface: v2.00
11067 11:13:25.388628 <6>[ 19.983678] NET: Registered PF_BLUETOOTH protocol family
11068 11:13:25.391965 <6>[ 19.983681] Bluetooth: HCI device and connection manager initialized
11069 11:13:25.399397 <6>[ 19.983701] Bluetooth: HCI socket layer initialized
11070 11:13:25.402510 <6>[ 19.983706] Bluetooth: L2CAP socket layer initialized
11071 11:13:25.408902 <6>[ 19.983714] Bluetooth: SCO socket layer initialized
11072 11:13:25.416007 <3>[ 19.984181] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11073 11:13:25.426046 <3>[ 19.984196] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11074 11:13:25.432273 <3>[ 19.984199] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11075 11:13:25.442414 <3>[ 19.984205] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11076 11:13:25.449456 <3>[ 19.984208] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11077 11:13:25.456281 <3>[ 19.984243] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11078 11:13:25.463534 <6>[ 19.984770] usbcore: registered new device driver r8152-cfgselector
11079 11:13:25.470494 <6>[ 19.986851] pci_bus 0000:00: root bus resource [bus 00-ff]
11080 11:13:25.480281 <6>[ 20.016318] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11081 11:13:25.486891 <6>[ 20.018127] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11082 11:13:25.493812 <3>[ 20.033869] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11083 11:13:25.503906 <6>[ 20.035414] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11084 11:13:25.510041 <6>[ 20.035460] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11085 11:13:25.520198 <6>[ 20.063687] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11086 11:13:25.530287 <6>[ 20.070110] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11087 11:13:25.534130 <6>[ 20.070227] pci 0000:00:00.0: supports D1 D2
11088 11:13:25.541459 <6>[ 20.078740] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11089 11:13:25.551756 <6>[ 20.078825] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11090 11:13:25.558425 <6>[ 20.086384] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11091 11:13:25.565429 <6>[ 20.089002] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11092 11:13:25.575776 <6>[ 20.100092] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11093 11:13:25.578840 <6>[ 20.101235] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11094 11:13:25.589580 <3>[ 20.101393] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11095 11:13:25.596228 <3>[ 20.102174] power_supply sbs-5-000b: driver failed to report `status' property: -6
11096 11:13:25.606326 <3>[ 20.104821] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11097 11:13:25.613063 <6>[ 20.109779] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11098 11:13:25.622995 <6>[ 20.116110] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11099 11:13:25.629213 <4>[ 20.122042] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11100 11:13:25.640063 <4>[ 20.122051] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11101 11:13:25.642912 <6>[ 20.133556] usbcore: registered new interface driver btusb
11102 11:13:25.657173 <4>[ 20.133950] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11103 11:13:25.660376 <3>[ 20.133959] Bluetooth: hci0: Failed to load firmware file (-2)
11104 11:13:25.667176 <3>[ 20.133963] Bluetooth: hci0: Failed to set up firmware (-2)
11105 11:13:25.676979 <4>[ 20.133966] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11106 11:13:25.683387 <6>[ 20.141908] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11107 11:13:25.690904 <6>[ 20.149170] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11108 11:13:25.701003 <6>[ 20.158246] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11109 11:13:25.707626 <6>[ 20.158883] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11110 11:13:25.718378 <6>[ 20.166743] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11111 11:13:25.721466 <6>[ 20.170336] pci 0000:01:00.0: supports D1 D2
11112 11:13:25.731528 <3>[ 20.177411] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11113 11:13:25.738332 <3>[ 20.178151] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
11114 11:13:25.745279 <6>[ 20.178715] usbcore: registered new interface driver uvcvideo
11115 11:13:25.748213 <6>[ 20.179141] r8152 2-1.3:1.0 eth0: v1.12.13
11116 11:13:25.755913 <6>[ 20.179192] usbcore: registered new interface driver r8152
11117 11:13:25.762659 <6>[ 20.187606] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11118 11:13:25.769317 <6>[ 20.199190] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11119 11:13:25.779239 <3>[ 20.200738] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11120 11:13:25.785507 <6>[ 20.211379] usbcore: registered new interface driver cdc_ether
11121 11:13:25.792208 <6>[ 20.217271] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11122 11:13:25.802056 <3>[ 20.220338] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11123 11:13:25.808761 <6>[ 20.243165] usbcore: registered new interface driver r8153_ecm
11124 11:13:25.815512 <6>[ 20.250906] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11125 11:13:25.822204 <6>[ 20.270328] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
11126 11:13:25.828728 <3>[ 20.274684] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11127 11:13:25.838684 <6>[ 20.275492] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11128 11:13:25.845323 <3>[ 20.295142] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11129 11:13:25.854910 <6>[ 20.297821] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11130 11:13:25.861695 <6>[ 20.491388] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11131 11:13:25.868115 <6>[ 20.491401] pci 0000:00:00.0: PCI bridge to [bus 01]
11132 11:13:25.874613 <6>[ 20.491407] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11133 11:13:25.881371 <6>[ 20.491576] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11134 11:13:25.888097 [[0;32m OK [<6>[ 20.519610] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11135 11:13:25.897829 0m] Found device<6>[ 20.526880] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11136 11:13:25.897983 [0;1;39m/dev/ttyS0[0m.
11137 11:13:25.920695 <5>[ 20.549149] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11138 11:13:25.940541 <5>[ 20.568824] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11139 11:13:25.950460 <5>[ 20.577335] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11140 11:13:25.956660 <4>[ 20.585815] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11141 11:13:25.963752 <6>[ 20.594795] cfg80211: failed to load regulatory.db
11142 11:13:25.979407 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11143 11:13:26.012698 <6>[ 20.641001] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11144 11:13:26.019210 <6>[ 20.648510] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11145 11:13:26.043692 <6>[ 20.675212] mt7921e 0000:01:00.0: ASIC revision: 79610010
11146 11:13:26.056549 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11147 11:13:26.071845 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11148 11:13:26.090665 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11149 11:13:26.103697 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11150 11:13:26.119449 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11151 11:13:26.148043 [[0;32m OK [0m] Started [0;<6>[ 20.775335] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
11152 11:13:26.148136 <6>[ 20.775335]
11153 11:13:26.154459 1;39mDiscard unused blocks once a week[0m.
11154 11:13:26.167805 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11155 11:13:26.187818 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11156 11:13:26.199825 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11157 11:13:26.215508 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11158 11:13:26.235184 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11159 11:13:26.272640 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11160 11:13:26.352688 Starting [0;1;39mUser Login Management[0m...
11161 11:13:26.372602 Starting [0;1;39mPermit User Sessions[0m...
11162 11:13:26.392045 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11163 11:13:26.416701 <6>[ 21.045269] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11164 11:13:26.423285 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11165 11:13:26.492829 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11166 11:13:26.499516 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11167 11:13:26.520604 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11168 11:13:26.536508 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11169 11:13:26.551947 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11170 11:13:26.569455 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11171 11:13:26.584351 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11172 11:13:26.620323 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11173 11:13:26.650509 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11174 11:13:26.696149
11175 11:13:26.696260
11176 11:13:26.699108 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11177 11:13:26.699194
11178 11:13:26.702210 debian-bullseye-arm64 login: root (automatic login)
11179 11:13:26.702312
11180 11:13:26.702391
11181 11:13:26.718091 Linux debian-bullseye-arm64 6.1.80-cip16 #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024 aarch64
11182 11:13:26.718179
11183 11:13:26.724687 The programs included with the Debian GNU/Linux system are free software;
11184 11:13:26.731589 the exact distribution terms for each program are described in the
11185 11:13:26.734602 individual files in /usr/share/doc/*/copyright.
11186 11:13:26.734686
11187 11:13:26.741330 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11188 11:13:26.744348 permitted by applicable law.
11189 11:13:26.744721 Matched prompt #10: / #
11191 11:13:26.744922 Setting prompt string to ['/ #']
11192 11:13:26.745032 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11194 11:13:26.745223 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11195 11:13:26.745310 start: 2.2.6 expect-shell-connection (timeout 00:03:00) [common]
11196 11:13:26.745380 Setting prompt string to ['/ #']
11197 11:13:26.745440 Forcing a shell prompt, looking for ['/ #']
11199 11:13:26.795625 / #
11200 11:13:26.795747 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11201 11:13:26.795823 Waiting using forced prompt support (timeout 00:02:30)
11202 11:13:26.800572
11203 11:13:26.800848 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11204 11:13:26.800947 start: 2.2.7 export-device-env (timeout 00:03:00) [common]
11205 11:13:26.801044 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11206 11:13:26.801135 end: 2.2 depthcharge-retry (duration 00:02:00) [common]
11207 11:13:26.801226 end: 2 depthcharge-action (duration 00:02:00) [common]
11208 11:13:26.801313 start: 3 lava-test-retry (timeout 00:05:00) [common]
11209 11:13:26.801399 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11210 11:13:26.801472 Using namespace: common
11212 11:13:26.901755 / # #
11213 11:13:26.901940 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11214 11:13:26.907564 #
11215 11:13:26.907835 Using /lava-12925665
11217 11:13:27.008154 / # export SHELL=/bin/sh
11218 11:13:27.013666 export SHELL=/bin/sh
11220 11:13:27.114294 / # . /lava-12925665/environment
11221 11:13:27.119283 . /lava-12925665/environment
11223 11:13:27.219865 / # /lava-12925665/bin/lava-test-runner /lava-12925665/0
11224 11:13:27.220047 Test shell timeout: 10s (minimum of the action and connection timeout)
11225 11:13:27.224965 /lava-12925665/bin/lava-test-runner /lava-12925665/0
11226 11:13:27.245398 + export TESTRUN_ID=0_sleep
11227 11:13:27.249183 + cd /lava-12925665/0/tests/0_sleep
11228 11:13:27.252163 + cat uuid
11229 11:13:27.252260 + UUID=12925665_1.5.2.3.1
11230 11:13:27.255848 + set +x
11231 11:13:27.258843 <LAVA_SIGNAL_STARTRUN 0_sleep 12925665_1.5.2.3.1>
11232 11:13:27.259129 Received signal: <STARTRUN> 0_sleep 12925665_1.5.2.3.1
11233 11:13:27.259227 Starting test lava.0_sleep (12925665_1.5.2.3.1)
11234 11:13:27.259342 Skipping test definition patterns.
11235 11:13:27.265205 + ./config/lava/sleep/slee<6>[ 21.896907] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11236 11:13:27.268919 p.sh mem
11237 11:13:27.272070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11238 11:13:27.272338 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11240 11:13:27.278272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11241 11:13:27.278524 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11243 11:13:27.281915 rtcwake: assuming RTC uses UTC ...
11244 11:13:27.288362 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 11:10:44 2024
11245 11:13:27.297498 <6>[ 21.929344] PM: suspend entry (deep)
11246 11:13:27.300579 <6>[ 21.933364] Filesystems sync: 0.000 seconds
11247 11:13:27.308068 <6>[ 21.939677] Freezing user space processes
11248 11:13:27.314152 <6>[ 21.945570] Freezing user space processes completed (elapsed 0.001 seconds)
11249 11:13:27.320803 <6>[ 21.952814] OOM killer disabled.
11250 11:13:27.324128 <6>[ 21.956305] Freezing remaining freezable tasks
11251 11:13:27.334155 <6>[ 21.962288] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11252 11:13:27.340933 <6>[ 21.969946] printk: Suspending console(s) (use no_console_suspend to debug)
11253 11:13:33.227594 <6>[ 22.114877] Disabling non-boot CPUs ...
11254 11:13:33.230730 <4>[ 22.115850] IRQ283: set affinity failed(-22).
11255 11:13:33.233857 <4>[ 22.115866] IRQ284: set affinity failed(-22).
11256 11:13:33.240706 <6>[ 22.115944] psci: CPU1 killed (polled 0 ms)
11257 11:13:33.244243 <4>[ 22.117435] IRQ283: set affinity failed(-22).
11258 11:13:33.250563 <4>[ 22.117447] IRQ284: set affinity failed(-22).
11259 11:13:33.254041 <6>[ 22.117513] psci: CPU2 killed (polled 0 ms)
11260 11:13:33.257444 <4>[ 22.118684] IRQ283: set affinity failed(-22).
11261 11:13:33.264321 <4>[ 22.118696] IRQ284: set affinity failed(-22).
11262 11:13:33.267421 <6>[ 22.119768] psci: CPU3 killed (polled 4 ms)
11263 11:13:33.270802 <4>[ 22.120627] IRQ283: set affinity failed(-22).
11264 11:13:33.277359 <4>[ 22.120632] IRQ284: set affinity failed(-22).
11265 11:13:33.280892 <6>[ 22.120668] psci: CPU4 killed (polled 0 ms)
11266 11:13:33.284547 <4>[ 22.121580] IRQ283: set affinity failed(-22).
11267 11:13:33.291121 <4>[ 22.121587] IRQ284: set affinity failed(-22).
11268 11:13:33.294247 <6>[ 22.121625] psci: CPU5 killed (polled 0 ms)
11269 11:13:33.300964 <6>[ 22.122511] psci: CPU6 killed (polled 0 ms)
11270 11:13:33.304080 <6>[ 22.123758] psci: CPU7 killed (polled 0 ms)
11271 11:13:33.307568 <6>[ 22.124420] Enabling non-boot CPUs ...
11272 11:13:33.310461 <6>[ 22.124656] Detected VIPT I-cache on CPU1
11273 11:13:33.320972 <6>[ 22.124745] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11274 11:13:33.327698 <6>[ 22.124809] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11275 11:13:33.327783 <6>[ 22.125401] CPU1 is up
11276 11:13:33.333984 <6>[ 22.125549] Detected VIPT I-cache on CPU2
11277 11:13:33.340743 <6>[ 22.125609] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11278 11:13:33.347545 <6>[ 22.125648] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11279 11:13:33.350710 <6>[ 22.126125] CPU2 is up
11280 11:13:33.353717 <6>[ 22.126266] Detected VIPT I-cache on CPU3
11281 11:13:33.360827 <6>[ 22.126325] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11282 11:13:33.367551 <6>[ 22.126364] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11283 11:13:33.370745 <6>[ 22.126887] CPU3 is up
11284 11:13:33.377286 <6>[ 22.127056] CPU features: detected: Hardware dirty bit management
11285 11:13:33.380589 <6>[ 22.127076] Detected PIPT I-cache on CPU4
11286 11:13:33.387399 <6>[ 22.127102] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11287 11:13:33.393877 <6>[ 22.127121] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11288 11:13:33.397423 <6>[ 22.127431] CPU4 is up
11289 11:13:33.400587 <6>[ 22.127565] Detected PIPT I-cache on CPU5
11290 11:13:33.410479 <6>[ 22.127596] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11291 11:13:33.417443 <6>[ 22.127615] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11292 11:13:33.417554 <6>[ 22.127909] CPU5 is up
11293 11:13:33.423864 <6>[ 22.128041] Detected PIPT I-cache on CPU6
11294 11:13:33.430659 <6>[ 22.128071] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11295 11:13:33.437318 <6>[ 22.128090] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11296 11:13:33.440732 <6>[ 22.128388] CPU6 is up
11297 11:13:33.443842 <6>[ 22.128527] Detected PIPT I-cache on CPU7
11298 11:13:33.450691 <6>[ 22.128558] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11299 11:13:33.457488 <6>[ 22.128577] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11300 11:13:33.460516 <6>[ 22.128884] CPU7 is up
11301 11:13:33.467492 <4>[ 22.263974] typec port0-partner: PM: parent port0 should not be sleeping
11302 11:13:33.470523 <6>[ 22.726565] OOM killer enabled.
11303 11:13:33.474160 <6>[ 22.729956] Restarting tasks ... done.
11304 11:13:33.480415 <5>[ 22.734362] random: crng reseeded on system resumption
11305 11:13:33.484245 <6>[ 22.740887] PM: suspend exit
11306 11:13:33.495476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=pass>
11307 11:13:33.495796 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=pass
11309 11:13:33.498859 rtcwake: assuming RTC uses UTC ...
11310 11:13:33.505617 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 11:10:50 2024
11311 11:13:33.518051 <6>[ 22.772383] PM: suspend entry (deep)
11312 11:13:33.521530 <6>[ 22.776253] Filesystems sync: 0.000 seconds
11313 11:13:33.524615 <6>[ 22.781027] Freezing user space processes
11314 11:13:33.536299 <6>[ 22.786752] Freezing user space processes completed (elapsed 0.001 seconds)
11315 11:13:33.539533 <6>[ 22.793979] OOM killer disabled.
11316 11:13:33.543101 <6>[ 22.797464] Freezing remaining freezable tasks
11317 11:13:33.553016 <6>[ 22.802924] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11318 11:13:33.559373 <6>[ 22.810571] printk: Suspending console(s) (use no_console_suspend to debug)
11319 11:13:39.228485 <6>[ 22.882821] Disabling non-boot CPUs ...
11320 11:13:39.231511 <6>[ 22.883370] psci: CPU1 killed (polled 0 ms)
11321 11:13:39.235419 <6>[ 22.883992] psci: CPU2 killed (polled 0 ms)
11322 11:13:39.241444 <6>[ 22.885540] psci: CPU3 killed (polled 0 ms)
11323 11:13:39.245132 <6>[ 22.885946] psci: CPU4 killed (polled 0 ms)
11324 11:13:39.248257 <6>[ 22.886908] psci: CPU5 killed (polled 4 ms)
11325 11:13:39.254997 <6>[ 22.888337] psci: CPU6 killed (polled 0 ms)
11326 11:13:39.258158 <6>[ 22.889759] psci: CPU7 killed (polled 0 ms)
11327 11:13:39.261720 <6>[ 22.889949] Enabling non-boot CPUs ...
11328 11:13:39.265223 <6>[ 22.890120] Detected VIPT I-cache on CPU1
11329 11:13:39.275065 <6>[ 22.890177] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11330 11:13:39.282097 <6>[ 22.890219] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11331 11:13:39.282220 <6>[ 22.890595] CPU1 is up
11332 11:13:39.288912 <6>[ 22.890679] Detected VIPT I-cache on CPU2
11333 11:13:39.295144 <6>[ 22.890706] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11334 11:13:39.302051 <6>[ 22.890726] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11335 11:13:39.305104 <6>[ 22.890988] CPU2 is up
11336 11:13:39.308088 <6>[ 22.891070] Detected VIPT I-cache on CPU3
11337 11:13:39.315085 <6>[ 22.891098] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11338 11:13:39.322093 <6>[ 22.891116] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11339 11:13:39.324888 <6>[ 22.891383] CPU3 is up
11340 11:13:39.328512 <6>[ 22.891476] Detected PIPT I-cache on CPU4
11341 11:13:39.338527 <6>[ 22.891498] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11342 11:13:39.345016 <6>[ 22.891511] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11343 11:13:39.345098 <6>[ 22.891740] CPU4 is up
11344 11:13:39.351833 <6>[ 22.891830] Detected PIPT I-cache on CPU5
11345 11:13:39.358782 <6>[ 22.891851] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11346 11:13:39.365563 <6>[ 22.891864] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11347 11:13:39.368513 <6>[ 22.892072] CPU5 is up
11348 11:13:39.371920 <6>[ 22.892167] Detected PIPT I-cache on CPU6
11349 11:13:39.378503 <6>[ 22.892188] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11350 11:13:39.385294 <6>[ 22.892202] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11351 11:13:39.388408 <6>[ 22.892410] CPU6 is up
11352 11:13:39.392134 <6>[ 22.892499] Detected PIPT I-cache on CPU7
11353 11:13:39.398301 <6>[ 22.892520] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11354 11:13:39.405359 <6>[ 22.892534] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11355 11:13:39.408496 <6>[ 22.892763] CPU7 is up
11356 11:13:39.412105 <6>[ 23.434559] OOM killer enabled.
11357 11:13:39.418683 <6>[ 23.437951] Restarting tasks ... done.
11358 11:13:39.421813 <5>[ 23.442305] random: crng reseeded on system resumption
11359 11:13:39.425073 <6>[ 23.448855] PM: suspend exit
11360 11:13:39.437145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=pass>
11361 11:13:39.437447 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=pass
11363 11:13:39.440085 rtcwake: assuming RTC uses UTC ...
11364 11:13:39.446827 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 11:10:56 2024
11365 11:13:39.459991 <6>[ 23.480204] PM: suspend entry (deep)
11366 11:13:39.463201 <6>[ 23.484070] Filesystems sync: 0.000 seconds
11367 11:13:39.466274 <6>[ 23.488844] Freezing user space processes
11368 11:13:39.477281 <6>[ 23.494538] Freezing user space processes completed (elapsed 0.001 seconds)
11369 11:13:39.480566 <6>[ 23.501763] OOM killer disabled.
11370 11:13:39.483880 <6>[ 23.505245] Freezing remaining freezable tasks
11371 11:13:39.494307 <6>[ 23.510888] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11372 11:13:39.501055 <6>[ 23.518540] printk: Suspending console(s) (use no_console_suspend to debug)
11373 11:13:45.234767 <6>[ 23.599523] Disabling non-boot CPUs ...
11374 11:13:45.238591 <6>[ 23.600503] psci: CPU1 killed (polled 0 ms)
11375 11:13:45.241609 <6>[ 23.602664] psci: CPU2 killed (polled 0 ms)
11376 11:13:45.248008 <6>[ 23.604621] psci: CPU3 killed (polled 0 ms)
11377 11:13:45.251875 <6>[ 23.605124] psci: CPU4 killed (polled 0 ms)
11378 11:13:45.254871 <6>[ 23.605764] psci: CPU5 killed (polled 0 ms)
11379 11:13:45.261881 <6>[ 23.606295] psci: CPU6 killed (polled 0 ms)
11380 11:13:45.264671 <6>[ 23.606885] psci: CPU7 killed (polled 0 ms)
11381 11:13:45.268492 <6>[ 23.607165] Enabling non-boot CPUs ...
11382 11:13:45.275057 <6>[ 23.607393] Detected VIPT I-cache on CPU1
11383 11:13:45.281356 <6>[ 23.607479] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11384 11:13:45.288246 <6>[ 23.607539] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11385 11:13:45.291270 <6>[ 23.608157] CPU1 is up
11386 11:13:45.294942 <6>[ 23.608297] Detected VIPT I-cache on CPU2
11387 11:13:45.301647 <6>[ 23.608353] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11388 11:13:45.308450 <6>[ 23.608391] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11389 11:13:45.311210 <6>[ 23.608902] CPU2 is up
11390 11:13:45.314816 <6>[ 23.609038] Detected VIPT I-cache on CPU3
11391 11:13:45.321515 <6>[ 23.609094] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11392 11:13:45.328042 <6>[ 23.609131] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11393 11:13:45.331748 <6>[ 23.609668] CPU3 is up
11394 11:13:45.338533 <6>[ 23.609792] Detected PIPT I-cache on CPU4
11395 11:13:45.344877 <6>[ 23.609814] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11396 11:13:45.351207 <6>[ 23.609830] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11397 11:13:45.354882 <6>[ 23.610096] CPU4 is up
11398 11:13:45.358506 <6>[ 23.610217] Detected PIPT I-cache on CPU5
11399 11:13:45.364633 <6>[ 23.610240] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11400 11:13:45.371690 <6>[ 23.610255] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11401 11:13:45.375141 <6>[ 23.610483] CPU5 is up
11402 11:13:45.378111 <6>[ 23.610603] Detected PIPT I-cache on CPU6
11403 11:13:45.384724 <6>[ 23.610626] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11404 11:13:45.391528 <6>[ 23.610641] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11405 11:13:45.394877 <6>[ 23.610969] CPU6 is up
11406 11:13:45.397769 <6>[ 23.611095] Detected PIPT I-cache on CPU7
11407 11:13:45.407930 <6>[ 23.611118] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11408 11:13:45.414827 <6>[ 23.611133] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11409 11:13:45.415000 <6>[ 23.611397] CPU7 is up
11410 11:13:45.421225 <6>[ 24.159604] OOM killer enabled.
11411 11:13:45.424673 <6>[ 24.162995] Restarting tasks ... done.
11412 11:13:45.428006 <5>[ 24.167361] random: crng reseeded on system resumption
11413 11:13:45.432198 <6>[ 24.173801] PM: suspend exit
11414 11:13:45.443832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=pass>
11415 11:13:45.444220 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=pass
11417 11:13:45.446953 rtcwake: assuming RTC uses UTC ...
11418 11:13:45.453867 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 11:11:02 2024
11419 11:13:45.465954 <6>[ 24.204610] PM: suspend entry (deep)
11420 11:13:45.469621 <6>[ 24.208476] Filesystems sync: 0.000 seconds
11421 11:13:45.472746 <6>[ 24.213222] Freezing user space processes
11422 11:13:45.483608 <6>[ 24.218800] Freezing user space processes completed (elapsed 0.001 seconds)
11423 11:13:45.487187 <6>[ 24.226028] OOM killer disabled.
11424 11:13:45.490644 <6>[ 24.229507] Freezing remaining freezable tasks
11425 11:13:45.500766 <6>[ 24.235364] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11426 11:13:45.506947 <6>[ 24.243014] printk: Suspending console(s) (use no_console_suspend to debug)
11427 11:13:51.238931 <6>[ 24.335234] Disabling non-boot CPUs ...
11428 11:13:51.242675 <6>[ 24.336152] psci: CPU1 killed (polled 0 ms)
11429 11:13:51.245684 <6>[ 24.338315] psci: CPU2 killed (polled 0 ms)
11430 11:13:51.252547 <6>[ 24.339455] psci: CPU3 killed (polled 0 ms)
11431 11:13:51.255846 <6>[ 24.339813] psci: CPU4 killed (polled 0 ms)
11432 11:13:51.259013 <6>[ 24.340494] psci: CPU5 killed (polled 0 ms)
11433 11:13:51.265777 <6>[ 24.341126] psci: CPU6 killed (polled 0 ms)
11434 11:13:51.269317 <6>[ 24.341630] psci: CPU7 killed (polled 0 ms)
11435 11:13:51.272462 <6>[ 24.341963] Enabling non-boot CPUs ...
11436 11:13:51.279096 <6>[ 24.342198] Detected VIPT I-cache on CPU1
11437 11:13:51.285730 <6>[ 24.342283] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11438 11:13:51.292538 <6>[ 24.342344] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11439 11:13:51.295654 <6>[ 24.342999] CPU1 is up
11440 11:13:51.299397 <6>[ 24.343140] Detected VIPT I-cache on CPU2
11441 11:13:51.305790 <6>[ 24.343196] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11442 11:13:51.312467 <6>[ 24.343233] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11443 11:13:51.315976 <6>[ 24.343737] CPU2 is up
11444 11:13:51.319320 <6>[ 24.343872] Detected VIPT I-cache on CPU3
11445 11:13:51.325823 <6>[ 24.343927] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11446 11:13:51.332820 <6>[ 24.343964] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11447 11:13:51.336184 <6>[ 24.344506] CPU3 is up
11448 11:13:51.339067 <6>[ 24.344630] Detected PIPT I-cache on CPU4
11449 11:13:51.349181 <6>[ 24.344653] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11450 11:13:51.355828 <6>[ 24.344667] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11451 11:13:51.355961 <6>[ 24.344929] CPU4 is up
11452 11:13:51.362496 <6>[ 24.345061] Detected PIPT I-cache on CPU5
11453 11:13:51.369197 <6>[ 24.345083] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11454 11:13:51.375857 <6>[ 24.345098] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11455 11:13:51.378934 <6>[ 24.345319] CPU5 is up
11456 11:13:51.382631 <6>[ 24.345439] Detected PIPT I-cache on CPU6
11457 11:13:51.389037 <6>[ 24.345461] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11458 11:13:51.395812 <6>[ 24.345475] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11459 11:13:51.399544 <6>[ 24.345714] CPU6 is up
11460 11:13:51.402591 <6>[ 24.345835] Detected PIPT I-cache on CPU7
11461 11:13:51.409592 <6>[ 24.345858] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11462 11:13:51.416115 <6>[ 24.345871] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11463 11:13:51.419123 <6>[ 24.346118] CPU7 is up
11464 11:13:51.422831 <6>[ 24.899117] OOM killer enabled.
11465 11:13:51.429509 <6>[ 24.902507] Restarting tasks ... done.
11466 11:13:51.432612 <5>[ 24.906893] random: crng reseeded on system resumption
11467 11:13:51.435544 <6>[ 24.913166] PM: suspend exit
11468 11:13:51.445915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=pass>
11469 11:13:51.446253 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=pass
11471 11:13:51.449551 rtcwake: assuming RTC uses UTC ...
11472 11:13:51.456362 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 11:11:08 2024
11473 11:13:51.468424 <6>[ 24.942365] PM: suspend entry (deep)
11474 11:13:51.471882 <6>[ 24.946229] Filesystems sync: 0.000 seconds
11475 11:13:51.474674 <6>[ 24.950986] Freezing user space processes
11476 11:13:51.485771 <6>[ 24.956644] Freezing user space processes completed (elapsed 0.001 seconds)
11477 11:13:51.489092 <6>[ 24.963865] OOM killer disabled.
11478 11:13:51.492516 <6>[ 24.967343] Freezing remaining freezable tasks
11479 11:13:51.502683 <6>[ 24.973246] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11480 11:13:51.509221 <6>[ 24.980912] printk: Suspending console(s) (use no_console_suspend to debug)
11481 11:13:57.219502 <6>[ 25.054416] Disabling non-boot CPUs ...
11482 11:13:57.222519 <6>[ 25.055400] psci: CPU1 killed (polled 0 ms)
11483 11:13:57.226063 <6>[ 25.057609] psci: CPU2 killed (polled 0 ms)
11484 11:13:57.232598 <6>[ 25.058467] psci: CPU3 killed (polled 0 ms)
11485 11:13:57.235865 <6>[ 25.058822] psci: CPU4 killed (polled 0 ms)
11486 11:13:57.239359 <6>[ 25.059401] psci: CPU5 killed (polled 0 ms)
11487 11:13:57.245718 <6>[ 25.059960] psci: CPU6 killed (polled 0 ms)
11488 11:13:57.249174 <6>[ 25.060472] psci: CPU7 killed (polled 0 ms)
11489 11:13:57.252755 <6>[ 25.060771] Enabling non-boot CPUs ...
11490 11:13:57.259662 <6>[ 25.060999] Detected VIPT I-cache on CPU1
11491 11:13:57.266313 <6>[ 25.061084] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11492 11:13:57.272676 <6>[ 25.061143] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11493 11:13:57.275831 <6>[ 25.061769] CPU1 is up
11494 11:13:57.279495 <6>[ 25.061907] Detected VIPT I-cache on CPU2
11495 11:13:57.286215 <6>[ 25.061962] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11496 11:13:57.292244 <6>[ 25.061999] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11497 11:13:57.295867 <6>[ 25.062500] CPU2 is up
11498 11:13:57.299761 <6>[ 25.062635] Detected VIPT I-cache on CPU3
11499 11:13:57.305877 <6>[ 25.062691] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11500 11:13:57.312555 <6>[ 25.062727] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11501 11:13:57.316069 <6>[ 25.063279] CPU3 is up
11502 11:13:57.322896 <6>[ 25.063402] Detected PIPT I-cache on CPU4
11503 11:13:57.329152 <6>[ 25.063422] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11504 11:13:57.335933 <6>[ 25.063435] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11505 11:13:57.339260 <6>[ 25.063679] CPU4 is up
11506 11:13:57.342468 <6>[ 25.063802] Detected PIPT I-cache on CPU5
11507 11:13:57.349426 <6>[ 25.063823] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11508 11:13:57.356098 <6>[ 25.063836] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11509 11:13:57.359341 <6>[ 25.064055] CPU5 is up
11510 11:13:57.362397 <6>[ 25.064172] Detected PIPT I-cache on CPU6
11511 11:13:57.369404 <6>[ 25.064192] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11512 11:13:57.375872 <6>[ 25.064205] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11513 11:13:57.379587 <6>[ 25.064423] CPU6 is up
11514 11:13:57.382781 <6>[ 25.064549] Detected PIPT I-cache on CPU7
11515 11:13:57.392565 <6>[ 25.064569] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11516 11:13:57.399226 <6>[ 25.064582] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11517 11:13:57.399307 <6>[ 25.064819] CPU7 is up
11518 11:13:57.402627 <6>[ 25.599170] OOM killer enabled.
11519 11:13:57.409537 <6>[ 25.602561] Restarting tasks ... done.
11520 11:13:57.413058 <5>[ 25.606935] random: crng reseeded on system resumption
11521 11:13:57.416542 <6>[ 25.613412] PM: suspend exit
11522 11:13:57.427080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=pass>
11523 11:13:57.427347 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=pass
11525 11:13:57.430746 rtcwake: assuming RTC uses UTC ...
11526 11:13:57.437038 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 11:11:14 2024
11527 11:13:57.449791 <6>[ 25.643518] PM: suspend entry (deep)
11528 11:13:57.453438 <6>[ 25.647406] Filesystems sync: 0.000 seconds
11529 11:13:57.456628 <6>[ 25.652477] Freezing user space processes
11530 11:13:57.467912 <6>[ 25.658413] Freezing user space processes completed (elapsed 0.001 seconds)
11531 11:13:57.471500 <6>[ 25.665645] OOM killer disabled.
11532 11:13:57.474826 <6>[ 25.669134] Freezing remaining freezable tasks
11533 11:13:57.484777 <6>[ 25.674838] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11534 11:13:57.491637 <6>[ 25.682499] printk: Suspending console(s) (use no_console_suspend to debug)
11535 11:14:03.221014 <6>[ 25.771375] Disabling non-boot CPUs ...
11536 11:14:03.224184 <6>[ 25.773035] psci: CPU1 killed (polled 0 ms)
11537 11:14:03.227424 <6>[ 25.774738] psci: CPU2 killed (polled 4 ms)
11538 11:14:03.234273 <6>[ 25.776410] psci: CPU3 killed (polled 0 ms)
11539 11:14:03.237347 <6>[ 25.777961] psci: CPU4 killed (polled 0 ms)
11540 11:14:03.240587 <6>[ 25.778751] psci: CPU5 killed (polled 4 ms)
11541 11:14:03.247473 <6>[ 25.780330] psci: CPU6 killed (polled 0 ms)
11542 11:14:03.251064 <6>[ 25.781856] psci: CPU7 killed (polled 0 ms)
11543 11:14:03.254177 <6>[ 25.782078] Enabling non-boot CPUs ...
11544 11:14:03.260812 <6>[ 25.782255] Detected VIPT I-cache on CPU1
11545 11:14:03.267374 <6>[ 25.782317] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11546 11:14:03.273914 <6>[ 25.782362] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11547 11:14:03.277653 <6>[ 25.782786] CPU1 is up
11548 11:14:03.280784 <6>[ 25.782876] Detected VIPT I-cache on CPU2
11549 11:14:03.287640 <6>[ 25.782907] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11550 11:14:03.294166 <6>[ 25.782928] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11551 11:14:03.297219 <6>[ 25.783204] CPU2 is up
11552 11:14:03.300907 <6>[ 25.783295] Detected VIPT I-cache on CPU3
11553 11:14:03.307509 <6>[ 25.783326] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11554 11:14:03.314292 <6>[ 25.783347] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11555 11:14:03.317379 <6>[ 25.783639] CPU3 is up
11556 11:14:03.320493 <6>[ 25.783758] Detected PIPT I-cache on CPU4
11557 11:14:03.330896 <6>[ 25.783793] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11558 11:14:03.337242 <6>[ 25.783815] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11559 11:14:03.337325 <6>[ 25.784155] CPU4 is up
11560 11:14:03.343924 <6>[ 25.784272] Detected PIPT I-cache on CPU5
11561 11:14:03.350703 <6>[ 25.784309] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11562 11:14:03.357307 <6>[ 25.784332] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11563 11:14:03.361069 <6>[ 25.784661] CPU5 is up
11564 11:14:03.364033 <6>[ 25.784776] Detected PIPT I-cache on CPU6
11565 11:14:03.371085 <6>[ 25.784813] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11566 11:14:03.377359 <6>[ 25.784835] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11567 11:14:03.380895 <6>[ 25.785174] CPU6 is up
11568 11:14:03.384155 <6>[ 25.785289] Detected PIPT I-cache on CPU7
11569 11:14:03.390996 <6>[ 25.785326] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11570 11:14:03.397584 <6>[ 25.785349] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11571 11:14:03.400742 <6>[ 25.785700] CPU7 is up
11572 11:14:03.404332 <6>[ 26.322660] OOM killer enabled.
11573 11:14:03.410710 <6>[ 26.326051] Restarting tasks ... done.
11574 11:14:03.414503 <5>[ 26.330433] random: crng reseeded on system resumption
11575 11:14:03.418043 <6>[ 26.336968] PM: suspend exit
11576 11:14:03.429256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=pass>
11577 11:14:03.429546 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=pass
11579 11:14:03.432417 rtcwake: assuming RTC uses UTC ...
11580 11:14:03.439169 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 11:11:20 2024
11581 11:14:03.451786 <6>[ 26.367656] PM: suspend entry (deep)
11582 11:14:03.455259 <6>[ 26.371545] Filesystems sync: 0.000 seconds
11583 11:14:03.458839 <6>[ 26.376306] Freezing user space processes
11584 11:14:03.469616 <6>[ 26.382049] Freezing user space processes completed (elapsed 0.001 seconds)
11585 11:14:03.472907 <6>[ 26.389281] OOM killer disabled.
11586 11:14:03.476102 <6>[ 26.392764] Freezing remaining freezable tasks
11587 11:14:03.486187 <6>[ 26.398675] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11588 11:14:03.493048 <6>[ 26.406349] printk: Suspending console(s) (use no_console_suspend to debug)
11589 11:14:09.237328 <6>[ 26.486494] Disabling non-boot CPUs ...
11590 11:14:09.240278 <6>[ 26.487456] psci: CPU1 killed (polled 0 ms)
11591 11:14:09.244056 <6>[ 26.489468] psci: CPU2 killed (polled 0 ms)
11592 11:14:09.250513 <6>[ 26.490723] psci: CPU3 killed (polled 4 ms)
11593 11:14:09.253583 <6>[ 26.491282] psci: CPU4 killed (polled 0 ms)
11594 11:14:09.257315 <6>[ 26.491892] psci: CPU5 killed (polled 0 ms)
11595 11:14:09.263584 <6>[ 26.492483] psci: CPU6 killed (polled 0 ms)
11596 11:14:09.267089 <6>[ 26.493121] psci: CPU7 killed (polled 0 ms)
11597 11:14:09.270586 <6>[ 26.493453] Enabling non-boot CPUs ...
11598 11:14:09.277467 <6>[ 26.493681] Detected VIPT I-cache on CPU1
11599 11:14:09.283678 <6>[ 26.493768] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11600 11:14:09.290796 <6>[ 26.493829] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11601 11:14:09.293837 <6>[ 26.494456] CPU1 is up
11602 11:14:09.297072 <6>[ 26.494593] Detected VIPT I-cache on CPU2
11603 11:14:09.304029 <6>[ 26.494649] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11604 11:14:09.310328 <6>[ 26.494686] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11605 11:14:09.314010 <6>[ 26.495195] CPU2 is up
11606 11:14:09.317369 <6>[ 26.495340] Detected VIPT I-cache on CPU3
11607 11:14:09.323673 <6>[ 26.495397] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11608 11:14:09.330400 <6>[ 26.495434] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11609 11:14:09.333911 <6>[ 26.495978] CPU3 is up
11610 11:14:09.336924 <6>[ 26.496103] Detected PIPT I-cache on CPU4
11611 11:14:09.347375 <6>[ 26.496124] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11612 11:14:09.354210 <6>[ 26.496138] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11613 11:14:09.354336 <6>[ 26.496388] CPU4 is up
11614 11:14:09.360625 <6>[ 26.496508] Detected PIPT I-cache on CPU5
11615 11:14:09.367491 <6>[ 26.496530] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11616 11:14:09.374190 <6>[ 26.496544] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11617 11:14:09.377068 <6>[ 26.496774] CPU5 is up
11618 11:14:09.380664 <6>[ 26.496892] Detected PIPT I-cache on CPU6
11619 11:14:09.386976 <6>[ 26.496913] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11620 11:14:09.393450 <6>[ 26.496927] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11621 11:14:09.396831 <6>[ 26.497161] CPU6 is up
11622 11:14:09.400239 <6>[ 26.497279] Detected PIPT I-cache on CPU7
11623 11:14:09.407142 <6>[ 26.497301] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11624 11:14:09.417023 <6>[ 26.497314] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11625 11:14:09.417147 <6>[ 26.497562] CPU7 is up
11626 11:14:09.420615 <6>[ 27.051019] OOM killer enabled.
11627 11:14:09.427212 <6>[ 27.054409] Restarting tasks ... done.
11628 11:14:09.430415 <5>[ 27.058779] random: crng reseeded on system resumption
11629 11:14:09.433918 <6>[ 27.065260] PM: suspend exit
11630 11:14:09.444838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=pass>
11631 11:14:09.445158 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=pass
11633 11:14:09.447743 rtcwake: assuming RTC uses UTC ...
11634 11:14:09.454436 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 11:11:26 2024
11635 11:14:09.466952 <6>[ 27.095167] PM: suspend entry (deep)
11636 11:14:09.470396 <6>[ 27.099030] Filesystems sync: 0.000 seconds
11637 11:14:09.473578 <6>[ 27.103788] Freezing user space processes
11638 11:14:09.484768 <6>[ 27.109452] Freezing user space processes completed (elapsed 0.001 seconds)
11639 11:14:09.488358 <6>[ 27.116681] OOM killer disabled.
11640 11:14:09.491342 <6>[ 27.120163] Freezing remaining freezable tasks
11641 11:14:09.501490 <6>[ 27.126085] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11642 11:14:09.508144 <6>[ 27.133755] printk: Suspending console(s) (use no_console_suspend to debug)
11643 11:14:15.238142 <6>[ 27.206858] Disabling non-boot CPUs ...
11644 11:14:15.241795 <4>[ 27.207818] migrate_one_irq: 88 callbacks suppressed
11645 11:14:15.248304 <4>[ 27.207831] IRQ283: set affinity failed(-22).
11646 11:14:15.251386 <4>[ 27.207840] IRQ284: set affinity failed(-22).
11647 11:14:15.255213 <6>[ 27.208920] psci: CPU1 killed (polled 0 ms)
11648 11:14:15.261459 <4>[ 27.209917] IRQ283: set affinity failed(-22).
11649 11:14:15.265221 <4>[ 27.209928] IRQ284: set affinity failed(-22).
11650 11:14:15.268414 <6>[ 27.210672] psci: CPU2 killed (polled 4 ms)
11651 11:14:15.274832 <4>[ 27.211621] IRQ283: set affinity failed(-22).
11652 11:14:15.278403 <4>[ 27.211632] IRQ284: set affinity failed(-22).
11653 11:14:15.284744 <6>[ 27.212695] psci: CPU3 killed (polled 0 ms)
11654 11:14:15.288507 <4>[ 27.213219] IRQ283: set affinity failed(-22).
11655 11:14:15.291657 <4>[ 27.213223] IRQ284: set affinity failed(-22).
11656 11:14:15.298559 <6>[ 27.213254] psci: CPU4 killed (polled 0 ms)
11657 11:14:15.301725 <4>[ 27.213830] IRQ283: set affinity failed(-22).
11658 11:14:15.304749 <4>[ 27.213836] IRQ284: set affinity failed(-22).
11659 11:14:15.311818 <6>[ 27.213870] psci: CPU5 killed (polled 0 ms)
11660 11:14:15.314957 <6>[ 27.214480] psci: CPU6 killed (polled 0 ms)
11661 11:14:15.318441 <6>[ 27.215071] psci: CPU7 killed (polled 0 ms)
11662 11:14:15.324904 <6>[ 27.215405] Enabling non-boot CPUs ...
11663 11:14:15.328104 <6>[ 27.215634] Detected VIPT I-cache on CPU1
11664 11:14:15.335060 <6>[ 27.215721] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11665 11:14:15.341505 <6>[ 27.215782] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11666 11:14:15.344715 <6>[ 27.216408] CPU1 is up
11667 11:14:15.348363 <6>[ 27.216546] Detected VIPT I-cache on CPU2
11668 11:14:15.354762 <6>[ 27.216603] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11669 11:14:15.361565 <6>[ 27.216640] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11670 11:14:15.364679 <6>[ 27.217143] CPU2 is up
11671 11:14:15.368377 <6>[ 27.217279] Detected VIPT I-cache on CPU3
11672 11:14:15.378308 <6>[ 27.217335] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11673 11:14:15.385288 <6>[ 27.217373] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11674 11:14:15.385406 <6>[ 27.217899] CPU3 is up
11675 11:14:15.391713 <6>[ 27.218023] Detected PIPT I-cache on CPU4
11676 11:14:15.398011 <6>[ 27.218046] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11677 11:14:15.405039 <6>[ 27.218061] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11678 11:14:15.408160 <6>[ 27.218358] CPU4 is up
11679 11:14:15.411268 <6>[ 27.218492] Detected PIPT I-cache on CPU5
11680 11:14:15.418191 <6>[ 27.218515] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11681 11:14:15.424768 <6>[ 27.218530] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11682 11:14:15.428092 <6>[ 27.218790] CPU5 is up
11683 11:14:15.431201 <6>[ 27.218913] Detected PIPT I-cache on CPU6
11684 11:14:15.441291 <6>[ 27.218937] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11685 11:14:15.448378 <6>[ 27.218952] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11686 11:14:15.448472 <6>[ 27.219197] CPU6 is up
11687 11:14:15.455182 <6>[ 27.219318] Detected PIPT I-cache on CPU7
11688 11:14:15.461706 <6>[ 27.219341] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11689 11:14:15.468088 <6>[ 27.219356] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11690 11:14:15.471348 <6>[ 27.219607] CPU7 is up
11691 11:14:15.474595 <6>[ 27.826225] OOM killer enabled.
11692 11:14:15.477821 <6>[ 27.829617] Restarting tasks ... done.
11693 11:14:15.484492 <5>[ 27.833970] random: crng reseeded on system resumption
11694 11:14:15.488217 <6>[ 27.840944] PM: suspend exit
11695 11:14:15.498234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=pass>
11696 11:14:15.498581 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=pass
11698 11:14:15.502133 rtcwake: assuming RTC uses UTC ...
11699 11:14:15.508503 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 11:11:32 2024
11700 11:14:15.521571 <6>[ 27.872136] PM: suspend entry (deep)
11701 11:14:15.524841 <6>[ 27.876000] Filesystems sync: 0.000 seconds
11702 11:14:15.528049 <6>[ 27.880746] Freezing user space processes
11703 11:14:15.539232 <6>[ 27.886534] Freezing user space processes completed (elapsed 0.001 seconds)
11704 11:14:15.542290 <6>[ 27.893762] OOM killer disabled.
11705 11:14:15.545478 <6>[ 27.897243] Freezing remaining freezable tasks
11706 11:14:15.555735 <6>[ 27.902629] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11707 11:14:15.562392 <6>[ 27.910281] printk: Suspending console(s) (use no_console_suspend to debug)
11708 11:14:21.227445 <6>[ 27.986548] Disabling non-boot CPUs ...
11709 11:14:21.230416 <6>[ 27.987609] psci: CPU1 killed (polled 0 ms)
11710 11:14:21.233589 <6>[ 27.989622] psci: CPU2 killed (polled 0 ms)
11711 11:14:21.240703 <6>[ 27.990662] psci: CPU3 killed (polled 0 ms)
11712 11:14:21.243820 <6>[ 27.991244] psci: CPU4 killed (polled 0 ms)
11713 11:14:21.246974 <6>[ 27.991885] psci: CPU5 killed (polled 0 ms)
11714 11:14:21.253537 <6>[ 27.992468] psci: CPU6 killed (polled 0 ms)
11715 11:14:21.256915 <6>[ 27.993047] psci: CPU7 killed (polled 0 ms)
11716 11:14:21.260340 <6>[ 27.993366] Enabling non-boot CPUs ...
11717 11:14:21.267180 <6>[ 27.993596] Detected VIPT I-cache on CPU1
11718 11:14:21.273473 <6>[ 27.993682] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11719 11:14:21.280452 <6>[ 27.993743] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11720 11:14:21.283581 <6>[ 27.994379] CPU1 is up
11721 11:14:21.286772 <6>[ 27.994520] Detected VIPT I-cache on CPU2
11722 11:14:21.294014 <6>[ 27.994575] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11723 11:14:21.300613 <6>[ 27.994613] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11724 11:14:21.303770 <6>[ 27.995112] CPU2 is up
11725 11:14:21.306970 <6>[ 27.995248] Detected VIPT I-cache on CPU3
11726 11:14:21.313605 <6>[ 27.995304] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11727 11:14:21.320458 <6>[ 27.995341] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11728 11:14:21.323847 <6>[ 27.995873] CPU3 is up
11729 11:14:21.327498 <6>[ 27.996000] Detected PIPT I-cache on CPU4
11730 11:14:21.337434 <6>[ 27.996021] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11731 11:14:21.343594 <6>[ 27.996035] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11732 11:14:21.343681 <6>[ 27.996304] CPU4 is up
11733 11:14:21.350290 <6>[ 27.996423] Detected PIPT I-cache on CPU5
11734 11:14:21.357044 <6>[ 27.996445] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11735 11:14:21.363588 <6>[ 27.996459] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11736 11:14:21.366525 <6>[ 27.996690] CPU5 is up
11737 11:14:21.369963 <6>[ 27.996811] Detected PIPT I-cache on CPU6
11738 11:14:21.376490 <6>[ 27.996833] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11739 11:14:21.383328 <6>[ 27.996847] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11740 11:14:21.386780 <6>[ 27.997082] CPU6 is up
11741 11:14:21.390168 <6>[ 27.997208] Detected PIPT I-cache on CPU7
11742 11:14:21.400056 <6>[ 27.997231] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11743 11:14:21.406879 <6>[ 27.997245] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11744 11:14:21.407011 <6>[ 27.997488] CPU7 is up
11745 11:14:21.413057 <6>[ 28.542745] OOM killer enabled.
11746 11:14:21.416189 <6>[ 28.546135] Restarting tasks ... done.
11747 11:14:21.420048 <5>[ 28.550542] random: crng reseeded on system resumption
11748 11:14:21.424363 <6>[ 28.557100] PM: suspend exit
11749 11:14:21.435457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=pass>
11750 11:14:21.435725 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=pass
11752 11:14:21.439156 rtcwake: assuming RTC uses UTC ...
11753 11:14:21.445273 rtcwake: wakeup from "mem" using rtc0 at Sun Mar 3 11:11:38 2024
11754 11:14:21.458089 <6>[ 28.587845] PM: suspend entry (deep)
11755 11:14:21.461499 <6>[ 28.591734] Filesystems sync: 0.000 seconds
11756 11:14:21.464748 <6>[ 28.596488] Freezing user space processes
11757 11:14:21.475501 <6>[ 28.602174] Freezing user space processes completed (elapsed 0.001 seconds)
11758 11:14:21.479168 <6>[ 28.609406] OOM killer disabled.
11759 11:14:21.482695 <6>[ 28.612889] Freezing remaining freezable tasks
11760 11:14:21.492467 <6>[ 28.618583] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11761 11:14:21.499050 <6>[ 28.626230] printk: Suspending console(s) (use no_console_suspend to debug)
11762 11:14:27.228632 <6>[ 28.707925] Disabling non-boot CPUs ...
11763 11:14:27.231829 <6>[ 28.708915] psci: CPU1 killed (polled 0 ms)
11764 11:14:27.235001 <6>[ 28.710581] psci: CPU2 killed (polled 4 ms)
11765 11:14:27.241777 <6>[ 28.712576] psci: CPU3 killed (polled 0 ms)
11766 11:14:27.245041 <6>[ 28.713191] psci: CPU4 killed (polled 0 ms)
11767 11:14:27.248584 <6>[ 28.713798] psci: CPU5 killed (polled 0 ms)
11768 11:14:27.255001 <6>[ 28.714356] psci: CPU6 killed (polled 0 ms)
11769 11:14:27.258389 <6>[ 28.714927] psci: CPU7 killed (polled 0 ms)
11770 11:14:27.262195 <6>[ 28.715376] Enabling non-boot CPUs ...
11771 11:14:27.268308 <6>[ 28.715605] Detected VIPT I-cache on CPU1
11772 11:14:27.275109 <6>[ 28.715693] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11773 11:14:27.281894 <6>[ 28.715754] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11774 11:14:27.285400 <6>[ 28.716387] CPU1 is up
11775 11:14:27.288616 <6>[ 28.716524] Detected VIPT I-cache on CPU2
11776 11:14:27.295111 <6>[ 28.716580] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11777 11:14:27.302359 <6>[ 28.716617] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11778 11:14:27.305151 <6>[ 28.717109] CPU2 is up
11779 11:14:27.308802 <6>[ 28.717248] Detected VIPT I-cache on CPU3
11780 11:14:27.315450 <6>[ 28.717305] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11781 11:14:27.321898 <6>[ 28.717341] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11782 11:14:27.325690 <6>[ 28.717875] CPU3 is up
11783 11:14:27.328779 <6>[ 28.717997] Detected PIPT I-cache on CPU4
11784 11:14:27.338562 <6>[ 28.718019] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11785 11:14:27.345231 <6>[ 28.718034] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11786 11:14:27.345314 <6>[ 28.718311] CPU4 is up
11787 11:14:27.352126 <6>[ 28.718441] Detected PIPT I-cache on CPU5
11788 11:14:27.358340 <6>[ 28.718463] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11789 11:14:27.365170 <6>[ 28.718477] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11790 11:14:27.368752 <6>[ 28.718739] CPU5 is up
11791 11:14:27.371698 <6>[ 28.718863] Detected PIPT I-cache on CPU6
11792 11:14:27.378476 <6>[ 28.718886] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11793 11:14:27.385270 <6>[ 28.718900] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11794 11:14:27.388773 <6>[ 28.719139] CPU6 is up
11795 11:14:27.392039 <6>[ 28.719260] Detected PIPT I-cache on CPU7
11796 11:14:27.398382 <6>[ 28.719283] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11797 11:14:27.408441 <6>[ 28.719297] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11798 11:14:27.408525 <6>[ 28.719544] CPU7 is up
11799 11:14:27.411471 <6>[ 29.266863] OOM killer enabled.
11800 11:14:27.418221 <6>[ 29.270253] Restarting tasks ... done.
11801 11:14:27.421493 <5>[ 29.274624] random: crng reseeded on system resumption
11802 11:14:27.425047 <6>[ 29.281137] PM: suspend exit
11803 11:14:27.436034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=pass>
11804 11:14:27.436117 + set +x
11805 11:14:27.436352 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=pass
11807 11:14:27.442880 <LAVA_SIGNAL_ENDRUN 0_sleep 12925665_1.5.2.3.1>
11808 11:14:27.442964 <LAVA_TEST_RUNNER EXIT>
11809 11:14:27.443201 Received signal: <ENDRUN> 0_sleep 12925665_1.5.2.3.1
11810 11:14:27.443283 Ending use of test pattern.
11811 11:14:27.443346 Ending test lava.0_sleep (12925665_1.5.2.3.1), duration 60.18
11813 11:14:27.443569 ok: lava_test_shell seems to have completed
11814 11:14:27.443704 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-mem-1: pass
rtcwake-mem-10: pass
rtcwake-mem-2: pass
rtcwake-mem-3: pass
rtcwake-mem-4: pass
rtcwake-mem-5: pass
rtcwake-mem-6: pass
rtcwake-mem-7: pass
rtcwake-mem-8: pass
rtcwake-mem-9: pass
11815 11:14:27.443800 end: 3.1 lava-test-shell (duration 00:01:01) [common]
11816 11:14:27.443884 end: 3 lava-test-retry (duration 00:01:01) [common]
11817 11:14:27.443969 start: 4 finalize (timeout 00:06:27) [common]
11818 11:14:27.444058 start: 4.1 power-off (timeout 00:00:30) [common]
11819 11:14:27.444210 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11820 11:14:27.522495 >> Command sent successfully.
11821 11:14:27.524941 Returned 0 in 0 seconds
11822 11:14:27.625318 end: 4.1 power-off (duration 00:00:00) [common]
11824 11:14:27.625642 start: 4.2 read-feedback (timeout 00:06:27) [common]
11825 11:14:27.625897 Listened to connection for namespace 'common' for up to 1s
11826 11:14:28.626863 Finalising connection for namespace 'common'
11827 11:14:28.627046 Disconnecting from shell: Finalise
11828 11:14:28.627127 / #
11829 11:14:28.727461 end: 4.2 read-feedback (duration 00:00:01) [common]
11830 11:14:28.727618 end: 4 finalize (duration 00:00:01) [common]
11831 11:14:28.727734 Cleaning after the job
11832 11:14:28.727827 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925665/tftp-deploy-qak9d4qr/ramdisk
11833 11:14:28.741369 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925665/tftp-deploy-qak9d4qr/kernel
11834 11:14:28.766633 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925665/tftp-deploy-qak9d4qr/dtb
11835 11:14:28.766856 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925665/tftp-deploy-qak9d4qr/modules
11836 11:14:28.774119 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12925665
11837 11:14:28.950719 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12925665
11838 11:14:28.950894 Job finished correctly