Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 33
- Boot result: PASS
- Errors: 1
- Warnings: 1
- Kernel Warnings: 14
1 11:07:55.078822 lava-dispatcher, installed at version: 2024.01
2 11:07:55.079024 start: 0 validate
3 11:07:55.079166 Start time: 2024-03-03 11:07:55.079158+00:00 (UTC)
4 11:07:55.079298 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:07:55.079428 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 11:07:55.353044 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:07:55.353276 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:07:55.619068 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:07:55.619375 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:07:55.884788 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:07:55.884978 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.80-cip16%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:07:56.151906 validate duration: 1.07
14 11:07:56.152262 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:07:56.152410 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:07:56.152535 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:07:56.152689 Not decompressing ramdisk as can be used compressed.
18 11:07:56.152805 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 11:07:56.152903 saving as /var/lib/lava/dispatcher/tmp/12925657/tftp-deploy-8ly4v_t3/ramdisk/rootfs.cpio.gz
20 11:07:56.152999 total size: 26246609 (25 MB)
21 11:07:56.154504 progress 0 % (0 MB)
22 11:07:56.161526 progress 5 % (1 MB)
23 11:07:56.168552 progress 10 % (2 MB)
24 11:07:56.175731 progress 15 % (3 MB)
25 11:07:56.182535 progress 20 % (5 MB)
26 11:07:56.189310 progress 25 % (6 MB)
27 11:07:56.196074 progress 30 % (7 MB)
28 11:07:56.203272 progress 35 % (8 MB)
29 11:07:56.210501 progress 40 % (10 MB)
30 11:07:56.217419 progress 45 % (11 MB)
31 11:07:56.224224 progress 50 % (12 MB)
32 11:07:56.231195 progress 55 % (13 MB)
33 11:07:56.238344 progress 60 % (15 MB)
34 11:07:56.245252 progress 65 % (16 MB)
35 11:07:56.252214 progress 70 % (17 MB)
36 11:07:56.259016 progress 75 % (18 MB)
37 11:07:56.265834 progress 80 % (20 MB)
38 11:07:56.272783 progress 85 % (21 MB)
39 11:07:56.279474 progress 90 % (22 MB)
40 11:07:56.286217 progress 95 % (23 MB)
41 11:07:56.292824 progress 100 % (25 MB)
42 11:07:56.293074 25 MB downloaded in 0.14 s (178.69 MB/s)
43 11:07:56.293234 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:07:56.293484 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:07:56.293579 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:07:56.293665 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:07:56.293805 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:07:56.293903 saving as /var/lib/lava/dispatcher/tmp/12925657/tftp-deploy-8ly4v_t3/kernel/Image
50 11:07:56.293995 total size: 51599872 (49 MB)
51 11:07:56.294065 No compression specified
52 11:07:56.295184 progress 0 % (0 MB)
53 11:07:56.308816 progress 5 % (2 MB)
54 11:07:56.322395 progress 10 % (4 MB)
55 11:07:56.336085 progress 15 % (7 MB)
56 11:07:56.349547 progress 20 % (9 MB)
57 11:07:56.363227 progress 25 % (12 MB)
58 11:07:56.376654 progress 30 % (14 MB)
59 11:07:56.390065 progress 35 % (17 MB)
60 11:07:56.403259 progress 40 % (19 MB)
61 11:07:56.417287 progress 45 % (22 MB)
62 11:07:56.431569 progress 50 % (24 MB)
63 11:07:56.445322 progress 55 % (27 MB)
64 11:07:56.458630 progress 60 % (29 MB)
65 11:07:56.471747 progress 65 % (32 MB)
66 11:07:56.484849 progress 70 % (34 MB)
67 11:07:56.498177 progress 75 % (36 MB)
68 11:07:56.511706 progress 80 % (39 MB)
69 11:07:56.525565 progress 85 % (41 MB)
70 11:07:56.539512 progress 90 % (44 MB)
71 11:07:56.552943 progress 95 % (46 MB)
72 11:07:56.566307 progress 100 % (49 MB)
73 11:07:56.566530 49 MB downloaded in 0.27 s (180.56 MB/s)
74 11:07:56.566686 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:07:56.566925 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:07:56.567013 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:07:56.567097 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:07:56.567241 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:07:56.567311 saving as /var/lib/lava/dispatcher/tmp/12925657/tftp-deploy-8ly4v_t3/dtb/mt8192-asurada-spherion-r0.dtb
81 11:07:56.567373 total size: 47278 (0 MB)
82 11:07:56.567443 No compression specified
83 11:07:56.568581 progress 69 % (0 MB)
84 11:07:56.568858 progress 100 % (0 MB)
85 11:07:56.569019 0 MB downloaded in 0.00 s (27.44 MB/s)
86 11:07:56.569151 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:07:56.569381 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:07:56.569467 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:07:56.569550 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:07:56.569664 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.80-cip16/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:07:56.569733 saving as /var/lib/lava/dispatcher/tmp/12925657/tftp-deploy-8ly4v_t3/modules/modules.tar
93 11:07:56.569794 total size: 8628476 (8 MB)
94 11:07:56.569859 Using unxz to decompress xz
95 11:07:56.573382 progress 0 % (0 MB)
96 11:07:56.593309 progress 5 % (0 MB)
97 11:07:56.617190 progress 10 % (0 MB)
98 11:07:56.641474 progress 15 % (1 MB)
99 11:07:56.664182 progress 20 % (1 MB)
100 11:07:56.688490 progress 25 % (2 MB)
101 11:07:56.712096 progress 30 % (2 MB)
102 11:07:56.740358 progress 35 % (2 MB)
103 11:07:56.765367 progress 40 % (3 MB)
104 11:07:56.789001 progress 45 % (3 MB)
105 11:07:56.813249 progress 50 % (4 MB)
106 11:07:56.838041 progress 55 % (4 MB)
107 11:07:56.861543 progress 60 % (4 MB)
108 11:07:56.887203 progress 65 % (5 MB)
109 11:07:56.911856 progress 70 % (5 MB)
110 11:07:56.936920 progress 75 % (6 MB)
111 11:07:56.963213 progress 80 % (6 MB)
112 11:07:56.987440 progress 85 % (7 MB)
113 11:07:57.011626 progress 90 % (7 MB)
114 11:07:57.041881 progress 95 % (7 MB)
115 11:07:57.070633 progress 100 % (8 MB)
116 11:07:57.075785 8 MB downloaded in 0.51 s (16.26 MB/s)
117 11:07:57.076064 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:07:57.076459 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:07:57.076582 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:07:57.076708 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:07:57.076820 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:07:57.076940 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:07:57.077192 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd
125 11:07:57.077358 makedir: /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin
126 11:07:57.077494 makedir: /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/tests
127 11:07:57.077628 makedir: /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/results
128 11:07:57.077774 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-add-keys
129 11:07:57.077958 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-add-sources
130 11:07:57.078119 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-background-process-start
131 11:07:57.078284 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-background-process-stop
132 11:07:57.078445 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-common-functions
133 11:07:57.078573 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-echo-ipv4
134 11:07:57.078700 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-install-packages
135 11:07:57.078820 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-installed-packages
136 11:07:57.078944 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-os-build
137 11:07:57.079063 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-probe-channel
138 11:07:57.079186 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-probe-ip
139 11:07:57.079305 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-target-ip
140 11:07:57.079427 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-target-mac
141 11:07:57.079578 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-target-storage
142 11:07:57.079736 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-test-case
143 11:07:57.079888 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-test-event
144 11:07:57.080041 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-test-feedback
145 11:07:57.080195 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-test-raise
146 11:07:57.080349 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-test-reference
147 11:07:57.080503 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-test-runner
148 11:07:57.080654 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-test-set
149 11:07:57.080809 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-test-shell
150 11:07:57.080966 Updating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-install-packages (oe)
151 11:07:57.081144 Updating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/bin/lava-installed-packages (oe)
152 11:07:57.081296 Creating /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/environment
153 11:07:57.081424 LAVA metadata
154 11:07:57.081526 - LAVA_JOB_ID=12925657
155 11:07:57.081622 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:07:57.081760 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:07:57.081854 skipped lava-vland-overlay
158 11:07:57.081967 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:07:57.082051 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:07:57.082115 skipped lava-multinode-overlay
161 11:07:57.082203 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:07:57.082297 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:07:57.082372 Loading test definitions
164 11:07:57.082469 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:07:57.082544 Using /lava-12925657 at stage 0
166 11:07:57.082838 uuid=12925657_1.5.2.3.1 testdef=None
167 11:07:57.082930 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:07:57.083015 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:07:57.083575 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:07:57.083934 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:07:57.084820 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:07:57.085195 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:07:57.086014 runner path: /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 12925657_1.5.2.3.1
176 11:07:57.086180 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:07:57.086392 Creating lava-test-runner.conf files
179 11:07:57.086457 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12925657/lava-overlay-u0mc7zvd/lava-12925657/0 for stage 0
180 11:07:57.086545 - 0_v4l2-compliance-mtk-vcodec-enc
181 11:07:57.086642 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:07:57.086732 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:07:57.094808 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:07:57.094915 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:07:57.095002 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:07:57.095096 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:07:57.095182 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:07:57.772846 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:07:57.773203 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:07:57.773319 extracting modules file /var/lib/lava/dispatcher/tmp/12925657/tftp-deploy-8ly4v_t3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12925657/extract-overlay-ramdisk-o2_78un7/ramdisk
191 11:07:58.035211 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:07:58.035387 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:07:58.035487 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925657/compress-overlay-o9xptcm1/overlay-1.5.2.4.tar.gz to ramdisk
194 11:07:58.035561 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12925657/compress-overlay-o9xptcm1/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12925657/extract-overlay-ramdisk-o2_78un7/ramdisk
195 11:07:58.042023 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:07:58.042138 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:07:58.042247 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:07:58.042339 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:07:58.042421 Building ramdisk /var/lib/lava/dispatcher/tmp/12925657/extract-overlay-ramdisk-o2_78un7/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12925657/extract-overlay-ramdisk-o2_78un7/ramdisk
200 11:07:58.538931 >> 228478 blocks
201 11:08:02.429863 rename /var/lib/lava/dispatcher/tmp/12925657/extract-overlay-ramdisk-o2_78un7/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12925657/tftp-deploy-8ly4v_t3/ramdisk/ramdisk.cpio.gz
202 11:08:02.430355 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 11:08:02.430488 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 11:08:02.430597 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 11:08:02.430710 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12925657/tftp-deploy-8ly4v_t3/kernel/Image'
206 11:08:14.964638 Returned 0 in 12 seconds
207 11:08:15.065249 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12925657/tftp-deploy-8ly4v_t3/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12925657/tftp-deploy-8ly4v_t3/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12925657/tftp-deploy-8ly4v_t3/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12925657/tftp-deploy-8ly4v_t3/kernel/image.itb
208 11:08:15.628009 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:08:15.628364 output: Created: Sun Mar 3 11:08:15 2024
210 11:08:15.628440 output: Image 0 (kernel-1)
211 11:08:15.628506 output: Description:
212 11:08:15.628574 output: Created: Sun Mar 3 11:08:15 2024
213 11:08:15.628640 output: Type: Kernel Image
214 11:08:15.628702 output: Compression: lzma compressed
215 11:08:15.628764 output: Data Size: 12057697 Bytes = 11775.09 KiB = 11.50 MiB
216 11:08:15.628828 output: Architecture: AArch64
217 11:08:15.628888 output: OS: Linux
218 11:08:15.628946 output: Load Address: 0x00000000
219 11:08:15.629003 output: Entry Point: 0x00000000
220 11:08:15.629062 output: Hash algo: crc32
221 11:08:15.629125 output: Hash value: cf43f4f3
222 11:08:15.629185 output: Image 1 (fdt-1)
223 11:08:15.629244 output: Description: mt8192-asurada-spherion-r0
224 11:08:15.629309 output: Created: Sun Mar 3 11:08:15 2024
225 11:08:15.629394 output: Type: Flat Device Tree
226 11:08:15.629478 output: Compression: uncompressed
227 11:08:15.629564 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 11:08:15.629650 output: Architecture: AArch64
229 11:08:15.629734 output: Hash algo: crc32
230 11:08:15.629819 output: Hash value: cc4352de
231 11:08:15.629902 output: Image 2 (ramdisk-1)
232 11:08:15.630011 output: Description: unavailable
233 11:08:15.630072 output: Created: Sun Mar 3 11:08:15 2024
234 11:08:15.630128 output: Type: RAMDisk Image
235 11:08:15.630183 output: Compression: Unknown Compression
236 11:08:15.630238 output: Data Size: 39380731 Bytes = 38457.75 KiB = 37.56 MiB
237 11:08:15.630295 output: Architecture: AArch64
238 11:08:15.630350 output: OS: Linux
239 11:08:15.630404 output: Load Address: unavailable
240 11:08:15.630461 output: Entry Point: unavailable
241 11:08:15.630540 output: Hash algo: crc32
242 11:08:15.630599 output: Hash value: f6fd0db6
243 11:08:15.630654 output: Default Configuration: 'conf-1'
244 11:08:15.630708 output: Configuration 0 (conf-1)
245 11:08:15.630763 output: Description: mt8192-asurada-spherion-r0
246 11:08:15.630821 output: Kernel: kernel-1
247 11:08:15.630876 output: Init Ramdisk: ramdisk-1
248 11:08:15.630930 output: FDT: fdt-1
249 11:08:15.630985 output: Loadables: kernel-1
250 11:08:15.631041 output:
251 11:08:15.631231 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 11:08:15.631330 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 11:08:15.631433 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 11:08:15.631527 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 11:08:15.631613 No LXC device requested
256 11:08:15.631699 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:08:15.631788 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 11:08:15.631868 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:08:15.631938 Checking files for TFTP limit of 4294967296 bytes.
260 11:08:15.632443 end: 1 tftp-deploy (duration 00:00:19) [common]
261 11:08:15.632553 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:08:15.632645 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:08:15.632774 substitutions:
264 11:08:15.632848 - {DTB}: 12925657/tftp-deploy-8ly4v_t3/dtb/mt8192-asurada-spherion-r0.dtb
265 11:08:15.632914 - {INITRD}: 12925657/tftp-deploy-8ly4v_t3/ramdisk/ramdisk.cpio.gz
266 11:08:15.632975 - {KERNEL}: 12925657/tftp-deploy-8ly4v_t3/kernel/Image
267 11:08:15.633036 - {LAVA_MAC}: None
268 11:08:15.633098 - {PRESEED_CONFIG}: None
269 11:08:15.633186 - {PRESEED_LOCAL}: None
270 11:08:15.633273 - {RAMDISK}: 12925657/tftp-deploy-8ly4v_t3/ramdisk/ramdisk.cpio.gz
271 11:08:15.633362 - {ROOT_PART}: None
272 11:08:15.633452 - {ROOT}: None
273 11:08:15.633537 - {SERVER_IP}: 192.168.201.1
274 11:08:15.633626 - {TEE}: None
275 11:08:15.633711 Parsed boot commands:
276 11:08:15.633798 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:08:15.634041 Parsed boot commands: tftpboot 192.168.201.1 12925657/tftp-deploy-8ly4v_t3/kernel/image.itb 12925657/tftp-deploy-8ly4v_t3/kernel/cmdline
278 11:08:15.634140 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:08:15.634232 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:08:15.634330 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:08:15.634423 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:08:15.634496 Not connected, no need to disconnect.
283 11:08:15.634576 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:08:15.634677 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:08:15.634755 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 11:08:15.638031 Setting prompt string to ['lava-test: # ']
287 11:08:15.638367 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:08:15.638481 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:08:15.638585 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:08:15.638680 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:08:15.638910 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 11:08:20.768417 >> Command sent successfully.
293 11:08:20.770777 Returned 0 in 5 seconds
294 11:08:20.871153 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:08:20.871566 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:08:20.871695 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:08:20.871820 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:08:20.871922 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:08:20.872024 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:08:20.872333 [Enter `^Ec?' for help]
302 11:08:21.044792
303 11:08:21.044944
304 11:08:21.045045 F0: 102B 0000
305 11:08:21.045133
306 11:08:21.045197 F3: 1001 0000 [0200]
307 11:08:21.045260
308 11:08:21.048219 F3: 1001 0000
309 11:08:21.048321
310 11:08:21.048415 F7: 102D 0000
311 11:08:21.048505
312 11:08:21.048595 F1: 0000 0000
313 11:08:21.048683
314 11:08:21.051921 V0: 0000 0000 [0001]
315 11:08:21.051996
316 11:08:21.052059 00: 0007 8000
317 11:08:21.052128
318 11:08:21.055791 01: 0000 0000
319 11:08:21.055869
320 11:08:21.055936 BP: 0C00 0209 [0000]
321 11:08:21.055995
322 11:08:21.059710 G0: 1182 0000
323 11:08:21.059799
324 11:08:21.059867 EC: 0000 0021 [4000]
325 11:08:21.059957
326 11:08:21.063068 S7: 0000 0000 [0000]
327 11:08:21.063147
328 11:08:21.063210 CC: 0000 0000 [0001]
329 11:08:21.063269
330 11:08:21.066452 T0: 0000 0040 [010F]
331 11:08:21.066551
332 11:08:21.066629 Jump to BL
333 11:08:21.066689
334 11:08:21.091525
335 11:08:21.091640
336 11:08:21.091736
337 11:08:21.098749 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:08:21.102551 ARM64: Exception handlers installed.
339 11:08:21.106342 ARM64: Testing exception
340 11:08:21.106418 ARM64: Done test exception
341 11:08:21.114109 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:08:21.125762 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:08:21.132792 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:08:21.142672 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:08:21.149072 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:08:21.156164 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:08:21.168274 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:08:21.175125 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:08:21.194031 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:08:21.197705 WDT: Last reset was cold boot
351 11:08:21.200599 SPI1(PAD0) initialized at 2873684 Hz
352 11:08:21.203934 SPI5(PAD0) initialized at 992727 Hz
353 11:08:21.207432 VBOOT: Loading verstage.
354 11:08:21.214024 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:08:21.217342 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:08:21.220815 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:08:21.224208 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:08:21.231547 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:08:21.238148 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:08:21.249430 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 11:08:21.249546
362 11:08:21.249641
363 11:08:21.259270 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:08:21.262533 ARM64: Exception handlers installed.
365 11:08:21.265665 ARM64: Testing exception
366 11:08:21.265771 ARM64: Done test exception
367 11:08:21.272623 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:08:21.275986 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:08:21.289793 Probing TPM: . done!
370 11:08:21.289899 TPM ready after 0 ms
371 11:08:21.296925 Connected to device vid:did:rid of 1ae0:0028:00
372 11:08:21.303708 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 11:08:21.362457 Initialized TPM device CR50 revision 0
374 11:08:21.371796 tlcl_send_startup: Startup return code is 0
375 11:08:21.371883 TPM: setup succeeded
376 11:08:21.383017 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:08:21.392120 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:08:21.402024 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:08:21.411150 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:08:21.414693 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:08:21.424799 in-header: 03 07 00 00 08 00 00 00
382 11:08:21.428176 in-data: aa e4 47 04 13 02 00 00
383 11:08:21.431986 Chrome EC: UHEPI supported
384 11:08:21.438809 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:08:21.442674 in-header: 03 ad 00 00 08 00 00 00
386 11:08:21.446582 in-data: 00 20 20 08 00 00 00 00
387 11:08:21.446664 Phase 1
388 11:08:21.449786 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:08:21.456994 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:08:21.460866 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:08:21.464485 Recovery requested (1009000e)
392 11:08:21.473720 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:08:21.479468 tlcl_extend: response is 0
394 11:08:21.488853 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:08:21.494316 tlcl_extend: response is 0
396 11:08:21.501477 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:08:21.521891 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 11:08:21.528516 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:08:21.528603
400 11:08:21.528689
401 11:08:21.538493 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:08:21.542099 ARM64: Exception handlers installed.
403 11:08:21.542185 ARM64: Testing exception
404 11:08:21.545427 ARM64: Done test exception
405 11:08:21.567025 pmic_efuse_setting: Set efuses in 11 msecs
406 11:08:21.570736 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:08:21.577456 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:08:21.580712 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:08:21.584406 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:08:21.590722 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:08:21.594101 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:08:21.601860 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:08:21.605351 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:08:21.609181 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:08:21.612601 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:08:21.620292 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:08:21.624174 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:08:21.627978 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:08:21.634501 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:08:21.637874 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:08:21.644470 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:08:21.651198 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:08:21.655134 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:08:21.662197 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:08:21.665862 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:08:21.672911 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:08:21.680193 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:08:21.683927 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:08:21.690556 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:08:21.693876 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:08:21.700316 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:08:21.707424 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:08:21.710815 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:08:21.717244 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:08:21.720819 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:08:21.727185 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:08:21.730691 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:08:21.737295 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:08:21.740712 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:08:21.747301 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:08:21.750603 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:08:21.757209 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:08:21.760622 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:08:21.767254 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:08:21.770468 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:08:21.773878 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:08:21.780604 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:08:21.784452 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:08:21.787679 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:08:21.791216 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:08:21.798003 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:08:21.801320 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:08:21.804793 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:08:21.808033 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:08:21.814513 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:08:21.818085 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:08:21.821228 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:08:21.828159 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:08:21.838301 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:08:21.841704 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:08:21.851491 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:08:21.858174 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:08:21.864904 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:08:21.868117 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:08:21.871460 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:08:21.879805 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x31
467 11:08:21.886333 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:08:21.889542 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 11:08:21.892739 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:08:21.903999 [RTC]rtc_get_frequency_meter,154: input=15, output=771
471 11:08:21.913481 [RTC]rtc_get_frequency_meter,154: input=23, output=957
472 11:08:21.922896 [RTC]rtc_get_frequency_meter,154: input=19, output=865
473 11:08:21.932928 [RTC]rtc_get_frequency_meter,154: input=17, output=819
474 11:08:21.942650 [RTC]rtc_get_frequency_meter,154: input=16, output=796
475 11:08:21.946071 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 11:08:21.949958 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 11:08:21.953920 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
478 11:08:21.961344 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 11:08:21.965230 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
480 11:08:21.965359 ADC[4]: Raw value=902876 ID=7
481 11:08:21.968999 ADC[3]: Raw value=213179 ID=1
482 11:08:21.969084 RAM Code: 0x71
483 11:08:21.976414 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 11:08:21.980391 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 11:08:21.987378 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 11:08:21.994785 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 11:08:21.998579 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 11:08:22.001798 in-header: 03 07 00 00 08 00 00 00
489 11:08:22.005104 in-data: aa e4 47 04 13 02 00 00
490 11:08:22.008920 Chrome EC: UHEPI supported
491 11:08:22.015488 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 11:08:22.018640 in-header: 03 ed 00 00 08 00 00 00
493 11:08:22.022112 in-data: 80 20 60 08 00 00 00 00
494 11:08:22.025323 MRC: failed to locate region type 0.
495 11:08:22.031844 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 11:08:22.031929 DRAM-K: Running full calibration
497 11:08:22.038814 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 11:08:22.042196 header.status = 0x0
499 11:08:22.045482 header.version = 0x6 (expected: 0x6)
500 11:08:22.048584 header.size = 0xd00 (expected: 0xd00)
501 11:08:22.048669 header.flags = 0x0
502 11:08:22.055722 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 11:08:22.074576 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
504 11:08:22.082284 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 11:08:22.085710 dram_init: ddr_geometry: 2
506 11:08:22.085794 [EMI] MDL number = 2
507 11:08:22.088829 [EMI] Get MDL freq = 0
508 11:08:22.088913 dram_init: ddr_type: 0
509 11:08:22.092147 is_discrete_lpddr4: 1
510 11:08:22.095492 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 11:08:22.095576
512 11:08:22.095645
513 11:08:22.098667 [Bian_co] ETT version 0.0.0.1
514 11:08:22.102429 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 11:08:22.102514
516 11:08:22.105669 dramc_set_vcore_voltage set vcore to 650000
517 11:08:22.108931 Read voltage for 800, 4
518 11:08:22.109016 Vio18 = 0
519 11:08:22.112259 Vcore = 650000
520 11:08:22.112343 Vdram = 0
521 11:08:22.112411 Vddq = 0
522 11:08:22.115666 Vmddr = 0
523 11:08:22.115750 dram_init: config_dvfs: 1
524 11:08:22.122147 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 11:08:22.125399 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 11:08:22.128747 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 11:08:22.135785 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 11:08:22.139166 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 11:08:22.142453 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 11:08:22.145723 MEM_TYPE=3, freq_sel=18
531 11:08:22.149169 sv_algorithm_assistance_LP4_1600
532 11:08:22.152329 ============ PULL DRAM RESETB DOWN ============
533 11:08:22.155609 ========== PULL DRAM RESETB DOWN end =========
534 11:08:22.159041 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 11:08:22.162515 ===================================
536 11:08:22.165504 LPDDR4 DRAM CONFIGURATION
537 11:08:22.169148 ===================================
538 11:08:22.172459 EX_ROW_EN[0] = 0x0
539 11:08:22.172543 EX_ROW_EN[1] = 0x0
540 11:08:22.175873 LP4Y_EN = 0x0
541 11:08:22.175957 WORK_FSP = 0x0
542 11:08:22.179063 WL = 0x2
543 11:08:22.179148 RL = 0x2
544 11:08:22.182448 BL = 0x2
545 11:08:22.182532 RPST = 0x0
546 11:08:22.185406 RD_PRE = 0x0
547 11:08:22.185490 WR_PRE = 0x1
548 11:08:22.188709 WR_PST = 0x0
549 11:08:22.188794 DBI_WR = 0x0
550 11:08:22.192425 DBI_RD = 0x0
551 11:08:22.192509 OTF = 0x1
552 11:08:22.195652 ===================================
553 11:08:22.199061 ===================================
554 11:08:22.202247 ANA top config
555 11:08:22.205609 ===================================
556 11:08:22.209006 DLL_ASYNC_EN = 0
557 11:08:22.209091 ALL_SLAVE_EN = 1
558 11:08:22.212327 NEW_RANK_MODE = 1
559 11:08:22.215669 DLL_IDLE_MODE = 1
560 11:08:22.219002 LP45_APHY_COMB_EN = 1
561 11:08:22.219086 TX_ODT_DIS = 1
562 11:08:22.222738 NEW_8X_MODE = 1
563 11:08:22.225879 ===================================
564 11:08:22.229179 ===================================
565 11:08:22.232527 data_rate = 1600
566 11:08:22.235761 CKR = 1
567 11:08:22.239149 DQ_P2S_RATIO = 8
568 11:08:22.242496 ===================================
569 11:08:22.245896 CA_P2S_RATIO = 8
570 11:08:22.246020 DQ_CA_OPEN = 0
571 11:08:22.249099 DQ_SEMI_OPEN = 0
572 11:08:22.252551 CA_SEMI_OPEN = 0
573 11:08:22.255671 CA_FULL_RATE = 0
574 11:08:22.259213 DQ_CKDIV4_EN = 1
575 11:08:22.259298 CA_CKDIV4_EN = 1
576 11:08:22.263249 CA_PREDIV_EN = 0
577 11:08:22.265721 PH8_DLY = 0
578 11:08:22.269096 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 11:08:22.272488 DQ_AAMCK_DIV = 4
580 11:08:22.275944 CA_AAMCK_DIV = 4
581 11:08:22.276028 CA_ADMCK_DIV = 4
582 11:08:22.279343 DQ_TRACK_CA_EN = 0
583 11:08:22.282397 CA_PICK = 800
584 11:08:22.286115 CA_MCKIO = 800
585 11:08:22.289231 MCKIO_SEMI = 0
586 11:08:22.292544 PLL_FREQ = 3068
587 11:08:22.295924 DQ_UI_PI_RATIO = 32
588 11:08:22.296009 CA_UI_PI_RATIO = 0
589 11:08:22.299279 ===================================
590 11:08:22.302595 ===================================
591 11:08:22.305893 memory_type:LPDDR4
592 11:08:22.309150 GP_NUM : 10
593 11:08:22.309234 SRAM_EN : 1
594 11:08:22.312988 MD32_EN : 0
595 11:08:22.315915 ===================================
596 11:08:22.320192 [ANA_INIT] >>>>>>>>>>>>>>
597 11:08:22.320276 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 11:08:22.323509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 11:08:22.327284 ===================================
600 11:08:22.331014 data_rate = 1600,PCW = 0X7600
601 11:08:22.334665 ===================================
602 11:08:22.338465 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 11:08:22.342138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 11:08:22.349336 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 11:08:22.352964 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 11:08:22.356081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 11:08:22.359658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 11:08:22.363224 [ANA_INIT] flow start
609 11:08:22.363330 [ANA_INIT] PLL >>>>>>>>
610 11:08:22.366621 [ANA_INIT] PLL <<<<<<<<
611 11:08:22.369750 [ANA_INIT] MIDPI >>>>>>>>
612 11:08:22.369854 [ANA_INIT] MIDPI <<<<<<<<
613 11:08:22.372784 [ANA_INIT] DLL >>>>>>>>
614 11:08:22.376471 [ANA_INIT] flow end
615 11:08:22.379726 ============ LP4 DIFF to SE enter ============
616 11:08:22.383080 ============ LP4 DIFF to SE exit ============
617 11:08:22.386208 [ANA_INIT] <<<<<<<<<<<<<
618 11:08:22.389736 [Flow] Enable top DCM control >>>>>
619 11:08:22.392906 [Flow] Enable top DCM control <<<<<
620 11:08:22.396556 Enable DLL master slave shuffle
621 11:08:22.399642 ==============================================================
622 11:08:22.402951 Gating Mode config
623 11:08:22.406354 ==============================================================
624 11:08:22.409708 Config description:
625 11:08:22.419594 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 11:08:22.426288 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 11:08:22.429620 SELPH_MODE 0: By rank 1: By Phase
628 11:08:22.436193 ==============================================================
629 11:08:22.439501 GAT_TRACK_EN = 1
630 11:08:22.442886 RX_GATING_MODE = 2
631 11:08:22.446535 RX_GATING_TRACK_MODE = 2
632 11:08:22.449873 SELPH_MODE = 1
633 11:08:22.453224 PICG_EARLY_EN = 1
634 11:08:22.453330 VALID_LAT_VALUE = 1
635 11:08:22.460126 ==============================================================
636 11:08:22.463356 Enter into Gating configuration >>>>
637 11:08:22.466603 Exit from Gating configuration <<<<
638 11:08:22.469893 Enter into DVFS_PRE_config >>>>>
639 11:08:22.479726 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 11:08:22.483450 Exit from DVFS_PRE_config <<<<<
641 11:08:22.486904 Enter into PICG configuration >>>>
642 11:08:22.490598 Exit from PICG configuration <<<<
643 11:08:22.493328 [RX_INPUT] configuration >>>>>
644 11:08:22.496865 [RX_INPUT] configuration <<<<<
645 11:08:22.500189 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 11:08:22.506744 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 11:08:22.513187 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 11:08:22.520238 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 11:08:22.526455 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 11:08:22.529839 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 11:08:22.536986 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 11:08:22.540668 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 11:08:22.544367 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 11:08:22.548167 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 11:08:22.551512 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 11:08:22.554966 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 11:08:22.558715 ===================================
658 11:08:22.562549 LPDDR4 DRAM CONFIGURATION
659 11:08:22.566251 ===================================
660 11:08:22.566347 EX_ROW_EN[0] = 0x0
661 11:08:22.569868 EX_ROW_EN[1] = 0x0
662 11:08:22.569969 LP4Y_EN = 0x0
663 11:08:22.573752 WORK_FSP = 0x0
664 11:08:22.573826 WL = 0x2
665 11:08:22.577169 RL = 0x2
666 11:08:22.577253 BL = 0x2
667 11:08:22.580892 RPST = 0x0
668 11:08:22.580960 RD_PRE = 0x0
669 11:08:22.584311 WR_PRE = 0x1
670 11:08:22.584382 WR_PST = 0x0
671 11:08:22.588398 DBI_WR = 0x0
672 11:08:22.588474 DBI_RD = 0x0
673 11:08:22.588537 OTF = 0x1
674 11:08:22.592098 ===================================
675 11:08:22.595990 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 11:08:22.599596 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 11:08:22.607148 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 11:08:22.611015 ===================================
679 11:08:22.611106 LPDDR4 DRAM CONFIGURATION
680 11:08:22.614904 ===================================
681 11:08:22.618737 EX_ROW_EN[0] = 0x10
682 11:08:22.618810 EX_ROW_EN[1] = 0x0
683 11:08:22.618876 LP4Y_EN = 0x0
684 11:08:22.622062 WORK_FSP = 0x0
685 11:08:22.622138 WL = 0x2
686 11:08:22.625914 RL = 0x2
687 11:08:22.626033 BL = 0x2
688 11:08:22.629707 RPST = 0x0
689 11:08:22.629806 RD_PRE = 0x0
690 11:08:22.633450 WR_PRE = 0x1
691 11:08:22.633549 WR_PST = 0x0
692 11:08:22.637207 DBI_WR = 0x0
693 11:08:22.637307 DBI_RD = 0x0
694 11:08:22.640899 OTF = 0x1
695 11:08:22.644488 ===================================
696 11:08:22.647395 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 11:08:22.652911 nWR fixed to 40
698 11:08:22.653013 [ModeRegInit_LP4] CH0 RK0
699 11:08:22.656709 [ModeRegInit_LP4] CH0 RK1
700 11:08:22.660457 [ModeRegInit_LP4] CH1 RK0
701 11:08:22.660532 [ModeRegInit_LP4] CH1 RK1
702 11:08:22.664291 match AC timing 13
703 11:08:22.668006 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 11:08:22.671721 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 11:08:22.675369 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 11:08:22.682077 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 11:08:22.685994 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 11:08:22.686099 [EMI DOE] emi_dcm 0
709 11:08:22.693110 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 11:08:22.693212 ==
711 11:08:22.697006 Dram Type= 6, Freq= 0, CH_0, rank 0
712 11:08:22.700698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 11:08:22.700799 ==
714 11:08:22.703900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 11:08:22.710878 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 11:08:22.720257 [CA 0] Center 38 (7~69) winsize 63
717 11:08:22.724073 [CA 1] Center 38 (7~69) winsize 63
718 11:08:22.727827 [CA 2] Center 35 (5~66) winsize 62
719 11:08:22.731737 [CA 3] Center 35 (5~66) winsize 62
720 11:08:22.735014 [CA 4] Center 34 (4~65) winsize 62
721 11:08:22.739268 [CA 5] Center 34 (3~65) winsize 63
722 11:08:22.739402
723 11:08:22.743071 [CmdBusTrainingLP45] Vref(ca) range 1: 34
724 11:08:22.743170
725 11:08:22.746693 [CATrainingPosCal] consider 1 rank data
726 11:08:22.746795 u2DelayCellTimex100 = 270/100 ps
727 11:08:22.750724 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
728 11:08:22.754473 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
729 11:08:22.758302 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
730 11:08:22.762159 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
731 11:08:22.765491 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
732 11:08:22.769166 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
733 11:08:22.769251
734 11:08:22.773100 CA PerBit enable=1, Macro0, CA PI delay=34
735 11:08:22.773202
736 11:08:22.776868 [CBTSetCACLKResult] CA Dly = 34
737 11:08:22.776945 CS Dly: 6 (0~37)
738 11:08:22.777010 ==
739 11:08:22.780591 Dram Type= 6, Freq= 0, CH_0, rank 1
740 11:08:22.784076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 11:08:22.788182 ==
742 11:08:22.791531 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 11:08:22.798484 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 11:08:22.806376 [CA 0] Center 38 (7~69) winsize 63
745 11:08:22.810146 [CA 1] Center 38 (8~69) winsize 62
746 11:08:22.814055 [CA 2] Center 36 (6~67) winsize 62
747 11:08:22.817889 [CA 3] Center 36 (5~67) winsize 63
748 11:08:22.821746 [CA 4] Center 35 (4~66) winsize 63
749 11:08:22.825022 [CA 5] Center 34 (4~65) winsize 62
750 11:08:22.825125
751 11:08:22.828913 [CmdBusTrainingLP45] Vref(ca) range 1: 34
752 11:08:22.829022
753 11:08:22.832672 [CATrainingPosCal] consider 2 rank data
754 11:08:22.832777 u2DelayCellTimex100 = 270/100 ps
755 11:08:22.836207 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 11:08:22.839913 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
757 11:08:22.843659 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 11:08:22.846872 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 11:08:22.853783 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 11:08:22.857136 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
761 11:08:22.857241
762 11:08:22.860302 CA PerBit enable=1, Macro0, CA PI delay=34
763 11:08:22.860400
764 11:08:22.863718 [CBTSetCACLKResult] CA Dly = 34
765 11:08:22.863788 CS Dly: 6 (0~38)
766 11:08:22.863848
767 11:08:22.867126 ----->DramcWriteLeveling(PI) begin...
768 11:08:22.867221 ==
769 11:08:22.870492 Dram Type= 6, Freq= 0, CH_0, rank 0
770 11:08:22.877206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 11:08:22.877316 ==
772 11:08:22.880363 Write leveling (Byte 0): 34 => 34
773 11:08:22.880472 Write leveling (Byte 1): 28 => 28
774 11:08:22.883795 DramcWriteLeveling(PI) end<-----
775 11:08:22.883893
776 11:08:22.883991 ==
777 11:08:22.887229 Dram Type= 6, Freq= 0, CH_0, rank 0
778 11:08:22.893739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 11:08:22.893839 ==
780 11:08:22.897114 [Gating] SW mode calibration
781 11:08:22.905104 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 11:08:22.908685 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 11:08:22.912228 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 11:08:22.915978 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
785 11:08:22.922655 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
786 11:08:22.925991 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
787 11:08:22.929898 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 11:08:22.933279 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:08:22.940642 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:08:22.943470 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:08:22.946971 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:08:22.953726 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:08:22.956734 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:08:22.960080 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:08:22.963474 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:08:22.970138 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:08:22.973441 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:08:22.976892 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:08:22.983390 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 11:08:22.986504 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
801 11:08:22.989783 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
802 11:08:22.996549 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:08:23.000270 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:08:23.003716 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 11:08:23.010062 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:08:23.013357 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:08:23.016910 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:08:23.023277 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
809 11:08:23.027206 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
810 11:08:23.030382 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
811 11:08:23.036588 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 11:08:23.040111 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 11:08:23.043572 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 11:08:23.046891 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:08:23.053495 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:08:23.056786 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 1)
817 11:08:23.060019 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
818 11:08:23.066822 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
819 11:08:23.070147 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 11:08:23.073467 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 11:08:23.080137 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 11:08:23.083503 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:08:23.086769 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:08:23.093666 0 11 4 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
825 11:08:23.097021 0 11 8 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
826 11:08:23.100382 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 11:08:23.106727 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 11:08:23.110247 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 11:08:23.113535 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 11:08:23.120199 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:08:23.123515 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:08:23.126985 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
833 11:08:23.130268 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 11:08:23.137065 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 11:08:23.140284 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 11:08:23.143657 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 11:08:23.150515 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:08:23.153945 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:08:23.157176 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:08:23.163761 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:08:23.166961 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:08:23.170662 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:08:23.177334 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:08:23.180710 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:08:23.183940 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:08:23.190656 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:08:23.193827 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
848 11:08:23.197146 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
849 11:08:23.203978 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 11:08:23.204062 Total UI for P1: 0, mck2ui 16
851 11:08:23.207384 best dqsien dly found for B0: ( 0, 14, 2)
852 11:08:23.210692 Total UI for P1: 0, mck2ui 16
853 11:08:23.213886 best dqsien dly found for B1: ( 0, 14, 4)
854 11:08:23.217507 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
855 11:08:23.220818 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
856 11:08:23.223820
857 11:08:23.227507 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
858 11:08:23.230632 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
859 11:08:23.234046 [Gating] SW calibration Done
860 11:08:23.234128 ==
861 11:08:23.237402 Dram Type= 6, Freq= 0, CH_0, rank 0
862 11:08:23.240691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
863 11:08:23.240801 ==
864 11:08:23.240890 RX Vref Scan: 0
865 11:08:23.240954
866 11:08:23.243791 RX Vref 0 -> 0, step: 1
867 11:08:23.243874
868 11:08:23.247264 RX Delay -130 -> 252, step: 16
869 11:08:23.250686 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
870 11:08:23.253846 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
871 11:08:23.260317 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
872 11:08:23.263748 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
873 11:08:23.267089 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
874 11:08:23.270659 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
875 11:08:23.273818 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
876 11:08:23.280493 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
877 11:08:23.283867 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
878 11:08:23.286967 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
879 11:08:23.290364 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
880 11:08:23.293712 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
881 11:08:23.300666 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
882 11:08:23.303835 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
883 11:08:23.307381 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
884 11:08:23.310443 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
885 11:08:23.310527 ==
886 11:08:23.314176 Dram Type= 6, Freq= 0, CH_0, rank 0
887 11:08:23.320332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
888 11:08:23.320432 ==
889 11:08:23.320498 DQS Delay:
890 11:08:23.320559 DQS0 = 0, DQS1 = 0
891 11:08:23.323825 DQM Delay:
892 11:08:23.323949 DQM0 = 93, DQM1 = 81
893 11:08:23.327129 DQ Delay:
894 11:08:23.330529 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
895 11:08:23.334083 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
896 11:08:23.337180 DQ8 =77, DQ9 =61, DQ10 =85, DQ11 =77
897 11:08:23.340558 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
898 11:08:23.340642
899 11:08:23.340707
900 11:08:23.340768 ==
901 11:08:23.344006 Dram Type= 6, Freq= 0, CH_0, rank 0
902 11:08:23.346928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 11:08:23.347012 ==
904 11:08:23.347080
905 11:08:23.347141
906 11:08:23.350291 TX Vref Scan disable
907 11:08:23.350374 == TX Byte 0 ==
908 11:08:23.357111 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
909 11:08:23.360410 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
910 11:08:23.360516 == TX Byte 1 ==
911 11:08:23.367515 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
912 11:08:23.370594 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
913 11:08:23.370859 ==
914 11:08:23.373912 Dram Type= 6, Freq= 0, CH_0, rank 0
915 11:08:23.377245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
916 11:08:23.377354 ==
917 11:08:23.392005 TX Vref=22, minBit 1, minWin=27, winSum=442
918 11:08:23.395703 TX Vref=24, minBit 8, minWin=27, winSum=445
919 11:08:23.398318 TX Vref=26, minBit 8, minWin=27, winSum=448
920 11:08:23.401674 TX Vref=28, minBit 13, minWin=27, winSum=450
921 11:08:23.405237 TX Vref=30, minBit 4, minWin=28, winSum=454
922 11:08:23.408561 TX Vref=32, minBit 5, minWin=28, winSum=455
923 11:08:23.415407 [TxChooseVref] Worse bit 5, Min win 28, Win sum 455, Final Vref 32
924 11:08:23.415494
925 11:08:23.418614 Final TX Range 1 Vref 32
926 11:08:23.418701
927 11:08:23.418788 ==
928 11:08:23.421869 Dram Type= 6, Freq= 0, CH_0, rank 0
929 11:08:23.425192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 11:08:23.425279 ==
931 11:08:23.425365
932 11:08:23.425466
933 11:08:23.428721 TX Vref Scan disable
934 11:08:23.432056 == TX Byte 0 ==
935 11:08:23.435616 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
936 11:08:23.438542 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
937 11:08:23.442183 == TX Byte 1 ==
938 11:08:23.445319 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
939 11:08:23.448699 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
940 11:08:23.448787
941 11:08:23.452041 [DATLAT]
942 11:08:23.452129 Freq=800, CH0 RK0
943 11:08:23.452219
944 11:08:23.455700 DATLAT Default: 0xa
945 11:08:23.455787 0, 0xFFFF, sum = 0
946 11:08:23.458712 1, 0xFFFF, sum = 0
947 11:08:23.458801 2, 0xFFFF, sum = 0
948 11:08:23.462049 3, 0xFFFF, sum = 0
949 11:08:23.462137 4, 0xFFFF, sum = 0
950 11:08:23.465258 5, 0xFFFF, sum = 0
951 11:08:23.465358 6, 0xFFFF, sum = 0
952 11:08:23.468893 7, 0xFFFF, sum = 0
953 11:08:23.468980 8, 0xFFFF, sum = 0
954 11:08:23.472357 9, 0x0, sum = 1
955 11:08:23.472444 10, 0x0, sum = 2
956 11:08:23.475555 11, 0x0, sum = 3
957 11:08:23.475641 12, 0x0, sum = 4
958 11:08:23.478955 best_step = 10
959 11:08:23.479061
960 11:08:23.479157 ==
961 11:08:23.482337 Dram Type= 6, Freq= 0, CH_0, rank 0
962 11:08:23.485842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
963 11:08:23.485928 ==
964 11:08:23.488964 RX Vref Scan: 1
965 11:08:23.489049
966 11:08:23.489131 Set Vref Range= 32 -> 127
967 11:08:23.489206
968 11:08:23.492452 RX Vref 32 -> 127, step: 1
969 11:08:23.492537
970 11:08:23.495795 RX Delay -95 -> 252, step: 8
971 11:08:23.495880
972 11:08:23.499139 Set Vref, RX VrefLevel [Byte0]: 32
973 11:08:23.502502 [Byte1]: 32
974 11:08:23.502599
975 11:08:23.505829 Set Vref, RX VrefLevel [Byte0]: 33
976 11:08:23.508996 [Byte1]: 33
977 11:08:23.509108
978 11:08:23.512526 Set Vref, RX VrefLevel [Byte0]: 34
979 11:08:23.515774 [Byte1]: 34
980 11:08:23.519886
981 11:08:23.519971 Set Vref, RX VrefLevel [Byte0]: 35
982 11:08:23.523183 [Byte1]: 35
983 11:08:23.527606
984 11:08:23.527717 Set Vref, RX VrefLevel [Byte0]: 36
985 11:08:23.530827 [Byte1]: 36
986 11:08:23.534782
987 11:08:23.534867 Set Vref, RX VrefLevel [Byte0]: 37
988 11:08:23.538130 [Byte1]: 37
989 11:08:23.542742
990 11:08:23.542856 Set Vref, RX VrefLevel [Byte0]: 38
991 11:08:23.545812 [Byte1]: 38
992 11:08:23.550426
993 11:08:23.550509 Set Vref, RX VrefLevel [Byte0]: 39
994 11:08:23.553459 [Byte1]: 39
995 11:08:23.557660
996 11:08:23.557744 Set Vref, RX VrefLevel [Byte0]: 40
997 11:08:23.561566 [Byte1]: 40
998 11:08:23.565933
999 11:08:23.566063 Set Vref, RX VrefLevel [Byte0]: 41
1000 11:08:23.569336 [Byte1]: 41
1001 11:08:23.573331
1002 11:08:23.573414 Set Vref, RX VrefLevel [Byte0]: 42
1003 11:08:23.576704 [Byte1]: 42
1004 11:08:23.580751
1005 11:08:23.580843 Set Vref, RX VrefLevel [Byte0]: 43
1006 11:08:23.584077 [Byte1]: 43
1007 11:08:23.588445
1008 11:08:23.588530 Set Vref, RX VrefLevel [Byte0]: 44
1009 11:08:23.591831 [Byte1]: 44
1010 11:08:23.596259
1011 11:08:23.596343 Set Vref, RX VrefLevel [Byte0]: 45
1012 11:08:23.599385 [Byte1]: 45
1013 11:08:23.603713
1014 11:08:23.603797 Set Vref, RX VrefLevel [Byte0]: 46
1015 11:08:23.607003 [Byte1]: 46
1016 11:08:23.611168
1017 11:08:23.611255 Set Vref, RX VrefLevel [Byte0]: 47
1018 11:08:23.614397 [Byte1]: 47
1019 11:08:23.618715
1020 11:08:23.618799 Set Vref, RX VrefLevel [Byte0]: 48
1021 11:08:23.622051 [Byte1]: 48
1022 11:08:23.625883
1023 11:08:23.625996 Set Vref, RX VrefLevel [Byte0]: 49
1024 11:08:23.629253 [Byte1]: 49
1025 11:08:23.633803
1026 11:08:23.633885 Set Vref, RX VrefLevel [Byte0]: 50
1027 11:08:23.637137 [Byte1]: 50
1028 11:08:23.641491
1029 11:08:23.641587 Set Vref, RX VrefLevel [Byte0]: 51
1030 11:08:23.645042 [Byte1]: 51
1031 11:08:23.648893
1032 11:08:23.648970 Set Vref, RX VrefLevel [Byte0]: 52
1033 11:08:23.652415 [Byte1]: 52
1034 11:08:23.656712
1035 11:08:23.656810 Set Vref, RX VrefLevel [Byte0]: 53
1036 11:08:23.659886 [Byte1]: 53
1037 11:08:23.663870
1038 11:08:23.663969 Set Vref, RX VrefLevel [Byte0]: 54
1039 11:08:23.667247 [Byte1]: 54
1040 11:08:23.671736
1041 11:08:23.671805 Set Vref, RX VrefLevel [Byte0]: 55
1042 11:08:23.675034 [Byte1]: 55
1043 11:08:23.679480
1044 11:08:23.679562 Set Vref, RX VrefLevel [Byte0]: 56
1045 11:08:23.682815 [Byte1]: 56
1046 11:08:23.686984
1047 11:08:23.687066 Set Vref, RX VrefLevel [Byte0]: 57
1048 11:08:23.690296 [Byte1]: 57
1049 11:08:23.694925
1050 11:08:23.695007 Set Vref, RX VrefLevel [Byte0]: 58
1051 11:08:23.697859 [Byte1]: 58
1052 11:08:23.701880
1053 11:08:23.702019 Set Vref, RX VrefLevel [Byte0]: 59
1054 11:08:23.705278 [Byte1]: 59
1055 11:08:23.709843
1056 11:08:23.709925 Set Vref, RX VrefLevel [Byte0]: 60
1057 11:08:23.713029 [Byte1]: 60
1058 11:08:23.717175
1059 11:08:23.717256 Set Vref, RX VrefLevel [Byte0]: 61
1060 11:08:23.720397 [Byte1]: 61
1061 11:08:23.724985
1062 11:08:23.725067 Set Vref, RX VrefLevel [Byte0]: 62
1063 11:08:23.728321 [Byte1]: 62
1064 11:08:23.732588
1065 11:08:23.732670 Set Vref, RX VrefLevel [Byte0]: 63
1066 11:08:23.735711 [Byte1]: 63
1067 11:08:23.740341
1068 11:08:23.740423 Set Vref, RX VrefLevel [Byte0]: 64
1069 11:08:23.743723 [Byte1]: 64
1070 11:08:23.747990
1071 11:08:23.748073 Set Vref, RX VrefLevel [Byte0]: 65
1072 11:08:23.751108 [Byte1]: 65
1073 11:08:23.755550
1074 11:08:23.755632 Set Vref, RX VrefLevel [Byte0]: 66
1075 11:08:23.758610 [Byte1]: 66
1076 11:08:23.762705
1077 11:08:23.762864 Set Vref, RX VrefLevel [Byte0]: 67
1078 11:08:23.766170 [Byte1]: 67
1079 11:08:23.770519
1080 11:08:23.770594 Set Vref, RX VrefLevel [Byte0]: 68
1081 11:08:23.773756 [Byte1]: 68
1082 11:08:23.778154
1083 11:08:23.778240 Set Vref, RX VrefLevel [Byte0]: 69
1084 11:08:23.781503 [Byte1]: 69
1085 11:08:23.785580
1086 11:08:23.785653 Set Vref, RX VrefLevel [Byte0]: 70
1087 11:08:23.789292 [Byte1]: 70
1088 11:08:23.793170
1089 11:08:23.793267 Set Vref, RX VrefLevel [Byte0]: 71
1090 11:08:23.796365 [Byte1]: 71
1091 11:08:23.801130
1092 11:08:23.801212 Set Vref, RX VrefLevel [Byte0]: 72
1093 11:08:23.804288 [Byte1]: 72
1094 11:08:23.808321
1095 11:08:23.808404 Set Vref, RX VrefLevel [Byte0]: 73
1096 11:08:23.811818 [Byte1]: 73
1097 11:08:23.816256
1098 11:08:23.816339 Set Vref, RX VrefLevel [Byte0]: 74
1099 11:08:23.819634 [Byte1]: 74
1100 11:08:23.823672
1101 11:08:23.823754 Set Vref, RX VrefLevel [Byte0]: 75
1102 11:08:23.826932 [Byte1]: 75
1103 11:08:23.831160
1104 11:08:23.831243 Set Vref, RX VrefLevel [Byte0]: 76
1105 11:08:23.834457 [Byte1]: 76
1106 11:08:23.838618
1107 11:08:23.838700 Set Vref, RX VrefLevel [Byte0]: 77
1108 11:08:23.841921 [Byte1]: 77
1109 11:08:23.846616
1110 11:08:23.846698 Set Vref, RX VrefLevel [Byte0]: 78
1111 11:08:23.849861 [Byte1]: 78
1112 11:08:23.853900
1113 11:08:23.854004 Set Vref, RX VrefLevel [Byte0]: 79
1114 11:08:23.857205 [Byte1]: 79
1115 11:08:23.861398
1116 11:08:23.861480 Final RX Vref Byte 0 = 62 to rank0
1117 11:08:23.864840 Final RX Vref Byte 1 = 61 to rank0
1118 11:08:23.868183 Final RX Vref Byte 0 = 62 to rank1
1119 11:08:23.871551 Final RX Vref Byte 1 = 61 to rank1==
1120 11:08:23.874879 Dram Type= 6, Freq= 0, CH_0, rank 0
1121 11:08:23.881625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1122 11:08:23.881708 ==
1123 11:08:23.881776 DQS Delay:
1124 11:08:23.881838 DQS0 = 0, DQS1 = 0
1125 11:08:23.884970 DQM Delay:
1126 11:08:23.885053 DQM0 = 93, DQM1 = 82
1127 11:08:23.888294 DQ Delay:
1128 11:08:23.891460 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1129 11:08:23.894878 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1130 11:08:23.898313 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1131 11:08:23.901448 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =92
1132 11:08:23.901666
1133 11:08:23.901788
1134 11:08:23.908168 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1135 11:08:23.911935 CH0 RK0: MR19=606, MR18=3E39
1136 11:08:23.918537 CH0_RK0: MR19=0x606, MR18=0x3E39, DQSOSC=394, MR23=63, INC=95, DEC=63
1137 11:08:23.918621
1138 11:08:23.921615 ----->DramcWriteLeveling(PI) begin...
1139 11:08:23.921699 ==
1140 11:08:23.924827 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 11:08:23.928296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 11:08:23.928379 ==
1143 11:08:23.931682 Write leveling (Byte 0): 33 => 33
1144 11:08:23.935149 Write leveling (Byte 1): 32 => 32
1145 11:08:23.938163 DramcWriteLeveling(PI) end<-----
1146 11:08:23.938245
1147 11:08:23.938310 ==
1148 11:08:23.941397 Dram Type= 6, Freq= 0, CH_0, rank 1
1149 11:08:23.944896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1150 11:08:23.944979 ==
1151 11:08:23.948174 [Gating] SW mode calibration
1152 11:08:23.955174 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1153 11:08:23.961620 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1154 11:08:23.964884 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1155 11:08:23.968227 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1156 11:08:24.012011 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:08:24.012283 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 11:08:24.012356 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:08:24.012420 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:08:24.012480 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:08:24.012549 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:08:24.012977 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:08:24.013242 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:08:24.013316 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:08:24.013382 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:08:24.021190 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:08:24.024010 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:08:24.027572 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:08:24.030596 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:08:24.034091 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1171 11:08:24.040550 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1172 11:08:24.043898 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:08:24.047204 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 11:08:24.054216 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:08:24.057415 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:08:24.060598 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:08:24.067229 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:08:24.070445 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:08:24.073850 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1180 11:08:24.080513 0 9 8 | B1->B0 | 2d2d 3434 | 0 0 | (0 0) (0 0)
1181 11:08:24.083824 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 11:08:24.087214 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 11:08:24.094093 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 11:08:24.097557 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 11:08:24.100815 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 11:08:24.107608 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 11:08:24.110875 0 10 4 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
1188 11:08:24.113974 0 10 8 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (1 0)
1189 11:08:24.117488 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 11:08:24.124256 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:08:24.128040 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:08:24.131222 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 11:08:24.137754 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 11:08:24.141077 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 11:08:24.144485 0 11 4 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
1196 11:08:24.151716 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1197 11:08:24.155426 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 11:08:24.159046 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 11:08:24.162763 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 11:08:24.166042 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 11:08:24.172917 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 11:08:24.176323 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1203 11:08:24.180238 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 11:08:24.183351 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1205 11:08:24.190154 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 11:08:24.193619 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:08:24.197065 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:08:24.203715 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:08:24.206987 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:08:24.210375 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:08:24.216702 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:08:24.220239 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:08:24.223554 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:08:24.230232 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:08:24.233803 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:08:24.237073 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:08:24.243884 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 11:08:24.246854 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 11:08:24.250317 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1220 11:08:24.256728 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 11:08:24.256838 Total UI for P1: 0, mck2ui 16
1222 11:08:24.260001 best dqsien dly found for B0: ( 0, 14, 4)
1223 11:08:24.263281 Total UI for P1: 0, mck2ui 16
1224 11:08:24.266702 best dqsien dly found for B1: ( 0, 14, 4)
1225 11:08:24.270107 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1226 11:08:24.276788 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1227 11:08:24.276895
1228 11:08:24.280131 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1229 11:08:24.283564 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1230 11:08:24.286737 [Gating] SW calibration Done
1231 11:08:24.286816 ==
1232 11:08:24.290124 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 11:08:24.293298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 11:08:24.293403 ==
1235 11:08:24.293493 RX Vref Scan: 0
1236 11:08:24.293589
1237 11:08:24.296686 RX Vref 0 -> 0, step: 1
1238 11:08:24.296782
1239 11:08:24.299882 RX Delay -130 -> 252, step: 16
1240 11:08:24.303593 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1241 11:08:24.306792 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1242 11:08:24.313558 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1243 11:08:24.316778 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1244 11:08:24.320320 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1245 11:08:24.323340 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1246 11:08:24.326818 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1247 11:08:24.333461 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1248 11:08:24.336730 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1249 11:08:24.340075 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1250 11:08:24.343742 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1251 11:08:24.346618 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1252 11:08:24.353315 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1253 11:08:24.356735 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1254 11:08:24.360025 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1255 11:08:24.363325 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1256 11:08:24.363411 ==
1257 11:08:24.366929 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 11:08:24.373438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 11:08:24.373538 ==
1260 11:08:24.373622 DQS Delay:
1261 11:08:24.376832 DQS0 = 0, DQS1 = 0
1262 11:08:24.376933 DQM Delay:
1263 11:08:24.377025 DQM0 = 88, DQM1 = 78
1264 11:08:24.380204 DQ Delay:
1265 11:08:24.383497 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1266 11:08:24.386701 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
1267 11:08:24.390102 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1268 11:08:24.393475 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1269 11:08:24.393564
1270 11:08:24.393630
1271 11:08:24.393705 ==
1272 11:08:24.396821 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 11:08:24.400124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 11:08:24.400240 ==
1275 11:08:24.400335
1276 11:08:24.400425
1277 11:08:24.403431 TX Vref Scan disable
1278 11:08:24.403544 == TX Byte 0 ==
1279 11:08:24.409896 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1280 11:08:24.413225 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1281 11:08:24.413325 == TX Byte 1 ==
1282 11:08:24.420195 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1283 11:08:24.423489 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1284 11:08:24.423588 ==
1285 11:08:24.426901 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 11:08:24.430374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 11:08:24.430479 ==
1288 11:08:24.444240 TX Vref=22, minBit 1, minWin=27, winSum=446
1289 11:08:24.447148 TX Vref=24, minBit 8, minWin=27, winSum=450
1290 11:08:24.450398 TX Vref=26, minBit 4, minWin=28, winSum=455
1291 11:08:24.454067 TX Vref=28, minBit 8, minWin=27, winSum=454
1292 11:08:24.457346 TX Vref=30, minBit 4, minWin=28, winSum=456
1293 11:08:24.460718 TX Vref=32, minBit 8, minWin=27, winSum=455
1294 11:08:24.467438 [TxChooseVref] Worse bit 4, Min win 28, Win sum 456, Final Vref 30
1295 11:08:24.467546
1296 11:08:24.470808 Final TX Range 1 Vref 30
1297 11:08:24.470889
1298 11:08:24.470953 ==
1299 11:08:24.474110 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 11:08:24.477296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 11:08:24.477377 ==
1302 11:08:24.477441
1303 11:08:24.477501
1304 11:08:24.481109 TX Vref Scan disable
1305 11:08:24.484440 == TX Byte 0 ==
1306 11:08:24.487841 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1307 11:08:24.491104 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1308 11:08:24.494414 == TX Byte 1 ==
1309 11:08:24.497723 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1310 11:08:24.501149 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1311 11:08:24.501230
1312 11:08:24.504543 [DATLAT]
1313 11:08:24.504623 Freq=800, CH0 RK1
1314 11:08:24.504686
1315 11:08:24.507753 DATLAT Default: 0xa
1316 11:08:24.507834 0, 0xFFFF, sum = 0
1317 11:08:24.510999 1, 0xFFFF, sum = 0
1318 11:08:24.511080 2, 0xFFFF, sum = 0
1319 11:08:24.514194 3, 0xFFFF, sum = 0
1320 11:08:24.514275 4, 0xFFFF, sum = 0
1321 11:08:24.517556 5, 0xFFFF, sum = 0
1322 11:08:24.517637 6, 0xFFFF, sum = 0
1323 11:08:24.521003 7, 0xFFFF, sum = 0
1324 11:08:24.521085 8, 0xFFFF, sum = 0
1325 11:08:24.524243 9, 0x0, sum = 1
1326 11:08:24.524325 10, 0x0, sum = 2
1327 11:08:24.527453 11, 0x0, sum = 3
1328 11:08:24.527535 12, 0x0, sum = 4
1329 11:08:24.531140 best_step = 10
1330 11:08:24.531221
1331 11:08:24.531284 ==
1332 11:08:24.534166 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 11:08:24.537866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 11:08:24.538007 ==
1335 11:08:24.540927 RX Vref Scan: 0
1336 11:08:24.541007
1337 11:08:24.541072 RX Vref 0 -> 0, step: 1
1338 11:08:24.541132
1339 11:08:24.544353 RX Delay -79 -> 252, step: 8
1340 11:08:24.551026 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1341 11:08:24.554269 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1342 11:08:24.557586 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1343 11:08:24.561067 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1344 11:08:24.564154 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1345 11:08:24.567791 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1346 11:08:24.574232 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1347 11:08:24.577492 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1348 11:08:24.580913 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1349 11:08:24.584055 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1350 11:08:24.587721 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1351 11:08:24.594494 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1352 11:08:24.598079 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1353 11:08:24.600975 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1354 11:08:24.604668 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1355 11:08:24.607826 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1356 11:08:24.611057 ==
1357 11:08:24.614646 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 11:08:24.617809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 11:08:24.617916 ==
1360 11:08:24.617997 DQS Delay:
1361 11:08:24.621275 DQS0 = 0, DQS1 = 0
1362 11:08:24.621356 DQM Delay:
1363 11:08:24.624385 DQM0 = 91, DQM1 = 81
1364 11:08:24.624465 DQ Delay:
1365 11:08:24.627622 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =88
1366 11:08:24.630950 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1367 11:08:24.634271 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1368 11:08:24.637874 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1369 11:08:24.638016
1370 11:08:24.638083
1371 11:08:24.644439 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1372 11:08:24.647488 CH0 RK1: MR19=606, MR18=3F18
1373 11:08:24.654408 CH0_RK1: MR19=0x606, MR18=0x3F18, DQSOSC=393, MR23=63, INC=95, DEC=63
1374 11:08:24.657553 [RxdqsGatingPostProcess] freq 800
1375 11:08:24.664562 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1376 11:08:24.664646 Pre-setting of DQS Precalculation
1377 11:08:24.671073 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1378 11:08:24.671158 ==
1379 11:08:24.674303 Dram Type= 6, Freq= 0, CH_1, rank 0
1380 11:08:24.677910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 11:08:24.678032 ==
1382 11:08:24.684566 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1383 11:08:24.691314 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1384 11:08:24.698738 [CA 0] Center 36 (6~67) winsize 62
1385 11:08:24.702087 [CA 1] Center 37 (6~68) winsize 63
1386 11:08:24.705797 [CA 2] Center 34 (4~65) winsize 62
1387 11:08:24.709167 [CA 3] Center 34 (4~65) winsize 62
1388 11:08:24.712490 [CA 4] Center 34 (4~65) winsize 62
1389 11:08:24.715697 [CA 5] Center 33 (3~64) winsize 62
1390 11:08:24.715780
1391 11:08:24.718954 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1392 11:08:24.719038
1393 11:08:24.721864 [CATrainingPosCal] consider 1 rank data
1394 11:08:24.725308 u2DelayCellTimex100 = 270/100 ps
1395 11:08:24.728600 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1396 11:08:24.732279 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1397 11:08:24.738900 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1398 11:08:24.742135 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1399 11:08:24.745173 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1400 11:08:24.748440 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1401 11:08:24.748518
1402 11:08:24.751996 CA PerBit enable=1, Macro0, CA PI delay=33
1403 11:08:24.752072
1404 11:08:24.755622 [CBTSetCACLKResult] CA Dly = 33
1405 11:08:24.755694 CS Dly: 5 (0~36)
1406 11:08:24.758689 ==
1407 11:08:24.761867 Dram Type= 6, Freq= 0, CH_1, rank 1
1408 11:08:24.765276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 11:08:24.765354 ==
1410 11:08:24.768440 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1411 11:08:24.775395 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1412 11:08:24.784929 [CA 0] Center 36 (6~67) winsize 62
1413 11:08:24.788455 [CA 1] Center 37 (6~68) winsize 63
1414 11:08:24.791753 [CA 2] Center 35 (5~66) winsize 62
1415 11:08:24.795068 [CA 3] Center 34 (4~65) winsize 62
1416 11:08:24.798471 [CA 4] Center 35 (5~65) winsize 61
1417 11:08:24.801782 [CA 5] Center 34 (4~65) winsize 62
1418 11:08:24.801860
1419 11:08:24.805143 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1420 11:08:24.805215
1421 11:08:24.808519 [CATrainingPosCal] consider 2 rank data
1422 11:08:24.811658 u2DelayCellTimex100 = 270/100 ps
1423 11:08:24.815133 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 11:08:24.818588 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1425 11:08:24.822380 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1426 11:08:24.825675 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 11:08:24.829509 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1428 11:08:24.832889 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1429 11:08:24.832958
1430 11:08:24.837231 CA PerBit enable=1, Macro0, CA PI delay=34
1431 11:08:24.837303
1432 11:08:24.840627 [CBTSetCACLKResult] CA Dly = 34
1433 11:08:24.844480 CS Dly: 6 (0~38)
1434 11:08:24.844562
1435 11:08:24.848395 ----->DramcWriteLeveling(PI) begin...
1436 11:08:24.848463 ==
1437 11:08:24.851980 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 11:08:24.855146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 11:08:24.855215 ==
1440 11:08:24.859117 Write leveling (Byte 0): 27 => 27
1441 11:08:24.862096 Write leveling (Byte 1): 28 => 28
1442 11:08:24.862164 DramcWriteLeveling(PI) end<-----
1443 11:08:24.865255
1444 11:08:24.865319 ==
1445 11:08:24.868684 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 11:08:24.872042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 11:08:24.872115 ==
1448 11:08:24.875550 [Gating] SW mode calibration
1449 11:08:24.882328 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1450 11:08:24.885150 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1451 11:08:24.892116 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1452 11:08:24.895170 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1453 11:08:24.898443 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:08:24.905405 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:08:24.908706 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:08:24.911927 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:08:24.918678 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:08:24.921844 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:08:24.925169 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:08:24.932221 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:08:24.935596 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:08:24.939005 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:08:24.941914 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:08:24.948847 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:08:24.952171 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:08:24.955486 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:08:24.962326 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:08:24.965413 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1469 11:08:24.968898 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1470 11:08:24.975566 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 11:08:24.979104 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:08:24.982168 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:08:24.988759 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:08:24.992225 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:08:24.995705 0 9 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1476 11:08:25.001956 0 9 4 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
1477 11:08:25.005386 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1478 11:08:25.008639 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 11:08:25.015693 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 11:08:25.018715 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 11:08:25.022236 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 11:08:25.025688 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 11:08:25.032227 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1484 11:08:25.035645 0 10 4 | B1->B0 | 2f2f 2c2c | 1 0 | (1 0) (0 0)
1485 11:08:25.038995 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 11:08:25.045543 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 11:08:25.048913 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 11:08:25.052241 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 11:08:25.059196 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 11:08:25.062738 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 11:08:25.065831 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1492 11:08:25.072354 0 11 4 | B1->B0 | 2e2e 3a3a | 1 0 | (0 0) (0 0)
1493 11:08:25.075586 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 11:08:25.079604 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 11:08:25.085600 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 11:08:25.088832 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 11:08:25.092283 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 11:08:25.098913 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 11:08:25.102275 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1500 11:08:25.105680 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1501 11:08:25.112404 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 11:08:25.115733 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:08:25.119003 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:08:25.122340 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:08:25.128926 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:08:25.132308 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:08:25.135443 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:08:25.142027 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:08:25.145453 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:08:25.148848 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:08:25.155488 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:08:25.158916 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:08:25.162169 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:08:25.168977 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:08:25.172397 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1516 11:08:25.175727 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1517 11:08:25.182518 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1518 11:08:25.182624 Total UI for P1: 0, mck2ui 16
1519 11:08:25.188806 best dqsien dly found for B0: ( 0, 14, 2)
1520 11:08:25.192360 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 11:08:25.195664 Total UI for P1: 0, mck2ui 16
1522 11:08:25.198807 best dqsien dly found for B1: ( 0, 14, 6)
1523 11:08:25.202314 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1524 11:08:25.205674 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1525 11:08:25.205756
1526 11:08:25.209012 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1527 11:08:25.212361 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1528 11:08:25.215914 [Gating] SW calibration Done
1529 11:08:25.215996 ==
1530 11:08:25.218927 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 11:08:25.222303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 11:08:25.222387 ==
1533 11:08:25.225923 RX Vref Scan: 0
1534 11:08:25.226010
1535 11:08:25.226075 RX Vref 0 -> 0, step: 1
1536 11:08:25.229059
1537 11:08:25.229140 RX Delay -130 -> 252, step: 16
1538 11:08:25.235697 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1539 11:08:25.239046 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1540 11:08:25.242387 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1541 11:08:25.245758 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1542 11:08:25.249393 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1543 11:08:25.252387 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1544 11:08:25.258963 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1545 11:08:25.262340 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1546 11:08:25.265826 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1547 11:08:25.269119 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1548 11:08:25.272280 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1549 11:08:25.279318 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1550 11:08:25.282701 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1551 11:08:25.285907 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1552 11:08:25.289469 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1553 11:08:25.295721 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1554 11:08:25.295803 ==
1555 11:08:25.299157 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 11:08:25.302518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 11:08:25.302601 ==
1558 11:08:25.302667 DQS Delay:
1559 11:08:25.305928 DQS0 = 0, DQS1 = 0
1560 11:08:25.306044 DQM Delay:
1561 11:08:25.309644 DQM0 = 86, DQM1 = 80
1562 11:08:25.309763 DQ Delay:
1563 11:08:25.312492 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1564 11:08:25.315870 DQ4 =77, DQ5 =93, DQ6 =101, DQ7 =85
1565 11:08:25.318985 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1566 11:08:25.322305 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1567 11:08:25.322387
1568 11:08:25.322451
1569 11:08:25.322511 ==
1570 11:08:25.325824 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 11:08:25.329417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 11:08:25.329500 ==
1573 11:08:25.329565
1574 11:08:25.329625
1575 11:08:25.332736 TX Vref Scan disable
1576 11:08:25.336114 == TX Byte 0 ==
1577 11:08:25.339543 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1578 11:08:25.342920 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1579 11:08:25.346162 == TX Byte 1 ==
1580 11:08:25.349580 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1581 11:08:25.352945 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1582 11:08:25.353028 ==
1583 11:08:25.355866 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 11:08:25.359111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 11:08:25.362663 ==
1586 11:08:25.373714 TX Vref=22, minBit 10, minWin=27, winSum=450
1587 11:08:25.376999 TX Vref=24, minBit 15, minWin=27, winSum=455
1588 11:08:25.380295 TX Vref=26, minBit 15, minWin=27, winSum=456
1589 11:08:25.383657 TX Vref=28, minBit 15, minWin=27, winSum=458
1590 11:08:25.387073 TX Vref=30, minBit 8, minWin=28, winSum=458
1591 11:08:25.393717 TX Vref=32, minBit 12, minWin=27, winSum=458
1592 11:08:25.397468 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
1593 11:08:25.397550
1594 11:08:25.401249 Final TX Range 1 Vref 30
1595 11:08:25.401332
1596 11:08:25.401397 ==
1597 11:08:25.404426 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 11:08:25.407773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 11:08:25.407903 ==
1600 11:08:25.407983
1601 11:08:25.408044
1602 11:08:25.411348 TX Vref Scan disable
1603 11:08:25.414574 == TX Byte 0 ==
1604 11:08:25.418116 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1605 11:08:25.421231 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1606 11:08:25.424708 == TX Byte 1 ==
1607 11:08:25.428040 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1608 11:08:25.431061 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1609 11:08:25.431143
1610 11:08:25.434742 [DATLAT]
1611 11:08:25.434824 Freq=800, CH1 RK0
1612 11:08:25.434889
1613 11:08:25.438234 DATLAT Default: 0xa
1614 11:08:25.438317 0, 0xFFFF, sum = 0
1615 11:08:25.441496 1, 0xFFFF, sum = 0
1616 11:08:25.441580 2, 0xFFFF, sum = 0
1617 11:08:25.444806 3, 0xFFFF, sum = 0
1618 11:08:25.444890 4, 0xFFFF, sum = 0
1619 11:08:25.448175 5, 0xFFFF, sum = 0
1620 11:08:25.448260 6, 0xFFFF, sum = 0
1621 11:08:25.451553 7, 0xFFFF, sum = 0
1622 11:08:25.451637 8, 0xFFFF, sum = 0
1623 11:08:25.455039 9, 0x0, sum = 1
1624 11:08:25.455122 10, 0x0, sum = 2
1625 11:08:25.458341 11, 0x0, sum = 3
1626 11:08:25.458424 12, 0x0, sum = 4
1627 11:08:25.461728 best_step = 10
1628 11:08:25.461810
1629 11:08:25.461875 ==
1630 11:08:25.464873 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 11:08:25.468250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 11:08:25.468333 ==
1633 11:08:25.468398 RX Vref Scan: 1
1634 11:08:25.468459
1635 11:08:25.471485 Set Vref Range= 32 -> 127
1636 11:08:25.471566
1637 11:08:25.474865 RX Vref 32 -> 127, step: 1
1638 11:08:25.474947
1639 11:08:25.478196 RX Delay -95 -> 252, step: 8
1640 11:08:25.478277
1641 11:08:25.481436 Set Vref, RX VrefLevel [Byte0]: 32
1642 11:08:25.484871 [Byte1]: 32
1643 11:08:25.484953
1644 11:08:25.488122 Set Vref, RX VrefLevel [Byte0]: 33
1645 11:08:25.491499 [Byte1]: 33
1646 11:08:25.491584
1647 11:08:25.494729 Set Vref, RX VrefLevel [Byte0]: 34
1648 11:08:25.498278 [Byte1]: 34
1649 11:08:25.501782
1650 11:08:25.501863 Set Vref, RX VrefLevel [Byte0]: 35
1651 11:08:25.505409 [Byte1]: 35
1652 11:08:25.509686
1653 11:08:25.509768 Set Vref, RX VrefLevel [Byte0]: 36
1654 11:08:25.512789 [Byte1]: 36
1655 11:08:25.517123
1656 11:08:25.517204 Set Vref, RX VrefLevel [Byte0]: 37
1657 11:08:25.520616 [Byte1]: 37
1658 11:08:25.524834
1659 11:08:25.524915 Set Vref, RX VrefLevel [Byte0]: 38
1660 11:08:25.528088 [Byte1]: 38
1661 11:08:25.532577
1662 11:08:25.532659 Set Vref, RX VrefLevel [Byte0]: 39
1663 11:08:25.535434 [Byte1]: 39
1664 11:08:25.539778
1665 11:08:25.539860 Set Vref, RX VrefLevel [Byte0]: 40
1666 11:08:25.543095 [Byte1]: 40
1667 11:08:25.547417
1668 11:08:25.547498 Set Vref, RX VrefLevel [Byte0]: 41
1669 11:08:25.550765 [Byte1]: 41
1670 11:08:25.555350
1671 11:08:25.555432 Set Vref, RX VrefLevel [Byte0]: 42
1672 11:08:25.558259 [Byte1]: 42
1673 11:08:25.562933
1674 11:08:25.563014 Set Vref, RX VrefLevel [Byte0]: 43
1675 11:08:25.566146 [Byte1]: 43
1676 11:08:25.570468
1677 11:08:25.570550 Set Vref, RX VrefLevel [Byte0]: 44
1678 11:08:25.573601 [Byte1]: 44
1679 11:08:25.577780
1680 11:08:25.577862 Set Vref, RX VrefLevel [Byte0]: 45
1681 11:08:25.581061 [Byte1]: 45
1682 11:08:25.585681
1683 11:08:25.585791 Set Vref, RX VrefLevel [Byte0]: 46
1684 11:08:25.588977 [Byte1]: 46
1685 11:08:25.593204
1686 11:08:25.593301 Set Vref, RX VrefLevel [Byte0]: 47
1687 11:08:25.596466 [Byte1]: 47
1688 11:08:25.600573
1689 11:08:25.600669 Set Vref, RX VrefLevel [Byte0]: 48
1690 11:08:25.604384 [Byte1]: 48
1691 11:08:25.608223
1692 11:08:25.608321 Set Vref, RX VrefLevel [Byte0]: 49
1693 11:08:25.611568 [Byte1]: 49
1694 11:08:25.616163
1695 11:08:25.616247 Set Vref, RX VrefLevel [Byte0]: 50
1696 11:08:25.619066 [Byte1]: 50
1697 11:08:25.623420
1698 11:08:25.623526 Set Vref, RX VrefLevel [Byte0]: 51
1699 11:08:25.626874 [Byte1]: 51
1700 11:08:25.631402
1701 11:08:25.631489 Set Vref, RX VrefLevel [Byte0]: 52
1702 11:08:25.634799 [Byte1]: 52
1703 11:08:25.638723
1704 11:08:25.638824 Set Vref, RX VrefLevel [Byte0]: 53
1705 11:08:25.641771 [Byte1]: 53
1706 11:08:25.646336
1707 11:08:25.646438 Set Vref, RX VrefLevel [Byte0]: 54
1708 11:08:25.649749 [Byte1]: 54
1709 11:08:25.654082
1710 11:08:25.654158 Set Vref, RX VrefLevel [Byte0]: 55
1711 11:08:25.657387 [Byte1]: 55
1712 11:08:25.661839
1713 11:08:25.661923 Set Vref, RX VrefLevel [Byte0]: 56
1714 11:08:25.664670 [Byte1]: 56
1715 11:08:25.669231
1716 11:08:25.669313 Set Vref, RX VrefLevel [Byte0]: 57
1717 11:08:25.672627 [Byte1]: 57
1718 11:08:25.676802
1719 11:08:25.676884 Set Vref, RX VrefLevel [Byte0]: 58
1720 11:08:25.679987 [Byte1]: 58
1721 11:08:25.684267
1722 11:08:25.684350 Set Vref, RX VrefLevel [Byte0]: 59
1723 11:08:25.687664 [Byte1]: 59
1724 11:08:25.691994
1725 11:08:25.692077 Set Vref, RX VrefLevel [Byte0]: 60
1726 11:08:25.695448 [Byte1]: 60
1727 11:08:25.699266
1728 11:08:25.699348 Set Vref, RX VrefLevel [Byte0]: 61
1729 11:08:25.706009 [Byte1]: 61
1730 11:08:25.706095
1731 11:08:25.709522 Set Vref, RX VrefLevel [Byte0]: 62
1732 11:08:25.712381 [Byte1]: 62
1733 11:08:25.712463
1734 11:08:25.715859 Set Vref, RX VrefLevel [Byte0]: 63
1735 11:08:25.719587 [Byte1]: 63
1736 11:08:25.719687
1737 11:08:25.722743 Set Vref, RX VrefLevel [Byte0]: 64
1738 11:08:25.725927 [Byte1]: 64
1739 11:08:25.729863
1740 11:08:25.729956 Set Vref, RX VrefLevel [Byte0]: 65
1741 11:08:25.733201 [Byte1]: 65
1742 11:08:25.737623
1743 11:08:25.737697 Set Vref, RX VrefLevel [Byte0]: 66
1744 11:08:25.740723 [Byte1]: 66
1745 11:08:25.745218
1746 11:08:25.745300 Set Vref, RX VrefLevel [Byte0]: 67
1747 11:08:25.748300 [Byte1]: 67
1748 11:08:25.752844
1749 11:08:25.752926 Set Vref, RX VrefLevel [Byte0]: 68
1750 11:08:25.755867 [Byte1]: 68
1751 11:08:25.760240
1752 11:08:25.760346 Set Vref, RX VrefLevel [Byte0]: 69
1753 11:08:25.763509 [Byte1]: 69
1754 11:08:25.767724
1755 11:08:25.767823 Set Vref, RX VrefLevel [Byte0]: 70
1756 11:08:25.770896 [Byte1]: 70
1757 11:08:25.775745
1758 11:08:25.775828 Set Vref, RX VrefLevel [Byte0]: 71
1759 11:08:25.779022 [Byte1]: 71
1760 11:08:25.783364
1761 11:08:25.783448 Set Vref, RX VrefLevel [Byte0]: 72
1762 11:08:25.786172 [Byte1]: 72
1763 11:08:25.790458
1764 11:08:25.790544 Set Vref, RX VrefLevel [Byte0]: 73
1765 11:08:25.793727 [Byte1]: 73
1766 11:08:25.798451
1767 11:08:25.798534 Set Vref, RX VrefLevel [Byte0]: 74
1768 11:08:25.801272 [Byte1]: 74
1769 11:08:25.805866
1770 11:08:25.805973 Set Vref, RX VrefLevel [Byte0]: 75
1771 11:08:25.809241 [Byte1]: 75
1772 11:08:25.813496
1773 11:08:25.813579 Set Vref, RX VrefLevel [Byte0]: 76
1774 11:08:25.816832 [Byte1]: 76
1775 11:08:25.821090
1776 11:08:25.821173 Set Vref, RX VrefLevel [Byte0]: 77
1777 11:08:25.824443 [Byte1]: 77
1778 11:08:25.828665
1779 11:08:25.828748 Final RX Vref Byte 0 = 52 to rank0
1780 11:08:25.832179 Final RX Vref Byte 1 = 63 to rank0
1781 11:08:25.835322 Final RX Vref Byte 0 = 52 to rank1
1782 11:08:25.838770 Final RX Vref Byte 1 = 63 to rank1==
1783 11:08:25.841800 Dram Type= 6, Freq= 0, CH_1, rank 0
1784 11:08:25.848732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1785 11:08:25.848817 ==
1786 11:08:25.848900 DQS Delay:
1787 11:08:25.848978 DQS0 = 0, DQS1 = 0
1788 11:08:25.851793 DQM Delay:
1789 11:08:25.851902 DQM0 = 92, DQM1 = 83
1790 11:08:25.855445 DQ Delay:
1791 11:08:25.858558 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1792 11:08:25.862082 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
1793 11:08:25.862166 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1794 11:08:25.868587 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1795 11:08:25.868670
1796 11:08:25.868753
1797 11:08:25.875624 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 398 ps
1798 11:08:25.878942 CH1 RK0: MR19=606, MR18=2E4C
1799 11:08:25.885584 CH1_RK0: MR19=0x606, MR18=0x2E4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1800 11:08:25.885669
1801 11:08:25.888886 ----->DramcWriteLeveling(PI) begin...
1802 11:08:25.888970 ==
1803 11:08:25.892250 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 11:08:25.895620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1805 11:08:25.895705 ==
1806 11:08:25.898615 Write leveling (Byte 0): 29 => 29
1807 11:08:25.901859 Write leveling (Byte 1): 30 => 30
1808 11:08:25.905232 DramcWriteLeveling(PI) end<-----
1809 11:08:25.905315
1810 11:08:25.905398 ==
1811 11:08:25.909014 Dram Type= 6, Freq= 0, CH_1, rank 1
1812 11:08:25.912509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1813 11:08:25.912592 ==
1814 11:08:25.915365 [Gating] SW mode calibration
1815 11:08:25.922148 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1816 11:08:25.929109 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1817 11:08:25.932558 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1818 11:08:25.935565 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1819 11:08:25.942437 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:08:25.945435 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:08:25.948851 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:08:25.955642 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:08:25.958878 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:08:25.962069 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:08:25.968829 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:08:25.972482 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:08:25.975488 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:08:25.978869 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 11:08:25.985491 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 11:08:25.988766 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 11:08:25.992124 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:08:25.998759 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:08:26.002136 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 11:08:26.005654 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1835 11:08:26.012186 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1836 11:08:26.015633 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 11:08:26.018857 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 11:08:26.025511 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 11:08:26.028786 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 11:08:26.032216 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 11:08:26.038977 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 11:08:26.042016 0 9 4 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
1843 11:08:26.045545 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 11:08:26.052029 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 11:08:26.055786 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 11:08:26.059058 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 11:08:26.065735 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 11:08:26.069250 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 11:08:26.072247 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
1850 11:08:26.075744 0 10 4 | B1->B0 | 2f2f 3131 | 0 0 | (0 0) (0 1)
1851 11:08:26.082223 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 11:08:26.085902 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 11:08:26.089199 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 11:08:26.095892 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 11:08:26.098755 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 11:08:26.102162 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 11:08:26.109025 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 11:08:26.112439 0 11 4 | B1->B0 | 3838 3636 | 1 0 | (0 0) (0 0)
1859 11:08:26.115775 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1860 11:08:26.122414 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 11:08:26.125650 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 11:08:26.128924 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 11:08:26.135525 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 11:08:26.138806 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 11:08:26.142385 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 11:08:26.149118 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1867 11:08:26.152289 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1868 11:08:26.155819 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 11:08:26.158991 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 11:08:26.165722 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 11:08:26.169110 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 11:08:26.172262 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 11:08:26.178980 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 11:08:26.182474 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 11:08:26.186012 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 11:08:26.192286 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 11:08:26.195924 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 11:08:26.199257 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 11:08:26.206004 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 11:08:26.209092 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 11:08:26.212438 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 11:08:26.219107 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1883 11:08:26.219215 Total UI for P1: 0, mck2ui 16
1884 11:08:26.222657 best dqsien dly found for B1: ( 0, 14, 2)
1885 11:08:26.229148 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1886 11:08:26.232777 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 11:08:26.235851 Total UI for P1: 0, mck2ui 16
1888 11:08:26.239213 best dqsien dly found for B0: ( 0, 14, 6)
1889 11:08:26.242606 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1890 11:08:26.245899 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1891 11:08:26.246049
1892 11:08:26.249255 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1893 11:08:26.252500 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1894 11:08:26.256366 [Gating] SW calibration Done
1895 11:08:26.256468 ==
1896 11:08:26.259352 Dram Type= 6, Freq= 0, CH_1, rank 1
1897 11:08:26.262683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1898 11:08:26.266057 ==
1899 11:08:26.266139 RX Vref Scan: 0
1900 11:08:26.266203
1901 11:08:26.269435 RX Vref 0 -> 0, step: 1
1902 11:08:26.269517
1903 11:08:26.272907 RX Delay -130 -> 252, step: 16
1904 11:08:26.276157 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1905 11:08:26.279272 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1906 11:08:26.282649 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1907 11:08:26.286284 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1908 11:08:26.292725 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1909 11:08:26.296176 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1910 11:08:26.299582 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1911 11:08:26.302713 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1912 11:08:26.305993 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1913 11:08:26.312987 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1914 11:08:26.316181 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1915 11:08:26.319417 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1916 11:08:26.322740 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1917 11:08:26.325995 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1918 11:08:26.332718 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1919 11:08:26.335937 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1920 11:08:26.336019 ==
1921 11:08:26.339709 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 11:08:26.342626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 11:08:26.342707 ==
1924 11:08:26.346086 DQS Delay:
1925 11:08:26.346167 DQS0 = 0, DQS1 = 0
1926 11:08:26.346232 DQM Delay:
1927 11:08:26.349385 DQM0 = 88, DQM1 = 82
1928 11:08:26.349466 DQ Delay:
1929 11:08:26.352723 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1930 11:08:26.356080 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1931 11:08:26.359372 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1932 11:08:26.362966 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1933 11:08:26.363047
1934 11:08:26.363111
1935 11:08:26.363170 ==
1936 11:08:26.365974 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 11:08:26.369536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 11:08:26.372469 ==
1939 11:08:26.372550
1940 11:08:26.372614
1941 11:08:26.372674 TX Vref Scan disable
1942 11:08:26.376082 == TX Byte 0 ==
1943 11:08:26.379169 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1944 11:08:26.382685 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1945 11:08:26.385821 == TX Byte 1 ==
1946 11:08:26.389455 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1947 11:08:26.392487 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1948 11:08:26.396084 ==
1949 11:08:26.399435 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 11:08:26.402705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 11:08:26.402819 ==
1952 11:08:26.415031 TX Vref=22, minBit 8, minWin=27, winSum=449
1953 11:08:26.417907 TX Vref=24, minBit 13, minWin=27, winSum=455
1954 11:08:26.421308 TX Vref=26, minBit 13, minWin=27, winSum=454
1955 11:08:26.425074 TX Vref=28, minBit 8, minWin=28, winSum=462
1956 11:08:26.428220 TX Vref=30, minBit 8, minWin=28, winSum=459
1957 11:08:26.434859 TX Vref=32, minBit 8, minWin=28, winSum=458
1958 11:08:26.438231 [TxChooseVref] Worse bit 8, Min win 28, Win sum 462, Final Vref 28
1959 11:08:26.438330
1960 11:08:26.441655 Final TX Range 1 Vref 28
1961 11:08:26.441765
1962 11:08:26.441858 ==
1963 11:08:26.445087 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 11:08:26.448282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 11:08:26.448467 ==
1966 11:08:26.451301
1967 11:08:26.451382
1968 11:08:26.451446 TX Vref Scan disable
1969 11:08:26.455015 == TX Byte 0 ==
1970 11:08:26.458470 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1971 11:08:26.461641 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1972 11:08:26.464869 == TX Byte 1 ==
1973 11:08:26.468153 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1974 11:08:26.471725 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1975 11:08:26.471807
1976 11:08:26.474992 [DATLAT]
1977 11:08:26.475073 Freq=800, CH1 RK1
1978 11:08:26.475138
1979 11:08:26.478286 DATLAT Default: 0xa
1980 11:08:26.478368 0, 0xFFFF, sum = 0
1981 11:08:26.481740 1, 0xFFFF, sum = 0
1982 11:08:26.481852 2, 0xFFFF, sum = 0
1983 11:08:26.485136 3, 0xFFFF, sum = 0
1984 11:08:26.485220 4, 0xFFFF, sum = 0
1985 11:08:26.488539 5, 0xFFFF, sum = 0
1986 11:08:26.488622 6, 0xFFFF, sum = 0
1987 11:08:26.492045 7, 0xFFFF, sum = 0
1988 11:08:26.492128 8, 0xFFFF, sum = 0
1989 11:08:26.495109 9, 0x0, sum = 1
1990 11:08:26.495192 10, 0x0, sum = 2
1991 11:08:26.498145 11, 0x0, sum = 3
1992 11:08:26.498229 12, 0x0, sum = 4
1993 11:08:26.501479 best_step = 10
1994 11:08:26.501560
1995 11:08:26.501625 ==
1996 11:08:26.504865 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 11:08:26.508487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 11:08:26.508570 ==
1999 11:08:26.511773 RX Vref Scan: 0
2000 11:08:26.511854
2001 11:08:26.511918 RX Vref 0 -> 0, step: 1
2002 11:08:26.511978
2003 11:08:26.515136 RX Delay -95 -> 252, step: 8
2004 11:08:26.521843 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2005 11:08:26.525285 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2006 11:08:26.528401 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2007 11:08:26.531718 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2008 11:08:26.535161 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2009 11:08:26.541523 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2010 11:08:26.544864 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2011 11:08:26.548217 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2012 11:08:26.551645 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2013 11:08:26.554978 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2014 11:08:26.558799 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2015 11:08:26.564975 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2016 11:08:26.568316 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2017 11:08:26.571576 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2018 11:08:26.575175 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2019 11:08:26.581943 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2020 11:08:26.582026 ==
2021 11:08:26.584982 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 11:08:26.588577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 11:08:26.588659 ==
2024 11:08:26.588725 DQS Delay:
2025 11:08:26.592100 DQS0 = 0, DQS1 = 0
2026 11:08:26.592182 DQM Delay:
2027 11:08:26.595254 DQM0 = 91, DQM1 = 83
2028 11:08:26.595336 DQ Delay:
2029 11:08:26.598527 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2030 11:08:26.601982 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2031 11:08:26.605123 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2032 11:08:26.608269 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2033 11:08:26.608352
2034 11:08:26.608417
2035 11:08:26.615199 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2036 11:08:26.618502 CH1 RK1: MR19=606, MR18=3B11
2037 11:08:26.625277 CH1_RK1: MR19=0x606, MR18=0x3B11, DQSOSC=394, MR23=63, INC=95, DEC=63
2038 11:08:26.628442 [RxdqsGatingPostProcess] freq 800
2039 11:08:26.635167 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2040 11:08:26.635249 Pre-setting of DQS Precalculation
2041 11:08:26.641746 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2042 11:08:26.648492 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2043 11:08:26.655118 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2044 11:08:26.655200
2045 11:08:26.655266
2046 11:08:26.658502 [Calibration Summary] 1600 Mbps
2047 11:08:26.661723 CH 0, Rank 0
2048 11:08:26.661804 SW Impedance : PASS
2049 11:08:26.664951 DUTY Scan : NO K
2050 11:08:26.668194 ZQ Calibration : PASS
2051 11:08:26.668277 Jitter Meter : NO K
2052 11:08:26.671545 CBT Training : PASS
2053 11:08:26.671627 Write leveling : PASS
2054 11:08:26.674994 RX DQS gating : PASS
2055 11:08:26.678333 RX DQ/DQS(RDDQC) : PASS
2056 11:08:26.678415 TX DQ/DQS : PASS
2057 11:08:26.681596 RX DATLAT : PASS
2058 11:08:26.684861 RX DQ/DQS(Engine): PASS
2059 11:08:26.684943 TX OE : NO K
2060 11:08:26.688440 All Pass.
2061 11:08:26.688521
2062 11:08:26.688586 CH 0, Rank 1
2063 11:08:26.691362 SW Impedance : PASS
2064 11:08:26.691444 DUTY Scan : NO K
2065 11:08:26.694981 ZQ Calibration : PASS
2066 11:08:26.697978 Jitter Meter : NO K
2067 11:08:26.698075 CBT Training : PASS
2068 11:08:26.701580 Write leveling : PASS
2069 11:08:26.705114 RX DQS gating : PASS
2070 11:08:26.705196 RX DQ/DQS(RDDQC) : PASS
2071 11:08:26.708223 TX DQ/DQS : PASS
2072 11:08:26.711654 RX DATLAT : PASS
2073 11:08:26.711748 RX DQ/DQS(Engine): PASS
2074 11:08:26.714845 TX OE : NO K
2075 11:08:26.714925 All Pass.
2076 11:08:26.714994
2077 11:08:26.718192 CH 1, Rank 0
2078 11:08:26.718263 SW Impedance : PASS
2079 11:08:26.721721 DUTY Scan : NO K
2080 11:08:26.721827 ZQ Calibration : PASS
2081 11:08:26.725057 Jitter Meter : NO K
2082 11:08:26.728451 CBT Training : PASS
2083 11:08:26.728549 Write leveling : PASS
2084 11:08:26.731722 RX DQS gating : PASS
2085 11:08:26.735036 RX DQ/DQS(RDDQC) : PASS
2086 11:08:26.735140 TX DQ/DQS : PASS
2087 11:08:26.738381 RX DATLAT : PASS
2088 11:08:26.741653 RX DQ/DQS(Engine): PASS
2089 11:08:26.741752 TX OE : NO K
2090 11:08:26.745036 All Pass.
2091 11:08:26.745122
2092 11:08:26.745188 CH 1, Rank 1
2093 11:08:26.748345 SW Impedance : PASS
2094 11:08:26.748427 DUTY Scan : NO K
2095 11:08:26.751503 ZQ Calibration : PASS
2096 11:08:26.754921 Jitter Meter : NO K
2097 11:08:26.755004 CBT Training : PASS
2098 11:08:26.758246 Write leveling : PASS
2099 11:08:26.758329 RX DQS gating : PASS
2100 11:08:26.761881 RX DQ/DQS(RDDQC) : PASS
2101 11:08:26.765172 TX DQ/DQS : PASS
2102 11:08:26.765255 RX DATLAT : PASS
2103 11:08:26.768503 RX DQ/DQS(Engine): PASS
2104 11:08:26.771715 TX OE : NO K
2105 11:08:26.771797 All Pass.
2106 11:08:26.771864
2107 11:08:26.774894 DramC Write-DBI off
2108 11:08:26.774977 PER_BANK_REFRESH: Hybrid Mode
2109 11:08:26.778223 TX_TRACKING: ON
2110 11:08:26.781906 [GetDramInforAfterCalByMRR] Vendor 6.
2111 11:08:26.785073 [GetDramInforAfterCalByMRR] Revision 606.
2112 11:08:26.788546 [GetDramInforAfterCalByMRR] Revision 2 0.
2113 11:08:26.788624 MR0 0x3b3b
2114 11:08:26.791793 MR8 0x5151
2115 11:08:26.794796 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 11:08:26.794874
2117 11:08:26.794938 MR0 0x3b3b
2118 11:08:26.795003 MR8 0x5151
2119 11:08:26.801653 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 11:08:26.801769
2121 11:08:26.808209 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2122 11:08:26.811835 [FAST_K] Save calibration result to emmc
2123 11:08:26.814967 [FAST_K] Save calibration result to emmc
2124 11:08:26.818511 dram_init: config_dvfs: 1
2125 11:08:26.821687 dramc_set_vcore_voltage set vcore to 662500
2126 11:08:26.825078 Read voltage for 1200, 2
2127 11:08:26.825164 Vio18 = 0
2128 11:08:26.828247 Vcore = 662500
2129 11:08:26.828328 Vdram = 0
2130 11:08:26.828394 Vddq = 0
2131 11:08:26.828454 Vmddr = 0
2132 11:08:26.835397 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2133 11:08:26.841903 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2134 11:08:26.842026 MEM_TYPE=3, freq_sel=15
2135 11:08:26.845285 sv_algorithm_assistance_LP4_1600
2136 11:08:26.848561 ============ PULL DRAM RESETB DOWN ============
2137 11:08:26.855103 ========== PULL DRAM RESETB DOWN end =========
2138 11:08:26.858461 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2139 11:08:26.861664 ===================================
2140 11:08:26.864952 LPDDR4 DRAM CONFIGURATION
2141 11:08:26.868241 ===================================
2142 11:08:26.868325 EX_ROW_EN[0] = 0x0
2143 11:08:26.871532 EX_ROW_EN[1] = 0x0
2144 11:08:26.871626 LP4Y_EN = 0x0
2145 11:08:26.875207 WORK_FSP = 0x0
2146 11:08:26.875288 WL = 0x4
2147 11:08:26.878588 RL = 0x4
2148 11:08:26.881851 BL = 0x2
2149 11:08:26.881981 RPST = 0x0
2150 11:08:26.885258 RD_PRE = 0x0
2151 11:08:26.885341 WR_PRE = 0x1
2152 11:08:26.888415 WR_PST = 0x0
2153 11:08:26.888497 DBI_WR = 0x0
2154 11:08:26.891760 DBI_RD = 0x0
2155 11:08:26.891842 OTF = 0x1
2156 11:08:26.894853 ===================================
2157 11:08:26.898374 ===================================
2158 11:08:26.901808 ANA top config
2159 11:08:26.904884 ===================================
2160 11:08:26.904966 DLL_ASYNC_EN = 0
2161 11:08:26.908226 ALL_SLAVE_EN = 0
2162 11:08:26.911491 NEW_RANK_MODE = 1
2163 11:08:26.914915 DLL_IDLE_MODE = 1
2164 11:08:26.914996 LP45_APHY_COMB_EN = 1
2165 11:08:26.918501 TX_ODT_DIS = 1
2166 11:08:26.921522 NEW_8X_MODE = 1
2167 11:08:26.924978 ===================================
2168 11:08:26.928472 ===================================
2169 11:08:26.931495 data_rate = 2400
2170 11:08:26.934795 CKR = 1
2171 11:08:26.934877 DQ_P2S_RATIO = 8
2172 11:08:26.938445 ===================================
2173 11:08:26.941730 CA_P2S_RATIO = 8
2174 11:08:26.944986 DQ_CA_OPEN = 0
2175 11:08:26.948472 DQ_SEMI_OPEN = 0
2176 11:08:26.951617 CA_SEMI_OPEN = 0
2177 11:08:26.954948 CA_FULL_RATE = 0
2178 11:08:26.955030 DQ_CKDIV4_EN = 0
2179 11:08:26.958306 CA_CKDIV4_EN = 0
2180 11:08:26.961666 CA_PREDIV_EN = 0
2181 11:08:26.964917 PH8_DLY = 17
2182 11:08:26.968340 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2183 11:08:26.971681 DQ_AAMCK_DIV = 4
2184 11:08:26.971775 CA_AAMCK_DIV = 4
2185 11:08:26.974985 CA_ADMCK_DIV = 4
2186 11:08:26.978708 DQ_TRACK_CA_EN = 0
2187 11:08:26.981811 CA_PICK = 1200
2188 11:08:26.985237 CA_MCKIO = 1200
2189 11:08:26.988623 MCKIO_SEMI = 0
2190 11:08:26.991874 PLL_FREQ = 2366
2191 11:08:26.991957 DQ_UI_PI_RATIO = 32
2192 11:08:26.995180 CA_UI_PI_RATIO = 0
2193 11:08:26.998770 ===================================
2194 11:08:27.001994 ===================================
2195 11:08:27.005282 memory_type:LPDDR4
2196 11:08:27.008287 GP_NUM : 10
2197 11:08:27.008369 SRAM_EN : 1
2198 11:08:27.011823 MD32_EN : 0
2199 11:08:27.015019 ===================================
2200 11:08:27.015102 [ANA_INIT] >>>>>>>>>>>>>>
2201 11:08:27.018670 <<<<<< [CONFIGURE PHASE]: ANA_TX
2202 11:08:27.021691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2203 11:08:27.025229 ===================================
2204 11:08:27.028343 data_rate = 2400,PCW = 0X5b00
2205 11:08:27.031793 ===================================
2206 11:08:27.035338 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2207 11:08:27.042088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 11:08:27.045435 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2209 11:08:27.051691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2210 11:08:27.055069 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2211 11:08:27.058633 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2212 11:08:27.061853 [ANA_INIT] flow start
2213 11:08:27.061936 [ANA_INIT] PLL >>>>>>>>
2214 11:08:27.065209 [ANA_INIT] PLL <<<<<<<<
2215 11:08:27.068710 [ANA_INIT] MIDPI >>>>>>>>
2216 11:08:27.068792 [ANA_INIT] MIDPI <<<<<<<<
2217 11:08:27.071663 [ANA_INIT] DLL >>>>>>>>
2218 11:08:27.075041 [ANA_INIT] DLL <<<<<<<<
2219 11:08:27.075124 [ANA_INIT] flow end
2220 11:08:27.078402 ============ LP4 DIFF to SE enter ============
2221 11:08:27.085078 ============ LP4 DIFF to SE exit ============
2222 11:08:27.085161 [ANA_INIT] <<<<<<<<<<<<<
2223 11:08:27.088457 [Flow] Enable top DCM control >>>>>
2224 11:08:27.091750 [Flow] Enable top DCM control <<<<<
2225 11:08:27.095312 Enable DLL master slave shuffle
2226 11:08:27.101897 ==============================================================
2227 11:08:27.102027 Gating Mode config
2228 11:08:27.108673 ==============================================================
2229 11:08:27.111789 Config description:
2230 11:08:27.122117 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2231 11:08:27.128429 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2232 11:08:27.131568 SELPH_MODE 0: By rank 1: By Phase
2233 11:08:27.138273 ==============================================================
2234 11:08:27.141763 GAT_TRACK_EN = 1
2235 11:08:27.141845 RX_GATING_MODE = 2
2236 11:08:27.145169 RX_GATING_TRACK_MODE = 2
2237 11:08:27.148429 SELPH_MODE = 1
2238 11:08:27.151684 PICG_EARLY_EN = 1
2239 11:08:27.155020 VALID_LAT_VALUE = 1
2240 11:08:27.162119 ==============================================================
2241 11:08:27.165342 Enter into Gating configuration >>>>
2242 11:08:27.168621 Exit from Gating configuration <<<<
2243 11:08:27.171759 Enter into DVFS_PRE_config >>>>>
2244 11:08:27.182236 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2245 11:08:27.185454 Exit from DVFS_PRE_config <<<<<
2246 11:08:27.188762 Enter into PICG configuration >>>>
2247 11:08:27.192126 Exit from PICG configuration <<<<
2248 11:08:27.195156 [RX_INPUT] configuration >>>>>
2249 11:08:27.195237 [RX_INPUT] configuration <<<<<
2250 11:08:27.201899 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2251 11:08:27.208711 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2252 11:08:27.211990 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 11:08:27.218725 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 11:08:27.225126 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2255 11:08:27.231814 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2256 11:08:27.235188 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2257 11:08:27.238723 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2258 11:08:27.245279 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2259 11:08:27.248723 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2260 11:08:27.252187 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2261 11:08:27.255353 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2262 11:08:27.258696 ===================================
2263 11:08:27.262056 LPDDR4 DRAM CONFIGURATION
2264 11:08:27.265290 ===================================
2265 11:08:27.268682 EX_ROW_EN[0] = 0x0
2266 11:08:27.268765 EX_ROW_EN[1] = 0x0
2267 11:08:27.272166 LP4Y_EN = 0x0
2268 11:08:27.272249 WORK_FSP = 0x0
2269 11:08:27.275649 WL = 0x4
2270 11:08:27.275732 RL = 0x4
2271 11:08:27.278894 BL = 0x2
2272 11:08:27.278977 RPST = 0x0
2273 11:08:27.282164 RD_PRE = 0x0
2274 11:08:27.282264 WR_PRE = 0x1
2275 11:08:27.285317 WR_PST = 0x0
2276 11:08:27.288566 DBI_WR = 0x0
2277 11:08:27.288649 DBI_RD = 0x0
2278 11:08:27.291963 OTF = 0x1
2279 11:08:27.295352 ===================================
2280 11:08:27.298671 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2281 11:08:27.301924 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2282 11:08:27.305270 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2283 11:08:27.308621 ===================================
2284 11:08:27.312061 LPDDR4 DRAM CONFIGURATION
2285 11:08:27.315620 ===================================
2286 11:08:27.318850 EX_ROW_EN[0] = 0x10
2287 11:08:27.318933 EX_ROW_EN[1] = 0x0
2288 11:08:27.322088 LP4Y_EN = 0x0
2289 11:08:27.322197 WORK_FSP = 0x0
2290 11:08:27.325620 WL = 0x4
2291 11:08:27.325721 RL = 0x4
2292 11:08:27.328714 BL = 0x2
2293 11:08:27.328813 RPST = 0x0
2294 11:08:27.332195 RD_PRE = 0x0
2295 11:08:27.332296 WR_PRE = 0x1
2296 11:08:27.335394 WR_PST = 0x0
2297 11:08:27.335488 DBI_WR = 0x0
2298 11:08:27.338774 DBI_RD = 0x0
2299 11:08:27.338871 OTF = 0x1
2300 11:08:27.342005 ===================================
2301 11:08:27.348646 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2302 11:08:27.348752 ==
2303 11:08:27.352107 Dram Type= 6, Freq= 0, CH_0, rank 0
2304 11:08:27.358620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2305 11:08:27.358694 ==
2306 11:08:27.358757 [Duty_Offset_Calibration]
2307 11:08:27.361902 B0:2 B1:0 CA:1
2308 11:08:27.362021
2309 11:08:27.365137 [DutyScan_Calibration_Flow] k_type=0
2310 11:08:27.373078
2311 11:08:27.373154 ==CLK 0==
2312 11:08:27.376438 Final CLK duty delay cell = -4
2313 11:08:27.380105 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2314 11:08:27.383326 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2315 11:08:27.386735 [-4] AVG Duty = 4953%(X100)
2316 11:08:27.386833
2317 11:08:27.390002 CH0 CLK Duty spec in!! Max-Min= 156%
2318 11:08:27.393201 [DutyScan_Calibration_Flow] ====Done====
2319 11:08:27.393297
2320 11:08:27.396513 [DutyScan_Calibration_Flow] k_type=1
2321 11:08:27.411899
2322 11:08:27.412007 ==DQS 0 ==
2323 11:08:27.415606 Final DQS duty delay cell = 0
2324 11:08:27.418990 [0] MAX Duty = 5187%(X100), DQS PI = 30
2325 11:08:27.422216 [0] MIN Duty = 4938%(X100), DQS PI = 0
2326 11:08:27.422317 [0] AVG Duty = 5062%(X100)
2327 11:08:27.425325
2328 11:08:27.425424 ==DQS 1 ==
2329 11:08:27.428753 Final DQS duty delay cell = -4
2330 11:08:27.432343 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2331 11:08:27.435454 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2332 11:08:27.438869 [-4] AVG Duty = 5031%(X100)
2333 11:08:27.438973
2334 11:08:27.442091 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2335 11:08:27.442192
2336 11:08:27.445416 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2337 11:08:27.448905 [DutyScan_Calibration_Flow] ====Done====
2338 11:08:27.448991
2339 11:08:27.451925 [DutyScan_Calibration_Flow] k_type=3
2340 11:08:27.469017
2341 11:08:27.469125 ==DQM 0 ==
2342 11:08:27.472259 Final DQM duty delay cell = 0
2343 11:08:27.475489 [0] MAX Duty = 5062%(X100), DQS PI = 24
2344 11:08:27.479250 [0] MIN Duty = 4813%(X100), DQS PI = 2
2345 11:08:27.479355 [0] AVG Duty = 4937%(X100)
2346 11:08:27.482499
2347 11:08:27.482600 ==DQM 1 ==
2348 11:08:27.485642 Final DQM duty delay cell = 0
2349 11:08:27.488991 [0] MAX Duty = 5187%(X100), DQS PI = 48
2350 11:08:27.492207 [0] MIN Duty = 5000%(X100), DQS PI = 12
2351 11:08:27.495431 [0] AVG Duty = 5093%(X100)
2352 11:08:27.495530
2353 11:08:27.498772 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2354 11:08:27.498867
2355 11:08:27.502099 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2356 11:08:27.505334 [DutyScan_Calibration_Flow] ====Done====
2357 11:08:27.505431
2358 11:08:27.508653 [DutyScan_Calibration_Flow] k_type=2
2359 11:08:27.525798
2360 11:08:27.525899 ==DQ 0 ==
2361 11:08:27.528924 Final DQ duty delay cell = -4
2362 11:08:27.532520 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2363 11:08:27.535381 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2364 11:08:27.538725 [-4] AVG Duty = 4968%(X100)
2365 11:08:27.538827
2366 11:08:27.538919 ==DQ 1 ==
2367 11:08:27.542231 Final DQ duty delay cell = 4
2368 11:08:27.545703 [4] MAX Duty = 5093%(X100), DQS PI = 4
2369 11:08:27.549007 [4] MIN Duty = 5031%(X100), DQS PI = 0
2370 11:08:27.549087 [4] AVG Duty = 5062%(X100)
2371 11:08:27.549151
2372 11:08:27.552088 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2373 11:08:27.555624
2374 11:08:27.558932 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2375 11:08:27.562398 [DutyScan_Calibration_Flow] ====Done====
2376 11:08:27.562488 ==
2377 11:08:27.565559 Dram Type= 6, Freq= 0, CH_1, rank 0
2378 11:08:27.569128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2379 11:08:27.569210 ==
2380 11:08:27.572345 [Duty_Offset_Calibration]
2381 11:08:27.572425 B0:0 B1:-1 CA:2
2382 11:08:27.572489
2383 11:08:27.575608 [DutyScan_Calibration_Flow] k_type=0
2384 11:08:27.585895
2385 11:08:27.586015 ==CLK 0==
2386 11:08:27.589193 Final CLK duty delay cell = 0
2387 11:08:27.592537 [0] MAX Duty = 5156%(X100), DQS PI = 14
2388 11:08:27.595528 [0] MIN Duty = 4938%(X100), DQS PI = 44
2389 11:08:27.595611 [0] AVG Duty = 5047%(X100)
2390 11:08:27.598858
2391 11:08:27.598939 CH1 CLK Duty spec in!! Max-Min= 218%
2392 11:08:27.605506 [DutyScan_Calibration_Flow] ====Done====
2393 11:08:27.605587
2394 11:08:27.608848 [DutyScan_Calibration_Flow] k_type=1
2395 11:08:27.625169
2396 11:08:27.625250 ==DQS 0 ==
2397 11:08:27.628480 Final DQS duty delay cell = 0
2398 11:08:27.631705 [0] MAX Duty = 5093%(X100), DQS PI = 26
2399 11:08:27.635064 [0] MIN Duty = 4969%(X100), DQS PI = 0
2400 11:08:27.635146 [0] AVG Duty = 5031%(X100)
2401 11:08:27.638355
2402 11:08:27.638436 ==DQS 1 ==
2403 11:08:27.641653 Final DQS duty delay cell = 0
2404 11:08:27.645031 [0] MAX Duty = 5156%(X100), DQS PI = 0
2405 11:08:27.648530 [0] MIN Duty = 4844%(X100), DQS PI = 36
2406 11:08:27.648612 [0] AVG Duty = 5000%(X100)
2407 11:08:27.648680
2408 11:08:27.654842 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2409 11:08:27.654924
2410 11:08:27.658334 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2411 11:08:27.661767 [DutyScan_Calibration_Flow] ====Done====
2412 11:08:27.661849
2413 11:08:27.665024 [DutyScan_Calibration_Flow] k_type=3
2414 11:08:27.681337
2415 11:08:27.681423 ==DQM 0 ==
2416 11:08:27.685021 Final DQM duty delay cell = 4
2417 11:08:27.688322 [4] MAX Duty = 5093%(X100), DQS PI = 20
2418 11:08:27.691720 [4] MIN Duty = 4938%(X100), DQS PI = 48
2419 11:08:27.691803 [4] AVG Duty = 5015%(X100)
2420 11:08:27.694644
2421 11:08:27.694725 ==DQM 1 ==
2422 11:08:27.697989 Final DQM duty delay cell = -4
2423 11:08:27.701268 [-4] MAX Duty = 5000%(X100), DQS PI = 60
2424 11:08:27.704663 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2425 11:08:27.708037 [-4] AVG Duty = 4875%(X100)
2426 11:08:27.708120
2427 11:08:27.711266 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2428 11:08:27.711348
2429 11:08:27.714995 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2430 11:08:27.718414 [DutyScan_Calibration_Flow] ====Done====
2431 11:08:27.718496
2432 11:08:27.721483 [DutyScan_Calibration_Flow] k_type=2
2433 11:08:27.738364
2434 11:08:27.738445 ==DQ 0 ==
2435 11:08:27.741695 Final DQ duty delay cell = 0
2436 11:08:27.744969 [0] MAX Duty = 5062%(X100), DQS PI = 20
2437 11:08:27.748530 [0] MIN Duty = 4938%(X100), DQS PI = 0
2438 11:08:27.748637 [0] AVG Duty = 5000%(X100)
2439 11:08:27.748738
2440 11:08:27.751704 ==DQ 1 ==
2441 11:08:27.755183 Final DQ duty delay cell = 0
2442 11:08:27.758616 [0] MAX Duty = 5031%(X100), DQS PI = 2
2443 11:08:27.761639 [0] MIN Duty = 4813%(X100), DQS PI = 36
2444 11:08:27.761744 [0] AVG Duty = 4922%(X100)
2445 11:08:27.761833
2446 11:08:27.765249 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2447 11:08:27.765349
2448 11:08:27.768622 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2449 11:08:27.775197 [DutyScan_Calibration_Flow] ====Done====
2450 11:08:27.778252 nWR fixed to 30
2451 11:08:27.778352 [ModeRegInit_LP4] CH0 RK0
2452 11:08:27.781680 [ModeRegInit_LP4] CH0 RK1
2453 11:08:27.785401 [ModeRegInit_LP4] CH1 RK0
2454 11:08:27.785504 [ModeRegInit_LP4] CH1 RK1
2455 11:08:27.788572 match AC timing 7
2456 11:08:27.791906 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2457 11:08:27.795166 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2458 11:08:27.801847 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2459 11:08:27.805402 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2460 11:08:27.811915 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2461 11:08:27.812015 ==
2462 11:08:27.815198 Dram Type= 6, Freq= 0, CH_0, rank 0
2463 11:08:27.818484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2464 11:08:27.818565 ==
2465 11:08:27.825294 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2466 11:08:27.828610 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2467 11:08:27.838244 [CA 0] Center 38 (8~69) winsize 62
2468 11:08:27.841629 [CA 1] Center 38 (8~69) winsize 62
2469 11:08:27.844669 [CA 2] Center 35 (5~66) winsize 62
2470 11:08:27.848365 [CA 3] Center 35 (4~66) winsize 63
2471 11:08:27.851299 [CA 4] Center 34 (4~65) winsize 62
2472 11:08:27.854825 [CA 5] Center 33 (3~63) winsize 61
2473 11:08:27.854927
2474 11:08:27.857981 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2475 11:08:27.858076
2476 11:08:27.861464 [CATrainingPosCal] consider 1 rank data
2477 11:08:27.865004 u2DelayCellTimex100 = 270/100 ps
2478 11:08:27.868199 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2479 11:08:27.871612 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2480 11:08:27.875040 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2481 11:08:27.881623 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2482 11:08:27.884793 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2483 11:08:27.888215 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2484 11:08:27.888298
2485 11:08:27.891664 CA PerBit enable=1, Macro0, CA PI delay=33
2486 11:08:27.891747
2487 11:08:27.894913 [CBTSetCACLKResult] CA Dly = 33
2488 11:08:27.894996 CS Dly: 6 (0~37)
2489 11:08:27.895062 ==
2490 11:08:27.898331 Dram Type= 6, Freq= 0, CH_0, rank 1
2491 11:08:27.905033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2492 11:08:27.905117 ==
2493 11:08:27.908384 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2494 11:08:27.915153 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2495 11:08:27.924052 [CA 0] Center 39 (8~70) winsize 63
2496 11:08:27.927336 [CA 1] Center 38 (8~69) winsize 62
2497 11:08:27.930742 [CA 2] Center 35 (5~66) winsize 62
2498 11:08:27.934088 [CA 3] Center 35 (5~66) winsize 62
2499 11:08:27.937261 [CA 4] Center 35 (4~66) winsize 63
2500 11:08:27.940481 [CA 5] Center 34 (4~64) winsize 61
2501 11:08:27.940564
2502 11:08:27.943754 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2503 11:08:27.943837
2504 11:08:27.947101 [CATrainingPosCal] consider 2 rank data
2505 11:08:27.950349 u2DelayCellTimex100 = 270/100 ps
2506 11:08:27.953667 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2507 11:08:27.957007 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2508 11:08:27.963617 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2509 11:08:27.967153 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2510 11:08:27.970871 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2511 11:08:27.974030 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2512 11:08:27.974113
2513 11:08:27.977111 CA PerBit enable=1, Macro0, CA PI delay=33
2514 11:08:27.977194
2515 11:08:27.980790 [CBTSetCACLKResult] CA Dly = 33
2516 11:08:27.980874 CS Dly: 7 (0~39)
2517 11:08:27.980944
2518 11:08:27.983731 ----->DramcWriteLeveling(PI) begin...
2519 11:08:27.987100 ==
2520 11:08:27.987177 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 11:08:27.994095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 11:08:27.994184 ==
2523 11:08:27.997528 Write leveling (Byte 0): 35 => 35
2524 11:08:28.000789 Write leveling (Byte 1): 31 => 31
2525 11:08:28.004171 DramcWriteLeveling(PI) end<-----
2526 11:08:28.004252
2527 11:08:28.004316 ==
2528 11:08:28.007458 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 11:08:28.010784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 11:08:28.010866 ==
2531 11:08:28.013977 [Gating] SW mode calibration
2532 11:08:28.020771 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2533 11:08:28.023804 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2534 11:08:28.030430 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2535 11:08:28.033691 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2536 11:08:28.037338 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 11:08:28.043779 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 11:08:28.047314 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 11:08:28.050688 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 11:08:28.057219 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2541 11:08:28.060454 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2542 11:08:28.063838 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2543 11:08:28.070470 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2544 11:08:28.073811 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 11:08:28.077152 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 11:08:28.083869 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 11:08:28.086899 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 11:08:28.090376 1 0 24 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
2549 11:08:28.097310 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2550 11:08:28.100405 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
2551 11:08:28.103685 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2552 11:08:28.107187 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 11:08:28.113797 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 11:08:28.117388 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 11:08:28.120552 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 11:08:28.127539 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 11:08:28.130738 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2558 11:08:28.134019 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2559 11:08:28.140586 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 11:08:28.144197 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 11:08:28.147200 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 11:08:28.153725 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 11:08:28.157110 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 11:08:28.160447 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 11:08:28.167184 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 11:08:28.170673 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 11:08:28.173858 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 11:08:28.180416 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 11:08:28.184012 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 11:08:28.187338 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 11:08:28.194103 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 11:08:28.196980 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 11:08:28.200575 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2574 11:08:28.203732 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 11:08:28.207141 Total UI for P1: 0, mck2ui 16
2576 11:08:28.210494 best dqsien dly found for B0: ( 1, 3, 28)
2577 11:08:28.213900 Total UI for P1: 0, mck2ui 16
2578 11:08:28.217161 best dqsien dly found for B1: ( 1, 3, 30)
2579 11:08:28.220465 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2580 11:08:28.223848 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2581 11:08:28.227215
2582 11:08:28.230586 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2583 11:08:28.234018 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2584 11:08:28.237444 [Gating] SW calibration Done
2585 11:08:28.237527 ==
2586 11:08:28.240696 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 11:08:28.244088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 11:08:28.244172 ==
2589 11:08:28.244239 RX Vref Scan: 0
2590 11:08:28.244299
2591 11:08:28.247379 RX Vref 0 -> 0, step: 1
2592 11:08:28.247463
2593 11:08:28.250654 RX Delay -40 -> 252, step: 8
2594 11:08:28.254088 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2595 11:08:28.257417 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2596 11:08:28.264272 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2597 11:08:28.267591 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2598 11:08:28.270530 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2599 11:08:28.274070 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2600 11:08:28.277115 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2601 11:08:28.280727 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2602 11:08:28.287511 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2603 11:08:28.290505 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2604 11:08:28.294091 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2605 11:08:28.297178 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2606 11:08:28.300754 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2607 11:08:28.307353 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2608 11:08:28.310266 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2609 11:08:28.313631 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2610 11:08:28.313715 ==
2611 11:08:28.317174 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 11:08:28.320514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 11:08:28.323841 ==
2614 11:08:28.323916 DQS Delay:
2615 11:08:28.323980 DQS0 = 0, DQS1 = 0
2616 11:08:28.327141 DQM Delay:
2617 11:08:28.327223 DQM0 = 122, DQM1 = 110
2618 11:08:28.330546 DQ Delay:
2619 11:08:28.333936 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2620 11:08:28.337405 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2621 11:08:28.340621 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2622 11:08:28.344019 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2623 11:08:28.344101
2624 11:08:28.344167
2625 11:08:28.344227 ==
2626 11:08:28.347207 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 11:08:28.350468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 11:08:28.350555 ==
2629 11:08:28.350620
2630 11:08:28.350681
2631 11:08:28.353796 TX Vref Scan disable
2632 11:08:28.357069 == TX Byte 0 ==
2633 11:08:28.360493 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2634 11:08:28.363792 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2635 11:08:28.367127 == TX Byte 1 ==
2636 11:08:28.370193 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2637 11:08:28.373910 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2638 11:08:28.374025 ==
2639 11:08:28.377196 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 11:08:28.384229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 11:08:28.384312 ==
2642 11:08:28.394172 TX Vref=22, minBit 3, minWin=23, winSum=403
2643 11:08:28.397493 TX Vref=24, minBit 0, minWin=24, winSum=408
2644 11:08:28.401000 TX Vref=26, minBit 0, minWin=24, winSum=416
2645 11:08:28.404381 TX Vref=28, minBit 1, minWin=25, winSum=420
2646 11:08:28.407458 TX Vref=30, minBit 3, minWin=25, winSum=421
2647 11:08:28.413845 TX Vref=32, minBit 1, minWin=24, winSum=413
2648 11:08:28.417510 [TxChooseVref] Worse bit 3, Min win 25, Win sum 421, Final Vref 30
2649 11:08:28.417593
2650 11:08:28.420668 Final TX Range 1 Vref 30
2651 11:08:28.420750
2652 11:08:28.420816 ==
2653 11:08:28.424163 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 11:08:28.427266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 11:08:28.427353 ==
2656 11:08:28.427441
2657 11:08:28.430936
2658 11:08:28.431044 TX Vref Scan disable
2659 11:08:28.434092 == TX Byte 0 ==
2660 11:08:28.437549 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2661 11:08:28.440549 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2662 11:08:28.444166 == TX Byte 1 ==
2663 11:08:28.447400 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2664 11:08:28.450733 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2665 11:08:28.450815
2666 11:08:28.454048 [DATLAT]
2667 11:08:28.454130 Freq=1200, CH0 RK0
2668 11:08:28.454195
2669 11:08:28.457272 DATLAT Default: 0xd
2670 11:08:28.457354 0, 0xFFFF, sum = 0
2671 11:08:28.460692 1, 0xFFFF, sum = 0
2672 11:08:28.460775 2, 0xFFFF, sum = 0
2673 11:08:28.464022 3, 0xFFFF, sum = 0
2674 11:08:28.464106 4, 0xFFFF, sum = 0
2675 11:08:28.467284 5, 0xFFFF, sum = 0
2676 11:08:28.467367 6, 0xFFFF, sum = 0
2677 11:08:28.470775 7, 0xFFFF, sum = 0
2678 11:08:28.474144 8, 0xFFFF, sum = 0
2679 11:08:28.474254 9, 0xFFFF, sum = 0
2680 11:08:28.477045 10, 0xFFFF, sum = 0
2681 11:08:28.477155 11, 0xFFFF, sum = 0
2682 11:08:28.480555 12, 0x0, sum = 1
2683 11:08:28.480666 13, 0x0, sum = 2
2684 11:08:28.480761 14, 0x0, sum = 3
2685 11:08:28.483884 15, 0x0, sum = 4
2686 11:08:28.483971 best_step = 13
2687 11:08:28.484037
2688 11:08:28.487203 ==
2689 11:08:28.487288 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 11:08:28.494135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 11:08:28.494241 ==
2692 11:08:28.494336 RX Vref Scan: 1
2693 11:08:28.494414
2694 11:08:28.497170 Set Vref Range= 32 -> 127
2695 11:08:28.497270
2696 11:08:28.500583 RX Vref 32 -> 127, step: 1
2697 11:08:28.500669
2698 11:08:28.504205 RX Delay -13 -> 252, step: 4
2699 11:08:28.504287
2700 11:08:28.507551 Set Vref, RX VrefLevel [Byte0]: 32
2701 11:08:28.510900 [Byte1]: 32
2702 11:08:28.510982
2703 11:08:28.513796 Set Vref, RX VrefLevel [Byte0]: 33
2704 11:08:28.517385 [Byte1]: 33
2705 11:08:28.517467
2706 11:08:28.520964 Set Vref, RX VrefLevel [Byte0]: 34
2707 11:08:28.524131 [Byte1]: 34
2708 11:08:28.528156
2709 11:08:28.528263 Set Vref, RX VrefLevel [Byte0]: 35
2710 11:08:28.531370 [Byte1]: 35
2711 11:08:28.535800
2712 11:08:28.535883 Set Vref, RX VrefLevel [Byte0]: 36
2713 11:08:28.539616 [Byte1]: 36
2714 11:08:28.544070
2715 11:08:28.544151 Set Vref, RX VrefLevel [Byte0]: 37
2716 11:08:28.546967 [Byte1]: 37
2717 11:08:28.551933
2718 11:08:28.552014 Set Vref, RX VrefLevel [Byte0]: 38
2719 11:08:28.555208 [Byte1]: 38
2720 11:08:28.559696
2721 11:08:28.559804 Set Vref, RX VrefLevel [Byte0]: 39
2722 11:08:28.563110 [Byte1]: 39
2723 11:08:28.567506
2724 11:08:28.567587 Set Vref, RX VrefLevel [Byte0]: 40
2725 11:08:28.570908 [Byte1]: 40
2726 11:08:28.575796
2727 11:08:28.575878 Set Vref, RX VrefLevel [Byte0]: 41
2728 11:08:28.578688 [Byte1]: 41
2729 11:08:28.583661
2730 11:08:28.583743 Set Vref, RX VrefLevel [Byte0]: 42
2731 11:08:28.586574 [Byte1]: 42
2732 11:08:28.591434
2733 11:08:28.591516 Set Vref, RX VrefLevel [Byte0]: 43
2734 11:08:28.594688 [Byte1]: 43
2735 11:08:28.598996
2736 11:08:28.599078 Set Vref, RX VrefLevel [Byte0]: 44
2737 11:08:28.602464 [Byte1]: 44
2738 11:08:28.607161
2739 11:08:28.607242 Set Vref, RX VrefLevel [Byte0]: 45
2740 11:08:28.610221 [Byte1]: 45
2741 11:08:28.614715
2742 11:08:28.614800 Set Vref, RX VrefLevel [Byte0]: 46
2743 11:08:28.618299 [Byte1]: 46
2744 11:08:28.622851
2745 11:08:28.622929 Set Vref, RX VrefLevel [Byte0]: 47
2746 11:08:28.626245 [Byte1]: 47
2747 11:08:28.630528
2748 11:08:28.630605 Set Vref, RX VrefLevel [Byte0]: 48
2749 11:08:28.634141 [Byte1]: 48
2750 11:08:28.638479
2751 11:08:28.638566 Set Vref, RX VrefLevel [Byte0]: 49
2752 11:08:28.641968 [Byte1]: 49
2753 11:08:28.646471
2754 11:08:28.646545 Set Vref, RX VrefLevel [Byte0]: 50
2755 11:08:28.649831 [Byte1]: 50
2756 11:08:28.654135
2757 11:08:28.654226 Set Vref, RX VrefLevel [Byte0]: 51
2758 11:08:28.657761 [Byte1]: 51
2759 11:08:28.662389
2760 11:08:28.662493 Set Vref, RX VrefLevel [Byte0]: 52
2761 11:08:28.665697 [Byte1]: 52
2762 11:08:28.670121
2763 11:08:28.670201 Set Vref, RX VrefLevel [Byte0]: 53
2764 11:08:28.673338 [Byte1]: 53
2765 11:08:28.678092
2766 11:08:28.678163 Set Vref, RX VrefLevel [Byte0]: 54
2767 11:08:28.680986 [Byte1]: 54
2768 11:08:28.686149
2769 11:08:28.686253 Set Vref, RX VrefLevel [Byte0]: 55
2770 11:08:28.688942 [Byte1]: 55
2771 11:08:28.693702
2772 11:08:28.693799 Set Vref, RX VrefLevel [Byte0]: 56
2773 11:08:28.697061 [Byte1]: 56
2774 11:08:28.702314
2775 11:08:28.702417 Set Vref, RX VrefLevel [Byte0]: 57
2776 11:08:28.705052 [Byte1]: 57
2777 11:08:28.709770
2778 11:08:28.709870 Set Vref, RX VrefLevel [Byte0]: 58
2779 11:08:28.712790 [Byte1]: 58
2780 11:08:28.717293
2781 11:08:28.717368 Set Vref, RX VrefLevel [Byte0]: 59
2782 11:08:28.720671 [Byte1]: 59
2783 11:08:28.725137
2784 11:08:28.725217 Set Vref, RX VrefLevel [Byte0]: 60
2785 11:08:28.728643 [Byte1]: 60
2786 11:08:28.733036
2787 11:08:28.733128 Set Vref, RX VrefLevel [Byte0]: 61
2788 11:08:28.736364 [Byte1]: 61
2789 11:08:28.740968
2790 11:08:28.741046 Set Vref, RX VrefLevel [Byte0]: 62
2791 11:08:28.744598 [Byte1]: 62
2792 11:08:28.748957
2793 11:08:28.749031 Set Vref, RX VrefLevel [Byte0]: 63
2794 11:08:28.752640 [Byte1]: 63
2795 11:08:28.757299
2796 11:08:28.757397 Set Vref, RX VrefLevel [Byte0]: 64
2797 11:08:28.760305 [Byte1]: 64
2798 11:08:28.764546
2799 11:08:28.764640 Set Vref, RX VrefLevel [Byte0]: 65
2800 11:08:28.767863 [Byte1]: 65
2801 11:08:28.772637
2802 11:08:28.772706 Set Vref, RX VrefLevel [Byte0]: 66
2803 11:08:28.775863 [Byte1]: 66
2804 11:08:28.780355
2805 11:08:28.780422 Set Vref, RX VrefLevel [Byte0]: 67
2806 11:08:28.783654 [Byte1]: 67
2807 11:08:28.788373
2808 11:08:28.788472 Set Vref, RX VrefLevel [Byte0]: 68
2809 11:08:28.791874 [Byte1]: 68
2810 11:08:28.796636
2811 11:08:28.796736 Set Vref, RX VrefLevel [Byte0]: 69
2812 11:08:28.799750 [Byte1]: 69
2813 11:08:28.804029
2814 11:08:28.804118 Final RX Vref Byte 0 = 59 to rank0
2815 11:08:28.807874 Final RX Vref Byte 1 = 50 to rank0
2816 11:08:28.810935 Final RX Vref Byte 0 = 59 to rank1
2817 11:08:28.814135 Final RX Vref Byte 1 = 50 to rank1==
2818 11:08:28.817562 Dram Type= 6, Freq= 0, CH_0, rank 0
2819 11:08:28.820773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 11:08:28.824411 ==
2821 11:08:28.824494 DQS Delay:
2822 11:08:28.824560 DQS0 = 0, DQS1 = 0
2823 11:08:28.827622 DQM Delay:
2824 11:08:28.827695 DQM0 = 122, DQM1 = 109
2825 11:08:28.830826 DQ Delay:
2826 11:08:28.834308 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =118
2827 11:08:28.837434 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2828 11:08:28.840900 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =108
2829 11:08:28.844231 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2830 11:08:28.844311
2831 11:08:28.844375
2832 11:08:28.850950 [DQSOSCAuto] RK0, (LSB)MR18= 0x805, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2833 11:08:28.854185 CH0 RK0: MR19=404, MR18=805
2834 11:08:28.861021 CH0_RK0: MR19=0x404, MR18=0x805, DQSOSC=406, MR23=63, INC=39, DEC=26
2835 11:08:28.861099
2836 11:08:28.864275 ----->DramcWriteLeveling(PI) begin...
2837 11:08:28.864361 ==
2838 11:08:28.867660 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 11:08:28.870807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2840 11:08:28.870887 ==
2841 11:08:28.874125 Write leveling (Byte 0): 34 => 34
2842 11:08:28.877444 Write leveling (Byte 1): 29 => 29
2843 11:08:28.880860 DramcWriteLeveling(PI) end<-----
2844 11:08:28.880932
2845 11:08:28.881001 ==
2846 11:08:28.884151 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 11:08:28.887603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 11:08:28.890785 ==
2849 11:08:28.890878 [Gating] SW mode calibration
2850 11:08:28.900965 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2851 11:08:28.904589 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2852 11:08:28.907927 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2853 11:08:28.914272 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 11:08:28.917582 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 11:08:28.921185 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 11:08:28.927823 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 11:08:28.930918 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 11:08:28.934215 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2859 11:08:28.941077 0 15 28 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (0 1)
2860 11:08:28.944578 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2861 11:08:28.947789 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 11:08:28.954747 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 11:08:28.957635 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 11:08:28.961399 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 11:08:28.964852 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 11:08:28.970975 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2867 11:08:28.974452 1 0 28 | B1->B0 | 3636 3939 | 0 0 | (0 0) (0 0)
2868 11:08:28.977931 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 11:08:28.984694 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 11:08:28.988141 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 11:08:28.991618 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 11:08:28.997830 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 11:08:29.001311 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 11:08:29.004690 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 11:08:29.011680 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2876 11:08:29.015136 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 11:08:29.018247 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 11:08:29.025009 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 11:08:29.028212 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 11:08:29.031967 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 11:08:29.034866 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 11:08:29.041695 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 11:08:29.045215 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 11:08:29.048628 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 11:08:29.055372 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 11:08:29.058649 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 11:08:29.061838 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 11:08:29.068428 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 11:08:29.071918 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 11:08:29.075070 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 11:08:29.081845 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2892 11:08:29.085631 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2893 11:08:29.088751 Total UI for P1: 0, mck2ui 16
2894 11:08:29.092065 best dqsien dly found for B1: ( 1, 3, 28)
2895 11:08:29.095532 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 11:08:29.098939 Total UI for P1: 0, mck2ui 16
2897 11:08:29.101687 best dqsien dly found for B0: ( 1, 3, 30)
2898 11:08:29.105017 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2899 11:08:29.108120 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2900 11:08:29.108534
2901 11:08:29.111690 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2902 11:08:29.118633 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2903 11:08:29.118874 [Gating] SW calibration Done
2904 11:08:29.119064 ==
2905 11:08:29.121783 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 11:08:29.128619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 11:08:29.128950 ==
2908 11:08:29.129158 RX Vref Scan: 0
2909 11:08:29.129341
2910 11:08:29.132031 RX Vref 0 -> 0, step: 1
2911 11:08:29.132363
2912 11:08:29.134981 RX Delay -40 -> 252, step: 8
2913 11:08:29.138894 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2914 11:08:29.142379 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2915 11:08:29.145274 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2916 11:08:29.152188 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2917 11:08:29.155125 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2918 11:08:29.158669 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2919 11:08:29.161762 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2920 11:08:29.165307 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2921 11:08:29.168379 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2922 11:08:29.175197 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2923 11:08:29.178631 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2924 11:08:29.181913 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2925 11:08:29.185105 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2926 11:08:29.188542 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2927 11:08:29.195300 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2928 11:08:29.198729 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2929 11:08:29.199189 ==
2930 11:08:29.202072 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 11:08:29.205730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 11:08:29.206245 ==
2933 11:08:29.208707 DQS Delay:
2934 11:08:29.209302 DQS0 = 0, DQS1 = 0
2935 11:08:29.209906 DQM Delay:
2936 11:08:29.212021 DQM0 = 120, DQM1 = 108
2937 11:08:29.212537 DQ Delay:
2938 11:08:29.215560 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2939 11:08:29.218423 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2940 11:08:29.221987 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2941 11:08:29.228236 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2942 11:08:29.228558
2943 11:08:29.228809
2944 11:08:29.229043 ==
2945 11:08:29.231922 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 11:08:29.234741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 11:08:29.235105 ==
2948 11:08:29.235362
2949 11:08:29.235597
2950 11:08:29.238529 TX Vref Scan disable
2951 11:08:29.238949 == TX Byte 0 ==
2952 11:08:29.245076 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2953 11:08:29.248309 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2954 11:08:29.248789 == TX Byte 1 ==
2955 11:08:29.255138 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2956 11:08:29.258453 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2957 11:08:29.258925 ==
2958 11:08:29.261759 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 11:08:29.265028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 11:08:29.265501 ==
2961 11:08:29.278240 TX Vref=22, minBit 2, minWin=24, winSum=406
2962 11:08:29.281738 TX Vref=24, minBit 0, minWin=24, winSum=413
2963 11:08:29.285044 TX Vref=26, minBit 1, minWin=24, winSum=419
2964 11:08:29.288301 TX Vref=28, minBit 1, minWin=25, winSum=423
2965 11:08:29.291445 TX Vref=30, minBit 5, minWin=25, winSum=426
2966 11:08:29.294734 TX Vref=32, minBit 7, minWin=24, winSum=419
2967 11:08:29.301316 [TxChooseVref] Worse bit 5, Min win 25, Win sum 426, Final Vref 30
2968 11:08:29.301793
2969 11:08:29.304551 Final TX Range 1 Vref 30
2970 11:08:29.305022
2971 11:08:29.305486 ==
2972 11:08:29.308142 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 11:08:29.311290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 11:08:29.311761 ==
2975 11:08:29.312235
2976 11:08:29.314675
2977 11:08:29.315143 TX Vref Scan disable
2978 11:08:29.318452 == TX Byte 0 ==
2979 11:08:29.321393 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2980 11:08:29.324605 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2981 11:08:29.328087 == TX Byte 1 ==
2982 11:08:29.331506 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2983 11:08:29.334768 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2984 11:08:29.335231
2985 11:08:29.338004 [DATLAT]
2986 11:08:29.338327 Freq=1200, CH0 RK1
2987 11:08:29.338585
2988 11:08:29.341417 DATLAT Default: 0xd
2989 11:08:29.341738 0, 0xFFFF, sum = 0
2990 11:08:29.344886 1, 0xFFFF, sum = 0
2991 11:08:29.345215 2, 0xFFFF, sum = 0
2992 11:08:29.348330 3, 0xFFFF, sum = 0
2993 11:08:29.348754 4, 0xFFFF, sum = 0
2994 11:08:29.351378 5, 0xFFFF, sum = 0
2995 11:08:29.351706 6, 0xFFFF, sum = 0
2996 11:08:29.354562 7, 0xFFFF, sum = 0
2997 11:08:29.354889 8, 0xFFFF, sum = 0
2998 11:08:29.358029 9, 0xFFFF, sum = 0
2999 11:08:29.361578 10, 0xFFFF, sum = 0
3000 11:08:29.361920 11, 0xFFFF, sum = 0
3001 11:08:29.364999 12, 0x0, sum = 1
3002 11:08:29.365329 13, 0x0, sum = 2
3003 11:08:29.365593 14, 0x0, sum = 3
3004 11:08:29.368319 15, 0x0, sum = 4
3005 11:08:29.368647 best_step = 13
3006 11:08:29.368906
3007 11:08:29.369146 ==
3008 11:08:29.371639 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 11:08:29.378374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 11:08:29.378701 ==
3011 11:08:29.378963 RX Vref Scan: 0
3012 11:08:29.379208
3013 11:08:29.381209 RX Vref 0 -> 0, step: 1
3014 11:08:29.381534
3015 11:08:29.384656 RX Delay -21 -> 252, step: 4
3016 11:08:29.388100 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3017 11:08:29.391593 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3018 11:08:29.398213 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3019 11:08:29.401699 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3020 11:08:29.404739 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3021 11:08:29.408467 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3022 11:08:29.411801 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3023 11:08:29.418300 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3024 11:08:29.421625 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3025 11:08:29.425009 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3026 11:08:29.428194 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3027 11:08:29.431601 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3028 11:08:29.438354 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3029 11:08:29.441492 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3030 11:08:29.445008 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3031 11:08:29.448166 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3032 11:08:29.448572 ==
3033 11:08:29.451396 Dram Type= 6, Freq= 0, CH_0, rank 1
3034 11:08:29.458100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3035 11:08:29.458362 ==
3036 11:08:29.458559 DQS Delay:
3037 11:08:29.458755 DQS0 = 0, DQS1 = 0
3038 11:08:29.461187 DQM Delay:
3039 11:08:29.461487 DQM0 = 118, DQM1 = 107
3040 11:08:29.464536 DQ Delay:
3041 11:08:29.467923 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =112
3042 11:08:29.471401 DQ4 =120, DQ5 =114, DQ6 =124, DQ7 =124
3043 11:08:29.474676 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =104
3044 11:08:29.478412 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3045 11:08:29.478708
3046 11:08:29.478920
3047 11:08:29.484739 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3048 11:08:29.487999 CH0 RK1: MR19=403, MR18=10F7
3049 11:08:29.494899 CH0_RK1: MR19=0x403, MR18=0x10F7, DQSOSC=403, MR23=63, INC=40, DEC=26
3050 11:08:29.498362 [RxdqsGatingPostProcess] freq 1200
3051 11:08:29.504974 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3052 11:08:29.508082 best DQS0 dly(2T, 0.5T) = (0, 11)
3053 11:08:29.508274 best DQS1 dly(2T, 0.5T) = (0, 11)
3054 11:08:29.511699 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3055 11:08:29.514844 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3056 11:08:29.518368 best DQS0 dly(2T, 0.5T) = (0, 11)
3057 11:08:29.521263 best DQS1 dly(2T, 0.5T) = (0, 11)
3058 11:08:29.524970 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3059 11:08:29.528356 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3060 11:08:29.531776 Pre-setting of DQS Precalculation
3061 11:08:29.538515 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3062 11:08:29.538746 ==
3063 11:08:29.541703 Dram Type= 6, Freq= 0, CH_1, rank 0
3064 11:08:29.545036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 11:08:29.545249 ==
3066 11:08:29.548421 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3067 11:08:29.554879 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3068 11:08:29.564209 [CA 0] Center 37 (7~68) winsize 62
3069 11:08:29.567484 [CA 1] Center 37 (7~68) winsize 62
3070 11:08:29.570799 [CA 2] Center 35 (5~65) winsize 61
3071 11:08:29.574167 [CA 3] Center 34 (4~65) winsize 62
3072 11:08:29.577694 [CA 4] Center 34 (3~65) winsize 63
3073 11:08:29.580817 [CA 5] Center 33 (3~64) winsize 62
3074 11:08:29.580900
3075 11:08:29.584334 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3076 11:08:29.584417
3077 11:08:29.587480 [CATrainingPosCal] consider 1 rank data
3078 11:08:29.590860 u2DelayCellTimex100 = 270/100 ps
3079 11:08:29.594551 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3080 11:08:29.597660 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3081 11:08:29.601089 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3082 11:08:29.607541 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3083 11:08:29.611386 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
3084 11:08:29.614280 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3085 11:08:29.614393
3086 11:08:29.617759 CA PerBit enable=1, Macro0, CA PI delay=33
3087 11:08:29.617880
3088 11:08:29.620871 [CBTSetCACLKResult] CA Dly = 33
3089 11:08:29.620994 CS Dly: 5 (0~36)
3090 11:08:29.621090 ==
3091 11:08:29.624274 Dram Type= 6, Freq= 0, CH_1, rank 1
3092 11:08:29.630966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 11:08:29.631119 ==
3094 11:08:29.634422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3095 11:08:29.641121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3096 11:08:29.650046 [CA 0] Center 38 (8~68) winsize 61
3097 11:08:29.653271 [CA 1] Center 37 (7~68) winsize 62
3098 11:08:29.656874 [CA 2] Center 35 (5~66) winsize 62
3099 11:08:29.660012 [CA 3] Center 34 (4~65) winsize 62
3100 11:08:29.663753 [CA 4] Center 35 (5~65) winsize 61
3101 11:08:29.666612 [CA 5] Center 34 (4~64) winsize 61
3102 11:08:29.667079
3103 11:08:29.669907 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3104 11:08:29.670408
3105 11:08:29.673498 [CATrainingPosCal] consider 2 rank data
3106 11:08:29.676515 u2DelayCellTimex100 = 270/100 ps
3107 11:08:29.679854 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3108 11:08:29.683282 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3109 11:08:29.690009 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3110 11:08:29.693337 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3111 11:08:29.697110 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3112 11:08:29.700499 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3113 11:08:29.700964
3114 11:08:29.703792 CA PerBit enable=1, Macro0, CA PI delay=34
3115 11:08:29.704257
3116 11:08:29.707234 [CBTSetCACLKResult] CA Dly = 34
3117 11:08:29.707829 CS Dly: 6 (0~39)
3118 11:08:29.708361
3119 11:08:29.710103 ----->DramcWriteLeveling(PI) begin...
3120 11:08:29.710668 ==
3121 11:08:29.713536 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 11:08:29.720276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 11:08:29.720884 ==
3124 11:08:29.723540 Write leveling (Byte 0): 25 => 25
3125 11:08:29.727148 Write leveling (Byte 1): 27 => 27
3126 11:08:29.727647 DramcWriteLeveling(PI) end<-----
3127 11:08:29.729767
3128 11:08:29.730265 ==
3129 11:08:29.733401 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 11:08:29.736756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 11:08:29.737215 ==
3132 11:08:29.740009 [Gating] SW mode calibration
3133 11:08:29.746488 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3134 11:08:29.750036 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3135 11:08:29.756684 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 11:08:29.759745 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 11:08:29.763402 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 11:08:29.769930 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 11:08:29.773303 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 11:08:29.776360 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3141 11:08:29.783154 0 15 24 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (1 0)
3142 11:08:29.786605 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3143 11:08:29.790255 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 11:08:29.796503 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 11:08:29.799907 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 11:08:29.803397 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 11:08:29.809790 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 11:08:29.813631 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 11:08:29.816616 1 0 24 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
3150 11:08:29.823348 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 11:08:29.826674 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 11:08:29.830375 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 11:08:29.833201 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 11:08:29.839899 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 11:08:29.843477 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 11:08:29.846495 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3157 11:08:29.853394 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3158 11:08:29.856686 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 11:08:29.859859 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 11:08:29.866925 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 11:08:29.870028 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 11:08:29.873448 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 11:08:29.879879 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 11:08:29.883510 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 11:08:29.886753 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 11:08:29.893748 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 11:08:29.896928 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 11:08:29.899965 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 11:08:29.906666 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 11:08:29.909887 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 11:08:29.913583 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 11:08:29.916800 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3173 11:08:29.923335 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3174 11:08:29.926677 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 11:08:29.929928 Total UI for P1: 0, mck2ui 16
3176 11:08:29.933533 best dqsien dly found for B0: ( 1, 3, 22)
3177 11:08:29.936670 Total UI for P1: 0, mck2ui 16
3178 11:08:29.939898 best dqsien dly found for B1: ( 1, 3, 24)
3179 11:08:29.943446 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3180 11:08:29.946687 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3181 11:08:29.946964
3182 11:08:29.949934 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3183 11:08:29.953279 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3184 11:08:29.957026 [Gating] SW calibration Done
3185 11:08:29.957298 ==
3186 11:08:29.959854 Dram Type= 6, Freq= 0, CH_1, rank 0
3187 11:08:29.966710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3188 11:08:29.966984 ==
3189 11:08:29.967203 RX Vref Scan: 0
3190 11:08:29.967404
3191 11:08:29.969926 RX Vref 0 -> 0, step: 1
3192 11:08:29.970219
3193 11:08:29.973494 RX Delay -40 -> 252, step: 8
3194 11:08:29.976883 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3195 11:08:29.979831 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3196 11:08:29.983724 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3197 11:08:29.986599 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3198 11:08:29.993423 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3199 11:08:29.996651 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3200 11:08:29.999991 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3201 11:08:30.003395 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3202 11:08:30.007034 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3203 11:08:30.013692 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3204 11:08:30.017066 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3205 11:08:30.020253 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3206 11:08:30.023254 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3207 11:08:30.026841 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3208 11:08:30.033361 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3209 11:08:30.036662 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3210 11:08:30.036826 ==
3211 11:08:30.040127 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 11:08:30.043387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 11:08:30.043552 ==
3214 11:08:30.043706 DQS Delay:
3215 11:08:30.046901 DQS0 = 0, DQS1 = 0
3216 11:08:30.047063 DQM Delay:
3217 11:08:30.050066 DQM0 = 120, DQM1 = 113
3218 11:08:30.050229 DQ Delay:
3219 11:08:30.053468 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3220 11:08:30.056771 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3221 11:08:30.060137 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3222 11:08:30.063286 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3223 11:08:30.066741
3224 11:08:30.066908
3225 11:08:30.067037 ==
3226 11:08:30.070015 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 11:08:30.073319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 11:08:30.073485 ==
3229 11:08:30.073613
3230 11:08:30.073734
3231 11:08:30.076906 TX Vref Scan disable
3232 11:08:30.077069 == TX Byte 0 ==
3233 11:08:30.083498 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3234 11:08:30.086729 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3235 11:08:30.086895 == TX Byte 1 ==
3236 11:08:30.093139 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3237 11:08:30.096765 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3238 11:08:30.096930 ==
3239 11:08:30.099962 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 11:08:30.103242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 11:08:30.103407 ==
3242 11:08:30.115321 TX Vref=22, minBit 10, minWin=24, winSum=404
3243 11:08:30.118603 TX Vref=24, minBit 1, minWin=25, winSum=409
3244 11:08:30.121991 TX Vref=26, minBit 8, minWin=25, winSum=417
3245 11:08:30.125239 TX Vref=28, minBit 9, minWin=25, winSum=421
3246 11:08:30.128710 TX Vref=30, minBit 10, minWin=25, winSum=423
3247 11:08:30.135399 TX Vref=32, minBit 10, minWin=25, winSum=421
3248 11:08:30.138878 [TxChooseVref] Worse bit 10, Min win 25, Win sum 423, Final Vref 30
3249 11:08:30.139044
3250 11:08:30.141929 Final TX Range 1 Vref 30
3251 11:08:30.142108
3252 11:08:30.142238 ==
3253 11:08:30.145444 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 11:08:30.148744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 11:08:30.152059 ==
3256 11:08:30.152225
3257 11:08:30.152355
3258 11:08:30.152477 TX Vref Scan disable
3259 11:08:30.155571 == TX Byte 0 ==
3260 11:08:30.158692 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3261 11:08:30.162066 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3262 11:08:30.165749 == TX Byte 1 ==
3263 11:08:30.168836 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3264 11:08:30.172214 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3265 11:08:30.172406
3266 11:08:30.175552 [DATLAT]
3267 11:08:30.175742 Freq=1200, CH1 RK0
3268 11:08:30.175896
3269 11:08:30.178885 DATLAT Default: 0xd
3270 11:08:30.179110 0, 0xFFFF, sum = 0
3271 11:08:30.182115 1, 0xFFFF, sum = 0
3272 11:08:30.182397 2, 0xFFFF, sum = 0
3273 11:08:30.185737 3, 0xFFFF, sum = 0
3274 11:08:30.185821 4, 0xFFFF, sum = 0
3275 11:08:30.189047 5, 0xFFFF, sum = 0
3276 11:08:30.189130 6, 0xFFFF, sum = 0
3277 11:08:30.192272 7, 0xFFFF, sum = 0
3278 11:08:30.195559 8, 0xFFFF, sum = 0
3279 11:08:30.195642 9, 0xFFFF, sum = 0
3280 11:08:30.198904 10, 0xFFFF, sum = 0
3281 11:08:30.198988 11, 0xFFFF, sum = 0
3282 11:08:30.202243 12, 0x0, sum = 1
3283 11:08:30.202326 13, 0x0, sum = 2
3284 11:08:30.205484 14, 0x0, sum = 3
3285 11:08:30.205567 15, 0x0, sum = 4
3286 11:08:30.205632 best_step = 13
3287 11:08:30.205691
3288 11:08:30.208742 ==
3289 11:08:30.208824 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 11:08:30.215824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 11:08:30.215907 ==
3292 11:08:30.215972 RX Vref Scan: 1
3293 11:08:30.216032
3294 11:08:30.218901 Set Vref Range= 32 -> 127
3295 11:08:30.218981
3296 11:08:30.222326 RX Vref 32 -> 127, step: 1
3297 11:08:30.222406
3298 11:08:30.225606 RX Delay -13 -> 252, step: 4
3299 11:08:30.225685
3300 11:08:30.228938 Set Vref, RX VrefLevel [Byte0]: 32
3301 11:08:30.232383 [Byte1]: 32
3302 11:08:30.232463
3303 11:08:30.235746 Set Vref, RX VrefLevel [Byte0]: 33
3304 11:08:30.238887 [Byte1]: 33
3305 11:08:30.238966
3306 11:08:30.242433 Set Vref, RX VrefLevel [Byte0]: 34
3307 11:08:30.245842 [Byte1]: 34
3308 11:08:30.249530
3309 11:08:30.249609 Set Vref, RX VrefLevel [Byte0]: 35
3310 11:08:30.252719 [Byte1]: 35
3311 11:08:30.257392
3312 11:08:30.257472 Set Vref, RX VrefLevel [Byte0]: 36
3313 11:08:30.260900 [Byte1]: 36
3314 11:08:30.265257
3315 11:08:30.265336 Set Vref, RX VrefLevel [Byte0]: 37
3316 11:08:30.268668 [Byte1]: 37
3317 11:08:30.273022
3318 11:08:30.273101 Set Vref, RX VrefLevel [Byte0]: 38
3319 11:08:30.276440 [Byte1]: 38
3320 11:08:30.281050
3321 11:08:30.281130 Set Vref, RX VrefLevel [Byte0]: 39
3322 11:08:30.284339 [Byte1]: 39
3323 11:08:30.289074
3324 11:08:30.289154 Set Vref, RX VrefLevel [Byte0]: 40
3325 11:08:30.292403 [Byte1]: 40
3326 11:08:30.297089
3327 11:08:30.297169 Set Vref, RX VrefLevel [Byte0]: 41
3328 11:08:30.300123 [Byte1]: 41
3329 11:08:30.304722
3330 11:08:30.304801 Set Vref, RX VrefLevel [Byte0]: 42
3331 11:08:30.307933 [Byte1]: 42
3332 11:08:30.312678
3333 11:08:30.312763 Set Vref, RX VrefLevel [Byte0]: 43
3334 11:08:30.315935 [Byte1]: 43
3335 11:08:30.320702
3336 11:08:30.320783 Set Vref, RX VrefLevel [Byte0]: 44
3337 11:08:30.323886 [Byte1]: 44
3338 11:08:30.328609
3339 11:08:30.328688 Set Vref, RX VrefLevel [Byte0]: 45
3340 11:08:30.331586 [Byte1]: 45
3341 11:08:30.336517
3342 11:08:30.336596 Set Vref, RX VrefLevel [Byte0]: 46
3343 11:08:30.339759 [Byte1]: 46
3344 11:08:30.344074
3345 11:08:30.344153 Set Vref, RX VrefLevel [Byte0]: 47
3346 11:08:30.347300 [Byte1]: 47
3347 11:08:30.352178
3348 11:08:30.352258 Set Vref, RX VrefLevel [Byte0]: 48
3349 11:08:30.355658 [Byte1]: 48
3350 11:08:30.360136
3351 11:08:30.360215 Set Vref, RX VrefLevel [Byte0]: 49
3352 11:08:30.363497 [Byte1]: 49
3353 11:08:30.367735
3354 11:08:30.367814 Set Vref, RX VrefLevel [Byte0]: 50
3355 11:08:30.371235 [Byte1]: 50
3356 11:08:30.375674
3357 11:08:30.375753 Set Vref, RX VrefLevel [Byte0]: 51
3358 11:08:30.379245 [Byte1]: 51
3359 11:08:30.383848
3360 11:08:30.383930 Set Vref, RX VrefLevel [Byte0]: 52
3361 11:08:30.387084 [Byte1]: 52
3362 11:08:30.391604
3363 11:08:30.391686 Set Vref, RX VrefLevel [Byte0]: 53
3364 11:08:30.395085 [Byte1]: 53
3365 11:08:30.399542
3366 11:08:30.399711 Set Vref, RX VrefLevel [Byte0]: 54
3367 11:08:30.403337 [Byte1]: 54
3368 11:08:30.407531
3369 11:08:30.407716 Set Vref, RX VrefLevel [Byte0]: 55
3370 11:08:30.411028 [Byte1]: 55
3371 11:08:30.415538
3372 11:08:30.415683 Set Vref, RX VrefLevel [Byte0]: 56
3373 11:08:30.418360 [Byte1]: 56
3374 11:08:30.423519
3375 11:08:30.423741 Set Vref, RX VrefLevel [Byte0]: 57
3376 11:08:30.426900 [Byte1]: 57
3377 11:08:30.431018
3378 11:08:30.431256 Set Vref, RX VrefLevel [Byte0]: 58
3379 11:08:30.434253 [Byte1]: 58
3380 11:08:30.438843
3381 11:08:30.439064 Set Vref, RX VrefLevel [Byte0]: 59
3382 11:08:30.442476 [Byte1]: 59
3383 11:08:30.447540
3384 11:08:30.447836 Set Vref, RX VrefLevel [Byte0]: 60
3385 11:08:30.450274 [Byte1]: 60
3386 11:08:30.455134
3387 11:08:30.455516 Set Vref, RX VrefLevel [Byte0]: 61
3388 11:08:30.458507 [Byte1]: 61
3389 11:08:30.462657
3390 11:08:30.463117 Set Vref, RX VrefLevel [Byte0]: 62
3391 11:08:30.466399 [Byte1]: 62
3392 11:08:30.471063
3393 11:08:30.471524 Set Vref, RX VrefLevel [Byte0]: 63
3394 11:08:30.474165 [Byte1]: 63
3395 11:08:30.478704
3396 11:08:30.479169 Set Vref, RX VrefLevel [Byte0]: 64
3397 11:08:30.482004 [Byte1]: 64
3398 11:08:30.486652
3399 11:08:30.487115 Set Vref, RX VrefLevel [Byte0]: 65
3400 11:08:30.493129 [Byte1]: 65
3401 11:08:30.493702
3402 11:08:30.496224 Set Vref, RX VrefLevel [Byte0]: 66
3403 11:08:30.499863 [Byte1]: 66
3404 11:08:30.500426
3405 11:08:30.503159 Set Vref, RX VrefLevel [Byte0]: 67
3406 11:08:30.506565 [Byte1]: 67
3407 11:08:30.510108
3408 11:08:30.510686 Final RX Vref Byte 0 = 51 to rank0
3409 11:08:30.513350 Final RX Vref Byte 1 = 52 to rank0
3410 11:08:30.516850 Final RX Vref Byte 0 = 51 to rank1
3411 11:08:30.520239 Final RX Vref Byte 1 = 52 to rank1==
3412 11:08:30.523635 Dram Type= 6, Freq= 0, CH_1, rank 0
3413 11:08:30.527222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3414 11:08:30.530614 ==
3415 11:08:30.531071 DQS Delay:
3416 11:08:30.531432 DQS0 = 0, DQS1 = 0
3417 11:08:30.533868 DQM Delay:
3418 11:08:30.534377 DQM0 = 119, DQM1 = 112
3419 11:08:30.537142 DQ Delay:
3420 11:08:30.540294 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3421 11:08:30.543491 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3422 11:08:30.546965 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3423 11:08:30.550199 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =118
3424 11:08:30.550699
3425 11:08:30.551063
3426 11:08:30.556652 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe11, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3427 11:08:30.560172 CH1 RK0: MR19=304, MR18=FE11
3428 11:08:30.566706 CH1_RK0: MR19=0x304, MR18=0xFE11, DQSOSC=403, MR23=63, INC=40, DEC=26
3429 11:08:30.566968
3430 11:08:30.569874 ----->DramcWriteLeveling(PI) begin...
3431 11:08:30.570163 ==
3432 11:08:30.573584 Dram Type= 6, Freq= 0, CH_1, rank 1
3433 11:08:30.576893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 11:08:30.580221 ==
3435 11:08:30.580467 Write leveling (Byte 0): 25 => 25
3436 11:08:30.583731 Write leveling (Byte 1): 29 => 29
3437 11:08:30.586839 DramcWriteLeveling(PI) end<-----
3438 11:08:30.587162
3439 11:08:30.587407 ==
3440 11:08:30.590114 Dram Type= 6, Freq= 0, CH_1, rank 1
3441 11:08:30.597033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3442 11:08:30.597286 ==
3443 11:08:30.597534 [Gating] SW mode calibration
3444 11:08:30.607146 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3445 11:08:30.610273 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3446 11:08:30.613487 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 11:08:30.620405 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 11:08:30.623818 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 11:08:30.627062 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 11:08:30.633402 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 11:08:30.636865 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3452 11:08:30.640133 0 15 24 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 0)
3453 11:08:30.647097 0 15 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
3454 11:08:30.650246 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 11:08:30.653729 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 11:08:30.660501 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 11:08:30.663732 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 11:08:30.667060 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 11:08:30.673611 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 11:08:30.676865 1 0 24 | B1->B0 | 4242 3131 | 0 1 | (0 0) (0 0)
3461 11:08:30.680137 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3462 11:08:30.687310 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 11:08:30.690354 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 11:08:30.693639 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 11:08:30.697013 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 11:08:30.703513 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 11:08:30.707112 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 11:08:30.710170 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3469 11:08:30.717150 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3470 11:08:30.720034 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 11:08:30.723414 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 11:08:30.730512 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 11:08:30.733757 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 11:08:30.737125 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 11:08:30.743872 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 11:08:30.747245 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 11:08:30.750150 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 11:08:30.756754 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 11:08:30.760101 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 11:08:30.763410 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 11:08:30.770519 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 11:08:30.774185 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 11:08:30.777344 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 11:08:30.783690 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3485 11:08:30.786856 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3486 11:08:30.789812 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 11:08:30.793290 Total UI for P1: 0, mck2ui 16
3488 11:08:30.796334 best dqsien dly found for B0: ( 1, 3, 26)
3489 11:08:30.800095 Total UI for P1: 0, mck2ui 16
3490 11:08:30.803523 best dqsien dly found for B1: ( 1, 3, 26)
3491 11:08:30.806897 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3492 11:08:30.810097 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3493 11:08:30.810628
3494 11:08:30.816578 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3495 11:08:30.820035 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3496 11:08:30.820499 [Gating] SW calibration Done
3497 11:08:30.822983 ==
3498 11:08:30.823451 Dram Type= 6, Freq= 0, CH_1, rank 1
3499 11:08:30.829862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 11:08:30.830357 ==
3501 11:08:30.830729 RX Vref Scan: 0
3502 11:08:30.831071
3503 11:08:30.833129 RX Vref 0 -> 0, step: 1
3504 11:08:30.833589
3505 11:08:30.836477 RX Delay -40 -> 252, step: 8
3506 11:08:30.839658 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3507 11:08:30.842976 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3508 11:08:30.846357 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3509 11:08:30.853067 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3510 11:08:30.856117 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3511 11:08:30.859569 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3512 11:08:30.862782 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3513 11:08:30.866120 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3514 11:08:30.872526 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3515 11:08:30.876442 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3516 11:08:30.879697 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3517 11:08:30.882957 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3518 11:08:30.889312 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3519 11:08:30.892486 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3520 11:08:30.895782 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3521 11:08:30.899504 iDelay=200, Bit 15, Center 127 (56 ~ 199) 144
3522 11:08:30.900189 ==
3523 11:08:30.902583 Dram Type= 6, Freq= 0, CH_1, rank 1
3524 11:08:30.905867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3525 11:08:30.909049 ==
3526 11:08:30.909579 DQS Delay:
3527 11:08:30.910179 DQS0 = 0, DQS1 = 0
3528 11:08:30.911952 DQM Delay:
3529 11:08:30.912051 DQM0 = 119, DQM1 = 114
3530 11:08:30.915664 DQ Delay:
3531 11:08:30.919052 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3532 11:08:30.922423 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3533 11:08:30.926101 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3534 11:08:30.928878 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =127
3535 11:08:30.928981
3536 11:08:30.929071
3537 11:08:30.929140 ==
3538 11:08:30.932184 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 11:08:30.935554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 11:08:30.935657 ==
3541 11:08:30.935747
3542 11:08:30.938892
3543 11:08:30.938995 TX Vref Scan disable
3544 11:08:30.942114 == TX Byte 0 ==
3545 11:08:30.945310 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3546 11:08:30.948738 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3547 11:08:30.952116 == TX Byte 1 ==
3548 11:08:30.955378 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3549 11:08:30.958554 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3550 11:08:30.958636 ==
3551 11:08:30.962183 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 11:08:30.968469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 11:08:30.968551 ==
3554 11:08:30.979387 TX Vref=22, minBit 3, minWin=25, winSum=417
3555 11:08:30.982739 TX Vref=24, minBit 1, minWin=26, winSum=427
3556 11:08:30.985958 TX Vref=26, minBit 1, minWin=26, winSum=431
3557 11:08:30.989131 TX Vref=28, minBit 8, minWin=26, winSum=429
3558 11:08:30.992314 TX Vref=30, minBit 10, minWin=26, winSum=431
3559 11:08:30.999362 TX Vref=32, minBit 9, minWin=25, winSum=428
3560 11:08:31.002528 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 26
3561 11:08:31.002611
3562 11:08:31.005714 Final TX Range 1 Vref 26
3563 11:08:31.005796
3564 11:08:31.005861 ==
3565 11:08:31.009215 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 11:08:31.012536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 11:08:31.015753 ==
3568 11:08:31.015835
3569 11:08:31.015900
3570 11:08:31.015959 TX Vref Scan disable
3571 11:08:31.019306 == TX Byte 0 ==
3572 11:08:31.022593 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3573 11:08:31.025894 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3574 11:08:31.029180 == TX Byte 1 ==
3575 11:08:31.032552 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3576 11:08:31.035695 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3577 11:08:31.039259
3578 11:08:31.039340 [DATLAT]
3579 11:08:31.039406 Freq=1200, CH1 RK1
3580 11:08:31.039466
3581 11:08:31.042970 DATLAT Default: 0xd
3582 11:08:31.043432 0, 0xFFFF, sum = 0
3583 11:08:31.046204 1, 0xFFFF, sum = 0
3584 11:08:31.046692 2, 0xFFFF, sum = 0
3585 11:08:31.049598 3, 0xFFFF, sum = 0
3586 11:08:31.052842 4, 0xFFFF, sum = 0
3587 11:08:31.053330 5, 0xFFFF, sum = 0
3588 11:08:31.056165 6, 0xFFFF, sum = 0
3589 11:08:31.056636 7, 0xFFFF, sum = 0
3590 11:08:31.059541 8, 0xFFFF, sum = 0
3591 11:08:31.060011 9, 0xFFFF, sum = 0
3592 11:08:31.062806 10, 0xFFFF, sum = 0
3593 11:08:31.063436 11, 0xFFFF, sum = 0
3594 11:08:31.065674 12, 0x0, sum = 1
3595 11:08:31.066321 13, 0x0, sum = 2
3596 11:08:31.069091 14, 0x0, sum = 3
3597 11:08:31.069561 15, 0x0, sum = 4
3598 11:08:31.069936 best_step = 13
3599 11:08:31.072740
3600 11:08:31.073198 ==
3601 11:08:31.076036 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 11:08:31.079747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 11:08:31.080370 ==
3604 11:08:31.080759 RX Vref Scan: 0
3605 11:08:31.081135
3606 11:08:31.082832 RX Vref 0 -> 0, step: 1
3607 11:08:31.083448
3608 11:08:31.085771 RX Delay -13 -> 252, step: 4
3609 11:08:31.089020 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3610 11:08:31.095920 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3611 11:08:31.099183 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3612 11:08:31.102978 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3613 11:08:31.106089 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3614 11:08:31.109105 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3615 11:08:31.115844 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3616 11:08:31.118927 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3617 11:08:31.122183 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3618 11:08:31.125753 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3619 11:08:31.129211 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3620 11:08:31.135911 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3621 11:08:31.139012 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3622 11:08:31.142183 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3623 11:08:31.145506 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3624 11:08:31.148946 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3625 11:08:31.152271 ==
3626 11:08:31.155774 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 11:08:31.159002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 11:08:31.159499 ==
3629 11:08:31.159878 DQS Delay:
3630 11:08:31.162191 DQS0 = 0, DQS1 = 0
3631 11:08:31.162676 DQM Delay:
3632 11:08:31.165727 DQM0 = 119, DQM1 = 113
3633 11:08:31.166247 DQ Delay:
3634 11:08:31.169071 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3635 11:08:31.172312 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3636 11:08:31.175460 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =108
3637 11:08:31.178840 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3638 11:08:31.179306
3639 11:08:31.179674
3640 11:08:31.188961 [DQSOSCAuto] RK1, (LSB)MR18= 0xaee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3641 11:08:31.189521 CH1 RK1: MR19=403, MR18=AEE
3642 11:08:31.195850 CH1_RK1: MR19=0x403, MR18=0xAEE, DQSOSC=406, MR23=63, INC=39, DEC=26
3643 11:08:31.199023 [RxdqsGatingPostProcess] freq 1200
3644 11:08:31.205630 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3645 11:08:31.209057 best DQS0 dly(2T, 0.5T) = (0, 11)
3646 11:08:31.212516 best DQS1 dly(2T, 0.5T) = (0, 11)
3647 11:08:31.215901 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3648 11:08:31.219199 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3649 11:08:31.222443 best DQS0 dly(2T, 0.5T) = (0, 11)
3650 11:08:31.223008 best DQS1 dly(2T, 0.5T) = (0, 11)
3651 11:08:31.225886 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3652 11:08:31.228828 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3653 11:08:31.231889 Pre-setting of DQS Precalculation
3654 11:08:31.238632 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3655 11:08:31.245241 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3656 11:08:31.252168 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3657 11:08:31.252748
3658 11:08:31.253117
3659 11:08:31.255219 [Calibration Summary] 2400 Mbps
3660 11:08:31.258794 CH 0, Rank 0
3661 11:08:31.259266 SW Impedance : PASS
3662 11:08:31.262187 DUTY Scan : NO K
3663 11:08:31.265191 ZQ Calibration : PASS
3664 11:08:31.265657 Jitter Meter : NO K
3665 11:08:31.268606 CBT Training : PASS
3666 11:08:31.269071 Write leveling : PASS
3667 11:08:31.272061 RX DQS gating : PASS
3668 11:08:31.275420 RX DQ/DQS(RDDQC) : PASS
3669 11:08:31.275912 TX DQ/DQS : PASS
3670 11:08:31.278503 RX DATLAT : PASS
3671 11:08:31.281871 RX DQ/DQS(Engine): PASS
3672 11:08:31.282388 TX OE : NO K
3673 11:08:31.285199 All Pass.
3674 11:08:31.285663
3675 11:08:31.286062 CH 0, Rank 1
3676 11:08:31.288565 SW Impedance : PASS
3677 11:08:31.289030 DUTY Scan : NO K
3678 11:08:31.291933 ZQ Calibration : PASS
3679 11:08:31.295262 Jitter Meter : NO K
3680 11:08:31.295736 CBT Training : PASS
3681 11:08:31.298480 Write leveling : PASS
3682 11:08:31.301733 RX DQS gating : PASS
3683 11:08:31.302230 RX DQ/DQS(RDDQC) : PASS
3684 11:08:31.304872 TX DQ/DQS : PASS
3685 11:08:31.308562 RX DATLAT : PASS
3686 11:08:31.309019 RX DQ/DQS(Engine): PASS
3687 11:08:31.311462 TX OE : NO K
3688 11:08:31.311927 All Pass.
3689 11:08:31.312292
3690 11:08:31.314826 CH 1, Rank 0
3691 11:08:31.315282 SW Impedance : PASS
3692 11:08:31.318416 DUTY Scan : NO K
3693 11:08:31.321743 ZQ Calibration : PASS
3694 11:08:31.322236 Jitter Meter : NO K
3695 11:08:31.325002 CBT Training : PASS
3696 11:08:31.328416 Write leveling : PASS
3697 11:08:31.328872 RX DQS gating : PASS
3698 11:08:31.331673 RX DQ/DQS(RDDQC) : PASS
3699 11:08:31.332130 TX DQ/DQS : PASS
3700 11:08:31.334928 RX DATLAT : PASS
3701 11:08:31.338374 RX DQ/DQS(Engine): PASS
3702 11:08:31.338834 TX OE : NO K
3703 11:08:31.341265 All Pass.
3704 11:08:31.341774
3705 11:08:31.342228 CH 1, Rank 1
3706 11:08:31.344613 SW Impedance : PASS
3707 11:08:31.345181 DUTY Scan : NO K
3708 11:08:31.348008 ZQ Calibration : PASS
3709 11:08:31.351352 Jitter Meter : NO K
3710 11:08:31.352147 CBT Training : PASS
3711 11:08:31.354490 Write leveling : PASS
3712 11:08:31.357797 RX DQS gating : PASS
3713 11:08:31.358313 RX DQ/DQS(RDDQC) : PASS
3714 11:08:31.361227 TX DQ/DQS : PASS
3715 11:08:31.364764 RX DATLAT : PASS
3716 11:08:31.365220 RX DQ/DQS(Engine): PASS
3717 11:08:31.367978 TX OE : NO K
3718 11:08:31.368439 All Pass.
3719 11:08:31.368891
3720 11:08:31.371489 DramC Write-DBI off
3721 11:08:31.374569 PER_BANK_REFRESH: Hybrid Mode
3722 11:08:31.375178 TX_TRACKING: ON
3723 11:08:31.384517 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3724 11:08:31.387733 [FAST_K] Save calibration result to emmc
3725 11:08:31.391157 dramc_set_vcore_voltage set vcore to 650000
3726 11:08:31.394652 Read voltage for 600, 5
3727 11:08:31.395131 Vio18 = 0
3728 11:08:31.395493 Vcore = 650000
3729 11:08:31.397859 Vdram = 0
3730 11:08:31.398361 Vddq = 0
3731 11:08:31.398726 Vmddr = 0
3732 11:08:31.404482 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3733 11:08:31.407782 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3734 11:08:31.411357 MEM_TYPE=3, freq_sel=19
3735 11:08:31.414561 sv_algorithm_assistance_LP4_1600
3736 11:08:31.417960 ============ PULL DRAM RESETB DOWN ============
3737 11:08:31.421205 ========== PULL DRAM RESETB DOWN end =========
3738 11:08:31.427843 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3739 11:08:31.431177 ===================================
3740 11:08:31.431640 LPDDR4 DRAM CONFIGURATION
3741 11:08:31.434277 ===================================
3742 11:08:31.437576 EX_ROW_EN[0] = 0x0
3743 11:08:31.440931 EX_ROW_EN[1] = 0x0
3744 11:08:31.441391 LP4Y_EN = 0x0
3745 11:08:31.444495 WORK_FSP = 0x0
3746 11:08:31.445026 WL = 0x2
3747 11:08:31.447610 RL = 0x2
3748 11:08:31.448072 BL = 0x2
3749 11:08:31.450614 RPST = 0x0
3750 11:08:31.451139 RD_PRE = 0x0
3751 11:08:31.453978 WR_PRE = 0x1
3752 11:08:31.454539 WR_PST = 0x0
3753 11:08:31.457402 DBI_WR = 0x0
3754 11:08:31.457863 DBI_RD = 0x0
3755 11:08:31.460861 OTF = 0x1
3756 11:08:31.464533 ===================================
3757 11:08:31.467594 ===================================
3758 11:08:31.468055 ANA top config
3759 11:08:31.470911 ===================================
3760 11:08:31.474194 DLL_ASYNC_EN = 0
3761 11:08:31.477630 ALL_SLAVE_EN = 1
3762 11:08:31.480981 NEW_RANK_MODE = 1
3763 11:08:31.481542 DLL_IDLE_MODE = 1
3764 11:08:31.483999 LP45_APHY_COMB_EN = 1
3765 11:08:31.487113 TX_ODT_DIS = 1
3766 11:08:31.490540 NEW_8X_MODE = 1
3767 11:08:31.493904 ===================================
3768 11:08:31.497216 ===================================
3769 11:08:31.500454 data_rate = 1200
3770 11:08:31.500871 CKR = 1
3771 11:08:31.504154 DQ_P2S_RATIO = 8
3772 11:08:31.507490 ===================================
3773 11:08:31.510849 CA_P2S_RATIO = 8
3774 11:08:31.513843 DQ_CA_OPEN = 0
3775 11:08:31.517054 DQ_SEMI_OPEN = 0
3776 11:08:31.520781 CA_SEMI_OPEN = 0
3777 11:08:31.521340 CA_FULL_RATE = 0
3778 11:08:31.524143 DQ_CKDIV4_EN = 1
3779 11:08:31.527247 CA_CKDIV4_EN = 1
3780 11:08:31.530483 CA_PREDIV_EN = 0
3781 11:08:31.533842 PH8_DLY = 0
3782 11:08:31.536978 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3783 11:08:31.537419 DQ_AAMCK_DIV = 4
3784 11:08:31.540229 CA_AAMCK_DIV = 4
3785 11:08:31.543579 CA_ADMCK_DIV = 4
3786 11:08:31.547170 DQ_TRACK_CA_EN = 0
3787 11:08:31.550452 CA_PICK = 600
3788 11:08:31.553736 CA_MCKIO = 600
3789 11:08:31.554275 MCKIO_SEMI = 0
3790 11:08:31.557026 PLL_FREQ = 2288
3791 11:08:31.560285 DQ_UI_PI_RATIO = 32
3792 11:08:31.563856 CA_UI_PI_RATIO = 0
3793 11:08:31.566866 ===================================
3794 11:08:31.570218 ===================================
3795 11:08:31.573669 memory_type:LPDDR4
3796 11:08:31.574123 GP_NUM : 10
3797 11:08:31.577051 SRAM_EN : 1
3798 11:08:31.579985 MD32_EN : 0
3799 11:08:31.583462 ===================================
3800 11:08:31.583950 [ANA_INIT] >>>>>>>>>>>>>>
3801 11:08:31.586731 <<<<<< [CONFIGURE PHASE]: ANA_TX
3802 11:08:31.590290 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3803 11:08:31.593462 ===================================
3804 11:08:31.596634 data_rate = 1200,PCW = 0X5800
3805 11:08:31.600002 ===================================
3806 11:08:31.603831 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3807 11:08:31.610109 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3808 11:08:31.613333 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3809 11:08:31.620048 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3810 11:08:31.623474 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3811 11:08:31.626866 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3812 11:08:31.627301 [ANA_INIT] flow start
3813 11:08:31.630047 [ANA_INIT] PLL >>>>>>>>
3814 11:08:31.633300 [ANA_INIT] PLL <<<<<<<<
3815 11:08:31.636617 [ANA_INIT] MIDPI >>>>>>>>
3816 11:08:31.637047 [ANA_INIT] MIDPI <<<<<<<<
3817 11:08:31.640048 [ANA_INIT] DLL >>>>>>>>
3818 11:08:31.643319 [ANA_INIT] flow end
3819 11:08:31.646742 ============ LP4 DIFF to SE enter ============
3820 11:08:31.649774 ============ LP4 DIFF to SE exit ============
3821 11:08:31.653174 [ANA_INIT] <<<<<<<<<<<<<
3822 11:08:31.656505 [Flow] Enable top DCM control >>>>>
3823 11:08:31.659879 [Flow] Enable top DCM control <<<<<
3824 11:08:31.663149 Enable DLL master slave shuffle
3825 11:08:31.666403 ==============================================================
3826 11:08:31.669719 Gating Mode config
3827 11:08:31.673250 ==============================================================
3828 11:08:31.676046 Config description:
3829 11:08:31.686133 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3830 11:08:31.693013 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3831 11:08:31.695946 SELPH_MODE 0: By rank 1: By Phase
3832 11:08:31.702769 ==============================================================
3833 11:08:31.705892 GAT_TRACK_EN = 1
3834 11:08:31.709191 RX_GATING_MODE = 2
3835 11:08:31.712552 RX_GATING_TRACK_MODE = 2
3836 11:08:31.716191 SELPH_MODE = 1
3837 11:08:31.719397 PICG_EARLY_EN = 1
3838 11:08:31.719481 VALID_LAT_VALUE = 1
3839 11:08:31.725913 ==============================================================
3840 11:08:31.729258 Enter into Gating configuration >>>>
3841 11:08:31.732557 Exit from Gating configuration <<<<
3842 11:08:31.736169 Enter into DVFS_PRE_config >>>>>
3843 11:08:31.745653 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3844 11:08:31.748935 Exit from DVFS_PRE_config <<<<<
3845 11:08:31.752588 Enter into PICG configuration >>>>
3846 11:08:31.755981 Exit from PICG configuration <<<<
3847 11:08:31.759306 [RX_INPUT] configuration >>>>>
3848 11:08:31.762484 [RX_INPUT] configuration <<<<<
3849 11:08:31.765858 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3850 11:08:31.772685 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3851 11:08:31.779159 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3852 11:08:31.786268 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3853 11:08:31.792430 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3854 11:08:31.795977 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3855 11:08:31.802605 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3856 11:08:31.805934 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3857 11:08:31.809110 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3858 11:08:31.812626 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3859 11:08:31.819323 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3860 11:08:31.822854 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3861 11:08:31.826101 ===================================
3862 11:08:31.829469 LPDDR4 DRAM CONFIGURATION
3863 11:08:31.832711 ===================================
3864 11:08:31.833175 EX_ROW_EN[0] = 0x0
3865 11:08:31.836059 EX_ROW_EN[1] = 0x0
3866 11:08:31.836635 LP4Y_EN = 0x0
3867 11:08:31.839129 WORK_FSP = 0x0
3868 11:08:31.839611 WL = 0x2
3869 11:08:31.843091 RL = 0x2
3870 11:08:31.843556 BL = 0x2
3871 11:08:31.846373 RPST = 0x0
3872 11:08:31.846834 RD_PRE = 0x0
3873 11:08:31.849677 WR_PRE = 0x1
3874 11:08:31.850181 WR_PST = 0x0
3875 11:08:31.852911 DBI_WR = 0x0
3876 11:08:31.853372 DBI_RD = 0x0
3877 11:08:31.856339 OTF = 0x1
3878 11:08:31.859564 ===================================
3879 11:08:31.862733 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3880 11:08:31.866377 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3881 11:08:31.872729 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3882 11:08:31.875973 ===================================
3883 11:08:31.879197 LPDDR4 DRAM CONFIGURATION
3884 11:08:31.882813 ===================================
3885 11:08:31.883286 EX_ROW_EN[0] = 0x10
3886 11:08:31.886261 EX_ROW_EN[1] = 0x0
3887 11:08:31.886732 LP4Y_EN = 0x0
3888 11:08:31.889457 WORK_FSP = 0x0
3889 11:08:31.890003 WL = 0x2
3890 11:08:31.892682 RL = 0x2
3891 11:08:31.893150 BL = 0x2
3892 11:08:31.896251 RPST = 0x0
3893 11:08:31.896875 RD_PRE = 0x0
3894 11:08:31.899545 WR_PRE = 0x1
3895 11:08:31.900003 WR_PST = 0x0
3896 11:08:31.902455 DBI_WR = 0x0
3897 11:08:31.902915 DBI_RD = 0x0
3898 11:08:31.906424 OTF = 0x1
3899 11:08:31.909298 ===================================
3900 11:08:31.915924 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3901 11:08:31.919151 nWR fixed to 30
3902 11:08:31.922376 [ModeRegInit_LP4] CH0 RK0
3903 11:08:31.922833 [ModeRegInit_LP4] CH0 RK1
3904 11:08:31.925810 [ModeRegInit_LP4] CH1 RK0
3905 11:08:31.929164 [ModeRegInit_LP4] CH1 RK1
3906 11:08:31.929621 match AC timing 17
3907 11:08:31.935675 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3908 11:08:31.938816 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3909 11:08:31.942285 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3910 11:08:31.948754 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3911 11:08:31.952027 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3912 11:08:31.952657 ==
3913 11:08:31.955262 Dram Type= 6, Freq= 0, CH_0, rank 0
3914 11:08:31.959053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3915 11:08:31.959623 ==
3916 11:08:31.965366 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3917 11:08:31.972172 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3918 11:08:31.975587 [CA 0] Center 36 (6~67) winsize 62
3919 11:08:31.978827 [CA 1] Center 36 (6~67) winsize 62
3920 11:08:31.982146 [CA 2] Center 34 (4~65) winsize 62
3921 11:08:31.985623 [CA 3] Center 34 (4~65) winsize 62
3922 11:08:31.988954 [CA 4] Center 34 (3~65) winsize 63
3923 11:08:31.992302 [CA 5] Center 33 (3~64) winsize 62
3924 11:08:31.992762
3925 11:08:31.995390 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3926 11:08:31.995852
3927 11:08:31.998621 [CATrainingPosCal] consider 1 rank data
3928 11:08:32.002458 u2DelayCellTimex100 = 270/100 ps
3929 11:08:32.005205 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3930 11:08:32.008456 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3931 11:08:32.011656 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3932 11:08:32.015314 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3933 11:08:32.018461 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3934 11:08:32.025329 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3935 11:08:32.025793
3936 11:08:32.028536 CA PerBit enable=1, Macro0, CA PI delay=33
3937 11:08:32.028998
3938 11:08:32.032029 [CBTSetCACLKResult] CA Dly = 33
3939 11:08:32.032491 CS Dly: 4 (0~35)
3940 11:08:32.032860 ==
3941 11:08:32.035268 Dram Type= 6, Freq= 0, CH_0, rank 1
3942 11:08:32.038458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3943 11:08:32.041798 ==
3944 11:08:32.045081 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3945 11:08:32.051552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3946 11:08:32.054812 [CA 0] Center 36 (6~67) winsize 62
3947 11:08:32.058739 [CA 1] Center 36 (6~67) winsize 62
3948 11:08:32.061851 [CA 2] Center 35 (4~66) winsize 63
3949 11:08:32.065185 [CA 3] Center 35 (4~66) winsize 63
3950 11:08:32.068326 [CA 4] Center 34 (4~65) winsize 62
3951 11:08:32.071564 [CA 5] Center 34 (3~65) winsize 63
3952 11:08:32.072052
3953 11:08:32.075016 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3954 11:08:32.075643
3955 11:08:32.078471 [CATrainingPosCal] consider 2 rank data
3956 11:08:32.081432 u2DelayCellTimex100 = 270/100 ps
3957 11:08:32.085181 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3958 11:08:32.088022 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3959 11:08:32.091756 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3960 11:08:32.098251 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3961 11:08:32.101473 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3962 11:08:32.104990 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3963 11:08:32.105447
3964 11:08:32.108227 CA PerBit enable=1, Macro0, CA PI delay=33
3965 11:08:32.108701
3966 11:08:32.111641 [CBTSetCACLKResult] CA Dly = 33
3967 11:08:32.112102 CS Dly: 4 (0~36)
3968 11:08:32.112467
3969 11:08:32.115187 ----->DramcWriteLeveling(PI) begin...
3970 11:08:32.115697 ==
3971 11:08:32.118248 Dram Type= 6, Freq= 0, CH_0, rank 0
3972 11:08:32.125134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3973 11:08:32.125598 ==
3974 11:08:32.128084 Write leveling (Byte 0): 34 => 34
3975 11:08:32.131420 Write leveling (Byte 1): 31 => 31
3976 11:08:32.131884 DramcWriteLeveling(PI) end<-----
3977 11:08:32.132255
3978 11:08:32.134621 ==
3979 11:08:32.138047 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 11:08:32.141493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 11:08:32.141989 ==
3982 11:08:32.144751 [Gating] SW mode calibration
3983 11:08:32.151444 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3984 11:08:32.154633 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3985 11:08:32.161006 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3986 11:08:32.164248 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 11:08:32.167703 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3988 11:08:32.174627 0 9 12 | B1->B0 | 3333 2e2e | 1 1 | (1 1) (1 1)
3989 11:08:32.177857 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
3990 11:08:32.181168 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 11:08:32.187672 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 11:08:32.190965 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 11:08:32.194427 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 11:08:32.200918 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 11:08:32.204426 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3996 11:08:32.207536 0 10 12 | B1->B0 | 2727 3f3f | 0 0 | (0 0) (0 0)
3997 11:08:32.214054 0 10 16 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
3998 11:08:32.217424 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 11:08:32.220654 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 11:08:32.227390 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 11:08:32.230797 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 11:08:32.234181 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 11:08:32.240632 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 11:08:32.244323 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 11:08:32.247543 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4006 11:08:32.254170 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 11:08:32.257444 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 11:08:32.260709 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 11:08:32.263963 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 11:08:32.270533 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 11:08:32.274189 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 11:08:32.277555 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 11:08:32.284198 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 11:08:32.287568 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 11:08:32.290480 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 11:08:32.297192 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 11:08:32.300495 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 11:08:32.304039 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 11:08:32.310737 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 11:08:32.314041 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4021 11:08:32.317356 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 11:08:32.320192 Total UI for P1: 0, mck2ui 16
4023 11:08:32.323526 best dqsien dly found for B0: ( 0, 13, 12)
4024 11:08:32.327316 Total UI for P1: 0, mck2ui 16
4025 11:08:32.330311 best dqsien dly found for B1: ( 0, 13, 14)
4026 11:08:32.333895 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4027 11:08:32.337337 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4028 11:08:32.340576
4029 11:08:32.343899 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4030 11:08:32.347065 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4031 11:08:32.350253 [Gating] SW calibration Done
4032 11:08:32.350772 ==
4033 11:08:32.353521 Dram Type= 6, Freq= 0, CH_0, rank 0
4034 11:08:32.356883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 11:08:32.357303 ==
4036 11:08:32.357634 RX Vref Scan: 0
4037 11:08:32.357998
4038 11:08:32.360171 RX Vref 0 -> 0, step: 1
4039 11:08:32.360581
4040 11:08:32.363313 RX Delay -230 -> 252, step: 16
4041 11:08:32.366838 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4042 11:08:32.373582 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4043 11:08:32.376877 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4044 11:08:32.379895 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4045 11:08:32.383313 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4046 11:08:32.386581 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4047 11:08:32.393030 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4048 11:08:32.396262 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4049 11:08:32.399745 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4050 11:08:32.403310 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4051 11:08:32.409936 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4052 11:08:32.413529 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4053 11:08:32.416405 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4054 11:08:32.419683 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4055 11:08:32.426628 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4056 11:08:32.430055 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4057 11:08:32.430522 ==
4058 11:08:32.433358 Dram Type= 6, Freq= 0, CH_0, rank 0
4059 11:08:32.436534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4060 11:08:32.437066 ==
4061 11:08:32.437536 DQS Delay:
4062 11:08:32.440044 DQS0 = 0, DQS1 = 0
4063 11:08:32.440566 DQM Delay:
4064 11:08:32.443411 DQM0 = 47, DQM1 = 38
4065 11:08:32.444035 DQ Delay:
4066 11:08:32.446888 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4067 11:08:32.449738 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4068 11:08:32.453073 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4069 11:08:32.456667 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4070 11:08:32.457275
4071 11:08:32.457839
4072 11:08:32.458477 ==
4073 11:08:32.459979 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 11:08:32.462934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 11:08:32.466594 ==
4076 11:08:32.467169
4077 11:08:32.467739
4078 11:08:32.468304 TX Vref Scan disable
4079 11:08:32.469642 == TX Byte 0 ==
4080 11:08:32.472812 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4081 11:08:32.479708 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4082 11:08:32.480127 == TX Byte 1 ==
4083 11:08:32.482885 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4084 11:08:32.489489 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4085 11:08:32.489918 ==
4086 11:08:32.493116 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 11:08:32.496410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 11:08:32.496836 ==
4089 11:08:32.497176
4090 11:08:32.497489
4091 11:08:32.499611 TX Vref Scan disable
4092 11:08:32.503026 == TX Byte 0 ==
4093 11:08:32.506283 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4094 11:08:32.509760 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4095 11:08:32.512949 == TX Byte 1 ==
4096 11:08:32.516361 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4097 11:08:32.519619 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4098 11:08:32.520046
4099 11:08:32.520386 [DATLAT]
4100 11:08:32.522731 Freq=600, CH0 RK0
4101 11:08:32.523155
4102 11:08:32.523495 DATLAT Default: 0x9
4103 11:08:32.525978 0, 0xFFFF, sum = 0
4104 11:08:32.529424 1, 0xFFFF, sum = 0
4105 11:08:32.530216 2, 0xFFFF, sum = 0
4106 11:08:32.532597 3, 0xFFFF, sum = 0
4107 11:08:32.533073 4, 0xFFFF, sum = 0
4108 11:08:32.536133 5, 0xFFFF, sum = 0
4109 11:08:32.536553 6, 0xFFFF, sum = 0
4110 11:08:32.539585 7, 0xFFFF, sum = 0
4111 11:08:32.540005 8, 0x0, sum = 1
4112 11:08:32.542619 9, 0x0, sum = 2
4113 11:08:32.543040 10, 0x0, sum = 3
4114 11:08:32.543375 11, 0x0, sum = 4
4115 11:08:32.545653 best_step = 9
4116 11:08:32.546043
4117 11:08:32.546396 ==
4118 11:08:32.549446 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 11:08:32.552463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 11:08:32.552917 ==
4121 11:08:32.555647 RX Vref Scan: 1
4122 11:08:32.556091
4123 11:08:32.556513 RX Vref 0 -> 0, step: 1
4124 11:08:32.559106
4125 11:08:32.559531 RX Delay -179 -> 252, step: 8
4126 11:08:32.559954
4127 11:08:32.562677 Set Vref, RX VrefLevel [Byte0]: 59
4128 11:08:32.565999 [Byte1]: 50
4129 11:08:32.570246
4130 11:08:32.570668 Final RX Vref Byte 0 = 59 to rank0
4131 11:08:32.573643 Final RX Vref Byte 1 = 50 to rank0
4132 11:08:32.576770 Final RX Vref Byte 0 = 59 to rank1
4133 11:08:32.580156 Final RX Vref Byte 1 = 50 to rank1==
4134 11:08:32.583517 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 11:08:32.590026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 11:08:32.590443 ==
4137 11:08:32.590775 DQS Delay:
4138 11:08:32.591084 DQS0 = 0, DQS1 = 0
4139 11:08:32.593497 DQM Delay:
4140 11:08:32.593836 DQM0 = 48, DQM1 = 40
4141 11:08:32.596654 DQ Delay:
4142 11:08:32.600240 DQ0 =44, DQ1 =44, DQ2 =44, DQ3 =44
4143 11:08:32.600831 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4144 11:08:32.603281 DQ8 =36, DQ9 =28, DQ10 =36, DQ11 =32
4145 11:08:32.609869 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =52
4146 11:08:32.610332
4147 11:08:32.610667
4148 11:08:32.616573 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c56, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4149 11:08:32.620223 CH0 RK0: MR19=808, MR18=5C56
4150 11:08:32.627024 CH0_RK0: MR19=0x808, MR18=0x5C56, DQSOSC=392, MR23=63, INC=170, DEC=113
4151 11:08:32.627455
4152 11:08:32.630411 ----->DramcWriteLeveling(PI) begin...
4153 11:08:32.630884 ==
4154 11:08:32.633603 Dram Type= 6, Freq= 0, CH_0, rank 1
4155 11:08:32.636845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 11:08:32.637267 ==
4157 11:08:32.640106 Write leveling (Byte 0): 31 => 31
4158 11:08:32.643547 Write leveling (Byte 1): 30 => 30
4159 11:08:32.646815 DramcWriteLeveling(PI) end<-----
4160 11:08:32.647324
4161 11:08:32.647665 ==
4162 11:08:32.650040 Dram Type= 6, Freq= 0, CH_0, rank 1
4163 11:08:32.653012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 11:08:32.653504 ==
4165 11:08:32.656703 [Gating] SW mode calibration
4166 11:08:32.663266 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4167 11:08:32.669885 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4168 11:08:32.673237 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4169 11:08:32.676546 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4170 11:08:32.683301 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 11:08:32.686291 0 9 12 | B1->B0 | 3333 3131 | 1 1 | (1 0) (1 0)
4172 11:08:32.689969 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4173 11:08:32.695814 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 11:08:32.699264 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 11:08:32.702516 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 11:08:32.709433 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 11:08:32.712758 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 11:08:32.715926 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 11:08:32.723033 0 10 12 | B1->B0 | 2d2d 3030 | 0 1 | (0 0) (0 0)
4180 11:08:32.726250 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 11:08:32.729426 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 11:08:32.736196 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 11:08:32.739491 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 11:08:32.742851 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 11:08:32.749352 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 11:08:32.752688 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 11:08:32.755989 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4188 11:08:32.763315 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 11:08:32.766473 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 11:08:32.769312 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 11:08:32.776277 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 11:08:32.779639 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 11:08:32.782831 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 11:08:32.789332 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 11:08:32.792836 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 11:08:32.796130 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 11:08:32.799657 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 11:08:32.805825 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 11:08:32.809593 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 11:08:32.812866 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 11:08:32.819707 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 11:08:32.822828 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 11:08:32.826117 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4204 11:08:32.829575 Total UI for P1: 0, mck2ui 16
4205 11:08:32.832892 best dqsien dly found for B0: ( 0, 13, 10)
4206 11:08:32.839226 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 11:08:32.842588 Total UI for P1: 0, mck2ui 16
4208 11:08:32.845842 best dqsien dly found for B1: ( 0, 13, 12)
4209 11:08:32.849120 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4210 11:08:32.852469 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4211 11:08:32.852933
4212 11:08:32.856180 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4213 11:08:32.859033 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4214 11:08:32.862366 [Gating] SW calibration Done
4215 11:08:32.862846 ==
4216 11:08:32.865789 Dram Type= 6, Freq= 0, CH_0, rank 1
4217 11:08:32.868776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4218 11:08:32.869349 ==
4219 11:08:32.872407 RX Vref Scan: 0
4220 11:08:32.872890
4221 11:08:32.875622 RX Vref 0 -> 0, step: 1
4222 11:08:32.876167
4223 11:08:32.876547 RX Delay -230 -> 252, step: 16
4224 11:08:32.882270 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4225 11:08:32.885822 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4226 11:08:32.889162 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4227 11:08:32.892131 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4228 11:08:32.899264 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4229 11:08:32.902360 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4230 11:08:32.905637 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4231 11:08:32.908904 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4232 11:08:32.912181 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4233 11:08:32.919154 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4234 11:08:32.922409 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4235 11:08:32.925760 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4236 11:08:32.928998 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4237 11:08:32.935488 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4238 11:08:32.938795 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4239 11:08:32.942501 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4240 11:08:32.942969 ==
4241 11:08:32.945858 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 11:08:32.949096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 11:08:32.952405 ==
4244 11:08:32.952873 DQS Delay:
4245 11:08:32.953245 DQS0 = 0, DQS1 = 0
4246 11:08:32.955724 DQM Delay:
4247 11:08:32.956223 DQM0 = 51, DQM1 = 42
4248 11:08:32.958941 DQ Delay:
4249 11:08:32.959405 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4250 11:08:32.962255 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4251 11:08:32.965573 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4252 11:08:32.969004 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4253 11:08:32.969470
4254 11:08:32.971992
4255 11:08:32.972456 ==
4256 11:08:32.975234 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 11:08:32.978546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 11:08:32.979014 ==
4259 11:08:32.979379
4260 11:08:32.979717
4261 11:08:32.982196 TX Vref Scan disable
4262 11:08:32.982660 == TX Byte 0 ==
4263 11:08:32.988762 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4264 11:08:32.992247 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4265 11:08:32.992726 == TX Byte 1 ==
4266 11:08:32.998583 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4267 11:08:33.002230 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4268 11:08:33.002881 ==
4269 11:08:33.004919 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 11:08:33.008708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 11:08:33.009331 ==
4272 11:08:33.009916
4273 11:08:33.010490
4274 11:08:33.012075 TX Vref Scan disable
4275 11:08:33.015206 == TX Byte 0 ==
4276 11:08:33.018322 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4277 11:08:33.021372 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4278 11:08:33.024791 == TX Byte 1 ==
4279 11:08:33.028090 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4280 11:08:33.031267 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4281 11:08:33.031350
4282 11:08:33.034869 [DATLAT]
4283 11:08:33.034950 Freq=600, CH0 RK1
4284 11:08:33.035016
4285 11:08:33.038225 DATLAT Default: 0x9
4286 11:08:33.038306 0, 0xFFFF, sum = 0
4287 11:08:33.041469 1, 0xFFFF, sum = 0
4288 11:08:33.041648 2, 0xFFFF, sum = 0
4289 11:08:33.044601 3, 0xFFFF, sum = 0
4290 11:08:33.044752 4, 0xFFFF, sum = 0
4291 11:08:33.048035 5, 0xFFFF, sum = 0
4292 11:08:33.048131 6, 0xFFFF, sum = 0
4293 11:08:33.051262 7, 0xFFFF, sum = 0
4294 11:08:33.051363 8, 0x0, sum = 1
4295 11:08:33.054637 9, 0x0, sum = 2
4296 11:08:33.054747 10, 0x0, sum = 3
4297 11:08:33.057897 11, 0x0, sum = 4
4298 11:08:33.058019 best_step = 9
4299 11:08:33.058106
4300 11:08:33.058187 ==
4301 11:08:33.061087 Dram Type= 6, Freq= 0, CH_0, rank 1
4302 11:08:33.067679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4303 11:08:33.067760 ==
4304 11:08:33.067824 RX Vref Scan: 0
4305 11:08:33.067883
4306 11:08:33.071091 RX Vref 0 -> 0, step: 1
4307 11:08:33.071176
4308 11:08:33.074447 RX Delay -179 -> 252, step: 8
4309 11:08:33.077850 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4310 11:08:33.084156 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4311 11:08:33.087726 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4312 11:08:33.090890 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4313 11:08:33.094496 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4314 11:08:33.097386 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4315 11:08:33.104011 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4316 11:08:33.107770 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4317 11:08:33.110753 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4318 11:08:33.114207 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4319 11:08:33.117529 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4320 11:08:33.124100 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4321 11:08:33.127545 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4322 11:08:33.130500 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4323 11:08:33.134172 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4324 11:08:33.140670 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4325 11:08:33.140750 ==
4326 11:08:33.143942 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 11:08:33.147097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 11:08:33.147179 ==
4329 11:08:33.147242 DQS Delay:
4330 11:08:33.150389 DQS0 = 0, DQS1 = 0
4331 11:08:33.150469 DQM Delay:
4332 11:08:33.154040 DQM0 = 48, DQM1 = 40
4333 11:08:33.154147 DQ Delay:
4334 11:08:33.157399 DQ0 =44, DQ1 =48, DQ2 =48, DQ3 =44
4335 11:08:33.160675 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4336 11:08:33.164092 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4337 11:08:33.167218 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =44
4338 11:08:33.167298
4339 11:08:33.167361
4340 11:08:33.174144 [DQSOSCAuto] RK1, (LSB)MR18= 0x612e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
4341 11:08:33.176947 CH0 RK1: MR19=808, MR18=612E
4342 11:08:33.183442 CH0_RK1: MR19=0x808, MR18=0x612E, DQSOSC=391, MR23=63, INC=171, DEC=114
4343 11:08:33.187353 [RxdqsGatingPostProcess] freq 600
4344 11:08:33.193688 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4345 11:08:33.196964 Pre-setting of DQS Precalculation
4346 11:08:33.200081 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4347 11:08:33.200224 ==
4348 11:08:33.203824 Dram Type= 6, Freq= 0, CH_1, rank 0
4349 11:08:33.206836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 11:08:33.206989 ==
4351 11:08:33.213433 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4352 11:08:33.220305 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4353 11:08:33.223540 [CA 0] Center 35 (5~66) winsize 62
4354 11:08:33.226905 [CA 1] Center 35 (5~66) winsize 62
4355 11:08:33.230406 [CA 2] Center 34 (4~64) winsize 61
4356 11:08:33.233772 [CA 3] Center 33 (3~64) winsize 62
4357 11:08:33.237116 [CA 4] Center 34 (3~65) winsize 63
4358 11:08:33.240396 [CA 5] Center 33 (3~64) winsize 62
4359 11:08:33.240858
4360 11:08:33.243943 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4361 11:08:33.244415
4362 11:08:33.247193 [CATrainingPosCal] consider 1 rank data
4363 11:08:33.250517 u2DelayCellTimex100 = 270/100 ps
4364 11:08:33.253799 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4365 11:08:33.257082 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4366 11:08:33.260436 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4367 11:08:33.263607 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4368 11:08:33.270394 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4369 11:08:33.273759 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4370 11:08:33.274245
4371 11:08:33.277050 CA PerBit enable=1, Macro0, CA PI delay=33
4372 11:08:33.277513
4373 11:08:33.280368 [CBTSetCACLKResult] CA Dly = 33
4374 11:08:33.280870 CS Dly: 5 (0~36)
4375 11:08:33.281247 ==
4376 11:08:33.283731 Dram Type= 6, Freq= 0, CH_1, rank 1
4377 11:08:33.287039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 11:08:33.290576 ==
4379 11:08:33.293660 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4380 11:08:33.300456 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4381 11:08:33.303498 [CA 0] Center 35 (5~66) winsize 62
4382 11:08:33.307044 [CA 1] Center 35 (5~66) winsize 62
4383 11:08:33.310141 [CA 2] Center 34 (4~65) winsize 62
4384 11:08:33.313492 [CA 3] Center 34 (4~65) winsize 62
4385 11:08:33.316878 [CA 4] Center 34 (4~65) winsize 62
4386 11:08:33.320178 [CA 5] Center 33 (3~64) winsize 62
4387 11:08:33.320709
4388 11:08:33.323300 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4389 11:08:33.323764
4390 11:08:33.326840 [CATrainingPosCal] consider 2 rank data
4391 11:08:33.330062 u2DelayCellTimex100 = 270/100 ps
4392 11:08:33.333385 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4393 11:08:33.336581 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4394 11:08:33.339942 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4395 11:08:33.343275 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4396 11:08:33.350202 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4397 11:08:33.353315 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4398 11:08:33.353779
4399 11:08:33.357006 CA PerBit enable=1, Macro0, CA PI delay=33
4400 11:08:33.357426
4401 11:08:33.360069 [CBTSetCACLKResult] CA Dly = 33
4402 11:08:33.360537 CS Dly: 4 (0~35)
4403 11:08:33.360934
4404 11:08:33.363397 ----->DramcWriteLeveling(PI) begin...
4405 11:08:33.363964 ==
4406 11:08:33.366745 Dram Type= 6, Freq= 0, CH_1, rank 0
4407 11:08:33.373177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 11:08:33.373827 ==
4409 11:08:33.376427 Write leveling (Byte 0): 28 => 28
4410 11:08:33.380033 Write leveling (Byte 1): 28 => 28
4411 11:08:33.380760 DramcWriteLeveling(PI) end<-----
4412 11:08:33.381415
4413 11:08:33.383537 ==
4414 11:08:33.386467 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 11:08:33.389802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 11:08:33.390334 ==
4417 11:08:33.393269 [Gating] SW mode calibration
4418 11:08:33.400076 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4419 11:08:33.403245 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4420 11:08:33.409667 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4421 11:08:33.412932 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4422 11:08:33.416524 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
4423 11:08:33.423130 0 9 12 | B1->B0 | 2c2c 2c2c | 0 0 | (0 0) (1 0)
4424 11:08:33.426535 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 11:08:33.429569 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 11:08:33.436547 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 11:08:33.439806 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 11:08:33.443189 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 11:08:33.449550 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 11:08:33.452717 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4431 11:08:33.456074 0 10 12 | B1->B0 | 3a3a 3a3a | 0 0 | (0 0) (1 1)
4432 11:08:33.462741 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 11:08:33.466022 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 11:08:33.469369 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 11:08:33.476043 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 11:08:33.479217 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 11:08:33.482522 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 11:08:33.489381 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 11:08:33.492740 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4440 11:08:33.496075 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 11:08:33.502485 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 11:08:33.506179 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 11:08:33.509371 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:08:33.512605 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 11:08:33.519827 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 11:08:33.522354 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 11:08:33.525841 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 11:08:33.532355 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 11:08:33.535986 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 11:08:33.539022 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 11:08:33.545880 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 11:08:33.549153 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 11:08:33.552397 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 11:08:33.558902 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4455 11:08:33.562319 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 11:08:33.565846 Total UI for P1: 0, mck2ui 16
4457 11:08:33.569005 best dqsien dly found for B0: ( 0, 13, 8)
4458 11:08:33.572596 Total UI for P1: 0, mck2ui 16
4459 11:08:33.575533 best dqsien dly found for B1: ( 0, 13, 8)
4460 11:08:33.578834 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4461 11:08:33.582307 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4462 11:08:33.582778
4463 11:08:33.585619 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4464 11:08:33.588844 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4465 11:08:33.592100 [Gating] SW calibration Done
4466 11:08:33.592516 ==
4467 11:08:33.595483 Dram Type= 6, Freq= 0, CH_1, rank 0
4468 11:08:33.598928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4469 11:08:33.602302 ==
4470 11:08:33.602867 RX Vref Scan: 0
4471 11:08:33.603266
4472 11:08:33.605443 RX Vref 0 -> 0, step: 1
4473 11:08:33.605905
4474 11:08:33.608963 RX Delay -230 -> 252, step: 16
4475 11:08:33.612175 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4476 11:08:33.615749 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4477 11:08:33.618765 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4478 11:08:33.622237 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4479 11:08:33.628555 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4480 11:08:33.632137 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4481 11:08:33.635219 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4482 11:08:33.638753 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4483 11:08:33.645088 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4484 11:08:33.648686 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4485 11:08:33.652332 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4486 11:08:33.655599 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4487 11:08:33.658809 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4488 11:08:33.665529 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4489 11:08:33.668462 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4490 11:08:33.672109 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4491 11:08:33.672690 ==
4492 11:08:33.675321 Dram Type= 6, Freq= 0, CH_1, rank 0
4493 11:08:33.682025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4494 11:08:33.682527 ==
4495 11:08:33.682923 DQS Delay:
4496 11:08:33.683284 DQS0 = 0, DQS1 = 0
4497 11:08:33.685417 DQM Delay:
4498 11:08:33.685873 DQM0 = 52, DQM1 = 44
4499 11:08:33.688795 DQ Delay:
4500 11:08:33.691863 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4501 11:08:33.695052 DQ4 =49, DQ5 =57, DQ6 =65, DQ7 =49
4502 11:08:33.698377 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4503 11:08:33.701723 DQ12 =57, DQ13 =57, DQ14 =41, DQ15 =57
4504 11:08:33.702275
4505 11:08:33.702844
4506 11:08:33.703254 ==
4507 11:08:33.705076 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 11:08:33.707968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 11:08:33.708499 ==
4510 11:08:33.708890
4511 11:08:33.709242
4512 11:08:33.711588 TX Vref Scan disable
4513 11:08:33.712132 == TX Byte 0 ==
4514 11:08:33.718066 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4515 11:08:33.721652 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4516 11:08:33.722362 == TX Byte 1 ==
4517 11:08:33.728195 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4518 11:08:33.731407 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4519 11:08:33.731875 ==
4520 11:08:33.734641 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 11:08:33.737975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 11:08:33.738476 ==
4523 11:08:33.741483
4524 11:08:33.741984
4525 11:08:33.742368 TX Vref Scan disable
4526 11:08:33.744900 == TX Byte 0 ==
4527 11:08:33.748072 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4528 11:08:33.754580 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4529 11:08:33.755050 == TX Byte 1 ==
4530 11:08:33.757998 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4531 11:08:33.764788 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4532 11:08:33.765259
4533 11:08:33.765738 [DATLAT]
4534 11:08:33.766157 Freq=600, CH1 RK0
4535 11:08:33.766509
4536 11:08:33.768134 DATLAT Default: 0x9
4537 11:08:33.768600 0, 0xFFFF, sum = 0
4538 11:08:33.771451 1, 0xFFFF, sum = 0
4539 11:08:33.771921 2, 0xFFFF, sum = 0
4540 11:08:33.774735 3, 0xFFFF, sum = 0
4541 11:08:33.777828 4, 0xFFFF, sum = 0
4542 11:08:33.778359 5, 0xFFFF, sum = 0
4543 11:08:33.781109 6, 0xFFFF, sum = 0
4544 11:08:33.781573 7, 0xFFFF, sum = 0
4545 11:08:33.784768 8, 0x0, sum = 1
4546 11:08:33.785332 9, 0x0, sum = 2
4547 11:08:33.785707 10, 0x0, sum = 3
4548 11:08:33.788106 11, 0x0, sum = 4
4549 11:08:33.788674 best_step = 9
4550 11:08:33.789041
4551 11:08:33.789382 ==
4552 11:08:33.791232 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 11:08:33.798107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 11:08:33.798630 ==
4555 11:08:33.798999 RX Vref Scan: 1
4556 11:08:33.799389
4557 11:08:33.801070 RX Vref 0 -> 0, step: 1
4558 11:08:33.801727
4559 11:08:33.804359 RX Delay -163 -> 252, step: 8
4560 11:08:33.804996
4561 11:08:33.807823 Set Vref, RX VrefLevel [Byte0]: 51
4562 11:08:33.811498 [Byte1]: 52
4563 11:08:33.811959
4564 11:08:33.814370 Final RX Vref Byte 0 = 51 to rank0
4565 11:08:33.817514 Final RX Vref Byte 1 = 52 to rank0
4566 11:08:33.821091 Final RX Vref Byte 0 = 51 to rank1
4567 11:08:33.824250 Final RX Vref Byte 1 = 52 to rank1==
4568 11:08:33.827620 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 11:08:33.830944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 11:08:33.831405 ==
4571 11:08:33.834529 DQS Delay:
4572 11:08:33.834986 DQS0 = 0, DQS1 = 0
4573 11:08:33.837725 DQM Delay:
4574 11:08:33.838341 DQM0 = 48, DQM1 = 41
4575 11:08:33.838711 DQ Delay:
4576 11:08:33.840948 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4577 11:08:33.844272 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4578 11:08:33.847689 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =36
4579 11:08:33.851273 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4580 11:08:33.851843
4581 11:08:33.852213
4582 11:08:33.860811 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4583 11:08:33.863860 CH1 RK0: MR19=808, MR18=4A71
4584 11:08:33.870605 CH1_RK0: MR19=0x808, MR18=0x4A71, DQSOSC=388, MR23=63, INC=174, DEC=116
4585 11:08:33.871072
4586 11:08:33.873862 ----->DramcWriteLeveling(PI) begin...
4587 11:08:33.874353 ==
4588 11:08:33.877064 Dram Type= 6, Freq= 0, CH_1, rank 1
4589 11:08:33.880596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 11:08:33.881076 ==
4591 11:08:33.883724 Write leveling (Byte 0): 29 => 29
4592 11:08:33.887251 Write leveling (Byte 1): 30 => 30
4593 11:08:33.890519 DramcWriteLeveling(PI) end<-----
4594 11:08:33.891033
4595 11:08:33.891404 ==
4596 11:08:33.893892 Dram Type= 6, Freq= 0, CH_1, rank 1
4597 11:08:33.897391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 11:08:33.898014 ==
4599 11:08:33.900606 [Gating] SW mode calibration
4600 11:08:33.907470 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4601 11:08:33.913999 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4602 11:08:33.917280 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4603 11:08:33.920595 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4604 11:08:33.927317 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
4605 11:08:33.930693 0 9 12 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 0)
4606 11:08:33.934122 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4607 11:08:33.940371 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 11:08:33.943927 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 11:08:33.947184 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 11:08:33.953998 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 11:08:33.956968 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 11:08:33.960438 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 11:08:33.967070 0 10 12 | B1->B0 | 4040 3232 | 0 0 | (0 0) (0 0)
4614 11:08:33.970208 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4615 11:08:33.973444 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 11:08:33.976787 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 11:08:33.983894 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 11:08:33.986993 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 11:08:33.990418 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 11:08:33.996901 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4621 11:08:34.000208 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4622 11:08:34.003619 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 11:08:34.010398 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 11:08:34.013681 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 11:08:34.016839 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 11:08:34.023594 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 11:08:34.027049 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 11:08:34.030520 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 11:08:34.037208 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 11:08:34.040499 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 11:08:34.043804 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 11:08:34.050495 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 11:08:34.053481 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 11:08:34.057108 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 11:08:34.063480 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 11:08:34.067009 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 11:08:34.069934 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4638 11:08:34.073041 Total UI for P1: 0, mck2ui 16
4639 11:08:34.076390 best dqsien dly found for B1: ( 0, 13, 10)
4640 11:08:34.083241 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 11:08:34.083681 Total UI for P1: 0, mck2ui 16
4642 11:08:34.086622 best dqsien dly found for B0: ( 0, 13, 12)
4643 11:08:34.093576 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4644 11:08:34.096736 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4645 11:08:34.097166
4646 11:08:34.100100 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4647 11:08:34.103393 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4648 11:08:34.106186 [Gating] SW calibration Done
4649 11:08:34.106605 ==
4650 11:08:34.110005 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 11:08:34.113079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 11:08:34.113502 ==
4653 11:08:34.116707 RX Vref Scan: 0
4654 11:08:34.117173
4655 11:08:34.117540 RX Vref 0 -> 0, step: 1
4656 11:08:34.117880
4657 11:08:34.119986 RX Delay -230 -> 252, step: 16
4658 11:08:34.123185 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4659 11:08:34.129980 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4660 11:08:34.133020 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4661 11:08:34.136560 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4662 11:08:34.139749 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4663 11:08:34.143162 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4664 11:08:34.149686 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4665 11:08:34.153097 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4666 11:08:34.156599 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4667 11:08:34.160503 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4668 11:08:34.166394 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4669 11:08:34.169983 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4670 11:08:34.173040 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4671 11:08:34.176396 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4672 11:08:34.183011 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4673 11:08:34.186455 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4674 11:08:34.186921 ==
4675 11:08:34.189805 Dram Type= 6, Freq= 0, CH_1, rank 1
4676 11:08:34.193116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4677 11:08:34.193583 ==
4678 11:08:34.193983 DQS Delay:
4679 11:08:34.196163 DQS0 = 0, DQS1 = 0
4680 11:08:34.196628 DQM Delay:
4681 11:08:34.199551 DQM0 = 52, DQM1 = 45
4682 11:08:34.200016 DQ Delay:
4683 11:08:34.203090 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4684 11:08:34.206231 DQ4 =57, DQ5 =65, DQ6 =57, DQ7 =49
4685 11:08:34.209510 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4686 11:08:34.212841 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =65
4687 11:08:34.213307
4688 11:08:34.213676
4689 11:08:34.214070 ==
4690 11:08:34.216124 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 11:08:34.219669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 11:08:34.222721 ==
4693 11:08:34.223205
4694 11:08:34.223570
4695 11:08:34.223912 TX Vref Scan disable
4696 11:08:34.226011 == TX Byte 0 ==
4697 11:08:34.229318 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4698 11:08:34.235937 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4699 11:08:34.236362 == TX Byte 1 ==
4700 11:08:34.239562 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4701 11:08:34.245711 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4702 11:08:34.246299 ==
4703 11:08:34.249509 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 11:08:34.252795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 11:08:34.253218 ==
4706 11:08:34.253553
4707 11:08:34.253862
4708 11:08:34.256198 TX Vref Scan disable
4709 11:08:34.256668 == TX Byte 0 ==
4710 11:08:34.262612 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4711 11:08:34.266026 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4712 11:08:34.266480 == TX Byte 1 ==
4713 11:08:34.272655 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4714 11:08:34.276185 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4715 11:08:34.276682
4716 11:08:34.277109 [DATLAT]
4717 11:08:34.279203 Freq=600, CH1 RK1
4718 11:08:34.279637
4719 11:08:34.280065 DATLAT Default: 0x9
4720 11:08:34.282810 0, 0xFFFF, sum = 0
4721 11:08:34.283294 1, 0xFFFF, sum = 0
4722 11:08:34.285984 2, 0xFFFF, sum = 0
4723 11:08:34.286471 3, 0xFFFF, sum = 0
4724 11:08:34.289193 4, 0xFFFF, sum = 0
4725 11:08:34.292494 5, 0xFFFF, sum = 0
4726 11:08:34.292936 6, 0xFFFF, sum = 0
4727 11:08:34.295842 7, 0xFFFF, sum = 0
4728 11:08:34.296426 8, 0x0, sum = 1
4729 11:08:34.296978 9, 0x0, sum = 2
4730 11:08:34.299431 10, 0x0, sum = 3
4731 11:08:34.299862 11, 0x0, sum = 4
4732 11:08:34.302571 best_step = 9
4733 11:08:34.303029
4734 11:08:34.303437 ==
4735 11:08:34.305784 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 11:08:34.309203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 11:08:34.309701 ==
4738 11:08:34.312458 RX Vref Scan: 0
4739 11:08:34.312920
4740 11:08:34.313285 RX Vref 0 -> 0, step: 1
4741 11:08:34.313670
4742 11:08:34.315856 RX Delay -163 -> 252, step: 8
4743 11:08:34.323056 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4744 11:08:34.326411 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4745 11:08:34.329642 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4746 11:08:34.333052 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4747 11:08:34.336309 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4748 11:08:34.342993 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4749 11:08:34.346323 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4750 11:08:34.349246 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4751 11:08:34.352831 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4752 11:08:34.356025 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4753 11:08:34.362911 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4754 11:08:34.365930 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4755 11:08:34.369445 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4756 11:08:34.372829 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4757 11:08:34.379220 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4758 11:08:34.382807 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4759 11:08:34.382987 ==
4760 11:08:34.385914 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 11:08:34.389357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 11:08:34.389508 ==
4763 11:08:34.392601 DQS Delay:
4764 11:08:34.392751 DQS0 = 0, DQS1 = 0
4765 11:08:34.392871 DQM Delay:
4766 11:08:34.395873 DQM0 = 49, DQM1 = 44
4767 11:08:34.396021 DQ Delay:
4768 11:08:34.399637 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =48
4769 11:08:34.402643 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4770 11:08:34.405612 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4771 11:08:34.409248 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4772 11:08:34.409399
4773 11:08:34.409518
4774 11:08:34.419078 [DQSOSCAuto] RK1, (LSB)MR18= 0x561d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4775 11:08:34.419253 CH1 RK1: MR19=808, MR18=561D
4776 11:08:34.425880 CH1_RK1: MR19=0x808, MR18=0x561D, DQSOSC=393, MR23=63, INC=169, DEC=113
4777 11:08:34.429176 [RxdqsGatingPostProcess] freq 600
4778 11:08:34.435929 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4779 11:08:34.439907 Pre-setting of DQS Precalculation
4780 11:08:34.443044 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4781 11:08:34.449508 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4782 11:08:34.459537 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4783 11:08:34.459960
4784 11:08:34.460293
4785 11:08:34.460601 [Calibration Summary] 1200 Mbps
4786 11:08:34.462894 CH 0, Rank 0
4787 11:08:34.466037 SW Impedance : PASS
4788 11:08:34.466459 DUTY Scan : NO K
4789 11:08:34.469757 ZQ Calibration : PASS
4790 11:08:34.470356 Jitter Meter : NO K
4791 11:08:34.472826 CBT Training : PASS
4792 11:08:34.476067 Write leveling : PASS
4793 11:08:34.476634 RX DQS gating : PASS
4794 11:08:34.479303 RX DQ/DQS(RDDQC) : PASS
4795 11:08:34.482714 TX DQ/DQS : PASS
4796 11:08:34.483178 RX DATLAT : PASS
4797 11:08:34.486328 RX DQ/DQS(Engine): PASS
4798 11:08:34.489094 TX OE : NO K
4799 11:08:34.489559 All Pass.
4800 11:08:34.489929
4801 11:08:34.490328 CH 0, Rank 1
4802 11:08:34.492810 SW Impedance : PASS
4803 11:08:34.495995 DUTY Scan : NO K
4804 11:08:34.496463 ZQ Calibration : PASS
4805 11:08:34.499270 Jitter Meter : NO K
4806 11:08:34.502373 CBT Training : PASS
4807 11:08:34.502837 Write leveling : PASS
4808 11:08:34.505799 RX DQS gating : PASS
4809 11:08:34.509344 RX DQ/DQS(RDDQC) : PASS
4810 11:08:34.509810 TX DQ/DQS : PASS
4811 11:08:34.512548 RX DATLAT : PASS
4812 11:08:34.515976 RX DQ/DQS(Engine): PASS
4813 11:08:34.516446 TX OE : NO K
4814 11:08:34.516819 All Pass.
4815 11:08:34.517168
4816 11:08:34.519249 CH 1, Rank 0
4817 11:08:34.522072 SW Impedance : PASS
4818 11:08:34.522497 DUTY Scan : NO K
4819 11:08:34.525775 ZQ Calibration : PASS
4820 11:08:34.526287 Jitter Meter : NO K
4821 11:08:34.529269 CBT Training : PASS
4822 11:08:34.532060 Write leveling : PASS
4823 11:08:34.532528 RX DQS gating : PASS
4824 11:08:34.535398 RX DQ/DQS(RDDQC) : PASS
4825 11:08:34.539129 TX DQ/DQS : PASS
4826 11:08:34.539596 RX DATLAT : PASS
4827 11:08:34.542481 RX DQ/DQS(Engine): PASS
4828 11:08:34.545705 TX OE : NO K
4829 11:08:34.546369 All Pass.
4830 11:08:34.546748
4831 11:08:34.547092 CH 1, Rank 1
4832 11:08:34.548958 SW Impedance : PASS
4833 11:08:34.552076 DUTY Scan : NO K
4834 11:08:34.552639 ZQ Calibration : PASS
4835 11:08:34.555783 Jitter Meter : NO K
4836 11:08:34.558796 CBT Training : PASS
4837 11:08:34.559266 Write leveling : PASS
4838 11:08:34.562418 RX DQS gating : PASS
4839 11:08:34.565764 RX DQ/DQS(RDDQC) : PASS
4840 11:08:34.566394 TX DQ/DQS : PASS
4841 11:08:34.569047 RX DATLAT : PASS
4842 11:08:34.572030 RX DQ/DQS(Engine): PASS
4843 11:08:34.572614 TX OE : NO K
4844 11:08:34.573101 All Pass.
4845 11:08:34.575312
4846 11:08:34.575781 DramC Write-DBI off
4847 11:08:34.578403 PER_BANK_REFRESH: Hybrid Mode
4848 11:08:34.578879 TX_TRACKING: ON
4849 11:08:34.588644 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4850 11:08:34.592571 [FAST_K] Save calibration result to emmc
4851 11:08:34.595725 dramc_set_vcore_voltage set vcore to 662500
4852 11:08:34.598791 Read voltage for 933, 3
4853 11:08:34.599263 Vio18 = 0
4854 11:08:34.602089 Vcore = 662500
4855 11:08:34.602675 Vdram = 0
4856 11:08:34.603158 Vddq = 0
4857 11:08:34.603606 Vmddr = 0
4858 11:08:34.608559 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4859 11:08:34.615397 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4860 11:08:34.615997 MEM_TYPE=3, freq_sel=17
4861 11:08:34.618651 sv_algorithm_assistance_LP4_1600
4862 11:08:34.621912 ============ PULL DRAM RESETB DOWN ============
4863 11:08:34.628446 ========== PULL DRAM RESETB DOWN end =========
4864 11:08:34.631900 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4865 11:08:34.635076 ===================================
4866 11:08:34.638339 LPDDR4 DRAM CONFIGURATION
4867 11:08:34.642038 ===================================
4868 11:08:34.642592 EX_ROW_EN[0] = 0x0
4869 11:08:34.645060 EX_ROW_EN[1] = 0x0
4870 11:08:34.645633 LP4Y_EN = 0x0
4871 11:08:34.648392 WORK_FSP = 0x0
4872 11:08:34.648971 WL = 0x3
4873 11:08:34.651942 RL = 0x3
4874 11:08:34.652408 BL = 0x2
4875 11:08:34.654958 RPST = 0x0
4876 11:08:34.658148 RD_PRE = 0x0
4877 11:08:34.658638 WR_PRE = 0x1
4878 11:08:34.661427 WR_PST = 0x0
4879 11:08:34.661897 DBI_WR = 0x0
4880 11:08:34.664805 DBI_RD = 0x0
4881 11:08:34.665276 OTF = 0x1
4882 11:08:34.668190 ===================================
4883 11:08:34.671534 ===================================
4884 11:08:34.672003 ANA top config
4885 11:08:34.675129 ===================================
4886 11:08:34.678486 DLL_ASYNC_EN = 0
4887 11:08:34.681629 ALL_SLAVE_EN = 1
4888 11:08:34.685103 NEW_RANK_MODE = 1
4889 11:08:34.688725 DLL_IDLE_MODE = 1
4890 11:08:34.689282 LP45_APHY_COMB_EN = 1
4891 11:08:34.691441 TX_ODT_DIS = 1
4892 11:08:34.694825 NEW_8X_MODE = 1
4893 11:08:34.698559 ===================================
4894 11:08:34.701707 ===================================
4895 11:08:34.705143 data_rate = 1866
4896 11:08:34.708335 CKR = 1
4897 11:08:34.708802 DQ_P2S_RATIO = 8
4898 11:08:34.711749 ===================================
4899 11:08:34.715407 CA_P2S_RATIO = 8
4900 11:08:34.718626 DQ_CA_OPEN = 0
4901 11:08:34.721630 DQ_SEMI_OPEN = 0
4902 11:08:34.724908 CA_SEMI_OPEN = 0
4903 11:08:34.728443 CA_FULL_RATE = 0
4904 11:08:34.729003 DQ_CKDIV4_EN = 1
4905 11:08:34.731546 CA_CKDIV4_EN = 1
4906 11:08:34.734987 CA_PREDIV_EN = 0
4907 11:08:34.738508 PH8_DLY = 0
4908 11:08:34.741752 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4909 11:08:34.744817 DQ_AAMCK_DIV = 4
4910 11:08:34.745372 CA_AAMCK_DIV = 4
4911 11:08:34.748230 CA_ADMCK_DIV = 4
4912 11:08:34.751527 DQ_TRACK_CA_EN = 0
4913 11:08:34.754859 CA_PICK = 933
4914 11:08:34.757983 CA_MCKIO = 933
4915 11:08:34.761139 MCKIO_SEMI = 0
4916 11:08:34.764793 PLL_FREQ = 3732
4917 11:08:34.765357 DQ_UI_PI_RATIO = 32
4918 11:08:34.767998 CA_UI_PI_RATIO = 0
4919 11:08:34.771285 ===================================
4920 11:08:34.774813 ===================================
4921 11:08:34.778532 memory_type:LPDDR4
4922 11:08:34.781242 GP_NUM : 10
4923 11:08:34.781806 SRAM_EN : 1
4924 11:08:34.784798 MD32_EN : 0
4925 11:08:34.788305 ===================================
4926 11:08:34.791444 [ANA_INIT] >>>>>>>>>>>>>>
4927 11:08:34.791998 <<<<<< [CONFIGURE PHASE]: ANA_TX
4928 11:08:34.794543 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4929 11:08:34.797743 ===================================
4930 11:08:34.800879 data_rate = 1866,PCW = 0X8f00
4931 11:08:34.804556 ===================================
4932 11:08:34.808002 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4933 11:08:34.814451 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4934 11:08:34.821332 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4935 11:08:34.824709 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4936 11:08:34.827818 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4937 11:08:34.831285 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4938 11:08:34.834882 [ANA_INIT] flow start
4939 11:08:34.835342 [ANA_INIT] PLL >>>>>>>>
4940 11:08:34.837825 [ANA_INIT] PLL <<<<<<<<
4941 11:08:34.840893 [ANA_INIT] MIDPI >>>>>>>>
4942 11:08:34.841406 [ANA_INIT] MIDPI <<<<<<<<
4943 11:08:34.844339 [ANA_INIT] DLL >>>>>>>>
4944 11:08:34.847977 [ANA_INIT] flow end
4945 11:08:34.851223 ============ LP4 DIFF to SE enter ============
4946 11:08:34.854840 ============ LP4 DIFF to SE exit ============
4947 11:08:34.857985 [ANA_INIT] <<<<<<<<<<<<<
4948 11:08:34.861286 [Flow] Enable top DCM control >>>>>
4949 11:08:34.864860 [Flow] Enable top DCM control <<<<<
4950 11:08:34.868196 Enable DLL master slave shuffle
4951 11:08:34.871072 ==============================================================
4952 11:08:34.874456 Gating Mode config
4953 11:08:34.880877 ==============================================================
4954 11:08:34.881428 Config description:
4955 11:08:34.891118 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4956 11:08:34.897638 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4957 11:08:34.900824 SELPH_MODE 0: By rank 1: By Phase
4958 11:08:34.908220 ==============================================================
4959 11:08:34.910906 GAT_TRACK_EN = 1
4960 11:08:34.914485 RX_GATING_MODE = 2
4961 11:08:34.917480 RX_GATING_TRACK_MODE = 2
4962 11:08:34.920894 SELPH_MODE = 1
4963 11:08:34.924075 PICG_EARLY_EN = 1
4964 11:08:34.927782 VALID_LAT_VALUE = 1
4965 11:08:34.930638 ==============================================================
4966 11:08:34.934066 Enter into Gating configuration >>>>
4967 11:08:34.937482 Exit from Gating configuration <<<<
4968 11:08:34.941075 Enter into DVFS_PRE_config >>>>>
4969 11:08:34.954086 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4970 11:08:34.954659 Exit from DVFS_PRE_config <<<<<
4971 11:08:34.957793 Enter into PICG configuration >>>>
4972 11:08:34.961131 Exit from PICG configuration <<<<
4973 11:08:34.964487 [RX_INPUT] configuration >>>>>
4974 11:08:34.967689 [RX_INPUT] configuration <<<<<
4975 11:08:34.974234 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4976 11:08:34.978053 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4977 11:08:34.984524 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4978 11:08:34.991185 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4979 11:08:34.997770 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4980 11:08:35.003876 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4981 11:08:35.007139 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4982 11:08:35.010561 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4983 11:08:35.013875 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4984 11:08:35.020481 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4985 11:08:35.023671 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4986 11:08:35.027722 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4987 11:08:35.030349 ===================================
4988 11:08:35.033877 LPDDR4 DRAM CONFIGURATION
4989 11:08:35.037272 ===================================
4990 11:08:35.037833 EX_ROW_EN[0] = 0x0
4991 11:08:35.040759 EX_ROW_EN[1] = 0x0
4992 11:08:35.043858 LP4Y_EN = 0x0
4993 11:08:35.044377 WORK_FSP = 0x0
4994 11:08:35.047456 WL = 0x3
4995 11:08:35.048019 RL = 0x3
4996 11:08:35.050582 BL = 0x2
4997 11:08:35.051039 RPST = 0x0
4998 11:08:35.053692 RD_PRE = 0x0
4999 11:08:35.054199 WR_PRE = 0x1
5000 11:08:35.056873 WR_PST = 0x0
5001 11:08:35.057336 DBI_WR = 0x0
5002 11:08:35.060230 DBI_RD = 0x0
5003 11:08:35.060686 OTF = 0x1
5004 11:08:35.063504 ===================================
5005 11:08:35.067264 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5006 11:08:35.073997 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5007 11:08:35.077616 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5008 11:08:35.080996 ===================================
5009 11:08:35.083598 LPDDR4 DRAM CONFIGURATION
5010 11:08:35.086851 ===================================
5011 11:08:35.087313 EX_ROW_EN[0] = 0x10
5012 11:08:35.090303 EX_ROW_EN[1] = 0x0
5013 11:08:35.090827 LP4Y_EN = 0x0
5014 11:08:35.094008 WORK_FSP = 0x0
5015 11:08:35.094564 WL = 0x3
5016 11:08:35.097402 RL = 0x3
5017 11:08:35.097998 BL = 0x2
5018 11:08:35.100928 RPST = 0x0
5019 11:08:35.104049 RD_PRE = 0x0
5020 11:08:35.104605 WR_PRE = 0x1
5021 11:08:35.107337 WR_PST = 0x0
5022 11:08:35.107890 DBI_WR = 0x0
5023 11:08:35.110449 DBI_RD = 0x0
5024 11:08:35.110909 OTF = 0x1
5025 11:08:35.113631 ===================================
5026 11:08:35.120193 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5027 11:08:35.123926 nWR fixed to 30
5028 11:08:35.127715 [ModeRegInit_LP4] CH0 RK0
5029 11:08:35.128295 [ModeRegInit_LP4] CH0 RK1
5030 11:08:35.130745 [ModeRegInit_LP4] CH1 RK0
5031 11:08:35.133990 [ModeRegInit_LP4] CH1 RK1
5032 11:08:35.134455 match AC timing 9
5033 11:08:35.140638 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5034 11:08:35.143951 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5035 11:08:35.147049 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5036 11:08:35.153976 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5037 11:08:35.157101 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5038 11:08:35.157567 ==
5039 11:08:35.160344 Dram Type= 6, Freq= 0, CH_0, rank 0
5040 11:08:35.163909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5041 11:08:35.164548 ==
5042 11:08:35.170537 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5043 11:08:35.177185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5044 11:08:35.180307 [CA 0] Center 38 (7~69) winsize 63
5045 11:08:35.183476 [CA 1] Center 38 (8~69) winsize 62
5046 11:08:35.186692 [CA 2] Center 35 (5~66) winsize 62
5047 11:08:35.189892 [CA 3] Center 35 (5~66) winsize 62
5048 11:08:35.193347 [CA 4] Center 34 (4~64) winsize 61
5049 11:08:35.196683 [CA 5] Center 33 (3~64) winsize 62
5050 11:08:35.197203
5051 11:08:35.200096 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5052 11:08:35.200562
5053 11:08:35.203166 [CATrainingPosCal] consider 1 rank data
5054 11:08:35.206485 u2DelayCellTimex100 = 270/100 ps
5055 11:08:35.210338 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5056 11:08:35.213570 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5057 11:08:35.216888 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5058 11:08:35.220198 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5059 11:08:35.227026 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5060 11:08:35.230120 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5061 11:08:35.230690
5062 11:08:35.233200 CA PerBit enable=1, Macro0, CA PI delay=33
5063 11:08:35.233658
5064 11:08:35.236489 [CBTSetCACLKResult] CA Dly = 33
5065 11:08:35.237031 CS Dly: 7 (0~38)
5066 11:08:35.237402 ==
5067 11:08:35.239757 Dram Type= 6, Freq= 0, CH_0, rank 1
5068 11:08:35.243194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5069 11:08:35.246487 ==
5070 11:08:35.249732 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5071 11:08:35.256644 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5072 11:08:35.259743 [CA 0] Center 38 (8~69) winsize 62
5073 11:08:35.263221 [CA 1] Center 38 (8~69) winsize 62
5074 11:08:35.266438 [CA 2] Center 36 (6~66) winsize 61
5075 11:08:35.269587 [CA 3] Center 35 (5~66) winsize 62
5076 11:08:35.272845 [CA 4] Center 35 (4~66) winsize 63
5077 11:08:35.276170 [CA 5] Center 34 (4~65) winsize 62
5078 11:08:35.276624
5079 11:08:35.279507 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5080 11:08:35.280026
5081 11:08:35.283207 [CATrainingPosCal] consider 2 rank data
5082 11:08:35.286395 u2DelayCellTimex100 = 270/100 ps
5083 11:08:35.289797 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5084 11:08:35.293146 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5085 11:08:35.296492 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5086 11:08:35.303141 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5087 11:08:35.306361 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5088 11:08:35.309653 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5089 11:08:35.310116
5090 11:08:35.312940 CA PerBit enable=1, Macro0, CA PI delay=34
5091 11:08:35.313412
5092 11:08:35.316281 [CBTSetCACLKResult] CA Dly = 34
5093 11:08:35.316739 CS Dly: 7 (0~39)
5094 11:08:35.317089
5095 11:08:35.319516 ----->DramcWriteLeveling(PI) begin...
5096 11:08:35.319937 ==
5097 11:08:35.322788 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 11:08:35.329308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 11:08:35.329724 ==
5100 11:08:35.332766 Write leveling (Byte 0): 32 => 32
5101 11:08:35.336114 Write leveling (Byte 1): 29 => 29
5102 11:08:35.336530 DramcWriteLeveling(PI) end<-----
5103 11:08:35.339362
5104 11:08:35.339774 ==
5105 11:08:35.342447 Dram Type= 6, Freq= 0, CH_0, rank 0
5106 11:08:35.346083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 11:08:35.346500 ==
5108 11:08:35.349186 [Gating] SW mode calibration
5109 11:08:35.356001 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5110 11:08:35.359439 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5111 11:08:35.366090 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5112 11:08:35.368983 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 11:08:35.372483 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 11:08:35.379398 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 11:08:35.382682 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 11:08:35.385792 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 11:08:35.392410 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5118 11:08:35.395724 0 14 28 | B1->B0 | 3333 2323 | 1 0 | (1 1) (1 0)
5119 11:08:35.399151 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 11:08:35.405603 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 11:08:35.408533 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 11:08:35.411713 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 11:08:35.418392 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 11:08:35.422099 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 11:08:35.425364 0 15 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
5126 11:08:35.431731 0 15 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
5127 11:08:35.435022 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 11:08:35.438314 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 11:08:35.445082 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 11:08:35.448618 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 11:08:35.452026 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 11:08:35.458757 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 11:08:35.461869 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 11:08:35.465112 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5135 11:08:35.471690 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5136 11:08:35.475049 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 11:08:35.478367 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 11:08:35.481582 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 11:08:35.488614 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 11:08:35.491961 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 11:08:35.495212 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 11:08:35.501735 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 11:08:35.505031 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 11:08:35.508381 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 11:08:35.514992 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 11:08:35.518304 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 11:08:35.521757 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 11:08:35.528256 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 11:08:35.531670 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5150 11:08:35.535104 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5151 11:08:35.541677 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5152 11:08:35.541762 Total UI for P1: 0, mck2ui 16
5153 11:08:35.548261 best dqsien dly found for B0: ( 1, 2, 26)
5154 11:08:35.551354 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 11:08:35.554679 Total UI for P1: 0, mck2ui 16
5156 11:08:35.558246 best dqsien dly found for B1: ( 1, 3, 0)
5157 11:08:35.561584 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5158 11:08:35.564778 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5159 11:08:35.564860
5160 11:08:35.568152 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5161 11:08:35.571537 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5162 11:08:35.574679 [Gating] SW calibration Done
5163 11:08:35.574761 ==
5164 11:08:35.578175 Dram Type= 6, Freq= 0, CH_0, rank 0
5165 11:08:35.581517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5166 11:08:35.584905 ==
5167 11:08:35.584986 RX Vref Scan: 0
5168 11:08:35.585051
5169 11:08:35.588053 RX Vref 0 -> 0, step: 1
5170 11:08:35.588135
5171 11:08:35.588201 RX Delay -80 -> 252, step: 8
5172 11:08:35.595071 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5173 11:08:35.598198 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5174 11:08:35.601307 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5175 11:08:35.604661 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5176 11:08:35.608108 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5177 11:08:35.615134 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5178 11:08:35.617934 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5179 11:08:35.621314 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5180 11:08:35.624963 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5181 11:08:35.627905 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5182 11:08:35.631249 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5183 11:08:35.637981 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5184 11:08:35.641292 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5185 11:08:35.644540 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5186 11:08:35.647848 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5187 11:08:35.651190 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5188 11:08:35.651270 ==
5189 11:08:35.654948 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 11:08:35.661394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 11:08:35.661504 ==
5192 11:08:35.661568 DQS Delay:
5193 11:08:35.661627 DQS0 = 0, DQS1 = 0
5194 11:08:35.665027 DQM Delay:
5195 11:08:35.665108 DQM0 = 105, DQM1 = 90
5196 11:08:35.667781 DQ Delay:
5197 11:08:35.671606 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5198 11:08:35.674410 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5199 11:08:35.677753 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5200 11:08:35.681017 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5201 11:08:35.681125
5202 11:08:35.681226
5203 11:08:35.681359 ==
5204 11:08:35.684520 Dram Type= 6, Freq= 0, CH_0, rank 0
5205 11:08:35.687669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5206 11:08:35.687772 ==
5207 11:08:35.687872
5208 11:08:35.687972
5209 11:08:35.691161 TX Vref Scan disable
5210 11:08:35.694606 == TX Byte 0 ==
5211 11:08:35.698068 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5212 11:08:35.701458 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5213 11:08:35.704175 == TX Byte 1 ==
5214 11:08:35.707528 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5215 11:08:35.710836 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5216 11:08:35.710939 ==
5217 11:08:35.714220 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 11:08:35.717480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 11:08:35.721045 ==
5220 11:08:35.721149
5221 11:08:35.721249
5222 11:08:35.721348 TX Vref Scan disable
5223 11:08:35.724741 == TX Byte 0 ==
5224 11:08:35.727591 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5225 11:08:35.734214 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5226 11:08:35.734294 == TX Byte 1 ==
5227 11:08:35.737831 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5228 11:08:35.744641 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5229 11:08:35.744745
5230 11:08:35.744846 [DATLAT]
5231 11:08:35.744946 Freq=933, CH0 RK0
5232 11:08:35.745044
5233 11:08:35.747815 DATLAT Default: 0xd
5234 11:08:35.747918 0, 0xFFFF, sum = 0
5235 11:08:35.751127 1, 0xFFFF, sum = 0
5236 11:08:35.751205 2, 0xFFFF, sum = 0
5237 11:08:35.754400 3, 0xFFFF, sum = 0
5238 11:08:35.757617 4, 0xFFFF, sum = 0
5239 11:08:35.757722 5, 0xFFFF, sum = 0
5240 11:08:35.760869 6, 0xFFFF, sum = 0
5241 11:08:35.760975 7, 0xFFFF, sum = 0
5242 11:08:35.764237 8, 0xFFFF, sum = 0
5243 11:08:35.764319 9, 0xFFFF, sum = 0
5244 11:08:35.767501 10, 0x0, sum = 1
5245 11:08:35.767588 11, 0x0, sum = 2
5246 11:08:35.771217 12, 0x0, sum = 3
5247 11:08:35.771324 13, 0x0, sum = 4
5248 11:08:35.771427 best_step = 11
5249 11:08:35.771525
5250 11:08:35.774431 ==
5251 11:08:35.777846 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 11:08:35.781123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 11:08:35.781224 ==
5254 11:08:35.781323 RX Vref Scan: 1
5255 11:08:35.781423
5256 11:08:35.784157 RX Vref 0 -> 0, step: 1
5257 11:08:35.784232
5258 11:08:35.787376 RX Delay -53 -> 252, step: 4
5259 11:08:35.787478
5260 11:08:35.790735 Set Vref, RX VrefLevel [Byte0]: 59
5261 11:08:35.794278 [Byte1]: 50
5262 11:08:35.794378
5263 11:08:35.797401 Final RX Vref Byte 0 = 59 to rank0
5264 11:08:35.800971 Final RX Vref Byte 1 = 50 to rank0
5265 11:08:35.804011 Final RX Vref Byte 0 = 59 to rank1
5266 11:08:35.807561 Final RX Vref Byte 1 = 50 to rank1==
5267 11:08:35.810868 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 11:08:35.813733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 11:08:35.817635 ==
5270 11:08:35.817709 DQS Delay:
5271 11:08:35.817805 DQS0 = 0, DQS1 = 0
5272 11:08:35.820833 DQM Delay:
5273 11:08:35.820934 DQM0 = 108, DQM1 = 92
5274 11:08:35.823746 DQ Delay:
5275 11:08:35.827076 DQ0 =108, DQ1 =108, DQ2 =104, DQ3 =106
5276 11:08:35.830450 DQ4 =108, DQ5 =100, DQ6 =118, DQ7 =114
5277 11:08:35.833806 DQ8 =86, DQ9 =82, DQ10 =92, DQ11 =90
5278 11:08:35.837185 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =98
5279 11:08:35.837257
5280 11:08:35.837319
5281 11:08:35.843743 [DQSOSCAuto] RK0, (LSB)MR18= 0x211c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5282 11:08:35.847036 CH0 RK0: MR19=505, MR18=211C
5283 11:08:35.853624 CH0_RK0: MR19=0x505, MR18=0x211C, DQSOSC=411, MR23=63, INC=64, DEC=42
5284 11:08:35.853725
5285 11:08:35.857075 ----->DramcWriteLeveling(PI) begin...
5286 11:08:35.857165 ==
5287 11:08:35.860328 Dram Type= 6, Freq= 0, CH_0, rank 1
5288 11:08:35.863877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 11:08:35.864000 ==
5290 11:08:35.867211 Write leveling (Byte 0): 32 => 32
5291 11:08:35.869892 Write leveling (Byte 1): 31 => 31
5292 11:08:35.873253 DramcWriteLeveling(PI) end<-----
5293 11:08:35.873331
5294 11:08:35.873392 ==
5295 11:08:35.876762 Dram Type= 6, Freq= 0, CH_0, rank 1
5296 11:08:35.880006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 11:08:35.883495 ==
5298 11:08:35.883601 [Gating] SW mode calibration
5299 11:08:35.893400 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5300 11:08:35.896845 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5301 11:08:35.900237 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 11:08:35.906491 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 11:08:35.909815 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 11:08:35.913188 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 11:08:35.919748 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 11:08:35.923207 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 11:08:35.926534 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5308 11:08:35.933161 0 14 28 | B1->B0 | 2e2e 2828 | 0 1 | (0 0) (1 0)
5309 11:08:35.936532 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 11:08:35.939954 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 11:08:35.946517 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 11:08:35.949770 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 11:08:35.953131 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 11:08:35.959636 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 11:08:35.963102 0 15 24 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
5316 11:08:35.966231 0 15 28 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
5317 11:08:35.973085 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 11:08:35.976069 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 11:08:35.979470 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 11:08:35.986233 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 11:08:35.989273 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 11:08:35.993154 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 11:08:35.999653 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5324 11:08:36.002558 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5325 11:08:36.006036 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5326 11:08:36.012470 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 11:08:36.015800 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 11:08:36.019100 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 11:08:36.025756 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 11:08:36.029157 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 11:08:36.032662 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 11:08:36.038879 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 11:08:36.042506 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 11:08:36.045858 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 11:08:36.052397 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 11:08:36.055693 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 11:08:36.059046 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 11:08:36.065616 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 11:08:36.068999 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5340 11:08:36.072490 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 11:08:36.075843 Total UI for P1: 0, mck2ui 16
5342 11:08:36.079575 best dqsien dly found for B0: ( 1, 2, 24)
5343 11:08:36.082420 Total UI for P1: 0, mck2ui 16
5344 11:08:36.086015 best dqsien dly found for B1: ( 1, 2, 26)
5345 11:08:36.089355 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5346 11:08:36.092405 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5347 11:08:36.092832
5348 11:08:36.095589 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5349 11:08:36.102568 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5350 11:08:36.102941 [Gating] SW calibration Done
5351 11:08:36.103256 ==
5352 11:08:36.105850 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 11:08:36.112114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 11:08:36.112800 ==
5355 11:08:36.113305 RX Vref Scan: 0
5356 11:08:36.113812
5357 11:08:36.116050 RX Vref 0 -> 0, step: 1
5358 11:08:36.116509
5359 11:08:36.119103 RX Delay -80 -> 252, step: 8
5360 11:08:36.122470 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5361 11:08:36.125869 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5362 11:08:36.128935 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5363 11:08:36.132288 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5364 11:08:36.139160 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5365 11:08:36.142439 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5366 11:08:36.145767 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5367 11:08:36.149079 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5368 11:08:36.152359 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5369 11:08:36.155812 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5370 11:08:36.162350 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5371 11:08:36.165582 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5372 11:08:36.168934 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5373 11:08:36.172223 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5374 11:08:36.175572 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5375 11:08:36.178892 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5376 11:08:36.182214 ==
5377 11:08:36.185578 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 11:08:36.188956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 11:08:36.189373 ==
5380 11:08:36.189700 DQS Delay:
5381 11:08:36.192278 DQS0 = 0, DQS1 = 0
5382 11:08:36.192738 DQM Delay:
5383 11:08:36.195495 DQM0 = 104, DQM1 = 89
5384 11:08:36.195955 DQ Delay:
5385 11:08:36.198864 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5386 11:08:36.201785 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5387 11:08:36.205462 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5388 11:08:36.208541 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5389 11:08:36.208954
5390 11:08:36.209467
5391 11:08:36.209803 ==
5392 11:08:36.211750 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 11:08:36.215234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 11:08:36.218470 ==
5395 11:08:36.218883
5396 11:08:36.219213
5397 11:08:36.219521 TX Vref Scan disable
5398 11:08:36.221852 == TX Byte 0 ==
5399 11:08:36.224908 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5400 11:08:36.228226 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5401 11:08:36.231713 == TX Byte 1 ==
5402 11:08:36.235322 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5403 11:08:36.238253 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5404 11:08:36.238716 ==
5405 11:08:36.241532 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 11:08:36.248305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 11:08:36.248725 ==
5408 11:08:36.249059
5409 11:08:36.249367
5410 11:08:36.249639 TX Vref Scan disable
5411 11:08:36.252273 == TX Byte 0 ==
5412 11:08:36.255892 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5413 11:08:36.262136 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5414 11:08:36.262218 == TX Byte 1 ==
5415 11:08:36.265327 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5416 11:08:36.272432 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5417 11:08:36.272513
5418 11:08:36.272578 [DATLAT]
5419 11:08:36.272636 Freq=933, CH0 RK1
5420 11:08:36.272693
5421 11:08:36.275727 DATLAT Default: 0xb
5422 11:08:36.275808 0, 0xFFFF, sum = 0
5423 11:08:36.279047 1, 0xFFFF, sum = 0
5424 11:08:36.279129 2, 0xFFFF, sum = 0
5425 11:08:36.282346 3, 0xFFFF, sum = 0
5426 11:08:36.285624 4, 0xFFFF, sum = 0
5427 11:08:36.285705 5, 0xFFFF, sum = 0
5428 11:08:36.288864 6, 0xFFFF, sum = 0
5429 11:08:36.288947 7, 0xFFFF, sum = 0
5430 11:08:36.292200 8, 0xFFFF, sum = 0
5431 11:08:36.292282 9, 0xFFFF, sum = 0
5432 11:08:36.295404 10, 0x0, sum = 1
5433 11:08:36.295485 11, 0x0, sum = 2
5434 11:08:36.299070 12, 0x0, sum = 3
5435 11:08:36.299153 13, 0x0, sum = 4
5436 11:08:36.299218 best_step = 11
5437 11:08:36.299278
5438 11:08:36.302410 ==
5439 11:08:36.302491 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 11:08:36.308957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 11:08:36.309039 ==
5442 11:08:36.309104 RX Vref Scan: 0
5443 11:08:36.309162
5444 11:08:36.312157 RX Vref 0 -> 0, step: 1
5445 11:08:36.312238
5446 11:08:36.315403 RX Delay -53 -> 252, step: 4
5447 11:08:36.318936 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5448 11:08:36.325732 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5449 11:08:36.328984 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5450 11:08:36.331852 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5451 11:08:36.335303 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5452 11:08:36.338760 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5453 11:08:36.345204 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5454 11:08:36.348580 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5455 11:08:36.351743 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5456 11:08:36.355195 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5457 11:08:36.358495 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5458 11:08:36.361726 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5459 11:08:36.368541 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5460 11:08:36.371726 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5461 11:08:36.375339 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5462 11:08:36.378619 iDelay=199, Bit 15, Center 100 (19 ~ 182) 164
5463 11:08:36.378699 ==
5464 11:08:36.381900 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 11:08:36.388491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 11:08:36.388574 ==
5467 11:08:36.388637 DQS Delay:
5468 11:08:36.391883 DQS0 = 0, DQS1 = 0
5469 11:08:36.391962 DQM Delay:
5470 11:08:36.392026 DQM0 = 103, DQM1 = 93
5471 11:08:36.395179 DQ Delay:
5472 11:08:36.398477 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5473 11:08:36.401816 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5474 11:08:36.404991 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5475 11:08:36.408438 DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =100
5476 11:08:36.408518
5477 11:08:36.408579
5478 11:08:36.415160 [DQSOSCAuto] RK1, (LSB)MR18= 0x2607, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5479 11:08:36.418849 CH0 RK1: MR19=505, MR18=2607
5480 11:08:36.425098 CH0_RK1: MR19=0x505, MR18=0x2607, DQSOSC=409, MR23=63, INC=64, DEC=43
5481 11:08:36.428612 [RxdqsGatingPostProcess] freq 933
5482 11:08:36.435159 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5483 11:08:36.438470 best DQS0 dly(2T, 0.5T) = (0, 10)
5484 11:08:36.438636 best DQS1 dly(2T, 0.5T) = (0, 11)
5485 11:08:36.441476 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5486 11:08:36.444927 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5487 11:08:36.448410 best DQS0 dly(2T, 0.5T) = (0, 10)
5488 11:08:36.452093 best DQS1 dly(2T, 0.5T) = (0, 10)
5489 11:08:36.454790 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5490 11:08:36.458439 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5491 11:08:36.461842 Pre-setting of DQS Precalculation
5492 11:08:36.468573 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5493 11:08:36.468853 ==
5494 11:08:36.471928 Dram Type= 6, Freq= 0, CH_1, rank 0
5495 11:08:36.475231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 11:08:36.475549 ==
5497 11:08:36.481800 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5498 11:08:36.485185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5499 11:08:36.489448 [CA 0] Center 37 (7~68) winsize 62
5500 11:08:36.492804 [CA 1] Center 37 (7~68) winsize 62
5501 11:08:36.496150 [CA 2] Center 35 (5~65) winsize 61
5502 11:08:36.499114 [CA 3] Center 34 (4~65) winsize 62
5503 11:08:36.502711 [CA 4] Center 34 (4~65) winsize 62
5504 11:08:36.506483 [CA 5] Center 34 (4~65) winsize 62
5505 11:08:36.507047
5506 11:08:36.509203 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5507 11:08:36.509769
5508 11:08:36.512380 [CATrainingPosCal] consider 1 rank data
5509 11:08:36.515933 u2DelayCellTimex100 = 270/100 ps
5510 11:08:36.519427 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5511 11:08:36.522469 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5512 11:08:36.529035 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5513 11:08:36.532381 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5514 11:08:36.536150 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5515 11:08:36.538868 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5516 11:08:36.539326
5517 11:08:36.542234 CA PerBit enable=1, Macro0, CA PI delay=34
5518 11:08:36.542847
5519 11:08:36.545767 [CBTSetCACLKResult] CA Dly = 34
5520 11:08:36.546360 CS Dly: 5 (0~36)
5521 11:08:36.548627 ==
5522 11:08:36.552302 Dram Type= 6, Freq= 0, CH_1, rank 1
5523 11:08:36.555808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5524 11:08:36.556496 ==
5525 11:08:36.558612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5526 11:08:36.565155 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5527 11:08:36.569082 [CA 0] Center 37 (7~68) winsize 62
5528 11:08:36.572597 [CA 1] Center 37 (7~68) winsize 62
5529 11:08:36.575786 [CA 2] Center 35 (5~66) winsize 62
5530 11:08:36.579240 [CA 3] Center 35 (5~65) winsize 61
5531 11:08:36.582346 [CA 4] Center 35 (5~65) winsize 61
5532 11:08:36.585713 [CA 5] Center 34 (4~64) winsize 61
5533 11:08:36.586220
5534 11:08:36.589043 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5535 11:08:36.589526
5536 11:08:36.592095 [CATrainingPosCal] consider 2 rank data
5537 11:08:36.595362 u2DelayCellTimex100 = 270/100 ps
5538 11:08:36.599007 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5539 11:08:36.605550 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5540 11:08:36.608810 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5541 11:08:36.612111 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5542 11:08:36.615368 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5543 11:08:36.619088 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5544 11:08:36.619658
5545 11:08:36.622058 CA PerBit enable=1, Macro0, CA PI delay=34
5546 11:08:36.622522
5547 11:08:36.625257 [CBTSetCACLKResult] CA Dly = 34
5548 11:08:36.625719 CS Dly: 6 (0~38)
5549 11:08:36.628436
5550 11:08:36.631849 ----->DramcWriteLeveling(PI) begin...
5551 11:08:36.632318 ==
5552 11:08:36.635286 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 11:08:36.638783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 11:08:36.639250 ==
5555 11:08:36.642227 Write leveling (Byte 0): 24 => 24
5556 11:08:36.645389 Write leveling (Byte 1): 28 => 28
5557 11:08:36.648443 DramcWriteLeveling(PI) end<-----
5558 11:08:36.648906
5559 11:08:36.649273 ==
5560 11:08:36.651793 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 11:08:36.655257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 11:08:36.655725 ==
5563 11:08:36.658419 [Gating] SW mode calibration
5564 11:08:36.665267 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5565 11:08:36.671766 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5566 11:08:36.674874 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 11:08:36.678076 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 11:08:36.684773 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 11:08:36.687982 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 11:08:36.691466 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 11:08:36.698173 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5572 11:08:36.701323 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 1)
5573 11:08:36.704973 0 14 28 | B1->B0 | 2727 2525 | 0 0 | (0 0) (1 1)
5574 11:08:36.708169 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 11:08:36.714917 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 11:08:36.718243 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 11:08:36.721583 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 11:08:36.728338 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 11:08:36.731963 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 11:08:36.735693 0 15 24 | B1->B0 | 2626 2828 | 0 0 | (0 0) (0 0)
5581 11:08:36.742377 0 15 28 | B1->B0 | 4040 4141 | 0 1 | (0 0) (0 0)
5582 11:08:36.745645 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 11:08:36.748892 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 11:08:36.755216 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 11:08:36.758319 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 11:08:36.761800 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 11:08:36.768187 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5588 11:08:36.771624 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5589 11:08:36.774749 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5590 11:08:36.781626 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 11:08:36.784978 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 11:08:36.788339 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 11:08:36.795194 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 11:08:36.798468 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 11:08:36.801725 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 11:08:36.808806 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 11:08:36.811956 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 11:08:36.815081 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 11:08:36.818571 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 11:08:36.825029 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 11:08:36.828368 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 11:08:36.831564 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 11:08:36.838370 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5604 11:08:36.841729 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5605 11:08:36.845066 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5606 11:08:36.848395 Total UI for P1: 0, mck2ui 16
5607 11:08:36.851602 best dqsien dly found for B0: ( 1, 2, 22)
5608 11:08:36.858196 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 11:08:36.858781 Total UI for P1: 0, mck2ui 16
5610 11:08:36.864948 best dqsien dly found for B1: ( 1, 2, 28)
5611 11:08:36.868612 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5612 11:08:36.871541 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5613 11:08:36.872002
5614 11:08:36.875097 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5615 11:08:36.878210 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5616 11:08:36.881852 [Gating] SW calibration Done
5617 11:08:36.882317 ==
5618 11:08:36.885265 Dram Type= 6, Freq= 0, CH_1, rank 0
5619 11:08:36.888544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 11:08:36.888969 ==
5621 11:08:36.891598 RX Vref Scan: 0
5622 11:08:36.892015
5623 11:08:36.892345 RX Vref 0 -> 0, step: 1
5624 11:08:36.892653
5625 11:08:36.894852 RX Delay -80 -> 252, step: 8
5626 11:08:36.898581 iDelay=208, Bit 0, Center 111 (32 ~ 191) 160
5627 11:08:36.905143 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5628 11:08:36.908265 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5629 11:08:36.911443 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5630 11:08:36.914881 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5631 11:08:36.918420 iDelay=208, Bit 5, Center 115 (32 ~ 199) 168
5632 11:08:36.921543 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5633 11:08:36.928160 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5634 11:08:36.931444 iDelay=208, Bit 8, Center 87 (-8 ~ 183) 192
5635 11:08:36.934753 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5636 11:08:36.938106 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5637 11:08:36.941090 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5638 11:08:36.944620 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5639 11:08:36.951182 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5640 11:08:36.954548 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5641 11:08:36.957802 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5642 11:08:36.958257 ==
5643 11:08:36.961483 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 11:08:36.964649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 11:08:36.965068 ==
5646 11:08:36.967967 DQS Delay:
5647 11:08:36.968380 DQS0 = 0, DQS1 = 0
5648 11:08:36.971290 DQM Delay:
5649 11:08:36.971705 DQM0 = 104, DQM1 = 96
5650 11:08:36.972033 DQ Delay:
5651 11:08:36.974546 DQ0 =111, DQ1 =95, DQ2 =95, DQ3 =99
5652 11:08:36.977736 DQ4 =99, DQ5 =115, DQ6 =119, DQ7 =99
5653 11:08:36.981822 DQ8 =87, DQ9 =83, DQ10 =99, DQ11 =91
5654 11:08:36.984452 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5655 11:08:36.984866
5656 11:08:36.987732
5657 11:08:36.988146 ==
5658 11:08:36.991262 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 11:08:36.994390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 11:08:36.994808 ==
5661 11:08:36.995140
5662 11:08:36.995448
5663 11:08:36.997783 TX Vref Scan disable
5664 11:08:36.998223 == TX Byte 0 ==
5665 11:08:37.004455 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5666 11:08:37.008159 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5667 11:08:37.008574 == TX Byte 1 ==
5668 11:08:37.014378 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5669 11:08:37.017976 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5670 11:08:37.018401 ==
5671 11:08:37.021256 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 11:08:37.024344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 11:08:37.024773 ==
5674 11:08:37.025276
5675 11:08:37.025688
5676 11:08:37.027788 TX Vref Scan disable
5677 11:08:37.030836 == TX Byte 0 ==
5678 11:08:37.034203 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5679 11:08:37.037725 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5680 11:08:37.040992 == TX Byte 1 ==
5681 11:08:37.044022 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5682 11:08:37.047543 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5683 11:08:37.047958
5684 11:08:37.050806 [DATLAT]
5685 11:08:37.051218 Freq=933, CH1 RK0
5686 11:08:37.051549
5687 11:08:37.054126 DATLAT Default: 0xd
5688 11:08:37.054537 0, 0xFFFF, sum = 0
5689 11:08:37.057518 1, 0xFFFF, sum = 0
5690 11:08:37.057967 2, 0xFFFF, sum = 0
5691 11:08:37.060851 3, 0xFFFF, sum = 0
5692 11:08:37.061273 4, 0xFFFF, sum = 0
5693 11:08:37.064079 5, 0xFFFF, sum = 0
5694 11:08:37.064501 6, 0xFFFF, sum = 0
5695 11:08:37.067255 7, 0xFFFF, sum = 0
5696 11:08:37.067678 8, 0xFFFF, sum = 0
5697 11:08:37.071065 9, 0xFFFF, sum = 0
5698 11:08:37.071486 10, 0x0, sum = 1
5699 11:08:37.073902 11, 0x0, sum = 2
5700 11:08:37.074002 12, 0x0, sum = 3
5701 11:08:37.076967 13, 0x0, sum = 4
5702 11:08:37.077050 best_step = 11
5703 11:08:37.077114
5704 11:08:37.077172 ==
5705 11:08:37.080660 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 11:08:37.087260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 11:08:37.087680 ==
5708 11:08:37.088017 RX Vref Scan: 1
5709 11:08:37.088326
5710 11:08:37.090539 RX Vref 0 -> 0, step: 1
5711 11:08:37.090976
5712 11:08:37.093896 RX Delay -53 -> 252, step: 4
5713 11:08:37.094371
5714 11:08:37.097658 Set Vref, RX VrefLevel [Byte0]: 51
5715 11:08:37.100450 [Byte1]: 52
5716 11:08:37.100898
5717 11:08:37.103952 Final RX Vref Byte 0 = 51 to rank0
5718 11:08:37.107372 Final RX Vref Byte 1 = 52 to rank0
5719 11:08:37.110608 Final RX Vref Byte 0 = 51 to rank1
5720 11:08:37.113583 Final RX Vref Byte 1 = 52 to rank1==
5721 11:08:37.117101 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 11:08:37.120585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 11:08:37.121010 ==
5724 11:08:37.123565 DQS Delay:
5725 11:08:37.124005 DQS0 = 0, DQS1 = 0
5726 11:08:37.124340 DQM Delay:
5727 11:08:37.127081 DQM0 = 107, DQM1 = 100
5728 11:08:37.127539 DQ Delay:
5729 11:08:37.130534 DQ0 =110, DQ1 =102, DQ2 =100, DQ3 =106
5730 11:08:37.133813 DQ4 =106, DQ5 =116, DQ6 =116, DQ7 =104
5731 11:08:37.137146 DQ8 =92, DQ9 =88, DQ10 =102, DQ11 =94
5732 11:08:37.143508 DQ12 =112, DQ13 =104, DQ14 =108, DQ15 =106
5733 11:08:37.143928
5734 11:08:37.144258
5735 11:08:37.150113 [DQSOSCAuto] RK0, (LSB)MR18= 0x1932, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5736 11:08:37.153768 CH1 RK0: MR19=505, MR18=1932
5737 11:08:37.160205 CH1_RK0: MR19=0x505, MR18=0x1932, DQSOSC=406, MR23=63, INC=65, DEC=43
5738 11:08:37.160774
5739 11:08:37.163622 ----->DramcWriteLeveling(PI) begin...
5740 11:08:37.164107 ==
5741 11:08:37.166975 Dram Type= 6, Freq= 0, CH_1, rank 1
5742 11:08:37.170337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 11:08:37.170759 ==
5744 11:08:37.173578 Write leveling (Byte 0): 28 => 28
5745 11:08:37.176672 Write leveling (Byte 1): 29 => 29
5746 11:08:37.180109 DramcWriteLeveling(PI) end<-----
5747 11:08:37.180572
5748 11:08:37.180924 ==
5749 11:08:37.183458 Dram Type= 6, Freq= 0, CH_1, rank 1
5750 11:08:37.187057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 11:08:37.187516 ==
5752 11:08:37.190386 [Gating] SW mode calibration
5753 11:08:37.197000 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5754 11:08:37.203058 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5755 11:08:37.206944 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 11:08:37.213092 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 11:08:37.216643 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 11:08:37.220217 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 11:08:37.226409 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 11:08:37.230055 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 11:08:37.233094 0 14 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 0)
5762 11:08:37.239934 0 14 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 1)
5763 11:08:37.243295 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5764 11:08:37.246565 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 11:08:37.253404 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 11:08:37.256487 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 11:08:37.259992 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 11:08:37.263192 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 11:08:37.269847 0 15 24 | B1->B0 | 2424 2828 | 0 1 | (0 0) (0 0)
5770 11:08:37.273110 0 15 28 | B1->B0 | 3a3a 3232 | 0 0 | (0 0) (0 0)
5771 11:08:37.276255 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5772 11:08:37.282897 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 11:08:37.286140 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 11:08:37.290020 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 11:08:37.296449 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 11:08:37.299815 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 11:08:37.302755 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5778 11:08:37.309817 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5779 11:08:37.313087 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 11:08:37.316561 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 11:08:37.322857 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 11:08:37.326152 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 11:08:37.329513 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 11:08:37.336219 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 11:08:37.339146 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 11:08:37.343064 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 11:08:37.349758 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 11:08:37.352802 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 11:08:37.356068 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 11:08:37.362591 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 11:08:37.366138 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 11:08:37.368978 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5793 11:08:37.376029 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5794 11:08:37.379233 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5795 11:08:37.382500 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 11:08:37.386127 Total UI for P1: 0, mck2ui 16
5797 11:08:37.388995 best dqsien dly found for B0: ( 1, 2, 26)
5798 11:08:37.392619 Total UI for P1: 0, mck2ui 16
5799 11:08:37.395612 best dqsien dly found for B1: ( 1, 2, 24)
5800 11:08:37.398574 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5801 11:08:37.401773 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5802 11:08:37.401855
5803 11:08:37.408768 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5804 11:08:37.411913 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5805 11:08:37.412009 [Gating] SW calibration Done
5806 11:08:37.415234 ==
5807 11:08:37.415328 Dram Type= 6, Freq= 0, CH_1, rank 1
5808 11:08:37.421537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 11:08:37.421651 ==
5810 11:08:37.421738 RX Vref Scan: 0
5811 11:08:37.421821
5812 11:08:37.425415 RX Vref 0 -> 0, step: 1
5813 11:08:37.425526
5814 11:08:37.428281 RX Delay -80 -> 252, step: 8
5815 11:08:37.431846 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
5816 11:08:37.435257 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5817 11:08:37.438242 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5818 11:08:37.444842 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5819 11:08:37.448467 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5820 11:08:37.451815 iDelay=200, Bit 5, Center 115 (32 ~ 199) 168
5821 11:08:37.455002 iDelay=200, Bit 6, Center 115 (32 ~ 199) 168
5822 11:08:37.458380 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5823 11:08:37.464797 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5824 11:08:37.468583 iDelay=200, Bit 9, Center 91 (8 ~ 175) 168
5825 11:08:37.471708 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5826 11:08:37.475300 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5827 11:08:37.478573 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5828 11:08:37.484960 iDelay=200, Bit 13, Center 103 (16 ~ 191) 176
5829 11:08:37.488368 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5830 11:08:37.491853 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5831 11:08:37.492276 ==
5832 11:08:37.494902 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 11:08:37.498273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 11:08:37.498692 ==
5835 11:08:37.501795 DQS Delay:
5836 11:08:37.502249 DQS0 = 0, DQS1 = 0
5837 11:08:37.502585 DQM Delay:
5838 11:08:37.505237 DQM0 = 105, DQM1 = 97
5839 11:08:37.505655 DQ Delay:
5840 11:08:37.508637 DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =103
5841 11:08:37.511485 DQ4 =103, DQ5 =115, DQ6 =115, DQ7 =103
5842 11:08:37.515087 DQ8 =83, DQ9 =91, DQ10 =95, DQ11 =91
5843 11:08:37.521668 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5844 11:08:37.522121
5845 11:08:37.522459
5846 11:08:37.522768 ==
5847 11:08:37.524991 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 11:08:37.528212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 11:08:37.528681 ==
5850 11:08:37.529020
5851 11:08:37.529327
5852 11:08:37.531534 TX Vref Scan disable
5853 11:08:37.531953 == TX Byte 0 ==
5854 11:08:37.538368 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5855 11:08:37.541517 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5856 11:08:37.541960 == TX Byte 1 ==
5857 11:08:37.548313 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5858 11:08:37.551354 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5859 11:08:37.551775 ==
5860 11:08:37.554813 Dram Type= 6, Freq= 0, CH_1, rank 1
5861 11:08:37.558281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5862 11:08:37.558706 ==
5863 11:08:37.559039
5864 11:08:37.559347
5865 11:08:37.561752 TX Vref Scan disable
5866 11:08:37.564972 == TX Byte 0 ==
5867 11:08:37.568257 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5868 11:08:37.571519 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5869 11:08:37.574813 == TX Byte 1 ==
5870 11:08:37.578220 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5871 11:08:37.581506 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5872 11:08:37.581926
5873 11:08:37.584483 [DATLAT]
5874 11:08:37.584901 Freq=933, CH1 RK1
5875 11:08:37.585239
5876 11:08:37.587719 DATLAT Default: 0xb
5877 11:08:37.588161 0, 0xFFFF, sum = 0
5878 11:08:37.590889 1, 0xFFFF, sum = 0
5879 11:08:37.591315 2, 0xFFFF, sum = 0
5880 11:08:37.594418 3, 0xFFFF, sum = 0
5881 11:08:37.594844 4, 0xFFFF, sum = 0
5882 11:08:37.597698 5, 0xFFFF, sum = 0
5883 11:08:37.598152 6, 0xFFFF, sum = 0
5884 11:08:37.601009 7, 0xFFFF, sum = 0
5885 11:08:37.601434 8, 0xFFFF, sum = 0
5886 11:08:37.604585 9, 0xFFFF, sum = 0
5887 11:08:37.605012 10, 0x0, sum = 1
5888 11:08:37.607482 11, 0x0, sum = 2
5889 11:08:37.607907 12, 0x0, sum = 3
5890 11:08:37.610967 13, 0x0, sum = 4
5891 11:08:37.611398 best_step = 11
5892 11:08:37.611733
5893 11:08:37.612048 ==
5894 11:08:37.614374 Dram Type= 6, Freq= 0, CH_1, rank 1
5895 11:08:37.621374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5896 11:08:37.621798 ==
5897 11:08:37.622181 RX Vref Scan: 0
5898 11:08:37.622500
5899 11:08:37.624607 RX Vref 0 -> 0, step: 1
5900 11:08:37.625025
5901 11:08:37.627800 RX Delay -53 -> 252, step: 4
5902 11:08:37.631032 iDelay=199, Bit 0, Center 112 (39 ~ 186) 148
5903 11:08:37.638066 iDelay=199, Bit 1, Center 102 (27 ~ 178) 152
5904 11:08:37.641049 iDelay=199, Bit 2, Center 96 (23 ~ 170) 148
5905 11:08:37.644331 iDelay=199, Bit 3, Center 104 (27 ~ 182) 156
5906 11:08:37.647661 iDelay=199, Bit 4, Center 108 (31 ~ 186) 156
5907 11:08:37.650962 iDelay=199, Bit 5, Center 118 (39 ~ 198) 160
5908 11:08:37.654336 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5909 11:08:37.660794 iDelay=199, Bit 7, Center 104 (27 ~ 182) 156
5910 11:08:37.664359 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5911 11:08:37.667782 iDelay=199, Bit 9, Center 90 (11 ~ 170) 160
5912 11:08:37.671006 iDelay=199, Bit 10, Center 100 (19 ~ 182) 164
5913 11:08:37.674188 iDelay=199, Bit 11, Center 96 (15 ~ 178) 164
5914 11:08:37.680808 iDelay=199, Bit 12, Center 108 (27 ~ 190) 164
5915 11:08:37.684129 iDelay=199, Bit 13, Center 106 (27 ~ 186) 160
5916 11:08:37.687300 iDelay=199, Bit 14, Center 106 (19 ~ 194) 176
5917 11:08:37.691063 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5918 11:08:37.691484 ==
5919 11:08:37.694292 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 11:08:37.700819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 11:08:37.701272 ==
5922 11:08:37.701692 DQS Delay:
5923 11:08:37.702112 DQS0 = 0, DQS1 = 0
5924 11:08:37.704092 DQM Delay:
5925 11:08:37.704582 DQM0 = 107, DQM1 = 100
5926 11:08:37.707395 DQ Delay:
5927 11:08:37.710906 DQ0 =112, DQ1 =102, DQ2 =96, DQ3 =104
5928 11:08:37.714170 DQ4 =108, DQ5 =118, DQ6 =114, DQ7 =104
5929 11:08:37.717493 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =96
5930 11:08:37.720863 DQ12 =108, DQ13 =106, DQ14 =106, DQ15 =108
5931 11:08:37.721345
5932 11:08:37.721740
5933 11:08:37.727443 [DQSOSCAuto] RK1, (LSB)MR18= 0x22ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
5934 11:08:37.730710 CH1 RK1: MR19=504, MR18=22FF
5935 11:08:37.737394 CH1_RK1: MR19=0x504, MR18=0x22FF, DQSOSC=411, MR23=63, INC=64, DEC=42
5936 11:08:37.740710 [RxdqsGatingPostProcess] freq 933
5937 11:08:37.747322 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5938 11:08:37.750878 best DQS0 dly(2T, 0.5T) = (0, 10)
5939 11:08:37.751381 best DQS1 dly(2T, 0.5T) = (0, 10)
5940 11:08:37.754214 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5941 11:08:37.757314 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5942 11:08:37.760558 best DQS0 dly(2T, 0.5T) = (0, 10)
5943 11:08:37.764149 best DQS1 dly(2T, 0.5T) = (0, 10)
5944 11:08:37.767468 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5945 11:08:37.770539 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5946 11:08:37.773813 Pre-setting of DQS Precalculation
5947 11:08:37.780678 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5948 11:08:37.787446 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5949 11:08:37.794167 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5950 11:08:37.794596
5951 11:08:37.794976
5952 11:08:37.796968 [Calibration Summary] 1866 Mbps
5953 11:08:37.797429 CH 0, Rank 0
5954 11:08:37.800493 SW Impedance : PASS
5955 11:08:37.803744 DUTY Scan : NO K
5956 11:08:37.804234 ZQ Calibration : PASS
5957 11:08:37.807150 Jitter Meter : NO K
5958 11:08:37.810372 CBT Training : PASS
5959 11:08:37.810874 Write leveling : PASS
5960 11:08:37.813886 RX DQS gating : PASS
5961 11:08:37.814365 RX DQ/DQS(RDDQC) : PASS
5962 11:08:37.817123 TX DQ/DQS : PASS
5963 11:08:37.820443 RX DATLAT : PASS
5964 11:08:37.820864 RX DQ/DQS(Engine): PASS
5965 11:08:37.823866 TX OE : NO K
5966 11:08:37.824286 All Pass.
5967 11:08:37.824680
5968 11:08:37.827110 CH 0, Rank 1
5969 11:08:37.827585 SW Impedance : PASS
5970 11:08:37.830301 DUTY Scan : NO K
5971 11:08:37.833624 ZQ Calibration : PASS
5972 11:08:37.834086 Jitter Meter : NO K
5973 11:08:37.837298 CBT Training : PASS
5974 11:08:37.840421 Write leveling : PASS
5975 11:08:37.840844 RX DQS gating : PASS
5976 11:08:37.844014 RX DQ/DQS(RDDQC) : PASS
5977 11:08:37.847441 TX DQ/DQS : PASS
5978 11:08:37.847873 RX DATLAT : PASS
5979 11:08:37.850601 RX DQ/DQS(Engine): PASS
5980 11:08:37.853911 TX OE : NO K
5981 11:08:37.854373 All Pass.
5982 11:08:37.854783
5983 11:08:37.855105 CH 1, Rank 0
5984 11:08:37.856794 SW Impedance : PASS
5985 11:08:37.860394 DUTY Scan : NO K
5986 11:08:37.860814 ZQ Calibration : PASS
5987 11:08:37.863689 Jitter Meter : NO K
5988 11:08:37.864155 CBT Training : PASS
5989 11:08:37.866939 Write leveling : PASS
5990 11:08:37.870432 RX DQS gating : PASS
5991 11:08:37.870885 RX DQ/DQS(RDDQC) : PASS
5992 11:08:37.873666 TX DQ/DQS : PASS
5993 11:08:37.877022 RX DATLAT : PASS
5994 11:08:37.877488 RX DQ/DQS(Engine): PASS
5995 11:08:37.880019 TX OE : NO K
5996 11:08:37.880483 All Pass.
5997 11:08:37.880713
5998 11:08:37.883329 CH 1, Rank 1
5999 11:08:37.883410 SW Impedance : PASS
6000 11:08:37.886336 DUTY Scan : NO K
6001 11:08:37.890203 ZQ Calibration : PASS
6002 11:08:37.890285 Jitter Meter : NO K
6003 11:08:37.892976 CBT Training : PASS
6004 11:08:37.896596 Write leveling : PASS
6005 11:08:37.896684 RX DQS gating : PASS
6006 11:08:37.899943 RX DQ/DQS(RDDQC) : PASS
6007 11:08:37.903195 TX DQ/DQS : PASS
6008 11:08:37.903290 RX DATLAT : PASS
6009 11:08:37.906670 RX DQ/DQS(Engine): PASS
6010 11:08:37.909685 TX OE : NO K
6011 11:08:37.909823 All Pass.
6012 11:08:37.909946
6013 11:08:37.910028 DramC Write-DBI off
6014 11:08:37.912760 PER_BANK_REFRESH: Hybrid Mode
6015 11:08:37.916458 TX_TRACKING: ON
6016 11:08:37.923206 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6017 11:08:37.926507 [FAST_K] Save calibration result to emmc
6018 11:08:37.933391 dramc_set_vcore_voltage set vcore to 650000
6019 11:08:37.933566 Read voltage for 400, 6
6020 11:08:37.933732 Vio18 = 0
6021 11:08:37.936718 Vcore = 650000
6022 11:08:37.936919 Vdram = 0
6023 11:08:37.937079 Vddq = 0
6024 11:08:37.940088 Vmddr = 0
6025 11:08:37.943377 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6026 11:08:37.950178 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6027 11:08:37.953100 MEM_TYPE=3, freq_sel=20
6028 11:08:37.953529 sv_algorithm_assistance_LP4_800
6029 11:08:37.959860 ============ PULL DRAM RESETB DOWN ============
6030 11:08:37.963179 ========== PULL DRAM RESETB DOWN end =========
6031 11:08:37.966549 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6032 11:08:37.970244 ===================================
6033 11:08:37.973090 LPDDR4 DRAM CONFIGURATION
6034 11:08:37.976827 ===================================
6035 11:08:37.980159 EX_ROW_EN[0] = 0x0
6036 11:08:37.980580 EX_ROW_EN[1] = 0x0
6037 11:08:37.983300 LP4Y_EN = 0x0
6038 11:08:37.983722 WORK_FSP = 0x0
6039 11:08:37.986505 WL = 0x2
6040 11:08:37.986965 RL = 0x2
6041 11:08:37.989894 BL = 0x2
6042 11:08:37.990348 RPST = 0x0
6043 11:08:37.993320 RD_PRE = 0x0
6044 11:08:37.993736 WR_PRE = 0x1
6045 11:08:37.996425 WR_PST = 0x0
6046 11:08:37.996846 DBI_WR = 0x0
6047 11:08:37.999727 DBI_RD = 0x0
6048 11:08:38.000147 OTF = 0x1
6049 11:08:38.003521 ===================================
6050 11:08:38.006685 ===================================
6051 11:08:38.009999 ANA top config
6052 11:08:38.013158 ===================================
6053 11:08:38.016616 DLL_ASYNC_EN = 0
6054 11:08:38.017034 ALL_SLAVE_EN = 1
6055 11:08:38.019844 NEW_RANK_MODE = 1
6056 11:08:38.023154 DLL_IDLE_MODE = 1
6057 11:08:38.026275 LP45_APHY_COMB_EN = 1
6058 11:08:38.026743 TX_ODT_DIS = 1
6059 11:08:38.029847 NEW_8X_MODE = 1
6060 11:08:38.032817 ===================================
6061 11:08:38.036488 ===================================
6062 11:08:38.039719 data_rate = 800
6063 11:08:38.043039 CKR = 1
6064 11:08:38.046201 DQ_P2S_RATIO = 4
6065 11:08:38.049823 ===================================
6066 11:08:38.052941 CA_P2S_RATIO = 4
6067 11:08:38.053439 DQ_CA_OPEN = 0
6068 11:08:38.056255 DQ_SEMI_OPEN = 1
6069 11:08:38.059543 CA_SEMI_OPEN = 1
6070 11:08:38.062782 CA_FULL_RATE = 0
6071 11:08:38.065733 DQ_CKDIV4_EN = 0
6072 11:08:38.069540 CA_CKDIV4_EN = 1
6073 11:08:38.070098 CA_PREDIV_EN = 0
6074 11:08:38.072890 PH8_DLY = 0
6075 11:08:38.076266 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6076 11:08:38.079404 DQ_AAMCK_DIV = 0
6077 11:08:38.082790 CA_AAMCK_DIV = 0
6078 11:08:38.085907 CA_ADMCK_DIV = 4
6079 11:08:38.086378 DQ_TRACK_CA_EN = 0
6080 11:08:38.089077 CA_PICK = 800
6081 11:08:38.092677 CA_MCKIO = 400
6082 11:08:38.095894 MCKIO_SEMI = 400
6083 11:08:38.099354 PLL_FREQ = 3016
6084 11:08:38.102892 DQ_UI_PI_RATIO = 32
6085 11:08:38.106106 CA_UI_PI_RATIO = 32
6086 11:08:38.109273 ===================================
6087 11:08:38.112545 ===================================
6088 11:08:38.112984 memory_type:LPDDR4
6089 11:08:38.115571 GP_NUM : 10
6090 11:08:38.118927 SRAM_EN : 1
6091 11:08:38.119349 MD32_EN : 0
6092 11:08:38.122285 ===================================
6093 11:08:38.125930 [ANA_INIT] >>>>>>>>>>>>>>
6094 11:08:38.129054 <<<<<< [CONFIGURE PHASE]: ANA_TX
6095 11:08:38.132480 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6096 11:08:38.135888 ===================================
6097 11:08:38.139090 data_rate = 800,PCW = 0X7400
6098 11:08:38.142256 ===================================
6099 11:08:38.145486 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6100 11:08:38.149181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6101 11:08:38.161802 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6102 11:08:38.165289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6103 11:08:38.168704 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6104 11:08:38.171861 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6105 11:08:38.175168 [ANA_INIT] flow start
6106 11:08:38.178870 [ANA_INIT] PLL >>>>>>>>
6107 11:08:38.179000 [ANA_INIT] PLL <<<<<<<<
6108 11:08:38.182543 [ANA_INIT] MIDPI >>>>>>>>
6109 11:08:38.185304 [ANA_INIT] MIDPI <<<<<<<<
6110 11:08:38.185902 [ANA_INIT] DLL >>>>>>>>
6111 11:08:38.188782 [ANA_INIT] flow end
6112 11:08:38.192229 ============ LP4 DIFF to SE enter ============
6113 11:08:38.195409 ============ LP4 DIFF to SE exit ============
6114 11:08:38.198546 [ANA_INIT] <<<<<<<<<<<<<
6115 11:08:38.202115 [Flow] Enable top DCM control >>>>>
6116 11:08:38.205600 [Flow] Enable top DCM control <<<<<
6117 11:08:38.209045 Enable DLL master slave shuffle
6118 11:08:38.214973 ==============================================================
6119 11:08:38.215056 Gating Mode config
6120 11:08:38.221777 ==============================================================
6121 11:08:38.221868 Config description:
6122 11:08:38.231696 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6123 11:08:38.238392 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6124 11:08:38.244825 SELPH_MODE 0: By rank 1: By Phase
6125 11:08:38.248500 ==============================================================
6126 11:08:38.251754 GAT_TRACK_EN = 0
6127 11:08:38.254984 RX_GATING_MODE = 2
6128 11:08:38.258566 RX_GATING_TRACK_MODE = 2
6129 11:08:38.261646 SELPH_MODE = 1
6130 11:08:38.264730 PICG_EARLY_EN = 1
6131 11:08:38.268132 VALID_LAT_VALUE = 1
6132 11:08:38.275001 ==============================================================
6133 11:08:38.278225 Enter into Gating configuration >>>>
6134 11:08:38.281977 Exit from Gating configuration <<<<
6135 11:08:38.282101 Enter into DVFS_PRE_config >>>>>
6136 11:08:38.294731 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6137 11:08:38.298860 Exit from DVFS_PRE_config <<<<<
6138 11:08:38.302039 Enter into PICG configuration >>>>
6139 11:08:38.304782 Exit from PICG configuration <<<<
6140 11:08:38.304865 [RX_INPUT] configuration >>>>>
6141 11:08:38.308227 [RX_INPUT] configuration <<<<<
6142 11:08:38.315015 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6143 11:08:38.318279 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6144 11:08:38.324818 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6145 11:08:38.331695 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6146 11:08:38.338164 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6147 11:08:38.344967 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6148 11:08:38.348114 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6149 11:08:38.351584 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6150 11:08:38.354975 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6151 11:08:38.361545 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6152 11:08:38.364697 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6153 11:08:38.368277 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6154 11:08:38.371565 ===================================
6155 11:08:38.374717 LPDDR4 DRAM CONFIGURATION
6156 11:08:38.378106 ===================================
6157 11:08:38.381370 EX_ROW_EN[0] = 0x0
6158 11:08:38.381536 EX_ROW_EN[1] = 0x0
6159 11:08:38.384874 LP4Y_EN = 0x0
6160 11:08:38.385048 WORK_FSP = 0x0
6161 11:08:38.388142 WL = 0x2
6162 11:08:38.388345 RL = 0x2
6163 11:08:38.391332 BL = 0x2
6164 11:08:38.391550 RPST = 0x0
6165 11:08:38.395045 RD_PRE = 0x0
6166 11:08:38.395284 WR_PRE = 0x1
6167 11:08:38.398070 WR_PST = 0x0
6168 11:08:38.398368 DBI_WR = 0x0
6169 11:08:38.401337 DBI_RD = 0x0
6170 11:08:38.401697 OTF = 0x1
6171 11:08:38.405025 ===================================
6172 11:08:38.411672 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6173 11:08:38.414751 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6174 11:08:38.418195 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6175 11:08:38.422098 ===================================
6176 11:08:38.424771 LPDDR4 DRAM CONFIGURATION
6177 11:08:38.428104 ===================================
6178 11:08:38.431090 EX_ROW_EN[0] = 0x10
6179 11:08:38.431510 EX_ROW_EN[1] = 0x0
6180 11:08:38.434590 LP4Y_EN = 0x0
6181 11:08:38.435011 WORK_FSP = 0x0
6182 11:08:38.437789 WL = 0x2
6183 11:08:38.438226 RL = 0x2
6184 11:08:38.441394 BL = 0x2
6185 11:08:38.441813 RPST = 0x0
6186 11:08:38.444607 RD_PRE = 0x0
6187 11:08:38.445024 WR_PRE = 0x1
6188 11:08:38.447972 WR_PST = 0x0
6189 11:08:38.448392 DBI_WR = 0x0
6190 11:08:38.451179 DBI_RD = 0x0
6191 11:08:38.451596 OTF = 0x1
6192 11:08:38.454475 ===================================
6193 11:08:38.461134 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6194 11:08:38.465750 nWR fixed to 30
6195 11:08:38.469437 [ModeRegInit_LP4] CH0 RK0
6196 11:08:38.469855 [ModeRegInit_LP4] CH0 RK1
6197 11:08:38.472507 [ModeRegInit_LP4] CH1 RK0
6198 11:08:38.476222 [ModeRegInit_LP4] CH1 RK1
6199 11:08:38.476637 match AC timing 19
6200 11:08:38.482827 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6201 11:08:38.486148 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6202 11:08:38.489272 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6203 11:08:38.495747 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6204 11:08:38.499009 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6205 11:08:38.499428 ==
6206 11:08:38.502475 Dram Type= 6, Freq= 0, CH_0, rank 0
6207 11:08:38.505658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6208 11:08:38.506136 ==
6209 11:08:38.512361 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6210 11:08:38.518832 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6211 11:08:38.522087 [CA 0] Center 36 (8~64) winsize 57
6212 11:08:38.526067 [CA 1] Center 36 (8~64) winsize 57
6213 11:08:38.528665 [CA 2] Center 36 (8~64) winsize 57
6214 11:08:38.532195 [CA 3] Center 36 (8~64) winsize 57
6215 11:08:38.532620 [CA 4] Center 36 (8~64) winsize 57
6216 11:08:38.535338 [CA 5] Center 36 (8~64) winsize 57
6217 11:08:38.535761
6218 11:08:38.542052 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6219 11:08:38.542477
6220 11:08:38.545653 [CATrainingPosCal] consider 1 rank data
6221 11:08:38.549083 u2DelayCellTimex100 = 270/100 ps
6222 11:08:38.551989 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 11:08:38.555265 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 11:08:38.558650 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 11:08:38.562108 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 11:08:38.565039 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 11:08:38.568760 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 11:08:38.569185
6229 11:08:38.572297 CA PerBit enable=1, Macro0, CA PI delay=36
6230 11:08:38.572718
6231 11:08:38.575126 [CBTSetCACLKResult] CA Dly = 36
6232 11:08:38.578831 CS Dly: 1 (0~32)
6233 11:08:38.579256 ==
6234 11:08:38.582218 Dram Type= 6, Freq= 0, CH_0, rank 1
6235 11:08:38.585494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6236 11:08:38.585919 ==
6237 11:08:38.592123 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6238 11:08:38.598507 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6239 11:08:38.598932 [CA 0] Center 36 (8~64) winsize 57
6240 11:08:38.601843 [CA 1] Center 36 (8~64) winsize 57
6241 11:08:38.605110 [CA 2] Center 36 (8~64) winsize 57
6242 11:08:38.608007 [CA 3] Center 36 (8~64) winsize 57
6243 11:08:38.612054 [CA 4] Center 36 (8~64) winsize 57
6244 11:08:38.615395 [CA 5] Center 36 (8~64) winsize 57
6245 11:08:38.615847
6246 11:08:38.618708 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6247 11:08:38.619130
6248 11:08:38.622037 [CATrainingPosCal] consider 2 rank data
6249 11:08:38.625169 u2DelayCellTimex100 = 270/100 ps
6250 11:08:38.628455 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 11:08:38.631978 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 11:08:38.638488 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 11:08:38.641572 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 11:08:38.645225 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 11:08:38.648744 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 11:08:38.649326
6257 11:08:38.651668 CA PerBit enable=1, Macro0, CA PI delay=36
6258 11:08:38.652138
6259 11:08:38.655432 [CBTSetCACLKResult] CA Dly = 36
6260 11:08:38.656002 CS Dly: 1 (0~32)
6261 11:08:38.656381
6262 11:08:38.658699 ----->DramcWriteLeveling(PI) begin...
6263 11:08:38.661716 ==
6264 11:08:38.665345 Dram Type= 6, Freq= 0, CH_0, rank 0
6265 11:08:38.668599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 11:08:38.669174 ==
6267 11:08:38.671795 Write leveling (Byte 0): 40 => 8
6268 11:08:38.675114 Write leveling (Byte 1): 32 => 0
6269 11:08:38.678650 DramcWriteLeveling(PI) end<-----
6270 11:08:38.679225
6271 11:08:38.679599 ==
6272 11:08:38.682013 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 11:08:38.685418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 11:08:38.686033 ==
6275 11:08:38.688457 [Gating] SW mode calibration
6276 11:08:38.695127 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6277 11:08:38.698480 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6278 11:08:38.705413 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6279 11:08:38.707997 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6280 11:08:38.711623 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 11:08:38.718450 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 11:08:38.721721 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 11:08:38.724794 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 11:08:38.731405 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 11:08:38.734579 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 11:08:38.737991 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 11:08:38.741343 Total UI for P1: 0, mck2ui 16
6288 11:08:38.745189 best dqsien dly found for B0: ( 0, 14, 24)
6289 11:08:38.748050 Total UI for P1: 0, mck2ui 16
6290 11:08:38.751021 best dqsien dly found for B1: ( 0, 14, 24)
6291 11:08:38.754310 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6292 11:08:38.760959 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6293 11:08:38.761460
6294 11:08:38.764419 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6295 11:08:38.767613 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6296 11:08:38.770859 [Gating] SW calibration Done
6297 11:08:38.771315 ==
6298 11:08:38.774311 Dram Type= 6, Freq= 0, CH_0, rank 0
6299 11:08:38.777578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6300 11:08:38.778073 ==
6301 11:08:38.778446 RX Vref Scan: 0
6302 11:08:38.780942
6303 11:08:38.781397 RX Vref 0 -> 0, step: 1
6304 11:08:38.781759
6305 11:08:38.784365 RX Delay -410 -> 252, step: 16
6306 11:08:38.787629 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6307 11:08:38.794144 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6308 11:08:38.797681 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6309 11:08:38.801034 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6310 11:08:38.804284 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6311 11:08:38.810658 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6312 11:08:38.814133 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6313 11:08:38.817877 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6314 11:08:38.821036 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6315 11:08:38.827485 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6316 11:08:38.830613 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6317 11:08:38.834269 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6318 11:08:38.837524 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6319 11:08:38.844223 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6320 11:08:38.847458 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6321 11:08:38.851029 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6322 11:08:38.851623 ==
6323 11:08:38.854086 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 11:08:38.860698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 11:08:38.861261 ==
6326 11:08:38.861626 DQS Delay:
6327 11:08:38.864137 DQS0 = 27, DQS1 = 43
6328 11:08:38.864581 DQM Delay:
6329 11:08:38.864936 DQM0 = 12, DQM1 = 13
6330 11:08:38.867461 DQ Delay:
6331 11:08:38.870938 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6332 11:08:38.871508 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6333 11:08:38.874155 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6334 11:08:38.877642 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6335 11:08:38.878263
6336 11:08:38.878626
6337 11:08:38.880908 ==
6338 11:08:38.884250 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 11:08:38.887385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 11:08:38.887982 ==
6341 11:08:38.888361
6342 11:08:38.888688
6343 11:08:38.890788 TX Vref Scan disable
6344 11:08:38.891347 == TX Byte 0 ==
6345 11:08:38.894312 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 11:08:38.901035 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 11:08:38.901587 == TX Byte 1 ==
6348 11:08:38.903923 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6349 11:08:38.911407 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6350 11:08:38.911963 ==
6351 11:08:38.914459 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 11:08:38.918177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 11:08:38.918745 ==
6354 11:08:38.919110
6355 11:08:38.919441
6356 11:08:38.920591 TX Vref Scan disable
6357 11:08:38.921034 == TX Byte 0 ==
6358 11:08:38.923965 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6359 11:08:38.930682 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6360 11:08:38.931144 == TX Byte 1 ==
6361 11:08:38.934109 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6362 11:08:38.941064 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6363 11:08:38.941620
6364 11:08:38.942039 [DATLAT]
6365 11:08:38.942522 Freq=400, CH0 RK0
6366 11:08:38.943852
6367 11:08:38.944304 DATLAT Default: 0xf
6368 11:08:38.947274 0, 0xFFFF, sum = 0
6369 11:08:38.947845 1, 0xFFFF, sum = 0
6370 11:08:38.950874 2, 0xFFFF, sum = 0
6371 11:08:38.951434 3, 0xFFFF, sum = 0
6372 11:08:38.954098 4, 0xFFFF, sum = 0
6373 11:08:38.954665 5, 0xFFFF, sum = 0
6374 11:08:38.957421 6, 0xFFFF, sum = 0
6375 11:08:38.958007 7, 0xFFFF, sum = 0
6376 11:08:38.960412 8, 0xFFFF, sum = 0
6377 11:08:38.960880 9, 0xFFFF, sum = 0
6378 11:08:38.963932 10, 0xFFFF, sum = 0
6379 11:08:38.964499 11, 0xFFFF, sum = 0
6380 11:08:38.967286 12, 0xFFFF, sum = 0
6381 11:08:38.967754 13, 0x0, sum = 1
6382 11:08:38.970421 14, 0x0, sum = 2
6383 11:08:38.970885 15, 0x0, sum = 3
6384 11:08:38.974239 16, 0x0, sum = 4
6385 11:08:38.974806 best_step = 14
6386 11:08:38.975174
6387 11:08:38.975514 ==
6388 11:08:38.977075 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 11:08:38.984028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 11:08:38.984586 ==
6391 11:08:38.984955 RX Vref Scan: 1
6392 11:08:38.985299
6393 11:08:38.986733 RX Vref 0 -> 0, step: 1
6394 11:08:38.987190
6395 11:08:38.990585 RX Delay -327 -> 252, step: 8
6396 11:08:38.991045
6397 11:08:38.993571 Set Vref, RX VrefLevel [Byte0]: 59
6398 11:08:38.997167 [Byte1]: 50
6399 11:08:38.997735
6400 11:08:39.000607 Final RX Vref Byte 0 = 59 to rank0
6401 11:08:39.003793 Final RX Vref Byte 1 = 50 to rank0
6402 11:08:39.007397 Final RX Vref Byte 0 = 59 to rank1
6403 11:08:39.010828 Final RX Vref Byte 1 = 50 to rank1==
6404 11:08:39.013685 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 11:08:39.017123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 11:08:39.020298 ==
6407 11:08:39.020758 DQS Delay:
6408 11:08:39.021126 DQS0 = 28, DQS1 = 48
6409 11:08:39.023553 DQM Delay:
6410 11:08:39.024224 DQM0 = 12, DQM1 = 15
6411 11:08:39.027094 DQ Delay:
6412 11:08:39.027651 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6413 11:08:39.030191 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6414 11:08:39.033276 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6415 11:08:39.037164 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6416 11:08:39.037724
6417 11:08:39.038148
6418 11:08:39.046489 [DQSOSCAuto] RK0, (LSB)MR18= 0xaaa2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6419 11:08:39.050514 CH0 RK0: MR19=C0C, MR18=AAA2
6420 11:08:39.056812 CH0_RK0: MR19=0xC0C, MR18=0xAAA2, DQSOSC=388, MR23=63, INC=392, DEC=261
6421 11:08:39.057387 ==
6422 11:08:39.059764 Dram Type= 6, Freq= 0, CH_0, rank 1
6423 11:08:39.063456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 11:08:39.064106 ==
6425 11:08:39.066677 [Gating] SW mode calibration
6426 11:08:39.073043 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6427 11:08:39.076936 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6428 11:08:39.083164 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6429 11:08:39.086284 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6430 11:08:39.089711 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 11:08:39.096591 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 11:08:39.099867 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 11:08:39.102999 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 11:08:39.110120 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 11:08:39.113407 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 11:08:39.116452 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 11:08:39.119842 Total UI for P1: 0, mck2ui 16
6438 11:08:39.123024 best dqsien dly found for B0: ( 0, 14, 24)
6439 11:08:39.126061 Total UI for P1: 0, mck2ui 16
6440 11:08:39.129803 best dqsien dly found for B1: ( 0, 14, 24)
6441 11:08:39.133228 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6442 11:08:39.136346 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6443 11:08:39.139719
6444 11:08:39.143236 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6445 11:08:39.146849 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6446 11:08:39.149690 [Gating] SW calibration Done
6447 11:08:39.150293 ==
6448 11:08:39.152622 Dram Type= 6, Freq= 0, CH_0, rank 1
6449 11:08:39.156318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 11:08:39.156897 ==
6451 11:08:39.157385 RX Vref Scan: 0
6452 11:08:39.157841
6453 11:08:39.159324 RX Vref 0 -> 0, step: 1
6454 11:08:39.159801
6455 11:08:39.162832 RX Delay -410 -> 252, step: 16
6456 11:08:39.166558 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6457 11:08:39.173038 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6458 11:08:39.176358 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6459 11:08:39.179633 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6460 11:08:39.182583 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6461 11:08:39.189489 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6462 11:08:39.192492 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6463 11:08:39.196305 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6464 11:08:39.199467 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6465 11:08:39.206557 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6466 11:08:39.209456 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6467 11:08:39.212795 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6468 11:08:39.215805 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6469 11:08:39.222620 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6470 11:08:39.225837 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6471 11:08:39.229327 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6472 11:08:39.229894 ==
6473 11:08:39.232587 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 11:08:39.235989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 11:08:39.239102 ==
6476 11:08:39.239667 DQS Delay:
6477 11:08:39.240041 DQS0 = 19, DQS1 = 43
6478 11:08:39.242453 DQM Delay:
6479 11:08:39.242910 DQM0 = 3, DQM1 = 16
6480 11:08:39.245841 DQ Delay:
6481 11:08:39.246354 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6482 11:08:39.249123 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =8
6483 11:08:39.252571 DQ8 =0, DQ9 =0, DQ10 =24, DQ11 =8
6484 11:08:39.255937 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6485 11:08:39.256522
6486 11:08:39.256897
6487 11:08:39.257236 ==
6488 11:08:39.258641 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 11:08:39.265486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 11:08:39.266011 ==
6491 11:08:39.266431
6492 11:08:39.266827
6493 11:08:39.267161 TX Vref Scan disable
6494 11:08:39.268929 == TX Byte 0 ==
6495 11:08:39.271973 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6496 11:08:39.275268 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6497 11:08:39.278638 == TX Byte 1 ==
6498 11:08:39.282089 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6499 11:08:39.285362 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6500 11:08:39.288781 ==
6501 11:08:39.289421 Dram Type= 6, Freq= 0, CH_0, rank 1
6502 11:08:39.295363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 11:08:39.295840 ==
6504 11:08:39.296212
6505 11:08:39.296582
6506 11:08:39.298736 TX Vref Scan disable
6507 11:08:39.299253 == TX Byte 0 ==
6508 11:08:39.301996 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6509 11:08:39.308636 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6510 11:08:39.308770 == TX Byte 1 ==
6511 11:08:39.311644 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6512 11:08:39.318162 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6513 11:08:39.318243
6514 11:08:39.318309 [DATLAT]
6515 11:08:39.318368 Freq=400, CH0 RK1
6516 11:08:39.318427
6517 11:08:39.321426 DATLAT Default: 0xe
6518 11:08:39.321507 0, 0xFFFF, sum = 0
6519 11:08:39.324709 1, 0xFFFF, sum = 0
6520 11:08:39.324791 2, 0xFFFF, sum = 0
6521 11:08:39.328382 3, 0xFFFF, sum = 0
6522 11:08:39.328524 4, 0xFFFF, sum = 0
6523 11:08:39.331302 5, 0xFFFF, sum = 0
6524 11:08:39.335036 6, 0xFFFF, sum = 0
6525 11:08:39.335124 7, 0xFFFF, sum = 0
6526 11:08:39.338320 8, 0xFFFF, sum = 0
6527 11:08:39.338414 9, 0xFFFF, sum = 0
6528 11:08:39.341608 10, 0xFFFF, sum = 0
6529 11:08:39.341690 11, 0xFFFF, sum = 0
6530 11:08:39.344727 12, 0xFFFF, sum = 0
6531 11:08:39.344812 13, 0x0, sum = 1
6532 11:08:39.348011 14, 0x0, sum = 2
6533 11:08:39.348098 15, 0x0, sum = 3
6534 11:08:39.351249 16, 0x0, sum = 4
6535 11:08:39.351333 best_step = 14
6536 11:08:39.351399
6537 11:08:39.351459 ==
6538 11:08:39.354729 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 11:08:39.358111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 11:08:39.358194 ==
6541 11:08:39.361033 RX Vref Scan: 0
6542 11:08:39.361116
6543 11:08:39.364428 RX Vref 0 -> 0, step: 1
6544 11:08:39.364510
6545 11:08:39.364577 RX Delay -327 -> 252, step: 8
6546 11:08:39.373717 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6547 11:08:39.376908 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6548 11:08:39.380268 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6549 11:08:39.383493 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6550 11:08:39.389872 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6551 11:08:39.393630 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6552 11:08:39.396696 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6553 11:08:39.400047 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6554 11:08:39.406329 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6555 11:08:39.409911 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6556 11:08:39.413583 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6557 11:08:39.417104 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6558 11:08:39.423452 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6559 11:08:39.426843 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6560 11:08:39.430200 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6561 11:08:39.433965 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6562 11:08:39.436943 ==
6563 11:08:39.440270 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 11:08:39.443940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 11:08:39.444460 ==
6566 11:08:39.444808 DQS Delay:
6567 11:08:39.447049 DQS0 = 28, DQS1 = 44
6568 11:08:39.447463 DQM Delay:
6569 11:08:39.450254 DQM0 = 10, DQM1 = 15
6570 11:08:39.450709 DQ Delay:
6571 11:08:39.453504 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6572 11:08:39.457158 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6573 11:08:39.460647 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6574 11:08:39.463830 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6575 11:08:39.464294
6576 11:08:39.464658
6577 11:08:39.470367 [DQSOSCAuto] RK1, (LSB)MR18= 0xb467, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6578 11:08:39.473633 CH0 RK1: MR19=C0C, MR18=B467
6579 11:08:39.480525 CH0_RK1: MR19=0xC0C, MR18=0xB467, DQSOSC=387, MR23=63, INC=394, DEC=262
6580 11:08:39.483701 [RxdqsGatingPostProcess] freq 400
6581 11:08:39.486924 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6582 11:08:39.490134 best DQS0 dly(2T, 0.5T) = (0, 10)
6583 11:08:39.493537 best DQS1 dly(2T, 0.5T) = (0, 10)
6584 11:08:39.496925 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6585 11:08:39.500490 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6586 11:08:39.503799 best DQS0 dly(2T, 0.5T) = (0, 10)
6587 11:08:39.507044 best DQS1 dly(2T, 0.5T) = (0, 10)
6588 11:08:39.510359 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6589 11:08:39.513432 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6590 11:08:39.516725 Pre-setting of DQS Precalculation
6591 11:08:39.519952 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6592 11:08:39.523385 ==
6593 11:08:39.523969 Dram Type= 6, Freq= 0, CH_1, rank 0
6594 11:08:39.530112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 11:08:39.530573 ==
6596 11:08:39.533354 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6597 11:08:39.540249 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6598 11:08:39.543435 [CA 0] Center 36 (8~64) winsize 57
6599 11:08:39.546844 [CA 1] Center 36 (8~64) winsize 57
6600 11:08:39.549925 [CA 2] Center 36 (8~64) winsize 57
6601 11:08:39.553464 [CA 3] Center 36 (8~64) winsize 57
6602 11:08:39.556643 [CA 4] Center 36 (8~64) winsize 57
6603 11:08:39.560278 [CA 5] Center 36 (8~64) winsize 57
6604 11:08:39.560835
6605 11:08:39.563598 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6606 11:08:39.564158
6607 11:08:39.566419 [CATrainingPosCal] consider 1 rank data
6608 11:08:39.570043 u2DelayCellTimex100 = 270/100 ps
6609 11:08:39.573604 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 11:08:39.576838 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 11:08:39.580193 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 11:08:39.583115 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 11:08:39.590050 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 11:08:39.593024 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 11:08:39.593590
6616 11:08:39.596125 CA PerBit enable=1, Macro0, CA PI delay=36
6617 11:08:39.596586
6618 11:08:39.599718 [CBTSetCACLKResult] CA Dly = 36
6619 11:08:39.600281 CS Dly: 1 (0~32)
6620 11:08:39.600646 ==
6621 11:08:39.603233 Dram Type= 6, Freq= 0, CH_1, rank 1
6622 11:08:39.606669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6623 11:08:39.610125 ==
6624 11:08:39.613355 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6625 11:08:39.619640 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6626 11:08:39.622932 [CA 0] Center 36 (8~64) winsize 57
6627 11:08:39.626204 [CA 1] Center 36 (8~64) winsize 57
6628 11:08:39.629818 [CA 2] Center 36 (8~64) winsize 57
6629 11:08:39.632948 [CA 3] Center 36 (8~64) winsize 57
6630 11:08:39.636652 [CA 4] Center 36 (8~64) winsize 57
6631 11:08:39.639596 [CA 5] Center 36 (8~64) winsize 57
6632 11:08:39.640155
6633 11:08:39.642794 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6634 11:08:39.643263
6635 11:08:39.646390 [CATrainingPosCal] consider 2 rank data
6636 11:08:39.649882 u2DelayCellTimex100 = 270/100 ps
6637 11:08:39.652932 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 11:08:39.656522 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 11:08:39.659757 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 11:08:39.663233 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 11:08:39.666631 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 11:08:39.669827 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 11:08:39.670515
6644 11:08:39.672984 CA PerBit enable=1, Macro0, CA PI delay=36
6645 11:08:39.673547
6646 11:08:39.676358 [CBTSetCACLKResult] CA Dly = 36
6647 11:08:39.679715 CS Dly: 1 (0~32)
6648 11:08:39.680278
6649 11:08:39.682869 ----->DramcWriteLeveling(PI) begin...
6650 11:08:39.683443 ==
6651 11:08:39.686348 Dram Type= 6, Freq= 0, CH_1, rank 0
6652 11:08:39.689624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 11:08:39.690366 ==
6654 11:08:39.692846 Write leveling (Byte 0): 40 => 8
6655 11:08:39.696104 Write leveling (Byte 1): 32 => 0
6656 11:08:39.700088 DramcWriteLeveling(PI) end<-----
6657 11:08:39.700648
6658 11:08:39.701015 ==
6659 11:08:39.703352 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 11:08:39.706586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 11:08:39.707174 ==
6662 11:08:39.709681 [Gating] SW mode calibration
6663 11:08:39.716393 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6664 11:08:39.723058 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6665 11:08:39.726496 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6666 11:08:39.729572 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6667 11:08:39.736252 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 11:08:39.739472 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6669 11:08:39.742980 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 11:08:39.749736 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 11:08:39.752897 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 11:08:39.756444 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6673 11:08:39.763036 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 11:08:39.766301 Total UI for P1: 0, mck2ui 16
6675 11:08:39.769413 best dqsien dly found for B0: ( 0, 14, 24)
6676 11:08:39.769873 Total UI for P1: 0, mck2ui 16
6677 11:08:39.776102 best dqsien dly found for B1: ( 0, 14, 24)
6678 11:08:39.779313 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6679 11:08:39.782498 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6680 11:08:39.782962
6681 11:08:39.785812 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6682 11:08:39.789639 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6683 11:08:39.792360 [Gating] SW calibration Done
6684 11:08:39.792837 ==
6685 11:08:39.795636 Dram Type= 6, Freq= 0, CH_1, rank 0
6686 11:08:39.799419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6687 11:08:39.800007 ==
6688 11:08:39.802631 RX Vref Scan: 0
6689 11:08:39.803089
6690 11:08:39.805717 RX Vref 0 -> 0, step: 1
6691 11:08:39.806343
6692 11:08:39.806764 RX Delay -410 -> 252, step: 16
6693 11:08:39.812229 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6694 11:08:39.815684 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6695 11:08:39.818987 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6696 11:08:39.822486 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6697 11:08:39.829201 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6698 11:08:39.832663 iDelay=230, Bit 5, Center -11 (-234 ~ 213) 448
6699 11:08:39.835786 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6700 11:08:39.838940 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6701 11:08:39.845849 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6702 11:08:39.848832 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6703 11:08:39.852474 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6704 11:08:39.855604 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6705 11:08:39.862687 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6706 11:08:39.865635 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6707 11:08:39.868804 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6708 11:08:39.875848 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6709 11:08:39.876417 ==
6710 11:08:39.879073 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 11:08:39.882474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 11:08:39.883049 ==
6713 11:08:39.883423 DQS Delay:
6714 11:08:39.885754 DQS0 = 27, DQS1 = 43
6715 11:08:39.886370 DQM Delay:
6716 11:08:39.889342 DQM0 = 7, DQM1 = 15
6717 11:08:39.889911 DQ Delay:
6718 11:08:39.892445 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6719 11:08:39.895579 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6720 11:08:39.898873 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6721 11:08:39.902291 DQ12 =32, DQ13 =16, DQ14 =16, DQ15 =24
6722 11:08:39.902887
6723 11:08:39.903262
6724 11:08:39.903607 ==
6725 11:08:39.905983 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 11:08:39.908833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 11:08:39.909408 ==
6728 11:08:39.909789
6729 11:08:39.910181
6730 11:08:39.911884 TX Vref Scan disable
6731 11:08:39.912351 == TX Byte 0 ==
6732 11:08:39.918797 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 11:08:39.922309 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 11:08:39.922882 == TX Byte 1 ==
6735 11:08:39.928722 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6736 11:08:39.932380 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6737 11:08:39.932945 ==
6738 11:08:39.935485 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 11:08:39.938891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 11:08:39.939459 ==
6741 11:08:39.939833
6742 11:08:39.940181
6743 11:08:39.941990 TX Vref Scan disable
6744 11:08:39.942493 == TX Byte 0 ==
6745 11:08:39.949216 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6746 11:08:39.952082 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6747 11:08:39.952650 == TX Byte 1 ==
6748 11:08:39.958583 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6749 11:08:39.962337 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6750 11:08:39.962916
6751 11:08:39.963294 [DATLAT]
6752 11:08:39.965441 Freq=400, CH1 RK0
6753 11:08:39.966040
6754 11:08:39.966422 DATLAT Default: 0xf
6755 11:08:39.968608 0, 0xFFFF, sum = 0
6756 11:08:39.969146 1, 0xFFFF, sum = 0
6757 11:08:39.971889 2, 0xFFFF, sum = 0
6758 11:08:39.972370 3, 0xFFFF, sum = 0
6759 11:08:39.975702 4, 0xFFFF, sum = 0
6760 11:08:39.976274 5, 0xFFFF, sum = 0
6761 11:08:39.978658 6, 0xFFFF, sum = 0
6762 11:08:39.982383 7, 0xFFFF, sum = 0
6763 11:08:39.982955 8, 0xFFFF, sum = 0
6764 11:08:39.985389 9, 0xFFFF, sum = 0
6765 11:08:39.985989 10, 0xFFFF, sum = 0
6766 11:08:39.988734 11, 0xFFFF, sum = 0
6767 11:08:39.989324 12, 0xFFFF, sum = 0
6768 11:08:39.992084 13, 0x0, sum = 1
6769 11:08:39.992558 14, 0x0, sum = 2
6770 11:08:39.995365 15, 0x0, sum = 3
6771 11:08:39.995834 16, 0x0, sum = 4
6772 11:08:39.996212 best_step = 14
6773 11:08:39.998543
6774 11:08:39.999105 ==
6775 11:08:40.001816 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 11:08:40.004979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 11:08:40.005445 ==
6778 11:08:40.005815 RX Vref Scan: 1
6779 11:08:40.006197
6780 11:08:40.008700 RX Vref 0 -> 0, step: 1
6781 11:08:40.009167
6782 11:08:40.012150 RX Delay -327 -> 252, step: 8
6783 11:08:40.012712
6784 11:08:40.015510 Set Vref, RX VrefLevel [Byte0]: 51
6785 11:08:40.018765 [Byte1]: 52
6786 11:08:40.022126
6787 11:08:40.022589 Final RX Vref Byte 0 = 51 to rank0
6788 11:08:40.025704 Final RX Vref Byte 1 = 52 to rank0
6789 11:08:40.028737 Final RX Vref Byte 0 = 51 to rank1
6790 11:08:40.032393 Final RX Vref Byte 1 = 52 to rank1==
6791 11:08:40.035605 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 11:08:40.042495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 11:08:40.042965 ==
6794 11:08:40.043334 DQS Delay:
6795 11:08:40.045323 DQS0 = 32, DQS1 = 40
6796 11:08:40.045787 DQM Delay:
6797 11:08:40.046208 DQM0 = 11, DQM1 = 12
6798 11:08:40.048536 DQ Delay:
6799 11:08:40.052473 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6800 11:08:40.053036 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6801 11:08:40.055378 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6802 11:08:40.059116 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6803 11:08:40.059703
6804 11:08:40.060079
6805 11:08:40.068683 [DQSOSCAuto] RK0, (LSB)MR18= 0x90cb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6806 11:08:40.072283 CH1 RK0: MR19=C0C, MR18=90CB
6807 11:08:40.078618 CH1_RK0: MR19=0xC0C, MR18=0x90CB, DQSOSC=384, MR23=63, INC=400, DEC=267
6808 11:08:40.079176 ==
6809 11:08:40.082089 Dram Type= 6, Freq= 0, CH_1, rank 1
6810 11:08:40.085698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 11:08:40.086302 ==
6812 11:08:40.088630 [Gating] SW mode calibration
6813 11:08:40.095293 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6814 11:08:40.101814 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6815 11:08:40.105033 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6816 11:08:40.108405 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6817 11:08:40.111928 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 11:08:40.118728 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6819 11:08:40.122230 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 11:08:40.125259 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 11:08:40.132068 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 11:08:40.134934 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6823 11:08:40.138615 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 11:08:40.141847 Total UI for P1: 0, mck2ui 16
6825 11:08:40.144883 best dqsien dly found for B0: ( 0, 14, 24)
6826 11:08:40.148739 Total UI for P1: 0, mck2ui 16
6827 11:08:40.152186 best dqsien dly found for B1: ( 0, 14, 24)
6828 11:08:40.155183 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6829 11:08:40.158404 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6830 11:08:40.161845
6831 11:08:40.165174 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6832 11:08:40.168295 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6833 11:08:40.171836 [Gating] SW calibration Done
6834 11:08:40.172404 ==
6835 11:08:40.175393 Dram Type= 6, Freq= 0, CH_1, rank 1
6836 11:08:40.178635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 11:08:40.179103 ==
6838 11:08:40.179474 RX Vref Scan: 0
6839 11:08:40.179816
6840 11:08:40.182105 RX Vref 0 -> 0, step: 1
6841 11:08:40.182661
6842 11:08:40.185351 RX Delay -410 -> 252, step: 16
6843 11:08:40.188605 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6844 11:08:40.195348 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6845 11:08:40.198377 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6846 11:08:40.202050 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6847 11:08:40.205211 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6848 11:08:40.212008 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6849 11:08:40.215267 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6850 11:08:40.218218 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6851 11:08:40.222103 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6852 11:08:40.225494 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6853 11:08:40.231477 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6854 11:08:40.235278 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6855 11:08:40.238427 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6856 11:08:40.245108 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6857 11:08:40.248244 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6858 11:08:40.251595 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6859 11:08:40.252160 ==
6860 11:08:40.254736 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 11:08:40.258273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 11:08:40.261334 ==
6863 11:08:40.261906 DQS Delay:
6864 11:08:40.262318 DQS0 = 35, DQS1 = 35
6865 11:08:40.265146 DQM Delay:
6866 11:08:40.265725 DQM0 = 18, DQM1 = 11
6867 11:08:40.268186 DQ Delay:
6868 11:08:40.271173 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6869 11:08:40.271635 DQ4 =16, DQ5 =24, DQ6 =32, DQ7 =16
6870 11:08:40.274944 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6871 11:08:40.278015 DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =24
6872 11:08:40.278485
6873 11:08:40.278876
6874 11:08:40.281832 ==
6875 11:08:40.284749 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 11:08:40.288327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 11:08:40.288895 ==
6878 11:08:40.289362
6879 11:08:40.289714
6880 11:08:40.291280 TX Vref Scan disable
6881 11:08:40.291918 == TX Byte 0 ==
6882 11:08:40.294525 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6883 11:08:40.301567 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6884 11:08:40.302168 == TX Byte 1 ==
6885 11:08:40.304527 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6886 11:08:40.308346 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6887 11:08:40.311560 ==
6888 11:08:40.314783 Dram Type= 6, Freq= 0, CH_1, rank 1
6889 11:08:40.318113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 11:08:40.318686 ==
6891 11:08:40.319062
6892 11:08:40.319405
6893 11:08:40.321182 TX Vref Scan disable
6894 11:08:40.321642 == TX Byte 0 ==
6895 11:08:40.324612 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6896 11:08:40.331110 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6897 11:08:40.331683 == TX Byte 1 ==
6898 11:08:40.334575 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6899 11:08:40.341445 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6900 11:08:40.342066
6901 11:08:40.342446 [DATLAT]
6902 11:08:40.342790 Freq=400, CH1 RK1
6903 11:08:40.343125
6904 11:08:40.344394 DATLAT Default: 0xe
6905 11:08:40.344853 0, 0xFFFF, sum = 0
6906 11:08:40.347994 1, 0xFFFF, sum = 0
6907 11:08:40.348567 2, 0xFFFF, sum = 0
6908 11:08:40.351232 3, 0xFFFF, sum = 0
6909 11:08:40.354328 4, 0xFFFF, sum = 0
6910 11:08:40.354900 5, 0xFFFF, sum = 0
6911 11:08:40.358195 6, 0xFFFF, sum = 0
6912 11:08:40.358763 7, 0xFFFF, sum = 0
6913 11:08:40.361114 8, 0xFFFF, sum = 0
6914 11:08:40.361682 9, 0xFFFF, sum = 0
6915 11:08:40.364501 10, 0xFFFF, sum = 0
6916 11:08:40.365077 11, 0xFFFF, sum = 0
6917 11:08:40.367583 12, 0xFFFF, sum = 0
6918 11:08:40.368229 13, 0x0, sum = 1
6919 11:08:40.370985 14, 0x0, sum = 2
6920 11:08:40.371454 15, 0x0, sum = 3
6921 11:08:40.374495 16, 0x0, sum = 4
6922 11:08:40.375204 best_step = 14
6923 11:08:40.375593
6924 11:08:40.375939 ==
6925 11:08:40.377591 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 11:08:40.380990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 11:08:40.381558 ==
6928 11:08:40.384046 RX Vref Scan: 0
6929 11:08:40.384508
6930 11:08:40.387774 RX Vref 0 -> 0, step: 1
6931 11:08:40.388367
6932 11:08:40.390820 RX Delay -311 -> 252, step: 8
6933 11:08:40.394258 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6934 11:08:40.400889 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6935 11:08:40.403781 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6936 11:08:40.407670 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6937 11:08:40.410868 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6938 11:08:40.417408 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6939 11:08:40.420653 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6940 11:08:40.424244 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6941 11:08:40.427564 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6942 11:08:40.434294 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6943 11:08:40.437337 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6944 11:08:40.440845 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6945 11:08:40.444270 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6946 11:08:40.450815 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6947 11:08:40.454225 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6948 11:08:40.457433 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6949 11:08:40.458115 ==
6950 11:08:40.460609 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 11:08:40.467015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 11:08:40.467585 ==
6953 11:08:40.467959 DQS Delay:
6954 11:08:40.470617 DQS0 = 32, DQS1 = 36
6955 11:08:40.471084 DQM Delay:
6956 11:08:40.471454 DQM0 = 11, DQM1 = 11
6957 11:08:40.474330 DQ Delay:
6958 11:08:40.477252 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6959 11:08:40.477810 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =8
6960 11:08:40.481031 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6961 11:08:40.483935 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6962 11:08:40.484499
6963 11:08:40.487495
6964 11:08:40.493773 [DQSOSCAuto] RK1, (LSB)MR18= 0xa54e, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 389 ps
6965 11:08:40.497090 CH1 RK1: MR19=C0C, MR18=A54E
6966 11:08:40.503887 CH1_RK1: MR19=0xC0C, MR18=0xA54E, DQSOSC=389, MR23=63, INC=390, DEC=260
6967 11:08:40.506994 [RxdqsGatingPostProcess] freq 400
6968 11:08:40.510504 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6969 11:08:40.513597 best DQS0 dly(2T, 0.5T) = (0, 10)
6970 11:08:40.517136 best DQS1 dly(2T, 0.5T) = (0, 10)
6971 11:08:40.520155 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6972 11:08:40.523832 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6973 11:08:40.527490 best DQS0 dly(2T, 0.5T) = (0, 10)
6974 11:08:40.530574 best DQS1 dly(2T, 0.5T) = (0, 10)
6975 11:08:40.533536 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6976 11:08:40.537414 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6977 11:08:40.540355 Pre-setting of DQS Precalculation
6978 11:08:40.543806 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6979 11:08:40.550425 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6980 11:08:40.560461 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6981 11:08:40.561030
6982 11:08:40.561408
6983 11:08:40.561754 [Calibration Summary] 800 Mbps
6984 11:08:40.563437 CH 0, Rank 0
6985 11:08:40.563961 SW Impedance : PASS
6986 11:08:40.566725 DUTY Scan : NO K
6987 11:08:40.569866 ZQ Calibration : PASS
6988 11:08:40.570521 Jitter Meter : NO K
6989 11:08:40.573569 CBT Training : PASS
6990 11:08:40.576913 Write leveling : PASS
6991 11:08:40.577474 RX DQS gating : PASS
6992 11:08:40.580269 RX DQ/DQS(RDDQC) : PASS
6993 11:08:40.583498 TX DQ/DQS : PASS
6994 11:08:40.584076 RX DATLAT : PASS
6995 11:08:40.586295 RX DQ/DQS(Engine): PASS
6996 11:08:40.589884 TX OE : NO K
6997 11:08:40.590529 All Pass.
6998 11:08:40.590917
6999 11:08:40.591265 CH 0, Rank 1
7000 11:08:40.592961 SW Impedance : PASS
7001 11:08:40.596557 DUTY Scan : NO K
7002 11:08:40.597023 ZQ Calibration : PASS
7003 11:08:40.599958 Jitter Meter : NO K
7004 11:08:40.603134 CBT Training : PASS
7005 11:08:40.603692 Write leveling : NO K
7006 11:08:40.606666 RX DQS gating : PASS
7007 11:08:40.609913 RX DQ/DQS(RDDQC) : PASS
7008 11:08:40.610507 TX DQ/DQS : PASS
7009 11:08:40.613763 RX DATLAT : PASS
7010 11:08:40.614359 RX DQ/DQS(Engine): PASS
7011 11:08:40.617005 TX OE : NO K
7012 11:08:40.617574 All Pass.
7013 11:08:40.617980
7014 11:08:40.619804 CH 1, Rank 0
7015 11:08:40.620270 SW Impedance : PASS
7016 11:08:40.623440 DUTY Scan : NO K
7017 11:08:40.626592 ZQ Calibration : PASS
7018 11:08:40.627154 Jitter Meter : NO K
7019 11:08:40.629929 CBT Training : PASS
7020 11:08:40.633052 Write leveling : PASS
7021 11:08:40.633561 RX DQS gating : PASS
7022 11:08:40.636184 RX DQ/DQS(RDDQC) : PASS
7023 11:08:40.639871 TX DQ/DQS : PASS
7024 11:08:40.640443 RX DATLAT : PASS
7025 11:08:40.643266 RX DQ/DQS(Engine): PASS
7026 11:08:40.646343 TX OE : NO K
7027 11:08:40.646811 All Pass.
7028 11:08:40.647181
7029 11:08:40.647521 CH 1, Rank 1
7030 11:08:40.649574 SW Impedance : PASS
7031 11:08:40.653484 DUTY Scan : NO K
7032 11:08:40.654095 ZQ Calibration : PASS
7033 11:08:40.656728 Jitter Meter : NO K
7034 11:08:40.659675 CBT Training : PASS
7035 11:08:40.660142 Write leveling : NO K
7036 11:08:40.662596 RX DQS gating : PASS
7037 11:08:40.666336 RX DQ/DQS(RDDQC) : PASS
7038 11:08:40.666800 TX DQ/DQS : PASS
7039 11:08:40.669512 RX DATLAT : PASS
7040 11:08:40.670009 RX DQ/DQS(Engine): PASS
7041 11:08:40.672923 TX OE : NO K
7042 11:08:40.673387 All Pass.
7043 11:08:40.673758
7044 11:08:40.676247 DramC Write-DBI off
7045 11:08:40.679508 PER_BANK_REFRESH: Hybrid Mode
7046 11:08:40.679972 TX_TRACKING: ON
7047 11:08:40.689444 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7048 11:08:40.692543 [FAST_K] Save calibration result to emmc
7049 11:08:40.696150 dramc_set_vcore_voltage set vcore to 725000
7050 11:08:40.699282 Read voltage for 1600, 0
7051 11:08:40.699701 Vio18 = 0
7052 11:08:40.702483 Vcore = 725000
7053 11:08:40.702902 Vdram = 0
7054 11:08:40.703239 Vddq = 0
7055 11:08:40.703554 Vmddr = 0
7056 11:08:40.709253 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7057 11:08:40.716140 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7058 11:08:40.716560 MEM_TYPE=3, freq_sel=13
7059 11:08:40.719446 sv_algorithm_assistance_LP4_3733
7060 11:08:40.722662 ============ PULL DRAM RESETB DOWN ============
7061 11:08:40.729473 ========== PULL DRAM RESETB DOWN end =========
7062 11:08:40.732354 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7063 11:08:40.736103 ===================================
7064 11:08:40.739363 LPDDR4 DRAM CONFIGURATION
7065 11:08:40.742465 ===================================
7066 11:08:40.742882 EX_ROW_EN[0] = 0x0
7067 11:08:40.746092 EX_ROW_EN[1] = 0x0
7068 11:08:40.746509 LP4Y_EN = 0x0
7069 11:08:40.748589 WORK_FSP = 0x1
7070 11:08:40.748671 WL = 0x5
7071 11:08:40.752329 RL = 0x5
7072 11:08:40.752410 BL = 0x2
7073 11:08:40.755375 RPST = 0x0
7074 11:08:40.755459 RD_PRE = 0x0
7075 11:08:40.758857 WR_PRE = 0x1
7076 11:08:40.761933 WR_PST = 0x1
7077 11:08:40.762058 DBI_WR = 0x0
7078 11:08:40.765236 DBI_RD = 0x0
7079 11:08:40.765343 OTF = 0x1
7080 11:08:40.768840 ===================================
7081 11:08:40.771860 ===================================
7082 11:08:40.771948 ANA top config
7083 11:08:40.775419 ===================================
7084 11:08:40.779001 DLL_ASYNC_EN = 0
7085 11:08:40.782055 ALL_SLAVE_EN = 0
7086 11:08:40.785521 NEW_RANK_MODE = 1
7087 11:08:40.789269 DLL_IDLE_MODE = 1
7088 11:08:40.789350 LP45_APHY_COMB_EN = 1
7089 11:08:40.792232 TX_ODT_DIS = 0
7090 11:08:40.795449 NEW_8X_MODE = 1
7091 11:08:40.798827 ===================================
7092 11:08:40.802135 ===================================
7093 11:08:40.805779 data_rate = 3200
7094 11:08:40.808906 CKR = 1
7095 11:08:40.809038 DQ_P2S_RATIO = 8
7096 11:08:40.812000 ===================================
7097 11:08:40.815670 CA_P2S_RATIO = 8
7098 11:08:40.818752 DQ_CA_OPEN = 0
7099 11:08:40.821920 DQ_SEMI_OPEN = 0
7100 11:08:40.825452 CA_SEMI_OPEN = 0
7101 11:08:40.828534 CA_FULL_RATE = 0
7102 11:08:40.828615 DQ_CKDIV4_EN = 0
7103 11:08:40.832359 CA_CKDIV4_EN = 0
7104 11:08:40.835211 CA_PREDIV_EN = 0
7105 11:08:40.838815 PH8_DLY = 12
7106 11:08:40.841934 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7107 11:08:40.845454 DQ_AAMCK_DIV = 4
7108 11:08:40.845630 CA_AAMCK_DIV = 4
7109 11:08:40.848789 CA_ADMCK_DIV = 4
7110 11:08:40.852256 DQ_TRACK_CA_EN = 0
7111 11:08:40.855538 CA_PICK = 1600
7112 11:08:40.859214 CA_MCKIO = 1600
7113 11:08:40.862184 MCKIO_SEMI = 0
7114 11:08:40.865568 PLL_FREQ = 3068
7115 11:08:40.865798 DQ_UI_PI_RATIO = 32
7116 11:08:40.868564 CA_UI_PI_RATIO = 0
7117 11:08:40.871780 ===================================
7118 11:08:40.875906 ===================================
7119 11:08:40.878801 memory_type:LPDDR4
7120 11:08:40.882383 GP_NUM : 10
7121 11:08:40.882771 SRAM_EN : 1
7122 11:08:40.885618 MD32_EN : 0
7123 11:08:40.889078 ===================================
7124 11:08:40.892555 [ANA_INIT] >>>>>>>>>>>>>>
7125 11:08:40.893113 <<<<<< [CONFIGURE PHASE]: ANA_TX
7126 11:08:40.895307 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7127 11:08:40.898762 ===================================
7128 11:08:40.902726 data_rate = 3200,PCW = 0X7600
7129 11:08:40.905797 ===================================
7130 11:08:40.909357 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7131 11:08:40.915209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7132 11:08:40.922250 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7133 11:08:40.925191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7134 11:08:40.928859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7135 11:08:40.932028 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7136 11:08:40.935209 [ANA_INIT] flow start
7137 11:08:40.935697 [ANA_INIT] PLL >>>>>>>>
7138 11:08:40.938516 [ANA_INIT] PLL <<<<<<<<
7139 11:08:40.942186 [ANA_INIT] MIDPI >>>>>>>>
7140 11:08:40.942751 [ANA_INIT] MIDPI <<<<<<<<
7141 11:08:40.945546 [ANA_INIT] DLL >>>>>>>>
7142 11:08:40.948563 [ANA_INIT] DLL <<<<<<<<
7143 11:08:40.949032 [ANA_INIT] flow end
7144 11:08:40.955064 ============ LP4 DIFF to SE enter ============
7145 11:08:40.958678 ============ LP4 DIFF to SE exit ============
7146 11:08:40.962179 [ANA_INIT] <<<<<<<<<<<<<
7147 11:08:40.965281 [Flow] Enable top DCM control >>>>>
7148 11:08:40.968839 [Flow] Enable top DCM control <<<<<
7149 11:08:40.969463 Enable DLL master slave shuffle
7150 11:08:40.975412 ==============================================================
7151 11:08:40.978778 Gating Mode config
7152 11:08:40.981712 ==============================================================
7153 11:08:40.985232 Config description:
7154 11:08:40.994817 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7155 11:08:41.001762 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7156 11:08:41.005039 SELPH_MODE 0: By rank 1: By Phase
7157 11:08:41.011565 ==============================================================
7158 11:08:41.014829 GAT_TRACK_EN = 1
7159 11:08:41.018173 RX_GATING_MODE = 2
7160 11:08:41.021651 RX_GATING_TRACK_MODE = 2
7161 11:08:41.024642 SELPH_MODE = 1
7162 11:08:41.025126 PICG_EARLY_EN = 1
7163 11:08:41.027910 VALID_LAT_VALUE = 1
7164 11:08:41.034492 ==============================================================
7165 11:08:41.037852 Enter into Gating configuration >>>>
7166 11:08:41.041342 Exit from Gating configuration <<<<
7167 11:08:41.044668 Enter into DVFS_PRE_config >>>>>
7168 11:08:41.054398 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7169 11:08:41.058051 Exit from DVFS_PRE_config <<<<<
7170 11:08:41.061658 Enter into PICG configuration >>>>
7171 11:08:41.064855 Exit from PICG configuration <<<<
7172 11:08:41.067961 [RX_INPUT] configuration >>>>>
7173 11:08:41.070953 [RX_INPUT] configuration <<<<<
7174 11:08:41.074626 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7175 11:08:41.081128 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7176 11:08:41.088046 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7177 11:08:41.094670 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7178 11:08:41.101319 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7179 11:08:41.107905 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7180 11:08:41.110913 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7181 11:08:41.114349 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7182 11:08:41.117634 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7183 11:08:41.120847 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7184 11:08:41.127683 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7185 11:08:41.131189 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7186 11:08:41.134366 ===================================
7187 11:08:41.137635 LPDDR4 DRAM CONFIGURATION
7188 11:08:41.140926 ===================================
7189 11:08:41.141520 EX_ROW_EN[0] = 0x0
7190 11:08:41.144207 EX_ROW_EN[1] = 0x0
7191 11:08:41.144672 LP4Y_EN = 0x0
7192 11:08:41.147331 WORK_FSP = 0x1
7193 11:08:41.147796 WL = 0x5
7194 11:08:41.150593 RL = 0x5
7195 11:08:41.151057 BL = 0x2
7196 11:08:41.154112 RPST = 0x0
7197 11:08:41.157558 RD_PRE = 0x0
7198 11:08:41.158061 WR_PRE = 0x1
7199 11:08:41.160726 WR_PST = 0x1
7200 11:08:41.161188 DBI_WR = 0x0
7201 11:08:41.164054 DBI_RD = 0x0
7202 11:08:41.164522 OTF = 0x1
7203 11:08:41.167335 ===================================
7204 11:08:41.171009 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7205 11:08:41.177496 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7206 11:08:41.180739 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7207 11:08:41.183951 ===================================
7208 11:08:41.187262 LPDDR4 DRAM CONFIGURATION
7209 11:08:41.190624 ===================================
7210 11:08:41.191093 EX_ROW_EN[0] = 0x10
7211 11:08:41.194046 EX_ROW_EN[1] = 0x0
7212 11:08:41.194513 LP4Y_EN = 0x0
7213 11:08:41.197523 WORK_FSP = 0x1
7214 11:08:41.198121 WL = 0x5
7215 11:08:41.200370 RL = 0x5
7216 11:08:41.200833 BL = 0x2
7217 11:08:41.204156 RPST = 0x0
7218 11:08:41.204715 RD_PRE = 0x0
7219 11:08:41.207474 WR_PRE = 0x1
7220 11:08:41.210857 WR_PST = 0x1
7221 11:08:41.211419 DBI_WR = 0x0
7222 11:08:41.213918 DBI_RD = 0x0
7223 11:08:41.214509 OTF = 0x1
7224 11:08:41.217257 ===================================
7225 11:08:41.223943 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7226 11:08:41.224509 ==
7227 11:08:41.227361 Dram Type= 6, Freq= 0, CH_0, rank 0
7228 11:08:41.230502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7229 11:08:41.231068 ==
7230 11:08:41.233724 [Duty_Offset_Calibration]
7231 11:08:41.234313 B0:2 B1:0 CA:1
7232 11:08:41.237124
7233 11:08:41.240324 [DutyScan_Calibration_Flow] k_type=0
7234 11:08:41.247486
7235 11:08:41.248070 ==CLK 0==
7236 11:08:41.251071 Final CLK duty delay cell = -4
7237 11:08:41.254489 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7238 11:08:41.257352 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7239 11:08:41.260775 [-4] AVG Duty = 4906%(X100)
7240 11:08:41.261333
7241 11:08:41.263907 CH0 CLK Duty spec in!! Max-Min= 187%
7242 11:08:41.267272 [DutyScan_Calibration_Flow] ====Done====
7243 11:08:41.267737
7244 11:08:41.270851 [DutyScan_Calibration_Flow] k_type=1
7245 11:08:41.286908
7246 11:08:41.287468 ==DQS 0 ==
7247 11:08:41.290848 Final DQS duty delay cell = 0
7248 11:08:41.293918 [0] MAX Duty = 5218%(X100), DQS PI = 26
7249 11:08:41.296903 [0] MIN Duty = 4969%(X100), DQS PI = 0
7250 11:08:41.297369 [0] AVG Duty = 5093%(X100)
7251 11:08:41.300561
7252 11:08:41.301026 ==DQS 1 ==
7253 11:08:41.304018 Final DQS duty delay cell = -4
7254 11:08:41.307274 [-4] MAX Duty = 5125%(X100), DQS PI = 28
7255 11:08:41.310573 [-4] MIN Duty = 4875%(X100), DQS PI = 2
7256 11:08:41.313831 [-4] AVG Duty = 5000%(X100)
7257 11:08:41.314431
7258 11:08:41.316880 CH0 DQS 0 Duty spec in!! Max-Min= 249%
7259 11:08:41.317343
7260 11:08:41.320370 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7261 11:08:41.323478 [DutyScan_Calibration_Flow] ====Done====
7262 11:08:41.323946
7263 11:08:41.326886 [DutyScan_Calibration_Flow] k_type=3
7264 11:08:41.344603
7265 11:08:41.345169 ==DQM 0 ==
7266 11:08:41.347846 Final DQM duty delay cell = 0
7267 11:08:41.350863 [0] MAX Duty = 5093%(X100), DQS PI = 26
7268 11:08:41.354117 [0] MIN Duty = 4813%(X100), DQS PI = 50
7269 11:08:41.357515 [0] AVG Duty = 4953%(X100)
7270 11:08:41.358122
7271 11:08:41.358508 ==DQM 1 ==
7272 11:08:41.361117 Final DQM duty delay cell = 0
7273 11:08:41.363942 [0] MAX Duty = 5249%(X100), DQS PI = 28
7274 11:08:41.367462 [0] MIN Duty = 5000%(X100), DQS PI = 20
7275 11:08:41.370988 [0] AVG Duty = 5124%(X100)
7276 11:08:41.371546
7277 11:08:41.374465 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7278 11:08:41.375033
7279 11:08:41.377550 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7280 11:08:41.381153 [DutyScan_Calibration_Flow] ====Done====
7281 11:08:41.381715
7282 11:08:41.384326 [DutyScan_Calibration_Flow] k_type=2
7283 11:08:41.402015
7284 11:08:41.402577 ==DQ 0 ==
7285 11:08:41.405004 Final DQ duty delay cell = 0
7286 11:08:41.408349 [0] MAX Duty = 5124%(X100), DQS PI = 34
7287 11:08:41.411720 [0] MIN Duty = 5000%(X100), DQS PI = 0
7288 11:08:41.412289 [0] AVG Duty = 5062%(X100)
7289 11:08:41.414878
7290 11:08:41.415441 ==DQ 1 ==
7291 11:08:41.418348 Final DQ duty delay cell = 0
7292 11:08:41.421533 [0] MAX Duty = 4969%(X100), DQS PI = 42
7293 11:08:41.424880 [0] MIN Duty = 4875%(X100), DQS PI = 0
7294 11:08:41.425335 [0] AVG Duty = 4922%(X100)
7295 11:08:41.425698
7296 11:08:41.428086 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7297 11:08:41.428539
7298 11:08:41.431451 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7299 11:08:41.438233 [DutyScan_Calibration_Flow] ====Done====
7300 11:08:41.438685 ==
7301 11:08:41.441535 Dram Type= 6, Freq= 0, CH_1, rank 0
7302 11:08:41.445097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7303 11:08:41.445644 ==
7304 11:08:41.448368 [Duty_Offset_Calibration]
7305 11:08:41.448919 B0:0 B1:-1 CA:2
7306 11:08:41.449282
7307 11:08:41.451499 [DutyScan_Calibration_Flow] k_type=0
7308 11:08:41.461723
7309 11:08:41.462472 ==CLK 0==
7310 11:08:41.465211 Final CLK duty delay cell = 0
7311 11:08:41.468675 [0] MAX Duty = 5156%(X100), DQS PI = 10
7312 11:08:41.471679 [0] MIN Duty = 4906%(X100), DQS PI = 46
7313 11:08:41.472127 [0] AVG Duty = 5031%(X100)
7314 11:08:41.475255
7315 11:08:41.478469 CH1 CLK Duty spec in!! Max-Min= 250%
7316 11:08:41.481795 [DutyScan_Calibration_Flow] ====Done====
7317 11:08:41.482263
7318 11:08:41.485224 [DutyScan_Calibration_Flow] k_type=1
7319 11:08:41.501472
7320 11:08:41.502104 ==DQS 0 ==
7321 11:08:41.505034 Final DQS duty delay cell = 0
7322 11:08:41.508447 [0] MAX Duty = 5093%(X100), DQS PI = 24
7323 11:08:41.511759 [0] MIN Duty = 4969%(X100), DQS PI = 16
7324 11:08:41.514932 [0] AVG Duty = 5031%(X100)
7325 11:08:41.515478
7326 11:08:41.515835 ==DQS 1 ==
7327 11:08:41.518024 Final DQS duty delay cell = 0
7328 11:08:41.521549 [0] MAX Duty = 5187%(X100), DQS PI = 0
7329 11:08:41.524984 [0] MIN Duty = 4844%(X100), DQS PI = 34
7330 11:08:41.528336 [0] AVG Duty = 5015%(X100)
7331 11:08:41.528888
7332 11:08:41.531364 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7333 11:08:41.531912
7334 11:08:41.534911 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7335 11:08:41.538332 [DutyScan_Calibration_Flow] ====Done====
7336 11:08:41.538891
7337 11:08:41.541287 [DutyScan_Calibration_Flow] k_type=3
7338 11:08:41.559024
7339 11:08:41.559564 ==DQM 0 ==
7340 11:08:41.562620 Final DQM duty delay cell = 4
7341 11:08:41.566178 [4] MAX Duty = 5125%(X100), DQS PI = 8
7342 11:08:41.569161 [4] MIN Duty = 5000%(X100), DQS PI = 30
7343 11:08:41.569721 [4] AVG Duty = 5062%(X100)
7344 11:08:41.572295
7345 11:08:41.572800 ==DQM 1 ==
7346 11:08:41.575814 Final DQM duty delay cell = 0
7347 11:08:41.579131 [0] MAX Duty = 5281%(X100), DQS PI = 60
7348 11:08:41.582592 [0] MIN Duty = 4876%(X100), DQS PI = 34
7349 11:08:41.585882 [0] AVG Duty = 5078%(X100)
7350 11:08:41.586485
7351 11:08:41.589509 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7352 11:08:41.590112
7353 11:08:41.592520 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7354 11:08:41.595373 [DutyScan_Calibration_Flow] ====Done====
7355 11:08:41.595832
7356 11:08:41.598666 [DutyScan_Calibration_Flow] k_type=2
7357 11:08:41.616307
7358 11:08:41.616863 ==DQ 0 ==
7359 11:08:41.619393 Final DQ duty delay cell = 0
7360 11:08:41.622693 [0] MAX Duty = 5062%(X100), DQS PI = 18
7361 11:08:41.626033 [0] MIN Duty = 4969%(X100), DQS PI = 48
7362 11:08:41.626597 [0] AVG Duty = 5015%(X100)
7363 11:08:41.629252
7364 11:08:41.629704 ==DQ 1 ==
7365 11:08:41.632897 Final DQ duty delay cell = 0
7366 11:08:41.635533 [0] MAX Duty = 5062%(X100), DQS PI = 2
7367 11:08:41.639437 [0] MIN Duty = 4813%(X100), DQS PI = 34
7368 11:08:41.639994 [0] AVG Duty = 4937%(X100)
7369 11:08:41.640361
7370 11:08:41.642194 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7371 11:08:41.645697
7372 11:08:41.649359 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7373 11:08:41.652634 [DutyScan_Calibration_Flow] ====Done====
7374 11:08:41.655869 nWR fixed to 30
7375 11:08:41.656436 [ModeRegInit_LP4] CH0 RK0
7376 11:08:41.658868 [ModeRegInit_LP4] CH0 RK1
7377 11:08:41.662207 [ModeRegInit_LP4] CH1 RK0
7378 11:08:41.665609 [ModeRegInit_LP4] CH1 RK1
7379 11:08:41.666198 match AC timing 5
7380 11:08:41.669308 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7381 11:08:41.675864 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7382 11:08:41.679121 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7383 11:08:41.685679 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7384 11:08:41.688912 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7385 11:08:41.689501 [MiockJmeterHQA]
7386 11:08:41.689880
7387 11:08:41.692099 [DramcMiockJmeter] u1RxGatingPI = 0
7388 11:08:41.695610 0 : 4253, 4026
7389 11:08:41.696175 4 : 4257, 4032
7390 11:08:41.696555 8 : 4252, 4027
7391 11:08:41.698721 12 : 4258, 4029
7392 11:08:41.699190 16 : 4257, 4030
7393 11:08:41.702357 20 : 4368, 4139
7394 11:08:41.702821 24 : 4368, 4140
7395 11:08:41.705670 28 : 4371, 4142
7396 11:08:41.706274 32 : 4252, 4027
7397 11:08:41.709050 36 : 4262, 4031
7398 11:08:41.709624 40 : 4260, 4029
7399 11:08:41.710047 44 : 4368, 4140
7400 11:08:41.712052 48 : 4258, 4029
7401 11:08:41.712517 52 : 4255, 4027
7402 11:08:41.715994 56 : 4252, 4026
7403 11:08:41.716671 60 : 4252, 4027
7404 11:08:41.719220 64 : 4363, 4138
7405 11:08:41.719789 68 : 4250, 4027
7406 11:08:41.722630 72 : 4360, 4138
7407 11:08:41.723199 76 : 4253, 4029
7408 11:08:41.723583 80 : 4361, 4137
7409 11:08:41.725617 84 : 4250, 4027
7410 11:08:41.726112 88 : 4250, 3466
7411 11:08:41.729025 92 : 4255, 0
7412 11:08:41.729591 96 : 4363, 0
7413 11:08:41.729994 100 : 4253, 0
7414 11:08:41.732306 104 : 4361, 0
7415 11:08:41.732873 108 : 4360, 0
7416 11:08:41.735582 112 : 4250, 0
7417 11:08:41.736156 116 : 4250, 0
7418 11:08:41.736536 120 : 4250, 0
7419 11:08:41.738635 124 : 4363, 0
7420 11:08:41.739138 128 : 4255, 0
7421 11:08:41.741989 132 : 4252, 0
7422 11:08:41.742461 136 : 4361, 0
7423 11:08:41.742831 140 : 4250, 0
7424 11:08:41.745717 144 : 4249, 0
7425 11:08:41.746329 148 : 4250, 0
7426 11:08:41.746710 152 : 4253, 0
7427 11:08:41.749052 156 : 4361, 0
7428 11:08:41.749627 160 : 4361, 0
7429 11:08:41.752157 164 : 4250, 0
7430 11:08:41.752724 168 : 4255, 0
7431 11:08:41.753100 172 : 4360, 0
7432 11:08:41.755504 176 : 4250, 0
7433 11:08:41.756085 180 : 4255, 0
7434 11:08:41.759155 184 : 4250, 0
7435 11:08:41.759623 188 : 4250, 0
7436 11:08:41.759996 192 : 4253, 0
7437 11:08:41.762273 196 : 4250, 0
7438 11:08:41.762843 200 : 4250, 9
7439 11:08:41.765308 204 : 4253, 2522
7440 11:08:41.765777 208 : 4250, 4027
7441 11:08:41.768552 212 : 4252, 4027
7442 11:08:41.769121 216 : 4361, 4137
7443 11:08:41.769495 220 : 4250, 4027
7444 11:08:41.771794 224 : 4361, 4137
7445 11:08:41.772281 228 : 4360, 4138
7446 11:08:41.775191 232 : 4363, 4138
7447 11:08:41.775657 236 : 4250, 4027
7448 11:08:41.778694 240 : 4363, 4140
7449 11:08:41.779262 244 : 4253, 4029
7450 11:08:41.782038 248 : 4250, 4027
7451 11:08:41.782665 252 : 4253, 4029
7452 11:08:41.785261 256 : 4252, 4029
7453 11:08:41.785831 260 : 4253, 4029
7454 11:08:41.788627 264 : 4363, 4140
7455 11:08:41.789191 268 : 4254, 4029
7456 11:08:41.792381 272 : 4250, 4027
7457 11:08:41.792973 276 : 4250, 4027
7458 11:08:41.793349 280 : 4363, 4140
7459 11:08:41.795256 284 : 4363, 4138
7460 11:08:41.795722 288 : 4250, 4027
7461 11:08:41.798609 292 : 4363, 4140
7462 11:08:41.799082 296 : 4253, 4029
7463 11:08:41.801796 300 : 4250, 4027
7464 11:08:41.802292 304 : 4252, 4029
7465 11:08:41.805319 308 : 4252, 4029
7466 11:08:41.805890 312 : 4253, 3920
7467 11:08:41.808834 316 : 4363, 1974
7468 11:08:41.809416
7469 11:08:41.809783 MIOCK jitter meter ch=0
7470 11:08:41.810188
7471 11:08:41.811928 1T = (316-92) = 224 dly cells
7472 11:08:41.818564 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7473 11:08:41.819124 ==
7474 11:08:41.822038 Dram Type= 6, Freq= 0, CH_0, rank 0
7475 11:08:41.825107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7476 11:08:41.825747 ==
7477 11:08:41.831571 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7478 11:08:41.835070 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7479 11:08:41.841334 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7480 11:08:41.844786 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7481 11:08:41.855186 [CA 0] Center 43 (13~73) winsize 61
7482 11:08:41.858165 [CA 1] Center 43 (13~73) winsize 61
7483 11:08:41.861717 [CA 2] Center 38 (8~68) winsize 61
7484 11:08:41.865014 [CA 3] Center 37 (8~67) winsize 60
7485 11:08:41.868340 [CA 4] Center 36 (6~66) winsize 61
7486 11:08:41.871284 [CA 5] Center 35 (5~65) winsize 61
7487 11:08:41.871749
7488 11:08:41.874679 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7489 11:08:41.875142
7490 11:08:41.878118 [CATrainingPosCal] consider 1 rank data
7491 11:08:41.881367 u2DelayCellTimex100 = 290/100 ps
7492 11:08:41.884687 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7493 11:08:41.891115 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7494 11:08:41.894748 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7495 11:08:41.898119 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7496 11:08:41.901019 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7497 11:08:41.904469 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7498 11:08:41.905038
7499 11:08:41.907876 CA PerBit enable=1, Macro0, CA PI delay=35
7500 11:08:41.908441
7501 11:08:41.911146 [CBTSetCACLKResult] CA Dly = 35
7502 11:08:41.914091 CS Dly: 8 (0~39)
7503 11:08:41.917791 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7504 11:08:41.921184 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7505 11:08:41.921752 ==
7506 11:08:41.924033 Dram Type= 6, Freq= 0, CH_0, rank 1
7507 11:08:41.931164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7508 11:08:41.931737 ==
7509 11:08:41.934259 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7510 11:08:41.937583 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7511 11:08:41.944233 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7512 11:08:41.950800 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7513 11:08:41.958502 [CA 0] Center 43 (13~73) winsize 61
7514 11:08:41.961750 [CA 1] Center 43 (13~73) winsize 61
7515 11:08:41.965178 [CA 2] Center 38 (8~68) winsize 61
7516 11:08:41.968197 [CA 3] Center 38 (8~68) winsize 61
7517 11:08:41.971317 [CA 4] Center 36 (6~66) winsize 61
7518 11:08:41.974628 [CA 5] Center 36 (6~66) winsize 61
7519 11:08:41.975091
7520 11:08:41.977933 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7521 11:08:41.978489
7522 11:08:41.981460 [CATrainingPosCal] consider 2 rank data
7523 11:08:41.984786 u2DelayCellTimex100 = 290/100 ps
7524 11:08:41.991164 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7525 11:08:41.994475 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7526 11:08:41.997608 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7527 11:08:42.001117 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7528 11:08:42.004399 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7529 11:08:42.007519 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7530 11:08:42.008083
7531 11:08:42.010701 CA PerBit enable=1, Macro0, CA PI delay=35
7532 11:08:42.011261
7533 11:08:42.014101 [CBTSetCACLKResult] CA Dly = 35
7534 11:08:42.017333 CS Dly: 10 (0~43)
7535 11:08:42.020818 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7536 11:08:42.024153 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7537 11:08:42.024690
7538 11:08:42.027751 ----->DramcWriteLeveling(PI) begin...
7539 11:08:42.028371 ==
7540 11:08:42.030693 Dram Type= 6, Freq= 0, CH_0, rank 0
7541 11:08:42.037409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7542 11:08:42.038014 ==
7543 11:08:42.040543 Write leveling (Byte 0): 36 => 36
7544 11:08:42.043945 Write leveling (Byte 1): 30 => 30
7545 11:08:42.047260 DramcWriteLeveling(PI) end<-----
7546 11:08:42.047826
7547 11:08:42.048193 ==
7548 11:08:42.050323 Dram Type= 6, Freq= 0, CH_0, rank 0
7549 11:08:42.053895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 11:08:42.054507 ==
7551 11:08:42.057386 [Gating] SW mode calibration
7552 11:08:42.064165 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7553 11:08:42.067268 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7554 11:08:42.073669 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 11:08:42.076894 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 11:08:42.080168 1 4 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7557 11:08:42.086912 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7558 11:08:42.090163 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7559 11:08:42.093596 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7560 11:08:42.100419 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 11:08:42.103267 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7562 11:08:42.106777 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7563 11:08:42.113145 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7564 11:08:42.116474 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
7565 11:08:42.119484 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7566 11:08:42.126602 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7567 11:08:42.129857 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
7568 11:08:42.133322 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 11:08:42.139895 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 11:08:42.142838 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 11:08:42.146513 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7572 11:08:42.153218 1 6 8 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
7573 11:08:42.156477 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7574 11:08:42.159477 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7575 11:08:42.166071 1 6 20 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7576 11:08:42.169464 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 11:08:42.172499 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 11:08:42.179538 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 11:08:42.182809 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7580 11:08:42.186151 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 11:08:42.192693 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7582 11:08:42.196021 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7583 11:08:42.199180 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7584 11:08:42.206014 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7585 11:08:42.209332 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 11:08:42.212731 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 11:08:42.219306 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 11:08:42.222480 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 11:08:42.225865 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 11:08:42.232670 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 11:08:42.236083 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 11:08:42.239390 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 11:08:42.245721 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 11:08:42.249252 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 11:08:42.252547 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 11:08:42.258883 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7597 11:08:42.262706 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7598 11:08:42.265528 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7599 11:08:42.269192 Total UI for P1: 0, mck2ui 16
7600 11:08:42.272274 best dqsien dly found for B0: ( 1, 9, 10)
7601 11:08:42.275801 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7602 11:08:42.282631 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7603 11:08:42.286099 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 11:08:42.289518 Total UI for P1: 0, mck2ui 16
7605 11:08:42.292404 best dqsien dly found for B1: ( 1, 9, 22)
7606 11:08:42.295852 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7607 11:08:42.299052 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7608 11:08:42.299622
7609 11:08:42.302413 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7610 11:08:42.309051 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7611 11:08:42.309619 [Gating] SW calibration Done
7612 11:08:42.310038 ==
7613 11:08:42.312294 Dram Type= 6, Freq= 0, CH_0, rank 0
7614 11:08:42.319026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7615 11:08:42.319594 ==
7616 11:08:42.319962 RX Vref Scan: 0
7617 11:08:42.320306
7618 11:08:42.322424 RX Vref 0 -> 0, step: 1
7619 11:08:42.322887
7620 11:08:42.325386 RX Delay 0 -> 252, step: 8
7621 11:08:42.329089 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7622 11:08:42.332113 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7623 11:08:42.335498 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7624 11:08:42.339040 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7625 11:08:42.345510 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7626 11:08:42.348581 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7627 11:08:42.352195 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7628 11:08:42.355224 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7629 11:08:42.358461 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7630 11:08:42.365813 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7631 11:08:42.368918 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7632 11:08:42.372001 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7633 11:08:42.375404 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7634 11:08:42.378800 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7635 11:08:42.385499 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7636 11:08:42.388784 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7637 11:08:42.389351 ==
7638 11:08:42.391845 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 11:08:42.395067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 11:08:42.395536 ==
7641 11:08:42.398415 DQS Delay:
7642 11:08:42.399012 DQS0 = 0, DQS1 = 0
7643 11:08:42.399394 DQM Delay:
7644 11:08:42.401874 DQM0 = 138, DQM1 = 127
7645 11:08:42.402473 DQ Delay:
7646 11:08:42.405259 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7647 11:08:42.408491 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7648 11:08:42.411948 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7649 11:08:42.418539 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7650 11:08:42.419111
7651 11:08:42.419486
7652 11:08:42.419828 ==
7653 11:08:42.421722 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 11:08:42.425215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 11:08:42.425689 ==
7656 11:08:42.426100
7657 11:08:42.426450
7658 11:08:42.428279 TX Vref Scan disable
7659 11:08:42.428743 == TX Byte 0 ==
7660 11:08:42.435238 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7661 11:08:42.438274 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7662 11:08:42.438847 == TX Byte 1 ==
7663 11:08:42.445213 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7664 11:08:42.448790 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7665 11:08:42.449364 ==
7666 11:08:42.451820 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 11:08:42.455081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 11:08:42.455576 ==
7669 11:08:42.469552
7670 11:08:42.472575 TX Vref early break, caculate TX vref
7671 11:08:42.475626 TX Vref=16, minBit 7, minWin=22, winSum=377
7672 11:08:42.479175 TX Vref=18, minBit 8, minWin=23, winSum=384
7673 11:08:42.482545 TX Vref=20, minBit 12, minWin=23, winSum=398
7674 11:08:42.485838 TX Vref=22, minBit 7, minWin=24, winSum=410
7675 11:08:42.489311 TX Vref=24, minBit 2, minWin=25, winSum=417
7676 11:08:42.495972 TX Vref=26, minBit 2, minWin=25, winSum=424
7677 11:08:42.498905 TX Vref=28, minBit 1, minWin=26, winSum=430
7678 11:08:42.502488 TX Vref=30, minBit 0, minWin=25, winSum=422
7679 11:08:42.505725 TX Vref=32, minBit 0, minWin=25, winSum=413
7680 11:08:42.509335 TX Vref=34, minBit 0, minWin=25, winSum=406
7681 11:08:42.515997 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 28
7682 11:08:42.516563
7683 11:08:42.519146 Final TX Range 0 Vref 28
7684 11:08:42.519614
7685 11:08:42.519989 ==
7686 11:08:42.522290 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 11:08:42.526016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 11:08:42.526585 ==
7689 11:08:42.526961
7690 11:08:42.527308
7691 11:08:42.529254 TX Vref Scan disable
7692 11:08:42.535620 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7693 11:08:42.536181 == TX Byte 0 ==
7694 11:08:42.538725 u2DelayCellOfst[0]=13 cells (4 PI)
7695 11:08:42.542439 u2DelayCellOfst[1]=16 cells (5 PI)
7696 11:08:42.545607 u2DelayCellOfst[2]=10 cells (3 PI)
7697 11:08:42.548592 u2DelayCellOfst[3]=10 cells (3 PI)
7698 11:08:42.551970 u2DelayCellOfst[4]=6 cells (2 PI)
7699 11:08:42.555513 u2DelayCellOfst[5]=0 cells (0 PI)
7700 11:08:42.558625 u2DelayCellOfst[6]=16 cells (5 PI)
7701 11:08:42.562153 u2DelayCellOfst[7]=13 cells (4 PI)
7702 11:08:42.565265 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7703 11:08:42.568562 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7704 11:08:42.571773 == TX Byte 1 ==
7705 11:08:42.575059 u2DelayCellOfst[8]=0 cells (0 PI)
7706 11:08:42.575502 u2DelayCellOfst[9]=0 cells (0 PI)
7707 11:08:42.578396 u2DelayCellOfst[10]=6 cells (2 PI)
7708 11:08:42.581607 u2DelayCellOfst[11]=3 cells (1 PI)
7709 11:08:42.585064 u2DelayCellOfst[12]=13 cells (4 PI)
7710 11:08:42.588249 u2DelayCellOfst[13]=13 cells (4 PI)
7711 11:08:42.591887 u2DelayCellOfst[14]=13 cells (4 PI)
7712 11:08:42.595146 u2DelayCellOfst[15]=10 cells (3 PI)
7713 11:08:42.597908 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7714 11:08:42.604895 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7715 11:08:42.605365 DramC Write-DBI on
7716 11:08:42.605734 ==
7717 11:08:42.608280 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 11:08:42.614935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 11:08:42.615096 ==
7720 11:08:42.615170
7721 11:08:42.615236
7722 11:08:42.615298 TX Vref Scan disable
7723 11:08:42.618606 == TX Byte 0 ==
7724 11:08:42.621680 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7725 11:08:42.625029 == TX Byte 1 ==
7726 11:08:42.628247 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7727 11:08:42.631659 DramC Write-DBI off
7728 11:08:42.631740
7729 11:08:42.631804 [DATLAT]
7730 11:08:42.631863 Freq=1600, CH0 RK0
7731 11:08:42.631921
7732 11:08:42.634977 DATLAT Default: 0xf
7733 11:08:42.635072 0, 0xFFFF, sum = 0
7734 11:08:42.638326 1, 0xFFFF, sum = 0
7735 11:08:42.641571 2, 0xFFFF, sum = 0
7736 11:08:42.641652 3, 0xFFFF, sum = 0
7737 11:08:42.644849 4, 0xFFFF, sum = 0
7738 11:08:42.644957 5, 0xFFFF, sum = 0
7739 11:08:42.648178 6, 0xFFFF, sum = 0
7740 11:08:42.648262 7, 0xFFFF, sum = 0
7741 11:08:42.651362 8, 0xFFFF, sum = 0
7742 11:08:42.651445 9, 0xFFFF, sum = 0
7743 11:08:42.654843 10, 0xFFFF, sum = 0
7744 11:08:42.654927 11, 0xFFFF, sum = 0
7745 11:08:42.658174 12, 0xFFFF, sum = 0
7746 11:08:42.658258 13, 0xFFFF, sum = 0
7747 11:08:42.661154 14, 0x0, sum = 1
7748 11:08:42.661238 15, 0x0, sum = 2
7749 11:08:42.664715 16, 0x0, sum = 3
7750 11:08:42.664799 17, 0x0, sum = 4
7751 11:08:42.668072 best_step = 15
7752 11:08:42.668154
7753 11:08:42.668220 ==
7754 11:08:42.671267 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 11:08:42.674397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 11:08:42.674487 ==
7757 11:08:42.678264 RX Vref Scan: 1
7758 11:08:42.678691
7759 11:08:42.679027 Set Vref Range= 24 -> 127
7760 11:08:42.679339
7761 11:08:42.681818 RX Vref 24 -> 127, step: 1
7762 11:08:42.682294
7763 11:08:42.684866 RX Delay 19 -> 252, step: 4
7764 11:08:42.685288
7765 11:08:42.687994 Set Vref, RX VrefLevel [Byte0]: 24
7766 11:08:42.691412 [Byte1]: 24
7767 11:08:42.691835
7768 11:08:42.695143 Set Vref, RX VrefLevel [Byte0]: 25
7769 11:08:42.698365 [Byte1]: 25
7770 11:08:42.698789
7771 11:08:42.701516 Set Vref, RX VrefLevel [Byte0]: 26
7772 11:08:42.704804 [Byte1]: 26
7773 11:08:42.709045
7774 11:08:42.709467 Set Vref, RX VrefLevel [Byte0]: 27
7775 11:08:42.712158 [Byte1]: 27
7776 11:08:42.716395
7777 11:08:42.716816 Set Vref, RX VrefLevel [Byte0]: 28
7778 11:08:42.719589 [Byte1]: 28
7779 11:08:42.724123
7780 11:08:42.724569 Set Vref, RX VrefLevel [Byte0]: 29
7781 11:08:42.727363 [Byte1]: 29
7782 11:08:42.732158
7783 11:08:42.732719 Set Vref, RX VrefLevel [Byte0]: 30
7784 11:08:42.735305 [Byte1]: 30
7785 11:08:42.739356
7786 11:08:42.739927 Set Vref, RX VrefLevel [Byte0]: 31
7787 11:08:42.742446 [Byte1]: 31
7788 11:08:42.746618
7789 11:08:42.747079 Set Vref, RX VrefLevel [Byte0]: 32
7790 11:08:42.750115 [Byte1]: 32
7791 11:08:42.754168
7792 11:08:42.754637 Set Vref, RX VrefLevel [Byte0]: 33
7793 11:08:42.757787 [Byte1]: 33
7794 11:08:42.762072
7795 11:08:42.762634 Set Vref, RX VrefLevel [Byte0]: 34
7796 11:08:42.765632 [Byte1]: 34
7797 11:08:42.769714
7798 11:08:42.770250 Set Vref, RX VrefLevel [Byte0]: 35
7799 11:08:42.772711 [Byte1]: 35
7800 11:08:42.777091
7801 11:08:42.777559 Set Vref, RX VrefLevel [Byte0]: 36
7802 11:08:42.780254 [Byte1]: 36
7803 11:08:42.785040
7804 11:08:42.785617 Set Vref, RX VrefLevel [Byte0]: 37
7805 11:08:42.787847 [Byte1]: 37
7806 11:08:42.792227
7807 11:08:42.792787 Set Vref, RX VrefLevel [Byte0]: 38
7808 11:08:42.795629 [Byte1]: 38
7809 11:08:42.799724
7810 11:08:42.800291 Set Vref, RX VrefLevel [Byte0]: 39
7811 11:08:42.803306 [Byte1]: 39
7812 11:08:42.807529
7813 11:08:42.808090 Set Vref, RX VrefLevel [Byte0]: 40
7814 11:08:42.810589 [Byte1]: 40
7815 11:08:42.815080
7816 11:08:42.815640 Set Vref, RX VrefLevel [Byte0]: 41
7817 11:08:42.818396 [Byte1]: 41
7818 11:08:42.822703
7819 11:08:42.823267 Set Vref, RX VrefLevel [Byte0]: 42
7820 11:08:42.825642 [Byte1]: 42
7821 11:08:42.830600
7822 11:08:42.831164 Set Vref, RX VrefLevel [Byte0]: 43
7823 11:08:42.833517 [Byte1]: 43
7824 11:08:42.837769
7825 11:08:42.838375 Set Vref, RX VrefLevel [Byte0]: 44
7826 11:08:42.840986 [Byte1]: 44
7827 11:08:42.845480
7828 11:08:42.846023 Set Vref, RX VrefLevel [Byte0]: 45
7829 11:08:42.848568 [Byte1]: 45
7830 11:08:42.853172
7831 11:08:42.853755 Set Vref, RX VrefLevel [Byte0]: 46
7832 11:08:42.855965 [Byte1]: 46
7833 11:08:42.860405
7834 11:08:42.860866 Set Vref, RX VrefLevel [Byte0]: 47
7835 11:08:42.863641 [Byte1]: 47
7836 11:08:42.867945
7837 11:08:42.868408 Set Vref, RX VrefLevel [Byte0]: 48
7838 11:08:42.871085 [Byte1]: 48
7839 11:08:42.875374
7840 11:08:42.875838 Set Vref, RX VrefLevel [Byte0]: 49
7841 11:08:42.878964 [Byte1]: 49
7842 11:08:42.883359
7843 11:08:42.883875 Set Vref, RX VrefLevel [Byte0]: 50
7844 11:08:42.886426 [Byte1]: 50
7845 11:08:42.890488
7846 11:08:42.890963 Set Vref, RX VrefLevel [Byte0]: 51
7847 11:08:42.894630 [Byte1]: 51
7848 11:08:42.898101
7849 11:08:42.898563 Set Vref, RX VrefLevel [Byte0]: 52
7850 11:08:42.901869 [Byte1]: 52
7851 11:08:42.905807
7852 11:08:42.906304 Set Vref, RX VrefLevel [Byte0]: 53
7853 11:08:42.909188 [Byte1]: 53
7854 11:08:42.913423
7855 11:08:42.914037 Set Vref, RX VrefLevel [Byte0]: 54
7856 11:08:42.916526 [Byte1]: 54
7857 11:08:42.921254
7858 11:08:42.921831 Set Vref, RX VrefLevel [Byte0]: 55
7859 11:08:42.924457 [Byte1]: 55
7860 11:08:42.928715
7861 11:08:42.929290 Set Vref, RX VrefLevel [Byte0]: 56
7862 11:08:42.932176 [Byte1]: 56
7863 11:08:42.936334
7864 11:08:42.936902 Set Vref, RX VrefLevel [Byte0]: 57
7865 11:08:42.939265 [Byte1]: 57
7866 11:08:42.943699
7867 11:08:42.944261 Set Vref, RX VrefLevel [Byte0]: 58
7868 11:08:42.946819 [Byte1]: 58
7869 11:08:42.951490
7870 11:08:42.952070 Set Vref, RX VrefLevel [Byte0]: 59
7871 11:08:42.954526 [Byte1]: 59
7872 11:08:42.959041
7873 11:08:42.959604 Set Vref, RX VrefLevel [Byte0]: 60
7874 11:08:42.962123 [Byte1]: 60
7875 11:08:42.966697
7876 11:08:42.967284 Set Vref, RX VrefLevel [Byte0]: 61
7877 11:08:42.969846 [Byte1]: 61
7878 11:08:42.974092
7879 11:08:42.974655 Set Vref, RX VrefLevel [Byte0]: 62
7880 11:08:42.977403 [Byte1]: 62
7881 11:08:42.981451
7882 11:08:42.982072 Set Vref, RX VrefLevel [Byte0]: 63
7883 11:08:42.984933 [Byte1]: 63
7884 11:08:42.989026
7885 11:08:42.989491 Set Vref, RX VrefLevel [Byte0]: 64
7886 11:08:42.992732 [Byte1]: 64
7887 11:08:42.996709
7888 11:08:42.997177 Set Vref, RX VrefLevel [Byte0]: 65
7889 11:08:42.999971 [Byte1]: 65
7890 11:08:43.004172
7891 11:08:43.004637 Set Vref, RX VrefLevel [Byte0]: 66
7892 11:08:43.007599 [Byte1]: 66
7893 11:08:43.011849
7894 11:08:43.012412 Set Vref, RX VrefLevel [Byte0]: 67
7895 11:08:43.015278 [Byte1]: 67
7896 11:08:43.019646
7897 11:08:43.020201 Set Vref, RX VrefLevel [Byte0]: 68
7898 11:08:43.022830 [Byte1]: 68
7899 11:08:43.027458
7900 11:08:43.028022 Set Vref, RX VrefLevel [Byte0]: 69
7901 11:08:43.030203 [Byte1]: 69
7902 11:08:43.034873
7903 11:08:43.035425 Set Vref, RX VrefLevel [Byte0]: 70
7904 11:08:43.038356 [Byte1]: 70
7905 11:08:43.042548
7906 11:08:43.043107 Set Vref, RX VrefLevel [Byte0]: 71
7907 11:08:43.045179 [Byte1]: 71
7908 11:08:43.049855
7909 11:08:43.050357 Set Vref, RX VrefLevel [Byte0]: 72
7910 11:08:43.053065 [Byte1]: 72
7911 11:08:43.057505
7912 11:08:43.058118 Set Vref, RX VrefLevel [Byte0]: 73
7913 11:08:43.060834 [Byte1]: 73
7914 11:08:43.064987
7915 11:08:43.065547 Set Vref, RX VrefLevel [Byte0]: 74
7916 11:08:43.068207 [Byte1]: 74
7917 11:08:43.072534
7918 11:08:43.073109 Set Vref, RX VrefLevel [Byte0]: 75
7919 11:08:43.075692 [Byte1]: 75
7920 11:08:43.080125
7921 11:08:43.080690 Set Vref, RX VrefLevel [Byte0]: 76
7922 11:08:43.083233 [Byte1]: 76
7923 11:08:43.087825
7924 11:08:43.088389 Set Vref, RX VrefLevel [Byte0]: 77
7925 11:08:43.090897 [Byte1]: 77
7926 11:08:43.095208
7927 11:08:43.095767 Set Vref, RX VrefLevel [Byte0]: 78
7928 11:08:43.098673 [Byte1]: 78
7929 11:08:43.102896
7930 11:08:43.103455 Set Vref, RX VrefLevel [Byte0]: 79
7931 11:08:43.105798 [Byte1]: 79
7932 11:08:43.110561
7933 11:08:43.111051 Set Vref, RX VrefLevel [Byte0]: 80
7934 11:08:43.113799 [Byte1]: 80
7935 11:08:43.117914
7936 11:08:43.118546 Set Vref, RX VrefLevel [Byte0]: 81
7937 11:08:43.121404 [Byte1]: 81
7938 11:08:43.125400
7939 11:08:43.125995 Final RX Vref Byte 0 = 58 to rank0
7940 11:08:43.128875 Final RX Vref Byte 1 = 62 to rank0
7941 11:08:43.132252 Final RX Vref Byte 0 = 58 to rank1
7942 11:08:43.135619 Final RX Vref Byte 1 = 62 to rank1==
7943 11:08:43.138827 Dram Type= 6, Freq= 0, CH_0, rank 0
7944 11:08:43.145759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7945 11:08:43.146388 ==
7946 11:08:43.146770 DQS Delay:
7947 11:08:43.147113 DQS0 = 0, DQS1 = 0
7948 11:08:43.148853 DQM Delay:
7949 11:08:43.149325 DQM0 = 136, DQM1 = 124
7950 11:08:43.152002 DQ Delay:
7951 11:08:43.155627 DQ0 =136, DQ1 =140, DQ2 =132, DQ3 =132
7952 11:08:43.158902 DQ4 =140, DQ5 =126, DQ6 =142, DQ7 =144
7953 11:08:43.162053 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
7954 11:08:43.165757 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
7955 11:08:43.166375
7956 11:08:43.166754
7957 11:08:43.167098
7958 11:08:43.168847 [DramC_TX_OE_Calibration] TA2
7959 11:08:43.172087 Original DQ_B0 (3 6) =30, OEN = 27
7960 11:08:43.175214 Original DQ_B1 (3 6) =30, OEN = 27
7961 11:08:43.178637 24, 0x0, End_B0=24 End_B1=24
7962 11:08:43.179235 25, 0x0, End_B0=25 End_B1=25
7963 11:08:43.182051 26, 0x0, End_B0=26 End_B1=26
7964 11:08:43.185295 27, 0x0, End_B0=27 End_B1=27
7965 11:08:43.188852 28, 0x0, End_B0=28 End_B1=28
7966 11:08:43.189423 29, 0x0, End_B0=29 End_B1=29
7967 11:08:43.192142 30, 0x0, End_B0=30 End_B1=30
7968 11:08:43.195461 31, 0x4141, End_B0=30 End_B1=30
7969 11:08:43.198874 Byte0 end_step=30 best_step=27
7970 11:08:43.202136 Byte1 end_step=30 best_step=27
7971 11:08:43.205842 Byte0 TX OE(2T, 0.5T) = (3, 3)
7972 11:08:43.206447 Byte1 TX OE(2T, 0.5T) = (3, 3)
7973 11:08:43.208987
7974 11:08:43.209545
7975 11:08:43.215019 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7976 11:08:43.218429 CH0 RK0: MR19=303, MR18=1C1B
7977 11:08:43.224861 CH0_RK0: MR19=0x303, MR18=0x1C1B, DQSOSC=395, MR23=63, INC=23, DEC=15
7978 11:08:43.225343
7979 11:08:43.228437 ----->DramcWriteLeveling(PI) begin...
7980 11:08:43.228910 ==
7981 11:08:43.231560 Dram Type= 6, Freq= 0, CH_0, rank 1
7982 11:08:43.235181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7983 11:08:43.235754 ==
7984 11:08:43.238829 Write leveling (Byte 0): 35 => 35
7985 11:08:43.242136 Write leveling (Byte 1): 29 => 29
7986 11:08:43.245533 DramcWriteLeveling(PI) end<-----
7987 11:08:43.246158
7988 11:08:43.246640 ==
7989 11:08:43.248511 Dram Type= 6, Freq= 0, CH_0, rank 1
7990 11:08:43.252247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7991 11:08:43.252812 ==
7992 11:08:43.254749 [Gating] SW mode calibration
7993 11:08:43.262006 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7994 11:08:43.268659 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7995 11:08:43.271853 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 11:08:43.275157 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 11:08:43.281670 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
7998 11:08:43.285340 1 4 12 | B1->B0 | 2828 3333 | 0 0 | (0 0) (1 1)
7999 11:08:43.288272 1 4 16 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8000 11:08:43.295229 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 11:08:43.298557 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 11:08:43.301701 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8003 11:08:43.308263 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8004 11:08:43.312021 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8005 11:08:43.315023 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8006 11:08:43.321373 1 5 12 | B1->B0 | 3434 2828 | 1 1 | (1 0) (1 0)
8007 11:08:43.324606 1 5 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
8008 11:08:43.328146 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 11:08:43.334693 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 11:08:43.338051 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 11:08:43.341067 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 11:08:43.348414 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 11:08:43.351495 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8014 11:08:43.355103 1 6 12 | B1->B0 | 3030 4545 | 0 0 | (0 0) (0 0)
8015 11:08:43.361700 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 11:08:43.364536 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 11:08:43.368221 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 11:08:43.374795 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 11:08:43.378091 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 11:08:43.381531 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 11:08:43.384725 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 11:08:43.391195 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8023 11:08:43.394862 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8024 11:08:43.398020 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8025 11:08:43.404723 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 11:08:43.407879 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 11:08:43.411055 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 11:08:43.418054 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 11:08:43.421233 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 11:08:43.424611 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 11:08:43.431093 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 11:08:43.434617 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 11:08:43.438188 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 11:08:43.444869 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 11:08:43.447795 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 11:08:43.451244 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 11:08:43.458390 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8038 11:08:43.461672 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8039 11:08:43.464527 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8040 11:08:43.471154 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 11:08:43.471736 Total UI for P1: 0, mck2ui 16
8042 11:08:43.478084 best dqsien dly found for B0: ( 1, 9, 12)
8043 11:08:43.478653 Total UI for P1: 0, mck2ui 16
8044 11:08:43.481262 best dqsien dly found for B1: ( 1, 9, 16)
8045 11:08:43.488069 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8046 11:08:43.491342 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8047 11:08:43.491916
8048 11:08:43.494445 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8049 11:08:43.497622 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8050 11:08:43.500753 [Gating] SW calibration Done
8051 11:08:43.501226 ==
8052 11:08:43.504491 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 11:08:43.507838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 11:08:43.508418 ==
8055 11:08:43.510793 RX Vref Scan: 0
8056 11:08:43.511257
8057 11:08:43.511625 RX Vref 0 -> 0, step: 1
8058 11:08:43.511973
8059 11:08:43.513967 RX Delay 0 -> 252, step: 8
8060 11:08:43.517299 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8061 11:08:43.524286 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8062 11:08:43.527492 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8063 11:08:43.530678 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8064 11:08:43.534157 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8065 11:08:43.537196 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8066 11:08:43.544056 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8067 11:08:43.547540 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8068 11:08:43.550631 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8069 11:08:43.553647 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8070 11:08:43.557415 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8071 11:08:43.560809 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8072 11:08:43.567295 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8073 11:08:43.571151 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8074 11:08:43.574208 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8075 11:08:43.577368 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8076 11:08:43.577857 ==
8077 11:08:43.580839 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 11:08:43.587315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 11:08:43.587891 ==
8080 11:08:43.588269 DQS Delay:
8081 11:08:43.590474 DQS0 = 0, DQS1 = 0
8082 11:08:43.590942 DQM Delay:
8083 11:08:43.594031 DQM0 = 136, DQM1 = 125
8084 11:08:43.594589 DQ Delay:
8085 11:08:43.597317 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8086 11:08:43.600531 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8087 11:08:43.603671 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8088 11:08:43.607189 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8089 11:08:43.607655
8090 11:08:43.608022
8091 11:08:43.608367 ==
8092 11:08:43.610608 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 11:08:43.617131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 11:08:43.617695 ==
8095 11:08:43.618112
8096 11:08:43.618458
8097 11:08:43.618786 TX Vref Scan disable
8098 11:08:43.620543 == TX Byte 0 ==
8099 11:08:43.623898 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8100 11:08:43.630550 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8101 11:08:43.631118 == TX Byte 1 ==
8102 11:08:43.633869 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8103 11:08:43.640652 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8104 11:08:43.641218 ==
8105 11:08:43.643600 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 11:08:43.647014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 11:08:43.647481 ==
8108 11:08:43.660383
8109 11:08:43.663717 TX Vref early break, caculate TX vref
8110 11:08:43.667059 TX Vref=16, minBit 3, minWin=23, winSum=389
8111 11:08:43.670191 TX Vref=18, minBit 1, minWin=24, winSum=400
8112 11:08:43.673746 TX Vref=20, minBit 0, minWin=24, winSum=408
8113 11:08:43.676767 TX Vref=22, minBit 0, minWin=25, winSum=415
8114 11:08:43.680049 TX Vref=24, minBit 0, minWin=25, winSum=423
8115 11:08:43.686716 TX Vref=26, minBit 2, minWin=25, winSum=429
8116 11:08:43.690286 TX Vref=28, minBit 2, minWin=25, winSum=433
8117 11:08:43.693423 TX Vref=30, minBit 2, minWin=25, winSum=425
8118 11:08:43.697093 TX Vref=32, minBit 2, minWin=25, winSum=414
8119 11:08:43.700033 TX Vref=34, minBit 1, minWin=24, winSum=407
8120 11:08:43.706560 [TxChooseVref] Worse bit 2, Min win 25, Win sum 433, Final Vref 28
8121 11:08:43.707118
8122 11:08:43.709613 Final TX Range 0 Vref 28
8123 11:08:43.710117
8124 11:08:43.710489 ==
8125 11:08:43.713125 Dram Type= 6, Freq= 0, CH_0, rank 1
8126 11:08:43.716719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8127 11:08:43.717283 ==
8128 11:08:43.717654
8129 11:08:43.718025
8130 11:08:43.719880 TX Vref Scan disable
8131 11:08:43.726348 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8132 11:08:43.726906 == TX Byte 0 ==
8133 11:08:43.729847 u2DelayCellOfst[0]=13 cells (4 PI)
8134 11:08:43.733290 u2DelayCellOfst[1]=16 cells (5 PI)
8135 11:08:43.736481 u2DelayCellOfst[2]=10 cells (3 PI)
8136 11:08:43.739627 u2DelayCellOfst[3]=13 cells (4 PI)
8137 11:08:43.742667 u2DelayCellOfst[4]=10 cells (3 PI)
8138 11:08:43.746121 u2DelayCellOfst[5]=0 cells (0 PI)
8139 11:08:43.749792 u2DelayCellOfst[6]=16 cells (5 PI)
8140 11:08:43.752767 u2DelayCellOfst[7]=16 cells (5 PI)
8141 11:08:43.756575 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8142 11:08:43.759459 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8143 11:08:43.762905 == TX Byte 1 ==
8144 11:08:43.766101 u2DelayCellOfst[8]=0 cells (0 PI)
8145 11:08:43.766566 u2DelayCellOfst[9]=3 cells (1 PI)
8146 11:08:43.769398 u2DelayCellOfst[10]=6 cells (2 PI)
8147 11:08:43.773305 u2DelayCellOfst[11]=3 cells (1 PI)
8148 11:08:43.776260 u2DelayCellOfst[12]=13 cells (4 PI)
8149 11:08:43.779577 u2DelayCellOfst[13]=10 cells (3 PI)
8150 11:08:43.783113 u2DelayCellOfst[14]=13 cells (4 PI)
8151 11:08:43.786230 u2DelayCellOfst[15]=10 cells (3 PI)
8152 11:08:43.789721 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8153 11:08:43.796212 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8154 11:08:43.796771 DramC Write-DBI on
8155 11:08:43.797144 ==
8156 11:08:43.799221 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 11:08:43.806040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 11:08:43.806608 ==
8159 11:08:43.806981
8160 11:08:43.807318
8161 11:08:43.807643 TX Vref Scan disable
8162 11:08:43.809658 == TX Byte 0 ==
8163 11:08:43.813054 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8164 11:08:43.816622 == TX Byte 1 ==
8165 11:08:43.819718 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8166 11:08:43.823034 DramC Write-DBI off
8167 11:08:43.823592
8168 11:08:43.823961 [DATLAT]
8169 11:08:43.824300 Freq=1600, CH0 RK1
8170 11:08:43.824629
8171 11:08:43.826134 DATLAT Default: 0xf
8172 11:08:43.826621 0, 0xFFFF, sum = 0
8173 11:08:43.829829 1, 0xFFFF, sum = 0
8174 11:08:43.833328 2, 0xFFFF, sum = 0
8175 11:08:43.833905 3, 0xFFFF, sum = 0
8176 11:08:43.836672 4, 0xFFFF, sum = 0
8177 11:08:43.837255 5, 0xFFFF, sum = 0
8178 11:08:43.839776 6, 0xFFFF, sum = 0
8179 11:08:43.840358 7, 0xFFFF, sum = 0
8180 11:08:43.843056 8, 0xFFFF, sum = 0
8181 11:08:43.843645 9, 0xFFFF, sum = 0
8182 11:08:43.846150 10, 0xFFFF, sum = 0
8183 11:08:43.846726 11, 0xFFFF, sum = 0
8184 11:08:43.849300 12, 0xFFFF, sum = 0
8185 11:08:43.849778 13, 0xFFFF, sum = 0
8186 11:08:43.852966 14, 0x0, sum = 1
8187 11:08:43.853583 15, 0x0, sum = 2
8188 11:08:43.856404 16, 0x0, sum = 3
8189 11:08:43.856989 17, 0x0, sum = 4
8190 11:08:43.859549 best_step = 15
8191 11:08:43.860017
8192 11:08:43.860389 ==
8193 11:08:43.862763 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 11:08:43.866158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 11:08:43.866727 ==
8196 11:08:43.869324 RX Vref Scan: 0
8197 11:08:43.869876
8198 11:08:43.870307 RX Vref 0 -> 0, step: 1
8199 11:08:43.870656
8200 11:08:43.872787 RX Delay 11 -> 252, step: 4
8201 11:08:43.876019 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8202 11:08:43.882783 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8203 11:08:43.886043 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8204 11:08:43.888974 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8205 11:08:43.892445 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8206 11:08:43.895535 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8207 11:08:43.902690 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8208 11:08:43.905819 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8209 11:08:43.909270 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8210 11:08:43.912933 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8211 11:08:43.916085 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8212 11:08:43.922646 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8213 11:08:43.925543 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8214 11:08:43.929452 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8215 11:08:43.932655 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8216 11:08:43.935725 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8217 11:08:43.939219 ==
8218 11:08:43.942404 Dram Type= 6, Freq= 0, CH_0, rank 1
8219 11:08:43.945883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8220 11:08:43.946466 ==
8221 11:08:43.946883 DQS Delay:
8222 11:08:43.949042 DQS0 = 0, DQS1 = 0
8223 11:08:43.949501 DQM Delay:
8224 11:08:43.952475 DQM0 = 133, DQM1 = 123
8225 11:08:43.953053 DQ Delay:
8226 11:08:43.955957 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8227 11:08:43.959718 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8228 11:08:43.962099 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8229 11:08:43.965551 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8230 11:08:43.966038
8231 11:08:43.966577
8232 11:08:43.967020
8233 11:08:43.968820 [DramC_TX_OE_Calibration] TA2
8234 11:08:43.972535 Original DQ_B0 (3 6) =30, OEN = 27
8235 11:08:43.975518 Original DQ_B1 (3 6) =30, OEN = 27
8236 11:08:43.978629 24, 0x0, End_B0=24 End_B1=24
8237 11:08:43.982080 25, 0x0, End_B0=25 End_B1=25
8238 11:08:43.982601 26, 0x0, End_B0=26 End_B1=26
8239 11:08:43.985577 27, 0x0, End_B0=27 End_B1=27
8240 11:08:43.989142 28, 0x0, End_B0=28 End_B1=28
8241 11:08:43.992014 29, 0x0, End_B0=29 End_B1=29
8242 11:08:43.995122 30, 0x0, End_B0=30 End_B1=30
8243 11:08:43.995591 31, 0x4141, End_B0=30 End_B1=30
8244 11:08:43.998497 Byte0 end_step=30 best_step=27
8245 11:08:44.001897 Byte1 end_step=30 best_step=27
8246 11:08:44.005466 Byte0 TX OE(2T, 0.5T) = (3, 3)
8247 11:08:44.008783 Byte1 TX OE(2T, 0.5T) = (3, 3)
8248 11:08:44.009348
8249 11:08:44.009715
8250 11:08:44.015255 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
8251 11:08:44.018701 CH0 RK1: MR19=303, MR18=1E0B
8252 11:08:44.025242 CH0_RK1: MR19=0x303, MR18=0x1E0B, DQSOSC=394, MR23=63, INC=23, DEC=15
8253 11:08:44.028628 [RxdqsGatingPostProcess] freq 1600
8254 11:08:44.035181 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8255 11:08:44.035746 best DQS0 dly(2T, 0.5T) = (1, 1)
8256 11:08:44.038221 best DQS1 dly(2T, 0.5T) = (1, 1)
8257 11:08:44.041988 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8258 11:08:44.045518 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8259 11:08:44.048655 best DQS0 dly(2T, 0.5T) = (1, 1)
8260 11:08:44.052134 best DQS1 dly(2T, 0.5T) = (1, 1)
8261 11:08:44.055067 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8262 11:08:44.058470 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8263 11:08:44.061809 Pre-setting of DQS Precalculation
8264 11:08:44.065276 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8265 11:08:44.065868 ==
8266 11:08:44.068402 Dram Type= 6, Freq= 0, CH_1, rank 0
8267 11:08:44.075120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8268 11:08:44.075732 ==
8269 11:08:44.078681 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8270 11:08:44.085523 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8271 11:08:44.088332 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8272 11:08:44.095266 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8273 11:08:44.102411 [CA 0] Center 42 (12~72) winsize 61
8274 11:08:44.106201 [CA 1] Center 42 (12~72) winsize 61
8275 11:08:44.109634 [CA 2] Center 38 (9~68) winsize 60
8276 11:08:44.112832 [CA 3] Center 37 (8~67) winsize 60
8277 11:08:44.116020 [CA 4] Center 37 (8~67) winsize 60
8278 11:08:44.119250 [CA 5] Center 37 (7~67) winsize 61
8279 11:08:44.119809
8280 11:08:44.122908 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8281 11:08:44.123472
8282 11:08:44.126096 [CATrainingPosCal] consider 1 rank data
8283 11:08:44.129628 u2DelayCellTimex100 = 290/100 ps
8284 11:08:44.132766 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8285 11:08:44.139186 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8286 11:08:44.142461 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8287 11:08:44.146305 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8288 11:08:44.149249 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8289 11:08:44.152893 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8290 11:08:44.153453
8291 11:08:44.156192 CA PerBit enable=1, Macro0, CA PI delay=37
8292 11:08:44.156759
8293 11:08:44.159233 [CBTSetCACLKResult] CA Dly = 37
8294 11:08:44.162574 CS Dly: 8 (0~39)
8295 11:08:44.165745 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8296 11:08:44.169064 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8297 11:08:44.169517 ==
8298 11:08:44.172362 Dram Type= 6, Freq= 0, CH_1, rank 1
8299 11:08:44.175996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 11:08:44.176455 ==
8301 11:08:44.182492 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8302 11:08:44.185791 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8303 11:08:44.192159 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8304 11:08:44.195197 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8305 11:08:44.205824 [CA 0] Center 42 (12~72) winsize 61
8306 11:08:44.209133 [CA 1] Center 42 (12~72) winsize 61
8307 11:08:44.212699 [CA 2] Center 37 (8~67) winsize 60
8308 11:08:44.215982 [CA 3] Center 37 (8~66) winsize 59
8309 11:08:44.219321 [CA 4] Center 37 (8~67) winsize 60
8310 11:08:44.222517 [CA 5] Center 36 (7~66) winsize 60
8311 11:08:44.223065
8312 11:08:44.225586 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8313 11:08:44.226077
8314 11:08:44.228817 [CATrainingPosCal] consider 2 rank data
8315 11:08:44.232480 u2DelayCellTimex100 = 290/100 ps
8316 11:08:44.235669 CA0 delay=42 (12~72),Diff = 6 PI (20 cell)
8317 11:08:44.242489 CA1 delay=42 (12~72),Diff = 6 PI (20 cell)
8318 11:08:44.245615 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8319 11:08:44.248984 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8320 11:08:44.252238 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8321 11:08:44.255297 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8322 11:08:44.255823
8323 11:08:44.258589 CA PerBit enable=1, Macro0, CA PI delay=36
8324 11:08:44.259041
8325 11:08:44.262254 [CBTSetCACLKResult] CA Dly = 36
8326 11:08:44.265357 CS Dly: 9 (0~42)
8327 11:08:44.268807 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8328 11:08:44.272153 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8329 11:08:44.272702
8330 11:08:44.275195 ----->DramcWriteLeveling(PI) begin...
8331 11:08:44.275686 ==
8332 11:08:44.278547 Dram Type= 6, Freq= 0, CH_1, rank 0
8333 11:08:44.282046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 11:08:44.285692 ==
8335 11:08:44.288398 Write leveling (Byte 0): 23 => 23
8336 11:08:44.288928 Write leveling (Byte 1): 27 => 27
8337 11:08:44.291969 DramcWriteLeveling(PI) end<-----
8338 11:08:44.292518
8339 11:08:44.292902 ==
8340 11:08:44.295505 Dram Type= 6, Freq= 0, CH_1, rank 0
8341 11:08:44.301695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8342 11:08:44.302272 ==
8343 11:08:44.305346 [Gating] SW mode calibration
8344 11:08:44.312138 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8345 11:08:44.315292 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8346 11:08:44.322093 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 11:08:44.325314 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
8348 11:08:44.328704 1 4 8 | B1->B0 | 3030 3232 | 1 1 | (1 1) (1 1)
8349 11:08:44.335222 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 11:08:44.338592 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 11:08:44.341689 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 11:08:44.348525 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 11:08:44.351923 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 11:08:44.354881 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 11:08:44.358093 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8356 11:08:44.365258 1 5 8 | B1->B0 | 2a2a 2727 | 1 0 | (1 0) (1 0)
8357 11:08:44.368312 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 11:08:44.371807 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 11:08:44.378175 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 11:08:44.381563 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 11:08:44.385372 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 11:08:44.391917 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 11:08:44.394905 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 11:08:44.398520 1 6 8 | B1->B0 | 3737 4444 | 0 0 | (0 0) (0 0)
8365 11:08:44.405083 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 11:08:44.408373 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 11:08:44.411742 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 11:08:44.418414 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 11:08:44.421572 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 11:08:44.424599 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 11:08:44.431777 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 11:08:44.434957 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8373 11:08:44.438468 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8374 11:08:44.444920 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 11:08:44.447894 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 11:08:44.451853 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 11:08:44.458053 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 11:08:44.461249 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 11:08:44.464841 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 11:08:44.471343 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 11:08:44.474971 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 11:08:44.478199 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 11:08:44.481630 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 11:08:44.488202 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 11:08:44.491646 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 11:08:44.494529 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 11:08:44.501184 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8388 11:08:44.504764 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8389 11:08:44.508101 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8390 11:08:44.511185 Total UI for P1: 0, mck2ui 16
8391 11:08:44.514847 best dqsien dly found for B0: ( 1, 9, 6)
8392 11:08:44.521413 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 11:08:44.522021 Total UI for P1: 0, mck2ui 16
8394 11:08:44.528428 best dqsien dly found for B1: ( 1, 9, 10)
8395 11:08:44.531068 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8396 11:08:44.534548 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8397 11:08:44.535163
8398 11:08:44.537847 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8399 11:08:44.541359 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8400 11:08:44.544655 [Gating] SW calibration Done
8401 11:08:44.545216 ==
8402 11:08:44.547381 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 11:08:44.551109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 11:08:44.551669 ==
8405 11:08:44.554063 RX Vref Scan: 0
8406 11:08:44.554520
8407 11:08:44.554885 RX Vref 0 -> 0, step: 1
8408 11:08:44.557782
8409 11:08:44.558306 RX Delay 0 -> 252, step: 8
8410 11:08:44.561413 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8411 11:08:44.568046 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8412 11:08:44.571279 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8413 11:08:44.574160 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8414 11:08:44.577562 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8415 11:08:44.581167 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8416 11:08:44.587928 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8417 11:08:44.591319 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8418 11:08:44.594057 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8419 11:08:44.598020 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8420 11:08:44.601190 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8421 11:08:44.607766 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8422 11:08:44.610800 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8423 11:08:44.614530 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8424 11:08:44.617222 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8425 11:08:44.621142 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8426 11:08:44.623941 ==
8427 11:08:44.624402 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 11:08:44.630566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 11:08:44.631131 ==
8430 11:08:44.631501 DQS Delay:
8431 11:08:44.634282 DQS0 = 0, DQS1 = 0
8432 11:08:44.634844 DQM Delay:
8433 11:08:44.637654 DQM0 = 137, DQM1 = 129
8434 11:08:44.638271 DQ Delay:
8435 11:08:44.640977 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8436 11:08:44.644281 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8437 11:08:44.647522 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8438 11:08:44.650865 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8439 11:08:44.651422
8440 11:08:44.651788
8441 11:08:44.652128 ==
8442 11:08:44.654192 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 11:08:44.660648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 11:08:44.661215 ==
8445 11:08:44.661593
8446 11:08:44.661936
8447 11:08:44.662319 TX Vref Scan disable
8448 11:08:44.664027 == TX Byte 0 ==
8449 11:08:44.667682 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8450 11:08:44.670593 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8451 11:08:44.674261 == TX Byte 1 ==
8452 11:08:44.677416 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8453 11:08:44.684442 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8454 11:08:44.685011 ==
8455 11:08:44.687300 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 11:08:44.690602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 11:08:44.691177 ==
8458 11:08:44.703932
8459 11:08:44.707361 TX Vref early break, caculate TX vref
8460 11:08:44.710957 TX Vref=16, minBit 9, minWin=22, winSum=374
8461 11:08:44.714020 TX Vref=18, minBit 10, minWin=22, winSum=383
8462 11:08:44.717633 TX Vref=20, minBit 10, minWin=22, winSum=392
8463 11:08:44.720543 TX Vref=22, minBit 10, minWin=24, winSum=402
8464 11:08:44.723679 TX Vref=24, minBit 11, minWin=24, winSum=404
8465 11:08:44.730938 TX Vref=26, minBit 10, minWin=25, winSum=421
8466 11:08:44.733919 TX Vref=28, minBit 10, minWin=25, winSum=420
8467 11:08:44.737808 TX Vref=30, minBit 12, minWin=25, winSum=421
8468 11:08:44.740935 TX Vref=32, minBit 12, minWin=24, winSum=410
8469 11:08:44.744102 TX Vref=34, minBit 9, minWin=24, winSum=399
8470 11:08:44.750677 TX Vref=36, minBit 12, minWin=23, winSum=391
8471 11:08:44.753937 [TxChooseVref] Worse bit 10, Min win 25, Win sum 421, Final Vref 26
8472 11:08:44.754547
8473 11:08:44.757337 Final TX Range 0 Vref 26
8474 11:08:44.758228
8475 11:08:44.758634 ==
8476 11:08:44.760747 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 11:08:44.764370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 11:08:44.766974 ==
8479 11:08:44.767446
8480 11:08:44.767814
8481 11:08:44.768157 TX Vref Scan disable
8482 11:08:44.774011 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8483 11:08:44.774591 == TX Byte 0 ==
8484 11:08:44.777586 u2DelayCellOfst[0]=16 cells (5 PI)
8485 11:08:44.780902 u2DelayCellOfst[1]=10 cells (3 PI)
8486 11:08:44.784219 u2DelayCellOfst[2]=0 cells (0 PI)
8487 11:08:44.787438 u2DelayCellOfst[3]=6 cells (2 PI)
8488 11:08:44.790619 u2DelayCellOfst[4]=6 cells (2 PI)
8489 11:08:44.793897 u2DelayCellOfst[5]=16 cells (5 PI)
8490 11:08:44.797359 u2DelayCellOfst[6]=16 cells (5 PI)
8491 11:08:44.800826 u2DelayCellOfst[7]=3 cells (1 PI)
8492 11:08:44.803690 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8493 11:08:44.807060 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8494 11:08:44.810420 == TX Byte 1 ==
8495 11:08:44.814131 u2DelayCellOfst[8]=0 cells (0 PI)
8496 11:08:44.817448 u2DelayCellOfst[9]=3 cells (1 PI)
8497 11:08:44.820927 u2DelayCellOfst[10]=10 cells (3 PI)
8498 11:08:44.821493 u2DelayCellOfst[11]=3 cells (1 PI)
8499 11:08:44.823545 u2DelayCellOfst[12]=13 cells (4 PI)
8500 11:08:44.826753 u2DelayCellOfst[13]=16 cells (5 PI)
8501 11:08:44.830425 u2DelayCellOfst[14]=16 cells (5 PI)
8502 11:08:44.833737 u2DelayCellOfst[15]=16 cells (5 PI)
8503 11:08:44.840500 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8504 11:08:44.843785 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8505 11:08:44.844390 DramC Write-DBI on
8506 11:08:44.847051 ==
8507 11:08:44.847619 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 11:08:44.853906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 11:08:44.854526 ==
8510 11:08:44.854905
8511 11:08:44.855258
8512 11:08:44.857458 TX Vref Scan disable
8513 11:08:44.858080 == TX Byte 0 ==
8514 11:08:44.863550 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8515 11:08:44.864021 == TX Byte 1 ==
8516 11:08:44.866878 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8517 11:08:44.870099 DramC Write-DBI off
8518 11:08:44.870563
8519 11:08:44.870934 [DATLAT]
8520 11:08:44.873595 Freq=1600, CH1 RK0
8521 11:08:44.874212
8522 11:08:44.874594 DATLAT Default: 0xf
8523 11:08:44.876603 0, 0xFFFF, sum = 0
8524 11:08:44.877207 1, 0xFFFF, sum = 0
8525 11:08:44.880044 2, 0xFFFF, sum = 0
8526 11:08:44.880690 3, 0xFFFF, sum = 0
8527 11:08:44.883673 4, 0xFFFF, sum = 0
8528 11:08:44.884253 5, 0xFFFF, sum = 0
8529 11:08:44.886870 6, 0xFFFF, sum = 0
8530 11:08:44.887448 7, 0xFFFF, sum = 0
8531 11:08:44.890382 8, 0xFFFF, sum = 0
8532 11:08:44.890960 9, 0xFFFF, sum = 0
8533 11:08:44.893689 10, 0xFFFF, sum = 0
8534 11:08:44.897090 11, 0xFFFF, sum = 0
8535 11:08:44.897671 12, 0xFFFF, sum = 0
8536 11:08:44.900276 13, 0xFFFF, sum = 0
8537 11:08:44.900853 14, 0x0, sum = 1
8538 11:08:44.903725 15, 0x0, sum = 2
8539 11:08:44.904305 16, 0x0, sum = 3
8540 11:08:44.904686 17, 0x0, sum = 4
8541 11:08:44.906848 best_step = 15
8542 11:08:44.907313
8543 11:08:44.907683 ==
8544 11:08:44.910091 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 11:08:44.913369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 11:08:44.913841 ==
8547 11:08:44.916653 RX Vref Scan: 1
8548 11:08:44.917312
8549 11:08:44.919820 Set Vref Range= 24 -> 127
8550 11:08:44.920457
8551 11:08:44.920998 RX Vref 24 -> 127, step: 1
8552 11:08:44.921515
8553 11:08:44.923143 RX Delay 19 -> 252, step: 4
8554 11:08:44.923650
8555 11:08:44.926592 Set Vref, RX VrefLevel [Byte0]: 24
8556 11:08:44.930035 [Byte1]: 24
8557 11:08:44.930491
8558 11:08:44.933212 Set Vref, RX VrefLevel [Byte0]: 25
8559 11:08:44.936300 [Byte1]: 25
8560 11:08:44.940518
8561 11:08:44.940990 Set Vref, RX VrefLevel [Byte0]: 26
8562 11:08:44.943763 [Byte1]: 26
8563 11:08:44.948076
8564 11:08:44.948543 Set Vref, RX VrefLevel [Byte0]: 27
8565 11:08:44.951592 [Byte1]: 27
8566 11:08:44.955689
8567 11:08:44.956270 Set Vref, RX VrefLevel [Byte0]: 28
8568 11:08:44.958839 [Byte1]: 28
8569 11:08:44.963330
8570 11:08:44.963901 Set Vref, RX VrefLevel [Byte0]: 29
8571 11:08:44.966440 [Byte1]: 29
8572 11:08:44.971162
8573 11:08:44.971728 Set Vref, RX VrefLevel [Byte0]: 30
8574 11:08:44.974281 [Byte1]: 30
8575 11:08:44.978515
8576 11:08:44.979075 Set Vref, RX VrefLevel [Byte0]: 31
8577 11:08:44.981598 [Byte1]: 31
8578 11:08:44.986342
8579 11:08:44.986899 Set Vref, RX VrefLevel [Byte0]: 32
8580 11:08:44.989665 [Byte1]: 32
8581 11:08:44.993830
8582 11:08:44.994491 Set Vref, RX VrefLevel [Byte0]: 33
8583 11:08:44.996818 [Byte1]: 33
8584 11:08:45.001395
8585 11:08:45.002003 Set Vref, RX VrefLevel [Byte0]: 34
8586 11:08:45.004580 [Byte1]: 34
8587 11:08:45.008965
8588 11:08:45.009527 Set Vref, RX VrefLevel [Byte0]: 35
8589 11:08:45.012126 [Byte1]: 35
8590 11:08:45.016561
8591 11:08:45.017123 Set Vref, RX VrefLevel [Byte0]: 36
8592 11:08:45.019905 [Byte1]: 36
8593 11:08:45.023867
8594 11:08:45.024455 Set Vref, RX VrefLevel [Byte0]: 37
8595 11:08:45.027065 [Byte1]: 37
8596 11:08:45.031251
8597 11:08:45.031714 Set Vref, RX VrefLevel [Byte0]: 38
8598 11:08:45.035240 [Byte1]: 38
8599 11:08:45.039162
8600 11:08:45.039720 Set Vref, RX VrefLevel [Byte0]: 39
8601 11:08:45.042324 [Byte1]: 39
8602 11:08:45.046569
8603 11:08:45.047035 Set Vref, RX VrefLevel [Byte0]: 40
8604 11:08:45.049563 [Byte1]: 40
8605 11:08:45.054453
8606 11:08:45.055012 Set Vref, RX VrefLevel [Byte0]: 41
8607 11:08:45.057227 [Byte1]: 41
8608 11:08:45.061638
8609 11:08:45.062259 Set Vref, RX VrefLevel [Byte0]: 42
8610 11:08:45.065050 [Byte1]: 42
8611 11:08:45.069363
8612 11:08:45.069927 Set Vref, RX VrefLevel [Byte0]: 43
8613 11:08:45.072711 [Byte1]: 43
8614 11:08:45.076602
8615 11:08:45.077082 Set Vref, RX VrefLevel [Byte0]: 44
8616 11:08:45.083307 [Byte1]: 44
8617 11:08:45.083853
8618 11:08:45.086659 Set Vref, RX VrefLevel [Byte0]: 45
8619 11:08:45.090317 [Byte1]: 45
8620 11:08:45.090877
8621 11:08:45.093264 Set Vref, RX VrefLevel [Byte0]: 46
8622 11:08:45.096700 [Byte1]: 46
8623 11:08:45.097264
8624 11:08:45.100035 Set Vref, RX VrefLevel [Byte0]: 47
8625 11:08:45.103591 [Byte1]: 47
8626 11:08:45.107216
8627 11:08:45.107683 Set Vref, RX VrefLevel [Byte0]: 48
8628 11:08:45.110506 [Byte1]: 48
8629 11:08:45.114880
8630 11:08:45.115457 Set Vref, RX VrefLevel [Byte0]: 49
8631 11:08:45.117838 [Byte1]: 49
8632 11:08:45.122016
8633 11:08:45.122482 Set Vref, RX VrefLevel [Byte0]: 50
8634 11:08:45.125527 [Byte1]: 50
8635 11:08:45.130083
8636 11:08:45.130635 Set Vref, RX VrefLevel [Byte0]: 51
8637 11:08:45.133201 [Byte1]: 51
8638 11:08:45.137737
8639 11:08:45.138322 Set Vref, RX VrefLevel [Byte0]: 52
8640 11:08:45.140762 [Byte1]: 52
8641 11:08:45.145175
8642 11:08:45.145741 Set Vref, RX VrefLevel [Byte0]: 53
8643 11:08:45.148134 [Byte1]: 53
8644 11:08:45.152572
8645 11:08:45.153126 Set Vref, RX VrefLevel [Byte0]: 54
8646 11:08:45.155989 [Byte1]: 54
8647 11:08:45.160047
8648 11:08:45.160534 Set Vref, RX VrefLevel [Byte0]: 55
8649 11:08:45.163157 [Byte1]: 55
8650 11:08:45.167731
8651 11:08:45.168291 Set Vref, RX VrefLevel [Byte0]: 56
8652 11:08:45.171113 [Byte1]: 56
8653 11:08:45.175329
8654 11:08:45.175785 Set Vref, RX VrefLevel [Byte0]: 57
8655 11:08:45.178483 [Byte1]: 57
8656 11:08:45.182871
8657 11:08:45.183430 Set Vref, RX VrefLevel [Byte0]: 58
8658 11:08:45.186013 [Byte1]: 58
8659 11:08:45.190392
8660 11:08:45.190949 Set Vref, RX VrefLevel [Byte0]: 59
8661 11:08:45.193910 [Byte1]: 59
8662 11:08:45.198002
8663 11:08:45.198461 Set Vref, RX VrefLevel [Byte0]: 60
8664 11:08:45.201419 [Byte1]: 60
8665 11:08:45.205735
8666 11:08:45.206240 Set Vref, RX VrefLevel [Byte0]: 61
8667 11:08:45.209309 [Byte1]: 61
8668 11:08:45.213373
8669 11:08:45.213933 Set Vref, RX VrefLevel [Byte0]: 62
8670 11:08:45.216671 [Byte1]: 62
8671 11:08:45.220921
8672 11:08:45.221481 Set Vref, RX VrefLevel [Byte0]: 63
8673 11:08:45.223848 [Byte1]: 63
8674 11:08:45.228314
8675 11:08:45.228879 Set Vref, RX VrefLevel [Byte0]: 64
8676 11:08:45.231304 [Byte1]: 64
8677 11:08:45.236412
8678 11:08:45.236972 Set Vref, RX VrefLevel [Byte0]: 65
8679 11:08:45.239535 [Byte1]: 65
8680 11:08:45.243337
8681 11:08:45.244056 Set Vref, RX VrefLevel [Byte0]: 66
8682 11:08:45.246708 [Byte1]: 66
8683 11:08:45.251233
8684 11:08:45.251785 Set Vref, RX VrefLevel [Byte0]: 67
8685 11:08:45.254605 [Byte1]: 67
8686 11:08:45.258568
8687 11:08:45.259030 Set Vref, RX VrefLevel [Byte0]: 68
8688 11:08:45.261933 [Byte1]: 68
8689 11:08:45.266284
8690 11:08:45.266745 Set Vref, RX VrefLevel [Byte0]: 69
8691 11:08:45.269230 [Byte1]: 69
8692 11:08:45.273654
8693 11:08:45.274164 Set Vref, RX VrefLevel [Byte0]: 70
8694 11:08:45.277050 [Byte1]: 70
8695 11:08:45.280945
8696 11:08:45.281406 Set Vref, RX VrefLevel [Byte0]: 71
8697 11:08:45.284557 [Byte1]: 71
8698 11:08:45.288839
8699 11:08:45.289299 Set Vref, RX VrefLevel [Byte0]: 72
8700 11:08:45.292051 [Byte1]: 72
8701 11:08:45.296108
8702 11:08:45.296528 Set Vref, RX VrefLevel [Byte0]: 73
8703 11:08:45.300012 [Byte1]: 73
8704 11:08:45.304103
8705 11:08:45.304520 Set Vref, RX VrefLevel [Byte0]: 74
8706 11:08:45.307012 [Byte1]: 74
8707 11:08:45.311355
8708 11:08:45.311772 Set Vref, RX VrefLevel [Byte0]: 75
8709 11:08:45.314663 [Byte1]: 75
8710 11:08:45.319351
8711 11:08:45.319768 Final RX Vref Byte 0 = 59 to rank0
8712 11:08:45.322504 Final RX Vref Byte 1 = 62 to rank0
8713 11:08:45.325775 Final RX Vref Byte 0 = 59 to rank1
8714 11:08:45.329106 Final RX Vref Byte 1 = 62 to rank1==
8715 11:08:45.332425 Dram Type= 6, Freq= 0, CH_1, rank 0
8716 11:08:45.339185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8717 11:08:45.339608 ==
8718 11:08:45.339945 DQS Delay:
8719 11:08:45.340255 DQS0 = 0, DQS1 = 0
8720 11:08:45.342423 DQM Delay:
8721 11:08:45.342843 DQM0 = 134, DQM1 = 129
8722 11:08:45.345471 DQ Delay:
8723 11:08:45.349103 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =132
8724 11:08:45.352178 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8725 11:08:45.355687 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8726 11:08:45.358793 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8727 11:08:45.358875
8728 11:08:45.358939
8729 11:08:45.358999
8730 11:08:45.361861 [DramC_TX_OE_Calibration] TA2
8731 11:08:45.365087 Original DQ_B0 (3 6) =30, OEN = 27
8732 11:08:45.368567 Original DQ_B1 (3 6) =30, OEN = 27
8733 11:08:45.371979 24, 0x0, End_B0=24 End_B1=24
8734 11:08:45.372074 25, 0x0, End_B0=25 End_B1=25
8735 11:08:45.375085 26, 0x0, End_B0=26 End_B1=26
8736 11:08:45.378471 27, 0x0, End_B0=27 End_B1=27
8737 11:08:45.381689 28, 0x0, End_B0=28 End_B1=28
8738 11:08:45.381802 29, 0x0, End_B0=29 End_B1=29
8739 11:08:45.385378 30, 0x0, End_B0=30 End_B1=30
8740 11:08:45.388558 31, 0x4141, End_B0=30 End_B1=30
8741 11:08:45.391813 Byte0 end_step=30 best_step=27
8742 11:08:45.395565 Byte1 end_step=30 best_step=27
8743 11:08:45.398494 Byte0 TX OE(2T, 0.5T) = (3, 3)
8744 11:08:45.398668 Byte1 TX OE(2T, 0.5T) = (3, 3)
8745 11:08:45.401956
8746 11:08:45.402128
8747 11:08:45.408887 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8748 11:08:45.412264 CH1 RK0: MR19=303, MR18=1725
8749 11:08:45.418744 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8750 11:08:45.418826
8751 11:08:45.422152 ----->DramcWriteLeveling(PI) begin...
8752 11:08:45.422236 ==
8753 11:08:45.425200 Dram Type= 6, Freq= 0, CH_1, rank 1
8754 11:08:45.428515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8755 11:08:45.428615 ==
8756 11:08:45.431759 Write leveling (Byte 0): 24 => 24
8757 11:08:45.435145 Write leveling (Byte 1): 29 => 29
8758 11:08:45.438522 DramcWriteLeveling(PI) end<-----
8759 11:08:45.438707
8760 11:08:45.438800 ==
8761 11:08:45.441821 Dram Type= 6, Freq= 0, CH_1, rank 1
8762 11:08:45.445205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8763 11:08:45.445396 ==
8764 11:08:45.448500 [Gating] SW mode calibration
8765 11:08:45.455337 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8766 11:08:45.461478 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8767 11:08:45.465459 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 11:08:45.468132 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 11:08:45.475217 1 4 8 | B1->B0 | 3131 2323 | 1 0 | (1 1) (0 0)
8770 11:08:45.478681 1 4 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
8771 11:08:45.481633 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 11:08:45.488579 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 11:08:45.492195 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 11:08:45.495047 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 11:08:45.502327 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 11:08:45.505290 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 11:08:45.508310 1 5 8 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 1)
8778 11:08:45.515492 1 5 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8779 11:08:45.518783 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 11:08:45.521890 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 11:08:45.528704 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 11:08:45.531632 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 11:08:45.535137 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 11:08:45.541761 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8785 11:08:45.545015 1 6 8 | B1->B0 | 3f3f 2525 | 0 0 | (0 0) (0 0)
8786 11:08:45.548874 1 6 12 | B1->B0 | 4646 3b3b | 0 0 | (0 0) (0 0)
8787 11:08:45.555508 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 11:08:45.558604 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 11:08:45.561731 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 11:08:45.568498 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 11:08:45.571708 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 11:08:45.575292 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 11:08:45.578135 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8794 11:08:45.585197 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8795 11:08:45.588455 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 11:08:45.591912 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 11:08:45.598159 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 11:08:45.601547 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 11:08:45.605040 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 11:08:45.611900 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 11:08:45.615010 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 11:08:45.618384 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 11:08:45.625153 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 11:08:45.628885 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 11:08:45.631759 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 11:08:45.638159 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 11:08:45.641747 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 11:08:45.644940 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8809 11:08:45.651341 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8810 11:08:45.654707 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8811 11:08:45.658058 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 11:08:45.661501 Total UI for P1: 0, mck2ui 16
8813 11:08:45.664452 best dqsien dly found for B0: ( 1, 9, 10)
8814 11:08:45.667850 Total UI for P1: 0, mck2ui 16
8815 11:08:45.671728 best dqsien dly found for B1: ( 1, 9, 8)
8816 11:08:45.674536 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8817 11:08:45.678103 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8818 11:08:45.678750
8819 11:08:45.684307 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8820 11:08:45.687916 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8821 11:08:45.688504 [Gating] SW calibration Done
8822 11:08:45.691531 ==
8823 11:08:45.694554 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 11:08:45.697806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 11:08:45.698312 ==
8826 11:08:45.698684 RX Vref Scan: 0
8827 11:08:45.699026
8828 11:08:45.701084 RX Vref 0 -> 0, step: 1
8829 11:08:45.701652
8830 11:08:45.704485 RX Delay 0 -> 252, step: 8
8831 11:08:45.708306 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8832 11:08:45.710726 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8833 11:08:45.714658 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8834 11:08:45.721202 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8835 11:08:45.724310 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8836 11:08:45.727622 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8837 11:08:45.730770 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8838 11:08:45.734239 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8839 11:08:45.740795 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8840 11:08:45.744444 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8841 11:08:45.747509 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8842 11:08:45.750490 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8843 11:08:45.754099 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8844 11:08:45.760977 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8845 11:08:45.764038 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8846 11:08:45.767372 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8847 11:08:45.767842 ==
8848 11:08:45.770890 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 11:08:45.774064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 11:08:45.774539 ==
8851 11:08:45.777576 DQS Delay:
8852 11:08:45.778177 DQS0 = 0, DQS1 = 0
8853 11:08:45.781089 DQM Delay:
8854 11:08:45.781660 DQM0 = 137, DQM1 = 132
8855 11:08:45.783876 DQ Delay:
8856 11:08:45.787868 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8857 11:08:45.790619 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =135
8858 11:08:45.794108 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8859 11:08:45.797222 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8860 11:08:45.797684
8861 11:08:45.798099
8862 11:08:45.798476 ==
8863 11:08:45.800997 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 11:08:45.804170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 11:08:45.804644 ==
8866 11:08:45.805110
8867 11:08:45.805467
8868 11:08:45.807012 TX Vref Scan disable
8869 11:08:45.810401 == TX Byte 0 ==
8870 11:08:45.814141 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8871 11:08:45.817290 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8872 11:08:45.820735 == TX Byte 1 ==
8873 11:08:45.824410 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8874 11:08:45.827271 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8875 11:08:45.827844 ==
8876 11:08:45.830448 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 11:08:45.837159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 11:08:45.837735 ==
8879 11:08:45.848720
8880 11:08:45.852312 TX Vref early break, caculate TX vref
8881 11:08:45.855665 TX Vref=16, minBit 9, minWin=21, winSum=378
8882 11:08:45.858878 TX Vref=18, minBit 8, minWin=23, winSum=389
8883 11:08:45.862381 TX Vref=20, minBit 8, minWin=22, winSum=397
8884 11:08:45.865467 TX Vref=22, minBit 9, minWin=23, winSum=403
8885 11:08:45.868740 TX Vref=24, minBit 9, minWin=24, winSum=411
8886 11:08:45.875860 TX Vref=26, minBit 11, minWin=24, winSum=415
8887 11:08:45.878908 TX Vref=28, minBit 8, minWin=24, winSum=418
8888 11:08:45.882174 TX Vref=30, minBit 8, minWin=24, winSum=412
8889 11:08:45.885863 TX Vref=32, minBit 0, minWin=24, winSum=397
8890 11:08:45.888917 TX Vref=34, minBit 8, minWin=23, winSum=392
8891 11:08:45.895107 [TxChooseVref] Worse bit 8, Min win 24, Win sum 418, Final Vref 28
8892 11:08:45.895580
8893 11:08:45.898580 Final TX Range 0 Vref 28
8894 11:08:45.899046
8895 11:08:45.899418 ==
8896 11:08:45.901554 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 11:08:45.905480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 11:08:45.906090 ==
8899 11:08:45.906470
8900 11:08:45.906814
8901 11:08:45.908598 TX Vref Scan disable
8902 11:08:45.915257 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8903 11:08:45.915840 == TX Byte 0 ==
8904 11:08:45.918495 u2DelayCellOfst[0]=13 cells (4 PI)
8905 11:08:45.922093 u2DelayCellOfst[1]=10 cells (3 PI)
8906 11:08:45.925315 u2DelayCellOfst[2]=0 cells (0 PI)
8907 11:08:45.928605 u2DelayCellOfst[3]=6 cells (2 PI)
8908 11:08:45.931880 u2DelayCellOfst[4]=6 cells (2 PI)
8909 11:08:45.935323 u2DelayCellOfst[5]=16 cells (5 PI)
8910 11:08:45.938068 u2DelayCellOfst[6]=16 cells (5 PI)
8911 11:08:45.938539 u2DelayCellOfst[7]=6 cells (2 PI)
8912 11:08:45.944936 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8913 11:08:45.948411 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8914 11:08:45.951244 == TX Byte 1 ==
8915 11:08:45.951712 u2DelayCellOfst[8]=0 cells (0 PI)
8916 11:08:45.954591 u2DelayCellOfst[9]=3 cells (1 PI)
8917 11:08:45.957885 u2DelayCellOfst[10]=6 cells (2 PI)
8918 11:08:45.961080 u2DelayCellOfst[11]=3 cells (1 PI)
8919 11:08:45.964458 u2DelayCellOfst[12]=10 cells (3 PI)
8920 11:08:45.968194 u2DelayCellOfst[13]=16 cells (5 PI)
8921 11:08:45.971592 u2DelayCellOfst[14]=16 cells (5 PI)
8922 11:08:45.974587 u2DelayCellOfst[15]=16 cells (5 PI)
8923 11:08:45.978116 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8924 11:08:45.984687 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8925 11:08:45.985240 DramC Write-DBI on
8926 11:08:45.985611 ==
8927 11:08:45.987757 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 11:08:45.991351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 11:08:45.994598 ==
8930 11:08:45.995067
8931 11:08:45.995438
8932 11:08:45.995788 TX Vref Scan disable
8933 11:08:45.998017 == TX Byte 0 ==
8934 11:08:46.001378 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8935 11:08:46.004669 == TX Byte 1 ==
8936 11:08:46.007888 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8937 11:08:46.011287 DramC Write-DBI off
8938 11:08:46.011757
8939 11:08:46.012126 [DATLAT]
8940 11:08:46.012471 Freq=1600, CH1 RK1
8941 11:08:46.012809
8942 11:08:46.014492 DATLAT Default: 0xf
8943 11:08:46.014957 0, 0xFFFF, sum = 0
8944 11:08:46.018081 1, 0xFFFF, sum = 0
8945 11:08:46.018550 2, 0xFFFF, sum = 0
8946 11:08:46.021024 3, 0xFFFF, sum = 0
8947 11:08:46.024802 4, 0xFFFF, sum = 0
8948 11:08:46.025274 5, 0xFFFF, sum = 0
8949 11:08:46.028037 6, 0xFFFF, sum = 0
8950 11:08:46.028620 7, 0xFFFF, sum = 0
8951 11:08:46.031241 8, 0xFFFF, sum = 0
8952 11:08:46.031717 9, 0xFFFF, sum = 0
8953 11:08:46.034700 10, 0xFFFF, sum = 0
8954 11:08:46.035274 11, 0xFFFF, sum = 0
8955 11:08:46.037871 12, 0xFFFF, sum = 0
8956 11:08:46.038473 13, 0xFFFF, sum = 0
8957 11:08:46.041301 14, 0x0, sum = 1
8958 11:08:46.041773 15, 0x0, sum = 2
8959 11:08:46.044891 16, 0x0, sum = 3
8960 11:08:46.045456 17, 0x0, sum = 4
8961 11:08:46.047778 best_step = 15
8962 11:08:46.048239
8963 11:08:46.048608 ==
8964 11:08:46.050969 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 11:08:46.054873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 11:08:46.055437 ==
8967 11:08:46.055812 RX Vref Scan: 0
8968 11:08:46.058037
8969 11:08:46.058498 RX Vref 0 -> 0, step: 1
8970 11:08:46.058865
8971 11:08:46.061017 RX Delay 19 -> 252, step: 4
8972 11:08:46.064184 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8973 11:08:46.071417 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8974 11:08:46.074524 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8975 11:08:46.078027 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8976 11:08:46.081081 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8977 11:08:46.084682 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8978 11:08:46.087985 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8979 11:08:46.094851 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8980 11:08:46.097605 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8981 11:08:46.101012 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
8982 11:08:46.104338 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8983 11:08:46.107855 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8984 11:08:46.114350 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8985 11:08:46.117478 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8986 11:08:46.121248 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8987 11:08:46.124758 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8988 11:08:46.125335 ==
8989 11:08:46.127561 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 11:08:46.134293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 11:08:46.134874 ==
8992 11:08:46.135254 DQS Delay:
8993 11:08:46.137530 DQS0 = 0, DQS1 = 0
8994 11:08:46.138024 DQM Delay:
8995 11:08:46.138401 DQM0 = 133, DQM1 = 130
8996 11:08:46.141156 DQ Delay:
8997 11:08:46.144357 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
8998 11:08:46.147217 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8999 11:08:46.150867 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
9000 11:08:46.153857 DQ12 =136, DQ13 =138, DQ14 =138, DQ15 =140
9001 11:08:46.154353
9002 11:08:46.154722
9003 11:08:46.155064
9004 11:08:46.157186 [DramC_TX_OE_Calibration] TA2
9005 11:08:46.160723 Original DQ_B0 (3 6) =30, OEN = 27
9006 11:08:46.163849 Original DQ_B1 (3 6) =30, OEN = 27
9007 11:08:46.167126 24, 0x0, End_B0=24 End_B1=24
9008 11:08:46.167598 25, 0x0, End_B0=25 End_B1=25
9009 11:08:46.170498 26, 0x0, End_B0=26 End_B1=26
9010 11:08:46.173991 27, 0x0, End_B0=27 End_B1=27
9011 11:08:46.177528 28, 0x0, End_B0=28 End_B1=28
9012 11:08:46.180736 29, 0x0, End_B0=29 End_B1=29
9013 11:08:46.181208 30, 0x0, End_B0=30 End_B1=30
9014 11:08:46.184238 31, 0x4141, End_B0=30 End_B1=30
9015 11:08:46.187444 Byte0 end_step=30 best_step=27
9016 11:08:46.190860 Byte1 end_step=30 best_step=27
9017 11:08:46.193968 Byte0 TX OE(2T, 0.5T) = (3, 3)
9018 11:08:46.197268 Byte1 TX OE(2T, 0.5T) = (3, 3)
9019 11:08:46.197827
9020 11:08:46.198252
9021 11:08:46.203874 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9022 11:08:46.207043 CH1 RK1: MR19=303, MR18=1C07
9023 11:08:46.213545 CH1_RK1: MR19=0x303, MR18=0x1C07, DQSOSC=395, MR23=63, INC=23, DEC=15
9024 11:08:46.216812 [RxdqsGatingPostProcess] freq 1600
9025 11:08:46.220327 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9026 11:08:46.223588 best DQS0 dly(2T, 0.5T) = (1, 1)
9027 11:08:46.227149 best DQS1 dly(2T, 0.5T) = (1, 1)
9028 11:08:46.230318 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9029 11:08:46.233310 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9030 11:08:46.236913 best DQS0 dly(2T, 0.5T) = (1, 1)
9031 11:08:46.240140 best DQS1 dly(2T, 0.5T) = (1, 1)
9032 11:08:46.243827 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9033 11:08:46.246721 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9034 11:08:46.250007 Pre-setting of DQS Precalculation
9035 11:08:46.253801 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9036 11:08:46.260242 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9037 11:08:46.270482 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9038 11:08:46.271046
9039 11:08:46.271416
9040 11:08:46.273446 [Calibration Summary] 3200 Mbps
9041 11:08:46.273919 CH 0, Rank 0
9042 11:08:46.277037 SW Impedance : PASS
9043 11:08:46.277596 DUTY Scan : NO K
9044 11:08:46.280205 ZQ Calibration : PASS
9045 11:08:46.280676 Jitter Meter : NO K
9046 11:08:46.283480 CBT Training : PASS
9047 11:08:46.286793 Write leveling : PASS
9048 11:08:46.287354 RX DQS gating : PASS
9049 11:08:46.290392 RX DQ/DQS(RDDQC) : PASS
9050 11:08:46.293444 TX DQ/DQS : PASS
9051 11:08:46.294004 RX DATLAT : PASS
9052 11:08:46.296784 RX DQ/DQS(Engine): PASS
9053 11:08:46.300238 TX OE : PASS
9054 11:08:46.300802 All Pass.
9055 11:08:46.301175
9056 11:08:46.301513 CH 0, Rank 1
9057 11:08:46.303519 SW Impedance : PASS
9058 11:08:46.306565 DUTY Scan : NO K
9059 11:08:46.307026 ZQ Calibration : PASS
9060 11:08:46.309964 Jitter Meter : NO K
9061 11:08:46.313447 CBT Training : PASS
9062 11:08:46.314046 Write leveling : PASS
9063 11:08:46.316283 RX DQS gating : PASS
9064 11:08:46.319826 RX DQ/DQS(RDDQC) : PASS
9065 11:08:46.320403 TX DQ/DQS : PASS
9066 11:08:46.323441 RX DATLAT : PASS
9067 11:08:46.326543 RX DQ/DQS(Engine): PASS
9068 11:08:46.327121 TX OE : PASS
9069 11:08:46.327497 All Pass.
9070 11:08:46.329867
9071 11:08:46.330489 CH 1, Rank 0
9072 11:08:46.333093 SW Impedance : PASS
9073 11:08:46.333562 DUTY Scan : NO K
9074 11:08:46.336457 ZQ Calibration : PASS
9075 11:08:46.337018 Jitter Meter : NO K
9076 11:08:46.339849 CBT Training : PASS
9077 11:08:46.342916 Write leveling : PASS
9078 11:08:46.343386 RX DQS gating : PASS
9079 11:08:46.346304 RX DQ/DQS(RDDQC) : PASS
9080 11:08:46.350037 TX DQ/DQS : PASS
9081 11:08:46.350603 RX DATLAT : PASS
9082 11:08:46.352844 RX DQ/DQS(Engine): PASS
9083 11:08:46.356264 TX OE : PASS
9084 11:08:46.356856 All Pass.
9085 11:08:46.357340
9086 11:08:46.357786 CH 1, Rank 1
9087 11:08:46.359390 SW Impedance : PASS
9088 11:08:46.362719 DUTY Scan : NO K
9089 11:08:46.363195 ZQ Calibration : PASS
9090 11:08:46.366002 Jitter Meter : NO K
9091 11:08:46.369446 CBT Training : PASS
9092 11:08:46.369903 Write leveling : PASS
9093 11:08:46.372947 RX DQS gating : PASS
9094 11:08:46.376423 RX DQ/DQS(RDDQC) : PASS
9095 11:08:46.376986 TX DQ/DQS : PASS
9096 11:08:46.379349 RX DATLAT : PASS
9097 11:08:46.382615 RX DQ/DQS(Engine): PASS
9098 11:08:46.383076 TX OE : PASS
9099 11:08:46.383444 All Pass.
9100 11:08:46.386066
9101 11:08:46.386522 DramC Write-DBI on
9102 11:08:46.389367 PER_BANK_REFRESH: Hybrid Mode
9103 11:08:46.389825 TX_TRACKING: ON
9104 11:08:46.399316 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9105 11:08:46.406113 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9106 11:08:46.416107 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9107 11:08:46.419776 [FAST_K] Save calibration result to emmc
9108 11:08:46.422810 sync common calibartion params.
9109 11:08:46.423371 sync cbt_mode0:1, 1:1
9110 11:08:46.426269 dram_init: ddr_geometry: 2
9111 11:08:46.429487 dram_init: ddr_geometry: 2
9112 11:08:46.430097 dram_init: ddr_geometry: 2
9113 11:08:46.432529 0:dram_rank_size:100000000
9114 11:08:46.435723 1:dram_rank_size:100000000
9115 11:08:46.439281 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9116 11:08:46.442539 DFS_SHUFFLE_HW_MODE: ON
9117 11:08:46.446321 dramc_set_vcore_voltage set vcore to 725000
9118 11:08:46.449297 Read voltage for 1600, 0
9119 11:08:46.449862 Vio18 = 0
9120 11:08:46.452447 Vcore = 725000
9121 11:08:46.453099 Vdram = 0
9122 11:08:46.453517 Vddq = 0
9123 11:08:46.453865 Vmddr = 0
9124 11:08:46.455713 switch to 3200 Mbps bootup
9125 11:08:46.458760 [DramcRunTimeConfig]
9126 11:08:46.459221 PHYPLL
9127 11:08:46.462272 DPM_CONTROL_AFTERK: ON
9128 11:08:46.462900 PER_BANK_REFRESH: ON
9129 11:08:46.465809 REFRESH_OVERHEAD_REDUCTION: ON
9130 11:08:46.469149 CMD_PICG_NEW_MODE: OFF
9131 11:08:46.469719 XRTWTW_NEW_MODE: ON
9132 11:08:46.472817 XRTRTR_NEW_MODE: ON
9133 11:08:46.473374 TX_TRACKING: ON
9134 11:08:46.475926 RDSEL_TRACKING: OFF
9135 11:08:46.478896 DQS Precalculation for DVFS: ON
9136 11:08:46.479357 RX_TRACKING: OFF
9137 11:08:46.479721 HW_GATING DBG: ON
9138 11:08:46.482404 ZQCS_ENABLE_LP4: ON
9139 11:08:46.486060 RX_PICG_NEW_MODE: ON
9140 11:08:46.486617 TX_PICG_NEW_MODE: ON
9141 11:08:46.489478 ENABLE_RX_DCM_DPHY: ON
9142 11:08:46.492738 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9143 11:08:46.495939 DUMMY_READ_FOR_TRACKING: OFF
9144 11:08:46.496497 !!! SPM_CONTROL_AFTERK: OFF
9145 11:08:46.499221 !!! SPM could not control APHY
9146 11:08:46.502688 IMPEDANCE_TRACKING: ON
9147 11:08:46.503147 TEMP_SENSOR: ON
9148 11:08:46.506189 HW_SAVE_FOR_SR: OFF
9149 11:08:46.508994 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9150 11:08:46.512378 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9151 11:08:46.512839 Read ODT Tracking: ON
9152 11:08:46.515919 Refresh Rate DeBounce: ON
9153 11:08:46.519606 DFS_NO_QUEUE_FLUSH: ON
9154 11:08:46.522845 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9155 11:08:46.523410 ENABLE_DFS_RUNTIME_MRW: OFF
9156 11:08:46.526057 DDR_RESERVE_NEW_MODE: ON
9157 11:08:46.529412 MR_CBT_SWITCH_FREQ: ON
9158 11:08:46.530018 =========================
9159 11:08:46.549387 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9160 11:08:46.552253 dram_init: ddr_geometry: 2
9161 11:08:46.570421 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9162 11:08:46.574032 dram_init: dram init end (result: 0)
9163 11:08:46.580666 DRAM-K: Full calibration passed in 24534 msecs
9164 11:08:46.583740 MRC: failed to locate region type 0.
9165 11:08:46.584203 DRAM rank0 size:0x100000000,
9166 11:08:46.587334 DRAM rank1 size=0x100000000
9167 11:08:46.597392 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9168 11:08:46.603924 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9169 11:08:46.610282 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9170 11:08:46.617312 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9171 11:08:46.620420 DRAM rank0 size:0x100000000,
9172 11:08:46.623895 DRAM rank1 size=0x100000000
9173 11:08:46.624455 CBMEM:
9174 11:08:46.626636 IMD: root @ 0xfffff000 254 entries.
9175 11:08:46.630606 IMD: root @ 0xffffec00 62 entries.
9176 11:08:46.634064 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9177 11:08:46.637025 WARNING: RO_VPD is uninitialized or empty.
9178 11:08:46.643623 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9179 11:08:46.650622 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9180 11:08:46.663378 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9181 11:08:46.674541 BS: romstage times (exec / console): total (unknown) / 24028 ms
9182 11:08:46.675090
9183 11:08:46.675455
9184 11:08:46.684492 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9185 11:08:46.688258 ARM64: Exception handlers installed.
9186 11:08:46.691582 ARM64: Testing exception
9187 11:08:46.694707 ARM64: Done test exception
9188 11:08:46.695171 Enumerating buses...
9189 11:08:46.698075 Show all devs... Before device enumeration.
9190 11:08:46.701586 Root Device: enabled 1
9191 11:08:46.704498 CPU_CLUSTER: 0: enabled 1
9192 11:08:46.704959 CPU: 00: enabled 1
9193 11:08:46.707972 Compare with tree...
9194 11:08:46.708432 Root Device: enabled 1
9195 11:08:46.711191 CPU_CLUSTER: 0: enabled 1
9196 11:08:46.714738 CPU: 00: enabled 1
9197 11:08:46.715299 Root Device scanning...
9198 11:08:46.718160 scan_static_bus for Root Device
9199 11:08:46.721357 CPU_CLUSTER: 0 enabled
9200 11:08:46.724796 scan_static_bus for Root Device done
9201 11:08:46.728151 scan_bus: bus Root Device finished in 8 msecs
9202 11:08:46.728716 done
9203 11:08:46.734464 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9204 11:08:46.737853 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9205 11:08:46.744710 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9206 11:08:46.747915 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9207 11:08:46.751487 Allocating resources...
9208 11:08:46.754692 Reading resources...
9209 11:08:46.757755 Root Device read_resources bus 0 link: 0
9210 11:08:46.758354 DRAM rank0 size:0x100000000,
9211 11:08:46.761296 DRAM rank1 size=0x100000000
9212 11:08:46.764088 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9213 11:08:46.767667 CPU: 00 missing read_resources
9214 11:08:46.771032 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9215 11:08:46.777293 Root Device read_resources bus 0 link: 0 done
9216 11:08:46.777755 Done reading resources.
9217 11:08:46.784215 Show resources in subtree (Root Device)...After reading.
9218 11:08:46.787564 Root Device child on link 0 CPU_CLUSTER: 0
9219 11:08:46.790579 CPU_CLUSTER: 0 child on link 0 CPU: 00
9220 11:08:46.800993 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9221 11:08:46.801559 CPU: 00
9222 11:08:46.804251 Root Device assign_resources, bus 0 link: 0
9223 11:08:46.807403 CPU_CLUSTER: 0 missing set_resources
9224 11:08:46.810615 Root Device assign_resources, bus 0 link: 0 done
9225 11:08:46.813903 Done setting resources.
9226 11:08:46.820954 Show resources in subtree (Root Device)...After assigning values.
9227 11:08:46.824284 Root Device child on link 0 CPU_CLUSTER: 0
9228 11:08:46.827514 CPU_CLUSTER: 0 child on link 0 CPU: 00
9229 11:08:46.837624 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9230 11:08:46.838240 CPU: 00
9231 11:08:46.840776 Done allocating resources.
9232 11:08:46.844079 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9233 11:08:46.847378 Enabling resources...
9234 11:08:46.847940 done.
9235 11:08:46.854164 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9236 11:08:46.854723 Initializing devices...
9237 11:08:46.857716 Root Device init
9238 11:08:46.858327 init hardware done!
9239 11:08:46.860891 0x00000018: ctrlr->caps
9240 11:08:46.864052 52.000 MHz: ctrlr->f_max
9241 11:08:46.864525 0.400 MHz: ctrlr->f_min
9242 11:08:46.867209 0x40ff8080: ctrlr->voltages
9243 11:08:46.867745 sclk: 390625
9244 11:08:46.870642 Bus Width = 1
9245 11:08:46.871103 sclk: 390625
9246 11:08:46.871507 Bus Width = 1
9247 11:08:46.874048 Early init status = 3
9248 11:08:46.880629 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9249 11:08:46.884342 in-header: 03 fc 00 00 01 00 00 00
9250 11:08:46.884905 in-data: 00
9251 11:08:46.890450 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9252 11:08:46.894384 in-header: 03 fd 00 00 00 00 00 00
9253 11:08:46.897698 in-data:
9254 11:08:46.900952 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9255 11:08:46.905364 in-header: 03 fc 00 00 01 00 00 00
9256 11:08:46.908708 in-data: 00
9257 11:08:46.911980 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9258 11:08:46.917711 in-header: 03 fd 00 00 00 00 00 00
9259 11:08:46.920921 in-data:
9260 11:08:46.924367 [SSUSB] Setting up USB HOST controller...
9261 11:08:46.927772 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9262 11:08:46.930959 [SSUSB] phy power-on done.
9263 11:08:46.934182 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9264 11:08:46.940755 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9265 11:08:46.943961 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9266 11:08:46.950556 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9267 11:08:46.957349 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9268 11:08:46.964094 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9269 11:08:46.970446 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9270 11:08:46.976996 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9271 11:08:46.980084 SPM: binary array size = 0x9dc
9272 11:08:46.983643 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9273 11:08:46.990431 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9274 11:08:46.996993 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9275 11:08:47.003661 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9276 11:08:47.006613 configure_display: Starting display init
9277 11:08:47.040889 anx7625_power_on_init: Init interface.
9278 11:08:47.044742 anx7625_disable_pd_protocol: Disabled PD feature.
9279 11:08:47.047513 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9280 11:08:47.075350 anx7625_start_dp_work: Secure OCM version=00
9281 11:08:47.078616 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9282 11:08:47.096274 sp_tx_get_edid_block: EDID Block = 1
9283 11:08:47.195758 Extracted contents:
9284 11:08:47.199257 header: 00 ff ff ff ff ff ff 00
9285 11:08:47.202492 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9286 11:08:47.205804 version: 01 04
9287 11:08:47.208711 basic params: 95 1f 11 78 0a
9288 11:08:47.212265 chroma info: 76 90 94 55 54 90 27 21 50 54
9289 11:08:47.215631 established: 00 00 00
9290 11:08:47.222023 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9291 11:08:47.225391 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9292 11:08:47.232138 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9293 11:08:47.238878 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9294 11:08:47.245532 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9295 11:08:47.248529 extensions: 00
9296 11:08:47.248984 checksum: fb
9297 11:08:47.249347
9298 11:08:47.252101 Manufacturer: IVO Model 57d Serial Number 0
9299 11:08:47.255234 Made week 0 of 2020
9300 11:08:47.255689 EDID version: 1.4
9301 11:08:47.258664 Digital display
9302 11:08:47.261810 6 bits per primary color channel
9303 11:08:47.262348 DisplayPort interface
9304 11:08:47.265448 Maximum image size: 31 cm x 17 cm
9305 11:08:47.268564 Gamma: 220%
9306 11:08:47.269018 Check DPMS levels
9307 11:08:47.271854 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9308 11:08:47.278629 First detailed timing is preferred timing
9309 11:08:47.279085 Established timings supported:
9310 11:08:47.281801 Standard timings supported:
9311 11:08:47.285240 Detailed timings
9312 11:08:47.288432 Hex of detail: 383680a07038204018303c0035ae10000019
9313 11:08:47.295011 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9314 11:08:47.298356 0780 0798 07c8 0820 hborder 0
9315 11:08:47.301696 0438 043b 0447 0458 vborder 0
9316 11:08:47.305018 -hsync -vsync
9317 11:08:47.305501 Did detailed timing
9318 11:08:47.311795 Hex of detail: 000000000000000000000000000000000000
9319 11:08:47.314771 Manufacturer-specified data, tag 0
9320 11:08:47.318618 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9321 11:08:47.321781 ASCII string: InfoVision
9322 11:08:47.325331 Hex of detail: 000000fe00523134304e574635205248200a
9323 11:08:47.328232 ASCII string: R140NWF5 RH
9324 11:08:47.328699 Checksum
9325 11:08:47.331660 Checksum: 0xfb (valid)
9326 11:08:47.334968 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9327 11:08:47.338154 DSI data_rate: 832800000 bps
9328 11:08:47.345194 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9329 11:08:47.348647 anx7625_parse_edid: pixelclock(138800).
9330 11:08:47.351560 hactive(1920), hsync(48), hfp(24), hbp(88)
9331 11:08:47.354683 vactive(1080), vsync(12), vfp(3), vbp(17)
9332 11:08:47.358235 anx7625_dsi_config: config dsi.
9333 11:08:47.364777 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9334 11:08:47.377986 anx7625_dsi_config: success to config DSI
9335 11:08:47.381520 anx7625_dp_start: MIPI phy setup OK.
9336 11:08:47.384844 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9337 11:08:47.387970 mtk_ddp_mode_set invalid vrefresh 60
9338 11:08:47.391340 main_disp_path_setup
9339 11:08:47.391891 ovl_layer_smi_id_en
9340 11:08:47.394594 ovl_layer_smi_id_en
9341 11:08:47.395050 ccorr_config
9342 11:08:47.395410 aal_config
9343 11:08:47.397751 gamma_config
9344 11:08:47.398254 postmask_config
9345 11:08:47.401124 dither_config
9346 11:08:47.404706 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9347 11:08:47.410970 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9348 11:08:47.414597 Root Device init finished in 554 msecs
9349 11:08:47.417826 CPU_CLUSTER: 0 init
9350 11:08:47.425019 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9351 11:08:47.427741 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9352 11:08:47.430765 APU_MBOX 0x190000b0 = 0x10001
9353 11:08:47.434394 APU_MBOX 0x190001b0 = 0x10001
9354 11:08:47.437639 APU_MBOX 0x190005b0 = 0x10001
9355 11:08:47.441139 APU_MBOX 0x190006b0 = 0x10001
9356 11:08:47.444240 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9357 11:08:47.457173 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9358 11:08:47.469429 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9359 11:08:47.475787 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9360 11:08:47.487501 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9361 11:08:47.496477 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9362 11:08:47.500000 CPU_CLUSTER: 0 init finished in 81 msecs
9363 11:08:47.503055 Devices initialized
9364 11:08:47.506462 Show all devs... After init.
9365 11:08:47.506929 Root Device: enabled 1
9366 11:08:47.509712 CPU_CLUSTER: 0: enabled 1
9367 11:08:47.513121 CPU: 00: enabled 1
9368 11:08:47.516721 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9369 11:08:47.519752 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9370 11:08:47.522978 ELOG: NV offset 0x57f000 size 0x1000
9371 11:08:47.529803 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9372 11:08:47.536452 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9373 11:08:47.539879 ELOG: Event(17) added with size 13 at 2024-03-03 11:08:09 UTC
9374 11:08:47.546044 out: cmd=0x121: 03 db 21 01 00 00 00 00
9375 11:08:47.549652 in-header: 03 12 00 00 2c 00 00 00
9376 11:08:47.559368 in-data: 4d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9377 11:08:47.565975 ELOG: Event(A1) added with size 10 at 2024-03-03 11:08:09 UTC
9378 11:08:47.572561 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9379 11:08:47.579646 ELOG: Event(A0) added with size 9 at 2024-03-03 11:08:09 UTC
9380 11:08:47.582645 elog_add_boot_reason: Logged dev mode boot
9381 11:08:47.589146 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9382 11:08:47.589625 Finalize devices...
9383 11:08:47.592586 Devices finalized
9384 11:08:47.596173 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9385 11:08:47.599540 Writing coreboot table at 0xffe64000
9386 11:08:47.602613 0. 000000000010a000-0000000000113fff: RAMSTAGE
9387 11:08:47.606265 1. 0000000040000000-00000000400fffff: RAM
9388 11:08:47.612708 2. 0000000040100000-000000004032afff: RAMSTAGE
9389 11:08:47.616206 3. 000000004032b000-00000000545fffff: RAM
9390 11:08:47.619500 4. 0000000054600000-000000005465ffff: BL31
9391 11:08:47.622641 5. 0000000054660000-00000000ffe63fff: RAM
9392 11:08:47.629676 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9393 11:08:47.632853 7. 0000000100000000-000000023fffffff: RAM
9394 11:08:47.635897 Passing 5 GPIOs to payload:
9395 11:08:47.639126 NAME | PORT | POLARITY | VALUE
9396 11:08:47.642445 EC in RW | 0x000000aa | low | undefined
9397 11:08:47.649093 EC interrupt | 0x00000005 | low | undefined
9398 11:08:47.652604 TPM interrupt | 0x000000ab | high | undefined
9399 11:08:47.659237 SD card detect | 0x00000011 | high | undefined
9400 11:08:47.662453 speaker enable | 0x00000093 | high | undefined
9401 11:08:47.665855 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9402 11:08:47.669243 in-header: 03 f9 00 00 02 00 00 00
9403 11:08:47.672610 in-data: 02 00
9404 11:08:47.673128 ADC[4]: Raw value=901032 ID=7
9405 11:08:47.675812 ADC[3]: Raw value=213179 ID=1
9406 11:08:47.679050 RAM Code: 0x71
9407 11:08:47.679651 ADC[6]: Raw value=74870 ID=0
9408 11:08:47.682133 ADC[5]: Raw value=212072 ID=1
9409 11:08:47.685403 SKU Code: 0x1
9410 11:08:47.688824 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d51e
9411 11:08:47.692436 coreboot table: 964 bytes.
9412 11:08:47.695754 IMD ROOT 0. 0xfffff000 0x00001000
9413 11:08:47.698821 IMD SMALL 1. 0xffffe000 0x00001000
9414 11:08:47.702091 RO MCACHE 2. 0xffffc000 0x00001104
9415 11:08:47.705618 CONSOLE 3. 0xfff7c000 0x00080000
9416 11:08:47.709023 FMAP 4. 0xfff7b000 0x00000452
9417 11:08:47.712101 TIME STAMP 5. 0xfff7a000 0x00000910
9418 11:08:47.715374 VBOOT WORK 6. 0xfff66000 0x00014000
9419 11:08:47.718790 RAMOOPS 7. 0xffe66000 0x00100000
9420 11:08:47.722122 COREBOOT 8. 0xffe64000 0x00002000
9421 11:08:47.725479 IMD small region:
9422 11:08:47.728765 IMD ROOT 0. 0xffffec00 0x00000400
9423 11:08:47.731943 VPD 1. 0xffffeb80 0x0000006c
9424 11:08:47.735250 MMC STATUS 2. 0xffffeb60 0x00000004
9425 11:08:47.738528 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9426 11:08:47.742441 Probing TPM: done!
9427 11:08:47.745712 Connected to device vid:did:rid of 1ae0:0028:00
9428 11:08:47.755691 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9429 11:08:47.758867 Initialized TPM device CR50 revision 0
9430 11:08:47.762244 Checking cr50 for pending updates
9431 11:08:47.766414 Reading cr50 TPM mode
9432 11:08:47.774718 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9433 11:08:47.781705 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9434 11:08:47.821897 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9435 11:08:47.825204 Checking segment from ROM address 0x40100000
9436 11:08:47.828405 Checking segment from ROM address 0x4010001c
9437 11:08:47.835337 Loading segment from ROM address 0x40100000
9438 11:08:47.835943 code (compression=0)
9439 11:08:47.842157 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9440 11:08:47.851590 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9441 11:08:47.852128 it's not compressed!
9442 11:08:47.858267 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9443 11:08:47.861610 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9444 11:08:47.882098 Loading segment from ROM address 0x4010001c
9445 11:08:47.882652 Entry Point 0x80000000
9446 11:08:47.885568 Loaded segments
9447 11:08:47.888802 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9448 11:08:47.895881 Jumping to boot code at 0x80000000(0xffe64000)
9449 11:08:47.902215 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9450 11:08:47.908776 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9451 11:08:47.916686 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9452 11:08:47.920282 Checking segment from ROM address 0x40100000
9453 11:08:47.923403 Checking segment from ROM address 0x4010001c
9454 11:08:47.930231 Loading segment from ROM address 0x40100000
9455 11:08:47.930808 code (compression=1)
9456 11:08:47.936572 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9457 11:08:47.946699 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9458 11:08:47.947281 using LZMA
9459 11:08:47.955148 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9460 11:08:47.961861 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9461 11:08:47.965100 Loading segment from ROM address 0x4010001c
9462 11:08:47.965576 Entry Point 0x54601000
9463 11:08:47.968548 Loaded segments
9464 11:08:47.971733 NOTICE: MT8192 bl31_setup
9465 11:08:47.978430 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9466 11:08:47.981849 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9467 11:08:47.984796 WARNING: region 0:
9468 11:08:47.988241 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 11:08:47.988755 WARNING: region 1:
9470 11:08:47.995304 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9471 11:08:47.998580 WARNING: region 2:
9472 11:08:48.001756 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9473 11:08:48.005042 WARNING: region 3:
9474 11:08:48.008174 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9475 11:08:48.012154 WARNING: region 4:
9476 11:08:48.018330 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9477 11:08:48.018984 WARNING: region 5:
9478 11:08:48.021616 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 11:08:48.025028 WARNING: region 6:
9480 11:08:48.028497 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 11:08:48.031665 WARNING: region 7:
9482 11:08:48.035029 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 11:08:48.041688 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9484 11:08:48.045158 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9485 11:08:48.048562 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9486 11:08:48.055337 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9487 11:08:48.058843 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9488 11:08:48.061641 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9489 11:08:48.068804 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9490 11:08:48.072054 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9491 11:08:48.078717 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9492 11:08:48.081820 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9493 11:08:48.084977 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9494 11:08:48.091646 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9495 11:08:48.095196 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9496 11:08:48.098407 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9497 11:08:48.104948 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9498 11:08:48.108529 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9499 11:08:48.115217 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9500 11:08:48.118867 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9501 11:08:48.121452 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9502 11:08:48.128646 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9503 11:08:48.131798 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9504 11:08:48.135719 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9505 11:08:48.142144 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9506 11:08:48.145507 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9507 11:08:48.151693 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9508 11:08:48.155235 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9509 11:08:48.158523 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9510 11:08:48.165407 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9511 11:08:48.168695 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9512 11:08:48.175326 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9513 11:08:48.178522 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9514 11:08:48.181864 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9515 11:08:48.188485 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9516 11:08:48.191820 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9517 11:08:48.194984 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9518 11:08:48.198708 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9519 11:08:48.205109 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9520 11:08:48.208088 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9521 11:08:48.211733 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9522 11:08:48.215455 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9523 11:08:48.222028 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9524 11:08:48.225257 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9525 11:08:48.228679 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9526 11:08:48.231650 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9527 11:08:48.238814 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9528 11:08:48.242251 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9529 11:08:48.245498 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9530 11:08:48.248868 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9531 11:08:48.255103 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9532 11:08:48.258548 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9533 11:08:48.265448 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9534 11:08:48.268718 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9535 11:08:48.272074 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9536 11:08:48.278426 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9537 11:08:48.282157 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9538 11:08:48.288534 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9539 11:08:48.291581 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9540 11:08:48.298556 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9541 11:08:48.302092 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9542 11:08:48.305618 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9543 11:08:48.311504 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9544 11:08:48.315064 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9545 11:08:48.322010 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9546 11:08:48.325206 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9547 11:08:48.331813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9548 11:08:48.334953 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9549 11:08:48.342168 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9550 11:08:48.345495 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9551 11:08:48.348779 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9552 11:08:48.355231 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9553 11:08:48.358453 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9554 11:08:48.365462 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9555 11:08:48.368805 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9556 11:08:48.372037 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9557 11:08:48.378444 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9558 11:08:48.381886 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9559 11:08:48.388229 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9560 11:08:48.392062 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9561 11:08:48.398738 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9562 11:08:48.401804 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9563 11:08:48.408494 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9564 11:08:48.411829 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9565 11:08:48.414935 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9566 11:08:48.421886 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9567 11:08:48.425051 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9568 11:08:48.431601 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9569 11:08:48.435083 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9570 11:08:48.441491 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9571 11:08:48.445405 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9572 11:08:48.448743 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9573 11:08:48.455152 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9574 11:08:48.458344 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9575 11:08:48.465292 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9576 11:08:48.468275 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9577 11:08:48.475332 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9578 11:08:48.478379 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9579 11:08:48.482067 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9580 11:08:48.488568 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9581 11:08:48.492284 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9582 11:08:48.495075 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9583 11:08:48.498810 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9584 11:08:48.505573 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9585 11:08:48.508673 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9586 11:08:48.515097 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9587 11:08:48.518382 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9588 11:08:48.521843 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9589 11:08:48.528530 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9590 11:08:48.531427 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9591 11:08:48.535160 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9592 11:08:48.541700 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9593 11:08:48.545610 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9594 11:08:48.552054 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9595 11:08:48.555309 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9596 11:08:48.558521 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9597 11:08:48.565560 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9598 11:08:48.568928 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9599 11:08:48.571837 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9600 11:08:48.578782 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9601 11:08:48.582273 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9602 11:08:48.585283 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9603 11:08:48.592084 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9604 11:08:48.595428 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9605 11:08:48.598746 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9606 11:08:48.601999 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9607 11:08:48.608464 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9608 11:08:48.611932 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9609 11:08:48.615210 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9610 11:08:48.622186 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9611 11:08:48.625036 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9612 11:08:48.631838 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9613 11:08:48.635268 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9614 11:08:48.638398 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9615 11:08:48.645134 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9616 11:08:48.648363 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9617 11:08:48.655025 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9618 11:08:48.658771 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9619 11:08:48.661698 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9620 11:08:48.668371 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9621 11:08:48.671835 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9622 11:08:48.675203 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9623 11:08:48.681910 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9624 11:08:48.684987 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9625 11:08:48.691915 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9626 11:08:48.695273 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9627 11:08:48.698668 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9628 11:08:48.705037 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9629 11:08:48.708788 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9630 11:08:48.714886 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9631 11:08:48.718551 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9632 11:08:48.722086 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9633 11:08:48.728787 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9634 11:08:48.731846 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9635 11:08:48.735238 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9636 11:08:48.741778 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9637 11:08:48.745305 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9638 11:08:48.751724 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9639 11:08:48.755161 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9640 11:08:48.758296 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9641 11:08:48.765561 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9642 11:08:48.768981 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9643 11:08:48.775378 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9644 11:08:48.778717 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9645 11:08:48.782046 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9646 11:08:48.788496 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9647 11:08:48.791919 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9648 11:08:48.795420 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9649 11:08:48.801786 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9650 11:08:48.805140 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9651 11:08:48.811544 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9652 11:08:48.815165 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9653 11:08:48.818356 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9654 11:08:48.825068 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9655 11:08:48.828500 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9656 11:08:48.834962 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9657 11:08:48.838075 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9658 11:08:48.841708 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9659 11:08:48.847967 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9660 11:08:48.851511 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9661 11:08:48.858479 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9662 11:08:48.861491 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9663 11:08:48.864705 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9664 11:08:48.871599 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9665 11:08:48.874892 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9666 11:08:48.881511 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9667 11:08:48.884383 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9668 11:08:48.887938 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9669 11:08:48.894838 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9670 11:08:48.898191 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9671 11:08:48.904835 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9672 11:08:48.908005 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9673 11:08:48.911312 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9674 11:08:48.918099 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9675 11:08:48.921300 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9676 11:08:48.927986 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9677 11:08:48.931338 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9678 11:08:48.934687 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9679 11:08:48.941348 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9680 11:08:48.944624 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9681 11:08:48.951133 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9682 11:08:48.954548 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9683 11:08:48.961211 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9684 11:08:48.964354 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9685 11:08:48.967692 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9686 11:08:48.974138 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9687 11:08:48.977413 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9688 11:08:48.983994 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9689 11:08:48.987182 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9690 11:08:48.990929 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9691 11:08:48.997747 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9692 11:08:49.001081 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9693 11:08:49.007687 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9694 11:08:49.010704 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9695 11:08:49.017729 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9696 11:08:49.020569 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9697 11:08:49.024059 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9698 11:08:49.030409 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9699 11:08:49.033680 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9700 11:08:49.040084 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9701 11:08:49.043977 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9702 11:08:49.050239 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9703 11:08:49.053615 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9704 11:08:49.057143 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9705 11:08:49.063836 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9706 11:08:49.067110 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9707 11:08:49.073554 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9708 11:08:49.076922 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9709 11:08:49.080334 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9710 11:08:49.086714 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9711 11:08:49.090297 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9712 11:08:49.093827 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9713 11:08:49.100584 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9714 11:08:49.103803 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9715 11:08:49.107015 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9716 11:08:49.110460 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9717 11:08:49.117083 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9718 11:08:49.120160 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9719 11:08:49.126796 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9720 11:08:49.130125 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9721 11:08:49.133312 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9722 11:08:49.140139 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9723 11:08:49.143447 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9724 11:08:49.146791 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9725 11:08:49.153347 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9726 11:08:49.156798 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9727 11:08:49.159805 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9728 11:08:49.166511 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9729 11:08:49.169692 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9730 11:08:49.176563 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9731 11:08:49.179441 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9732 11:08:49.183039 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9733 11:08:49.189571 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9734 11:08:49.192708 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9735 11:08:49.199559 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9736 11:08:49.203253 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9737 11:08:49.206441 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9738 11:08:49.213219 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9739 11:08:49.216538 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9740 11:08:49.219570 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9741 11:08:49.226458 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9742 11:08:49.229771 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9743 11:08:49.233022 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9744 11:08:49.239424 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9745 11:08:49.242455 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9746 11:08:49.246113 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9747 11:08:49.252853 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9748 11:08:49.256148 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9749 11:08:49.262696 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9750 11:08:49.265747 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9751 11:08:49.269031 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9752 11:08:49.272513 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9753 11:08:49.279145 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9754 11:08:49.282111 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9755 11:08:49.285995 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9756 11:08:49.288794 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9757 11:08:49.295487 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9758 11:08:49.299177 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9759 11:08:49.302530 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9760 11:08:49.305886 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9761 11:08:49.312463 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9762 11:08:49.315637 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9763 11:08:49.319005 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9764 11:08:49.322150 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9765 11:08:49.328811 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9766 11:08:49.331881 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9767 11:08:49.338822 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9768 11:08:49.342172 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9769 11:08:49.348606 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9770 11:08:49.352356 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9771 11:08:49.355655 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9772 11:08:49.362219 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9773 11:08:49.365595 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9774 11:08:49.371911 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9775 11:08:49.375260 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9776 11:08:49.378509 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9777 11:08:49.385368 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9778 11:08:49.388381 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9779 11:08:49.395441 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9780 11:08:49.398441 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9781 11:08:49.402126 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9782 11:08:49.408697 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9783 11:08:49.412270 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9784 11:08:49.418826 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9785 11:08:49.422258 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9786 11:08:49.425610 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9787 11:08:49.432021 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9788 11:08:49.435382 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9789 11:08:49.441927 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9790 11:08:49.445219 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9791 11:08:49.448417 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9792 11:08:49.455301 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9793 11:08:49.458739 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9794 11:08:49.465013 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9795 11:08:49.468586 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9796 11:08:49.472314 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9797 11:08:49.478596 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9798 11:08:49.481801 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9799 11:08:49.488354 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9800 11:08:49.492024 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9801 11:08:49.498148 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9802 11:08:49.501582 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9803 11:08:49.504940 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9804 11:08:49.511659 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9805 11:08:49.514548 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9806 11:08:49.521796 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9807 11:08:49.525237 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9808 11:08:49.528445 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9809 11:08:49.535061 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9810 11:08:49.538351 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9811 11:08:49.544707 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9812 11:08:49.548091 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9813 11:08:49.551324 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9814 11:08:49.557999 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9815 11:08:49.561186 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9816 11:08:49.568076 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9817 11:08:49.571260 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9818 11:08:49.578051 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9819 11:08:49.581247 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9820 11:08:49.584353 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9821 11:08:49.591263 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9822 11:08:49.594539 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9823 11:08:49.601174 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9824 11:08:49.604713 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9825 11:08:49.607641 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9826 11:08:49.614349 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9827 11:08:49.617427 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9828 11:08:49.624431 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9829 11:08:49.627634 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9830 11:08:49.631097 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9831 11:08:49.637554 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9832 11:08:49.641215 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9833 11:08:49.647619 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9834 11:08:49.650610 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9835 11:08:49.657483 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9836 11:08:49.660406 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9837 11:08:49.664364 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9838 11:08:49.670681 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9839 11:08:49.674216 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9840 11:08:49.680800 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9841 11:08:49.683798 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9842 11:08:49.690624 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9843 11:08:49.693928 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9844 11:08:49.696958 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9845 11:08:49.703745 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9846 11:08:49.707283 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9847 11:08:49.713556 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9848 11:08:49.717103 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9849 11:08:49.724092 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9850 11:08:49.727186 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9851 11:08:49.733745 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9852 11:08:49.736681 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9853 11:08:49.740505 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9854 11:08:49.747337 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9855 11:08:49.750618 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9856 11:08:49.757250 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9857 11:08:49.760312 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9858 11:08:49.766739 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9859 11:08:49.769978 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9860 11:08:49.773500 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9861 11:08:49.780079 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9862 11:08:49.783738 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9863 11:08:49.790306 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9864 11:08:49.793671 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9865 11:08:49.800219 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9866 11:08:49.803442 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9867 11:08:49.810075 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9868 11:08:49.813110 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9869 11:08:49.816350 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9870 11:08:49.823144 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9871 11:08:49.826465 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9872 11:08:49.833199 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9873 11:08:49.836527 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9874 11:08:49.843172 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9875 11:08:49.846866 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9876 11:08:49.849621 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9877 11:08:49.856359 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9878 11:08:49.859970 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9879 11:08:49.866316 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9880 11:08:49.869852 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9881 11:08:49.876519 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9882 11:08:49.879666 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9883 11:08:49.886011 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9884 11:08:49.889239 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9885 11:08:49.892777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9886 11:08:49.899784 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9887 11:08:49.903149 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9888 11:08:49.909353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9889 11:08:49.912931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9890 11:08:49.915919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9891 11:08:49.922540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9892 11:08:49.926186 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9893 11:08:49.932517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9894 11:08:49.936026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9895 11:08:49.942633 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9896 11:08:49.945597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9897 11:08:49.952481 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9898 11:08:49.955656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9899 11:08:49.962269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9900 11:08:49.966040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9901 11:08:49.972524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9902 11:08:49.975420 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9903 11:08:49.982372 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9904 11:08:49.985241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9905 11:08:49.992047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9906 11:08:49.995237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9907 11:08:50.002084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9908 11:08:50.005362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9909 11:08:50.012340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9910 11:08:50.015325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9911 11:08:50.021832 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9912 11:08:50.025240 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9913 11:08:50.031936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9914 11:08:50.035417 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9915 11:08:50.041830 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9916 11:08:50.045249 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9917 11:08:50.051830 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9918 11:08:50.052386 INFO: [APUAPC] vio 0
9919 11:08:50.058126 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9920 11:08:50.061799 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9921 11:08:50.065215 INFO: [APUAPC] D0_APC_0: 0x400510
9922 11:08:50.068309 INFO: [APUAPC] D0_APC_1: 0x0
9923 11:08:50.071974 INFO: [APUAPC] D0_APC_2: 0x1540
9924 11:08:50.075179 INFO: [APUAPC] D0_APC_3: 0x0
9925 11:08:50.078456 INFO: [APUAPC] D1_APC_0: 0xffffffff
9926 11:08:50.081448 INFO: [APUAPC] D1_APC_1: 0xffffffff
9927 11:08:50.084771 INFO: [APUAPC] D1_APC_2: 0x3fffff
9928 11:08:50.088274 INFO: [APUAPC] D1_APC_3: 0x0
9929 11:08:50.091878 INFO: [APUAPC] D2_APC_0: 0xffffffff
9930 11:08:50.094949 INFO: [APUAPC] D2_APC_1: 0xffffffff
9931 11:08:50.098589 INFO: [APUAPC] D2_APC_2: 0x3fffff
9932 11:08:50.101828 INFO: [APUAPC] D2_APC_3: 0x0
9933 11:08:50.105111 INFO: [APUAPC] D3_APC_0: 0xffffffff
9934 11:08:50.108421 INFO: [APUAPC] D3_APC_1: 0xffffffff
9935 11:08:50.111746 INFO: [APUAPC] D3_APC_2: 0x3fffff
9936 11:08:50.115012 INFO: [APUAPC] D3_APC_3: 0x0
9937 11:08:50.118451 INFO: [APUAPC] D4_APC_0: 0xffffffff
9938 11:08:50.121715 INFO: [APUAPC] D4_APC_1: 0xffffffff
9939 11:08:50.125262 INFO: [APUAPC] D4_APC_2: 0x3fffff
9940 11:08:50.125825 INFO: [APUAPC] D4_APC_3: 0x0
9941 11:08:50.128474 INFO: [APUAPC] D5_APC_0: 0xffffffff
9942 11:08:50.135081 INFO: [APUAPC] D5_APC_1: 0xffffffff
9943 11:08:50.135646 INFO: [APUAPC] D5_APC_2: 0x3fffff
9944 11:08:50.138173 INFO: [APUAPC] D5_APC_3: 0x0
9945 11:08:50.141677 INFO: [APUAPC] D6_APC_0: 0xffffffff
9946 11:08:50.144852 INFO: [APUAPC] D6_APC_1: 0xffffffff
9947 11:08:50.148119 INFO: [APUAPC] D6_APC_2: 0x3fffff
9948 11:08:50.151686 INFO: [APUAPC] D6_APC_3: 0x0
9949 11:08:50.154733 INFO: [APUAPC] D7_APC_0: 0xffffffff
9950 11:08:50.158065 INFO: [APUAPC] D7_APC_1: 0xffffffff
9951 11:08:50.161484 INFO: [APUAPC] D7_APC_2: 0x3fffff
9952 11:08:50.164890 INFO: [APUAPC] D7_APC_3: 0x0
9953 11:08:50.168306 INFO: [APUAPC] D8_APC_0: 0xffffffff
9954 11:08:50.171405 INFO: [APUAPC] D8_APC_1: 0xffffffff
9955 11:08:50.174506 INFO: [APUAPC] D8_APC_2: 0x3fffff
9956 11:08:50.178294 INFO: [APUAPC] D8_APC_3: 0x0
9957 11:08:50.181572 INFO: [APUAPC] D9_APC_0: 0xffffffff
9958 11:08:50.184532 INFO: [APUAPC] D9_APC_1: 0xffffffff
9959 11:08:50.187668 INFO: [APUAPC] D9_APC_2: 0x3fffff
9960 11:08:50.191154 INFO: [APUAPC] D9_APC_3: 0x0
9961 11:08:50.194492 INFO: [APUAPC] D10_APC_0: 0xffffffff
9962 11:08:50.197799 INFO: [APUAPC] D10_APC_1: 0xffffffff
9963 11:08:50.201206 INFO: [APUAPC] D10_APC_2: 0x3fffff
9964 11:08:50.204383 INFO: [APUAPC] D10_APC_3: 0x0
9965 11:08:50.207845 INFO: [APUAPC] D11_APC_0: 0xffffffff
9966 11:08:50.211182 INFO: [APUAPC] D11_APC_1: 0xffffffff
9967 11:08:50.214374 INFO: [APUAPC] D11_APC_2: 0x3fffff
9968 11:08:50.217539 INFO: [APUAPC] D11_APC_3: 0x0
9969 11:08:50.220785 INFO: [APUAPC] D12_APC_0: 0xffffffff
9970 11:08:50.224344 INFO: [APUAPC] D12_APC_1: 0xffffffff
9971 11:08:50.227517 INFO: [APUAPC] D12_APC_2: 0x3fffff
9972 11:08:50.231084 INFO: [APUAPC] D12_APC_3: 0x0
9973 11:08:50.234314 INFO: [APUAPC] D13_APC_0: 0xffffffff
9974 11:08:50.237713 INFO: [APUAPC] D13_APC_1: 0xffffffff
9975 11:08:50.240870 INFO: [APUAPC] D13_APC_2: 0x3fffff
9976 11:08:50.244055 INFO: [APUAPC] D13_APC_3: 0x0
9977 11:08:50.247385 INFO: [APUAPC] D14_APC_0: 0xffffffff
9978 11:08:50.250594 INFO: [APUAPC] D14_APC_1: 0xffffffff
9979 11:08:50.254098 INFO: [APUAPC] D14_APC_2: 0x3fffff
9980 11:08:50.257111 INFO: [APUAPC] D14_APC_3: 0x0
9981 11:08:50.260694 INFO: [APUAPC] D15_APC_0: 0xffffffff
9982 11:08:50.263759 INFO: [APUAPC] D15_APC_1: 0xffffffff
9983 11:08:50.267054 INFO: [APUAPC] D15_APC_2: 0x3fffff
9984 11:08:50.270760 INFO: [APUAPC] D15_APC_3: 0x0
9985 11:08:50.273782 INFO: [APUAPC] APC_CON: 0x4
9986 11:08:50.277052 INFO: [NOCDAPC] D0_APC_0: 0x0
9987 11:08:50.280550 INFO: [NOCDAPC] D0_APC_1: 0x0
9988 11:08:50.283767 INFO: [NOCDAPC] D1_APC_0: 0x0
9989 11:08:50.286878 INFO: [NOCDAPC] D1_APC_1: 0xfff
9990 11:08:50.290443 INFO: [NOCDAPC] D2_APC_0: 0x0
9991 11:08:50.293622 INFO: [NOCDAPC] D2_APC_1: 0xfff
9992 11:08:50.294241 INFO: [NOCDAPC] D3_APC_0: 0x0
9993 11:08:50.297149 INFO: [NOCDAPC] D3_APC_1: 0xfff
9994 11:08:50.300489 INFO: [NOCDAPC] D4_APC_0: 0x0
9995 11:08:50.303720 INFO: [NOCDAPC] D4_APC_1: 0xfff
9996 11:08:50.307140 INFO: [NOCDAPC] D5_APC_0: 0x0
9997 11:08:50.310409 INFO: [NOCDAPC] D5_APC_1: 0xfff
9998 11:08:50.313801 INFO: [NOCDAPC] D6_APC_0: 0x0
9999 11:08:50.317145 INFO: [NOCDAPC] D6_APC_1: 0xfff
10000 11:08:50.320152 INFO: [NOCDAPC] D7_APC_0: 0x0
10001 11:08:50.323652 INFO: [NOCDAPC] D7_APC_1: 0xfff
10002 11:08:50.326927 INFO: [NOCDAPC] D8_APC_0: 0x0
10003 11:08:50.327510 INFO: [NOCDAPC] D8_APC_1: 0xfff
10004 11:08:50.330243 INFO: [NOCDAPC] D9_APC_0: 0x0
10005 11:08:50.333505 INFO: [NOCDAPC] D9_APC_1: 0xfff
10006 11:08:50.337026 INFO: [NOCDAPC] D10_APC_0: 0x0
10007 11:08:50.340315 INFO: [NOCDAPC] D10_APC_1: 0xfff
10008 11:08:50.343595 INFO: [NOCDAPC] D11_APC_0: 0x0
10009 11:08:50.346881 INFO: [NOCDAPC] D11_APC_1: 0xfff
10010 11:08:50.350250 INFO: [NOCDAPC] D12_APC_0: 0x0
10011 11:08:50.353427 INFO: [NOCDAPC] D12_APC_1: 0xfff
10012 11:08:50.356860 INFO: [NOCDAPC] D13_APC_0: 0x0
10013 11:08:50.360468 INFO: [NOCDAPC] D13_APC_1: 0xfff
10014 11:08:50.363254 INFO: [NOCDAPC] D14_APC_0: 0x0
10015 11:08:50.366867 INFO: [NOCDAPC] D14_APC_1: 0xfff
10016 11:08:50.370165 INFO: [NOCDAPC] D15_APC_0: 0x0
10017 11:08:50.373480 INFO: [NOCDAPC] D15_APC_1: 0xfff
10018 11:08:50.374106 INFO: [NOCDAPC] APC_CON: 0x4
10019 11:08:50.376599 INFO: [APUAPC] set_apusys_apc done
10020 11:08:50.379842 INFO: [DEVAPC] devapc_init done
10021 11:08:50.386457 INFO: GICv3 without legacy support detected.
10022 11:08:50.389634 INFO: ARM GICv3 driver initialized in EL3
10023 11:08:50.393056 INFO: Maximum SPI INTID supported: 639
10024 11:08:50.396357 INFO: BL31: Initializing runtime services
10025 11:08:50.403228 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10026 11:08:50.406361 INFO: SPM: enable CPC mode
10027 11:08:50.409777 INFO: mcdi ready for mcusys-off-idle and system suspend
10028 11:08:50.416027 INFO: BL31: Preparing for EL3 exit to normal world
10029 11:08:50.419700 INFO: Entry point address = 0x80000000
10030 11:08:50.420276 INFO: SPSR = 0x8
10031 11:08:50.426857
10032 11:08:50.427429
10033 11:08:50.427914
10034 11:08:50.429863 Starting depthcharge on Spherion...
10035 11:08:50.430381
10036 11:08:50.430858 Wipe memory regions:
10037 11:08:50.431306
10038 11:08:50.434811 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10039 11:08:50.435575 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10040 11:08:50.436093 Setting prompt string to ['asurada:']
10041 11:08:50.436619 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10042 11:08:50.437602 [0x00000040000000, 0x00000054600000)
10043 11:08:50.555579
10044 11:08:50.556157 [0x00000054660000, 0x00000080000000)
10045 11:08:50.816183
10046 11:08:50.816776 [0x000000821a7280, 0x000000ffe64000)
10047 11:08:51.560546
10048 11:08:51.561064 [0x00000100000000, 0x00000240000000)
10049 11:08:53.450491
10050 11:08:53.453759 Initializing XHCI USB controller at 0x11200000.
10051 11:08:54.492751
10052 11:08:54.496086 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10053 11:08:54.496579
10054 11:08:54.496955
10055 11:08:54.497405
10056 11:08:54.498215 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10058 11:08:54.599297 asurada: tftpboot 192.168.201.1 12925657/tftp-deploy-8ly4v_t3/kernel/image.itb 12925657/tftp-deploy-8ly4v_t3/kernel/cmdline
10059 11:08:54.599827 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10060 11:08:54.600238 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10061 11:08:54.604427 tftpboot 192.168.201.1 12925657/tftp-deploy-8ly4v_t3/kernel/image.itp-deploy-8ly4v_t3/kernel/cmdline
10062 11:08:54.604862
10063 11:08:54.605200 Waiting for link
10064 11:08:54.764877
10065 11:08:54.765377 R8152: Initializing
10066 11:08:54.765726
10067 11:08:54.768156 Version 9 (ocp_data = 6010)
10068 11:08:54.768579
10069 11:08:54.771400 R8152: Done initializing
10070 11:08:54.771823
10071 11:08:54.772160 Adding net device
10072 11:08:56.640667
10073 11:08:56.641187 done.
10074 11:08:56.641854
10075 11:08:56.642670 MAC: 00:e0:4c:72:2d:d6
10076 11:08:56.643427
10077 11:08:56.644092 Sending DHCP discover... done.
10078 11:08:56.644504
10079 11:08:56.647076 Waiting for reply... done.
10080 11:08:56.647596
10081 11:08:56.650602 Sending DHCP request... done.
10082 11:08:56.651160
10083 11:08:56.656596 Waiting for reply... done.
10084 11:08:56.657067
10085 11:08:56.657442 My ip is 192.168.201.21
10086 11:08:56.657792
10087 11:08:56.660107 The DHCP server ip is 192.168.201.1
10088 11:08:56.660683
10089 11:08:56.666291 TFTP server IP predefined by user: 192.168.201.1
10090 11:08:56.666852
10091 11:08:56.672937 Bootfile predefined by user: 12925657/tftp-deploy-8ly4v_t3/kernel/image.itb
10092 11:08:56.673414
10093 11:08:56.675877 Sending tftp read request... done.
10094 11:08:56.676346
10095 11:08:56.681122 Waiting for the transfer...
10096 11:08:56.681590
10097 11:08:57.024238 00000000 ################################################################
10098 11:08:57.024377
10099 11:08:57.291983 00080000 ################################################################
10100 11:08:57.292112
10101 11:08:57.574556 00100000 ################################################################
10102 11:08:57.574693
10103 11:08:57.842656 00180000 ################################################################
10104 11:08:57.842794
10105 11:08:58.103263 00200000 ################################################################
10106 11:08:58.103398
10107 11:08:58.406045 00280000 ################################################################
10108 11:08:58.406202
10109 11:08:58.758192 00300000 ################################################################
10110 11:08:58.758333
10111 11:08:59.097913 00380000 ################################################################
10112 11:08:59.098062
10113 11:08:59.420148 00400000 ################################################################
10114 11:08:59.420319
10115 11:08:59.702617 00480000 ################################################################
10116 11:08:59.702755
10117 11:09:00.003390 00500000 ################################################################
10118 11:09:00.003546
10119 11:09:00.293042 00580000 ################################################################
10120 11:09:00.293171
10121 11:09:00.572932 00600000 ################################################################
10122 11:09:00.573070
10123 11:09:00.850950 00680000 ################################################################
10124 11:09:00.851095
10125 11:09:01.134777 00700000 ################################################################
10126 11:09:01.134905
10127 11:09:01.386152 00780000 ################################################################
10128 11:09:01.386280
10129 11:09:01.651480 00800000 ################################################################
10130 11:09:01.651628
10131 11:09:01.937363 00880000 ################################################################
10132 11:09:01.937502
10133 11:09:02.210501 00900000 ################################################################
10134 11:09:02.210626
10135 11:09:02.473608 00980000 ################################################################
10136 11:09:02.473751
10137 11:09:02.747919 00a00000 ################################################################
10138 11:09:02.748054
10139 11:09:03.023388 00a80000 ################################################################
10140 11:09:03.023531
10141 11:09:03.275142 00b00000 ################################################################
10142 11:09:03.275274
10143 11:09:03.534798 00b80000 ################################################################
10144 11:09:03.534966
10145 11:09:03.784242 00c00000 ################################################################
10146 11:09:03.784371
10147 11:09:04.033383 00c80000 ################################################################
10148 11:09:04.033521
10149 11:09:04.310675 00d00000 ################################################################
10150 11:09:04.310806
10151 11:09:04.579769 00d80000 ################################################################
10152 11:09:04.579907
10153 11:09:04.829651 00e00000 ################################################################
10154 11:09:04.829774
10155 11:09:05.132425 00e80000 ################################################################
10156 11:09:05.132576
10157 11:09:05.390242 00f00000 ################################################################
10158 11:09:05.390383
10159 11:09:05.650837 00f80000 ################################################################
10160 11:09:05.650979
10161 11:09:05.914775 01000000 ################################################################
10162 11:09:05.914904
10163 11:09:06.174684 01080000 ################################################################
10164 11:09:06.174814
10165 11:09:06.460902 01100000 ################################################################
10166 11:09:06.461037
10167 11:09:06.716298 01180000 ################################################################
10168 11:09:06.716447
10169 11:09:06.972829 01200000 ################################################################
10170 11:09:06.972971
10171 11:09:07.250899 01280000 ################################################################
10172 11:09:07.251045
10173 11:09:07.546777 01300000 ################################################################
10174 11:09:07.546921
10175 11:09:07.883626 01380000 ################################################################
10176 11:09:07.883781
10177 11:09:08.194888 01400000 ################################################################
10178 11:09:08.195040
10179 11:09:08.500833 01480000 ################################################################
10180 11:09:08.501005
10181 11:09:08.783099 01500000 ################################################################
10182 11:09:08.783272
10183 11:09:09.047187 01580000 ################################################################
10184 11:09:09.047355
10185 11:09:09.314940 01600000 ################################################################
10186 11:09:09.315103
10187 11:09:09.594360 01680000 ################################################################
10188 11:09:09.594529
10189 11:09:09.896719 01700000 ################################################################
10190 11:09:09.896863
10191 11:09:10.190189 01780000 ################################################################
10192 11:09:10.190345
10193 11:09:10.454308 01800000 ################################################################
10194 11:09:10.454462
10195 11:09:10.712252 01880000 ################################################################
10196 11:09:10.712383
10197 11:09:10.977996 01900000 ################################################################
10198 11:09:10.978129
10199 11:09:11.241044 01980000 ################################################################
10200 11:09:11.241177
10201 11:09:11.505591 01a00000 ################################################################
10202 11:09:11.505723
10203 11:09:11.753376 01a80000 ################################################################
10204 11:09:11.753510
10205 11:09:12.002826 01b00000 ################################################################
10206 11:09:12.002951
10207 11:09:12.276389 01b80000 ################################################################
10208 11:09:12.276528
10209 11:09:12.543804 01c00000 ################################################################
10210 11:09:12.543944
10211 11:09:12.825834 01c80000 ################################################################
10212 11:09:12.826015
10213 11:09:13.105565 01d00000 ################################################################
10214 11:09:13.105708
10215 11:09:13.498665 01d80000 ################################################################
10216 11:09:13.498795
10217 11:09:13.762616 01e00000 ################################################################
10218 11:09:13.762757
10219 11:09:14.062729 01e80000 ################################################################
10220 11:09:14.062893
10221 11:09:14.368710 01f00000 ################################################################
10222 11:09:14.368864
10223 11:09:14.666203 01f80000 ################################################################
10224 11:09:14.666354
10225 11:09:14.983389 02000000 ################################################################
10226 11:09:14.983538
10227 11:09:15.278079 02080000 ################################################################
10228 11:09:15.278221
10229 11:09:15.565985 02100000 ################################################################
10230 11:09:15.566116
10231 11:09:15.857896 02180000 ################################################################
10232 11:09:15.858073
10233 11:09:16.155252 02200000 ################################################################
10234 11:09:16.155685
10235 11:09:16.539459 02280000 ################################################################
10236 11:09:16.539960
10237 11:09:16.933313 02300000 ################################################################
10238 11:09:16.933838
10239 11:09:17.312754 02380000 ################################################################
10240 11:09:17.313256
10241 11:09:17.638948 02400000 ################################################################
10242 11:09:17.639081
10243 11:09:17.928985 02480000 ################################################################
10244 11:09:17.929123
10245 11:09:18.216710 02500000 ################################################################
10246 11:09:18.216880
10247 11:09:18.540761 02580000 ################################################################
10248 11:09:18.541249
10249 11:09:18.933253 02600000 ################################################################
10250 11:09:18.933765
10251 11:09:19.243615 02680000 ################################################################
10252 11:09:19.243753
10253 11:09:19.541762 02700000 ################################################################
10254 11:09:19.541924
10255 11:09:19.832742 02780000 ################################################################
10256 11:09:19.832867
10257 11:09:20.116494 02800000 ################################################################
10258 11:09:20.116632
10259 11:09:20.414635 02880000 ################################################################
10260 11:09:20.414762
10261 11:09:20.715876 02900000 ################################################################
10262 11:09:20.716030
10263 11:09:21.013444 02980000 ################################################################
10264 11:09:21.013595
10265 11:09:21.312132 02a00000 ################################################################
10266 11:09:21.312305
10267 11:09:21.592575 02a80000 ################################################################
10268 11:09:21.592721
10269 11:09:21.883338 02b00000 ################################################################
10270 11:09:21.883476
10271 11:09:22.156182 02b80000 ################################################################
10272 11:09:22.156318
10273 11:09:22.405477 02c00000 ################################################################
10274 11:09:22.405599
10275 11:09:22.664742 02c80000 ################################################################
10276 11:09:22.664869
10277 11:09:22.938158 02d00000 ################################################################
10278 11:09:22.938288
10279 11:09:23.229706 02d80000 ################################################################
10280 11:09:23.229842
10281 11:09:23.522480 02e00000 ################################################################
10282 11:09:23.522616
10283 11:09:23.787926 02e80000 ################################################################
10284 11:09:23.788060
10285 11:09:24.044255 02f00000 ################################################################
10286 11:09:24.044429
10287 11:09:24.296274 02f80000 ################################################################
10288 11:09:24.296408
10289 11:09:24.576153 03000000 ################################################################
10290 11:09:24.576319
10291 11:09:24.875724 03080000 ################################################################
10292 11:09:24.875854
10293 11:09:24.937487 03100000 ############## done.
10294 11:09:24.937576
10295 11:09:24.940933 The bootfile was 51487742 bytes long.
10296 11:09:24.941017
10297 11:09:24.944211 Sending tftp read request... done.
10298 11:09:24.944300
10299 11:09:24.947623 Waiting for the transfer...
10300 11:09:24.947799
10301 11:09:24.947885 00000000 # done.
10302 11:09:24.947964
10303 11:09:24.954362 Command line loaded dynamically from TFTP file: 12925657/tftp-deploy-8ly4v_t3/kernel/cmdline
10304 11:09:24.954541
10305 11:09:24.970880 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10306 11:09:24.971103
10307 11:09:24.971227 Loading FIT.
10308 11:09:24.971341
10309 11:09:24.974011 Image ramdisk-1 has 39380731 bytes.
10310 11:09:24.974244
10311 11:09:24.977562 Image fdt-1 has 47278 bytes.
10312 11:09:24.977822
10313 11:09:24.981311 Image kernel-1 has 12057697 bytes.
10314 11:09:24.981570
10315 11:09:24.987590 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10316 11:09:24.987929
10317 11:09:25.007423 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10318 11:09:25.008000
10319 11:09:25.010576 Choosing best match conf-1 for compat google,spherion-rev2.
10320 11:09:25.015480
10321 11:09:25.020699 Connected to device vid:did:rid of 1ae0:0028:00
10322 11:09:25.028460
10323 11:09:25.031466 tpm_get_response: command 0x17b, return code 0x0
10324 11:09:25.031938
10325 11:09:25.035031 ec_init: CrosEC protocol v3 supported (256, 248)
10326 11:09:25.038682
10327 11:09:25.042341 tpm_cleanup: add release locality here.
10328 11:09:25.042808
10329 11:09:25.043173 Shutting down all USB controllers.
10330 11:09:25.045101
10331 11:09:25.045620 Removing current net device
10332 11:09:25.046004
10333 11:09:25.052216 Exiting depthcharge with code 4 at timestamp: 63956800
10334 11:09:25.052744
10335 11:09:25.055453 LZMA decompressing kernel-1 to 0x821a6718
10336 11:09:25.056020
10337 11:09:25.058888 LZMA decompressing kernel-1 to 0x40000000
10338 11:09:26.559401
10339 11:09:26.559961 jumping to kernel
10340 11:09:26.562061 end: 2.2.4 bootloader-commands (duration 00:00:36) [common]
10341 11:09:26.562613 start: 2.2.5 auto-login-action (timeout 00:03:49) [common]
10342 11:09:26.563038 Setting prompt string to ['Linux version [0-9]']
10343 11:09:26.563447 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10344 11:09:26.563834 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10345 11:09:26.641191
10346 11:09:26.644820 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10347 11:09:26.648348 start: 2.2.5.1 login-action (timeout 00:03:49) [common]
10348 11:09:26.648858 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10349 11:09:26.649284 Setting prompt string to []
10350 11:09:26.649733 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10351 11:09:26.650190 Using line separator: #'\n'#
10352 11:09:26.650537 No login prompt set.
10353 11:09:26.650882 Parsing kernel messages
10354 11:09:26.651197 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10355 11:09:26.652018 [login-action] Waiting for messages, (timeout 00:03:49)
10356 11:09:26.652430 Waiting using forced prompt support (timeout 00:01:54)
10357 11:09:26.667202 [ 0.000000] Linux version 6.1.80-cip16 (KernelCI@build-j128891-arm64-gcc-10-defconfig-arm64-chromebook-nrg4h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024
10358 11:09:26.670755 [ 0.000000] random: crng init done
10359 11:09:26.677491 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10360 11:09:26.680584 [ 0.000000] efi: UEFI not found.
10361 11:09:26.687494 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10362 11:09:26.694021 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10363 11:09:26.703886 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10364 11:09:26.714282 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10365 11:09:26.720761 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10366 11:09:26.727077 [ 0.000000] printk: bootconsole [mtk8250] enabled
10367 11:09:26.734065 [ 0.000000] NUMA: No NUMA configuration found
10368 11:09:26.740654 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10369 11:09:26.744420 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10370 11:09:26.747095 [ 0.000000] Zone ranges:
10371 11:09:26.754071 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10372 11:09:26.757259 [ 0.000000] DMA32 empty
10373 11:09:26.763865 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10374 11:09:26.767025 [ 0.000000] Movable zone start for each node
10375 11:09:26.770200 [ 0.000000] Early memory node ranges
10376 11:09:26.777026 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10377 11:09:26.784042 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10378 11:09:26.790552 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10379 11:09:26.797144 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10380 11:09:26.800429 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10381 11:09:26.810022 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10382 11:09:26.866114 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10383 11:09:26.872402 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10384 11:09:26.879471 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10385 11:09:26.882877 [ 0.000000] psci: probing for conduit method from DT.
10386 11:09:26.889377 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10387 11:09:26.892715 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10388 11:09:26.899385 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10389 11:09:26.902472 [ 0.000000] psci: SMC Calling Convention v1.2
10390 11:09:26.909444 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10391 11:09:26.912618 [ 0.000000] Detected VIPT I-cache on CPU0
10392 11:09:26.919013 [ 0.000000] CPU features: detected: GIC system register CPU interface
10393 11:09:26.926052 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10394 11:09:26.932545 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10395 11:09:26.938851 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10396 11:09:26.945409 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10397 11:09:26.955965 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10398 11:09:26.959006 [ 0.000000] alternatives: applying boot alternatives
10399 11:09:26.965195 [ 0.000000] Fallback order for Node 0: 0
10400 11:09:26.972381 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10401 11:09:26.975276 [ 0.000000] Policy zone: Normal
10402 11:09:26.988664 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10403 11:09:26.998453 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10404 11:09:27.010301 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10405 11:09:27.019989 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10406 11:09:27.026848 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10407 11:09:27.030491 <6>[ 0.000000] software IO TLB: area num 8.
10408 11:09:27.086965 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10409 11:09:27.235558 <6>[ 0.000000] Memory: 7928740K/8385536K available (18048K kernel code, 4118K rwdata, 19616K rodata, 8448K init, 616K bss, 424028K reserved, 32768K cma-reserved)
10410 11:09:27.242491 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10411 11:09:27.248957 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10412 11:09:27.252364 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10413 11:09:27.258987 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10414 11:09:27.265569 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10415 11:09:27.269391 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10416 11:09:27.278718 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10417 11:09:27.285425 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10418 11:09:27.289288 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10419 11:09:27.296774 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10420 11:09:27.300101 <6>[ 0.000000] GICv3: 608 SPIs implemented
10421 11:09:27.306519 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10422 11:09:27.309981 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10423 11:09:27.313380 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10424 11:09:27.323539 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10425 11:09:27.333087 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10426 11:09:27.346458 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10427 11:09:27.352835 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10428 11:09:27.362237 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10429 11:09:27.375078 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10430 11:09:27.381886 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10431 11:09:27.388450 <6>[ 0.009181] Console: colour dummy device 80x25
10432 11:09:27.398134 <6>[ 0.013911] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10433 11:09:27.405111 <6>[ 0.024353] pid_max: default: 32768 minimum: 301
10434 11:09:27.408413 <6>[ 0.029224] LSM: Security Framework initializing
10435 11:09:27.415230 <6>[ 0.034163] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10436 11:09:27.425110 <6>[ 0.041980] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10437 11:09:27.432005 <6>[ 0.051407] cblist_init_generic: Setting adjustable number of callback queues.
10438 11:09:27.438145 <6>[ 0.058898] cblist_init_generic: Setting shift to 3 and lim to 1.
10439 11:09:27.448478 <6>[ 0.065237] cblist_init_generic: Setting adjustable number of callback queues.
10440 11:09:27.454970 <6>[ 0.072663] cblist_init_generic: Setting shift to 3 and lim to 1.
10441 11:09:27.458753 <6>[ 0.079065] rcu: Hierarchical SRCU implementation.
10442 11:09:27.464963 <6>[ 0.084080] rcu: Max phase no-delay instances is 1000.
10443 11:09:27.471514 <6>[ 0.091107] EFI services will not be available.
10444 11:09:27.474753 <6>[ 0.096064] smp: Bringing up secondary CPUs ...
10445 11:09:27.483120 <6>[ 0.101117] Detected VIPT I-cache on CPU1
10446 11:09:27.489444 <6>[ 0.101187] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10447 11:09:27.496627 <6>[ 0.101222] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10448 11:09:27.499280 <6>[ 0.101557] Detected VIPT I-cache on CPU2
10449 11:09:27.505805 <6>[ 0.101604] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10450 11:09:27.513057 <6>[ 0.101619] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10451 11:09:27.519565 <6>[ 0.101877] Detected VIPT I-cache on CPU3
10452 11:09:27.525902 <6>[ 0.101923] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10453 11:09:27.532649 <6>[ 0.101936] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10454 11:09:27.535727 <6>[ 0.102243] CPU features: detected: Spectre-v4
10455 11:09:27.542849 <6>[ 0.102249] CPU features: detected: Spectre-BHB
10456 11:09:27.545690 <6>[ 0.102254] Detected PIPT I-cache on CPU4
10457 11:09:27.552458 <6>[ 0.102311] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10458 11:09:27.559047 <6>[ 0.102328] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10459 11:09:27.566020 <6>[ 0.102618] Detected PIPT I-cache on CPU5
10460 11:09:27.572403 <6>[ 0.102680] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10461 11:09:27.578621 <6>[ 0.102697] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10462 11:09:27.582315 <6>[ 0.102982] Detected PIPT I-cache on CPU6
10463 11:09:27.588775 <6>[ 0.103048] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10464 11:09:27.595372 <6>[ 0.103064] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10465 11:09:27.601816 <6>[ 0.103361] Detected PIPT I-cache on CPU7
10466 11:09:27.608511 <6>[ 0.103425] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10467 11:09:27.615203 <6>[ 0.103441] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10468 11:09:27.618632 <6>[ 0.103489] smp: Brought up 1 node, 8 CPUs
10469 11:09:27.625040 <6>[ 0.244799] SMP: Total of 8 processors activated.
10470 11:09:27.628509 <6>[ 0.249750] CPU features: detected: 32-bit EL0 Support
10471 11:09:27.638577 <6>[ 0.255147] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10472 11:09:27.645324 <6>[ 0.263947] CPU features: detected: Common not Private translations
10473 11:09:27.651487 <6>[ 0.270423] CPU features: detected: CRC32 instructions
10474 11:09:27.654969 <6>[ 0.275775] CPU features: detected: RCpc load-acquire (LDAPR)
10475 11:09:27.661715 <6>[ 0.281735] CPU features: detected: LSE atomic instructions
10476 11:09:27.668123 <6>[ 0.287552] CPU features: detected: Privileged Access Never
10477 11:09:27.675162 <6>[ 0.293332] CPU features: detected: RAS Extension Support
10478 11:09:27.681267 <6>[ 0.298941] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10479 11:09:27.684544 <6>[ 0.306161] CPU: All CPU(s) started at EL2
10480 11:09:27.691030 <6>[ 0.310477] alternatives: applying system-wide alternatives
10481 11:09:27.700527 <6>[ 0.321301] devtmpfs: initialized
10482 11:09:27.716285 <6>[ 0.330341] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10483 11:09:27.722741 <6>[ 0.340303] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10484 11:09:27.729739 <6>[ 0.348188] pinctrl core: initialized pinctrl subsystem
10485 11:09:27.733086 <6>[ 0.354860] DMI not present or invalid.
10486 11:09:27.740026 <6>[ 0.359271] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10487 11:09:27.749826 <6>[ 0.366122] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10488 11:09:27.756032 <6>[ 0.373715] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10489 11:09:27.766367 <6>[ 0.381934] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10490 11:09:27.769694 <6>[ 0.390176] audit: initializing netlink subsys (disabled)
10491 11:09:27.779425 <5>[ 0.395870] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10492 11:09:27.786129 <6>[ 0.396582] thermal_sys: Registered thermal governor 'step_wise'
10493 11:09:27.792493 <6>[ 0.403837] thermal_sys: Registered thermal governor 'power_allocator'
10494 11:09:27.795997 <6>[ 0.410096] cpuidle: using governor menu
10495 11:09:27.799136 <6>[ 0.421059] NET: Registered PF_QIPCRTR protocol family
10496 11:09:27.809604 <6>[ 0.426535] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10497 11:09:27.812689 <6>[ 0.433637] ASID allocator initialised with 32768 entries
10498 11:09:27.819609 <6>[ 0.440212] Serial: AMBA PL011 UART driver
10499 11:09:27.828131 <4>[ 0.448981] Trying to register duplicate clock ID: 134
10500 11:09:27.882837 <6>[ 0.506459] KASLR enabled
10501 11:09:27.896673 <6>[ 0.514194] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10502 11:09:27.903386 <6>[ 0.521209] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10503 11:09:27.910202 <6>[ 0.527697] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10504 11:09:27.916537 <6>[ 0.534701] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10505 11:09:27.922946 <6>[ 0.541187] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10506 11:09:27.930384 <6>[ 0.548191] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10507 11:09:27.936388 <6>[ 0.554678] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10508 11:09:27.943375 <6>[ 0.561681] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10509 11:09:27.946552 <6>[ 0.569311] ACPI: Interpreter disabled.
10510 11:09:27.955520 <6>[ 0.575721] iommu: Default domain type: Translated
10511 11:09:27.961835 <6>[ 0.580831] iommu: DMA domain TLB invalidation policy: strict mode
10512 11:09:27.964988 <5>[ 0.587494] SCSI subsystem initialized
10513 11:09:27.971771 <6>[ 0.591661] usbcore: registered new interface driver usbfs
10514 11:09:27.978289 <6>[ 0.597396] usbcore: registered new interface driver hub
10515 11:09:27.981204 <6>[ 0.602944] usbcore: registered new device driver usb
10516 11:09:27.988280 <6>[ 0.609047] pps_core: LinuxPPS API ver. 1 registered
10517 11:09:27.998334 <6>[ 0.614241] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10518 11:09:28.001643 <6>[ 0.623584] PTP clock support registered
10519 11:09:28.004847 <6>[ 0.627822] EDAC MC: Ver: 3.0.0
10520 11:09:28.012781 <6>[ 0.632979] FPGA manager framework
10521 11:09:28.015891 <6>[ 0.636662] Advanced Linux Sound Architecture Driver Initialized.
10522 11:09:28.019411 <6>[ 0.643444] vgaarb: loaded
10523 11:09:28.026139 <6>[ 0.646620] clocksource: Switched to clocksource arch_sys_counter
10524 11:09:28.032995 <5>[ 0.653060] VFS: Disk quotas dquot_6.6.0
10525 11:09:28.039076 <6>[ 0.657245] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10526 11:09:28.042591 <6>[ 0.664436] pnp: PnP ACPI: disabled
10527 11:09:28.050112 <6>[ 0.671106] NET: Registered PF_INET protocol family
10528 11:09:28.060543 <6>[ 0.676695] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10529 11:09:28.071971 <6>[ 0.688994] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10530 11:09:28.081419 <6>[ 0.697808] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10531 11:09:28.087980 <6>[ 0.705778] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10532 11:09:28.097799 <6>[ 0.714477] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10533 11:09:28.104814 <6>[ 0.724220] TCP: Hash tables configured (established 65536 bind 65536)
10534 11:09:28.111208 <6>[ 0.731081] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10535 11:09:28.121017 <6>[ 0.738282] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10536 11:09:28.124931 <6>[ 0.745982] NET: Registered PF_UNIX/PF_LOCAL protocol family
10537 11:09:28.131405 <6>[ 0.752152] RPC: Registered named UNIX socket transport module.
10538 11:09:28.138305 <6>[ 0.758309] RPC: Registered udp transport module.
10539 11:09:28.141626 <6>[ 0.763243] RPC: Registered tcp transport module.
10540 11:09:28.148260 <6>[ 0.768176] RPC: Registered tcp NFSv4.1 backchannel transport module.
10541 11:09:28.154787 <6>[ 0.774842] PCI: CLS 0 bytes, default 64
10542 11:09:28.157863 <6>[ 0.779232] Unpacking initramfs...
10543 11:09:28.177670 <6>[ 0.795181] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10544 11:09:28.188264 <6>[ 0.803839] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10545 11:09:28.191056 <6>[ 0.812702] kvm [1]: IPA Size Limit: 40 bits
10546 11:09:28.198090 <6>[ 0.817217] kvm [1]: GICv3: no GICV resource entry
10547 11:09:28.201366 <6>[ 0.822237] kvm [1]: disabling GICv2 emulation
10548 11:09:28.207485 <6>[ 0.826923] kvm [1]: GIC system register CPU interface enabled
10549 11:09:28.211051 <6>[ 0.833084] kvm [1]: vgic interrupt IRQ18
10550 11:09:28.217693 <6>[ 0.837451] kvm [1]: VHE mode initialized successfully
10551 11:09:28.224593 <5>[ 0.843751] Initialise system trusted keyrings
10552 11:09:28.230998 <6>[ 0.848525] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10553 11:09:28.237856 <6>[ 0.858630] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10554 11:09:28.244673 <5>[ 0.865037] NFS: Registering the id_resolver key type
10555 11:09:28.247988 <5>[ 0.870340] Key type id_resolver registered
10556 11:09:28.254484 <5>[ 0.874754] Key type id_legacy registered
10557 11:09:28.261344 <6>[ 0.879038] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10558 11:09:28.267471 <6>[ 0.885959] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10559 11:09:28.274406 <6>[ 0.893662] 9p: Installing v9fs 9p2000 file system support
10560 11:09:28.311398 <5>[ 0.931668] Key type asymmetric registered
10561 11:09:28.314479 <5>[ 0.935999] Asymmetric key parser 'x509' registered
10562 11:09:28.324514 <6>[ 0.941139] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10563 11:09:28.327646 <6>[ 0.948753] io scheduler mq-deadline registered
10564 11:09:28.330788 <6>[ 0.953513] io scheduler kyber registered
10565 11:09:28.349752 <6>[ 0.970353] EINJ: ACPI disabled.
10566 11:09:28.381414 <4>[ 0.995733] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10567 11:09:28.391754 <4>[ 1.006352] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10568 11:09:28.406125 <6>[ 1.026955] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10569 11:09:28.414112 <6>[ 1.034942] printk: console [ttyS0] disabled
10570 11:09:28.442571 <6>[ 1.059566] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10571 11:09:28.449445 <6>[ 1.069058] printk: console [ttyS0] enabled
10572 11:09:28.452132 <6>[ 1.069058] printk: console [ttyS0] enabled
10573 11:09:28.458896 <6>[ 1.077953] printk: bootconsole [mtk8250] disabled
10574 11:09:28.461844 <6>[ 1.077953] printk: bootconsole [mtk8250] disabled
10575 11:09:28.469055 <6>[ 1.088946] SuperH (H)SCI(F) driver initialized
10576 11:09:28.472032 <6>[ 1.094215] msm_serial: driver initialized
10577 11:09:28.486087 <6>[ 1.103121] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10578 11:09:28.495870 <6>[ 1.111663] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10579 11:09:28.502144 <6>[ 1.120205] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10580 11:09:28.512544 <6>[ 1.128831] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10581 11:09:28.522344 <6>[ 1.137542] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10582 11:09:28.529345 <6>[ 1.146260] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10583 11:09:28.538506 <6>[ 1.154798] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10584 11:09:28.545404 <6>[ 1.163595] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10585 11:09:28.555083 <6>[ 1.172138] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10586 11:09:28.566845 <6>[ 1.187439] loop: module loaded
10587 11:09:28.573636 <6>[ 1.193405] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10588 11:09:28.596195 <4>[ 1.216559] mtk-pmic-keys: Failed to locate of_node [id: -1]
10589 11:09:28.602402 <6>[ 1.223314] megasas: 07.719.03.00-rc1
10590 11:09:28.612132 <6>[ 1.232790] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10591 11:09:28.621712 <6>[ 1.242001] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10592 11:09:28.638005 <6>[ 1.258533] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10593 11:09:28.693581 <6>[ 1.307719] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10594 11:09:29.788238 <6>[ 2.409296] Freeing initrd memory: 38452K
10595 11:09:29.798319 <6>[ 2.419494] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10596 11:09:29.809092 <6>[ 2.430329] tun: Universal TUN/TAP device driver, 1.6
10597 11:09:29.812332 <6>[ 2.436384] thunder_xcv, ver 1.0
10598 11:09:29.815976 <6>[ 2.439891] thunder_bgx, ver 1.0
10599 11:09:29.819024 <6>[ 2.443385] nicpf, ver 1.0
10600 11:09:29.829407 <6>[ 2.447399] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10601 11:09:29.833059 <6>[ 2.454876] hns3: Copyright (c) 2017 Huawei Corporation.
10602 11:09:29.839558 <6>[ 2.460463] hclge is initializing
10603 11:09:29.842953 <6>[ 2.464045] e1000: Intel(R) PRO/1000 Network Driver
10604 11:09:29.850009 <6>[ 2.469174] e1000: Copyright (c) 1999-2006 Intel Corporation.
10605 11:09:29.852989 <6>[ 2.475188] e1000e: Intel(R) PRO/1000 Network Driver
10606 11:09:29.859562 <6>[ 2.480403] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10607 11:09:29.866340 <6>[ 2.486590] igb: Intel(R) Gigabit Ethernet Network Driver
10608 11:09:29.872995 <6>[ 2.492239] igb: Copyright (c) 2007-2014 Intel Corporation.
10609 11:09:29.879682 <6>[ 2.498079] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10610 11:09:29.886323 <6>[ 2.504597] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10611 11:09:29.889684 <6>[ 2.511057] sky2: driver version 1.30
10612 11:09:29.896066 <6>[ 2.516046] VFIO - User Level meta-driver version: 0.3
10613 11:09:29.903464 <6>[ 2.524254] usbcore: registered new interface driver usb-storage
10614 11:09:29.910094 <6>[ 2.530720] usbcore: registered new device driver onboard-usb-hub
10615 11:09:29.919252 <6>[ 2.539880] mt6397-rtc mt6359-rtc: registered as rtc0
10616 11:09:29.929418 <6>[ 2.545369] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T11:08:52 UTC (1709464132)
10617 11:09:29.932476 <6>[ 2.554969] i2c_dev: i2c /dev entries driver
10618 11:09:29.949008 <6>[ 2.566659] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10619 11:09:29.969132 <6>[ 2.589656] cpu cpu0: EM: created perf domain
10620 11:09:29.972261 <6>[ 2.594587] cpu cpu4: EM: created perf domain
10621 11:09:29.979192 <6>[ 2.600147] sdhci: Secure Digital Host Controller Interface driver
10622 11:09:29.986089 <6>[ 2.606579] sdhci: Copyright(c) Pierre Ossman
10623 11:09:29.992727 <6>[ 2.611531] Synopsys Designware Multimedia Card Interface Driver
10624 11:09:29.999438 <6>[ 2.618165] sdhci-pltfm: SDHCI platform and OF driver helper
10625 11:09:30.002527 <6>[ 2.618191] mmc0: CQHCI version 5.10
10626 11:09:30.009088 <6>[ 2.628593] ledtrig-cpu: registered to indicate activity on CPUs
10627 11:09:30.015745 <6>[ 2.635622] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10628 11:09:30.022297 <6>[ 2.642687] usbcore: registered new interface driver usbhid
10629 11:09:30.025528 <6>[ 2.648509] usbhid: USB HID core driver
10630 11:09:30.035641 <6>[ 2.652716] spi_master spi0: will run message pump with realtime priority
10631 11:09:30.076113 <6>[ 2.690503] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10632 11:09:30.094730 <6>[ 2.705467] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10633 11:09:30.101751 <6>[ 2.720693] cros-ec-spi spi0.0: Chrome EC device registered
10634 11:09:30.105283 <6>[ 2.726708] mmc0: Command Queue Engine enabled
10635 11:09:30.112154 <6>[ 2.731454] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10636 11:09:30.118197 <6>[ 2.739023] mmcblk0: mmc0:0001 DA4128 116 GiB
10637 11:09:30.126616 <6>[ 2.747279] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10638 11:09:30.134075 <6>[ 2.754678] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10639 11:09:30.143639 <6>[ 2.759770] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10640 11:09:30.147034 <6>[ 2.760539] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10641 11:09:30.153640 <6>[ 2.770456] NET: Registered PF_PACKET protocol family
10642 11:09:30.160154 <6>[ 2.775129] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10643 11:09:30.163480 <6>[ 2.779810] 9pnet: Installing 9P2000 support
10644 11:09:30.170259 <5>[ 2.790807] Key type dns_resolver registered
10645 11:09:30.173734 <6>[ 2.795770] registered taskstats version 1
10646 11:09:30.179830 <5>[ 2.800138] Loading compiled-in X.509 certificates
10647 11:09:30.207559 <4>[ 2.821985] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10648 11:09:30.217778 <4>[ 2.832717] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10649 11:09:30.224575 <3>[ 2.843252] debugfs: File 'uA_load' in directory '/' already present!
10650 11:09:30.230675 <3>[ 2.850009] debugfs: File 'min_uV' in directory '/' already present!
10651 11:09:30.237121 <3>[ 2.856625] debugfs: File 'max_uV' in directory '/' already present!
10652 11:09:30.243790 <3>[ 2.863234] debugfs: File 'constraint_flags' in directory '/' already present!
10653 11:09:30.254838 <3>[ 2.872845] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10654 11:09:30.264305 <6>[ 2.885198] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10655 11:09:30.270923 <6>[ 2.892009] xhci-mtk 11200000.usb: xHCI Host Controller
10656 11:09:30.277720 <6>[ 2.897516] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10657 11:09:30.287729 <6>[ 2.905358] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10658 11:09:30.294891 <6>[ 2.914777] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10659 11:09:30.300787 <6>[ 2.920847] xhci-mtk 11200000.usb: xHCI Host Controller
10660 11:09:30.307720 <6>[ 2.926322] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10661 11:09:30.314065 <6>[ 2.933969] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10662 11:09:30.321130 <6>[ 2.941631] hub 1-0:1.0: USB hub found
10663 11:09:30.323937 <6>[ 2.945637] hub 1-0:1.0: 1 port detected
10664 11:09:30.333725 <6>[ 2.949898] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10665 11:09:30.337258 <6>[ 2.958528] hub 2-0:1.0: USB hub found
10666 11:09:30.340520 <6>[ 2.962539] hub 2-0:1.0: 1 port detected
10667 11:09:30.348379 <6>[ 2.969106] mtk-msdc 11f70000.mmc: Got CD GPIO
10668 11:09:30.361292 <6>[ 2.979010] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10669 11:09:30.367898 <6>[ 2.987041] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10670 11:09:30.378108 <4>[ 2.994958] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10671 11:09:30.388104 <6>[ 3.004485] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10672 11:09:30.394539 <6>[ 3.012562] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10673 11:09:30.401147 <6>[ 3.020600] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10674 11:09:30.411043 <6>[ 3.028513] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10675 11:09:30.417667 <6>[ 3.036335] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10676 11:09:30.427755 <6>[ 3.044151] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10677 11:09:30.437387 <6>[ 3.054583] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10678 11:09:30.444150 <6>[ 3.062939] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10679 11:09:30.453933 <6>[ 3.071289] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10680 11:09:30.460251 <6>[ 3.079627] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10681 11:09:30.470479 <6>[ 3.087964] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10682 11:09:30.477480 <6>[ 3.096302] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10683 11:09:30.486641 <6>[ 3.104639] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10684 11:09:30.497102 <6>[ 3.112975] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10685 11:09:30.503908 <6>[ 3.121314] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10686 11:09:30.513803 <6>[ 3.129652] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10687 11:09:30.520217 <6>[ 3.137990] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10688 11:09:30.530400 <6>[ 3.146339] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10689 11:09:30.537097 <6>[ 3.154676] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10690 11:09:30.546643 <6>[ 3.163013] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10691 11:09:30.553531 <6>[ 3.171352] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10692 11:09:30.560346 <6>[ 3.180074] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10693 11:09:30.566409 <6>[ 3.187245] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10694 11:09:30.573835 <6>[ 3.194004] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10695 11:09:30.582874 <6>[ 3.200763] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10696 11:09:30.589447 <6>[ 3.207740] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10697 11:09:30.596427 <6>[ 3.214592] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10698 11:09:30.605992 <6>[ 3.223723] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10699 11:09:30.616195 <6>[ 3.232842] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10700 11:09:30.626123 <6>[ 3.242136] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10701 11:09:30.636149 <6>[ 3.251632] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10702 11:09:30.645759 <6>[ 3.261103] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10703 11:09:30.652490 <6>[ 3.270222] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10704 11:09:30.662387 <6>[ 3.279691] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10705 11:09:30.672255 <6>[ 3.288809] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10706 11:09:30.682357 <6>[ 3.298104] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10707 11:09:30.691981 <6>[ 3.308264] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10708 11:09:30.701901 <6>[ 3.319895] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10709 11:09:30.749192 <6>[ 3.366885] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10710 11:09:30.904323 <6>[ 3.525087] hub 1-1:1.0: USB hub found
10711 11:09:30.908281 <6>[ 3.529634] hub 1-1:1.0: 4 ports detected
10712 11:09:30.916811 <6>[ 3.537998] hub 1-1:1.0: USB hub found
10713 11:09:30.920148 <6>[ 3.542311] hub 1-1:1.0: 4 ports detected
10714 11:09:31.029378 <6>[ 3.647321] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10715 11:09:31.057505 <6>[ 3.678426] hub 2-1:1.0: USB hub found
10716 11:09:31.060629 <6>[ 3.682975] hub 2-1:1.0: 3 ports detected
10717 11:09:31.071253 <6>[ 3.692122] hub 2-1:1.0: USB hub found
10718 11:09:31.074454 <6>[ 3.696668] hub 2-1:1.0: 3 ports detected
10719 11:09:31.241317 <6>[ 3.858929] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10720 11:09:31.373178 <6>[ 3.993992] hub 1-1.4:1.0: USB hub found
10721 11:09:31.376095 <6>[ 3.998541] hub 1-1.4:1.0: 2 ports detected
10722 11:09:31.385212 <6>[ 4.006104] hub 1-1.4:1.0: USB hub found
10723 11:09:31.388425 <6>[ 4.010665] hub 1-1.4:1.0: 2 ports detected
10724 11:09:31.457533 <6>[ 4.075125] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10725 11:09:31.684739 <6>[ 4.302928] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10726 11:09:31.877412 <6>[ 4.494902] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10727 11:09:42.974167 <6>[ 15.599935] ALSA device list:
10728 11:09:42.980908 <6>[ 15.603225] No soundcards found.
10729 11:09:42.989235 <6>[ 15.611200] Freeing unused kernel memory: 8448K
10730 11:09:42.991720 <6>[ 15.616734] Run /init as init process
10731 11:09:43.023487 <6>[ 15.646136] NET: Registered PF_INET6 protocol family
10732 11:09:43.030224 <6>[ 15.652398] Segment Routing with IPv6
10733 11:09:43.033373 <6>[ 15.656351] In-situ OAM (IOAM) with IPv6
10734 11:09:43.066879 <30>[ 15.669781] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10735 11:09:43.070685 <30>[ 15.693655] systemd[1]: Detected architecture arm64.
10736 11:09:43.071328
10737 11:09:43.077398 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10738 11:09:43.078017
10739 11:09:43.092316 <30>[ 15.715011] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10740 11:09:43.251319 <30>[ 15.870556] systemd[1]: Queued start job for default target Graphical Interface.
10741 11:09:43.285424 <30>[ 15.907603] systemd[1]: Created slice system-getty.slice.
10742 11:09:43.291931 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10743 11:09:43.308853 <30>[ 15.931247] systemd[1]: Created slice system-modprobe.slice.
10744 11:09:43.315387 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10745 11:09:43.333069 <30>[ 15.955385] systemd[1]: Created slice system-serial\x2dgetty.slice.
10746 11:09:43.343112 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10747 11:09:43.357474 <30>[ 15.980178] systemd[1]: Created slice User and Session Slice.
10748 11:09:43.364135 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10749 11:09:43.384615 <30>[ 16.003495] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10750 11:09:43.394326 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10751 11:09:43.412207 <30>[ 16.031474] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10752 11:09:43.418983 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10753 11:09:43.443254 <30>[ 16.059005] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10754 11:09:43.449653 <30>[ 16.071155] systemd[1]: Reached target Local Encrypted Volumes.
10755 11:09:43.456071 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10756 11:09:43.472912 <30>[ 16.095469] systemd[1]: Reached target Paths.
10757 11:09:43.479559 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10758 11:09:43.492430 <30>[ 16.114899] systemd[1]: Reached target Remote File Systems.
10759 11:09:43.498812 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10760 11:09:43.516923 <30>[ 16.139280] systemd[1]: Reached target Slices.
10761 11:09:43.523287 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10762 11:09:43.537066 <30>[ 16.158921] systemd[1]: Reached target Swap.
10763 11:09:43.539686 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10764 11:09:43.560725 <30>[ 16.179408] systemd[1]: Listening on initctl Compatibility Named Pipe.
10765 11:09:43.566624 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10766 11:09:43.573119 <30>[ 16.194559] systemd[1]: Listening on Journal Audit Socket.
10767 11:09:43.579731 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10768 11:09:43.593090 <30>[ 16.215384] systemd[1]: Listening on Journal Socket (/dev/log).
10769 11:09:43.599585 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10770 11:09:43.617722 <30>[ 16.240145] systemd[1]: Listening on Journal Socket.
10771 11:09:43.624287 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10772 11:09:43.640263 <30>[ 16.259599] systemd[1]: Listening on Network Service Netlink Socket.
10773 11:09:43.646829 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10774 11:09:43.660895 <30>[ 16.283470] systemd[1]: Listening on udev Control Socket.
10775 11:09:43.667237 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10776 11:09:43.685500 <30>[ 16.307980] systemd[1]: Listening on udev Kernel Socket.
10777 11:09:43.691904 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10778 11:09:43.740907 <30>[ 16.363154] systemd[1]: Mounting Huge Pages File System...
10779 11:09:43.747335 Mounting [0;1;39mHuge Pages File System[0m...
10780 11:09:43.763248 <30>[ 16.385718] systemd[1]: Mounting POSIX Message Queue File System...
10781 11:09:43.769791 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10782 11:09:43.787821 <30>[ 16.410401] systemd[1]: Mounting Kernel Debug File System...
10783 11:09:43.794400 Mounting [0;1;39mKernel Debug File System[0m...
10784 11:09:43.812081 <30>[ 16.431136] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10785 11:09:43.840383 <30>[ 16.459112] systemd[1]: Starting Create list of static device nodes for the current kernel...
10786 11:09:43.846381 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10787 11:09:43.868667 <30>[ 16.491113] systemd[1]: Starting Load Kernel Module configfs...
10788 11:09:43.875255 Starting [0;1;39mLoad Kernel Module configfs[0m...
10789 11:09:43.892543 <30>[ 16.514962] systemd[1]: Starting Load Kernel Module drm...
10790 11:09:43.898600 Starting [0;1;39mLoad Kernel Module drm[0m...
10791 11:09:43.915988 <30>[ 16.534943] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10792 11:09:43.929411 <30>[ 16.551767] systemd[1]: Starting Journal Service...
10793 11:09:43.935627 Starting [0;1;39mJournal Service[0m...
10794 11:09:43.950875 <30>[ 16.573599] systemd[1]: Starting Load Kernel Modules...
10795 11:09:43.957741 Starting [0;1;39mLoad Kernel Modules[0m...
10796 11:09:44.008318 <30>[ 16.627578] systemd[1]: Starting Remount Root and Kernel File Systems...
10797 11:09:44.014974 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10798 11:09:44.032897 <30>[ 16.655441] systemd[1]: Starting Coldplug All udev Devices...
10799 11:09:44.039934 Starting [0;1;39mColdplug All udev Devices[0m...
10800 11:09:44.055030 <30>[ 16.677504] systemd[1]: Started Journal Service.
10801 11:09:44.061507 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10802 11:09:44.079843 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10803 11:09:44.097333 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10804 11:09:44.113663 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10805 11:09:44.133436 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10806 11:09:44.150769 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10807 11:09:44.174736 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10808 11:09:44.194576 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10809 11:09:44.214581 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10810 11:09:44.228414 See 'systemctl status systemd-remount-fs.service' for details.
10811 11:09:44.274500 Mounting [0;1;39mKernel Configuration File System[0m...
10812 11:09:44.299828 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10813 11:09:44.313139 <46>[ 16.932486] systemd-journald[181]: Received client request to flush runtime journal.
10814 11:09:44.323549 Starting [0;1;39mLoad/Save Random Seed[0m...
10815 11:09:44.344199 Starting [0;1;39mApply Kernel Variables[0m...
10816 11:09:44.370372 Starting [0;1;39mCreate System Users[0m...
10817 11:09:44.394610 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10818 11:09:44.418220 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10819 11:09:44.441120 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10820 11:09:44.454004 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10821 11:09:44.470058 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10822 11:09:44.486283 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10823 11:09:44.533177 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10824 11:09:44.559072 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10825 11:09:44.572525 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10826 11:09:44.592718 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10827 11:09:44.624640 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10828 11:09:44.652619 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10829 11:09:44.676056 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10830 11:09:44.701692 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10831 11:09:44.759035 Starting [0;1;39mNetwork Service[0m...
10832 11:09:44.783204 Starting [0;1;39mNetwork Time Synchronization[0m...
10833 11:09:44.804716 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10834 11:09:44.834904 [[0;32m OK [0m] Started [0;1;39mNetwork Ser<6>[ 17.453839] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10835 11:09:44.835478 vice[0m.
10836 11:09:44.847828 <6>[ 17.467071] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10837 11:09:44.854804 <6>[ 17.474845] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10838 11:09:44.861539 <6>[ 17.479804] remoteproc remoteproc0: scp is available
10839 11:09:44.871009 <6>[ 17.483668] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10840 11:09:44.874255 <6>[ 17.489491] remoteproc remoteproc0: powering up scp
10841 11:09:44.884324 <6>[ 17.502763] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10842 11:09:44.890474 <6>[ 17.502793] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10843 11:09:44.893970 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10844 11:09:44.902932 <6>[ 17.525670] mc: Linux media interface: v0.10
10845 11:09:44.913668 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10846 11:09:44.936417 [[0;32m OK [0m] Found device<6>[ 17.558018] videodev: Linux video capture interface: v2.00
10847 11:09:44.939391 [0;1;39m/dev/ttyS0[0m.
10848 11:09:44.952998 <3>[ 17.572090] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10849 11:09:44.959216 <3>[ 17.580349] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10850 11:09:44.969115 <3>[ 17.588444] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10851 11:09:44.979102 [[0;32m OK [<4>[ 17.597089] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10852 11:09:44.986128 0m] Created slic<6>[ 17.605749] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10853 11:09:44.995799 e [0;1;39msyste<3>[ 17.606910] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10854 11:09:45.002467 <4>[ 17.612605] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10855 11:09:45.012402 m-systemd\x2dbac<3>[ 17.631940] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10856 11:09:45.018942 <6>[ 17.638866] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10857 11:09:45.028610 klight.slice[0m<4>[ 17.640523] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10858 11:09:45.035625 <4>[ 17.640523] Fallback method does not support PEC.
10859 11:09:45.042370 <3>[ 17.640849] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10860 11:09:45.049216 <6>[ 17.642844] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10861 11:09:45.055864 <6>[ 17.647876] pci_bus 0000:00: root bus resource [bus 00-ff]
10862 11:09:45.066261 <6>[ 17.662764] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10863 11:09:45.066838 .
10864 11:09:45.072656 <6>[ 17.663064] usbcore: registered new device driver r8152-cfgselector
10865 11:09:45.079620 <3>[ 17.663260] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10866 11:09:45.086199 <3>[ 17.663272] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10867 11:09:45.096996 <3>[ 17.663878] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10868 11:09:45.103805 <3>[ 17.665197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10869 11:09:45.109871 <3>[ 17.665203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10870 11:09:45.120124 <3>[ 17.665207] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10871 11:09:45.126826 <3>[ 17.665281] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10872 11:09:45.136646 <3>[ 17.665285] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10873 11:09:45.143740 <3>[ 17.665288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10874 11:09:45.153574 <3>[ 17.665297] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10875 11:09:45.160094 <3>[ 17.665301] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10876 11:09:45.169983 <3>[ 17.665324] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10877 11:09:45.176102 <6>[ 17.670847] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10878 11:09:45.183002 <3>[ 17.675262] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 11:09:45.189719 <6>[ 17.677936] remoteproc remoteproc0: remote processor scp is now up
10880 11:09:45.199667 <6>[ 17.683625] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10881 11:09:45.209383 <3>[ 17.718246] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 11:09:45.219400 <6>[ 17.719101] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10883 11:09:45.229360 <3>[ 17.719183] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10884 11:09:45.236347 <6>[ 17.723281] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10885 11:09:45.243647 <6>[ 17.734884] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10886 11:09:45.250290 <6>[ 17.739563] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10887 11:09:45.260584 <6>[ 17.748085] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10888 11:09:45.264073 <6>[ 17.755656] pci 0000:00:00.0: supports D1 D2
10889 11:09:45.270518 <6>[ 17.823643] Bluetooth: Core ver 2.22
10890 11:09:45.277214 <6>[ 17.828323] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10891 11:09:45.280529 <6>[ 17.837891] NET: Registered PF_BLUETOOTH protocol family
10892 11:09:45.290253 <6>[ 17.850386] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10893 11:09:45.297200 <6>[ 17.858409] Bluetooth: HCI device and connection manager initialized
10894 11:09:45.303841 <6>[ 17.860719] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10895 11:09:45.310316 <6>[ 17.862850] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10896 11:09:45.323904 <6>[ 17.867371] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10897 11:09:45.327501 <6>[ 17.867706] usbcore: registered new interface driver uvcvideo
10898 11:09:45.339171 <3>[ 17.868616] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 11:09:45.345621 <6>[ 17.872037] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10900 11:09:45.351852 <6>[ 17.879522] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10901 11:09:45.362379 <6>[ 17.879542] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10902 11:09:45.368429 <6>[ 17.879557] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10903 11:09:45.371950 <6>[ 17.879687] pci 0000:01:00.0: supports D1 D2
10904 11:09:45.378316 <6>[ 17.880411] Bluetooth: HCI socket layer initialized
10905 11:09:45.381755 <6>[ 17.880422] Bluetooth: L2CAP socket layer initialized
10906 11:09:45.389378 <6>[ 17.880458] Bluetooth: SCO socket layer initialized
10907 11:09:45.393080 <6>[ 17.890535] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10908 11:09:45.403240 <3>[ 17.890774] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 11:09:45.410202 <6>[ 17.893455] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10910 11:09:45.419392 <4>[ 17.920231] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10911 11:09:45.426305 <6>[ 17.925900] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10912 11:09:45.433034 <6>[ 17.926179] usbcore: registered new interface driver btusb
10913 11:09:45.442907 <4>[ 17.926787] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10914 11:09:45.449668 <3>[ 17.926805] Bluetooth: hci0: Failed to load firmware file (-2)
10915 11:09:45.455668 <3>[ 17.926818] Bluetooth: hci0: Failed to set up firmware (-2)
10916 11:09:45.466087 <4>[ 17.926823] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10917 11:09:45.472696 <4>[ 17.931423] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10918 11:09:45.479988 <6>[ 17.938886] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10919 11:09:45.490519 <6>[ 17.939589] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10920 11:09:45.496992 <3>[ 17.955559] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10921 11:09:45.503884 <6>[ 17.956269] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10922 11:09:45.513638 <3>[ 17.968628] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 11:09:45.520994 <6>[ 17.973217] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10924 11:09:45.531060 <6>[ 17.973228] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10925 11:09:45.534200 <6>[ 18.006807] r8152 2-1.3:1.0 eth0: v1.12.13
10926 11:09:45.541185 <6>[ 18.010583] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10927 11:09:45.548254 <6>[ 18.015808] usbcore: registered new interface driver r8152
10928 11:09:45.558445 <3>[ 18.020690] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 11:09:45.565917 <3>[ 18.021464] power_supply sbs-5-000b: driver failed to report `energy_full' property: -6
10930 11:09:45.572969 <6>[ 18.022221] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10931 11:09:45.579041 <6>[ 18.022233] pci 0000:00:00.0: PCI bridge to [bus 01]
10932 11:09:45.586481 <6>[ 18.061326] usbcore: registered new interface driver cdc_ether
10933 11:09:45.592695 <6>[ 18.071371] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10934 11:09:45.599910 <6>[ 18.071523] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10935 11:09:45.606923 <6>[ 18.093821] usbcore: registered new interface driver r8153_ecm
10936 11:09:45.609798 <6>[ 18.102272] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10937 11:09:45.619966 <3>[ 18.108767] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 11:09:45.626464 <6>[ 18.117332] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10939 11:09:45.633094 <6>[ 18.141595] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10940 11:09:45.636723 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10941 11:09:45.652311 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10942 11:09:45.690000 <5>[ 18.309351] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10943 11:09:45.710549 <5>[ 18.330395] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10944 11:09:45.720615 Startin<5>[ 18.337487] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10945 11:09:45.730526 g [0;1;39mLoad/<4>[ 18.347356] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10946 11:09:45.737410 Save Screen …o<6>[ 18.357569] cfg80211: failed to load regulatory.db
10947 11:09:45.740569 f leds:white:kbd_backlight[0m...
10948 11:09:45.750638 Starting [0;1;39mNetwork Name Resolution[0m...
10949 11:09:45.771127 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10950 11:09:45.788961 <6>[ 18.408673] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10951 11:09:45.795730 <6>[ 18.416204] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10952 11:09:45.819756 <6>[ 18.443099] mt7921e 0000:01:00.0: ASIC revision: 79610010
10953 11:09:45.826209 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10954 11:09:45.922938 <6>[ 18.542415] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10955 11:09:45.926747 <6>[ 18.542415]
10956 11:09:45.963122 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10957 11:09:45.976205 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10958 11:09:45.995318 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10959 11:09:46.007943 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10960 11:09:46.032014 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10961 11:09:46.047738 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10962 11:09:46.064607 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10963 11:09:46.084395 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10964 11:09:46.100579 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10965 11:09:46.116153 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10966 11:09:46.136346 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10967 11:09:46.172493 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10968 11:09:46.190341 <6>[ 18.810127] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10969 11:09:46.212477 Starting [0;1;39mUser Login Management[0m...
10970 11:09:46.231872 Starting [0;1;39mPermit User Sessions[0m...
10971 11:09:46.252250 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10972 11:09:46.274919 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10973 11:09:46.293322 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10974 11:09:46.308460 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10975 11:09:46.328785 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10976 11:09:46.345650 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10977 11:09:46.361474 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10978 11:09:46.369512 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10979 11:09:46.385432 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10980 11:09:46.440624 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10981 11:09:46.469010 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10982 11:09:46.508536
10983 11:09:46.509095
10984 11:09:46.512077 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10985 11:09:46.512638
10986 11:09:46.515095 debian-bullseye-arm64 login: root (automatic login)
10987 11:09:46.515565
10988 11:09:46.515936
10989 11:09:46.530521 Linux debian-bullseye-arm64 6.1.80-cip16 #1 SMP PREEMPT Sun Mar 3 10:48:40 UTC 2024 aarch64
10990 11:09:46.531071
10991 11:09:46.537349 The programs included with the Debian GNU/Linux system are free software;
10992 11:09:46.544022 the exact distribution terms for each program are described in the
10993 11:09:46.547248 individual files in /usr/share/doc/*/copyright.
10994 11:09:46.547814
10995 11:09:46.553900 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10996 11:09:46.557013 permitted by applicable law.
10997 11:09:46.558558 Matched prompt #10: / #
10999 11:09:46.559690 Setting prompt string to ['/ #']
11000 11:09:46.560172 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11002 11:09:46.561240 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11003 11:09:46.561729 start: 2.2.6 expect-shell-connection (timeout 00:03:29) [common]
11004 11:09:46.562149 Setting prompt string to ['/ #']
11005 11:09:46.562500 Forcing a shell prompt, looking for ['/ #']
11007 11:09:46.613462 / #
11008 11:09:46.614170 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11009 11:09:46.614739 Waiting using forced prompt support (timeout 00:02:30)
11010 11:09:46.619976
11011 11:09:46.620918 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11012 11:09:46.621470 start: 2.2.7 export-device-env (timeout 00:03:29) [common]
11013 11:09:46.622033 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11014 11:09:46.622540 end: 2.2 depthcharge-retry (duration 00:01:31) [common]
11015 11:09:46.623038 end: 2 depthcharge-action (duration 00:01:31) [common]
11016 11:09:46.623536 start: 3 lava-test-retry (timeout 00:08:10) [common]
11017 11:09:46.624017 start: 3.1 lava-test-shell (timeout 00:08:10) [common]
11018 11:09:46.624504 Using namespace: common
11020 11:09:46.725930 / # #
11021 11:09:46.726831 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11022 11:09:46.732967 #
11023 11:09:46.734087 Using /lava-12925657
11025 11:09:46.835473 / # export SHELL=/bin/sh
11026 11:09:46.842271 export SHELL=/bin/sh
11028 11:09:46.943937 / # . /lava-12925657/environment
11029 11:09:46.950322 . /lava-12925657/environment
11031 11:09:47.051914 / # /lava-12925657/bin/lava-test-runner /lava-12925657/0
11032 11:09:47.052556 Test shell timeout: 10s (minimum of the action and connection timeout)
11033 11:09:47.054190 /lava-12925657/bin/lava-test-runner /lava-12925657/0<6>[ 19.662781] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11034 11:09:47.054621 <6>[ 19.668863] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
11035 11:09:47.057879
11036 11:09:47.102431 <6>[ 19.693146] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
11037 11:09:47.103403 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11038 11:09:47.103828 + cd /lava-12925657/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11039 11:09:47.104195 + cat uuid
11040 11:09:47.104541 + UUID=12925657_1.5.2.3.1
11041 11:09:47.104873 + set +x
11042 11:09:47.108034 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 12925657_1.5.2.3.1>
11043 11:09:47.108888 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 12925657_1.5.2.3.1
11044 11:09:47.109311 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (12925657_1.5.2.3.1)
11045 11:09:47.109770 Skipping test definition patterns.
11046 11:09:47.111047 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11047 11:09:47.117907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11048 11:09:47.118797 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11050 11:09:47.127928 device: /dev/vide<4>[ 19.745942] use of bytesused == 0 is deprecated and will be removed in the future,
11051 11:09:47.128507 o2
11052 11:09:47.131423 <4>[ 19.754299] use the actual size instead.
11053 11:09:47.146589 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11054 11:09:47.155130 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11055 11:09:47.165441
11056 11:09:47.178311 Compliance test for mtk-vcodec-enc device /dev/video2:
11057 11:09:47.185106
11058 11:09:47.194871 Driver Info:
11059 11:09:47.207159 Driver name : mtk-vcodec-enc
11060 11:09:47.221918 Card type : MT8192 video encoder
11061 11:09:47.233123 Bus info : platform:17020000.vcodec
11062 11:09:47.238850 Driver version : 6.1.80
11063 11:09:47.249995 Capabilities : 0x84204000
11064 11:09:47.260691 Video Memory-to-Memory Multiplanar
11065 11:09:47.270815 Streaming
11066 11:09:47.282049 Extended Pix Format
11067 11:09:47.293363 Device Capabilities
11068 11:09:47.303061 Device Caps : 0x04204000
11069 11:09:47.315352 Video Memory-to-Memory Multiplanar
11070 11:09:47.326785 Streaming
11071 11:09:47.342433 Extended Pix Format
11072 11:09:47.352204 Detected Stateful Encoder
11073 11:09:47.366215
11074 11:09:47.377028 Required ioctls:
11075 11:09:47.392818 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11076 11:09:47.393376 test VIDIOC_QUERYCAP: OK
11077 11:09:47.394067 Received signal: <TESTSET> START Required-ioctls
11078 11:09:47.394474 Starting test_set Required-ioctls
11079 11:09:47.419172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11080 11:09:47.419999 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11082 11:09:47.422139 test invalid ioctls: OK
11083 11:09:47.444824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11084 11:09:47.445438
11085 11:09:47.446141 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11087 11:09:47.454079 Allow for multiple opens:
11088 11:09:47.462542 <LAVA_SIGNAL_TESTSET STOP>
11089 11:09:47.463357 Received signal: <TESTSET> STOP
11090 11:09:47.463764 Closing test_set Required-ioctls
11091 11:09:47.471864 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11092 11:09:47.472687 Received signal: <TESTSET> START Allow-for-multiple-opens
11093 11:09:47.473086 Starting test_set Allow-for-multiple-opens
11094 11:09:47.475008 test second /dev/video2 open: OK
11095 11:09:47.497065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11096 11:09:47.497903 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11098 11:09:47.500396 test VIDIOC_QUERYCAP: OK
11099 11:09:47.522720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11100 11:09:47.523549 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11102 11:09:47.525421 test VIDIOC_G/S_PRIORITY: OK
11103 11:09:47.547218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11104 11:09:47.548049 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11106 11:09:47.550668 test for unlimited opens: OK
11107 11:09:47.571080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11108 11:09:47.571656
11109 11:09:47.572301 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11111 11:09:47.582113 Debug ioctls:
11112 11:09:47.588434 <LAVA_SIGNAL_TESTSET STOP>
11113 11:09:47.589260 Received signal: <TESTSET> STOP
11114 11:09:47.589649 Closing test_set Allow-for-multiple-opens
11115 11:09:47.597592 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11116 11:09:47.598353 Received signal: <TESTSET> START Debug-ioctls
11117 11:09:47.598746 Starting test_set Debug-ioctls
11118 11:09:47.600586 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11119 11:09:47.623665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11120 11:09:47.624518 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11122 11:09:47.630261 test VIDIOC_LOG_STATUS: OK (Not Supported)
11123 11:09:47.648852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11124 11:09:47.649428
11125 11:09:47.650067 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11127 11:09:47.661186 Input ioctls:
11128 11:09:47.667458 <LAVA_SIGNAL_TESTSET STOP>
11129 11:09:47.668281 Received signal: <TESTSET> STOP
11130 11:09:47.668670 Closing test_set Debug-ioctls
11131 11:09:47.676825 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11132 11:09:47.677659 Received signal: <TESTSET> START Input-ioctls
11133 11:09:47.678083 Starting test_set Input-ioctls
11134 11:09:47.679645 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11135 11:09:47.706073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11136 11:09:47.706891 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11138 11:09:47.709170 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11139 11:09:47.726488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11140 11:09:47.727390 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11142 11:09:47.733278 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11143 11:09:47.751388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11144 11:09:47.752213 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11146 11:09:47.757906 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11147 11:09:47.776883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11148 11:09:47.777613 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11150 11:09:47.780366 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11151 11:09:47.802527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11152 11:09:47.803353 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11154 11:09:47.809177 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11155 11:09:47.830919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11156 11:09:47.831767 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11158 11:09:47.833703 Inputs: 0 Audio Inputs: 0 Tuners: 0
11159 11:09:47.840292
11160 11:09:47.859528 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11161 11:09:47.885175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11162 11:09:47.886061 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11164 11:09:47.891920 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11165 11:09:47.911258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11166 11:09:47.912090 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11168 11:09:47.917409 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11169 11:09:47.935257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11170 11:09:47.936066 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11172 11:09:47.941503 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11173 11:09:47.959905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11174 11:09:47.960731 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11176 11:09:47.966778 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11177 11:09:47.986171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11178 11:09:47.986741
11179 11:09:47.987372 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11181 11:09:48.003654 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11182 11:09:48.025764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11183 11:09:48.026648 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11185 11:09:48.032125 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11186 11:09:48.055491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11187 11:09:48.056308 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11189 11:09:48.058733 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11190 11:09:48.076482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11191 11:09:48.077302 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11193 11:09:48.079572 test VIDIOC_G/S_EDID: OK (Not Supported)
11194 11:09:48.104006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11195 11:09:48.104557
11196 11:09:48.105191 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11198 11:09:48.119925 Control ioctls:
11199 11:09:48.125926 <LAVA_SIGNAL_TESTSET STOP>
11200 11:09:48.126784 Received signal: <TESTSET> STOP
11201 11:09:48.127261 Closing test_set Input-ioctls
11202 11:09:48.135784 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11203 11:09:48.136598 Received signal: <TESTSET> START Control-ioctls
11204 11:09:48.136985 Starting test_set Control-ioctls
11205 11:09:48.138740 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11206 11:09:48.162963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11207 11:09:48.163527 test VIDIOC_QUERYCTRL: OK
11208 11:09:48.164172 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11210 11:09:48.187278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11211 11:09:48.188109 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11213 11:09:48.190079 test VIDIOC_G/S_CTRL: OK
11214 11:09:48.211375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11215 11:09:48.212193 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11217 11:09:48.214156 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11218 11:09:48.240414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11219 11:09:48.241220 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11221 11:09:48.250365 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11222 11:09:48.257314 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11223 11:09:48.286858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11224 11:09:48.287708 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11226 11:09:48.290367 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11227 11:09:48.308600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11228 11:09:48.309436 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11230 11:09:48.312044 Standard Controls: 16 Private Controls: 0
11231 11:09:48.320386
11232 11:09:48.334772 Format ioctls:
11233 11:09:48.340884 <LAVA_SIGNAL_TESTSET STOP>
11234 11:09:48.341865 Received signal: <TESTSET> STOP
11235 11:09:48.342347 Closing test_set Control-ioctls
11236 11:09:48.350730 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11237 11:09:48.351562 Received signal: <TESTSET> START Format-ioctls
11238 11:09:48.351961 Starting test_set Format-ioctls
11239 11:09:48.353791 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11240 11:09:48.380255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11241 11:09:48.381095 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11243 11:09:48.383397 test VIDIOC_G/S_PARM: OK
11244 11:09:48.401372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11245 11:09:48.402239 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11247 11:09:48.404698 test VIDIOC_G_FBUF: OK (Not Supported)
11248 11:09:48.428387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11249 11:09:48.429334 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11251 11:09:48.431802 test VIDIOC_G_FMT: OK
11252 11:09:48.451921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11253 11:09:48.452752 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11255 11:09:48.455380 test VIDIOC_TRY_FMT: OK
11256 11:09:48.476421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11257 11:09:48.477244 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11259 11:09:48.486114 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11260 11:09:48.486678 test VIDIOC_S_FMT: FAIL
11261 11:09:48.510773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11262 11:09:48.511606 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11264 11:09:48.514102 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11265 11:09:48.537318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11266 11:09:48.538147 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11268 11:09:48.539959 test Cropping: OK
11269 11:09:48.566123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11270 11:09:48.566962 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11272 11:09:48.568875 test Composing: OK (Not Supported)
11273 11:09:48.596845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11274 11:09:48.597680 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11276 11:09:48.600051 test Scaling: OK (Not Supported)
11277 11:09:48.622533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11278 11:09:48.623101
11279 11:09:48.623741 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11281 11:09:48.633368 Codec ioctls:
11282 11:09:48.641055 <LAVA_SIGNAL_TESTSET STOP>
11283 11:09:48.641881 Received signal: <TESTSET> STOP
11284 11:09:48.642291 Closing test_set Format-ioctls
11285 11:09:48.650557 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11286 11:09:48.651390 Received signal: <TESTSET> START Codec-ioctls
11287 11:09:48.651787 Starting test_set Codec-ioctls
11288 11:09:48.653257 test VIDIOC_(TRY_)ENCODER_CMD: OK
11289 11:09:48.677323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11290 11:09:48.678162 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11292 11:09:48.683808 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11293 11:09:48.704355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11294 11:09:48.705161 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11296 11:09:48.711237 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11297 11:09:48.730761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11298 11:09:48.731328
11299 11:09:48.731959 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11301 11:09:48.741413 Buffer ioctls:
11302 11:09:48.748515 <LAVA_SIGNAL_TESTSET STOP>
11303 11:09:48.749344 Received signal: <TESTSET> STOP
11304 11:09:48.749748 Closing test_set Codec-ioctls
11305 11:09:48.757790 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11306 11:09:48.758660 Received signal: <TESTSET> START Buffer-ioctls
11307 11:09:48.759059 Starting test_set Buffer-ioctls
11308 11:09:48.761064 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11309 11:09:48.786255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11310 11:09:48.786805 test VIDIOC_EXPBUF: OK
11311 11:09:48.787444 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11313 11:09:48.808797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11314 11:09:48.809628 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11316 11:09:48.812080 test Requests: OK (Not Supported)
11317 11:09:48.835462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11318 11:09:48.836029
11319 11:09:48.836666 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11321 11:09:48.846063 Test input 0:
11322 11:09:48.855956
11323 11:09:48.866674 Streaming ioctls:
11324 11:09:48.873480 <LAVA_SIGNAL_TESTSET STOP>
11325 11:09:48.874337 Received signal: <TESTSET> STOP
11326 11:09:48.874725 Closing test_set Buffer-ioctls
11327 11:09:48.883123 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11328 11:09:48.884010 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11329 11:09:48.884414 Starting test_set Streaming-ioctls_Test-input-0
11330 11:09:48.886161 test read/write: OK (Not Supported)
11331 11:09:48.908293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11332 11:09:48.909132 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11334 11:09:48.914685 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11335 11:09:48.928783 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11336 11:09:48.937321 test blocking wait: FAIL
11337 11:09:48.964340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11338 11:09:48.965173 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11340 11:09:48.970932 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11341 11:09:48.977987 test MMAP (select): FAIL
11342 11:09:49.006811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11343 11:09:49.007671 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11345 11:09:49.013077 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11346 11:09:49.018544 test MMAP (epoll): FAIL
11347 11:09:49.045106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11348 11:09:49.045965 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11350 11:09:49.055063 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11351 11:09:49.061679 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11352 11:09:49.066793 test USERPTR (select): FAIL
11353 11:09:49.097205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11354 11:09:49.098061 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11356 11:09:49.103448 test DMABUF: Cannot test, specify --expbuf-device
11357 11:09:49.103915
11358 11:09:49.125759 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11359 11:09:49.131185 <LAVA_TEST_RUNNER EXIT>
11360 11:09:49.132058 ok: lava_test_shell seems to have completed
11361 11:09:49.132462 Marking unfinished test run as failed
11363 11:09:49.137439 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11364 11:09:49.138100 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11365 11:09:49.138565 end: 3 lava-test-retry (duration 00:00:03) [common]
11366 11:09:49.139048 start: 4 finalize (timeout 00:08:07) [common]
11367 11:09:49.139539 start: 4.1 power-off (timeout 00:00:30) [common]
11368 11:09:49.140350 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11369 11:09:49.229350 >> Command sent successfully.
11370 11:09:49.240703 Returned 0 in 0 seconds
11371 11:09:49.342203 end: 4.1 power-off (duration 00:00:00) [common]
11373 11:09:49.343743 start: 4.2 read-feedback (timeout 00:08:07) [common]
11374 11:09:49.345190 Listened to connection for namespace 'common' for up to 1s
11375 11:09:50.345736 Finalising connection for namespace 'common'
11376 11:09:50.346464 Disconnecting from shell: Finalise
11377 11:09:50.346879 / #
11378 11:09:50.447953 end: 4.2 read-feedback (duration 00:00:01) [common]
11379 11:09:50.448650 end: 4 finalize (duration 00:00:01) [common]
11380 11:09:50.449280 Cleaning after the job
11381 11:09:50.449801 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925657/tftp-deploy-8ly4v_t3/ramdisk
11382 11:09:50.471490 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925657/tftp-deploy-8ly4v_t3/kernel
11383 11:09:50.489297 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925657/tftp-deploy-8ly4v_t3/dtb
11384 11:09:50.489594 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12925657/tftp-deploy-8ly4v_t3/modules
11385 11:09:50.498455 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12925657
11386 11:09:50.555224 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12925657
11387 11:09:50.555407 Job finished correctly