Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
- Kernel Errors: 27
- Boot result: PASS
1 23:17:51.899409 lava-dispatcher, installed at version: 2024.01
2 23:17:51.899622 start: 0 validate
3 23:17:51.899754 Start time: 2024-04-03 23:17:51.899746+00:00 (UTC)
4 23:17:51.899878 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:17:51.900011 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 23:17:52.160877 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:17:52.161607 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:17:54.921867 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:17:54.922138 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:17:55.188420 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:17:55.188643 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:17:59.453880 validate duration: 7.55
14 23:17:59.454159 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:17:59.454257 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:17:59.454343 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:17:59.454509 Not decompressing ramdisk as can be used compressed.
18 23:17:59.454591 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 23:17:59.454651 saving as /var/lib/lava/dispatcher/tmp/13248486/tftp-deploy-7v0d_pg_/ramdisk/rootfs.cpio.gz
20 23:17:59.454711 total size: 8181887 (7 MB)
21 23:17:59.455987 progress 0 % (0 MB)
22 23:17:59.458471 progress 5 % (0 MB)
23 23:17:59.460691 progress 10 % (0 MB)
24 23:17:59.462979 progress 15 % (1 MB)
25 23:17:59.465092 progress 20 % (1 MB)
26 23:17:59.467365 progress 25 % (1 MB)
27 23:17:59.469539 progress 30 % (2 MB)
28 23:17:59.471846 progress 35 % (2 MB)
29 23:17:59.474112 progress 40 % (3 MB)
30 23:17:59.476511 progress 45 % (3 MB)
31 23:17:59.478877 progress 50 % (3 MB)
32 23:17:59.481212 progress 55 % (4 MB)
33 23:17:59.483337 progress 60 % (4 MB)
34 23:17:59.485570 progress 65 % (5 MB)
35 23:17:59.487727 progress 70 % (5 MB)
36 23:17:59.490018 progress 75 % (5 MB)
37 23:17:59.492224 progress 80 % (6 MB)
38 23:17:59.494574 progress 85 % (6 MB)
39 23:17:59.496696 progress 90 % (7 MB)
40 23:17:59.499013 progress 95 % (7 MB)
41 23:17:59.501121 progress 100 % (7 MB)
42 23:17:59.501331 7 MB downloaded in 0.05 s (167.37 MB/s)
43 23:17:59.501483 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:17:59.501748 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:17:59.501834 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:17:59.501915 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:17:59.502055 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:17:59.502122 saving as /var/lib/lava/dispatcher/tmp/13248486/tftp-deploy-7v0d_pg_/kernel/Image
50 23:17:59.502180 total size: 54286848 (51 MB)
51 23:17:59.502238 No compression specified
52 23:17:59.503491 progress 0 % (0 MB)
53 23:17:59.517736 progress 5 % (2 MB)
54 23:17:59.532193 progress 10 % (5 MB)
55 23:17:59.546472 progress 15 % (7 MB)
56 23:17:59.560808 progress 20 % (10 MB)
57 23:17:59.575200 progress 25 % (12 MB)
58 23:17:59.589543 progress 30 % (15 MB)
59 23:17:59.603764 progress 35 % (18 MB)
60 23:17:59.617900 progress 40 % (20 MB)
61 23:17:59.632154 progress 45 % (23 MB)
62 23:17:59.646404 progress 50 % (25 MB)
63 23:17:59.660699 progress 55 % (28 MB)
64 23:17:59.675550 progress 60 % (31 MB)
65 23:17:59.689862 progress 65 % (33 MB)
66 23:17:59.704415 progress 70 % (36 MB)
67 23:17:59.718520 progress 75 % (38 MB)
68 23:17:59.732736 progress 80 % (41 MB)
69 23:17:59.746890 progress 85 % (44 MB)
70 23:17:59.761023 progress 90 % (46 MB)
71 23:17:59.774967 progress 95 % (49 MB)
72 23:17:59.788889 progress 100 % (51 MB)
73 23:17:59.789178 51 MB downloaded in 0.29 s (180.39 MB/s)
74 23:17:59.789337 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:17:59.789573 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:17:59.789663 start: 1.3 download-retry (timeout 00:10:00) [common]
78 23:17:59.789751 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 23:17:59.789890 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:17:59.789957 saving as /var/lib/lava/dispatcher/tmp/13248486/tftp-deploy-7v0d_pg_/dtb/mt8192-asurada-spherion-r0.dtb
81 23:17:59.790017 total size: 47230 (0 MB)
82 23:17:59.790076 No compression specified
83 23:17:59.791284 progress 69 % (0 MB)
84 23:17:59.791562 progress 100 % (0 MB)
85 23:17:59.791716 0 MB downloaded in 0.00 s (26.55 MB/s)
86 23:17:59.791839 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:17:59.792056 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:17:59.792139 start: 1.4 download-retry (timeout 00:10:00) [common]
90 23:17:59.792220 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 23:17:59.792332 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:17:59.792399 saving as /var/lib/lava/dispatcher/tmp/13248486/tftp-deploy-7v0d_pg_/modules/modules.tar
93 23:17:59.792457 total size: 8629908 (8 MB)
94 23:17:59.792516 Using unxz to decompress xz
95 23:17:59.796789 progress 0 % (0 MB)
96 23:17:59.816234 progress 5 % (0 MB)
97 23:17:59.841015 progress 10 % (0 MB)
98 23:17:59.865205 progress 15 % (1 MB)
99 23:17:59.888853 progress 20 % (1 MB)
100 23:17:59.913922 progress 25 % (2 MB)
101 23:17:59.940154 progress 30 % (2 MB)
102 23:17:59.964274 progress 35 % (2 MB)
103 23:17:59.989907 progress 40 % (3 MB)
104 23:18:00.013948 progress 45 % (3 MB)
105 23:18:00.039335 progress 50 % (4 MB)
106 23:18:00.064469 progress 55 % (4 MB)
107 23:18:00.093152 progress 60 % (4 MB)
108 23:18:00.118814 progress 65 % (5 MB)
109 23:18:00.144184 progress 70 % (5 MB)
110 23:18:00.169171 progress 75 % (6 MB)
111 23:18:00.194716 progress 80 % (6 MB)
112 23:18:00.221085 progress 85 % (7 MB)
113 23:18:00.249870 progress 90 % (7 MB)
114 23:18:00.279961 progress 95 % (7 MB)
115 23:18:00.306682 progress 100 % (8 MB)
116 23:18:00.312093 8 MB downloaded in 0.52 s (15.84 MB/s)
117 23:18:00.312351 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:18:00.312617 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:18:00.312707 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:18:00.312803 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:18:00.312883 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:18:00.312972 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:18:00.313199 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl
125 23:18:00.313338 makedir: /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin
126 23:18:00.313441 makedir: /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/tests
127 23:18:00.313539 makedir: /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/results
128 23:18:00.313657 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-add-keys
129 23:18:00.313868 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-add-sources
130 23:18:00.314029 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-background-process-start
131 23:18:00.314163 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-background-process-stop
132 23:18:00.314290 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-common-functions
133 23:18:00.314437 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-echo-ipv4
134 23:18:00.314582 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-install-packages
135 23:18:00.314707 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-installed-packages
136 23:18:00.314832 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-os-build
137 23:18:00.314958 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-probe-channel
138 23:18:00.315091 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-probe-ip
139 23:18:00.315215 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-target-ip
140 23:18:00.315341 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-target-mac
141 23:18:00.315492 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-target-storage
142 23:18:00.315664 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-test-case
143 23:18:00.315796 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-test-event
144 23:18:00.315922 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-test-feedback
145 23:18:00.316047 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-test-raise
146 23:18:00.316174 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-test-reference
147 23:18:00.316306 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-test-runner
148 23:18:00.316430 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-test-set
149 23:18:00.316555 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-test-shell
150 23:18:00.316682 Updating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-install-packages (oe)
151 23:18:00.316842 Updating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/bin/lava-installed-packages (oe)
152 23:18:00.316968 Creating /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/environment
153 23:18:00.317068 LAVA metadata
154 23:18:00.317144 - LAVA_JOB_ID=13248486
155 23:18:00.317216 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:18:00.317368 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:18:00.317456 skipped lava-vland-overlay
158 23:18:00.317530 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:18:00.317608 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:18:00.317710 skipped lava-multinode-overlay
161 23:18:00.317841 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:18:00.317946 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:18:00.318022 Loading test definitions
164 23:18:00.318121 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:18:00.318195 Using /lava-13248486 at stage 0
166 23:18:00.318582 uuid=13248486_1.5.2.3.1 testdef=None
167 23:18:00.318673 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:18:00.318765 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:18:00.319311 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:18:00.319608 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:18:00.320282 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:18:00.320509 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:18:00.321180 runner path: /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/0/tests/0_dmesg test_uuid 13248486_1.5.2.3.1
176 23:18:00.321382 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:18:00.321590 Creating lava-test-runner.conf files
179 23:18:00.321660 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13248486/lava-overlay-ci36k9wl/lava-13248486/0 for stage 0
180 23:18:00.321749 - 0_dmesg
181 23:18:00.321852 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:18:00.321935 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:18:00.329543 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:18:00.329662 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:18:00.329751 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:18:00.329839 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:18:00.329927 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:18:00.582827 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 23:18:00.583226 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
190 23:18:00.583344 extracting modules file /var/lib/lava/dispatcher/tmp/13248486/tftp-deploy-7v0d_pg_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248486/extract-overlay-ramdisk-jgj5_w3w/ramdisk
191 23:18:00.807101 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:18:00.807287 start: 1.5.5 apply-overlay-tftp (timeout 00:09:59) [common]
193 23:18:00.807384 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248486/compress-overlay-3euqovuo/overlay-1.5.2.4.tar.gz to ramdisk
194 23:18:00.807453 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248486/compress-overlay-3euqovuo/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13248486/extract-overlay-ramdisk-jgj5_w3w/ramdisk
195 23:18:00.814089 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:18:00.814221 start: 1.5.6 configure-preseed-file (timeout 00:09:59) [common]
197 23:18:00.814341 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:18:00.814491 start: 1.5.7 compress-ramdisk (timeout 00:09:59) [common]
199 23:18:00.814572 Building ramdisk /var/lib/lava/dispatcher/tmp/13248486/extract-overlay-ramdisk-jgj5_w3w/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13248486/extract-overlay-ramdisk-jgj5_w3w/ramdisk
200 23:18:01.233703 >> 145375 blocks
201 23:18:03.557042 rename /var/lib/lava/dispatcher/tmp/13248486/extract-overlay-ramdisk-jgj5_w3w/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13248486/tftp-deploy-7v0d_pg_/ramdisk/ramdisk.cpio.gz
202 23:18:03.557502 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 23:18:03.557621 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
204 23:18:03.557724 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
205 23:18:03.557835 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13248486/tftp-deploy-7v0d_pg_/kernel/Image'
206 23:18:17.311243 Returned 0 in 13 seconds
207 23:18:17.411989 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13248486/tftp-deploy-7v0d_pg_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13248486/tftp-deploy-7v0d_pg_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13248486/tftp-deploy-7v0d_pg_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13248486/tftp-deploy-7v0d_pg_/kernel/image.itb
208 23:18:17.850645 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:18:17.851125 output: Created: Thu Apr 4 00:18:17 2024
210 23:18:17.851237 output: Image 0 (kernel-1)
211 23:18:17.851341 output: Description:
212 23:18:17.851435 output: Created: Thu Apr 4 00:18:17 2024
213 23:18:17.851525 output: Type: Kernel Image
214 23:18:17.851610 output: Compression: lzma compressed
215 23:18:17.851695 output: Data Size: 12907270 Bytes = 12604.76 KiB = 12.31 MiB
216 23:18:17.851787 output: Architecture: AArch64
217 23:18:17.851875 output: OS: Linux
218 23:18:17.851966 output: Load Address: 0x00000000
219 23:18:17.852056 output: Entry Point: 0x00000000
220 23:18:17.852160 output: Hash algo: crc32
221 23:18:17.852260 output: Hash value: d7c9dcc1
222 23:18:17.852355 output: Image 1 (fdt-1)
223 23:18:17.852452 output: Description: mt8192-asurada-spherion-r0
224 23:18:17.852554 output: Created: Thu Apr 4 00:18:17 2024
225 23:18:17.852649 output: Type: Flat Device Tree
226 23:18:17.852746 output: Compression: uncompressed
227 23:18:17.852852 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
228 23:18:17.852952 output: Architecture: AArch64
229 23:18:17.853047 output: Hash algo: crc32
230 23:18:17.853134 output: Hash value: 4bf0d1ac
231 23:18:17.853222 output: Image 2 (ramdisk-1)
232 23:18:17.853307 output: Description: unavailable
233 23:18:17.853397 output: Created: Thu Apr 4 00:18:17 2024
234 23:18:17.853489 output: Type: RAMDisk Image
235 23:18:17.853580 output: Compression: Unknown Compression
236 23:18:17.853671 output: Data Size: 21383185 Bytes = 20882.02 KiB = 20.39 MiB
237 23:18:17.853761 output: Architecture: AArch64
238 23:18:17.853850 output: OS: Linux
239 23:18:17.853932 output: Load Address: unavailable
240 23:18:17.854012 output: Entry Point: unavailable
241 23:18:17.854096 output: Hash algo: crc32
242 23:18:17.854184 output: Hash value: 812242cd
243 23:18:17.854271 output: Default Configuration: 'conf-1'
244 23:18:17.854369 output: Configuration 0 (conf-1)
245 23:18:17.854473 output: Description: mt8192-asurada-spherion-r0
246 23:18:17.854566 output: Kernel: kernel-1
247 23:18:17.854657 output: Init Ramdisk: ramdisk-1
248 23:18:17.854748 output: FDT: fdt-1
249 23:18:17.854838 output: Loadables: kernel-1
250 23:18:17.854927 output:
251 23:18:17.855216 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 23:18:17.855368 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 23:18:17.855522 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 23:18:17.855663 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
255 23:18:17.855793 No LXC device requested
256 23:18:17.855914 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:18:17.856036 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
258 23:18:17.856170 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:18:17.856285 Checking files for TFTP limit of 4294967296 bytes.
260 23:18:17.857008 end: 1 tftp-deploy (duration 00:00:18) [common]
261 23:18:17.857158 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:18:17.857300 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:18:17.857485 substitutions:
264 23:18:17.857587 - {DTB}: 13248486/tftp-deploy-7v0d_pg_/dtb/mt8192-asurada-spherion-r0.dtb
265 23:18:17.857686 - {INITRD}: 13248486/tftp-deploy-7v0d_pg_/ramdisk/ramdisk.cpio.gz
266 23:18:17.857777 - {KERNEL}: 13248486/tftp-deploy-7v0d_pg_/kernel/Image
267 23:18:17.857863 - {LAVA_MAC}: None
268 23:18:17.857949 - {PRESEED_CONFIG}: None
269 23:18:17.858036 - {PRESEED_LOCAL}: None
270 23:18:17.858122 - {RAMDISK}: 13248486/tftp-deploy-7v0d_pg_/ramdisk/ramdisk.cpio.gz
271 23:18:17.858216 - {ROOT_PART}: None
272 23:18:17.858308 - {ROOT}: None
273 23:18:17.858415 - {SERVER_IP}: 192.168.201.1
274 23:18:17.858512 - {TEE}: None
275 23:18:17.858604 Parsed boot commands:
276 23:18:17.858694 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:18:17.858945 Parsed boot commands: tftpboot 192.168.201.1 13248486/tftp-deploy-7v0d_pg_/kernel/image.itb 13248486/tftp-deploy-7v0d_pg_/kernel/cmdline
278 23:18:17.859084 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:18:17.859215 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:18:17.859355 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:18:17.859491 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:18:17.859603 Not connected, no need to disconnect.
283 23:18:17.859715 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:18:17.859835 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:18:17.859941 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 23:18:17.864945 Setting prompt string to ['lava-test: # ']
287 23:18:17.865460 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:18:17.865613 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:18:17.865763 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:18:17.865902 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:18:17.866205 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 23:18:22.997669 >> Command sent successfully.
293 23:18:23.000114 Returned 0 in 5 seconds
294 23:18:23.100505 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:18:23.100837 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:18:23.100934 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:18:23.101034 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:18:23.101128 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:18:23.101228 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:18:23.101613 [Enter `^Ec?' for help]
302 23:18:23.276310
303 23:18:23.276477
304 23:18:23.276580 F0: 102B 0000
305 23:18:23.276674
306 23:18:23.276770 F3: 1001 0000 [0200]
307 23:18:23.276867
308 23:18:23.280227 F3: 1001 0000
309 23:18:23.280332
310 23:18:23.280424 F7: 102D 0000
311 23:18:23.280513
312 23:18:23.280601 F1: 0000 0000
313 23:18:23.280686
314 23:18:23.284116 V0: 0000 0000 [0001]
315 23:18:23.284220
316 23:18:23.284320 00: 0007 8000
317 23:18:23.284454
318 23:18:23.287980 01: 0000 0000
319 23:18:23.288083
320 23:18:23.288175 BP: 0C00 0209 [0000]
321 23:18:23.288264
322 23:18:23.288352 G0: 1182 0000
323 23:18:23.288440
324 23:18:23.291450 EC: 0000 0021 [4000]
325 23:18:23.291540
326 23:18:23.291605 S7: 0000 0000 [0000]
327 23:18:23.295371
328 23:18:23.295453 CC: 0000 0000 [0001]
329 23:18:23.295518
330 23:18:23.295578 T0: 0000 0040 [010F]
331 23:18:23.298680
332 23:18:23.298762 Jump to BL
333 23:18:23.298826
334 23:18:23.323303
335 23:18:23.323392
336 23:18:23.323458
337 23:18:23.330781 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 23:18:23.334379 ARM64: Exception handlers installed.
339 23:18:23.338249 ARM64: Testing exception
340 23:18:23.341564 ARM64: Done test exception
341 23:18:23.348329 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 23:18:23.359877 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 23:18:23.366538 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 23:18:23.373274 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 23:18:23.383657 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 23:18:23.390087 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 23:18:23.400947 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 23:18:23.407324 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 23:18:23.425971 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 23:18:23.429718 WDT: Last reset was cold boot
351 23:18:23.433129 SPI1(PAD0) initialized at 2873684 Hz
352 23:18:23.436552 SPI5(PAD0) initialized at 992727 Hz
353 23:18:23.439315 VBOOT: Loading verstage.
354 23:18:23.446013 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 23:18:23.449208 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 23:18:23.452773 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 23:18:23.456065 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 23:18:23.463369 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 23:18:23.469721 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 23:18:23.480635 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
361 23:18:23.480751
362 23:18:23.480843
363 23:18:23.490865 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 23:18:23.494609 ARM64: Exception handlers installed.
365 23:18:23.497695 ARM64: Testing exception
366 23:18:23.497778 ARM64: Done test exception
367 23:18:23.504715 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 23:18:23.507927 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 23:18:23.523064 Probing TPM: . done!
370 23:18:23.523148 TPM ready after 0 ms
371 23:18:23.530311 Connected to device vid:did:rid of 1ae0:0028:00
372 23:18:23.536991 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 23:18:23.594589 Initialized TPM device CR50 revision 0
374 23:18:23.606469 tlcl_send_startup: Startup return code is 0
375 23:18:23.606585 TPM: setup succeeded
376 23:18:23.617591 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 23:18:23.626417 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 23:18:23.639049 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 23:18:23.648955 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 23:18:23.652526 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 23:18:23.656499 in-header: 03 07 00 00 08 00 00 00
382 23:18:23.659875 in-data: aa e4 47 04 13 02 00 00
383 23:18:23.663637 Chrome EC: UHEPI supported
384 23:18:23.671278 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 23:18:23.674857 in-header: 03 ad 00 00 08 00 00 00
386 23:18:23.678411 in-data: 00 20 20 08 00 00 00 00
387 23:18:23.678509 Phase 1
388 23:18:23.682298 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 23:18:23.686291 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 23:18:23.693183 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 23:18:23.696877 Recovery requested (1009000e)
392 23:18:23.704976 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 23:18:23.710700 tlcl_extend: response is 0
394 23:18:23.719924 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 23:18:23.725608 tlcl_extend: response is 0
396 23:18:23.731831 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 23:18:23.751912 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
398 23:18:23.759165 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 23:18:23.759276
400 23:18:23.759368
401 23:18:23.769662 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 23:18:23.773581 ARM64: Exception handlers installed.
403 23:18:23.773685 ARM64: Testing exception
404 23:18:23.776905 ARM64: Done test exception
405 23:18:23.797607 pmic_efuse_setting: Set efuses in 11 msecs
406 23:18:23.801396 pmwrap_interface_init: Select PMIF_VLD_RDY
407 23:18:23.808097 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 23:18:23.811223 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 23:18:23.818483 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 23:18:23.821702 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 23:18:23.825951 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 23:18:23.829611 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 23:18:23.836269 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 23:18:23.841256 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 23:18:23.844118 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 23:18:23.851033 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 23:18:23.854547 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 23:18:23.858306 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 23:18:23.861903 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 23:18:23.869994 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 23:18:23.876882 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 23:18:23.880978 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 23:18:23.888019 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 23:18:23.892084 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 23:18:23.899293 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 23:18:23.902378 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 23:18:23.909874 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 23:18:23.913758 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 23:18:23.921474 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 23:18:23.924715 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 23:18:23.932300 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 23:18:23.935895 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 23:18:23.943512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 23:18:23.947841 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 23:18:23.950940 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 23:18:23.958123 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 23:18:23.961807 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 23:18:23.965776 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 23:18:23.972849 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 23:18:23.976926 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 23:18:23.980024 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 23:18:23.987746 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 23:18:23.991145 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 23:18:23.998723 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 23:18:24.002455 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 23:18:24.006311 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 23:18:24.009888 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 23:18:24.013517 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 23:18:24.017212 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 23:18:24.024453 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 23:18:24.028450 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 23:18:24.032446 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 23:18:24.036005 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 23:18:24.040098 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 23:18:24.043501 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 23:18:24.047684 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 23:18:24.050995 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 23:18:24.062201 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 23:18:24.070308 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 23:18:24.074029 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 23:18:24.080698 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 23:18:24.091953 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 23:18:24.095445 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 23:18:24.099128 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:18:24.102409 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 23:18:24.110804 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x2a
467 23:18:24.114588 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 23:18:24.123185 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 23:18:24.126586 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 23:18:24.135244 [RTC]rtc_get_frequency_meter,154: input=15, output=790
471 23:18:24.144771 [RTC]rtc_get_frequency_meter,154: input=23, output=977
472 23:18:24.154289 [RTC]rtc_get_frequency_meter,154: input=19, output=884
473 23:18:24.163612 [RTC]rtc_get_frequency_meter,154: input=17, output=837
474 23:18:24.173558 [RTC]rtc_get_frequency_meter,154: input=16, output=814
475 23:18:24.182687 [RTC]rtc_get_frequency_meter,154: input=15, output=790
476 23:18:24.192873 [RTC]rtc_get_frequency_meter,154: input=16, output=814
477 23:18:24.196403 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 23:18:24.203489 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 23:18:24.207001 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 23:18:24.210659 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 23:18:24.214596 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 23:18:24.218536 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 23:18:24.222294 ADC[4]: Raw value=901697 ID=7
484 23:18:24.225865 ADC[3]: Raw value=213336 ID=1
485 23:18:24.225951 RAM Code: 0x71
486 23:18:24.229524 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 23:18:24.233839 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 23:18:24.244344 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 23:18:24.251786 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 23:18:24.251898 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 23:18:24.255535 in-header: 03 07 00 00 08 00 00 00
492 23:18:24.259664 in-data: aa e4 47 04 13 02 00 00
493 23:18:24.263187 Chrome EC: UHEPI supported
494 23:18:24.270519 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 23:18:24.274262 in-header: 03 ed 00 00 08 00 00 00
496 23:18:24.274353 in-data: 80 20 60 08 00 00 00 00
497 23:18:24.278065 MRC: failed to locate region type 0.
498 23:18:24.285496 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 23:18:24.289138 DRAM-K: Running full calibration
500 23:18:24.296591 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 23:18:24.296679 header.status = 0x0
502 23:18:24.300287 header.version = 0x6 (expected: 0x6)
503 23:18:24.303841 header.size = 0xd00 (expected: 0xd00)
504 23:18:24.303925 header.flags = 0x0
505 23:18:24.310819 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 23:18:24.329767 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
507 23:18:24.337130 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 23:18:24.341036 dram_init: ddr_geometry: 2
509 23:18:24.341120 [EMI] MDL number = 2
510 23:18:24.344596 [EMI] Get MDL freq = 0
511 23:18:24.344682 dram_init: ddr_type: 0
512 23:18:24.348402 is_discrete_lpddr4: 1
513 23:18:24.351923 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 23:18:24.352006
515 23:18:24.352071
516 23:18:24.352131 [Bian_co] ETT version 0.0.0.1
517 23:18:24.359333 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 23:18:24.359418
519 23:18:24.362935 dramc_set_vcore_voltage set vcore to 650000
520 23:18:24.363017 Read voltage for 800, 4
521 23:18:24.366781 Vio18 = 0
522 23:18:24.366865 Vcore = 650000
523 23:18:24.366929 Vdram = 0
524 23:18:24.366990 Vddq = 0
525 23:18:24.370656 Vmddr = 0
526 23:18:24.370740 dram_init: config_dvfs: 1
527 23:18:24.378224 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 23:18:24.381809 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 23:18:24.384820 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 23:18:24.388824 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 23:18:24.391642 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 23:18:24.398304 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 23:18:24.398387 MEM_TYPE=3, freq_sel=18
534 23:18:24.401698 sv_algorithm_assistance_LP4_1600
535 23:18:24.405012 ============ PULL DRAM RESETB DOWN ============
536 23:18:24.412218 ========== PULL DRAM RESETB DOWN end =========
537 23:18:24.415300 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 23:18:24.418455 ===================================
539 23:18:24.422148 LPDDR4 DRAM CONFIGURATION
540 23:18:24.425506 ===================================
541 23:18:24.425589 EX_ROW_EN[0] = 0x0
542 23:18:24.428944 EX_ROW_EN[1] = 0x0
543 23:18:24.429025 LP4Y_EN = 0x0
544 23:18:24.432376 WORK_FSP = 0x0
545 23:18:24.432458 WL = 0x2
546 23:18:24.435801 RL = 0x2
547 23:18:24.435884 BL = 0x2
548 23:18:24.439016 RPST = 0x0
549 23:18:24.439099 RD_PRE = 0x0
550 23:18:24.442033 WR_PRE = 0x1
551 23:18:24.442131 WR_PST = 0x0
552 23:18:24.445873 DBI_WR = 0x0
553 23:18:24.445970 DBI_RD = 0x0
554 23:18:24.448824 OTF = 0x1
555 23:18:24.452191 ===================================
556 23:18:24.455662 ===================================
557 23:18:24.455752 ANA top config
558 23:18:24.459238 ===================================
559 23:18:24.462588 DLL_ASYNC_EN = 0
560 23:18:24.465491 ALL_SLAVE_EN = 1
561 23:18:24.469139 NEW_RANK_MODE = 1
562 23:18:24.469231 DLL_IDLE_MODE = 1
563 23:18:24.472368 LP45_APHY_COMB_EN = 1
564 23:18:24.476099 TX_ODT_DIS = 1
565 23:18:24.478892 NEW_8X_MODE = 1
566 23:18:24.482172 ===================================
567 23:18:24.486440 ===================================
568 23:18:24.489680 data_rate = 1600
569 23:18:24.489799 CKR = 1
570 23:18:24.492858 DQ_P2S_RATIO = 8
571 23:18:24.495863 ===================================
572 23:18:24.499165 CA_P2S_RATIO = 8
573 23:18:24.502617 DQ_CA_OPEN = 0
574 23:18:24.506227 DQ_SEMI_OPEN = 0
575 23:18:24.506342 CA_SEMI_OPEN = 0
576 23:18:24.509273 CA_FULL_RATE = 0
577 23:18:24.512532 DQ_CKDIV4_EN = 1
578 23:18:24.515736 CA_CKDIV4_EN = 1
579 23:18:24.519494 CA_PREDIV_EN = 0
580 23:18:24.522783 PH8_DLY = 0
581 23:18:24.522871 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 23:18:24.525845 DQ_AAMCK_DIV = 4
583 23:18:24.529550 CA_AAMCK_DIV = 4
584 23:18:24.533110 CA_ADMCK_DIV = 4
585 23:18:24.535935 DQ_TRACK_CA_EN = 0
586 23:18:24.539391 CA_PICK = 800
587 23:18:24.539479 CA_MCKIO = 800
588 23:18:24.542664 MCKIO_SEMI = 0
589 23:18:24.546246 PLL_FREQ = 3068
590 23:18:24.550171 DQ_UI_PI_RATIO = 32
591 23:18:24.553610 CA_UI_PI_RATIO = 0
592 23:18:24.557710 ===================================
593 23:18:24.557802 ===================================
594 23:18:24.561772 memory_type:LPDDR4
595 23:18:24.561863 GP_NUM : 10
596 23:18:24.565225 SRAM_EN : 1
597 23:18:24.569073 MD32_EN : 0
598 23:18:24.569162 ===================================
599 23:18:24.573008 [ANA_INIT] >>>>>>>>>>>>>>
600 23:18:24.576572 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 23:18:24.580342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 23:18:24.583934 ===================================
603 23:18:24.584019 data_rate = 1600,PCW = 0X7600
604 23:18:24.587854 ===================================
605 23:18:24.591106 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 23:18:24.597383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:18:24.604295 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 23:18:24.607908 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 23:18:24.611075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:18:24.614383 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 23:18:24.617679 [ANA_INIT] flow start
612 23:18:24.617762 [ANA_INIT] PLL >>>>>>>>
613 23:18:24.621469 [ANA_INIT] PLL <<<<<<<<
614 23:18:24.624820 [ANA_INIT] MIDPI >>>>>>>>
615 23:18:24.624902 [ANA_INIT] MIDPI <<<<<<<<
616 23:18:24.627893 [ANA_INIT] DLL >>>>>>>>
617 23:18:24.631193 [ANA_INIT] flow end
618 23:18:24.634995 ============ LP4 DIFF to SE enter ============
619 23:18:24.637788 ============ LP4 DIFF to SE exit ============
620 23:18:24.641376 [ANA_INIT] <<<<<<<<<<<<<
621 23:18:24.644694 [Flow] Enable top DCM control >>>>>
622 23:18:24.648023 [Flow] Enable top DCM control <<<<<
623 23:18:24.651469 Enable DLL master slave shuffle
624 23:18:24.654791 ==============================================================
625 23:18:24.658360 Gating Mode config
626 23:18:24.661931 ==============================================================
627 23:18:24.664564 Config description:
628 23:18:24.675031 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 23:18:24.681947 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 23:18:24.685072 SELPH_MODE 0: By rank 1: By Phase
631 23:18:24.691694 ==============================================================
632 23:18:24.695081 GAT_TRACK_EN = 1
633 23:18:24.698304 RX_GATING_MODE = 2
634 23:18:24.701921 RX_GATING_TRACK_MODE = 2
635 23:18:24.705195 SELPH_MODE = 1
636 23:18:24.705287 PICG_EARLY_EN = 1
637 23:18:24.708554 VALID_LAT_VALUE = 1
638 23:18:24.714923 ==============================================================
639 23:18:24.718366 Enter into Gating configuration >>>>
640 23:18:24.721642 Exit from Gating configuration <<<<
641 23:18:24.725537 Enter into DVFS_PRE_config >>>>>
642 23:18:24.735123 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 23:18:24.738979 Exit from DVFS_PRE_config <<<<<
644 23:18:24.742160 Enter into PICG configuration >>>>
645 23:18:24.745229 Exit from PICG configuration <<<<
646 23:18:24.748620 [RX_INPUT] configuration >>>>>
647 23:18:24.751989 [RX_INPUT] configuration <<<<<
648 23:18:24.755267 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 23:18:24.762146 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 23:18:24.768936 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 23:18:24.772357 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 23:18:24.779467 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 23:18:24.786465 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 23:18:24.789599 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 23:18:24.792770 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 23:18:24.799498 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 23:18:24.802942 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 23:18:24.806742 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 23:18:24.809549 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 23:18:24.812880 ===================================
661 23:18:24.816133 LPDDR4 DRAM CONFIGURATION
662 23:18:24.820194 ===================================
663 23:18:24.823560 EX_ROW_EN[0] = 0x0
664 23:18:24.823643 EX_ROW_EN[1] = 0x0
665 23:18:24.826658 LP4Y_EN = 0x0
666 23:18:24.826744 WORK_FSP = 0x0
667 23:18:24.829353 WL = 0x2
668 23:18:24.829437 RL = 0x2
669 23:18:24.833850 BL = 0x2
670 23:18:24.833932 RPST = 0x0
671 23:18:24.836578 RD_PRE = 0x0
672 23:18:24.836692 WR_PRE = 0x1
673 23:18:24.839884 WR_PST = 0x0
674 23:18:24.839966 DBI_WR = 0x0
675 23:18:24.842948 DBI_RD = 0x0
676 23:18:24.843031 OTF = 0x1
677 23:18:24.846339 ===================================
678 23:18:24.853159 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 23:18:24.856361 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 23:18:24.859441 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 23:18:24.863153 ===================================
682 23:18:24.866444 LPDDR4 DRAM CONFIGURATION
683 23:18:24.870058 ===================================
684 23:18:24.873685 EX_ROW_EN[0] = 0x10
685 23:18:24.873767 EX_ROW_EN[1] = 0x0
686 23:18:24.876399 LP4Y_EN = 0x0
687 23:18:24.876481 WORK_FSP = 0x0
688 23:18:24.880130 WL = 0x2
689 23:18:24.880212 RL = 0x2
690 23:18:24.883161 BL = 0x2
691 23:18:24.883244 RPST = 0x0
692 23:18:24.887054 RD_PRE = 0x0
693 23:18:24.887136 WR_PRE = 0x1
694 23:18:24.889935 WR_PST = 0x0
695 23:18:24.890017 DBI_WR = 0x0
696 23:18:24.893361 DBI_RD = 0x0
697 23:18:24.893443 OTF = 0x1
698 23:18:24.896510 ===================================
699 23:18:24.903381 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 23:18:24.907646 nWR fixed to 40
701 23:18:24.910881 [ModeRegInit_LP4] CH0 RK0
702 23:18:24.910963 [ModeRegInit_LP4] CH0 RK1
703 23:18:24.914086 [ModeRegInit_LP4] CH1 RK0
704 23:18:24.917397 [ModeRegInit_LP4] CH1 RK1
705 23:18:24.917480 match AC timing 13
706 23:18:24.924392 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 23:18:24.927664 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 23:18:24.931105 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 23:18:24.937933 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 23:18:24.940997 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 23:18:24.941165 [EMI DOE] emi_dcm 0
712 23:18:24.947878 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 23:18:24.947960 ==
714 23:18:24.951038 Dram Type= 6, Freq= 0, CH_0, rank 0
715 23:18:24.954678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 23:18:24.954761 ==
717 23:18:24.961967 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 23:18:24.964646 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 23:18:24.975058 [CA 0] Center 37 (7~68) winsize 62
720 23:18:24.978340 [CA 1] Center 37 (6~68) winsize 63
721 23:18:24.981637 [CA 2] Center 35 (5~66) winsize 62
722 23:18:24.985066 [CA 3] Center 35 (5~65) winsize 61
723 23:18:24.988714 [CA 4] Center 34 (3~65) winsize 63
724 23:18:24.991902 [CA 5] Center 33 (3~64) winsize 62
725 23:18:24.991983
726 23:18:24.994901 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 23:18:24.994983
728 23:18:24.998746 [CATrainingPosCal] consider 1 rank data
729 23:18:25.001611 u2DelayCellTimex100 = 270/100 ps
730 23:18:25.004927 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 23:18:25.008377 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 23:18:25.012235 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 23:18:25.018428 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
734 23:18:25.021826 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 23:18:25.024930 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 23:18:25.025013
737 23:18:25.028540 CA PerBit enable=1, Macro0, CA PI delay=33
738 23:18:25.028623
739 23:18:25.032084 [CBTSetCACLKResult] CA Dly = 33
740 23:18:25.032166 CS Dly: 5 (0~36)
741 23:18:25.032230 ==
742 23:18:25.035066 Dram Type= 6, Freq= 0, CH_0, rank 1
743 23:18:25.041862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 23:18:25.041946 ==
745 23:18:25.045403 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 23:18:25.051909 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 23:18:25.061035 [CA 0] Center 37 (6~68) winsize 63
748 23:18:25.064465 [CA 1] Center 37 (7~68) winsize 62
749 23:18:25.067836 [CA 2] Center 35 (5~66) winsize 62
750 23:18:25.071489 [CA 3] Center 35 (4~66) winsize 63
751 23:18:25.074547 [CA 4] Center 34 (4~65) winsize 62
752 23:18:25.077808 [CA 5] Center 33 (3~64) winsize 62
753 23:18:25.077890
754 23:18:25.081358 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 23:18:25.081440
756 23:18:25.084814 [CATrainingPosCal] consider 2 rank data
757 23:18:25.088101 u2DelayCellTimex100 = 270/100 ps
758 23:18:25.091341 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 23:18:25.094655 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 23:18:25.101007 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 23:18:25.104272 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
762 23:18:25.108121 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
763 23:18:25.111113 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 23:18:25.111195
765 23:18:25.114736 CA PerBit enable=1, Macro0, CA PI delay=33
766 23:18:25.114819
767 23:18:25.118365 [CBTSetCACLKResult] CA Dly = 33
768 23:18:25.118494 CS Dly: 6 (0~38)
769 23:18:25.118560
770 23:18:25.121038 ----->DramcWriteLeveling(PI) begin...
771 23:18:25.124644 ==
772 23:18:25.128057 Dram Type= 6, Freq= 0, CH_0, rank 0
773 23:18:25.131597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 23:18:25.131681 ==
775 23:18:25.135403 Write leveling (Byte 0): 29 => 29
776 23:18:25.139028 Write leveling (Byte 1): 28 => 28
777 23:18:25.139110 DramcWriteLeveling(PI) end<-----
778 23:18:25.139175
779 23:18:25.139266 ==
780 23:18:25.142587 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:18:25.147086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 23:18:25.147169 ==
783 23:18:25.149673 [Gating] SW mode calibration
784 23:18:25.156506 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 23:18:25.164708 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 23:18:25.168210 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 23:18:25.170816 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 23:18:25.177659 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 23:18:25.180951 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
790 23:18:25.184333 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:18:25.187721 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:18:25.194250 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:18:25.197772 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:18:25.201130 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:18:25.208034 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:18:25.210914 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:18:25.214794 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:18:25.221115 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:18:25.224562 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:18:25.227780 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:18:25.234435 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:18:25.237972 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:18:25.241370 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 23:18:25.247974 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
805 23:18:25.251400 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
806 23:18:25.254698 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:18:25.257747 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:18:25.264961 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:18:25.268204 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:18:25.271391 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:18:25.277967 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 23:18:25.281746 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 23:18:25.284662 0 9 12 | B1->B0 | 2b2b 3232 | 0 1 | (1 1) (1 1)
814 23:18:25.291189 0 9 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
815 23:18:25.294635 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 23:18:25.298377 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 23:18:25.304912 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 23:18:25.308438 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 23:18:25.311904 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 23:18:25.318424 0 10 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
821 23:18:25.321798 0 10 12 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
822 23:18:25.324832 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:18:25.328189 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:18:25.335293 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:18:25.338268 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:18:25.341854 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:18:25.348800 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 23:18:25.352022 0 11 8 | B1->B0 | 2929 2e2e | 0 0 | (0 0) (0 0)
829 23:18:25.355357 0 11 12 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
830 23:18:25.362083 0 11 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
831 23:18:25.365440 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:18:25.368602 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 23:18:25.372244 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 23:18:25.379162 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 23:18:25.381995 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 23:18:25.385384 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 23:18:25.392570 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 23:18:25.396333 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:18:25.398829 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:18:25.405665 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:18:25.409393 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:18:25.412388 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:18:25.419834 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:18:25.422313 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:18:25.426204 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:18:25.429190 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:18:25.436585 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:18:25.439232 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:18:25.443100 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:18:25.449321 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:18:25.453079 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 23:18:25.456421 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 23:18:25.463247 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
854 23:18:25.466334 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 23:18:25.469844 Total UI for P1: 0, mck2ui 16
856 23:18:25.472998 best dqsien dly found for B0: ( 0, 14, 10)
857 23:18:25.476576 Total UI for P1: 0, mck2ui 16
858 23:18:25.479957 best dqsien dly found for B1: ( 0, 14, 10)
859 23:18:25.483096 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
860 23:18:25.486526 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 23:18:25.486608
862 23:18:25.489745 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 23:18:25.492935 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 23:18:25.496313 [Gating] SW calibration Done
865 23:18:25.496421 ==
866 23:18:25.499689 Dram Type= 6, Freq= 0, CH_0, rank 0
867 23:18:25.503144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 23:18:25.503227 ==
869 23:18:25.506803 RX Vref Scan: 0
870 23:18:25.506883
871 23:18:25.510004 RX Vref 0 -> 0, step: 1
872 23:18:25.510085
873 23:18:25.510149 RX Delay -130 -> 252, step: 16
874 23:18:25.516496 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 23:18:25.520193 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 23:18:25.523317 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 23:18:25.526963 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
878 23:18:25.530284 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 23:18:25.533621 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
880 23:18:25.540013 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
881 23:18:25.543391 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
882 23:18:25.547077 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
883 23:18:25.550214 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
884 23:18:25.553940 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
885 23:18:25.560258 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 23:18:25.564096 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
887 23:18:25.566915 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
888 23:18:25.570133 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 23:18:25.573619 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
890 23:18:25.577164 ==
891 23:18:25.580487 Dram Type= 6, Freq= 0, CH_0, rank 0
892 23:18:25.583799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 23:18:25.583881 ==
894 23:18:25.583946 DQS Delay:
895 23:18:25.587373 DQS0 = 0, DQS1 = 0
896 23:18:25.587455 DQM Delay:
897 23:18:25.590803 DQM0 = 83, DQM1 = 78
898 23:18:25.590911 DQ Delay:
899 23:18:25.594341 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
900 23:18:25.597411 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
901 23:18:25.600534 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
902 23:18:25.604100 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
903 23:18:25.604183
904 23:18:25.604246
905 23:18:25.604305 ==
906 23:18:25.607533 Dram Type= 6, Freq= 0, CH_0, rank 0
907 23:18:25.610702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 23:18:25.610785 ==
909 23:18:25.610848
910 23:18:25.610907
911 23:18:25.614030 TX Vref Scan disable
912 23:18:25.614111 == TX Byte 0 ==
913 23:18:25.620664 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
914 23:18:25.624089 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
915 23:18:25.627428 == TX Byte 1 ==
916 23:18:25.630487 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
917 23:18:25.634012 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
918 23:18:25.634096 ==
919 23:18:25.637147 Dram Type= 6, Freq= 0, CH_0, rank 0
920 23:18:25.640462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 23:18:25.640546 ==
922 23:18:25.655106 TX Vref=22, minBit 1, minWin=27, winSum=439
923 23:18:25.658184 TX Vref=24, minBit 0, minWin=27, winSum=440
924 23:18:25.661939 TX Vref=26, minBit 5, minWin=27, winSum=447
925 23:18:25.664966 TX Vref=28, minBit 13, minWin=27, winSum=449
926 23:18:25.668783 TX Vref=30, minBit 12, minWin=27, winSum=452
927 23:18:25.674722 TX Vref=32, minBit 3, minWin=27, winSum=451
928 23:18:25.678828 [TxChooseVref] Worse bit 12, Min win 27, Win sum 452, Final Vref 30
929 23:18:25.678912
930 23:18:25.681886 Final TX Range 1 Vref 30
931 23:18:25.681991
932 23:18:25.682104 ==
933 23:18:25.684889 Dram Type= 6, Freq= 0, CH_0, rank 0
934 23:18:25.688198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 23:18:25.688282 ==
936 23:18:25.688347
937 23:18:25.691671
938 23:18:25.691753 TX Vref Scan disable
939 23:18:25.695123 == TX Byte 0 ==
940 23:18:25.698671 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
941 23:18:25.701914 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
942 23:18:25.705444 == TX Byte 1 ==
943 23:18:25.708537 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
944 23:18:25.712025 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
945 23:18:25.712133
946 23:18:25.715708 [DATLAT]
947 23:18:25.715789 Freq=800, CH0 RK0
948 23:18:25.715853
949 23:18:25.718710 DATLAT Default: 0xa
950 23:18:25.718791 0, 0xFFFF, sum = 0
951 23:18:25.722313 1, 0xFFFF, sum = 0
952 23:18:25.722461 2, 0xFFFF, sum = 0
953 23:18:25.725617 3, 0xFFFF, sum = 0
954 23:18:25.725699 4, 0xFFFF, sum = 0
955 23:18:25.728950 5, 0xFFFF, sum = 0
956 23:18:25.729033 6, 0xFFFF, sum = 0
957 23:18:25.732071 7, 0xFFFF, sum = 0
958 23:18:25.732153 8, 0xFFFF, sum = 0
959 23:18:25.735780 9, 0x0, sum = 1
960 23:18:25.735862 10, 0x0, sum = 2
961 23:18:25.739149 11, 0x0, sum = 3
962 23:18:25.739231 12, 0x0, sum = 4
963 23:18:25.742352 best_step = 10
964 23:18:25.742491
965 23:18:25.742586 ==
966 23:18:25.745546 Dram Type= 6, Freq= 0, CH_0, rank 0
967 23:18:25.749157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 23:18:25.749243 ==
969 23:18:25.752768 RX Vref Scan: 1
970 23:18:25.752857
971 23:18:25.752922 Set Vref Range= 32 -> 127
972 23:18:25.752982
973 23:18:25.755813 RX Vref 32 -> 127, step: 1
974 23:18:25.755895
975 23:18:25.759186 RX Delay -95 -> 252, step: 8
976 23:18:25.759269
977 23:18:25.762496 Set Vref, RX VrefLevel [Byte0]: 32
978 23:18:25.765648 [Byte1]: 32
979 23:18:25.765742
980 23:18:25.770164 Set Vref, RX VrefLevel [Byte0]: 33
981 23:18:25.773552 [Byte1]: 33
982 23:18:25.773633
983 23:18:25.776898 Set Vref, RX VrefLevel [Byte0]: 34
984 23:18:25.780062 [Byte1]: 34
985 23:18:25.780143
986 23:18:25.783439 Set Vref, RX VrefLevel [Byte0]: 35
987 23:18:25.787114 [Byte1]: 35
988 23:18:25.790949
989 23:18:25.791030 Set Vref, RX VrefLevel [Byte0]: 36
990 23:18:25.794494 [Byte1]: 36
991 23:18:25.798832
992 23:18:25.798987 Set Vref, RX VrefLevel [Byte0]: 37
993 23:18:25.802393 [Byte1]: 37
994 23:18:25.806262
995 23:18:25.806425 Set Vref, RX VrefLevel [Byte0]: 38
996 23:18:25.809570 [Byte1]: 38
997 23:18:25.814195
998 23:18:25.814351 Set Vref, RX VrefLevel [Byte0]: 39
999 23:18:25.817265 [Byte1]: 39
1000 23:18:25.821898
1001 23:18:25.822058 Set Vref, RX VrefLevel [Byte0]: 40
1002 23:18:25.824896 [Byte1]: 40
1003 23:18:25.829107
1004 23:18:25.829276 Set Vref, RX VrefLevel [Byte0]: 41
1005 23:18:25.833097 [Byte1]: 41
1006 23:18:25.836438
1007 23:18:25.836585 Set Vref, RX VrefLevel [Byte0]: 42
1008 23:18:25.839809 [Byte1]: 42
1009 23:18:25.844046
1010 23:18:25.844199 Set Vref, RX VrefLevel [Byte0]: 43
1011 23:18:25.847199 [Byte1]: 43
1012 23:18:25.851293
1013 23:18:25.851449 Set Vref, RX VrefLevel [Byte0]: 44
1014 23:18:25.855108 [Byte1]: 44
1015 23:18:25.858773
1016 23:18:25.858925 Set Vref, RX VrefLevel [Byte0]: 45
1017 23:18:25.862336 [Byte1]: 45
1018 23:18:25.866864
1019 23:18:25.866946 Set Vref, RX VrefLevel [Byte0]: 46
1020 23:18:25.870174 [Byte1]: 46
1021 23:18:25.874175
1022 23:18:25.874248 Set Vref, RX VrefLevel [Byte0]: 47
1023 23:18:25.877423 [Byte1]: 47
1024 23:18:25.881974
1025 23:18:25.882058 Set Vref, RX VrefLevel [Byte0]: 48
1026 23:18:25.885525 [Byte1]: 48
1027 23:18:25.889391
1028 23:18:25.889471 Set Vref, RX VrefLevel [Byte0]: 49
1029 23:18:25.892824 [Byte1]: 49
1030 23:18:25.896791
1031 23:18:25.896870 Set Vref, RX VrefLevel [Byte0]: 50
1032 23:18:25.900546 [Byte1]: 50
1033 23:18:25.904340
1034 23:18:25.904420 Set Vref, RX VrefLevel [Byte0]: 51
1035 23:18:25.907718 [Byte1]: 51
1036 23:18:25.912151
1037 23:18:25.912235 Set Vref, RX VrefLevel [Byte0]: 52
1038 23:18:25.915565 [Byte1]: 52
1039 23:18:25.919817
1040 23:18:25.919973 Set Vref, RX VrefLevel [Byte0]: 53
1041 23:18:25.923212 [Byte1]: 53
1042 23:18:25.927392
1043 23:18:25.927545 Set Vref, RX VrefLevel [Byte0]: 54
1044 23:18:25.930876 [Byte1]: 54
1045 23:18:25.934964
1046 23:18:25.935111 Set Vref, RX VrefLevel [Byte0]: 55
1047 23:18:25.938516 [Byte1]: 55
1048 23:18:25.942635
1049 23:18:25.942784 Set Vref, RX VrefLevel [Byte0]: 56
1050 23:18:25.946068 [Byte1]: 56
1051 23:18:25.950140
1052 23:18:25.950286 Set Vref, RX VrefLevel [Byte0]: 57
1053 23:18:25.953753 [Byte1]: 57
1054 23:18:25.958024
1055 23:18:25.958174 Set Vref, RX VrefLevel [Byte0]: 58
1056 23:18:25.961462 [Byte1]: 58
1057 23:18:25.965290
1058 23:18:25.965442 Set Vref, RX VrefLevel [Byte0]: 59
1059 23:18:25.969107 [Byte1]: 59
1060 23:18:25.972976
1061 23:18:25.973121 Set Vref, RX VrefLevel [Byte0]: 60
1062 23:18:25.976318 [Byte1]: 60
1063 23:18:25.980890
1064 23:18:25.981043 Set Vref, RX VrefLevel [Byte0]: 61
1065 23:18:25.984014 [Byte1]: 61
1066 23:18:25.988099
1067 23:18:25.988252 Set Vref, RX VrefLevel [Byte0]: 62
1068 23:18:25.991479 [Byte1]: 62
1069 23:18:25.996037
1070 23:18:25.996188 Set Vref, RX VrefLevel [Byte0]: 63
1071 23:18:25.999284 [Byte1]: 63
1072 23:18:26.003074
1073 23:18:26.003228 Set Vref, RX VrefLevel [Byte0]: 64
1074 23:18:26.006916 [Byte1]: 64
1075 23:18:26.011126
1076 23:18:26.011278 Set Vref, RX VrefLevel [Byte0]: 65
1077 23:18:26.014311 [Byte1]: 65
1078 23:18:26.018746
1079 23:18:26.018826 Set Vref, RX VrefLevel [Byte0]: 66
1080 23:18:26.022431 [Byte1]: 66
1081 23:18:26.025888
1082 23:18:26.025968 Set Vref, RX VrefLevel [Byte0]: 67
1083 23:18:26.029205 [Byte1]: 67
1084 23:18:26.033913
1085 23:18:26.033992 Set Vref, RX VrefLevel [Byte0]: 68
1086 23:18:26.037194 [Byte1]: 68
1087 23:18:26.041365
1088 23:18:26.041445 Set Vref, RX VrefLevel [Byte0]: 69
1089 23:18:26.044743 [Byte1]: 69
1090 23:18:26.048810
1091 23:18:26.048890 Set Vref, RX VrefLevel [Byte0]: 70
1092 23:18:26.052130 [Byte1]: 70
1093 23:18:26.056474
1094 23:18:26.056554 Set Vref, RX VrefLevel [Byte0]: 71
1095 23:18:26.059585 [Byte1]: 71
1096 23:18:26.063837
1097 23:18:26.063945 Set Vref, RX VrefLevel [Byte0]: 72
1098 23:18:26.067355 [Byte1]: 72
1099 23:18:26.071898
1100 23:18:26.071979 Set Vref, RX VrefLevel [Byte0]: 73
1101 23:18:26.074686 [Byte1]: 73
1102 23:18:26.079248
1103 23:18:26.079347 Set Vref, RX VrefLevel [Byte0]: 74
1104 23:18:26.082443 [Byte1]: 74
1105 23:18:26.086906
1106 23:18:26.086985 Set Vref, RX VrefLevel [Byte0]: 75
1107 23:18:26.090543 [Byte1]: 75
1108 23:18:26.094291
1109 23:18:26.094370 Set Vref, RX VrefLevel [Byte0]: 76
1110 23:18:26.098052 [Byte1]: 76
1111 23:18:26.102110
1112 23:18:26.102190 Final RX Vref Byte 0 = 61 to rank0
1113 23:18:26.105445 Final RX Vref Byte 1 = 56 to rank0
1114 23:18:26.108565 Final RX Vref Byte 0 = 61 to rank1
1115 23:18:26.112293 Final RX Vref Byte 1 = 56 to rank1==
1116 23:18:26.115468 Dram Type= 6, Freq= 0, CH_0, rank 0
1117 23:18:26.118618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1118 23:18:26.121954 ==
1119 23:18:26.122066 DQS Delay:
1120 23:18:26.122160 DQS0 = 0, DQS1 = 0
1121 23:18:26.125517 DQM Delay:
1122 23:18:26.125625 DQM0 = 88, DQM1 = 79
1123 23:18:26.129048 DQ Delay:
1124 23:18:26.129152 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1125 23:18:26.132544 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1126 23:18:26.135379 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1127 23:18:26.138989 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1128 23:18:26.139096
1129 23:18:26.142270
1130 23:18:26.148853 [DQSOSCAuto] RK0, (LSB)MR18= 0x260d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1131 23:18:26.152179 CH0 RK0: MR19=606, MR18=260D
1132 23:18:26.159322 CH0_RK0: MR19=0x606, MR18=0x260D, DQSOSC=400, MR23=63, INC=92, DEC=61
1133 23:18:26.159429
1134 23:18:26.162136 ----->DramcWriteLeveling(PI) begin...
1135 23:18:26.162242 ==
1136 23:18:26.165440 Dram Type= 6, Freq= 0, CH_0, rank 1
1137 23:18:26.168878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1138 23:18:26.168985 ==
1139 23:18:26.172167 Write leveling (Byte 0): 30 => 30
1140 23:18:26.175659 Write leveling (Byte 1): 30 => 30
1141 23:18:26.179336 DramcWriteLeveling(PI) end<-----
1142 23:18:26.179442
1143 23:18:26.179532 ==
1144 23:18:26.182159 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 23:18:26.185479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 23:18:26.185585 ==
1147 23:18:26.189661 [Gating] SW mode calibration
1148 23:18:26.196015 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1149 23:18:26.202433 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1150 23:18:26.205896 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 23:18:26.209378 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1152 23:18:26.253369 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1153 23:18:26.254201 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 23:18:26.254522 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 23:18:26.254622 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 23:18:26.254903 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 23:18:26.255016 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 23:18:26.255458 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 23:18:26.255919 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:18:26.256011 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:18:26.256296 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:18:26.259223 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:18:26.262324 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:18:26.265751 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:18:26.272384 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 23:18:26.275788 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 23:18:26.279015 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1168 23:18:26.286073 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1169 23:18:26.289023 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:18:26.292514 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:18:26.299384 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:18:26.302473 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:18:26.306033 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:18:26.309501 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:18:26.316593 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 23:18:26.319480 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1177 23:18:26.322621 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
1178 23:18:26.329305 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 23:18:26.332500 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 23:18:26.336196 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 23:18:26.342562 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 23:18:26.346361 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 23:18:26.349339 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1184 23:18:26.356152 0 10 8 | B1->B0 | 3333 2d2d | 1 0 | (1 0) (1 1)
1185 23:18:26.359679 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
1186 23:18:26.363425 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 23:18:26.366002 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:18:26.372958 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:18:26.376513 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 23:18:26.380427 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 23:18:26.387357 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1192 23:18:26.390951 0 11 8 | B1->B0 | 2626 3e3e | 0 0 | (0 0) (0 0)
1193 23:18:26.394083 0 11 12 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
1194 23:18:26.397788 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 23:18:26.404300 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 23:18:26.407908 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 23:18:26.411906 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 23:18:26.415181 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 23:18:26.422063 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1200 23:18:26.424808 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1201 23:18:26.428436 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 23:18:26.435713 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 23:18:26.438287 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:18:26.441970 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:18:26.448573 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:18:26.451814 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 23:18:26.455387 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 23:18:26.458825 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:18:26.465097 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:18:26.468471 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:18:26.472064 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:18:26.478968 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:18:26.482231 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 23:18:26.485254 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 23:18:26.492170 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1216 23:18:26.495448 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1217 23:18:26.498686 Total UI for P1: 0, mck2ui 16
1218 23:18:26.501865 best dqsien dly found for B0: ( 0, 14, 4)
1219 23:18:26.505760 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 23:18:26.508625 Total UI for P1: 0, mck2ui 16
1221 23:18:26.512218 best dqsien dly found for B1: ( 0, 14, 8)
1222 23:18:26.515706 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1223 23:18:26.518790 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1224 23:18:26.518871
1225 23:18:26.522571 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1226 23:18:26.525561 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1227 23:18:26.529101 [Gating] SW calibration Done
1228 23:18:26.529182 ==
1229 23:18:26.532175 Dram Type= 6, Freq= 0, CH_0, rank 1
1230 23:18:26.539197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1231 23:18:26.539279 ==
1232 23:18:26.539344 RX Vref Scan: 0
1233 23:18:26.539403
1234 23:18:26.543083 RX Vref 0 -> 0, step: 1
1235 23:18:26.543165
1236 23:18:26.545974 RX Delay -130 -> 252, step: 16
1237 23:18:26.549301 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1238 23:18:26.552344 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1239 23:18:26.555735 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1240 23:18:26.559328 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1241 23:18:26.565801 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1242 23:18:26.569656 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1243 23:18:26.572903 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1244 23:18:26.575694 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1245 23:18:26.579091 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1246 23:18:26.582842 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1247 23:18:26.589239 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1248 23:18:26.592544 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1249 23:18:26.596172 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1250 23:18:26.599131 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1251 23:18:26.606082 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1252 23:18:26.609347 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1253 23:18:26.609428 ==
1254 23:18:26.612776 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 23:18:26.616180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1256 23:18:26.616262 ==
1257 23:18:26.616325 DQS Delay:
1258 23:18:26.619821 DQS0 = 0, DQS1 = 0
1259 23:18:26.619902 DQM Delay:
1260 23:18:26.622945 DQM0 = 85, DQM1 = 78
1261 23:18:26.623026 DQ Delay:
1262 23:18:26.625991 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1263 23:18:26.629610 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =85
1264 23:18:26.632798 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1265 23:18:26.636318 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1266 23:18:26.636421
1267 23:18:26.636512
1268 23:18:26.636599 ==
1269 23:18:26.639632 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 23:18:26.643015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 23:18:26.643120 ==
1272 23:18:26.646388
1273 23:18:26.646531
1274 23:18:26.646621 TX Vref Scan disable
1275 23:18:26.649775 == TX Byte 0 ==
1276 23:18:26.653274 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1277 23:18:26.656462 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1278 23:18:26.659952 == TX Byte 1 ==
1279 23:18:26.663123 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1280 23:18:26.666958 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1281 23:18:26.667063 ==
1282 23:18:26.670644 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 23:18:26.676484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 23:18:26.676590 ==
1285 23:18:26.688287 TX Vref=22, minBit 3, minWin=27, winSum=444
1286 23:18:26.691380 TX Vref=24, minBit 7, minWin=27, winSum=449
1287 23:18:26.694854 TX Vref=26, minBit 3, minWin=27, winSum=448
1288 23:18:26.698179 TX Vref=28, minBit 0, minWin=28, winSum=454
1289 23:18:26.701307 TX Vref=30, minBit 0, minWin=28, winSum=453
1290 23:18:26.705098 TX Vref=32, minBit 0, minWin=28, winSum=453
1291 23:18:26.711724 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 28
1292 23:18:26.711806
1293 23:18:26.715162 Final TX Range 1 Vref 28
1294 23:18:26.715244
1295 23:18:26.715307 ==
1296 23:18:26.718546 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 23:18:26.722438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 23:18:26.722521 ==
1299 23:18:26.722584
1300 23:18:26.722643
1301 23:18:26.724726 TX Vref Scan disable
1302 23:18:26.728184 == TX Byte 0 ==
1303 23:18:26.731848 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1304 23:18:26.735200 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1305 23:18:26.738200 == TX Byte 1 ==
1306 23:18:26.741438 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1307 23:18:26.745475 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1308 23:18:26.745555
1309 23:18:26.748319 [DATLAT]
1310 23:18:26.748399 Freq=800, CH0 RK1
1311 23:18:26.748462
1312 23:18:26.751788 DATLAT Default: 0xa
1313 23:18:26.751868 0, 0xFFFF, sum = 0
1314 23:18:26.755025 1, 0xFFFF, sum = 0
1315 23:18:26.755108 2, 0xFFFF, sum = 0
1316 23:18:26.758467 3, 0xFFFF, sum = 0
1317 23:18:26.758576 4, 0xFFFF, sum = 0
1318 23:18:26.761808 5, 0xFFFF, sum = 0
1319 23:18:26.761890 6, 0xFFFF, sum = 0
1320 23:18:26.765178 7, 0xFFFF, sum = 0
1321 23:18:26.765260 8, 0xFFFF, sum = 0
1322 23:18:26.768708 9, 0x0, sum = 1
1323 23:18:26.768791 10, 0x0, sum = 2
1324 23:18:26.772246 11, 0x0, sum = 3
1325 23:18:26.772341 12, 0x0, sum = 4
1326 23:18:26.775811 best_step = 10
1327 23:18:26.775892
1328 23:18:26.775954 ==
1329 23:18:26.778542 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 23:18:26.781952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 23:18:26.782034 ==
1332 23:18:26.782096 RX Vref Scan: 0
1333 23:18:26.785606
1334 23:18:26.785685 RX Vref 0 -> 0, step: 1
1335 23:18:26.785748
1336 23:18:26.788667 RX Delay -95 -> 252, step: 8
1337 23:18:26.792279 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1338 23:18:26.798994 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1339 23:18:26.802055 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1340 23:18:26.805391 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1341 23:18:26.809304 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1342 23:18:26.812423 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1343 23:18:26.819369 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1344 23:18:26.822040 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1345 23:18:26.825719 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1346 23:18:26.828932 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1347 23:18:26.832189 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1348 23:18:26.835609 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1349 23:18:26.842419 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1350 23:18:26.845868 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1351 23:18:26.849292 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1352 23:18:26.852523 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1353 23:18:26.852603 ==
1354 23:18:26.855848 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 23:18:26.862539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 23:18:26.862620 ==
1357 23:18:26.862683 DQS Delay:
1358 23:18:26.865945 DQS0 = 0, DQS1 = 0
1359 23:18:26.866024 DQM Delay:
1360 23:18:26.866087 DQM0 = 87, DQM1 = 77
1361 23:18:26.869258 DQ Delay:
1362 23:18:26.872580 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1363 23:18:26.875983 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1364 23:18:26.879482 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1365 23:18:26.882660 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1366 23:18:26.882767
1367 23:18:26.882867
1368 23:18:26.889522 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1369 23:18:26.893065 CH0 RK1: MR19=606, MR18=2F19
1370 23:18:26.899354 CH0_RK1: MR19=0x606, MR18=0x2F19, DQSOSC=397, MR23=63, INC=93, DEC=62
1371 23:18:26.903023 [RxdqsGatingPostProcess] freq 800
1372 23:18:26.905946 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1373 23:18:26.909684 Pre-setting of DQS Precalculation
1374 23:18:26.916052 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1375 23:18:26.916134 ==
1376 23:18:26.919385 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 23:18:26.923140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 23:18:26.923222 ==
1379 23:18:26.929400 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 23:18:26.932621 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 23:18:26.942752 [CA 0] Center 36 (6~66) winsize 61
1382 23:18:26.946356 [CA 1] Center 36 (6~66) winsize 61
1383 23:18:26.949307 [CA 2] Center 35 (5~65) winsize 61
1384 23:18:26.953163 [CA 3] Center 34 (4~65) winsize 62
1385 23:18:26.956436 [CA 4] Center 34 (4~65) winsize 62
1386 23:18:26.959405 [CA 5] Center 34 (4~64) winsize 61
1387 23:18:26.959487
1388 23:18:26.963141 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1389 23:18:26.963223
1390 23:18:26.966563 [CATrainingPosCal] consider 1 rank data
1391 23:18:26.969644 u2DelayCellTimex100 = 270/100 ps
1392 23:18:26.972867 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1393 23:18:26.976146 CA1 delay=36 (6~66),Diff = 2 PI (14 cell)
1394 23:18:26.979863 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1395 23:18:26.986501 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1396 23:18:26.989765 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1397 23:18:26.993367 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1398 23:18:26.993455
1399 23:18:26.996610 CA PerBit enable=1, Macro0, CA PI delay=34
1400 23:18:26.996691
1401 23:18:26.999971 [CBTSetCACLKResult] CA Dly = 34
1402 23:18:27.000051 CS Dly: 5 (0~36)
1403 23:18:27.000115 ==
1404 23:18:27.003587 Dram Type= 6, Freq= 0, CH_1, rank 1
1405 23:18:27.010138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 23:18:27.010220 ==
1407 23:18:27.013373 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1408 23:18:27.020309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1409 23:18:27.028864 [CA 0] Center 36 (6~66) winsize 61
1410 23:18:27.032195 [CA 1] Center 36 (6~66) winsize 61
1411 23:18:27.035621 [CA 2] Center 34 (4~64) winsize 61
1412 23:18:27.038843 [CA 3] Center 33 (3~64) winsize 62
1413 23:18:27.041996 [CA 4] Center 34 (4~65) winsize 62
1414 23:18:27.045980 [CA 5] Center 33 (3~64) winsize 62
1415 23:18:27.046084
1416 23:18:27.049936 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1417 23:18:27.050039
1418 23:18:27.053030 [CATrainingPosCal] consider 2 rank data
1419 23:18:27.056889 u2DelayCellTimex100 = 270/100 ps
1420 23:18:27.061091 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1421 23:18:27.064807 CA1 delay=36 (6~66),Diff = 2 PI (14 cell)
1422 23:18:27.068408 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1423 23:18:27.072397 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1424 23:18:27.075743 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1425 23:18:27.079332 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1426 23:18:27.079413
1427 23:18:27.083649 CA PerBit enable=1, Macro0, CA PI delay=34
1428 23:18:27.083731
1429 23:18:27.086781 [CBTSetCACLKResult] CA Dly = 34
1430 23:18:27.086862 CS Dly: 6 (0~38)
1431 23:18:27.086926
1432 23:18:27.090186 ----->DramcWriteLeveling(PI) begin...
1433 23:18:27.090268 ==
1434 23:18:27.093676 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 23:18:27.096760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 23:18:27.096842 ==
1437 23:18:27.100221 Write leveling (Byte 0): 26 => 26
1438 23:18:27.103322 Write leveling (Byte 1): 31 => 31
1439 23:18:27.106674 DramcWriteLeveling(PI) end<-----
1440 23:18:27.106756
1441 23:18:27.106819 ==
1442 23:18:27.110165 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 23:18:27.113644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 23:18:27.117001 ==
1445 23:18:27.117082 [Gating] SW mode calibration
1446 23:18:27.123945 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1447 23:18:27.130253 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1448 23:18:27.133637 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 23:18:27.140251 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1450 23:18:27.143910 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 23:18:27.147207 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 23:18:27.150626 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 23:18:27.157215 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 23:18:27.160763 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 23:18:27.163928 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 23:18:27.170715 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 23:18:27.173995 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 23:18:27.177693 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:18:27.184349 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:18:27.187870 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:18:27.190624 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:18:27.197526 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:18:27.200791 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 23:18:27.204202 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:18:27.211220 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1466 23:18:27.214557 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1467 23:18:27.217828 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:18:27.220689 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:18:27.227380 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:18:27.230801 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:18:27.234515 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:18:27.240706 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:18:27.244173 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 23:18:27.247426 0 9 8 | B1->B0 | 2525 2524 | 1 1 | (1 1) (1 1)
1475 23:18:27.254220 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 23:18:27.257441 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 23:18:27.260923 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 23:18:27.267849 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 23:18:27.271519 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 23:18:27.274352 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 23:18:27.280967 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 23:18:27.284756 0 10 8 | B1->B0 | 2e2e 2f2f | 1 1 | (1 0) (1 0)
1483 23:18:27.287661 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 23:18:27.291264 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 23:18:27.297993 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 23:18:27.301245 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:18:27.304885 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 23:18:27.311463 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 23:18:27.314938 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1490 23:18:27.318246 0 11 8 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
1491 23:18:27.324561 0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1492 23:18:27.327976 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 23:18:27.331375 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 23:18:27.338460 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 23:18:27.341987 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 23:18:27.344962 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 23:18:27.351667 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 23:18:27.355087 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1499 23:18:27.358591 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 23:18:27.361914 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 23:18:27.368366 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 23:18:27.371896 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 23:18:27.375235 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 23:18:27.382187 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 23:18:27.385083 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 23:18:27.388349 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:18:27.395191 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:18:27.398863 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:18:27.402028 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:18:27.409040 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:18:27.411908 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:18:27.415392 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 23:18:27.418610 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1514 23:18:27.425502 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1515 23:18:27.428594 Total UI for P1: 0, mck2ui 16
1516 23:18:27.432067 best dqsien dly found for B0: ( 0, 14, 4)
1517 23:18:27.435567 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 23:18:27.438939 Total UI for P1: 0, mck2ui 16
1519 23:18:27.442131 best dqsien dly found for B1: ( 0, 14, 6)
1520 23:18:27.445426 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1521 23:18:27.448729 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1522 23:18:27.448810
1523 23:18:27.452106 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1524 23:18:27.455963 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1525 23:18:27.458744 [Gating] SW calibration Done
1526 23:18:27.458833 ==
1527 23:18:27.462370 Dram Type= 6, Freq= 0, CH_1, rank 0
1528 23:18:27.465739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1529 23:18:27.465810 ==
1530 23:18:27.469037 RX Vref Scan: 0
1531 23:18:27.469113
1532 23:18:27.472115 RX Vref 0 -> 0, step: 1
1533 23:18:27.472189
1534 23:18:27.475298 RX Delay -130 -> 252, step: 16
1535 23:18:27.478664 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1536 23:18:27.482729 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1537 23:18:27.485519 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1538 23:18:27.488734 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1539 23:18:27.492204 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1540 23:18:27.499636 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1541 23:18:27.502255 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1542 23:18:27.505968 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1543 23:18:27.509202 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1544 23:18:27.512722 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1545 23:18:27.519016 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1546 23:18:27.522793 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1547 23:18:27.525838 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1548 23:18:27.529192 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1549 23:18:27.532636 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1550 23:18:27.539360 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1551 23:18:27.539441 ==
1552 23:18:27.542832 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 23:18:27.546379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1554 23:18:27.546500 ==
1555 23:18:27.546563 DQS Delay:
1556 23:18:27.549977 DQS0 = 0, DQS1 = 0
1557 23:18:27.550057 DQM Delay:
1558 23:18:27.552877 DQM0 = 84, DQM1 = 77
1559 23:18:27.552957 DQ Delay:
1560 23:18:27.556435 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1561 23:18:27.559884 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1562 23:18:27.562846 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1563 23:18:27.566256 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1564 23:18:27.566362
1565 23:18:27.566472
1566 23:18:27.566532 ==
1567 23:18:27.569445 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 23:18:27.572831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 23:18:27.572912 ==
1570 23:18:27.572976
1571 23:18:27.573034
1572 23:18:27.576526 TX Vref Scan disable
1573 23:18:27.579956 == TX Byte 0 ==
1574 23:18:27.583331 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1575 23:18:27.586567 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1576 23:18:27.590233 == TX Byte 1 ==
1577 23:18:27.593517 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1578 23:18:27.597161 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1579 23:18:27.597232 ==
1580 23:18:27.600372 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 23:18:27.603936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 23:18:27.604006 ==
1583 23:18:27.617747 TX Vref=22, minBit 0, minWin=27, winSum=438
1584 23:18:27.621581 TX Vref=24, minBit 1, minWin=27, winSum=440
1585 23:18:27.624534 TX Vref=26, minBit 0, minWin=27, winSum=444
1586 23:18:27.627886 TX Vref=28, minBit 5, minWin=27, winSum=448
1587 23:18:27.631885 TX Vref=30, minBit 1, minWin=28, winSum=450
1588 23:18:27.635148 TX Vref=32, minBit 11, minWin=27, winSum=453
1589 23:18:27.642471 [TxChooseVref] Worse bit 1, Min win 28, Win sum 450, Final Vref 30
1590 23:18:27.642546
1591 23:18:27.645522 Final TX Range 1 Vref 30
1592 23:18:27.645617
1593 23:18:27.645709 ==
1594 23:18:27.649256 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 23:18:27.652109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 23:18:27.652180 ==
1597 23:18:27.652239
1598 23:18:27.652297
1599 23:18:27.655329 TX Vref Scan disable
1600 23:18:27.659159 == TX Byte 0 ==
1601 23:18:27.662180 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1602 23:18:27.665608 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1603 23:18:27.669195 == TX Byte 1 ==
1604 23:18:27.672421 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1605 23:18:27.675756 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1606 23:18:27.675827
1607 23:18:27.675885 [DATLAT]
1608 23:18:27.678963 Freq=800, CH1 RK0
1609 23:18:27.679036
1610 23:18:27.682460 DATLAT Default: 0xa
1611 23:18:27.682534 0, 0xFFFF, sum = 0
1612 23:18:27.685973 1, 0xFFFF, sum = 0
1613 23:18:27.686042 2, 0xFFFF, sum = 0
1614 23:18:27.689119 3, 0xFFFF, sum = 0
1615 23:18:27.689187 4, 0xFFFF, sum = 0
1616 23:18:27.692359 5, 0xFFFF, sum = 0
1617 23:18:27.692433 6, 0xFFFF, sum = 0
1618 23:18:27.695799 7, 0xFFFF, sum = 0
1619 23:18:27.695902 8, 0xFFFF, sum = 0
1620 23:18:27.699043 9, 0x0, sum = 1
1621 23:18:27.699112 10, 0x0, sum = 2
1622 23:18:27.699171 11, 0x0, sum = 3
1623 23:18:27.702463 12, 0x0, sum = 4
1624 23:18:27.702531 best_step = 10
1625 23:18:27.702587
1626 23:18:27.705690 ==
1627 23:18:27.705757 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 23:18:27.712879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 23:18:27.712949 ==
1630 23:18:27.713008 RX Vref Scan: 1
1631 23:18:27.713071
1632 23:18:27.715874 Set Vref Range= 32 -> 127
1633 23:18:27.715939
1634 23:18:27.719403 RX Vref 32 -> 127, step: 1
1635 23:18:27.719470
1636 23:18:27.722696 RX Delay -95 -> 252, step: 8
1637 23:18:27.722774
1638 23:18:27.725827 Set Vref, RX VrefLevel [Byte0]: 32
1639 23:18:27.729350 [Byte1]: 32
1640 23:18:27.729448
1641 23:18:27.733104 Set Vref, RX VrefLevel [Byte0]: 33
1642 23:18:27.735829 [Byte1]: 33
1643 23:18:27.735902
1644 23:18:27.739207 Set Vref, RX VrefLevel [Byte0]: 34
1645 23:18:27.742584 [Byte1]: 34
1646 23:18:27.742683
1647 23:18:27.746155 Set Vref, RX VrefLevel [Byte0]: 35
1648 23:18:27.749538 [Byte1]: 35
1649 23:18:27.753441
1650 23:18:27.753518 Set Vref, RX VrefLevel [Byte0]: 36
1651 23:18:27.756974 [Byte1]: 36
1652 23:18:27.760922
1653 23:18:27.760994 Set Vref, RX VrefLevel [Byte0]: 37
1654 23:18:27.764320 [Byte1]: 37
1655 23:18:27.768800
1656 23:18:27.768898 Set Vref, RX VrefLevel [Byte0]: 38
1657 23:18:27.771940 [Byte1]: 38
1658 23:18:27.776650
1659 23:18:27.776722 Set Vref, RX VrefLevel [Byte0]: 39
1660 23:18:27.779641 [Byte1]: 39
1661 23:18:27.784279
1662 23:18:27.784350 Set Vref, RX VrefLevel [Byte0]: 40
1663 23:18:27.787241 [Byte1]: 40
1664 23:18:27.791551
1665 23:18:27.791617 Set Vref, RX VrefLevel [Byte0]: 41
1666 23:18:27.794692 [Byte1]: 41
1667 23:18:27.798816
1668 23:18:27.798900 Set Vref, RX VrefLevel [Byte0]: 42
1669 23:18:27.802385 [Byte1]: 42
1670 23:18:27.806819
1671 23:18:27.806890 Set Vref, RX VrefLevel [Byte0]: 43
1672 23:18:27.810223 [Byte1]: 43
1673 23:18:27.814492
1674 23:18:27.814587 Set Vref, RX VrefLevel [Byte0]: 44
1675 23:18:27.817635 [Byte1]: 44
1676 23:18:27.822327
1677 23:18:27.822468 Set Vref, RX VrefLevel [Byte0]: 45
1678 23:18:27.825128 [Byte1]: 45
1679 23:18:27.829217
1680 23:18:27.829314 Set Vref, RX VrefLevel [Byte0]: 46
1681 23:18:27.833059 [Byte1]: 46
1682 23:18:27.837066
1683 23:18:27.837162 Set Vref, RX VrefLevel [Byte0]: 47
1684 23:18:27.840256 [Byte1]: 47
1685 23:18:27.844723
1686 23:18:27.844798 Set Vref, RX VrefLevel [Byte0]: 48
1687 23:18:27.847874 [Byte1]: 48
1688 23:18:27.852394
1689 23:18:27.852472 Set Vref, RX VrefLevel [Byte0]: 49
1690 23:18:27.855502 [Byte1]: 49
1691 23:18:27.859652
1692 23:18:27.859724 Set Vref, RX VrefLevel [Byte0]: 50
1693 23:18:27.863501 [Byte1]: 50
1694 23:18:27.867498
1695 23:18:27.867571 Set Vref, RX VrefLevel [Byte0]: 51
1696 23:18:27.870511 [Byte1]: 51
1697 23:18:27.875100
1698 23:18:27.875198 Set Vref, RX VrefLevel [Byte0]: 52
1699 23:18:27.878190 [Byte1]: 52
1700 23:18:27.882847
1701 23:18:27.882947 Set Vref, RX VrefLevel [Byte0]: 53
1702 23:18:27.886135 [Byte1]: 53
1703 23:18:27.890057
1704 23:18:27.890141 Set Vref, RX VrefLevel [Byte0]: 54
1705 23:18:27.894053 [Byte1]: 54
1706 23:18:27.897912
1707 23:18:27.898006 Set Vref, RX VrefLevel [Byte0]: 55
1708 23:18:27.901129 [Byte1]: 55
1709 23:18:27.905761
1710 23:18:27.905877 Set Vref, RX VrefLevel [Byte0]: 56
1711 23:18:27.908435 [Byte1]: 56
1712 23:18:27.912876
1713 23:18:27.912953 Set Vref, RX VrefLevel [Byte0]: 57
1714 23:18:27.916005 [Byte1]: 57
1715 23:18:27.921124
1716 23:18:27.921204 Set Vref, RX VrefLevel [Byte0]: 58
1717 23:18:27.923849 [Byte1]: 58
1718 23:18:27.928288
1719 23:18:27.928370 Set Vref, RX VrefLevel [Byte0]: 59
1720 23:18:27.931791 [Byte1]: 59
1721 23:18:27.935683
1722 23:18:27.935764 Set Vref, RX VrefLevel [Byte0]: 60
1723 23:18:27.939358 [Byte1]: 60
1724 23:18:27.943131
1725 23:18:27.943211 Set Vref, RX VrefLevel [Byte0]: 61
1726 23:18:27.946485 [Byte1]: 61
1727 23:18:27.950879
1728 23:18:27.950996 Set Vref, RX VrefLevel [Byte0]: 62
1729 23:18:27.954056 [Byte1]: 62
1730 23:18:27.958279
1731 23:18:27.958385 Set Vref, RX VrefLevel [Byte0]: 63
1732 23:18:27.962001 [Byte1]: 63
1733 23:18:27.965922
1734 23:18:27.965994 Set Vref, RX VrefLevel [Byte0]: 64
1735 23:18:27.969637 [Byte1]: 64
1736 23:18:27.973497
1737 23:18:27.973573 Set Vref, RX VrefLevel [Byte0]: 65
1738 23:18:27.976906 [Byte1]: 65
1739 23:18:27.981620
1740 23:18:27.981703 Set Vref, RX VrefLevel [Byte0]: 66
1741 23:18:27.984525 [Byte1]: 66
1742 23:18:27.989383
1743 23:18:27.989461 Set Vref, RX VrefLevel [Byte0]: 67
1744 23:18:27.992052 [Byte1]: 67
1745 23:18:27.996879
1746 23:18:27.996953 Set Vref, RX VrefLevel [Byte0]: 68
1747 23:18:27.999885 [Byte1]: 68
1748 23:18:28.004152
1749 23:18:28.004225 Set Vref, RX VrefLevel [Byte0]: 69
1750 23:18:28.008114 [Byte1]: 69
1751 23:18:28.011795
1752 23:18:28.011871 Set Vref, RX VrefLevel [Byte0]: 70
1753 23:18:28.014891 [Byte1]: 70
1754 23:18:28.019262
1755 23:18:28.019359 Set Vref, RX VrefLevel [Byte0]: 71
1756 23:18:28.023529 [Byte1]: 71
1757 23:18:28.026914
1758 23:18:28.026994 Set Vref, RX VrefLevel [Byte0]: 72
1759 23:18:28.029918 [Byte1]: 72
1760 23:18:28.034601
1761 23:18:28.034680 Set Vref, RX VrefLevel [Byte0]: 73
1762 23:18:28.038057 [Byte1]: 73
1763 23:18:28.041825
1764 23:18:28.041899 Set Vref, RX VrefLevel [Byte0]: 74
1765 23:18:28.045137 [Byte1]: 74
1766 23:18:28.049987
1767 23:18:28.050084 Set Vref, RX VrefLevel [Byte0]: 75
1768 23:18:28.053184 [Byte1]: 75
1769 23:18:28.057346
1770 23:18:28.057415 Set Vref, RX VrefLevel [Byte0]: 76
1771 23:18:28.060642 [Byte1]: 76
1772 23:18:28.064937
1773 23:18:28.065008 Set Vref, RX VrefLevel [Byte0]: 77
1774 23:18:28.068034 [Byte1]: 77
1775 23:18:28.072419
1776 23:18:28.072501 Set Vref, RX VrefLevel [Byte0]: 78
1777 23:18:28.075749 [Byte1]: 78
1778 23:18:28.080233
1779 23:18:28.080314 Set Vref, RX VrefLevel [Byte0]: 79
1780 23:18:28.083237 [Byte1]: 79
1781 23:18:28.087750
1782 23:18:28.087831 Final RX Vref Byte 0 = 55 to rank0
1783 23:18:28.091166 Final RX Vref Byte 1 = 59 to rank0
1784 23:18:28.094639 Final RX Vref Byte 0 = 55 to rank1
1785 23:18:28.097398 Final RX Vref Byte 1 = 59 to rank1==
1786 23:18:28.101244 Dram Type= 6, Freq= 0, CH_1, rank 0
1787 23:18:28.107815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 23:18:28.107897 ==
1789 23:18:28.107961 DQS Delay:
1790 23:18:28.108020 DQS0 = 0, DQS1 = 0
1791 23:18:28.111154 DQM Delay:
1792 23:18:28.111235 DQM0 = 83, DQM1 = 74
1793 23:18:28.114359 DQ Delay:
1794 23:18:28.117647 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1795 23:18:28.117728 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =76
1796 23:18:28.120862 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1797 23:18:28.124879 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1798 23:18:28.128005
1799 23:18:28.128085
1800 23:18:28.134256 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e03, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1801 23:18:28.137908 CH1 RK0: MR19=606, MR18=2E03
1802 23:18:28.144483 CH1_RK0: MR19=0x606, MR18=0x2E03, DQSOSC=398, MR23=63, INC=93, DEC=62
1803 23:18:28.144562
1804 23:18:28.147845 ----->DramcWriteLeveling(PI) begin...
1805 23:18:28.147925 ==
1806 23:18:28.151424 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 23:18:28.155102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 23:18:28.155182 ==
1809 23:18:28.157817 Write leveling (Byte 0): 26 => 26
1810 23:18:28.161171 Write leveling (Byte 1): 31 => 31
1811 23:18:28.164455 DramcWriteLeveling(PI) end<-----
1812 23:18:28.164534
1813 23:18:28.164596 ==
1814 23:18:28.168162 Dram Type= 6, Freq= 0, CH_1, rank 1
1815 23:18:28.171277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1816 23:18:28.171357 ==
1817 23:18:28.174563 [Gating] SW mode calibration
1818 23:18:28.181160 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1819 23:18:28.188515 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1820 23:18:28.191448 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1821 23:18:28.194828 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1822 23:18:28.201558 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 23:18:28.204545 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:18:28.208218 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 23:18:28.211282 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 23:18:28.218464 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 23:18:28.222058 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 23:18:28.225324 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 23:18:28.231892 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 23:18:28.234815 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 23:18:28.238514 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 23:18:28.245255 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1833 23:18:28.248423 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 23:18:28.251625 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:18:28.258306 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1836 23:18:28.262048 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1837 23:18:28.265106 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1838 23:18:28.268676 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:18:28.275660 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1840 23:18:28.278504 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 23:18:28.281918 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 23:18:28.288588 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 23:18:28.291960 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 23:18:28.295548 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 23:18:28.302336 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1846 23:18:28.305701 0 9 8 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
1847 23:18:28.308853 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 23:18:28.315962 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 23:18:28.319126 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 23:18:28.322451 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 23:18:28.325627 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 23:18:28.332877 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1853 23:18:28.336143 0 10 4 | B1->B0 | 3030 2d2d | 0 1 | (0 0) (1 0)
1854 23:18:28.339120 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
1855 23:18:28.346031 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 23:18:28.349224 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 23:18:28.352697 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 23:18:28.359346 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 23:18:28.362739 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 23:18:28.365802 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 23:18:28.373181 0 11 4 | B1->B0 | 2828 3535 | 0 1 | (0 0) (0 0)
1862 23:18:28.376055 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1863 23:18:28.379485 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 23:18:28.382848 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 23:18:28.389566 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 23:18:28.392577 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 23:18:28.396047 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 23:18:28.402449 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1869 23:18:28.406092 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1870 23:18:28.409589 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 23:18:28.416410 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 23:18:28.419345 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 23:18:28.422735 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 23:18:28.429795 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 23:18:28.432905 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 23:18:28.436388 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 23:18:28.443074 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 23:18:28.446254 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 23:18:28.449872 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 23:18:28.453190 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 23:18:28.459916 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 23:18:28.463241 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 23:18:28.466585 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 23:18:28.473506 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1885 23:18:28.476766 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1886 23:18:28.480536 Total UI for P1: 0, mck2ui 16
1887 23:18:28.483360 best dqsien dly found for B0: ( 0, 14, 0)
1888 23:18:28.487173 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 23:18:28.490551 Total UI for P1: 0, mck2ui 16
1890 23:18:28.493899 best dqsien dly found for B1: ( 0, 14, 4)
1891 23:18:28.496825 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1892 23:18:28.500235 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1893 23:18:28.500318
1894 23:18:28.503605 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1895 23:18:28.506866 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1896 23:18:28.509966 [Gating] SW calibration Done
1897 23:18:28.510044 ==
1898 23:18:28.513383 Dram Type= 6, Freq= 0, CH_1, rank 1
1899 23:18:28.520375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1900 23:18:28.520468 ==
1901 23:18:28.520540 RX Vref Scan: 0
1902 23:18:28.520598
1903 23:18:28.523451 RX Vref 0 -> 0, step: 1
1904 23:18:28.523532
1905 23:18:28.526783 RX Delay -130 -> 252, step: 16
1906 23:18:28.530090 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1907 23:18:28.533894 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1908 23:18:28.536948 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1909 23:18:28.540374 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1910 23:18:28.547323 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1911 23:18:28.550612 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1912 23:18:28.553856 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1913 23:18:28.556971 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1914 23:18:28.560287 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1915 23:18:28.567004 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1916 23:18:28.570628 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1917 23:18:28.573756 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1918 23:18:28.577617 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1919 23:18:28.580366 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1920 23:18:28.587249 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1921 23:18:28.590426 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1922 23:18:28.590522 ==
1923 23:18:28.593795 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 23:18:28.597195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1925 23:18:28.597297 ==
1926 23:18:28.597390 DQS Delay:
1927 23:18:28.601093 DQS0 = 0, DQS1 = 0
1928 23:18:28.601166 DQM Delay:
1929 23:18:28.604233 DQM0 = 80, DQM1 = 77
1930 23:18:28.604310 DQ Delay:
1931 23:18:28.607354 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1932 23:18:28.610642 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =69
1933 23:18:28.614578 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1934 23:18:28.617865 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1935 23:18:28.617945
1936 23:18:28.618005
1937 23:18:28.618067 ==
1938 23:18:28.621116 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 23:18:28.624392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 23:18:28.624471 ==
1941 23:18:28.627416
1942 23:18:28.627500
1943 23:18:28.627560 TX Vref Scan disable
1944 23:18:28.631188 == TX Byte 0 ==
1945 23:18:28.634616 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1946 23:18:28.638119 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1947 23:18:28.641520 == TX Byte 1 ==
1948 23:18:28.644490 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1949 23:18:28.647502 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1950 23:18:28.647593 ==
1951 23:18:28.651693 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 23:18:28.657541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 23:18:28.657628 ==
1954 23:18:28.669918 TX Vref=22, minBit 1, minWin=27, winSum=443
1955 23:18:28.673303 TX Vref=24, minBit 11, minWin=27, winSum=445
1956 23:18:28.676758 TX Vref=26, minBit 15, minWin=27, winSum=448
1957 23:18:28.679826 TX Vref=28, minBit 15, minWin=27, winSum=450
1958 23:18:28.683193 TX Vref=30, minBit 0, minWin=28, winSum=458
1959 23:18:28.689854 TX Vref=32, minBit 0, minWin=28, winSum=453
1960 23:18:28.693033 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30
1961 23:18:28.693120
1962 23:18:28.696777 Final TX Range 1 Vref 30
1963 23:18:28.696858
1964 23:18:28.696919 ==
1965 23:18:28.700175 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 23:18:28.703417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 23:18:28.703490 ==
1968 23:18:28.706383
1969 23:18:28.706523
1970 23:18:28.706611 TX Vref Scan disable
1971 23:18:28.709812 == TX Byte 0 ==
1972 23:18:28.713286 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1973 23:18:28.717008 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1974 23:18:28.720149 == TX Byte 1 ==
1975 23:18:28.723494 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1976 23:18:28.726904 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1977 23:18:28.726989
1978 23:18:28.730552 [DATLAT]
1979 23:18:28.730632 Freq=800, CH1 RK1
1980 23:18:28.730694
1981 23:18:28.733501 DATLAT Default: 0xa
1982 23:18:28.733576 0, 0xFFFF, sum = 0
1983 23:18:28.736668 1, 0xFFFF, sum = 0
1984 23:18:28.736766 2, 0xFFFF, sum = 0
1985 23:18:28.740152 3, 0xFFFF, sum = 0
1986 23:18:28.740223 4, 0xFFFF, sum = 0
1987 23:18:28.743971 5, 0xFFFF, sum = 0
1988 23:18:28.744055 6, 0xFFFF, sum = 0
1989 23:18:28.747285 7, 0xFFFF, sum = 0
1990 23:18:28.747358 8, 0xFFFF, sum = 0
1991 23:18:28.750383 9, 0x0, sum = 1
1992 23:18:28.750497 10, 0x0, sum = 2
1993 23:18:28.753968 11, 0x0, sum = 3
1994 23:18:28.754072 12, 0x0, sum = 4
1995 23:18:28.757177 best_step = 10
1996 23:18:28.757246
1997 23:18:28.757303 ==
1998 23:18:28.760454 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 23:18:28.764008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 23:18:28.764097 ==
2001 23:18:28.767114 RX Vref Scan: 0
2002 23:18:28.767189
2003 23:18:28.767248 RX Vref 0 -> 0, step: 1
2004 23:18:28.767303
2005 23:18:28.770737 RX Delay -95 -> 252, step: 8
2006 23:18:28.776976 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2007 23:18:28.780530 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2008 23:18:28.783899 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2009 23:18:28.787525 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2010 23:18:28.790555 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2011 23:18:28.793963 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2012 23:18:28.800836 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2013 23:18:28.804387 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2014 23:18:28.807998 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2015 23:18:28.811029 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
2016 23:18:28.814186 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2017 23:18:28.820772 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2018 23:18:28.824168 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2019 23:18:28.828103 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2020 23:18:28.831012 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2021 23:18:28.834324 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2022 23:18:28.837528 ==
2023 23:18:28.837613 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 23:18:28.844338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 23:18:28.844427 ==
2026 23:18:28.844491 DQS Delay:
2027 23:18:28.848027 DQS0 = 0, DQS1 = 0
2028 23:18:28.848105 DQM Delay:
2029 23:18:28.848165 DQM0 = 81, DQM1 = 75
2030 23:18:28.851228 DQ Delay:
2031 23:18:28.854305 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2032 23:18:28.857819 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =76
2033 23:18:28.861102 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =68
2034 23:18:28.864786 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2035 23:18:28.864871
2036 23:18:28.864934
2037 23:18:28.871033 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 402 ps
2038 23:18:28.874346 CH1 RK1: MR19=606, MR18=1F2B
2039 23:18:28.880882 CH1_RK1: MR19=0x606, MR18=0x1F2B, DQSOSC=398, MR23=63, INC=93, DEC=62
2040 23:18:28.884561 [RxdqsGatingPostProcess] freq 800
2041 23:18:28.887887 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2042 23:18:28.891475 Pre-setting of DQS Precalculation
2043 23:18:28.897893 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2044 23:18:28.904495 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2045 23:18:28.911146 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2046 23:18:28.911388
2047 23:18:28.911479
2048 23:18:28.914924 [Calibration Summary] 1600 Mbps
2049 23:18:28.915014 CH 0, Rank 0
2050 23:18:28.917630 SW Impedance : PASS
2051 23:18:28.921473 DUTY Scan : NO K
2052 23:18:28.921560 ZQ Calibration : PASS
2053 23:18:28.924319 Jitter Meter : NO K
2054 23:18:28.927583 CBT Training : PASS
2055 23:18:28.927672 Write leveling : PASS
2056 23:18:28.931068 RX DQS gating : PASS
2057 23:18:28.931154 RX DQ/DQS(RDDQC) : PASS
2058 23:18:28.934363 TX DQ/DQS : PASS
2059 23:18:28.938237 RX DATLAT : PASS
2060 23:18:28.938326 RX DQ/DQS(Engine): PASS
2061 23:18:28.941198 TX OE : NO K
2062 23:18:28.941285 All Pass.
2063 23:18:28.941349
2064 23:18:28.944699 CH 0, Rank 1
2065 23:18:28.944785 SW Impedance : PASS
2066 23:18:28.948149 DUTY Scan : NO K
2067 23:18:28.951338 ZQ Calibration : PASS
2068 23:18:28.951422 Jitter Meter : NO K
2069 23:18:28.954949 CBT Training : PASS
2070 23:18:28.957966 Write leveling : PASS
2071 23:18:28.958067 RX DQS gating : PASS
2072 23:18:28.961463 RX DQ/DQS(RDDQC) : PASS
2073 23:18:28.964774 TX DQ/DQS : PASS
2074 23:18:28.964861 RX DATLAT : PASS
2075 23:18:28.968124 RX DQ/DQS(Engine): PASS
2076 23:18:28.968199 TX OE : NO K
2077 23:18:28.971392 All Pass.
2078 23:18:28.971472
2079 23:18:28.971534 CH 1, Rank 0
2080 23:18:28.974825 SW Impedance : PASS
2081 23:18:28.974911 DUTY Scan : NO K
2082 23:18:28.978199 ZQ Calibration : PASS
2083 23:18:28.981788 Jitter Meter : NO K
2084 23:18:28.981866 CBT Training : PASS
2085 23:18:28.985134 Write leveling : PASS
2086 23:18:28.988170 RX DQS gating : PASS
2087 23:18:28.988281 RX DQ/DQS(RDDQC) : PASS
2088 23:18:28.991650 TX DQ/DQS : PASS
2089 23:18:28.994875 RX DATLAT : PASS
2090 23:18:28.994974 RX DQ/DQS(Engine): PASS
2091 23:18:28.998376 TX OE : NO K
2092 23:18:28.998507 All Pass.
2093 23:18:28.998602
2094 23:18:29.001695 CH 1, Rank 1
2095 23:18:29.001797 SW Impedance : PASS
2096 23:18:29.005138 DUTY Scan : NO K
2097 23:18:29.005253 ZQ Calibration : PASS
2098 23:18:29.008568 Jitter Meter : NO K
2099 23:18:29.011649 CBT Training : PASS
2100 23:18:29.011736 Write leveling : PASS
2101 23:18:29.015824 RX DQS gating : PASS
2102 23:18:29.018457 RX DQ/DQS(RDDQC) : PASS
2103 23:18:29.018541 TX DQ/DQS : PASS
2104 23:18:29.022094 RX DATLAT : PASS
2105 23:18:29.025343 RX DQ/DQS(Engine): PASS
2106 23:18:29.025439 TX OE : NO K
2107 23:18:29.025504 All Pass.
2108 23:18:29.028663
2109 23:18:29.028756 DramC Write-DBI off
2110 23:18:29.032050 PER_BANK_REFRESH: Hybrid Mode
2111 23:18:29.032143 TX_TRACKING: ON
2112 23:18:29.036019 [GetDramInforAfterCalByMRR] Vendor 6.
2113 23:18:29.038578 [GetDramInforAfterCalByMRR] Revision 606.
2114 23:18:29.045260 [GetDramInforAfterCalByMRR] Revision 2 0.
2115 23:18:29.045414 MR0 0x3b3b
2116 23:18:29.045514 MR8 0x5151
2117 23:18:29.049092 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2118 23:18:29.049203
2119 23:18:29.052258 MR0 0x3b3b
2120 23:18:29.052372 MR8 0x5151
2121 23:18:29.055607 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2122 23:18:29.055726
2123 23:18:29.065558 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2124 23:18:29.068799 [FAST_K] Save calibration result to emmc
2125 23:18:29.072541 [FAST_K] Save calibration result to emmc
2126 23:18:29.076173 dram_init: config_dvfs: 1
2127 23:18:29.078831 dramc_set_vcore_voltage set vcore to 662500
2128 23:18:29.078951 Read voltage for 1200, 2
2129 23:18:29.082164 Vio18 = 0
2130 23:18:29.082275 Vcore = 662500
2131 23:18:29.082365 Vdram = 0
2132 23:18:29.085387 Vddq = 0
2133 23:18:29.085488 Vmddr = 0
2134 23:18:29.088945 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2135 23:18:29.095629 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2136 23:18:29.099220 MEM_TYPE=3, freq_sel=15
2137 23:18:29.102427 sv_algorithm_assistance_LP4_1600
2138 23:18:29.105644 ============ PULL DRAM RESETB DOWN ============
2139 23:18:29.109026 ========== PULL DRAM RESETB DOWN end =========
2140 23:18:29.112795 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2141 23:18:29.115710 ===================================
2142 23:18:29.119320 LPDDR4 DRAM CONFIGURATION
2143 23:18:29.122473 ===================================
2144 23:18:29.125948 EX_ROW_EN[0] = 0x0
2145 23:18:29.126070 EX_ROW_EN[1] = 0x0
2146 23:18:29.129159 LP4Y_EN = 0x0
2147 23:18:29.129247 WORK_FSP = 0x0
2148 23:18:29.132716 WL = 0x4
2149 23:18:29.132806 RL = 0x4
2150 23:18:29.136386 BL = 0x2
2151 23:18:29.136502 RPST = 0x0
2152 23:18:29.139610 RD_PRE = 0x0
2153 23:18:29.139715 WR_PRE = 0x1
2154 23:18:29.143006 WR_PST = 0x0
2155 23:18:29.143087 DBI_WR = 0x0
2156 23:18:29.145809 DBI_RD = 0x0
2157 23:18:29.145893 OTF = 0x1
2158 23:18:29.149513 ===================================
2159 23:18:29.152737 ===================================
2160 23:18:29.156275 ANA top config
2161 23:18:29.159593 ===================================
2162 23:18:29.162939 DLL_ASYNC_EN = 0
2163 23:18:29.163031 ALL_SLAVE_EN = 0
2164 23:18:29.166153 NEW_RANK_MODE = 1
2165 23:18:29.169545 DLL_IDLE_MODE = 1
2166 23:18:29.172947 LP45_APHY_COMB_EN = 1
2167 23:18:29.173053 TX_ODT_DIS = 1
2168 23:18:29.175954 NEW_8X_MODE = 1
2169 23:18:29.179575 ===================================
2170 23:18:29.182647 ===================================
2171 23:18:29.186390 data_rate = 2400
2172 23:18:29.189317 CKR = 1
2173 23:18:29.193000 DQ_P2S_RATIO = 8
2174 23:18:29.196488 ===================================
2175 23:18:29.196589 CA_P2S_RATIO = 8
2176 23:18:29.200112 DQ_CA_OPEN = 0
2177 23:18:29.202913 DQ_SEMI_OPEN = 0
2178 23:18:29.206258 CA_SEMI_OPEN = 0
2179 23:18:29.209513 CA_FULL_RATE = 0
2180 23:18:29.213266 DQ_CKDIV4_EN = 0
2181 23:18:29.213357 CA_CKDIV4_EN = 0
2182 23:18:29.216612 CA_PREDIV_EN = 0
2183 23:18:29.219840 PH8_DLY = 17
2184 23:18:29.223203 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2185 23:18:29.226856 DQ_AAMCK_DIV = 4
2186 23:18:29.229641 CA_AAMCK_DIV = 4
2187 23:18:29.229729 CA_ADMCK_DIV = 4
2188 23:18:29.233480 DQ_TRACK_CA_EN = 0
2189 23:18:29.236612 CA_PICK = 1200
2190 23:18:29.239763 CA_MCKIO = 1200
2191 23:18:29.243109 MCKIO_SEMI = 0
2192 23:18:29.246908 PLL_FREQ = 2366
2193 23:18:29.249864 DQ_UI_PI_RATIO = 32
2194 23:18:29.249949 CA_UI_PI_RATIO = 0
2195 23:18:29.253106 ===================================
2196 23:18:29.256617 ===================================
2197 23:18:29.259761 memory_type:LPDDR4
2198 23:18:29.263501 GP_NUM : 10
2199 23:18:29.263588 SRAM_EN : 1
2200 23:18:29.266618 MD32_EN : 0
2201 23:18:29.270021 ===================================
2202 23:18:29.273354 [ANA_INIT] >>>>>>>>>>>>>>
2203 23:18:29.273465 <<<<<< [CONFIGURE PHASE]: ANA_TX
2204 23:18:29.279875 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2205 23:18:29.283300 ===================================
2206 23:18:29.283394 data_rate = 2400,PCW = 0X5b00
2207 23:18:29.286839 ===================================
2208 23:18:29.289936 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2209 23:18:29.296677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2210 23:18:29.303258 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 23:18:29.306799 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2212 23:18:29.310508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2213 23:18:29.313421 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2214 23:18:29.316607 [ANA_INIT] flow start
2215 23:18:29.316692 [ANA_INIT] PLL >>>>>>>>
2216 23:18:29.319969 [ANA_INIT] PLL <<<<<<<<
2217 23:18:29.323501 [ANA_INIT] MIDPI >>>>>>>>
2218 23:18:29.323589 [ANA_INIT] MIDPI <<<<<<<<
2219 23:18:29.327221 [ANA_INIT] DLL >>>>>>>>
2220 23:18:29.330205 [ANA_INIT] DLL <<<<<<<<
2221 23:18:29.330291 [ANA_INIT] flow end
2222 23:18:29.337366 ============ LP4 DIFF to SE enter ============
2223 23:18:29.340207 ============ LP4 DIFF to SE exit ============
2224 23:18:29.340323 [ANA_INIT] <<<<<<<<<<<<<
2225 23:18:29.343952 [Flow] Enable top DCM control >>>>>
2226 23:18:29.347169 [Flow] Enable top DCM control <<<<<
2227 23:18:29.350256 Enable DLL master slave shuffle
2228 23:18:29.356942 ==============================================================
2229 23:18:29.357051 Gating Mode config
2230 23:18:29.363553 ==============================================================
2231 23:18:29.367589 Config description:
2232 23:18:29.377272 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2233 23:18:29.383775 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2234 23:18:29.387373 SELPH_MODE 0: By rank 1: By Phase
2235 23:18:29.393994 ==============================================================
2236 23:18:29.397092 GAT_TRACK_EN = 1
2237 23:18:29.397205 RX_GATING_MODE = 2
2238 23:18:29.400445 RX_GATING_TRACK_MODE = 2
2239 23:18:29.403961 SELPH_MODE = 1
2240 23:18:29.407432 PICG_EARLY_EN = 1
2241 23:18:29.410527 VALID_LAT_VALUE = 1
2242 23:18:29.417444 ==============================================================
2243 23:18:29.421106 Enter into Gating configuration >>>>
2244 23:18:29.424394 Exit from Gating configuration <<<<
2245 23:18:29.427406 Enter into DVFS_PRE_config >>>>>
2246 23:18:29.437703 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2247 23:18:29.440900 Exit from DVFS_PRE_config <<<<<
2248 23:18:29.444086 Enter into PICG configuration >>>>
2249 23:18:29.447768 Exit from PICG configuration <<<<
2250 23:18:29.450668 [RX_INPUT] configuration >>>>>
2251 23:18:29.450821 [RX_INPUT] configuration <<<<<
2252 23:18:29.457433 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2253 23:18:29.461098 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2254 23:18:29.467440 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2255 23:18:29.474197 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2256 23:18:29.481379 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2257 23:18:29.487787 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2258 23:18:29.491077 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2259 23:18:29.494800 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2260 23:18:29.497878 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2261 23:18:29.504747 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2262 23:18:29.507817 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2263 23:18:29.511133 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2264 23:18:29.514763 ===================================
2265 23:18:29.518167 LPDDR4 DRAM CONFIGURATION
2266 23:18:29.521152 ===================================
2267 23:18:29.525120 EX_ROW_EN[0] = 0x0
2268 23:18:29.525235 EX_ROW_EN[1] = 0x0
2269 23:18:29.528633 LP4Y_EN = 0x0
2270 23:18:29.528725 WORK_FSP = 0x0
2271 23:18:29.531368 WL = 0x4
2272 23:18:29.531479 RL = 0x4
2273 23:18:29.534638 BL = 0x2
2274 23:18:29.534717 RPST = 0x0
2275 23:18:29.538019 RD_PRE = 0x0
2276 23:18:29.538124 WR_PRE = 0x1
2277 23:18:29.541384 WR_PST = 0x0
2278 23:18:29.541485 DBI_WR = 0x0
2279 23:18:29.544843 DBI_RD = 0x0
2280 23:18:29.544947 OTF = 0x1
2281 23:18:29.548233 ===================================
2282 23:18:29.551566 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2283 23:18:29.558532 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2284 23:18:29.561785 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2285 23:18:29.564794 ===================================
2286 23:18:29.568206 LPDDR4 DRAM CONFIGURATION
2287 23:18:29.571648 ===================================
2288 23:18:29.571736 EX_ROW_EN[0] = 0x10
2289 23:18:29.575110 EX_ROW_EN[1] = 0x0
2290 23:18:29.575191 LP4Y_EN = 0x0
2291 23:18:29.578555 WORK_FSP = 0x0
2292 23:18:29.578659 WL = 0x4
2293 23:18:29.581591 RL = 0x4
2294 23:18:29.581686 BL = 0x2
2295 23:18:29.584701 RPST = 0x0
2296 23:18:29.588332 RD_PRE = 0x0
2297 23:18:29.588450 WR_PRE = 0x1
2298 23:18:29.592009 WR_PST = 0x0
2299 23:18:29.592118 DBI_WR = 0x0
2300 23:18:29.595153 DBI_RD = 0x0
2301 23:18:29.595261 OTF = 0x1
2302 23:18:29.599044 ===================================
2303 23:18:29.605130 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2304 23:18:29.605260 ==
2305 23:18:29.608336 Dram Type= 6, Freq= 0, CH_0, rank 0
2306 23:18:29.611843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2307 23:18:29.611925 ==
2308 23:18:29.615303 [Duty_Offset_Calibration]
2309 23:18:29.615384 B0:2 B1:-1 CA:1
2310 23:18:29.615447
2311 23:18:29.618809 [DutyScan_Calibration_Flow] k_type=0
2312 23:18:29.628911
2313 23:18:29.629052 ==CLK 0==
2314 23:18:29.632195 Final CLK duty delay cell = -4
2315 23:18:29.635416 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2316 23:18:29.638959 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2317 23:18:29.639045 [-4] AVG Duty = 4953%(X100)
2318 23:18:29.642253
2319 23:18:29.645797 CH0 CLK Duty spec in!! Max-Min= 156%
2320 23:18:29.648997 [DutyScan_Calibration_Flow] ====Done====
2321 23:18:29.649083
2322 23:18:29.652096 [DutyScan_Calibration_Flow] k_type=1
2323 23:18:29.667211
2324 23:18:29.667357 ==DQS 0 ==
2325 23:18:29.670264 Final DQS duty delay cell = -4
2326 23:18:29.673492 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2327 23:18:29.676705 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2328 23:18:29.679955 [-4] AVG Duty = 4938%(X100)
2329 23:18:29.680042
2330 23:18:29.680104 ==DQS 1 ==
2331 23:18:29.683832 Final DQS duty delay cell = -4
2332 23:18:29.686713 [-4] MAX Duty = 5124%(X100), DQS PI = 18
2333 23:18:29.690261 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2334 23:18:29.693495 [-4] AVG Duty = 5062%(X100)
2335 23:18:29.693650
2336 23:18:29.696770 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2337 23:18:29.696872
2338 23:18:29.700441 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2339 23:18:29.703443 [DutyScan_Calibration_Flow] ====Done====
2340 23:18:29.703549
2341 23:18:29.706829 [DutyScan_Calibration_Flow] k_type=3
2342 23:18:29.724366
2343 23:18:29.724517 ==DQM 0 ==
2344 23:18:29.727123 Final DQM duty delay cell = 0
2345 23:18:29.731007 [0] MAX Duty = 5031%(X100), DQS PI = 54
2346 23:18:29.734040 [0] MIN Duty = 4907%(X100), DQS PI = 2
2347 23:18:29.734120 [0] AVG Duty = 4969%(X100)
2348 23:18:29.737490
2349 23:18:29.737589 ==DQM 1 ==
2350 23:18:29.740825 Final DQM duty delay cell = 0
2351 23:18:29.744396 [0] MAX Duty = 5156%(X100), DQS PI = 62
2352 23:18:29.747612 [0] MIN Duty = 4969%(X100), DQS PI = 10
2353 23:18:29.747735 [0] AVG Duty = 5062%(X100)
2354 23:18:29.750818
2355 23:18:29.754411 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2356 23:18:29.754504
2357 23:18:29.757733 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2358 23:18:29.760887 [DutyScan_Calibration_Flow] ====Done====
2359 23:18:29.761011
2360 23:18:29.764015 [DutyScan_Calibration_Flow] k_type=2
2361 23:18:29.779541
2362 23:18:29.779679 ==DQ 0 ==
2363 23:18:29.783012 Final DQ duty delay cell = -4
2364 23:18:29.786655 [-4] MAX Duty = 5031%(X100), DQS PI = 0
2365 23:18:29.789597 [-4] MIN Duty = 4844%(X100), DQS PI = 18
2366 23:18:29.793452 [-4] AVG Duty = 4937%(X100)
2367 23:18:29.793561
2368 23:18:29.793640 ==DQ 1 ==
2369 23:18:29.796922 Final DQ duty delay cell = 0
2370 23:18:29.799788 [0] MAX Duty = 5031%(X100), DQS PI = 18
2371 23:18:29.803123 [0] MIN Duty = 4907%(X100), DQS PI = 46
2372 23:18:29.803215 [0] AVG Duty = 4969%(X100)
2373 23:18:29.803280
2374 23:18:29.806706 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2375 23:18:29.810238
2376 23:18:29.813671 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2377 23:18:29.816768 [DutyScan_Calibration_Flow] ====Done====
2378 23:18:29.816848 ==
2379 23:18:29.820198 Dram Type= 6, Freq= 0, CH_1, rank 0
2380 23:18:29.823302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2381 23:18:29.823421 ==
2382 23:18:29.826709 [Duty_Offset_Calibration]
2383 23:18:29.826820 B0:1 B1:1 CA:2
2384 23:18:29.826882
2385 23:18:29.830299 [DutyScan_Calibration_Flow] k_type=0
2386 23:18:29.839986
2387 23:18:29.840158 ==CLK 0==
2388 23:18:29.843320 Final CLK duty delay cell = 0
2389 23:18:29.846610 [0] MAX Duty = 5187%(X100), DQS PI = 24
2390 23:18:29.849952 [0] MIN Duty = 4969%(X100), DQS PI = 40
2391 23:18:29.850063 [0] AVG Duty = 5078%(X100)
2392 23:18:29.853325
2393 23:18:29.853427 CH1 CLK Duty spec in!! Max-Min= 218%
2394 23:18:29.860001 [DutyScan_Calibration_Flow] ====Done====
2395 23:18:29.860095
2396 23:18:29.863396 [DutyScan_Calibration_Flow] k_type=1
2397 23:18:29.879074
2398 23:18:29.879236 ==DQS 0 ==
2399 23:18:29.882584 Final DQS duty delay cell = 0
2400 23:18:29.886129 [0] MAX Duty = 5031%(X100), DQS PI = 18
2401 23:18:29.889528 [0] MIN Duty = 4844%(X100), DQS PI = 48
2402 23:18:29.889638 [0] AVG Duty = 4937%(X100)
2403 23:18:29.892886
2404 23:18:29.892992 ==DQS 1 ==
2405 23:18:29.896014 Final DQS duty delay cell = 0
2406 23:18:29.899744 [0] MAX Duty = 5062%(X100), DQS PI = 36
2407 23:18:29.902966 [0] MIN Duty = 4907%(X100), DQS PI = 8
2408 23:18:29.903082 [0] AVG Duty = 4984%(X100)
2409 23:18:29.903172
2410 23:18:29.906714 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2411 23:18:29.909915
2412 23:18:29.912867 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2413 23:18:29.916168 [DutyScan_Calibration_Flow] ====Done====
2414 23:18:29.916246
2415 23:18:29.920190 [DutyScan_Calibration_Flow] k_type=3
2416 23:18:29.936087
2417 23:18:29.936230 ==DQM 0 ==
2418 23:18:29.939540 Final DQM duty delay cell = 0
2419 23:18:29.942676 [0] MAX Duty = 5093%(X100), DQS PI = 18
2420 23:18:29.945906 [0] MIN Duty = 4907%(X100), DQS PI = 48
2421 23:18:29.946015 [0] AVG Duty = 5000%(X100)
2422 23:18:29.949444
2423 23:18:29.949546 ==DQM 1 ==
2424 23:18:29.952554 Final DQM duty delay cell = 0
2425 23:18:29.956236 [0] MAX Duty = 5125%(X100), DQS PI = 0
2426 23:18:29.959312 [0] MIN Duty = 4938%(X100), DQS PI = 22
2427 23:18:29.959390 [0] AVG Duty = 5031%(X100)
2428 23:18:29.962776
2429 23:18:29.965900 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2430 23:18:29.965990
2431 23:18:29.969409 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2432 23:18:29.972432 [DutyScan_Calibration_Flow] ====Done====
2433 23:18:29.972541
2434 23:18:29.975943 [DutyScan_Calibration_Flow] k_type=2
2435 23:18:29.992863
2436 23:18:29.993034 ==DQ 0 ==
2437 23:18:29.995710 Final DQ duty delay cell = 0
2438 23:18:29.998814 [0] MAX Duty = 5124%(X100), DQS PI = 18
2439 23:18:30.002504 [0] MIN Duty = 4938%(X100), DQS PI = 50
2440 23:18:30.002643 [0] AVG Duty = 5031%(X100)
2441 23:18:30.002739
2442 23:18:30.005655 ==DQ 1 ==
2443 23:18:30.009113 Final DQ duty delay cell = 0
2444 23:18:30.012543 [0] MAX Duty = 5093%(X100), DQS PI = 10
2445 23:18:30.016299 [0] MIN Duty = 5000%(X100), DQS PI = 50
2446 23:18:30.016426 [0] AVG Duty = 5046%(X100)
2447 23:18:30.016520
2448 23:18:30.018943 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2449 23:18:30.019025
2450 23:18:30.022546 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2451 23:18:30.029269 [DutyScan_Calibration_Flow] ====Done====
2452 23:18:30.032212 nWR fixed to 30
2453 23:18:30.032337 [ModeRegInit_LP4] CH0 RK0
2454 23:18:30.036048 [ModeRegInit_LP4] CH0 RK1
2455 23:18:30.039059 [ModeRegInit_LP4] CH1 RK0
2456 23:18:30.039179 [ModeRegInit_LP4] CH1 RK1
2457 23:18:30.042423 match AC timing 7
2458 23:18:30.045983 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2459 23:18:30.048822 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2460 23:18:30.055690 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2461 23:18:30.059071 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2462 23:18:30.066204 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2463 23:18:30.066368 ==
2464 23:18:30.069662 Dram Type= 6, Freq= 0, CH_0, rank 0
2465 23:18:30.072936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2466 23:18:30.073029 ==
2467 23:18:30.079664 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2468 23:18:30.082438 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2469 23:18:30.092240 [CA 0] Center 40 (10~71) winsize 62
2470 23:18:30.095942 [CA 1] Center 39 (9~70) winsize 62
2471 23:18:30.098875 [CA 2] Center 36 (6~67) winsize 62
2472 23:18:30.102364 [CA 3] Center 35 (5~66) winsize 62
2473 23:18:30.105905 [CA 4] Center 34 (4~65) winsize 62
2474 23:18:30.109153 [CA 5] Center 34 (4~64) winsize 61
2475 23:18:30.109249
2476 23:18:30.112422 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2477 23:18:30.112509
2478 23:18:30.115627 [CATrainingPosCal] consider 1 rank data
2479 23:18:30.118994 u2DelayCellTimex100 = 270/100 ps
2480 23:18:30.122597 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2481 23:18:30.125967 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2482 23:18:30.132446 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2483 23:18:30.136144 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2484 23:18:30.139335 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2485 23:18:30.142801 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2486 23:18:30.142906
2487 23:18:30.145874 CA PerBit enable=1, Macro0, CA PI delay=34
2488 23:18:30.145993
2489 23:18:30.149490 [CBTSetCACLKResult] CA Dly = 34
2490 23:18:30.149612 CS Dly: 7 (0~38)
2491 23:18:30.149725 ==
2492 23:18:30.152703 Dram Type= 6, Freq= 0, CH_0, rank 1
2493 23:18:30.159634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2494 23:18:30.159769 ==
2495 23:18:30.162538 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2496 23:18:30.169213 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2497 23:18:30.178197 [CA 0] Center 39 (9~70) winsize 62
2498 23:18:30.181923 [CA 1] Center 39 (9~70) winsize 62
2499 23:18:30.185031 [CA 2] Center 36 (6~67) winsize 62
2500 23:18:30.188559 [CA 3] Center 36 (5~67) winsize 63
2501 23:18:30.191631 [CA 4] Center 34 (4~65) winsize 62
2502 23:18:30.195060 [CA 5] Center 34 (4~64) winsize 61
2503 23:18:30.195213
2504 23:18:30.198387 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2505 23:18:30.198516
2506 23:18:30.201981 [CATrainingPosCal] consider 2 rank data
2507 23:18:30.205168 u2DelayCellTimex100 = 270/100 ps
2508 23:18:30.208395 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2509 23:18:30.211741 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2510 23:18:30.215768 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2511 23:18:30.221690 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2512 23:18:30.225220 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2513 23:18:30.228500 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2514 23:18:30.228602
2515 23:18:30.231824 CA PerBit enable=1, Macro0, CA PI delay=34
2516 23:18:30.231917
2517 23:18:30.235477 [CBTSetCACLKResult] CA Dly = 34
2518 23:18:30.235570 CS Dly: 8 (0~41)
2519 23:18:30.235655
2520 23:18:30.238915 ----->DramcWriteLeveling(PI) begin...
2521 23:18:30.239010 ==
2522 23:18:30.242131 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 23:18:30.249234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 23:18:30.249345 ==
2525 23:18:30.252079 Write leveling (Byte 0): 30 => 30
2526 23:18:30.255463 Write leveling (Byte 1): 29 => 29
2527 23:18:30.255553 DramcWriteLeveling(PI) end<-----
2528 23:18:30.255622
2529 23:18:30.258766 ==
2530 23:18:30.258852 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 23:18:30.265842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 23:18:30.265943 ==
2533 23:18:30.269084 [Gating] SW mode calibration
2534 23:18:30.275737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2535 23:18:30.278849 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2536 23:18:30.285760 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 23:18:30.289254 0 15 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2538 23:18:30.292355 0 15 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2539 23:18:30.298830 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 23:18:30.302617 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 23:18:30.305589 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 23:18:30.308928 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 23:18:30.316259 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 23:18:30.318932 1 0 0 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
2545 23:18:30.322250 1 0 4 | B1->B0 | 2b2b 2323 | 1 0 | (0 1) (0 0)
2546 23:18:30.329363 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 23:18:30.332744 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 23:18:30.335938 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 23:18:30.342603 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 23:18:30.346364 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 23:18:30.349382 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 23:18:30.355775 1 1 0 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
2553 23:18:30.359597 1 1 4 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
2554 23:18:30.362511 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 23:18:30.366320 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 23:18:30.372942 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 23:18:30.376468 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 23:18:30.379554 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 23:18:30.386503 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 23:18:30.389999 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2561 23:18:30.392742 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2562 23:18:30.399663 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 23:18:30.402991 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 23:18:30.406594 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 23:18:30.413605 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 23:18:30.416802 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 23:18:30.419885 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 23:18:30.423355 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 23:18:30.429889 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 23:18:30.433664 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 23:18:30.436688 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 23:18:30.443423 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 23:18:30.446422 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 23:18:30.449751 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 23:18:30.456437 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 23:18:30.459854 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2577 23:18:30.463286 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2578 23:18:30.469775 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 23:18:30.469874 Total UI for P1: 0, mck2ui 16
2580 23:18:30.476810 best dqsien dly found for B0: ( 1, 4, 2)
2581 23:18:30.476921 Total UI for P1: 0, mck2ui 16
2582 23:18:30.480233 best dqsien dly found for B1: ( 1, 4, 4)
2583 23:18:30.486651 best DQS0 dly(MCK, UI, PI) = (1, 4, 2)
2584 23:18:30.490394 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2585 23:18:30.490517
2586 23:18:30.493552 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 2)
2587 23:18:30.496718 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2588 23:18:30.499986 [Gating] SW calibration Done
2589 23:18:30.500074 ==
2590 23:18:30.503424 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 23:18:30.506792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 23:18:30.506865 ==
2593 23:18:30.506929 RX Vref Scan: 0
2594 23:18:30.506984
2595 23:18:30.510050 RX Vref 0 -> 0, step: 1
2596 23:18:30.510115
2597 23:18:30.514014 RX Delay -40 -> 252, step: 8
2598 23:18:30.516844 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2599 23:18:30.520045 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2600 23:18:30.526980 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2601 23:18:30.530626 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2602 23:18:30.533763 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2603 23:18:30.537503 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2604 23:18:30.540759 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2605 23:18:30.544075 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2606 23:18:30.550669 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2607 23:18:30.553965 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2608 23:18:30.557513 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2609 23:18:30.560736 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2610 23:18:30.564380 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2611 23:18:30.570991 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2612 23:18:30.574588 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2613 23:18:30.577486 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2614 23:18:30.577580 ==
2615 23:18:30.581151 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 23:18:30.584101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 23:18:30.584183 ==
2618 23:18:30.587427 DQS Delay:
2619 23:18:30.587505 DQS0 = 0, DQS1 = 0
2620 23:18:30.587566 DQM Delay:
2621 23:18:30.590922 DQM0 = 115, DQM1 = 108
2622 23:18:30.591005 DQ Delay:
2623 23:18:30.594285 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2624 23:18:30.597486 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2625 23:18:30.601095 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2626 23:18:30.607834 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2627 23:18:30.607919
2628 23:18:30.607980
2629 23:18:30.608037 ==
2630 23:18:30.610783 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 23:18:30.614218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 23:18:30.614288 ==
2633 23:18:30.614346
2634 23:18:30.614423
2635 23:18:30.617593 TX Vref Scan disable
2636 23:18:30.617656 == TX Byte 0 ==
2637 23:18:30.624489 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2638 23:18:30.627764 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2639 23:18:30.627870 == TX Byte 1 ==
2640 23:18:30.634340 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2641 23:18:30.637534 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2642 23:18:30.637617 ==
2643 23:18:30.640998 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 23:18:30.644237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 23:18:30.644322 ==
2646 23:18:30.656982 TX Vref=22, minBit 1, minWin=24, winSum=417
2647 23:18:30.660063 TX Vref=24, minBit 1, minWin=25, winSum=420
2648 23:18:30.663591 TX Vref=26, minBit 1, minWin=25, winSum=424
2649 23:18:30.666818 TX Vref=28, minBit 1, minWin=26, winSum=430
2650 23:18:30.670348 TX Vref=30, minBit 0, minWin=26, winSum=432
2651 23:18:30.673635 TX Vref=32, minBit 0, minWin=26, winSum=432
2652 23:18:30.680474 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 30
2653 23:18:30.680600
2654 23:18:30.684220 Final TX Range 1 Vref 30
2655 23:18:30.684308
2656 23:18:30.684370 ==
2657 23:18:30.686821 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 23:18:30.690293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 23:18:30.690406 ==
2660 23:18:30.690490
2661 23:18:30.690549
2662 23:18:30.694063 TX Vref Scan disable
2663 23:18:30.697038 == TX Byte 0 ==
2664 23:18:30.700975 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2665 23:18:30.703734 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2666 23:18:30.707448 == TX Byte 1 ==
2667 23:18:30.710889 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2668 23:18:30.713905 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2669 23:18:30.714018
2670 23:18:30.717581 [DATLAT]
2671 23:18:30.717655 Freq=1200, CH0 RK0
2672 23:18:30.717716
2673 23:18:30.721145 DATLAT Default: 0xd
2674 23:18:30.721231 0, 0xFFFF, sum = 0
2675 23:18:30.724007 1, 0xFFFF, sum = 0
2676 23:18:30.724115 2, 0xFFFF, sum = 0
2677 23:18:30.727686 3, 0xFFFF, sum = 0
2678 23:18:30.727809 4, 0xFFFF, sum = 0
2679 23:18:30.730967 5, 0xFFFF, sum = 0
2680 23:18:30.731083 6, 0xFFFF, sum = 0
2681 23:18:30.734203 7, 0xFFFF, sum = 0
2682 23:18:30.734313 8, 0xFFFF, sum = 0
2683 23:18:30.737796 9, 0xFFFF, sum = 0
2684 23:18:30.737891 10, 0xFFFF, sum = 0
2685 23:18:30.741012 11, 0xFFFF, sum = 0
2686 23:18:30.741104 12, 0x0, sum = 1
2687 23:18:30.744584 13, 0x0, sum = 2
2688 23:18:30.744676 14, 0x0, sum = 3
2689 23:18:30.748127 15, 0x0, sum = 4
2690 23:18:30.748224 best_step = 13
2691 23:18:30.748308
2692 23:18:30.748389 ==
2693 23:18:30.751217 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 23:18:30.754738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 23:18:30.758456 ==
2696 23:18:30.758558 RX Vref Scan: 1
2697 23:18:30.758645
2698 23:18:30.761472 Set Vref Range= 32 -> 127
2699 23:18:30.761559
2700 23:18:30.761645 RX Vref 32 -> 127, step: 1
2701 23:18:30.764832
2702 23:18:30.764924 RX Delay -21 -> 252, step: 4
2703 23:18:30.765027
2704 23:18:30.767937 Set Vref, RX VrefLevel [Byte0]: 32
2705 23:18:30.771390 [Byte1]: 32
2706 23:18:30.775102
2707 23:18:30.775229 Set Vref, RX VrefLevel [Byte0]: 33
2708 23:18:30.778691 [Byte1]: 33
2709 23:18:30.782991
2710 23:18:30.783083 Set Vref, RX VrefLevel [Byte0]: 34
2711 23:18:30.786354 [Byte1]: 34
2712 23:18:30.790973
2713 23:18:30.791094 Set Vref, RX VrefLevel [Byte0]: 35
2714 23:18:30.794265 [Byte1]: 35
2715 23:18:30.799164
2716 23:18:30.799283 Set Vref, RX VrefLevel [Byte0]: 36
2717 23:18:30.802286 [Byte1]: 36
2718 23:18:30.806872
2719 23:18:30.806961 Set Vref, RX VrefLevel [Byte0]: 37
2720 23:18:30.810539 [Byte1]: 37
2721 23:18:30.814573
2722 23:18:30.814660 Set Vref, RX VrefLevel [Byte0]: 38
2723 23:18:30.818254 [Byte1]: 38
2724 23:18:30.822347
2725 23:18:30.822458 Set Vref, RX VrefLevel [Byte0]: 39
2726 23:18:30.826056 [Byte1]: 39
2727 23:18:30.830847
2728 23:18:30.830952 Set Vref, RX VrefLevel [Byte0]: 40
2729 23:18:30.833784 [Byte1]: 40
2730 23:18:30.838580
2731 23:18:30.838681 Set Vref, RX VrefLevel [Byte0]: 41
2732 23:18:30.841803 [Byte1]: 41
2733 23:18:30.846375
2734 23:18:30.846514 Set Vref, RX VrefLevel [Byte0]: 42
2735 23:18:30.850056 [Byte1]: 42
2736 23:18:30.854430
2737 23:18:30.854522 Set Vref, RX VrefLevel [Byte0]: 43
2738 23:18:30.858097 [Byte1]: 43
2739 23:18:30.862478
2740 23:18:30.862598 Set Vref, RX VrefLevel [Byte0]: 44
2741 23:18:30.865767 [Byte1]: 44
2742 23:18:30.870164
2743 23:18:30.870286 Set Vref, RX VrefLevel [Byte0]: 45
2744 23:18:30.873911 [Byte1]: 45
2745 23:18:30.878727
2746 23:18:30.878826 Set Vref, RX VrefLevel [Byte0]: 46
2747 23:18:30.881538 [Byte1]: 46
2748 23:18:30.886065
2749 23:18:30.886156 Set Vref, RX VrefLevel [Byte0]: 47
2750 23:18:30.889573 [Byte1]: 47
2751 23:18:30.893867
2752 23:18:30.893978 Set Vref, RX VrefLevel [Byte0]: 48
2753 23:18:30.897124 [Byte1]: 48
2754 23:18:30.901923
2755 23:18:30.902055 Set Vref, RX VrefLevel [Byte0]: 49
2756 23:18:30.905037 [Byte1]: 49
2757 23:18:30.909682
2758 23:18:30.909777 Set Vref, RX VrefLevel [Byte0]: 50
2759 23:18:30.912917 [Byte1]: 50
2760 23:18:30.917901
2761 23:18:30.918030 Set Vref, RX VrefLevel [Byte0]: 51
2762 23:18:30.920965 [Byte1]: 51
2763 23:18:30.925515
2764 23:18:30.925636 Set Vref, RX VrefLevel [Byte0]: 52
2765 23:18:30.929042 [Byte1]: 52
2766 23:18:30.933797
2767 23:18:30.933925 Set Vref, RX VrefLevel [Byte0]: 53
2768 23:18:30.937519 [Byte1]: 53
2769 23:18:30.941534
2770 23:18:30.941650 Set Vref, RX VrefLevel [Byte0]: 54
2771 23:18:30.944946 [Byte1]: 54
2772 23:18:30.949532
2773 23:18:30.949657 Set Vref, RX VrefLevel [Byte0]: 55
2774 23:18:30.952785 [Byte1]: 55
2775 23:18:30.957255
2776 23:18:30.957384 Set Vref, RX VrefLevel [Byte0]: 56
2777 23:18:30.960800 [Byte1]: 56
2778 23:18:30.965328
2779 23:18:30.965464 Set Vref, RX VrefLevel [Byte0]: 57
2780 23:18:30.968617 [Byte1]: 57
2781 23:18:30.973292
2782 23:18:30.973417 Set Vref, RX VrefLevel [Byte0]: 58
2783 23:18:30.976422 [Byte1]: 58
2784 23:18:30.981948
2785 23:18:30.982078 Set Vref, RX VrefLevel [Byte0]: 59
2786 23:18:30.984284 [Byte1]: 59
2787 23:18:30.989034
2788 23:18:30.989155 Set Vref, RX VrefLevel [Byte0]: 60
2789 23:18:30.992256 [Byte1]: 60
2790 23:18:30.997127
2791 23:18:30.997249 Set Vref, RX VrefLevel [Byte0]: 61
2792 23:18:31.000184 [Byte1]: 61
2793 23:18:31.004733
2794 23:18:31.004860 Set Vref, RX VrefLevel [Byte0]: 62
2795 23:18:31.008436 [Byte1]: 62
2796 23:18:31.013129
2797 23:18:31.013222 Set Vref, RX VrefLevel [Byte0]: 63
2798 23:18:31.016293 [Byte1]: 63
2799 23:18:31.020827
2800 23:18:31.020914 Set Vref, RX VrefLevel [Byte0]: 64
2801 23:18:31.024038 [Byte1]: 64
2802 23:18:31.028790
2803 23:18:31.028883 Set Vref, RX VrefLevel [Byte0]: 65
2804 23:18:31.032100 [Byte1]: 65
2805 23:18:31.036516
2806 23:18:31.036606 Set Vref, RX VrefLevel [Byte0]: 66
2807 23:18:31.040104 [Byte1]: 66
2808 23:18:31.044561
2809 23:18:31.044644 Set Vref, RX VrefLevel [Byte0]: 67
2810 23:18:31.048544 [Byte1]: 67
2811 23:18:31.052724
2812 23:18:31.052815 Set Vref, RX VrefLevel [Byte0]: 68
2813 23:18:31.055965 [Byte1]: 68
2814 23:18:31.060709
2815 23:18:31.060839 Set Vref, RX VrefLevel [Byte0]: 69
2816 23:18:31.063668 [Byte1]: 69
2817 23:18:31.068346
2818 23:18:31.068472 Set Vref, RX VrefLevel [Byte0]: 70
2819 23:18:31.071814 [Byte1]: 70
2820 23:18:31.076271
2821 23:18:31.076387 Set Vref, RX VrefLevel [Byte0]: 71
2822 23:18:31.079714 [Byte1]: 71
2823 23:18:31.083931
2824 23:18:31.084027 Final RX Vref Byte 0 = 58 to rank0
2825 23:18:31.087514 Final RX Vref Byte 1 = 51 to rank0
2826 23:18:31.091587 Final RX Vref Byte 0 = 58 to rank1
2827 23:18:31.094343 Final RX Vref Byte 1 = 51 to rank1==
2828 23:18:31.097696 Dram Type= 6, Freq= 0, CH_0, rank 0
2829 23:18:31.100872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 23:18:31.104697 ==
2831 23:18:31.104791 DQS Delay:
2832 23:18:31.104857 DQS0 = 0, DQS1 = 0
2833 23:18:31.107863 DQM Delay:
2834 23:18:31.107948 DQM0 = 115, DQM1 = 104
2835 23:18:31.111086 DQ Delay:
2836 23:18:31.114307 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2837 23:18:31.117948 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2838 23:18:31.121501 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2839 23:18:31.124206 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
2840 23:18:31.124320
2841 23:18:31.124411
2842 23:18:31.131403 [DQSOSCAuto] RK0, (LSB)MR18= 0xfaea, (MSB)MR19= 0x303, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
2843 23:18:31.134529 CH0 RK0: MR19=303, MR18=FAEA
2844 23:18:31.141388 CH0_RK0: MR19=0x303, MR18=0xFAEA, DQSOSC=412, MR23=63, INC=38, DEC=25
2845 23:18:31.141527
2846 23:18:31.144634 ----->DramcWriteLeveling(PI) begin...
2847 23:18:31.144749 ==
2848 23:18:31.147933 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 23:18:31.151900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 23:18:31.152013 ==
2851 23:18:31.154979 Write leveling (Byte 0): 32 => 32
2852 23:18:31.158149 Write leveling (Byte 1): 29 => 29
2853 23:18:31.161321 DramcWriteLeveling(PI) end<-----
2854 23:18:31.161437
2855 23:18:31.161527 ==
2856 23:18:31.164881 Dram Type= 6, Freq= 0, CH_0, rank 1
2857 23:18:31.167982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2858 23:18:31.168080 ==
2859 23:18:31.171387 [Gating] SW mode calibration
2860 23:18:31.178133 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2861 23:18:31.184875 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2862 23:18:31.188171 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2863 23:18:31.194681 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2864 23:18:32.436682 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 23:18:32.436900 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 23:18:32.437021 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 23:18:32.437135 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 23:18:32.437242 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2869 23:18:32.437352 0 15 28 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 0)
2870 23:18:32.437457 1 0 0 | B1->B0 | 2e2e 2a2a | 0 0 | (0 0) (0 0)
2871 23:18:32.437565 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2872 23:18:32.437668 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 23:18:32.437775 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 23:18:32.437879 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 23:18:32.437986 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 23:18:32.438088 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
2877 23:18:32.438187 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2878 23:18:32.438287 1 1 0 | B1->B0 | 2626 3e3e | 1 0 | (0 0) (0 0)
2879 23:18:32.438382 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2880 23:18:32.438484 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 23:18:32.438538 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 23:18:32.438591 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 23:18:32.438644 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 23:18:32.438696 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 23:18:32.438747 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2886 23:18:32.438798 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2887 23:18:32.438850 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 23:18:32.438902 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 23:18:32.438954 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 23:18:32.439006 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 23:18:32.439058 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 23:18:32.439109 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 23:18:32.439160 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 23:18:32.439211 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 23:18:32.439261 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 23:18:32.439312 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 23:18:32.439363 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 23:18:32.439414 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 23:18:32.439466 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 23:18:32.439517 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 23:18:32.439569 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2902 23:18:32.439620 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2903 23:18:32.439672 Total UI for P1: 0, mck2ui 16
2904 23:18:32.439724 best dqsien dly found for B0: ( 1, 3, 28)
2905 23:18:32.439776 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 23:18:32.439827 Total UI for P1: 0, mck2ui 16
2907 23:18:32.439879 best dqsien dly found for B1: ( 1, 4, 2)
2908 23:18:32.439930 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2909 23:18:32.439982 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2910 23:18:32.440034
2911 23:18:32.440085 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2912 23:18:32.440137 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2913 23:18:32.440188 [Gating] SW calibration Done
2914 23:18:32.440239 ==
2915 23:18:32.440291 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 23:18:32.440342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 23:18:32.440394 ==
2918 23:18:32.440445 RX Vref Scan: 0
2919 23:18:32.440496
2920 23:18:32.440548 RX Vref 0 -> 0, step: 1
2921 23:18:32.440598
2922 23:18:32.440658 RX Delay -40 -> 252, step: 8
2923 23:18:32.440710 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2924 23:18:32.440762 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2925 23:18:32.440814 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2926 23:18:32.440866 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2927 23:18:32.440917 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2928 23:18:32.440969 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2929 23:18:32.441020 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2930 23:18:32.441071 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2931 23:18:32.441123 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2932 23:18:32.441174 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2933 23:18:32.441225 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2934 23:18:32.441276 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2935 23:18:32.441327 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2936 23:18:32.441379 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2937 23:18:32.441430 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2938 23:18:32.441481 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2939 23:18:32.441532 ==
2940 23:18:32.441583 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 23:18:32.441634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 23:18:32.441686 ==
2943 23:18:32.441738 DQS Delay:
2944 23:18:32.441789 DQS0 = 0, DQS1 = 0
2945 23:18:32.441840 DQM Delay:
2946 23:18:32.441890 DQM0 = 116, DQM1 = 105
2947 23:18:32.441941 DQ Delay:
2948 23:18:32.441991 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2949 23:18:32.442042 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2950 23:18:32.442093 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =95
2951 23:18:32.442148 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2952 23:18:32.442199
2953 23:18:32.442250
2954 23:18:32.442301 ==
2955 23:18:32.442352 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 23:18:32.442445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 23:18:32.442500 ==
2958 23:18:32.442552
2959 23:18:32.442603
2960 23:18:32.442654 TX Vref Scan disable
2961 23:18:32.442705 == TX Byte 0 ==
2962 23:18:32.442757 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2963 23:18:32.442808 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2964 23:18:32.442860 == TX Byte 1 ==
2965 23:18:32.442911 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2966 23:18:32.442962 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2967 23:18:32.443013 ==
2968 23:18:32.443065 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 23:18:32.443116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 23:18:32.443168 ==
2971 23:18:32.443220 TX Vref=22, minBit 0, minWin=26, winSum=429
2972 23:18:32.443490 TX Vref=24, minBit 3, minWin=25, winSum=428
2973 23:18:32.443550 TX Vref=26, minBit 3, minWin=26, winSum=433
2974 23:18:32.443603 TX Vref=28, minBit 0, minWin=27, winSum=439
2975 23:18:32.443655 TX Vref=30, minBit 0, minWin=27, winSum=439
2976 23:18:32.443706 TX Vref=32, minBit 0, minWin=27, winSum=438
2977 23:18:32.443762 [TxChooseVref] Worse bit 0, Min win 27, Win sum 439, Final Vref 28
2978 23:18:32.443816
2979 23:18:32.443868 Final TX Range 1 Vref 28
2980 23:18:32.443919
2981 23:18:32.443970 ==
2982 23:18:32.444022 Dram Type= 6, Freq= 0, CH_0, rank 1
2983 23:18:32.444073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2984 23:18:32.444125 ==
2985 23:18:32.444176
2986 23:18:32.444226
2987 23:18:32.444276 TX Vref Scan disable
2988 23:18:32.444328 == TX Byte 0 ==
2989 23:18:32.444379 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2990 23:18:32.444431 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2991 23:18:32.444482 == TX Byte 1 ==
2992 23:18:32.444533 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2993 23:18:32.444584 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2994 23:18:32.444635
2995 23:18:32.444685 [DATLAT]
2996 23:18:32.444736 Freq=1200, CH0 RK1
2997 23:18:32.444787
2998 23:18:32.444838 DATLAT Default: 0xd
2999 23:18:32.444889 0, 0xFFFF, sum = 0
3000 23:18:32.444942 1, 0xFFFF, sum = 0
3001 23:18:32.444994 2, 0xFFFF, sum = 0
3002 23:18:32.445046 3, 0xFFFF, sum = 0
3003 23:18:32.445098 4, 0xFFFF, sum = 0
3004 23:18:32.445150 5, 0xFFFF, sum = 0
3005 23:18:32.445201 6, 0xFFFF, sum = 0
3006 23:18:32.445253 7, 0xFFFF, sum = 0
3007 23:18:32.445305 8, 0xFFFF, sum = 0
3008 23:18:32.445357 9, 0xFFFF, sum = 0
3009 23:18:32.445408 10, 0xFFFF, sum = 0
3010 23:18:32.445459 11, 0xFFFF, sum = 0
3011 23:18:32.445511 12, 0x0, sum = 1
3012 23:18:32.445562 13, 0x0, sum = 2
3013 23:18:32.445613 14, 0x0, sum = 3
3014 23:18:32.445664 15, 0x0, sum = 4
3015 23:18:32.445716 best_step = 13
3016 23:18:32.445767
3017 23:18:32.445817 ==
3018 23:18:32.445868 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 23:18:32.445919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 23:18:32.445971 ==
3021 23:18:32.446022 RX Vref Scan: 0
3022 23:18:32.446073
3023 23:18:32.446123 RX Vref 0 -> 0, step: 1
3024 23:18:32.446174
3025 23:18:32.446224 RX Delay -21 -> 252, step: 4
3026 23:18:32.446275 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3027 23:18:32.446327 iDelay=195, Bit 1, Center 112 (39 ~ 186) 148
3028 23:18:32.446377 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
3029 23:18:32.446471 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3030 23:18:32.446523 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3031 23:18:32.446574 iDelay=195, Bit 5, Center 106 (39 ~ 174) 136
3032 23:18:32.446625 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3033 23:18:32.446676 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3034 23:18:32.446727 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3035 23:18:32.446778 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3036 23:18:32.446830 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3037 23:18:32.446881 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3038 23:18:32.446932 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3039 23:18:32.446983 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3040 23:18:32.447035 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3041 23:18:32.447122 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3042 23:18:32.447174 ==
3043 23:18:32.447225 Dram Type= 6, Freq= 0, CH_0, rank 1
3044 23:18:32.447277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 23:18:32.447329 ==
3046 23:18:32.447380 DQS Delay:
3047 23:18:32.447432 DQS0 = 0, DQS1 = 0
3048 23:18:32.447483 DQM Delay:
3049 23:18:32.447535 DQM0 = 114, DQM1 = 104
3050 23:18:32.447586 DQ Delay:
3051 23:18:32.447637 DQ0 =114, DQ1 =112, DQ2 =112, DQ3 =114
3052 23:18:32.447688 DQ4 =112, DQ5 =106, DQ6 =122, DQ7 =122
3053 23:18:32.447740 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3054 23:18:32.447791 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3055 23:18:32.447842
3056 23:18:32.447892
3057 23:18:32.447943 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3058 23:18:32.447996 CH0 RK1: MR19=403, MR18=5F5
3059 23:18:32.448047 CH0_RK1: MR19=0x403, MR18=0x5F5, DQSOSC=408, MR23=63, INC=39, DEC=26
3060 23:18:32.448099 [RxdqsGatingPostProcess] freq 1200
3061 23:18:32.448150 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3062 23:18:32.448201 best DQS0 dly(2T, 0.5T) = (0, 12)
3063 23:18:32.448252 best DQS1 dly(2T, 0.5T) = (0, 12)
3064 23:18:32.448304 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3065 23:18:32.448355 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3066 23:18:32.448406 best DQS0 dly(2T, 0.5T) = (0, 11)
3067 23:18:32.448457 best DQS1 dly(2T, 0.5T) = (0, 12)
3068 23:18:32.448509 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3069 23:18:32.448560 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3070 23:18:32.448611 Pre-setting of DQS Precalculation
3071 23:18:32.448663 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3072 23:18:32.448714 ==
3073 23:18:32.448765 Dram Type= 6, Freq= 0, CH_1, rank 0
3074 23:18:32.448816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 23:18:32.448868 ==
3076 23:18:32.448919 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3077 23:18:32.448970 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3078 23:18:32.449022 [CA 0] Center 38 (9~68) winsize 60
3079 23:18:32.449073 [CA 1] Center 38 (8~68) winsize 61
3080 23:18:32.449124 [CA 2] Center 35 (5~65) winsize 61
3081 23:18:32.449176 [CA 3] Center 34 (4~65) winsize 62
3082 23:18:32.449228 [CA 4] Center 34 (4~65) winsize 62
3083 23:18:32.449279 [CA 5] Center 34 (4~64) winsize 61
3084 23:18:32.449329
3085 23:18:32.449380 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3086 23:18:32.449431
3087 23:18:32.449482 [CATrainingPosCal] consider 1 rank data
3088 23:18:32.449533 u2DelayCellTimex100 = 270/100 ps
3089 23:18:32.449584 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3090 23:18:32.449636 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3091 23:18:32.449687 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3092 23:18:32.449739 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3093 23:18:32.449789 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3094 23:18:32.449872 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3095 23:18:32.449922
3096 23:18:32.449973 CA PerBit enable=1, Macro0, CA PI delay=34
3097 23:18:32.450024
3098 23:18:32.450074 [CBTSetCACLKResult] CA Dly = 34
3099 23:18:32.450125 CS Dly: 6 (0~37)
3100 23:18:32.450176 ==
3101 23:18:32.450227 Dram Type= 6, Freq= 0, CH_1, rank 1
3102 23:18:32.450278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 23:18:32.450329 ==
3104 23:18:32.450380 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3105 23:18:32.450677 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3106 23:18:32.450737 [CA 0] Center 38 (8~68) winsize 61
3107 23:18:32.450790 [CA 1] Center 38 (8~68) winsize 61
3108 23:18:32.450848 [CA 2] Center 34 (4~65) winsize 62
3109 23:18:32.450900 [CA 3] Center 34 (3~65) winsize 63
3110 23:18:32.450952 [CA 4] Center 34 (4~65) winsize 62
3111 23:18:32.451003 [CA 5] Center 33 (3~63) winsize 61
3112 23:18:32.451055
3113 23:18:32.451106 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3114 23:18:32.451157
3115 23:18:32.451208 [CATrainingPosCal] consider 2 rank data
3116 23:18:32.451259 u2DelayCellTimex100 = 270/100 ps
3117 23:18:32.451310 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3118 23:18:32.451361 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3119 23:18:32.451413 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3120 23:18:32.451464 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3121 23:18:32.451515 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3122 23:18:32.451566 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3123 23:18:32.451617
3124 23:18:32.451667 CA PerBit enable=1, Macro0, CA PI delay=33
3125 23:18:32.451718
3126 23:18:32.451768 [CBTSetCACLKResult] CA Dly = 33
3127 23:18:32.451820 CS Dly: 7 (0~40)
3128 23:18:32.451870
3129 23:18:32.451921 ----->DramcWriteLeveling(PI) begin...
3130 23:18:32.451974 ==
3131 23:18:32.452025 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 23:18:32.452076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 23:18:32.452127 ==
3134 23:18:32.452177 Write leveling (Byte 0): 25 => 25
3135 23:18:32.452229 Write leveling (Byte 1): 30 => 30
3136 23:18:32.452280 DramcWriteLeveling(PI) end<-----
3137 23:18:32.452330
3138 23:18:32.452381 ==
3139 23:18:32.452431 Dram Type= 6, Freq= 0, CH_1, rank 0
3140 23:18:32.452482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3141 23:18:32.452534 ==
3142 23:18:32.452585 [Gating] SW mode calibration
3143 23:18:32.452636 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3144 23:18:32.452688 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3145 23:18:32.452739 0 15 0 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
3146 23:18:32.452790 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 23:18:32.452842 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 23:18:32.452893 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 23:18:32.452944 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 23:18:32.452995 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 23:18:32.453046 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 23:18:32.453097 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3153 23:18:32.453148 1 0 0 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 0)
3154 23:18:32.453199 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 23:18:32.453250 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3156 23:18:32.453301 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 23:18:32.453352 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 23:18:32.453404 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 23:18:32.453455 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 23:18:32.453506 1 0 28 | B1->B0 | 2a2a 2727 | 0 0 | (0 0) (0 0)
3161 23:18:32.453558 1 1 0 | B1->B0 | 4343 3636 | 0 0 | (0 0) (0 0)
3162 23:18:32.453609 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 23:18:32.453660 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 23:18:32.453710 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 23:18:32.453761 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 23:18:32.453812 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 23:18:32.453863 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 23:18:32.453919 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 23:18:32.453971 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3170 23:18:32.454023 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 23:18:32.454074 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 23:18:32.454124 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 23:18:32.454175 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 23:18:32.454226 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 23:18:32.454277 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 23:18:32.454327 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 23:18:32.454378 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 23:18:32.454480 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 23:18:32.454533 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 23:18:32.454584 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 23:18:32.454635 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 23:18:32.454687 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 23:18:32.454738 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 23:18:32.454789 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3185 23:18:32.454840 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3186 23:18:32.454891 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 23:18:32.454943 Total UI for P1: 0, mck2ui 16
3188 23:18:32.454994 best dqsien dly found for B0: ( 1, 3, 30)
3189 23:18:32.455047 Total UI for P1: 0, mck2ui 16
3190 23:18:32.455098 best dqsien dly found for B1: ( 1, 4, 0)
3191 23:18:32.455150 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3192 23:18:32.455202 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3193 23:18:32.455253
3194 23:18:32.455304 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3195 23:18:32.455355 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3196 23:18:32.455406 [Gating] SW calibration Done
3197 23:18:32.455458 ==
3198 23:18:32.455509 Dram Type= 6, Freq= 0, CH_1, rank 0
3199 23:18:32.455560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 23:18:32.455611 ==
3201 23:18:32.455662 RX Vref Scan: 0
3202 23:18:32.455713
3203 23:18:32.455763 RX Vref 0 -> 0, step: 1
3204 23:18:32.455814
3205 23:18:32.455865 RX Delay -40 -> 252, step: 8
3206 23:18:32.455916 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3207 23:18:32.455967 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3208 23:18:32.456019 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3209 23:18:32.456070 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3210 23:18:32.456316 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3211 23:18:32.456376 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3212 23:18:32.456429 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3213 23:18:32.456480 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3214 23:18:32.456531 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3215 23:18:32.456583 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3216 23:18:32.456634 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3217 23:18:32.456685 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3218 23:18:32.456736 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3219 23:18:32.456788 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3220 23:18:32.456839 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3221 23:18:32.456890 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3222 23:18:32.456942 ==
3223 23:18:32.456993 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 23:18:32.457044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 23:18:32.457095 ==
3226 23:18:32.457146 DQS Delay:
3227 23:18:32.457197 DQS0 = 0, DQS1 = 0
3228 23:18:32.457251 DQM Delay:
3229 23:18:32.457302 DQM0 = 116, DQM1 = 109
3230 23:18:32.457353 DQ Delay:
3231 23:18:32.457404 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3232 23:18:32.457455 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3233 23:18:32.457506 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3234 23:18:32.457563 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
3235 23:18:32.457644
3236 23:18:32.457723
3237 23:18:32.457802 ==
3238 23:18:32.457882 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 23:18:32.457963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 23:18:32.458044 ==
3241 23:18:32.458123
3242 23:18:32.458202
3243 23:18:32.458282 TX Vref Scan disable
3244 23:18:32.458361 == TX Byte 0 ==
3245 23:18:32.458484 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3246 23:18:32.458566 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3247 23:18:32.458646 == TX Byte 1 ==
3248 23:18:32.458726 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3249 23:18:32.458807 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3250 23:18:32.458887 ==
3251 23:18:32.458967 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 23:18:32.459048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 23:18:32.459128 ==
3254 23:18:32.459209 TX Vref=22, minBit 0, minWin=25, winSum=411
3255 23:18:32.459290 TX Vref=24, minBit 15, minWin=24, winSum=416
3256 23:18:32.459371 TX Vref=26, minBit 1, minWin=25, winSum=420
3257 23:18:32.459451 TX Vref=28, minBit 1, minWin=26, winSum=426
3258 23:18:32.459532 TX Vref=30, minBit 0, minWin=26, winSum=432
3259 23:18:32.459622 TX Vref=32, minBit 1, minWin=26, winSum=426
3260 23:18:32.459679 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 30
3261 23:18:32.459732
3262 23:18:32.459783 Final TX Range 1 Vref 30
3263 23:18:32.459835
3264 23:18:32.459885 ==
3265 23:18:32.459937 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 23:18:32.459989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 23:18:32.460041 ==
3268 23:18:32.460092
3269 23:18:32.460142
3270 23:18:32.460193 TX Vref Scan disable
3271 23:18:32.460244 == TX Byte 0 ==
3272 23:18:32.460295 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3273 23:18:32.460346 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3274 23:18:32.460397 == TX Byte 1 ==
3275 23:18:32.460464 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3276 23:18:32.460519 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3277 23:18:32.460571
3278 23:18:32.463622 [DATLAT]
3279 23:18:32.463706 Freq=1200, CH1 RK0
3280 23:18:32.463770
3281 23:18:32.467017 DATLAT Default: 0xd
3282 23:18:32.467101 0, 0xFFFF, sum = 0
3283 23:18:32.470225 1, 0xFFFF, sum = 0
3284 23:18:32.470309 2, 0xFFFF, sum = 0
3285 23:18:32.474144 3, 0xFFFF, sum = 0
3286 23:18:32.474234 4, 0xFFFF, sum = 0
3287 23:18:32.477145 5, 0xFFFF, sum = 0
3288 23:18:32.477230 6, 0xFFFF, sum = 0
3289 23:18:32.480150 7, 0xFFFF, sum = 0
3290 23:18:32.480234 8, 0xFFFF, sum = 0
3291 23:18:32.483501 9, 0xFFFF, sum = 0
3292 23:18:32.483594 10, 0xFFFF, sum = 0
3293 23:18:32.487162 11, 0xFFFF, sum = 0
3294 23:18:32.487256 12, 0x0, sum = 1
3295 23:18:32.490231 13, 0x0, sum = 2
3296 23:18:32.490319 14, 0x0, sum = 3
3297 23:18:32.493839 15, 0x0, sum = 4
3298 23:18:32.493924 best_step = 13
3299 23:18:32.493988
3300 23:18:32.494047 ==
3301 23:18:32.497245 Dram Type= 6, Freq= 0, CH_1, rank 0
3302 23:18:32.503975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3303 23:18:32.504090 ==
3304 23:18:32.504188 RX Vref Scan: 1
3305 23:18:32.504277
3306 23:18:32.506908 Set Vref Range= 32 -> 127
3307 23:18:32.506990
3308 23:18:32.510347 RX Vref 32 -> 127, step: 1
3309 23:18:32.510483
3310 23:18:32.510547 RX Delay -21 -> 252, step: 4
3311 23:18:32.510606
3312 23:18:32.514122 Set Vref, RX VrefLevel [Byte0]: 32
3313 23:18:32.517389 [Byte1]: 32
3314 23:18:32.521802
3315 23:18:32.521892 Set Vref, RX VrefLevel [Byte0]: 33
3316 23:18:32.524693 [Byte1]: 33
3317 23:18:32.529667
3318 23:18:32.529762 Set Vref, RX VrefLevel [Byte0]: 34
3319 23:18:32.532746 [Byte1]: 34
3320 23:18:32.537180
3321 23:18:32.537308 Set Vref, RX VrefLevel [Byte0]: 35
3322 23:18:32.540555 [Byte1]: 35
3323 23:18:32.545369
3324 23:18:32.545495 Set Vref, RX VrefLevel [Byte0]: 36
3325 23:18:32.548941 [Byte1]: 36
3326 23:18:32.553322
3327 23:18:32.553414 Set Vref, RX VrefLevel [Byte0]: 37
3328 23:18:32.556571 [Byte1]: 37
3329 23:18:32.560807
3330 23:18:32.560896 Set Vref, RX VrefLevel [Byte0]: 38
3331 23:18:32.564374 [Byte1]: 38
3332 23:18:32.568734
3333 23:18:32.568821 Set Vref, RX VrefLevel [Byte0]: 39
3334 23:18:32.572301 [Byte1]: 39
3335 23:18:32.576739
3336 23:18:32.576827 Set Vref, RX VrefLevel [Byte0]: 40
3337 23:18:32.580125 [Byte1]: 40
3338 23:18:32.584567
3339 23:18:32.584656 Set Vref, RX VrefLevel [Byte0]: 41
3340 23:18:32.588204 [Byte1]: 41
3341 23:18:32.592971
3342 23:18:32.593065 Set Vref, RX VrefLevel [Byte0]: 42
3343 23:18:32.596297 [Byte1]: 42
3344 23:18:32.600968
3345 23:18:32.601056 Set Vref, RX VrefLevel [Byte0]: 43
3346 23:18:32.604064 [Byte1]: 43
3347 23:18:32.608783
3348 23:18:32.608869 Set Vref, RX VrefLevel [Byte0]: 44
3349 23:18:32.611832 [Byte1]: 44
3350 23:18:32.616590
3351 23:18:32.616678 Set Vref, RX VrefLevel [Byte0]: 45
3352 23:18:32.619982 [Byte1]: 45
3353 23:18:32.624448
3354 23:18:32.624536 Set Vref, RX VrefLevel [Byte0]: 46
3355 23:18:32.627743 [Byte1]: 46
3356 23:18:32.632054
3357 23:18:32.632145 Set Vref, RX VrefLevel [Byte0]: 47
3358 23:18:32.635599 [Byte1]: 47
3359 23:18:32.640464
3360 23:18:32.640556 Set Vref, RX VrefLevel [Byte0]: 48
3361 23:18:32.643662 [Byte1]: 48
3362 23:18:32.648297
3363 23:18:32.648384 Set Vref, RX VrefLevel [Byte0]: 49
3364 23:18:32.651412 [Byte1]: 49
3365 23:18:32.656239
3366 23:18:32.656331 Set Vref, RX VrefLevel [Byte0]: 50
3367 23:18:32.659456 [Byte1]: 50
3368 23:18:32.664131
3369 23:18:32.664261 Set Vref, RX VrefLevel [Byte0]: 51
3370 23:18:32.667134 [Byte1]: 51
3371 23:18:32.671842
3372 23:18:32.671931 Set Vref, RX VrefLevel [Byte0]: 52
3373 23:18:32.675055 [Byte1]: 52
3374 23:18:32.679622
3375 23:18:32.679708 Set Vref, RX VrefLevel [Byte0]: 53
3376 23:18:32.682985 [Byte1]: 53
3377 23:18:32.688083
3378 23:18:32.688171 Set Vref, RX VrefLevel [Byte0]: 54
3379 23:18:32.690934 [Byte1]: 54
3380 23:18:32.695995
3381 23:18:32.696082 Set Vref, RX VrefLevel [Byte0]: 55
3382 23:18:32.699116 [Byte1]: 55
3383 23:18:32.703422
3384 23:18:32.703508 Set Vref, RX VrefLevel [Byte0]: 56
3385 23:18:32.706838 [Byte1]: 56
3386 23:18:32.711364
3387 23:18:32.711450 Set Vref, RX VrefLevel [Byte0]: 57
3388 23:18:32.714739 [Byte1]: 57
3389 23:18:32.719292
3390 23:18:32.719378 Set Vref, RX VrefLevel [Byte0]: 58
3391 23:18:32.722961 [Byte1]: 58
3392 23:18:32.727313
3393 23:18:32.727401 Set Vref, RX VrefLevel [Byte0]: 59
3394 23:18:32.730638 [Byte1]: 59
3395 23:18:32.735194
3396 23:18:32.735283 Set Vref, RX VrefLevel [Byte0]: 60
3397 23:18:32.738335 [Byte1]: 60
3398 23:18:32.743313
3399 23:18:32.743404 Set Vref, RX VrefLevel [Byte0]: 61
3400 23:18:32.746681 [Byte1]: 61
3401 23:18:32.751032
3402 23:18:32.751117 Set Vref, RX VrefLevel [Byte0]: 62
3403 23:18:32.754348 [Byte1]: 62
3404 23:18:32.758728
3405 23:18:32.758843 Set Vref, RX VrefLevel [Byte0]: 63
3406 23:18:32.762157 [Byte1]: 63
3407 23:18:32.767016
3408 23:18:32.767104 Set Vref, RX VrefLevel [Byte0]: 64
3409 23:18:32.770425 [Byte1]: 64
3410 23:18:32.774746
3411 23:18:32.774885 Set Vref, RX VrefLevel [Byte0]: 65
3412 23:18:32.778272 [Byte1]: 65
3413 23:18:32.782999
3414 23:18:32.783119 Set Vref, RX VrefLevel [Byte0]: 66
3415 23:18:32.786269 [Byte1]: 66
3416 23:18:32.791092
3417 23:18:32.791183 Set Vref, RX VrefLevel [Byte0]: 67
3418 23:18:32.794295 [Byte1]: 67
3419 23:18:32.798952
3420 23:18:32.799041 Set Vref, RX VrefLevel [Byte0]: 68
3421 23:18:32.801895 [Byte1]: 68
3422 23:18:32.806856
3423 23:18:32.806980 Set Vref, RX VrefLevel [Byte0]: 69
3424 23:18:32.810246 [Byte1]: 69
3425 23:18:32.814872
3426 23:18:32.814988 Final RX Vref Byte 0 = 57 to rank0
3427 23:18:32.817737 Final RX Vref Byte 1 = 46 to rank0
3428 23:18:32.821662 Final RX Vref Byte 0 = 57 to rank1
3429 23:18:32.824476 Final RX Vref Byte 1 = 46 to rank1==
3430 23:18:32.828030 Dram Type= 6, Freq= 0, CH_1, rank 0
3431 23:18:32.831314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 23:18:32.834751 ==
3433 23:18:32.834839 DQS Delay:
3434 23:18:32.834902 DQS0 = 0, DQS1 = 0
3435 23:18:32.838167 DQM Delay:
3436 23:18:32.838251 DQM0 = 116, DQM1 = 107
3437 23:18:32.841722 DQ Delay:
3438 23:18:32.845244 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3439 23:18:32.847963 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =112
3440 23:18:32.851556 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =102
3441 23:18:32.854958 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3442 23:18:32.855044
3443 23:18:32.855108
3444 23:18:32.861534 [DQSOSCAuto] RK0, (LSB)MR18= 0xe5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3445 23:18:32.864945 CH1 RK0: MR19=403, MR18=E5
3446 23:18:32.871899 CH1_RK0: MR19=0x403, MR18=0xE5, DQSOSC=410, MR23=63, INC=39, DEC=26
3447 23:18:32.872003
3448 23:18:32.875061 ----->DramcWriteLeveling(PI) begin...
3449 23:18:32.875146 ==
3450 23:18:32.878350 Dram Type= 6, Freq= 0, CH_1, rank 1
3451 23:18:32.881787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 23:18:32.881872 ==
3453 23:18:32.884966 Write leveling (Byte 0): 26 => 26
3454 23:18:32.888426 Write leveling (Byte 1): 26 => 26
3455 23:18:32.891684 DramcWriteLeveling(PI) end<-----
3456 23:18:32.891771
3457 23:18:32.891834 ==
3458 23:18:32.894955 Dram Type= 6, Freq= 0, CH_1, rank 1
3459 23:18:32.898302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 23:18:32.898450 ==
3461 23:18:32.901923 [Gating] SW mode calibration
3462 23:18:32.908768 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3463 23:18:32.915390 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3464 23:18:32.918515 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3465 23:18:32.921684 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 23:18:32.928708 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 23:18:32.931785 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 23:18:32.935500 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 23:18:32.941905 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3470 23:18:32.945320 0 15 24 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
3471 23:18:32.948705 0 15 28 | B1->B0 | 2d2d 2323 | 1 0 | (1 1) (0 0)
3472 23:18:32.955563 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 23:18:32.958875 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3474 23:18:32.961929 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3475 23:18:32.968923 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 23:18:32.972222 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 23:18:32.975615 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 23:18:32.981771 1 0 24 | B1->B0 | 2828 4141 | 0 0 | (0 0) (0 0)
3479 23:18:32.985393 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3480 23:18:32.988338 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3481 23:18:32.991760 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 23:18:32.998913 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 23:18:33.001901 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 23:18:33.005021 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 23:18:33.011577 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 23:18:33.015207 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3487 23:18:33.018361 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3488 23:18:33.025005 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 23:18:33.029227 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 23:18:33.031891 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 23:18:33.038331 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 23:18:33.041753 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 23:18:33.045216 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 23:18:33.051956 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 23:18:33.055208 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 23:18:33.058664 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 23:18:33.065425 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 23:18:33.069089 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 23:18:33.071799 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 23:18:33.078894 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 23:18:33.081626 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3502 23:18:33.084998 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3503 23:18:33.088586 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3504 23:18:33.091744 Total UI for P1: 0, mck2ui 16
3505 23:18:33.095496 best dqsien dly found for B0: ( 1, 3, 22)
3506 23:18:33.102054 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 23:18:33.105475 Total UI for P1: 0, mck2ui 16
3508 23:18:33.108244 best dqsien dly found for B1: ( 1, 3, 28)
3509 23:18:33.111829 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3510 23:18:33.115321 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3511 23:18:33.115406
3512 23:18:33.118827 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3513 23:18:33.121607 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3514 23:18:33.125021 [Gating] SW calibration Done
3515 23:18:33.125107 ==
3516 23:18:33.128446 Dram Type= 6, Freq= 0, CH_1, rank 1
3517 23:18:33.131546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3518 23:18:33.131633 ==
3519 23:18:33.135060 RX Vref Scan: 0
3520 23:18:33.135146
3521 23:18:33.135210 RX Vref 0 -> 0, step: 1
3522 23:18:33.138576
3523 23:18:33.138662 RX Delay -40 -> 252, step: 8
3524 23:18:33.145110 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3525 23:18:33.149030 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3526 23:18:33.151780 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3527 23:18:33.155282 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3528 23:18:33.158677 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3529 23:18:33.162111 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3530 23:18:33.168717 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3531 23:18:33.171696 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3532 23:18:33.175070 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3533 23:18:33.178439 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3534 23:18:33.182011 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3535 23:18:33.188826 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3536 23:18:33.192092 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3537 23:18:33.195020 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3538 23:18:33.198271 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3539 23:18:33.201786 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3540 23:18:33.205085 ==
3541 23:18:33.205175 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 23:18:33.211815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 23:18:33.211913 ==
3544 23:18:33.211978 DQS Delay:
3545 23:18:33.215155 DQS0 = 0, DQS1 = 0
3546 23:18:33.215239 DQM Delay:
3547 23:18:33.218607 DQM0 = 113, DQM1 = 108
3548 23:18:33.218690 DQ Delay:
3549 23:18:33.222141 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3550 23:18:33.225506 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3551 23:18:33.228574 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =99
3552 23:18:33.231886 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3553 23:18:33.231978
3554 23:18:33.232042
3555 23:18:33.232101 ==
3556 23:18:33.235439 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 23:18:33.238427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 23:18:33.241977 ==
3559 23:18:33.242065
3560 23:18:33.242129
3561 23:18:33.242187 TX Vref Scan disable
3562 23:18:33.245141 == TX Byte 0 ==
3563 23:18:33.248476 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3564 23:18:33.251970 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3565 23:18:33.255341 == TX Byte 1 ==
3566 23:18:33.259019 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3567 23:18:33.262393 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3568 23:18:33.262510 ==
3569 23:18:33.265710 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 23:18:33.272236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 23:18:33.272334 ==
3572 23:18:33.282692 TX Vref=22, minBit 0, minWin=25, winSum=409
3573 23:18:33.286155 TX Vref=24, minBit 1, minWin=25, winSum=415
3574 23:18:33.289274 TX Vref=26, minBit 4, minWin=26, winSum=427
3575 23:18:33.292765 TX Vref=28, minBit 1, minWin=25, winSum=426
3576 23:18:33.295918 TX Vref=30, minBit 4, minWin=26, winSum=430
3577 23:18:33.299236 TX Vref=32, minBit 0, minWin=26, winSum=432
3578 23:18:33.305919 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 32
3579 23:18:33.306048
3580 23:18:33.309660 Final TX Range 1 Vref 32
3581 23:18:33.309758
3582 23:18:33.309822 ==
3583 23:18:33.312572 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 23:18:33.315966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 23:18:33.316051 ==
3586 23:18:33.316114
3587 23:18:33.319455
3588 23:18:33.319539 TX Vref Scan disable
3589 23:18:33.322862 == TX Byte 0 ==
3590 23:18:33.326279 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3591 23:18:33.329559 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3592 23:18:33.332791 == TX Byte 1 ==
3593 23:18:33.336502 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3594 23:18:33.339489 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3595 23:18:33.339579
3596 23:18:33.342723 [DATLAT]
3597 23:18:33.342806 Freq=1200, CH1 RK1
3598 23:18:33.342870
3599 23:18:33.345998 DATLAT Default: 0xd
3600 23:18:33.346080 0, 0xFFFF, sum = 0
3601 23:18:33.349433 1, 0xFFFF, sum = 0
3602 23:18:33.349518 2, 0xFFFF, sum = 0
3603 23:18:33.352628 3, 0xFFFF, sum = 0
3604 23:18:33.352713 4, 0xFFFF, sum = 0
3605 23:18:33.355946 5, 0xFFFF, sum = 0
3606 23:18:33.356032 6, 0xFFFF, sum = 0
3607 23:18:33.359722 7, 0xFFFF, sum = 0
3608 23:18:33.359836 8, 0xFFFF, sum = 0
3609 23:18:33.362912 9, 0xFFFF, sum = 0
3610 23:18:33.363024 10, 0xFFFF, sum = 0
3611 23:18:33.365801 11, 0xFFFF, sum = 0
3612 23:18:33.369424 12, 0x0, sum = 1
3613 23:18:33.369520 13, 0x0, sum = 2
3614 23:18:33.369585 14, 0x0, sum = 3
3615 23:18:33.372727 15, 0x0, sum = 4
3616 23:18:33.372813 best_step = 13
3617 23:18:33.372876
3618 23:18:33.372936 ==
3619 23:18:33.376055 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 23:18:33.382452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 23:18:33.382552 ==
3622 23:18:33.382620 RX Vref Scan: 0
3623 23:18:33.382679
3624 23:18:33.385971 RX Vref 0 -> 0, step: 1
3625 23:18:33.386079
3626 23:18:33.389572 RX Delay -21 -> 252, step: 4
3627 23:18:33.392896 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3628 23:18:33.396318 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3629 23:18:33.403140 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3630 23:18:33.405783 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3631 23:18:33.409379 iDelay=191, Bit 4, Center 116 (51 ~ 182) 132
3632 23:18:33.412645 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3633 23:18:33.416693 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3634 23:18:33.422588 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3635 23:18:33.426176 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3636 23:18:33.429561 iDelay=191, Bit 9, Center 96 (31 ~ 162) 132
3637 23:18:33.433160 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3638 23:18:33.436073 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3639 23:18:33.442549 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3640 23:18:33.445897 iDelay=191, Bit 13, Center 116 (51 ~ 182) 132
3641 23:18:33.449029 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3642 23:18:33.452640 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3643 23:18:33.452731 ==
3644 23:18:33.456286 Dram Type= 6, Freq= 0, CH_1, rank 1
3645 23:18:33.459803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3646 23:18:33.462797 ==
3647 23:18:33.462923 DQS Delay:
3648 23:18:33.463014 DQS0 = 0, DQS1 = 0
3649 23:18:33.465732 DQM Delay:
3650 23:18:33.465831 DQM0 = 113, DQM1 = 108
3651 23:18:33.469242 DQ Delay:
3652 23:18:33.472534 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3653 23:18:33.475814 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =110
3654 23:18:33.479345 DQ8 =96, DQ9 =96, DQ10 =110, DQ11 =100
3655 23:18:33.482678 DQ12 =114, DQ13 =116, DQ14 =118, DQ15 =116
3656 23:18:33.482768
3657 23:18:33.482854
3658 23:18:33.489453 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6fd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 414 ps
3659 23:18:33.492617 CH1 RK1: MR19=303, MR18=F6FD
3660 23:18:33.499421 CH1_RK1: MR19=0x303, MR18=0xF6FD, DQSOSC=411, MR23=63, INC=38, DEC=25
3661 23:18:33.502573 [RxdqsGatingPostProcess] freq 1200
3662 23:18:33.509334 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3663 23:18:33.512645 best DQS0 dly(2T, 0.5T) = (0, 11)
3664 23:18:33.512741 best DQS1 dly(2T, 0.5T) = (0, 12)
3665 23:18:33.515785 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3666 23:18:33.519630 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3667 23:18:33.522439 best DQS0 dly(2T, 0.5T) = (0, 11)
3668 23:18:33.525940 best DQS1 dly(2T, 0.5T) = (0, 11)
3669 23:18:33.529366 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3670 23:18:33.532750 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3671 23:18:33.536246 Pre-setting of DQS Precalculation
3672 23:18:33.539588 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3673 23:18:33.549519 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3674 23:18:33.556217 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3675 23:18:33.556340
3676 23:18:33.556405
3677 23:18:33.559976 [Calibration Summary] 2400 Mbps
3678 23:18:33.560088 CH 0, Rank 0
3679 23:18:33.562967 SW Impedance : PASS
3680 23:18:33.563068 DUTY Scan : NO K
3681 23:18:33.566473 ZQ Calibration : PASS
3682 23:18:33.569539 Jitter Meter : NO K
3683 23:18:33.569624 CBT Training : PASS
3684 23:18:33.573075 Write leveling : PASS
3685 23:18:33.576558 RX DQS gating : PASS
3686 23:18:33.576647 RX DQ/DQS(RDDQC) : PASS
3687 23:18:33.579485 TX DQ/DQS : PASS
3688 23:18:33.582840 RX DATLAT : PASS
3689 23:18:33.582933 RX DQ/DQS(Engine): PASS
3690 23:18:33.586308 TX OE : NO K
3691 23:18:33.586468 All Pass.
3692 23:18:33.586562
3693 23:18:33.589833 CH 0, Rank 1
3694 23:18:33.589915 SW Impedance : PASS
3695 23:18:33.593097 DUTY Scan : NO K
3696 23:18:33.596656 ZQ Calibration : PASS
3697 23:18:33.596766 Jitter Meter : NO K
3698 23:18:33.599622 CBT Training : PASS
3699 23:18:33.599722 Write leveling : PASS
3700 23:18:33.602882 RX DQS gating : PASS
3701 23:18:33.606220 RX DQ/DQS(RDDQC) : PASS
3702 23:18:33.606331 TX DQ/DQS : PASS
3703 23:18:33.609811 RX DATLAT : PASS
3704 23:18:33.612910 RX DQ/DQS(Engine): PASS
3705 23:18:33.612995 TX OE : NO K
3706 23:18:33.616269 All Pass.
3707 23:18:33.616379
3708 23:18:33.616469 CH 1, Rank 0
3709 23:18:33.620201 SW Impedance : PASS
3710 23:18:33.620284 DUTY Scan : NO K
3711 23:18:33.622991 ZQ Calibration : PASS
3712 23:18:33.626331 Jitter Meter : NO K
3713 23:18:33.626421 CBT Training : PASS
3714 23:18:33.629775 Write leveling : PASS
3715 23:18:33.633295 RX DQS gating : PASS
3716 23:18:33.633380 RX DQ/DQS(RDDQC) : PASS
3717 23:18:33.636369 TX DQ/DQS : PASS
3718 23:18:33.636484 RX DATLAT : PASS
3719 23:18:33.639698 RX DQ/DQS(Engine): PASS
3720 23:18:33.643115 TX OE : NO K
3721 23:18:33.643203 All Pass.
3722 23:18:33.643266
3723 23:18:33.643324 CH 1, Rank 1
3724 23:18:33.646303 SW Impedance : PASS
3725 23:18:33.649891 DUTY Scan : NO K
3726 23:18:33.650001 ZQ Calibration : PASS
3727 23:18:33.653332 Jitter Meter : NO K
3728 23:18:33.656489 CBT Training : PASS
3729 23:18:33.656575 Write leveling : PASS
3730 23:18:33.659782 RX DQS gating : PASS
3731 23:18:33.663094 RX DQ/DQS(RDDQC) : PASS
3732 23:18:33.663205 TX DQ/DQS : PASS
3733 23:18:33.666548 RX DATLAT : PASS
3734 23:18:33.669965 RX DQ/DQS(Engine): PASS
3735 23:18:33.670051 TX OE : NO K
3736 23:18:33.670119 All Pass.
3737 23:18:33.673162
3738 23:18:33.673243 DramC Write-DBI off
3739 23:18:33.676646 PER_BANK_REFRESH: Hybrid Mode
3740 23:18:33.676736 TX_TRACKING: ON
3741 23:18:33.686512 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3742 23:18:33.689750 [FAST_K] Save calibration result to emmc
3743 23:18:33.693189 dramc_set_vcore_voltage set vcore to 650000
3744 23:18:33.696395 Read voltage for 600, 5
3745 23:18:33.696480 Vio18 = 0
3746 23:18:33.699792 Vcore = 650000
3747 23:18:33.699874 Vdram = 0
3748 23:18:33.699937 Vddq = 0
3749 23:18:33.699996 Vmddr = 0
3750 23:18:33.706965 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3751 23:18:33.709941 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3752 23:18:33.713505 MEM_TYPE=3, freq_sel=19
3753 23:18:33.717122 sv_algorithm_assistance_LP4_1600
3754 23:18:33.720113 ============ PULL DRAM RESETB DOWN ============
3755 23:18:33.726437 ========== PULL DRAM RESETB DOWN end =========
3756 23:18:33.730199 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3757 23:18:33.733047 ===================================
3758 23:18:33.736889 LPDDR4 DRAM CONFIGURATION
3759 23:18:33.739593 ===================================
3760 23:18:33.739704 EX_ROW_EN[0] = 0x0
3761 23:18:33.742884 EX_ROW_EN[1] = 0x0
3762 23:18:33.742984 LP4Y_EN = 0x0
3763 23:18:33.746841 WORK_FSP = 0x0
3764 23:18:33.746925 WL = 0x2
3765 23:18:33.749798 RL = 0x2
3766 23:18:33.749917 BL = 0x2
3767 23:18:33.752977 RPST = 0x0
3768 23:18:33.753058 RD_PRE = 0x0
3769 23:18:33.756487 WR_PRE = 0x1
3770 23:18:33.756570 WR_PST = 0x0
3771 23:18:33.759879 DBI_WR = 0x0
3772 23:18:33.762995 DBI_RD = 0x0
3773 23:18:33.763098 OTF = 0x1
3774 23:18:33.766433 ===================================
3775 23:18:33.769783 ===================================
3776 23:18:33.769871 ANA top config
3777 23:18:33.773076 ===================================
3778 23:18:33.776088 DLL_ASYNC_EN = 0
3779 23:18:33.779578 ALL_SLAVE_EN = 1
3780 23:18:33.782816 NEW_RANK_MODE = 1
3781 23:18:33.786179 DLL_IDLE_MODE = 1
3782 23:18:33.786284 LP45_APHY_COMB_EN = 1
3783 23:18:33.790065 TX_ODT_DIS = 1
3784 23:18:33.793183 NEW_8X_MODE = 1
3785 23:18:33.796632 ===================================
3786 23:18:33.800287 ===================================
3787 23:18:33.802839 data_rate = 1200
3788 23:18:33.806475 CKR = 1
3789 23:18:33.806566 DQ_P2S_RATIO = 8
3790 23:18:33.809736 ===================================
3791 23:18:33.812892 CA_P2S_RATIO = 8
3792 23:18:33.816302 DQ_CA_OPEN = 0
3793 23:18:33.819812 DQ_SEMI_OPEN = 0
3794 23:18:33.823111 CA_SEMI_OPEN = 0
3795 23:18:33.826372 CA_FULL_RATE = 0
3796 23:18:33.826497 DQ_CKDIV4_EN = 1
3797 23:18:33.829323 CA_CKDIV4_EN = 1
3798 23:18:33.832678 CA_PREDIV_EN = 0
3799 23:18:33.836205 PH8_DLY = 0
3800 23:18:33.839423 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3801 23:18:33.842764 DQ_AAMCK_DIV = 4
3802 23:18:33.842868 CA_AAMCK_DIV = 4
3803 23:18:33.846337 CA_ADMCK_DIV = 4
3804 23:18:33.849513 DQ_TRACK_CA_EN = 0
3805 23:18:33.852719 CA_PICK = 600
3806 23:18:33.856392 CA_MCKIO = 600
3807 23:18:33.859173 MCKIO_SEMI = 0
3808 23:18:33.859278 PLL_FREQ = 2288
3809 23:18:33.863007 DQ_UI_PI_RATIO = 32
3810 23:18:33.865941 CA_UI_PI_RATIO = 0
3811 23:18:33.869532 ===================================
3812 23:18:33.872901 ===================================
3813 23:18:33.875788 memory_type:LPDDR4
3814 23:18:33.879513 GP_NUM : 10
3815 23:18:33.879602 SRAM_EN : 1
3816 23:18:33.882914 MD32_EN : 0
3817 23:18:33.953675 ===================================
3818 23:18:33.954230 [ANA_INIT] >>>>>>>>>>>>>>
3819 23:18:33.954614 <<<<<< [CONFIGURE PHASE]: ANA_TX
3820 23:18:33.954968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3821 23:18:33.955361 ===================================
3822 23:18:33.955742 data_rate = 1200,PCW = 0X5800
3823 23:18:33.956103 ===================================
3824 23:18:33.956398 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3825 23:18:33.956765 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3826 23:18:33.957309 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3827 23:18:33.957687 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3828 23:18:33.957785 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3829 23:18:33.957840 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3830 23:18:33.957894 [ANA_INIT] flow start
3831 23:18:33.957962 [ANA_INIT] PLL >>>>>>>>
3832 23:18:33.958059 [ANA_INIT] PLL <<<<<<<<
3833 23:18:33.958142 [ANA_INIT] MIDPI >>>>>>>>
3834 23:18:33.958210 [ANA_INIT] MIDPI <<<<<<<<
3835 23:18:33.958280 [ANA_INIT] DLL >>>>>>>>
3836 23:18:33.958334 [ANA_INIT] flow end
3837 23:18:33.958388 ============ LP4 DIFF to SE enter ============
3838 23:18:33.958466 ============ LP4 DIFF to SE exit ============
3839 23:18:33.958740 [ANA_INIT] <<<<<<<<<<<<<
3840 23:18:33.959319 [Flow] Enable top DCM control >>>>>
3841 23:18:33.962613 [Flow] Enable top DCM control <<<<<
3842 23:18:33.966286 Enable DLL master slave shuffle
3843 23:18:33.969606 ==============================================================
3844 23:18:33.972670 Gating Mode config
3845 23:18:33.976253 ==============================================================
3846 23:18:33.979524 Config description:
3847 23:18:33.989152 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3848 23:18:33.995909 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3849 23:18:33.999174 SELPH_MODE 0: By rank 1: By Phase
3850 23:18:34.006114 ==============================================================
3851 23:18:34.009155 GAT_TRACK_EN = 1
3852 23:18:34.012538 RX_GATING_MODE = 2
3853 23:18:34.016101 RX_GATING_TRACK_MODE = 2
3854 23:18:34.019453 SELPH_MODE = 1
3855 23:18:34.019545 PICG_EARLY_EN = 1
3856 23:18:34.022887 VALID_LAT_VALUE = 1
3857 23:18:34.029834 ==============================================================
3858 23:18:34.032547 Enter into Gating configuration >>>>
3859 23:18:34.036042 Exit from Gating configuration <<<<
3860 23:18:34.039367 Enter into DVFS_PRE_config >>>>>
3861 23:18:34.049561 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3862 23:18:34.052882 Exit from DVFS_PRE_config <<<<<
3863 23:18:34.056398 Enter into PICG configuration >>>>
3864 23:18:34.059138 Exit from PICG configuration <<<<
3865 23:18:34.062693 [RX_INPUT] configuration >>>>>
3866 23:18:34.066199 [RX_INPUT] configuration <<<<<
3867 23:18:34.069729 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3868 23:18:34.076915 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3869 23:18:34.082697 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3870 23:18:34.090019 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3871 23:18:34.092855 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3872 23:18:34.099645 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3873 23:18:34.102987 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3874 23:18:34.109242 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3875 23:18:34.113043 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3876 23:18:34.116058 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3877 23:18:34.119219 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3878 23:18:34.126262 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3879 23:18:34.129429 ===================================
3880 23:18:34.132645 LPDDR4 DRAM CONFIGURATION
3881 23:18:34.135952 ===================================
3882 23:18:34.136047 EX_ROW_EN[0] = 0x0
3883 23:18:34.139675 EX_ROW_EN[1] = 0x0
3884 23:18:34.139788 LP4Y_EN = 0x0
3885 23:18:34.142666 WORK_FSP = 0x0
3886 23:18:34.142751 WL = 0x2
3887 23:18:34.145916 RL = 0x2
3888 23:18:34.146002 BL = 0x2
3889 23:18:34.149540 RPST = 0x0
3890 23:18:34.149625 RD_PRE = 0x0
3891 23:18:34.152735 WR_PRE = 0x1
3892 23:18:34.152819 WR_PST = 0x0
3893 23:18:34.156409 DBI_WR = 0x0
3894 23:18:34.156498 DBI_RD = 0x0
3895 23:18:34.159352 OTF = 0x1
3896 23:18:34.162576 ===================================
3897 23:18:34.166298 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3898 23:18:34.169305 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3899 23:18:34.176245 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3900 23:18:34.179394 ===================================
3901 23:18:34.179488 LPDDR4 DRAM CONFIGURATION
3902 23:18:34.182820 ===================================
3903 23:18:34.186342 EX_ROW_EN[0] = 0x10
3904 23:18:34.189649 EX_ROW_EN[1] = 0x0
3905 23:18:34.189743 LP4Y_EN = 0x0
3906 23:18:34.192907 WORK_FSP = 0x0
3907 23:18:34.192993 WL = 0x2
3908 23:18:34.195910 RL = 0x2
3909 23:18:34.195995 BL = 0x2
3910 23:18:34.199295 RPST = 0x0
3911 23:18:34.199379 RD_PRE = 0x0
3912 23:18:34.202651 WR_PRE = 0x1
3913 23:18:34.202735 WR_PST = 0x0
3914 23:18:34.206109 DBI_WR = 0x0
3915 23:18:34.206194 DBI_RD = 0x0
3916 23:18:34.209469 OTF = 0x1
3917 23:18:34.212654 ===================================
3918 23:18:34.219469 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3919 23:18:34.222656 nWR fixed to 30
3920 23:18:34.222761 [ModeRegInit_LP4] CH0 RK0
3921 23:18:34.225991 [ModeRegInit_LP4] CH0 RK1
3922 23:18:34.229480 [ModeRegInit_LP4] CH1 RK0
3923 23:18:34.229571 [ModeRegInit_LP4] CH1 RK1
3924 23:18:34.232660 match AC timing 17
3925 23:18:34.236458 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3926 23:18:34.239640 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3927 23:18:34.246452 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3928 23:18:34.249600 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3929 23:18:34.256535 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3930 23:18:34.256664 ==
3931 23:18:34.259423 Dram Type= 6, Freq= 0, CH_0, rank 0
3932 23:18:34.262903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3933 23:18:34.262993 ==
3934 23:18:34.269709 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3935 23:18:34.273087 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3936 23:18:34.277044 [CA 0] Center 36 (6~66) winsize 61
3937 23:18:34.280764 [CA 1] Center 36 (6~66) winsize 61
3938 23:18:34.283885 [CA 2] Center 34 (4~65) winsize 62
3939 23:18:34.287296 [CA 3] Center 34 (4~64) winsize 61
3940 23:18:34.290291 [CA 4] Center 34 (4~64) winsize 61
3941 23:18:34.294072 [CA 5] Center 33 (3~64) winsize 62
3942 23:18:34.294182
3943 23:18:34.296922 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3944 23:18:34.297008
3945 23:18:34.300480 [CATrainingPosCal] consider 1 rank data
3946 23:18:34.304051 u2DelayCellTimex100 = 270/100 ps
3947 23:18:34.307108 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3948 23:18:34.311152 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3949 23:18:34.317079 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3950 23:18:34.320518 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3951 23:18:34.323896 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3952 23:18:34.327413 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3953 23:18:34.327497
3954 23:18:34.330765 CA PerBit enable=1, Macro0, CA PI delay=33
3955 23:18:34.330869
3956 23:18:34.334064 [CBTSetCACLKResult] CA Dly = 33
3957 23:18:34.334157 CS Dly: 5 (0~36)
3958 23:18:34.334221 ==
3959 23:18:34.337221 Dram Type= 6, Freq= 0, CH_0, rank 1
3960 23:18:34.344060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 23:18:34.344168 ==
3962 23:18:34.347347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3963 23:18:34.353998 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3964 23:18:34.357167 [CA 0] Center 36 (6~66) winsize 61
3965 23:18:34.360673 [CA 1] Center 36 (6~66) winsize 61
3966 23:18:34.363825 [CA 2] Center 34 (4~65) winsize 62
3967 23:18:34.367462 [CA 3] Center 34 (4~65) winsize 62
3968 23:18:34.370780 [CA 4] Center 33 (3~64) winsize 62
3969 23:18:34.374010 [CA 5] Center 33 (3~64) winsize 62
3970 23:18:34.374101
3971 23:18:34.377263 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3972 23:18:34.377350
3973 23:18:34.380570 [CATrainingPosCal] consider 2 rank data
3974 23:18:34.383744 u2DelayCellTimex100 = 270/100 ps
3975 23:18:34.387077 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3976 23:18:34.390863 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3977 23:18:34.397670 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3978 23:18:34.400606 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3979 23:18:34.403978 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3980 23:18:34.407279 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3981 23:18:34.407376
3982 23:18:34.410575 CA PerBit enable=1, Macro0, CA PI delay=33
3983 23:18:34.410661
3984 23:18:34.413967 [CBTSetCACLKResult] CA Dly = 33
3985 23:18:34.414050 CS Dly: 5 (0~37)
3986 23:18:34.414114
3987 23:18:34.417146 ----->DramcWriteLeveling(PI) begin...
3988 23:18:34.420761 ==
3989 23:18:34.420852 Dram Type= 6, Freq= 0, CH_0, rank 0
3990 23:18:34.427406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3991 23:18:34.427508 ==
3992 23:18:34.430777 Write leveling (Byte 0): 32 => 32
3993 23:18:34.433708 Write leveling (Byte 1): 28 => 28
3994 23:18:34.437371 DramcWriteLeveling(PI) end<-----
3995 23:18:34.437466
3996 23:18:34.437530 ==
3997 23:18:34.440613 Dram Type= 6, Freq= 0, CH_0, rank 0
3998 23:18:34.444399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3999 23:18:34.444494 ==
4000 23:18:34.447002 [Gating] SW mode calibration
4001 23:18:34.454297 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4002 23:18:34.457027 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4003 23:18:34.463724 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4004 23:18:34.467242 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 23:18:34.470299 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4006 23:18:34.477239 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 23:18:34.480391 0 9 16 | B1->B0 | 3232 2828 | 0 0 | (0 0) (0 0)
4008 23:18:34.483983 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 23:18:34.490579 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 23:18:34.493715 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 23:18:34.496923 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 23:18:34.504270 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 23:18:34.506948 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 23:18:34.510758 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 23:18:34.517890 0 10 16 | B1->B0 | 3030 3a3a | 1 0 | (0 0) (0 0)
4016 23:18:34.520257 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4017 23:18:34.523738 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 23:18:34.530369 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 23:18:34.534080 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 23:18:34.537555 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 23:18:34.540413 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 23:18:34.547259 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 23:18:34.550874 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 23:18:34.553862 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4025 23:18:34.560690 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 23:18:34.563779 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 23:18:34.567549 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 23:18:34.573780 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 23:18:34.577483 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 23:18:34.580618 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 23:18:34.587414 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 23:18:34.590764 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 23:18:34.594054 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 23:18:34.600508 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 23:18:34.603652 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 23:18:34.607054 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 23:18:34.613871 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 23:18:34.616871 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 23:18:34.620303 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4040 23:18:34.626892 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 23:18:34.627021 Total UI for P1: 0, mck2ui 16
4042 23:18:34.633323 best dqsien dly found for B0: ( 0, 13, 16)
4043 23:18:34.633424 Total UI for P1: 0, mck2ui 16
4044 23:18:34.637255 best dqsien dly found for B1: ( 0, 13, 16)
4045 23:18:34.643755 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4046 23:18:34.646761 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4047 23:18:34.646856
4048 23:18:34.650164 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4049 23:18:34.653728 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4050 23:18:34.656939 [Gating] SW calibration Done
4051 23:18:34.657032 ==
4052 23:18:34.660198 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 23:18:34.663680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 23:18:34.663770 ==
4055 23:18:34.667455 RX Vref Scan: 0
4056 23:18:34.667545
4057 23:18:34.667609 RX Vref 0 -> 0, step: 1
4058 23:18:34.667669
4059 23:18:34.670164 RX Delay -230 -> 252, step: 16
4060 23:18:34.673444 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4061 23:18:34.680230 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4062 23:18:34.683678 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4063 23:18:34.687019 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4064 23:18:34.690213 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4065 23:18:34.696946 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4066 23:18:34.700145 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4067 23:18:34.703359 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4068 23:18:34.706922 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4069 23:18:34.710210 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4070 23:18:34.717242 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4071 23:18:34.720390 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4072 23:18:34.723406 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4073 23:18:34.726616 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4074 23:18:34.733852 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4075 23:18:34.736586 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4076 23:18:34.736702 ==
4077 23:18:34.740419 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 23:18:34.743355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 23:18:34.743446 ==
4080 23:18:34.746778 DQS Delay:
4081 23:18:34.746864 DQS0 = 0, DQS1 = 0
4082 23:18:34.746928 DQM Delay:
4083 23:18:34.749940 DQM0 = 42, DQM1 = 31
4084 23:18:34.750023 DQ Delay:
4085 23:18:34.753559 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4086 23:18:34.757190 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4087 23:18:34.760134 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4088 23:18:34.763313 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4089 23:18:34.763424
4090 23:18:34.763502
4091 23:18:34.763593 ==
4092 23:18:34.766865 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 23:18:34.773732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 23:18:34.773842 ==
4095 23:18:34.773905
4096 23:18:34.773965
4097 23:18:34.774022 TX Vref Scan disable
4098 23:18:34.776764 == TX Byte 0 ==
4099 23:18:34.780317 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4100 23:18:34.787177 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4101 23:18:34.787284 == TX Byte 1 ==
4102 23:18:34.790171 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4103 23:18:34.797003 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4104 23:18:34.797116 ==
4105 23:18:34.800439 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 23:18:34.803996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 23:18:34.804104 ==
4108 23:18:34.804170
4109 23:18:34.804230
4110 23:18:34.806726 TX Vref Scan disable
4111 23:18:34.810278 == TX Byte 0 ==
4112 23:18:34.813531 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4113 23:18:34.816944 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4114 23:18:34.817034 == TX Byte 1 ==
4115 23:18:34.823686 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4116 23:18:34.827141 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4117 23:18:34.827234
4118 23:18:34.827300 [DATLAT]
4119 23:18:34.830191 Freq=600, CH0 RK0
4120 23:18:34.830276
4121 23:18:34.830338 DATLAT Default: 0x9
4122 23:18:34.833584 0, 0xFFFF, sum = 0
4123 23:18:34.833669 1, 0xFFFF, sum = 0
4124 23:18:34.836736 2, 0xFFFF, sum = 0
4125 23:18:34.840063 3, 0xFFFF, sum = 0
4126 23:18:34.840159 4, 0xFFFF, sum = 0
4127 23:18:34.843969 5, 0xFFFF, sum = 0
4128 23:18:34.844060 6, 0xFFFF, sum = 0
4129 23:18:34.846882 7, 0xFFFF, sum = 0
4130 23:18:34.846997 8, 0x0, sum = 1
4131 23:18:34.847092 9, 0x0, sum = 2
4132 23:18:34.850602 10, 0x0, sum = 3
4133 23:18:34.850710 11, 0x0, sum = 4
4134 23:18:34.853426 best_step = 9
4135 23:18:34.853524
4136 23:18:34.853614 ==
4137 23:18:34.856882 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 23:18:34.860659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 23:18:34.860753 ==
4140 23:18:34.863642 RX Vref Scan: 1
4141 23:18:34.863717
4142 23:18:34.863778 RX Vref 0 -> 0, step: 1
4143 23:18:34.863854
4144 23:18:34.866853 RX Delay -195 -> 252, step: 8
4145 23:18:34.866940
4146 23:18:34.870120 Set Vref, RX VrefLevel [Byte0]: 58
4147 23:18:34.873447 [Byte1]: 51
4148 23:18:34.877493
4149 23:18:34.877584 Final RX Vref Byte 0 = 58 to rank0
4150 23:18:34.880772 Final RX Vref Byte 1 = 51 to rank0
4151 23:18:34.884067 Final RX Vref Byte 0 = 58 to rank1
4152 23:18:34.887656 Final RX Vref Byte 1 = 51 to rank1==
4153 23:18:34.891121 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 23:18:34.897240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 23:18:34.897362 ==
4156 23:18:34.897453 DQS Delay:
4157 23:18:34.897542 DQS0 = 0, DQS1 = 0
4158 23:18:34.901350 DQM Delay:
4159 23:18:34.901457 DQM0 = 41, DQM1 = 33
4160 23:18:34.904691 DQ Delay:
4161 23:18:34.907606 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4162 23:18:34.907716 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
4163 23:18:34.910817 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4164 23:18:34.914253 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4165 23:18:34.917664
4166 23:18:34.917770
4167 23:18:34.924041 [DQSOSCAuto] RK0, (LSB)MR18= 0x4222, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
4168 23:18:34.927482 CH0 RK0: MR19=808, MR18=4222
4169 23:18:34.933978 CH0_RK0: MR19=0x808, MR18=0x4222, DQSOSC=397, MR23=63, INC=166, DEC=110
4170 23:18:34.934110
4171 23:18:34.937568 ----->DramcWriteLeveling(PI) begin...
4172 23:18:34.937678 ==
4173 23:18:34.940581 Dram Type= 6, Freq= 0, CH_0, rank 1
4174 23:18:34.944093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 23:18:34.944220 ==
4176 23:18:34.947793 Write leveling (Byte 0): 31 => 31
4177 23:18:34.950596 Write leveling (Byte 1): 28 => 28
4178 23:18:34.954237 DramcWriteLeveling(PI) end<-----
4179 23:18:34.954347
4180 23:18:34.954469 ==
4181 23:18:34.957371 Dram Type= 6, Freq= 0, CH_0, rank 1
4182 23:18:34.960714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 23:18:34.960823 ==
4184 23:18:34.964153 [Gating] SW mode calibration
4185 23:18:34.970984 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4186 23:18:34.977676 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4187 23:18:34.981669 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4188 23:18:34.984309 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4189 23:18:34.991023 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4190 23:18:34.994340 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4191 23:18:34.997410 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
4192 23:18:35.004034 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 23:18:35.007247 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 23:18:35.010790 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 23:18:35.017522 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 23:18:35.020728 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 23:18:35.024364 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 23:18:35.031093 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
4199 23:18:35.033880 0 10 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
4200 23:18:35.037542 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 23:18:35.044840 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 23:18:35.047658 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 23:18:35.051039 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 23:18:35.053981 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 23:18:35.060643 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 23:18:35.064183 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4207 23:18:35.067460 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4208 23:18:35.073964 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 23:18:35.077323 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 23:18:35.080953 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 23:18:35.087518 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 23:18:35.091219 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 23:18:35.094305 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 23:18:35.100862 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 23:18:35.104230 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 23:18:35.108156 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 23:18:35.114301 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 23:18:35.117861 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 23:18:35.120906 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 23:18:35.127641 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 23:18:35.131033 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 23:18:35.134575 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4223 23:18:35.137734 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 23:18:35.140731 Total UI for P1: 0, mck2ui 16
4225 23:18:35.144742 best dqsien dly found for B0: ( 0, 13, 12)
4226 23:18:35.147856 Total UI for P1: 0, mck2ui 16
4227 23:18:35.150958 best dqsien dly found for B1: ( 0, 13, 14)
4228 23:18:35.154509 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4229 23:18:35.161179 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4230 23:18:35.161321
4231 23:18:35.164267 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4232 23:18:35.167601 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4233 23:18:35.170828 [Gating] SW calibration Done
4234 23:18:35.170918 ==
4235 23:18:35.174280 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 23:18:35.177727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 23:18:35.177835 ==
4238 23:18:35.177926 RX Vref Scan: 0
4239 23:18:35.180667
4240 23:18:35.180768 RX Vref 0 -> 0, step: 1
4241 23:18:35.180855
4242 23:18:35.184139 RX Delay -230 -> 252, step: 16
4243 23:18:35.187603 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4244 23:18:35.194659 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4245 23:18:35.197800 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4246 23:18:35.200680 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4247 23:18:35.204760 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4248 23:18:35.207753 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4249 23:18:35.214336 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4250 23:18:35.217840 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4251 23:18:35.221062 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4252 23:18:35.224434 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4253 23:18:35.227557 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4254 23:18:35.234298 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4255 23:18:35.237724 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4256 23:18:35.240841 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4257 23:18:35.244289 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4258 23:18:35.250994 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4259 23:18:35.251138 ==
4260 23:18:35.254657 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 23:18:35.257987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 23:18:35.258102 ==
4263 23:18:35.258194 DQS Delay:
4264 23:18:35.261131 DQS0 = 0, DQS1 = 0
4265 23:18:35.261233 DQM Delay:
4266 23:18:35.264560 DQM0 = 44, DQM1 = 33
4267 23:18:35.264664 DQ Delay:
4268 23:18:35.267969 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4269 23:18:35.271011 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4270 23:18:35.274289 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4271 23:18:35.277920 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4272 23:18:35.278025
4273 23:18:35.278111
4274 23:18:35.278173 ==
4275 23:18:35.281183 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 23:18:35.284637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 23:18:35.284744 ==
4278 23:18:35.284812
4279 23:18:35.287599
4280 23:18:35.287669 TX Vref Scan disable
4281 23:18:35.290897 == TX Byte 0 ==
4282 23:18:35.294426 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4283 23:18:35.297785 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4284 23:18:35.301298 == TX Byte 1 ==
4285 23:18:35.304811 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4286 23:18:35.307636 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4287 23:18:35.307721 ==
4288 23:18:35.311130 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 23:18:35.318148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 23:18:35.318273 ==
4291 23:18:35.318367
4292 23:18:35.318479
4293 23:18:35.318542 TX Vref Scan disable
4294 23:18:35.322107 == TX Byte 0 ==
4295 23:18:35.325514 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4296 23:18:35.333030 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4297 23:18:35.333201 == TX Byte 1 ==
4298 23:18:35.335405 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4299 23:18:35.342025 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4300 23:18:35.342164
4301 23:18:35.342257 [DATLAT]
4302 23:18:35.342359 Freq=600, CH0 RK1
4303 23:18:35.342490
4304 23:18:35.345314 DATLAT Default: 0x9
4305 23:18:35.345411 0, 0xFFFF, sum = 0
4306 23:18:35.348852 1, 0xFFFF, sum = 0
4307 23:18:35.348958 2, 0xFFFF, sum = 0
4308 23:18:35.352421 3, 0xFFFF, sum = 0
4309 23:18:35.355533 4, 0xFFFF, sum = 0
4310 23:18:35.355649 5, 0xFFFF, sum = 0
4311 23:18:35.358723 6, 0xFFFF, sum = 0
4312 23:18:35.358828 7, 0xFFFF, sum = 0
4313 23:18:35.361728 8, 0x0, sum = 1
4314 23:18:35.361832 9, 0x0, sum = 2
4315 23:18:35.361925 10, 0x0, sum = 3
4316 23:18:35.364884 11, 0x0, sum = 4
4317 23:18:35.364987 best_step = 9
4318 23:18:35.365087
4319 23:18:35.368865 ==
4320 23:18:35.368971 Dram Type= 6, Freq= 0, CH_0, rank 1
4321 23:18:35.375289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 23:18:35.375412 ==
4323 23:18:35.375514 RX Vref Scan: 0
4324 23:18:35.375601
4325 23:18:35.378536 RX Vref 0 -> 0, step: 1
4326 23:18:35.378615
4327 23:18:35.381965 RX Delay -179 -> 252, step: 8
4328 23:18:35.385453 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4329 23:18:35.391835 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4330 23:18:35.395353 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4331 23:18:35.398293 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4332 23:18:35.401838 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4333 23:18:35.408645 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4334 23:18:35.411704 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4335 23:18:35.415566 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4336 23:18:35.418726 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4337 23:18:35.421906 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4338 23:18:35.428785 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4339 23:18:35.432269 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4340 23:18:35.434929 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4341 23:18:35.438675 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4342 23:18:35.445765 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4343 23:18:35.448223 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4344 23:18:35.448333 ==
4345 23:18:35.451841 Dram Type= 6, Freq= 0, CH_0, rank 1
4346 23:18:35.454999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 23:18:35.455092 ==
4348 23:18:35.458575 DQS Delay:
4349 23:18:35.458680 DQS0 = 0, DQS1 = 0
4350 23:18:35.458774 DQM Delay:
4351 23:18:35.461193 DQM0 = 41, DQM1 = 32
4352 23:18:35.461278 DQ Delay:
4353 23:18:35.464604 DQ0 =40, DQ1 =40, DQ2 =40, DQ3 =40
4354 23:18:35.468353 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
4355 23:18:35.471856 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =20
4356 23:18:35.474703 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
4357 23:18:35.474818
4358 23:18:35.474911
4359 23:18:35.484397 [DQSOSCAuto] RK1, (LSB)MR18= 0x482a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4360 23:18:35.488092 CH0 RK1: MR19=808, MR18=482A
4361 23:18:35.491556 CH0_RK1: MR19=0x808, MR18=0x482A, DQSOSC=396, MR23=63, INC=167, DEC=111
4362 23:18:35.494707 [RxdqsGatingPostProcess] freq 600
4363 23:18:35.501500 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4364 23:18:35.504690 Pre-setting of DQS Precalculation
4365 23:18:35.507734 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4366 23:18:35.507822 ==
4367 23:18:35.511063 Dram Type= 6, Freq= 0, CH_1, rank 0
4368 23:18:35.517838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 23:18:35.517965 ==
4370 23:18:35.521165 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4371 23:18:35.527919 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4372 23:18:35.531442 [CA 0] Center 35 (5~65) winsize 61
4373 23:18:35.534562 [CA 1] Center 35 (5~66) winsize 62
4374 23:18:35.537781 [CA 2] Center 34 (3~65) winsize 63
4375 23:18:35.541641 [CA 3] Center 33 (3~64) winsize 62
4376 23:18:35.544596 [CA 4] Center 34 (3~65) winsize 63
4377 23:18:35.548140 [CA 5] Center 33 (3~64) winsize 62
4378 23:18:35.548254
4379 23:18:35.551256 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4380 23:18:35.551355
4381 23:18:35.554522 [CATrainingPosCal] consider 1 rank data
4382 23:18:35.557994 u2DelayCellTimex100 = 270/100 ps
4383 23:18:35.561495 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4384 23:18:35.564941 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4385 23:18:35.571505 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4386 23:18:35.574809 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4387 23:18:35.577900 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4388 23:18:35.581099 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4389 23:18:35.581191
4390 23:18:35.584563 CA PerBit enable=1, Macro0, CA PI delay=33
4391 23:18:35.584650
4392 23:18:35.587986 [CBTSetCACLKResult] CA Dly = 33
4393 23:18:35.588072 CS Dly: 3 (0~34)
4394 23:18:35.591731 ==
4395 23:18:35.591819 Dram Type= 6, Freq= 0, CH_1, rank 1
4396 23:18:35.598634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 23:18:35.598738 ==
4398 23:18:35.601124 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4399 23:18:35.607872 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4400 23:18:35.611709 [CA 0] Center 35 (5~66) winsize 62
4401 23:18:35.614595 [CA 1] Center 36 (6~66) winsize 61
4402 23:18:35.618130 [CA 2] Center 34 (4~65) winsize 62
4403 23:18:35.621590 [CA 3] Center 34 (3~65) winsize 63
4404 23:18:35.625026 [CA 4] Center 34 (3~65) winsize 63
4405 23:18:35.628073 [CA 5] Center 33 (3~64) winsize 62
4406 23:18:35.628162
4407 23:18:35.631505 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4408 23:18:35.631616
4409 23:18:35.634787 [CATrainingPosCal] consider 2 rank data
4410 23:18:35.638171 u2DelayCellTimex100 = 270/100 ps
4411 23:18:35.641596 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4412 23:18:35.645144 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4413 23:18:35.648002 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4414 23:18:35.655015 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4415 23:18:35.658457 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4416 23:18:35.661360 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 23:18:35.661450
4418 23:18:35.664918 CA PerBit enable=1, Macro0, CA PI delay=33
4419 23:18:35.665005
4420 23:18:35.668251 [CBTSetCACLKResult] CA Dly = 33
4421 23:18:35.668345 CS Dly: 3 (0~35)
4422 23:18:35.668465
4423 23:18:35.671626 ----->DramcWriteLeveling(PI) begin...
4424 23:18:35.671714 ==
4425 23:18:35.674774 Dram Type= 6, Freq= 0, CH_1, rank 0
4426 23:18:35.682062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4427 23:18:35.682171 ==
4428 23:18:35.684799 Write leveling (Byte 0): 29 => 29
4429 23:18:35.688390 Write leveling (Byte 1): 32 => 32
4430 23:18:35.688484 DramcWriteLeveling(PI) end<-----
4431 23:18:35.688546
4432 23:18:35.691627 ==
4433 23:18:35.695027 Dram Type= 6, Freq= 0, CH_1, rank 0
4434 23:18:35.698324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4435 23:18:35.698481 ==
4436 23:18:35.701439 [Gating] SW mode calibration
4437 23:18:35.708400 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4438 23:18:35.711458 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4439 23:18:35.718314 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4440 23:18:35.721860 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4441 23:18:35.725174 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4442 23:18:35.731863 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4443 23:18:35.734742 0 9 16 | B1->B0 | 2e2e 2a2a | 0 0 | (0 0) (0 0)
4444 23:18:35.738529 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 23:18:35.744866 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4446 23:18:35.748444 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 23:18:35.751525 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 23:18:35.754931 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 23:18:35.761971 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 23:18:35.765073 0 10 12 | B1->B0 | 2525 2626 | 0 0 | (1 1) (0 0)
4451 23:18:35.768568 0 10 16 | B1->B0 | 4141 4444 | 0 0 | (0 0) (0 0)
4452 23:18:35.774989 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 23:18:35.778060 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 23:18:35.781622 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 23:18:35.788562 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 23:18:35.791916 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 23:18:35.794955 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 23:18:35.801595 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 23:18:35.804832 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 23:18:35.808447 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 23:18:35.815038 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 23:18:35.818212 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 23:18:35.821938 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 23:18:35.828644 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 23:18:35.831550 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 23:18:35.835554 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 23:18:35.841668 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 23:18:35.845251 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 23:18:35.848147 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 23:18:35.851814 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 23:18:35.858679 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 23:18:35.861492 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 23:18:35.864851 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 23:18:35.871898 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4475 23:18:35.874926 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 23:18:35.878537 Total UI for P1: 0, mck2ui 16
4477 23:18:35.881659 best dqsien dly found for B0: ( 0, 13, 12)
4478 23:18:35.884834 Total UI for P1: 0, mck2ui 16
4479 23:18:35.888166 best dqsien dly found for B1: ( 0, 13, 14)
4480 23:18:35.891633 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4481 23:18:35.895208 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4482 23:18:35.895304
4483 23:18:35.898258 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4484 23:18:35.902052 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4485 23:18:35.905264 [Gating] SW calibration Done
4486 23:18:35.905346 ==
4487 23:18:35.908905 Dram Type= 6, Freq= 0, CH_1, rank 0
4488 23:18:35.911815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4489 23:18:35.915174 ==
4490 23:18:35.915262 RX Vref Scan: 0
4491 23:18:35.915370
4492 23:18:35.918597 RX Vref 0 -> 0, step: 1
4493 23:18:35.918695
4494 23:18:35.921556 RX Delay -230 -> 252, step: 16
4495 23:18:35.925279 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4496 23:18:35.928352 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4497 23:18:35.932032 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4498 23:18:35.938325 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4499 23:18:35.941799 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4500 23:18:35.945326 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4501 23:18:35.948686 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4502 23:18:35.951753 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4503 23:18:35.958577 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4504 23:18:35.961752 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4505 23:18:35.964989 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4506 23:18:35.968571 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4507 23:18:35.975136 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4508 23:18:35.978727 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4509 23:18:35.982049 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4510 23:18:35.985330 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4511 23:18:35.985423 ==
4512 23:18:35.988845 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 23:18:35.995204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 23:18:35.995305 ==
4515 23:18:35.995392 DQS Delay:
4516 23:18:35.995453 DQS0 = 0, DQS1 = 0
4517 23:18:35.998326 DQM Delay:
4518 23:18:35.998463 DQM0 = 42, DQM1 = 36
4519 23:18:36.001577 DQ Delay:
4520 23:18:36.004908 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4521 23:18:36.008871 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41
4522 23:18:36.008961 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4523 23:18:36.015608 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4524 23:18:36.015708
4525 23:18:36.015772
4526 23:18:36.015831 ==
4527 23:18:36.018613 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 23:18:36.021661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 23:18:36.021746 ==
4530 23:18:36.021810
4531 23:18:36.021868
4532 23:18:36.024994 TX Vref Scan disable
4533 23:18:36.025078 == TX Byte 0 ==
4534 23:18:36.031870 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4535 23:18:36.035390 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4536 23:18:36.035498 == TX Byte 1 ==
4537 23:18:36.041572 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4538 23:18:36.045239 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4539 23:18:36.045334 ==
4540 23:18:36.048372 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 23:18:36.051941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 23:18:36.052031 ==
4543 23:18:36.052095
4544 23:18:36.052169
4545 23:18:36.055384 TX Vref Scan disable
4546 23:18:36.058585 == TX Byte 0 ==
4547 23:18:36.062311 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4548 23:18:36.065272 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4549 23:18:36.068450 == TX Byte 1 ==
4550 23:18:36.071581 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4551 23:18:36.075417 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4552 23:18:36.075514
4553 23:18:36.078490 [DATLAT]
4554 23:18:36.078572 Freq=600, CH1 RK0
4555 23:18:36.078646
4556 23:18:36.081532 DATLAT Default: 0x9
4557 23:18:36.081604 0, 0xFFFF, sum = 0
4558 23:18:36.084956 1, 0xFFFF, sum = 0
4559 23:18:36.085061 2, 0xFFFF, sum = 0
4560 23:18:36.088325 3, 0xFFFF, sum = 0
4561 23:18:36.088403 4, 0xFFFF, sum = 0
4562 23:18:36.092056 5, 0xFFFF, sum = 0
4563 23:18:36.092143 6, 0xFFFF, sum = 0
4564 23:18:36.095532 7, 0xFFFF, sum = 0
4565 23:18:36.095618 8, 0x0, sum = 1
4566 23:18:36.098540 9, 0x0, sum = 2
4567 23:18:36.098625 10, 0x0, sum = 3
4568 23:18:36.101881 11, 0x0, sum = 4
4569 23:18:36.101967 best_step = 9
4570 23:18:36.102030
4571 23:18:36.102088 ==
4572 23:18:36.104784 Dram Type= 6, Freq= 0, CH_1, rank 0
4573 23:18:36.111461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4574 23:18:36.111560 ==
4575 23:18:36.111624 RX Vref Scan: 1
4576 23:18:36.111683
4577 23:18:36.114854 RX Vref 0 -> 0, step: 1
4578 23:18:36.114938
4579 23:18:36.118246 RX Delay -179 -> 252, step: 8
4580 23:18:36.118356
4581 23:18:36.121797 Set Vref, RX VrefLevel [Byte0]: 57
4582 23:18:36.124862 [Byte1]: 46
4583 23:18:36.124947
4584 23:18:36.128589 Final RX Vref Byte 0 = 57 to rank0
4585 23:18:36.131416 Final RX Vref Byte 1 = 46 to rank0
4586 23:18:36.135200 Final RX Vref Byte 0 = 57 to rank1
4587 23:18:36.138211 Final RX Vref Byte 1 = 46 to rank1==
4588 23:18:36.141587 Dram Type= 6, Freq= 0, CH_1, rank 0
4589 23:18:36.145154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 23:18:36.145279 ==
4591 23:18:36.148413 DQS Delay:
4592 23:18:36.148527 DQS0 = 0, DQS1 = 0
4593 23:18:36.148619 DQM Delay:
4594 23:18:36.151933 DQM0 = 41, DQM1 = 33
4595 23:18:36.152037 DQ Delay:
4596 23:18:36.155239 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4597 23:18:36.158186 DQ4 =44, DQ5 =48, DQ6 =52, DQ7 =36
4598 23:18:36.161474 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4599 23:18:36.165214 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4600 23:18:36.165332
4601 23:18:36.165419
4602 23:18:36.174739 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f04, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 397 ps
4603 23:18:36.174873 CH1 RK0: MR19=808, MR18=3F04
4604 23:18:36.181885 CH1_RK0: MR19=0x808, MR18=0x3F04, DQSOSC=397, MR23=63, INC=166, DEC=110
4605 23:18:36.182012
4606 23:18:36.184909 ----->DramcWriteLeveling(PI) begin...
4607 23:18:36.185021 ==
4608 23:18:36.188073 Dram Type= 6, Freq= 0, CH_1, rank 1
4609 23:18:36.195330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 23:18:36.195471 ==
4611 23:18:36.198631 Write leveling (Byte 0): 28 => 28
4612 23:18:36.201608 Write leveling (Byte 1): 29 => 29
4613 23:18:36.201727 DramcWriteLeveling(PI) end<-----
4614 23:18:36.205101
4615 23:18:36.205187 ==
4616 23:18:36.208124 Dram Type= 6, Freq= 0, CH_1, rank 1
4617 23:18:36.211672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 23:18:36.211805 ==
4619 23:18:36.215098 [Gating] SW mode calibration
4620 23:18:36.221784 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4621 23:18:36.225002 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4622 23:18:36.231919 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4623 23:18:36.234847 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4624 23:18:36.238187 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4625 23:18:36.244863 0 9 12 | B1->B0 | 3030 2d2d | 0 1 | (0 0) (1 0)
4626 23:18:36.248538 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4627 23:18:36.251850 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 23:18:36.258304 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 23:18:36.262035 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 23:18:36.265026 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 23:18:36.272147 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 23:18:36.275411 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4633 23:18:36.278284 0 10 12 | B1->B0 | 3131 3b3b | 0 1 | (0 0) (0 0)
4634 23:18:36.281933 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4635 23:18:36.288317 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 23:18:36.291525 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 23:18:36.295203 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 23:18:36.302290 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 23:18:36.305205 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 23:18:36.308279 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 23:18:36.314935 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4642 23:18:36.318092 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 23:18:36.321417 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 23:18:36.328002 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 23:18:36.331581 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 23:18:36.335396 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 23:18:36.342017 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 23:18:36.345323 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 23:18:36.348344 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 23:18:36.354709 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 23:18:36.358237 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 23:18:36.361460 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 23:18:36.368398 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 23:18:36.371495 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 23:18:36.374939 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 23:18:36.381360 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 23:18:36.384874 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4658 23:18:36.388501 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 23:18:36.391736 Total UI for P1: 0, mck2ui 16
4660 23:18:36.394765 best dqsien dly found for B0: ( 0, 13, 12)
4661 23:18:36.398022 Total UI for P1: 0, mck2ui 16
4662 23:18:36.401425 best dqsien dly found for B1: ( 0, 13, 14)
4663 23:18:36.405548 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4664 23:18:36.408212 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4665 23:18:36.408306
4666 23:18:36.411508 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4667 23:18:36.414972 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4668 23:18:36.418306 [Gating] SW calibration Done
4669 23:18:36.418462 ==
4670 23:18:36.421536 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 23:18:36.428212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 23:18:36.428322 ==
4673 23:18:36.428409 RX Vref Scan: 0
4674 23:18:36.428489
4675 23:18:36.431668 RX Vref 0 -> 0, step: 1
4676 23:18:36.431753
4677 23:18:36.435088 RX Delay -230 -> 252, step: 16
4678 23:18:36.438067 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4679 23:18:36.441970 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4680 23:18:36.445111 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4681 23:18:36.451598 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4682 23:18:36.455345 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4683 23:18:36.458097 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4684 23:18:36.461523 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4685 23:18:36.465140 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4686 23:18:36.471503 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4687 23:18:36.474886 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4688 23:18:36.478596 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4689 23:18:36.481638 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4690 23:18:36.488162 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4691 23:18:36.491839 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4692 23:18:36.495211 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4693 23:18:36.498886 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4694 23:18:36.498974 ==
4695 23:18:36.501732 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 23:18:36.508188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 23:18:36.508284 ==
4698 23:18:36.508368 DQS Delay:
4699 23:18:36.511639 DQS0 = 0, DQS1 = 0
4700 23:18:36.511722 DQM Delay:
4701 23:18:36.511805 DQM0 = 42, DQM1 = 36
4702 23:18:36.514842 DQ Delay:
4703 23:18:36.518482 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4704 23:18:36.521794 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4705 23:18:36.524923 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4706 23:18:36.528202 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4707 23:18:36.528286
4708 23:18:36.528377
4709 23:18:36.528459 ==
4710 23:18:36.531658 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 23:18:36.535253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 23:18:36.535338 ==
4713 23:18:36.535421
4714 23:18:36.535501
4715 23:18:36.538440 TX Vref Scan disable
4716 23:18:36.538524 == TX Byte 0 ==
4717 23:18:36.544944 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4718 23:18:36.548054 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4719 23:18:36.548138 == TX Byte 1 ==
4720 23:18:36.554721 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4721 23:18:36.558328 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4722 23:18:36.558437 ==
4723 23:18:36.561604 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 23:18:36.564956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 23:18:36.565068 ==
4726 23:18:36.565169
4727 23:18:36.568285
4728 23:18:36.568392 TX Vref Scan disable
4729 23:18:36.571746 == TX Byte 0 ==
4730 23:18:36.575012 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4731 23:18:36.578314 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4732 23:18:36.581503 == TX Byte 1 ==
4733 23:18:36.585053 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4734 23:18:36.588510 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4735 23:18:36.591973
4736 23:18:36.592053 [DATLAT]
4737 23:18:36.592115 Freq=600, CH1 RK1
4738 23:18:36.592174
4739 23:18:36.595176 DATLAT Default: 0x9
4740 23:18:36.595257 0, 0xFFFF, sum = 0
4741 23:18:36.598213 1, 0xFFFF, sum = 0
4742 23:18:36.598289 2, 0xFFFF, sum = 0
4743 23:18:36.601518 3, 0xFFFF, sum = 0
4744 23:18:36.601592 4, 0xFFFF, sum = 0
4745 23:18:36.605144 5, 0xFFFF, sum = 0
4746 23:18:36.608540 6, 0xFFFF, sum = 0
4747 23:18:36.608622 7, 0xFFFF, sum = 0
4748 23:18:36.608686 8, 0x0, sum = 1
4749 23:18:36.613462 9, 0x0, sum = 2
4750 23:18:36.613545 10, 0x0, sum = 3
4751 23:18:36.615440 11, 0x0, sum = 4
4752 23:18:36.615523 best_step = 9
4753 23:18:36.615586
4754 23:18:36.615644 ==
4755 23:18:36.618335 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 23:18:36.624954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 23:18:36.625065 ==
4758 23:18:36.625161 RX Vref Scan: 0
4759 23:18:36.625252
4760 23:18:36.628248 RX Vref 0 -> 0, step: 1
4761 23:18:36.628350
4762 23:18:36.631640 RX Delay -179 -> 252, step: 8
4763 23:18:36.634946 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4764 23:18:36.641859 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4765 23:18:36.645201 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4766 23:18:36.648433 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4767 23:18:36.652102 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4768 23:18:36.655028 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4769 23:18:36.662068 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4770 23:18:36.664928 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4771 23:18:36.668437 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4772 23:18:36.671805 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4773 23:18:36.675106 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4774 23:18:36.681821 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4775 23:18:36.684888 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4776 23:18:36.688471 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4777 23:18:36.692177 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4778 23:18:36.698206 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4779 23:18:36.698321 ==
4780 23:18:36.701879 Dram Type= 6, Freq= 0, CH_1, rank 1
4781 23:18:36.704887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4782 23:18:36.704970 ==
4783 23:18:36.705033 DQS Delay:
4784 23:18:36.709022 DQS0 = 0, DQS1 = 0
4785 23:18:36.709103 DQM Delay:
4786 23:18:36.712073 DQM0 = 38, DQM1 = 34
4787 23:18:36.712155 DQ Delay:
4788 23:18:36.714971 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4789 23:18:36.718783 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4790 23:18:36.722284 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4791 23:18:36.724896 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4792 23:18:36.724982
4793 23:18:36.725047
4794 23:18:36.732185 [DQSOSCAuto] RK1, (LSB)MR18= 0x3240, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4795 23:18:36.735074 CH1 RK1: MR19=808, MR18=3240
4796 23:18:36.741884 CH1_RK1: MR19=0x808, MR18=0x3240, DQSOSC=397, MR23=63, INC=166, DEC=110
4797 23:18:36.745286 [RxdqsGatingPostProcess] freq 600
4798 23:18:36.752386 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4799 23:18:36.755171 Pre-setting of DQS Precalculation
4800 23:18:36.758633 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4801 23:18:36.765191 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4802 23:18:36.772104 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4803 23:18:36.772227
4804 23:18:36.772324
4805 23:18:36.775350 [Calibration Summary] 1200 Mbps
4806 23:18:36.778628 CH 0, Rank 0
4807 23:18:36.778733 SW Impedance : PASS
4808 23:18:36.782127 DUTY Scan : NO K
4809 23:18:36.785123 ZQ Calibration : PASS
4810 23:18:36.785237 Jitter Meter : NO K
4811 23:18:36.788471 CBT Training : PASS
4812 23:18:36.791752 Write leveling : PASS
4813 23:18:36.791858 RX DQS gating : PASS
4814 23:18:36.795141 RX DQ/DQS(RDDQC) : PASS
4815 23:18:36.795248 TX DQ/DQS : PASS
4816 23:18:36.798630 RX DATLAT : PASS
4817 23:18:36.801987 RX DQ/DQS(Engine): PASS
4818 23:18:36.802094 TX OE : NO K
4819 23:18:36.805191 All Pass.
4820 23:18:36.805296
4821 23:18:36.805385 CH 0, Rank 1
4822 23:18:36.808414 SW Impedance : PASS
4823 23:18:36.808516 DUTY Scan : NO K
4824 23:18:36.811782 ZQ Calibration : PASS
4825 23:18:36.815358 Jitter Meter : NO K
4826 23:18:36.815463 CBT Training : PASS
4827 23:18:36.818668 Write leveling : PASS
4828 23:18:36.821610 RX DQS gating : PASS
4829 23:18:36.821717 RX DQ/DQS(RDDQC) : PASS
4830 23:18:36.825336 TX DQ/DQS : PASS
4831 23:18:36.828660 RX DATLAT : PASS
4832 23:18:36.828765 RX DQ/DQS(Engine): PASS
4833 23:18:36.831921 TX OE : NO K
4834 23:18:36.832025 All Pass.
4835 23:18:36.832113
4836 23:18:36.835060 CH 1, Rank 0
4837 23:18:36.835166 SW Impedance : PASS
4838 23:18:36.838566 DUTY Scan : NO K
4839 23:18:36.838667 ZQ Calibration : PASS
4840 23:18:36.841766 Jitter Meter : NO K
4841 23:18:36.845307 CBT Training : PASS
4842 23:18:36.845412 Write leveling : PASS
4843 23:18:36.848338 RX DQS gating : PASS
4844 23:18:36.851864 RX DQ/DQS(RDDQC) : PASS
4845 23:18:36.851992 TX DQ/DQS : PASS
4846 23:18:36.854970 RX DATLAT : PASS
4847 23:18:36.858263 RX DQ/DQS(Engine): PASS
4848 23:18:36.858366 TX OE : NO K
4849 23:18:36.861487 All Pass.
4850 23:18:36.861592
4851 23:18:36.861682 CH 1, Rank 1
4852 23:18:36.865608 SW Impedance : PASS
4853 23:18:36.865713 DUTY Scan : NO K
4854 23:18:36.869193 ZQ Calibration : PASS
4855 23:18:36.871664 Jitter Meter : NO K
4856 23:18:36.871767 CBT Training : PASS
4857 23:18:36.875613 Write leveling : PASS
4858 23:18:36.875697 RX DQS gating : PASS
4859 23:18:36.878633 RX DQ/DQS(RDDQC) : PASS
4860 23:18:36.881737 TX DQ/DQS : PASS
4861 23:18:36.881826 RX DATLAT : PASS
4862 23:18:36.885398 RX DQ/DQS(Engine): PASS
4863 23:18:36.889061 TX OE : NO K
4864 23:18:36.889143 All Pass.
4865 23:18:36.889205
4866 23:18:36.891653 DramC Write-DBI off
4867 23:18:36.891734 PER_BANK_REFRESH: Hybrid Mode
4868 23:18:36.895044 TX_TRACKING: ON
4869 23:18:36.901738 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4870 23:18:36.908266 [FAST_K] Save calibration result to emmc
4871 23:18:36.911822 dramc_set_vcore_voltage set vcore to 662500
4872 23:18:36.911921 Read voltage for 933, 3
4873 23:18:36.914995 Vio18 = 0
4874 23:18:36.915076 Vcore = 662500
4875 23:18:36.915139 Vdram = 0
4876 23:18:36.918360 Vddq = 0
4877 23:18:36.918465 Vmddr = 0
4878 23:18:36.921931 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4879 23:18:36.928770 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4880 23:18:36.932197 MEM_TYPE=3, freq_sel=17
4881 23:18:36.935672 sv_algorithm_assistance_LP4_1600
4882 23:18:36.939084 ============ PULL DRAM RESETB DOWN ============
4883 23:18:36.941911 ========== PULL DRAM RESETB DOWN end =========
4884 23:18:36.945562 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4885 23:18:36.948684 ===================================
4886 23:18:36.952032 LPDDR4 DRAM CONFIGURATION
4887 23:18:36.955750 ===================================
4888 23:18:36.958532 EX_ROW_EN[0] = 0x0
4889 23:18:36.958615 EX_ROW_EN[1] = 0x0
4890 23:18:36.961924 LP4Y_EN = 0x0
4891 23:18:36.962006 WORK_FSP = 0x0
4892 23:18:36.965104 WL = 0x3
4893 23:18:36.965185 RL = 0x3
4894 23:18:36.968896 BL = 0x2
4895 23:18:36.968977 RPST = 0x0
4896 23:18:36.972220 RD_PRE = 0x0
4897 23:18:36.972300 WR_PRE = 0x1
4898 23:18:36.975589 WR_PST = 0x0
4899 23:18:36.975671 DBI_WR = 0x0
4900 23:18:36.978839 DBI_RD = 0x0
4901 23:18:36.978935 OTF = 0x1
4902 23:18:36.982222 ===================================
4903 23:18:36.985414 ===================================
4904 23:18:36.988698 ANA top config
4905 23:18:36.992409 ===================================
4906 23:18:36.995282 DLL_ASYNC_EN = 0
4907 23:18:36.995364 ALL_SLAVE_EN = 1
4908 23:18:36.998777 NEW_RANK_MODE = 1
4909 23:18:37.002218 DLL_IDLE_MODE = 1
4910 23:18:37.005520 LP45_APHY_COMB_EN = 1
4911 23:18:37.005602 TX_ODT_DIS = 1
4912 23:18:37.008831 NEW_8X_MODE = 1
4913 23:18:37.012433 ===================================
4914 23:18:37.015951 ===================================
4915 23:18:37.018694 data_rate = 1866
4916 23:18:37.022094 CKR = 1
4917 23:18:37.025825 DQ_P2S_RATIO = 8
4918 23:18:37.028998 ===================================
4919 23:18:37.032204 CA_P2S_RATIO = 8
4920 23:18:37.032286 DQ_CA_OPEN = 0
4921 23:18:37.035358 DQ_SEMI_OPEN = 0
4922 23:18:37.038682 CA_SEMI_OPEN = 0
4923 23:18:37.042384 CA_FULL_RATE = 0
4924 23:18:37.045522 DQ_CKDIV4_EN = 1
4925 23:18:37.049074 CA_CKDIV4_EN = 1
4926 23:18:37.049157 CA_PREDIV_EN = 0
4927 23:18:37.051976 PH8_DLY = 0
4928 23:18:37.055597 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4929 23:18:37.058953 DQ_AAMCK_DIV = 4
4930 23:18:37.062451 CA_AAMCK_DIV = 4
4931 23:18:37.062534 CA_ADMCK_DIV = 4
4932 23:18:37.065403 DQ_TRACK_CA_EN = 0
4933 23:18:37.068959 CA_PICK = 933
4934 23:18:37.072068 CA_MCKIO = 933
4935 23:18:37.075590 MCKIO_SEMI = 0
4936 23:18:37.078952 PLL_FREQ = 3732
4937 23:18:37.082316 DQ_UI_PI_RATIO = 32
4938 23:18:37.082411 CA_UI_PI_RATIO = 0
4939 23:18:37.085866 ===================================
4940 23:18:37.089023 ===================================
4941 23:18:37.092156 memory_type:LPDDR4
4942 23:18:37.095567 GP_NUM : 10
4943 23:18:37.095649 SRAM_EN : 1
4944 23:18:37.099167 MD32_EN : 0
4945 23:18:37.102159 ===================================
4946 23:18:37.105738 [ANA_INIT] >>>>>>>>>>>>>>
4947 23:18:37.108770 <<<<<< [CONFIGURE PHASE]: ANA_TX
4948 23:18:37.112277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4949 23:18:37.115383 ===================================
4950 23:18:37.115465 data_rate = 1866,PCW = 0X8f00
4951 23:18:37.119207 ===================================
4952 23:18:37.122230 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4953 23:18:37.128839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4954 23:18:37.135452 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4955 23:18:37.138691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4956 23:18:37.142254 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4957 23:18:37.145440 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4958 23:18:37.148885 [ANA_INIT] flow start
4959 23:18:37.148972 [ANA_INIT] PLL >>>>>>>>
4960 23:18:37.152834 [ANA_INIT] PLL <<<<<<<<
4961 23:18:37.155990 [ANA_INIT] MIDPI >>>>>>>>
4962 23:18:37.159478 [ANA_INIT] MIDPI <<<<<<<<
4963 23:18:37.159561 [ANA_INIT] DLL >>>>>>>>
4964 23:18:37.162171 [ANA_INIT] flow end
4965 23:18:37.165908 ============ LP4 DIFF to SE enter ============
4966 23:18:37.169006 ============ LP4 DIFF to SE exit ============
4967 23:18:37.172838 [ANA_INIT] <<<<<<<<<<<<<
4968 23:18:37.176159 [Flow] Enable top DCM control >>>>>
4969 23:18:37.179159 [Flow] Enable top DCM control <<<<<
4970 23:18:37.181936 Enable DLL master slave shuffle
4971 23:18:37.188820 ==============================================================
4972 23:18:37.188933 Gating Mode config
4973 23:18:37.195331 ==============================================================
4974 23:18:37.195444 Config description:
4975 23:18:37.205858 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4976 23:18:37.211999 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4977 23:18:37.218862 SELPH_MODE 0: By rank 1: By Phase
4978 23:18:37.221891 ==============================================================
4979 23:18:37.225194 GAT_TRACK_EN = 1
4980 23:18:37.228871 RX_GATING_MODE = 2
4981 23:18:37.231909 RX_GATING_TRACK_MODE = 2
4982 23:18:37.235416 SELPH_MODE = 1
4983 23:18:37.238445 PICG_EARLY_EN = 1
4984 23:18:37.241829 VALID_LAT_VALUE = 1
4985 23:18:37.245064 ==============================================================
4986 23:18:37.248726 Enter into Gating configuration >>>>
4987 23:18:37.252022 Exit from Gating configuration <<<<
4988 23:18:37.255439 Enter into DVFS_PRE_config >>>>>
4989 23:18:37.268534 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4990 23:18:37.271979 Exit from DVFS_PRE_config <<<<<
4991 23:18:37.274978 Enter into PICG configuration >>>>
4992 23:18:37.275088 Exit from PICG configuration <<<<
4993 23:18:37.278301 [RX_INPUT] configuration >>>>>
4994 23:18:37.281816 [RX_INPUT] configuration <<<<<
4995 23:18:37.288460 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4996 23:18:37.291873 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4997 23:18:37.298806 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4998 23:18:37.305221 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4999 23:18:37.311649 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5000 23:18:37.318742 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5001 23:18:37.322108 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5002 23:18:37.325405 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5003 23:18:37.328783 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5004 23:18:37.334919 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5005 23:18:37.338864 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5006 23:18:37.341841 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5007 23:18:37.345138 ===================================
5008 23:18:37.348266 LPDDR4 DRAM CONFIGURATION
5009 23:18:37.351922 ===================================
5010 23:18:37.355029 EX_ROW_EN[0] = 0x0
5011 23:18:37.355139 EX_ROW_EN[1] = 0x0
5012 23:18:37.358640 LP4Y_EN = 0x0
5013 23:18:37.358751 WORK_FSP = 0x0
5014 23:18:37.361759 WL = 0x3
5015 23:18:37.361877 RL = 0x3
5016 23:18:37.364867 BL = 0x2
5017 23:18:37.364976 RPST = 0x0
5018 23:18:37.368135 RD_PRE = 0x0
5019 23:18:37.368245 WR_PRE = 0x1
5020 23:18:37.371597 WR_PST = 0x0
5021 23:18:37.371706 DBI_WR = 0x0
5022 23:18:37.375559 DBI_RD = 0x0
5023 23:18:37.375671 OTF = 0x1
5024 23:18:37.378564 ===================================
5025 23:18:37.381969 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5026 23:18:37.388447 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5027 23:18:37.391921 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5028 23:18:37.395384 ===================================
5029 23:18:37.398806 LPDDR4 DRAM CONFIGURATION
5030 23:18:37.401837 ===================================
5031 23:18:37.401951 EX_ROW_EN[0] = 0x10
5032 23:18:37.405423 EX_ROW_EN[1] = 0x0
5033 23:18:37.405533 LP4Y_EN = 0x0
5034 23:18:37.409146 WORK_FSP = 0x0
5035 23:18:37.409259 WL = 0x3
5036 23:18:37.412051 RL = 0x3
5037 23:18:37.415241 BL = 0x2
5038 23:18:37.415349 RPST = 0x0
5039 23:18:37.418820 RD_PRE = 0x0
5040 23:18:37.418927 WR_PRE = 0x1
5041 23:18:37.421962 WR_PST = 0x0
5042 23:18:37.422069 DBI_WR = 0x0
5043 23:18:37.425838 DBI_RD = 0x0
5044 23:18:37.425954 OTF = 0x1
5045 23:18:37.429035 ===================================
5046 23:18:37.435208 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5047 23:18:37.439171 nWR fixed to 30
5048 23:18:37.442088 [ModeRegInit_LP4] CH0 RK0
5049 23:18:37.442211 [ModeRegInit_LP4] CH0 RK1
5050 23:18:37.445819 [ModeRegInit_LP4] CH1 RK0
5051 23:18:37.449154 [ModeRegInit_LP4] CH1 RK1
5052 23:18:37.449267 match AC timing 9
5053 23:18:37.455818 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5054 23:18:37.459220 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5055 23:18:37.462316 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5056 23:18:37.468910 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5057 23:18:37.472559 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5058 23:18:37.472667 ==
5059 23:18:37.475692 Dram Type= 6, Freq= 0, CH_0, rank 0
5060 23:18:37.478905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5061 23:18:37.479012 ==
5062 23:18:37.485902 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5063 23:18:37.492236 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5064 23:18:37.495827 [CA 0] Center 38 (8~69) winsize 62
5065 23:18:37.498924 [CA 1] Center 38 (7~69) winsize 63
5066 23:18:37.502084 [CA 2] Center 35 (5~66) winsize 62
5067 23:18:37.505504 [CA 3] Center 34 (4~65) winsize 62
5068 23:18:37.509489 [CA 4] Center 34 (4~64) winsize 61
5069 23:18:37.512289 [CA 5] Center 34 (4~64) winsize 61
5070 23:18:37.512394
5071 23:18:37.515589 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5072 23:18:37.515695
5073 23:18:37.519062 [CATrainingPosCal] consider 1 rank data
5074 23:18:37.522477 u2DelayCellTimex100 = 270/100 ps
5075 23:18:37.525774 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5076 23:18:37.528882 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5077 23:18:37.532237 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5078 23:18:37.535489 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5079 23:18:37.538835 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5080 23:18:37.542403 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5081 23:18:37.542525
5082 23:18:37.548997 CA PerBit enable=1, Macro0, CA PI delay=34
5083 23:18:37.549106
5084 23:18:37.549195 [CBTSetCACLKResult] CA Dly = 34
5085 23:18:37.552148 CS Dly: 6 (0~37)
5086 23:18:37.552250 ==
5087 23:18:37.555877 Dram Type= 6, Freq= 0, CH_0, rank 1
5088 23:18:37.559211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 23:18:37.559314 ==
5090 23:18:37.565674 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5091 23:18:37.572794 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5092 23:18:37.576065 [CA 0] Center 38 (7~69) winsize 63
5093 23:18:37.578969 [CA 1] Center 38 (7~69) winsize 63
5094 23:18:37.582356 [CA 2] Center 35 (5~66) winsize 62
5095 23:18:37.586201 [CA 3] Center 35 (4~66) winsize 63
5096 23:18:37.589236 [CA 4] Center 34 (3~65) winsize 63
5097 23:18:37.592348 [CA 5] Center 33 (3~64) winsize 62
5098 23:18:37.592456
5099 23:18:37.595780 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5100 23:18:37.595886
5101 23:18:37.599122 [CATrainingPosCal] consider 2 rank data
5102 23:18:37.602704 u2DelayCellTimex100 = 270/100 ps
5103 23:18:37.606037 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5104 23:18:37.608995 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5105 23:18:37.612446 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5106 23:18:37.616277 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5107 23:18:37.619206 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5108 23:18:37.622596 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5109 23:18:37.622704
5110 23:18:37.625888 CA PerBit enable=1, Macro0, CA PI delay=34
5111 23:18:37.629129
5112 23:18:37.629234 [CBTSetCACLKResult] CA Dly = 34
5113 23:18:37.632695 CS Dly: 7 (0~39)
5114 23:18:37.632798
5115 23:18:37.635761 ----->DramcWriteLeveling(PI) begin...
5116 23:18:37.635868 ==
5117 23:18:37.638900 Dram Type= 6, Freq= 0, CH_0, rank 0
5118 23:18:37.642339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5119 23:18:37.642468 ==
5120 23:18:37.645607 Write leveling (Byte 0): 31 => 31
5121 23:18:37.648719 Write leveling (Byte 1): 30 => 30
5122 23:18:37.651996 DramcWriteLeveling(PI) end<-----
5123 23:18:37.652100
5124 23:18:37.652193 ==
5125 23:18:37.655703 Dram Type= 6, Freq= 0, CH_0, rank 0
5126 23:18:37.658639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5127 23:18:37.662457 ==
5128 23:18:37.662563 [Gating] SW mode calibration
5129 23:18:37.668998 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5130 23:18:37.675886 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5131 23:18:37.678884 0 14 0 | B1->B0 | 2323 2b2b | 1 1 | (1 1) (1 1)
5132 23:18:37.685940 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5133 23:18:37.689125 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 23:18:37.692570 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 23:18:37.699117 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 23:18:37.702526 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 23:18:37.705817 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 23:18:37.712242 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
5139 23:18:37.715220 0 15 0 | B1->B0 | 3232 2626 | 1 0 | (1 0) (0 0)
5140 23:18:37.718932 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
5141 23:18:37.725076 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 23:18:37.728896 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 23:18:37.731987 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 23:18:37.735442 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 23:18:37.741967 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 23:18:37.745426 0 15 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5147 23:18:37.748582 1 0 0 | B1->B0 | 2e2e 3d3d | 1 0 | (1 1) (0 0)
5148 23:18:37.755483 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 23:18:37.758988 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 23:18:37.762220 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 23:18:37.768964 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 23:18:37.772178 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 23:18:37.775512 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 23:18:37.782445 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5155 23:18:37.785274 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5156 23:18:37.789077 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 23:18:37.795912 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 23:18:37.799178 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 23:18:37.802085 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 23:18:37.808819 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 23:18:37.812775 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 23:18:37.815558 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 23:18:37.818899 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 23:18:37.825484 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 23:18:37.829169 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 23:18:37.832390 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 23:18:37.838677 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 23:18:37.842129 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 23:18:37.845699 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 23:18:37.852546 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5171 23:18:37.855467 Total UI for P1: 0, mck2ui 16
5172 23:18:37.858924 best dqsien dly found for B0: ( 1, 2, 26)
5173 23:18:37.862458 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5174 23:18:37.865513 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 23:18:37.868902 Total UI for P1: 0, mck2ui 16
5176 23:18:37.872762 best dqsien dly found for B1: ( 1, 2, 30)
5177 23:18:37.875555 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5178 23:18:37.879138 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5179 23:18:37.879243
5180 23:18:37.885837 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5181 23:18:37.889434 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5182 23:18:37.889542 [Gating] SW calibration Done
5183 23:18:37.892234 ==
5184 23:18:37.895309 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 23:18:37.898770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 23:18:37.898881 ==
5187 23:18:37.898973 RX Vref Scan: 0
5188 23:18:37.899061
5189 23:18:37.902647 RX Vref 0 -> 0, step: 1
5190 23:18:37.902753
5191 23:18:37.905182 RX Delay -80 -> 252, step: 8
5192 23:18:37.908910 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5193 23:18:37.912251 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5194 23:18:37.915459 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5195 23:18:37.918999 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5196 23:18:37.925493 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5197 23:18:37.929275 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5198 23:18:37.932264 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5199 23:18:37.935466 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5200 23:18:37.938570 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5201 23:18:37.942646 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5202 23:18:37.948959 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5203 23:18:37.952651 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5204 23:18:37.955409 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5205 23:18:37.959001 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5206 23:18:37.962707 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5207 23:18:37.965686 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5208 23:18:37.968996 ==
5209 23:18:37.972254 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 23:18:37.975636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 23:18:37.975737 ==
5212 23:18:37.975815 DQS Delay:
5213 23:18:37.979147 DQS0 = 0, DQS1 = 0
5214 23:18:37.979229 DQM Delay:
5215 23:18:37.981954 DQM0 = 97, DQM1 = 88
5216 23:18:37.982035 DQ Delay:
5217 23:18:37.985306 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5218 23:18:37.988678 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5219 23:18:37.992013 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5220 23:18:37.995429 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5221 23:18:37.995539
5222 23:18:37.995628
5223 23:18:37.995715 ==
5224 23:18:37.998896 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 23:18:38.002411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 23:18:38.002519 ==
5227 23:18:38.002610
5228 23:18:38.002698
5229 23:18:38.005373 TX Vref Scan disable
5230 23:18:38.008473 == TX Byte 0 ==
5231 23:18:38.012060 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5232 23:18:38.015142 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5233 23:18:38.018687 == TX Byte 1 ==
5234 23:18:38.021906 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5235 23:18:38.025656 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5236 23:18:38.025760 ==
5237 23:18:38.028974 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 23:18:38.032081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 23:18:38.035594 ==
5240 23:18:38.035700
5241 23:18:38.035791
5242 23:18:38.035878 TX Vref Scan disable
5243 23:18:38.039276 == TX Byte 0 ==
5244 23:18:38.042816 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5245 23:18:38.049558 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5246 23:18:38.049676 == TX Byte 1 ==
5247 23:18:38.052104 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5248 23:18:38.059211 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5249 23:18:38.059326
5250 23:18:38.059418 [DATLAT]
5251 23:18:38.059506 Freq=933, CH0 RK0
5252 23:18:38.059592
5253 23:18:38.062472 DATLAT Default: 0xd
5254 23:18:38.062577 0, 0xFFFF, sum = 0
5255 23:18:38.065562 1, 0xFFFF, sum = 0
5256 23:18:38.065667 2, 0xFFFF, sum = 0
5257 23:18:38.069188 3, 0xFFFF, sum = 0
5258 23:18:38.069294 4, 0xFFFF, sum = 0
5259 23:18:38.072224 5, 0xFFFF, sum = 0
5260 23:18:38.075961 6, 0xFFFF, sum = 0
5261 23:18:38.076070 7, 0xFFFF, sum = 0
5262 23:18:38.078995 8, 0xFFFF, sum = 0
5263 23:18:38.079099 9, 0xFFFF, sum = 0
5264 23:18:38.082555 10, 0x0, sum = 1
5265 23:18:38.082662 11, 0x0, sum = 2
5266 23:18:38.082754 12, 0x0, sum = 3
5267 23:18:38.085863 13, 0x0, sum = 4
5268 23:18:38.085968 best_step = 11
5269 23:18:38.086058
5270 23:18:38.086147 ==
5271 23:18:38.089255 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 23:18:38.095580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 23:18:38.095689 ==
5274 23:18:38.095779 RX Vref Scan: 1
5275 23:18:38.095867
5276 23:18:38.099312 RX Vref 0 -> 0, step: 1
5277 23:18:38.099416
5278 23:18:38.102637 RX Delay -61 -> 252, step: 4
5279 23:18:38.102740
5280 23:18:38.106006 Set Vref, RX VrefLevel [Byte0]: 58
5281 23:18:38.108940 [Byte1]: 51
5282 23:18:38.109045
5283 23:18:38.112274 Final RX Vref Byte 0 = 58 to rank0
5284 23:18:38.116031 Final RX Vref Byte 1 = 51 to rank0
5285 23:18:38.119303 Final RX Vref Byte 0 = 58 to rank1
5286 23:18:38.122698 Final RX Vref Byte 1 = 51 to rank1==
5287 23:18:38.125451 Dram Type= 6, Freq= 0, CH_0, rank 0
5288 23:18:38.129532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 23:18:38.129639 ==
5290 23:18:38.132601 DQS Delay:
5291 23:18:38.132705 DQS0 = 0, DQS1 = 0
5292 23:18:38.135856 DQM Delay:
5293 23:18:38.135966 DQM0 = 96, DQM1 = 87
5294 23:18:38.136056 DQ Delay:
5295 23:18:38.139289 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =92
5296 23:18:38.142267 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =104
5297 23:18:38.146046 DQ8 =80, DQ9 =74, DQ10 =86, DQ11 =80
5298 23:18:38.148788 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =98
5299 23:18:38.148891
5300 23:18:38.152359
5301 23:18:38.158934 [DQSOSCAuto] RK0, (LSB)MR18= 0x1400, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5302 23:18:38.162232 CH0 RK0: MR19=505, MR18=1400
5303 23:18:38.168839 CH0_RK0: MR19=0x505, MR18=0x1400, DQSOSC=415, MR23=63, INC=62, DEC=41
5304 23:18:38.168933
5305 23:18:38.172088 ----->DramcWriteLeveling(PI) begin...
5306 23:18:38.172171 ==
5307 23:18:38.175329 Dram Type= 6, Freq= 0, CH_0, rank 1
5308 23:18:38.178619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 23:18:38.178703 ==
5310 23:18:38.181985 Write leveling (Byte 0): 35 => 35
5311 23:18:38.185562 Write leveling (Byte 1): 30 => 30
5312 23:18:38.189382 DramcWriteLeveling(PI) end<-----
5313 23:18:38.189465
5314 23:18:38.189527 ==
5315 23:18:38.192231 Dram Type= 6, Freq= 0, CH_0, rank 1
5316 23:18:38.195514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 23:18:38.195596 ==
5318 23:18:38.198830 [Gating] SW mode calibration
5319 23:18:38.205268 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5320 23:18:38.212091 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5321 23:18:38.215499 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5322 23:18:38.218616 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5323 23:18:38.226119 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 23:18:38.228542 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 23:18:38.231958 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 23:18:38.238462 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 23:18:38.241915 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5328 23:18:38.245400 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
5329 23:18:38.252063 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5330 23:18:38.255295 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5331 23:18:38.258683 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 23:18:38.261935 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 23:18:38.268858 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 23:18:38.272014 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 23:18:38.275454 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 23:18:38.281908 0 15 28 | B1->B0 | 2626 3535 | 0 0 | (0 0) (1 1)
5337 23:18:38.285562 1 0 0 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
5338 23:18:38.288542 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 23:18:38.295650 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 23:18:38.300300 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 23:18:38.302222 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 23:18:38.308584 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 23:18:38.311956 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5344 23:18:38.315310 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5345 23:18:38.321984 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5346 23:18:38.325199 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5347 23:18:38.328721 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 23:18:38.335736 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 23:18:38.338408 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 23:18:38.342266 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 23:18:38.349101 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 23:18:38.351839 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 23:18:38.355284 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 23:18:38.358604 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 23:18:38.365631 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 23:18:38.368744 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 23:18:38.371989 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 23:18:38.378566 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 23:18:38.382144 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 23:18:38.385097 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5361 23:18:38.388377 Total UI for P1: 0, mck2ui 16
5362 23:18:38.392135 best dqsien dly found for B0: ( 1, 2, 26)
5363 23:18:38.398565 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5364 23:18:38.401882 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 23:18:38.405454 Total UI for P1: 0, mck2ui 16
5366 23:18:38.408930 best dqsien dly found for B1: ( 1, 2, 30)
5367 23:18:38.412343 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5368 23:18:38.415741 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5369 23:18:38.415845
5370 23:18:38.418897 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5371 23:18:38.422102 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5372 23:18:38.425711 [Gating] SW calibration Done
5373 23:18:38.425815 ==
5374 23:18:38.428866 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 23:18:38.432246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 23:18:38.435327 ==
5377 23:18:38.435430 RX Vref Scan: 0
5378 23:18:38.435519
5379 23:18:38.438754 RX Vref 0 -> 0, step: 1
5380 23:18:38.438858
5381 23:18:38.438947 RX Delay -80 -> 252, step: 8
5382 23:18:38.445540 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5383 23:18:38.448737 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5384 23:18:38.452336 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5385 23:18:38.455648 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5386 23:18:38.458720 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5387 23:18:38.462170 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5388 23:18:38.469158 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5389 23:18:38.472117 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5390 23:18:38.475790 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5391 23:18:38.479053 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5392 23:18:38.482601 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5393 23:18:38.489237 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5394 23:18:38.492230 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5395 23:18:38.495494 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5396 23:18:38.499172 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5397 23:18:38.502322 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5398 23:18:38.502461 ==
5399 23:18:38.505642 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 23:18:38.512200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 23:18:38.512280 ==
5402 23:18:38.512342 DQS Delay:
5403 23:18:38.516163 DQS0 = 0, DQS1 = 0
5404 23:18:38.516243 DQM Delay:
5405 23:18:38.516305 DQM0 = 96, DQM1 = 87
5406 23:18:38.518703 DQ Delay:
5407 23:18:38.522418 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5408 23:18:38.525705 DQ4 =95, DQ5 =87, DQ6 =111, DQ7 =103
5409 23:18:38.528789 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =79
5410 23:18:38.532600 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =95
5411 23:18:38.532680
5412 23:18:38.532742
5413 23:18:38.532799 ==
5414 23:18:38.535316 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 23:18:38.538585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 23:18:38.538675 ==
5417 23:18:38.538738
5418 23:18:38.538795
5419 23:18:38.542003 TX Vref Scan disable
5420 23:18:38.542106 == TX Byte 0 ==
5421 23:18:38.548699 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5422 23:18:38.552056 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5423 23:18:38.552138 == TX Byte 1 ==
5424 23:18:38.558816 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5425 23:18:38.561980 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5426 23:18:38.562060 ==
5427 23:18:38.565250 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 23:18:38.568476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 23:18:38.568556 ==
5430 23:18:38.568618
5431 23:18:38.571926
5432 23:18:38.572005 TX Vref Scan disable
5433 23:18:38.575464 == TX Byte 0 ==
5434 23:18:38.578679 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5435 23:18:38.582370 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5436 23:18:38.585481 == TX Byte 1 ==
5437 23:18:38.588857 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5438 23:18:38.592206 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5439 23:18:38.592313
5440 23:18:38.595557 [DATLAT]
5441 23:18:38.595636 Freq=933, CH0 RK1
5442 23:18:38.595698
5443 23:18:38.598665 DATLAT Default: 0xb
5444 23:18:38.598744 0, 0xFFFF, sum = 0
5445 23:18:38.602189 1, 0xFFFF, sum = 0
5446 23:18:38.602270 2, 0xFFFF, sum = 0
5447 23:18:38.605360 3, 0xFFFF, sum = 0
5448 23:18:38.605442 4, 0xFFFF, sum = 0
5449 23:18:38.608921 5, 0xFFFF, sum = 0
5450 23:18:38.609006 6, 0xFFFF, sum = 0
5451 23:18:38.612457 7, 0xFFFF, sum = 0
5452 23:18:38.612541 8, 0xFFFF, sum = 0
5453 23:18:38.616549 9, 0xFFFF, sum = 0
5454 23:18:38.616633 10, 0x0, sum = 1
5455 23:18:38.619112 11, 0x0, sum = 2
5456 23:18:38.619193 12, 0x0, sum = 3
5457 23:18:38.622012 13, 0x0, sum = 4
5458 23:18:38.622093 best_step = 11
5459 23:18:38.622156
5460 23:18:38.622214 ==
5461 23:18:38.625852 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 23:18:38.632222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 23:18:38.632305 ==
5464 23:18:38.632368 RX Vref Scan: 0
5465 23:18:38.632425
5466 23:18:38.636040 RX Vref 0 -> 0, step: 1
5467 23:18:38.636122
5468 23:18:38.639292 RX Delay -61 -> 252, step: 4
5469 23:18:38.642167 iDelay=199, Bit 0, Center 96 (-1 ~ 194) 196
5470 23:18:38.645854 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5471 23:18:38.649180 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5472 23:18:38.655995 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5473 23:18:38.658966 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5474 23:18:38.662250 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5475 23:18:38.665598 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5476 23:18:38.668843 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5477 23:18:38.675410 iDelay=199, Bit 8, Center 78 (-9 ~ 166) 176
5478 23:18:38.678993 iDelay=199, Bit 9, Center 76 (-13 ~ 166) 180
5479 23:18:38.682573 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5480 23:18:38.685802 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5481 23:18:38.689490 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5482 23:18:38.692614 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5483 23:18:38.698869 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5484 23:18:38.702611 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5485 23:18:38.702700 ==
5486 23:18:38.705814 Dram Type= 6, Freq= 0, CH_0, rank 1
5487 23:18:38.708837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 23:18:38.708918 ==
5489 23:18:38.708981 DQS Delay:
5490 23:18:38.712406 DQS0 = 0, DQS1 = 0
5491 23:18:38.712487 DQM Delay:
5492 23:18:38.715809 DQM0 = 96, DQM1 = 87
5493 23:18:38.715889 DQ Delay:
5494 23:18:38.719379 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5495 23:18:38.722439 DQ4 =94, DQ5 =86, DQ6 =106, DQ7 =104
5496 23:18:38.725909 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =80
5497 23:18:38.728951 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =94
5498 23:18:38.729032
5499 23:18:38.729095
5500 23:18:38.738908 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b08, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5501 23:18:38.739005 CH0 RK1: MR19=505, MR18=1B08
5502 23:18:38.745809 CH0_RK1: MR19=0x505, MR18=0x1B08, DQSOSC=413, MR23=63, INC=63, DEC=42
5503 23:18:38.748929 [RxdqsGatingPostProcess] freq 933
5504 23:18:38.755795 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5505 23:18:38.759039 best DQS0 dly(2T, 0.5T) = (0, 10)
5506 23:18:38.762269 best DQS1 dly(2T, 0.5T) = (0, 10)
5507 23:18:38.765852 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5508 23:18:38.769323 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5509 23:18:38.772554 best DQS0 dly(2T, 0.5T) = (0, 10)
5510 23:18:38.772637 best DQS1 dly(2T, 0.5T) = (0, 10)
5511 23:18:38.775618 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5512 23:18:38.779061 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5513 23:18:38.782532 Pre-setting of DQS Precalculation
5514 23:18:38.788677 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5515 23:18:38.788760 ==
5516 23:18:38.792864 Dram Type= 6, Freq= 0, CH_1, rank 0
5517 23:18:38.795484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5518 23:18:38.795568 ==
5519 23:18:38.802278 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5520 23:18:38.809094 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5521 23:18:38.812443 [CA 0] Center 36 (6~67) winsize 62
5522 23:18:38.815643 [CA 1] Center 36 (6~67) winsize 62
5523 23:18:38.818863 [CA 2] Center 34 (4~64) winsize 61
5524 23:18:38.822627 [CA 3] Center 33 (3~64) winsize 62
5525 23:18:38.825538 [CA 4] Center 34 (4~65) winsize 62
5526 23:18:38.825621 [CA 5] Center 33 (3~64) winsize 62
5527 23:18:38.828818
5528 23:18:38.832241 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5529 23:18:38.832322
5530 23:18:38.835390 [CATrainingPosCal] consider 1 rank data
5531 23:18:38.839008 u2DelayCellTimex100 = 270/100 ps
5532 23:18:38.842505 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5533 23:18:38.845600 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5534 23:18:38.849130 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5535 23:18:38.852235 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5536 23:18:38.856131 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5537 23:18:38.858844 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5538 23:18:38.858949
5539 23:18:38.862054 CA PerBit enable=1, Macro0, CA PI delay=33
5540 23:18:38.862162
5541 23:18:38.865852 [CBTSetCACLKResult] CA Dly = 33
5542 23:18:38.869162 CS Dly: 4 (0~35)
5543 23:18:38.869268 ==
5544 23:18:38.872140 Dram Type= 6, Freq= 0, CH_1, rank 1
5545 23:18:38.875945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 23:18:38.876052 ==
5547 23:18:38.882223 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5548 23:18:38.885787 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5549 23:18:38.889915 [CA 0] Center 36 (6~67) winsize 62
5550 23:18:38.893158 [CA 1] Center 37 (7~67) winsize 61
5551 23:18:38.896517 [CA 2] Center 33 (3~64) winsize 62
5552 23:18:38.899873 [CA 3] Center 33 (3~64) winsize 62
5553 23:18:38.903256 [CA 4] Center 33 (3~64) winsize 62
5554 23:18:38.906604 [CA 5] Center 32 (2~63) winsize 62
5555 23:18:38.906712
5556 23:18:38.910265 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5557 23:18:38.910370
5558 23:18:38.913528 [CATrainingPosCal] consider 2 rank data
5559 23:18:38.916913 u2DelayCellTimex100 = 270/100 ps
5560 23:18:38.920337 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5561 23:18:38.923466 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5562 23:18:38.930738 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5563 23:18:38.933519 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5564 23:18:38.937170 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5565 23:18:38.940756 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5566 23:18:38.940869
5567 23:18:38.943401 CA PerBit enable=1, Macro0, CA PI delay=33
5568 23:18:38.943520
5569 23:18:38.946916 [CBTSetCACLKResult] CA Dly = 33
5570 23:18:38.947026 CS Dly: 5 (0~38)
5571 23:18:38.947119
5572 23:18:38.950691 ----->DramcWriteLeveling(PI) begin...
5573 23:18:38.950799 ==
5574 23:18:38.953699 Dram Type= 6, Freq= 0, CH_1, rank 0
5575 23:18:38.960505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5576 23:18:38.960592 ==
5577 23:18:38.963545 Write leveling (Byte 0): 24 => 24
5578 23:18:38.967352 Write leveling (Byte 1): 28 => 28
5579 23:18:38.967442 DramcWriteLeveling(PI) end<-----
5580 23:18:38.967505
5581 23:18:38.970215 ==
5582 23:18:38.973463 Dram Type= 6, Freq= 0, CH_1, rank 0
5583 23:18:38.977435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5584 23:18:38.977547 ==
5585 23:18:38.980284 [Gating] SW mode calibration
5586 23:18:38.986845 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5587 23:18:38.990876 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5588 23:18:38.997007 0 14 0 | B1->B0 | 3131 3131 | 0 0 | (0 0) (0 0)
5589 23:18:39.000373 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 23:18:39.003815 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 23:18:39.010318 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 23:18:39.013456 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 23:18:39.016728 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 23:18:39.023439 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5595 23:18:39.026775 0 14 28 | B1->B0 | 2f2f 3131 | 0 0 | (1 1) (0 1)
5596 23:18:39.030336 0 15 0 | B1->B0 | 2727 2c2c | 0 1 | (0 0) (1 0)
5597 23:18:39.037127 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 23:18:39.040320 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 23:18:39.043891 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 23:18:39.050115 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 23:18:39.053228 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 23:18:39.056773 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 23:18:39.063918 0 15 28 | B1->B0 | 2828 2b2b | 1 1 | (0 0) (0 0)
5604 23:18:39.067050 1 0 0 | B1->B0 | 4343 4242 | 0 0 | (0 0) (0 0)
5605 23:18:39.070168 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 23:18:39.073830 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 23:18:39.080352 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 23:18:39.083516 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 23:18:39.087198 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 23:18:39.094137 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 23:18:39.097023 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5612 23:18:39.100641 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5613 23:18:39.106810 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 23:18:39.110534 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 23:18:39.113479 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 23:18:39.120393 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 23:18:39.123401 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 23:18:39.126928 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 23:18:39.133996 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 23:18:39.136802 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 23:18:39.140360 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 23:18:39.147145 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 23:18:39.150301 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 23:18:39.153814 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 23:18:39.160001 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 23:18:39.163344 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 23:18:39.167066 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5628 23:18:39.170513 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 23:18:39.173573 Total UI for P1: 0, mck2ui 16
5630 23:18:39.176975 best dqsien dly found for B0: ( 1, 2, 28)
5631 23:18:39.180587 Total UI for P1: 0, mck2ui 16
5632 23:18:39.184155 best dqsien dly found for B1: ( 1, 2, 28)
5633 23:18:39.187432 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5634 23:18:39.190573 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5635 23:18:39.190676
5636 23:18:39.196967 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5637 23:18:39.200055 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5638 23:18:39.203394 [Gating] SW calibration Done
5639 23:18:39.203497 ==
5640 23:18:39.206709 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 23:18:39.210283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 23:18:39.210386 ==
5643 23:18:39.210512 RX Vref Scan: 0
5644 23:18:39.210599
5645 23:18:39.213525 RX Vref 0 -> 0, step: 1
5646 23:18:39.213625
5647 23:18:39.217104 RX Delay -80 -> 252, step: 8
5648 23:18:39.220402 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5649 23:18:39.223817 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5650 23:18:39.227159 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5651 23:18:39.233564 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5652 23:18:39.237224 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5653 23:18:39.240187 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5654 23:18:39.243661 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5655 23:18:39.246701 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5656 23:18:39.250471 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5657 23:18:39.256783 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5658 23:18:39.260100 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5659 23:18:39.263411 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5660 23:18:39.266904 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5661 23:18:39.270270 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5662 23:18:39.274174 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5663 23:18:39.280414 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5664 23:18:39.280511 ==
5665 23:18:39.283490 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 23:18:39.286789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 23:18:39.286864 ==
5668 23:18:39.286931 DQS Delay:
5669 23:18:39.290202 DQS0 = 0, DQS1 = 0
5670 23:18:39.290272 DQM Delay:
5671 23:18:39.293780 DQM0 = 97, DQM1 = 88
5672 23:18:39.293848 DQ Delay:
5673 23:18:39.296894 DQ0 =99, DQ1 =95, DQ2 =83, DQ3 =95
5674 23:18:39.300554 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5675 23:18:39.303467 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5676 23:18:39.307049 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5677 23:18:39.307123
5678 23:18:39.307184
5679 23:18:39.307247 ==
5680 23:18:39.310263 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 23:18:39.313639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 23:18:39.313711 ==
5683 23:18:39.317102
5684 23:18:39.317171
5685 23:18:39.317229 TX Vref Scan disable
5686 23:18:39.320203 == TX Byte 0 ==
5687 23:18:39.323746 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5688 23:18:39.326906 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5689 23:18:39.330221 == TX Byte 1 ==
5690 23:18:39.333866 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5691 23:18:39.337099 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5692 23:18:39.337172 ==
5693 23:18:39.340403 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 23:18:39.346893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 23:18:39.346988 ==
5696 23:18:39.347052
5697 23:18:39.347112
5698 23:18:39.347170 TX Vref Scan disable
5699 23:18:39.350833 == TX Byte 0 ==
5700 23:18:39.354514 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5701 23:18:39.357822 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5702 23:18:39.361240 == TX Byte 1 ==
5703 23:18:39.364618 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5704 23:18:39.370744 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5705 23:18:39.370821
5706 23:18:39.370889 [DATLAT]
5707 23:18:39.370948 Freq=933, CH1 RK0
5708 23:18:39.371005
5709 23:18:39.374784 DATLAT Default: 0xd
5710 23:18:39.374855 0, 0xFFFF, sum = 0
5711 23:18:39.377772 1, 0xFFFF, sum = 0
5712 23:18:39.377841 2, 0xFFFF, sum = 0
5713 23:18:39.380774 3, 0xFFFF, sum = 0
5714 23:18:39.380847 4, 0xFFFF, sum = 0
5715 23:18:39.384159 5, 0xFFFF, sum = 0
5716 23:18:39.388406 6, 0xFFFF, sum = 0
5717 23:18:39.388507 7, 0xFFFF, sum = 0
5718 23:18:39.390734 8, 0xFFFF, sum = 0
5719 23:18:39.390804 9, 0xFFFF, sum = 0
5720 23:18:39.394568 10, 0x0, sum = 1
5721 23:18:39.394643 11, 0x0, sum = 2
5722 23:18:39.394703 12, 0x0, sum = 3
5723 23:18:39.398159 13, 0x0, sum = 4
5724 23:18:39.398256 best_step = 11
5725 23:18:39.398342
5726 23:18:39.400678 ==
5727 23:18:39.400749 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 23:18:39.407440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 23:18:39.407518 ==
5730 23:18:39.407579 RX Vref Scan: 1
5731 23:18:39.407634
5732 23:18:39.411105 RX Vref 0 -> 0, step: 1
5733 23:18:39.411179
5734 23:18:39.414556 RX Delay -69 -> 252, step: 4
5735 23:18:39.414628
5736 23:18:39.417339 Set Vref, RX VrefLevel [Byte0]: 57
5737 23:18:39.420902 [Byte1]: 46
5738 23:18:39.420974
5739 23:18:39.424370 Final RX Vref Byte 0 = 57 to rank0
5740 23:18:39.427806 Final RX Vref Byte 1 = 46 to rank0
5741 23:18:39.430813 Final RX Vref Byte 0 = 57 to rank1
5742 23:18:39.434367 Final RX Vref Byte 1 = 46 to rank1==
5743 23:18:39.437789 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 23:18:39.440926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 23:18:39.441000 ==
5746 23:18:39.444552 DQS Delay:
5747 23:18:39.444627 DQS0 = 0, DQS1 = 0
5748 23:18:39.447916 DQM Delay:
5749 23:18:39.447993 DQM0 = 97, DQM1 = 90
5750 23:18:39.448056 DQ Delay:
5751 23:18:39.451012 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =98
5752 23:18:39.454260 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =94
5753 23:18:39.457440 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =88
5754 23:18:39.461331 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =96
5755 23:18:39.461405
5756 23:18:39.461466
5757 23:18:39.471103 [DQSOSCAuto] RK0, (LSB)MR18= 0x11ee, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5758 23:18:39.474655 CH1 RK0: MR19=504, MR18=11EE
5759 23:18:39.477815 CH1_RK0: MR19=0x504, MR18=0x11EE, DQSOSC=416, MR23=63, INC=62, DEC=41
5760 23:18:39.481003
5761 23:18:39.484297 ----->DramcWriteLeveling(PI) begin...
5762 23:18:39.484368 ==
5763 23:18:39.487587 Dram Type= 6, Freq= 0, CH_1, rank 1
5764 23:18:39.491307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 23:18:39.491377 ==
5766 23:18:39.495049 Write leveling (Byte 0): 27 => 27
5767 23:18:39.497782 Write leveling (Byte 1): 29 => 29
5768 23:18:39.501077 DramcWriteLeveling(PI) end<-----
5769 23:18:39.501151
5770 23:18:39.501209 ==
5771 23:18:39.504528 Dram Type= 6, Freq= 0, CH_1, rank 1
5772 23:18:39.507952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 23:18:39.508027 ==
5774 23:18:39.511316 [Gating] SW mode calibration
5775 23:18:39.517785 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5776 23:18:39.524286 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5777 23:18:39.527780 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 23:18:39.530998 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 23:18:39.534529 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5780 23:18:39.541184 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 23:18:39.544780 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 23:18:39.547912 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 23:18:39.554867 0 14 24 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (0 0)
5784 23:18:39.557565 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
5785 23:18:39.561265 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 23:18:39.568213 0 15 4 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5787 23:18:39.570927 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 23:18:39.574967 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 23:18:39.581485 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 23:18:39.584457 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 23:18:39.588009 0 15 24 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
5792 23:18:39.594295 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5793 23:18:39.597651 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 23:18:39.601085 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 23:18:39.608055 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 23:18:39.611094 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 23:18:39.614567 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 23:18:39.620990 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 23:18:39.624642 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5800 23:18:39.627552 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 23:18:39.631003 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5802 23:18:39.637532 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 23:18:39.640963 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 23:18:39.644960 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 23:18:39.651140 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 23:18:39.654679 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 23:18:39.657872 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 23:18:39.664391 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 23:18:39.668197 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 23:18:39.671475 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 23:18:39.678081 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 23:18:39.680885 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 23:18:39.684693 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 23:18:39.691237 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 23:18:39.694367 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5816 23:18:39.697783 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 23:18:39.701215 Total UI for P1: 0, mck2ui 16
5818 23:18:39.704644 best dqsien dly found for B0: ( 1, 2, 24)
5819 23:18:39.707675 Total UI for P1: 0, mck2ui 16
5820 23:18:39.711186 best dqsien dly found for B1: ( 1, 2, 26)
5821 23:18:39.714786 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5822 23:18:39.717916 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5823 23:18:39.717992
5824 23:18:39.721165 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5825 23:18:39.727947 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5826 23:18:39.728038 [Gating] SW calibration Done
5827 23:18:39.728100 ==
5828 23:18:39.731179 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 23:18:39.737917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 23:18:39.738004 ==
5831 23:18:39.738064 RX Vref Scan: 0
5832 23:18:39.738127
5833 23:18:39.741824 RX Vref 0 -> 0, step: 1
5834 23:18:39.741896
5835 23:18:39.744424 RX Delay -80 -> 252, step: 8
5836 23:18:39.747726 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5837 23:18:39.751360 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5838 23:18:39.754763 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5839 23:18:39.757906 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5840 23:18:39.764577 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5841 23:18:39.767949 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5842 23:18:39.771474 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5843 23:18:39.774348 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5844 23:18:39.777721 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5845 23:18:39.781053 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5846 23:18:39.787992 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5847 23:18:39.791194 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5848 23:18:39.794358 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5849 23:18:39.797372 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5850 23:18:39.800827 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5851 23:18:39.804280 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5852 23:18:39.807578 ==
5853 23:18:39.811038 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 23:18:39.814366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 23:18:39.814510 ==
5856 23:18:39.814600 DQS Delay:
5857 23:18:39.817775 DQS0 = 0, DQS1 = 0
5858 23:18:39.817877 DQM Delay:
5859 23:18:39.820766 DQM0 = 94, DQM1 = 89
5860 23:18:39.820868 DQ Delay:
5861 23:18:39.824042 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5862 23:18:39.827400 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5863 23:18:39.831000 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5864 23:18:39.834456 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5865 23:18:39.834560
5866 23:18:39.834648
5867 23:18:39.834735 ==
5868 23:18:39.837460 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 23:18:39.840758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 23:18:39.840864 ==
5871 23:18:39.840953
5872 23:18:39.841039
5873 23:18:39.844175 TX Vref Scan disable
5874 23:18:39.847684 == TX Byte 0 ==
5875 23:18:39.851125 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5876 23:18:39.854492 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5877 23:18:39.857460 == TX Byte 1 ==
5878 23:18:39.860803 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5879 23:18:39.864238 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5880 23:18:39.864347 ==
5881 23:18:39.867805 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 23:18:39.870693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 23:18:39.874061 ==
5884 23:18:39.874169
5885 23:18:39.874260
5886 23:18:39.874348 TX Vref Scan disable
5887 23:18:39.878327 == TX Byte 0 ==
5888 23:18:39.881138 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5889 23:18:39.884428 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5890 23:18:39.887717 == TX Byte 1 ==
5891 23:18:39.891308 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5892 23:18:39.894716 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5893 23:18:39.897942
5894 23:18:39.898049 [DATLAT]
5895 23:18:39.898141 Freq=933, CH1 RK1
5896 23:18:39.898229
5897 23:18:39.901299 DATLAT Default: 0xb
5898 23:18:39.901404 0, 0xFFFF, sum = 0
5899 23:18:39.904623 1, 0xFFFF, sum = 0
5900 23:18:39.904733 2, 0xFFFF, sum = 0
5901 23:18:39.907987 3, 0xFFFF, sum = 0
5902 23:18:39.908097 4, 0xFFFF, sum = 0
5903 23:18:39.911141 5, 0xFFFF, sum = 0
5904 23:18:39.911246 6, 0xFFFF, sum = 0
5905 23:18:39.914664 7, 0xFFFF, sum = 0
5906 23:18:39.914767 8, 0xFFFF, sum = 0
5907 23:18:39.918494 9, 0xFFFF, sum = 0
5908 23:18:39.918599 10, 0x0, sum = 1
5909 23:18:39.921205 11, 0x0, sum = 2
5910 23:18:39.921310 12, 0x0, sum = 3
5911 23:18:39.924891 13, 0x0, sum = 4
5912 23:18:39.924997 best_step = 11
5913 23:18:39.925089
5914 23:18:39.925178 ==
5915 23:18:39.927879 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 23:18:39.934583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 23:18:39.934693 ==
5918 23:18:39.934786 RX Vref Scan: 0
5919 23:18:39.934873
5920 23:18:39.938261 RX Vref 0 -> 0, step: 1
5921 23:18:39.938364
5922 23:18:39.941363 RX Delay -61 -> 252, step: 4
5923 23:18:39.944962 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5924 23:18:39.947697 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5925 23:18:39.954718 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5926 23:18:39.958148 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5927 23:18:39.961461 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5928 23:18:39.964589 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5929 23:18:39.968586 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5930 23:18:39.971469 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5931 23:18:39.978238 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5932 23:18:39.981888 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5933 23:18:39.984943 iDelay=199, Bit 10, Center 92 (3 ~ 182) 180
5934 23:18:39.988129 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5935 23:18:39.991544 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5936 23:18:39.994676 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5937 23:18:40.001608 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5938 23:18:40.004842 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5939 23:18:40.004953 ==
5940 23:18:40.008130 Dram Type= 6, Freq= 0, CH_1, rank 1
5941 23:18:40.011184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5942 23:18:40.011290 ==
5943 23:18:40.014802 DQS Delay:
5944 23:18:40.014908 DQS0 = 0, DQS1 = 0
5945 23:18:40.015008 DQM Delay:
5946 23:18:40.018072 DQM0 = 95, DQM1 = 90
5947 23:18:40.018176 DQ Delay:
5948 23:18:40.021746 DQ0 =98, DQ1 =90, DQ2 =84, DQ3 =92
5949 23:18:40.024902 DQ4 =98, DQ5 =106, DQ6 =102, DQ7 =90
5950 23:18:40.027994 DQ8 =78, DQ9 =80, DQ10 =92, DQ11 =84
5951 23:18:40.031440 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =96
5952 23:18:40.031546
5953 23:18:40.031636
5954 23:18:40.041488 [DQSOSCAuto] RK1, (LSB)MR18= 0x912, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 419 ps
5955 23:18:40.041609 CH1 RK1: MR19=505, MR18=912
5956 23:18:40.048586 CH1_RK1: MR19=0x505, MR18=0x912, DQSOSC=416, MR23=63, INC=62, DEC=41
5957 23:18:40.051499 [RxdqsGatingPostProcess] freq 933
5958 23:18:40.058264 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5959 23:18:40.061476 best DQS0 dly(2T, 0.5T) = (0, 10)
5960 23:18:40.064738 best DQS1 dly(2T, 0.5T) = (0, 10)
5961 23:18:40.068695 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5962 23:18:40.071526 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5963 23:18:40.071634 best DQS0 dly(2T, 0.5T) = (0, 10)
5964 23:18:40.074782 best DQS1 dly(2T, 0.5T) = (0, 10)
5965 23:18:40.078529 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5966 23:18:40.081791 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5967 23:18:40.085529 Pre-setting of DQS Precalculation
5968 23:18:40.091765 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5969 23:18:40.098479 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5970 23:18:40.104761 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5971 23:18:40.104874
5972 23:18:40.104966
5973 23:18:40.108319 [Calibration Summary] 1866 Mbps
5974 23:18:40.108422 CH 0, Rank 0
5975 23:18:40.111856 SW Impedance : PASS
5976 23:18:40.115167 DUTY Scan : NO K
5977 23:18:40.115270 ZQ Calibration : PASS
5978 23:18:40.118632 Jitter Meter : NO K
5979 23:18:40.121612 CBT Training : PASS
5980 23:18:40.121716 Write leveling : PASS
5981 23:18:40.124582 RX DQS gating : PASS
5982 23:18:40.128589 RX DQ/DQS(RDDQC) : PASS
5983 23:18:40.128695 TX DQ/DQS : PASS
5984 23:18:40.131513 RX DATLAT : PASS
5985 23:18:40.131618 RX DQ/DQS(Engine): PASS
5986 23:18:40.135112 TX OE : NO K
5987 23:18:40.135218 All Pass.
5988 23:18:40.135310
5989 23:18:40.138243 CH 0, Rank 1
5990 23:18:40.138347 SW Impedance : PASS
5991 23:18:40.141775 DUTY Scan : NO K
5992 23:18:40.145267 ZQ Calibration : PASS
5993 23:18:40.145347 Jitter Meter : NO K
5994 23:18:40.148088 CBT Training : PASS
5995 23:18:40.151734 Write leveling : PASS
5996 23:18:40.151813 RX DQS gating : PASS
5997 23:18:40.155182 RX DQ/DQS(RDDQC) : PASS
5998 23:18:40.158346 TX DQ/DQS : PASS
5999 23:18:40.158477 RX DATLAT : PASS
6000 23:18:40.161641 RX DQ/DQS(Engine): PASS
6001 23:18:40.164965 TX OE : NO K
6002 23:18:40.165040 All Pass.
6003 23:18:40.165100
6004 23:18:40.165169 CH 1, Rank 0
6005 23:18:40.168165 SW Impedance : PASS
6006 23:18:40.171411 DUTY Scan : NO K
6007 23:18:40.171487 ZQ Calibration : PASS
6008 23:18:40.175008 Jitter Meter : NO K
6009 23:18:40.177960 CBT Training : PASS
6010 23:18:40.178035 Write leveling : PASS
6011 23:18:40.181576 RX DQS gating : PASS
6012 23:18:40.181645 RX DQ/DQS(RDDQC) : PASS
6013 23:18:40.184970 TX DQ/DQS : PASS
6014 23:18:40.187980 RX DATLAT : PASS
6015 23:18:40.188053 RX DQ/DQS(Engine): PASS
6016 23:18:40.191322 TX OE : NO K
6017 23:18:40.191395 All Pass.
6018 23:18:40.191479
6019 23:18:40.194824 CH 1, Rank 1
6020 23:18:40.194895 SW Impedance : PASS
6021 23:18:40.198102 DUTY Scan : NO K
6022 23:18:40.201527 ZQ Calibration : PASS
6023 23:18:40.201614 Jitter Meter : NO K
6024 23:18:40.204431 CBT Training : PASS
6025 23:18:40.207826 Write leveling : PASS
6026 23:18:40.207904 RX DQS gating : PASS
6027 23:18:40.211204 RX DQ/DQS(RDDQC) : PASS
6028 23:18:40.214681 TX DQ/DQS : PASS
6029 23:18:40.214755 RX DATLAT : PASS
6030 23:18:40.218104 RX DQ/DQS(Engine): PASS
6031 23:18:40.221323 TX OE : NO K
6032 23:18:40.221400 All Pass.
6033 23:18:40.221460
6034 23:18:40.221520 DramC Write-DBI off
6035 23:18:40.224816 PER_BANK_REFRESH: Hybrid Mode
6036 23:18:40.228155 TX_TRACKING: ON
6037 23:18:40.234896 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6038 23:18:40.238539 [FAST_K] Save calibration result to emmc
6039 23:18:40.245055 dramc_set_vcore_voltage set vcore to 650000
6040 23:18:40.245140 Read voltage for 400, 6
6041 23:18:40.245202 Vio18 = 0
6042 23:18:40.248155 Vcore = 650000
6043 23:18:40.248227 Vdram = 0
6044 23:18:40.248285 Vddq = 0
6045 23:18:40.251515 Vmddr = 0
6046 23:18:40.254962 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6047 23:18:40.261456 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6048 23:18:40.261565 MEM_TYPE=3, freq_sel=20
6049 23:18:40.264594 sv_algorithm_assistance_LP4_800
6050 23:18:40.271323 ============ PULL DRAM RESETB DOWN ============
6051 23:18:40.274615 ========== PULL DRAM RESETB DOWN end =========
6052 23:18:40.277961 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6053 23:18:40.281579 ===================================
6054 23:18:40.285022 LPDDR4 DRAM CONFIGURATION
6055 23:18:40.288306 ===================================
6056 23:18:40.291588 EX_ROW_EN[0] = 0x0
6057 23:18:40.291661 EX_ROW_EN[1] = 0x0
6058 23:18:40.294886 LP4Y_EN = 0x0
6059 23:18:40.294959 WORK_FSP = 0x0
6060 23:18:40.298637 WL = 0x2
6061 23:18:40.298705 RL = 0x2
6062 23:18:40.301269 BL = 0x2
6063 23:18:40.301338 RPST = 0x0
6064 23:18:40.304944 RD_PRE = 0x0
6065 23:18:40.305010 WR_PRE = 0x1
6066 23:18:40.308121 WR_PST = 0x0
6067 23:18:40.308189 DBI_WR = 0x0
6068 23:18:40.311841 DBI_RD = 0x0
6069 23:18:40.311914 OTF = 0x1
6070 23:18:40.314946 ===================================
6071 23:18:40.318286 ===================================
6072 23:18:40.321679 ANA top config
6073 23:18:40.324770 ===================================
6074 23:18:40.324838 DLL_ASYNC_EN = 0
6075 23:18:40.327946 ALL_SLAVE_EN = 1
6076 23:18:40.331374 NEW_RANK_MODE = 1
6077 23:18:40.334585 DLL_IDLE_MODE = 1
6078 23:18:40.338509 LP45_APHY_COMB_EN = 1
6079 23:18:40.338583 TX_ODT_DIS = 1
6080 23:18:40.341283 NEW_8X_MODE = 1
6081 23:18:40.345061 ===================================
6082 23:18:40.348112 ===================================
6083 23:18:40.351183 data_rate = 800
6084 23:18:40.354909 CKR = 1
6085 23:18:40.358195 DQ_P2S_RATIO = 4
6086 23:18:40.361627 ===================================
6087 23:18:40.361703 CA_P2S_RATIO = 4
6088 23:18:40.364675 DQ_CA_OPEN = 0
6089 23:18:40.368266 DQ_SEMI_OPEN = 1
6090 23:18:40.371575 CA_SEMI_OPEN = 1
6091 23:18:40.374952 CA_FULL_RATE = 0
6092 23:18:40.377939 DQ_CKDIV4_EN = 0
6093 23:18:40.378007 CA_CKDIV4_EN = 1
6094 23:18:40.381298 CA_PREDIV_EN = 0
6095 23:18:40.385046 PH8_DLY = 0
6096 23:18:40.388187 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6097 23:18:40.391190 DQ_AAMCK_DIV = 0
6098 23:18:40.394731 CA_AAMCK_DIV = 0
6099 23:18:40.394799 CA_ADMCK_DIV = 4
6100 23:18:40.398016 DQ_TRACK_CA_EN = 0
6101 23:18:40.401737 CA_PICK = 800
6102 23:18:40.404939 CA_MCKIO = 400
6103 23:18:40.408103 MCKIO_SEMI = 400
6104 23:18:40.411198 PLL_FREQ = 3016
6105 23:18:40.414584 DQ_UI_PI_RATIO = 32
6106 23:18:40.414661 CA_UI_PI_RATIO = 32
6107 23:18:40.418229 ===================================
6108 23:18:40.421266 ===================================
6109 23:18:40.424411 memory_type:LPDDR4
6110 23:18:40.428427 GP_NUM : 10
6111 23:18:40.428494 SRAM_EN : 1
6112 23:18:40.431333 MD32_EN : 0
6113 23:18:40.434557 ===================================
6114 23:18:40.437921 [ANA_INIT] >>>>>>>>>>>>>>
6115 23:18:40.441164 <<<<<< [CONFIGURE PHASE]: ANA_TX
6116 23:18:40.444868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6117 23:18:40.447928 ===================================
6118 23:18:40.448039 data_rate = 800,PCW = 0X7400
6119 23:18:40.451518 ===================================
6120 23:18:40.454856 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6121 23:18:40.461242 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6122 23:18:40.471461 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6123 23:18:40.478313 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6124 23:18:40.481477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6125 23:18:40.484972 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6126 23:18:40.488219 [ANA_INIT] flow start
6127 23:18:40.488295 [ANA_INIT] PLL >>>>>>>>
6128 23:18:40.491424 [ANA_INIT] PLL <<<<<<<<
6129 23:18:40.495080 [ANA_INIT] MIDPI >>>>>>>>
6130 23:18:40.495154 [ANA_INIT] MIDPI <<<<<<<<
6131 23:18:40.498173 [ANA_INIT] DLL >>>>>>>>
6132 23:18:40.501512 [ANA_INIT] flow end
6133 23:18:40.504733 ============ LP4 DIFF to SE enter ============
6134 23:18:40.508001 ============ LP4 DIFF to SE exit ============
6135 23:18:40.511488 [ANA_INIT] <<<<<<<<<<<<<
6136 23:18:40.514825 [Flow] Enable top DCM control >>>>>
6137 23:18:40.517965 [Flow] Enable top DCM control <<<<<
6138 23:18:40.521584 Enable DLL master slave shuffle
6139 23:18:40.524533 ==============================================================
6140 23:18:40.527806 Gating Mode config
6141 23:18:40.531067 ==============================================================
6142 23:18:40.534459 Config description:
6143 23:18:40.544939 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6144 23:18:40.551292 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6145 23:18:40.554811 SELPH_MODE 0: By rank 1: By Phase
6146 23:18:40.561354 ==============================================================
6147 23:18:40.564636 GAT_TRACK_EN = 0
6148 23:18:40.568011 RX_GATING_MODE = 2
6149 23:18:40.571308 RX_GATING_TRACK_MODE = 2
6150 23:18:40.574739 SELPH_MODE = 1
6151 23:18:40.577886 PICG_EARLY_EN = 1
6152 23:18:40.577991 VALID_LAT_VALUE = 1
6153 23:18:40.584615 ==============================================================
6154 23:18:40.588215 Enter into Gating configuration >>>>
6155 23:18:40.591282 Exit from Gating configuration <<<<
6156 23:18:40.594915 Enter into DVFS_PRE_config >>>>>
6157 23:18:40.604607 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6158 23:18:40.607824 Exit from DVFS_PRE_config <<<<<
6159 23:18:40.611358 Enter into PICG configuration >>>>
6160 23:18:40.614712 Exit from PICG configuration <<<<
6161 23:18:40.618048 [RX_INPUT] configuration >>>>>
6162 23:18:40.621261 [RX_INPUT] configuration <<<<<
6163 23:18:40.624646 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6164 23:18:40.631607 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6165 23:18:40.638489 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6166 23:18:40.645280 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6167 23:18:40.651653 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6168 23:18:40.654673 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6169 23:18:40.661547 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6170 23:18:40.664997 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6171 23:18:40.667919 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6172 23:18:40.671129 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6173 23:18:40.677783 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6174 23:18:40.681057 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6175 23:18:40.684749 ===================================
6176 23:18:40.687771 LPDDR4 DRAM CONFIGURATION
6177 23:18:40.690878 ===================================
6178 23:18:40.690983 EX_ROW_EN[0] = 0x0
6179 23:18:40.694588 EX_ROW_EN[1] = 0x0
6180 23:18:40.694692 LP4Y_EN = 0x0
6181 23:18:40.697759 WORK_FSP = 0x0
6182 23:18:40.697862 WL = 0x2
6183 23:18:40.700935 RL = 0x2
6184 23:18:40.701038 BL = 0x2
6185 23:18:40.704572 RPST = 0x0
6186 23:18:40.704676 RD_PRE = 0x0
6187 23:18:40.707746 WR_PRE = 0x1
6188 23:18:40.707851 WR_PST = 0x0
6189 23:18:40.710977 DBI_WR = 0x0
6190 23:18:40.714382 DBI_RD = 0x0
6191 23:18:40.714525 OTF = 0x1
6192 23:18:40.717760 ===================================
6193 23:18:40.721083 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6194 23:18:40.724385 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6195 23:18:40.731092 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6196 23:18:40.734367 ===================================
6197 23:18:40.734508 LPDDR4 DRAM CONFIGURATION
6198 23:18:40.737834 ===================================
6199 23:18:40.741570 EX_ROW_EN[0] = 0x10
6200 23:18:40.744736 EX_ROW_EN[1] = 0x0
6201 23:18:40.744841 LP4Y_EN = 0x0
6202 23:18:40.747526 WORK_FSP = 0x0
6203 23:18:40.747630 WL = 0x2
6204 23:18:40.750924 RL = 0x2
6205 23:18:40.751030 BL = 0x2
6206 23:18:40.754237 RPST = 0x0
6207 23:18:40.754340 RD_PRE = 0x0
6208 23:18:40.757735 WR_PRE = 0x1
6209 23:18:40.757840 WR_PST = 0x0
6210 23:18:40.760670 DBI_WR = 0x0
6211 23:18:40.760772 DBI_RD = 0x0
6212 23:18:40.764075 OTF = 0x1
6213 23:18:40.767355 ===================================
6214 23:18:40.774410 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6215 23:18:40.777517 nWR fixed to 30
6216 23:18:40.781368 [ModeRegInit_LP4] CH0 RK0
6217 23:18:40.781474 [ModeRegInit_LP4] CH0 RK1
6218 23:18:40.784748 [ModeRegInit_LP4] CH1 RK0
6219 23:18:40.787487 [ModeRegInit_LP4] CH1 RK1
6220 23:18:40.787592 match AC timing 19
6221 23:18:40.794550 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6222 23:18:40.797730 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6223 23:18:40.800937 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6224 23:18:40.808133 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6225 23:18:40.811093 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6226 23:18:40.811201 ==
6227 23:18:40.813984 Dram Type= 6, Freq= 0, CH_0, rank 0
6228 23:18:40.817935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6229 23:18:40.818041 ==
6230 23:18:40.824496 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6231 23:18:40.831078 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6232 23:18:40.834631 [CA 0] Center 36 (8~64) winsize 57
6233 23:18:40.834736 [CA 1] Center 36 (8~64) winsize 57
6234 23:18:40.837950 [CA 2] Center 36 (8~64) winsize 57
6235 23:18:40.841029 [CA 3] Center 36 (8~64) winsize 57
6236 23:18:40.844326 [CA 4] Center 36 (8~64) winsize 57
6237 23:18:40.847511 [CA 5] Center 36 (8~64) winsize 57
6238 23:18:40.847592
6239 23:18:40.850794 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6240 23:18:40.850876
6241 23:18:40.854156 [CATrainingPosCal] consider 1 rank data
6242 23:18:40.857523 u2DelayCellTimex100 = 270/100 ps
6243 23:18:40.860804 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 23:18:40.864473 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 23:18:40.871186 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 23:18:40.874499 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 23:18:40.877691 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 23:18:40.881303 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 23:18:40.881408
6250 23:18:40.884425 CA PerBit enable=1, Macro0, CA PI delay=36
6251 23:18:40.884530
6252 23:18:40.888050 [CBTSetCACLKResult] CA Dly = 36
6253 23:18:40.888153 CS Dly: 1 (0~32)
6254 23:18:40.888281 ==
6255 23:18:40.891202 Dram Type= 6, Freq= 0, CH_0, rank 1
6256 23:18:40.897850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 23:18:40.897959 ==
6258 23:18:40.901321 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6259 23:18:40.907582 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6260 23:18:40.911505 [CA 0] Center 36 (8~64) winsize 57
6261 23:18:40.914837 [CA 1] Center 36 (8~64) winsize 57
6262 23:18:40.918036 [CA 2] Center 36 (8~64) winsize 57
6263 23:18:40.921359 [CA 3] Center 36 (8~64) winsize 57
6264 23:18:40.924423 [CA 4] Center 36 (8~64) winsize 57
6265 23:18:40.928294 [CA 5] Center 36 (8~64) winsize 57
6266 23:18:40.928399
6267 23:18:40.931425 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6268 23:18:40.931530
6269 23:18:40.934572 [CATrainingPosCal] consider 2 rank data
6270 23:18:40.938097 u2DelayCellTimex100 = 270/100 ps
6271 23:18:40.941097 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 23:18:40.945126 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 23:18:40.947856 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 23:18:40.951501 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 23:18:40.954556 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 23:18:40.957757 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 23:18:40.957861
6278 23:18:40.964651 CA PerBit enable=1, Macro0, CA PI delay=36
6279 23:18:40.964762
6280 23:18:40.964854 [CBTSetCACLKResult] CA Dly = 36
6281 23:18:40.967765 CS Dly: 1 (0~32)
6282 23:18:40.967873
6283 23:18:40.971038 ----->DramcWriteLeveling(PI) begin...
6284 23:18:40.971146 ==
6285 23:18:40.974365 Dram Type= 6, Freq= 0, CH_0, rank 0
6286 23:18:40.978172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 23:18:40.978278 ==
6288 23:18:40.981245 Write leveling (Byte 0): 40 => 8
6289 23:18:40.984853 Write leveling (Byte 1): 32 => 0
6290 23:18:40.987863 DramcWriteLeveling(PI) end<-----
6291 23:18:40.987966
6292 23:18:40.988055 ==
6293 23:18:40.991127 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 23:18:40.994532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 23:18:40.994640 ==
6296 23:18:40.997776 [Gating] SW mode calibration
6297 23:18:41.004498 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6298 23:18:41.011279 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6299 23:18:41.014584 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6300 23:18:41.021545 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6301 23:18:41.024730 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6302 23:18:41.027817 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6303 23:18:41.034654 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 23:18:41.037588 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 23:18:41.041610 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 23:18:41.044508 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6307 23:18:41.051295 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6308 23:18:41.055026 Total UI for P1: 0, mck2ui 16
6309 23:18:41.058230 best dqsien dly found for B0: ( 0, 14, 24)
6310 23:18:41.058336 Total UI for P1: 0, mck2ui 16
6311 23:18:41.065133 best dqsien dly found for B1: ( 0, 14, 24)
6312 23:18:41.067987 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6313 23:18:41.071931 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6314 23:18:41.072006
6315 23:18:41.074930 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6316 23:18:41.078479 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6317 23:18:41.081471 [Gating] SW calibration Done
6318 23:18:41.081550 ==
6319 23:18:41.084841 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 23:18:41.087908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 23:18:41.087991 ==
6322 23:18:41.091501 RX Vref Scan: 0
6323 23:18:41.091580
6324 23:18:41.091644 RX Vref 0 -> 0, step: 1
6325 23:18:41.091701
6326 23:18:41.094644 RX Delay -410 -> 252, step: 16
6327 23:18:41.101639 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6328 23:18:41.104600 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6329 23:18:41.107995 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6330 23:18:41.111404 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6331 23:18:41.118257 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6332 23:18:41.121489 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6333 23:18:41.124776 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6334 23:18:41.128008 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6335 23:18:41.134779 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6336 23:18:41.138182 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6337 23:18:41.141499 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6338 23:18:41.144728 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6339 23:18:41.151645 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6340 23:18:41.154808 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6341 23:18:41.158494 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6342 23:18:41.161705 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6343 23:18:41.165158 ==
6344 23:18:41.165263 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 23:18:41.171693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 23:18:41.171804 ==
6347 23:18:41.171897 DQS Delay:
6348 23:18:41.175153 DQS0 = 35, DQS1 = 51
6349 23:18:41.175259 DQM Delay:
6350 23:18:41.178427 DQM0 = 8, DQM1 = 10
6351 23:18:41.178544 DQ Delay:
6352 23:18:41.181958 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6353 23:18:41.184944 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6354 23:18:41.185048 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6355 23:18:41.188088 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6356 23:18:41.191472
6357 23:18:41.191576
6358 23:18:41.191668 ==
6359 23:18:41.194811 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 23:18:41.198343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 23:18:41.198528 ==
6362 23:18:41.198620
6363 23:18:41.198705
6364 23:18:41.202127 TX Vref Scan disable
6365 23:18:41.202232 == TX Byte 0 ==
6366 23:18:41.205182 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 23:18:41.211675 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 23:18:41.211785 == TX Byte 1 ==
6369 23:18:41.215065 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6370 23:18:41.221497 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6371 23:18:41.221605 ==
6372 23:18:41.224690 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 23:18:41.228310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 23:18:41.228417 ==
6375 23:18:41.228508
6376 23:18:41.228596
6377 23:18:41.231767 TX Vref Scan disable
6378 23:18:41.231876 == TX Byte 0 ==
6379 23:18:41.238034 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6380 23:18:41.241394 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6381 23:18:41.241501 == TX Byte 1 ==
6382 23:18:41.244815 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6383 23:18:41.251443 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6384 23:18:41.251568
6385 23:18:41.251661 [DATLAT]
6386 23:18:41.254923 Freq=400, CH0 RK0
6387 23:18:41.255032
6388 23:18:41.255124 DATLAT Default: 0xf
6389 23:18:41.258489 0, 0xFFFF, sum = 0
6390 23:18:41.258595 1, 0xFFFF, sum = 0
6391 23:18:41.261609 2, 0xFFFF, sum = 0
6392 23:18:41.261721 3, 0xFFFF, sum = 0
6393 23:18:41.264880 4, 0xFFFF, sum = 0
6394 23:18:41.264988 5, 0xFFFF, sum = 0
6395 23:18:41.268124 6, 0xFFFF, sum = 0
6396 23:18:41.268232 7, 0xFFFF, sum = 0
6397 23:18:41.271666 8, 0xFFFF, sum = 0
6398 23:18:41.271772 9, 0xFFFF, sum = 0
6399 23:18:41.274827 10, 0xFFFF, sum = 0
6400 23:18:41.274936 11, 0xFFFF, sum = 0
6401 23:18:41.278195 12, 0xFFFF, sum = 0
6402 23:18:41.278285 13, 0x0, sum = 1
6403 23:18:41.282128 14, 0x0, sum = 2
6404 23:18:41.282209 15, 0x0, sum = 3
6405 23:18:41.285045 16, 0x0, sum = 4
6406 23:18:41.285119 best_step = 14
6407 23:18:41.285179
6408 23:18:41.285236 ==
6409 23:18:41.288391 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 23:18:41.294884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 23:18:41.294971 ==
6412 23:18:41.295036 RX Vref Scan: 1
6413 23:18:41.295093
6414 23:18:41.298240 RX Vref 0 -> 0, step: 1
6415 23:18:41.298312
6416 23:18:41.301955 RX Delay -343 -> 252, step: 8
6417 23:18:41.302030
6418 23:18:41.305309 Set Vref, RX VrefLevel [Byte0]: 58
6419 23:18:41.308544 [Byte1]: 51
6420 23:18:41.308616
6421 23:18:41.311619 Final RX Vref Byte 0 = 58 to rank0
6422 23:18:41.315310 Final RX Vref Byte 1 = 51 to rank0
6423 23:18:41.318138 Final RX Vref Byte 0 = 58 to rank1
6424 23:18:41.321525 Final RX Vref Byte 1 = 51 to rank1==
6425 23:18:41.325403 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 23:18:41.328142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 23:18:41.328217 ==
6428 23:18:41.331889 DQS Delay:
6429 23:18:41.331961 DQS0 = 44, DQS1 = 60
6430 23:18:41.334826 DQM Delay:
6431 23:18:41.334901 DQM0 = 11, DQM1 = 14
6432 23:18:41.334960 DQ Delay:
6433 23:18:41.338580 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6434 23:18:41.341585 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6435 23:18:41.344837 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =12
6436 23:18:41.348339 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6437 23:18:41.348417
6438 23:18:41.348477
6439 23:18:41.358489 [DQSOSCAuto] RK0, (LSB)MR18= 0x7e4d, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
6440 23:18:41.361733 CH0 RK0: MR19=C0C, MR18=7E4D
6441 23:18:41.364915 CH0_RK0: MR19=0xC0C, MR18=0x7E4D, DQSOSC=393, MR23=63, INC=382, DEC=254
6442 23:18:41.368379 ==
6443 23:18:41.371910 Dram Type= 6, Freq= 0, CH_0, rank 1
6444 23:18:41.375193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 23:18:41.375267 ==
6446 23:18:41.378489 [Gating] SW mode calibration
6447 23:18:41.385122 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6448 23:18:41.388162 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6449 23:18:41.395055 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6450 23:18:41.398233 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6451 23:18:41.401380 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6452 23:18:41.408425 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6453 23:18:41.411989 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 23:18:41.415355 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 23:18:41.421843 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 23:18:41.424674 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 23:18:41.428720 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6458 23:18:41.431357 Total UI for P1: 0, mck2ui 16
6459 23:18:41.435068 best dqsien dly found for B0: ( 0, 14, 24)
6460 23:18:41.438351 Total UI for P1: 0, mck2ui 16
6461 23:18:41.441266 best dqsien dly found for B1: ( 0, 14, 24)
6462 23:18:41.444768 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6463 23:18:41.448046 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6464 23:18:41.448159
6465 23:18:41.451637 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6466 23:18:41.458265 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6467 23:18:41.458348 [Gating] SW calibration Done
6468 23:18:41.458454 ==
6469 23:18:41.461506 Dram Type= 6, Freq= 0, CH_0, rank 1
6470 23:18:41.468192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 23:18:41.468275 ==
6472 23:18:41.468343 RX Vref Scan: 0
6473 23:18:41.468403
6474 23:18:41.471824 RX Vref 0 -> 0, step: 1
6475 23:18:41.471898
6476 23:18:41.474845 RX Delay -410 -> 252, step: 16
6477 23:18:41.478488 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6478 23:18:41.482104 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6479 23:18:41.487990 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6480 23:18:41.491318 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6481 23:18:41.494931 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6482 23:18:41.498277 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6483 23:18:41.504861 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6484 23:18:41.508120 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6485 23:18:41.511808 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6486 23:18:41.515107 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6487 23:18:41.521437 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6488 23:18:41.524651 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6489 23:18:41.528164 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6490 23:18:41.531430 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6491 23:18:41.538186 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6492 23:18:41.541719 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6493 23:18:41.541804 ==
6494 23:18:41.545200 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 23:18:41.548060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 23:18:41.548138 ==
6497 23:18:41.551217 DQS Delay:
6498 23:18:41.551299 DQS0 = 43, DQS1 = 51
6499 23:18:41.551361 DQM Delay:
6500 23:18:41.554986 DQM0 = 11, DQM1 = 10
6501 23:18:41.555081 DQ Delay:
6502 23:18:41.558344 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6503 23:18:41.561634 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6504 23:18:41.564930 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6505 23:18:41.568148 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6506 23:18:41.568224
6507 23:18:41.568286
6508 23:18:41.568348 ==
6509 23:18:41.571592 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 23:18:41.574575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 23:18:41.578945 ==
6512 23:18:41.579052
6513 23:18:41.579143
6514 23:18:41.579230 TX Vref Scan disable
6515 23:18:41.581428 == TX Byte 0 ==
6516 23:18:41.585373 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6517 23:18:41.587967 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6518 23:18:41.591536 == TX Byte 1 ==
6519 23:18:41.595164 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6520 23:18:41.597982 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6521 23:18:41.598085 ==
6522 23:18:41.601421 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 23:18:41.604847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 23:18:41.608012 ==
6525 23:18:41.608114
6526 23:18:41.608204
6527 23:18:41.608292 TX Vref Scan disable
6528 23:18:41.611379 == TX Byte 0 ==
6529 23:18:41.614944 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6530 23:18:41.618320 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6531 23:18:41.621539 == TX Byte 1 ==
6532 23:18:41.624740 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6533 23:18:41.628390 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6534 23:18:41.628495
6535 23:18:41.628585 [DATLAT]
6536 23:18:41.631887 Freq=400, CH0 RK1
6537 23:18:41.631994
6538 23:18:41.632087 DATLAT Default: 0xe
6539 23:18:41.634943 0, 0xFFFF, sum = 0
6540 23:18:41.638448 1, 0xFFFF, sum = 0
6541 23:18:41.638553 2, 0xFFFF, sum = 0
6542 23:18:41.641865 3, 0xFFFF, sum = 0
6543 23:18:41.641968 4, 0xFFFF, sum = 0
6544 23:18:41.645082 5, 0xFFFF, sum = 0
6545 23:18:41.645187 6, 0xFFFF, sum = 0
6546 23:18:41.648579 7, 0xFFFF, sum = 0
6547 23:18:41.648686 8, 0xFFFF, sum = 0
6548 23:18:41.651779 9, 0xFFFF, sum = 0
6549 23:18:41.651888 10, 0xFFFF, sum = 0
6550 23:18:41.655013 11, 0xFFFF, sum = 0
6551 23:18:41.655120 12, 0xFFFF, sum = 0
6552 23:18:41.658451 13, 0x0, sum = 1
6553 23:18:41.658556 14, 0x0, sum = 2
6554 23:18:41.661926 15, 0x0, sum = 3
6555 23:18:41.662031 16, 0x0, sum = 4
6556 23:18:41.664782 best_step = 14
6557 23:18:41.664886
6558 23:18:41.664977 ==
6559 23:18:41.668160 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 23:18:41.671323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 23:18:41.671434 ==
6562 23:18:41.671527 RX Vref Scan: 0
6563 23:18:41.671615
6564 23:18:41.674641 RX Vref 0 -> 0, step: 1
6565 23:18:41.674745
6566 23:18:41.678099 RX Delay -343 -> 252, step: 8
6567 23:18:41.686103 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6568 23:18:41.688942 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6569 23:18:41.691912 iDelay=217, Bit 2, Center -36 (-279 ~ 208) 488
6570 23:18:41.695184 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6571 23:18:41.702143 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6572 23:18:41.705391 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6573 23:18:41.708764 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6574 23:18:41.712223 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6575 23:18:41.718526 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6576 23:18:41.721999 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6577 23:18:41.725568 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6578 23:18:41.728714 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6579 23:18:41.735907 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6580 23:18:41.738907 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6581 23:18:41.742081 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6582 23:18:41.745347 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6583 23:18:41.749002 ==
6584 23:18:41.752424 Dram Type= 6, Freq= 0, CH_0, rank 1
6585 23:18:41.755573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 23:18:41.755680 ==
6587 23:18:41.755771 DQS Delay:
6588 23:18:41.758710 DQS0 = 48, DQS1 = 60
6589 23:18:41.758814 DQM Delay:
6590 23:18:41.762337 DQM0 = 12, DQM1 = 13
6591 23:18:41.762478 DQ Delay:
6592 23:18:41.765484 DQ0 =12, DQ1 =12, DQ2 =12, DQ3 =12
6593 23:18:41.768659 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6594 23:18:41.772305 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6595 23:18:41.775266 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6596 23:18:41.775369
6597 23:18:41.775459
6598 23:18:41.782003 [DQSOSCAuto] RK1, (LSB)MR18= 0x9769, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6599 23:18:41.785310 CH0 RK1: MR19=C0C, MR18=9769
6600 23:18:41.791876 CH0_RK1: MR19=0xC0C, MR18=0x9769, DQSOSC=390, MR23=63, INC=388, DEC=258
6601 23:18:41.795322 [RxdqsGatingPostProcess] freq 400
6602 23:18:41.802340 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6603 23:18:41.802487 best DQS0 dly(2T, 0.5T) = (0, 10)
6604 23:18:41.805159 best DQS1 dly(2T, 0.5T) = (0, 10)
6605 23:18:41.808483 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6606 23:18:41.811806 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6607 23:18:41.815767 best DQS0 dly(2T, 0.5T) = (0, 10)
6608 23:18:41.818985 best DQS1 dly(2T, 0.5T) = (0, 10)
6609 23:18:41.822137 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6610 23:18:41.825431 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6611 23:18:41.828771 Pre-setting of DQS Precalculation
6612 23:18:41.832100 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6613 23:18:41.835141 ==
6614 23:18:41.838589 Dram Type= 6, Freq= 0, CH_1, rank 0
6615 23:18:41.841856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 23:18:41.841960 ==
6617 23:18:41.845518 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6618 23:18:41.851908 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6619 23:18:41.855160 [CA 0] Center 36 (8~64) winsize 57
6620 23:18:41.858849 [CA 1] Center 36 (8~64) winsize 57
6621 23:18:41.861783 [CA 2] Center 36 (8~64) winsize 57
6622 23:18:41.865078 [CA 3] Center 36 (8~64) winsize 57
6623 23:18:41.868637 [CA 4] Center 36 (8~64) winsize 57
6624 23:18:41.872194 [CA 5] Center 36 (8~64) winsize 57
6625 23:18:41.872300
6626 23:18:41.875725 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6627 23:18:41.875830
6628 23:18:41.878896 [CATrainingPosCal] consider 1 rank data
6629 23:18:41.881879 u2DelayCellTimex100 = 270/100 ps
6630 23:18:41.885456 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 23:18:41.888532 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 23:18:41.892208 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 23:18:41.895400 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 23:18:41.898501 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 23:18:41.905586 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 23:18:41.905696
6637 23:18:41.908786 CA PerBit enable=1, Macro0, CA PI delay=36
6638 23:18:41.908892
6639 23:18:41.911880 [CBTSetCACLKResult] CA Dly = 36
6640 23:18:41.911985 CS Dly: 1 (0~32)
6641 23:18:41.912075 ==
6642 23:18:41.915643 Dram Type= 6, Freq= 0, CH_1, rank 1
6643 23:18:41.918510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 23:18:41.918614 ==
6645 23:18:41.925615 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6646 23:18:41.932281 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6647 23:18:41.935197 [CA 0] Center 36 (8~64) winsize 57
6648 23:18:41.938776 [CA 1] Center 36 (8~64) winsize 57
6649 23:18:41.942115 [CA 2] Center 36 (8~64) winsize 57
6650 23:18:41.945576 [CA 3] Center 36 (8~64) winsize 57
6651 23:18:41.948822 [CA 4] Center 36 (8~64) winsize 57
6652 23:18:41.948943 [CA 5] Center 36 (8~64) winsize 57
6653 23:18:41.951730
6654 23:18:41.955358 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6655 23:18:41.955462
6656 23:18:41.958687 [CATrainingPosCal] consider 2 rank data
6657 23:18:41.962039 u2DelayCellTimex100 = 270/100 ps
6658 23:18:41.965467 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 23:18:41.968462 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 23:18:41.972091 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 23:18:41.975457 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 23:18:41.978618 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 23:18:41.982235 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 23:18:41.982340
6665 23:18:41.985217 CA PerBit enable=1, Macro0, CA PI delay=36
6666 23:18:41.985322
6667 23:18:41.988751 [CBTSetCACLKResult] CA Dly = 36
6668 23:18:41.992106 CS Dly: 1 (0~32)
6669 23:18:41.992211
6670 23:18:41.995163 ----->DramcWriteLeveling(PI) begin...
6671 23:18:41.995267 ==
6672 23:18:41.998982 Dram Type= 6, Freq= 0, CH_1, rank 0
6673 23:18:42.002470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 23:18:42.002575 ==
6675 23:18:42.005818 Write leveling (Byte 0): 40 => 8
6676 23:18:42.009418 Write leveling (Byte 1): 40 => 8
6677 23:18:42.011892 DramcWriteLeveling(PI) end<-----
6678 23:18:42.011997
6679 23:18:42.012088 ==
6680 23:18:42.015734 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 23:18:42.018707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 23:18:42.018812 ==
6683 23:18:42.022182 [Gating] SW mode calibration
6684 23:18:42.029273 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6685 23:18:42.035520 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6686 23:18:42.038671 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6687 23:18:42.042474 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6688 23:18:42.048731 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6689 23:18:42.052311 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6690 23:18:42.055529 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 23:18:42.062431 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 23:18:42.065763 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 23:18:42.069035 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6694 23:18:42.075386 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6695 23:18:42.075497 Total UI for P1: 0, mck2ui 16
6696 23:18:42.078704 best dqsien dly found for B0: ( 0, 14, 24)
6697 23:18:42.082333 Total UI for P1: 0, mck2ui 16
6698 23:18:42.085408 best dqsien dly found for B1: ( 0, 14, 24)
6699 23:18:42.088699 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6700 23:18:42.095567 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6701 23:18:42.095679
6702 23:18:42.098776 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6703 23:18:42.102313 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6704 23:18:42.105501 [Gating] SW calibration Done
6705 23:18:42.105609 ==
6706 23:18:42.108655 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 23:18:42.112039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 23:18:42.112146 ==
6709 23:18:42.115398 RX Vref Scan: 0
6710 23:18:42.115501
6711 23:18:42.115590 RX Vref 0 -> 0, step: 1
6712 23:18:42.115679
6713 23:18:42.119267 RX Delay -410 -> 252, step: 16
6714 23:18:42.121901 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6715 23:18:42.128727 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6716 23:18:42.131762 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6717 23:18:42.135819 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6718 23:18:42.138735 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6719 23:18:42.145417 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6720 23:18:42.148578 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6721 23:18:42.152156 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6722 23:18:42.155404 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6723 23:18:42.162495 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6724 23:18:42.165449 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6725 23:18:42.168673 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6726 23:18:42.172257 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6727 23:18:42.178708 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6728 23:18:42.182129 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6729 23:18:42.185731 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6730 23:18:42.185835 ==
6731 23:18:42.188751 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 23:18:42.192209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 23:18:42.195300 ==
6734 23:18:42.195404 DQS Delay:
6735 23:18:42.195494 DQS0 = 51, DQS1 = 59
6736 23:18:42.198813 DQM Delay:
6737 23:18:42.198915 DQM0 = 19, DQM1 = 16
6738 23:18:42.202596 DQ Delay:
6739 23:18:42.206031 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6740 23:18:42.206136 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6741 23:18:42.208710 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6742 23:18:42.212260 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6743 23:18:42.212364
6744 23:18:42.212454
6745 23:18:42.215991 ==
6746 23:18:42.219029 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 23:18:42.222693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 23:18:42.222799 ==
6749 23:18:42.222890
6750 23:18:42.222978
6751 23:18:42.225633 TX Vref Scan disable
6752 23:18:42.225736 == TX Byte 0 ==
6753 23:18:42.229370 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 23:18:42.236884 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 23:18:42.236999 == TX Byte 1 ==
6756 23:18:42.239084 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6757 23:18:42.242263 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6758 23:18:42.245829 ==
6759 23:18:42.248789 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 23:18:42.252234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 23:18:42.252343 ==
6762 23:18:42.252433
6763 23:18:42.252520
6764 23:18:42.255708 TX Vref Scan disable
6765 23:18:42.255813 == TX Byte 0 ==
6766 23:18:42.259017 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6767 23:18:42.265695 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6768 23:18:42.265801 == TX Byte 1 ==
6769 23:18:42.268959 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6770 23:18:42.275748 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6771 23:18:42.275858
6772 23:18:42.275951 [DATLAT]
6773 23:18:42.276038 Freq=400, CH1 RK0
6774 23:18:42.276125
6775 23:18:42.278892 DATLAT Default: 0xf
6776 23:18:42.282379 0, 0xFFFF, sum = 0
6777 23:18:42.282491 1, 0xFFFF, sum = 0
6778 23:18:42.285467 2, 0xFFFF, sum = 0
6779 23:18:42.285570 3, 0xFFFF, sum = 0
6780 23:18:42.288532 4, 0xFFFF, sum = 0
6781 23:18:42.288636 5, 0xFFFF, sum = 0
6782 23:18:42.292128 6, 0xFFFF, sum = 0
6783 23:18:42.292233 7, 0xFFFF, sum = 0
6784 23:18:42.295535 8, 0xFFFF, sum = 0
6785 23:18:42.295640 9, 0xFFFF, sum = 0
6786 23:18:42.298586 10, 0xFFFF, sum = 0
6787 23:18:42.298690 11, 0xFFFF, sum = 0
6788 23:18:42.301835 12, 0xFFFF, sum = 0
6789 23:18:42.301940 13, 0x0, sum = 1
6790 23:18:42.305465 14, 0x0, sum = 2
6791 23:18:42.305570 15, 0x0, sum = 3
6792 23:18:42.308660 16, 0x0, sum = 4
6793 23:18:42.308766 best_step = 14
6794 23:18:42.308855
6795 23:18:42.308941 ==
6796 23:18:42.311835 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 23:18:42.315271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 23:18:42.318305 ==
6799 23:18:42.318430 RX Vref Scan: 1
6800 23:18:42.318571
6801 23:18:42.321840 RX Vref 0 -> 0, step: 1
6802 23:18:42.321942
6803 23:18:42.325242 RX Delay -359 -> 252, step: 8
6804 23:18:42.325346
6805 23:18:42.328553 Set Vref, RX VrefLevel [Byte0]: 57
6806 23:18:42.331838 [Byte1]: 46
6807 23:18:42.331942
6808 23:18:42.335069 Final RX Vref Byte 0 = 57 to rank0
6809 23:18:42.338434 Final RX Vref Byte 1 = 46 to rank0
6810 23:18:42.342054 Final RX Vref Byte 0 = 57 to rank1
6811 23:18:42.344774 Final RX Vref Byte 1 = 46 to rank1==
6812 23:18:42.348290 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 23:18:42.351717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 23:18:42.354732 ==
6815 23:18:42.354843 DQS Delay:
6816 23:18:42.354935 DQS0 = 48, DQS1 = 60
6817 23:18:42.358247 DQM Delay:
6818 23:18:42.358350 DQM0 = 11, DQM1 = 11
6819 23:18:42.361750 DQ Delay:
6820 23:18:42.361854 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6821 23:18:42.364832 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6822 23:18:42.368295 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6823 23:18:42.371834 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =16
6824 23:18:42.371943
6825 23:18:42.372034
6826 23:18:42.382210 [DQSOSCAuto] RK0, (LSB)MR18= 0x8932, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6827 23:18:42.385160 CH1 RK0: MR19=C0C, MR18=8932
6828 23:18:42.388138 CH1_RK0: MR19=0xC0C, MR18=0x8932, DQSOSC=392, MR23=63, INC=384, DEC=256
6829 23:18:42.391503 ==
6830 23:18:42.394780 Dram Type= 6, Freq= 0, CH_1, rank 1
6831 23:18:42.398167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 23:18:42.398251 ==
6833 23:18:42.401990 [Gating] SW mode calibration
6834 23:18:42.408180 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6835 23:18:42.411422 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6836 23:18:42.418384 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6837 23:18:42.421452 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6838 23:18:42.424730 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6839 23:18:42.431518 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6840 23:18:42.434767 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 23:18:42.438347 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 23:18:42.444900 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 23:18:42.448069 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6844 23:18:42.451713 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6845 23:18:42.455320 Total UI for P1: 0, mck2ui 16
6846 23:18:42.458530 best dqsien dly found for B0: ( 0, 14, 24)
6847 23:18:42.461374 Total UI for P1: 0, mck2ui 16
6848 23:18:42.464878 best dqsien dly found for B1: ( 0, 14, 24)
6849 23:18:42.468479 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6850 23:18:42.471372 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6851 23:18:42.471461
6852 23:18:42.474967 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6853 23:18:42.481640 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6854 23:18:42.481731 [Gating] SW calibration Done
6855 23:18:42.481818 ==
6856 23:18:42.484956 Dram Type= 6, Freq= 0, CH_1, rank 1
6857 23:18:42.491509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 23:18:42.491598 ==
6859 23:18:42.491682 RX Vref Scan: 0
6860 23:18:42.491763
6861 23:18:42.494977 RX Vref 0 -> 0, step: 1
6862 23:18:42.495060
6863 23:18:42.498112 RX Delay -410 -> 252, step: 16
6864 23:18:42.501784 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6865 23:18:42.505143 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6866 23:18:42.511758 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6867 23:18:42.514752 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6868 23:18:42.518144 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6869 23:18:42.521842 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6870 23:18:42.528077 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6871 23:18:42.531789 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6872 23:18:42.534664 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6873 23:18:42.538156 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6874 23:18:42.545159 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6875 23:18:42.547963 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6876 23:18:42.551414 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6877 23:18:42.555083 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6878 23:18:42.562045 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6879 23:18:42.564957 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6880 23:18:42.565059 ==
6881 23:18:42.568317 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 23:18:42.571786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 23:18:42.571890 ==
6884 23:18:42.571980 DQS Delay:
6885 23:18:42.574954 DQS0 = 43, DQS1 = 51
6886 23:18:42.575057 DQM Delay:
6887 23:18:42.578278 DQM0 = 9, DQM1 = 9
6888 23:18:42.578380 DQ Delay:
6889 23:18:42.581827 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6890 23:18:42.584977 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6891 23:18:42.588536 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6892 23:18:42.592159 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6893 23:18:42.592258
6894 23:18:42.592343
6895 23:18:42.592423 ==
6896 23:18:42.595228 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 23:18:42.598488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 23:18:42.598588 ==
6899 23:18:42.598677
6900 23:18:42.598762
6901 23:18:42.601595 TX Vref Scan disable
6902 23:18:42.601695 == TX Byte 0 ==
6903 23:18:42.608530 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6904 23:18:42.612344 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6905 23:18:42.612447 == TX Byte 1 ==
6906 23:18:42.618537 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6907 23:18:42.621921 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6908 23:18:42.622022 ==
6909 23:18:42.625368 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 23:18:42.628821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 23:18:42.628922 ==
6912 23:18:42.629009
6913 23:18:42.629091
6914 23:18:42.632240 TX Vref Scan disable
6915 23:18:42.632341 == TX Byte 0 ==
6916 23:18:42.638469 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6917 23:18:42.641956 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6918 23:18:42.642058 == TX Byte 1 ==
6919 23:18:42.648675 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6920 23:18:42.651906 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6921 23:18:42.652009
6922 23:18:42.652097 [DATLAT]
6923 23:18:42.655310 Freq=400, CH1 RK1
6924 23:18:42.655414
6925 23:18:42.655503 DATLAT Default: 0xe
6926 23:18:42.658527 0, 0xFFFF, sum = 0
6927 23:18:42.658630 1, 0xFFFF, sum = 0
6928 23:18:42.661777 2, 0xFFFF, sum = 0
6929 23:18:42.661879 3, 0xFFFF, sum = 0
6930 23:18:42.665115 4, 0xFFFF, sum = 0
6931 23:18:42.665218 5, 0xFFFF, sum = 0
6932 23:18:42.668629 6, 0xFFFF, sum = 0
6933 23:18:42.668733 7, 0xFFFF, sum = 0
6934 23:18:42.671685 8, 0xFFFF, sum = 0
6935 23:18:42.671787 9, 0xFFFF, sum = 0
6936 23:18:42.675072 10, 0xFFFF, sum = 0
6937 23:18:42.679080 11, 0xFFFF, sum = 0
6938 23:18:42.679184 12, 0xFFFF, sum = 0
6939 23:18:42.682082 13, 0x0, sum = 1
6940 23:18:42.682183 14, 0x0, sum = 2
6941 23:18:42.682272 15, 0x0, sum = 3
6942 23:18:42.685167 16, 0x0, sum = 4
6943 23:18:42.685269 best_step = 14
6944 23:18:42.685357
6945 23:18:42.685442 ==
6946 23:18:42.688857 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 23:18:42.695166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 23:18:42.695273 ==
6949 23:18:42.695364 RX Vref Scan: 0
6950 23:18:42.695453
6951 23:18:42.698371 RX Vref 0 -> 0, step: 1
6952 23:18:42.698509
6953 23:18:42.701631 RX Delay -343 -> 252, step: 8
6954 23:18:42.708651 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6955 23:18:42.712463 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6956 23:18:42.715333 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6957 23:18:42.718722 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6958 23:18:42.725304 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6959 23:18:42.728677 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6960 23:18:42.732247 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6961 23:18:42.735703 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6962 23:18:42.741981 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6963 23:18:42.745320 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6964 23:18:42.748898 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6965 23:18:42.751799 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6966 23:18:42.758379 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6967 23:18:42.761971 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6968 23:18:42.765092 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6969 23:18:42.768460 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6970 23:18:42.771791 ==
6971 23:18:42.775509 Dram Type= 6, Freq= 0, CH_1, rank 1
6972 23:18:42.778542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6973 23:18:42.778646 ==
6974 23:18:42.778735 DQS Delay:
6975 23:18:42.782449 DQS0 = 52, DQS1 = 60
6976 23:18:42.782552 DQM Delay:
6977 23:18:42.784990 DQM0 = 13, DQM1 = 14
6978 23:18:42.785090 DQ Delay:
6979 23:18:42.788425 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6980 23:18:42.792182 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6981 23:18:42.795359 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6982 23:18:42.798651 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
6983 23:18:42.798758
6984 23:18:42.798844
6985 23:18:42.805301 [DQSOSCAuto] RK1, (LSB)MR18= 0x7b92, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 394 ps
6986 23:18:42.808665 CH1 RK1: MR19=C0C, MR18=7B92
6987 23:18:42.815299 CH1_RK1: MR19=0xC0C, MR18=0x7B92, DQSOSC=391, MR23=63, INC=386, DEC=257
6988 23:18:42.818846 [RxdqsGatingPostProcess] freq 400
6989 23:18:42.821844 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6990 23:18:42.825542 best DQS0 dly(2T, 0.5T) = (0, 10)
6991 23:18:42.828903 best DQS1 dly(2T, 0.5T) = (0, 10)
6992 23:18:42.832307 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6993 23:18:42.835380 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6994 23:18:42.838589 best DQS0 dly(2T, 0.5T) = (0, 10)
6995 23:18:42.842305 best DQS1 dly(2T, 0.5T) = (0, 10)
6996 23:18:42.845033 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6997 23:18:42.848979 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6998 23:18:42.852352 Pre-setting of DQS Precalculation
6999 23:18:42.855800 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7000 23:18:42.862416 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7001 23:18:42.872340 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7002 23:18:42.872445
7003 23:18:42.872532
7004 23:18:42.875924 [Calibration Summary] 800 Mbps
7005 23:18:42.876024 CH 0, Rank 0
7006 23:18:42.879250 SW Impedance : PASS
7007 23:18:42.879350 DUTY Scan : NO K
7008 23:18:42.882306 ZQ Calibration : PASS
7009 23:18:42.882413 Jitter Meter : NO K
7010 23:18:42.885363 CBT Training : PASS
7011 23:18:42.888703 Write leveling : PASS
7012 23:18:42.888803 RX DQS gating : PASS
7013 23:18:42.892358 RX DQ/DQS(RDDQC) : PASS
7014 23:18:42.895816 TX DQ/DQS : PASS
7015 23:18:42.895919 RX DATLAT : PASS
7016 23:18:42.898542 RX DQ/DQS(Engine): PASS
7017 23:18:42.901924 TX OE : NO K
7018 23:18:42.902028 All Pass.
7019 23:18:42.902117
7020 23:18:42.902204 CH 0, Rank 1
7021 23:18:42.905540 SW Impedance : PASS
7022 23:18:42.908702 DUTY Scan : NO K
7023 23:18:42.908807 ZQ Calibration : PASS
7024 23:18:42.912327 Jitter Meter : NO K
7025 23:18:42.915504 CBT Training : PASS
7026 23:18:42.915608 Write leveling : NO K
7027 23:18:42.918970 RX DQS gating : PASS
7028 23:18:42.922335 RX DQ/DQS(RDDQC) : PASS
7029 23:18:42.922476 TX DQ/DQS : PASS
7030 23:18:42.925474 RX DATLAT : PASS
7031 23:18:42.925604 RX DQ/DQS(Engine): PASS
7032 23:18:42.928616 TX OE : NO K
7033 23:18:42.928697 All Pass.
7034 23:18:42.928760
7035 23:18:42.932163 CH 1, Rank 0
7036 23:18:42.932244 SW Impedance : PASS
7037 23:18:42.935754 DUTY Scan : NO K
7038 23:18:42.938738 ZQ Calibration : PASS
7039 23:18:42.938818 Jitter Meter : NO K
7040 23:18:42.942120 CBT Training : PASS
7041 23:18:42.945489 Write leveling : PASS
7042 23:18:42.945569 RX DQS gating : PASS
7043 23:18:42.948843 RX DQ/DQS(RDDQC) : PASS
7044 23:18:42.952117 TX DQ/DQS : PASS
7045 23:18:42.952197 RX DATLAT : PASS
7046 23:18:42.955496 RX DQ/DQS(Engine): PASS
7047 23:18:42.958814 TX OE : NO K
7048 23:18:42.958894 All Pass.
7049 23:18:42.958957
7050 23:18:42.959016 CH 1, Rank 1
7051 23:18:42.961985 SW Impedance : PASS
7052 23:18:42.965340 DUTY Scan : NO K
7053 23:18:42.965445 ZQ Calibration : PASS
7054 23:18:42.968785 Jitter Meter : NO K
7055 23:18:42.968884 CBT Training : PASS
7056 23:18:42.971989 Write leveling : NO K
7057 23:18:42.975712 RX DQS gating : PASS
7058 23:18:42.975792 RX DQ/DQS(RDDQC) : PASS
7059 23:18:42.978703 TX DQ/DQS : PASS
7060 23:18:42.982730 RX DATLAT : PASS
7061 23:18:42.982810 RX DQ/DQS(Engine): PASS
7062 23:18:42.985730 TX OE : NO K
7063 23:18:42.985819 All Pass.
7064 23:18:42.985881
7065 23:18:42.988804 DramC Write-DBI off
7066 23:18:42.992265 PER_BANK_REFRESH: Hybrid Mode
7067 23:18:42.992343 TX_TRACKING: ON
7068 23:18:43.002184 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7069 23:18:43.005851 [FAST_K] Save calibration result to emmc
7070 23:18:43.008921 dramc_set_vcore_voltage set vcore to 725000
7071 23:18:43.012170 Read voltage for 1600, 0
7072 23:18:43.012250 Vio18 = 0
7073 23:18:43.012312 Vcore = 725000
7074 23:18:43.016123 Vdram = 0
7075 23:18:43.016202 Vddq = 0
7076 23:18:43.016264 Vmddr = 0
7077 23:18:43.022382 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7078 23:18:43.025405 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7079 23:18:43.029152 MEM_TYPE=3, freq_sel=13
7080 23:18:43.032464 sv_algorithm_assistance_LP4_3733
7081 23:18:43.036121 ============ PULL DRAM RESETB DOWN ============
7082 23:18:43.038854 ========== PULL DRAM RESETB DOWN end =========
7083 23:18:43.045516 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7084 23:18:43.049060 ===================================
7085 23:18:43.049167 LPDDR4 DRAM CONFIGURATION
7086 23:18:43.052189 ===================================
7087 23:18:43.055697 EX_ROW_EN[0] = 0x0
7088 23:18:43.058918 EX_ROW_EN[1] = 0x0
7089 23:18:43.059028 LP4Y_EN = 0x0
7090 23:18:43.062461 WORK_FSP = 0x1
7091 23:18:43.062549 WL = 0x5
7092 23:18:43.065595 RL = 0x5
7093 23:18:43.065680 BL = 0x2
7094 23:18:43.068769 RPST = 0x0
7095 23:18:43.068850 RD_PRE = 0x0
7096 23:18:43.072093 WR_PRE = 0x1
7097 23:18:43.072175 WR_PST = 0x1
7098 23:18:43.075482 DBI_WR = 0x0
7099 23:18:43.075572 DBI_RD = 0x0
7100 23:18:43.078943 OTF = 0x1
7101 23:18:43.082155 ===================================
7102 23:18:43.085447 ===================================
7103 23:18:43.085546 ANA top config
7104 23:18:43.088813 ===================================
7105 23:18:43.092205 DLL_ASYNC_EN = 0
7106 23:18:43.095796 ALL_SLAVE_EN = 0
7107 23:18:43.098833 NEW_RANK_MODE = 1
7108 23:18:43.098915 DLL_IDLE_MODE = 1
7109 23:18:43.101919 LP45_APHY_COMB_EN = 1
7110 23:18:43.105295 TX_ODT_DIS = 0
7111 23:18:43.109253 NEW_8X_MODE = 1
7112 23:18:43.112342 ===================================
7113 23:18:43.115515 ===================================
7114 23:18:43.118856 data_rate = 3200
7115 23:18:43.118936 CKR = 1
7116 23:18:43.121997 DQ_P2S_RATIO = 8
7117 23:18:43.125636 ===================================
7118 23:18:43.128668 CA_P2S_RATIO = 8
7119 23:18:43.132095 DQ_CA_OPEN = 0
7120 23:18:43.135505 DQ_SEMI_OPEN = 0
7121 23:18:43.135586 CA_SEMI_OPEN = 0
7122 23:18:43.138883 CA_FULL_RATE = 0
7123 23:18:43.142183 DQ_CKDIV4_EN = 0
7124 23:18:43.145585 CA_CKDIV4_EN = 0
7125 23:18:43.148782 CA_PREDIV_EN = 0
7126 23:18:43.152506 PH8_DLY = 12
7127 23:18:43.152588 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7128 23:18:43.155727 DQ_AAMCK_DIV = 4
7129 23:18:43.159015 CA_AAMCK_DIV = 4
7130 23:18:43.162058 CA_ADMCK_DIV = 4
7131 23:18:43.165578 DQ_TRACK_CA_EN = 0
7132 23:18:43.168931 CA_PICK = 1600
7133 23:18:43.172238 CA_MCKIO = 1600
7134 23:18:43.172319 MCKIO_SEMI = 0
7135 23:18:43.175596 PLL_FREQ = 3068
7136 23:18:43.179132 DQ_UI_PI_RATIO = 32
7137 23:18:43.181964 CA_UI_PI_RATIO = 0
7138 23:18:43.185613 ===================================
7139 23:18:43.188815 ===================================
7140 23:18:43.192217 memory_type:LPDDR4
7141 23:18:43.192315 GP_NUM : 10
7142 23:18:43.195563 SRAM_EN : 1
7143 23:18:43.198914 MD32_EN : 0
7144 23:18:43.202347 ===================================
7145 23:18:43.202472 [ANA_INIT] >>>>>>>>>>>>>>
7146 23:18:43.205428 <<<<<< [CONFIGURE PHASE]: ANA_TX
7147 23:18:43.208432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7148 23:18:43.212016 ===================================
7149 23:18:43.215608 data_rate = 3200,PCW = 0X7600
7150 23:18:43.218472 ===================================
7151 23:18:43.221853 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7152 23:18:43.229089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7153 23:18:43.231884 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7154 23:18:43.238686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7155 23:18:43.241640 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7156 23:18:43.245187 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7157 23:18:43.245298 [ANA_INIT] flow start
7158 23:18:43.248409 [ANA_INIT] PLL >>>>>>>>
7159 23:18:43.251731 [ANA_INIT] PLL <<<<<<<<
7160 23:18:43.251812 [ANA_INIT] MIDPI >>>>>>>>
7161 23:18:43.255046 [ANA_INIT] MIDPI <<<<<<<<
7162 23:18:43.258327 [ANA_INIT] DLL >>>>>>>>
7163 23:18:43.261791 [ANA_INIT] DLL <<<<<<<<
7164 23:18:43.261898 [ANA_INIT] flow end
7165 23:18:43.265552 ============ LP4 DIFF to SE enter ============
7166 23:18:43.272055 ============ LP4 DIFF to SE exit ============
7167 23:18:43.272159 [ANA_INIT] <<<<<<<<<<<<<
7168 23:18:43.275214 [Flow] Enable top DCM control >>>>>
7169 23:18:43.278708 [Flow] Enable top DCM control <<<<<
7170 23:18:43.282093 Enable DLL master slave shuffle
7171 23:18:43.288402 ==============================================================
7172 23:18:43.288485 Gating Mode config
7173 23:18:43.295059 ==============================================================
7174 23:18:43.298789 Config description:
7175 23:18:43.305568 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7176 23:18:43.311973 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7177 23:18:43.318985 SELPH_MODE 0: By rank 1: By Phase
7178 23:18:43.322265 ==============================================================
7179 23:18:43.325287 GAT_TRACK_EN = 1
7180 23:18:43.328485 RX_GATING_MODE = 2
7181 23:18:43.332227 RX_GATING_TRACK_MODE = 2
7182 23:18:43.335334 SELPH_MODE = 1
7183 23:18:43.339481 PICG_EARLY_EN = 1
7184 23:18:43.342139 VALID_LAT_VALUE = 1
7185 23:18:43.348705 ==============================================================
7186 23:18:43.351764 Enter into Gating configuration >>>>
7187 23:18:43.355481 Exit from Gating configuration <<<<
7188 23:18:43.355611 Enter into DVFS_PRE_config >>>>>
7189 23:18:43.368818 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7190 23:18:43.372277 Exit from DVFS_PRE_config <<<<<
7191 23:18:43.375128 Enter into PICG configuration >>>>
7192 23:18:43.378753 Exit from PICG configuration <<<<
7193 23:18:43.378862 [RX_INPUT] configuration >>>>>
7194 23:18:43.381909 [RX_INPUT] configuration <<<<<
7195 23:18:43.388889 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7196 23:18:43.392065 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7197 23:18:43.398646 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7198 23:18:43.405717 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7199 23:18:43.412655 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7200 23:18:43.419102 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7201 23:18:43.422436 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7202 23:18:43.425924 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7203 23:18:43.428805 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7204 23:18:43.435621 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7205 23:18:43.438889 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7206 23:18:43.442316 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7207 23:18:43.445917 ===================================
7208 23:18:43.448741 LPDDR4 DRAM CONFIGURATION
7209 23:18:43.452066 ===================================
7210 23:18:43.455577 EX_ROW_EN[0] = 0x0
7211 23:18:43.455745 EX_ROW_EN[1] = 0x0
7212 23:18:43.459042 LP4Y_EN = 0x0
7213 23:18:43.459150 WORK_FSP = 0x1
7214 23:18:43.462310 WL = 0x5
7215 23:18:43.462436 RL = 0x5
7216 23:18:43.465693 BL = 0x2
7217 23:18:43.465802 RPST = 0x0
7218 23:18:43.468915 RD_PRE = 0x0
7219 23:18:43.469063 WR_PRE = 0x1
7220 23:18:43.472153 WR_PST = 0x1
7221 23:18:43.472241 DBI_WR = 0x0
7222 23:18:43.475667 DBI_RD = 0x0
7223 23:18:43.475775 OTF = 0x1
7224 23:18:43.478758 ===================================
7225 23:18:43.482333 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7226 23:18:43.488868 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7227 23:18:43.492373 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7228 23:18:43.495307 ===================================
7229 23:18:43.499148 LPDDR4 DRAM CONFIGURATION
7230 23:18:43.502378 ===================================
7231 23:18:43.502492 EX_ROW_EN[0] = 0x10
7232 23:18:43.505333 EX_ROW_EN[1] = 0x0
7233 23:18:43.509000 LP4Y_EN = 0x0
7234 23:18:43.509133 WORK_FSP = 0x1
7235 23:18:43.512290 WL = 0x5
7236 23:18:43.512405 RL = 0x5
7237 23:18:43.515874 BL = 0x2
7238 23:18:43.515956 RPST = 0x0
7239 23:18:43.519164 RD_PRE = 0x0
7240 23:18:43.519247 WR_PRE = 0x1
7241 23:18:43.522051 WR_PST = 0x1
7242 23:18:43.522158 DBI_WR = 0x0
7243 23:18:43.525397 DBI_RD = 0x0
7244 23:18:43.525505 OTF = 0x1
7245 23:18:43.528608 ===================================
7246 23:18:43.535580 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7247 23:18:43.535708 ==
7248 23:18:43.538779 Dram Type= 6, Freq= 0, CH_0, rank 0
7249 23:18:43.542235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7250 23:18:43.542368 ==
7251 23:18:43.545729 [Duty_Offset_Calibration]
7252 23:18:43.548980 B0:2 B1:-1 CA:1
7253 23:18:43.549093
7254 23:18:43.551959 [DutyScan_Calibration_Flow] k_type=0
7255 23:18:43.559967
7256 23:18:43.560073 ==CLK 0==
7257 23:18:43.563619 Final CLK duty delay cell = -4
7258 23:18:43.566718 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7259 23:18:43.570245 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7260 23:18:43.573222 [-4] AVG Duty = 4937%(X100)
7261 23:18:43.573326
7262 23:18:43.577013 CH0 CLK Duty spec in!! Max-Min= 187%
7263 23:18:43.579924 [DutyScan_Calibration_Flow] ====Done====
7264 23:18:43.580041
7265 23:18:43.582922 [DutyScan_Calibration_Flow] k_type=1
7266 23:18:43.599299
7267 23:18:43.599415 ==DQS 0 ==
7268 23:18:43.602982 Final DQS duty delay cell = 0
7269 23:18:43.606017 [0] MAX Duty = 5125%(X100), DQS PI = 20
7270 23:18:43.609072 [0] MIN Duty = 5000%(X100), DQS PI = 14
7271 23:18:43.612434 [0] AVG Duty = 5062%(X100)
7272 23:18:43.612525
7273 23:18:43.612615 ==DQS 1 ==
7274 23:18:43.615945 Final DQS duty delay cell = -4
7275 23:18:43.619147 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7276 23:18:43.622927 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7277 23:18:43.625873 [-4] AVG Duty = 5046%(X100)
7278 23:18:43.625984
7279 23:18:43.629291 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7280 23:18:43.629373
7281 23:18:43.632790 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7282 23:18:43.635646 [DutyScan_Calibration_Flow] ====Done====
7283 23:18:43.635816
7284 23:18:43.638926 [DutyScan_Calibration_Flow] k_type=3
7285 23:18:43.656547
7286 23:18:43.656799 ==DQM 0 ==
7287 23:18:43.660276 Final DQM duty delay cell = 0
7288 23:18:43.663957 [0] MAX Duty = 5000%(X100), DQS PI = 18
7289 23:18:43.666612 [0] MIN Duty = 4875%(X100), DQS PI = 4
7290 23:18:43.666776 [0] AVG Duty = 4937%(X100)
7291 23:18:43.670126
7292 23:18:43.670285 ==DQM 1 ==
7293 23:18:43.673461 Final DQM duty delay cell = 0
7294 23:18:43.676382 [0] MAX Duty = 5218%(X100), DQS PI = 58
7295 23:18:43.680047 [0] MIN Duty = 4969%(X100), DQS PI = 20
7296 23:18:43.683550 [0] AVG Duty = 5093%(X100)
7297 23:18:43.683629
7298 23:18:43.686687 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7299 23:18:43.686806
7300 23:18:43.690334 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7301 23:18:43.693550 [DutyScan_Calibration_Flow] ====Done====
7302 23:18:43.693629
7303 23:18:43.696796 [DutyScan_Calibration_Flow] k_type=2
7304 23:18:43.713997
7305 23:18:43.714173 ==DQ 0 ==
7306 23:18:43.717242 Final DQ duty delay cell = 0
7307 23:18:43.720205 [0] MAX Duty = 5156%(X100), DQS PI = 0
7308 23:18:43.723581 [0] MIN Duty = 5031%(X100), DQS PI = 14
7309 23:18:43.723665 [0] AVG Duty = 5093%(X100)
7310 23:18:43.723727
7311 23:18:43.727422 ==DQ 1 ==
7312 23:18:43.730481 Final DQ duty delay cell = 0
7313 23:18:43.733680 [0] MAX Duty = 5000%(X100), DQS PI = 14
7314 23:18:43.737409 [0] MIN Duty = 4907%(X100), DQS PI = 18
7315 23:18:43.737488 [0] AVG Duty = 4953%(X100)
7316 23:18:43.737550
7317 23:18:43.740722 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7318 23:18:43.740802
7319 23:18:43.744162 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7320 23:18:43.750979 [DutyScan_Calibration_Flow] ====Done====
7321 23:18:43.751059 ==
7322 23:18:43.754019 Dram Type= 6, Freq= 0, CH_1, rank 0
7323 23:18:43.757446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7324 23:18:43.757556 ==
7325 23:18:43.760504 [Duty_Offset_Calibration]
7326 23:18:43.760579 B0:1 B1:1 CA:2
7327 23:18:43.760641
7328 23:18:43.763920 [DutyScan_Calibration_Flow] k_type=0
7329 23:18:43.773889
7330 23:18:43.773971 ==CLK 0==
7331 23:18:43.777876 Final CLK duty delay cell = 0
7332 23:18:43.780458 [0] MAX Duty = 5156%(X100), DQS PI = 24
7333 23:18:43.783859 [0] MIN Duty = 4938%(X100), DQS PI = 50
7334 23:18:43.783944 [0] AVG Duty = 5047%(X100)
7335 23:18:43.787501
7336 23:18:43.790657 CH1 CLK Duty spec in!! Max-Min= 218%
7337 23:18:43.793738 [DutyScan_Calibration_Flow] ====Done====
7338 23:18:43.793840
7339 23:18:43.797664 [DutyScan_Calibration_Flow] k_type=1
7340 23:18:43.813629
7341 23:18:43.813734 ==DQS 0 ==
7342 23:18:43.816813 Final DQS duty delay cell = 0
7343 23:18:43.820161 [0] MAX Duty = 5062%(X100), DQS PI = 20
7344 23:18:43.823324 [0] MIN Duty = 4844%(X100), DQS PI = 44
7345 23:18:43.826929 [0] AVG Duty = 4953%(X100)
7346 23:18:43.827030
7347 23:18:43.827119 ==DQS 1 ==
7348 23:18:43.830363 Final DQS duty delay cell = 0
7349 23:18:43.833978 [0] MAX Duty = 5031%(X100), DQS PI = 42
7350 23:18:43.837365 [0] MIN Duty = 4938%(X100), DQS PI = 12
7351 23:18:43.837468 [0] AVG Duty = 4984%(X100)
7352 23:18:43.840313
7353 23:18:43.843647 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7354 23:18:43.843750
7355 23:18:43.847018 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7356 23:18:43.850162 [DutyScan_Calibration_Flow] ====Done====
7357 23:18:43.850260
7358 23:18:43.853268 [DutyScan_Calibration_Flow] k_type=3
7359 23:18:43.870175
7360 23:18:43.870281 ==DQM 0 ==
7361 23:18:43.873747 Final DQM duty delay cell = 0
7362 23:18:43.876788 [0] MAX Duty = 5187%(X100), DQS PI = 20
7363 23:18:43.880296 [0] MIN Duty = 4844%(X100), DQS PI = 50
7364 23:18:43.883758 [0] AVG Duty = 5015%(X100)
7365 23:18:43.883858
7366 23:18:43.883946 ==DQM 1 ==
7367 23:18:43.886735 Final DQM duty delay cell = 0
7368 23:18:43.890340 [0] MAX Duty = 5125%(X100), DQS PI = 8
7369 23:18:43.893835 [0] MIN Duty = 4875%(X100), DQS PI = 20
7370 23:18:43.896724 [0] AVG Duty = 5000%(X100)
7371 23:18:43.896824
7372 23:18:43.900287 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7373 23:18:43.900388
7374 23:18:43.903717 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7375 23:18:43.906902 [DutyScan_Calibration_Flow] ====Done====
7376 23:18:43.906979
7377 23:18:43.910325 [DutyScan_Calibration_Flow] k_type=2
7378 23:18:43.927002
7379 23:18:43.927107 ==DQ 0 ==
7380 23:18:43.930835 Final DQ duty delay cell = 0
7381 23:18:43.933738 [0] MAX Duty = 5156%(X100), DQS PI = 20
7382 23:18:43.937215 [0] MIN Duty = 4907%(X100), DQS PI = 52
7383 23:18:43.937319 [0] AVG Duty = 5031%(X100)
7384 23:18:43.937409
7385 23:18:43.940698 ==DQ 1 ==
7386 23:18:43.943734 Final DQ duty delay cell = 0
7387 23:18:43.947371 [0] MAX Duty = 5093%(X100), DQS PI = 6
7388 23:18:43.950194 [0] MIN Duty = 5031%(X100), DQS PI = 0
7389 23:18:43.950315 [0] AVG Duty = 5062%(X100)
7390 23:18:43.950433
7391 23:18:43.953742 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7392 23:18:43.953846
7393 23:18:43.957256 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7394 23:18:43.963508 [DutyScan_Calibration_Flow] ====Done====
7395 23:18:43.966678 nWR fixed to 30
7396 23:18:43.966759 [ModeRegInit_LP4] CH0 RK0
7397 23:18:43.970524 [ModeRegInit_LP4] CH0 RK1
7398 23:18:43.973631 [ModeRegInit_LP4] CH1 RK0
7399 23:18:43.973711 [ModeRegInit_LP4] CH1 RK1
7400 23:18:43.977163 match AC timing 5
7401 23:18:43.980188 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7402 23:18:43.983718 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7403 23:18:43.990046 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7404 23:18:43.993879 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7405 23:18:44.000478 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7406 23:18:44.000555 [MiockJmeterHQA]
7407 23:18:44.000624
7408 23:18:44.003640 [DramcMiockJmeter] u1RxGatingPI = 0
7409 23:18:44.007143 0 : 4255, 4026
7410 23:18:44.007216 4 : 4257, 4030
7411 23:18:44.007283 8 : 4254, 4029
7412 23:18:44.010335 12 : 4258, 4030
7413 23:18:44.010472 16 : 4370, 4142
7414 23:18:44.013849 20 : 4257, 4029
7415 23:18:44.013930 24 : 4257, 4029
7416 23:18:44.017610 28 : 4253, 4027
7417 23:18:44.017689 32 : 4253, 4026
7418 23:18:44.017752 36 : 4368, 4142
7419 23:18:44.020253 40 : 4255, 4030
7420 23:18:44.020352 44 : 4253, 4026
7421 23:18:44.024109 48 : 4252, 4027
7422 23:18:44.024211 52 : 4365, 4140
7423 23:18:44.026965 56 : 4252, 4027
7424 23:18:44.027064 60 : 4363, 4137
7425 23:18:44.027153 64 : 4253, 4029
7426 23:18:44.030431 68 : 4253, 4029
7427 23:18:44.030516 72 : 4252, 4029
7428 23:18:44.033822 76 : 4252, 4030
7429 23:18:44.033920 80 : 4360, 4138
7430 23:18:44.037321 84 : 4252, 4029
7431 23:18:44.037421 88 : 4250, 4027
7432 23:18:44.040666 92 : 4250, 4027
7433 23:18:44.040766 96 : 4257, 3266
7434 23:18:44.040857 100 : 4250, 0
7435 23:18:44.044008 104 : 4255, 0
7436 23:18:44.044104 108 : 4250, 0
7437 23:18:44.044194 112 : 4255, 0
7438 23:18:44.047157 116 : 4255, 0
7439 23:18:44.047230 120 : 4250, 0
7440 23:18:44.050347 124 : 4253, 0
7441 23:18:44.050475 128 : 4253, 0
7442 23:18:44.050555 132 : 4255, 0
7443 23:18:44.053785 136 : 4363, 0
7444 23:18:44.053893 140 : 4366, 0
7445 23:18:44.057254 144 : 4255, 0
7446 23:18:44.057358 148 : 4250, 0
7447 23:18:44.057449 152 : 4252, 0
7448 23:18:44.060729 156 : 4250, 0
7449 23:18:44.060829 160 : 4253, 0
7450 23:18:44.064300 164 : 4365, 0
7451 23:18:44.064401 168 : 4253, 0
7452 23:18:44.064496 172 : 4363, 0
7453 23:18:44.067158 176 : 4252, 0
7454 23:18:44.067231 180 : 4255, 0
7455 23:18:44.067291 184 : 4254, 0
7456 23:18:44.071176 188 : 4363, 0
7457 23:18:44.071278 192 : 4253, 0
7458 23:18:44.074201 196 : 4250, 0
7459 23:18:44.074302 200 : 4255, 0
7460 23:18:44.074391 204 : 4255, 0
7461 23:18:44.077372 208 : 4257, 0
7462 23:18:44.077456 212 : 4255, 28
7463 23:18:44.080509 216 : 4250, 3378
7464 23:18:44.080618 220 : 4363, 4137
7465 23:18:44.083637 224 : 4252, 4029
7466 23:18:44.083721 228 : 4361, 4137
7467 23:18:44.087492 232 : 4363, 4139
7468 23:18:44.087605 236 : 4250, 4027
7469 23:18:44.087669 240 : 4250, 4027
7470 23:18:44.090506 244 : 4252, 4029
7471 23:18:44.090603 248 : 4363, 4139
7472 23:18:44.094322 252 : 4250, 4027
7473 23:18:44.094447 256 : 4360, 4137
7474 23:18:44.097640 260 : 4250, 4027
7475 23:18:44.097720 264 : 4250, 4026
7476 23:18:44.100795 268 : 4253, 4029
7477 23:18:44.100876 272 : 4252, 4030
7478 23:18:44.103952 276 : 4250, 4027
7479 23:18:44.104049 280 : 4257, 4034
7480 23:18:44.107093 284 : 4253, 4029
7481 23:18:44.107174 288 : 4252, 4030
7482 23:18:44.107238 292 : 4255, 4029
7483 23:18:44.110617 296 : 4250, 4026
7484 23:18:44.110698 300 : 4367, 4142
7485 23:18:44.114007 304 : 4360, 4138
7486 23:18:44.114123 308 : 4250, 4027
7487 23:18:44.117675 312 : 4363, 4140
7488 23:18:44.117755 316 : 4250, 4026
7489 23:18:44.121105 320 : 4250, 4027
7490 23:18:44.121186 324 : 4250, 4027
7491 23:18:44.123913 328 : 4250, 4026
7492 23:18:44.123995 332 : 4254, 3186
7493 23:18:44.127663 336 : 4250, 102
7494 23:18:44.127744
7495 23:18:44.127806 MIOCK jitter meter ch=0
7496 23:18:44.127864
7497 23:18:44.130634 1T = (336-100) = 236 dly cells
7498 23:18:44.136935 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7499 23:18:44.137015 ==
7500 23:18:44.140558 Dram Type= 6, Freq= 0, CH_0, rank 0
7501 23:18:44.143726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7502 23:18:44.143807 ==
7503 23:18:44.150665 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7504 23:18:44.154268 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7505 23:18:44.157305 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7506 23:18:44.164183 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7507 23:18:44.173532 [CA 0] Center 44 (14~75) winsize 62
7508 23:18:44.176977 [CA 1] Center 44 (14~74) winsize 61
7509 23:18:44.180269 [CA 2] Center 39 (10~68) winsize 59
7510 23:18:44.183831 [CA 3] Center 39 (10~68) winsize 59
7511 23:18:44.187163 [CA 4] Center 37 (7~67) winsize 61
7512 23:18:44.190187 [CA 5] Center 37 (7~67) winsize 61
7513 23:18:44.190266
7514 23:18:44.193697 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7515 23:18:44.193781
7516 23:18:44.197120 [CATrainingPosCal] consider 1 rank data
7517 23:18:44.200422 u2DelayCellTimex100 = 275/100 ps
7518 23:18:44.203358 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7519 23:18:44.210017 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7520 23:18:44.213644 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7521 23:18:44.216719 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7522 23:18:44.220012 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7523 23:18:44.223463 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7524 23:18:44.223543
7525 23:18:44.227237 CA PerBit enable=1, Macro0, CA PI delay=37
7526 23:18:44.227317
7527 23:18:44.230236 [CBTSetCACLKResult] CA Dly = 37
7528 23:18:44.233439 CS Dly: 11 (0~42)
7529 23:18:44.236953 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7530 23:18:44.240387 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7531 23:18:44.240467 ==
7532 23:18:44.243326 Dram Type= 6, Freq= 0, CH_0, rank 1
7533 23:18:44.246705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7534 23:18:44.250124 ==
7535 23:18:44.253500 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7536 23:18:44.256827 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7537 23:18:44.263692 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7538 23:18:44.266494 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7539 23:18:44.277529 [CA 0] Center 44 (14~75) winsize 62
7540 23:18:44.280677 [CA 1] Center 44 (14~75) winsize 62
7541 23:18:44.284174 [CA 2] Center 39 (10~69) winsize 60
7542 23:18:44.286917 [CA 3] Center 39 (10~69) winsize 60
7543 23:18:44.290310 [CA 4] Center 38 (8~68) winsize 61
7544 23:18:44.293850 [CA 5] Center 37 (7~67) winsize 61
7545 23:18:44.293960
7546 23:18:44.297386 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7547 23:18:44.297466
7548 23:18:44.303501 [CATrainingPosCal] consider 2 rank data
7549 23:18:44.303581 u2DelayCellTimex100 = 275/100 ps
7550 23:18:44.310762 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7551 23:18:44.313758 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7552 23:18:44.316929 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7553 23:18:44.320018 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7554 23:18:44.323871 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7555 23:18:44.327451 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7556 23:18:44.327577
7557 23:18:44.330503 CA PerBit enable=1, Macro0, CA PI delay=37
7558 23:18:44.330583
7559 23:18:44.333828 [CBTSetCACLKResult] CA Dly = 37
7560 23:18:44.337167 CS Dly: 12 (0~44)
7561 23:18:44.340440 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7562 23:18:44.343900 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7563 23:18:44.343979
7564 23:18:44.347588 ----->DramcWriteLeveling(PI) begin...
7565 23:18:44.347668 ==
7566 23:18:44.350259 Dram Type= 6, Freq= 0, CH_0, rank 0
7567 23:18:44.357225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7568 23:18:44.357307 ==
7569 23:18:44.360598 Write leveling (Byte 0): 29 => 29
7570 23:18:44.360678 Write leveling (Byte 1): 26 => 26
7571 23:18:44.363272 DramcWriteLeveling(PI) end<-----
7572 23:18:44.363352
7573 23:18:44.367037 ==
7574 23:18:44.370367 Dram Type= 6, Freq= 0, CH_0, rank 0
7575 23:18:44.373345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7576 23:18:44.373425 ==
7577 23:18:44.376842 [Gating] SW mode calibration
7578 23:18:44.383466 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7579 23:18:44.386502 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7580 23:18:44.393336 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 23:18:44.396462 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 23:18:44.400126 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 23:18:44.406384 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 23:18:44.409932 1 4 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7585 23:18:44.413192 1 4 20 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
7586 23:18:44.419947 1 4 24 | B1->B0 | 3433 3434 | 1 1 | (0 0) (1 1)
7587 23:18:44.423218 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 23:18:44.426558 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 23:18:44.432759 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 23:18:44.436705 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 23:18:44.439375 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 23:18:44.446215 1 5 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7593 23:18:44.449575 1 5 20 | B1->B0 | 3333 2323 | 1 1 | (1 0) (1 0)
7594 23:18:44.452979 1 5 24 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7595 23:18:44.459487 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 23:18:44.462907 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 23:18:44.466228 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 23:18:44.472656 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 23:18:44.476004 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7600 23:18:44.479185 1 6 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7601 23:18:44.486577 1 6 20 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
7602 23:18:44.489158 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7603 23:18:44.492449 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 23:18:44.499496 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 23:18:44.502496 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 23:18:44.505643 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 23:18:44.512381 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 23:18:44.516120 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7609 23:18:44.519293 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7610 23:18:44.522925 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7611 23:18:44.529372 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 23:18:44.532275 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 23:18:44.535764 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 23:18:44.542639 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 23:18:44.545824 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 23:18:44.548972 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 23:18:44.555808 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 23:18:44.559121 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 23:18:44.562131 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 23:18:44.568798 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 23:18:44.572259 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 23:18:44.575704 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 23:18:44.582488 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 23:18:44.585882 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7625 23:18:44.588838 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7626 23:18:44.592214 Total UI for P1: 0, mck2ui 16
7627 23:18:44.596017 best dqsien dly found for B0: ( 1, 9, 16)
7628 23:18:44.602626 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7629 23:18:44.605633 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 23:18:44.608814 Total UI for P1: 0, mck2ui 16
7631 23:18:44.612060 best dqsien dly found for B1: ( 1, 9, 22)
7632 23:18:44.615686 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7633 23:18:44.618929 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7634 23:18:44.619037
7635 23:18:44.622211 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7636 23:18:44.625713 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7637 23:18:44.628896 [Gating] SW calibration Done
7638 23:18:44.629001 ==
7639 23:18:44.632240 Dram Type= 6, Freq= 0, CH_0, rank 0
7640 23:18:44.635533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7641 23:18:44.638950 ==
7642 23:18:44.639041 RX Vref Scan: 0
7643 23:18:44.639131
7644 23:18:44.642611 RX Vref 0 -> 0, step: 1
7645 23:18:44.642711
7646 23:18:44.642800 RX Delay 0 -> 252, step: 8
7647 23:18:44.648760 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7648 23:18:44.652265 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7649 23:18:44.656038 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7650 23:18:44.658691 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7651 23:18:44.662052 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7652 23:18:44.668694 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7653 23:18:44.672196 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7654 23:18:44.675331 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7655 23:18:44.678702 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7656 23:18:44.681880 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7657 23:18:44.688504 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7658 23:18:44.692010 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7659 23:18:44.695321 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7660 23:18:44.698801 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7661 23:18:44.702281 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7662 23:18:44.708711 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7663 23:18:44.708811 ==
7664 23:18:44.712056 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 23:18:44.715663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 23:18:44.715764 ==
7667 23:18:44.715857 DQS Delay:
7668 23:18:44.718990 DQS0 = 0, DQS1 = 0
7669 23:18:44.719088 DQM Delay:
7670 23:18:44.722005 DQM0 = 132, DQM1 = 125
7671 23:18:44.722103 DQ Delay:
7672 23:18:44.725444 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7673 23:18:44.729228 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7674 23:18:44.732185 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7675 23:18:44.735161 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7676 23:18:44.735261
7677 23:18:44.739227
7678 23:18:44.739303 ==
7679 23:18:44.742453 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 23:18:44.745336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 23:18:44.745432 ==
7682 23:18:44.745519
7683 23:18:44.745607
7684 23:18:44.749168 TX Vref Scan disable
7685 23:18:44.749269 == TX Byte 0 ==
7686 23:18:44.752243 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7687 23:18:44.759112 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7688 23:18:44.759196 == TX Byte 1 ==
7689 23:18:44.762005 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7690 23:18:44.769248 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7691 23:18:44.769352 ==
7692 23:18:44.773033 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 23:18:44.775718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 23:18:44.775817 ==
7695 23:18:44.790050
7696 23:18:44.793838 TX Vref early break, caculate TX vref
7697 23:18:44.796671 TX Vref=16, minBit 1, minWin=21, winSum=358
7698 23:18:44.800298 TX Vref=18, minBit 7, minWin=21, winSum=367
7699 23:18:44.803693 TX Vref=20, minBit 8, minWin=22, winSum=377
7700 23:18:44.807080 TX Vref=22, minBit 7, minWin=23, winSum=390
7701 23:18:44.810369 TX Vref=24, minBit 0, minWin=24, winSum=397
7702 23:18:44.817298 TX Vref=26, minBit 8, minWin=24, winSum=411
7703 23:18:44.820361 TX Vref=28, minBit 7, minWin=24, winSum=419
7704 23:18:44.823323 TX Vref=30, minBit 3, minWin=24, winSum=414
7705 23:18:44.826839 TX Vref=32, minBit 8, minWin=24, winSum=408
7706 23:18:44.830419 TX Vref=34, minBit 9, minWin=23, winSum=399
7707 23:18:44.833368 TX Vref=36, minBit 4, minWin=23, winSum=385
7708 23:18:44.839817 [TxChooseVref] Worse bit 7, Min win 24, Win sum 419, Final Vref 28
7709 23:18:44.839914
7710 23:18:44.843232 Final TX Range 0 Vref 28
7711 23:18:44.843314
7712 23:18:44.843376 ==
7713 23:18:44.846778 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 23:18:44.850315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 23:18:44.850406 ==
7716 23:18:44.850485
7717 23:18:44.850559
7718 23:18:44.853498 TX Vref Scan disable
7719 23:18:44.860514 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7720 23:18:44.860597 == TX Byte 0 ==
7721 23:18:44.863617 u2DelayCellOfst[0]=14 cells (4 PI)
7722 23:18:44.866755 u2DelayCellOfst[1]=21 cells (6 PI)
7723 23:18:44.870269 u2DelayCellOfst[2]=10 cells (3 PI)
7724 23:18:44.873506 u2DelayCellOfst[3]=14 cells (4 PI)
7725 23:18:44.876523 u2DelayCellOfst[4]=7 cells (2 PI)
7726 23:18:44.880183 u2DelayCellOfst[5]=0 cells (0 PI)
7727 23:18:44.883312 u2DelayCellOfst[6]=17 cells (5 PI)
7728 23:18:44.886765 u2DelayCellOfst[7]=17 cells (5 PI)
7729 23:18:44.890159 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7730 23:18:44.893052 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7731 23:18:44.896996 == TX Byte 1 ==
7732 23:18:44.897090 u2DelayCellOfst[8]=3 cells (1 PI)
7733 23:18:44.900036 u2DelayCellOfst[9]=0 cells (0 PI)
7734 23:18:44.903555 u2DelayCellOfst[10]=7 cells (2 PI)
7735 23:18:44.906507 u2DelayCellOfst[11]=0 cells (0 PI)
7736 23:18:44.910127 u2DelayCellOfst[12]=10 cells (3 PI)
7737 23:18:44.913729 u2DelayCellOfst[13]=10 cells (3 PI)
7738 23:18:44.916542 u2DelayCellOfst[14]=17 cells (5 PI)
7739 23:18:44.919766 u2DelayCellOfst[15]=10 cells (3 PI)
7740 23:18:44.923562 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7741 23:18:44.929784 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7742 23:18:44.929865 DramC Write-DBI on
7743 23:18:44.929926 ==
7744 23:18:44.933268 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 23:18:44.936854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 23:18:44.939887 ==
7747 23:18:44.939966
7748 23:18:44.940028
7749 23:18:44.940085 TX Vref Scan disable
7750 23:18:44.943286 == TX Byte 0 ==
7751 23:18:44.946674 Update DQM dly =731 (2 ,6, 27) DQM OEN =(3 ,3)
7752 23:18:44.950319 == TX Byte 1 ==
7753 23:18:44.953751 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7754 23:18:44.953862 DramC Write-DBI off
7755 23:18:44.956660
7756 23:18:44.956789 [DATLAT]
7757 23:18:44.956886 Freq=1600, CH0 RK0
7758 23:18:44.956956
7759 23:18:44.959906 DATLAT Default: 0xf
7760 23:18:44.960000 0, 0xFFFF, sum = 0
7761 23:18:44.963457 1, 0xFFFF, sum = 0
7762 23:18:44.963538 2, 0xFFFF, sum = 0
7763 23:18:44.967345 3, 0xFFFF, sum = 0
7764 23:18:44.967426 4, 0xFFFF, sum = 0
7765 23:18:44.970584 5, 0xFFFF, sum = 0
7766 23:18:44.974038 6, 0xFFFF, sum = 0
7767 23:18:44.974120 7, 0xFFFF, sum = 0
7768 23:18:44.977082 8, 0xFFFF, sum = 0
7769 23:18:44.977162 9, 0xFFFF, sum = 0
7770 23:18:44.980486 10, 0xFFFF, sum = 0
7771 23:18:44.980567 11, 0xFFFF, sum = 0
7772 23:18:44.983883 12, 0xFFFF, sum = 0
7773 23:18:44.983965 13, 0xFFFF, sum = 0
7774 23:18:44.986675 14, 0x0, sum = 1
7775 23:18:44.986757 15, 0x0, sum = 2
7776 23:18:44.990272 16, 0x0, sum = 3
7777 23:18:44.990353 17, 0x0, sum = 4
7778 23:18:44.994276 best_step = 15
7779 23:18:44.994356
7780 23:18:44.994455 ==
7781 23:18:44.996994 Dram Type= 6, Freq= 0, CH_0, rank 0
7782 23:18:45.000606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7783 23:18:45.000686 ==
7784 23:18:45.000749 RX Vref Scan: 1
7785 23:18:45.000807
7786 23:18:45.003547 Set Vref Range= 24 -> 127
7787 23:18:45.003626
7788 23:18:45.006813 RX Vref 24 -> 127, step: 1
7789 23:18:45.006893
7790 23:18:45.010048 RX Delay 11 -> 252, step: 4
7791 23:18:45.010157
7792 23:18:45.013874 Set Vref, RX VrefLevel [Byte0]: 24
7793 23:18:45.016884 [Byte1]: 24
7794 23:18:45.016990
7795 23:18:45.020264 Set Vref, RX VrefLevel [Byte0]: 25
7796 23:18:45.023547 [Byte1]: 25
7797 23:18:45.023645
7798 23:18:45.026779 Set Vref, RX VrefLevel [Byte0]: 26
7799 23:18:45.030208 [Byte1]: 26
7800 23:18:45.033562
7801 23:18:45.033663 Set Vref, RX VrefLevel [Byte0]: 27
7802 23:18:45.037325 [Byte1]: 27
7803 23:18:45.041729
7804 23:18:45.041803 Set Vref, RX VrefLevel [Byte0]: 28
7805 23:18:45.044718 [Byte1]: 28
7806 23:18:45.048829
7807 23:18:45.048909 Set Vref, RX VrefLevel [Byte0]: 29
7808 23:18:45.055783 [Byte1]: 29
7809 23:18:45.055869
7810 23:18:45.058894 Set Vref, RX VrefLevel [Byte0]: 30
7811 23:18:45.061852 [Byte1]: 30
7812 23:18:45.061933
7813 23:18:45.065204 Set Vref, RX VrefLevel [Byte0]: 31
7814 23:18:45.068813 [Byte1]: 31
7815 23:18:45.072280
7816 23:18:45.072389 Set Vref, RX VrefLevel [Byte0]: 32
7817 23:18:45.075342 [Byte1]: 32
7818 23:18:45.079726
7819 23:18:45.079830 Set Vref, RX VrefLevel [Byte0]: 33
7820 23:18:45.082495 [Byte1]: 33
7821 23:18:45.087136
7822 23:18:45.087239 Set Vref, RX VrefLevel [Byte0]: 34
7823 23:18:45.090425 [Byte1]: 34
7824 23:18:45.094827
7825 23:18:45.094918 Set Vref, RX VrefLevel [Byte0]: 35
7826 23:18:45.097823 [Byte1]: 35
7827 23:18:45.102123
7828 23:18:45.102234 Set Vref, RX VrefLevel [Byte0]: 36
7829 23:18:45.105540 [Byte1]: 36
7830 23:18:45.110093
7831 23:18:45.110219 Set Vref, RX VrefLevel [Byte0]: 37
7832 23:18:45.113165 [Byte1]: 37
7833 23:18:45.117352
7834 23:18:45.117464 Set Vref, RX VrefLevel [Byte0]: 38
7835 23:18:45.120786 [Byte1]: 38
7836 23:18:45.125330
7837 23:18:45.125418 Set Vref, RX VrefLevel [Byte0]: 39
7838 23:18:45.128775 [Byte1]: 39
7839 23:18:45.132622
7840 23:18:45.132703 Set Vref, RX VrefLevel [Byte0]: 40
7841 23:18:45.136112 [Byte1]: 40
7842 23:18:45.140109
7843 23:18:45.140188 Set Vref, RX VrefLevel [Byte0]: 41
7844 23:18:45.143924 [Byte1]: 41
7845 23:18:45.148203
7846 23:18:45.148283 Set Vref, RX VrefLevel [Byte0]: 42
7847 23:18:45.151676 [Byte1]: 42
7848 23:18:45.155443
7849 23:18:45.155523 Set Vref, RX VrefLevel [Byte0]: 43
7850 23:18:45.158994 [Byte1]: 43
7851 23:18:45.163029
7852 23:18:45.163109 Set Vref, RX VrefLevel [Byte0]: 44
7853 23:18:45.166649 [Byte1]: 44
7854 23:18:45.170943
7855 23:18:45.171023 Set Vref, RX VrefLevel [Byte0]: 45
7856 23:18:45.174346 [Byte1]: 45
7857 23:18:45.178214
7858 23:18:45.178321 Set Vref, RX VrefLevel [Byte0]: 46
7859 23:18:45.181886 [Byte1]: 46
7860 23:18:45.186082
7861 23:18:45.186161 Set Vref, RX VrefLevel [Byte0]: 47
7862 23:18:45.189687 [Byte1]: 47
7863 23:18:45.193482
7864 23:18:45.193562 Set Vref, RX VrefLevel [Byte0]: 48
7865 23:18:45.196854 [Byte1]: 48
7866 23:18:45.201279
7867 23:18:45.201371 Set Vref, RX VrefLevel [Byte0]: 49
7868 23:18:45.204822 [Byte1]: 49
7869 23:18:45.209084
7870 23:18:45.209163 Set Vref, RX VrefLevel [Byte0]: 50
7871 23:18:45.212271 [Byte1]: 50
7872 23:18:45.216627
7873 23:18:45.216708 Set Vref, RX VrefLevel [Byte0]: 51
7874 23:18:45.220221 [Byte1]: 51
7875 23:18:45.224098
7876 23:18:45.224178 Set Vref, RX VrefLevel [Byte0]: 52
7877 23:18:45.227390 [Byte1]: 52
7878 23:18:45.232155
7879 23:18:45.232234 Set Vref, RX VrefLevel [Byte0]: 53
7880 23:18:45.234897 [Byte1]: 53
7881 23:18:45.239330
7882 23:18:45.239410 Set Vref, RX VrefLevel [Byte0]: 54
7883 23:18:45.242356 [Byte1]: 54
7884 23:18:45.247149
7885 23:18:45.247240 Set Vref, RX VrefLevel [Byte0]: 55
7886 23:18:45.250154 [Byte1]: 55
7887 23:18:45.254857
7888 23:18:45.254937 Set Vref, RX VrefLevel [Byte0]: 56
7889 23:18:45.257969 [Byte1]: 56
7890 23:18:45.262514
7891 23:18:45.262594 Set Vref, RX VrefLevel [Byte0]: 57
7892 23:18:45.265566 [Byte1]: 57
7893 23:18:45.269855
7894 23:18:45.269935 Set Vref, RX VrefLevel [Byte0]: 58
7895 23:18:45.273193 [Byte1]: 58
7896 23:18:45.277313
7897 23:18:45.277410 Set Vref, RX VrefLevel [Byte0]: 59
7898 23:18:45.280992 [Byte1]: 59
7899 23:18:45.284896
7900 23:18:45.284969 Set Vref, RX VrefLevel [Byte0]: 60
7901 23:18:45.288478 [Byte1]: 60
7902 23:18:45.292718
7903 23:18:45.292788 Set Vref, RX VrefLevel [Byte0]: 61
7904 23:18:45.295766 [Byte1]: 61
7905 23:18:45.300288
7906 23:18:45.300358 Set Vref, RX VrefLevel [Byte0]: 62
7907 23:18:45.303452 [Byte1]: 62
7908 23:18:45.307931
7909 23:18:45.308011 Set Vref, RX VrefLevel [Byte0]: 63
7910 23:18:45.310971 [Byte1]: 63
7911 23:18:45.315231
7912 23:18:45.315300 Set Vref, RX VrefLevel [Byte0]: 64
7913 23:18:45.318525 [Byte1]: 64
7914 23:18:45.323479
7915 23:18:45.323578 Set Vref, RX VrefLevel [Byte0]: 65
7916 23:18:45.326790 [Byte1]: 65
7917 23:18:45.331027
7918 23:18:45.331107 Set Vref, RX VrefLevel [Byte0]: 66
7919 23:18:45.333969 [Byte1]: 66
7920 23:18:45.338355
7921 23:18:45.338462 Set Vref, RX VrefLevel [Byte0]: 67
7922 23:18:45.341484 [Byte1]: 67
7923 23:18:45.345831
7924 23:18:45.345911 Set Vref, RX VrefLevel [Byte0]: 68
7925 23:18:45.349097 [Byte1]: 68
7926 23:18:45.353815
7927 23:18:45.353894 Set Vref, RX VrefLevel [Byte0]: 69
7928 23:18:45.357334 [Byte1]: 69
7929 23:18:45.361032
7930 23:18:45.361112 Set Vref, RX VrefLevel [Byte0]: 70
7931 23:18:45.364633 [Byte1]: 70
7932 23:18:45.369079
7933 23:18:45.369187 Set Vref, RX VrefLevel [Byte0]: 71
7934 23:18:45.372053 [Byte1]: 71
7935 23:18:45.376586
7936 23:18:45.376666 Set Vref, RX VrefLevel [Byte0]: 72
7937 23:18:45.379791 [Byte1]: 72
7938 23:18:45.383983
7939 23:18:45.384067 Set Vref, RX VrefLevel [Byte0]: 73
7940 23:18:45.387145 [Byte1]: 73
7941 23:18:45.391825
7942 23:18:45.391905 Set Vref, RX VrefLevel [Byte0]: 74
7943 23:18:45.394815 [Byte1]: 74
7944 23:18:45.399397
7945 23:18:45.399476 Set Vref, RX VrefLevel [Byte0]: 75
7946 23:18:45.402299 [Byte1]: 75
7947 23:18:45.406720
7948 23:18:45.406800 Set Vref, RX VrefLevel [Byte0]: 76
7949 23:18:45.410212 [Byte1]: 76
7950 23:18:45.414523
7951 23:18:45.414602 Final RX Vref Byte 0 = 57 to rank0
7952 23:18:45.418332 Final RX Vref Byte 1 = 60 to rank0
7953 23:18:45.420982 Final RX Vref Byte 0 = 57 to rank1
7954 23:18:45.424214 Final RX Vref Byte 1 = 60 to rank1==
7955 23:18:45.427503 Dram Type= 6, Freq= 0, CH_0, rank 0
7956 23:18:45.434782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7957 23:18:45.434864 ==
7958 23:18:45.434927 DQS Delay:
7959 23:18:45.434985 DQS0 = 0, DQS1 = 0
7960 23:18:45.437863 DQM Delay:
7961 23:18:45.437942 DQM0 = 129, DQM1 = 122
7962 23:18:45.440858 DQ Delay:
7963 23:18:45.452576 DQ0 =128, DQ1 =132, DQ2 =122, DQ3 =126
7964 23:18:45.452688 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
7965 23:18:45.452753 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =118
7966 23:18:45.454336 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =132
7967 23:18:45.454440
7968 23:18:45.454504
7969 23:18:45.454562
7970 23:18:45.457879 [DramC_TX_OE_Calibration] TA2
7971 23:18:45.461765 Original DQ_B0 (3 6) =30, OEN = 27
7972 23:18:45.464287 Original DQ_B1 (3 6) =30, OEN = 27
7973 23:18:45.467852 24, 0x0, End_B0=24 End_B1=24
7974 23:18:45.467934 25, 0x0, End_B0=25 End_B1=25
7975 23:18:45.471442 26, 0x0, End_B0=26 End_B1=26
7976 23:18:45.474839 27, 0x0, End_B0=27 End_B1=27
7977 23:18:45.477978 28, 0x0, End_B0=28 End_B1=28
7978 23:18:45.478060 29, 0x0, End_B0=29 End_B1=29
7979 23:18:45.481108 30, 0x0, End_B0=30 End_B1=30
7980 23:18:45.484624 31, 0x4141, End_B0=30 End_B1=30
7981 23:18:45.487634 Byte0 end_step=30 best_step=27
7982 23:18:45.491302 Byte1 end_step=30 best_step=27
7983 23:18:45.494358 Byte0 TX OE(2T, 0.5T) = (3, 3)
7984 23:18:45.494515 Byte1 TX OE(2T, 0.5T) = (3, 3)
7985 23:18:45.494636
7986 23:18:45.497687
7987 23:18:45.504290 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7988 23:18:45.508005 CH0 RK0: MR19=303, MR18=1509
7989 23:18:45.514882 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
7990 23:18:45.514964
7991 23:18:45.517804 ----->DramcWriteLeveling(PI) begin...
7992 23:18:45.517887 ==
7993 23:18:45.520808 Dram Type= 6, Freq= 0, CH_0, rank 1
7994 23:18:45.524290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7995 23:18:45.524371 ==
7996 23:18:45.527812 Write leveling (Byte 0): 33 => 33
7997 23:18:45.531127 Write leveling (Byte 1): 29 => 29
7998 23:18:45.534499 DramcWriteLeveling(PI) end<-----
7999 23:18:45.534579
8000 23:18:45.534642 ==
8001 23:18:45.537673 Dram Type= 6, Freq= 0, CH_0, rank 1
8002 23:18:45.541500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8003 23:18:45.541602 ==
8004 23:18:45.544208 [Gating] SW mode calibration
8005 23:18:45.551177 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8006 23:18:45.557540 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8007 23:18:45.560875 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 23:18:45.564395 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 23:18:45.570920 1 4 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
8010 23:18:45.574419 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8011 23:18:45.577610 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8012 23:18:45.584512 1 4 20 | B1->B0 | 2a2a 3434 | 0 1 | (1 1) (1 1)
8013 23:18:45.588156 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 23:18:45.591706 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 23:18:45.594304 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8016 23:18:45.600871 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 23:18:45.604234 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8018 23:18:45.607985 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
8019 23:18:45.614653 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8020 23:18:45.617882 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8021 23:18:45.621395 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8022 23:18:45.627612 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 23:18:45.630953 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 23:18:45.634151 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 23:18:45.641368 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8026 23:18:45.644523 1 6 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8027 23:18:45.648171 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8028 23:18:45.654479 1 6 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8029 23:18:45.657846 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 23:18:45.661283 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 23:18:45.667961 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 23:18:45.671006 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 23:18:45.674250 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 23:18:45.681593 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8035 23:18:45.684512 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8036 23:18:45.687759 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8037 23:18:45.691333 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8038 23:18:45.698356 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 23:18:45.701321 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 23:18:45.704659 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 23:18:45.711157 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 23:18:45.714325 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 23:18:45.718167 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 23:18:45.725010 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 23:18:45.727915 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 23:18:45.731344 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 23:18:45.738137 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 23:18:45.741310 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8049 23:18:45.744968 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8050 23:18:45.751089 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8051 23:18:45.751161 Total UI for P1: 0, mck2ui 16
8052 23:18:45.757783 best dqsien dly found for B0: ( 1, 9, 6)
8053 23:18:45.761135 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8054 23:18:45.764381 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8055 23:18:45.768099 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8056 23:18:45.774609 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 23:18:45.777935 Total UI for P1: 0, mck2ui 16
8058 23:18:45.781389 best dqsien dly found for B1: ( 1, 9, 22)
8059 23:18:45.785194 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8060 23:18:45.788096 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
8061 23:18:45.788197
8062 23:18:45.791163 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8063 23:18:45.794814 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
8064 23:18:45.798216 [Gating] SW calibration Done
8065 23:18:45.798295 ==
8066 23:18:45.801786 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 23:18:45.804673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 23:18:45.804754 ==
8069 23:18:45.807960 RX Vref Scan: 0
8070 23:18:45.808039
8071 23:18:45.808101 RX Vref 0 -> 0, step: 1
8072 23:18:45.811648
8073 23:18:45.811740 RX Delay 0 -> 252, step: 8
8074 23:18:45.814596 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8075 23:18:45.821108 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8076 23:18:45.825122 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8077 23:18:45.828363 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8078 23:18:45.831246 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8079 23:18:45.835214 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8080 23:18:45.841282 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8081 23:18:45.845690 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8082 23:18:45.848346 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8083 23:18:45.852034 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8084 23:18:45.854981 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8085 23:18:45.861668 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8086 23:18:45.865066 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8087 23:18:45.868411 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8088 23:18:45.871620 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8089 23:18:45.874827 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8090 23:18:45.878592 ==
8091 23:18:45.878673 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 23:18:45.885040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 23:18:45.885121 ==
8094 23:18:45.885184 DQS Delay:
8095 23:18:45.888372 DQS0 = 0, DQS1 = 0
8096 23:18:45.888452 DQM Delay:
8097 23:18:45.892054 DQM0 = 131, DQM1 = 124
8098 23:18:45.892134 DQ Delay:
8099 23:18:45.894768 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8100 23:18:45.898069 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8101 23:18:45.901622 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
8102 23:18:45.904972 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8103 23:18:45.905052
8104 23:18:45.905115
8105 23:18:45.905172 ==
8106 23:18:45.908239 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 23:18:45.914749 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 23:18:45.914831 ==
8109 23:18:45.914893
8110 23:18:45.914952
8111 23:18:45.915007 TX Vref Scan disable
8112 23:18:45.918281 == TX Byte 0 ==
8113 23:18:45.921560 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8114 23:18:45.924651 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8115 23:18:45.928331 == TX Byte 1 ==
8116 23:18:45.931867 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8117 23:18:45.934917 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8118 23:18:45.938605 ==
8119 23:18:45.941559 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 23:18:45.944632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 23:18:45.944713 ==
8122 23:18:45.958806
8123 23:18:45.962363 TX Vref early break, caculate TX vref
8124 23:18:45.965201 TX Vref=16, minBit 0, minWin=23, winSum=381
8125 23:18:45.968737 TX Vref=18, minBit 3, minWin=23, winSum=388
8126 23:18:45.972411 TX Vref=20, minBit 1, minWin=24, winSum=400
8127 23:18:45.975593 TX Vref=22, minBit 0, minWin=24, winSum=403
8128 23:18:45.985077 TX Vref=24, minBit 3, minWin=24, winSum=419
8129 23:18:45.985382 TX Vref=26, minBit 3, minWin=25, winSum=419
8130 23:18:45.988871 TX Vref=28, minBit 3, minWin=25, winSum=425
8131 23:18:45.991775 TX Vref=30, minBit 0, minWin=26, winSum=429
8132 23:18:45.995335 TX Vref=32, minBit 1, minWin=25, winSum=419
8133 23:18:45.998685 TX Vref=34, minBit 1, minWin=25, winSum=413
8134 23:18:46.001913 TX Vref=36, minBit 0, minWin=24, winSum=402
8135 23:18:46.009056 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 30
8136 23:18:46.009137
8137 23:18:46.011874 Final TX Range 0 Vref 30
8138 23:18:46.011954
8139 23:18:46.012018 ==
8140 23:18:46.015587 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 23:18:46.018810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 23:18:46.018891 ==
8143 23:18:46.018953
8144 23:18:46.019011
8145 23:18:46.022177 TX Vref Scan disable
8146 23:18:46.029073 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8147 23:18:46.029153 == TX Byte 0 ==
8148 23:18:46.032637 u2DelayCellOfst[0]=14 cells (4 PI)
8149 23:18:46.035480 u2DelayCellOfst[1]=21 cells (6 PI)
8150 23:18:46.038935 u2DelayCellOfst[2]=14 cells (4 PI)
8151 23:18:46.042304 u2DelayCellOfst[3]=14 cells (4 PI)
8152 23:18:46.045936 u2DelayCellOfst[4]=10 cells (3 PI)
8153 23:18:46.049035 u2DelayCellOfst[5]=0 cells (0 PI)
8154 23:18:46.052161 u2DelayCellOfst[6]=21 cells (6 PI)
8155 23:18:46.055866 u2DelayCellOfst[7]=21 cells (6 PI)
8156 23:18:46.059374 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8157 23:18:46.062912 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8158 23:18:46.065948 == TX Byte 1 ==
8159 23:18:46.066028 u2DelayCellOfst[8]=0 cells (0 PI)
8160 23:18:46.068853 u2DelayCellOfst[9]=0 cells (0 PI)
8161 23:18:46.072353 u2DelayCellOfst[10]=3 cells (1 PI)
8162 23:18:46.075536 u2DelayCellOfst[11]=0 cells (0 PI)
8163 23:18:46.078885 u2DelayCellOfst[12]=10 cells (3 PI)
8164 23:18:46.082032 u2DelayCellOfst[13]=7 cells (2 PI)
8165 23:18:46.085284 u2DelayCellOfst[14]=14 cells (4 PI)
8166 23:18:46.088581 u2DelayCellOfst[15]=7 cells (2 PI)
8167 23:18:46.092458 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8168 23:18:46.098779 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8169 23:18:46.098864 DramC Write-DBI on
8170 23:18:46.098955 ==
8171 23:18:46.101952 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 23:18:46.105258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 23:18:46.105339 ==
8174 23:18:46.108963
8175 23:18:46.109044
8176 23:18:46.109106 TX Vref Scan disable
8177 23:18:46.111792 == TX Byte 0 ==
8178 23:18:46.115609 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8179 23:18:46.118908 == TX Byte 1 ==
8180 23:18:46.122231 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8181 23:18:46.125071 DramC Write-DBI off
8182 23:18:46.125179
8183 23:18:46.125316 [DATLAT]
8184 23:18:46.125428 Freq=1600, CH0 RK1
8185 23:18:46.125514
8186 23:18:46.128681 DATLAT Default: 0xf
8187 23:18:46.128761 0, 0xFFFF, sum = 0
8188 23:18:46.132156 1, 0xFFFF, sum = 0
8189 23:18:46.132281 2, 0xFFFF, sum = 0
8190 23:18:46.135168 3, 0xFFFF, sum = 0
8191 23:18:46.138613 4, 0xFFFF, sum = 0
8192 23:18:46.138695 5, 0xFFFF, sum = 0
8193 23:18:46.141733 6, 0xFFFF, sum = 0
8194 23:18:46.141829 7, 0xFFFF, sum = 0
8195 23:18:46.145472 8, 0xFFFF, sum = 0
8196 23:18:46.145570 9, 0xFFFF, sum = 0
8197 23:18:46.148643 10, 0xFFFF, sum = 0
8198 23:18:46.148770 11, 0xFFFF, sum = 0
8199 23:18:46.152056 12, 0xFFFF, sum = 0
8200 23:18:46.152154 13, 0xFFFF, sum = 0
8201 23:18:46.155430 14, 0x0, sum = 1
8202 23:18:46.155527 15, 0x0, sum = 2
8203 23:18:46.159203 16, 0x0, sum = 3
8204 23:18:46.159302 17, 0x0, sum = 4
8205 23:18:46.162507 best_step = 15
8206 23:18:46.162605
8207 23:18:46.162698 ==
8208 23:18:46.165143 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 23:18:46.168665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 23:18:46.168747 ==
8211 23:18:46.168810 RX Vref Scan: 0
8212 23:18:46.168868
8213 23:18:46.171900 RX Vref 0 -> 0, step: 1
8214 23:18:46.171997
8215 23:18:46.175593 RX Delay 11 -> 252, step: 4
8216 23:18:46.179024 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8217 23:18:46.185437 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8218 23:18:46.188997 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8219 23:18:46.191847 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8220 23:18:46.195586 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8221 23:18:46.198880 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8222 23:18:46.202114 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8223 23:18:46.208705 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8224 23:18:46.211948 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8225 23:18:46.215715 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8226 23:18:46.218468 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8227 23:18:46.222289 iDelay=191, Bit 11, Center 114 (63 ~ 166) 104
8228 23:18:46.228647 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8229 23:18:46.232192 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8230 23:18:46.235133 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8231 23:18:46.238872 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8232 23:18:46.238949 ==
8233 23:18:46.242248 Dram Type= 6, Freq= 0, CH_0, rank 1
8234 23:18:46.248489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8235 23:18:46.248599 ==
8236 23:18:46.248693 DQS Delay:
8237 23:18:46.252223 DQS0 = 0, DQS1 = 0
8238 23:18:46.252324 DQM Delay:
8239 23:18:46.255237 DQM0 = 126, DQM1 = 122
8240 23:18:46.255336 DQ Delay:
8241 23:18:46.258787 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8242 23:18:46.262494 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =134
8243 23:18:46.265590 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =114
8244 23:18:46.268545 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8245 23:18:46.268632
8246 23:18:46.268695
8247 23:18:46.268752
8248 23:18:46.272065 [DramC_TX_OE_Calibration] TA2
8249 23:18:46.275672 Original DQ_B0 (3 6) =30, OEN = 27
8250 23:18:46.278944 Original DQ_B1 (3 6) =30, OEN = 27
8251 23:18:46.282385 24, 0x0, End_B0=24 End_B1=24
8252 23:18:46.282502 25, 0x0, End_B0=25 End_B1=25
8253 23:18:46.285438 26, 0x0, End_B0=26 End_B1=26
8254 23:18:46.289095 27, 0x0, End_B0=27 End_B1=27
8255 23:18:46.291796 28, 0x0, End_B0=28 End_B1=28
8256 23:18:46.295761 29, 0x0, End_B0=29 End_B1=29
8257 23:18:46.295842 30, 0x0, End_B0=30 End_B1=30
8258 23:18:46.298737 31, 0x4141, End_B0=30 End_B1=30
8259 23:18:46.301731 Byte0 end_step=30 best_step=27
8260 23:18:46.305293 Byte1 end_step=30 best_step=27
8261 23:18:46.308553 Byte0 TX OE(2T, 0.5T) = (3, 3)
8262 23:18:46.312125 Byte1 TX OE(2T, 0.5T) = (3, 3)
8263 23:18:46.312219
8264 23:18:46.312283
8265 23:18:46.318336 [DQSOSCAuto] RK1, (LSB)MR18= 0x170c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8266 23:18:46.322086 CH0 RK1: MR19=303, MR18=170C
8267 23:18:46.328744 CH0_RK1: MR19=0x303, MR18=0x170C, DQSOSC=398, MR23=63, INC=23, DEC=15
8268 23:18:46.331684 [RxdqsGatingPostProcess] freq 1600
8269 23:18:46.335403 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8270 23:18:46.338439 best DQS0 dly(2T, 0.5T) = (1, 1)
8271 23:18:46.341785 best DQS1 dly(2T, 0.5T) = (1, 1)
8272 23:18:46.345355 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8273 23:18:46.348455 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8274 23:18:46.352037 best DQS0 dly(2T, 0.5T) = (1, 1)
8275 23:18:46.355674 best DQS1 dly(2T, 0.5T) = (1, 1)
8276 23:18:46.358712 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8277 23:18:46.361784 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8278 23:18:46.365088 Pre-setting of DQS Precalculation
8279 23:18:46.368413 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8280 23:18:46.368494 ==
8281 23:18:46.372007 Dram Type= 6, Freq= 0, CH_1, rank 0
8282 23:18:46.375078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 23:18:46.375197 ==
8284 23:18:46.381853 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8285 23:18:46.385231 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8286 23:18:46.392240 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8287 23:18:46.394906 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8288 23:18:46.405193 [CA 0] Center 43 (15~72) winsize 58
8289 23:18:46.408289 [CA 1] Center 43 (14~72) winsize 59
8290 23:18:46.411537 [CA 2] Center 39 (11~67) winsize 57
8291 23:18:46.414993 [CA 3] Center 37 (8~67) winsize 60
8292 23:18:46.418176 [CA 4] Center 38 (8~68) winsize 61
8293 23:18:46.422004 [CA 5] Center 37 (8~66) winsize 59
8294 23:18:46.422091
8295 23:18:46.425113 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8296 23:18:46.425207
8297 23:18:46.428637 [CATrainingPosCal] consider 1 rank data
8298 23:18:46.431901 u2DelayCellTimex100 = 275/100 ps
8299 23:18:46.435554 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8300 23:18:46.441947 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8301 23:18:46.445056 CA2 delay=39 (11~67),Diff = 2 PI (7 cell)
8302 23:18:46.448275 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8303 23:18:46.451617 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8304 23:18:46.455442 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8305 23:18:46.455544
8306 23:18:46.458717 CA PerBit enable=1, Macro0, CA PI delay=37
8307 23:18:46.458797
8308 23:18:46.462248 [CBTSetCACLKResult] CA Dly = 37
8309 23:18:46.465170 CS Dly: 8 (0~39)
8310 23:18:46.468487 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8311 23:18:46.471953 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8312 23:18:46.472033 ==
8313 23:18:46.475157 Dram Type= 6, Freq= 0, CH_1, rank 1
8314 23:18:46.478818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8315 23:18:46.478899 ==
8316 23:18:46.485460 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8317 23:18:46.488449 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8318 23:18:46.495685 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8319 23:18:46.498860 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8320 23:18:46.508629 [CA 0] Center 42 (13~72) winsize 60
8321 23:18:46.511558 [CA 1] Center 43 (14~72) winsize 59
8322 23:18:46.514925 [CA 2] Center 38 (9~67) winsize 59
8323 23:18:46.518182 [CA 3] Center 36 (7~66) winsize 60
8324 23:18:46.521959 [CA 4] Center 37 (8~67) winsize 60
8325 23:18:46.525271 [CA 5] Center 36 (6~66) winsize 61
8326 23:18:46.525351
8327 23:18:46.528549 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8328 23:18:46.528629
8329 23:18:46.531822 [CATrainingPosCal] consider 2 rank data
8330 23:18:46.535560 u2DelayCellTimex100 = 275/100 ps
8331 23:18:46.538387 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8332 23:18:46.544827 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8333 23:18:46.548468 CA2 delay=39 (11~67),Diff = 2 PI (7 cell)
8334 23:18:46.552133 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8335 23:18:46.555078 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8336 23:18:46.558334 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8337 23:18:46.558437
8338 23:18:46.561393 CA PerBit enable=1, Macro0, CA PI delay=37
8339 23:18:46.561476
8340 23:18:46.565413 [CBTSetCACLKResult] CA Dly = 37
8341 23:18:46.568126 CS Dly: 10 (0~44)
8342 23:18:46.571820 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8343 23:18:46.575210 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8344 23:18:46.575290
8345 23:18:46.578615 ----->DramcWriteLeveling(PI) begin...
8346 23:18:46.578726 ==
8347 23:18:46.581671 Dram Type= 6, Freq= 0, CH_1, rank 0
8348 23:18:46.585181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8349 23:18:46.588190 ==
8350 23:18:46.588288 Write leveling (Byte 0): 23 => 23
8351 23:18:46.591465 Write leveling (Byte 1): 28 => 28
8352 23:18:46.594872 DramcWriteLeveling(PI) end<-----
8353 23:18:46.594943
8354 23:18:46.595016 ==
8355 23:18:46.598161 Dram Type= 6, Freq= 0, CH_1, rank 0
8356 23:18:46.604811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8357 23:18:46.604919 ==
8358 23:18:46.605008 [Gating] SW mode calibration
8359 23:18:46.615197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8360 23:18:46.618520 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8361 23:18:46.621939 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 23:18:46.628036 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 23:18:46.631834 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 23:18:46.635081 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 23:18:46.641753 1 4 16 | B1->B0 | 2f2f 2727 | 1 0 | (0 0) (0 0)
8366 23:18:46.644887 1 4 20 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
8367 23:18:46.648320 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 23:18:46.654689 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 23:18:46.658235 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 23:18:46.661706 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 23:18:46.668331 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 23:18:46.671410 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 23:18:46.675121 1 5 16 | B1->B0 | 2b2b 3131 | 1 0 | (1 0) (0 0)
8374 23:18:46.681684 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8375 23:18:46.685184 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 23:18:46.688182 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 23:18:46.694689 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 23:18:46.698190 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 23:18:46.701367 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 23:18:46.708131 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 23:18:46.711454 1 6 16 | B1->B0 | 4545 3c3c | 0 1 | (0 0) (0 0)
8382 23:18:46.714648 1 6 20 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8383 23:18:46.721628 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 23:18:46.725332 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 23:18:46.727998 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 23:18:46.731719 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 23:18:46.738365 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 23:18:46.741280 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 23:18:46.744473 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8390 23:18:46.751274 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 23:18:46.755078 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 23:18:46.758067 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 23:18:46.764835 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 23:18:46.767860 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 23:18:46.771384 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 23:18:46.777663 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 23:18:46.781342 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 23:18:46.784917 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 23:18:46.791086 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 23:18:46.794767 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 23:18:46.797806 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 23:18:46.804520 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 23:18:46.807898 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 23:18:46.811393 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8405 23:18:46.818061 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8406 23:18:46.821378 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 23:18:46.824769 Total UI for P1: 0, mck2ui 16
8408 23:18:46.827835 best dqsien dly found for B0: ( 1, 9, 14)
8409 23:18:46.831423 Total UI for P1: 0, mck2ui 16
8410 23:18:46.834567 best dqsien dly found for B1: ( 1, 9, 16)
8411 23:18:46.837776 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8412 23:18:46.841170 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8413 23:18:46.841251
8414 23:18:46.844665 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8415 23:18:46.847820 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8416 23:18:46.851397 [Gating] SW calibration Done
8417 23:18:46.851478 ==
8418 23:18:46.854692 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 23:18:46.858250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 23:18:46.858358 ==
8421 23:18:46.861916 RX Vref Scan: 0
8422 23:18:46.861997
8423 23:18:46.864777 RX Vref 0 -> 0, step: 1
8424 23:18:46.864857
8425 23:18:46.864919 RX Delay 0 -> 252, step: 8
8426 23:18:46.871506 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8427 23:18:46.875041 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8428 23:18:46.878166 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8429 23:18:46.881611 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8430 23:18:46.884714 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8431 23:18:46.891874 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8432 23:18:46.894717 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8433 23:18:46.898197 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8434 23:18:46.901402 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8435 23:18:46.904563 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8436 23:18:46.911473 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8437 23:18:46.914634 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8438 23:18:46.917550 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8439 23:18:46.921024 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8440 23:18:46.924229 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8441 23:18:46.931036 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8442 23:18:46.931117 ==
8443 23:18:46.934386 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 23:18:46.937999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 23:18:46.938080 ==
8446 23:18:46.938143 DQS Delay:
8447 23:18:46.940888 DQS0 = 0, DQS1 = 0
8448 23:18:46.940969 DQM Delay:
8449 23:18:46.944286 DQM0 = 135, DQM1 = 127
8450 23:18:46.944367 DQ Delay:
8451 23:18:46.947967 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8452 23:18:46.950851 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =135
8453 23:18:46.954436 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8454 23:18:46.957609 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8455 23:18:46.957691
8456 23:18:46.961030
8457 23:18:46.961110 ==
8458 23:18:46.964048 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 23:18:46.967569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 23:18:46.967651 ==
8461 23:18:46.967712
8462 23:18:46.967771
8463 23:18:46.970817 TX Vref Scan disable
8464 23:18:46.970896 == TX Byte 0 ==
8465 23:18:46.974420 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8466 23:18:46.980974 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8467 23:18:46.981054 == TX Byte 1 ==
8468 23:18:46.987409 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8469 23:18:46.991016 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8470 23:18:46.991096 ==
8471 23:18:46.994148 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 23:18:46.997334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 23:18:46.997414 ==
8474 23:18:47.010683
8475 23:18:47.014252 TX Vref early break, caculate TX vref
8476 23:18:47.017444 TX Vref=16, minBit 8, minWin=20, winSum=370
8477 23:18:47.020688 TX Vref=18, minBit 8, minWin=21, winSum=372
8478 23:18:47.024091 TX Vref=20, minBit 5, minWin=22, winSum=384
8479 23:18:47.027659 TX Vref=22, minBit 8, minWin=22, winSum=392
8480 23:18:47.031124 TX Vref=24, minBit 5, minWin=24, winSum=404
8481 23:18:47.037814 TX Vref=26, minBit 8, minWin=24, winSum=414
8482 23:18:47.040699 TX Vref=28, minBit 8, minWin=25, winSum=420
8483 23:18:47.044143 TX Vref=30, minBit 8, minWin=24, winSum=419
8484 23:18:47.047933 TX Vref=32, minBit 8, minWin=24, winSum=409
8485 23:18:47.051312 TX Vref=34, minBit 8, minWin=23, winSum=398
8486 23:18:47.057723 [TxChooseVref] Worse bit 8, Min win 25, Win sum 420, Final Vref 28
8487 23:18:47.057803
8488 23:18:47.060651 Final TX Range 0 Vref 28
8489 23:18:47.060732
8490 23:18:47.060794 ==
8491 23:18:47.064137 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 23:18:47.067704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 23:18:47.067784 ==
8494 23:18:47.067846
8495 23:18:47.067903
8496 23:18:47.070818 TX Vref Scan disable
8497 23:18:47.077277 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8498 23:18:47.077365 == TX Byte 0 ==
8499 23:18:47.080629 u2DelayCellOfst[0]=17 cells (5 PI)
8500 23:18:47.084121 u2DelayCellOfst[1]=14 cells (4 PI)
8501 23:18:47.087488 u2DelayCellOfst[2]=0 cells (0 PI)
8502 23:18:47.090819 u2DelayCellOfst[3]=7 cells (2 PI)
8503 23:18:47.094031 u2DelayCellOfst[4]=7 cells (2 PI)
8504 23:18:47.097658 u2DelayCellOfst[5]=17 cells (5 PI)
8505 23:18:47.097733 u2DelayCellOfst[6]=17 cells (5 PI)
8506 23:18:47.101327 u2DelayCellOfst[7]=3 cells (1 PI)
8507 23:18:47.107586 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8508 23:18:47.110643 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8509 23:18:47.110725 == TX Byte 1 ==
8510 23:18:47.114153 u2DelayCellOfst[8]=0 cells (0 PI)
8511 23:18:47.117718 u2DelayCellOfst[9]=3 cells (1 PI)
8512 23:18:47.120944 u2DelayCellOfst[10]=10 cells (3 PI)
8513 23:18:47.124207 u2DelayCellOfst[11]=7 cells (2 PI)
8514 23:18:47.127725 u2DelayCellOfst[12]=14 cells (4 PI)
8515 23:18:47.130600 u2DelayCellOfst[13]=14 cells (4 PI)
8516 23:18:47.133944 u2DelayCellOfst[14]=17 cells (5 PI)
8517 23:18:47.137439 u2DelayCellOfst[15]=17 cells (5 PI)
8518 23:18:47.140808 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8519 23:18:47.144456 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8520 23:18:47.147713 DramC Write-DBI on
8521 23:18:47.147816 ==
8522 23:18:47.150524 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 23:18:47.154524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 23:18:47.154624 ==
8525 23:18:47.154716
8526 23:18:47.154803
8527 23:18:47.157664 TX Vref Scan disable
8528 23:18:47.161036 == TX Byte 0 ==
8529 23:18:47.164291 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8530 23:18:47.164399 == TX Byte 1 ==
8531 23:18:47.170970 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8532 23:18:47.171068 DramC Write-DBI off
8533 23:18:47.171132
8534 23:18:47.174362 [DATLAT]
8535 23:18:47.174494 Freq=1600, CH1 RK0
8536 23:18:47.174560
8537 23:18:47.177637 DATLAT Default: 0xf
8538 23:18:47.177712 0, 0xFFFF, sum = 0
8539 23:18:47.181280 1, 0xFFFF, sum = 0
8540 23:18:47.181381 2, 0xFFFF, sum = 0
8541 23:18:47.184694 3, 0xFFFF, sum = 0
8542 23:18:47.184796 4, 0xFFFF, sum = 0
8543 23:18:47.187696 5, 0xFFFF, sum = 0
8544 23:18:47.187799 6, 0xFFFF, sum = 0
8545 23:18:47.191154 7, 0xFFFF, sum = 0
8546 23:18:47.191257 8, 0xFFFF, sum = 0
8547 23:18:47.194391 9, 0xFFFF, sum = 0
8548 23:18:47.194509 10, 0xFFFF, sum = 0
8549 23:18:47.197739 11, 0xFFFF, sum = 0
8550 23:18:47.197833 12, 0xFFFF, sum = 0
8551 23:18:47.201096 13, 0xFFFF, sum = 0
8552 23:18:47.201190 14, 0x0, sum = 1
8553 23:18:47.204486 15, 0x0, sum = 2
8554 23:18:47.204572 16, 0x0, sum = 3
8555 23:18:47.207506 17, 0x0, sum = 4
8556 23:18:47.207593 best_step = 15
8557 23:18:47.207655
8558 23:18:47.207725 ==
8559 23:18:47.210745 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 23:18:47.218043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 23:18:47.218156 ==
8562 23:18:47.218246 RX Vref Scan: 1
8563 23:18:47.218342
8564 23:18:47.221235 Set Vref Range= 24 -> 127
8565 23:18:47.221306
8566 23:18:47.224110 RX Vref 24 -> 127, step: 1
8567 23:18:47.224209
8568 23:18:47.227715 RX Delay 11 -> 252, step: 4
8569 23:18:47.227811
8570 23:18:47.231173 Set Vref, RX VrefLevel [Byte0]: 24
8571 23:18:47.231270 [Byte1]: 24
8572 23:18:47.235268
8573 23:18:47.235368 Set Vref, RX VrefLevel [Byte0]: 25
8574 23:18:47.238428 [Byte1]: 25
8575 23:18:47.242990
8576 23:18:47.243084 Set Vref, RX VrefLevel [Byte0]: 26
8577 23:18:47.246133 [Byte1]: 26
8578 23:18:47.250299
8579 23:18:47.250430 Set Vref, RX VrefLevel [Byte0]: 27
8580 23:18:47.254102 [Byte1]: 27
8581 23:18:47.258453
8582 23:18:47.258534 Set Vref, RX VrefLevel [Byte0]: 28
8583 23:18:47.261912 [Byte1]: 28
8584 23:18:47.265647
8585 23:18:47.265746 Set Vref, RX VrefLevel [Byte0]: 29
8586 23:18:47.269100 [Byte1]: 29
8587 23:18:47.273156
8588 23:18:47.273254 Set Vref, RX VrefLevel [Byte0]: 30
8589 23:18:47.276667 [Byte1]: 30
8590 23:18:47.281274
8591 23:18:47.281371 Set Vref, RX VrefLevel [Byte0]: 31
8592 23:18:47.284134 [Byte1]: 31
8593 23:18:47.288691
8594 23:18:47.288795 Set Vref, RX VrefLevel [Byte0]: 32
8595 23:18:47.291683 [Byte1]: 32
8596 23:18:47.296190
8597 23:18:47.296262 Set Vref, RX VrefLevel [Byte0]: 33
8598 23:18:47.299968 [Byte1]: 33
8599 23:18:47.303871
8600 23:18:47.303947 Set Vref, RX VrefLevel [Byte0]: 34
8601 23:18:47.307133 [Byte1]: 34
8602 23:18:47.311215
8603 23:18:47.311289 Set Vref, RX VrefLevel [Byte0]: 35
8604 23:18:47.314807 [Byte1]: 35
8605 23:18:47.319225
8606 23:18:47.319326 Set Vref, RX VrefLevel [Byte0]: 36
8607 23:18:47.322272 [Byte1]: 36
8608 23:18:47.326975
8609 23:18:47.327054 Set Vref, RX VrefLevel [Byte0]: 37
8610 23:18:47.330187 [Byte1]: 37
8611 23:18:47.334223
8612 23:18:47.334362 Set Vref, RX VrefLevel [Byte0]: 38
8613 23:18:47.337492 [Byte1]: 38
8614 23:18:47.342324
8615 23:18:47.342452 Set Vref, RX VrefLevel [Byte0]: 39
8616 23:18:47.345213 [Byte1]: 39
8617 23:18:47.349307
8618 23:18:47.349409 Set Vref, RX VrefLevel [Byte0]: 40
8619 23:18:47.352865 [Byte1]: 40
8620 23:18:47.356914
8621 23:18:47.357009 Set Vref, RX VrefLevel [Byte0]: 41
8622 23:18:47.360637 [Byte1]: 41
8623 23:18:47.364686
8624 23:18:47.364783 Set Vref, RX VrefLevel [Byte0]: 42
8625 23:18:47.368283 [Byte1]: 42
8626 23:18:47.372555
8627 23:18:47.372632 Set Vref, RX VrefLevel [Byte0]: 43
8628 23:18:47.375418 [Byte1]: 43
8629 23:18:47.380097
8630 23:18:47.380184 Set Vref, RX VrefLevel [Byte0]: 44
8631 23:18:47.383551 [Byte1]: 44
8632 23:18:47.387708
8633 23:18:47.387776 Set Vref, RX VrefLevel [Byte0]: 45
8634 23:18:47.390622 [Byte1]: 45
8635 23:18:47.395102
8636 23:18:47.395179 Set Vref, RX VrefLevel [Byte0]: 46
8637 23:18:47.398583 [Byte1]: 46
8638 23:18:47.402863
8639 23:18:47.402931 Set Vref, RX VrefLevel [Byte0]: 47
8640 23:18:47.406068 [Byte1]: 47
8641 23:18:47.410321
8642 23:18:47.410452 Set Vref, RX VrefLevel [Byte0]: 48
8643 23:18:47.413657 [Byte1]: 48
8644 23:18:47.417753
8645 23:18:47.417862 Set Vref, RX VrefLevel [Byte0]: 49
8646 23:18:47.421182 [Byte1]: 49
8647 23:18:47.425345
8648 23:18:47.425440 Set Vref, RX VrefLevel [Byte0]: 50
8649 23:18:47.429000 [Byte1]: 50
8650 23:18:47.433303
8651 23:18:47.433408 Set Vref, RX VrefLevel [Byte0]: 51
8652 23:18:47.436806 [Byte1]: 51
8653 23:18:47.441208
8654 23:18:47.441315 Set Vref, RX VrefLevel [Byte0]: 52
8655 23:18:47.444254 [Byte1]: 52
8656 23:18:47.448428
8657 23:18:47.448537 Set Vref, RX VrefLevel [Byte0]: 53
8658 23:18:47.452046 [Byte1]: 53
8659 23:18:47.456164
8660 23:18:47.456267 Set Vref, RX VrefLevel [Byte0]: 54
8661 23:18:47.459635 [Byte1]: 54
8662 23:18:47.463569
8663 23:18:47.463667 Set Vref, RX VrefLevel [Byte0]: 55
8664 23:18:47.466965 [Byte1]: 55
8665 23:18:47.471248
8666 23:18:47.471323 Set Vref, RX VrefLevel [Byte0]: 56
8667 23:18:47.474539 [Byte1]: 56
8668 23:18:47.478993
8669 23:18:47.479095 Set Vref, RX VrefLevel [Byte0]: 57
8670 23:18:47.482408 [Byte1]: 57
8671 23:18:47.486312
8672 23:18:47.486433 Set Vref, RX VrefLevel [Byte0]: 58
8673 23:18:47.489607 [Byte1]: 58
8674 23:18:47.494048
8675 23:18:47.494145 Set Vref, RX VrefLevel [Byte0]: 59
8676 23:18:47.497382 [Byte1]: 59
8677 23:18:47.501597
8678 23:18:47.501694 Set Vref, RX VrefLevel [Byte0]: 60
8679 23:18:47.504989 [Byte1]: 60
8680 23:18:47.509309
8681 23:18:47.509407 Set Vref, RX VrefLevel [Byte0]: 61
8682 23:18:47.512525 [Byte1]: 61
8683 23:18:47.516883
8684 23:18:47.516977 Set Vref, RX VrefLevel [Byte0]: 62
8685 23:18:47.520117 [Byte1]: 62
8686 23:18:47.524597
8687 23:18:47.524702 Set Vref, RX VrefLevel [Byte0]: 63
8688 23:18:47.527680 [Byte1]: 63
8689 23:18:47.532347
8690 23:18:47.532444 Set Vref, RX VrefLevel [Byte0]: 64
8691 23:18:47.535329 [Byte1]: 64
8692 23:18:47.539841
8693 23:18:47.539939 Set Vref, RX VrefLevel [Byte0]: 65
8694 23:18:47.543289 [Byte1]: 65
8695 23:18:47.547288
8696 23:18:47.547384 Set Vref, RX VrefLevel [Byte0]: 66
8697 23:18:47.550619 [Byte1]: 66
8698 23:18:47.555110
8699 23:18:47.555211 Set Vref, RX VrefLevel [Byte0]: 67
8700 23:18:47.558285 [Byte1]: 67
8701 23:18:47.562792
8702 23:18:47.562866 Set Vref, RX VrefLevel [Byte0]: 68
8703 23:18:47.565923 [Byte1]: 68
8704 23:18:47.570556
8705 23:18:47.570631 Set Vref, RX VrefLevel [Byte0]: 69
8706 23:18:47.573446 [Byte1]: 69
8707 23:18:47.578272
8708 23:18:47.578393 Set Vref, RX VrefLevel [Byte0]: 70
8709 23:18:47.580923 [Byte1]: 70
8710 23:18:47.585665
8711 23:18:47.585764 Set Vref, RX VrefLevel [Byte0]: 71
8712 23:18:47.588535 [Byte1]: 71
8713 23:18:47.593293
8714 23:18:47.593397 Set Vref, RX VrefLevel [Byte0]: 72
8715 23:18:47.596312 [Byte1]: 72
8716 23:18:47.600629
8717 23:18:47.600731 Set Vref, RX VrefLevel [Byte0]: 73
8718 23:18:47.603806 [Byte1]: 73
8719 23:18:47.608199
8720 23:18:47.608307 Set Vref, RX VrefLevel [Byte0]: 74
8721 23:18:47.611585 [Byte1]: 74
8722 23:18:47.615772
8723 23:18:47.615876 Final RX Vref Byte 0 = 60 to rank0
8724 23:18:47.619291 Final RX Vref Byte 1 = 55 to rank0
8725 23:18:47.622868 Final RX Vref Byte 0 = 60 to rank1
8726 23:18:47.626580 Final RX Vref Byte 1 = 55 to rank1==
8727 23:18:47.629058 Dram Type= 6, Freq= 0, CH_1, rank 0
8728 23:18:47.636082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8729 23:18:47.636185 ==
8730 23:18:47.636277 DQS Delay:
8731 23:18:47.636364 DQS0 = 0, DQS1 = 0
8732 23:18:47.639348 DQM Delay:
8733 23:18:47.639442 DQM0 = 131, DQM1 = 124
8734 23:18:47.642947 DQ Delay:
8735 23:18:47.646492 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8736 23:18:47.649959 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8737 23:18:47.652685 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8738 23:18:47.656334 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8739 23:18:47.656431
8740 23:18:47.656523
8741 23:18:47.656606
8742 23:18:47.659955 [DramC_TX_OE_Calibration] TA2
8743 23:18:47.662418 Original DQ_B0 (3 6) =30, OEN = 27
8744 23:18:47.665898 Original DQ_B1 (3 6) =30, OEN = 27
8745 23:18:47.669646 24, 0x0, End_B0=24 End_B1=24
8746 23:18:47.669728 25, 0x0, End_B0=25 End_B1=25
8747 23:18:47.672592 26, 0x0, End_B0=26 End_B1=26
8748 23:18:47.675890 27, 0x0, End_B0=27 End_B1=27
8749 23:18:47.679365 28, 0x0, End_B0=28 End_B1=28
8750 23:18:47.679446 29, 0x0, End_B0=29 End_B1=29
8751 23:18:47.682913 30, 0x0, End_B0=30 End_B1=30
8752 23:18:47.685969 31, 0x4141, End_B0=30 End_B1=30
8753 23:18:47.689084 Byte0 end_step=30 best_step=27
8754 23:18:47.692376 Byte1 end_step=30 best_step=27
8755 23:18:47.695777 Byte0 TX OE(2T, 0.5T) = (3, 3)
8756 23:18:47.695857 Byte1 TX OE(2T, 0.5T) = (3, 3)
8757 23:18:47.699419
8758 23:18:47.699500
8759 23:18:47.705909 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fd, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8760 23:18:47.709370 CH1 RK0: MR19=302, MR18=13FD
8761 23:18:47.715729 CH1_RK0: MR19=0x302, MR18=0x13FD, DQSOSC=400, MR23=63, INC=23, DEC=15
8762 23:18:47.715834
8763 23:18:47.719655 ----->DramcWriteLeveling(PI) begin...
8764 23:18:47.719757 ==
8765 23:18:47.722254 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 23:18:47.726040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8767 23:18:47.726121 ==
8768 23:18:47.728943 Write leveling (Byte 0): 23 => 23
8769 23:18:47.732789 Write leveling (Byte 1): 27 => 27
8770 23:18:47.735678 DramcWriteLeveling(PI) end<-----
8771 23:18:47.735758
8772 23:18:47.735820 ==
8773 23:18:47.739003 Dram Type= 6, Freq= 0, CH_1, rank 1
8774 23:18:47.742631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 23:18:47.742711 ==
8776 23:18:47.745343 [Gating] SW mode calibration
8777 23:18:47.752135 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8778 23:18:47.759356 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8779 23:18:47.762303 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 23:18:47.765951 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 23:18:47.772425 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8782 23:18:47.775876 1 4 12 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
8783 23:18:47.779154 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 23:18:47.785537 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 23:18:47.789061 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 23:18:47.792297 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 23:18:47.798971 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 23:18:47.802203 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8789 23:18:47.805553 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 0)
8790 23:18:47.812247 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (1 0)
8791 23:18:47.815613 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8792 23:18:47.819371 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 23:18:47.825447 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 23:18:47.828782 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 23:18:47.832287 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 23:18:47.835538 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 23:18:47.842813 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8798 23:18:47.845441 1 6 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
8799 23:18:47.848914 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 23:18:47.855682 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 23:18:47.859004 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 23:18:47.862822 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 23:18:47.869196 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 23:18:47.872023 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 23:18:47.875578 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8806 23:18:47.882322 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8807 23:18:47.885658 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 23:18:47.888842 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8809 23:18:47.895788 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 23:18:47.899086 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 23:18:47.902073 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 23:18:47.908855 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 23:18:47.912470 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 23:18:47.915497 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 23:18:47.922697 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 23:18:47.926061 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 23:18:47.928718 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 23:18:47.932620 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 23:18:47.938925 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 23:18:47.942335 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8821 23:18:47.945763 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8822 23:18:47.952461 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8823 23:18:47.955598 Total UI for P1: 0, mck2ui 16
8824 23:18:47.959211 best dqsien dly found for B0: ( 1, 9, 6)
8825 23:18:47.962276 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8826 23:18:47.965555 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 23:18:47.969169 Total UI for P1: 0, mck2ui 16
8828 23:18:47.972458 best dqsien dly found for B1: ( 1, 9, 12)
8829 23:18:47.976039 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8830 23:18:47.979055 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8831 23:18:47.979131
8832 23:18:47.985552 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8833 23:18:47.988936 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8834 23:18:47.989054 [Gating] SW calibration Done
8835 23:18:47.992673 ==
8836 23:18:47.995498 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 23:18:47.998903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 23:18:47.998976 ==
8839 23:18:47.999059 RX Vref Scan: 0
8840 23:18:47.999144
8841 23:18:48.002120 RX Vref 0 -> 0, step: 1
8842 23:18:48.002216
8843 23:18:48.005933 RX Delay 0 -> 252, step: 8
8844 23:18:48.009001 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8845 23:18:48.012434 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8846 23:18:48.016063 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8847 23:18:48.022669 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8848 23:18:48.025533 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8849 23:18:48.028846 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8850 23:18:48.032430 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8851 23:18:48.035436 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8852 23:18:48.042488 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8853 23:18:48.045410 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8854 23:18:48.048798 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8855 23:18:48.052264 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8856 23:18:48.055587 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8857 23:18:48.062674 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8858 23:18:48.065584 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8859 23:18:48.068641 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8860 23:18:48.068726 ==
8861 23:18:48.072158 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 23:18:48.075616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 23:18:48.075697 ==
8864 23:18:48.079069 DQS Delay:
8865 23:18:48.079149 DQS0 = 0, DQS1 = 0
8866 23:18:48.082077 DQM Delay:
8867 23:18:48.082157 DQM0 = 132, DQM1 = 128
8868 23:18:48.082220 DQ Delay:
8869 23:18:48.089123 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8870 23:18:48.091928 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8871 23:18:48.095550 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8872 23:18:48.098946 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8873 23:18:48.099026
8874 23:18:48.099088
8875 23:18:48.099144 ==
8876 23:18:48.102010 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 23:18:48.105657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 23:18:48.105738 ==
8879 23:18:48.105801
8880 23:18:48.105859
8881 23:18:48.108490 TX Vref Scan disable
8882 23:18:48.111804 == TX Byte 0 ==
8883 23:18:48.115681 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8884 23:18:48.118432 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8885 23:18:48.122137 == TX Byte 1 ==
8886 23:18:48.125255 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8887 23:18:48.128826 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8888 23:18:48.128907 ==
8889 23:18:48.131920 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 23:18:48.135270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 23:18:48.138565 ==
8892 23:18:48.151318
8893 23:18:48.154443 TX Vref early break, caculate TX vref
8894 23:18:48.157900 TX Vref=16, minBit 8, minWin=21, winSum=380
8895 23:18:48.160880 TX Vref=18, minBit 9, minWin=22, winSum=387
8896 23:18:48.164201 TX Vref=20, minBit 11, minWin=23, winSum=400
8897 23:18:48.167627 TX Vref=22, minBit 9, minWin=24, winSum=401
8898 23:18:48.171602 TX Vref=24, minBit 8, minWin=25, winSum=416
8899 23:18:48.178038 TX Vref=26, minBit 11, minWin=25, winSum=421
8900 23:18:48.181248 TX Vref=28, minBit 15, minWin=25, winSum=427
8901 23:18:48.184640 TX Vref=30, minBit 5, minWin=25, winSum=423
8902 23:18:48.188026 TX Vref=32, minBit 1, minWin=25, winSum=418
8903 23:18:48.191149 TX Vref=34, minBit 8, minWin=24, winSum=408
8904 23:18:48.194332 TX Vref=36, minBit 8, minWin=23, winSum=398
8905 23:18:48.201121 [TxChooseVref] Worse bit 15, Min win 25, Win sum 427, Final Vref 28
8906 23:18:48.201249
8907 23:18:48.204195 Final TX Range 0 Vref 28
8908 23:18:48.204293
8909 23:18:48.204375 ==
8910 23:18:48.207878 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 23:18:48.211259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 23:18:48.211342 ==
8913 23:18:48.211425
8914 23:18:48.211503
8915 23:18:48.214715 TX Vref Scan disable
8916 23:18:48.221076 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8917 23:18:48.221158 == TX Byte 0 ==
8918 23:18:48.224582 u2DelayCellOfst[0]=17 cells (5 PI)
8919 23:18:48.227577 u2DelayCellOfst[1]=10 cells (3 PI)
8920 23:18:48.231121 u2DelayCellOfst[2]=0 cells (0 PI)
8921 23:18:48.234853 u2DelayCellOfst[3]=7 cells (2 PI)
8922 23:18:48.237506 u2DelayCellOfst[4]=7 cells (2 PI)
8923 23:18:48.241129 u2DelayCellOfst[5]=17 cells (5 PI)
8924 23:18:48.244635 u2DelayCellOfst[6]=17 cells (5 PI)
8925 23:18:48.247826 u2DelayCellOfst[7]=3 cells (1 PI)
8926 23:18:48.251005 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8927 23:18:48.254591 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8928 23:18:48.257784 == TX Byte 1 ==
8929 23:18:48.261562 u2DelayCellOfst[8]=0 cells (0 PI)
8930 23:18:48.261645 u2DelayCellOfst[9]=3 cells (1 PI)
8931 23:18:48.264713 u2DelayCellOfst[10]=10 cells (3 PI)
8932 23:18:48.267920 u2DelayCellOfst[11]=7 cells (2 PI)
8933 23:18:48.271395 u2DelayCellOfst[12]=14 cells (4 PI)
8934 23:18:48.274357 u2DelayCellOfst[13]=14 cells (4 PI)
8935 23:18:48.278130 u2DelayCellOfst[14]=17 cells (5 PI)
8936 23:18:48.280864 u2DelayCellOfst[15]=14 cells (4 PI)
8937 23:18:48.284393 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8938 23:18:48.291089 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8939 23:18:48.291169 DramC Write-DBI on
8940 23:18:48.291238 ==
8941 23:18:48.294796 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 23:18:48.298053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 23:18:48.301086 ==
8944 23:18:48.301189
8945 23:18:48.301301
8946 23:18:48.301399 TX Vref Scan disable
8947 23:18:48.304656 == TX Byte 0 ==
8948 23:18:48.308129 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8949 23:18:48.311454 == TX Byte 1 ==
8950 23:18:48.314476 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8951 23:18:48.314582 DramC Write-DBI off
8952 23:18:48.318128
8953 23:18:48.318209 [DATLAT]
8954 23:18:48.318271 Freq=1600, CH1 RK1
8955 23:18:48.318330
8956 23:18:48.321164 DATLAT Default: 0xf
8957 23:18:48.321261 0, 0xFFFF, sum = 0
8958 23:18:48.324807 1, 0xFFFF, sum = 0
8959 23:18:48.324903 2, 0xFFFF, sum = 0
8960 23:18:48.328266 3, 0xFFFF, sum = 0
8961 23:18:48.328347 4, 0xFFFF, sum = 0
8962 23:18:48.331697 5, 0xFFFF, sum = 0
8963 23:18:48.334482 6, 0xFFFF, sum = 0
8964 23:18:48.334565 7, 0xFFFF, sum = 0
8965 23:18:48.337806 8, 0xFFFF, sum = 0
8966 23:18:48.337887 9, 0xFFFF, sum = 0
8967 23:18:48.341402 10, 0xFFFF, sum = 0
8968 23:18:48.341483 11, 0xFFFF, sum = 0
8969 23:18:48.344862 12, 0xFFFF, sum = 0
8970 23:18:48.344943 13, 0xFFFF, sum = 0
8971 23:18:48.348282 14, 0x0, sum = 1
8972 23:18:48.348363 15, 0x0, sum = 2
8973 23:18:48.351550 16, 0x0, sum = 3
8974 23:18:48.351635 17, 0x0, sum = 4
8975 23:18:48.354567 best_step = 15
8976 23:18:48.354647
8977 23:18:48.354708 ==
8978 23:18:48.358250 Dram Type= 6, Freq= 0, CH_1, rank 1
8979 23:18:48.361173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8980 23:18:48.361250 ==
8981 23:18:48.361312 RX Vref Scan: 0
8982 23:18:48.361370
8983 23:18:48.364938 RX Vref 0 -> 0, step: 1
8984 23:18:48.365012
8985 23:18:48.368140 RX Delay 11 -> 252, step: 4
8986 23:18:48.371284 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8987 23:18:48.378166 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8988 23:18:48.381666 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8989 23:18:48.384693 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8990 23:18:48.388500 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8991 23:18:48.391083 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8992 23:18:48.394493 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8993 23:18:48.401421 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
8994 23:18:48.404458 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8995 23:18:48.408111 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8996 23:18:48.411301 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8997 23:18:48.414403 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8998 23:18:48.420979 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8999 23:18:48.424403 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
9000 23:18:48.428010 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
9001 23:18:48.431291 iDelay=191, Bit 15, Center 136 (83 ~ 190) 108
9002 23:18:48.431390 ==
9003 23:18:48.434380 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 23:18:48.441204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 23:18:48.441306 ==
9006 23:18:48.441395 DQS Delay:
9007 23:18:48.444648 DQS0 = 0, DQS1 = 0
9008 23:18:48.444717 DQM Delay:
9009 23:18:48.444774 DQM0 = 129, DQM1 = 126
9010 23:18:48.448367 DQ Delay:
9011 23:18:48.451066 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9012 23:18:48.454708 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
9013 23:18:48.458007 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9014 23:18:48.461215 DQ12 =134, DQ13 =134, DQ14 =132, DQ15 =136
9015 23:18:48.461297
9016 23:18:48.461379
9017 23:18:48.461471
9018 23:18:48.464566 [DramC_TX_OE_Calibration] TA2
9019 23:18:48.468384 Original DQ_B0 (3 6) =30, OEN = 27
9020 23:18:48.471317 Original DQ_B1 (3 6) =30, OEN = 27
9021 23:18:48.474645 24, 0x0, End_B0=24 End_B1=24
9022 23:18:48.474728 25, 0x0, End_B0=25 End_B1=25
9023 23:18:48.478139 26, 0x0, End_B0=26 End_B1=26
9024 23:18:48.481709 27, 0x0, End_B0=27 End_B1=27
9025 23:18:48.484659 28, 0x0, End_B0=28 End_B1=28
9026 23:18:48.484743 29, 0x0, End_B0=29 End_B1=29
9027 23:18:48.487986 30, 0x0, End_B0=30 End_B1=30
9028 23:18:48.491320 31, 0x4141, End_B0=30 End_B1=30
9029 23:18:48.494822 Byte0 end_step=30 best_step=27
9030 23:18:48.498168 Byte1 end_step=30 best_step=27
9031 23:18:48.502139 Byte0 TX OE(2T, 0.5T) = (3, 3)
9032 23:18:48.502222 Byte1 TX OE(2T, 0.5T) = (3, 3)
9033 23:18:48.502320
9034 23:18:48.502442
9035 23:18:48.511743 [DQSOSCAuto] RK1, (LSB)MR18= 0xd13, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
9036 23:18:48.514964 CH1 RK1: MR19=303, MR18=D13
9037 23:18:48.518205 CH1_RK1: MR19=0x303, MR18=0xD13, DQSOSC=400, MR23=63, INC=23, DEC=15
9038 23:18:48.521515 [RxdqsGatingPostProcess] freq 1600
9039 23:18:48.528968 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9040 23:18:48.532431 best DQS0 dly(2T, 0.5T) = (1, 1)
9041 23:18:48.535528 best DQS1 dly(2T, 0.5T) = (1, 1)
9042 23:18:48.539029 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9043 23:18:48.542008 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9044 23:18:48.545680 best DQS0 dly(2T, 0.5T) = (1, 1)
9045 23:18:48.545762 best DQS1 dly(2T, 0.5T) = (1, 1)
9046 23:18:48.548762 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9047 23:18:48.552005 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9048 23:18:48.555428 Pre-setting of DQS Precalculation
9049 23:18:48.562130 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9050 23:18:48.568674 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9051 23:18:48.574891 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9052 23:18:48.574974
9053 23:18:48.575055
9054 23:18:48.578236 [Calibration Summary] 3200 Mbps
9055 23:18:48.578343 CH 0, Rank 0
9056 23:18:48.581669 SW Impedance : PASS
9057 23:18:48.584977 DUTY Scan : NO K
9058 23:18:48.585059 ZQ Calibration : PASS
9059 23:18:48.588267 Jitter Meter : NO K
9060 23:18:48.592014 CBT Training : PASS
9061 23:18:48.592098 Write leveling : PASS
9062 23:18:48.594759 RX DQS gating : PASS
9063 23:18:48.598213 RX DQ/DQS(RDDQC) : PASS
9064 23:18:48.598292 TX DQ/DQS : PASS
9065 23:18:48.601865 RX DATLAT : PASS
9066 23:18:48.604896 RX DQ/DQS(Engine): PASS
9067 23:18:48.604975 TX OE : PASS
9068 23:18:48.607996 All Pass.
9069 23:18:48.608075
9070 23:18:48.608136 CH 0, Rank 1
9071 23:18:48.611415 SW Impedance : PASS
9072 23:18:48.611501 DUTY Scan : NO K
9073 23:18:48.614889 ZQ Calibration : PASS
9074 23:18:48.618170 Jitter Meter : NO K
9075 23:18:48.618248 CBT Training : PASS
9076 23:18:48.621849 Write leveling : PASS
9077 23:18:48.621928 RX DQS gating : PASS
9078 23:18:48.624687 RX DQ/DQS(RDDQC) : PASS
9079 23:18:48.627891 TX DQ/DQS : PASS
9080 23:18:48.627971 RX DATLAT : PASS
9081 23:18:48.631873 RX DQ/DQS(Engine): PASS
9082 23:18:48.634560 TX OE : PASS
9083 23:18:48.634639 All Pass.
9084 23:18:48.634700
9085 23:18:48.634756 CH 1, Rank 0
9086 23:18:48.638150 SW Impedance : PASS
9087 23:18:48.641634 DUTY Scan : NO K
9088 23:18:48.641713 ZQ Calibration : PASS
9089 23:18:48.644990 Jitter Meter : NO K
9090 23:18:48.648303 CBT Training : PASS
9091 23:18:48.648382 Write leveling : PASS
9092 23:18:48.651616 RX DQS gating : PASS
9093 23:18:48.654653 RX DQ/DQS(RDDQC) : PASS
9094 23:18:48.654735 TX DQ/DQS : PASS
9095 23:18:48.658521 RX DATLAT : PASS
9096 23:18:48.661393 RX DQ/DQS(Engine): PASS
9097 23:18:48.661475 TX OE : PASS
9098 23:18:48.661563 All Pass.
9099 23:18:48.664873
9100 23:18:48.664955 CH 1, Rank 1
9101 23:18:48.668259 SW Impedance : PASS
9102 23:18:48.668341 DUTY Scan : NO K
9103 23:18:48.671626 ZQ Calibration : PASS
9104 23:18:48.674515 Jitter Meter : NO K
9105 23:18:48.674597 CBT Training : PASS
9106 23:18:48.677956 Write leveling : PASS
9107 23:18:48.678038 RX DQS gating : PASS
9108 23:18:48.681189 RX DQ/DQS(RDDQC) : PASS
9109 23:18:48.684888 TX DQ/DQS : PASS
9110 23:18:48.684970 RX DATLAT : PASS
9111 23:18:48.687685 RX DQ/DQS(Engine): PASS
9112 23:18:48.691070 TX OE : PASS
9113 23:18:48.691155 All Pass.
9114 23:18:48.691240
9115 23:18:48.694297 DramC Write-DBI on
9116 23:18:48.694379 PER_BANK_REFRESH: Hybrid Mode
9117 23:18:48.697831 TX_TRACKING: ON
9118 23:18:48.708014 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9119 23:18:48.714159 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9120 23:18:48.721145 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9121 23:18:48.724331 [FAST_K] Save calibration result to emmc
9122 23:18:48.727595 sync common calibartion params.
9123 23:18:48.731292 sync cbt_mode0:1, 1:1
9124 23:18:48.731373 dram_init: ddr_geometry: 2
9125 23:18:48.734316 dram_init: ddr_geometry: 2
9126 23:18:48.737785 dram_init: ddr_geometry: 2
9127 23:18:48.740979 0:dram_rank_size:100000000
9128 23:18:48.741079 1:dram_rank_size:100000000
9129 23:18:48.747332 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9130 23:18:48.751379 DFS_SHUFFLE_HW_MODE: ON
9131 23:18:48.753996 dramc_set_vcore_voltage set vcore to 725000
9132 23:18:48.754096 Read voltage for 1600, 0
9133 23:18:48.757428 Vio18 = 0
9134 23:18:48.757532 Vcore = 725000
9135 23:18:48.757624 Vdram = 0
9136 23:18:48.760798 Vddq = 0
9137 23:18:48.760894 Vmddr = 0
9138 23:18:48.764054 switch to 3200 Mbps bootup
9139 23:18:48.764159 [DramcRunTimeConfig]
9140 23:18:48.767489 PHYPLL
9141 23:18:48.767574 DPM_CONTROL_AFTERK: ON
9142 23:18:48.770466 PER_BANK_REFRESH: ON
9143 23:18:48.773783 REFRESH_OVERHEAD_REDUCTION: ON
9144 23:18:48.773896 CMD_PICG_NEW_MODE: OFF
9145 23:18:48.777363 XRTWTW_NEW_MODE: ON
9146 23:18:48.777458 XRTRTR_NEW_MODE: ON
9147 23:18:48.780430 TX_TRACKING: ON
9148 23:18:48.780538 RDSEL_TRACKING: OFF
9149 23:18:48.784305 DQS Precalculation for DVFS: ON
9150 23:18:48.787444 RX_TRACKING: OFF
9151 23:18:48.787530 HW_GATING DBG: ON
9152 23:18:48.790952 ZQCS_ENABLE_LP4: ON
9153 23:18:48.791030 RX_PICG_NEW_MODE: ON
9154 23:18:48.794240 TX_PICG_NEW_MODE: ON
9155 23:18:48.794346 ENABLE_RX_DCM_DPHY: ON
9156 23:18:48.796912 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9157 23:18:48.800690 DUMMY_READ_FOR_TRACKING: OFF
9158 23:18:48.803777 !!! SPM_CONTROL_AFTERK: OFF
9159 23:18:48.807750 !!! SPM could not control APHY
9160 23:18:48.807860 IMPEDANCE_TRACKING: ON
9161 23:18:48.810496 TEMP_SENSOR: ON
9162 23:18:48.810569 HW_SAVE_FOR_SR: OFF
9163 23:18:48.813764 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9164 23:18:48.817361 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9165 23:18:48.820367 Read ODT Tracking: ON
9166 23:18:48.823862 Refresh Rate DeBounce: ON
9167 23:18:48.823934 DFS_NO_QUEUE_FLUSH: ON
9168 23:18:48.827409 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9169 23:18:48.830765 ENABLE_DFS_RUNTIME_MRW: OFF
9170 23:18:48.833815 DDR_RESERVE_NEW_MODE: ON
9171 23:18:48.833914 MR_CBT_SWITCH_FREQ: ON
9172 23:18:48.837312 =========================
9173 23:18:48.855858 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9174 23:18:48.859222 dram_init: ddr_geometry: 2
9175 23:18:48.877300 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9176 23:18:48.880542 dram_init: dram init end (result: 0)
9177 23:18:48.887580 DRAM-K: Full calibration passed in 24586 msecs
9178 23:18:48.890626 MRC: failed to locate region type 0.
9179 23:18:48.890709 DRAM rank0 size:0x100000000,
9180 23:18:48.894310 DRAM rank1 size=0x100000000
9181 23:18:48.904224 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9182 23:18:48.911144 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9183 23:18:48.917466 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9184 23:18:48.924620 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9185 23:18:48.927394 DRAM rank0 size:0x100000000,
9186 23:18:48.931211 DRAM rank1 size=0x100000000
9187 23:18:48.931341 CBMEM:
9188 23:18:48.934380 IMD: root @ 0xfffff000 254 entries.
9189 23:18:48.937756 IMD: root @ 0xffffec00 62 entries.
9190 23:18:48.941429 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9191 23:18:48.944822 WARNING: RO_VPD is uninitialized or empty.
9192 23:18:48.950932 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9193 23:18:48.957445 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9194 23:18:48.970067 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9195 23:18:48.981426 BS: romstage times (exec / console): total (unknown) / 24089 ms
9196 23:18:48.981537
9197 23:18:48.981601
9198 23:18:48.991718 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9199 23:18:48.995136 ARM64: Exception handlers installed.
9200 23:18:48.998243 ARM64: Testing exception
9201 23:18:49.001632 ARM64: Done test exception
9202 23:18:49.001709 Enumerating buses...
9203 23:18:49.004815 Show all devs... Before device enumeration.
9204 23:18:49.008204 Root Device: enabled 1
9205 23:18:49.011465 CPU_CLUSTER: 0: enabled 1
9206 23:18:49.011546 CPU: 00: enabled 1
9207 23:18:49.014710 Compare with tree...
9208 23:18:49.014782 Root Device: enabled 1
9209 23:18:49.018180 CPU_CLUSTER: 0: enabled 1
9210 23:18:49.021613 CPU: 00: enabled 1
9211 23:18:49.021709 Root Device scanning...
9212 23:18:49.024704 scan_static_bus for Root Device
9213 23:18:49.028235 CPU_CLUSTER: 0 enabled
9214 23:18:49.031757 scan_static_bus for Root Device done
9215 23:18:49.034581 scan_bus: bus Root Device finished in 8 msecs
9216 23:18:49.034663 done
9217 23:18:49.041608 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9218 23:18:49.044756 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9219 23:18:49.051541 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9220 23:18:49.055043 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9221 23:18:49.058202 Allocating resources...
9222 23:18:49.058323 Reading resources...
9223 23:18:49.064354 Root Device read_resources bus 0 link: 0
9224 23:18:49.064438 DRAM rank0 size:0x100000000,
9225 23:18:49.067810 DRAM rank1 size=0x100000000
9226 23:18:49.071527 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9227 23:18:49.074365 CPU: 00 missing read_resources
9228 23:18:49.078233 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9229 23:18:49.085019 Root Device read_resources bus 0 link: 0 done
9230 23:18:49.085102 Done reading resources.
9231 23:18:49.091295 Show resources in subtree (Root Device)...After reading.
9232 23:18:49.094197 Root Device child on link 0 CPU_CLUSTER: 0
9233 23:18:49.097693 CPU_CLUSTER: 0 child on link 0 CPU: 00
9234 23:18:49.107935 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9235 23:18:49.108017 CPU: 00
9236 23:18:49.110859 Root Device assign_resources, bus 0 link: 0
9237 23:18:49.114389 CPU_CLUSTER: 0 missing set_resources
9238 23:18:49.117740 Root Device assign_resources, bus 0 link: 0 done
9239 23:18:49.121370 Done setting resources.
9240 23:18:49.127518 Show resources in subtree (Root Device)...After assigning values.
9241 23:18:49.131144 Root Device child on link 0 CPU_CLUSTER: 0
9242 23:18:49.134965 CPU_CLUSTER: 0 child on link 0 CPU: 00
9243 23:18:49.144368 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9244 23:18:49.144451 CPU: 00
9245 23:18:49.147510 Done allocating resources.
9246 23:18:49.151026 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9247 23:18:49.154623 Enabling resources...
9248 23:18:49.154703 done.
9249 23:18:49.161222 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9250 23:18:49.161340 Initializing devices...
9251 23:18:49.164758 Root Device init
9252 23:18:49.164837 init hardware done!
9253 23:18:49.168320 0x00000018: ctrlr->caps
9254 23:18:49.171376 52.000 MHz: ctrlr->f_max
9255 23:18:49.171458 0.400 MHz: ctrlr->f_min
9256 23:18:49.174625 0x40ff8080: ctrlr->voltages
9257 23:18:49.174706 sclk: 390625
9258 23:18:49.177711 Bus Width = 1
9259 23:18:49.177790 sclk: 390625
9260 23:18:49.177852 Bus Width = 1
9261 23:18:49.181149 Early init status = 3
9262 23:18:49.184334 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9263 23:18:49.189300 in-header: 03 fc 00 00 01 00 00 00
9264 23:18:49.192447 in-data: 00
9265 23:18:49.195964 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9266 23:18:49.200269 in-header: 03 fd 00 00 00 00 00 00
9267 23:18:49.203966 in-data:
9268 23:18:49.207238 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9269 23:18:49.210664 in-header: 03 fc 00 00 01 00 00 00
9270 23:18:49.214373 in-data: 00
9271 23:18:49.217386 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9272 23:18:49.222884 in-header: 03 fd 00 00 00 00 00 00
9273 23:18:49.225861 in-data:
9274 23:18:49.229255 [SSUSB] Setting up USB HOST controller...
9275 23:18:49.232525 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9276 23:18:49.235804 [SSUSB] phy power-on done.
9277 23:18:49.239316 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9278 23:18:49.246109 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9279 23:18:49.249867 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9280 23:18:49.256047 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9281 23:18:49.263063 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9282 23:18:49.269736 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9283 23:18:49.276321 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9284 23:18:49.279652 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9285 23:18:49.283553 SPM: binary array size = 0x9dc
9286 23:18:49.289646 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9287 23:18:49.296321 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9288 23:18:49.303377 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9289 23:18:49.306601 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9290 23:18:49.309516 configure_display: Starting display init
9291 23:18:49.346307 anx7625_power_on_init: Init interface.
9292 23:18:49.349779 anx7625_disable_pd_protocol: Disabled PD feature.
9293 23:18:49.352320 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9294 23:18:49.380637 anx7625_start_dp_work: Secure OCM version=00
9295 23:18:49.383832 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9296 23:18:49.398319 sp_tx_get_edid_block: EDID Block = 1
9297 23:18:49.501022 Extracted contents:
9298 23:18:49.504402 header: 00 ff ff ff ff ff ff 00
9299 23:18:49.507598 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9300 23:18:49.510828 version: 01 04
9301 23:18:49.514240 basic params: 95 1f 11 78 0a
9302 23:18:49.517527 chroma info: 76 90 94 55 54 90 27 21 50 54
9303 23:18:49.520843 established: 00 00 00
9304 23:18:49.527213 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9305 23:18:49.530762 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9306 23:18:49.537424 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9307 23:18:49.544190 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9308 23:18:49.551362 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9309 23:18:49.554635 extensions: 00
9310 23:18:49.554716 checksum: fb
9311 23:18:49.554780
9312 23:18:49.557275 Manufacturer: IVO Model 57d Serial Number 0
9313 23:18:49.560765 Made week 0 of 2020
9314 23:18:49.560845 EDID version: 1.4
9315 23:18:49.563919 Digital display
9316 23:18:49.567714 6 bits per primary color channel
9317 23:18:49.567816 DisplayPort interface
9318 23:18:49.570785 Maximum image size: 31 cm x 17 cm
9319 23:18:49.574346 Gamma: 220%
9320 23:18:49.574479 Check DPMS levels
9321 23:18:49.577752 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9322 23:18:49.580585 First detailed timing is preferred timing
9323 23:18:49.584114 Established timings supported:
9324 23:18:49.587586 Standard timings supported:
9325 23:18:49.587681 Detailed timings
9326 23:18:49.593889 Hex of detail: 383680a07038204018303c0035ae10000019
9327 23:18:49.597214 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9328 23:18:49.603827 0780 0798 07c8 0820 hborder 0
9329 23:18:49.607250 0438 043b 0447 0458 vborder 0
9330 23:18:49.610649 -hsync -vsync
9331 23:18:49.610732 Did detailed timing
9332 23:18:49.613712 Hex of detail: 000000000000000000000000000000000000
9333 23:18:49.617653 Manufacturer-specified data, tag 0
9334 23:18:49.623604 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9335 23:18:49.623684 ASCII string: InfoVision
9336 23:18:49.630691 Hex of detail: 000000fe00523134304e574635205248200a
9337 23:18:49.633590 ASCII string: R140NWF5 RH
9338 23:18:49.633676 Checksum
9339 23:18:49.633738 Checksum: 0xfb (valid)
9340 23:18:49.640320 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9341 23:18:49.643778 DSI data_rate: 832800000 bps
9342 23:18:49.647331 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9343 23:18:49.653490 anx7625_parse_edid: pixelclock(138800).
9344 23:18:49.656949 hactive(1920), hsync(48), hfp(24), hbp(88)
9345 23:18:49.660454 vactive(1080), vsync(12), vfp(3), vbp(17)
9346 23:18:49.663603 anx7625_dsi_config: config dsi.
9347 23:18:49.670828 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9348 23:18:49.683414 anx7625_dsi_config: success to config DSI
9349 23:18:49.686615 anx7625_dp_start: MIPI phy setup OK.
9350 23:18:49.689727 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9351 23:18:49.693399 mtk_ddp_mode_set invalid vrefresh 60
9352 23:18:49.696264 main_disp_path_setup
9353 23:18:49.696343 ovl_layer_smi_id_en
9354 23:18:49.699340 ovl_layer_smi_id_en
9355 23:18:49.699421 ccorr_config
9356 23:18:49.699483 aal_config
9357 23:18:49.702911 gamma_config
9358 23:18:49.702991 postmask_config
9359 23:18:49.706232 dither_config
9360 23:18:49.709638 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9361 23:18:49.716540 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9362 23:18:49.719891 Root Device init finished in 552 msecs
9363 23:18:49.722717 CPU_CLUSTER: 0 init
9364 23:18:49.729255 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9365 23:18:49.733417 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9366 23:18:49.736858 APU_MBOX 0x190000b0 = 0x10001
9367 23:18:49.739367 APU_MBOX 0x190001b0 = 0x10001
9368 23:18:49.743111 APU_MBOX 0x190005b0 = 0x10001
9369 23:18:49.746193 APU_MBOX 0x190006b0 = 0x10001
9370 23:18:49.749139 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9371 23:18:49.762061 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9372 23:18:49.774431 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9373 23:18:49.780946 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9374 23:18:49.792877 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9375 23:18:49.802095 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9376 23:18:49.805122 CPU_CLUSTER: 0 init finished in 81 msecs
9377 23:18:49.808948 Devices initialized
9378 23:18:49.811749 Show all devs... After init.
9379 23:18:49.811830 Root Device: enabled 1
9380 23:18:49.815166 CPU_CLUSTER: 0: enabled 1
9381 23:18:49.818655 CPU: 00: enabled 1
9382 23:18:49.822183 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9383 23:18:49.825249 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9384 23:18:49.828484 ELOG: NV offset 0x57f000 size 0x1000
9385 23:18:49.835313 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9386 23:18:49.841874 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9387 23:18:49.844968 ELOG: Event(17) added with size 13 at 2024-04-03 23:18:51 UTC
9388 23:18:49.848420 out: cmd=0x121: 03 db 21 01 00 00 00 00
9389 23:18:49.853185 in-header: 03 d0 00 00 2c 00 00 00
9390 23:18:49.866205 in-data: 8f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9391 23:18:49.872683 ELOG: Event(A1) added with size 10 at 2024-04-03 23:18:51 UTC
9392 23:18:49.879707 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9393 23:18:49.886601 ELOG: Event(A0) added with size 9 at 2024-04-03 23:18:51 UTC
9394 23:18:49.889514 elog_add_boot_reason: Logged dev mode boot
9395 23:18:49.892865 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9396 23:18:49.896468 Finalize devices...
9397 23:18:49.896560 Devices finalized
9398 23:18:49.902826 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9399 23:18:49.906054 Writing coreboot table at 0xffe64000
9400 23:18:49.909979 0. 000000000010a000-0000000000113fff: RAMSTAGE
9401 23:18:49.913463 1. 0000000040000000-00000000400fffff: RAM
9402 23:18:49.916101 2. 0000000040100000-000000004032afff: RAMSTAGE
9403 23:18:49.923280 3. 000000004032b000-00000000545fffff: RAM
9404 23:18:49.926231 4. 0000000054600000-000000005465ffff: BL31
9405 23:18:49.929836 5. 0000000054660000-00000000ffe63fff: RAM
9406 23:18:49.933651 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9407 23:18:49.939658 7. 0000000100000000-000000023fffffff: RAM
9408 23:18:49.939736 Passing 5 GPIOs to payload:
9409 23:18:49.946351 NAME | PORT | POLARITY | VALUE
9410 23:18:49.950338 EC in RW | 0x000000aa | low | undefined
9411 23:18:49.953269 EC interrupt | 0x00000005 | low | undefined
9412 23:18:49.959790 TPM interrupt | 0x000000ab | high | undefined
9413 23:18:49.963222 SD card detect | 0x00000011 | high | undefined
9414 23:18:49.969937 speaker enable | 0x00000093 | high | undefined
9415 23:18:49.973175 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9416 23:18:49.976423 in-header: 03 f9 00 00 02 00 00 00
9417 23:18:49.976507 in-data: 02 00
9418 23:18:49.979926 ADC[4]: Raw value=900590 ID=7
9419 23:18:49.983459 ADC[3]: Raw value=213336 ID=1
9420 23:18:49.983539 RAM Code: 0x71
9421 23:18:49.986903 ADC[6]: Raw value=74557 ID=0
9422 23:18:49.989842 ADC[5]: Raw value=212229 ID=1
9423 23:18:49.989921 SKU Code: 0x1
9424 23:18:49.996446 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a82b
9425 23:18:50.000244 coreboot table: 964 bytes.
9426 23:18:50.003499 IMD ROOT 0. 0xfffff000 0x00001000
9427 23:18:50.006802 IMD SMALL 1. 0xffffe000 0x00001000
9428 23:18:50.009830 RO MCACHE 2. 0xffffc000 0x00001104
9429 23:18:50.013491 CONSOLE 3. 0xfff7c000 0x00080000
9430 23:18:50.016600 FMAP 4. 0xfff7b000 0x00000452
9431 23:18:50.016724 TIME STAMP 5. 0xfff7a000 0x00000910
9432 23:18:50.020113 VBOOT WORK 6. 0xfff66000 0x00014000
9433 23:18:50.023207 RAMOOPS 7. 0xffe66000 0x00100000
9434 23:18:50.026950 COREBOOT 8. 0xffe64000 0x00002000
9435 23:18:50.029825 IMD small region:
9436 23:18:50.033412 IMD ROOT 0. 0xffffec00 0x00000400
9437 23:18:50.036776 VPD 1. 0xffffeb80 0x0000006c
9438 23:18:50.040364 MMC STATUS 2. 0xffffeb60 0x00000004
9439 23:18:50.047246 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9440 23:18:50.047348 Probing TPM: done!
9441 23:18:50.053852 Connected to device vid:did:rid of 1ae0:0028:00
9442 23:18:50.059790 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9443 23:18:50.063866 Initialized TPM device CR50 revision 0
9444 23:18:50.066695 Checking cr50 for pending updates
9445 23:18:50.072400 Reading cr50 TPM mode
9446 23:18:50.081347 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9447 23:18:50.088082 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9448 23:18:50.127520 read SPI 0x3990ec 0x4f1b0: 34856 us, 9295 KB/s, 74.360 Mbps
9449 23:18:50.131076 Checking segment from ROM address 0x40100000
9450 23:18:50.134783 Checking segment from ROM address 0x4010001c
9451 23:18:50.141348 Loading segment from ROM address 0x40100000
9452 23:18:50.141439 code (compression=0)
9453 23:18:50.148488 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9454 23:18:50.158422 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9455 23:18:50.158519 it's not compressed!
9456 23:18:50.164936 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9457 23:18:50.167907 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9458 23:18:50.188129 Loading segment from ROM address 0x4010001c
9459 23:18:50.188217 Entry Point 0x80000000
9460 23:18:50.191610 Loaded segments
9461 23:18:50.195434 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9462 23:18:50.201402 Jumping to boot code at 0x80000000(0xffe64000)
9463 23:18:50.208449 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9464 23:18:50.214593 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9465 23:18:50.222838 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9466 23:18:50.226077 Checking segment from ROM address 0x40100000
9467 23:18:50.229261 Checking segment from ROM address 0x4010001c
9468 23:18:50.235907 Loading segment from ROM address 0x40100000
9469 23:18:50.235998 code (compression=1)
9470 23:18:50.242878 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9471 23:18:50.252627 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9472 23:18:50.252708 using LZMA
9473 23:18:50.261737 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9474 23:18:50.267723 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9475 23:18:50.271061 Loading segment from ROM address 0x4010001c
9476 23:18:50.271141 Entry Point 0x54601000
9477 23:18:50.274265 Loaded segments
9478 23:18:50.277771 NOTICE: MT8192 bl31_setup
9479 23:18:50.284413 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9480 23:18:50.287673 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9481 23:18:50.291935 WARNING: region 0:
9482 23:18:50.294950 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 23:18:50.295032 WARNING: region 1:
9484 23:18:50.301320 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9485 23:18:50.304822 WARNING: region 2:
9486 23:18:50.308174 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9487 23:18:50.311516 WARNING: region 3:
9488 23:18:50.314977 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9489 23:18:50.318719 WARNING: region 4:
9490 23:18:50.321691 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9491 23:18:50.324908 WARNING: region 5:
9492 23:18:50.327998 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 23:18:50.331404 WARNING: region 6:
9494 23:18:50.335276 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 23:18:50.335355 WARNING: region 7:
9496 23:18:50.341704 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 23:18:50.348272 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9498 23:18:50.351525 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9499 23:18:50.354790 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9500 23:18:50.361787 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9501 23:18:50.365631 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9502 23:18:50.368604 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9503 23:18:50.375111 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9504 23:18:50.378527 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9505 23:18:50.381745 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9506 23:18:50.388511 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9507 23:18:50.391870 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9508 23:18:50.395246 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9509 23:18:50.401902 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9510 23:18:50.405258 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9511 23:18:50.411968 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9512 23:18:50.415333 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9513 23:18:50.418751 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9514 23:18:50.425363 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9515 23:18:50.429031 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9516 23:18:50.431868 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9517 23:18:50.438565 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9518 23:18:50.442312 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9519 23:18:50.448767 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9520 23:18:50.452061 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9521 23:18:50.455460 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9522 23:18:50.462026 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9523 23:18:50.465371 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9524 23:18:50.468678 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9525 23:18:50.475563 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9526 23:18:50.479102 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9527 23:18:50.485568 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9528 23:18:50.488874 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9529 23:18:50.492241 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9530 23:18:50.496081 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9531 23:18:50.502368 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9532 23:18:50.506071 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9533 23:18:50.508953 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9534 23:18:50.512380 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9535 23:18:50.518929 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9536 23:18:50.522784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9537 23:18:50.525937 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9538 23:18:50.529291 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9539 23:18:50.535981 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9540 23:18:50.539454 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9541 23:18:50.542906 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9542 23:18:50.545971 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9543 23:18:50.552794 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9544 23:18:50.556074 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9545 23:18:50.559172 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9546 23:18:50.566155 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9547 23:18:50.569311 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9548 23:18:50.573027 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9549 23:18:50.579332 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9550 23:18:50.582894 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9551 23:18:50.589787 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9552 23:18:50.592882 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9553 23:18:50.600013 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9554 23:18:50.603182 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9555 23:18:50.606430 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9556 23:18:50.612844 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9557 23:18:50.616359 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9558 23:18:50.623321 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9559 23:18:50.626617 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9560 23:18:50.633327 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9561 23:18:50.636621 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9562 23:18:50.639846 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9563 23:18:50.646892 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9564 23:18:50.649756 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9565 23:18:50.656580 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9566 23:18:50.660108 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9567 23:18:50.666480 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9568 23:18:50.670113 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9569 23:18:50.673487 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9570 23:18:50.680136 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9571 23:18:50.683419 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9572 23:18:50.690385 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9573 23:18:50.693836 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9574 23:18:50.700187 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9575 23:18:50.703661 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9576 23:18:50.706862 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9577 23:18:50.713534 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9578 23:18:50.717125 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9579 23:18:50.723648 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9580 23:18:50.727493 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9581 23:18:50.730374 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9582 23:18:50.737119 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9583 23:18:50.740650 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9584 23:18:50.747111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9585 23:18:50.750693 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9586 23:18:50.757360 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9587 23:18:50.760721 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9588 23:18:50.763769 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9589 23:18:50.770467 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9590 23:18:50.774414 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9591 23:18:50.780929 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9592 23:18:50.784150 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9593 23:18:50.787808 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9594 23:18:50.793776 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9595 23:18:50.797232 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9596 23:18:50.800510 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9597 23:18:50.804100 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9598 23:18:50.810835 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9599 23:18:50.813986 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9600 23:18:50.821120 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9601 23:18:50.824329 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9602 23:18:50.827616 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9603 23:18:50.834240 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9604 23:18:50.837384 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9605 23:18:50.844385 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9606 23:18:50.847734 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9607 23:18:50.851681 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9608 23:18:50.857946 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9609 23:18:50.861108 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9610 23:18:50.864548 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9611 23:18:50.871297 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9612 23:18:50.874429 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9613 23:18:50.877935 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9614 23:18:50.884648 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9615 23:18:50.887805 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9616 23:18:50.891155 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9617 23:18:50.894861 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9618 23:18:50.901225 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9619 23:18:50.904836 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9620 23:18:50.908402 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9621 23:18:50.914602 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9622 23:18:50.918231 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9623 23:18:50.921431 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9624 23:18:50.928429 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9625 23:18:50.931602 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9626 23:18:50.938242 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9627 23:18:50.941665 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9628 23:18:50.944953 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9629 23:18:50.951752 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9630 23:18:50.955005 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9631 23:18:50.958292 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9632 23:18:50.965125 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9633 23:18:50.968457 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9634 23:18:50.975017 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9635 23:18:50.978182 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9636 23:18:50.981639 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9637 23:18:50.988586 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9638 23:18:50.991853 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9639 23:18:50.995202 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9640 23:18:51.001497 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9641 23:18:51.005044 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9642 23:18:51.011799 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9643 23:18:51.015038 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9644 23:18:51.018498 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9645 23:18:51.025218 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9646 23:18:51.028495 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9647 23:18:51.035343 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9648 23:18:51.038685 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9649 23:18:51.042300 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9650 23:18:51.048514 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9651 23:18:51.051960 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9652 23:18:51.055336 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9653 23:18:51.061995 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9654 23:18:51.065212 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9655 23:18:51.068980 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9656 23:18:51.075698 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9657 23:18:51.078585 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9658 23:18:51.085451 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9659 23:18:51.088712 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9660 23:18:51.091994 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9661 23:18:51.099235 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9662 23:18:51.101990 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9663 23:18:51.105774 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9664 23:18:51.112201 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9665 23:18:51.115425 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9666 23:18:51.122086 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9667 23:18:51.125839 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9668 23:18:51.129223 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9669 23:18:51.135804 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9670 23:18:51.138795 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9671 23:18:51.146335 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9672 23:18:51.149080 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9673 23:18:51.152186 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9674 23:18:51.159007 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9675 23:18:51.162472 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9676 23:18:51.166167 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9677 23:18:51.172401 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9678 23:18:51.175585 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9679 23:18:51.182499 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9680 23:18:51.185459 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9681 23:18:51.189184 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9682 23:18:51.195978 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9683 23:18:51.198887 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9684 23:18:51.205675 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9685 23:18:51.208882 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9686 23:18:51.212157 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9687 23:18:51.219082 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9688 23:18:51.222095 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9689 23:18:51.228870 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9690 23:18:51.232149 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9691 23:18:51.235422 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9692 23:18:51.242253 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9693 23:18:51.245117 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9694 23:18:51.252577 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9695 23:18:51.255167 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9696 23:18:51.262057 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9697 23:18:51.265369 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9698 23:18:51.268648 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9699 23:18:51.275665 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9700 23:18:51.279222 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9701 23:18:51.285257 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9702 23:18:51.288556 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9703 23:18:51.295361 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9704 23:18:51.298556 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9705 23:18:51.302434 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9706 23:18:51.308623 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9707 23:18:51.312637 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9708 23:18:51.319107 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9709 23:18:51.322295 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9710 23:18:51.325292 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9711 23:18:51.332221 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9712 23:18:51.335706 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9713 23:18:51.341910 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9714 23:18:51.345597 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9715 23:18:51.349315 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9716 23:18:51.355170 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9717 23:18:51.358491 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9718 23:18:51.365684 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9719 23:18:51.368574 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9720 23:18:51.371734 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9721 23:18:51.378724 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9722 23:18:51.382339 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9723 23:18:51.388437 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9724 23:18:51.391897 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9725 23:18:51.398640 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9726 23:18:51.401891 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9727 23:18:51.405059 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9728 23:18:51.408834 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9729 23:18:51.411839 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9730 23:18:51.418457 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9731 23:18:51.421832 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9732 23:18:51.425248 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9733 23:18:51.432165 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9734 23:18:51.435141 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9735 23:18:51.438389 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9736 23:18:51.445581 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9737 23:18:51.448781 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9738 23:18:51.455146 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9739 23:18:51.458536 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9740 23:18:51.461764 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9741 23:18:51.468505 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9742 23:18:51.472161 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9743 23:18:51.475534 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9744 23:18:51.481635 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9745 23:18:51.485251 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9746 23:18:51.488880 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9747 23:18:51.495501 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9748 23:18:51.498373 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9749 23:18:51.505347 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9750 23:18:51.509126 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9751 23:18:51.511815 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9752 23:18:51.518648 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9753 23:18:51.521667 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9754 23:18:51.525058 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9755 23:18:51.531792 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9756 23:18:51.535015 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9757 23:18:51.538449 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9758 23:18:51.545248 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9759 23:18:51.548441 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9760 23:18:51.551926 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9761 23:18:51.559301 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9762 23:18:51.561972 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9763 23:18:51.568803 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9764 23:18:51.572053 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9765 23:18:51.575394 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9766 23:18:51.578871 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9767 23:18:51.585722 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9768 23:18:51.588650 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9769 23:18:51.591899 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9770 23:18:51.595503 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9771 23:18:51.598933 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9772 23:18:51.605417 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9773 23:18:51.608837 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9774 23:18:51.612035 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9775 23:18:51.615507 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9776 23:18:51.622244 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9777 23:18:51.625445 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9778 23:18:51.629479 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9779 23:18:51.635956 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9780 23:18:51.638751 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9781 23:18:51.645936 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9782 23:18:51.648820 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9783 23:18:51.652211 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9784 23:18:51.658825 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9785 23:18:51.662150 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9786 23:18:51.669256 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9787 23:18:51.672408 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9788 23:18:51.675812 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9789 23:18:51.682363 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9790 23:18:51.685626 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9791 23:18:51.692269 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9792 23:18:51.695866 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9793 23:18:51.698862 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9794 23:18:51.705818 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9795 23:18:51.708922 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9796 23:18:51.712601 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9797 23:18:51.719027 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9798 23:18:51.722314 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9799 23:18:51.729162 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9800 23:18:51.732193 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9801 23:18:51.739412 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9802 23:18:51.742143 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9803 23:18:51.745701 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9804 23:18:51.752159 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9805 23:18:51.755744 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9806 23:18:51.762292 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9807 23:18:51.765564 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9808 23:18:51.769195 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9809 23:18:51.775549 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9810 23:18:51.779570 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9811 23:18:51.785407 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9812 23:18:51.788971 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9813 23:18:51.792039 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9814 23:18:51.799091 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9815 23:18:51.802322 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9816 23:18:51.809530 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9817 23:18:51.812565 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9818 23:18:51.816097 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9819 23:18:51.822978 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9820 23:18:51.825543 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9821 23:18:51.832199 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9822 23:18:51.835724 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9823 23:18:51.838818 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9824 23:18:51.845772 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9825 23:18:51.849164 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9826 23:18:51.855988 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9827 23:18:51.859182 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9828 23:18:51.862437 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9829 23:18:51.869122 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9830 23:18:51.872142 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9831 23:18:51.878799 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9832 23:18:51.882604 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9833 23:18:51.885973 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9834 23:18:51.892215 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9835 23:18:51.895650 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9836 23:18:51.902572 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9837 23:18:51.905343 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9838 23:18:51.909067 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9839 23:18:51.915765 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9840 23:18:51.919156 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9841 23:18:51.925645 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9842 23:18:51.929127 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9843 23:18:51.932272 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9844 23:18:51.939133 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9845 23:18:51.942298 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9846 23:18:51.948886 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9847 23:18:51.951971 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9848 23:18:51.958530 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9849 23:18:51.961920 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9850 23:18:51.966059 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9851 23:18:51.972285 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9852 23:18:51.975368 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9853 23:18:51.982126 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9854 23:18:51.985401 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9855 23:18:51.991884 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9856 23:18:51.995069 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9857 23:18:51.998326 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9858 23:18:52.005716 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9859 23:18:52.008723 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9860 23:18:52.014994 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9861 23:18:52.018705 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9862 23:18:52.025599 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9863 23:18:52.028669 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9864 23:18:52.032347 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9865 23:18:52.039003 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9866 23:18:52.042225 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9867 23:18:52.048382 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9868 23:18:52.051771 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9869 23:18:52.058224 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9870 23:18:52.061840 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9871 23:18:52.064982 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9872 23:18:52.071863 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9873 23:18:52.075023 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9874 23:18:52.082247 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9875 23:18:52.085120 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9876 23:18:52.088923 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9877 23:18:52.095519 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9878 23:18:52.098651 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9879 23:18:52.105526 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9880 23:18:52.109112 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9881 23:18:52.115470 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9882 23:18:52.118669 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9883 23:18:52.122081 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9884 23:18:52.128563 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9885 23:18:52.132354 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9886 23:18:52.139321 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9887 23:18:52.142458 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9888 23:18:52.148708 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9889 23:18:52.152035 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9890 23:18:52.155509 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9891 23:18:52.162758 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9892 23:18:52.165574 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9893 23:18:52.172160 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9894 23:18:52.175484 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9895 23:18:52.182253 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9896 23:18:52.185709 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9897 23:18:52.189031 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9898 23:18:52.195721 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9899 23:18:52.199227 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9900 23:18:52.206050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9901 23:18:52.208744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9902 23:18:52.212138 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9903 23:18:52.218967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9904 23:18:52.222377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9905 23:18:52.229385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9906 23:18:52.232378 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9907 23:18:52.238969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9908 23:18:52.242290 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9909 23:18:52.248789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9910 23:18:52.252353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9911 23:18:52.259119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9912 23:18:52.262256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9913 23:18:52.269027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9914 23:18:52.272328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9915 23:18:52.278901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9916 23:18:52.282172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9917 23:18:52.289622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9918 23:18:52.292714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9919 23:18:52.299181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9920 23:18:52.302152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9921 23:18:52.309182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9922 23:18:52.312437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9923 23:18:52.319337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9924 23:18:52.322355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9925 23:18:52.329031 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9926 23:18:52.332594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9927 23:18:52.339198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9928 23:18:52.342083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9929 23:18:52.348959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9930 23:18:52.352819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9931 23:18:52.355609 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9932 23:18:52.358814 INFO: [APUAPC] vio 0
9933 23:18:52.362673 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9934 23:18:52.369081 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9935 23:18:52.372715 INFO: [APUAPC] D0_APC_0: 0x400510
9936 23:18:52.375821 INFO: [APUAPC] D0_APC_1: 0x0
9937 23:18:52.379141 INFO: [APUAPC] D0_APC_2: 0x1540
9938 23:18:52.379257 INFO: [APUAPC] D0_APC_3: 0x0
9939 23:18:52.382296 INFO: [APUAPC] D1_APC_0: 0xffffffff
9940 23:18:52.386106 INFO: [APUAPC] D1_APC_1: 0xffffffff
9941 23:18:52.388877 INFO: [APUAPC] D1_APC_2: 0x3fffff
9942 23:18:52.392042 INFO: [APUAPC] D1_APC_3: 0x0
9943 23:18:52.395356 INFO: [APUAPC] D2_APC_0: 0xffffffff
9944 23:18:52.398807 INFO: [APUAPC] D2_APC_1: 0xffffffff
9945 23:18:52.402213 INFO: [APUAPC] D2_APC_2: 0x3fffff
9946 23:18:52.405658 INFO: [APUAPC] D2_APC_3: 0x0
9947 23:18:52.408925 INFO: [APUAPC] D3_APC_0: 0xffffffff
9948 23:18:52.412081 INFO: [APUAPC] D3_APC_1: 0xffffffff
9949 23:18:52.415635 INFO: [APUAPC] D3_APC_2: 0x3fffff
9950 23:18:52.419369 INFO: [APUAPC] D3_APC_3: 0x0
9951 23:18:52.422026 INFO: [APUAPC] D4_APC_0: 0xffffffff
9952 23:18:52.425757 INFO: [APUAPC] D4_APC_1: 0xffffffff
9953 23:18:52.429132 INFO: [APUAPC] D4_APC_2: 0x3fffff
9954 23:18:52.432120 INFO: [APUAPC] D4_APC_3: 0x0
9955 23:18:52.435682 INFO: [APUAPC] D5_APC_0: 0xffffffff
9956 23:18:52.439268 INFO: [APUAPC] D5_APC_1: 0xffffffff
9957 23:18:52.442630 INFO: [APUAPC] D5_APC_2: 0x3fffff
9958 23:18:52.446116 INFO: [APUAPC] D5_APC_3: 0x0
9959 23:18:52.448903 INFO: [APUAPC] D6_APC_0: 0xffffffff
9960 23:18:52.453033 INFO: [APUAPC] D6_APC_1: 0xffffffff
9961 23:18:52.455650 INFO: [APUAPC] D6_APC_2: 0x3fffff
9962 23:18:52.459341 INFO: [APUAPC] D6_APC_3: 0x0
9963 23:18:52.462187 INFO: [APUAPC] D7_APC_0: 0xffffffff
9964 23:18:52.465571 INFO: [APUAPC] D7_APC_1: 0xffffffff
9965 23:18:52.469064 INFO: [APUAPC] D7_APC_2: 0x3fffff
9966 23:18:52.472753 INFO: [APUAPC] D7_APC_3: 0x0
9967 23:18:52.476333 INFO: [APUAPC] D8_APC_0: 0xffffffff
9968 23:18:52.479351 INFO: [APUAPC] D8_APC_1: 0xffffffff
9969 23:18:52.482529 INFO: [APUAPC] D8_APC_2: 0x3fffff
9970 23:18:52.486231 INFO: [APUAPC] D8_APC_3: 0x0
9971 23:18:52.489223 INFO: [APUAPC] D9_APC_0: 0xffffffff
9972 23:18:52.492470 INFO: [APUAPC] D9_APC_1: 0xffffffff
9973 23:18:52.495690 INFO: [APUAPC] D9_APC_2: 0x3fffff
9974 23:18:52.499168 INFO: [APUAPC] D9_APC_3: 0x0
9975 23:18:52.502883 INFO: [APUAPC] D10_APC_0: 0xffffffff
9976 23:18:52.505861 INFO: [APUAPC] D10_APC_1: 0xffffffff
9977 23:18:52.508932 INFO: [APUAPC] D10_APC_2: 0x3fffff
9978 23:18:52.512567 INFO: [APUAPC] D10_APC_3: 0x0
9979 23:18:52.515882 INFO: [APUAPC] D11_APC_0: 0xffffffff
9980 23:18:52.519451 INFO: [APUAPC] D11_APC_1: 0xffffffff
9981 23:18:52.522228 INFO: [APUAPC] D11_APC_2: 0x3fffff
9982 23:18:52.525551 INFO: [APUAPC] D11_APC_3: 0x0
9983 23:18:52.528993 INFO: [APUAPC] D12_APC_0: 0xffffffff
9984 23:18:52.532196 INFO: [APUAPC] D12_APC_1: 0xffffffff
9985 23:18:52.535935 INFO: [APUAPC] D12_APC_2: 0x3fffff
9986 23:18:52.539179 INFO: [APUAPC] D12_APC_3: 0x0
9987 23:18:52.542517 INFO: [APUAPC] D13_APC_0: 0xffffffff
9988 23:18:52.546254 INFO: [APUAPC] D13_APC_1: 0xffffffff
9989 23:18:52.549626 INFO: [APUAPC] D13_APC_2: 0x3fffff
9990 23:18:52.552568 INFO: [APUAPC] D13_APC_3: 0x0
9991 23:18:52.555832 INFO: [APUAPC] D14_APC_0: 0xffffffff
9992 23:18:52.559103 INFO: [APUAPC] D14_APC_1: 0xffffffff
9993 23:18:52.562642 INFO: [APUAPC] D14_APC_2: 0x3fffff
9994 23:18:52.565996 INFO: [APUAPC] D14_APC_3: 0x0
9995 23:18:52.568951 INFO: [APUAPC] D15_APC_0: 0xffffffff
9996 23:18:52.572455 INFO: [APUAPC] D15_APC_1: 0xffffffff
9997 23:18:52.575695 INFO: [APUAPC] D15_APC_2: 0x3fffff
9998 23:18:52.579399 INFO: [APUAPC] D15_APC_3: 0x0
9999 23:18:52.579488 INFO: [APUAPC] APC_CON: 0x4
10000 23:18:52.582259 INFO: [NOCDAPC] D0_APC_0: 0x0
10001 23:18:52.586216 INFO: [NOCDAPC] D0_APC_1: 0x0
10002 23:18:52.588966 INFO: [NOCDAPC] D1_APC_0: 0x0
10003 23:18:52.592466 INFO: [NOCDAPC] D1_APC_1: 0xfff
10004 23:18:52.595717 INFO: [NOCDAPC] D2_APC_0: 0x0
10005 23:18:52.599207 INFO: [NOCDAPC] D2_APC_1: 0xfff
10006 23:18:52.602439 INFO: [NOCDAPC] D3_APC_0: 0x0
10007 23:18:52.605773 INFO: [NOCDAPC] D3_APC_1: 0xfff
10008 23:18:52.605854 INFO: [NOCDAPC] D4_APC_0: 0x0
10009 23:18:52.609231 INFO: [NOCDAPC] D4_APC_1: 0xfff
10010 23:18:52.612404 INFO: [NOCDAPC] D5_APC_0: 0x0
10011 23:18:52.615601 INFO: [NOCDAPC] D5_APC_1: 0xfff
10012 23:18:52.618899 INFO: [NOCDAPC] D6_APC_0: 0x0
10013 23:18:52.622758 INFO: [NOCDAPC] D6_APC_1: 0xfff
10014 23:18:52.625638 INFO: [NOCDAPC] D7_APC_0: 0x0
10015 23:18:52.629152 INFO: [NOCDAPC] D7_APC_1: 0xfff
10016 23:18:52.632398 INFO: [NOCDAPC] D8_APC_0: 0x0
10017 23:18:52.635857 INFO: [NOCDAPC] D8_APC_1: 0xfff
10018 23:18:52.635955 INFO: [NOCDAPC] D9_APC_0: 0x0
10019 23:18:52.639106 INFO: [NOCDAPC] D9_APC_1: 0xfff
10020 23:18:52.642363 INFO: [NOCDAPC] D10_APC_0: 0x0
10021 23:18:52.646173 INFO: [NOCDAPC] D10_APC_1: 0xfff
10022 23:18:52.648854 INFO: [NOCDAPC] D11_APC_0: 0x0
10023 23:18:52.652574 INFO: [NOCDAPC] D11_APC_1: 0xfff
10024 23:18:52.656119 INFO: [NOCDAPC] D12_APC_0: 0x0
10025 23:18:52.658893 INFO: [NOCDAPC] D12_APC_1: 0xfff
10026 23:18:52.662454 INFO: [NOCDAPC] D13_APC_0: 0x0
10027 23:18:52.665845 INFO: [NOCDAPC] D13_APC_1: 0xfff
10028 23:18:52.669109 INFO: [NOCDAPC] D14_APC_0: 0x0
10029 23:18:52.672967 INFO: [NOCDAPC] D14_APC_1: 0xfff
10030 23:18:52.676130 INFO: [NOCDAPC] D15_APC_0: 0x0
10031 23:18:52.679187 INFO: [NOCDAPC] D15_APC_1: 0xfff
10032 23:18:52.679294 INFO: [NOCDAPC] APC_CON: 0x4
10033 23:18:52.683187 INFO: [APUAPC] set_apusys_apc done
10034 23:18:52.686302 INFO: [DEVAPC] devapc_init done
10035 23:18:52.692453 INFO: GICv3 without legacy support detected.
10036 23:18:52.697207 INFO: ARM GICv3 driver initialized in EL3
10037 23:18:52.699187 INFO: Maximum SPI INTID supported: 639
10038 23:18:52.702373 INFO: BL31: Initializing runtime services
10039 23:18:52.709547 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10040 23:18:52.712950 INFO: SPM: enable CPC mode
10041 23:18:52.716045 INFO: mcdi ready for mcusys-off-idle and system suspend
10042 23:18:52.722437 INFO: BL31: Preparing for EL3 exit to normal world
10043 23:18:52.725918 INFO: Entry point address = 0x80000000
10044 23:18:52.725999 INFO: SPSR = 0x8
10045 23:18:52.732468
10046 23:18:52.732548
10047 23:18:52.732611
10048 23:18:52.736031 Starting depthcharge on Spherion...
10049 23:18:52.736112
10050 23:18:52.736174 Wipe memory regions:
10051 23:18:52.736233
10052 23:18:52.736905 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10053 23:18:52.737002 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10054 23:18:52.737082 Setting prompt string to ['asurada:']
10055 23:18:52.737160 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10056 23:18:52.739265 [0x00000040000000, 0x00000054600000)
10057 23:18:52.861487
10058 23:18:52.861595 [0x00000054660000, 0x00000080000000)
10059 23:18:53.122100
10060 23:18:53.122243 [0x000000821a7280, 0x000000ffe64000)
10061 23:18:53.866557
10062 23:18:53.866722 [0x00000100000000, 0x00000240000000)
10063 23:18:55.756316
10064 23:18:55.759348 Initializing XHCI USB controller at 0x11200000.
10065 23:18:56.797337
10066 23:18:56.800835 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10067 23:18:56.800948
10068 23:18:56.801070
10069 23:18:56.801190
10070 23:18:56.801500 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10072 23:18:56.901836 asurada: tftpboot 192.168.201.1 13248486/tftp-deploy-7v0d_pg_/kernel/image.itb 13248486/tftp-deploy-7v0d_pg_/kernel/cmdline
10073 23:18:56.902001 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10074 23:18:56.902114 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10075 23:18:56.906287 tftpboot 192.168.201.1 13248486/tftp-deploy-7v0d_pg_/kernel/image.ittp-deploy-7v0d_pg_/kernel/cmdline
10076 23:18:56.906406
10077 23:18:56.906519 Waiting for link
10078 23:18:57.067291
10079 23:18:57.067414 R8152: Initializing
10080 23:18:57.067500
10081 23:18:57.069967 Version 6 (ocp_data = 5c30)
10082 23:18:57.070078
10083 23:18:57.073199 R8152: Done initializing
10084 23:18:57.073300
10085 23:18:57.073389 Adding net device
10086 23:18:58.944432
10087 23:18:58.944571 done.
10088 23:18:58.944638
10089 23:18:58.944697 MAC: 00:24:32:30:78:52
10090 23:18:58.944754
10091 23:18:58.947967 Sending DHCP discover... done.
10092 23:18:58.948050
10093 23:18:58.951060 Waiting for reply... done.
10094 23:18:58.951141
10095 23:18:58.954524 Sending DHCP request... done.
10096 23:18:58.954629
10097 23:18:58.959909 Waiting for reply... done.
10098 23:18:58.959990
10099 23:18:58.960053 My ip is 192.168.201.14
10100 23:18:58.960111
10101 23:18:58.963455 The DHCP server ip is 192.168.201.1
10102 23:18:58.963535
10103 23:18:58.970103 TFTP server IP predefined by user: 192.168.201.1
10104 23:18:58.970226
10105 23:18:58.976689 Bootfile predefined by user: 13248486/tftp-deploy-7v0d_pg_/kernel/image.itb
10106 23:18:58.976796
10107 23:18:58.976891 Sending tftp read request... done.
10108 23:18:58.979937
10109 23:18:58.984140 Waiting for the transfer...
10110 23:18:58.984248
10111 23:18:59.535298 00000000 ################################################################
10112 23:18:59.535468
10113 23:19:00.100835 00080000 ################################################################
10114 23:19:00.100981
10115 23:19:00.648470 00100000 ################################################################
10116 23:19:00.648629
10117 23:19:01.211058 00180000 ################################################################
10118 23:19:01.211218
10119 23:19:01.751130 00200000 ################################################################
10120 23:19:01.751278
10121 23:19:02.296465 00280000 ################################################################
10122 23:19:02.296615
10123 23:19:02.846442 00300000 ################################################################
10124 23:19:02.846589
10125 23:19:03.405050 00380000 ################################################################
10126 23:19:03.405223
10127 23:19:03.953944 00400000 ################################################################
10128 23:19:03.954105
10129 23:19:04.501905 00480000 ################################################################
10130 23:19:04.502068
10131 23:19:05.066533 00500000 ################################################################
10132 23:19:05.066672
10133 23:19:05.632451 00580000 ################################################################
10134 23:19:05.632616
10135 23:19:06.182560 00600000 ################################################################
10136 23:19:06.182712
10137 23:19:06.736442 00680000 ################################################################
10138 23:19:06.736590
10139 23:19:07.289476 00700000 ################################################################
10140 23:19:07.289623
10141 23:19:07.849117 00780000 ################################################################
10142 23:19:07.849261
10143 23:19:08.392139 00800000 ################################################################
10144 23:19:08.392314
10145 23:19:08.969937 00880000 ################################################################
10146 23:19:08.970490
10147 23:19:09.649305 00900000 ################################################################
10148 23:19:09.649515
10149 23:19:10.249168 00980000 ################################################################
10150 23:19:10.249319
10151 23:19:10.854678 00a00000 ################################################################
10152 23:19:10.855167
10153 23:19:11.577855 00a80000 ################################################################
10154 23:19:11.578348
10155 23:19:12.250329 00b00000 ################################################################
10156 23:19:12.250501
10157 23:19:12.895321 00b80000 ################################################################
10158 23:19:12.895943
10159 23:19:13.555595 00c00000 ################################################################
10160 23:19:13.555735
10161 23:19:14.238695 00c80000 ################################################################
10162 23:19:14.239188
10163 23:19:14.973198 00d00000 ################################################################
10164 23:19:14.973747
10165 23:19:15.725242 00d80000 ################################################################
10166 23:19:15.725756
10167 23:19:16.471595 00e00000 ################################################################
10168 23:19:16.472110
10169 23:19:17.211490 00e80000 ################################################################
10170 23:19:17.212036
10171 23:19:17.939865 00f00000 ################################################################
10172 23:19:17.940380
10173 23:19:18.678944 00f80000 ################################################################
10174 23:19:18.679481
10175 23:19:19.424104 01000000 ################################################################
10176 23:19:19.424633
10177 23:19:20.182298 01080000 ################################################################
10178 23:19:20.182871
10179 23:19:20.933898 01100000 ################################################################
10180 23:19:20.934475
10181 23:19:21.680457 01180000 ################################################################
10182 23:19:21.680992
10183 23:19:22.432094 01200000 ################################################################
10184 23:19:22.432581
10185 23:19:23.160662 01280000 ################################################################
10186 23:19:23.161187
10187 23:19:23.896110 01300000 ################################################################
10188 23:19:23.896652
10189 23:19:24.640978 01380000 ################################################################
10190 23:19:24.641527
10191 23:19:25.386091 01400000 ################################################################
10192 23:19:25.386646
10193 23:19:26.121052 01480000 ################################################################
10194 23:19:26.121564
10195 23:19:26.852042 01500000 ################################################################
10196 23:19:26.852628
10197 23:19:27.541436 01580000 ################################################################
10198 23:19:27.541672
10199 23:19:28.200200 01600000 ################################################################
10200 23:19:28.200713
10201 23:19:28.888526 01680000 ################################################################
10202 23:19:28.889085
10203 23:19:29.590593 01700000 ################################################################
10204 23:19:29.591268
10205 23:19:30.278057 01780000 ################################################################
10206 23:19:30.278217
10207 23:19:30.897054 01800000 ################################################################
10208 23:19:30.897191
10209 23:19:31.442650 01880000 ################################################################
10210 23:19:31.442786
10211 23:19:31.993550 01900000 ################################################################
10212 23:19:31.993700
10213 23:19:32.646417 01980000 ################################################################
10214 23:19:32.646596
10215 23:19:33.221369 01a00000 ################################################################
10216 23:19:33.221513
10217 23:19:33.811972 01a80000 ################################################################
10218 23:19:33.812110
10219 23:19:34.388803 01b00000 ################################################################
10220 23:19:34.388958
10221 23:19:34.964082 01b80000 ################################################################
10222 23:19:34.964222
10223 23:19:35.591841 01c00000 ################################################################
10224 23:19:35.591990
10225 23:19:36.278182 01c80000 ################################################################
10226 23:19:36.278344
10227 23:19:36.920537 01d00000 ################################################################
10228 23:19:36.920700
10229 23:19:37.516837 01d80000 ################################################################
10230 23:19:37.516992
10231 23:19:38.092372 01e00000 ################################################################
10232 23:19:38.092507
10233 23:19:38.678702 01e80000 ################################################################
10234 23:19:38.678831
10235 23:19:39.267683 01f00000 ################################################################
10236 23:19:39.267829
10237 23:19:39.936835 01f80000 ################################################################
10238 23:19:39.937325
10239 23:19:40.646205 02000000 ################################################################
10240 23:19:40.646762
10241 23:19:41.009310 02080000 ################################ done.
10242 23:19:41.009821
10243 23:19:41.012704 The bootfile was 34339722 bytes long.
10244 23:19:41.013127
10245 23:19:41.015307 Sending tftp read request... done.
10246 23:19:41.015726
10247 23:19:41.019489 Waiting for the transfer...
10248 23:19:41.019911
10249 23:19:41.020240 00000000 # done.
10250 23:19:41.020557
10251 23:19:41.026377 Command line loaded dynamically from TFTP file: 13248486/tftp-deploy-7v0d_pg_/kernel/cmdline
10252 23:19:41.026938
10253 23:19:41.040345 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10254 23:19:41.040862
10255 23:19:41.042846 Loading FIT.
10256 23:19:41.043254
10257 23:19:41.046331 Image ramdisk-1 has 21383185 bytes.
10258 23:19:41.046916
10259 23:19:41.047304 Image fdt-1 has 47230 bytes.
10260 23:19:41.049757
10261 23:19:41.050165 Image kernel-1 has 12907270 bytes.
10262 23:19:41.050541
10263 23:19:41.060025 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10264 23:19:41.060440
10265 23:19:41.077200 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10266 23:19:41.077740
10267 23:19:41.083026 Choosing best match conf-1 for compat google,spherion-rev2.
10268 23:19:41.086979
10269 23:19:41.092136 Connected to device vid:did:rid of 1ae0:0028:00
10270 23:19:41.099059
10271 23:19:41.101920 tpm_get_response: command 0x17b, return code 0x0
10272 23:19:41.102534
10273 23:19:41.108706 ec_init: CrosEC protocol v3 supported (256, 248)
10274 23:19:41.109295
10275 23:19:41.112370 tpm_cleanup: add release locality here.
10276 23:19:41.112783
10277 23:19:41.115342 Shutting down all USB controllers.
10278 23:19:41.115754
10279 23:19:41.118927 Removing current net device
10280 23:19:41.119336
10281 23:19:41.122341 Exiting depthcharge with code 4 at timestamp: 77797600
10282 23:19:41.122914
10283 23:19:41.128659 LZMA decompressing kernel-1 to 0x821a6718
10284 23:19:41.129158
10285 23:19:41.132333 LZMA decompressing kernel-1 to 0x40000000
10286 23:19:42.724963
10287 23:19:42.725516 jumping to kernel
10288 23:19:42.727614 end: 2.2.4 bootloader-commands (duration 00:00:50) [common]
10289 23:19:42.728154 start: 2.2.5 auto-login-action (timeout 00:03:35) [common]
10290 23:19:42.728568 Setting prompt string to ['Linux version [0-9]']
10291 23:19:42.728940 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10292 23:19:42.729312 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10293 23:19:42.806660
10294 23:19:42.810043 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10295 23:19:42.813821 start: 2.2.5.1 login-action (timeout 00:03:35) [common]
10296 23:19:42.814442 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10297 23:19:42.814842 Setting prompt string to []
10298 23:19:42.815272 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10299 23:19:42.815668 Using line separator: #'\n'#
10300 23:19:42.815997 No login prompt set.
10301 23:19:42.816323 Parsing kernel messages
10302 23:19:42.816630 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10303 23:19:42.817179 [login-action] Waiting for messages, (timeout 00:03:35)
10304 23:19:42.817532 Waiting using forced prompt support (timeout 00:01:48)
10305 23:19:42.833463 [ 0.000000] Linux version 6.1.83-cip18 (KernelCI@build-j154450-arm64-gcc-10-defconfig-arm64-chromebook-z5l88) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024
10306 23:19:42.836371 [ 0.000000] random: crng init done
10307 23:19:42.843491 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10308 23:19:42.846843 [ 0.000000] efi: UEFI not found.
10309 23:19:42.853526 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10310 23:19:42.860079 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10311 23:19:42.870377 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10312 23:19:42.880075 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10313 23:19:42.886935 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10314 23:19:42.890140 [ 0.000000] printk: bootconsole [mtk8250] enabled
10315 23:19:42.898810 [ 0.000000] NUMA: No NUMA configuration found
10316 23:19:42.905548 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10317 23:19:42.911851 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10318 23:19:42.912263 [ 0.000000] Zone ranges:
10319 23:19:42.918719 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10320 23:19:42.921972 [ 0.000000] DMA32 empty
10321 23:19:42.928606 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10322 23:19:42.932104 [ 0.000000] Movable zone start for each node
10323 23:19:42.936058 [ 0.000000] Early memory node ranges
10324 23:19:42.942631 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10325 23:19:42.949080 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10326 23:19:42.955567 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10327 23:19:42.962553 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10328 23:19:42.965269 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10329 23:19:42.975790 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10330 23:19:43.032005 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10331 23:19:43.037945 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10332 23:19:43.044818 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10333 23:19:43.048469 [ 0.000000] psci: probing for conduit method from DT.
10334 23:19:43.054434 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10335 23:19:43.058695 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10336 23:19:43.064912 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10337 23:19:43.067781 [ 0.000000] psci: SMC Calling Convention v1.2
10338 23:19:43.074692 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10339 23:19:43.077742 [ 0.000000] Detected VIPT I-cache on CPU0
10340 23:19:43.085012 [ 0.000000] CPU features: detected: GIC system register CPU interface
10341 23:19:43.091679 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10342 23:19:43.097760 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10343 23:19:43.104549 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10344 23:19:43.112048 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10345 23:19:43.118811 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10346 23:19:43.125487 [ 0.000000] alternatives: applying boot alternatives
10347 23:19:43.128398 [ 0.000000] Fallback order for Node 0: 0
10348 23:19:43.135153 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10349 23:19:43.138183 [ 0.000000] Policy zone: Normal
10350 23:19:43.155272 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10351 23:19:43.165525 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10352 23:19:43.175228 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10353 23:19:43.184792 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10354 23:19:43.191414 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10355 23:19:43.195049 <6>[ 0.000000] software IO TLB: area num 8.
10356 23:19:43.251288 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10357 23:19:43.400385 <6>[ 0.000000] Memory: 7943688K/8385536K available (18048K kernel code, 4118K rwdata, 22284K rodata, 8448K init, 616K bss, 409080K reserved, 32768K cma-reserved)
10358 23:19:43.406968 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10359 23:19:43.413965 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10360 23:19:43.417227 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10361 23:19:43.423719 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10362 23:19:43.430487 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10363 23:19:43.433583 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10364 23:19:43.443609 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10365 23:19:43.450722 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10366 23:19:43.453658 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10367 23:19:43.461231 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10368 23:19:43.464959 <6>[ 0.000000] GICv3: 608 SPIs implemented
10369 23:19:43.471259 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10370 23:19:43.474784 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10371 23:19:43.477809 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10372 23:19:43.487985 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10373 23:19:43.497819 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10374 23:19:43.510460 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10375 23:19:43.517583 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10376 23:19:43.525912 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10377 23:19:43.539548 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10378 23:19:43.545787 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10379 23:19:43.552814 <6>[ 0.009175] Console: colour dummy device 80x25
10380 23:19:43.562909 <6>[ 0.013930] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10381 23:19:43.569991 <6>[ 0.024437] pid_max: default: 32768 minimum: 301
10382 23:19:43.573137 <6>[ 0.029310] LSM: Security Framework initializing
10383 23:19:43.580275 <6>[ 0.034250] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10384 23:19:43.590144 <6>[ 0.042066] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10385 23:19:43.597322 <6>[ 0.051543] cblist_init_generic: Setting adjustable number of callback queues.
10386 23:19:43.603150 <6>[ 0.058984] cblist_init_generic: Setting shift to 3 and lim to 1.
10387 23:19:43.613213 <6>[ 0.065361] cblist_init_generic: Setting adjustable number of callback queues.
10388 23:19:43.616492 <6>[ 0.072789] cblist_init_generic: Setting shift to 3 and lim to 1.
10389 23:19:43.622636 <6>[ 0.079221] rcu: Hierarchical SRCU implementation.
10390 23:19:43.629280 <6>[ 0.084236] rcu: Max phase no-delay instances is 1000.
10391 23:19:43.636139 <6>[ 0.091258] EFI services will not be available.
10392 23:19:43.639217 <6>[ 0.096217] smp: Bringing up secondary CPUs ...
10393 23:19:43.646736 <6>[ 0.101295] Detected VIPT I-cache on CPU1
10394 23:19:43.653455 <6>[ 0.101368] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10395 23:19:43.660210 <6>[ 0.101399] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10396 23:19:43.663943 <6>[ 0.101737] Detected VIPT I-cache on CPU2
10397 23:19:43.670456 <6>[ 0.101789] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10398 23:19:43.677461 <6>[ 0.101807] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10399 23:19:43.683873 <6>[ 0.102063] Detected VIPT I-cache on CPU3
10400 23:19:43.690938 <6>[ 0.102111] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10401 23:19:43.697765 <6>[ 0.102126] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10402 23:19:43.700708 <6>[ 0.102429] CPU features: detected: Spectre-v4
10403 23:19:43.707482 <6>[ 0.102435] CPU features: detected: Spectre-BHB
10404 23:19:43.710929 <6>[ 0.102440] Detected PIPT I-cache on CPU4
10405 23:19:43.718093 <6>[ 0.102499] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10406 23:19:43.724610 <6>[ 0.102516] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10407 23:19:43.727628 <6>[ 0.102807] Detected PIPT I-cache on CPU5
10408 23:19:43.737772 <6>[ 0.102870] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10409 23:19:43.744139 <6>[ 0.102887] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10410 23:19:43.747025 <6>[ 0.103163] Detected PIPT I-cache on CPU6
10411 23:19:43.754940 <6>[ 0.103231] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10412 23:19:43.760619 <6>[ 0.103248] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10413 23:19:43.763960 <6>[ 0.103542] Detected PIPT I-cache on CPU7
10414 23:19:43.774148 <6>[ 0.103607] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10415 23:19:43.780908 <6>[ 0.103623] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10416 23:19:43.783939 <6>[ 0.103671] smp: Brought up 1 node, 8 CPUs
10417 23:19:43.786621 <6>[ 0.244934] SMP: Total of 8 processors activated.
10418 23:19:43.793478 <6>[ 0.249886] CPU features: detected: 32-bit EL0 Support
10419 23:19:43.803625 <6>[ 0.255249] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10420 23:19:43.809907 <6>[ 0.264049] CPU features: detected: Common not Private translations
10421 23:19:43.813882 <6>[ 0.270525] CPU features: detected: CRC32 instructions
10422 23:19:43.820519 <6>[ 0.275910] CPU features: detected: RCpc load-acquire (LDAPR)
10423 23:19:43.826677 <6>[ 0.281870] CPU features: detected: LSE atomic instructions
10424 23:19:43.833931 <6>[ 0.287687] CPU features: detected: Privileged Access Never
10425 23:19:43.837020 <6>[ 0.293467] CPU features: detected: RAS Extension Support
10426 23:19:43.843233 <6>[ 0.299076] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10427 23:19:43.850245 <6>[ 0.306298] CPU: All CPU(s) started at EL2
10428 23:19:43.853134 <6>[ 0.310641] alternatives: applying system-wide alternatives
10429 23:19:43.864664 <6>[ 0.321487] devtmpfs: initialized
10430 23:19:43.876892 <6>[ 0.330368] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10431 23:19:43.887278 <6>[ 0.340327] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10432 23:19:43.894034 <6>[ 0.348538] pinctrl core: initialized pinctrl subsystem
10433 23:19:43.896903 <6>[ 0.355216] DMI not present or invalid.
10434 23:19:43.903597 <6>[ 0.359631] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10435 23:19:43.913912 <6>[ 0.366538] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10436 23:19:43.920671 <6>[ 0.374129] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10437 23:19:43.930390 <6>[ 0.382357] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10438 23:19:43.933777 <6>[ 0.390598] audit: initializing netlink subsys (disabled)
10439 23:19:43.943259 <5>[ 0.396290] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10440 23:19:43.950142 <6>[ 0.396995] thermal_sys: Registered thermal governor 'step_wise'
10441 23:19:43.956844 <6>[ 0.404257] thermal_sys: Registered thermal governor 'power_allocator'
10442 23:19:43.960088 <6>[ 0.410513] cpuidle: using governor menu
10443 23:19:43.963553 <6>[ 0.421476] NET: Registered PF_QIPCRTR protocol family
10444 23:19:43.974253 <6>[ 0.426963] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10445 23:19:43.977656 <6>[ 0.434066] ASID allocator initialised with 32768 entries
10446 23:19:43.984280 <6>[ 0.440643] Serial: AMBA PL011 UART driver
10447 23:19:43.992548 <4>[ 0.449470] Trying to register duplicate clock ID: 134
10448 23:19:44.047113 <6>[ 0.507251] KASLR enabled
10449 23:19:44.062565 <6>[ 0.514972] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10450 23:19:44.068940 <6>[ 0.521987] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10451 23:19:44.074896 <6>[ 0.528477] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10452 23:19:44.081543 <6>[ 0.535481] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10453 23:19:44.087959 <6>[ 0.541967] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10454 23:19:44.094933 <6>[ 0.548970] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10455 23:19:44.101568 <6>[ 0.555455] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10456 23:19:44.107814 <6>[ 0.562459] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10457 23:19:44.111518 <6>[ 0.569996] ACPI: Interpreter disabled.
10458 23:19:44.119565 <6>[ 0.576496] iommu: Default domain type: Translated
10459 23:19:44.126124 <6>[ 0.581608] iommu: DMA domain TLB invalidation policy: strict mode
10460 23:19:44.129469 <5>[ 0.588274] SCSI subsystem initialized
10461 23:19:44.136113 <6>[ 0.592439] usbcore: registered new interface driver usbfs
10462 23:19:44.143123 <6>[ 0.598174] usbcore: registered new interface driver hub
10463 23:19:44.146731 <6>[ 0.603725] usbcore: registered new device driver usb
10464 23:19:44.153520 <6>[ 0.609829] pps_core: LinuxPPS API ver. 1 registered
10465 23:19:44.162945 <6>[ 0.615023] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10466 23:19:44.166662 <6>[ 0.624368] PTP clock support registered
10467 23:19:44.169718 <6>[ 0.628609] EDAC MC: Ver: 3.0.0
10468 23:19:44.177564 <6>[ 0.633772] FPGA manager framework
10469 23:19:44.183401 <6>[ 0.637454] Advanced Linux Sound Architecture Driver Initialized.
10470 23:19:44.186930 <6>[ 0.644237] vgaarb: loaded
10471 23:19:44.193687 <6>[ 0.647404] clocksource: Switched to clocksource arch_sys_counter
10472 23:19:44.196815 <5>[ 0.653847] VFS: Disk quotas dquot_6.6.0
10473 23:19:44.203326 <6>[ 0.658032] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10474 23:19:44.206595 <6>[ 0.665223] pnp: PnP ACPI: disabled
10475 23:19:44.215007 <6>[ 0.671922] NET: Registered PF_INET protocol family
10476 23:19:44.225213 <6>[ 0.677533] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10477 23:19:44.236476 <6>[ 0.689857] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10478 23:19:44.246993 <6>[ 0.698675] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10479 23:19:44.253415 <6>[ 0.706647] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10480 23:19:44.259778 <6>[ 0.715346] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10481 23:19:44.272041 <6>[ 0.725094] TCP: Hash tables configured (established 65536 bind 65536)
10482 23:19:44.278845 <6>[ 0.731959] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10483 23:19:44.285517 <6>[ 0.739157] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10484 23:19:44.292381 <6>[ 0.746863] NET: Registered PF_UNIX/PF_LOCAL protocol family
10485 23:19:44.298724 <6>[ 0.753016] RPC: Registered named UNIX socket transport module.
10486 23:19:44.301645 <6>[ 0.759167] RPC: Registered udp transport module.
10487 23:19:44.308391 <6>[ 0.764098] RPC: Registered tcp transport module.
10488 23:19:44.315140 <6>[ 0.769030] RPC: Registered tcp NFSv4.1 backchannel transport module.
10489 23:19:44.318183 <6>[ 0.775695] PCI: CLS 0 bytes, default 64
10490 23:19:44.321553 <6>[ 0.780028] Unpacking initramfs...
10491 23:19:44.346286 <6>[ 0.799503] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10492 23:19:44.355980 <6>[ 0.808165] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10493 23:19:44.359607 <6>[ 0.817023] kvm [1]: IPA Size Limit: 40 bits
10494 23:19:44.365908 <6>[ 0.821551] kvm [1]: GICv3: no GICV resource entry
10495 23:19:44.369662 <6>[ 0.826572] kvm [1]: disabling GICv2 emulation
10496 23:19:44.375914 <6>[ 0.831258] kvm [1]: GIC system register CPU interface enabled
10497 23:19:44.379367 <6>[ 0.837421] kvm [1]: vgic interrupt IRQ18
10498 23:19:44.386241 <6>[ 0.841777] kvm [1]: VHE mode initialized successfully
10499 23:19:44.392766 <5>[ 0.848236] Initialise system trusted keyrings
10500 23:19:44.399352 <6>[ 0.853040] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10501 23:19:44.406353 <6>[ 0.863095] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10502 23:19:44.413108 <5>[ 0.869484] NFS: Registering the id_resolver key type
10503 23:19:44.417688 <5>[ 0.874784] Key type id_resolver registered
10504 23:19:44.422928 <5>[ 0.879201] Key type id_legacy registered
10505 23:19:44.429271 <6>[ 0.883480] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10506 23:19:44.435969 <6>[ 0.890399] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10507 23:19:44.443214 <6>[ 0.898107] 9p: Installing v9fs 9p2000 file system support
10508 23:19:44.479012 <5>[ 0.935588] Key type asymmetric registered
10509 23:19:44.482926 <5>[ 0.939921] Asymmetric key parser 'x509' registered
10510 23:19:44.492540 <6>[ 0.945065] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10511 23:19:44.495778 <6>[ 0.952684] io scheduler mq-deadline registered
10512 23:19:44.498494 <6>[ 0.957458] io scheduler kyber registered
10513 23:19:44.517699 <6>[ 0.974768] EINJ: ACPI disabled.
10514 23:19:44.550095 <4>[ 1.000363] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10515 23:19:44.560051 <4>[ 1.010995] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10516 23:19:44.575352 <6>[ 1.031881] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10517 23:19:44.583116 <6>[ 1.040016] printk: console [ttyS0] disabled
10518 23:19:44.611565 <6>[ 1.064657] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10519 23:19:44.617718 <6>[ 1.074131] printk: console [ttyS0] enabled
10520 23:19:44.621089 <6>[ 1.074131] printk: console [ttyS0] enabled
10521 23:19:44.627958 <6>[ 1.083026] printk: bootconsole [mtk8250] disabled
10522 23:19:44.630980 <6>[ 1.083026] printk: bootconsole [mtk8250] disabled
10523 23:19:44.637764 <6>[ 1.094285] SuperH (H)SCI(F) driver initialized
10524 23:19:44.641063 <6>[ 1.099576] msm_serial: driver initialized
10525 23:19:44.655334 <6>[ 1.108581] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10526 23:19:44.665174 <6>[ 1.117127] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10527 23:19:44.672064 <6>[ 1.125670] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10528 23:19:44.682080 <6>[ 1.134297] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10529 23:19:44.688753 <6>[ 1.143003] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10530 23:19:44.698328 <6>[ 1.151723] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10531 23:19:44.708280 <6>[ 1.160265] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10532 23:19:44.715022 <6>[ 1.169085] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10533 23:19:44.725413 <6>[ 1.177630] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10534 23:19:44.736689 <6>[ 1.193386] loop: module loaded
10535 23:19:44.742965 <6>[ 1.199421] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10536 23:19:44.766044 <4>[ 1.222996] mtk-pmic-keys: Failed to locate of_node [id: -1]
10537 23:19:44.773585 <6>[ 1.230113] megasas: 07.719.03.00-rc1
10538 23:19:44.782955 <6>[ 1.239907] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10539 23:19:44.789966 <6>[ 1.246804] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10540 23:19:44.806980 <6>[ 1.263557] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10541 23:19:44.863410 <6>[ 1.313623] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10542 23:19:45.228255 <6>[ 1.684980] Freeing initrd memory: 20880K
10543 23:19:45.243802 <6>[ 1.700751] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10544 23:19:45.254930 <6>[ 1.711993] tun: Universal TUN/TAP device driver, 1.6
10545 23:19:45.258203 <6>[ 1.718079] thunder_xcv, ver 1.0
10546 23:19:45.261929 <6>[ 1.721590] thunder_bgx, ver 1.0
10547 23:19:45.265266 <6>[ 1.725086] nicpf, ver 1.0
10548 23:19:45.275830 <6>[ 1.729132] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10549 23:19:45.279150 <6>[ 1.736608] hns3: Copyright (c) 2017 Huawei Corporation.
10550 23:19:45.282468 <6>[ 1.742199] hclge is initializing
10551 23:19:45.289329 <6>[ 1.745780] e1000: Intel(R) PRO/1000 Network Driver
10552 23:19:45.295384 <6>[ 1.750909] e1000: Copyright (c) 1999-2006 Intel Corporation.
10553 23:19:45.298898 <6>[ 1.756922] e1000e: Intel(R) PRO/1000 Network Driver
10554 23:19:45.305419 <6>[ 1.762137] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10555 23:19:45.313183 <6>[ 1.768322] igb: Intel(R) Gigabit Ethernet Network Driver
10556 23:19:45.319190 <6>[ 1.773971] igb: Copyright (c) 2007-2014 Intel Corporation.
10557 23:19:45.325730 <6>[ 1.779810] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10558 23:19:45.328803 <6>[ 1.786328] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10559 23:19:45.335796 <6>[ 1.792800] sky2: driver version 1.30
10560 23:19:45.342696 <6>[ 1.797826] VFIO - User Level meta-driver version: 0.3
10561 23:19:45.349126 <6>[ 1.806140] usbcore: registered new interface driver usb-storage
10562 23:19:45.356207 <6>[ 1.812594] usbcore: registered new device driver onboard-usb-hub
10563 23:19:45.365283 <6>[ 1.821781] mt6397-rtc mt6359-rtc: registered as rtc0
10564 23:19:45.375148 <6>[ 1.827248] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-03T23:19:46 UTC (1712186386)
10565 23:19:45.378393 <6>[ 1.836829] i2c_dev: i2c /dev entries driver
10566 23:19:45.395255 <6>[ 1.848802] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10567 23:19:45.402316 <4>[ 1.857555] cpu cpu0: supply cpu not found, using dummy regulator
10568 23:19:45.408609 <4>[ 1.863980] cpu cpu1: supply cpu not found, using dummy regulator
10569 23:19:45.414975 <4>[ 1.870401] cpu cpu2: supply cpu not found, using dummy regulator
10570 23:19:45.422128 <4>[ 1.876804] cpu cpu3: supply cpu not found, using dummy regulator
10571 23:19:45.428421 <4>[ 1.883218] cpu cpu4: supply cpu not found, using dummy regulator
10572 23:19:45.435170 <4>[ 1.889615] cpu cpu5: supply cpu not found, using dummy regulator
10573 23:19:45.441982 <4>[ 1.896018] cpu cpu6: supply cpu not found, using dummy regulator
10574 23:19:45.445184 <4>[ 1.902432] cpu cpu7: supply cpu not found, using dummy regulator
10575 23:19:45.466211 <6>[ 1.923086] cpu cpu0: EM: created perf domain
10576 23:19:45.469446 <6>[ 1.928003] cpu cpu4: EM: created perf domain
10577 23:19:45.476559 <6>[ 1.933607] sdhci: Secure Digital Host Controller Interface driver
10578 23:19:45.483350 <6>[ 1.940039] sdhci: Copyright(c) Pierre Ossman
10579 23:19:45.490022 <6>[ 1.945003] Synopsys Designware Multimedia Card Interface Driver
10580 23:19:45.493849 <6>[ 1.951648] mmc0: CQHCI version 5.10
10581 23:19:45.500793 <6>[ 1.951675] sdhci-pltfm: SDHCI platform and OF driver helper
10582 23:19:45.506657 <6>[ 1.962869] ledtrig-cpu: registered to indicate activity on CPUs
10583 23:19:45.513747 <6>[ 1.970012] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10584 23:19:45.520104 <6>[ 1.977080] usbcore: registered new interface driver usbhid
10585 23:19:45.523463 <6>[ 1.982905] usbhid: USB HID core driver
10586 23:19:45.533503 <6>[ 1.987120] spi_master spi0: will run message pump with realtime priority
10587 23:19:45.574795 <6>[ 2.024983] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10588 23:19:45.590700 <6>[ 2.040914] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10589 23:19:45.597806 <6>[ 2.054567] mmc0: Command Queue Engine enabled
10590 23:19:45.604513 <6>[ 2.059389] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10591 23:19:45.611221 <6>[ 2.066330] cros-ec-spi spi0.0: Chrome EC device registered
10592 23:19:45.614635 <6>[ 2.066953] mmcblk0: mmc0:0001 DA4128 116 GiB
10593 23:19:45.625402 <6>[ 2.082075] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10594 23:19:45.632947 <6>[ 2.089600] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10595 23:19:45.639598 <6>[ 2.095516] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10596 23:19:45.646705 <6>[ 2.101592] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10597 23:19:45.656023 <6>[ 2.108483] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10598 23:19:45.662706 <6>[ 2.119181] NET: Registered PF_PACKET protocol family
10599 23:19:45.666117 <6>[ 2.124584] 9pnet: Installing 9P2000 support
10600 23:19:45.672715 <5>[ 2.129148] Key type dns_resolver registered
10601 23:19:45.676241 <6>[ 2.134138] registered taskstats version 1
10602 23:19:45.683486 <5>[ 2.138523] Loading compiled-in X.509 certificates
10603 23:19:45.714247 <4>[ 2.164602] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10604 23:19:45.724649 <4>[ 2.175495] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10605 23:19:45.731054 <3>[ 2.186043] debugfs: File 'uA_load' in directory '/' already present!
10606 23:19:45.737979 <3>[ 2.192745] debugfs: File 'min_uV' in directory '/' already present!
10607 23:19:45.744427 <3>[ 2.199355] debugfs: File 'max_uV' in directory '/' already present!
10608 23:19:45.751410 <3>[ 2.205963] debugfs: File 'constraint_flags' in directory '/' already present!
10609 23:19:45.762227 <3>[ 2.215808] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10610 23:19:45.775602 <6>[ 2.232749] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10611 23:19:45.782503 <6>[ 2.239552] xhci-mtk 11200000.usb: xHCI Host Controller
10612 23:19:45.789063 <6>[ 2.245076] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10613 23:19:45.800200 <6>[ 2.252986] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10614 23:19:45.806085 <6>[ 2.262435] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10615 23:19:45.812734 <6>[ 2.268522] xhci-mtk 11200000.usb: xHCI Host Controller
10616 23:19:45.819752 <6>[ 2.274008] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10617 23:19:45.826189 <6>[ 2.281664] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10618 23:19:45.832958 <6>[ 2.289494] hub 1-0:1.0: USB hub found
10619 23:19:45.836378 <6>[ 2.293521] hub 1-0:1.0: 1 port detected
10620 23:19:45.842998 <6>[ 2.297823] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10621 23:19:45.849629 <6>[ 2.306551] hub 2-0:1.0: USB hub found
10622 23:19:45.853217 <6>[ 2.310575] hub 2-0:1.0: 1 port detected
10623 23:19:45.860906 <6>[ 2.317544] mtk-msdc 11f70000.mmc: Got CD GPIO
10624 23:19:45.874064 <6>[ 2.327521] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10625 23:19:45.880881 <6>[ 2.335541] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10626 23:19:45.890302 <4>[ 2.343480] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10627 23:19:45.900386 <6>[ 2.353022] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10628 23:19:45.906873 <6>[ 2.361100] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10629 23:19:45.914300 <6>[ 2.369128] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10630 23:19:45.924642 <6>[ 2.377047] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10631 23:19:45.930995 <6>[ 2.384866] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10632 23:19:45.940611 <6>[ 2.392684] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10633 23:19:45.950506 <6>[ 2.403103] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10634 23:19:45.957562 <6>[ 2.411459] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10635 23:19:45.967265 <6>[ 2.419807] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10636 23:19:45.973632 <6>[ 2.428145] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10637 23:19:45.983952 <6>[ 2.436483] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10638 23:19:45.991454 <6>[ 2.444820] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10639 23:19:46.001251 <6>[ 2.453158] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10640 23:19:46.007419 <6>[ 2.461495] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10641 23:19:46.017093 <6>[ 2.469832] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10642 23:19:46.023808 <6>[ 2.478169] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10643 23:19:46.033590 <6>[ 2.486507] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10644 23:19:46.040356 <6>[ 2.494844] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10645 23:19:46.050810 <6>[ 2.503188] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10646 23:19:46.057299 <6>[ 2.511538] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10647 23:19:46.067726 <6>[ 2.519877] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10648 23:19:46.073906 <6>[ 2.528617] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10649 23:19:46.080918 <6>[ 2.535798] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10650 23:19:46.086808 <6>[ 2.542533] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10651 23:19:46.093584 <6>[ 2.549301] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10652 23:19:46.100180 <6>[ 2.556234] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10653 23:19:46.109963 <6>[ 2.563081] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10654 23:19:46.120319 <6>[ 2.572211] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10655 23:19:46.130262 <6>[ 2.581330] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10656 23:19:46.140019 <6>[ 2.590624] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10657 23:19:46.146907 <6>[ 2.600091] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10658 23:19:46.156496 <6>[ 2.609558] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10659 23:19:46.166228 <6>[ 2.618677] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10660 23:19:46.176339 <6>[ 2.628145] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10661 23:19:46.186822 <6>[ 2.637264] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10662 23:19:46.196180 <6>[ 2.646558] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10663 23:19:46.205739 <6>[ 2.656718] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10664 23:19:46.215576 <6>[ 2.668282] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10665 23:19:46.262342 <6>[ 2.715679] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10666 23:19:46.417213 <6>[ 2.873616] hub 1-1:1.0: USB hub found
10667 23:19:46.419980 <6>[ 2.878119] hub 1-1:1.0: 4 ports detected
10668 23:19:46.429977 <6>[ 2.886934] hub 1-1:1.0: USB hub found
10669 23:19:46.433491 <6>[ 2.891272] hub 1-1:1.0: 4 ports detected
10670 23:19:46.542940 <6>[ 2.996091] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10671 23:19:46.569016 <6>[ 3.025483] hub 2-1:1.0: USB hub found
10672 23:19:46.572195 <6>[ 3.029982] hub 2-1:1.0: 3 ports detected
10673 23:19:46.581357 <6>[ 3.038118] hub 2-1:1.0: USB hub found
10674 23:19:46.585255 <6>[ 3.042569] hub 2-1:1.0: 3 ports detected
10675 23:19:46.757911 <6>[ 3.211707] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10676 23:19:46.890657 <6>[ 3.347066] hub 1-1.4:1.0: USB hub found
10677 23:19:46.893184 <6>[ 3.351693] hub 1-1.4:1.0: 2 ports detected
10678 23:19:46.902206 <6>[ 3.359100] hub 1-1.4:1.0: USB hub found
10679 23:19:46.905534 <6>[ 3.363645] hub 1-1.4:1.0: 2 ports detected
10680 23:19:46.974458 <6>[ 3.427813] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10681 23:19:47.202241 <6>[ 3.655618] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10682 23:19:47.394319 <6>[ 3.847719] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10683 23:19:58.498763 <6>[ 14.960752] ALSA device list:
10684 23:19:58.505726 <6>[ 14.964040] No soundcards found.
10685 23:19:58.514067 <6>[ 14.972032] Freeing unused kernel memory: 8448K
10686 23:19:58.517223 <6>[ 14.977583] Run /init as init process
10687 23:19:58.548105 Starting syslogd: OK
10688 23:19:58.558096 Starting klogd: OK
10689 23:19:58.565569 Running sysctl: OK
10690 23:19:58.571228 Populating /dev using udev: <30>[ 15.031694] udevd[193]: starting version 3.2.9
10691 23:19:58.579901 <27>[ 15.038563] udevd[193]: specified user 'tss' unknown
10692 23:19:58.587005 <27>[ 15.043917] udevd[193]: specified group 'tss' unknown
10693 23:19:58.589647 <30>[ 15.050072] udevd[194]: starting eudev-3.2.9
10694 23:19:58.608543 <27>[ 15.066856] udevd[194]: specified user 'tss' unknown
10695 23:19:58.614913 <27>[ 15.072268] udevd[194]: specified group 'tss' unknown
10696 23:19:58.738241 <6>[ 15.193516] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10697 23:19:58.745214 <6>[ 15.201271] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10698 23:19:58.754898 <6>[ 15.210394] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10699 23:19:58.773525 <6>[ 15.228140] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10700 23:19:58.779315 <3>[ 15.232528] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 23:19:58.786710 <6>[ 15.245176] remoteproc remoteproc0: scp is available
10702 23:19:58.793801 <3>[ 15.245608] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 23:19:58.800644 <6>[ 15.250618] remoteproc remoteproc0: powering up scp
10704 23:19:58.806588 <3>[ 15.258693] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 23:19:58.816659 <6>[ 15.263828] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10706 23:19:58.823829 <6>[ 15.264722] usbcore: registered new device driver r8152-cfgselector
10707 23:19:58.830158 <6>[ 15.272469] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10708 23:19:58.836669 <6>[ 15.272605] mc: Linux media interface: v0.10
10709 23:19:58.840100 <6>[ 15.280401] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10710 23:19:58.846746 <6>[ 15.280977] videodev: Linux video capture interface: v2.00
10711 23:19:58.854178 <4>[ 15.281432] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10712 23:19:58.861277 <4>[ 15.281697] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10713 23:19:58.871518 <3>[ 15.287327] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 23:19:58.874941 <6>[ 15.301985] Bluetooth: Core ver 2.22
10715 23:19:58.881135 <4>[ 15.302123] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10716 23:19:58.887565 <4>[ 15.302123] Fallback method does not support PEC.
10717 23:19:58.894170 <3>[ 15.305074] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 23:19:58.900970 <6>[ 15.310685] NET: Registered PF_BLUETOOTH protocol family
10719 23:19:58.911000 <3>[ 15.321888] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10720 23:19:58.917536 <3>[ 15.323266] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 23:19:58.927378 <3>[ 15.323277] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 23:19:58.933922 <3>[ 15.323282] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 23:19:58.941228 <3>[ 15.323328] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 23:19:58.950937 <3>[ 15.323362] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 23:19:58.958262 <3>[ 15.323365] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 23:19:58.967542 <3>[ 15.323367] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 23:19:58.974622 <3>[ 15.323454] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 23:19:58.984623 <3>[ 15.323457] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 23:19:58.991388 <3>[ 15.323460] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 23:19:59.000739 <3>[ 15.323463] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 23:19:59.007264 <3>[ 15.323466] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 23:19:59.017367 <3>[ 15.323529] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 23:19:59.023862 <6>[ 15.325226] Bluetooth: HCI device and connection manager initialized
10734 23:19:59.027203 <6>[ 15.325260] Bluetooth: HCI socket layer initialized
10735 23:19:59.034040 <6>[ 15.325273] Bluetooth: L2CAP socket layer initialized
10736 23:19:59.037283 <6>[ 15.325296] Bluetooth: SCO socket layer initialized
10737 23:19:59.044061 <6>[ 15.346832] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10738 23:19:59.053865 <6>[ 15.389863] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10739 23:19:59.060337 <6>[ 15.397974] pci_bus 0000:00: root bus resource [bus 00-ff]
10740 23:19:59.067020 <6>[ 15.404202] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10741 23:19:59.077349 <6>[ 15.406947] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10742 23:19:59.087327 <6>[ 15.414338] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10743 23:19:59.093800 <6>[ 15.422629] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10744 23:19:59.101436 <6>[ 15.422639] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10745 23:19:59.106801 <6>[ 15.422646] remoteproc remoteproc0: remote processor scp is now up
10746 23:19:59.116819 <6>[ 15.423839] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10747 23:19:59.127267 <6>[ 15.430716] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10748 23:19:59.133864 <6>[ 15.430815] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10749 23:19:59.140156 <6>[ 15.430837] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10750 23:19:59.143677 <6>[ 15.430942] pci 0000:00:00.0: supports D1 D2
10751 23:19:59.153498 <3>[ 15.440065] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10752 23:19:59.163226 <4>[ 15.444062] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10753 23:19:59.169966 <4>[ 15.444074] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10754 23:19:59.177058 <6>[ 15.447024] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10755 23:19:59.186745 <6>[ 15.448509] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10756 23:19:59.193153 <6>[ 15.466750] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10757 23:19:59.200210 <6>[ 15.471621] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10758 23:19:59.203585 <6>[ 15.472395] usbcore: registered new interface driver btusb
10759 23:19:59.213316 <4>[ 15.473716] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10760 23:19:59.220601 <3>[ 15.473726] Bluetooth: hci0: Failed to load firmware file (-2)
10761 23:19:59.226758 <3>[ 15.473729] Bluetooth: hci0: Failed to set up firmware (-2)
10762 23:19:59.237271 <4>[ 15.473733] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10763 23:19:59.249835 <6>[ 15.480725] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10764 23:19:59.256393 <6>[ 15.486127] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10765 23:19:59.266291 <6>[ 15.487640] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10766 23:19:59.272952 <6>[ 15.489401] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10767 23:19:59.280059 <6>[ 15.491593] usbcore: registered new interface driver uvcvideo
10768 23:19:59.282864 <6>[ 15.491697] r8152 2-1.3:1.0 eth0: v1.12.13
10769 23:19:59.289569 <6>[ 15.491760] usbcore: registered new interface driver r8152
10770 23:19:59.296733 <6>[ 15.492241] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10771 23:19:59.302879 <6>[ 15.496564] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10772 23:19:59.309497 <6>[ 15.501998] usbcore: registered new interface driver cdc_ether
10773 23:19:59.316484 <6>[ 15.508563] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10774 23:19:59.322937 <6>[ 15.522817] usbcore: registered new interface driver r8153_ecm
10775 23:19:59.329457 <6>[ 15.532027] pci 0000:01:00.0: supports D1 D2
10776 23:19:59.336214 <6>[ 15.791622] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10777 23:19:59.352060 <6>[ 15.807573] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10778 23:19:59.358675 <6>[ 15.814476] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10779 23:19:59.365553 <6>[ 15.822557] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10780 23:19:59.375494 <6>[ 15.830556] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10781 23:19:59.382050 <6>[ 15.838557] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10782 23:19:59.391983 <6>[ 15.846558] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10783 23:19:59.395593 <6>[ 15.854558] pci 0000:00:00.0: PCI bridge to [bus 01]
10784 23:19:59.405513 <6>[ 15.859775] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10785 23:19:59.412443 <6>[ 15.867926] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10786 23:19:59.418631 <6>[ 15.874773] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10787 23:19:59.425335 <6>[ 15.881561] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10788 23:19:59.448322 <5>[ 15.903740] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10789 23:19:59.480656 <5>[ 15.935861] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10790 23:19:59.487198 <5>[ 15.943773] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10791 23:19:59.497203 <4>[ 15.952315] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10792 23:19:59.503628 <6>[ 15.961227] cfg80211: failed to load regulatory.db
10793 23:19:59.562896 <6>[ 16.018229] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10794 23:19:59.569779 <6>[ 16.025806] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10795 23:19:59.594800 <6>[ 16.052737] mt7921e 0000:01:00.0: ASIC revision: 79610010
10796 23:19:59.696816 <6>[ 16.152296] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10797 23:19:59.700063 <6>[ 16.152296]
10798 23:19:59.700178 done
10799 23:19:59.712484 Saving random seed: OK
10800 23:19:59.728084 Starting network: OK
10801 23:19:59.759845 Starting dropbear sshd: <6>[ 16.218550] NET: Registered PF_INET6 protocol family
10802 23:19:59.766695 <6>[ 16.224853] Segment Routing with IPv6
10803 23:19:59.769687 <6>[ 16.228832] In-situ OAM (IOAM) with IPv6
10804 23:19:59.773474 OK
10805 23:19:59.783201 /bin/sh: can't access tty; job control turned off
10806 23:19:59.783539 Matched prompt #10: / #
10808 23:19:59.783745 Setting prompt string to ['/ #']
10809 23:19:59.783861 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10811 23:19:59.784161 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10812 23:19:59.784272 start: 2.2.6 expect-shell-connection (timeout 00:03:18) [common]
10813 23:19:59.784370 Setting prompt string to ['/ #']
10814 23:19:59.784456 Forcing a shell prompt, looking for ['/ #']
10816 23:19:59.834690 / #
10817 23:19:59.834789 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10818 23:19:59.834868 Waiting using forced prompt support (timeout 00:02:30)
10819 23:19:59.840487
10820 23:19:59.840747 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10821 23:19:59.840838 start: 2.2.7 export-device-env (timeout 00:03:18) [common]
10822 23:19:59.840926 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10823 23:19:59.841007 end: 2.2 depthcharge-retry (duration 00:01:42) [common]
10824 23:19:59.841092 end: 2 depthcharge-action (duration 00:01:42) [common]
10825 23:19:59.841177 start: 3 lava-test-retry (timeout 00:01:00) [common]
10826 23:19:59.841260 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10827 23:19:59.841336 Using namespace: common
10829 23:19:59.941620 / # #
10830 23:19:59.941766 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10831 23:19:59.946950 #
10832 23:19:59.947212 Using /lava-13248486
10834 23:20:00.047493 / # export SHELL=/bin/sh
10835 23:20:00.047707 <6>[ 16.421424] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10836 23:20:00.053176 export SHELL=/bin/sh
10838 23:20:00.153690 / # . /lava-13248486/environment
10839 23:20:00.158903 . /lava-13248486/environment
10841 23:20:00.259418 / # /lava-13248486/bin/lava-test-runner /lava-13248486/0
10842 23:20:00.259584 Test shell timeout: 10s (minimum of the action and connection timeout)
10843 23:20:00.265122 /lava-13248486/bin/lava-test-runner /lava-13248486/0
10844 23:20:00.284519 + export 'TESTRUN_ID=0_dmesg'
10845 23:20:00.290720 +<8>[ 16.748465] <LAVA_SIGNAL_STARTRUN 0_dmesg 13248486_1.5.2.3.1>
10846 23:20:00.290984 Received signal: <STARTRUN> 0_dmesg 13248486_1.5.2.3.1
10847 23:20:00.291057 Starting test lava.0_dmesg (13248486_1.5.2.3.1)
10848 23:20:00.291139 Skipping test definition patterns.
10849 23:20:00.293822 cd /lava-13248486/0/tests/0_dmesg
10850 23:20:00.293913 + cat uuid
10851 23:20:00.297340 + UUID=13248486_1.5.2.3.1
10852 23:20:00.297422 + set +x
10853 23:20:00.303821 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10854 23:20:00.314005 <8>[ 16.768142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10855 23:20:00.314252 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10857 23:20:00.335121 <8>[ 16.790567] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10858 23:20:00.335371 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10860 23:20:00.358759 <8>[ 16.814094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10861 23:20:00.359007 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10863 23:20:00.362173 + set +x
10864 23:20:00.365566 <8>[ 16.823541] <LAVA_SIGNAL_ENDRUN 0_dmesg 13248486_1.5.2.3.1>
10865 23:20:00.365812 Received signal: <ENDRUN> 0_dmesg 13248486_1.5.2.3.1
10866 23:20:00.365891 Ending use of test pattern.
10867 23:20:00.365960 Ending test lava.0_dmesg (13248486_1.5.2.3.1), duration 0.07
10869 23:20:00.368889 <LAVA_TEST_RUNNER EXIT>
10870 23:20:00.369159 ok: lava_test_shell seems to have completed
10871 23:20:00.369305 alert: pass
crit: pass
emerg: pass
10872 23:20:00.369439 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10873 23:20:00.369548 end: 3 lava-test-retry (duration 00:00:01) [common]
10874 23:20:00.369641 start: 4 finalize (timeout 00:07:59) [common]
10875 23:20:00.369731 start: 4.1 power-off (timeout 00:00:30) [common]
10876 23:20:00.369888 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
10877 23:20:00.448896 >> Command sent successfully.
10878 23:20:00.453010 Returned 0 in 0 seconds
10879 23:20:00.554019 end: 4.1 power-off (duration 00:00:00) [common]
10881 23:20:00.555856 start: 4.2 read-feedback (timeout 00:07:59) [common]
10882 23:20:00.557539 Listened to connection for namespace 'common' for up to 1s
10883 23:20:01.557838 Finalising connection for namespace 'common'
10884 23:20:01.558041 Disconnecting from shell: Finalise
10885 23:20:01.558154 / #
10886 23:20:01.658516 end: 4.2 read-feedback (duration 00:00:01) [common]
10887 23:20:01.658678 end: 4 finalize (duration 00:00:01) [common]
10888 23:20:01.658803 Cleaning after the job
10889 23:20:01.658912 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248486/tftp-deploy-7v0d_pg_/ramdisk
10890 23:20:01.662057 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248486/tftp-deploy-7v0d_pg_/kernel
10891 23:20:01.671847 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248486/tftp-deploy-7v0d_pg_/dtb
10892 23:20:01.672062 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248486/tftp-deploy-7v0d_pg_/modules
10893 23:20:01.679656 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13248486
10894 23:20:01.728968 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13248486
10895 23:20:01.729137 Job finished correctly