Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
1 23:20:31.988933 lava-dispatcher, installed at version: 2024.01
2 23:20:31.989152 start: 0 validate
3 23:20:31.989289 Start time: 2024-04-03 23:20:31.989280+00:00 (UTC)
4 23:20:31.989412 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:20:31.989544 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:20:32.258447 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:20:32.258631 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:20:32.518571 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:20:32.518743 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:20:32.783779 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:20:32.783965 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:20:33.041626 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:20:33.041812 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:20:33.299587 validate duration: 1.31
16 23:20:33.299859 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:20:33.299956 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:20:33.300046 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:20:33.300177 Not decompressing ramdisk as can be used compressed.
20 23:20:33.300262 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 23:20:33.300331 saving as /var/lib/lava/dispatcher/tmp/13248464/tftp-deploy-vppbiez6/ramdisk/initrd.cpio.gz
22 23:20:33.300395 total size: 5628182 (5 MB)
23 23:20:33.301647 progress 0 % (0 MB)
24 23:20:33.303672 progress 5 % (0 MB)
25 23:20:33.305325 progress 10 % (0 MB)
26 23:20:33.306815 progress 15 % (0 MB)
27 23:20:33.308434 progress 20 % (1 MB)
28 23:20:33.309945 progress 25 % (1 MB)
29 23:20:33.311601 progress 30 % (1 MB)
30 23:20:33.313339 progress 35 % (1 MB)
31 23:20:33.314846 progress 40 % (2 MB)
32 23:20:33.316853 progress 45 % (2 MB)
33 23:20:33.318503 progress 50 % (2 MB)
34 23:20:33.320091 progress 55 % (2 MB)
35 23:20:33.321714 progress 60 % (3 MB)
36 23:20:33.323215 progress 65 % (3 MB)
37 23:20:33.325009 progress 70 % (3 MB)
38 23:20:33.326560 progress 75 % (4 MB)
39 23:20:33.328134 progress 80 % (4 MB)
40 23:20:33.329539 progress 85 % (4 MB)
41 23:20:33.331149 progress 90 % (4 MB)
42 23:20:33.332787 progress 95 % (5 MB)
43 23:20:33.334213 progress 100 % (5 MB)
44 23:20:33.334476 5 MB downloaded in 0.03 s (157.50 MB/s)
45 23:20:33.334645 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:20:33.334888 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:20:33.334976 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:20:33.335067 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:20:33.335213 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:20:33.335282 saving as /var/lib/lava/dispatcher/tmp/13248464/tftp-deploy-vppbiez6/kernel/Image
52 23:20:33.335348 total size: 54286848 (51 MB)
53 23:20:33.335411 No compression specified
54 23:20:33.336674 progress 0 % (0 MB)
55 23:20:33.352014 progress 5 % (2 MB)
56 23:20:33.366651 progress 10 % (5 MB)
57 23:20:33.381657 progress 15 % (7 MB)
58 23:20:33.396421 progress 20 % (10 MB)
59 23:20:33.411526 progress 25 % (12 MB)
60 23:20:33.426468 progress 30 % (15 MB)
61 23:20:33.441193 progress 35 % (18 MB)
62 23:20:33.456209 progress 40 % (20 MB)
63 23:20:33.470923 progress 45 % (23 MB)
64 23:20:33.485903 progress 50 % (25 MB)
65 23:20:33.501150 progress 55 % (28 MB)
66 23:20:33.516047 progress 60 % (31 MB)
67 23:20:33.530669 progress 65 % (33 MB)
68 23:20:33.545304 progress 70 % (36 MB)
69 23:20:33.560309 progress 75 % (38 MB)
70 23:20:33.574808 progress 80 % (41 MB)
71 23:20:33.589157 progress 85 % (44 MB)
72 23:20:33.603679 progress 90 % (46 MB)
73 23:20:33.617830 progress 95 % (49 MB)
74 23:20:33.631940 progress 100 % (51 MB)
75 23:20:33.632217 51 MB downloaded in 0.30 s (174.40 MB/s)
76 23:20:33.632383 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:20:33.632622 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:20:33.632709 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:20:33.632798 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:20:33.632946 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:20:33.633016 saving as /var/lib/lava/dispatcher/tmp/13248464/tftp-deploy-vppbiez6/dtb/mt8192-asurada-spherion-r0.dtb
83 23:20:33.633079 total size: 47230 (0 MB)
84 23:20:33.633143 No compression specified
85 23:20:33.634272 progress 69 % (0 MB)
86 23:20:33.634565 progress 100 % (0 MB)
87 23:20:33.634725 0 MB downloaded in 0.00 s (27.41 MB/s)
88 23:20:33.634850 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:20:33.635073 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:20:33.635164 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:20:33.635275 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:20:33.635414 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 23:20:33.635501 saving as /var/lib/lava/dispatcher/tmp/13248464/tftp-deploy-vppbiez6/nfsrootfs/full.rootfs.tar
95 23:20:33.635576 total size: 107552908 (102 MB)
96 23:20:33.635638 Using unxz to decompress xz
97 23:20:33.640884 progress 0 % (0 MB)
98 23:20:33.930154 progress 5 % (5 MB)
99 23:20:34.256803 progress 10 % (10 MB)
100 23:20:34.578236 progress 15 % (15 MB)
101 23:20:34.910860 progress 20 % (20 MB)
102 23:20:35.180002 progress 25 % (25 MB)
103 23:20:35.478026 progress 30 % (30 MB)
104 23:20:35.799426 progress 35 % (35 MB)
105 23:20:35.973474 progress 40 % (41 MB)
106 23:20:36.172811 progress 45 % (46 MB)
107 23:20:36.510863 progress 50 % (51 MB)
108 23:20:36.832798 progress 55 % (56 MB)
109 23:20:37.202921 progress 60 % (61 MB)
110 23:20:37.542299 progress 65 % (66 MB)
111 23:20:37.869154 progress 70 % (71 MB)
112 23:20:38.203532 progress 75 % (76 MB)
113 23:20:38.511171 progress 80 % (82 MB)
114 23:20:38.831907 progress 85 % (87 MB)
115 23:20:39.138261 progress 90 % (92 MB)
116 23:20:39.441693 progress 95 % (97 MB)
117 23:20:39.764447 progress 100 % (102 MB)
118 23:20:39.769519 102 MB downloaded in 6.13 s (16.72 MB/s)
119 23:20:39.769797 end: 1.4.1 http-download (duration 00:00:06) [common]
121 23:20:39.770101 end: 1.4 download-retry (duration 00:00:06) [common]
122 23:20:39.770193 start: 1.5 download-retry (timeout 00:09:54) [common]
123 23:20:39.770282 start: 1.5.1 http-download (timeout 00:09:54) [common]
124 23:20:39.770479 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:20:39.770549 saving as /var/lib/lava/dispatcher/tmp/13248464/tftp-deploy-vppbiez6/modules/modules.tar
126 23:20:39.770611 total size: 8629908 (8 MB)
127 23:20:39.770674 Using unxz to decompress xz
128 23:20:39.775267 progress 0 % (0 MB)
129 23:20:39.795607 progress 5 % (0 MB)
130 23:20:39.820436 progress 10 % (0 MB)
131 23:20:39.844543 progress 15 % (1 MB)
132 23:20:39.868382 progress 20 % (1 MB)
133 23:20:39.894999 progress 25 % (2 MB)
134 23:20:39.922235 progress 30 % (2 MB)
135 23:20:39.947984 progress 35 % (2 MB)
136 23:20:39.973377 progress 40 % (3 MB)
137 23:20:39.997406 progress 45 % (3 MB)
138 23:20:40.022618 progress 50 % (4 MB)
139 23:20:40.047485 progress 55 % (4 MB)
140 23:20:40.076215 progress 60 % (4 MB)
141 23:20:40.103190 progress 65 % (5 MB)
142 23:20:40.129214 progress 70 % (5 MB)
143 23:20:40.153414 progress 75 % (6 MB)
144 23:20:40.179717 progress 80 % (6 MB)
145 23:20:40.207764 progress 85 % (7 MB)
146 23:20:40.237992 progress 90 % (7 MB)
147 23:20:40.268706 progress 95 % (7 MB)
148 23:20:40.297220 progress 100 % (8 MB)
149 23:20:40.302935 8 MB downloaded in 0.53 s (15.46 MB/s)
150 23:20:40.303258 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:20:40.303538 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:20:40.303634 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 23:20:40.303730 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 23:20:42.472282 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13248464/extract-nfsrootfs-huwavqnr
156 23:20:42.472487 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 23:20:42.472595 start: 1.6.2 lava-overlay (timeout 00:09:51) [common]
158 23:20:42.472762 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo
159 23:20:42.472894 makedir: /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin
160 23:20:42.472997 makedir: /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/tests
161 23:20:42.473095 makedir: /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/results
162 23:20:42.473194 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-add-keys
163 23:20:42.473339 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-add-sources
164 23:20:42.473469 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-background-process-start
165 23:20:42.473597 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-background-process-stop
166 23:20:42.473725 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-common-functions
167 23:20:42.473853 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-echo-ipv4
168 23:20:42.473978 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-install-packages
169 23:20:42.474103 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-installed-packages
170 23:20:42.474227 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-os-build
171 23:20:42.474351 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-probe-channel
172 23:20:42.474662 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-probe-ip
173 23:20:42.474792 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-target-ip
174 23:20:42.474918 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-target-mac
175 23:20:42.475042 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-target-storage
176 23:20:42.475172 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-test-case
177 23:20:42.475299 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-test-event
178 23:20:42.475424 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-test-feedback
179 23:20:42.475549 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-test-raise
180 23:20:42.475675 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-test-reference
181 23:20:42.475801 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-test-runner
182 23:20:42.475925 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-test-set
183 23:20:42.476048 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-test-shell
184 23:20:42.476174 Updating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-install-packages (oe)
185 23:20:42.476329 Updating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/bin/lava-installed-packages (oe)
186 23:20:42.476452 Creating /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/environment
187 23:20:42.476548 LAVA metadata
188 23:20:42.476616 - LAVA_JOB_ID=13248464
189 23:20:42.476678 - LAVA_DISPATCHER_IP=192.168.201.1
190 23:20:42.476776 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:51) [common]
191 23:20:42.476844 skipped lava-vland-overlay
192 23:20:42.476917 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 23:20:42.476994 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
194 23:20:42.477053 skipped lava-multinode-overlay
195 23:20:42.477124 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 23:20:42.477199 start: 1.6.2.3 test-definition (timeout 00:09:51) [common]
197 23:20:42.477270 Loading test definitions
198 23:20:42.477354 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:51) [common]
199 23:20:42.477423 Using /lava-13248464 at stage 0
200 23:20:42.477738 uuid=13248464_1.6.2.3.1 testdef=None
201 23:20:42.477828 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 23:20:42.477912 start: 1.6.2.3.2 test-overlay (timeout 00:09:51) [common]
203 23:20:42.478441 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 23:20:42.478669 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:51) [common]
206 23:20:42.479306 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 23:20:42.479532 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
209 23:20:42.480149 runner path: /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/0/tests/0_dmesg test_uuid 13248464_1.6.2.3.1
210 23:20:42.480308 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 23:20:42.480509 Creating lava-test-runner.conf files
213 23:20:42.480570 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13248464/lava-overlay-abz834lo/lava-13248464/0 for stage 0
214 23:20:42.480659 - 0_dmesg
215 23:20:42.480756 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 23:20:42.480838 start: 1.6.2.4 compress-overlay (timeout 00:09:51) [common]
217 23:20:42.487005 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 23:20:42.487106 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
219 23:20:42.487190 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 23:20:42.487273 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 23:20:42.487357 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
222 23:20:42.659710 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 23:20:42.660117 start: 1.6.4 extract-modules (timeout 00:09:51) [common]
224 23:20:42.660238 extracting modules file /var/lib/lava/dispatcher/tmp/13248464/tftp-deploy-vppbiez6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248464/extract-nfsrootfs-huwavqnr
225 23:20:42.880706 extracting modules file /var/lib/lava/dispatcher/tmp/13248464/tftp-deploy-vppbiez6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248464/extract-overlay-ramdisk-419eff43/ramdisk
226 23:20:43.109822 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 23:20:43.109993 start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
228 23:20:43.110084 [common] Applying overlay to NFS
229 23:20:43.110155 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248464/compress-overlay-hcpc4mrp/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13248464/extract-nfsrootfs-huwavqnr
230 23:20:43.116819 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 23:20:43.116938 start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
232 23:20:43.117033 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 23:20:43.117120 start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
234 23:20:43.117199 Building ramdisk /var/lib/lava/dispatcher/tmp/13248464/extract-overlay-ramdisk-419eff43/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13248464/extract-overlay-ramdisk-419eff43/ramdisk
235 23:20:43.465284 >> 130593 blocks
236 23:20:45.512364 rename /var/lib/lava/dispatcher/tmp/13248464/extract-overlay-ramdisk-419eff43/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13248464/tftp-deploy-vppbiez6/ramdisk/ramdisk.cpio.gz
237 23:20:45.512958 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 23:20:45.513094 start: 1.6.8 prepare-kernel (timeout 00:09:48) [common]
239 23:20:45.513198 start: 1.6.8.1 prepare-fit (timeout 00:09:48) [common]
240 23:20:45.513307 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13248464/tftp-deploy-vppbiez6/kernel/Image'
241 23:20:59.119964 Returned 0 in 13 seconds
242 23:20:59.220680 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13248464/tftp-deploy-vppbiez6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13248464/tftp-deploy-vppbiez6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13248464/tftp-deploy-vppbiez6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13248464/tftp-deploy-vppbiez6/kernel/image.itb
243 23:20:59.599490 output: FIT description: Kernel Image image with one or more FDT blobs
244 23:20:59.599941 output: Created: Thu Apr 4 00:20:59 2024
245 23:20:59.600047 output: Image 0 (kernel-1)
246 23:20:59.600138 output: Description:
247 23:20:59.600230 output: Created: Thu Apr 4 00:20:59 2024
248 23:20:59.600324 output: Type: Kernel Image
249 23:20:59.600418 output: Compression: lzma compressed
250 23:20:59.600519 output: Data Size: 12907270 Bytes = 12604.76 KiB = 12.31 MiB
251 23:20:59.600633 output: Architecture: AArch64
252 23:20:59.600740 output: OS: Linux
253 23:20:59.600836 output: Load Address: 0x00000000
254 23:20:59.600930 output: Entry Point: 0x00000000
255 23:20:59.601026 output: Hash algo: crc32
256 23:20:59.601117 output: Hash value: d7c9dcc1
257 23:20:59.601209 output: Image 1 (fdt-1)
258 23:20:59.601296 output: Description: mt8192-asurada-spherion-r0
259 23:20:59.601380 output: Created: Thu Apr 4 00:20:59 2024
260 23:20:59.601468 output: Type: Flat Device Tree
261 23:20:59.601554 output: Compression: uncompressed
262 23:20:59.601641 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
263 23:20:59.601728 output: Architecture: AArch64
264 23:20:59.601815 output: Hash algo: crc32
265 23:20:59.601901 output: Hash value: 4bf0d1ac
266 23:20:59.601986 output: Image 2 (ramdisk-1)
267 23:20:59.602075 output: Description: unavailable
268 23:20:59.602164 output: Created: Thu Apr 4 00:20:59 2024
269 23:20:59.602252 output: Type: RAMDisk Image
270 23:20:59.602338 output: Compression: Unknown Compression
271 23:20:59.602457 output: Data Size: 18773303 Bytes = 18333.30 KiB = 17.90 MiB
272 23:20:59.602560 output: Architecture: AArch64
273 23:20:59.602648 output: OS: Linux
274 23:20:59.602735 output: Load Address: unavailable
275 23:20:59.602823 output: Entry Point: unavailable
276 23:20:59.602906 output: Hash algo: crc32
277 23:20:59.602986 output: Hash value: f6a3e556
278 23:20:59.603069 output: Default Configuration: 'conf-1'
279 23:20:59.603156 output: Configuration 0 (conf-1)
280 23:20:59.603242 output: Description: mt8192-asurada-spherion-r0
281 23:20:59.603329 output: Kernel: kernel-1
282 23:20:59.603415 output: Init Ramdisk: ramdisk-1
283 23:20:59.603501 output: FDT: fdt-1
284 23:20:59.603588 output: Loadables: kernel-1
285 23:20:59.603675 output:
286 23:20:59.603945 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 23:20:59.604084 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 23:20:59.604248 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
289 23:20:59.604387 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
290 23:20:59.604508 No LXC device requested
291 23:20:59.604628 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 23:20:59.604758 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
293 23:20:59.604873 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 23:20:59.604979 Checking files for TFTP limit of 4294967296 bytes.
295 23:20:59.605648 end: 1 tftp-deploy (duration 00:00:26) [common]
296 23:20:59.605790 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 23:20:59.605919 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 23:20:59.606097 substitutions:
299 23:20:59.606197 - {DTB}: 13248464/tftp-deploy-vppbiez6/dtb/mt8192-asurada-spherion-r0.dtb
300 23:20:59.606296 - {INITRD}: 13248464/tftp-deploy-vppbiez6/ramdisk/ramdisk.cpio.gz
301 23:20:59.606388 - {KERNEL}: 13248464/tftp-deploy-vppbiez6/kernel/Image
302 23:20:59.606522 - {LAVA_MAC}: None
303 23:20:59.606612 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13248464/extract-nfsrootfs-huwavqnr
304 23:20:59.606702 - {NFS_SERVER_IP}: 192.168.201.1
305 23:20:59.606791 - {PRESEED_CONFIG}: None
306 23:20:59.606880 - {PRESEED_LOCAL}: None
307 23:20:59.606968 - {RAMDISK}: 13248464/tftp-deploy-vppbiez6/ramdisk/ramdisk.cpio.gz
308 23:20:59.607056 - {ROOT_PART}: None
309 23:20:59.607144 - {ROOT}: None
310 23:20:59.607231 - {SERVER_IP}: 192.168.201.1
311 23:20:59.607319 - {TEE}: None
312 23:20:59.607418 Parsed boot commands:
313 23:20:59.607508 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 23:20:59.607754 Parsed boot commands: tftpboot 192.168.201.1 13248464/tftp-deploy-vppbiez6/kernel/image.itb 13248464/tftp-deploy-vppbiez6/kernel/cmdline
315 23:20:59.607880 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 23:20:59.608005 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 23:20:59.608140 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 23:20:59.608273 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 23:20:59.608386 Not connected, no need to disconnect.
320 23:20:59.608509 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 23:20:59.608628 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 23:20:59.608732 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
323 23:20:59.613513 Setting prompt string to ['lava-test: # ']
324 23:20:59.613981 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 23:20:59.614132 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 23:20:59.614289 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 23:20:59.614457 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 23:20:59.614756 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
329 23:21:04.749729 >> Command sent successfully.
330 23:21:04.752342 Returned 0 in 5 seconds
331 23:21:04.852815 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 23:21:04.853173 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 23:21:04.853278 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 23:21:04.853369 Setting prompt string to 'Starting depthcharge on Spherion...'
336 23:21:04.853439 Changing prompt to 'Starting depthcharge on Spherion...'
337 23:21:04.853506 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 23:21:04.853771 [Enter `^Ec?' for help]
339 23:21:05.027208
340 23:21:05.027377
341 23:21:05.027450 F0: 102B 0000
342 23:21:05.027517
343 23:21:05.027579 F3: 1001 0000 [0200]
344 23:21:05.031317
345 23:21:05.031421 F3: 1001 0000
346 23:21:05.031489
347 23:21:05.031550 F7: 102D 0000
348 23:21:05.031610
349 23:21:05.034322 F1: 0000 0000
350 23:21:05.034454
351 23:21:05.034520 V0: 0000 0000 [0001]
352 23:21:05.034586
353 23:21:05.037293 00: 0007 8000
354 23:21:05.037396
355 23:21:05.037462 01: 0000 0000
356 23:21:05.037525
357 23:21:05.041043 BP: 0C00 0209 [0000]
358 23:21:05.041145
359 23:21:05.041211 G0: 1182 0000
360 23:21:05.041272
361 23:21:05.044613 EC: 0000 0021 [4000]
362 23:21:05.044721
363 23:21:05.044790 S7: 0000 0000 [0000]
364 23:21:05.044852
365 23:21:05.048130 CC: 0000 0000 [0001]
366 23:21:05.048232
367 23:21:05.048299 T0: 0000 0040 [010F]
368 23:21:05.048361
369 23:21:05.048419 Jump to BL
370 23:21:05.051094
371 23:21:05.074557
372 23:21:05.074720
373 23:21:05.074792
374 23:21:05.082026 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 23:21:05.085731 ARM64: Exception handlers installed.
376 23:21:05.089104 ARM64: Testing exception
377 23:21:05.092630 ARM64: Done test exception
378 23:21:05.099370 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 23:21:05.109364 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 23:21:05.115956 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 23:21:05.126358 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 23:21:05.132602 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 23:21:05.139466 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 23:21:05.151548 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 23:21:05.158777 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 23:21:05.178200 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 23:21:05.180617 WDT: Last reset was cold boot
388 23:21:05.183969 SPI1(PAD0) initialized at 2873684 Hz
389 23:21:05.187248 SPI5(PAD0) initialized at 992727 Hz
390 23:21:05.190374 VBOOT: Loading verstage.
391 23:21:05.197084 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 23:21:05.200960 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 23:21:05.204035 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 23:21:05.207503 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 23:21:05.214541 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 23:21:05.221007 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 23:21:05.232325 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
398 23:21:05.232485
399 23:21:05.232557
400 23:21:05.242428 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 23:21:05.245533 ARM64: Exception handlers installed.
402 23:21:05.248793 ARM64: Testing exception
403 23:21:05.248914 ARM64: Done test exception
404 23:21:05.255912 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 23:21:05.259147 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 23:21:05.275079 Probing TPM: . done!
407 23:21:05.275248 TPM ready after 0 ms
408 23:21:05.281775 Connected to device vid:did:rid of 1ae0:0028:00
409 23:21:05.288928 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
410 23:21:05.345704 Initialized TPM device CR50 revision 0
411 23:21:05.357247 tlcl_send_startup: Startup return code is 0
412 23:21:05.357406 TPM: setup succeeded
413 23:21:05.368940 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 23:21:05.378032 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 23:21:05.389754 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 23:21:05.399927 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 23:21:05.404196 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 23:21:05.408209 in-header: 03 07 00 00 08 00 00 00
419 23:21:05.412510 in-data: aa e4 47 04 13 02 00 00
420 23:21:05.415541 Chrome EC: UHEPI supported
421 23:21:05.423612 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 23:21:05.426746 in-header: 03 ad 00 00 08 00 00 00
423 23:21:05.430068 in-data: 00 20 20 08 00 00 00 00
424 23:21:05.430204 Phase 1
425 23:21:05.434048 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 23:21:05.440887 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 23:21:05.444829 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 23:21:05.448512 Recovery requested (1009000e)
429 23:21:05.457766 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 23:21:05.462887 tlcl_extend: response is 0
431 23:21:05.471854 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 23:21:05.477541 tlcl_extend: response is 0
433 23:21:05.485019 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 23:21:05.504543 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 23:21:05.511318 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 23:21:05.511473
437 23:21:05.511545
438 23:21:05.522321 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 23:21:05.526131 ARM64: Exception handlers installed.
440 23:21:05.526270 ARM64: Testing exception
441 23:21:05.529521 ARM64: Done test exception
442 23:21:05.550134 pmic_efuse_setting: Set efuses in 11 msecs
443 23:21:05.553309 pmwrap_interface_init: Select PMIF_VLD_RDY
444 23:21:05.560007 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 23:21:05.564415 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 23:21:05.570886 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 23:21:05.574383 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 23:21:05.578720 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 23:21:05.583007 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 23:21:05.590101 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 23:21:05.593328 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 23:21:05.597641 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 23:21:05.600838 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 23:21:05.608352 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 23:21:05.612043 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 23:21:05.616170 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 23:21:05.623615 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 23:21:05.627571 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 23:21:05.635141 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 23:21:05.638656 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 23:21:05.645917 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 23:21:05.650072 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 23:21:05.657074 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 23:21:05.660532 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 23:21:05.667919 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 23:21:05.672037 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 23:21:05.679144 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 23:21:05.682989 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 23:21:05.690239 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 23:21:05.694684 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 23:21:05.697436 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 23:21:05.704928 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 23:21:05.708657 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 23:21:05.712921 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 23:21:05.719991 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 23:21:05.723681 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 23:21:05.727499 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 23:21:05.734462 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 23:21:05.738567 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 23:21:05.746847 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 23:21:05.749874 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 23:21:05.754633 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 23:21:05.757569 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 23:21:05.761001 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 23:21:05.765119 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 23:21:05.771940 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 23:21:05.776271 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 23:21:05.779766 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 23:21:05.783376 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 23:21:05.786796 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 23:21:05.794235 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 23:21:05.798289 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 23:21:05.801653 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 23:21:05.805048 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 23:21:05.813170 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 23:21:05.820631 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 23:21:05.824235 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 23:21:05.835955 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 23:21:05.842823 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 23:21:05.847271 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 23:21:05.850177 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 23:21:05.854049 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 23:21:05.863076 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x2a
504 23:21:05.866656 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 23:21:05.871867 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
506 23:21:05.878605 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 23:21:05.887458 [RTC]rtc_get_frequency_meter,154: input=15, output=790
508 23:21:05.896806 [RTC]rtc_get_frequency_meter,154: input=23, output=978
509 23:21:05.906587 [RTC]rtc_get_frequency_meter,154: input=19, output=884
510 23:21:05.915907 [RTC]rtc_get_frequency_meter,154: input=17, output=838
511 23:21:05.926328 [RTC]rtc_get_frequency_meter,154: input=16, output=812
512 23:21:05.935128 [RTC]rtc_get_frequency_meter,154: input=15, output=790
513 23:21:05.945165 [RTC]rtc_get_frequency_meter,154: input=16, output=813
514 23:21:05.949044 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
515 23:21:05.953428 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
516 23:21:05.956430 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 23:21:05.964218 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 23:21:05.967638 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 23:21:05.971582 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 23:21:05.975073 ADC[4]: Raw value=900959 ID=7
521 23:21:05.975225 ADC[3]: Raw value=213336 ID=1
522 23:21:05.979512 RAM Code: 0x71
523 23:21:05.982696 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 23:21:05.986134 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 23:21:05.997201 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 23:21:06.000928 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 23:21:06.004700 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 23:21:06.008672 in-header: 03 07 00 00 08 00 00 00
529 23:21:06.012530 in-data: aa e4 47 04 13 02 00 00
530 23:21:06.016050 Chrome EC: UHEPI supported
531 23:21:06.023731 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 23:21:06.027361 in-header: 03 ed 00 00 08 00 00 00
533 23:21:06.030653 in-data: 80 20 60 08 00 00 00 00
534 23:21:06.034234 MRC: failed to locate region type 0.
535 23:21:06.038060 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 23:21:06.042059 DRAM-K: Running full calibration
537 23:21:06.048998 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 23:21:06.049186 header.status = 0x0
539 23:21:06.052730 header.version = 0x6 (expected: 0x6)
540 23:21:06.056953 header.size = 0xd00 (expected: 0xd00)
541 23:21:06.059765 header.flags = 0x0
542 23:21:06.063919 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 23:21:06.083157 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
544 23:21:06.090760 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 23:21:06.090956 dram_init: ddr_geometry: 2
546 23:21:06.094302 [EMI] MDL number = 2
547 23:21:06.098806 [EMI] Get MDL freq = 0
548 23:21:06.098987 dram_init: ddr_type: 0
549 23:21:06.102894 is_discrete_lpddr4: 1
550 23:21:06.103050 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 23:21:06.103161
552 23:21:06.103253
553 23:21:06.105998 [Bian_co] ETT version 0.0.0.1
554 23:21:06.110375 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 23:21:06.110542
556 23:21:06.116766 dramc_set_vcore_voltage set vcore to 650000
557 23:21:06.116942 Read voltage for 800, 4
558 23:21:06.117045 Vio18 = 0
559 23:21:06.120702 Vcore = 650000
560 23:21:06.120837 Vdram = 0
561 23:21:06.120935 Vddq = 0
562 23:21:06.124015 Vmddr = 0
563 23:21:06.124137 dram_init: config_dvfs: 1
564 23:21:06.131529 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 23:21:06.135318 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 23:21:06.139147 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
567 23:21:06.142340 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
568 23:21:06.146120 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
569 23:21:06.149242 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
570 23:21:06.152765 MEM_TYPE=3, freq_sel=18
571 23:21:06.155941 sv_algorithm_assistance_LP4_1600
572 23:21:06.159975 ============ PULL DRAM RESETB DOWN ============
573 23:21:06.162859 ========== PULL DRAM RESETB DOWN end =========
574 23:21:06.169565 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 23:21:06.172738 ===================================
576 23:21:06.172883 LPDDR4 DRAM CONFIGURATION
577 23:21:06.176720 ===================================
578 23:21:06.179446 EX_ROW_EN[0] = 0x0
579 23:21:06.183143 EX_ROW_EN[1] = 0x0
580 23:21:06.183295 LP4Y_EN = 0x0
581 23:21:06.186534 WORK_FSP = 0x0
582 23:21:06.186665 WL = 0x2
583 23:21:06.189506 RL = 0x2
584 23:21:06.189630 BL = 0x2
585 23:21:06.192828 RPST = 0x0
586 23:21:06.192955 RD_PRE = 0x0
587 23:21:06.196612 WR_PRE = 0x1
588 23:21:06.196740 WR_PST = 0x0
589 23:21:06.199892 DBI_WR = 0x0
590 23:21:06.200013 DBI_RD = 0x0
591 23:21:06.203156 OTF = 0x1
592 23:21:06.206348 ===================================
593 23:21:06.209936 ===================================
594 23:21:06.210079 ANA top config
595 23:21:06.213118 ===================================
596 23:21:06.217017 DLL_ASYNC_EN = 0
597 23:21:06.220387 ALL_SLAVE_EN = 1
598 23:21:06.220525 NEW_RANK_MODE = 1
599 23:21:06.223962 DLL_IDLE_MODE = 1
600 23:21:06.227395 LP45_APHY_COMB_EN = 1
601 23:21:06.230331 TX_ODT_DIS = 1
602 23:21:06.230474 NEW_8X_MODE = 1
603 23:21:06.233477 ===================================
604 23:21:06.236672 ===================================
605 23:21:06.240202 data_rate = 1600
606 23:21:06.244050 CKR = 1
607 23:21:06.247936 DQ_P2S_RATIO = 8
608 23:21:06.250683 ===================================
609 23:21:06.253811 CA_P2S_RATIO = 8
610 23:21:06.257047 DQ_CA_OPEN = 0
611 23:21:06.257199 DQ_SEMI_OPEN = 0
612 23:21:06.260408 CA_SEMI_OPEN = 0
613 23:21:06.263297 CA_FULL_RATE = 0
614 23:21:06.267275 DQ_CKDIV4_EN = 1
615 23:21:06.270236 CA_CKDIV4_EN = 1
616 23:21:06.270410 CA_PREDIV_EN = 0
617 23:21:06.274262 PH8_DLY = 0
618 23:21:06.276967 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 23:21:06.280494 DQ_AAMCK_DIV = 4
620 23:21:06.284093 CA_AAMCK_DIV = 4
621 23:21:06.287251 CA_ADMCK_DIV = 4
622 23:21:06.287399 DQ_TRACK_CA_EN = 0
623 23:21:06.290419 CA_PICK = 800
624 23:21:06.294205 CA_MCKIO = 800
625 23:21:06.297072 MCKIO_SEMI = 0
626 23:21:06.300828 PLL_FREQ = 3068
627 23:21:06.304819 DQ_UI_PI_RATIO = 32
628 23:21:06.304985 CA_UI_PI_RATIO = 0
629 23:21:06.308649 ===================================
630 23:21:06.312078 ===================================
631 23:21:06.316113 memory_type:LPDDR4
632 23:21:06.316277 GP_NUM : 10
633 23:21:06.319221 SRAM_EN : 1
634 23:21:06.319348 MD32_EN : 0
635 23:21:06.323535 ===================================
636 23:21:06.327227 [ANA_INIT] >>>>>>>>>>>>>>
637 23:21:06.331285 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 23:21:06.334923 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 23:21:06.337897 ===================================
640 23:21:06.338037 data_rate = 1600,PCW = 0X7600
641 23:21:06.341085 ===================================
642 23:21:06.344636 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 23:21:06.351232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 23:21:06.357907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 23:21:06.361275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 23:21:06.364528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 23:21:06.368127 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 23:21:06.371282 [ANA_INIT] flow start
649 23:21:06.371427 [ANA_INIT] PLL >>>>>>>>
650 23:21:06.374871 [ANA_INIT] PLL <<<<<<<<
651 23:21:06.378133 [ANA_INIT] MIDPI >>>>>>>>
652 23:21:06.378264 [ANA_INIT] MIDPI <<<<<<<<
653 23:21:06.381394 [ANA_INIT] DLL >>>>>>>>
654 23:21:06.384886 [ANA_INIT] flow end
655 23:21:06.388109 ============ LP4 DIFF to SE enter ============
656 23:21:06.391640 ============ LP4 DIFF to SE exit ============
657 23:21:06.394885 [ANA_INIT] <<<<<<<<<<<<<
658 23:21:06.398244 [Flow] Enable top DCM control >>>>>
659 23:21:06.401861 [Flow] Enable top DCM control <<<<<
660 23:21:06.404772 Enable DLL master slave shuffle
661 23:21:06.408410 ==============================================================
662 23:21:06.411681 Gating Mode config
663 23:21:06.415184 ==============================================================
664 23:21:06.418375 Config description:
665 23:21:06.428522 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 23:21:06.435280 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 23:21:06.438248 SELPH_MODE 0: By rank 1: By Phase
668 23:21:06.445232 ==============================================================
669 23:21:06.449038 GAT_TRACK_EN = 1
670 23:21:06.451753 RX_GATING_MODE = 2
671 23:21:06.455342 RX_GATING_TRACK_MODE = 2
672 23:21:06.458730 SELPH_MODE = 1
673 23:21:06.458873 PICG_EARLY_EN = 1
674 23:21:06.462695 VALID_LAT_VALUE = 1
675 23:21:06.468579 ==============================================================
676 23:21:06.472144 Enter into Gating configuration >>>>
677 23:21:06.475148 Exit from Gating configuration <<<<
678 23:21:06.479080 Enter into DVFS_PRE_config >>>>>
679 23:21:06.488626 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 23:21:06.491922 Exit from DVFS_PRE_config <<<<<
681 23:21:06.495154 Enter into PICG configuration >>>>
682 23:21:06.498679 Exit from PICG configuration <<<<
683 23:21:06.502076 [RX_INPUT] configuration >>>>>
684 23:21:06.505341 [RX_INPUT] configuration <<<<<
685 23:21:06.508385 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 23:21:06.515358 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 23:21:06.522937 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 23:21:06.525955 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 23:21:06.532693 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 23:21:06.539274 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 23:21:06.543250 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 23:21:06.546244 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 23:21:06.553191 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 23:21:06.556458 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 23:21:06.559656 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 23:21:06.563562 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 23:21:06.566776 ===================================
698 23:21:06.570125 LPDDR4 DRAM CONFIGURATION
699 23:21:06.573355 ===================================
700 23:21:06.576281 EX_ROW_EN[0] = 0x0
701 23:21:06.576422 EX_ROW_EN[1] = 0x0
702 23:21:06.579615 LP4Y_EN = 0x0
703 23:21:06.579755 WORK_FSP = 0x0
704 23:21:06.583247 WL = 0x2
705 23:21:06.583382 RL = 0x2
706 23:21:06.586700 BL = 0x2
707 23:21:06.586827 RPST = 0x0
708 23:21:06.589629 RD_PRE = 0x0
709 23:21:06.589750 WR_PRE = 0x1
710 23:21:06.593454 WR_PST = 0x0
711 23:21:06.593594 DBI_WR = 0x0
712 23:21:06.596524 DBI_RD = 0x0
713 23:21:06.596652 OTF = 0x1
714 23:21:06.600036 ===================================
715 23:21:06.606727 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 23:21:06.609970 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 23:21:06.613324 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 23:21:06.616421 ===================================
719 23:21:06.619891 LPDDR4 DRAM CONFIGURATION
720 23:21:06.623317 ===================================
721 23:21:06.623464 EX_ROW_EN[0] = 0x10
722 23:21:06.627222 EX_ROW_EN[1] = 0x0
723 23:21:06.629939 LP4Y_EN = 0x0
724 23:21:06.630071 WORK_FSP = 0x0
725 23:21:06.633687 WL = 0x2
726 23:21:06.633818 RL = 0x2
727 23:21:06.637067 BL = 0x2
728 23:21:06.637193 RPST = 0x0
729 23:21:06.640210 RD_PRE = 0x0
730 23:21:06.640337 WR_PRE = 0x1
731 23:21:06.643639 WR_PST = 0x0
732 23:21:06.643770 DBI_WR = 0x0
733 23:21:06.647172 DBI_RD = 0x0
734 23:21:06.647308 OTF = 0x1
735 23:21:06.650165 ===================================
736 23:21:06.657008 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 23:21:06.661038 nWR fixed to 40
738 23:21:06.664791 [ModeRegInit_LP4] CH0 RK0
739 23:21:06.664951 [ModeRegInit_LP4] CH0 RK1
740 23:21:06.667683 [ModeRegInit_LP4] CH1 RK0
741 23:21:06.671259 [ModeRegInit_LP4] CH1 RK1
742 23:21:06.671403 match AC timing 13
743 23:21:06.677934 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 23:21:06.680947 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 23:21:06.684128 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 23:21:06.691525 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 23:21:06.694201 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 23:21:06.694337 [EMI DOE] emi_dcm 0
749 23:21:06.701397 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 23:21:06.701579 ==
751 23:21:06.704467 Dram Type= 6, Freq= 0, CH_0, rank 0
752 23:21:06.708292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 23:21:06.708437 ==
754 23:21:06.714434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 23:21:06.717583 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 23:21:06.728752 [CA 0] Center 37 (7~68) winsize 62
757 23:21:06.732600 [CA 1] Center 37 (6~68) winsize 63
758 23:21:06.735157 [CA 2] Center 35 (5~66) winsize 62
759 23:21:06.738459 [CA 3] Center 34 (4~65) winsize 62
760 23:21:06.742420 [CA 4] Center 34 (4~64) winsize 61
761 23:21:06.745012 [CA 5] Center 33 (3~64) winsize 62
762 23:21:06.745132
763 23:21:06.748228 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 23:21:06.748333
765 23:21:06.751644 [CATrainingPosCal] consider 1 rank data
766 23:21:06.755059 u2DelayCellTimex100 = 270/100 ps
767 23:21:06.758721 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
768 23:21:06.762455 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
769 23:21:06.768758 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
770 23:21:06.772055 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
771 23:21:06.775198 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
772 23:21:06.779083 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
773 23:21:06.779207
774 23:21:06.782160 CA PerBit enable=1, Macro0, CA PI delay=33
775 23:21:06.782256
776 23:21:06.785779 [CBTSetCACLKResult] CA Dly = 33
777 23:21:06.785881 CS Dly: 5 (0~36)
778 23:21:06.785951 ==
779 23:21:06.789217 Dram Type= 6, Freq= 0, CH_0, rank 1
780 23:21:06.795731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 23:21:06.795999 ==
782 23:21:06.798640 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 23:21:06.805166 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 23:21:06.814577 [CA 0] Center 37 (6~68) winsize 63
785 23:21:06.819151 [CA 1] Center 37 (7~68) winsize 62
786 23:21:06.821362 [CA 2] Center 35 (4~66) winsize 63
787 23:21:06.824661 [CA 3] Center 34 (4~65) winsize 62
788 23:21:06.827947 [CA 4] Center 34 (4~64) winsize 61
789 23:21:06.831359 [CA 5] Center 33 (3~64) winsize 62
790 23:21:06.831503
791 23:21:06.834887 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 23:21:06.834995
793 23:21:06.838726 [CATrainingPosCal] consider 2 rank data
794 23:21:06.841446 u2DelayCellTimex100 = 270/100 ps
795 23:21:06.844983 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
796 23:21:06.848133 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
797 23:21:06.851389 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
798 23:21:06.858641 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
799 23:21:06.861846 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
800 23:21:06.865059 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 23:21:06.865207
802 23:21:06.868272 CA PerBit enable=1, Macro0, CA PI delay=33
803 23:21:06.868401
804 23:21:06.871734 [CBTSetCACLKResult] CA Dly = 33
805 23:21:06.871868 CS Dly: 6 (0~38)
806 23:21:06.871967
807 23:21:06.875255 ----->DramcWriteLeveling(PI) begin...
808 23:21:06.875381 ==
809 23:21:06.878861 Dram Type= 6, Freq= 0, CH_0, rank 0
810 23:21:06.882822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:21:06.885922 ==
812 23:21:06.886068 Write leveling (Byte 0): 30 => 30
813 23:21:06.889452 Write leveling (Byte 1): 29 => 29
814 23:21:06.893391 DramcWriteLeveling(PI) end<-----
815 23:21:06.893549
816 23:21:06.893650 ==
817 23:21:06.897545 Dram Type= 6, Freq= 0, CH_0, rank 0
818 23:21:06.900619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 23:21:06.900762 ==
820 23:21:06.904463 [Gating] SW mode calibration
821 23:21:06.911302 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 23:21:06.914525 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 23:21:06.921768 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 23:21:06.924509 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
825 23:21:06.927975 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
826 23:21:06.935108 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
827 23:21:06.938370 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 23:21:06.941282 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 23:21:06.948303 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 23:21:06.951328 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 23:21:06.955111 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 23:21:06.961424 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 23:21:06.965119 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 23:21:06.968229 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 23:21:06.971854 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 23:21:06.978585 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 23:21:06.981467 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 23:21:06.985479 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 23:21:06.992031 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 23:21:06.995726 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 23:21:06.998659 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
842 23:21:07.005195 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 23:21:07.008889 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 23:21:07.011656 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 23:21:07.018339 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 23:21:07.022179 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 23:21:07.025412 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 23:21:07.028662 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 23:21:07.035169 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
850 23:21:07.039314 0 9 12 | B1->B0 | 2727 3232 | 0 1 | (0 0) (1 1)
851 23:21:07.042432 0 9 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
852 23:21:07.048706 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 23:21:07.052145 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 23:21:07.055678 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 23:21:07.062556 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 23:21:07.065990 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
857 23:21:07.068762 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
858 23:21:07.076551 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (1 0)
859 23:21:07.078904 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:21:07.082105 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:21:07.086160 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:21:07.092611 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:21:07.096005 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:21:07.099342 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:21:07.106086 0 11 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
866 23:21:07.109065 0 11 12 | B1->B0 | 3d3d 3e3e | 0 0 | (0 0) (0 0)
867 23:21:07.112788 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 23:21:07.119256 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 23:21:07.122448 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 23:21:07.125795 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 23:21:07.132745 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 23:21:07.135806 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 23:21:07.139762 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
874 23:21:07.146313 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 23:21:07.149552 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 23:21:07.153341 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 23:21:07.156432 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 23:21:07.163080 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 23:21:07.165956 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 23:21:07.169755 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 23:21:07.176022 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 23:21:07.179892 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 23:21:07.182730 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 23:21:07.189887 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 23:21:07.192740 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 23:21:07.196509 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 23:21:07.203417 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 23:21:07.206535 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 23:21:07.209817 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
890 23:21:07.216178 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
891 23:21:07.216328 Total UI for P1: 0, mck2ui 16
892 23:21:07.223314 best dqsien dly found for B0: ( 0, 14, 8)
893 23:21:07.226441 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 23:21:07.229455 Total UI for P1: 0, mck2ui 16
895 23:21:07.233018 best dqsien dly found for B1: ( 0, 14, 10)
896 23:21:07.236979 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
897 23:21:07.239419 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
898 23:21:07.239527
899 23:21:07.243045 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
900 23:21:07.246647 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
901 23:21:07.250134 [Gating] SW calibration Done
902 23:21:07.250254 ==
903 23:21:07.253053 Dram Type= 6, Freq= 0, CH_0, rank 0
904 23:21:07.256197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
905 23:21:07.256313 ==
906 23:21:07.260119 RX Vref Scan: 0
907 23:21:07.260228
908 23:21:07.260358 RX Vref 0 -> 0, step: 1
909 23:21:07.263095
910 23:21:07.263192 RX Delay -130 -> 252, step: 16
911 23:21:07.269871 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
912 23:21:07.272998 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
913 23:21:07.276391 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
914 23:21:07.280230 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
915 23:21:07.283208 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
916 23:21:07.287022 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
917 23:21:07.293888 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
918 23:21:07.297229 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
919 23:21:07.300266 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
920 23:21:07.303372 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
921 23:21:07.307416 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
922 23:21:07.313476 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
923 23:21:07.316684 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
924 23:21:07.320287 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
925 23:21:07.323726 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
926 23:21:07.327013 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
927 23:21:07.330269 ==
928 23:21:07.330393 Dram Type= 6, Freq= 0, CH_0, rank 0
929 23:21:07.337216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 23:21:07.337347 ==
931 23:21:07.337420 DQS Delay:
932 23:21:07.341023 DQS0 = 0, DQS1 = 0
933 23:21:07.341112 DQM Delay:
934 23:21:07.341179 DQM0 = 83, DQM1 = 76
935 23:21:07.344286 DQ Delay:
936 23:21:07.347287 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
937 23:21:07.350915 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
938 23:21:07.353923 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
939 23:21:07.357911 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
940 23:21:07.358015
941 23:21:07.358085
942 23:21:07.358146 ==
943 23:21:07.361179 Dram Type= 6, Freq= 0, CH_0, rank 0
944 23:21:07.363888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 23:21:07.363983 ==
946 23:21:07.364049
947 23:21:07.364110
948 23:21:07.367229 TX Vref Scan disable
949 23:21:07.367316 == TX Byte 0 ==
950 23:21:07.374132 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
951 23:21:07.377252 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
952 23:21:07.377353 == TX Byte 1 ==
953 23:21:07.384226 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
954 23:21:07.387842 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
955 23:21:07.387942 ==
956 23:21:07.391084 Dram Type= 6, Freq= 0, CH_0, rank 0
957 23:21:07.393768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 23:21:07.393862 ==
959 23:21:07.408342 TX Vref=22, minBit 5, minWin=27, winSum=441
960 23:21:07.411295 TX Vref=24, minBit 5, minWin=27, winSum=442
961 23:21:07.415121 TX Vref=26, minBit 5, minWin=27, winSum=446
962 23:21:07.418782 TX Vref=28, minBit 5, minWin=27, winSum=450
963 23:21:07.421548 TX Vref=30, minBit 2, minWin=28, winSum=457
964 23:21:07.424960 TX Vref=32, minBit 2, minWin=28, winSum=456
965 23:21:07.431352 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 30
966 23:21:07.431469
967 23:21:07.435131 Final TX Range 1 Vref 30
968 23:21:07.435224
969 23:21:07.435289 ==
970 23:21:07.438171 Dram Type= 6, Freq= 0, CH_0, rank 0
971 23:21:07.442107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
972 23:21:07.442207 ==
973 23:21:07.442275
974 23:21:07.442336
975 23:21:07.445127 TX Vref Scan disable
976 23:21:07.448449 == TX Byte 0 ==
977 23:21:07.451836 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
978 23:21:07.455444 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
979 23:21:07.458724 == TX Byte 1 ==
980 23:21:07.461932 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
981 23:21:07.465371 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
982 23:21:07.465471
983 23:21:07.469604 [DATLAT]
984 23:21:07.469716 Freq=800, CH0 RK0
985 23:21:07.469790
986 23:21:07.471564 DATLAT Default: 0xa
987 23:21:07.471668 0, 0xFFFF, sum = 0
988 23:21:07.475828 1, 0xFFFF, sum = 0
989 23:21:07.475935 2, 0xFFFF, sum = 0
990 23:21:07.478991 3, 0xFFFF, sum = 0
991 23:21:07.479086 4, 0xFFFF, sum = 0
992 23:21:07.481680 5, 0xFFFF, sum = 0
993 23:21:07.481770 6, 0xFFFF, sum = 0
994 23:21:07.485077 7, 0xFFFF, sum = 0
995 23:21:07.485172 8, 0xFFFF, sum = 0
996 23:21:07.489107 9, 0x0, sum = 1
997 23:21:07.489207 10, 0x0, sum = 2
998 23:21:07.491714 11, 0x0, sum = 3
999 23:21:07.491806 12, 0x0, sum = 4
1000 23:21:07.495233 best_step = 10
1001 23:21:07.495325
1002 23:21:07.495395 ==
1003 23:21:07.499182 Dram Type= 6, Freq= 0, CH_0, rank 0
1004 23:21:07.502261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1005 23:21:07.502376 ==
1006 23:21:07.502516 RX Vref Scan: 1
1007 23:21:07.505480
1008 23:21:07.505573 Set Vref Range= 32 -> 127
1009 23:21:07.505666
1010 23:21:07.508686 RX Vref 32 -> 127, step: 1
1011 23:21:07.508777
1012 23:21:07.512551 RX Delay -95 -> 252, step: 8
1013 23:21:07.512643
1014 23:21:07.515573 Set Vref, RX VrefLevel [Byte0]: 32
1015 23:21:07.518651 [Byte1]: 32
1016 23:21:07.518746
1017 23:21:07.522945 Set Vref, RX VrefLevel [Byte0]: 33
1018 23:21:07.526445 [Byte1]: 33
1019 23:21:07.526549
1020 23:21:07.529529 Set Vref, RX VrefLevel [Byte0]: 34
1021 23:21:07.532989 [Byte1]: 34
1022 23:21:07.533082
1023 23:21:07.536189 Set Vref, RX VrefLevel [Byte0]: 35
1024 23:21:07.539495 [Byte1]: 35
1025 23:21:07.543592
1026 23:21:07.543695 Set Vref, RX VrefLevel [Byte0]: 36
1027 23:21:07.547502 [Byte1]: 36
1028 23:21:07.551097
1029 23:21:07.551204 Set Vref, RX VrefLevel [Byte0]: 37
1030 23:21:07.555171 [Byte1]: 37
1031 23:21:07.559295
1032 23:21:07.559405 Set Vref, RX VrefLevel [Byte0]: 38
1033 23:21:07.562565 [Byte1]: 38
1034 23:21:07.566563
1035 23:21:07.566712 Set Vref, RX VrefLevel [Byte0]: 39
1036 23:21:07.570073 [Byte1]: 39
1037 23:21:07.574051
1038 23:21:07.577277 Set Vref, RX VrefLevel [Byte0]: 40
1039 23:21:07.577390 [Byte1]: 40
1040 23:21:07.581366
1041 23:21:07.581455 Set Vref, RX VrefLevel [Byte0]: 41
1042 23:21:07.584825 [Byte1]: 41
1043 23:21:07.589720
1044 23:21:07.589837 Set Vref, RX VrefLevel [Byte0]: 42
1045 23:21:07.592359 [Byte1]: 42
1046 23:21:07.596529
1047 23:21:07.596628 Set Vref, RX VrefLevel [Byte0]: 43
1048 23:21:07.600148 [Byte1]: 43
1049 23:21:07.604577
1050 23:21:07.604683 Set Vref, RX VrefLevel [Byte0]: 44
1051 23:21:07.607963 [Byte1]: 44
1052 23:21:07.612121
1053 23:21:07.612250 Set Vref, RX VrefLevel [Byte0]: 45
1054 23:21:07.614807 [Byte1]: 45
1055 23:21:07.619086
1056 23:21:07.619192 Set Vref, RX VrefLevel [Byte0]: 46
1057 23:21:07.622579 [Byte1]: 46
1058 23:21:07.626753
1059 23:21:07.626898 Set Vref, RX VrefLevel [Byte0]: 47
1060 23:21:07.630193 [Byte1]: 47
1061 23:21:07.634354
1062 23:21:07.634492 Set Vref, RX VrefLevel [Byte0]: 48
1063 23:21:07.637928 [Byte1]: 48
1064 23:21:07.642764
1065 23:21:07.642925 Set Vref, RX VrefLevel [Byte0]: 49
1066 23:21:07.645701 [Byte1]: 49
1067 23:21:07.649642
1068 23:21:07.649767 Set Vref, RX VrefLevel [Byte0]: 50
1069 23:21:07.653187 [Byte1]: 50
1070 23:21:07.657368
1071 23:21:07.657479 Set Vref, RX VrefLevel [Byte0]: 51
1072 23:21:07.660903 [Byte1]: 51
1073 23:21:07.664887
1074 23:21:07.664992 Set Vref, RX VrefLevel [Byte0]: 52
1075 23:21:07.668277 [Byte1]: 52
1076 23:21:07.672519
1077 23:21:07.672731 Set Vref, RX VrefLevel [Byte0]: 53
1078 23:21:07.675758 [Byte1]: 53
1079 23:21:07.680136
1080 23:21:07.680265 Set Vref, RX VrefLevel [Byte0]: 54
1081 23:21:07.683294 [Byte1]: 54
1082 23:21:07.687858
1083 23:21:07.687957 Set Vref, RX VrefLevel [Byte0]: 55
1084 23:21:07.690965 [Byte1]: 55
1085 23:21:07.695460
1086 23:21:07.695559 Set Vref, RX VrefLevel [Byte0]: 56
1087 23:21:07.698970 [Byte1]: 56
1088 23:21:07.702937
1089 23:21:07.703041 Set Vref, RX VrefLevel [Byte0]: 57
1090 23:21:07.706301 [Byte1]: 57
1091 23:21:07.710564
1092 23:21:07.710667 Set Vref, RX VrefLevel [Byte0]: 58
1093 23:21:07.713865 [Byte1]: 58
1094 23:21:07.717897
1095 23:21:07.717992 Set Vref, RX VrefLevel [Byte0]: 59
1096 23:21:07.721930 [Byte1]: 59
1097 23:21:07.725643
1098 23:21:07.725732 Set Vref, RX VrefLevel [Byte0]: 60
1099 23:21:07.729044 [Byte1]: 60
1100 23:21:07.733120
1101 23:21:07.733212 Set Vref, RX VrefLevel [Byte0]: 61
1102 23:21:07.736535 [Byte1]: 61
1103 23:21:07.741015
1104 23:21:07.741108 Set Vref, RX VrefLevel [Byte0]: 62
1105 23:21:07.744404 [Byte1]: 62
1106 23:21:07.748982
1107 23:21:07.749087 Set Vref, RX VrefLevel [Byte0]: 63
1108 23:21:07.751829 [Byte1]: 63
1109 23:21:07.756513
1110 23:21:07.756612 Set Vref, RX VrefLevel [Byte0]: 64
1111 23:21:07.759199 [Byte1]: 64
1112 23:21:07.764368
1113 23:21:07.764470 Set Vref, RX VrefLevel [Byte0]: 65
1114 23:21:07.766861 [Byte1]: 65
1115 23:21:07.771754
1116 23:21:07.771884 Set Vref, RX VrefLevel [Byte0]: 66
1117 23:21:07.775617 [Byte1]: 66
1118 23:21:07.779585
1119 23:21:07.779685 Set Vref, RX VrefLevel [Byte0]: 67
1120 23:21:07.782938 [Byte1]: 67
1121 23:21:07.786210
1122 23:21:07.786306 Set Vref, RX VrefLevel [Byte0]: 68
1123 23:21:07.789784 [Byte1]: 68
1124 23:21:07.794189
1125 23:21:07.794295 Set Vref, RX VrefLevel [Byte0]: 69
1126 23:21:07.797534 [Byte1]: 69
1127 23:21:07.802182
1128 23:21:07.802286 Set Vref, RX VrefLevel [Byte0]: 70
1129 23:21:07.805074 [Byte1]: 70
1130 23:21:07.809061
1131 23:21:07.809169 Set Vref, RX VrefLevel [Byte0]: 71
1132 23:21:07.812426 [Byte1]: 71
1133 23:21:07.816703
1134 23:21:07.816808 Set Vref, RX VrefLevel [Byte0]: 72
1135 23:21:07.820392 [Byte1]: 72
1136 23:21:07.824878
1137 23:21:07.824986 Set Vref, RX VrefLevel [Byte0]: 73
1138 23:21:07.827749 [Byte1]: 73
1139 23:21:07.831891
1140 23:21:07.831991 Set Vref, RX VrefLevel [Byte0]: 74
1141 23:21:07.835788 [Byte1]: 74
1142 23:21:07.839494
1143 23:21:07.839622 Set Vref, RX VrefLevel [Byte0]: 75
1144 23:21:07.842932 [Byte1]: 75
1145 23:21:07.847734
1146 23:21:07.847852 Set Vref, RX VrefLevel [Byte0]: 76
1147 23:21:07.850375 [Byte1]: 76
1148 23:21:07.854746
1149 23:21:07.854847 Set Vref, RX VrefLevel [Byte0]: 77
1150 23:21:07.857881 [Byte1]: 77
1151 23:21:07.862854
1152 23:21:07.862964 Final RX Vref Byte 0 = 62 to rank0
1153 23:21:07.865721 Final RX Vref Byte 1 = 62 to rank0
1154 23:21:07.869045 Final RX Vref Byte 0 = 62 to rank1
1155 23:21:07.872214 Final RX Vref Byte 1 = 62 to rank1==
1156 23:21:07.875743 Dram Type= 6, Freq= 0, CH_0, rank 0
1157 23:21:07.879046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1158 23:21:07.882855 ==
1159 23:21:07.882992 DQS Delay:
1160 23:21:07.883094 DQS0 = 0, DQS1 = 0
1161 23:21:07.885766 DQM Delay:
1162 23:21:07.885875 DQM0 = 88, DQM1 = 78
1163 23:21:07.889338 DQ Delay:
1164 23:21:07.889456 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1165 23:21:07.893297 DQ4 =92, DQ5 =76, DQ6 =96, DQ7 =92
1166 23:21:07.896111 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1167 23:21:07.899415 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1168 23:21:07.899542
1169 23:21:07.902514
1170 23:21:07.909199 [DQSOSCAuto] RK0, (LSB)MR18= 0x220a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 401 ps
1171 23:21:07.912702 CH0 RK0: MR19=606, MR18=220A
1172 23:21:07.919914 CH0_RK0: MR19=0x606, MR18=0x220A, DQSOSC=401, MR23=63, INC=91, DEC=61
1173 23:21:07.920076
1174 23:21:07.923130 ----->DramcWriteLeveling(PI) begin...
1175 23:21:07.923254 ==
1176 23:21:07.926599 Dram Type= 6, Freq= 0, CH_0, rank 1
1177 23:21:07.929433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1178 23:21:07.929558 ==
1179 23:21:07.932701 Write leveling (Byte 0): 29 => 29
1180 23:21:07.936449 Write leveling (Byte 1): 30 => 30
1181 23:21:07.939450 DramcWriteLeveling(PI) end<-----
1182 23:21:07.939570
1183 23:21:07.939666 ==
1184 23:21:07.942678 Dram Type= 6, Freq= 0, CH_0, rank 1
1185 23:21:07.946190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1186 23:21:07.946316 ==
1187 23:21:07.949411 [Gating] SW mode calibration
1188 23:21:07.956514 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1189 23:21:08.004099 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1190 23:21:08.004321 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1191 23:21:08.004638 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1192 23:21:08.004770 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1193 23:21:08.004833 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 23:21:08.004905 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 23:21:08.004992 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 23:21:08.005064 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 23:21:08.005224 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 23:21:08.005329 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 23:21:08.005417 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 23:21:08.009667 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 23:21:08.012860 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 23:21:08.019669 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 23:21:08.023059 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 23:21:08.026773 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 23:21:08.033412 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 23:21:08.038117 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1207 23:21:08.039815 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1208 23:21:08.043719 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1209 23:21:08.050210 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1210 23:21:08.053448 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 23:21:08.056799 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 23:21:08.063352 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 23:21:08.066830 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 23:21:08.069933 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 23:21:08.077201 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 23:21:08.080197 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1217 23:21:08.083461 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1218 23:21:08.090422 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 23:21:08.094100 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 23:21:08.097449 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 23:21:08.100762 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 23:21:08.107142 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 23:21:08.110537 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1224 23:21:08.113600 0 10 8 | B1->B0 | 3030 2626 | 1 0 | (1 1) (1 0)
1225 23:21:08.120696 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1226 23:21:08.123714 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:21:08.126821 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:21:08.134390 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:21:08.138138 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:21:08.141982 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:21:08.145360 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:21:08.149182 0 11 8 | B1->B0 | 2424 3d3d | 0 0 | (0 0) (0 0)
1233 23:21:08.156074 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1234 23:21:08.159144 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 23:21:08.163267 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 23:21:08.167684 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 23:21:08.173418 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 23:21:08.177291 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 23:21:08.180472 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1240 23:21:08.186773 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1241 23:21:08.190115 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1242 23:21:08.193627 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 23:21:08.200050 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 23:21:08.204001 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 23:21:08.206720 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 23:21:08.210340 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 23:21:08.216962 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 23:21:08.220985 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 23:21:08.223516 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 23:21:08.230569 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 23:21:08.233401 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 23:21:08.236922 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 23:21:08.243731 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 23:21:08.247297 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 23:21:08.250189 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1256 23:21:08.254112 Total UI for P1: 0, mck2ui 16
1257 23:21:08.257304 best dqsien dly found for B0: ( 0, 14, 2)
1258 23:21:08.261289 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1259 23:21:08.267680 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 23:21:08.270735 Total UI for P1: 0, mck2ui 16
1261 23:21:08.274414 best dqsien dly found for B1: ( 0, 14, 6)
1262 23:21:08.277754 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1263 23:21:08.280673 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1264 23:21:08.280801
1265 23:21:08.284582 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1266 23:21:08.287571 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1267 23:21:08.290915 [Gating] SW calibration Done
1268 23:21:08.291044 ==
1269 23:21:08.294173 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 23:21:08.297435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 23:21:08.297586 ==
1272 23:21:08.300941 RX Vref Scan: 0
1273 23:21:08.301060
1274 23:21:08.301129 RX Vref 0 -> 0, step: 1
1275 23:21:08.301191
1276 23:21:08.304569 RX Delay -130 -> 252, step: 16
1277 23:21:08.307631 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1278 23:21:08.315078 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1279 23:21:08.317935 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1280 23:21:08.321182 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1281 23:21:08.324524 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1282 23:21:08.327478 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1283 23:21:08.334340 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1284 23:21:08.337928 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1285 23:21:08.340837 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1286 23:21:08.344012 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1287 23:21:08.348040 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1288 23:21:08.354627 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1289 23:21:08.357957 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1290 23:21:08.361320 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1291 23:21:08.364868 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1292 23:21:08.367952 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1293 23:21:08.371883 ==
1294 23:21:08.372000 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 23:21:08.377743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 23:21:08.377871 ==
1297 23:21:08.377943 DQS Delay:
1298 23:21:08.380913 DQS0 = 0, DQS1 = 0
1299 23:21:08.381001 DQM Delay:
1300 23:21:08.384208 DQM0 = 84, DQM1 = 74
1301 23:21:08.384296 DQ Delay:
1302 23:21:08.388586 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1303 23:21:08.390752 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
1304 23:21:08.394259 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1305 23:21:08.397728 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1306 23:21:08.397829
1307 23:21:08.397898
1308 23:21:08.397959 ==
1309 23:21:08.401565 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 23:21:08.404674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 23:21:08.404777 ==
1312 23:21:08.404847
1313 23:21:08.404909
1314 23:21:08.407697 TX Vref Scan disable
1315 23:21:08.407784 == TX Byte 0 ==
1316 23:21:08.414775 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1317 23:21:08.418222 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1318 23:21:08.418331 == TX Byte 1 ==
1319 23:21:08.425066 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1320 23:21:08.428585 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1321 23:21:08.428704 ==
1322 23:21:08.431067 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 23:21:08.434366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 23:21:08.434474 ==
1325 23:21:08.448362 TX Vref=22, minBit 1, minWin=27, winSum=443
1326 23:21:08.451945 TX Vref=24, minBit 2, minWin=27, winSum=443
1327 23:21:08.455472 TX Vref=26, minBit 6, minWin=27, winSum=450
1328 23:21:08.458677 TX Vref=28, minBit 9, minWin=27, winSum=450
1329 23:21:08.461873 TX Vref=30, minBit 0, minWin=28, winSum=452
1330 23:21:08.465306 TX Vref=32, minBit 0, minWin=28, winSum=450
1331 23:21:08.472237 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 30
1332 23:21:08.472381
1333 23:21:08.477395 Final TX Range 1 Vref 30
1334 23:21:08.477544
1335 23:21:08.477644 ==
1336 23:21:08.479140 Dram Type= 6, Freq= 0, CH_0, rank 1
1337 23:21:08.482272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1338 23:21:08.482363 ==
1339 23:21:08.482480
1340 23:21:08.482543
1341 23:21:08.485191 TX Vref Scan disable
1342 23:21:08.488585 == TX Byte 0 ==
1343 23:21:08.492313 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1344 23:21:08.495624 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1345 23:21:08.499716 == TX Byte 1 ==
1346 23:21:08.502787 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1347 23:21:08.505481 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1348 23:21:08.505595
1349 23:21:08.508811 [DATLAT]
1350 23:21:08.508904 Freq=800, CH0 RK1
1351 23:21:08.508971
1352 23:21:08.512309 DATLAT Default: 0xa
1353 23:21:08.512406 0, 0xFFFF, sum = 0
1354 23:21:08.515647 1, 0xFFFF, sum = 0
1355 23:21:08.515738 2, 0xFFFF, sum = 0
1356 23:21:08.518686 3, 0xFFFF, sum = 0
1357 23:21:08.518777 4, 0xFFFF, sum = 0
1358 23:21:08.523057 5, 0xFFFF, sum = 0
1359 23:21:08.523169 6, 0xFFFF, sum = 0
1360 23:21:08.525682 7, 0xFFFF, sum = 0
1361 23:21:08.525770 8, 0xFFFF, sum = 0
1362 23:21:08.528747 9, 0x0, sum = 1
1363 23:21:08.528856 10, 0x0, sum = 2
1364 23:21:08.532485 11, 0x0, sum = 3
1365 23:21:08.532582 12, 0x0, sum = 4
1366 23:21:08.536276 best_step = 10
1367 23:21:08.536370
1368 23:21:08.536435 ==
1369 23:21:08.538891 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 23:21:08.542348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 23:21:08.542469 ==
1372 23:21:08.545343 RX Vref Scan: 0
1373 23:21:08.545434
1374 23:21:08.545501 RX Vref 0 -> 0, step: 1
1375 23:21:08.545562
1376 23:21:08.549121 RX Delay -95 -> 252, step: 8
1377 23:21:08.555730 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1378 23:21:08.559302 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1379 23:21:08.562539 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1380 23:21:08.565637 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1381 23:21:08.569206 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1382 23:21:08.572296 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1383 23:21:08.579218 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1384 23:21:08.582930 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1385 23:21:08.585945 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1386 23:21:08.589418 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1387 23:21:08.592767 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1388 23:21:08.599527 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1389 23:21:08.603236 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1390 23:21:08.605967 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1391 23:21:08.609414 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1392 23:21:08.612570 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1393 23:21:08.612701 ==
1394 23:21:08.616031 Dram Type= 6, Freq= 0, CH_0, rank 1
1395 23:21:08.623512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 23:21:08.623670 ==
1397 23:21:08.623771 DQS Delay:
1398 23:21:08.625758 DQS0 = 0, DQS1 = 0
1399 23:21:08.625864 DQM Delay:
1400 23:21:08.625955 DQM0 = 87, DQM1 = 79
1401 23:21:08.629619 DQ Delay:
1402 23:21:08.632732 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1403 23:21:08.636711 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1404 23:21:08.639592 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1405 23:21:08.643004 DQ12 =84, DQ13 =88, DQ14 =88, DQ15 =88
1406 23:21:08.643127
1407 23:21:08.643223
1408 23:21:08.649538 [DQSOSCAuto] RK1, (LSB)MR18= 0x311b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1409 23:21:08.652437 CH0 RK1: MR19=606, MR18=311B
1410 23:21:08.659790 CH0_RK1: MR19=0x606, MR18=0x311B, DQSOSC=397, MR23=63, INC=93, DEC=62
1411 23:21:08.662801 [RxdqsGatingPostProcess] freq 800
1412 23:21:08.666511 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1413 23:21:08.669385 Pre-setting of DQS Precalculation
1414 23:21:08.676546 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1415 23:21:08.676718 ==
1416 23:21:08.679414 Dram Type= 6, Freq= 0, CH_1, rank 0
1417 23:21:08.682805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 23:21:08.682940 ==
1419 23:21:08.689608 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1420 23:21:08.693425 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1421 23:21:08.703146 [CA 0] Center 36 (6~67) winsize 62
1422 23:21:08.706813 [CA 1] Center 36 (6~67) winsize 62
1423 23:21:08.710012 [CA 2] Center 34 (4~64) winsize 61
1424 23:21:08.713721 [CA 3] Center 33 (3~64) winsize 62
1425 23:21:08.716509 [CA 4] Center 34 (4~65) winsize 62
1426 23:21:08.720537 [CA 5] Center 34 (4~64) winsize 61
1427 23:21:08.720662
1428 23:21:08.723158 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1429 23:21:08.723248
1430 23:21:08.726984 [CATrainingPosCal] consider 1 rank data
1431 23:21:08.730112 u2DelayCellTimex100 = 270/100 ps
1432 23:21:08.733312 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1433 23:21:08.736851 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1434 23:21:08.743309 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1435 23:21:08.746864 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1436 23:21:08.750070 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1437 23:21:08.753763 CA5 delay=34 (4~64),Diff = 1 PI (7 cell)
1438 23:21:08.753875
1439 23:21:08.757751 CA PerBit enable=1, Macro0, CA PI delay=33
1440 23:21:08.757851
1441 23:21:08.760064 [CBTSetCACLKResult] CA Dly = 33
1442 23:21:08.760153 CS Dly: 4 (0~35)
1443 23:21:08.760220 ==
1444 23:21:08.763244 Dram Type= 6, Freq= 0, CH_1, rank 1
1445 23:21:08.770501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 23:21:08.770641 ==
1447 23:21:08.773588 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1448 23:21:08.780687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1449 23:21:08.789923 [CA 0] Center 36 (6~66) winsize 61
1450 23:21:08.792604 [CA 1] Center 36 (6~66) winsize 61
1451 23:21:08.795960 [CA 2] Center 34 (4~65) winsize 62
1452 23:21:08.799492 [CA 3] Center 34 (3~65) winsize 63
1453 23:21:08.802961 [CA 4] Center 34 (4~65) winsize 62
1454 23:21:08.807389 [CA 5] Center 33 (3~64) winsize 62
1455 23:21:08.807508
1456 23:21:08.810938 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1457 23:21:08.811041
1458 23:21:08.814596 [CATrainingPosCal] consider 2 rank data
1459 23:21:08.818005 u2DelayCellTimex100 = 270/100 ps
1460 23:21:08.822011 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1461 23:21:08.825662 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1462 23:21:08.829552 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1463 23:21:08.833071 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1464 23:21:08.836865 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1465 23:21:08.840531 CA5 delay=34 (4~64),Diff = 1 PI (7 cell)
1466 23:21:08.840667
1467 23:21:08.843459 CA PerBit enable=1, Macro0, CA PI delay=33
1468 23:21:08.843555
1469 23:21:08.846953 [CBTSetCACLKResult] CA Dly = 33
1470 23:21:08.847051 CS Dly: 5 (0~37)
1471 23:21:08.847118
1472 23:21:08.849943 ----->DramcWriteLeveling(PI) begin...
1473 23:21:08.850035 ==
1474 23:21:08.854027 Dram Type= 6, Freq= 0, CH_1, rank 0
1475 23:21:08.857024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1476 23:21:08.859886 ==
1477 23:21:08.859984 Write leveling (Byte 0): 25 => 25
1478 23:21:08.863634 Write leveling (Byte 1): 31 => 31
1479 23:21:08.866691 DramcWriteLeveling(PI) end<-----
1480 23:21:08.866821
1481 23:21:08.866917 ==
1482 23:21:08.870362 Dram Type= 6, Freq= 0, CH_1, rank 0
1483 23:21:08.876921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1484 23:21:08.877078 ==
1485 23:21:08.877177 [Gating] SW mode calibration
1486 23:21:08.887054 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1487 23:21:08.890111 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1488 23:21:08.893716 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1489 23:21:08.900638 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1490 23:21:08.904177 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1491 23:21:08.907690 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 23:21:08.913828 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 23:21:08.917138 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 23:21:08.921426 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 23:21:08.927740 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 23:21:08.931080 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 23:21:08.934011 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 23:21:08.937368 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 23:21:08.944157 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 23:21:08.947629 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1501 23:21:08.950638 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 23:21:08.957364 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 23:21:08.961066 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1504 23:21:08.964117 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 23:21:08.970740 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1506 23:21:08.974253 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1507 23:21:08.977720 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 23:21:08.984479 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 23:21:08.987532 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 23:21:08.991086 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 23:21:08.994316 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 23:21:09.001537 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 23:21:09.004318 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 23:21:09.007808 0 9 8 | B1->B0 | 2a2a 2a2a | 0 0 | (0 0) (0 0)
1515 23:21:09.014800 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 23:21:09.017896 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 23:21:09.021082 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1518 23:21:09.027935 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 23:21:09.031091 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 23:21:09.035044 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1521 23:21:09.041564 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1522 23:21:09.045020 0 10 8 | B1->B0 | 2f2f 2e2e | 1 1 | (1 1) (1 0)
1523 23:21:09.048238 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:21:09.054960 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:21:09.059001 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1526 23:21:09.061675 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1527 23:21:09.065098 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:21:09.072158 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:21:09.075003 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:21:09.078197 0 11 8 | B1->B0 | 3434 3030 | 1 1 | (0 0) (0 0)
1531 23:21:09.086151 0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1532 23:21:09.088300 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 23:21:09.092399 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 23:21:09.098597 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 23:21:09.102259 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 23:21:09.104907 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 23:21:09.111731 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 23:21:09.115224 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1539 23:21:09.118794 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 23:21:09.122245 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 23:21:09.128991 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 23:21:09.131983 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 23:21:09.135853 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 23:21:09.142664 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 23:21:09.145543 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 23:21:09.148832 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 23:21:09.155489 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 23:21:09.159318 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 23:21:09.162270 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 23:21:09.168975 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 23:21:09.172071 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 23:21:09.175874 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 23:21:09.182205 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1554 23:21:09.185701 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1555 23:21:09.188829 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 23:21:09.192120 Total UI for P1: 0, mck2ui 16
1557 23:21:09.196002 best dqsien dly found for B0: ( 0, 14, 6)
1558 23:21:09.198944 Total UI for P1: 0, mck2ui 16
1559 23:21:09.202147 best dqsien dly found for B1: ( 0, 14, 8)
1560 23:21:09.205595 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1561 23:21:09.208855 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1562 23:21:09.208946
1563 23:21:09.212380 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1564 23:21:09.215572 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1565 23:21:09.219753 [Gating] SW calibration Done
1566 23:21:09.219860 ==
1567 23:21:09.222392 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 23:21:09.225638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 23:21:09.229351 ==
1570 23:21:09.229442 RX Vref Scan: 0
1571 23:21:09.229506
1572 23:21:09.232691 RX Vref 0 -> 0, step: 1
1573 23:21:09.232775
1574 23:21:09.236044 RX Delay -130 -> 252, step: 16
1575 23:21:09.239318 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1576 23:21:09.242980 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1577 23:21:09.246193 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1578 23:21:09.249331 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1579 23:21:09.252912 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1580 23:21:09.259925 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1581 23:21:09.263101 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1582 23:21:09.265953 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1583 23:21:09.269227 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1584 23:21:09.272606 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1585 23:21:09.279502 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1586 23:21:09.282902 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1587 23:21:09.286317 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1588 23:21:09.289874 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1589 23:21:09.293076 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1590 23:21:09.299493 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1591 23:21:09.299585 ==
1592 23:21:09.303225 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 23:21:09.306312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 23:21:09.306403 ==
1595 23:21:09.306484 DQS Delay:
1596 23:21:09.309551 DQS0 = 0, DQS1 = 0
1597 23:21:09.309633 DQM Delay:
1598 23:21:09.313270 DQM0 = 84, DQM1 = 76
1599 23:21:09.313352 DQ Delay:
1600 23:21:09.316493 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1601 23:21:09.320097 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1602 23:21:09.322901 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1603 23:21:09.326238 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1604 23:21:09.326320
1605 23:21:09.326384
1606 23:21:09.326480 ==
1607 23:21:09.329630 Dram Type= 6, Freq= 0, CH_1, rank 0
1608 23:21:09.333174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1609 23:21:09.333257 ==
1610 23:21:09.333321
1611 23:21:09.333380
1612 23:21:09.336313 TX Vref Scan disable
1613 23:21:09.339525 == TX Byte 0 ==
1614 23:21:09.343108 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1615 23:21:09.346746 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1616 23:21:09.349803 == TX Byte 1 ==
1617 23:21:09.353317 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1618 23:21:09.356773 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1619 23:21:09.356883 ==
1620 23:21:09.359822 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 23:21:09.363253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 23:21:09.366751 ==
1623 23:21:09.378283 TX Vref=22, minBit 0, minWin=27, winSum=439
1624 23:21:09.382306 TX Vref=24, minBit 0, minWin=27, winSum=442
1625 23:21:09.385751 TX Vref=26, minBit 0, minWin=27, winSum=445
1626 23:21:09.389130 TX Vref=28, minBit 15, minWin=27, winSum=449
1627 23:21:09.392315 TX Vref=30, minBit 0, minWin=28, winSum=454
1628 23:21:09.395706 TX Vref=32, minBit 0, minWin=28, winSum=451
1629 23:21:09.403216 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
1630 23:21:09.403337
1631 23:21:09.405822 Final TX Range 1 Vref 30
1632 23:21:09.405935
1633 23:21:09.406024 ==
1634 23:21:09.409707 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 23:21:09.413580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 23:21:09.413689 ==
1637 23:21:09.413792
1638 23:21:09.413881
1639 23:21:09.416478 TX Vref Scan disable
1640 23:21:09.419647 == TX Byte 0 ==
1641 23:21:09.422715 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1642 23:21:09.426036 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1643 23:21:09.429373 == TX Byte 1 ==
1644 23:21:09.432747 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1645 23:21:09.436197 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1646 23:21:09.436304
1647 23:21:09.436394 [DATLAT]
1648 23:21:09.439523 Freq=800, CH1 RK0
1649 23:21:09.439628
1650 23:21:09.442778 DATLAT Default: 0xa
1651 23:21:09.442883 0, 0xFFFF, sum = 0
1652 23:21:09.446628 1, 0xFFFF, sum = 0
1653 23:21:09.446739 2, 0xFFFF, sum = 0
1654 23:21:09.449817 3, 0xFFFF, sum = 0
1655 23:21:09.449926 4, 0xFFFF, sum = 0
1656 23:21:09.453376 5, 0xFFFF, sum = 0
1657 23:21:09.453487 6, 0xFFFF, sum = 0
1658 23:21:09.456800 7, 0xFFFF, sum = 0
1659 23:21:09.456909 8, 0xFFFF, sum = 0
1660 23:21:09.459694 9, 0x0, sum = 1
1661 23:21:09.459804 10, 0x0, sum = 2
1662 23:21:09.463144 11, 0x0, sum = 3
1663 23:21:09.463263 12, 0x0, sum = 4
1664 23:21:09.463358 best_step = 10
1665 23:21:09.463446
1666 23:21:09.466198 ==
1667 23:21:09.469646 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 23:21:09.473025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1669 23:21:09.473131 ==
1670 23:21:09.473222 RX Vref Scan: 1
1671 23:21:09.473312
1672 23:21:09.477043 Set Vref Range= 32 -> 127
1673 23:21:09.477146
1674 23:21:09.479938 RX Vref 32 -> 127, step: 1
1675 23:21:09.480039
1676 23:21:09.482783 RX Delay -95 -> 252, step: 8
1677 23:21:09.482895
1678 23:21:09.487320 Set Vref, RX VrefLevel [Byte0]: 32
1679 23:21:09.490044 [Byte1]: 32
1680 23:21:09.490146
1681 23:21:09.493078 Set Vref, RX VrefLevel [Byte0]: 33
1682 23:21:09.496149 [Byte1]: 33
1683 23:21:09.496254
1684 23:21:09.499588 Set Vref, RX VrefLevel [Byte0]: 34
1685 23:21:09.503027 [Byte1]: 34
1686 23:21:09.506335
1687 23:21:09.506498 Set Vref, RX VrefLevel [Byte0]: 35
1688 23:21:09.509648 [Byte1]: 35
1689 23:21:09.513760
1690 23:21:09.513864 Set Vref, RX VrefLevel [Byte0]: 36
1691 23:21:09.517225 [Byte1]: 36
1692 23:21:09.521682
1693 23:21:09.521788 Set Vref, RX VrefLevel [Byte0]: 37
1694 23:21:09.524928 [Byte1]: 37
1695 23:21:09.528897
1696 23:21:09.528999 Set Vref, RX VrefLevel [Byte0]: 38
1697 23:21:09.532302 [Byte1]: 38
1698 23:21:09.536624
1699 23:21:09.536729 Set Vref, RX VrefLevel [Byte0]: 39
1700 23:21:09.540179 [Byte1]: 39
1701 23:21:09.544650
1702 23:21:09.544753 Set Vref, RX VrefLevel [Byte0]: 40
1703 23:21:09.547642 [Byte1]: 40
1704 23:21:09.552294
1705 23:21:09.552398 Set Vref, RX VrefLevel [Byte0]: 41
1706 23:21:09.555183 [Byte1]: 41
1707 23:21:09.559581
1708 23:21:09.559696 Set Vref, RX VrefLevel [Byte0]: 42
1709 23:21:09.563438 [Byte1]: 42
1710 23:21:09.567157
1711 23:21:09.567286 Set Vref, RX VrefLevel [Byte0]: 43
1712 23:21:09.570321 [Byte1]: 43
1713 23:21:09.574620
1714 23:21:09.574734 Set Vref, RX VrefLevel [Byte0]: 44
1715 23:21:09.578002 [Byte1]: 44
1716 23:21:09.582250
1717 23:21:09.582370 Set Vref, RX VrefLevel [Byte0]: 45
1718 23:21:09.585967 [Byte1]: 45
1719 23:21:09.590001
1720 23:21:09.590111 Set Vref, RX VrefLevel [Byte0]: 46
1721 23:21:09.593240 [Byte1]: 46
1722 23:21:09.597481
1723 23:21:09.597595 Set Vref, RX VrefLevel [Byte0]: 47
1724 23:21:09.601155 [Byte1]: 47
1725 23:21:09.605638
1726 23:21:09.605750 Set Vref, RX VrefLevel [Byte0]: 48
1727 23:21:09.608953 [Byte1]: 48
1728 23:21:09.612787
1729 23:21:09.612891 Set Vref, RX VrefLevel [Byte0]: 49
1730 23:21:09.616128 [Byte1]: 49
1731 23:21:09.620162
1732 23:21:09.620272 Set Vref, RX VrefLevel [Byte0]: 50
1733 23:21:09.623835 [Byte1]: 50
1734 23:21:09.627846
1735 23:21:09.627956 Set Vref, RX VrefLevel [Byte0]: 51
1736 23:21:09.631623 [Byte1]: 51
1737 23:21:09.635884
1738 23:21:09.636002 Set Vref, RX VrefLevel [Byte0]: 52
1739 23:21:09.638649 [Byte1]: 52
1740 23:21:09.643230
1741 23:21:09.643350 Set Vref, RX VrefLevel [Byte0]: 53
1742 23:21:09.646259 [Byte1]: 53
1743 23:21:09.650929
1744 23:21:09.651082 Set Vref, RX VrefLevel [Byte0]: 54
1745 23:21:09.654140 [Byte1]: 54
1746 23:21:09.658924
1747 23:21:09.659040 Set Vref, RX VrefLevel [Byte0]: 55
1748 23:21:09.662551 [Byte1]: 55
1749 23:21:09.665744
1750 23:21:09.665853 Set Vref, RX VrefLevel [Byte0]: 56
1751 23:21:09.669348 [Byte1]: 56
1752 23:21:09.673610
1753 23:21:09.673727 Set Vref, RX VrefLevel [Byte0]: 57
1754 23:21:09.676778 [Byte1]: 57
1755 23:21:09.681259
1756 23:21:09.681377 Set Vref, RX VrefLevel [Byte0]: 58
1757 23:21:09.684612 [Byte1]: 58
1758 23:21:09.689441
1759 23:21:09.689558 Set Vref, RX VrefLevel [Byte0]: 59
1760 23:21:09.693422 [Byte1]: 59
1761 23:21:09.696582
1762 23:21:09.696690 Set Vref, RX VrefLevel [Byte0]: 60
1763 23:21:09.699858 [Byte1]: 60
1764 23:21:09.704143
1765 23:21:09.704278 Set Vref, RX VrefLevel [Byte0]: 61
1766 23:21:09.707895 [Byte1]: 61
1767 23:21:09.711356
1768 23:21:09.711474 Set Vref, RX VrefLevel [Byte0]: 62
1769 23:21:09.715013 [Byte1]: 62
1770 23:21:09.719528
1771 23:21:09.719641 Set Vref, RX VrefLevel [Byte0]: 63
1772 23:21:09.722698 [Byte1]: 63
1773 23:21:09.726882
1774 23:21:09.726998 Set Vref, RX VrefLevel [Byte0]: 64
1775 23:21:09.730237 [Byte1]: 64
1776 23:21:09.734812
1777 23:21:09.734929 Set Vref, RX VrefLevel [Byte0]: 65
1778 23:21:09.737625 [Byte1]: 65
1779 23:21:09.742265
1780 23:21:09.742381 Set Vref, RX VrefLevel [Byte0]: 66
1781 23:21:09.744857 [Byte1]: 66
1782 23:21:09.749501
1783 23:21:09.749631 Set Vref, RX VrefLevel [Byte0]: 67
1784 23:21:09.752744 [Byte1]: 67
1785 23:21:09.756902
1786 23:21:09.757030 Set Vref, RX VrefLevel [Byte0]: 68
1787 23:21:09.761169 [Byte1]: 68
1788 23:21:09.764544
1789 23:21:09.764679 Set Vref, RX VrefLevel [Byte0]: 69
1790 23:21:09.768428 [Byte1]: 69
1791 23:21:09.772263
1792 23:21:09.772381 Set Vref, RX VrefLevel [Byte0]: 70
1793 23:21:09.775725 [Byte1]: 70
1794 23:21:09.780077
1795 23:21:09.780171 Set Vref, RX VrefLevel [Byte0]: 71
1796 23:21:09.783044 [Byte1]: 71
1797 23:21:09.787257
1798 23:21:09.787360 Set Vref, RX VrefLevel [Byte0]: 72
1799 23:21:09.790898 [Byte1]: 72
1800 23:21:09.795244
1801 23:21:09.795347 Set Vref, RX VrefLevel [Byte0]: 73
1802 23:21:09.798536 [Byte1]: 73
1803 23:21:09.803602
1804 23:21:09.803716 Set Vref, RX VrefLevel [Byte0]: 74
1805 23:21:09.807359 [Byte1]: 74
1806 23:21:09.810935
1807 23:21:09.811042 Set Vref, RX VrefLevel [Byte0]: 75
1808 23:21:09.813432 [Byte1]: 75
1809 23:21:09.817933
1810 23:21:09.818034 Set Vref, RX VrefLevel [Byte0]: 76
1811 23:21:09.821482 [Byte1]: 76
1812 23:21:09.825649
1813 23:21:09.825744 Set Vref, RX VrefLevel [Byte0]: 77
1814 23:21:09.828918 [Byte1]: 77
1815 23:21:09.833026
1816 23:21:09.833153 Set Vref, RX VrefLevel [Byte0]: 78
1817 23:21:09.836474 [Byte1]: 78
1818 23:21:09.840575
1819 23:21:09.840703 Set Vref, RX VrefLevel [Byte0]: 79
1820 23:21:09.843982 [Byte1]: 79
1821 23:21:09.848138
1822 23:21:09.848264 Final RX Vref Byte 0 = 54 to rank0
1823 23:21:09.851789 Final RX Vref Byte 1 = 58 to rank0
1824 23:21:09.855063 Final RX Vref Byte 0 = 54 to rank1
1825 23:21:09.858814 Final RX Vref Byte 1 = 58 to rank1==
1826 23:21:09.862231 Dram Type= 6, Freq= 0, CH_1, rank 0
1827 23:21:09.865067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1828 23:21:09.868767 ==
1829 23:21:09.868939 DQS Delay:
1830 23:21:09.869045 DQS0 = 0, DQS1 = 0
1831 23:21:09.871554 DQM Delay:
1832 23:21:09.871677 DQM0 = 83, DQM1 = 74
1833 23:21:09.875195 DQ Delay:
1834 23:21:09.875341 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1835 23:21:09.878528 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =76
1836 23:21:09.881754 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1837 23:21:09.885237 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1838 23:21:09.885380
1839 23:21:09.888656
1840 23:21:09.895635 [DQSOSCAuto] RK0, (LSB)MR18= 0x26fb, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1841 23:21:09.898723 CH1 RK0: MR19=605, MR18=26FB
1842 23:21:09.905395 CH1_RK0: MR19=0x605, MR18=0x26FB, DQSOSC=400, MR23=63, INC=92, DEC=61
1843 23:21:09.905537
1844 23:21:09.909139 ----->DramcWriteLeveling(PI) begin...
1845 23:21:09.909249 ==
1846 23:21:09.911973 Dram Type= 6, Freq= 0, CH_1, rank 1
1847 23:21:09.915378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 23:21:09.915496 ==
1849 23:21:09.918717 Write leveling (Byte 0): 26 => 26
1850 23:21:09.922342 Write leveling (Byte 1): 28 => 28
1851 23:21:09.925797 DramcWriteLeveling(PI) end<-----
1852 23:21:09.925916
1853 23:21:09.925984 ==
1854 23:21:09.928655 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 23:21:09.932180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 23:21:09.932294 ==
1857 23:21:09.935915 [Gating] SW mode calibration
1858 23:21:09.942345 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1859 23:21:09.949256 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1860 23:21:09.952306 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1861 23:21:09.956505 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1862 23:21:09.958855 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1863 23:21:09.965379 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 23:21:09.968748 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 23:21:09.972290 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 23:21:09.978902 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 23:21:09.982615 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 23:21:09.985622 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 23:21:09.993379 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:21:09.995995 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:21:09.999589 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1872 23:21:10.006177 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1873 23:21:10.009741 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:21:10.012593 0 7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1875 23:21:10.016376 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 23:21:10.022465 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1877 23:21:10.026046 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1878 23:21:10.029593 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:21:10.035734 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:21:10.039655 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:21:10.043146 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:21:10.049467 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:21:10.053006 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:21:10.056768 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:21:10.062240 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1886 23:21:10.066120 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1887 23:21:10.069375 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 23:21:10.075981 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 23:21:10.079680 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 23:21:10.082487 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 23:21:10.089045 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 23:21:10.092595 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 23:21:10.096416 0 10 4 | B1->B0 | 3232 2727 | 0 0 | (0 0) (1 0)
1894 23:21:10.099238 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1895 23:21:10.106100 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:21:10.109207 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1897 23:21:10.112961 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 23:21:10.119640 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 23:21:10.122592 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 23:21:10.126671 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 23:21:10.133271 0 11 4 | B1->B0 | 2c2c 3a3a | 1 0 | (1 1) (1 1)
1902 23:21:10.136530 0 11 8 | B1->B0 | 4242 4444 | 0 0 | (0 0) (0 0)
1903 23:21:10.139787 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 23:21:10.146267 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 23:21:10.149403 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 23:21:10.153367 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 23:21:10.160159 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 23:21:10.163345 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 23:21:10.166838 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1910 23:21:10.169728 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 23:21:10.176476 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 23:21:10.179727 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 23:21:10.183156 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 23:21:10.189643 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 23:21:10.193832 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 23:21:10.196838 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 23:21:10.203498 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 23:21:10.206913 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 23:21:10.209973 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 23:21:10.216585 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 23:21:10.219891 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 23:21:10.224079 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:21:10.226587 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 23:21:10.233545 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 23:21:10.237436 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1926 23:21:10.240178 Total UI for P1: 0, mck2ui 16
1927 23:21:10.243530 best dqsien dly found for B0: ( 0, 14, 2)
1928 23:21:10.247267 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 23:21:10.250360 Total UI for P1: 0, mck2ui 16
1930 23:21:10.254158 best dqsien dly found for B1: ( 0, 14, 4)
1931 23:21:10.257063 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1932 23:21:10.260208 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1933 23:21:10.260296
1934 23:21:10.266952 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1935 23:21:10.270291 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1936 23:21:10.270411 [Gating] SW calibration Done
1937 23:21:10.273853 ==
1938 23:21:10.273941 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 23:21:10.281099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 23:21:10.281208 ==
1941 23:21:10.281306 RX Vref Scan: 0
1942 23:21:10.281367
1943 23:21:10.283766 RX Vref 0 -> 0, step: 1
1944 23:21:10.283850
1945 23:21:10.287560 RX Delay -130 -> 252, step: 16
1946 23:21:10.290734 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1947 23:21:10.293914 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1948 23:21:10.297242 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1949 23:21:10.304048 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1950 23:21:10.307282 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1951 23:21:10.310927 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1952 23:21:10.314080 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1953 23:21:10.317376 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1954 23:21:10.320444 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1955 23:21:10.327138 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1956 23:21:10.330700 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1957 23:21:10.334190 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1958 23:21:10.337683 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1959 23:21:10.344422 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1960 23:21:10.347250 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1961 23:21:10.351448 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1962 23:21:10.351583 ==
1963 23:21:10.354074 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 23:21:10.357648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 23:21:10.357767 ==
1966 23:21:10.361282 DQS Delay:
1967 23:21:10.361399 DQS0 = 0, DQS1 = 0
1968 23:21:10.361497 DQM Delay:
1969 23:21:10.364046 DQM0 = 80, DQM1 = 75
1970 23:21:10.364155 DQ Delay:
1971 23:21:10.367922 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1972 23:21:10.371577 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =69
1973 23:21:10.374376 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1974 23:21:10.377638 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1975 23:21:10.377752
1976 23:21:10.377847
1977 23:21:10.377939 ==
1978 23:21:10.381844 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 23:21:10.384574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 23:21:10.388050 ==
1981 23:21:10.388161
1982 23:21:10.388264
1983 23:21:10.388354 TX Vref Scan disable
1984 23:21:10.391239 == TX Byte 0 ==
1985 23:21:10.394981 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1986 23:21:10.397907 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1987 23:21:10.401174 == TX Byte 1 ==
1988 23:21:10.404962 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1989 23:21:10.407785 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1990 23:21:10.411536 ==
1991 23:21:10.411657 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 23:21:10.418339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 23:21:10.418496 ==
1994 23:21:10.430353 TX Vref=22, minBit 15, minWin=26, winSum=442
1995 23:21:10.433389 TX Vref=24, minBit 1, minWin=27, winSum=446
1996 23:21:10.436820 TX Vref=26, minBit 1, minWin=27, winSum=446
1997 23:21:10.439999 TX Vref=28, minBit 10, minWin=27, winSum=449
1998 23:21:10.443182 TX Vref=30, minBit 0, minWin=28, winSum=452
1999 23:21:10.446802 TX Vref=32, minBit 0, minWin=28, winSum=454
2000 23:21:10.453488 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
2001 23:21:10.453610
2002 23:21:10.457108 Final TX Range 1 Vref 32
2003 23:21:10.457202
2004 23:21:10.457282 ==
2005 23:21:10.460163 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 23:21:10.463697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 23:21:10.463815 ==
2008 23:21:10.463884
2009 23:21:10.467011
2010 23:21:10.467095 TX Vref Scan disable
2011 23:21:10.470360 == TX Byte 0 ==
2012 23:21:10.473963 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2013 23:21:10.477200 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2014 23:21:10.480614 == TX Byte 1 ==
2015 23:21:10.483860 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2016 23:21:10.487817 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2017 23:21:10.487917
2018 23:21:10.490391 [DATLAT]
2019 23:21:10.490513 Freq=800, CH1 RK1
2020 23:21:10.490578
2021 23:21:10.493699 DATLAT Default: 0xa
2022 23:21:10.493782 0, 0xFFFF, sum = 0
2023 23:21:10.497248 1, 0xFFFF, sum = 0
2024 23:21:10.497359 2, 0xFFFF, sum = 0
2025 23:21:10.500606 3, 0xFFFF, sum = 0
2026 23:21:10.500691 4, 0xFFFF, sum = 0
2027 23:21:10.503835 5, 0xFFFF, sum = 0
2028 23:21:10.503920 6, 0xFFFF, sum = 0
2029 23:21:10.507163 7, 0xFFFF, sum = 0
2030 23:21:10.507257 8, 0xFFFF, sum = 0
2031 23:21:10.510356 9, 0x0, sum = 1
2032 23:21:10.510488 10, 0x0, sum = 2
2033 23:21:10.514172 11, 0x0, sum = 3
2034 23:21:10.514265 12, 0x0, sum = 4
2035 23:21:10.517121 best_step = 10
2036 23:21:10.517207
2037 23:21:10.517271 ==
2038 23:21:10.521095 Dram Type= 6, Freq= 0, CH_1, rank 1
2039 23:21:10.523746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2040 23:21:10.523834 ==
2041 23:21:10.527346 RX Vref Scan: 0
2042 23:21:10.527434
2043 23:21:10.527500 RX Vref 0 -> 0, step: 1
2044 23:21:10.527592
2045 23:21:10.531204 RX Delay -111 -> 252, step: 8
2046 23:21:10.537147 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2047 23:21:10.540761 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2048 23:21:10.543640 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2049 23:21:10.547248 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2050 23:21:10.550388 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2051 23:21:10.554467 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2052 23:21:10.560444 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2053 23:21:10.563897 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2054 23:21:10.567411 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2055 23:21:10.570706 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2056 23:21:10.573829 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2057 23:21:10.580847 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2058 23:21:10.584059 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2059 23:21:10.587354 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2060 23:21:10.590917 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2061 23:21:10.597640 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2062 23:21:10.597797 ==
2063 23:21:10.600613 Dram Type= 6, Freq= 0, CH_1, rank 1
2064 23:21:10.603926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2065 23:21:10.604054 ==
2066 23:21:10.604160 DQS Delay:
2067 23:21:10.608242 DQS0 = 0, DQS1 = 0
2068 23:21:10.608369 DQM Delay:
2069 23:21:10.610896 DQM0 = 80, DQM1 = 75
2070 23:21:10.611010 DQ Delay:
2071 23:21:10.614227 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2072 23:21:10.617524 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2073 23:21:10.620974 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2074 23:21:10.624832 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2075 23:21:10.624971
2076 23:21:10.625071
2077 23:21:10.631125 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2078 23:21:10.634292 CH1 RK1: MR19=606, MR18=1D28
2079 23:21:10.641020 CH1_RK1: MR19=0x606, MR18=0x1D28, DQSOSC=399, MR23=63, INC=92, DEC=61
2080 23:21:10.644452 [RxdqsGatingPostProcess] freq 800
2081 23:21:10.647437 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2082 23:21:10.650814 Pre-setting of DQS Precalculation
2083 23:21:10.657897 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2084 23:21:10.664564 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2085 23:21:10.671047 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2086 23:21:10.671217
2087 23:21:10.671320
2088 23:21:10.674917 [Calibration Summary] 1600 Mbps
2089 23:21:10.675046 CH 0, Rank 0
2090 23:21:10.678228 SW Impedance : PASS
2091 23:21:10.681461 DUTY Scan : NO K
2092 23:21:10.681596 ZQ Calibration : PASS
2093 23:21:10.684399 Jitter Meter : NO K
2094 23:21:10.687952 CBT Training : PASS
2095 23:21:10.688081 Write leveling : PASS
2096 23:21:10.691302 RX DQS gating : PASS
2097 23:21:10.694812 RX DQ/DQS(RDDQC) : PASS
2098 23:21:10.694945 TX DQ/DQS : PASS
2099 23:21:10.698337 RX DATLAT : PASS
2100 23:21:10.698497 RX DQ/DQS(Engine): PASS
2101 23:21:10.701643 TX OE : NO K
2102 23:21:10.701758 All Pass.
2103 23:21:10.701852
2104 23:21:10.704693 CH 0, Rank 1
2105 23:21:10.704809 SW Impedance : PASS
2106 23:21:10.708124 DUTY Scan : NO K
2107 23:21:10.712029 ZQ Calibration : PASS
2108 23:21:10.712163 Jitter Meter : NO K
2109 23:21:10.714684 CBT Training : PASS
2110 23:21:10.718337 Write leveling : PASS
2111 23:21:10.718507 RX DQS gating : PASS
2112 23:21:10.721711 RX DQ/DQS(RDDQC) : PASS
2113 23:21:10.725807 TX DQ/DQS : PASS
2114 23:21:10.725942 RX DATLAT : PASS
2115 23:21:10.728447 RX DQ/DQS(Engine): PASS
2116 23:21:10.728561 TX OE : NO K
2117 23:21:10.732073 All Pass.
2118 23:21:10.732201
2119 23:21:10.732307 CH 1, Rank 0
2120 23:21:10.735122 SW Impedance : PASS
2121 23:21:10.735233 DUTY Scan : NO K
2122 23:21:10.738127 ZQ Calibration : PASS
2123 23:21:10.741736 Jitter Meter : NO K
2124 23:21:10.741861 CBT Training : PASS
2125 23:21:10.745110 Write leveling : PASS
2126 23:21:10.748762 RX DQS gating : PASS
2127 23:21:10.748893 RX DQ/DQS(RDDQC) : PASS
2128 23:21:10.752238 TX DQ/DQS : PASS
2129 23:21:10.755312 RX DATLAT : PASS
2130 23:21:10.755438 RX DQ/DQS(Engine): PASS
2131 23:21:10.758322 TX OE : NO K
2132 23:21:10.758478 All Pass.
2133 23:21:10.758573
2134 23:21:10.762105 CH 1, Rank 1
2135 23:21:10.762231 SW Impedance : PASS
2136 23:21:10.765131 DUTY Scan : NO K
2137 23:21:10.765247 ZQ Calibration : PASS
2138 23:21:10.769236 Jitter Meter : NO K
2139 23:21:10.771731 CBT Training : PASS
2140 23:21:10.771863 Write leveling : PASS
2141 23:21:10.775120 RX DQS gating : PASS
2142 23:21:10.779105 RX DQ/DQS(RDDQC) : PASS
2143 23:21:10.779240 TX DQ/DQS : PASS
2144 23:21:10.782592 RX DATLAT : PASS
2145 23:21:10.785242 RX DQ/DQS(Engine): PASS
2146 23:21:10.785361 TX OE : NO K
2147 23:21:10.785467 All Pass.
2148 23:21:10.789360
2149 23:21:10.789480 DramC Write-DBI off
2150 23:21:10.792430 PER_BANK_REFRESH: Hybrid Mode
2151 23:21:10.792545 TX_TRACKING: ON
2152 23:21:10.795537 [GetDramInforAfterCalByMRR] Vendor 6.
2153 23:21:10.799059 [GetDramInforAfterCalByMRR] Revision 606.
2154 23:21:10.805376 [GetDramInforAfterCalByMRR] Revision 2 0.
2155 23:21:10.805508 MR0 0x3b3b
2156 23:21:10.805608 MR8 0x5151
2157 23:21:10.808726 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2158 23:21:10.808839
2159 23:21:10.812381 MR0 0x3b3b
2160 23:21:10.812492 MR8 0x5151
2161 23:21:10.815486 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2162 23:21:10.815595
2163 23:21:10.826049 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2164 23:21:10.829046 [FAST_K] Save calibration result to emmc
2165 23:21:10.832471 [FAST_K] Save calibration result to emmc
2166 23:21:10.835575 dram_init: config_dvfs: 1
2167 23:21:10.839437 dramc_set_vcore_voltage set vcore to 662500
2168 23:21:10.839565 Read voltage for 1200, 2
2169 23:21:10.843025 Vio18 = 0
2170 23:21:10.843135 Vcore = 662500
2171 23:21:10.843229 Vdram = 0
2172 23:21:10.845557 Vddq = 0
2173 23:21:10.845663 Vmddr = 0
2174 23:21:10.849043 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2175 23:21:10.856236 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2176 23:21:10.859268 MEM_TYPE=3, freq_sel=15
2177 23:21:10.859385 sv_algorithm_assistance_LP4_1600
2178 23:21:10.866640 ============ PULL DRAM RESETB DOWN ============
2179 23:21:10.869936 ========== PULL DRAM RESETB DOWN end =========
2180 23:21:10.872904 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2181 23:21:10.876380 ===================================
2182 23:21:10.879468 LPDDR4 DRAM CONFIGURATION
2183 23:21:10.882924 ===================================
2184 23:21:10.886200 EX_ROW_EN[0] = 0x0
2185 23:21:10.886318 EX_ROW_EN[1] = 0x0
2186 23:21:10.889615 LP4Y_EN = 0x0
2187 23:21:10.889722 WORK_FSP = 0x0
2188 23:21:10.894012 WL = 0x4
2189 23:21:10.894129 RL = 0x4
2190 23:21:10.896005 BL = 0x2
2191 23:21:10.896132 RPST = 0x0
2192 23:21:10.899937 RD_PRE = 0x0
2193 23:21:10.900074 WR_PRE = 0x1
2194 23:21:10.902714 WR_PST = 0x0
2195 23:21:10.902826 DBI_WR = 0x0
2196 23:21:10.906165 DBI_RD = 0x0
2197 23:21:10.906280 OTF = 0x1
2198 23:21:10.909794 ===================================
2199 23:21:10.912969 ===================================
2200 23:21:10.916707 ANA top config
2201 23:21:10.920059 ===================================
2202 23:21:10.920171 DLL_ASYNC_EN = 0
2203 23:21:10.922977 ALL_SLAVE_EN = 0
2204 23:21:10.926618 NEW_RANK_MODE = 1
2205 23:21:10.930061 DLL_IDLE_MODE = 1
2206 23:21:10.933950 LP45_APHY_COMB_EN = 1
2207 23:21:10.934046 TX_ODT_DIS = 1
2208 23:21:10.936489 NEW_8X_MODE = 1
2209 23:21:10.940129 ===================================
2210 23:21:10.943077 ===================================
2211 23:21:10.946374 data_rate = 2400
2212 23:21:10.949716 CKR = 1
2213 23:21:10.953028 DQ_P2S_RATIO = 8
2214 23:21:10.956738 ===================================
2215 23:21:10.956847 CA_P2S_RATIO = 8
2216 23:21:10.960049 DQ_CA_OPEN = 0
2217 23:21:10.963270 DQ_SEMI_OPEN = 0
2218 23:21:10.966670 CA_SEMI_OPEN = 0
2219 23:21:10.970067 CA_FULL_RATE = 0
2220 23:21:10.973310 DQ_CKDIV4_EN = 0
2221 23:21:10.973389 CA_CKDIV4_EN = 0
2222 23:21:10.976688 CA_PREDIV_EN = 0
2223 23:21:10.980490 PH8_DLY = 17
2224 23:21:10.983799 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2225 23:21:10.986596 DQ_AAMCK_DIV = 4
2226 23:21:10.989822 CA_AAMCK_DIV = 4
2227 23:21:10.989907 CA_ADMCK_DIV = 4
2228 23:21:10.993323 DQ_TRACK_CA_EN = 0
2229 23:21:10.996581 CA_PICK = 1200
2230 23:21:11.000201 CA_MCKIO = 1200
2231 23:21:11.003968 MCKIO_SEMI = 0
2232 23:21:11.006815 PLL_FREQ = 2366
2233 23:21:11.010544 DQ_UI_PI_RATIO = 32
2234 23:21:11.010619 CA_UI_PI_RATIO = 0
2235 23:21:11.013927 ===================================
2236 23:21:11.016997 ===================================
2237 23:21:11.020617 memory_type:LPDDR4
2238 23:21:11.023644 GP_NUM : 10
2239 23:21:11.023724 SRAM_EN : 1
2240 23:21:11.026942 MD32_EN : 0
2241 23:21:11.030781 ===================================
2242 23:21:11.033662 [ANA_INIT] >>>>>>>>>>>>>>
2243 23:21:11.033746 <<<<<< [CONFIGURE PHASE]: ANA_TX
2244 23:21:11.037065 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2245 23:21:11.040361 ===================================
2246 23:21:11.044357 data_rate = 2400,PCW = 0X5b00
2247 23:21:11.047461 ===================================
2248 23:21:11.050812 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2249 23:21:11.057773 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2250 23:21:11.060490 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2251 23:21:11.067182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2252 23:21:11.070793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2253 23:21:11.073885 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2254 23:21:11.077098 [ANA_INIT] flow start
2255 23:21:11.077185 [ANA_INIT] PLL >>>>>>>>
2256 23:21:11.080698 [ANA_INIT] PLL <<<<<<<<
2257 23:21:11.084459 [ANA_INIT] MIDPI >>>>>>>>
2258 23:21:11.084549 [ANA_INIT] MIDPI <<<<<<<<
2259 23:21:11.087521 [ANA_INIT] DLL >>>>>>>>
2260 23:21:11.090872 [ANA_INIT] DLL <<<<<<<<
2261 23:21:11.090984 [ANA_INIT] flow end
2262 23:21:11.094086 ============ LP4 DIFF to SE enter ============
2263 23:21:11.100869 ============ LP4 DIFF to SE exit ============
2264 23:21:11.100976 [ANA_INIT] <<<<<<<<<<<<<
2265 23:21:11.104042 [Flow] Enable top DCM control >>>>>
2266 23:21:11.107455 [Flow] Enable top DCM control <<<<<
2267 23:21:11.110763 Enable DLL master slave shuffle
2268 23:21:11.117658 ==============================================================
2269 23:21:11.117760 Gating Mode config
2270 23:21:11.124428 ==============================================================
2271 23:21:11.127502 Config description:
2272 23:21:11.134085 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2273 23:21:11.141381 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2274 23:21:11.148160 SELPH_MODE 0: By rank 1: By Phase
2275 23:21:11.154311 ==============================================================
2276 23:21:11.154523 GAT_TRACK_EN = 1
2277 23:21:11.157735 RX_GATING_MODE = 2
2278 23:21:11.161286 RX_GATING_TRACK_MODE = 2
2279 23:21:11.164366 SELPH_MODE = 1
2280 23:21:11.168338 PICG_EARLY_EN = 1
2281 23:21:11.170949 VALID_LAT_VALUE = 1
2282 23:21:11.177866 ==============================================================
2283 23:21:11.181206 Enter into Gating configuration >>>>
2284 23:21:11.184364 Exit from Gating configuration <<<<
2285 23:21:11.187736 Enter into DVFS_PRE_config >>>>>
2286 23:21:11.197669 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2287 23:21:11.201511 Exit from DVFS_PRE_config <<<<<
2288 23:21:11.204592 Enter into PICG configuration >>>>
2289 23:21:11.207673 Exit from PICG configuration <<<<
2290 23:21:11.207760 [RX_INPUT] configuration >>>>>
2291 23:21:11.211361 [RX_INPUT] configuration <<<<<
2292 23:21:11.217780 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2293 23:21:11.221253 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2294 23:21:11.228419 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2295 23:21:11.234644 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2296 23:21:11.241602 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2297 23:21:11.248250 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2298 23:21:11.251832 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2299 23:21:11.255229 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2300 23:21:11.258973 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2301 23:21:11.265171 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2302 23:21:11.268592 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2303 23:21:11.272094 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2304 23:21:11.275448 ===================================
2305 23:21:11.278338 LPDDR4 DRAM CONFIGURATION
2306 23:21:11.281746 ===================================
2307 23:21:11.281832 EX_ROW_EN[0] = 0x0
2308 23:21:11.285134 EX_ROW_EN[1] = 0x0
2309 23:21:11.288963 LP4Y_EN = 0x0
2310 23:21:11.289043 WORK_FSP = 0x0
2311 23:21:11.292301 WL = 0x4
2312 23:21:11.292380 RL = 0x4
2313 23:21:11.295540 BL = 0x2
2314 23:21:11.295616 RPST = 0x0
2315 23:21:11.298652 RD_PRE = 0x0
2316 23:21:11.298754 WR_PRE = 0x1
2317 23:21:11.301871 WR_PST = 0x0
2318 23:21:11.301946 DBI_WR = 0x0
2319 23:21:11.305620 DBI_RD = 0x0
2320 23:21:11.305695 OTF = 0x1
2321 23:21:11.308574 ===================================
2322 23:21:11.311821 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2323 23:21:11.318589 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2324 23:21:11.322248 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2325 23:21:11.325769 ===================================
2326 23:21:11.328441 LPDDR4 DRAM CONFIGURATION
2327 23:21:11.332350 ===================================
2328 23:21:11.332456 EX_ROW_EN[0] = 0x10
2329 23:21:11.335174 EX_ROW_EN[1] = 0x0
2330 23:21:11.335284 LP4Y_EN = 0x0
2331 23:21:11.338457 WORK_FSP = 0x0
2332 23:21:11.338568 WL = 0x4
2333 23:21:11.341871 RL = 0x4
2334 23:21:11.341965 BL = 0x2
2335 23:21:11.345407 RPST = 0x0
2336 23:21:11.345518 RD_PRE = 0x0
2337 23:21:11.349193 WR_PRE = 0x1
2338 23:21:11.349305 WR_PST = 0x0
2339 23:21:11.351930 DBI_WR = 0x0
2340 23:21:11.355452 DBI_RD = 0x0
2341 23:21:11.355534 OTF = 0x1
2342 23:21:11.358670 ===================================
2343 23:21:11.366386 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2344 23:21:11.366541 ==
2345 23:21:11.369402 Dram Type= 6, Freq= 0, CH_0, rank 0
2346 23:21:11.372016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2347 23:21:11.372094 ==
2348 23:21:11.375926 [Duty_Offset_Calibration]
2349 23:21:11.376001 B0:2 B1:-1 CA:1
2350 23:21:11.376063
2351 23:21:11.378849 [DutyScan_Calibration_Flow] k_type=0
2352 23:21:11.389172
2353 23:21:11.389277 ==CLK 0==
2354 23:21:11.392095 Final CLK duty delay cell = -4
2355 23:21:11.395541 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2356 23:21:11.398967 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2357 23:21:11.401984 [-4] AVG Duty = 4953%(X100)
2358 23:21:11.402062
2359 23:21:11.405563 CH0 CLK Duty spec in!! Max-Min= 156%
2360 23:21:11.409011 [DutyScan_Calibration_Flow] ====Done====
2361 23:21:11.409091
2362 23:21:11.412717 [DutyScan_Calibration_Flow] k_type=1
2363 23:21:11.427564
2364 23:21:11.427693 ==DQS 0 ==
2365 23:21:11.431386 Final DQS duty delay cell = 0
2366 23:21:11.434155 [0] MAX Duty = 5156%(X100), DQS PI = 46
2367 23:21:11.437754 [0] MIN Duty = 5000%(X100), DQS PI = 14
2368 23:21:11.437846 [0] AVG Duty = 5078%(X100)
2369 23:21:11.441009
2370 23:21:11.441092 ==DQS 1 ==
2371 23:21:11.444633 Final DQS duty delay cell = -4
2372 23:21:11.447595 [-4] MAX Duty = 5124%(X100), DQS PI = 16
2373 23:21:11.451056 [-4] MIN Duty = 5000%(X100), DQS PI = 42
2374 23:21:11.454184 [-4] AVG Duty = 5062%(X100)
2375 23:21:11.454303
2376 23:21:11.457753 CH0 DQS 0 Duty spec in!! Max-Min= 156%
2377 23:21:11.457841
2378 23:21:11.461246 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2379 23:21:11.465078 [DutyScan_Calibration_Flow] ====Done====
2380 23:21:11.465190
2381 23:21:11.467632 [DutyScan_Calibration_Flow] k_type=3
2382 23:21:11.484502
2383 23:21:11.484638 ==DQM 0 ==
2384 23:21:11.487866 Final DQM duty delay cell = 0
2385 23:21:11.491855 [0] MAX Duty = 5031%(X100), DQS PI = 54
2386 23:21:11.494311 [0] MIN Duty = 4907%(X100), DQS PI = 2
2387 23:21:11.494445 [0] AVG Duty = 4969%(X100)
2388 23:21:11.498232
2389 23:21:11.498341 ==DQM 1 ==
2390 23:21:11.501162 Final DQM duty delay cell = 0
2391 23:21:11.505118 [0] MAX Duty = 5124%(X100), DQS PI = 62
2392 23:21:11.508208 [0] MIN Duty = 4969%(X100), DQS PI = 10
2393 23:21:11.508294 [0] AVG Duty = 5046%(X100)
2394 23:21:11.511276
2395 23:21:11.514977 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2396 23:21:11.515062
2397 23:21:11.517914 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2398 23:21:11.521224 [DutyScan_Calibration_Flow] ====Done====
2399 23:21:11.521309
2400 23:21:11.524681 [DutyScan_Calibration_Flow] k_type=2
2401 23:21:11.540827
2402 23:21:11.540973 ==DQ 0 ==
2403 23:21:11.543342 Final DQ duty delay cell = -4
2404 23:21:11.546735 [-4] MAX Duty = 5031%(X100), DQS PI = 38
2405 23:21:11.550273 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2406 23:21:11.553506 [-4] AVG Duty = 4953%(X100)
2407 23:21:11.553632
2408 23:21:11.553724 ==DQ 1 ==
2409 23:21:11.557008 Final DQ duty delay cell = 0
2410 23:21:11.560198 [0] MAX Duty = 5031%(X100), DQS PI = 18
2411 23:21:11.563995 [0] MIN Duty = 4907%(X100), DQS PI = 46
2412 23:21:11.564087 [0] AVG Duty = 4969%(X100)
2413 23:21:11.567035
2414 23:21:11.570471 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2415 23:21:11.570563
2416 23:21:11.574539 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2417 23:21:11.577704 [DutyScan_Calibration_Flow] ====Done====
2418 23:21:11.577794 ==
2419 23:21:11.580763 Dram Type= 6, Freq= 0, CH_1, rank 0
2420 23:21:11.584319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2421 23:21:11.584412 ==
2422 23:21:11.587271 [Duty_Offset_Calibration]
2423 23:21:11.587354 B0:1 B1:1 CA:2
2424 23:21:11.587418
2425 23:21:11.590986 [DutyScan_Calibration_Flow] k_type=0
2426 23:21:11.600759
2427 23:21:11.600874 ==CLK 0==
2428 23:21:11.603854 Final CLK duty delay cell = 0
2429 23:21:11.607561 [0] MAX Duty = 5156%(X100), DQS PI = 24
2430 23:21:11.611036 [0] MIN Duty = 4938%(X100), DQS PI = 42
2431 23:21:11.611124 [0] AVG Duty = 5047%(X100)
2432 23:21:11.611188
2433 23:21:11.614182 CH1 CLK Duty spec in!! Max-Min= 218%
2434 23:21:11.620929 [DutyScan_Calibration_Flow] ====Done====
2435 23:21:11.621026
2436 23:21:11.624755 [DutyScan_Calibration_Flow] k_type=1
2437 23:21:11.639918
2438 23:21:11.640048 ==DQS 0 ==
2439 23:21:11.643186 Final DQS duty delay cell = 0
2440 23:21:11.646351 [0] MAX Duty = 5031%(X100), DQS PI = 18
2441 23:21:11.650191 [0] MIN Duty = 4813%(X100), DQS PI = 50
2442 23:21:11.650283 [0] AVG Duty = 4922%(X100)
2443 23:21:11.653083
2444 23:21:11.653171 ==DQS 1 ==
2445 23:21:11.656974 Final DQS duty delay cell = 0
2446 23:21:11.660039 [0] MAX Duty = 5062%(X100), DQS PI = 36
2447 23:21:11.663576 [0] MIN Duty = 4907%(X100), DQS PI = 8
2448 23:21:11.663691 [0] AVG Duty = 4984%(X100)
2449 23:21:11.666593
2450 23:21:11.670168 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2451 23:21:11.670258
2452 23:21:11.673696 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2453 23:21:11.676838 [DutyScan_Calibration_Flow] ====Done====
2454 23:21:11.676925
2455 23:21:11.679927 [DutyScan_Calibration_Flow] k_type=3
2456 23:21:11.696422
2457 23:21:11.696560 ==DQM 0 ==
2458 23:21:11.699669 Final DQM duty delay cell = 0
2459 23:21:11.703188 [0] MAX Duty = 5093%(X100), DQS PI = 18
2460 23:21:11.706461 [0] MIN Duty = 4876%(X100), DQS PI = 50
2461 23:21:11.706548 [0] AVG Duty = 4984%(X100)
2462 23:21:11.709849
2463 23:21:11.709945 ==DQM 1 ==
2464 23:21:11.713098 Final DQM duty delay cell = 0
2465 23:21:11.716854 [0] MAX Duty = 5156%(X100), DQS PI = 62
2466 23:21:11.719976 [0] MIN Duty = 4938%(X100), DQS PI = 22
2467 23:21:11.720062 [0] AVG Duty = 5047%(X100)
2468 23:21:11.720126
2469 23:21:11.723668 CH1 DQM 0 Duty spec in!! Max-Min= 217%
2470 23:21:11.726714
2471 23:21:11.730257 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2472 23:21:11.734189 [DutyScan_Calibration_Flow] ====Done====
2473 23:21:11.734277
2474 23:21:11.736881 [DutyScan_Calibration_Flow] k_type=2
2475 23:21:11.753083
2476 23:21:11.753222 ==DQ 0 ==
2477 23:21:11.756374 Final DQ duty delay cell = 0
2478 23:21:11.759696 [0] MAX Duty = 5156%(X100), DQS PI = 18
2479 23:21:11.762978 [0] MIN Duty = 4938%(X100), DQS PI = 60
2480 23:21:11.763067 [0] AVG Duty = 5047%(X100)
2481 23:21:11.763132
2482 23:21:11.766590 ==DQ 1 ==
2483 23:21:11.769501 Final DQ duty delay cell = 0
2484 23:21:11.772973 [0] MAX Duty = 5093%(X100), DQS PI = 10
2485 23:21:11.777367 [0] MIN Duty = 5000%(X100), DQS PI = 50
2486 23:21:11.777461 [0] AVG Duty = 5046%(X100)
2487 23:21:11.777526
2488 23:21:11.780056 CH1 DQ 0 Duty spec in!! Max-Min= 218%
2489 23:21:11.780141
2490 23:21:11.783563 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2491 23:21:11.786812 [DutyScan_Calibration_Flow] ====Done====
2492 23:21:11.791773 nWR fixed to 30
2493 23:21:11.796677 [ModeRegInit_LP4] CH0 RK0
2494 23:21:11.796802 [ModeRegInit_LP4] CH0 RK1
2495 23:21:11.799041 [ModeRegInit_LP4] CH1 RK0
2496 23:21:11.801954 [ModeRegInit_LP4] CH1 RK1
2497 23:21:11.802071 match AC timing 7
2498 23:21:11.808959 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2499 23:21:11.812382 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2500 23:21:11.815514 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2501 23:21:11.822888 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2502 23:21:11.825908 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2503 23:21:11.826030 ==
2504 23:21:11.828860 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 23:21:11.832024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 23:21:11.832134 ==
2507 23:21:11.838895 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2508 23:21:11.845274 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2509 23:21:11.852671 [CA 0] Center 40 (10~71) winsize 62
2510 23:21:11.856389 [CA 1] Center 39 (9~70) winsize 62
2511 23:21:11.859806 [CA 2] Center 36 (6~67) winsize 62
2512 23:21:11.863414 [CA 3] Center 36 (5~67) winsize 63
2513 23:21:11.866153 [CA 4] Center 35 (5~65) winsize 61
2514 23:21:11.869789 [CA 5] Center 34 (4~64) winsize 61
2515 23:21:11.869916
2516 23:21:11.872889 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2517 23:21:11.873014
2518 23:21:11.876504 [CATrainingPosCal] consider 1 rank data
2519 23:21:11.879861 u2DelayCellTimex100 = 270/100 ps
2520 23:21:11.883395 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2521 23:21:11.886628 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2522 23:21:11.893497 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2523 23:21:11.896519 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2524 23:21:11.900071 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2525 23:21:11.903290 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2526 23:21:11.903396
2527 23:21:11.907293 CA PerBit enable=1, Macro0, CA PI delay=34
2528 23:21:11.907389
2529 23:21:11.910308 [CBTSetCACLKResult] CA Dly = 34
2530 23:21:11.910464 CS Dly: 7 (0~38)
2531 23:21:11.910551 ==
2532 23:21:11.913296 Dram Type= 6, Freq= 0, CH_0, rank 1
2533 23:21:11.920384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 23:21:11.920525 ==
2535 23:21:11.923577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2536 23:21:11.930691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2537 23:21:11.938948 [CA 0] Center 39 (9~70) winsize 62
2538 23:21:11.942988 [CA 1] Center 40 (10~70) winsize 61
2539 23:21:11.945411 [CA 2] Center 36 (6~67) winsize 62
2540 23:21:11.948775 [CA 3] Center 35 (5~66) winsize 62
2541 23:21:11.952638 [CA 4] Center 34 (4~65) winsize 62
2542 23:21:11.955487 [CA 5] Center 34 (4~64) winsize 61
2543 23:21:11.955594
2544 23:21:11.958807 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2545 23:21:11.958896
2546 23:21:11.962024 [CATrainingPosCal] consider 2 rank data
2547 23:21:11.965722 u2DelayCellTimex100 = 270/100 ps
2548 23:21:11.969297 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2549 23:21:11.973066 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2550 23:21:11.978821 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2551 23:21:11.982255 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2552 23:21:11.985650 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2553 23:21:11.988986 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2554 23:21:11.989077
2555 23:21:11.992555 CA PerBit enable=1, Macro0, CA PI delay=34
2556 23:21:11.992640
2557 23:21:11.995836 [CBTSetCACLKResult] CA Dly = 34
2558 23:21:11.995927 CS Dly: 8 (0~41)
2559 23:21:11.996017
2560 23:21:11.998984 ----->DramcWriteLeveling(PI) begin...
2561 23:21:12.002539 ==
2562 23:21:12.002635 Dram Type= 6, Freq= 0, CH_0, rank 0
2563 23:21:12.009249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2564 23:21:12.009343 ==
2565 23:21:12.012706 Write leveling (Byte 0): 29 => 29
2566 23:21:12.015870 Write leveling (Byte 1): 29 => 29
2567 23:21:12.016045 DramcWriteLeveling(PI) end<-----
2568 23:21:12.019058
2569 23:21:12.019146 ==
2570 23:21:12.022728 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 23:21:12.026632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 23:21:12.026725 ==
2573 23:21:12.029351 [Gating] SW mode calibration
2574 23:21:12.036822 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2575 23:21:12.039438 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2576 23:21:12.046250 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2577 23:21:12.049151 0 15 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2578 23:21:12.053280 0 15 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2579 23:21:12.059767 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 23:21:12.063162 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 23:21:12.066263 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 23:21:12.072808 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 23:21:12.076567 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 23:21:12.079735 1 0 0 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
2585 23:21:12.082915 1 0 4 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2586 23:21:12.089924 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 23:21:12.093073 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 23:21:12.096085 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 23:21:12.103201 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 23:21:12.106766 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 23:21:12.109881 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 23:21:12.117117 1 1 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2593 23:21:12.119941 1 1 4 | B1->B0 | 3535 4242 | 0 0 | (0 0) (0 0)
2594 23:21:12.122895 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 23:21:12.130041 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 23:21:12.133023 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 23:21:12.137187 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 23:21:12.143124 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 23:21:12.146881 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 23:21:12.149985 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2601 23:21:12.153295 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2602 23:21:12.160369 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 23:21:12.163437 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 23:21:12.166966 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 23:21:12.174024 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 23:21:12.176929 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 23:21:12.180516 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 23:21:12.187012 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 23:21:12.190349 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 23:21:12.194517 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 23:21:12.200094 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 23:21:12.204151 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 23:21:12.207195 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 23:21:12.210081 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 23:21:12.216787 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 23:21:12.220761 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2617 23:21:12.224179 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2618 23:21:12.230908 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 23:21:12.233930 Total UI for P1: 0, mck2ui 16
2620 23:21:12.236915 best dqsien dly found for B0: ( 1, 4, 2)
2621 23:21:12.237002 Total UI for P1: 0, mck2ui 16
2622 23:21:12.244138 best dqsien dly found for B1: ( 1, 4, 2)
2623 23:21:12.247270 best DQS0 dly(MCK, UI, PI) = (1, 4, 2)
2624 23:21:12.250857 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2625 23:21:12.250950
2626 23:21:12.253854 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 2)
2627 23:21:12.257527 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2628 23:21:12.260691 [Gating] SW calibration Done
2629 23:21:12.260782 ==
2630 23:21:12.264280 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 23:21:12.267315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 23:21:12.267431 ==
2633 23:21:12.267522 RX Vref Scan: 0
2634 23:21:12.270478
2635 23:21:12.270561 RX Vref 0 -> 0, step: 1
2636 23:21:12.270645
2637 23:21:12.274270 RX Delay -40 -> 252, step: 8
2638 23:21:12.277476 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2639 23:21:12.280925 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2640 23:21:12.287692 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2641 23:21:12.291038 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2642 23:21:12.294088 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2643 23:21:12.297434 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2644 23:21:12.300961 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2645 23:21:12.307634 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2646 23:21:12.310985 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2647 23:21:12.314557 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2648 23:21:12.317703 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2649 23:21:12.321169 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2650 23:21:12.324466 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2651 23:21:12.331352 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2652 23:21:12.334440 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2653 23:21:12.338270 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2654 23:21:12.338386 ==
2655 23:21:12.341037 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 23:21:12.344599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 23:21:12.344682 ==
2658 23:21:12.348072 DQS Delay:
2659 23:21:12.348150 DQS0 = 0, DQS1 = 0
2660 23:21:12.351059 DQM Delay:
2661 23:21:12.351146 DQM0 = 115, DQM1 = 107
2662 23:21:12.354562 DQ Delay:
2663 23:21:12.357616 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2664 23:21:12.361571 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2665 23:21:12.364403 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2666 23:21:12.367666 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2667 23:21:12.367759
2668 23:21:12.367862
2669 23:21:12.367962 ==
2670 23:21:12.371400 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 23:21:12.374866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 23:21:12.374961 ==
2673 23:21:12.375065
2674 23:21:12.375166
2675 23:21:12.378351 TX Vref Scan disable
2676 23:21:12.381767 == TX Byte 0 ==
2677 23:21:12.384652 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2678 23:21:12.387999 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2679 23:21:12.388122 == TX Byte 1 ==
2680 23:21:12.394812 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2681 23:21:12.398645 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2682 23:21:12.398746 ==
2683 23:21:12.401848 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 23:21:12.404925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 23:21:12.405015 ==
2686 23:21:12.418318 TX Vref=22, minBit 1, minWin=25, winSum=417
2687 23:21:12.420871 TX Vref=24, minBit 5, minWin=25, winSum=426
2688 23:21:12.424984 TX Vref=26, minBit 0, minWin=26, winSum=426
2689 23:21:12.427426 TX Vref=28, minBit 0, minWin=26, winSum=433
2690 23:21:12.431188 TX Vref=30, minBit 7, minWin=26, winSum=438
2691 23:21:12.434313 TX Vref=32, minBit 0, minWin=26, winSum=434
2692 23:21:12.440853 [TxChooseVref] Worse bit 7, Min win 26, Win sum 438, Final Vref 30
2693 23:21:12.440992
2694 23:21:12.445192 Final TX Range 1 Vref 30
2695 23:21:12.445291
2696 23:21:12.445379 ==
2697 23:21:12.447701 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 23:21:12.451603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 23:21:12.451694 ==
2700 23:21:12.451798
2701 23:21:12.451900
2702 23:21:12.454373 TX Vref Scan disable
2703 23:21:12.458106 == TX Byte 0 ==
2704 23:21:12.461410 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2705 23:21:12.465180 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2706 23:21:12.468283 == TX Byte 1 ==
2707 23:21:12.471531 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2708 23:21:12.475271 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2709 23:21:12.475365
2710 23:21:12.478220 [DATLAT]
2711 23:21:12.478332 Freq=1200, CH0 RK0
2712 23:21:12.478470
2713 23:21:12.481725 DATLAT Default: 0xd
2714 23:21:12.481813 0, 0xFFFF, sum = 0
2715 23:21:12.484554 1, 0xFFFF, sum = 0
2716 23:21:12.484647 2, 0xFFFF, sum = 0
2717 23:21:12.488124 3, 0xFFFF, sum = 0
2718 23:21:12.488215 4, 0xFFFF, sum = 0
2719 23:21:12.491597 5, 0xFFFF, sum = 0
2720 23:21:12.491687 6, 0xFFFF, sum = 0
2721 23:21:12.494420 7, 0xFFFF, sum = 0
2722 23:21:12.494548 8, 0xFFFF, sum = 0
2723 23:21:12.498110 9, 0xFFFF, sum = 0
2724 23:21:12.498200 10, 0xFFFF, sum = 0
2725 23:21:12.501303 11, 0xFFFF, sum = 0
2726 23:21:12.501391 12, 0x0, sum = 1
2727 23:21:12.504779 13, 0x0, sum = 2
2728 23:21:12.504869 14, 0x0, sum = 3
2729 23:21:12.508358 15, 0x0, sum = 4
2730 23:21:12.508448 best_step = 13
2731 23:21:12.508537
2732 23:21:12.508618 ==
2733 23:21:12.512158 Dram Type= 6, Freq= 0, CH_0, rank 0
2734 23:21:12.514896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2735 23:21:12.518407 ==
2736 23:21:12.518517 RX Vref Scan: 1
2737 23:21:12.518605
2738 23:21:12.521386 Set Vref Range= 32 -> 127
2739 23:21:12.521473
2740 23:21:12.525025 RX Vref 32 -> 127, step: 1
2741 23:21:12.525166
2742 23:21:12.525316 RX Delay -21 -> 252, step: 4
2743 23:21:12.525417
2744 23:21:12.528123 Set Vref, RX VrefLevel [Byte0]: 32
2745 23:21:12.531995 [Byte1]: 32
2746 23:21:12.536579
2747 23:21:12.536676 Set Vref, RX VrefLevel [Byte0]: 33
2748 23:21:12.539201 [Byte1]: 33
2749 23:21:12.543683
2750 23:21:12.543774 Set Vref, RX VrefLevel [Byte0]: 34
2751 23:21:12.546905 [Byte1]: 34
2752 23:21:12.551803
2753 23:21:12.551899 Set Vref, RX VrefLevel [Byte0]: 35
2754 23:21:12.554803 [Byte1]: 35
2755 23:21:12.559510
2756 23:21:12.559629 Set Vref, RX VrefLevel [Byte0]: 36
2757 23:21:12.562993 [Byte1]: 36
2758 23:21:12.567329
2759 23:21:12.567433 Set Vref, RX VrefLevel [Byte0]: 37
2760 23:21:12.570437 [Byte1]: 37
2761 23:21:12.575817
2762 23:21:12.575943 Set Vref, RX VrefLevel [Byte0]: 38
2763 23:21:12.579532 [Byte1]: 38
2764 23:21:12.583646
2765 23:21:12.583742 Set Vref, RX VrefLevel [Byte0]: 39
2766 23:21:12.586558 [Byte1]: 39
2767 23:21:12.591580
2768 23:21:12.591670 Set Vref, RX VrefLevel [Byte0]: 40
2769 23:21:12.594708 [Byte1]: 40
2770 23:21:12.599329
2771 23:21:12.599418 Set Vref, RX VrefLevel [Byte0]: 41
2772 23:21:12.602276 [Byte1]: 41
2773 23:21:12.606948
2774 23:21:12.607038 Set Vref, RX VrefLevel [Byte0]: 42
2775 23:21:12.613491 [Byte1]: 42
2776 23:21:12.613584
2777 23:21:12.617024 Set Vref, RX VrefLevel [Byte0]: 43
2778 23:21:12.620259 [Byte1]: 43
2779 23:21:12.620349
2780 23:21:12.623881 Set Vref, RX VrefLevel [Byte0]: 44
2781 23:21:12.626769 [Byte1]: 44
2782 23:21:12.630635
2783 23:21:12.630730 Set Vref, RX VrefLevel [Byte0]: 45
2784 23:21:12.634074 [Byte1]: 45
2785 23:21:12.638555
2786 23:21:12.638648 Set Vref, RX VrefLevel [Byte0]: 46
2787 23:21:12.642123 [Byte1]: 46
2788 23:21:12.646951
2789 23:21:12.647046 Set Vref, RX VrefLevel [Byte0]: 47
2790 23:21:12.650857 [Byte1]: 47
2791 23:21:12.655248
2792 23:21:12.655340 Set Vref, RX VrefLevel [Byte0]: 48
2793 23:21:12.658151 [Byte1]: 48
2794 23:21:12.662937
2795 23:21:12.663054 Set Vref, RX VrefLevel [Byte0]: 49
2796 23:21:12.666088 [Byte1]: 49
2797 23:21:12.670438
2798 23:21:12.670547 Set Vref, RX VrefLevel [Byte0]: 50
2799 23:21:12.673970 [Byte1]: 50
2800 23:21:12.678263
2801 23:21:12.678379 Set Vref, RX VrefLevel [Byte0]: 51
2802 23:21:12.682012 [Byte1]: 51
2803 23:21:12.686542
2804 23:21:12.686629 Set Vref, RX VrefLevel [Byte0]: 52
2805 23:21:12.690349 [Byte1]: 52
2806 23:21:12.694752
2807 23:21:12.694861 Set Vref, RX VrefLevel [Byte0]: 53
2808 23:21:12.697701 [Byte1]: 53
2809 23:21:12.702310
2810 23:21:12.702440 Set Vref, RX VrefLevel [Byte0]: 54
2811 23:21:12.705345 [Byte1]: 54
2812 23:21:12.709899
2813 23:21:12.709983 Set Vref, RX VrefLevel [Byte0]: 55
2814 23:21:12.713632 [Byte1]: 55
2815 23:21:12.718268
2816 23:21:12.718375 Set Vref, RX VrefLevel [Byte0]: 56
2817 23:21:12.721352 [Byte1]: 56
2818 23:21:12.726226
2819 23:21:12.726308 Set Vref, RX VrefLevel [Byte0]: 57
2820 23:21:12.729429 [Byte1]: 57
2821 23:21:12.734192
2822 23:21:12.734280 Set Vref, RX VrefLevel [Byte0]: 58
2823 23:21:12.737783 [Byte1]: 58
2824 23:21:12.742071
2825 23:21:12.742153 Set Vref, RX VrefLevel [Byte0]: 59
2826 23:21:12.745022 [Byte1]: 59
2827 23:21:12.749778
2828 23:21:12.749861 Set Vref, RX VrefLevel [Byte0]: 60
2829 23:21:12.753249 [Byte1]: 60
2830 23:21:12.757981
2831 23:21:12.758070 Set Vref, RX VrefLevel [Byte0]: 61
2832 23:21:12.761091 [Byte1]: 61
2833 23:21:12.765812
2834 23:21:12.765928 Set Vref, RX VrefLevel [Byte0]: 62
2835 23:21:12.769476 [Byte1]: 62
2836 23:21:12.773541
2837 23:21:12.773649 Set Vref, RX VrefLevel [Byte0]: 63
2838 23:21:12.777005 [Byte1]: 63
2839 23:21:12.781546
2840 23:21:12.781638 Set Vref, RX VrefLevel [Byte0]: 64
2841 23:21:12.785630 [Byte1]: 64
2842 23:21:12.789417
2843 23:21:12.789507 Set Vref, RX VrefLevel [Byte0]: 65
2844 23:21:12.792936 [Byte1]: 65
2845 23:21:12.797152
2846 23:21:12.797261 Set Vref, RX VrefLevel [Byte0]: 66
2847 23:21:12.800317 [Byte1]: 66
2848 23:21:12.805118
2849 23:21:12.805230 Set Vref, RX VrefLevel [Byte0]: 67
2850 23:21:12.808628 [Byte1]: 67
2851 23:21:12.813310
2852 23:21:12.813401 Set Vref, RX VrefLevel [Byte0]: 68
2853 23:21:12.816406 [Byte1]: 68
2854 23:21:12.820891
2855 23:21:12.820987 Final RX Vref Byte 0 = 53 to rank0
2856 23:21:12.824557 Final RX Vref Byte 1 = 51 to rank0
2857 23:21:12.827683 Final RX Vref Byte 0 = 53 to rank1
2858 23:21:12.831311 Final RX Vref Byte 1 = 51 to rank1==
2859 23:21:12.834284 Dram Type= 6, Freq= 0, CH_0, rank 0
2860 23:21:12.840858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2861 23:21:12.840993 ==
2862 23:21:12.841093 DQS Delay:
2863 23:21:12.841185 DQS0 = 0, DQS1 = 0
2864 23:21:12.844492 DQM Delay:
2865 23:21:12.844601 DQM0 = 115, DQM1 = 105
2866 23:21:12.847723 DQ Delay:
2867 23:21:12.850757 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2868 23:21:12.854167 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2869 23:21:12.857615 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2870 23:21:12.860914 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2871 23:21:12.861029
2872 23:21:12.861122
2873 23:21:12.867652 [DQSOSCAuto] RK0, (LSB)MR18= 0xffef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2874 23:21:12.871546 CH0 RK0: MR19=303, MR18=FFEF
2875 23:21:12.877626 CH0_RK0: MR19=0x303, MR18=0xFFEF, DQSOSC=410, MR23=63, INC=39, DEC=26
2876 23:21:12.877758
2877 23:21:12.881465 ----->DramcWriteLeveling(PI) begin...
2878 23:21:12.881583 ==
2879 23:21:12.884386 Dram Type= 6, Freq= 0, CH_0, rank 1
2880 23:21:12.888240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2881 23:21:12.888355 ==
2882 23:21:12.891665 Write leveling (Byte 0): 33 => 33
2883 23:21:12.894515 Write leveling (Byte 1): 28 => 28
2884 23:21:12.898128 DramcWriteLeveling(PI) end<-----
2885 23:21:12.898242
2886 23:21:12.898336 ==
2887 23:21:12.901308 Dram Type= 6, Freq= 0, CH_0, rank 1
2888 23:21:12.904730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 23:21:12.907921 ==
2890 23:21:12.908038 [Gating] SW mode calibration
2891 23:21:12.914856 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2892 23:21:12.921205 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2893 23:21:12.924858 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2894 23:21:12.931694 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2895 23:21:12.934931 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 23:21:12.938722 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 23:21:12.945437 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 23:21:12.949143 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 23:21:12.951433 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 23:21:12.954957 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
2901 23:21:12.961481 1 0 0 | B1->B0 | 2f2f 2b2b | 0 0 | (0 1) (1 1)
2902 23:21:12.965293 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 23:21:12.968945 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 23:21:12.975715 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 23:21:12.978510 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 23:21:12.981610 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 23:21:12.988393 1 0 24 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
2908 23:21:12.991645 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2909 23:21:12.995810 1 1 0 | B1->B0 | 302f 3e3e | 1 0 | (0 0) (0 0)
2910 23:21:13.001712 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2911 23:21:13.005108 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 23:21:13.008527 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 23:21:13.012146 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 23:21:13.018610 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 23:21:13.022029 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2916 23:21:13.025320 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2917 23:21:13.032850 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2918 23:21:13.035221 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2919 23:21:13.038764 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 23:21:13.045320 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 23:21:13.048802 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 23:21:13.051890 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 23:21:13.058765 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 23:21:13.062347 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 23:21:13.065346 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 23:21:13.072331 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 23:21:13.076112 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 23:21:13.079062 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 23:21:13.082519 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 23:21:13.089379 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 23:21:13.092139 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 23:21:13.095408 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2933 23:21:13.102159 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2934 23:21:13.105635 Total UI for P1: 0, mck2ui 16
2935 23:21:13.109424 best dqsien dly found for B0: ( 1, 3, 28)
2936 23:21:13.113258 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2937 23:21:13.115563 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 23:21:13.118852 Total UI for P1: 0, mck2ui 16
2939 23:21:13.122171 best dqsien dly found for B1: ( 1, 4, 2)
2940 23:21:13.125912 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2941 23:21:13.129214 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2942 23:21:13.129311
2943 23:21:13.135990 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2944 23:21:13.139357 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2945 23:21:13.139453 [Gating] SW calibration Done
2946 23:21:13.139577 ==
2947 23:21:13.142888 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 23:21:13.149501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 23:21:13.149615 ==
2950 23:21:13.149684 RX Vref Scan: 0
2951 23:21:13.149745
2952 23:21:13.152773 RX Vref 0 -> 0, step: 1
2953 23:21:13.152885
2954 23:21:13.155885 RX Delay -40 -> 252, step: 8
2955 23:21:13.159882 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2956 23:21:13.162753 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2957 23:21:13.166018 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2958 23:21:13.169603 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2959 23:21:13.176480 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2960 23:21:13.179347 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2961 23:21:13.182673 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2962 23:21:13.186197 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2963 23:21:13.189567 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2964 23:21:13.196306 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2965 23:21:13.199415 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2966 23:21:13.202796 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2967 23:21:13.206516 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2968 23:21:13.209783 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2969 23:21:13.216493 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2970 23:21:13.219981 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2971 23:21:13.220084 ==
2972 23:21:13.222982 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 23:21:13.226736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 23:21:13.226832 ==
2975 23:21:13.226913 DQS Delay:
2976 23:21:13.230065 DQS0 = 0, DQS1 = 0
2977 23:21:13.230155 DQM Delay:
2978 23:21:13.233240 DQM0 = 115, DQM1 = 105
2979 23:21:13.233329 DQ Delay:
2980 23:21:13.236611 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2981 23:21:13.239744 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2982 23:21:13.242859 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2983 23:21:13.246443 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2984 23:21:13.246544
2985 23:21:13.246633
2986 23:21:13.250024 ==
2987 23:21:13.253481 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 23:21:13.256704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 23:21:13.256849 ==
2990 23:21:13.256944
2991 23:21:13.257025
2992 23:21:13.260305 TX Vref Scan disable
2993 23:21:13.260415 == TX Byte 0 ==
2994 23:21:13.263696 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2995 23:21:13.270176 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2996 23:21:13.270319 == TX Byte 1 ==
2997 23:21:13.273284 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2998 23:21:13.279709 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2999 23:21:13.279822 ==
3000 23:21:13.283164 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 23:21:13.287250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 23:21:13.287349 ==
3003 23:21:13.298944 TX Vref=22, minBit 1, minWin=25, winSum=420
3004 23:21:13.302198 TX Vref=24, minBit 0, minWin=25, winSum=424
3005 23:21:13.305198 TX Vref=26, minBit 1, minWin=26, winSum=430
3006 23:21:13.309587 TX Vref=28, minBit 0, minWin=26, winSum=429
3007 23:21:13.312074 TX Vref=30, minBit 2, minWin=26, winSum=433
3008 23:21:13.315396 TX Vref=32, minBit 3, minWin=26, winSum=434
3009 23:21:13.322692 [TxChooseVref] Worse bit 3, Min win 26, Win sum 434, Final Vref 32
3010 23:21:13.322810
3011 23:21:13.326013 Final TX Range 1 Vref 32
3012 23:21:13.326104
3013 23:21:13.326191 ==
3014 23:21:13.328960 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 23:21:13.332403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 23:21:13.332497 ==
3017 23:21:13.332587
3018 23:21:13.335910
3019 23:21:13.336001 TX Vref Scan disable
3020 23:21:13.338787 == TX Byte 0 ==
3021 23:21:13.342103 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3022 23:21:13.345664 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3023 23:21:13.349532 == TX Byte 1 ==
3024 23:21:13.352672 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3025 23:21:13.356426 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3026 23:21:13.356525
3027 23:21:13.359226 [DATLAT]
3028 23:21:13.359316 Freq=1200, CH0 RK1
3029 23:21:13.359405
3030 23:21:13.362195 DATLAT Default: 0xd
3031 23:21:13.362283 0, 0xFFFF, sum = 0
3032 23:21:13.366182 1, 0xFFFF, sum = 0
3033 23:21:13.366300 2, 0xFFFF, sum = 0
3034 23:21:13.369198 3, 0xFFFF, sum = 0
3035 23:21:13.369285 4, 0xFFFF, sum = 0
3036 23:21:13.372670 5, 0xFFFF, sum = 0
3037 23:21:13.372758 6, 0xFFFF, sum = 0
3038 23:21:13.375624 7, 0xFFFF, sum = 0
3039 23:21:13.375711 8, 0xFFFF, sum = 0
3040 23:21:13.378837 9, 0xFFFF, sum = 0
3041 23:21:13.378923 10, 0xFFFF, sum = 0
3042 23:21:13.382355 11, 0xFFFF, sum = 0
3043 23:21:13.382453 12, 0x0, sum = 1
3044 23:21:13.385864 13, 0x0, sum = 2
3045 23:21:13.385949 14, 0x0, sum = 3
3046 23:21:13.388812 15, 0x0, sum = 4
3047 23:21:13.388896 best_step = 13
3048 23:21:13.388962
3049 23:21:13.389022 ==
3050 23:21:13.392704 Dram Type= 6, Freq= 0, CH_0, rank 1
3051 23:21:13.399220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3052 23:21:13.399325 ==
3053 23:21:13.399397 RX Vref Scan: 0
3054 23:21:13.399460
3055 23:21:13.402320 RX Vref 0 -> 0, step: 1
3056 23:21:13.402427
3057 23:21:13.405615 RX Delay -21 -> 252, step: 4
3058 23:21:13.408765 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3059 23:21:13.412211 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3060 23:21:13.419017 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3061 23:21:13.422764 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3062 23:21:13.425723 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3063 23:21:13.429350 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3064 23:21:13.432760 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3065 23:21:13.435989 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3066 23:21:13.443041 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3067 23:21:13.446139 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3068 23:21:13.449387 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3069 23:21:13.452618 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3070 23:21:13.456483 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3071 23:21:13.462985 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3072 23:21:13.465954 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3073 23:21:13.469338 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3074 23:21:13.469434 ==
3075 23:21:13.473204 Dram Type= 6, Freq= 0, CH_0, rank 1
3076 23:21:13.476069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 23:21:13.476163 ==
3078 23:21:13.479300 DQS Delay:
3079 23:21:13.479386 DQS0 = 0, DQS1 = 0
3080 23:21:13.482634 DQM Delay:
3081 23:21:13.482754 DQM0 = 113, DQM1 = 104
3082 23:21:13.482852 DQ Delay:
3083 23:21:13.486156 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3084 23:21:13.493507 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =120
3085 23:21:13.496553 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3086 23:21:13.499866 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3087 23:21:13.499982
3088 23:21:13.500078
3089 23:21:13.506311 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3090 23:21:13.509462 CH0 RK1: MR19=403, MR18=3F5
3091 23:21:13.516275 CH0_RK1: MR19=0x403, MR18=0x3F5, DQSOSC=408, MR23=63, INC=39, DEC=26
3092 23:21:13.519521 [RxdqsGatingPostProcess] freq 1200
3093 23:21:13.523035 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3094 23:21:13.526655 best DQS0 dly(2T, 0.5T) = (0, 12)
3095 23:21:13.529795 best DQS1 dly(2T, 0.5T) = (0, 12)
3096 23:21:13.532943 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3097 23:21:13.536637 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3098 23:21:13.540416 best DQS0 dly(2T, 0.5T) = (0, 11)
3099 23:21:13.543365 best DQS1 dly(2T, 0.5T) = (0, 12)
3100 23:21:13.547136 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3101 23:21:13.549869 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3102 23:21:13.553351 Pre-setting of DQS Precalculation
3103 23:21:13.557265 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3104 23:21:13.557390 ==
3105 23:21:13.560222 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 23:21:13.564110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 23:21:13.564229 ==
3108 23:21:13.569861 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3109 23:21:13.576900 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3110 23:21:13.584729 [CA 0] Center 38 (9~68) winsize 60
3111 23:21:13.587922 [CA 1] Center 38 (8~68) winsize 61
3112 23:21:13.590949 [CA 2] Center 35 (6~65) winsize 60
3113 23:21:13.594410 [CA 3] Center 34 (4~65) winsize 62
3114 23:21:13.598006 [CA 4] Center 34 (4~65) winsize 62
3115 23:21:13.601376 [CA 5] Center 34 (4~64) winsize 61
3116 23:21:13.601500
3117 23:21:13.604855 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3118 23:21:13.604970
3119 23:21:13.608218 [CATrainingPosCal] consider 1 rank data
3120 23:21:13.611146 u2DelayCellTimex100 = 270/100 ps
3121 23:21:13.614367 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3122 23:21:13.617749 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3123 23:21:13.621569 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3124 23:21:13.628130 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3125 23:21:13.631473 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3126 23:21:13.634627 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3127 23:21:13.634753
3128 23:21:13.638067 CA PerBit enable=1, Macro0, CA PI delay=34
3129 23:21:13.638175
3130 23:21:13.641001 [CBTSetCACLKResult] CA Dly = 34
3131 23:21:13.641110 CS Dly: 6 (0~37)
3132 23:21:13.641205 ==
3133 23:21:13.644614 Dram Type= 6, Freq= 0, CH_1, rank 1
3134 23:21:13.651221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 23:21:13.651343 ==
3136 23:21:13.654592 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3137 23:21:13.661386 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3138 23:21:13.670336 [CA 0] Center 38 (8~68) winsize 61
3139 23:21:13.673090 [CA 1] Center 38 (9~68) winsize 60
3140 23:21:13.676611 [CA 2] Center 34 (4~65) winsize 62
3141 23:21:13.680063 [CA 3] Center 34 (4~65) winsize 62
3142 23:21:13.683574 [CA 4] Center 34 (4~65) winsize 62
3143 23:21:13.686975 [CA 5] Center 33 (3~64) winsize 62
3144 23:21:13.687087
3145 23:21:13.690171 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3146 23:21:13.690279
3147 23:21:13.693386 [CATrainingPosCal] consider 2 rank data
3148 23:21:13.696728 u2DelayCellTimex100 = 270/100 ps
3149 23:21:13.700518 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3150 23:21:13.704759 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3151 23:21:13.706805 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3152 23:21:13.713694 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3153 23:21:13.717107 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3154 23:21:13.720247 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3155 23:21:13.720364
3156 23:21:13.723392 CA PerBit enable=1, Macro0, CA PI delay=34
3157 23:21:13.723500
3158 23:21:13.727102 [CBTSetCACLKResult] CA Dly = 34
3159 23:21:13.727211 CS Dly: 8 (0~41)
3160 23:21:13.727305
3161 23:21:13.730088 ----->DramcWriteLeveling(PI) begin...
3162 23:21:13.730197 ==
3163 23:21:13.733582 Dram Type= 6, Freq= 0, CH_1, rank 0
3164 23:21:13.740425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 23:21:13.740547 ==
3166 23:21:13.743590 Write leveling (Byte 0): 25 => 25
3167 23:21:13.747099 Write leveling (Byte 1): 29 => 29
3168 23:21:13.747211 DramcWriteLeveling(PI) end<-----
3169 23:21:13.747304
3170 23:21:13.750501 ==
3171 23:21:13.750608 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 23:21:13.756921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 23:21:13.757040 ==
3174 23:21:13.760453 [Gating] SW mode calibration
3175 23:21:13.767366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3176 23:21:13.770644 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3177 23:21:13.777122 0 15 0 | B1->B0 | 2929 2322 | 1 1 | (1 1) (0 0)
3178 23:21:13.780653 0 15 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3179 23:21:13.783863 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 23:21:13.790872 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 23:21:13.794108 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 23:21:13.797485 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 23:21:13.800417 0 15 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3184 23:21:13.806999 0 15 28 | B1->B0 | 3232 3434 | 1 0 | (1 1) (0 0)
3185 23:21:13.810720 1 0 0 | B1->B0 | 2323 2b2b | 0 0 | (1 0) (1 0)
3186 23:21:13.813994 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 23:21:13.820572 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 23:21:13.823936 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 23:21:13.827312 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 23:21:13.833987 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 23:21:13.837483 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 23:21:13.840767 1 0 28 | B1->B0 | 2d2d 2525 | 0 0 | (0 0) (0 0)
3193 23:21:13.847630 1 1 0 | B1->B0 | 4444 3c3c | 1 0 | (0 0) (0 0)
3194 23:21:13.850605 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 23:21:13.853922 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 23:21:13.860559 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 23:21:13.864217 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 23:21:13.867821 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 23:21:13.871817 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 23:21:13.877912 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 23:21:13.880715 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3202 23:21:13.884328 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 23:21:13.890777 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 23:21:13.895037 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 23:21:13.897902 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 23:21:13.904354 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 23:21:13.907611 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 23:21:13.911529 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 23:21:13.918198 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 23:21:13.921542 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 23:21:13.924254 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 23:21:13.931983 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 23:21:13.934469 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 23:21:13.937995 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 23:21:13.941374 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 23:21:13.947817 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3217 23:21:13.951433 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3218 23:21:13.955062 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 23:21:13.957986 Total UI for P1: 0, mck2ui 16
3220 23:21:13.962154 best dqsien dly found for B0: ( 1, 3, 30)
3221 23:21:13.965296 Total UI for P1: 0, mck2ui 16
3222 23:21:13.968399 best dqsien dly found for B1: ( 1, 4, 0)
3223 23:21:13.971643 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3224 23:21:13.974788 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3225 23:21:13.974902
3226 23:21:13.981587 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3227 23:21:13.985189 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3228 23:21:13.985312 [Gating] SW calibration Done
3229 23:21:13.985406 ==
3230 23:21:13.988272 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 23:21:13.995031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 23:21:13.995157 ==
3233 23:21:13.995251 RX Vref Scan: 0
3234 23:21:13.995341
3235 23:21:13.998190 RX Vref 0 -> 0, step: 1
3236 23:21:13.998316
3237 23:21:14.001661 RX Delay -40 -> 252, step: 8
3238 23:21:14.004783 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3239 23:21:14.008466 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3240 23:21:14.011918 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3241 23:21:14.018304 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3242 23:21:14.022019 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3243 23:21:14.024911 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3244 23:21:14.028922 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3245 23:21:14.031908 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3246 23:21:14.035315 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3247 23:21:14.041826 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3248 23:21:14.045299 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3249 23:21:14.048512 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3250 23:21:14.051954 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3251 23:21:14.056176 iDelay=200, Bit 13, Center 119 (56 ~ 183) 128
3252 23:21:14.062701 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3253 23:21:14.065209 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3254 23:21:14.065342 ==
3255 23:21:14.069140 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 23:21:14.072369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 23:21:14.072482 ==
3258 23:21:14.072610 DQS Delay:
3259 23:21:14.075850 DQS0 = 0, DQS1 = 0
3260 23:21:14.075959 DQM Delay:
3261 23:21:14.078978 DQM0 = 115, DQM1 = 109
3262 23:21:14.079085 DQ Delay:
3263 23:21:14.082026 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3264 23:21:14.085445 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3265 23:21:14.089350 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3266 23:21:14.092001 DQ12 =123, DQ13 =119, DQ14 =111, DQ15 =115
3267 23:21:14.092085
3268 23:21:14.095787
3269 23:21:14.095895 ==
3270 23:21:14.098659 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 23:21:14.102019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 23:21:14.102128 ==
3273 23:21:14.102221
3274 23:21:14.102310
3275 23:21:14.105893 TX Vref Scan disable
3276 23:21:14.106000 == TX Byte 0 ==
3277 23:21:14.109539 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3278 23:21:14.115668 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3279 23:21:14.115785 == TX Byte 1 ==
3280 23:21:14.118986 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3281 23:21:14.125564 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3282 23:21:14.125680 ==
3283 23:21:14.128877 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 23:21:14.132634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 23:21:14.132744 ==
3286 23:21:14.144926 TX Vref=22, minBit 1, minWin=25, winSum=410
3287 23:21:14.147675 TX Vref=24, minBit 9, minWin=25, winSum=416
3288 23:21:14.151243 TX Vref=26, minBit 1, minWin=25, winSum=422
3289 23:21:14.154295 TX Vref=28, minBit 0, minWin=26, winSum=429
3290 23:21:14.158421 TX Vref=30, minBit 1, minWin=26, winSum=430
3291 23:21:14.161010 TX Vref=32, minBit 1, minWin=26, winSum=431
3292 23:21:14.167903 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 32
3293 23:21:14.168045
3294 23:21:14.171263 Final TX Range 1 Vref 32
3295 23:21:14.171482
3296 23:21:14.171587 ==
3297 23:21:14.174484 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 23:21:14.178382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 23:21:14.178591 ==
3300 23:21:14.178702
3301 23:21:14.178791
3302 23:21:14.181262 TX Vref Scan disable
3303 23:21:14.184795 == TX Byte 0 ==
3304 23:21:14.188231 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3305 23:21:14.191813 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3306 23:21:14.194616 == TX Byte 1 ==
3307 23:21:14.198365 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3308 23:21:14.201160 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3309 23:21:14.201298
3310 23:21:14.204706 [DATLAT]
3311 23:21:14.204817 Freq=1200, CH1 RK0
3312 23:21:14.204911
3313 23:21:14.208328 DATLAT Default: 0xd
3314 23:21:14.208438 0, 0xFFFF, sum = 0
3315 23:21:14.211138 1, 0xFFFF, sum = 0
3316 23:21:14.211261 2, 0xFFFF, sum = 0
3317 23:21:14.214571 3, 0xFFFF, sum = 0
3318 23:21:14.214706 4, 0xFFFF, sum = 0
3319 23:21:14.218309 5, 0xFFFF, sum = 0
3320 23:21:14.218490 6, 0xFFFF, sum = 0
3321 23:21:14.221472 7, 0xFFFF, sum = 0
3322 23:21:14.221603 8, 0xFFFF, sum = 0
3323 23:21:14.224702 9, 0xFFFF, sum = 0
3324 23:21:14.224866 10, 0xFFFF, sum = 0
3325 23:21:14.228365 11, 0xFFFF, sum = 0
3326 23:21:14.228485 12, 0x0, sum = 1
3327 23:21:14.231464 13, 0x0, sum = 2
3328 23:21:14.231577 14, 0x0, sum = 3
3329 23:21:14.234969 15, 0x0, sum = 4
3330 23:21:14.235101 best_step = 13
3331 23:21:14.235195
3332 23:21:14.235284 ==
3333 23:21:14.238337 Dram Type= 6, Freq= 0, CH_1, rank 0
3334 23:21:14.245244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3335 23:21:14.245395 ==
3336 23:21:14.245494 RX Vref Scan: 1
3337 23:21:14.245583
3338 23:21:14.248145 Set Vref Range= 32 -> 127
3339 23:21:14.248254
3340 23:21:14.252280 RX Vref 32 -> 127, step: 1
3341 23:21:14.252394
3342 23:21:14.252488 RX Delay -21 -> 252, step: 4
3343 23:21:14.252578
3344 23:21:14.255258 Set Vref, RX VrefLevel [Byte0]: 32
3345 23:21:14.258685 [Byte1]: 32
3346 23:21:14.262456
3347 23:21:14.262574 Set Vref, RX VrefLevel [Byte0]: 33
3348 23:21:14.266114 [Byte1]: 33
3349 23:21:14.270340
3350 23:21:14.270484 Set Vref, RX VrefLevel [Byte0]: 34
3351 23:21:14.274379 [Byte1]: 34
3352 23:21:14.278480
3353 23:21:14.278598 Set Vref, RX VrefLevel [Byte0]: 35
3354 23:21:14.282155 [Byte1]: 35
3355 23:21:14.286873
3356 23:21:14.286969 Set Vref, RX VrefLevel [Byte0]: 36
3357 23:21:14.289743 [Byte1]: 36
3358 23:21:14.294559
3359 23:21:14.294647 Set Vref, RX VrefLevel [Byte0]: 37
3360 23:21:14.297914 [Byte1]: 37
3361 23:21:14.302124
3362 23:21:14.302211 Set Vref, RX VrefLevel [Byte0]: 38
3363 23:21:14.305632 [Byte1]: 38
3364 23:21:14.310552
3365 23:21:14.310641 Set Vref, RX VrefLevel [Byte0]: 39
3366 23:21:14.313544 [Byte1]: 39
3367 23:21:14.318745
3368 23:21:14.318831 Set Vref, RX VrefLevel [Byte0]: 40
3369 23:21:14.321386 [Byte1]: 40
3370 23:21:14.325910
3371 23:21:14.325996 Set Vref, RX VrefLevel [Byte0]: 41
3372 23:21:14.329546 [Byte1]: 41
3373 23:21:14.334163
3374 23:21:14.334262 Set Vref, RX VrefLevel [Byte0]: 42
3375 23:21:14.337959 [Byte1]: 42
3376 23:21:14.341961
3377 23:21:14.342051 Set Vref, RX VrefLevel [Byte0]: 43
3378 23:21:14.344964 [Byte1]: 43
3379 23:21:14.350292
3380 23:21:14.350385 Set Vref, RX VrefLevel [Byte0]: 44
3381 23:21:14.352924 [Byte1]: 44
3382 23:21:14.358110
3383 23:21:14.358205 Set Vref, RX VrefLevel [Byte0]: 45
3384 23:21:14.361188 [Byte1]: 45
3385 23:21:14.365593
3386 23:21:14.365690 Set Vref, RX VrefLevel [Byte0]: 46
3387 23:21:14.369123 [Byte1]: 46
3388 23:21:14.373612
3389 23:21:14.373713 Set Vref, RX VrefLevel [Byte0]: 47
3390 23:21:14.376585 [Byte1]: 47
3391 23:21:14.381741
3392 23:21:14.381835 Set Vref, RX VrefLevel [Byte0]: 48
3393 23:21:14.385243 [Byte1]: 48
3394 23:21:14.389152
3395 23:21:14.389240 Set Vref, RX VrefLevel [Byte0]: 49
3396 23:21:14.392819 [Byte1]: 49
3397 23:21:14.397501
3398 23:21:14.397612 Set Vref, RX VrefLevel [Byte0]: 50
3399 23:21:14.400405 [Byte1]: 50
3400 23:21:14.405012
3401 23:21:14.405136 Set Vref, RX VrefLevel [Byte0]: 51
3402 23:21:14.408725 [Byte1]: 51
3403 23:21:14.413148
3404 23:21:14.413244 Set Vref, RX VrefLevel [Byte0]: 52
3405 23:21:14.416441 [Byte1]: 52
3406 23:21:14.421257
3407 23:21:14.421357 Set Vref, RX VrefLevel [Byte0]: 53
3408 23:21:14.424182 [Byte1]: 53
3409 23:21:14.428779
3410 23:21:14.428870 Set Vref, RX VrefLevel [Byte0]: 54
3411 23:21:14.432462 [Byte1]: 54
3412 23:21:14.436779
3413 23:21:14.436906 Set Vref, RX VrefLevel [Byte0]: 55
3414 23:21:14.440479 [Byte1]: 55
3415 23:21:14.444946
3416 23:21:14.445046 Set Vref, RX VrefLevel [Byte0]: 56
3417 23:21:14.448290 [Byte1]: 56
3418 23:21:14.452904
3419 23:21:14.453018 Set Vref, RX VrefLevel [Byte0]: 57
3420 23:21:14.456281 [Byte1]: 57
3421 23:21:14.460859
3422 23:21:14.460965 Set Vref, RX VrefLevel [Byte0]: 58
3423 23:21:14.464304 [Byte1]: 58
3424 23:21:14.468606
3425 23:21:14.468700 Set Vref, RX VrefLevel [Byte0]: 59
3426 23:21:14.472027 [Byte1]: 59
3427 23:21:14.476685
3428 23:21:14.476786 Set Vref, RX VrefLevel [Byte0]: 60
3429 23:21:14.479898 [Byte1]: 60
3430 23:21:14.484565
3431 23:21:14.484674 Set Vref, RX VrefLevel [Byte0]: 61
3432 23:21:14.487879 [Byte1]: 61
3433 23:21:14.493869
3434 23:21:14.493966 Set Vref, RX VrefLevel [Byte0]: 62
3435 23:21:14.495483 [Byte1]: 62
3436 23:21:14.500853
3437 23:21:14.500945 Set Vref, RX VrefLevel [Byte0]: 63
3438 23:21:14.503909 [Byte1]: 63
3439 23:21:14.508160
3440 23:21:14.508245 Set Vref, RX VrefLevel [Byte0]: 64
3441 23:21:14.511648 [Byte1]: 64
3442 23:21:14.516628
3443 23:21:14.516728 Set Vref, RX VrefLevel [Byte0]: 65
3444 23:21:14.519202 [Byte1]: 65
3445 23:21:14.523853
3446 23:21:14.523938 Set Vref, RX VrefLevel [Byte0]: 66
3447 23:21:14.527641 [Byte1]: 66
3448 23:21:14.531907
3449 23:21:14.531992 Set Vref, RX VrefLevel [Byte0]: 67
3450 23:21:14.535528 [Byte1]: 67
3451 23:21:14.540050
3452 23:21:14.540134 Set Vref, RX VrefLevel [Byte0]: 68
3453 23:21:14.543208 [Byte1]: 68
3454 23:21:14.548310
3455 23:21:14.548398 Set Vref, RX VrefLevel [Byte0]: 69
3456 23:21:14.551133 [Byte1]: 69
3457 23:21:14.555868
3458 23:21:14.555984 Final RX Vref Byte 0 = 54 to rank0
3459 23:21:14.558954 Final RX Vref Byte 1 = 54 to rank0
3460 23:21:14.562376 Final RX Vref Byte 0 = 54 to rank1
3461 23:21:14.566007 Final RX Vref Byte 1 = 54 to rank1==
3462 23:21:14.569127 Dram Type= 6, Freq= 0, CH_1, rank 0
3463 23:21:14.572411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3464 23:21:14.576020 ==
3465 23:21:14.576134 DQS Delay:
3466 23:21:14.576203 DQS0 = 0, DQS1 = 0
3467 23:21:14.579130 DQM Delay:
3468 23:21:14.579220 DQM0 = 115, DQM1 = 109
3469 23:21:14.583026 DQ Delay:
3470 23:21:14.586057 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =112
3471 23:21:14.589411 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =112
3472 23:21:14.592650 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =106
3473 23:21:14.595701 DQ12 =116, DQ13 =114, DQ14 =116, DQ15 =114
3474 23:21:14.595790
3475 23:21:14.595856
3476 23:21:14.602309 [DQSOSCAuto] RK0, (LSB)MR18= 0xfde2, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3477 23:21:14.605880 CH1 RK0: MR19=303, MR18=FDE2
3478 23:21:14.612344 CH1_RK0: MR19=0x303, MR18=0xFDE2, DQSOSC=411, MR23=63, INC=38, DEC=25
3479 23:21:14.612437
3480 23:21:14.615610 ----->DramcWriteLeveling(PI) begin...
3481 23:21:14.615695 ==
3482 23:21:14.619027 Dram Type= 6, Freq= 0, CH_1, rank 1
3483 23:21:14.622439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 23:21:14.622527 ==
3485 23:21:14.626043 Write leveling (Byte 0): 26 => 26
3486 23:21:14.629239 Write leveling (Byte 1): 29 => 29
3487 23:21:14.632661 DramcWriteLeveling(PI) end<-----
3488 23:21:14.632744
3489 23:21:14.632809 ==
3490 23:21:14.635958 Dram Type= 6, Freq= 0, CH_1, rank 1
3491 23:21:14.639565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3492 23:21:14.642376 ==
3493 23:21:14.642487 [Gating] SW mode calibration
3494 23:21:14.652449 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3495 23:21:14.656120 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3496 23:21:14.659377 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3497 23:21:14.666030 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 23:21:14.669633 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 23:21:14.673300 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 23:21:14.679531 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 23:21:14.683051 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3502 23:21:14.686515 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
3503 23:21:14.693193 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3504 23:21:14.695971 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3505 23:21:14.699267 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 23:21:14.706392 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 23:21:14.709227 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 23:21:14.712881 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 23:21:14.715806 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3510 23:21:14.722895 1 0 24 | B1->B0 | 2727 4242 | 0 0 | (1 1) (0 0)
3511 23:21:14.726251 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3512 23:21:14.729274 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 23:21:14.736338 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 23:21:14.739252 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 23:21:14.742521 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 23:21:14.749357 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 23:21:14.752548 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 23:21:14.756388 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3519 23:21:14.763130 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3520 23:21:14.766090 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 23:21:14.769213 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 23:21:14.775964 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 23:21:14.779398 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 23:21:14.782488 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 23:21:14.789353 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 23:21:14.792614 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 23:21:14.796032 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 23:21:14.802481 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 23:21:14.805962 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 23:21:14.809424 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 23:21:14.813011 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 23:21:14.819496 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 23:21:14.822972 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 23:21:14.826101 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3535 23:21:14.833052 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3536 23:21:14.836153 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 23:21:14.839634 Total UI for P1: 0, mck2ui 16
3538 23:21:14.842667 best dqsien dly found for B0: ( 1, 3, 26)
3539 23:21:14.846121 Total UI for P1: 0, mck2ui 16
3540 23:21:14.850104 best dqsien dly found for B1: ( 1, 3, 26)
3541 23:21:14.852797 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3542 23:21:14.856345 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3543 23:21:14.856430
3544 23:21:14.859542 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3545 23:21:14.863117 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3546 23:21:14.866234 [Gating] SW calibration Done
3547 23:21:14.866352 ==
3548 23:21:14.869396 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 23:21:14.873114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 23:21:14.876397 ==
3551 23:21:14.876482 RX Vref Scan: 0
3552 23:21:14.876547
3553 23:21:14.879757 RX Vref 0 -> 0, step: 1
3554 23:21:14.879840
3555 23:21:14.879905 RX Delay -40 -> 252, step: 8
3556 23:21:14.886784 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3557 23:21:14.890222 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3558 23:21:14.892776 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3559 23:21:14.896280 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3560 23:21:14.899960 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3561 23:21:14.906596 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3562 23:21:14.909618 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3563 23:21:14.913480 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3564 23:21:14.916250 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3565 23:21:14.919585 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3566 23:21:14.926544 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3567 23:21:14.929785 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3568 23:21:14.933014 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3569 23:21:14.936805 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3570 23:21:14.939842 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3571 23:21:14.946362 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3572 23:21:14.946487 ==
3573 23:21:14.949686 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 23:21:14.952973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 23:21:14.953058 ==
3576 23:21:14.953123 DQS Delay:
3577 23:21:14.956872 DQS0 = 0, DQS1 = 0
3578 23:21:14.956955 DQM Delay:
3579 23:21:14.959786 DQM0 = 114, DQM1 = 110
3580 23:21:14.959945 DQ Delay:
3581 23:21:14.962911 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3582 23:21:14.966165 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =111
3583 23:21:14.970173 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3584 23:21:14.973104 DQ12 =119, DQ13 =123, DQ14 =115, DQ15 =119
3585 23:21:14.973262
3586 23:21:14.973404
3587 23:21:14.973546 ==
3588 23:21:14.976241 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 23:21:14.983367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 23:21:14.983552 ==
3591 23:21:14.983698
3592 23:21:14.983829
3593 23:21:14.983965 TX Vref Scan disable
3594 23:21:14.986846 == TX Byte 0 ==
3595 23:21:14.990306 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3596 23:21:14.993618 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3597 23:21:14.997399 == TX Byte 1 ==
3598 23:21:15.000500 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3599 23:21:15.003613 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3600 23:21:15.006780 ==
3601 23:21:15.010363 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 23:21:15.013502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 23:21:15.013660 ==
3604 23:21:15.024830 TX Vref=22, minBit 1, minWin=25, winSum=420
3605 23:21:15.027866 TX Vref=24, minBit 0, minWin=25, winSum=424
3606 23:21:15.031051 TX Vref=26, minBit 3, minWin=25, winSum=427
3607 23:21:15.034909 TX Vref=28, minBit 1, minWin=26, winSum=433
3608 23:21:15.038404 TX Vref=30, minBit 2, minWin=26, winSum=431
3609 23:21:15.041363 TX Vref=32, minBit 0, minWin=26, winSum=431
3610 23:21:15.048046 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 28
3611 23:21:15.048216
3612 23:21:15.051461 Final TX Range 1 Vref 28
3613 23:21:15.051547
3614 23:21:15.051613 ==
3615 23:21:15.054537 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 23:21:15.057904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 23:21:15.057991 ==
3618 23:21:15.058058
3619 23:21:15.061713
3620 23:21:15.061800 TX Vref Scan disable
3621 23:21:15.065060 == TX Byte 0 ==
3622 23:21:15.067877 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3623 23:21:15.071540 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3624 23:21:15.074650 == TX Byte 1 ==
3625 23:21:15.077927 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3626 23:21:15.081339 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3627 23:21:15.081429
3628 23:21:15.084547 [DATLAT]
3629 23:21:15.084631 Freq=1200, CH1 RK1
3630 23:21:15.084697
3631 23:21:15.088141 DATLAT Default: 0xd
3632 23:21:15.088224 0, 0xFFFF, sum = 0
3633 23:21:15.092008 1, 0xFFFF, sum = 0
3634 23:21:15.092093 2, 0xFFFF, sum = 0
3635 23:21:15.096003 3, 0xFFFF, sum = 0
3636 23:21:15.096087 4, 0xFFFF, sum = 0
3637 23:21:15.099127 5, 0xFFFF, sum = 0
3638 23:21:15.099211 6, 0xFFFF, sum = 0
3639 23:21:15.101524 7, 0xFFFF, sum = 0
3640 23:21:15.101607 8, 0xFFFF, sum = 0
3641 23:21:15.104746 9, 0xFFFF, sum = 0
3642 23:21:15.107858 10, 0xFFFF, sum = 0
3643 23:21:15.107942 11, 0xFFFF, sum = 0
3644 23:21:15.111209 12, 0x0, sum = 1
3645 23:21:15.111299 13, 0x0, sum = 2
3646 23:21:15.111367 14, 0x0, sum = 3
3647 23:21:15.115336 15, 0x0, sum = 4
3648 23:21:15.115419 best_step = 13
3649 23:21:15.115482
3650 23:21:15.118082 ==
3651 23:21:15.118167 Dram Type= 6, Freq= 0, CH_1, rank 1
3652 23:21:15.124958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3653 23:21:15.125041 ==
3654 23:21:15.125106 RX Vref Scan: 0
3655 23:21:15.125166
3656 23:21:15.128095 RX Vref 0 -> 0, step: 1
3657 23:21:15.128177
3658 23:21:15.131516 RX Delay -21 -> 252, step: 4
3659 23:21:15.134611 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3660 23:21:15.138064 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3661 23:21:15.144995 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3662 23:21:15.148233 iDelay=191, Bit 3, Center 110 (43 ~ 178) 136
3663 23:21:15.151461 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3664 23:21:15.154836 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3665 23:21:15.157857 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3666 23:21:15.165026 iDelay=191, Bit 7, Center 110 (43 ~ 178) 136
3667 23:21:15.168039 iDelay=191, Bit 8, Center 100 (35 ~ 166) 132
3668 23:21:15.171143 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3669 23:21:15.174902 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3670 23:21:15.177984 iDelay=191, Bit 11, Center 104 (39 ~ 170) 132
3671 23:21:15.184456 iDelay=191, Bit 12, Center 116 (51 ~ 182) 132
3672 23:21:15.187961 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3673 23:21:15.191309 iDelay=191, Bit 14, Center 120 (55 ~ 186) 132
3674 23:21:15.195287 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3675 23:21:15.195369 ==
3676 23:21:15.198197 Dram Type= 6, Freq= 0, CH_1, rank 1
3677 23:21:15.204470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3678 23:21:15.204554 ==
3679 23:21:15.204619 DQS Delay:
3680 23:21:15.204678 DQS0 = 0, DQS1 = 0
3681 23:21:15.208637 DQM Delay:
3682 23:21:15.208721 DQM0 = 113, DQM1 = 110
3683 23:21:15.212245 DQ Delay:
3684 23:21:15.214774 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =110
3685 23:21:15.218416 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3686 23:21:15.221647 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =104
3687 23:21:15.225483 DQ12 =116, DQ13 =118, DQ14 =120, DQ15 =120
3688 23:21:15.225566
3689 23:21:15.225630
3690 23:21:15.231841 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa02, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3691 23:21:15.235082 CH1 RK1: MR19=304, MR18=FA02
3692 23:21:15.241387 CH1_RK1: MR19=0x304, MR18=0xFA02, DQSOSC=409, MR23=63, INC=39, DEC=26
3693 23:21:15.245283 [RxdqsGatingPostProcess] freq 1200
3694 23:21:15.251505 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3695 23:21:15.254937 best DQS0 dly(2T, 0.5T) = (0, 11)
3696 23:21:15.255019 best DQS1 dly(2T, 0.5T) = (0, 12)
3697 23:21:15.257914 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3698 23:21:15.261318 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3699 23:21:15.264936 best DQS0 dly(2T, 0.5T) = (0, 11)
3700 23:21:15.268340 best DQS1 dly(2T, 0.5T) = (0, 11)
3701 23:21:15.271581 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3702 23:21:15.275106 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3703 23:21:15.278098 Pre-setting of DQS Precalculation
3704 23:21:15.284810 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3705 23:21:15.291512 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3706 23:21:15.298193 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3707 23:21:15.298276
3708 23:21:15.298341
3709 23:21:15.301114 [Calibration Summary] 2400 Mbps
3710 23:21:15.301196 CH 0, Rank 0
3711 23:21:15.304786 SW Impedance : PASS
3712 23:21:15.308257 DUTY Scan : NO K
3713 23:21:15.308340 ZQ Calibration : PASS
3714 23:21:15.311495 Jitter Meter : NO K
3715 23:21:15.314663 CBT Training : PASS
3716 23:21:15.314745 Write leveling : PASS
3717 23:21:15.318605 RX DQS gating : PASS
3718 23:21:15.318688 RX DQ/DQS(RDDQC) : PASS
3719 23:21:15.321555 TX DQ/DQS : PASS
3720 23:21:15.325052 RX DATLAT : PASS
3721 23:21:15.325134 RX DQ/DQS(Engine): PASS
3722 23:21:15.328181 TX OE : NO K
3723 23:21:15.328263 All Pass.
3724 23:21:15.328328
3725 23:21:15.331548 CH 0, Rank 1
3726 23:21:15.331630 SW Impedance : PASS
3727 23:21:15.334819 DUTY Scan : NO K
3728 23:21:15.338144 ZQ Calibration : PASS
3729 23:21:15.338226 Jitter Meter : NO K
3730 23:21:15.341609 CBT Training : PASS
3731 23:21:15.344834 Write leveling : PASS
3732 23:21:15.344916 RX DQS gating : PASS
3733 23:21:15.348040 RX DQ/DQS(RDDQC) : PASS
3734 23:21:15.351366 TX DQ/DQS : PASS
3735 23:21:15.351448 RX DATLAT : PASS
3736 23:21:15.354829 RX DQ/DQS(Engine): PASS
3737 23:21:15.354910 TX OE : NO K
3738 23:21:15.358186 All Pass.
3739 23:21:15.358267
3740 23:21:15.358331 CH 1, Rank 0
3741 23:21:15.361590 SW Impedance : PASS
3742 23:21:15.361672 DUTY Scan : NO K
3743 23:21:15.364823 ZQ Calibration : PASS
3744 23:21:15.368299 Jitter Meter : NO K
3745 23:21:15.368381 CBT Training : PASS
3746 23:21:15.371631 Write leveling : PASS
3747 23:21:15.375011 RX DQS gating : PASS
3748 23:21:15.375120 RX DQ/DQS(RDDQC) : PASS
3749 23:21:15.378233 TX DQ/DQS : PASS
3750 23:21:15.381956 RX DATLAT : PASS
3751 23:21:15.382038 RX DQ/DQS(Engine): PASS
3752 23:21:15.385163 TX OE : NO K
3753 23:21:15.385244 All Pass.
3754 23:21:15.385309
3755 23:21:15.388613 CH 1, Rank 1
3756 23:21:15.388695 SW Impedance : PASS
3757 23:21:15.391983 DUTY Scan : NO K
3758 23:21:15.392065 ZQ Calibration : PASS
3759 23:21:15.395411 Jitter Meter : NO K
3760 23:21:15.398206 CBT Training : PASS
3761 23:21:15.398287 Write leveling : PASS
3762 23:21:15.401833 RX DQS gating : PASS
3763 23:21:15.405303 RX DQ/DQS(RDDQC) : PASS
3764 23:21:15.405384 TX DQ/DQS : PASS
3765 23:21:15.408646 RX DATLAT : PASS
3766 23:21:15.411650 RX DQ/DQS(Engine): PASS
3767 23:21:15.411732 TX OE : NO K
3768 23:21:15.415457 All Pass.
3769 23:21:15.415539
3770 23:21:15.415603 DramC Write-DBI off
3771 23:21:15.418609 PER_BANK_REFRESH: Hybrid Mode
3772 23:21:15.418691 TX_TRACKING: ON
3773 23:21:15.428269 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3774 23:21:15.431794 [FAST_K] Save calibration result to emmc
3775 23:21:15.435462 dramc_set_vcore_voltage set vcore to 650000
3776 23:21:15.438297 Read voltage for 600, 5
3777 23:21:15.438426 Vio18 = 0
3778 23:21:15.441699 Vcore = 650000
3779 23:21:15.441780 Vdram = 0
3780 23:21:15.441844 Vddq = 0
3781 23:21:15.441903 Vmddr = 0
3782 23:21:15.448285 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3783 23:21:15.455108 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3784 23:21:15.455192 MEM_TYPE=3, freq_sel=19
3785 23:21:15.458349 sv_algorithm_assistance_LP4_1600
3786 23:21:15.461842 ============ PULL DRAM RESETB DOWN ============
3787 23:21:15.468787 ========== PULL DRAM RESETB DOWN end =========
3788 23:21:15.471583 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3789 23:21:15.475018 ===================================
3790 23:21:15.478307 LPDDR4 DRAM CONFIGURATION
3791 23:21:15.482095 ===================================
3792 23:21:15.482196 EX_ROW_EN[0] = 0x0
3793 23:21:15.485422 EX_ROW_EN[1] = 0x0
3794 23:21:15.485520 LP4Y_EN = 0x0
3795 23:21:15.488491 WORK_FSP = 0x0
3796 23:21:15.488564 WL = 0x2
3797 23:21:15.491793 RL = 0x2
3798 23:21:15.491867 BL = 0x2
3799 23:21:15.494904 RPST = 0x0
3800 23:21:15.495035 RD_PRE = 0x0
3801 23:21:15.498566 WR_PRE = 0x1
3802 23:21:15.502023 WR_PST = 0x0
3803 23:21:15.502106 DBI_WR = 0x0
3804 23:21:15.505387 DBI_RD = 0x0
3805 23:21:15.505470 OTF = 0x1
3806 23:21:15.508818 ===================================
3807 23:21:15.511954 ===================================
3808 23:21:15.512033 ANA top config
3809 23:21:15.515338 ===================================
3810 23:21:15.518813 DLL_ASYNC_EN = 0
3811 23:21:15.522084 ALL_SLAVE_EN = 1
3812 23:21:15.525450 NEW_RANK_MODE = 1
3813 23:21:15.528584 DLL_IDLE_MODE = 1
3814 23:21:15.528666 LP45_APHY_COMB_EN = 1
3815 23:21:15.532025 TX_ODT_DIS = 1
3816 23:21:15.535568 NEW_8X_MODE = 1
3817 23:21:15.539029 ===================================
3818 23:21:15.541987 ===================================
3819 23:21:15.545177 data_rate = 1200
3820 23:21:15.548872 CKR = 1
3821 23:21:15.548954 DQ_P2S_RATIO = 8
3822 23:21:15.551613 ===================================
3823 23:21:15.554868 CA_P2S_RATIO = 8
3824 23:21:15.558194 DQ_CA_OPEN = 0
3825 23:21:15.561485 DQ_SEMI_OPEN = 0
3826 23:21:15.565096 CA_SEMI_OPEN = 0
3827 23:21:15.568345 CA_FULL_RATE = 0
3828 23:21:15.568431 DQ_CKDIV4_EN = 1
3829 23:21:15.571984 CA_CKDIV4_EN = 1
3830 23:21:15.574830 CA_PREDIV_EN = 0
3831 23:21:15.578353 PH8_DLY = 0
3832 23:21:15.581499 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3833 23:21:15.584945 DQ_AAMCK_DIV = 4
3834 23:21:15.585057 CA_AAMCK_DIV = 4
3835 23:21:15.588246 CA_ADMCK_DIV = 4
3836 23:21:15.591653 DQ_TRACK_CA_EN = 0
3837 23:21:15.594789 CA_PICK = 600
3838 23:21:15.598371 CA_MCKIO = 600
3839 23:21:15.601746 MCKIO_SEMI = 0
3840 23:21:15.605062 PLL_FREQ = 2288
3841 23:21:15.605143 DQ_UI_PI_RATIO = 32
3842 23:21:15.608375 CA_UI_PI_RATIO = 0
3843 23:21:15.612083 ===================================
3844 23:21:15.615241 ===================================
3845 23:21:15.618059 memory_type:LPDDR4
3846 23:21:15.621858 GP_NUM : 10
3847 23:21:15.621946 SRAM_EN : 1
3848 23:21:15.625151 MD32_EN : 0
3849 23:21:15.628187 ===================================
3850 23:21:15.628370 [ANA_INIT] >>>>>>>>>>>>>>
3851 23:21:15.631459 <<<<<< [CONFIGURE PHASE]: ANA_TX
3852 23:21:15.634744 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3853 23:21:15.638290 ===================================
3854 23:21:15.642154 data_rate = 1200,PCW = 0X5800
3855 23:21:15.645376 ===================================
3856 23:21:15.648356 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3857 23:21:15.654727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3858 23:21:15.658123 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3859 23:21:15.664723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3860 23:21:15.668123 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3861 23:21:15.671859 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3862 23:21:15.674723 [ANA_INIT] flow start
3863 23:21:15.674974 [ANA_INIT] PLL >>>>>>>>
3864 23:21:15.678046 [ANA_INIT] PLL <<<<<<<<
3865 23:21:15.681438 [ANA_INIT] MIDPI >>>>>>>>
3866 23:21:15.681603 [ANA_INIT] MIDPI <<<<<<<<
3867 23:21:15.684714 [ANA_INIT] DLL >>>>>>>>
3868 23:21:15.687965 [ANA_INIT] flow end
3869 23:21:15.692097 ============ LP4 DIFF to SE enter ============
3870 23:21:15.694822 ============ LP4 DIFF to SE exit ============
3871 23:21:15.698380 [ANA_INIT] <<<<<<<<<<<<<
3872 23:21:15.701818 [Flow] Enable top DCM control >>>>>
3873 23:21:15.704975 [Flow] Enable top DCM control <<<<<
3874 23:21:15.708298 Enable DLL master slave shuffle
3875 23:21:15.711551 ==============================================================
3876 23:21:15.715276 Gating Mode config
3877 23:21:15.718297 ==============================================================
3878 23:21:15.721608 Config description:
3879 23:21:15.731633 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3880 23:21:15.738088 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3881 23:21:15.741759 SELPH_MODE 0: By rank 1: By Phase
3882 23:21:15.748142 ==============================================================
3883 23:21:15.751740 GAT_TRACK_EN = 1
3884 23:21:15.755587 RX_GATING_MODE = 2
3885 23:21:15.758294 RX_GATING_TRACK_MODE = 2
3886 23:21:15.761616 SELPH_MODE = 1
3887 23:21:15.761725 PICG_EARLY_EN = 1
3888 23:21:15.765077 VALID_LAT_VALUE = 1
3889 23:21:15.771965 ==============================================================
3890 23:21:15.774718 Enter into Gating configuration >>>>
3891 23:21:15.778588 Exit from Gating configuration <<<<
3892 23:21:15.781525 Enter into DVFS_PRE_config >>>>>
3893 23:21:15.791418 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3894 23:21:15.794912 Exit from DVFS_PRE_config <<<<<
3895 23:21:15.798122 Enter into PICG configuration >>>>
3896 23:21:15.801861 Exit from PICG configuration <<<<
3897 23:21:15.805136 [RX_INPUT] configuration >>>>>
3898 23:21:15.808349 [RX_INPUT] configuration <<<<<
3899 23:21:15.811956 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3900 23:21:15.818931 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3901 23:21:15.825006 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3902 23:21:15.831881 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3903 23:21:15.838292 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3904 23:21:15.841769 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3905 23:21:15.848401 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3906 23:21:15.852029 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3907 23:21:15.854926 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3908 23:21:15.858673 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3909 23:21:15.861680 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3910 23:21:15.868447 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3911 23:21:15.871398 ===================================
3912 23:21:15.874713 LPDDR4 DRAM CONFIGURATION
3913 23:21:15.879088 ===================================
3914 23:21:15.879212 EX_ROW_EN[0] = 0x0
3915 23:21:15.881451 EX_ROW_EN[1] = 0x0
3916 23:21:15.881676 LP4Y_EN = 0x0
3917 23:21:15.884934 WORK_FSP = 0x0
3918 23:21:15.885084 WL = 0x2
3919 23:21:15.888179 RL = 0x2
3920 23:21:15.888295 BL = 0x2
3921 23:21:15.891514 RPST = 0x0
3922 23:21:15.891658 RD_PRE = 0x0
3923 23:21:15.894778 WR_PRE = 0x1
3924 23:21:15.894924 WR_PST = 0x0
3925 23:21:15.898558 DBI_WR = 0x0
3926 23:21:15.898643 DBI_RD = 0x0
3927 23:21:15.901918 OTF = 0x1
3928 23:21:15.904923 ===================================
3929 23:21:15.908187 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3930 23:21:15.911763 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3931 23:21:15.918362 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3932 23:21:15.921690 ===================================
3933 23:21:15.921822 LPDDR4 DRAM CONFIGURATION
3934 23:21:15.925175 ===================================
3935 23:21:15.928630 EX_ROW_EN[0] = 0x10
3936 23:21:15.931608 EX_ROW_EN[1] = 0x0
3937 23:21:15.931689 LP4Y_EN = 0x0
3938 23:21:15.935234 WORK_FSP = 0x0
3939 23:21:15.935308 WL = 0x2
3940 23:21:15.938646 RL = 0x2
3941 23:21:15.938718 BL = 0x2
3942 23:21:15.941824 RPST = 0x0
3943 23:21:15.941903 RD_PRE = 0x0
3944 23:21:15.944937 WR_PRE = 0x1
3945 23:21:15.945039 WR_PST = 0x0
3946 23:21:15.948466 DBI_WR = 0x0
3947 23:21:15.948584 DBI_RD = 0x0
3948 23:21:15.952119 OTF = 0x1
3949 23:21:15.955149 ===================================
3950 23:21:15.961715 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3951 23:21:15.965002 nWR fixed to 30
3952 23:21:15.965136 [ModeRegInit_LP4] CH0 RK0
3953 23:21:15.968651 [ModeRegInit_LP4] CH0 RK1
3954 23:21:15.971829 [ModeRegInit_LP4] CH1 RK0
3955 23:21:15.971924 [ModeRegInit_LP4] CH1 RK1
3956 23:21:15.975310 match AC timing 17
3957 23:21:15.978590 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3958 23:21:15.981713 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3959 23:21:15.988536 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3960 23:21:15.991471 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3961 23:21:15.998719 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3962 23:21:15.998845 ==
3963 23:21:16.001997 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 23:21:16.005264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 23:21:16.005349 ==
3966 23:21:16.011618 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3967 23:21:16.014972 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3968 23:21:16.019392 [CA 0] Center 36 (6~66) winsize 61
3969 23:21:16.022742 [CA 1] Center 36 (6~66) winsize 61
3970 23:21:16.026039 [CA 2] Center 34 (4~65) winsize 62
3971 23:21:16.029994 [CA 3] Center 34 (4~64) winsize 61
3972 23:21:16.032811 [CA 4] Center 33 (3~64) winsize 62
3973 23:21:16.036568 [CA 5] Center 33 (3~64) winsize 62
3974 23:21:16.036672
3975 23:21:16.039740 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3976 23:21:16.039831
3977 23:21:16.043198 [CATrainingPosCal] consider 1 rank data
3978 23:21:16.046117 u2DelayCellTimex100 = 270/100 ps
3979 23:21:16.049587 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3980 23:21:16.052715 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3981 23:21:16.059536 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3982 23:21:16.062767 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3983 23:21:16.066131 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3984 23:21:16.069846 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3985 23:21:16.070012
3986 23:21:16.072667 CA PerBit enable=1, Macro0, CA PI delay=33
3987 23:21:16.072787
3988 23:21:16.076179 [CBTSetCACLKResult] CA Dly = 33
3989 23:21:16.076268 CS Dly: 3 (0~34)
3990 23:21:16.076337 ==
3991 23:21:16.079407 Dram Type= 6, Freq= 0, CH_0, rank 1
3992 23:21:16.085833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 23:21:16.085940 ==
3994 23:21:16.089507 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3995 23:21:16.096168 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3996 23:21:16.099867 [CA 0] Center 36 (6~66) winsize 61
3997 23:21:16.102675 [CA 1] Center 36 (6~66) winsize 61
3998 23:21:16.106262 [CA 2] Center 34 (4~65) winsize 62
3999 23:21:16.109649 [CA 3] Center 34 (4~65) winsize 62
4000 23:21:16.113179 [CA 4] Center 33 (3~64) winsize 62
4001 23:21:16.116433 [CA 5] Center 33 (3~64) winsize 62
4002 23:21:16.116518
4003 23:21:16.119778 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4004 23:21:16.119862
4005 23:21:16.122738 [CATrainingPosCal] consider 2 rank data
4006 23:21:16.125997 u2DelayCellTimex100 = 270/100 ps
4007 23:21:16.129497 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4008 23:21:16.133052 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4009 23:21:16.139474 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4010 23:21:16.142769 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4011 23:21:16.146376 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4012 23:21:16.149205 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4013 23:21:16.149288
4014 23:21:16.153223 CA PerBit enable=1, Macro0, CA PI delay=33
4015 23:21:16.153306
4016 23:21:16.155846 [CBTSetCACLKResult] CA Dly = 33
4017 23:21:16.155929 CS Dly: 4 (0~36)
4018 23:21:16.155996
4019 23:21:16.159262 ----->DramcWriteLeveling(PI) begin...
4020 23:21:16.163161 ==
4021 23:21:16.166280 Dram Type= 6, Freq= 0, CH_0, rank 0
4022 23:21:16.169640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4023 23:21:16.169734 ==
4024 23:21:16.172610 Write leveling (Byte 0): 31 => 31
4025 23:21:16.176328 Write leveling (Byte 1): 31 => 31
4026 23:21:16.179500 DramcWriteLeveling(PI) end<-----
4027 23:21:16.179585
4028 23:21:16.179650 ==
4029 23:21:16.183047 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 23:21:16.186348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 23:21:16.186442 ==
4032 23:21:16.189437 [Gating] SW mode calibration
4033 23:21:16.196545 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4034 23:21:16.199681 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4035 23:21:16.206421 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4036 23:21:16.209649 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 23:21:16.213831 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 23:21:16.219713 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4039 23:21:16.223437 0 9 16 | B1->B0 | 3030 2b2b | 0 0 | (0 1) (1 1)
4040 23:21:16.226700 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4041 23:21:16.233393 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 23:21:16.236475 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 23:21:16.239870 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 23:21:16.246347 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 23:21:16.249919 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 23:21:16.253232 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 23:21:16.259924 0 10 16 | B1->B0 | 3030 3a3a | 0 1 | (0 0) (0 0)
4048 23:21:16.262856 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4049 23:21:16.266344 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 23:21:16.269842 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 23:21:16.276566 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 23:21:16.279896 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 23:21:16.282973 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 23:21:16.289477 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 23:21:16.292819 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4056 23:21:16.296285 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 23:21:16.302993 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 23:21:16.306356 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 23:21:16.309705 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 23:21:16.315936 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 23:21:16.319646 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 23:21:16.322557 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 23:21:16.329133 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 23:21:16.332758 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 23:21:16.336098 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 23:21:16.342811 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 23:21:16.346098 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 23:21:16.349636 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 23:21:16.356012 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 23:21:16.359382 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4071 23:21:16.363027 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4072 23:21:16.369661 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 23:21:16.369747 Total UI for P1: 0, mck2ui 16
4074 23:21:16.372771 best dqsien dly found for B0: ( 0, 13, 14)
4075 23:21:16.376270 Total UI for P1: 0, mck2ui 16
4076 23:21:16.379609 best dqsien dly found for B1: ( 0, 13, 16)
4077 23:21:16.382816 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4078 23:21:16.389595 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4079 23:21:16.389677
4080 23:21:16.393115 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4081 23:21:16.396726 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4082 23:21:16.399871 [Gating] SW calibration Done
4083 23:21:16.399953 ==
4084 23:21:16.402876 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 23:21:16.406623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 23:21:16.406705 ==
4087 23:21:16.406770 RX Vref Scan: 0
4088 23:21:16.409593
4089 23:21:16.409674 RX Vref 0 -> 0, step: 1
4090 23:21:16.409738
4091 23:21:16.412785 RX Delay -230 -> 252, step: 16
4092 23:21:16.416887 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4093 23:21:16.422767 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4094 23:21:16.426197 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4095 23:21:16.429990 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4096 23:21:16.433249 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4097 23:21:16.436466 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4098 23:21:16.443071 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4099 23:21:16.446735 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4100 23:21:16.450244 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4101 23:21:16.453114 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4102 23:21:16.459407 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4103 23:21:16.462693 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4104 23:21:16.466034 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4105 23:21:16.469430 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4106 23:21:16.472993 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4107 23:21:16.479405 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4108 23:21:16.479497 ==
4109 23:21:16.483213 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 23:21:16.486378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 23:21:16.486566 ==
4112 23:21:16.486677 DQS Delay:
4113 23:21:16.489826 DQS0 = 0, DQS1 = 0
4114 23:21:16.489952 DQM Delay:
4115 23:21:16.493121 DQM0 = 40, DQM1 = 32
4116 23:21:16.493258 DQ Delay:
4117 23:21:16.496060 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4118 23:21:16.499814 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4119 23:21:16.503153 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4120 23:21:16.506523 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4121 23:21:16.506619
4122 23:21:16.506686
4123 23:21:16.506746 ==
4124 23:21:16.509597 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 23:21:16.513128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 23:21:16.513238 ==
4127 23:21:16.516331
4128 23:21:16.516414
4129 23:21:16.516479 TX Vref Scan disable
4130 23:21:16.519461 == TX Byte 0 ==
4131 23:21:16.522815 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4132 23:21:16.526602 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4133 23:21:16.529584 == TX Byte 1 ==
4134 23:21:16.533330 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4135 23:21:16.536337 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4136 23:21:16.536425 ==
4137 23:21:16.539649 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 23:21:16.546515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 23:21:16.546612 ==
4140 23:21:16.546676
4141 23:21:16.546739
4142 23:21:16.546797 TX Vref Scan disable
4143 23:21:16.550856 == TX Byte 0 ==
4144 23:21:16.554336 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4145 23:21:16.557653 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4146 23:21:16.560811 == TX Byte 1 ==
4147 23:21:16.565018 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4148 23:21:16.567651 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4149 23:21:16.571091
4150 23:21:16.571168 [DATLAT]
4151 23:21:16.571252 Freq=600, CH0 RK0
4152 23:21:16.571316
4153 23:21:16.574309 DATLAT Default: 0x9
4154 23:21:16.574430 0, 0xFFFF, sum = 0
4155 23:21:16.577425 1, 0xFFFF, sum = 0
4156 23:21:16.577511 2, 0xFFFF, sum = 0
4157 23:21:16.581170 3, 0xFFFF, sum = 0
4158 23:21:16.584082 4, 0xFFFF, sum = 0
4159 23:21:16.584165 5, 0xFFFF, sum = 0
4160 23:21:16.587289 6, 0xFFFF, sum = 0
4161 23:21:16.587371 7, 0xFFFF, sum = 0
4162 23:21:16.590531 8, 0x0, sum = 1
4163 23:21:16.590614 9, 0x0, sum = 2
4164 23:21:16.590680 10, 0x0, sum = 3
4165 23:21:16.594030 11, 0x0, sum = 4
4166 23:21:16.594139 best_step = 9
4167 23:21:16.594231
4168 23:21:16.594319 ==
4169 23:21:16.597130 Dram Type= 6, Freq= 0, CH_0, rank 0
4170 23:21:16.603760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 23:21:16.603842 ==
4172 23:21:16.603906 RX Vref Scan: 1
4173 23:21:16.603966
4174 23:21:16.607359 RX Vref 0 -> 0, step: 1
4175 23:21:16.607440
4176 23:21:16.610610 RX Delay -195 -> 252, step: 8
4177 23:21:16.610690
4178 23:21:16.614157 Set Vref, RX VrefLevel [Byte0]: 53
4179 23:21:16.617375 [Byte1]: 51
4180 23:21:16.617456
4181 23:21:16.621105 Final RX Vref Byte 0 = 53 to rank0
4182 23:21:16.623979 Final RX Vref Byte 1 = 51 to rank0
4183 23:21:16.627416 Final RX Vref Byte 0 = 53 to rank1
4184 23:21:16.630419 Final RX Vref Byte 1 = 51 to rank1==
4185 23:21:16.634223 Dram Type= 6, Freq= 0, CH_0, rank 0
4186 23:21:16.637605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 23:21:16.637706 ==
4188 23:21:16.640706 DQS Delay:
4189 23:21:16.640810 DQS0 = 0, DQS1 = 0
4190 23:21:16.640902 DQM Delay:
4191 23:21:16.644351 DQM0 = 43, DQM1 = 33
4192 23:21:16.644451 DQ Delay:
4193 23:21:16.647336 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4194 23:21:16.650800 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4195 23:21:16.653966 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4196 23:21:16.657130 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4197 23:21:16.657262
4198 23:21:16.657381
4199 23:21:16.667386 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e1d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
4200 23:21:16.671032 CH0 RK0: MR19=808, MR18=3E1D
4201 23:21:16.674350 CH0_RK0: MR19=0x808, MR18=0x3E1D, DQSOSC=398, MR23=63, INC=165, DEC=110
4202 23:21:16.674490
4203 23:21:16.677344 ----->DramcWriteLeveling(PI) begin...
4204 23:21:16.680813 ==
4205 23:21:16.680895 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 23:21:16.687492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 23:21:16.687575 ==
4208 23:21:16.691017 Write leveling (Byte 0): 32 => 32
4209 23:21:16.694309 Write leveling (Byte 1): 32 => 32
4210 23:21:16.697994 DramcWriteLeveling(PI) end<-----
4211 23:21:16.698075
4212 23:21:16.698139 ==
4213 23:21:16.701490 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 23:21:16.704376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 23:21:16.704458 ==
4216 23:21:16.707901 [Gating] SW mode calibration
4217 23:21:16.714558 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4218 23:21:16.717642 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4219 23:21:16.723946 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4220 23:21:16.727501 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4221 23:21:16.730930 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 23:21:16.737577 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4223 23:21:16.740940 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
4224 23:21:16.744116 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 23:21:16.750740 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 23:21:16.754342 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 23:21:16.757797 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 23:21:16.764197 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 23:21:16.767529 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 23:21:16.770787 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
4231 23:21:16.777591 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4232 23:21:16.781057 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 23:21:16.783975 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 23:21:16.787416 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 23:21:16.794125 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 23:21:16.797439 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 23:21:16.800976 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 23:21:16.807607 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4239 23:21:16.810848 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4240 23:21:16.814109 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 23:21:16.821002 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 23:21:16.824215 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 23:21:16.827327 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 23:21:16.834354 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 23:21:16.837754 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 23:21:16.841073 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 23:21:16.847367 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 23:21:16.850645 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 23:21:16.854368 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 23:21:16.861057 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 23:21:16.864530 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 23:21:16.867699 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 23:21:16.874644 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 23:21:16.877683 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4255 23:21:16.880910 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 23:21:16.884277 Total UI for P1: 0, mck2ui 16
4257 23:21:16.887601 best dqsien dly found for B0: ( 0, 13, 12)
4258 23:21:16.891193 Total UI for P1: 0, mck2ui 16
4259 23:21:16.894000 best dqsien dly found for B1: ( 0, 13, 14)
4260 23:21:16.897393 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4261 23:21:16.900629 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4262 23:21:16.900720
4263 23:21:16.904306 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4264 23:21:16.911012 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4265 23:21:16.911094 [Gating] SW calibration Done
4266 23:21:16.911159 ==
4267 23:21:16.914390 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 23:21:16.921034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 23:21:16.921117 ==
4270 23:21:16.921183 RX Vref Scan: 0
4271 23:21:16.921243
4272 23:21:16.924464 RX Vref 0 -> 0, step: 1
4273 23:21:16.924547
4274 23:21:16.927386 RX Delay -230 -> 252, step: 16
4275 23:21:16.930833 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4276 23:21:16.934014 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4277 23:21:16.937230 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4278 23:21:16.944283 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4279 23:21:16.947676 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4280 23:21:16.950947 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4281 23:21:16.953796 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4282 23:21:16.960870 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4283 23:21:16.963899 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4284 23:21:16.967304 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4285 23:21:16.970598 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4286 23:21:16.974298 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4287 23:21:16.980660 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4288 23:21:16.984051 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4289 23:21:16.987405 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4290 23:21:16.990622 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4291 23:21:16.993991 ==
4292 23:21:16.994072 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 23:21:17.000618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 23:21:17.000701 ==
4295 23:21:17.000766 DQS Delay:
4296 23:21:17.004481 DQS0 = 0, DQS1 = 0
4297 23:21:17.004562 DQM Delay:
4298 23:21:17.008011 DQM0 = 39, DQM1 = 32
4299 23:21:17.008092 DQ Delay:
4300 23:21:17.010535 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4301 23:21:17.014037 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4302 23:21:17.017364 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4303 23:21:17.020725 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4304 23:21:17.020806
4305 23:21:17.020869
4306 23:21:17.020929 ==
4307 23:21:17.024284 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 23:21:17.027138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 23:21:17.027220 ==
4310 23:21:17.027284
4311 23:21:17.027342
4312 23:21:17.030585 TX Vref Scan disable
4313 23:21:17.034096 == TX Byte 0 ==
4314 23:21:17.037323 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4315 23:21:17.040767 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4316 23:21:17.044363 == TX Byte 1 ==
4317 23:21:17.048112 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4318 23:21:17.050931 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4319 23:21:17.051012 ==
4320 23:21:17.054305 Dram Type= 6, Freq= 0, CH_0, rank 1
4321 23:21:17.057556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 23:21:17.057638 ==
4323 23:21:17.057702
4324 23:21:17.060887
4325 23:21:17.060967 TX Vref Scan disable
4326 23:21:17.064702 == TX Byte 0 ==
4327 23:21:17.067609 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4328 23:21:17.071420 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4329 23:21:17.074292 == TX Byte 1 ==
4330 23:21:17.077610 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4331 23:21:17.081069 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4332 23:21:17.084221
4333 23:21:17.084302 [DATLAT]
4334 23:21:17.084367 Freq=600, CH0 RK1
4335 23:21:17.084426
4336 23:21:17.087608 DATLAT Default: 0x9
4337 23:21:17.087707 0, 0xFFFF, sum = 0
4338 23:21:17.090889 1, 0xFFFF, sum = 0
4339 23:21:17.090972 2, 0xFFFF, sum = 0
4340 23:21:17.094550 3, 0xFFFF, sum = 0
4341 23:21:17.094632 4, 0xFFFF, sum = 0
4342 23:21:17.097587 5, 0xFFFF, sum = 0
4343 23:21:17.097670 6, 0xFFFF, sum = 0
4344 23:21:17.100890 7, 0xFFFF, sum = 0
4345 23:21:17.100999 8, 0x0, sum = 1
4346 23:21:17.104704 9, 0x0, sum = 2
4347 23:21:17.104786 10, 0x0, sum = 3
4348 23:21:17.107480 11, 0x0, sum = 4
4349 23:21:17.107562 best_step = 9
4350 23:21:17.107626
4351 23:21:17.107685 ==
4352 23:21:17.111486 Dram Type= 6, Freq= 0, CH_0, rank 1
4353 23:21:17.117526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4354 23:21:17.117608 ==
4355 23:21:17.117670 RX Vref Scan: 0
4356 23:21:17.117729
4357 23:21:17.120956 RX Vref 0 -> 0, step: 1
4358 23:21:17.121036
4359 23:21:17.124549 RX Delay -195 -> 252, step: 8
4360 23:21:17.127898 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4361 23:21:17.134177 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4362 23:21:17.138078 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4363 23:21:17.140919 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4364 23:21:17.144368 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4365 23:21:17.147822 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4366 23:21:17.154526 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4367 23:21:17.157807 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4368 23:21:17.160978 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4369 23:21:17.165024 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4370 23:21:17.171122 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4371 23:21:17.174358 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4372 23:21:17.177869 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4373 23:21:17.181045 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4374 23:21:17.184052 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4375 23:21:17.190786 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4376 23:21:17.190868 ==
4377 23:21:17.194612 Dram Type= 6, Freq= 0, CH_0, rank 1
4378 23:21:17.197645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 23:21:17.197726 ==
4380 23:21:17.197790 DQS Delay:
4381 23:21:17.200854 DQS0 = 0, DQS1 = 0
4382 23:21:17.200934 DQM Delay:
4383 23:21:17.204060 DQM0 = 40, DQM1 = 33
4384 23:21:17.204140 DQ Delay:
4385 23:21:17.207958 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4386 23:21:17.210851 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4387 23:21:17.214740 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4388 23:21:17.217831 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4389 23:21:17.217913
4390 23:21:17.217976
4391 23:21:17.227859 [DQSOSCAuto] RK1, (LSB)MR18= 0x472a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4392 23:21:17.227943 CH0 RK1: MR19=808, MR18=472A
4393 23:21:17.234560 CH0_RK1: MR19=0x808, MR18=0x472A, DQSOSC=396, MR23=63, INC=167, DEC=111
4394 23:21:17.238046 [RxdqsGatingPostProcess] freq 600
4395 23:21:17.244715 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4396 23:21:17.248121 Pre-setting of DQS Precalculation
4397 23:21:17.251354 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4398 23:21:17.251436 ==
4399 23:21:17.254393 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 23:21:17.257580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 23:21:17.257661 ==
4402 23:21:17.264286 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4403 23:21:17.270988 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4404 23:21:17.274231 [CA 0] Center 35 (5~66) winsize 62
4405 23:21:17.277634 [CA 1] Center 35 (5~66) winsize 62
4406 23:21:17.281189 [CA 2] Center 33 (3~64) winsize 62
4407 23:21:17.284383 [CA 3] Center 33 (3~64) winsize 62
4408 23:21:17.288137 [CA 4] Center 33 (3~64) winsize 62
4409 23:21:17.290918 [CA 5] Center 33 (2~64) winsize 63
4410 23:21:17.290999
4411 23:21:17.294556 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4412 23:21:17.294638
4413 23:21:17.297719 [CATrainingPosCal] consider 1 rank data
4414 23:21:17.301006 u2DelayCellTimex100 = 270/100 ps
4415 23:21:17.304288 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4416 23:21:17.307933 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4417 23:21:17.311112 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4418 23:21:17.314386 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4419 23:21:17.317958 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4420 23:21:17.321343 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4421 23:21:17.324460
4422 23:21:17.327795 CA PerBit enable=1, Macro0, CA PI delay=33
4423 23:21:17.327876
4424 23:21:17.330942 [CBTSetCACLKResult] CA Dly = 33
4425 23:21:17.331023 CS Dly: 5 (0~36)
4426 23:21:17.331087 ==
4427 23:21:17.334883 Dram Type= 6, Freq= 0, CH_1, rank 1
4428 23:21:17.338051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 23:21:17.338133 ==
4430 23:21:17.344252 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4431 23:21:17.351214 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4432 23:21:17.354125 [CA 0] Center 35 (5~66) winsize 62
4433 23:21:17.357748 [CA 1] Center 35 (5~66) winsize 62
4434 23:21:17.360825 [CA 2] Center 34 (3~65) winsize 63
4435 23:21:17.364577 [CA 3] Center 33 (3~64) winsize 62
4436 23:21:17.368078 [CA 4] Center 34 (3~65) winsize 63
4437 23:21:17.371757 [CA 5] Center 33 (3~64) winsize 62
4438 23:21:17.371838
4439 23:21:17.374349 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4440 23:21:17.374470
4441 23:21:17.377800 [CATrainingPosCal] consider 2 rank data
4442 23:21:17.381161 u2DelayCellTimex100 = 270/100 ps
4443 23:21:17.384196 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4444 23:21:17.387952 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4445 23:21:17.391087 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4446 23:21:17.394291 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4447 23:21:17.397868 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4448 23:21:17.404241 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4449 23:21:17.404324
4450 23:21:17.407788 CA PerBit enable=1, Macro0, CA PI delay=33
4451 23:21:17.407870
4452 23:21:17.411419 [CBTSetCACLKResult] CA Dly = 33
4453 23:21:17.411501 CS Dly: 5 (0~36)
4454 23:21:17.411566
4455 23:21:17.414685 ----->DramcWriteLeveling(PI) begin...
4456 23:21:17.414769 ==
4457 23:21:17.417856 Dram Type= 6, Freq= 0, CH_1, rank 0
4458 23:21:17.421555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4459 23:21:17.421638 ==
4460 23:21:17.424832 Write leveling (Byte 0): 29 => 29
4461 23:21:17.428083 Write leveling (Byte 1): 29 => 29
4462 23:21:17.431407 DramcWriteLeveling(PI) end<-----
4463 23:21:17.431490
4464 23:21:17.431554 ==
4465 23:21:17.434886 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 23:21:17.440909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 23:21:17.440991 ==
4468 23:21:17.441057 [Gating] SW mode calibration
4469 23:21:17.451361 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4470 23:21:17.454542 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4471 23:21:17.458051 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4472 23:21:17.464375 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4473 23:21:17.467953 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 23:21:17.470985 0 9 12 | B1->B0 | 3333 3333 | 0 0 | (0 1) (0 0)
4475 23:21:17.477595 0 9 16 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
4476 23:21:17.480906 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 23:21:17.484635 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 23:21:17.490938 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 23:21:17.494256 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 23:21:17.498058 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 23:21:17.504358 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4482 23:21:17.507597 0 10 12 | B1->B0 | 2a2a 3030 | 0 0 | (0 0) (0 0)
4483 23:21:17.510960 0 10 16 | B1->B0 | 3e3e 4141 | 0 0 | (0 0) (1 1)
4484 23:21:17.517565 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 23:21:17.521266 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 23:21:17.524040 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 23:21:17.530751 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 23:21:17.534324 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 23:21:17.538217 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 23:21:17.544070 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 23:21:17.547253 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4492 23:21:17.551103 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 23:21:17.557751 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 23:21:17.560485 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 23:21:17.564085 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 23:21:17.570364 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 23:21:17.574263 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 23:21:17.577081 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 23:21:17.580521 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 23:21:17.587335 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 23:21:17.590522 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 23:21:17.594036 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 23:21:17.600940 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 23:21:17.603808 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 23:21:17.607054 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 23:21:17.613863 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 23:21:17.617189 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4508 23:21:17.620479 Total UI for P1: 0, mck2ui 16
4509 23:21:17.623937 best dqsien dly found for B0: ( 0, 13, 14)
4510 23:21:17.626981 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 23:21:17.630579 Total UI for P1: 0, mck2ui 16
4512 23:21:17.634058 best dqsien dly found for B1: ( 0, 13, 16)
4513 23:21:17.637175 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4514 23:21:17.640509 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4515 23:21:17.640591
4516 23:21:17.647198 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4517 23:21:17.650909 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4518 23:21:17.653585 [Gating] SW calibration Done
4519 23:21:17.653698 ==
4520 23:21:17.657072 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 23:21:17.660417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 23:21:17.660500 ==
4523 23:21:17.660564 RX Vref Scan: 0
4524 23:21:17.660624
4525 23:21:17.663816 RX Vref 0 -> 0, step: 1
4526 23:21:17.663898
4527 23:21:17.667424 RX Delay -230 -> 252, step: 16
4528 23:21:17.670277 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4529 23:21:17.673586 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4530 23:21:17.680687 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4531 23:21:17.684110 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4532 23:21:17.687000 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4533 23:21:17.690649 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4534 23:21:17.697152 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4535 23:21:17.700461 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4536 23:21:17.704033 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4537 23:21:17.707343 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4538 23:21:17.710815 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4539 23:21:17.717314 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4540 23:21:17.720622 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4541 23:21:17.724017 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4542 23:21:17.727321 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4543 23:21:17.733785 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4544 23:21:17.733921 ==
4545 23:21:17.737426 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 23:21:17.740651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 23:21:17.740734 ==
4548 23:21:17.740800 DQS Delay:
4549 23:21:17.743995 DQS0 = 0, DQS1 = 0
4550 23:21:17.744076 DQM Delay:
4551 23:21:17.747390 DQM0 = 42, DQM1 = 35
4552 23:21:17.747472 DQ Delay:
4553 23:21:17.751406 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4554 23:21:17.753664 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4555 23:21:17.756905 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4556 23:21:17.760894 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4557 23:21:17.760976
4558 23:21:17.761040
4559 23:21:17.761099 ==
4560 23:21:17.763981 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 23:21:17.767518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 23:21:17.767601 ==
4563 23:21:17.767667
4564 23:21:17.767726
4565 23:21:17.770901 TX Vref Scan disable
4566 23:21:17.774427 == TX Byte 0 ==
4567 23:21:17.777586 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4568 23:21:17.780568 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4569 23:21:17.784076 == TX Byte 1 ==
4570 23:21:17.787534 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4571 23:21:17.790933 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4572 23:21:17.791015 ==
4573 23:21:17.793662 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 23:21:17.800172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 23:21:17.800316 ==
4576 23:21:17.800381
4577 23:21:17.800440
4578 23:21:17.800498 TX Vref Scan disable
4579 23:21:17.804612 == TX Byte 0 ==
4580 23:21:17.808219 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4581 23:21:17.814792 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4582 23:21:17.814899 == TX Byte 1 ==
4583 23:21:17.817968 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4584 23:21:17.824643 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4585 23:21:17.824741
4586 23:21:17.824835 [DATLAT]
4587 23:21:17.824925 Freq=600, CH1 RK0
4588 23:21:17.825006
4589 23:21:17.827931 DATLAT Default: 0x9
4590 23:21:17.828013 0, 0xFFFF, sum = 0
4591 23:21:17.831435 1, 0xFFFF, sum = 0
4592 23:21:17.831518 2, 0xFFFF, sum = 0
4593 23:21:17.835060 3, 0xFFFF, sum = 0
4594 23:21:17.835144 4, 0xFFFF, sum = 0
4595 23:21:17.838122 5, 0xFFFF, sum = 0
4596 23:21:17.838206 6, 0xFFFF, sum = 0
4597 23:21:17.841420 7, 0xFFFF, sum = 0
4598 23:21:17.841503 8, 0x0, sum = 1
4599 23:21:17.845085 9, 0x0, sum = 2
4600 23:21:17.845168 10, 0x0, sum = 3
4601 23:21:17.848039 11, 0x0, sum = 4
4602 23:21:17.848122 best_step = 9
4603 23:21:17.848185
4604 23:21:17.848244 ==
4605 23:21:17.851823 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 23:21:17.858098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 23:21:17.858179 ==
4608 23:21:17.858243 RX Vref Scan: 1
4609 23:21:17.858302
4610 23:21:17.861573 RX Vref 0 -> 0, step: 1
4611 23:21:17.861654
4612 23:21:17.865209 RX Delay -195 -> 252, step: 8
4613 23:21:17.865290
4614 23:21:17.868130 Set Vref, RX VrefLevel [Byte0]: 54
4615 23:21:17.871399 [Byte1]: 54
4616 23:21:17.871480
4617 23:21:17.874530 Final RX Vref Byte 0 = 54 to rank0
4618 23:21:17.878007 Final RX Vref Byte 1 = 54 to rank0
4619 23:21:17.881352 Final RX Vref Byte 0 = 54 to rank1
4620 23:21:17.885122 Final RX Vref Byte 1 = 54 to rank1==
4621 23:21:17.888114 Dram Type= 6, Freq= 0, CH_1, rank 0
4622 23:21:17.891654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 23:21:17.891735 ==
4624 23:21:17.894578 DQS Delay:
4625 23:21:17.894658 DQS0 = 0, DQS1 = 0
4626 23:21:17.894722 DQM Delay:
4627 23:21:17.898280 DQM0 = 40, DQM1 = 33
4628 23:21:17.898387 DQ Delay:
4629 23:21:17.901141 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4630 23:21:17.904344 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4631 23:21:17.907721 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4632 23:21:17.911035 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4633 23:21:17.911116
4634 23:21:17.911180
4635 23:21:17.921005 [DQSOSCAuto] RK0, (LSB)MR18= 0x440a, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 396 ps
4636 23:21:17.924512 CH1 RK0: MR19=808, MR18=440A
4637 23:21:17.927826 CH1_RK0: MR19=0x808, MR18=0x440A, DQSOSC=396, MR23=63, INC=167, DEC=111
4638 23:21:17.927907
4639 23:21:17.931005 ----->DramcWriteLeveling(PI) begin...
4640 23:21:17.934515 ==
4641 23:21:17.937385 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 23:21:17.940863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 23:21:17.940945 ==
4644 23:21:17.944095 Write leveling (Byte 0): 31 => 31
4645 23:21:17.947839 Write leveling (Byte 1): 31 => 31
4646 23:21:17.950859 DramcWriteLeveling(PI) end<-----
4647 23:21:17.950940
4648 23:21:17.951004 ==
4649 23:21:17.954073 Dram Type= 6, Freq= 0, CH_1, rank 1
4650 23:21:17.957810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 23:21:17.957892 ==
4652 23:21:17.961227 [Gating] SW mode calibration
4653 23:21:17.967897 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4654 23:21:17.975924 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4655 23:21:17.977464 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4656 23:21:17.980886 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4657 23:21:17.984355 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4658 23:21:17.990701 0 9 12 | B1->B0 | 3030 2e2e | 0 1 | (0 0) (1 0)
4659 23:21:17.994230 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 23:21:17.997519 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 23:21:18.004361 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 23:21:18.007569 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 23:21:18.011329 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 23:21:18.017676 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4665 23:21:18.021354 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4666 23:21:18.024300 0 10 12 | B1->B0 | 3232 3c3c | 0 0 | (0 0) (0 0)
4667 23:21:18.031123 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 23:21:18.034647 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 23:21:18.037817 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 23:21:18.044638 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 23:21:18.047766 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 23:21:18.051579 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 23:21:18.054230 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4674 23:21:18.061284 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4675 23:21:18.064488 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 23:21:18.067860 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 23:21:18.074261 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 23:21:18.077851 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 23:21:18.081678 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 23:21:18.087954 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 23:21:18.091111 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 23:21:18.094653 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 23:21:18.101068 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 23:21:18.104526 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 23:21:18.107603 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 23:21:18.114292 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 23:21:18.117596 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 23:21:18.120841 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 23:21:18.127725 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 23:21:18.131154 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4691 23:21:18.134562 Total UI for P1: 0, mck2ui 16
4692 23:21:18.137770 best dqsien dly found for B0: ( 0, 13, 10)
4693 23:21:18.141319 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 23:21:18.144526 Total UI for P1: 0, mck2ui 16
4695 23:21:18.147777 best dqsien dly found for B1: ( 0, 13, 12)
4696 23:21:18.151258 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4697 23:21:18.154561 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4698 23:21:18.154643
4699 23:21:18.157641 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4700 23:21:18.164189 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4701 23:21:18.164271 [Gating] SW calibration Done
4702 23:21:18.164336 ==
4703 23:21:18.167795 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 23:21:18.174378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 23:21:18.174497 ==
4706 23:21:18.174562 RX Vref Scan: 0
4707 23:21:18.174623
4708 23:21:18.177537 RX Vref 0 -> 0, step: 1
4709 23:21:18.177617
4710 23:21:18.181171 RX Delay -230 -> 252, step: 16
4711 23:21:18.184600 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4712 23:21:18.188470 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4713 23:21:18.191522 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4714 23:21:18.197781 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4715 23:21:18.201140 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4716 23:21:18.204541 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4717 23:21:18.207963 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4718 23:21:18.214518 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4719 23:21:18.217875 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4720 23:21:18.221065 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4721 23:21:18.224487 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4722 23:21:18.227989 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4723 23:21:18.234342 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4724 23:21:18.238173 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4725 23:21:18.241382 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4726 23:21:18.244325 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4727 23:21:18.247642 ==
4728 23:21:18.247723 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 23:21:18.254818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 23:21:18.254900 ==
4731 23:21:18.254963 DQS Delay:
4732 23:21:18.257978 DQS0 = 0, DQS1 = 0
4733 23:21:18.258059 DQM Delay:
4734 23:21:18.261049 DQM0 = 37, DQM1 = 37
4735 23:21:18.261129 DQ Delay:
4736 23:21:18.265035 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4737 23:21:18.268264 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4738 23:21:18.271622 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4739 23:21:18.274935 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4740 23:21:18.275016
4741 23:21:18.275080
4742 23:21:18.275140 ==
4743 23:21:18.278114 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 23:21:18.281294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 23:21:18.281375 ==
4746 23:21:18.281439
4747 23:21:18.281499
4748 23:21:18.284222 TX Vref Scan disable
4749 23:21:18.287656 == TX Byte 0 ==
4750 23:21:18.291283 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4751 23:21:18.294366 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4752 23:21:18.297690 == TX Byte 1 ==
4753 23:21:18.301870 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4754 23:21:18.304305 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4755 23:21:18.304387 ==
4756 23:21:18.307814 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 23:21:18.311127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 23:21:18.314332 ==
4759 23:21:18.314469
4760 23:21:18.314534
4761 23:21:18.314594 TX Vref Scan disable
4762 23:21:18.318293 == TX Byte 0 ==
4763 23:21:18.321377 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4764 23:21:18.328279 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4765 23:21:18.328360 == TX Byte 1 ==
4766 23:21:18.331190 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4767 23:21:18.338233 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4768 23:21:18.338340
4769 23:21:18.338435 [DATLAT]
4770 23:21:18.338497 Freq=600, CH1 RK1
4771 23:21:18.338555
4772 23:21:18.342173 DATLAT Default: 0x9
4773 23:21:18.342254 0, 0xFFFF, sum = 0
4774 23:21:18.344870 1, 0xFFFF, sum = 0
4775 23:21:18.344953 2, 0xFFFF, sum = 0
4776 23:21:18.347772 3, 0xFFFF, sum = 0
4777 23:21:18.351472 4, 0xFFFF, sum = 0
4778 23:21:18.351554 5, 0xFFFF, sum = 0
4779 23:21:18.355029 6, 0xFFFF, sum = 0
4780 23:21:18.355112 7, 0xFFFF, sum = 0
4781 23:21:18.355177 8, 0x0, sum = 1
4782 23:21:18.358065 9, 0x0, sum = 2
4783 23:21:18.358147 10, 0x0, sum = 3
4784 23:21:18.361284 11, 0x0, sum = 4
4785 23:21:18.361366 best_step = 9
4786 23:21:18.361431
4787 23:21:18.361491 ==
4788 23:21:18.364620 Dram Type= 6, Freq= 0, CH_1, rank 1
4789 23:21:18.371096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4790 23:21:18.371178 ==
4791 23:21:18.371241 RX Vref Scan: 0
4792 23:21:18.371300
4793 23:21:18.374307 RX Vref 0 -> 0, step: 1
4794 23:21:18.374455
4795 23:21:18.378152 RX Delay -195 -> 252, step: 8
4796 23:21:18.381454 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4797 23:21:18.388279 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4798 23:21:18.391438 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4799 23:21:18.394555 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4800 23:21:18.397846 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4801 23:21:18.401261 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4802 23:21:18.408058 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4803 23:21:18.410986 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4804 23:21:18.414244 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4805 23:21:18.417595 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4806 23:21:18.424304 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4807 23:21:18.427955 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4808 23:21:18.431331 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4809 23:21:18.434287 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4810 23:21:18.441322 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4811 23:21:18.444594 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4812 23:21:18.444676 ==
4813 23:21:18.447583 Dram Type= 6, Freq= 0, CH_1, rank 1
4814 23:21:18.450808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4815 23:21:18.450890 ==
4816 23:21:18.454164 DQS Delay:
4817 23:21:18.454244 DQS0 = 0, DQS1 = 0
4818 23:21:18.454308 DQM Delay:
4819 23:21:18.457378 DQM0 = 36, DQM1 = 32
4820 23:21:18.457459 DQ Delay:
4821 23:21:18.461080 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4822 23:21:18.464385 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4823 23:21:18.467211 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4824 23:21:18.470905 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4825 23:21:18.470986
4826 23:21:18.471049
4827 23:21:18.480890 [DQSOSCAuto] RK1, (LSB)MR18= 0x3847, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4828 23:21:18.480974 CH1 RK1: MR19=808, MR18=3847
4829 23:21:18.490692 CH1_RK1: MR19=0x808, MR18=0x3847, DQSOSC=396, MR23=63, INC=167, DEC=111
4830 23:21:18.490792 [RxdqsGatingPostProcess] freq 600
4831 23:21:18.497283 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4832 23:21:18.500758 Pre-setting of DQS Precalculation
4833 23:21:18.504040 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4834 23:21:18.510844 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4835 23:21:18.520565 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4836 23:21:18.520649
4837 23:21:18.520713
4838 23:21:18.524155 [Calibration Summary] 1200 Mbps
4839 23:21:18.524237 CH 0, Rank 0
4840 23:21:18.527420 SW Impedance : PASS
4841 23:21:18.527506 DUTY Scan : NO K
4842 23:21:18.530878 ZQ Calibration : PASS
4843 23:21:18.533945 Jitter Meter : NO K
4844 23:21:18.534026 CBT Training : PASS
4845 23:21:18.537342 Write leveling : PASS
4846 23:21:18.537423 RX DQS gating : PASS
4847 23:21:18.540827 RX DQ/DQS(RDDQC) : PASS
4848 23:21:18.543701 TX DQ/DQS : PASS
4849 23:21:18.543783 RX DATLAT : PASS
4850 23:21:18.547273 RX DQ/DQS(Engine): PASS
4851 23:21:18.550305 TX OE : NO K
4852 23:21:18.550387 All Pass.
4853 23:21:18.550493
4854 23:21:18.550553 CH 0, Rank 1
4855 23:21:18.553709 SW Impedance : PASS
4856 23:21:18.557211 DUTY Scan : NO K
4857 23:21:18.557292 ZQ Calibration : PASS
4858 23:21:18.560934 Jitter Meter : NO K
4859 23:21:18.563967 CBT Training : PASS
4860 23:21:18.564048 Write leveling : PASS
4861 23:21:18.567416 RX DQS gating : PASS
4862 23:21:18.570768 RX DQ/DQS(RDDQC) : PASS
4863 23:21:18.570850 TX DQ/DQS : PASS
4864 23:21:18.574056 RX DATLAT : PASS
4865 23:21:18.577090 RX DQ/DQS(Engine): PASS
4866 23:21:18.577171 TX OE : NO K
4867 23:21:18.577236 All Pass.
4868 23:21:18.577296
4869 23:21:18.580783 CH 1, Rank 0
4870 23:21:18.583772 SW Impedance : PASS
4871 23:21:18.583854 DUTY Scan : NO K
4872 23:21:18.587185 ZQ Calibration : PASS
4873 23:21:18.587266 Jitter Meter : NO K
4874 23:21:18.590385 CBT Training : PASS
4875 23:21:18.594038 Write leveling : PASS
4876 23:21:18.594119 RX DQS gating : PASS
4877 23:21:18.597318 RX DQ/DQS(RDDQC) : PASS
4878 23:21:18.600613 TX DQ/DQS : PASS
4879 23:21:18.600754 RX DATLAT : PASS
4880 23:21:18.603787 RX DQ/DQS(Engine): PASS
4881 23:21:18.607790 TX OE : NO K
4882 23:21:18.607872 All Pass.
4883 23:21:18.607935
4884 23:21:18.607994 CH 1, Rank 1
4885 23:21:18.610361 SW Impedance : PASS
4886 23:21:18.614208 DUTY Scan : NO K
4887 23:21:18.614289 ZQ Calibration : PASS
4888 23:21:18.617701 Jitter Meter : NO K
4889 23:21:18.621393 CBT Training : PASS
4890 23:21:18.621475 Write leveling : PASS
4891 23:21:18.624366 RX DQS gating : PASS
4892 23:21:18.624451 RX DQ/DQS(RDDQC) : PASS
4893 23:21:18.627401 TX DQ/DQS : PASS
4894 23:21:18.630723 RX DATLAT : PASS
4895 23:21:18.630804 RX DQ/DQS(Engine): PASS
4896 23:21:18.633864 TX OE : NO K
4897 23:21:18.633945 All Pass.
4898 23:21:18.634009
4899 23:21:18.637539 DramC Write-DBI off
4900 23:21:18.640521 PER_BANK_REFRESH: Hybrid Mode
4901 23:21:18.640602 TX_TRACKING: ON
4902 23:21:18.650693 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4903 23:21:18.653994 [FAST_K] Save calibration result to emmc
4904 23:21:18.657421 dramc_set_vcore_voltage set vcore to 662500
4905 23:21:18.660733 Read voltage for 933, 3
4906 23:21:18.660814 Vio18 = 0
4907 23:21:18.660878 Vcore = 662500
4908 23:21:18.664436 Vdram = 0
4909 23:21:18.664517 Vddq = 0
4910 23:21:18.664581 Vmddr = 0
4911 23:21:18.671361 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4912 23:21:18.674230 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4913 23:21:18.677059 MEM_TYPE=3, freq_sel=17
4914 23:21:18.680429 sv_algorithm_assistance_LP4_1600
4915 23:21:18.684436 ============ PULL DRAM RESETB DOWN ============
4916 23:21:18.687273 ========== PULL DRAM RESETB DOWN end =========
4917 23:21:18.693994 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4918 23:21:18.697399 ===================================
4919 23:21:18.697480 LPDDR4 DRAM CONFIGURATION
4920 23:21:18.700794 ===================================
4921 23:21:18.704109 EX_ROW_EN[0] = 0x0
4922 23:21:18.707401 EX_ROW_EN[1] = 0x0
4923 23:21:18.707481 LP4Y_EN = 0x0
4924 23:21:18.710670 WORK_FSP = 0x0
4925 23:21:18.710751 WL = 0x3
4926 23:21:18.714027 RL = 0x3
4927 23:21:18.714108 BL = 0x2
4928 23:21:18.717486 RPST = 0x0
4929 23:21:18.717567 RD_PRE = 0x0
4930 23:21:18.720675 WR_PRE = 0x1
4931 23:21:18.720756 WR_PST = 0x0
4932 23:21:18.724315 DBI_WR = 0x0
4933 23:21:18.724396 DBI_RD = 0x0
4934 23:21:18.727495 OTF = 0x1
4935 23:21:18.731081 ===================================
4936 23:21:18.734279 ===================================
4937 23:21:18.734360 ANA top config
4938 23:21:18.737845 ===================================
4939 23:21:18.741100 DLL_ASYNC_EN = 0
4940 23:21:18.744548 ALL_SLAVE_EN = 1
4941 23:21:18.744629 NEW_RANK_MODE = 1
4942 23:21:18.747417 DLL_IDLE_MODE = 1
4943 23:21:18.750788 LP45_APHY_COMB_EN = 1
4944 23:21:18.754272 TX_ODT_DIS = 1
4945 23:21:18.757628 NEW_8X_MODE = 1
4946 23:21:18.760850 ===================================
4947 23:21:18.764280 ===================================
4948 23:21:18.764362 data_rate = 1866
4949 23:21:18.767253 CKR = 1
4950 23:21:18.771237 DQ_P2S_RATIO = 8
4951 23:21:18.774021 ===================================
4952 23:21:18.777639 CA_P2S_RATIO = 8
4953 23:21:18.780715 DQ_CA_OPEN = 0
4954 23:21:18.784119 DQ_SEMI_OPEN = 0
4955 23:21:18.784200 CA_SEMI_OPEN = 0
4956 23:21:18.787326 CA_FULL_RATE = 0
4957 23:21:18.790877 DQ_CKDIV4_EN = 1
4958 23:21:18.794351 CA_CKDIV4_EN = 1
4959 23:21:18.797358 CA_PREDIV_EN = 0
4960 23:21:18.801021 PH8_DLY = 0
4961 23:21:18.801104 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4962 23:21:18.804286 DQ_AAMCK_DIV = 4
4963 23:21:18.807253 CA_AAMCK_DIV = 4
4964 23:21:18.811005 CA_ADMCK_DIV = 4
4965 23:21:18.814363 DQ_TRACK_CA_EN = 0
4966 23:21:18.817326 CA_PICK = 933
4967 23:21:18.817408 CA_MCKIO = 933
4968 23:21:18.820868 MCKIO_SEMI = 0
4969 23:21:18.824188 PLL_FREQ = 3732
4970 23:21:18.827283 DQ_UI_PI_RATIO = 32
4971 23:21:18.831399 CA_UI_PI_RATIO = 0
4972 23:21:18.834257 ===================================
4973 23:21:18.838307 ===================================
4974 23:21:18.840678 memory_type:LPDDR4
4975 23:21:18.840761 GP_NUM : 10
4976 23:21:18.844329 SRAM_EN : 1
4977 23:21:18.844410 MD32_EN : 0
4978 23:21:18.847624 ===================================
4979 23:21:18.851263 [ANA_INIT] >>>>>>>>>>>>>>
4980 23:21:18.854270 <<<<<< [CONFIGURE PHASE]: ANA_TX
4981 23:21:18.857889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4982 23:21:18.860960 ===================================
4983 23:21:18.864470 data_rate = 1866,PCW = 0X8f00
4984 23:21:18.867536 ===================================
4985 23:21:18.871201 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4986 23:21:18.874190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4987 23:21:18.881069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4988 23:21:18.884616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4989 23:21:18.887966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4990 23:21:18.890900 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4991 23:21:18.894151 [ANA_INIT] flow start
4992 23:21:18.897529 [ANA_INIT] PLL >>>>>>>>
4993 23:21:18.897612 [ANA_INIT] PLL <<<<<<<<
4994 23:21:18.900881 [ANA_INIT] MIDPI >>>>>>>>
4995 23:21:18.904199 [ANA_INIT] MIDPI <<<<<<<<
4996 23:21:18.907911 [ANA_INIT] DLL >>>>>>>>
4997 23:21:18.907993 [ANA_INIT] flow end
4998 23:21:18.910810 ============ LP4 DIFF to SE enter ============
4999 23:21:18.917528 ============ LP4 DIFF to SE exit ============
5000 23:21:18.917611 [ANA_INIT] <<<<<<<<<<<<<
5001 23:21:18.921219 [Flow] Enable top DCM control >>>>>
5002 23:21:18.924441 [Flow] Enable top DCM control <<<<<
5003 23:21:18.927478 Enable DLL master slave shuffle
5004 23:21:18.934197 ==============================================================
5005 23:21:18.934280 Gating Mode config
5006 23:21:18.941295 ==============================================================
5007 23:21:18.944500 Config description:
5008 23:21:18.950958 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5009 23:21:18.958098 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5010 23:21:18.964254 SELPH_MODE 0: By rank 1: By Phase
5011 23:21:18.971599 ==============================================================
5012 23:21:18.971683 GAT_TRACK_EN = 1
5013 23:21:18.974738 RX_GATING_MODE = 2
5014 23:21:18.978198 RX_GATING_TRACK_MODE = 2
5015 23:21:18.981597 SELPH_MODE = 1
5016 23:21:18.984621 PICG_EARLY_EN = 1
5017 23:21:18.988087 VALID_LAT_VALUE = 1
5018 23:21:18.994289 ==============================================================
5019 23:21:18.998214 Enter into Gating configuration >>>>
5020 23:21:19.000999 Exit from Gating configuration <<<<
5021 23:21:19.004351 Enter into DVFS_PRE_config >>>>>
5022 23:21:19.014476 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5023 23:21:19.017906 Exit from DVFS_PRE_config <<<<<
5024 23:21:19.021313 Enter into PICG configuration >>>>
5025 23:21:19.024799 Exit from PICG configuration <<<<
5026 23:21:19.024881 [RX_INPUT] configuration >>>>>
5027 23:21:19.027788 [RX_INPUT] configuration <<<<<
5028 23:21:19.034345 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5029 23:21:19.038159 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5030 23:21:19.044521 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5031 23:21:19.051289 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5032 23:21:19.057933 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5033 23:21:19.065532 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5034 23:21:19.068140 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5035 23:21:19.071422 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5036 23:21:19.078074 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5037 23:21:19.081587 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5038 23:21:19.084647 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5039 23:21:19.087834 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5040 23:21:19.091286 ===================================
5041 23:21:19.094750 LPDDR4 DRAM CONFIGURATION
5042 23:21:19.098015 ===================================
5043 23:21:19.101327 EX_ROW_EN[0] = 0x0
5044 23:21:19.101409 EX_ROW_EN[1] = 0x0
5045 23:21:19.104700 LP4Y_EN = 0x0
5046 23:21:19.104781 WORK_FSP = 0x0
5047 23:21:19.107892 WL = 0x3
5048 23:21:19.107974 RL = 0x3
5049 23:21:19.111345 BL = 0x2
5050 23:21:19.111428 RPST = 0x0
5051 23:21:19.115001 RD_PRE = 0x0
5052 23:21:19.115083 WR_PRE = 0x1
5053 23:21:19.117719 WR_PST = 0x0
5054 23:21:19.117801 DBI_WR = 0x0
5055 23:21:19.121684 DBI_RD = 0x0
5056 23:21:19.121766 OTF = 0x1
5057 23:21:19.124345 ===================================
5058 23:21:19.131386 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5059 23:21:19.134511 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5060 23:21:19.137812 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5061 23:21:19.141604 ===================================
5062 23:21:19.144712 LPDDR4 DRAM CONFIGURATION
5063 23:21:19.147984 ===================================
5064 23:21:19.151212 EX_ROW_EN[0] = 0x10
5065 23:21:19.151293 EX_ROW_EN[1] = 0x0
5066 23:21:19.154617 LP4Y_EN = 0x0
5067 23:21:19.154699 WORK_FSP = 0x0
5068 23:21:19.158037 WL = 0x3
5069 23:21:19.158118 RL = 0x3
5070 23:21:19.161648 BL = 0x2
5071 23:21:19.161729 RPST = 0x0
5072 23:21:19.165008 RD_PRE = 0x0
5073 23:21:19.165089 WR_PRE = 0x1
5074 23:21:19.168037 WR_PST = 0x0
5075 23:21:19.168119 DBI_WR = 0x0
5076 23:21:19.171127 DBI_RD = 0x0
5077 23:21:19.171208 OTF = 0x1
5078 23:21:19.174620 ===================================
5079 23:21:19.181481 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5080 23:21:19.185987 nWR fixed to 30
5081 23:21:19.189196 [ModeRegInit_LP4] CH0 RK0
5082 23:21:19.189278 [ModeRegInit_LP4] CH0 RK1
5083 23:21:19.192224 [ModeRegInit_LP4] CH1 RK0
5084 23:21:19.195995 [ModeRegInit_LP4] CH1 RK1
5085 23:21:19.196102 match AC timing 9
5086 23:21:19.202007 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5087 23:21:19.205283 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5088 23:21:19.209300 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5089 23:21:19.215458 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5090 23:21:19.218778 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5091 23:21:19.218860 ==
5092 23:21:19.222283 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 23:21:19.225523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 23:21:19.225605 ==
5095 23:21:19.232166 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5096 23:21:19.239124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5097 23:21:19.242291 [CA 0] Center 38 (8~69) winsize 62
5098 23:21:19.245400 [CA 1] Center 38 (8~68) winsize 61
5099 23:21:19.248713 [CA 2] Center 35 (5~66) winsize 62
5100 23:21:19.251996 [CA 3] Center 35 (4~66) winsize 63
5101 23:21:19.255164 [CA 4] Center 34 (4~64) winsize 61
5102 23:21:19.259125 [CA 5] Center 34 (4~64) winsize 61
5103 23:21:19.259207
5104 23:21:19.261887 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5105 23:21:19.261968
5106 23:21:19.265277 [CATrainingPosCal] consider 1 rank data
5107 23:21:19.268629 u2DelayCellTimex100 = 270/100 ps
5108 23:21:19.272094 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5109 23:21:19.275442 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5110 23:21:19.278535 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5111 23:21:19.282050 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5112 23:21:19.285700 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5113 23:21:19.288831 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5114 23:21:19.288914
5115 23:21:19.295040 CA PerBit enable=1, Macro0, CA PI delay=34
5116 23:21:19.295123
5117 23:21:19.298301 [CBTSetCACLKResult] CA Dly = 34
5118 23:21:19.298433 CS Dly: 6 (0~37)
5119 23:21:19.298514 ==
5120 23:21:19.301624 Dram Type= 6, Freq= 0, CH_0, rank 1
5121 23:21:19.305200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 23:21:19.305309 ==
5123 23:21:19.311832 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5124 23:21:19.319026 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5125 23:21:19.321864 [CA 0] Center 38 (8~69) winsize 62
5126 23:21:19.325365 [CA 1] Center 38 (7~69) winsize 63
5127 23:21:19.328667 [CA 2] Center 35 (5~66) winsize 62
5128 23:21:19.331788 [CA 3] Center 35 (5~66) winsize 62
5129 23:21:19.335889 [CA 4] Center 34 (4~64) winsize 61
5130 23:21:19.338535 [CA 5] Center 33 (3~64) winsize 62
5131 23:21:19.338618
5132 23:21:19.342131 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5133 23:21:19.342221
5134 23:21:19.345351 [CATrainingPosCal] consider 2 rank data
5135 23:21:19.348469 u2DelayCellTimex100 = 270/100 ps
5136 23:21:19.352201 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5137 23:21:19.355655 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5138 23:21:19.358605 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5139 23:21:19.362116 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5140 23:21:19.365532 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5141 23:21:19.368499 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5142 23:21:19.368591
5143 23:21:19.375252 CA PerBit enable=1, Macro0, CA PI delay=34
5144 23:21:19.375352
5145 23:21:19.375420 [CBTSetCACLKResult] CA Dly = 34
5146 23:21:19.378763 CS Dly: 7 (0~39)
5147 23:21:19.378877
5148 23:21:19.382347 ----->DramcWriteLeveling(PI) begin...
5149 23:21:19.382485 ==
5150 23:21:19.385666 Dram Type= 6, Freq= 0, CH_0, rank 0
5151 23:21:19.388705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 23:21:19.388813 ==
5153 23:21:19.391928 Write leveling (Byte 0): 31 => 31
5154 23:21:19.395959 Write leveling (Byte 1): 30 => 30
5155 23:21:19.399167 DramcWriteLeveling(PI) end<-----
5156 23:21:19.399278
5157 23:21:19.399376 ==
5158 23:21:19.402100 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 23:21:19.405527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 23:21:19.409099 ==
5161 23:21:19.409194 [Gating] SW mode calibration
5162 23:21:19.415528 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5163 23:21:19.422031 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5164 23:21:19.425564 0 14 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5165 23:21:19.432004 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
5166 23:21:19.436007 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 23:21:19.438631 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 23:21:19.446053 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 23:21:19.449558 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 23:21:19.452266 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 23:21:19.458743 0 14 28 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5172 23:21:19.462371 0 15 0 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (0 0)
5173 23:21:19.465710 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 23:21:19.472667 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 23:21:19.475697 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 23:21:19.479358 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 23:21:19.482136 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 23:21:19.488851 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 23:21:19.492607 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 23:21:19.495751 1 0 0 | B1->B0 | 3231 4646 | 1 0 | (0 0) (0 0)
5181 23:21:19.502660 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 23:21:19.505777 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 23:21:19.509502 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 23:21:19.515838 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 23:21:19.519288 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 23:21:19.522254 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 23:21:19.529348 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5188 23:21:19.532478 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5189 23:21:19.535687 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 23:21:19.542390 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 23:21:19.545927 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 23:21:19.549038 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 23:21:19.555986 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 23:21:19.558963 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 23:21:19.562345 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 23:21:19.565652 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 23:21:19.572342 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 23:21:19.575822 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 23:21:19.579608 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 23:21:19.585806 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 23:21:19.589188 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 23:21:19.592768 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 23:21:19.599169 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 23:21:19.603225 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5205 23:21:19.606182 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 23:21:19.609552 Total UI for P1: 0, mck2ui 16
5207 23:21:19.612494 best dqsien dly found for B0: ( 1, 3, 0)
5208 23:21:19.616181 Total UI for P1: 0, mck2ui 16
5209 23:21:19.619514 best dqsien dly found for B1: ( 1, 3, 0)
5210 23:21:19.622985 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5211 23:21:19.625840 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5212 23:21:19.626216
5213 23:21:19.628944 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5214 23:21:19.635951 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5215 23:21:19.636366 [Gating] SW calibration Done
5216 23:21:19.636664 ==
5217 23:21:19.639599 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 23:21:19.645790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 23:21:19.646161 ==
5220 23:21:19.646614 RX Vref Scan: 0
5221 23:21:19.646980
5222 23:21:19.649281 RX Vref 0 -> 0, step: 1
5223 23:21:19.649716
5224 23:21:19.652590 RX Delay -80 -> 252, step: 8
5225 23:21:19.656159 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5226 23:21:19.659319 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5227 23:21:19.662773 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5228 23:21:19.665573 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5229 23:21:19.668902 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5230 23:21:19.676069 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5231 23:21:19.679215 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5232 23:21:19.682449 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5233 23:21:19.685758 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5234 23:21:19.689067 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5235 23:21:19.696404 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5236 23:21:19.699156 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5237 23:21:19.702871 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5238 23:21:19.705787 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5239 23:21:19.709701 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5240 23:21:19.712383 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5241 23:21:19.716134 ==
5242 23:21:19.716583 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 23:21:19.722594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 23:21:19.722970 ==
5245 23:21:19.723253 DQS Delay:
5246 23:21:19.725910 DQS0 = 0, DQS1 = 0
5247 23:21:19.726283 DQM Delay:
5248 23:21:19.729171 DQM0 = 98, DQM1 = 87
5249 23:21:19.729647 DQ Delay:
5250 23:21:19.732694 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5251 23:21:19.736191 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5252 23:21:19.739150 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5253 23:21:19.742686 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5254 23:21:19.743044
5255 23:21:19.743351
5256 23:21:19.743617 ==
5257 23:21:19.746081 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 23:21:19.749193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 23:21:19.749575 ==
5260 23:21:19.749864
5261 23:21:19.750163
5262 23:21:19.752523 TX Vref Scan disable
5263 23:21:19.756325 == TX Byte 0 ==
5264 23:21:19.759745 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5265 23:21:19.762899 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5266 23:21:19.765918 == TX Byte 1 ==
5267 23:21:19.769299 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5268 23:21:19.772656 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5269 23:21:19.773093 ==
5270 23:21:19.776164 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 23:21:19.779158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 23:21:19.782609 ==
5273 23:21:19.782976
5274 23:21:19.783350
5275 23:21:19.783636 TX Vref Scan disable
5276 23:21:19.786442 == TX Byte 0 ==
5277 23:21:19.789807 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5278 23:21:19.796595 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5279 23:21:19.797080 == TX Byte 1 ==
5280 23:21:19.799287 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5281 23:21:19.805916 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5282 23:21:19.806330
5283 23:21:19.806682 [DATLAT]
5284 23:21:19.807050 Freq=933, CH0 RK0
5285 23:21:19.807321
5286 23:21:19.809312 DATLAT Default: 0xd
5287 23:21:19.809746 0, 0xFFFF, sum = 0
5288 23:21:19.812959 1, 0xFFFF, sum = 0
5289 23:21:19.813337 2, 0xFFFF, sum = 0
5290 23:21:19.816536 3, 0xFFFF, sum = 0
5291 23:21:19.816959 4, 0xFFFF, sum = 0
5292 23:21:19.819733 5, 0xFFFF, sum = 0
5293 23:21:19.823067 6, 0xFFFF, sum = 0
5294 23:21:19.823510 7, 0xFFFF, sum = 0
5295 23:21:19.826245 8, 0xFFFF, sum = 0
5296 23:21:19.826660 9, 0xFFFF, sum = 0
5297 23:21:19.829949 10, 0x0, sum = 1
5298 23:21:19.830507 11, 0x0, sum = 2
5299 23:21:19.830820 12, 0x0, sum = 3
5300 23:21:19.832781 13, 0x0, sum = 4
5301 23:21:19.833174 best_step = 11
5302 23:21:19.833457
5303 23:21:19.833753 ==
5304 23:21:19.836298 Dram Type= 6, Freq= 0, CH_0, rank 0
5305 23:21:19.842860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 23:21:19.843389 ==
5307 23:21:19.843729 RX Vref Scan: 1
5308 23:21:19.843997
5309 23:21:19.846550 RX Vref 0 -> 0, step: 1
5310 23:21:19.847007
5311 23:21:19.849392 RX Delay -61 -> 252, step: 4
5312 23:21:19.849749
5313 23:21:19.852966 Set Vref, RX VrefLevel [Byte0]: 53
5314 23:21:19.856293 [Byte1]: 51
5315 23:21:19.856649
5316 23:21:19.859843 Final RX Vref Byte 0 = 53 to rank0
5317 23:21:19.862880 Final RX Vref Byte 1 = 51 to rank0
5318 23:21:19.866343 Final RX Vref Byte 0 = 53 to rank1
5319 23:21:19.869219 Final RX Vref Byte 1 = 51 to rank1==
5320 23:21:19.873215 Dram Type= 6, Freq= 0, CH_0, rank 0
5321 23:21:19.876476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 23:21:19.877025 ==
5323 23:21:19.879965 DQS Delay:
5324 23:21:19.880345 DQS0 = 0, DQS1 = 0
5325 23:21:19.880741 DQM Delay:
5326 23:21:19.883137 DQM0 = 97, DQM1 = 88
5327 23:21:19.883525 DQ Delay:
5328 23:21:19.886264 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =96
5329 23:21:19.889712 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =104
5330 23:21:19.892962 DQ8 =78, DQ9 =74, DQ10 =90, DQ11 =80
5331 23:21:19.896008 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5332 23:21:19.896413
5333 23:21:19.896839
5334 23:21:19.906336 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5335 23:21:19.909313 CH0 RK0: MR19=504, MR18=12FD
5336 23:21:19.912856 CH0_RK0: MR19=0x504, MR18=0x12FD, DQSOSC=416, MR23=63, INC=62, DEC=41
5337 23:21:19.916280
5338 23:21:19.919912 ----->DramcWriteLeveling(PI) begin...
5339 23:21:19.920309 ==
5340 23:21:19.922944 Dram Type= 6, Freq= 0, CH_0, rank 1
5341 23:21:19.926300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 23:21:19.926709 ==
5343 23:21:19.929756 Write leveling (Byte 0): 28 => 28
5344 23:21:19.933266 Write leveling (Byte 1): 27 => 27
5345 23:21:19.936168 DramcWriteLeveling(PI) end<-----
5346 23:21:19.936724
5347 23:21:19.937069 ==
5348 23:21:19.940208 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 23:21:19.943175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 23:21:19.943544 ==
5351 23:21:19.946075 [Gating] SW mode calibration
5352 23:21:19.953216 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5353 23:21:19.956818 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5354 23:21:19.963183 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5355 23:21:19.966655 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5356 23:21:19.970136 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 23:21:19.976342 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 23:21:19.979964 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 23:21:19.983674 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 23:21:19.989698 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 23:21:19.993202 0 14 28 | B1->B0 | 3333 2929 | 1 0 | (1 0) (0 0)
5362 23:21:19.996601 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)
5363 23:21:20.002984 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5364 23:21:20.006540 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 23:21:20.010004 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 23:21:20.016698 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 23:21:20.019798 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 23:21:20.023142 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 23:21:20.030188 0 15 28 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
5370 23:21:20.033192 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
5371 23:21:20.036567 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 23:21:20.040061 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 23:21:20.046852 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 23:21:20.050071 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 23:21:20.053407 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 23:21:20.059951 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 23:21:20.062817 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5378 23:21:20.066488 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5379 23:21:20.073081 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 23:21:20.076385 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 23:21:20.079851 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 23:21:20.086646 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 23:21:20.089896 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 23:21:20.093708 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 23:21:20.099965 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 23:21:20.103572 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 23:21:20.106566 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 23:21:20.113226 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 23:21:20.116573 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 23:21:20.120233 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 23:21:20.126839 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 23:21:20.130785 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5393 23:21:20.133232 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5394 23:21:20.136394 Total UI for P1: 0, mck2ui 16
5395 23:21:20.140180 best dqsien dly found for B0: ( 1, 2, 24)
5396 23:21:20.143069 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5397 23:21:20.150350 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5398 23:21:20.152986 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 23:21:20.156522 Total UI for P1: 0, mck2ui 16
5400 23:21:20.160008 best dqsien dly found for B1: ( 1, 2, 30)
5401 23:21:20.163242 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5402 23:21:20.166614 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5403 23:21:20.166972
5404 23:21:20.170169 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5405 23:21:20.173174 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5406 23:21:20.176677 [Gating] SW calibration Done
5407 23:21:20.177046 ==
5408 23:21:20.179592 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 23:21:20.186700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 23:21:20.187142 ==
5411 23:21:20.187435 RX Vref Scan: 0
5412 23:21:20.187796
5413 23:21:20.189960 RX Vref 0 -> 0, step: 1
5414 23:21:20.190462
5415 23:21:20.193092 RX Delay -80 -> 252, step: 8
5416 23:21:20.196542 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5417 23:21:20.200145 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5418 23:21:20.203004 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5419 23:21:20.206627 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5420 23:21:20.209762 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5421 23:21:20.216612 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5422 23:21:20.220225 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5423 23:21:20.223211 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5424 23:21:20.226307 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5425 23:21:20.229913 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5426 23:21:20.233116 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5427 23:21:20.240258 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5428 23:21:20.243443 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5429 23:21:20.246628 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5430 23:21:20.249578 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5431 23:21:20.252921 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5432 23:21:20.253285 ==
5433 23:21:20.256492 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 23:21:20.263023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 23:21:20.263475 ==
5436 23:21:20.263776 DQS Delay:
5437 23:21:20.267138 DQS0 = 0, DQS1 = 0
5438 23:21:20.267507 DQM Delay:
5439 23:21:20.267856 DQM0 = 98, DQM1 = 89
5440 23:21:20.270250 DQ Delay:
5441 23:21:20.273047 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5442 23:21:20.276664 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5443 23:21:20.279465 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =83
5444 23:21:20.282996 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5445 23:21:20.283438
5446 23:21:20.283734
5447 23:21:20.284066 ==
5448 23:21:20.286528 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 23:21:20.289449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 23:21:20.289895 ==
5451 23:21:20.290197
5452 23:21:20.290606
5453 23:21:20.292898 TX Vref Scan disable
5454 23:21:20.293267 == TX Byte 0 ==
5455 23:21:20.299660 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5456 23:21:20.303170 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5457 23:21:20.303586 == TX Byte 1 ==
5458 23:21:20.309778 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5459 23:21:20.313422 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5460 23:21:20.313825 ==
5461 23:21:20.316741 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 23:21:20.319524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 23:21:20.319927 ==
5464 23:21:20.320285
5465 23:21:20.320562
5466 23:21:20.322931 TX Vref Scan disable
5467 23:21:20.326718 == TX Byte 0 ==
5468 23:21:20.329897 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5469 23:21:20.333290 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5470 23:21:20.336497 == TX Byte 1 ==
5471 23:21:20.340083 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5472 23:21:20.342776 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5473 23:21:20.343286
5474 23:21:20.346127 [DATLAT]
5475 23:21:20.346614 Freq=933, CH0 RK1
5476 23:21:20.346907
5477 23:21:20.349617 DATLAT Default: 0xb
5478 23:21:20.349972 0, 0xFFFF, sum = 0
5479 23:21:20.352912 1, 0xFFFF, sum = 0
5480 23:21:20.353303 2, 0xFFFF, sum = 0
5481 23:21:20.356638 3, 0xFFFF, sum = 0
5482 23:21:20.357216 4, 0xFFFF, sum = 0
5483 23:21:20.360175 5, 0xFFFF, sum = 0
5484 23:21:20.360638 6, 0xFFFF, sum = 0
5485 23:21:20.362710 7, 0xFFFF, sum = 0
5486 23:21:20.363095 8, 0xFFFF, sum = 0
5487 23:21:20.366352 9, 0xFFFF, sum = 0
5488 23:21:20.366950 10, 0x0, sum = 1
5489 23:21:20.369950 11, 0x0, sum = 2
5490 23:21:20.370430 12, 0x0, sum = 3
5491 23:21:20.373494 13, 0x0, sum = 4
5492 23:21:20.373855 best_step = 11
5493 23:21:20.374137
5494 23:21:20.374422 ==
5495 23:21:20.376157 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 23:21:20.383266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 23:21:20.383629 ==
5498 23:21:20.383915 RX Vref Scan: 0
5499 23:21:20.384192
5500 23:21:20.386392 RX Vref 0 -> 0, step: 1
5501 23:21:20.386901
5502 23:21:20.389684 RX Delay -61 -> 252, step: 4
5503 23:21:20.393323 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5504 23:21:20.396283 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5505 23:21:20.402872 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5506 23:21:20.406233 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5507 23:21:20.409629 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5508 23:21:20.413004 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5509 23:21:20.416493 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5510 23:21:20.419706 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5511 23:21:20.426550 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5512 23:21:20.429717 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5513 23:21:20.433576 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5514 23:21:20.436505 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5515 23:21:20.439906 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5516 23:21:20.442886 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5517 23:21:20.449927 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5518 23:21:20.453054 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5519 23:21:20.453570 ==
5520 23:21:20.456637 Dram Type= 6, Freq= 0, CH_0, rank 1
5521 23:21:20.459868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 23:21:20.460292 ==
5523 23:21:20.462751 DQS Delay:
5524 23:21:20.463168 DQS0 = 0, DQS1 = 0
5525 23:21:20.463498 DQM Delay:
5526 23:21:20.467007 DQM0 = 95, DQM1 = 87
5527 23:21:20.467527 DQ Delay:
5528 23:21:20.469924 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5529 23:21:20.472927 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =102
5530 23:21:20.476164 DQ8 =82, DQ9 =80, DQ10 =88, DQ11 =80
5531 23:21:20.479348 DQ12 =90, DQ13 =92, DQ14 =96, DQ15 =94
5532 23:21:20.479832
5533 23:21:20.480168
5534 23:21:20.489596 [DQSOSCAuto] RK1, (LSB)MR18= 0x1806, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5535 23:21:20.490098 CH0 RK1: MR19=505, MR18=1806
5536 23:21:20.496076 CH0_RK1: MR19=0x505, MR18=0x1806, DQSOSC=414, MR23=63, INC=63, DEC=42
5537 23:21:20.499840 [RxdqsGatingPostProcess] freq 933
5538 23:21:20.506218 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5539 23:21:20.509934 best DQS0 dly(2T, 0.5T) = (0, 11)
5540 23:21:20.513041 best DQS1 dly(2T, 0.5T) = (0, 11)
5541 23:21:20.516537 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5542 23:21:20.519341 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5543 23:21:20.522658 best DQS0 dly(2T, 0.5T) = (0, 10)
5544 23:21:20.526436 best DQS1 dly(2T, 0.5T) = (0, 10)
5545 23:21:20.526971 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5546 23:21:20.529993 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5547 23:21:20.532995 Pre-setting of DQS Precalculation
5548 23:21:20.539168 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5549 23:21:20.539675 ==
5550 23:21:20.543257 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 23:21:20.546559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 23:21:20.547079 ==
5553 23:21:20.552645 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5554 23:21:20.560024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5555 23:21:20.562723 [CA 0] Center 37 (7~67) winsize 61
5556 23:21:20.566588 [CA 1] Center 37 (7~67) winsize 61
5557 23:21:20.569525 [CA 2] Center 34 (4~65) winsize 62
5558 23:21:20.572444 [CA 3] Center 33 (2~64) winsize 63
5559 23:21:20.575680 [CA 4] Center 34 (3~65) winsize 63
5560 23:21:20.579401 [CA 5] Center 33 (3~64) winsize 62
5561 23:21:20.579909
5562 23:21:20.582513 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5563 23:21:20.582931
5564 23:21:20.586137 [CATrainingPosCal] consider 1 rank data
5565 23:21:20.589662 u2DelayCellTimex100 = 270/100 ps
5566 23:21:20.592617 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5567 23:21:20.596510 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5568 23:21:20.599217 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5569 23:21:20.602857 CA3 delay=33 (2~64),Diff = 0 PI (0 cell)
5570 23:21:20.606640 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5571 23:21:20.609654 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5572 23:21:20.610175
5573 23:21:20.612794 CA PerBit enable=1, Macro0, CA PI delay=33
5574 23:21:20.616296
5575 23:21:20.616813 [CBTSetCACLKResult] CA Dly = 33
5576 23:21:20.619499 CS Dly: 4 (0~35)
5577 23:21:20.620022 ==
5578 23:21:20.622601 Dram Type= 6, Freq= 0, CH_1, rank 1
5579 23:21:20.625973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 23:21:20.626430 ==
5581 23:21:20.633135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5582 23:21:20.639691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5583 23:21:20.642829 [CA 0] Center 36 (6~67) winsize 62
5584 23:21:20.646240 [CA 1] Center 37 (7~67) winsize 61
5585 23:21:20.649927 [CA 2] Center 34 (4~65) winsize 62
5586 23:21:20.652789 [CA 3] Center 33 (3~64) winsize 62
5587 23:21:20.655888 [CA 4] Center 34 (4~65) winsize 62
5588 23:21:20.659375 [CA 5] Center 33 (2~64) winsize 63
5589 23:21:20.659885
5590 23:21:20.663124 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5591 23:21:20.663639
5592 23:21:20.665817 [CATrainingPosCal] consider 2 rank data
5593 23:21:20.669439 u2DelayCellTimex100 = 270/100 ps
5594 23:21:20.672487 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5595 23:21:20.675860 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5596 23:21:20.679077 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5597 23:21:20.682645 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5598 23:21:20.686292 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5599 23:21:20.689221 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5600 23:21:20.689638
5601 23:21:20.692679 CA PerBit enable=1, Macro0, CA PI delay=33
5602 23:21:20.696063
5603 23:21:20.696573 [CBTSetCACLKResult] CA Dly = 33
5604 23:21:20.699303 CS Dly: 5 (0~38)
5605 23:21:20.699813
5606 23:21:20.702322 ----->DramcWriteLeveling(PI) begin...
5607 23:21:20.702793 ==
5608 23:21:20.705861 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 23:21:20.708920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 23:21:20.709344 ==
5611 23:21:20.712476 Write leveling (Byte 0): 24 => 24
5612 23:21:20.715723 Write leveling (Byte 1): 30 => 30
5613 23:21:20.719346 DramcWriteLeveling(PI) end<-----
5614 23:21:20.719823
5615 23:21:20.720200 ==
5616 23:21:20.722625 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 23:21:20.725607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 23:21:20.726030 ==
5619 23:21:20.729274 [Gating] SW mode calibration
5620 23:21:20.735829 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5621 23:21:20.742103 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5622 23:21:20.745565 0 14 0 | B1->B0 | 3131 3232 | 1 1 | (1 1) (1 1)
5623 23:21:20.752113 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 23:21:20.755814 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 23:21:20.759204 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 23:21:20.762152 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 23:21:20.769068 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 23:21:20.772390 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
5629 23:21:20.775853 0 14 28 | B1->B0 | 3232 3030 | 1 1 | (1 0) (1 0)
5630 23:21:20.782695 0 15 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5631 23:21:20.785773 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 23:21:20.789246 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 23:21:20.795542 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 23:21:20.799276 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 23:21:20.802953 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5636 23:21:20.809398 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 23:21:20.812706 0 15 28 | B1->B0 | 2929 2929 | 0 0 | (0 0) (0 0)
5638 23:21:20.815833 1 0 0 | B1->B0 | 4545 4141 | 0 0 | (0 0) (0 0)
5639 23:21:20.822081 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 23:21:20.825600 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 23:21:20.829108 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 23:21:20.835399 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 23:21:20.838751 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 23:21:20.842344 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 23:21:20.849136 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5646 23:21:20.851814 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5647 23:21:20.855623 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 23:21:20.862410 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 23:21:20.865647 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 23:21:20.868856 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 23:21:20.872350 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 23:21:20.878758 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 23:21:20.882366 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 23:21:20.885540 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 23:21:20.892816 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 23:21:20.895961 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 23:21:20.899400 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 23:21:20.905897 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 23:21:20.909129 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 23:21:20.912350 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 23:21:20.919534 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5662 23:21:20.922574 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 23:21:20.926561 Total UI for P1: 0, mck2ui 16
5664 23:21:20.929437 best dqsien dly found for B0: ( 1, 2, 28)
5665 23:21:20.932480 Total UI for P1: 0, mck2ui 16
5666 23:21:20.936094 best dqsien dly found for B1: ( 1, 2, 28)
5667 23:21:20.939501 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5668 23:21:20.943317 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5669 23:21:20.943829
5670 23:21:20.946788 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5671 23:21:20.949853 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5672 23:21:20.953143 [Gating] SW calibration Done
5673 23:21:20.953559 ==
5674 23:21:20.956414 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 23:21:20.959637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 23:21:20.960161 ==
5677 23:21:20.962921 RX Vref Scan: 0
5678 23:21:20.963500
5679 23:21:20.966272 RX Vref 0 -> 0, step: 1
5680 23:21:20.966823
5681 23:21:20.967158 RX Delay -80 -> 252, step: 8
5682 23:21:20.972826 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5683 23:21:20.976039 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5684 23:21:20.979922 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5685 23:21:20.983019 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5686 23:21:20.986319 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5687 23:21:20.989687 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5688 23:21:20.996941 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5689 23:21:20.999744 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5690 23:21:21.003113 iDelay=200, Bit 8, Center 75 (-24 ~ 175) 200
5691 23:21:21.006146 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5692 23:21:21.009117 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5693 23:21:21.012588 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5694 23:21:21.019364 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5695 23:21:21.022750 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5696 23:21:21.025961 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5697 23:21:21.029471 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5698 23:21:21.030300 ==
5699 23:21:21.033016 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 23:21:21.036112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 23:21:21.039201 ==
5702 23:21:21.039627 DQS Delay:
5703 23:21:21.040314 DQS0 = 0, DQS1 = 0
5704 23:21:21.042735 DQM Delay:
5705 23:21:21.043291 DQM0 = 95, DQM1 = 88
5706 23:21:21.045710 DQ Delay:
5707 23:21:21.046248 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5708 23:21:21.049224 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5709 23:21:21.052934 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =87
5710 23:21:21.056065 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5711 23:21:21.059594
5712 23:21:21.060033
5713 23:21:21.060366 ==
5714 23:21:21.062347 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 23:21:21.065897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 23:21:21.066629 ==
5717 23:21:21.067251
5718 23:21:21.067703
5719 23:21:21.069382 TX Vref Scan disable
5720 23:21:21.069799 == TX Byte 0 ==
5721 23:21:21.075899 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5722 23:21:21.079453 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5723 23:21:21.079936 == TX Byte 1 ==
5724 23:21:21.085768 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5725 23:21:21.089240 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5726 23:21:21.089661 ==
5727 23:21:21.092546 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 23:21:21.095768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 23:21:21.096189 ==
5730 23:21:21.096520
5731 23:21:21.096824
5732 23:21:21.099407 TX Vref Scan disable
5733 23:21:21.102339 == TX Byte 0 ==
5734 23:21:21.105682 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5735 23:21:21.109602 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5736 23:21:21.112220 == TX Byte 1 ==
5737 23:21:21.115514 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5738 23:21:21.119108 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5739 23:21:21.119529
5740 23:21:21.122624 [DATLAT]
5741 23:21:21.123043 Freq=933, CH1 RK0
5742 23:21:21.123524
5743 23:21:21.125637 DATLAT Default: 0xd
5744 23:21:21.126373 0, 0xFFFF, sum = 0
5745 23:21:21.129177 1, 0xFFFF, sum = 0
5746 23:21:21.129607 2, 0xFFFF, sum = 0
5747 23:21:21.132173 3, 0xFFFF, sum = 0
5748 23:21:21.132602 4, 0xFFFF, sum = 0
5749 23:21:21.135657 5, 0xFFFF, sum = 0
5750 23:21:21.136270 6, 0xFFFF, sum = 0
5751 23:21:21.139182 7, 0xFFFF, sum = 0
5752 23:21:21.139612 8, 0xFFFF, sum = 0
5753 23:21:21.142286 9, 0xFFFF, sum = 0
5754 23:21:21.142760 10, 0x0, sum = 1
5755 23:21:21.145978 11, 0x0, sum = 2
5756 23:21:21.146449 12, 0x0, sum = 3
5757 23:21:21.148994 13, 0x0, sum = 4
5758 23:21:21.149423 best_step = 11
5759 23:21:21.149752
5760 23:21:21.150093 ==
5761 23:21:21.152502 Dram Type= 6, Freq= 0, CH_1, rank 0
5762 23:21:21.155574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 23:21:21.158939 ==
5764 23:21:21.159363 RX Vref Scan: 1
5765 23:21:21.159814
5766 23:21:21.162162 RX Vref 0 -> 0, step: 1
5767 23:21:21.162651
5768 23:21:21.165864 RX Delay -69 -> 252, step: 4
5769 23:21:21.166283
5770 23:21:21.168879 Set Vref, RX VrefLevel [Byte0]: 54
5771 23:21:21.172391 [Byte1]: 54
5772 23:21:21.172697
5773 23:21:21.175821 Final RX Vref Byte 0 = 54 to rank0
5774 23:21:21.179175 Final RX Vref Byte 1 = 54 to rank0
5775 23:21:21.182127 Final RX Vref Byte 0 = 54 to rank1
5776 23:21:21.185969 Final RX Vref Byte 1 = 54 to rank1==
5777 23:21:21.189258 Dram Type= 6, Freq= 0, CH_1, rank 0
5778 23:21:21.192693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5779 23:21:21.193031 ==
5780 23:21:21.193343 DQS Delay:
5781 23:21:21.195895 DQS0 = 0, DQS1 = 0
5782 23:21:21.196201 DQM Delay:
5783 23:21:21.198830 DQM0 = 98, DQM1 = 90
5784 23:21:21.199132 DQ Delay:
5785 23:21:21.202682 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =96
5786 23:21:21.205953 DQ4 =96, DQ5 =108, DQ6 =110, DQ7 =94
5787 23:21:21.209012 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =86
5788 23:21:21.212289 DQ12 =98, DQ13 =96, DQ14 =98, DQ15 =96
5789 23:21:21.212730
5790 23:21:21.213226
5791 23:21:21.222197 [DQSOSCAuto] RK0, (LSB)MR18= 0x10ee, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5792 23:21:21.222858 CH1 RK0: MR19=504, MR18=10EE
5793 23:21:21.229553 CH1_RK0: MR19=0x504, MR18=0x10EE, DQSOSC=416, MR23=63, INC=62, DEC=41
5794 23:21:21.230172
5795 23:21:21.232595 ----->DramcWriteLeveling(PI) begin...
5796 23:21:21.233026 ==
5797 23:21:21.236045 Dram Type= 6, Freq= 0, CH_1, rank 1
5798 23:21:21.242495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 23:21:21.242984 ==
5800 23:21:21.246074 Write leveling (Byte 0): 27 => 27
5801 23:21:21.246580 Write leveling (Byte 1): 27 => 27
5802 23:21:21.249210 DramcWriteLeveling(PI) end<-----
5803 23:21:21.249595
5804 23:21:21.252628 ==
5805 23:21:21.253018 Dram Type= 6, Freq= 0, CH_1, rank 1
5806 23:21:21.259373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5807 23:21:21.259764 ==
5808 23:21:21.263085 [Gating] SW mode calibration
5809 23:21:21.269720 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5810 23:21:21.272746 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5811 23:21:21.279823 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 23:21:21.282468 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 23:21:21.285762 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 23:21:21.292470 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 23:21:21.295503 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 23:21:21.299015 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 23:21:21.302294 0 14 24 | B1->B0 | 3030 2727 | 0 0 | (0 0) (0 1)
5818 23:21:21.308858 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
5819 23:21:21.312728 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 23:21:21.315850 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 23:21:21.322749 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 23:21:21.325761 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 23:21:21.329079 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 23:21:21.335838 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5825 23:21:21.339391 0 15 24 | B1->B0 | 2626 3030 | 0 1 | (0 0) (0 0)
5826 23:21:21.342488 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5827 23:21:21.350218 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 23:21:21.352441 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 23:21:21.355673 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 23:21:21.362610 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 23:21:21.366313 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 23:21:21.369347 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 23:21:21.376107 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5834 23:21:21.379659 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 23:21:21.382729 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 23:21:21.386338 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 23:21:21.393783 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 23:21:21.396058 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 23:21:21.399377 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 23:21:21.406277 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 23:21:21.409313 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 23:21:21.412558 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 23:21:21.419259 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 23:21:21.422378 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 23:21:21.426008 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 23:21:21.432649 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 23:21:21.436261 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 23:21:21.439236 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 23:21:21.445925 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5850 23:21:21.449041 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5851 23:21:21.452842 Total UI for P1: 0, mck2ui 16
5852 23:21:21.456421 best dqsien dly found for B0: ( 1, 2, 24)
5853 23:21:21.459358 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 23:21:21.462816 Total UI for P1: 0, mck2ui 16
5855 23:21:21.466241 best dqsien dly found for B1: ( 1, 2, 26)
5856 23:21:21.469356 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5857 23:21:21.472938 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5858 23:21:21.473021
5859 23:21:21.475978 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5860 23:21:21.480033 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5861 23:21:21.483000 [Gating] SW calibration Done
5862 23:21:21.483087 ==
5863 23:21:21.486430 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 23:21:21.493028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 23:21:21.493165 ==
5866 23:21:21.493275 RX Vref Scan: 0
5867 23:21:21.493376
5868 23:21:21.496096 RX Vref 0 -> 0, step: 1
5869 23:21:21.496242
5870 23:21:21.499840 RX Delay -80 -> 252, step: 8
5871 23:21:21.503011 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5872 23:21:21.506478 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5873 23:21:21.509502 iDelay=200, Bit 2, Center 83 (-16 ~ 183) 200
5874 23:21:21.512824 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5875 23:21:21.516402 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5876 23:21:21.522915 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5877 23:21:21.526129 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5878 23:21:21.529803 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5879 23:21:21.533361 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5880 23:21:21.536414 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5881 23:21:21.539767 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5882 23:21:21.546199 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5883 23:21:21.549765 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5884 23:21:21.552887 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5885 23:21:21.556791 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5886 23:21:21.559675 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5887 23:21:21.559774 ==
5888 23:21:21.563100 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 23:21:21.569773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 23:21:21.569869 ==
5891 23:21:21.569943 DQS Delay:
5892 23:21:21.573346 DQS0 = 0, DQS1 = 0
5893 23:21:21.573439 DQM Delay:
5894 23:21:21.573513 DQM0 = 93, DQM1 = 88
5895 23:21:21.576176 DQ Delay:
5896 23:21:21.580057 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =95
5897 23:21:21.583279 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5898 23:21:21.586209 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5899 23:21:21.589925 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5900 23:21:21.590059
5901 23:21:21.590165
5902 23:21:21.590263 ==
5903 23:21:21.592883 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 23:21:21.596416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 23:21:21.596553 ==
5906 23:21:21.596660
5907 23:21:21.596757
5908 23:21:21.599871 TX Vref Scan disable
5909 23:21:21.603267 == TX Byte 0 ==
5910 23:21:21.607092 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5911 23:21:21.609814 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5912 23:21:21.609950 == TX Byte 1 ==
5913 23:21:21.616717 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5914 23:21:21.620103 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5915 23:21:21.620468 ==
5916 23:21:21.623496 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 23:21:21.627069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 23:21:21.627459 ==
5919 23:21:21.627760
5920 23:21:21.629936
5921 23:21:21.630318 TX Vref Scan disable
5922 23:21:21.633432 == TX Byte 0 ==
5923 23:21:21.636791 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5924 23:21:21.639793 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5925 23:21:21.643670 == TX Byte 1 ==
5926 23:21:21.647015 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5927 23:21:21.649950 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5928 23:21:21.652982
5929 23:21:21.653381 [DATLAT]
5930 23:21:21.653802 Freq=933, CH1 RK1
5931 23:21:21.654101
5932 23:21:21.656644 DATLAT Default: 0xb
5933 23:21:21.657037 0, 0xFFFF, sum = 0
5934 23:21:21.660059 1, 0xFFFF, sum = 0
5935 23:21:21.660384 2, 0xFFFF, sum = 0
5936 23:21:21.663089 3, 0xFFFF, sum = 0
5937 23:21:21.663394 4, 0xFFFF, sum = 0
5938 23:21:21.666462 5, 0xFFFF, sum = 0
5939 23:21:21.666738 6, 0xFFFF, sum = 0
5940 23:21:21.669767 7, 0xFFFF, sum = 0
5941 23:21:21.669971 8, 0xFFFF, sum = 0
5942 23:21:21.673426 9, 0xFFFF, sum = 0
5943 23:21:21.673605 10, 0x0, sum = 1
5944 23:21:21.676341 11, 0x0, sum = 2
5945 23:21:21.676491 12, 0x0, sum = 3
5946 23:21:21.679890 13, 0x0, sum = 4
5947 23:21:21.680019 best_step = 11
5948 23:21:21.680119
5949 23:21:21.680210 ==
5950 23:21:21.683373 Dram Type= 6, Freq= 0, CH_1, rank 1
5951 23:21:21.690140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5952 23:21:21.690246 ==
5953 23:21:21.690326 RX Vref Scan: 0
5954 23:21:21.690407
5955 23:21:21.693066 RX Vref 0 -> 0, step: 1
5956 23:21:21.693166
5957 23:21:21.696540 RX Delay -61 -> 252, step: 4
5958 23:21:21.699503 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5959 23:21:21.703154 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5960 23:21:21.709428 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5961 23:21:21.713449 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5962 23:21:21.716485 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5963 23:21:21.719495 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5964 23:21:21.723053 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5965 23:21:21.726412 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5966 23:21:21.732890 iDelay=199, Bit 8, Center 82 (-9 ~ 174) 184
5967 23:21:21.736533 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5968 23:21:21.739539 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5969 23:21:21.743522 iDelay=199, Bit 11, Center 84 (-9 ~ 178) 188
5970 23:21:21.746640 iDelay=199, Bit 12, Center 96 (7 ~ 186) 180
5971 23:21:21.749786 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5972 23:21:21.757121 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5973 23:21:21.760011 iDelay=199, Bit 15, Center 100 (11 ~ 190) 180
5974 23:21:21.760113 ==
5975 23:21:21.763281 Dram Type= 6, Freq= 0, CH_1, rank 1
5976 23:21:21.766536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5977 23:21:21.766655 ==
5978 23:21:21.769641 DQS Delay:
5979 23:21:21.769759 DQS0 = 0, DQS1 = 0
5980 23:21:21.769865 DQM Delay:
5981 23:21:21.773484 DQM0 = 94, DQM1 = 91
5982 23:21:21.773602 DQ Delay:
5983 23:21:21.776593 DQ0 =96, DQ1 =90, DQ2 =84, DQ3 =92
5984 23:21:21.780411 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =90
5985 23:21:21.782985 DQ8 =82, DQ9 =80, DQ10 =90, DQ11 =84
5986 23:21:21.786186 DQ12 =96, DQ13 =100, DQ14 =100, DQ15 =100
5987 23:21:21.786332
5988 23:21:21.786494
5989 23:21:21.796347 [DQSOSCAuto] RK1, (LSB)MR18= 0x912, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 419 ps
5990 23:21:21.799940 CH1 RK1: MR19=505, MR18=912
5991 23:21:21.803121 CH1_RK1: MR19=0x505, MR18=0x912, DQSOSC=416, MR23=63, INC=62, DEC=41
5992 23:21:21.806429 [RxdqsGatingPostProcess] freq 933
5993 23:21:21.813337 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5994 23:21:21.816313 best DQS0 dly(2T, 0.5T) = (0, 10)
5995 23:21:21.819778 best DQS1 dly(2T, 0.5T) = (0, 10)
5996 23:21:21.823338 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5997 23:21:21.826294 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5998 23:21:21.830131 best DQS0 dly(2T, 0.5T) = (0, 10)
5999 23:21:21.833110 best DQS1 dly(2T, 0.5T) = (0, 10)
6000 23:21:21.836545 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6001 23:21:21.840210 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6002 23:21:21.840594 Pre-setting of DQS Precalculation
6003 23:21:21.846125 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6004 23:21:21.853277 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6005 23:21:21.859507 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6006 23:21:21.860176
6007 23:21:21.860787
6008 23:21:21.863008 [Calibration Summary] 1866 Mbps
6009 23:21:21.866610 CH 0, Rank 0
6010 23:21:21.867037 SW Impedance : PASS
6011 23:21:21.869825 DUTY Scan : NO K
6012 23:21:21.873152 ZQ Calibration : PASS
6013 23:21:21.873728 Jitter Meter : NO K
6014 23:21:21.876204 CBT Training : PASS
6015 23:21:21.879722 Write leveling : PASS
6016 23:21:21.880283 RX DQS gating : PASS
6017 23:21:21.882615 RX DQ/DQS(RDDQC) : PASS
6018 23:21:21.886143 TX DQ/DQS : PASS
6019 23:21:21.886798 RX DATLAT : PASS
6020 23:21:21.889908 RX DQ/DQS(Engine): PASS
6021 23:21:21.892999 TX OE : NO K
6022 23:21:21.893546 All Pass.
6023 23:21:21.893890
6024 23:21:21.894247 CH 0, Rank 1
6025 23:21:21.896348 SW Impedance : PASS
6026 23:21:21.899525 DUTY Scan : NO K
6027 23:21:21.899941 ZQ Calibration : PASS
6028 23:21:21.902743 Jitter Meter : NO K
6029 23:21:21.903288 CBT Training : PASS
6030 23:21:21.906088 Write leveling : PASS
6031 23:21:21.909129 RX DQS gating : PASS
6032 23:21:21.909559 RX DQ/DQS(RDDQC) : PASS
6033 23:21:21.913246 TX DQ/DQS : PASS
6034 23:21:21.915925 RX DATLAT : PASS
6035 23:21:21.916343 RX DQ/DQS(Engine): PASS
6036 23:21:21.919468 TX OE : NO K
6037 23:21:21.919891 All Pass.
6038 23:21:21.920231
6039 23:21:21.922521 CH 1, Rank 0
6040 23:21:21.922948 SW Impedance : PASS
6041 23:21:21.925713 DUTY Scan : NO K
6042 23:21:21.929427 ZQ Calibration : PASS
6043 23:21:21.929848 Jitter Meter : NO K
6044 23:21:21.932978 CBT Training : PASS
6045 23:21:21.936307 Write leveling : PASS
6046 23:21:21.936730 RX DQS gating : PASS
6047 23:21:21.939235 RX DQ/DQS(RDDQC) : PASS
6048 23:21:21.942756 TX DQ/DQS : PASS
6049 23:21:21.943188 RX DATLAT : PASS
6050 23:21:21.946152 RX DQ/DQS(Engine): PASS
6051 23:21:21.946490 TX OE : NO K
6052 23:21:21.949102 All Pass.
6053 23:21:21.949398
6054 23:21:21.949642 CH 1, Rank 1
6055 23:21:21.952527 SW Impedance : PASS
6056 23:21:21.952752 DUTY Scan : NO K
6057 23:21:21.955556 ZQ Calibration : PASS
6058 23:21:21.959127 Jitter Meter : NO K
6059 23:21:21.959308 CBT Training : PASS
6060 23:21:21.962061 Write leveling : PASS
6061 23:21:21.965571 RX DQS gating : PASS
6062 23:21:21.965701 RX DQ/DQS(RDDQC) : PASS
6063 23:21:21.969390 TX DQ/DQS : PASS
6064 23:21:21.972441 RX DATLAT : PASS
6065 23:21:21.972555 RX DQ/DQS(Engine): PASS
6066 23:21:21.975559 TX OE : NO K
6067 23:21:21.975662 All Pass.
6068 23:21:21.975742
6069 23:21:21.978958 DramC Write-DBI off
6070 23:21:21.982207 PER_BANK_REFRESH: Hybrid Mode
6071 23:21:21.982332 TX_TRACKING: ON
6072 23:21:21.992795 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6073 23:21:21.995495 [FAST_K] Save calibration result to emmc
6074 23:21:21.998966 dramc_set_vcore_voltage set vcore to 650000
6075 23:21:22.002475 Read voltage for 400, 6
6076 23:21:22.002561 Vio18 = 0
6077 23:21:22.002627 Vcore = 650000
6078 23:21:22.006050 Vdram = 0
6079 23:21:22.006138 Vddq = 0
6080 23:21:22.006205 Vmddr = 0
6081 23:21:22.012417 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6082 23:21:22.015641 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6083 23:21:22.018860 MEM_TYPE=3, freq_sel=20
6084 23:21:22.022846 sv_algorithm_assistance_LP4_800
6085 23:21:22.025397 ============ PULL DRAM RESETB DOWN ============
6086 23:21:22.029004 ========== PULL DRAM RESETB DOWN end =========
6087 23:21:22.036170 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6088 23:21:22.039049 ===================================
6089 23:21:22.039134 LPDDR4 DRAM CONFIGURATION
6090 23:21:22.042300 ===================================
6091 23:21:22.046123 EX_ROW_EN[0] = 0x0
6092 23:21:22.049230 EX_ROW_EN[1] = 0x0
6093 23:21:22.049659 LP4Y_EN = 0x0
6094 23:21:22.052614 WORK_FSP = 0x0
6095 23:21:22.052996 WL = 0x2
6096 23:21:22.055687 RL = 0x2
6097 23:21:22.056070 BL = 0x2
6098 23:21:22.059434 RPST = 0x0
6099 23:21:22.059818 RD_PRE = 0x0
6100 23:21:22.062816 WR_PRE = 0x1
6101 23:21:22.063201 WR_PST = 0x0
6102 23:21:22.066535 DBI_WR = 0x0
6103 23:21:22.066969 DBI_RD = 0x0
6104 23:21:22.069376 OTF = 0x1
6105 23:21:22.072779 ===================================
6106 23:21:22.075919 ===================================
6107 23:21:22.076303 ANA top config
6108 23:21:22.079186 ===================================
6109 23:21:22.082474 DLL_ASYNC_EN = 0
6110 23:21:22.086142 ALL_SLAVE_EN = 1
6111 23:21:22.086587 NEW_RANK_MODE = 1
6112 23:21:22.089620 DLL_IDLE_MODE = 1
6113 23:21:22.092866 LP45_APHY_COMB_EN = 1
6114 23:21:22.096139 TX_ODT_DIS = 1
6115 23:21:22.096540 NEW_8X_MODE = 1
6116 23:21:22.099495 ===================================
6117 23:21:22.102478 ===================================
6118 23:21:22.106022 data_rate = 800
6119 23:21:22.109317 CKR = 1
6120 23:21:22.112857 DQ_P2S_RATIO = 4
6121 23:21:22.116320 ===================================
6122 23:21:22.119675 CA_P2S_RATIO = 4
6123 23:21:22.122897 DQ_CA_OPEN = 0
6124 23:21:22.123304 DQ_SEMI_OPEN = 1
6125 23:21:22.125912 CA_SEMI_OPEN = 1
6126 23:21:22.129626 CA_FULL_RATE = 0
6127 23:21:22.132501 DQ_CKDIV4_EN = 0
6128 23:21:22.135906 CA_CKDIV4_EN = 1
6129 23:21:22.139208 CA_PREDIV_EN = 0
6130 23:21:22.139611 PH8_DLY = 0
6131 23:21:22.142666 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6132 23:21:22.146143 DQ_AAMCK_DIV = 0
6133 23:21:22.149318 CA_AAMCK_DIV = 0
6134 23:21:22.153729 CA_ADMCK_DIV = 4
6135 23:21:22.156416 DQ_TRACK_CA_EN = 0
6136 23:21:22.157049 CA_PICK = 800
6137 23:21:22.159158 CA_MCKIO = 400
6138 23:21:22.162884 MCKIO_SEMI = 400
6139 23:21:22.166506 PLL_FREQ = 3016
6140 23:21:22.169475 DQ_UI_PI_RATIO = 32
6141 23:21:22.172824 CA_UI_PI_RATIO = 32
6142 23:21:22.175823 ===================================
6143 23:21:22.179378 ===================================
6144 23:21:22.182298 memory_type:LPDDR4
6145 23:21:22.182617 GP_NUM : 10
6146 23:21:22.185652 SRAM_EN : 1
6147 23:21:22.185874 MD32_EN : 0
6148 23:21:22.189344 ===================================
6149 23:21:22.192491 [ANA_INIT] >>>>>>>>>>>>>>
6150 23:21:22.196192 <<<<<< [CONFIGURE PHASE]: ANA_TX
6151 23:21:22.199481 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6152 23:21:22.202528 ===================================
6153 23:21:22.205801 data_rate = 800,PCW = 0X7400
6154 23:21:22.209376 ===================================
6155 23:21:22.212948 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6156 23:21:22.215566 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6157 23:21:22.229083 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6158 23:21:22.232419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6159 23:21:22.236025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6160 23:21:22.238905 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6161 23:21:22.242434 [ANA_INIT] flow start
6162 23:21:22.245503 [ANA_INIT] PLL >>>>>>>>
6163 23:21:22.245605 [ANA_INIT] PLL <<<<<<<<
6164 23:21:22.249404 [ANA_INIT] MIDPI >>>>>>>>
6165 23:21:22.252433 [ANA_INIT] MIDPI <<<<<<<<
6166 23:21:22.252516 [ANA_INIT] DLL >>>>>>>>
6167 23:21:22.255762 [ANA_INIT] flow end
6168 23:21:22.259190 ============ LP4 DIFF to SE enter ============
6169 23:21:22.262335 ============ LP4 DIFF to SE exit ============
6170 23:21:22.266687 [ANA_INIT] <<<<<<<<<<<<<
6171 23:21:22.269268 [Flow] Enable top DCM control >>>>>
6172 23:21:22.272439 [Flow] Enable top DCM control <<<<<
6173 23:21:22.276056 Enable DLL master slave shuffle
6174 23:21:22.282786 ==============================================================
6175 23:21:22.283224 Gating Mode config
6176 23:21:22.289495 ==============================================================
6177 23:21:22.289911 Config description:
6178 23:21:22.299532 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6179 23:21:22.305879 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6180 23:21:22.312598 SELPH_MODE 0: By rank 1: By Phase
6181 23:21:22.315792 ==============================================================
6182 23:21:22.319294 GAT_TRACK_EN = 0
6183 23:21:22.322491 RX_GATING_MODE = 2
6184 23:21:22.325911 RX_GATING_TRACK_MODE = 2
6185 23:21:22.329438 SELPH_MODE = 1
6186 23:21:22.332905 PICG_EARLY_EN = 1
6187 23:21:22.336243 VALID_LAT_VALUE = 1
6188 23:21:22.339073 ==============================================================
6189 23:21:22.342655 Enter into Gating configuration >>>>
6190 23:21:22.345485 Exit from Gating configuration <<<<
6191 23:21:22.348992 Enter into DVFS_PRE_config >>>>>
6192 23:21:22.362347 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6193 23:21:22.365927 Exit from DVFS_PRE_config <<<<<
6194 23:21:22.369440 Enter into PICG configuration >>>>
6195 23:21:22.372603 Exit from PICG configuration <<<<
6196 23:21:22.372784 [RX_INPUT] configuration >>>>>
6197 23:21:22.375710 [RX_INPUT] configuration <<<<<
6198 23:21:22.382270 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6199 23:21:22.385507 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6200 23:21:22.392774 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6201 23:21:22.399457 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6202 23:21:22.405792 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6203 23:21:22.412144 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6204 23:21:22.415861 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6205 23:21:22.419463 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6206 23:21:22.422159 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6207 23:21:22.428979 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6208 23:21:22.432632 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6209 23:21:22.435783 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6210 23:21:22.439384 ===================================
6211 23:21:22.442242 LPDDR4 DRAM CONFIGURATION
6212 23:21:22.445635 ===================================
6213 23:21:22.449095 EX_ROW_EN[0] = 0x0
6214 23:21:22.449215 EX_ROW_EN[1] = 0x0
6215 23:21:22.452400 LP4Y_EN = 0x0
6216 23:21:22.452502 WORK_FSP = 0x0
6217 23:21:22.455734 WL = 0x2
6218 23:21:22.455829 RL = 0x2
6219 23:21:22.459313 BL = 0x2
6220 23:21:22.459406 RPST = 0x0
6221 23:21:22.462586 RD_PRE = 0x0
6222 23:21:22.462667 WR_PRE = 0x1
6223 23:21:22.465519 WR_PST = 0x0
6224 23:21:22.465624 DBI_WR = 0x0
6225 23:21:22.469133 DBI_RD = 0x0
6226 23:21:22.469213 OTF = 0x1
6227 23:21:22.472440 ===================================
6228 23:21:22.475951 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6229 23:21:22.482073 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6230 23:21:22.486130 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6231 23:21:22.488866 ===================================
6232 23:21:22.492463 LPDDR4 DRAM CONFIGURATION
6233 23:21:22.495803 ===================================
6234 23:21:22.495958 EX_ROW_EN[0] = 0x10
6235 23:21:22.499143 EX_ROW_EN[1] = 0x0
6236 23:21:22.499225 LP4Y_EN = 0x0
6237 23:21:22.502143 WORK_FSP = 0x0
6238 23:21:22.505873 WL = 0x2
6239 23:21:22.505946 RL = 0x2
6240 23:21:22.508737 BL = 0x2
6241 23:21:22.508823 RPST = 0x0
6242 23:21:22.512318 RD_PRE = 0x0
6243 23:21:22.512398 WR_PRE = 0x1
6244 23:21:22.515688 WR_PST = 0x0
6245 23:21:22.515775 DBI_WR = 0x0
6246 23:21:22.519069 DBI_RD = 0x0
6247 23:21:22.519178 OTF = 0x1
6248 23:21:22.522303 ===================================
6249 23:21:22.528744 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6250 23:21:22.532883 nWR fixed to 30
6251 23:21:22.536183 [ModeRegInit_LP4] CH0 RK0
6252 23:21:22.536320 [ModeRegInit_LP4] CH0 RK1
6253 23:21:22.539259 [ModeRegInit_LP4] CH1 RK0
6254 23:21:22.542576 [ModeRegInit_LP4] CH1 RK1
6255 23:21:22.542698 match AC timing 19
6256 23:21:22.549429 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6257 23:21:22.553086 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6258 23:21:22.556686 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6259 23:21:22.563351 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6260 23:21:22.566157 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6261 23:21:22.566568 ==
6262 23:21:22.569750 Dram Type= 6, Freq= 0, CH_0, rank 0
6263 23:21:22.573596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 23:21:22.573893 ==
6265 23:21:22.579509 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6266 23:21:22.586889 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6267 23:21:22.589650 [CA 0] Center 36 (8~64) winsize 57
6268 23:21:22.592975 [CA 1] Center 36 (8~64) winsize 57
6269 23:21:22.593366 [CA 2] Center 36 (8~64) winsize 57
6270 23:21:22.596528 [CA 3] Center 36 (8~64) winsize 57
6271 23:21:22.599902 [CA 4] Center 36 (8~64) winsize 57
6272 23:21:22.603211 [CA 5] Center 36 (8~64) winsize 57
6273 23:21:22.603744
6274 23:21:22.606369 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6275 23:21:22.606781
6276 23:21:22.613420 [CATrainingPosCal] consider 1 rank data
6277 23:21:22.613802 u2DelayCellTimex100 = 270/100 ps
6278 23:21:22.619762 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 23:21:22.623237 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 23:21:22.627154 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 23:21:22.629939 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 23:21:22.633664 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 23:21:22.636399 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 23:21:22.636844
6285 23:21:22.640138 CA PerBit enable=1, Macro0, CA PI delay=36
6286 23:21:22.640524
6287 23:21:22.643249 [CBTSetCACLKResult] CA Dly = 36
6288 23:21:22.643633 CS Dly: 1 (0~32)
6289 23:21:22.646474 ==
6290 23:21:22.649925 Dram Type= 6, Freq= 0, CH_0, rank 1
6291 23:21:22.653654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 23:21:22.654043 ==
6293 23:21:22.656708 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6294 23:21:22.663816 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6295 23:21:22.666611 [CA 0] Center 36 (8~64) winsize 57
6296 23:21:22.670145 [CA 1] Center 36 (8~64) winsize 57
6297 23:21:22.673450 [CA 2] Center 36 (8~64) winsize 57
6298 23:21:22.676536 [CA 3] Center 36 (8~64) winsize 57
6299 23:21:22.680085 [CA 4] Center 36 (8~64) winsize 57
6300 23:21:22.683152 [CA 5] Center 36 (8~64) winsize 57
6301 23:21:22.683421
6302 23:21:22.686802 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6303 23:21:22.686990
6304 23:21:22.690138 [CATrainingPosCal] consider 2 rank data
6305 23:21:22.693196 u2DelayCellTimex100 = 270/100 ps
6306 23:21:22.696265 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 23:21:22.699745 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 23:21:22.703077 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 23:21:22.706710 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 23:21:22.710265 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 23:21:22.716318 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 23:21:22.716424
6313 23:21:22.719914 CA PerBit enable=1, Macro0, CA PI delay=36
6314 23:21:22.720003
6315 23:21:22.722813 [CBTSetCACLKResult] CA Dly = 36
6316 23:21:22.722899 CS Dly: 1 (0~32)
6317 23:21:22.722964
6318 23:21:22.726280 ----->DramcWriteLeveling(PI) begin...
6319 23:21:22.726367 ==
6320 23:21:22.729716 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 23:21:22.732837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 23:21:22.736255 ==
6323 23:21:22.736376 Write leveling (Byte 0): 40 => 8
6324 23:21:22.740201 Write leveling (Byte 1): 32 => 0
6325 23:21:22.743299 DramcWriteLeveling(PI) end<-----
6326 23:21:22.743628
6327 23:21:22.743891 ==
6328 23:21:22.746384 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 23:21:22.753084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 23:21:22.753516 ==
6331 23:21:22.753884 [Gating] SW mode calibration
6332 23:21:22.763294 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6333 23:21:22.766814 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6334 23:21:22.769783 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6335 23:21:22.776357 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6336 23:21:22.779726 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6337 23:21:22.783328 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6338 23:21:22.789851 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6339 23:21:22.792727 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 23:21:22.796176 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 23:21:22.803503 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 23:21:22.806456 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6343 23:21:22.809496 Total UI for P1: 0, mck2ui 16
6344 23:21:22.812820 best dqsien dly found for B0: ( 0, 14, 24)
6345 23:21:22.816206 Total UI for P1: 0, mck2ui 16
6346 23:21:22.819742 best dqsien dly found for B1: ( 0, 14, 24)
6347 23:21:22.823230 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6348 23:21:22.826132 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6349 23:21:22.826497
6350 23:21:22.829753 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6351 23:21:22.833014 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6352 23:21:22.836681 [Gating] SW calibration Done
6353 23:21:22.837145 ==
6354 23:21:22.839682 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 23:21:22.842884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 23:21:22.846118 ==
6357 23:21:22.846571 RX Vref Scan: 0
6358 23:21:22.846843
6359 23:21:22.849467 RX Vref 0 -> 0, step: 1
6360 23:21:22.849842
6361 23:21:22.853494 RX Delay -410 -> 252, step: 16
6362 23:21:22.856222 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6363 23:21:22.859619 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6364 23:21:22.863175 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6365 23:21:22.869345 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6366 23:21:22.873096 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6367 23:21:22.876383 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6368 23:21:22.879756 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6369 23:21:22.886329 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6370 23:21:22.889973 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6371 23:21:22.893007 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6372 23:21:22.896518 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6373 23:21:22.902939 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6374 23:21:22.906031 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6375 23:21:22.909661 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6376 23:21:22.912533 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6377 23:21:22.919435 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6378 23:21:22.919552 ==
6379 23:21:22.922606 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 23:21:22.926337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 23:21:22.926494 ==
6382 23:21:22.926611 DQS Delay:
6383 23:21:22.929535 DQS0 = 35, DQS1 = 51
6384 23:21:22.929617 DQM Delay:
6385 23:21:22.932819 DQM0 = 7, DQM1 = 10
6386 23:21:22.932902 DQ Delay:
6387 23:21:22.935929 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6388 23:21:22.939290 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6389 23:21:22.942934 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6390 23:21:22.946044 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6391 23:21:22.946127
6392 23:21:22.946194
6393 23:21:22.946254 ==
6394 23:21:22.949387 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 23:21:22.953005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 23:21:22.953089 ==
6397 23:21:22.953154
6398 23:21:22.953214
6399 23:21:22.956405 TX Vref Scan disable
6400 23:21:22.956487 == TX Byte 0 ==
6401 23:21:22.963201 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6402 23:21:22.966371 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6403 23:21:22.966583 == TX Byte 1 ==
6404 23:21:22.973078 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6405 23:21:22.976108 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6406 23:21:22.976205 ==
6407 23:21:22.979557 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 23:21:22.982733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 23:21:22.982837 ==
6410 23:21:22.982918
6411 23:21:22.982993
6412 23:21:22.986213 TX Vref Scan disable
6413 23:21:22.989378 == TX Byte 0 ==
6414 23:21:22.992847 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6415 23:21:22.996550 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6416 23:21:22.996633 == TX Byte 1 ==
6417 23:21:23.003063 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6418 23:21:23.006002 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6419 23:21:23.006097
6420 23:21:23.006171 [DATLAT]
6421 23:21:23.009462 Freq=400, CH0 RK0
6422 23:21:23.009557
6423 23:21:23.009679 DATLAT Default: 0xf
6424 23:21:23.013160 0, 0xFFFF, sum = 0
6425 23:21:23.013265 1, 0xFFFF, sum = 0
6426 23:21:23.016144 2, 0xFFFF, sum = 0
6427 23:21:23.019730 3, 0xFFFF, sum = 0
6428 23:21:23.019941 4, 0xFFFF, sum = 0
6429 23:21:23.023171 5, 0xFFFF, sum = 0
6430 23:21:23.023322 6, 0xFFFF, sum = 0
6431 23:21:23.026234 7, 0xFFFF, sum = 0
6432 23:21:23.026372 8, 0xFFFF, sum = 0
6433 23:21:23.029835 9, 0xFFFF, sum = 0
6434 23:21:23.029991 10, 0xFFFF, sum = 0
6435 23:21:23.032731 11, 0xFFFF, sum = 0
6436 23:21:23.032940 12, 0xFFFF, sum = 0
6437 23:21:23.036126 13, 0x0, sum = 1
6438 23:21:23.036369 14, 0x0, sum = 2
6439 23:21:23.039471 15, 0x0, sum = 3
6440 23:21:23.039671 16, 0x0, sum = 4
6441 23:21:23.039835 best_step = 14
6442 23:21:23.043502
6443 23:21:23.043704 ==
6444 23:21:23.046879 Dram Type= 6, Freq= 0, CH_0, rank 0
6445 23:21:23.050002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 23:21:23.050429 ==
6447 23:21:23.050705 RX Vref Scan: 1
6448 23:21:23.050935
6449 23:21:23.053514 RX Vref 0 -> 0, step: 1
6450 23:21:23.053957
6451 23:21:23.056349 RX Delay -343 -> 252, step: 8
6452 23:21:23.056742
6453 23:21:23.060084 Set Vref, RX VrefLevel [Byte0]: 53
6454 23:21:23.063351 [Byte1]: 51
6455 23:21:23.066956
6456 23:21:23.067345 Final RX Vref Byte 0 = 53 to rank0
6457 23:21:23.070064 Final RX Vref Byte 1 = 51 to rank0
6458 23:21:23.073332 Final RX Vref Byte 0 = 53 to rank1
6459 23:21:23.076798 Final RX Vref Byte 1 = 51 to rank1==
6460 23:21:23.080163 Dram Type= 6, Freq= 0, CH_0, rank 0
6461 23:21:23.086724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 23:21:23.087133 ==
6463 23:21:23.087482 DQS Delay:
6464 23:21:23.089941 DQS0 = 44, DQS1 = 60
6465 23:21:23.090263 DQM Delay:
6466 23:21:23.090582 DQM0 = 11, DQM1 = 14
6467 23:21:23.093637 DQ Delay:
6468 23:21:23.096539 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6469 23:21:23.096758 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6470 23:21:23.100181 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6471 23:21:23.103590 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6472 23:21:23.103764
6473 23:21:23.103899
6474 23:21:23.113896 [DQSOSCAuto] RK0, (LSB)MR18= 0x8655, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6475 23:21:23.116578 CH0 RK0: MR19=C0C, MR18=8655
6476 23:21:23.123205 CH0_RK0: MR19=0xC0C, MR18=0x8655, DQSOSC=393, MR23=63, INC=382, DEC=254
6477 23:21:23.123321 ==
6478 23:21:23.126783 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 23:21:23.130158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 23:21:23.130247 ==
6481 23:21:23.133208 [Gating] SW mode calibration
6482 23:21:23.140046 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6483 23:21:23.143651 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6484 23:21:23.150052 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6485 23:21:23.153550 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 23:21:23.156623 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6487 23:21:23.163620 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 23:21:23.166555 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 23:21:23.170257 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 23:21:23.176700 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 23:21:23.179756 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 23:21:23.183890 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6493 23:21:23.186556 Total UI for P1: 0, mck2ui 16
6494 23:21:23.189821 best dqsien dly found for B0: ( 0, 14, 24)
6495 23:21:23.193449 Total UI for P1: 0, mck2ui 16
6496 23:21:23.196720 best dqsien dly found for B1: ( 0, 14, 24)
6497 23:21:23.200160 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6498 23:21:23.203522 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6499 23:21:23.203948
6500 23:21:23.210263 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6501 23:21:23.213917 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6502 23:21:23.214535 [Gating] SW calibration Done
6503 23:21:23.216863 ==
6504 23:21:23.220403 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 23:21:23.223854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 23:21:23.224288 ==
6507 23:21:23.224639 RX Vref Scan: 0
6508 23:21:23.224863
6509 23:21:23.226836 RX Vref 0 -> 0, step: 1
6510 23:21:23.227140
6511 23:21:23.230260 RX Delay -410 -> 252, step: 16
6512 23:21:23.233715 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6513 23:21:23.236695 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6514 23:21:23.243600 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6515 23:21:23.246877 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6516 23:21:23.250160 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6517 23:21:23.253814 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6518 23:21:23.260256 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6519 23:21:23.263362 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6520 23:21:23.266689 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6521 23:21:23.269967 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6522 23:21:23.276590 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6523 23:21:23.279869 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6524 23:21:23.283231 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6525 23:21:23.286670 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6526 23:21:23.293827 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6527 23:21:23.296560 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6528 23:21:23.296672 ==
6529 23:21:23.299814 Dram Type= 6, Freq= 0, CH_0, rank 1
6530 23:21:23.303484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6531 23:21:23.303582 ==
6532 23:21:23.306951 DQS Delay:
6533 23:21:23.307039 DQS0 = 43, DQS1 = 51
6534 23:21:23.310628 DQM Delay:
6535 23:21:23.310712 DQM0 = 11, DQM1 = 10
6536 23:21:23.310798 DQ Delay:
6537 23:21:23.313271 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6538 23:21:23.317182 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6539 23:21:23.320128 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6540 23:21:23.323886 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6541 23:21:23.323970
6542 23:21:23.324035
6543 23:21:23.324095 ==
6544 23:21:23.326630 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 23:21:23.330494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 23:21:23.330827 ==
6547 23:21:23.334151
6548 23:21:23.334523
6549 23:21:23.334793 TX Vref Scan disable
6550 23:21:23.337085 == TX Byte 0 ==
6551 23:21:23.340517 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6552 23:21:23.344092 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6553 23:21:23.347525 == TX Byte 1 ==
6554 23:21:23.350582 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6555 23:21:23.353827 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6556 23:21:23.354159 ==
6557 23:21:23.357318 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 23:21:23.360312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 23:21:23.360642 ==
6560 23:21:23.363818
6561 23:21:23.364144
6562 23:21:23.364402 TX Vref Scan disable
6563 23:21:23.367537 == TX Byte 0 ==
6564 23:21:23.370749 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6565 23:21:23.373737 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6566 23:21:23.377367 == TX Byte 1 ==
6567 23:21:23.380912 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6568 23:21:23.383687 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6569 23:21:23.384015
6570 23:21:23.384361 [DATLAT]
6571 23:21:23.387118 Freq=400, CH0 RK1
6572 23:21:23.387561
6573 23:21:23.387831 DATLAT Default: 0xe
6574 23:21:23.390479 0, 0xFFFF, sum = 0
6575 23:21:23.393498 1, 0xFFFF, sum = 0
6576 23:21:23.393833 2, 0xFFFF, sum = 0
6577 23:21:23.397049 3, 0xFFFF, sum = 0
6578 23:21:23.397440 4, 0xFFFF, sum = 0
6579 23:21:23.400261 5, 0xFFFF, sum = 0
6580 23:21:23.400661 6, 0xFFFF, sum = 0
6581 23:21:23.403956 7, 0xFFFF, sum = 0
6582 23:21:23.404296 8, 0xFFFF, sum = 0
6583 23:21:23.406957 9, 0xFFFF, sum = 0
6584 23:21:23.407364 10, 0xFFFF, sum = 0
6585 23:21:23.410378 11, 0xFFFF, sum = 0
6586 23:21:23.410839 12, 0xFFFF, sum = 0
6587 23:21:23.413849 13, 0x0, sum = 1
6588 23:21:23.414183 14, 0x0, sum = 2
6589 23:21:23.416878 15, 0x0, sum = 3
6590 23:21:23.417213 16, 0x0, sum = 4
6591 23:21:23.420297 best_step = 14
6592 23:21:23.420628
6593 23:21:23.420886 ==
6594 23:21:23.423699 Dram Type= 6, Freq= 0, CH_0, rank 1
6595 23:21:23.427023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 23:21:23.427357 ==
6597 23:21:23.427618 RX Vref Scan: 0
6598 23:21:23.430571
6599 23:21:23.430898 RX Vref 0 -> 0, step: 1
6600 23:21:23.431159
6601 23:21:23.433348 RX Delay -343 -> 252, step: 8
6602 23:21:23.441226 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6603 23:21:23.444568 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6604 23:21:23.447645 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6605 23:21:23.451075 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6606 23:21:23.457549 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6607 23:21:23.461158 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6608 23:21:23.464580 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6609 23:21:23.467750 iDelay=217, Bit 7, Center -24 (-263 ~ 216) 480
6610 23:21:23.474675 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6611 23:21:23.478037 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6612 23:21:23.480967 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6613 23:21:23.484264 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6614 23:21:23.490696 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6615 23:21:23.494100 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6616 23:21:23.497585 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6617 23:21:23.504204 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6618 23:21:23.504332 ==
6619 23:21:23.507785 Dram Type= 6, Freq= 0, CH_0, rank 1
6620 23:21:23.510497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 23:21:23.510594 ==
6622 23:21:23.510671 DQS Delay:
6623 23:21:23.513973 DQS0 = 48, DQS1 = 60
6624 23:21:23.514069 DQM Delay:
6625 23:21:23.517513 DQM0 = 12, DQM1 = 13
6626 23:21:23.517600 DQ Delay:
6627 23:21:23.520852 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6628 23:21:23.524213 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6629 23:21:23.527320 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6630 23:21:23.530891 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6631 23:21:23.530976
6632 23:21:23.531041
6633 23:21:23.537417 [DQSOSCAuto] RK1, (LSB)MR18= 0x8e61, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 392 ps
6634 23:21:23.540468 CH0 RK1: MR19=C0C, MR18=8E61
6635 23:21:23.547493 CH0_RK1: MR19=0xC0C, MR18=0x8E61, DQSOSC=392, MR23=63, INC=384, DEC=256
6636 23:21:23.550758 [RxdqsGatingPostProcess] freq 400
6637 23:21:23.554242 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6638 23:21:23.557626 best DQS0 dly(2T, 0.5T) = (0, 10)
6639 23:21:23.560866 best DQS1 dly(2T, 0.5T) = (0, 10)
6640 23:21:23.564010 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6641 23:21:23.567611 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6642 23:21:23.571203 best DQS0 dly(2T, 0.5T) = (0, 10)
6643 23:21:23.574679 best DQS1 dly(2T, 0.5T) = (0, 10)
6644 23:21:23.577800 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6645 23:21:23.581151 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6646 23:21:23.584195 Pre-setting of DQS Precalculation
6647 23:21:23.587590 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6648 23:21:23.587759 ==
6649 23:21:23.590933 Dram Type= 6, Freq= 0, CH_1, rank 0
6650 23:21:23.597490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 23:21:23.597614 ==
6652 23:21:23.601039 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6653 23:21:23.607886 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6654 23:21:23.611117 [CA 0] Center 36 (8~64) winsize 57
6655 23:21:23.614125 [CA 1] Center 36 (8~64) winsize 57
6656 23:21:23.617829 [CA 2] Center 36 (8~64) winsize 57
6657 23:21:23.621125 [CA 3] Center 36 (8~64) winsize 57
6658 23:21:23.624397 [CA 4] Center 36 (8~64) winsize 57
6659 23:21:23.628042 [CA 5] Center 36 (8~64) winsize 57
6660 23:21:23.628345
6661 23:21:23.630978 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6662 23:21:23.631403
6663 23:21:23.634685 [CATrainingPosCal] consider 1 rank data
6664 23:21:23.638181 u2DelayCellTimex100 = 270/100 ps
6665 23:21:23.641093 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 23:21:23.644626 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 23:21:23.648086 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 23:21:23.651609 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 23:21:23.655009 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 23:21:23.658445 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 23:21:23.658885
6672 23:21:23.664789 CA PerBit enable=1, Macro0, CA PI delay=36
6673 23:21:23.665228
6674 23:21:23.665568 [CBTSetCACLKResult] CA Dly = 36
6675 23:21:23.667917 CS Dly: 1 (0~32)
6676 23:21:23.668340 ==
6677 23:21:23.671743 Dram Type= 6, Freq= 0, CH_1, rank 1
6678 23:21:23.675274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 23:21:23.675706 ==
6680 23:21:23.681473 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6681 23:21:23.688009 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6682 23:21:23.691527 [CA 0] Center 36 (8~64) winsize 57
6683 23:21:23.694733 [CA 1] Center 36 (8~64) winsize 57
6684 23:21:23.698451 [CA 2] Center 36 (8~64) winsize 57
6685 23:21:23.698878 [CA 3] Center 36 (8~64) winsize 57
6686 23:21:23.701891 [CA 4] Center 36 (8~64) winsize 57
6687 23:21:23.705142 [CA 5] Center 36 (8~64) winsize 57
6688 23:21:23.705596
6689 23:21:23.708292 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6690 23:21:23.711463
6691 23:21:23.715019 [CATrainingPosCal] consider 2 rank data
6692 23:21:23.715552 u2DelayCellTimex100 = 270/100 ps
6693 23:21:23.722095 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 23:21:23.724549 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 23:21:23.727934 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 23:21:23.731509 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 23:21:23.735091 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 23:21:23.738140 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 23:21:23.738715
6700 23:21:23.741663 CA PerBit enable=1, Macro0, CA PI delay=36
6701 23:21:23.742183
6702 23:21:23.744988 [CBTSetCACLKResult] CA Dly = 36
6703 23:21:23.748387 CS Dly: 1 (0~32)
6704 23:21:23.749045
6705 23:21:23.751484 ----->DramcWriteLeveling(PI) begin...
6706 23:21:23.752079 ==
6707 23:21:23.754852 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 23:21:23.758482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 23:21:23.759055 ==
6710 23:21:23.761351 Write leveling (Byte 0): 40 => 8
6711 23:21:23.764782 Write leveling (Byte 1): 40 => 8
6712 23:21:23.768504 DramcWriteLeveling(PI) end<-----
6713 23:21:23.769105
6714 23:21:23.769609 ==
6715 23:21:23.771533 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 23:21:23.775114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 23:21:23.775670 ==
6718 23:21:23.778012 [Gating] SW mode calibration
6719 23:21:23.784665 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6720 23:21:23.791653 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6721 23:21:23.794958 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6722 23:21:23.798111 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6723 23:21:23.804768 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6724 23:21:23.807981 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6725 23:21:23.811614 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6726 23:21:23.814567 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 23:21:23.821384 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 23:21:23.824533 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 23:21:23.827952 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6730 23:21:23.831289 Total UI for P1: 0, mck2ui 16
6731 23:21:23.834940 best dqsien dly found for B0: ( 0, 14, 24)
6732 23:21:23.837892 Total UI for P1: 0, mck2ui 16
6733 23:21:23.841186 best dqsien dly found for B1: ( 0, 14, 24)
6734 23:21:23.844707 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6735 23:21:23.847873 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6736 23:21:23.847964
6737 23:21:23.855017 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6738 23:21:23.858462 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6739 23:21:23.861569 [Gating] SW calibration Done
6740 23:21:23.861761 ==
6741 23:21:23.864417 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 23:21:23.868045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 23:21:23.868236 ==
6744 23:21:23.868387 RX Vref Scan: 0
6745 23:21:23.868527
6746 23:21:23.871428 RX Vref 0 -> 0, step: 1
6747 23:21:23.871842
6748 23:21:23.875089 RX Delay -410 -> 252, step: 16
6749 23:21:23.878385 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6750 23:21:23.885183 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6751 23:21:23.888642 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6752 23:21:23.891605 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6753 23:21:23.894655 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6754 23:21:23.901318 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6755 23:21:23.904396 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6756 23:21:23.907806 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6757 23:21:23.911547 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6758 23:21:23.917824 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6759 23:21:23.921581 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6760 23:21:23.924662 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6761 23:21:23.927959 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6762 23:21:23.934970 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6763 23:21:23.937863 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6764 23:21:23.940970 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6765 23:21:23.941387 ==
6766 23:21:23.944362 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 23:21:23.947841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 23:21:23.951260 ==
6769 23:21:23.951675 DQS Delay:
6770 23:21:23.951998 DQS0 = 51, DQS1 = 59
6771 23:21:23.954278 DQM Delay:
6772 23:21:23.954726 DQM0 = 19, DQM1 = 16
6773 23:21:23.957575 DQ Delay:
6774 23:21:23.960925 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6775 23:21:23.961339 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6776 23:21:23.964598 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6777 23:21:23.968095 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6778 23:21:23.971044
6779 23:21:23.971454
6780 23:21:23.971780 ==
6781 23:21:23.974357 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 23:21:23.977964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 23:21:23.978388 ==
6784 23:21:23.978805
6785 23:21:23.979111
6786 23:21:23.981090 TX Vref Scan disable
6787 23:21:23.981502 == TX Byte 0 ==
6788 23:21:23.984388 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 23:21:23.990797 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 23:21:23.991239 == TX Byte 1 ==
6791 23:21:23.994000 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6792 23:21:24.001092 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6793 23:21:24.001644 ==
6794 23:21:24.004107 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 23:21:24.007651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 23:21:24.008074 ==
6797 23:21:24.008404
6798 23:21:24.008733
6799 23:21:24.010548 TX Vref Scan disable
6800 23:21:24.010966 == TX Byte 0 ==
6801 23:21:24.014304 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6802 23:21:24.020733 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6803 23:21:24.021149 == TX Byte 1 ==
6804 23:21:24.023955 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6805 23:21:24.030817 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6806 23:21:24.031306
6807 23:21:24.031632 [DATLAT]
6808 23:21:24.031936 Freq=400, CH1 RK0
6809 23:21:24.033973
6810 23:21:24.034387 DATLAT Default: 0xf
6811 23:21:24.037471 0, 0xFFFF, sum = 0
6812 23:21:24.037929 1, 0xFFFF, sum = 0
6813 23:21:24.040688 2, 0xFFFF, sum = 0
6814 23:21:24.041329 3, 0xFFFF, sum = 0
6815 23:21:24.044489 4, 0xFFFF, sum = 0
6816 23:21:24.044914 5, 0xFFFF, sum = 0
6817 23:21:24.047429 6, 0xFFFF, sum = 0
6818 23:21:24.047853 7, 0xFFFF, sum = 0
6819 23:21:24.050954 8, 0xFFFF, sum = 0
6820 23:21:24.051395 9, 0xFFFF, sum = 0
6821 23:21:24.053887 10, 0xFFFF, sum = 0
6822 23:21:24.054362 11, 0xFFFF, sum = 0
6823 23:21:24.057534 12, 0xFFFF, sum = 0
6824 23:21:24.057960 13, 0x0, sum = 1
6825 23:21:24.060298 14, 0x0, sum = 2
6826 23:21:24.060725 15, 0x0, sum = 3
6827 23:21:24.063804 16, 0x0, sum = 4
6828 23:21:24.064231 best_step = 14
6829 23:21:24.064560
6830 23:21:24.064865 ==
6831 23:21:24.067340 Dram Type= 6, Freq= 0, CH_1, rank 0
6832 23:21:24.074273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 23:21:24.074749 ==
6834 23:21:24.075088 RX Vref Scan: 1
6835 23:21:24.075399
6836 23:21:24.077346 RX Vref 0 -> 0, step: 1
6837 23:21:24.077928
6838 23:21:24.080615 RX Delay -359 -> 252, step: 8
6839 23:21:24.081060
6840 23:21:24.084114 Set Vref, RX VrefLevel [Byte0]: 54
6841 23:21:24.087336 [Byte1]: 54
6842 23:21:24.087760
6843 23:21:24.090678 Final RX Vref Byte 0 = 54 to rank0
6844 23:21:24.093965 Final RX Vref Byte 1 = 54 to rank0
6845 23:21:24.097357 Final RX Vref Byte 0 = 54 to rank1
6846 23:21:24.100843 Final RX Vref Byte 1 = 54 to rank1==
6847 23:21:24.104405 Dram Type= 6, Freq= 0, CH_1, rank 0
6848 23:21:24.107220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 23:21:24.107568 ==
6850 23:21:24.110816 DQS Delay:
6851 23:21:24.111107 DQS0 = 48, DQS1 = 60
6852 23:21:24.113843 DQM Delay:
6853 23:21:24.114140 DQM0 = 12, DQM1 = 13
6854 23:21:24.114440 DQ Delay:
6855 23:21:24.117413 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6856 23:21:24.120785 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6857 23:21:24.123774 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =12
6858 23:21:24.127286 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6859 23:21:24.127465
6860 23:21:24.127630
6861 23:21:24.137553 [DQSOSCAuto] RK0, (LSB)MR18= 0x862e, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6862 23:21:24.137711 CH1 RK0: MR19=C0C, MR18=862E
6863 23:21:24.143824 CH1_RK0: MR19=0xC0C, MR18=0x862E, DQSOSC=393, MR23=63, INC=382, DEC=254
6864 23:21:24.143968 ==
6865 23:21:24.147232 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 23:21:24.153701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 23:21:24.153805 ==
6868 23:21:24.157044 [Gating] SW mode calibration
6869 23:21:24.163918 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6870 23:21:24.167547 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6871 23:21:24.174202 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6872 23:21:24.177772 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6873 23:21:24.181183 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6874 23:21:24.187510 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6875 23:21:24.191170 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6876 23:21:24.194333 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 23:21:24.197547 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 23:21:24.204100 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 23:21:24.207600 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6880 23:21:24.211331 Total UI for P1: 0, mck2ui 16
6881 23:21:24.214324 best dqsien dly found for B0: ( 0, 14, 24)
6882 23:21:24.217702 Total UI for P1: 0, mck2ui 16
6883 23:21:24.220692 best dqsien dly found for B1: ( 0, 14, 24)
6884 23:21:24.224164 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6885 23:21:24.227240 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6886 23:21:24.227851
6887 23:21:24.230873 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6888 23:21:24.234059 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6889 23:21:24.237885 [Gating] SW calibration Done
6890 23:21:24.238355 ==
6891 23:21:24.240987 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 23:21:24.247343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 23:21:24.247763 ==
6894 23:21:24.248127 RX Vref Scan: 0
6895 23:21:24.248437
6896 23:21:24.250606 RX Vref 0 -> 0, step: 1
6897 23:21:24.251111
6898 23:21:24.254503 RX Delay -410 -> 252, step: 16
6899 23:21:24.257638 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6900 23:21:24.260692 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6901 23:21:24.267938 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6902 23:21:24.270712 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6903 23:21:24.274377 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6904 23:21:24.277314 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6905 23:21:24.280887 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6906 23:21:24.287320 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6907 23:21:24.290841 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6908 23:21:24.294379 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6909 23:21:24.297514 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6910 23:21:24.304403 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6911 23:21:24.307793 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6912 23:21:24.310969 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6913 23:21:24.317591 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6914 23:21:24.320594 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6915 23:21:24.321015 ==
6916 23:21:24.324325 Dram Type= 6, Freq= 0, CH_1, rank 1
6917 23:21:24.328113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6918 23:21:24.328537 ==
6919 23:21:24.330978 DQS Delay:
6920 23:21:24.331397 DQS0 = 43, DQS1 = 59
6921 23:21:24.331729 DQM Delay:
6922 23:21:24.334138 DQM0 = 9, DQM1 = 19
6923 23:21:24.334589 DQ Delay:
6924 23:21:24.337365 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6925 23:21:24.341205 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6926 23:21:24.344164 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6927 23:21:24.347663 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6928 23:21:24.348133
6929 23:21:24.348581
6930 23:21:24.348905 ==
6931 23:21:24.350596 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 23:21:24.354066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 23:21:24.354660 ==
6934 23:21:24.355045
6935 23:21:24.357675
6936 23:21:24.358251 TX Vref Scan disable
6937 23:21:24.361213 == TX Byte 0 ==
6938 23:21:24.363991 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6939 23:21:24.367399 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6940 23:21:24.370505 == TX Byte 1 ==
6941 23:21:24.374329 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6942 23:21:24.377725 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6943 23:21:24.378153 ==
6944 23:21:24.380513 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 23:21:24.384185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 23:21:24.384608 ==
6947 23:21:24.385022
6948 23:21:24.387238
6949 23:21:24.387653 TX Vref Scan disable
6950 23:21:24.390699 == TX Byte 0 ==
6951 23:21:24.394352 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6952 23:21:24.397290 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6953 23:21:24.401211 == TX Byte 1 ==
6954 23:21:24.404422 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6955 23:21:24.407771 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6956 23:21:24.408209
6957 23:21:24.408534 [DATLAT]
6958 23:21:24.410717 Freq=400, CH1 RK1
6959 23:21:24.411202
6960 23:21:24.411697 DATLAT Default: 0xe
6961 23:21:24.414572 0, 0xFFFF, sum = 0
6962 23:21:24.415158 1, 0xFFFF, sum = 0
6963 23:21:24.417394 2, 0xFFFF, sum = 0
6964 23:21:24.417820 3, 0xFFFF, sum = 0
6965 23:21:24.421166 4, 0xFFFF, sum = 0
6966 23:21:24.421591 5, 0xFFFF, sum = 0
6967 23:21:24.424389 6, 0xFFFF, sum = 0
6968 23:21:24.427254 7, 0xFFFF, sum = 0
6969 23:21:24.427838 8, 0xFFFF, sum = 0
6970 23:21:24.430691 9, 0xFFFF, sum = 0
6971 23:21:24.431129 10, 0xFFFF, sum = 0
6972 23:21:24.434028 11, 0xFFFF, sum = 0
6973 23:21:24.434523 12, 0xFFFF, sum = 0
6974 23:21:24.437218 13, 0x0, sum = 1
6975 23:21:24.437642 14, 0x0, sum = 2
6976 23:21:24.440535 15, 0x0, sum = 3
6977 23:21:24.440960 16, 0x0, sum = 4
6978 23:21:24.444179 best_step = 14
6979 23:21:24.444580
6980 23:21:24.444904 ==
6981 23:21:24.447158 Dram Type= 6, Freq= 0, CH_1, rank 1
6982 23:21:24.451264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6983 23:21:24.451694 ==
6984 23:21:24.452069 RX Vref Scan: 0
6985 23:21:24.452487
6986 23:21:24.453849 RX Vref 0 -> 0, step: 1
6987 23:21:24.454388
6988 23:21:24.457389 RX Delay -359 -> 252, step: 8
6989 23:21:24.464915 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6990 23:21:24.467688 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6991 23:21:24.471241 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6992 23:21:24.474767 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6993 23:21:24.481284 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6994 23:21:24.484909 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6995 23:21:24.487809 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6996 23:21:24.491535 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6997 23:21:24.498142 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6998 23:21:24.501220 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6999 23:21:24.504474 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7000 23:21:24.508035 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
7001 23:21:24.514610 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
7002 23:21:24.517289 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7003 23:21:24.520889 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7004 23:21:24.527327 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7005 23:21:24.527470 ==
7006 23:21:24.530794 Dram Type= 6, Freq= 0, CH_1, rank 1
7007 23:21:24.534299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7008 23:21:24.534434 ==
7009 23:21:24.534555 DQS Delay:
7010 23:21:24.537779 DQS0 = 52, DQS1 = 56
7011 23:21:24.537889 DQM Delay:
7012 23:21:24.541142 DQM0 = 13, DQM1 = 9
7013 23:21:24.541237 DQ Delay:
7014 23:21:24.544002 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7015 23:21:24.547849 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7016 23:21:24.550754 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
7017 23:21:24.554383 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7018 23:21:24.554503
7019 23:21:24.554592
7020 23:21:24.561298 [DQSOSCAuto] RK1, (LSB)MR18= 0x7186, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 395 ps
7021 23:21:24.564285 CH1 RK1: MR19=C0C, MR18=7186
7022 23:21:24.571361 CH1_RK1: MR19=0xC0C, MR18=0x7186, DQSOSC=393, MR23=63, INC=382, DEC=254
7023 23:21:24.573957 [RxdqsGatingPostProcess] freq 400
7024 23:21:24.577564 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7025 23:21:24.580976 best DQS0 dly(2T, 0.5T) = (0, 10)
7026 23:21:24.584627 best DQS1 dly(2T, 0.5T) = (0, 10)
7027 23:21:24.587446 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7028 23:21:24.590947 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7029 23:21:24.594687 best DQS0 dly(2T, 0.5T) = (0, 10)
7030 23:21:24.597416 best DQS1 dly(2T, 0.5T) = (0, 10)
7031 23:21:24.601018 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7032 23:21:24.603990 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7033 23:21:24.607416 Pre-setting of DQS Precalculation
7034 23:21:24.611050 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7035 23:21:24.620952 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7036 23:21:24.628015 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7037 23:21:24.628210
7038 23:21:24.628322
7039 23:21:24.631272 [Calibration Summary] 800 Mbps
7040 23:21:24.631481 CH 0, Rank 0
7041 23:21:24.634936 SW Impedance : PASS
7042 23:21:24.635075 DUTY Scan : NO K
7043 23:21:24.637660 ZQ Calibration : PASS
7044 23:21:24.637817 Jitter Meter : NO K
7045 23:21:24.641317 CBT Training : PASS
7046 23:21:24.644878 Write leveling : PASS
7047 23:21:24.645143 RX DQS gating : PASS
7048 23:21:24.648096 RX DQ/DQS(RDDQC) : PASS
7049 23:21:24.651661 TX DQ/DQS : PASS
7050 23:21:24.652022 RX DATLAT : PASS
7051 23:21:24.654615 RX DQ/DQS(Engine): PASS
7052 23:21:24.657986 TX OE : NO K
7053 23:21:24.658309 All Pass.
7054 23:21:24.658669
7055 23:21:24.658974 CH 0, Rank 1
7056 23:21:24.661416 SW Impedance : PASS
7057 23:21:24.665535 DUTY Scan : NO K
7058 23:21:24.665954 ZQ Calibration : PASS
7059 23:21:24.668177 Jitter Meter : NO K
7060 23:21:24.671606 CBT Training : PASS
7061 23:21:24.672026 Write leveling : NO K
7062 23:21:24.674822 RX DQS gating : PASS
7063 23:21:24.675245 RX DQ/DQS(RDDQC) : PASS
7064 23:21:24.678031 TX DQ/DQS : PASS
7065 23:21:24.681574 RX DATLAT : PASS
7066 23:21:24.682137 RX DQ/DQS(Engine): PASS
7067 23:21:24.684635 TX OE : NO K
7068 23:21:24.685270 All Pass.
7069 23:21:24.685833
7070 23:21:24.688032 CH 1, Rank 0
7071 23:21:24.688600 SW Impedance : PASS
7072 23:21:24.691307 DUTY Scan : NO K
7073 23:21:24.694800 ZQ Calibration : PASS
7074 23:21:24.695224 Jitter Meter : NO K
7075 23:21:24.698312 CBT Training : PASS
7076 23:21:24.701353 Write leveling : PASS
7077 23:21:24.701773 RX DQS gating : PASS
7078 23:21:24.704876 RX DQ/DQS(RDDQC) : PASS
7079 23:21:24.708389 TX DQ/DQS : PASS
7080 23:21:24.708813 RX DATLAT : PASS
7081 23:21:24.711900 RX DQ/DQS(Engine): PASS
7082 23:21:24.712317 TX OE : NO K
7083 23:21:24.714856 All Pass.
7084 23:21:24.715273
7085 23:21:24.715603 CH 1, Rank 1
7086 23:21:24.718676 SW Impedance : PASS
7087 23:21:24.719099 DUTY Scan : NO K
7088 23:21:24.721775 ZQ Calibration : PASS
7089 23:21:24.725054 Jitter Meter : NO K
7090 23:21:24.725475 CBT Training : PASS
7091 23:21:24.728601 Write leveling : NO K
7092 23:21:24.731659 RX DQS gating : PASS
7093 23:21:24.732078 RX DQ/DQS(RDDQC) : PASS
7094 23:21:24.735038 TX DQ/DQS : PASS
7095 23:21:24.738218 RX DATLAT : PASS
7096 23:21:24.738691 RX DQ/DQS(Engine): PASS
7097 23:21:24.741744 TX OE : NO K
7098 23:21:24.742277 All Pass.
7099 23:21:24.742705
7100 23:21:24.745006 DramC Write-DBI off
7101 23:21:24.748558 PER_BANK_REFRESH: Hybrid Mode
7102 23:21:24.748979 TX_TRACKING: ON
7103 23:21:24.758497 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7104 23:21:24.761854 [FAST_K] Save calibration result to emmc
7105 23:21:24.765036 dramc_set_vcore_voltage set vcore to 725000
7106 23:21:24.768426 Read voltage for 1600, 0
7107 23:21:24.768842 Vio18 = 0
7108 23:21:24.769174 Vcore = 725000
7109 23:21:24.771822 Vdram = 0
7110 23:21:24.772251 Vddq = 0
7111 23:21:24.772574 Vmddr = 0
7112 23:21:24.778763 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7113 23:21:24.781666 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7114 23:21:24.785143 MEM_TYPE=3, freq_sel=13
7115 23:21:24.788194 sv_algorithm_assistance_LP4_3733
7116 23:21:24.792250 ============ PULL DRAM RESETB DOWN ============
7117 23:21:24.794805 ========== PULL DRAM RESETB DOWN end =========
7118 23:21:24.801772 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7119 23:21:24.804946 ===================================
7120 23:21:24.805371 LPDDR4 DRAM CONFIGURATION
7121 23:21:24.808173 ===================================
7122 23:21:24.811735 EX_ROW_EN[0] = 0x0
7123 23:21:24.814950 EX_ROW_EN[1] = 0x0
7124 23:21:24.815396 LP4Y_EN = 0x0
7125 23:21:24.818631 WORK_FSP = 0x1
7126 23:21:24.819042 WL = 0x5
7127 23:21:24.821944 RL = 0x5
7128 23:21:24.822360 BL = 0x2
7129 23:21:24.824981 RPST = 0x0
7130 23:21:24.825394 RD_PRE = 0x0
7131 23:21:24.828289 WR_PRE = 0x1
7132 23:21:24.828710 WR_PST = 0x1
7133 23:21:24.832279 DBI_WR = 0x0
7134 23:21:24.832806 DBI_RD = 0x0
7135 23:21:24.834891 OTF = 0x1
7136 23:21:24.838451 ===================================
7137 23:21:24.842059 ===================================
7138 23:21:24.842656 ANA top config
7139 23:21:24.845038 ===================================
7140 23:21:24.848568 DLL_ASYNC_EN = 0
7141 23:21:24.851826 ALL_SLAVE_EN = 0
7142 23:21:24.852249 NEW_RANK_MODE = 1
7143 23:21:24.855293 DLL_IDLE_MODE = 1
7144 23:21:24.858643 LP45_APHY_COMB_EN = 1
7145 23:21:24.861749 TX_ODT_DIS = 0
7146 23:21:24.865543 NEW_8X_MODE = 1
7147 23:21:24.869057 ===================================
7148 23:21:24.871522 ===================================
7149 23:21:24.871947 data_rate = 3200
7150 23:21:24.875037 CKR = 1
7151 23:21:24.878710 DQ_P2S_RATIO = 8
7152 23:21:24.881581 ===================================
7153 23:21:24.885194 CA_P2S_RATIO = 8
7154 23:21:24.888049 DQ_CA_OPEN = 0
7155 23:21:24.891987 DQ_SEMI_OPEN = 0
7156 23:21:24.892412 CA_SEMI_OPEN = 0
7157 23:21:24.894908 CA_FULL_RATE = 0
7158 23:21:24.898195 DQ_CKDIV4_EN = 0
7159 23:21:24.901832 CA_CKDIV4_EN = 0
7160 23:21:24.905323 CA_PREDIV_EN = 0
7161 23:21:24.908734 PH8_DLY = 12
7162 23:21:24.909204 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7163 23:21:24.912021 DQ_AAMCK_DIV = 4
7164 23:21:24.915009 CA_AAMCK_DIV = 4
7165 23:21:24.918793 CA_ADMCK_DIV = 4
7166 23:21:24.921816 DQ_TRACK_CA_EN = 0
7167 23:21:24.925217 CA_PICK = 1600
7168 23:21:24.925821 CA_MCKIO = 1600
7169 23:21:24.928591 MCKIO_SEMI = 0
7170 23:21:24.931869 PLL_FREQ = 3068
7171 23:21:24.935632 DQ_UI_PI_RATIO = 32
7172 23:21:24.938368 CA_UI_PI_RATIO = 0
7173 23:21:24.941992 ===================================
7174 23:21:24.945252 ===================================
7175 23:21:24.948359 memory_type:LPDDR4
7176 23:21:24.948942 GP_NUM : 10
7177 23:21:24.951893 SRAM_EN : 1
7178 23:21:24.952468 MD32_EN : 0
7179 23:21:24.955278 ===================================
7180 23:21:24.958921 [ANA_INIT] >>>>>>>>>>>>>>
7181 23:21:24.961694 <<<<<< [CONFIGURE PHASE]: ANA_TX
7182 23:21:24.965237 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7183 23:21:24.968833 ===================================
7184 23:21:24.971838 data_rate = 3200,PCW = 0X7600
7185 23:21:24.975317 ===================================
7186 23:21:24.978641 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7187 23:21:24.981866 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7188 23:21:24.988247 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7189 23:21:24.991999 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7190 23:21:24.998180 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7191 23:21:25.001836 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7192 23:21:25.002264 [ANA_INIT] flow start
7193 23:21:25.005294 [ANA_INIT] PLL >>>>>>>>
7194 23:21:25.008458 [ANA_INIT] PLL <<<<<<<<
7195 23:21:25.008879 [ANA_INIT] MIDPI >>>>>>>>
7196 23:21:25.011937 [ANA_INIT] MIDPI <<<<<<<<
7197 23:21:25.015459 [ANA_INIT] DLL >>>>>>>>
7198 23:21:25.016034 [ANA_INIT] DLL <<<<<<<<
7199 23:21:25.018718 [ANA_INIT] flow end
7200 23:21:25.021586 ============ LP4 DIFF to SE enter ============
7201 23:21:25.025336 ============ LP4 DIFF to SE exit ============
7202 23:21:25.028379 [ANA_INIT] <<<<<<<<<<<<<
7203 23:21:25.031893 [Flow] Enable top DCM control >>>>>
7204 23:21:25.035344 [Flow] Enable top DCM control <<<<<
7205 23:21:25.038509 Enable DLL master slave shuffle
7206 23:21:25.045475 ==============================================================
7207 23:21:25.045896 Gating Mode config
7208 23:21:25.051721 ==============================================================
7209 23:21:25.052145 Config description:
7210 23:21:25.062117 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7211 23:21:25.068781 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7212 23:21:25.075830 SELPH_MODE 0: By rank 1: By Phase
7213 23:21:25.078977 ==============================================================
7214 23:21:25.082392 GAT_TRACK_EN = 1
7215 23:21:25.085340 RX_GATING_MODE = 2
7216 23:21:25.088794 RX_GATING_TRACK_MODE = 2
7217 23:21:25.091598 SELPH_MODE = 1
7218 23:21:25.095256 PICG_EARLY_EN = 1
7219 23:21:25.098293 VALID_LAT_VALUE = 1
7220 23:21:25.102124 ==============================================================
7221 23:21:25.104977 Enter into Gating configuration >>>>
7222 23:21:25.109039 Exit from Gating configuration <<<<
7223 23:21:25.112185 Enter into DVFS_PRE_config >>>>>
7224 23:21:25.125537 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7225 23:21:25.126084 Exit from DVFS_PRE_config <<<<<
7226 23:21:25.128874 Enter into PICG configuration >>>>
7227 23:21:25.132428 Exit from PICG configuration <<<<
7228 23:21:25.135571 [RX_INPUT] configuration >>>>>
7229 23:21:25.138733 [RX_INPUT] configuration <<<<<
7230 23:21:25.145571 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7231 23:21:25.149868 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7232 23:21:25.155829 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7233 23:21:25.162086 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7234 23:21:25.169241 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7235 23:21:25.175364 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7236 23:21:25.178814 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7237 23:21:25.182260 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7238 23:21:25.185366 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7239 23:21:25.192309 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7240 23:21:25.195251 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7241 23:21:25.198714 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7242 23:21:25.201898 ===================================
7243 23:21:25.205450 LPDDR4 DRAM CONFIGURATION
7244 23:21:25.208637 ===================================
7245 23:21:25.208936 EX_ROW_EN[0] = 0x0
7246 23:21:25.212087 EX_ROW_EN[1] = 0x0
7247 23:21:25.212312 LP4Y_EN = 0x0
7248 23:21:25.215763 WORK_FSP = 0x1
7249 23:21:25.215988 WL = 0x5
7250 23:21:25.218604 RL = 0x5
7251 23:21:25.218784 BL = 0x2
7252 23:21:25.222170 RPST = 0x0
7253 23:21:25.225056 RD_PRE = 0x0
7254 23:21:25.225207 WR_PRE = 0x1
7255 23:21:25.228467 WR_PST = 0x1
7256 23:21:25.228598 DBI_WR = 0x0
7257 23:21:25.232135 DBI_RD = 0x0
7258 23:21:25.232256 OTF = 0x1
7259 23:21:25.235088 ===================================
7260 23:21:25.238661 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7261 23:21:25.241815 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7262 23:21:25.248588 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7263 23:21:25.251815 ===================================
7264 23:21:25.255028 LPDDR4 DRAM CONFIGURATION
7265 23:21:25.258734 ===================================
7266 23:21:25.258836 EX_ROW_EN[0] = 0x10
7267 23:21:25.262010 EX_ROW_EN[1] = 0x0
7268 23:21:25.262097 LP4Y_EN = 0x0
7269 23:21:25.265228 WORK_FSP = 0x1
7270 23:21:25.265308 WL = 0x5
7271 23:21:25.268783 RL = 0x5
7272 23:21:25.268869 BL = 0x2
7273 23:21:25.271884 RPST = 0x0
7274 23:21:25.271958 RD_PRE = 0x0
7275 23:21:25.275390 WR_PRE = 0x1
7276 23:21:25.275463 WR_PST = 0x1
7277 23:21:25.278662 DBI_WR = 0x0
7278 23:21:25.278731 DBI_RD = 0x0
7279 23:21:25.282271 OTF = 0x1
7280 23:21:25.285765 ===================================
7281 23:21:25.292094 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7282 23:21:25.292196 ==
7283 23:21:25.295532 Dram Type= 6, Freq= 0, CH_0, rank 0
7284 23:21:25.298666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7285 23:21:25.298770 ==
7286 23:21:25.302273 [Duty_Offset_Calibration]
7287 23:21:25.302393 B0:2 B1:-1 CA:1
7288 23:21:25.302500
7289 23:21:25.305269 [DutyScan_Calibration_Flow] k_type=0
7290 23:21:25.315593
7291 23:21:25.315747 ==CLK 0==
7292 23:21:25.318796 Final CLK duty delay cell = -4
7293 23:21:25.322388 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7294 23:21:25.325310 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7295 23:21:25.329122 [-4] AVG Duty = 4937%(X100)
7296 23:21:25.329347
7297 23:21:25.332544 CH0 CLK Duty spec in!! Max-Min= 187%
7298 23:21:25.335757 [DutyScan_Calibration_Flow] ====Done====
7299 23:21:25.336029
7300 23:21:25.339176 [DutyScan_Calibration_Flow] k_type=1
7301 23:21:25.355396
7302 23:21:25.355830 ==DQS 0 ==
7303 23:21:25.358640 Final DQS duty delay cell = 0
7304 23:21:25.362036 [0] MAX Duty = 5125%(X100), DQS PI = 20
7305 23:21:25.364958 [0] MIN Duty = 5031%(X100), DQS PI = 4
7306 23:21:25.365383 [0] AVG Duty = 5078%(X100)
7307 23:21:25.368711
7308 23:21:25.369129 ==DQS 1 ==
7309 23:21:25.372018 Final DQS duty delay cell = -4
7310 23:21:25.375093 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7311 23:21:25.378485 [-4] MIN Duty = 5000%(X100), DQS PI = 24
7312 23:21:25.381836 [-4] AVG Duty = 5046%(X100)
7313 23:21:25.382255
7314 23:21:25.385276 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7315 23:21:25.385864
7316 23:21:25.388333 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7317 23:21:25.391464 [DutyScan_Calibration_Flow] ====Done====
7318 23:21:25.391572
7319 23:21:25.394827 [DutyScan_Calibration_Flow] k_type=3
7320 23:21:25.412154
7321 23:21:25.412264 ==DQM 0 ==
7322 23:21:25.415774 Final DQM duty delay cell = 0
7323 23:21:25.418534 [0] MAX Duty = 5000%(X100), DQS PI = 20
7324 23:21:25.422194 [0] MIN Duty = 4875%(X100), DQS PI = 4
7325 23:21:25.422266 [0] AVG Duty = 4937%(X100)
7326 23:21:25.425768
7327 23:21:25.425850 ==DQM 1 ==
7328 23:21:25.428732 Final DQM duty delay cell = 0
7329 23:21:25.432384 [0] MAX Duty = 5218%(X100), DQS PI = 58
7330 23:21:25.435891 [0] MIN Duty = 4969%(X100), DQS PI = 18
7331 23:21:25.435982 [0] AVG Duty = 5093%(X100)
7332 23:21:25.439095
7333 23:21:25.442090 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7334 23:21:25.442185
7335 23:21:25.445306 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7336 23:21:25.448907 [DutyScan_Calibration_Flow] ====Done====
7337 23:21:25.449024
7338 23:21:25.452451 [DutyScan_Calibration_Flow] k_type=2
7339 23:21:25.468247
7340 23:21:25.468323 ==DQ 0 ==
7341 23:21:25.471863 Final DQ duty delay cell = -4
7342 23:21:25.475080 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7343 23:21:25.478264 [-4] MIN Duty = 4844%(X100), DQS PI = 26
7344 23:21:25.481827 [-4] AVG Duty = 4922%(X100)
7345 23:21:25.481901
7346 23:21:25.481981 ==DQ 1 ==
7347 23:21:25.484942 Final DQ duty delay cell = 0
7348 23:21:25.488637 [0] MAX Duty = 5031%(X100), DQS PI = 30
7349 23:21:25.491632 [0] MIN Duty = 4907%(X100), DQS PI = 18
7350 23:21:25.491735 [0] AVG Duty = 4969%(X100)
7351 23:21:25.494831
7352 23:21:25.498328 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7353 23:21:25.498429
7354 23:21:25.501757 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7355 23:21:25.505019 [DutyScan_Calibration_Flow] ====Done====
7356 23:21:25.505120 ==
7357 23:21:25.508506 Dram Type= 6, Freq= 0, CH_1, rank 0
7358 23:21:25.511605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7359 23:21:25.511688 ==
7360 23:21:25.515035 [Duty_Offset_Calibration]
7361 23:21:25.515116 B0:1 B1:1 CA:2
7362 23:21:25.515180
7363 23:21:25.518689 [DutyScan_Calibration_Flow] k_type=0
7364 23:21:25.529075
7365 23:21:25.529155 ==CLK 0==
7366 23:21:25.532540 Final CLK duty delay cell = 0
7367 23:21:25.535487 [0] MAX Duty = 5187%(X100), DQS PI = 24
7368 23:21:25.539135 [0] MIN Duty = 4969%(X100), DQS PI = 38
7369 23:21:25.539238 [0] AVG Duty = 5078%(X100)
7370 23:21:25.542498
7371 23:21:25.545408 CH1 CLK Duty spec in!! Max-Min= 218%
7372 23:21:25.548837 [DutyScan_Calibration_Flow] ====Done====
7373 23:21:25.548914
7374 23:21:25.552432 [DutyScan_Calibration_Flow] k_type=1
7375 23:21:25.568527
7376 23:21:25.568606 ==DQS 0 ==
7377 23:21:25.572027 Final DQS duty delay cell = 0
7378 23:21:25.575746 [0] MAX Duty = 5062%(X100), DQS PI = 22
7379 23:21:25.578680 [0] MIN Duty = 4813%(X100), DQS PI = 52
7380 23:21:25.582070 [0] AVG Duty = 4937%(X100)
7381 23:21:25.582168
7382 23:21:25.582257 ==DQS 1 ==
7383 23:21:25.585229 Final DQS duty delay cell = 0
7384 23:21:25.588831 [0] MAX Duty = 5031%(X100), DQS PI = 36
7385 23:21:25.592127 [0] MIN Duty = 4938%(X100), DQS PI = 12
7386 23:21:25.595279 [0] AVG Duty = 4984%(X100)
7387 23:21:25.595377
7388 23:21:25.599118 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7389 23:21:25.599221
7390 23:21:25.602563 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7391 23:21:25.605634 [DutyScan_Calibration_Flow] ====Done====
7392 23:21:25.605737
7393 23:21:25.609157 [DutyScan_Calibration_Flow] k_type=3
7394 23:21:25.625939
7395 23:21:25.626048 ==DQM 0 ==
7396 23:21:25.628831 Final DQM duty delay cell = 0
7397 23:21:25.632228 [0] MAX Duty = 5156%(X100), DQS PI = 20
7398 23:21:25.635489 [0] MIN Duty = 4844%(X100), DQS PI = 50
7399 23:21:25.635590 [0] AVG Duty = 5000%(X100)
7400 23:21:25.639106
7401 23:21:25.639219 ==DQM 1 ==
7402 23:21:25.642879 Final DQM duty delay cell = 0
7403 23:21:25.645936 [0] MAX Duty = 5156%(X100), DQS PI = 60
7404 23:21:25.649149 [0] MIN Duty = 4875%(X100), DQS PI = 20
7405 23:21:25.649230 [0] AVG Duty = 5015%(X100)
7406 23:21:25.652298
7407 23:21:25.655520 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7408 23:21:25.655601
7409 23:21:25.658839 CH1 DQM 1 Duty spec in!! Max-Min= 281%
7410 23:21:25.662338 [DutyScan_Calibration_Flow] ====Done====
7411 23:21:25.662426
7412 23:21:25.665957 [DutyScan_Calibration_Flow] k_type=2
7413 23:21:25.682762
7414 23:21:25.682843 ==DQ 0 ==
7415 23:21:25.686241 Final DQ duty delay cell = 0
7416 23:21:25.689269 [0] MAX Duty = 5125%(X100), DQS PI = 20
7417 23:21:25.692761 [0] MIN Duty = 4907%(X100), DQS PI = 52
7418 23:21:25.692842 [0] AVG Duty = 5016%(X100)
7419 23:21:25.696199
7420 23:21:25.696281 ==DQ 1 ==
7421 23:21:25.699201 Final DQ duty delay cell = 0
7422 23:21:25.702339 [0] MAX Duty = 5093%(X100), DQS PI = 6
7423 23:21:25.705791 [0] MIN Duty = 5031%(X100), DQS PI = 0
7424 23:21:25.705874 [0] AVG Duty = 5062%(X100)
7425 23:21:25.705979
7426 23:21:25.709129 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7427 23:21:25.709211
7428 23:21:25.712610 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7429 23:21:25.718985 [DutyScan_Calibration_Flow] ====Done====
7430 23:21:25.722986 nWR fixed to 30
7431 23:21:25.723069 [ModeRegInit_LP4] CH0 RK0
7432 23:21:25.725703 [ModeRegInit_LP4] CH0 RK1
7433 23:21:25.729085 [ModeRegInit_LP4] CH1 RK0
7434 23:21:25.729168 [ModeRegInit_LP4] CH1 RK1
7435 23:21:25.732615 match AC timing 5
7436 23:21:25.735921 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7437 23:21:25.739023 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7438 23:21:25.746107 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7439 23:21:25.749051 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7440 23:21:25.755961 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7441 23:21:25.756043 [MiockJmeterHQA]
7442 23:21:25.756107
7443 23:21:25.759057 [DramcMiockJmeter] u1RxGatingPI = 0
7444 23:21:25.759139 0 : 4253, 4027
7445 23:21:25.762846 4 : 4258, 4026
7446 23:21:25.762955 8 : 4363, 4138
7447 23:21:25.765953 12 : 4253, 4027
7448 23:21:25.766052 16 : 4363, 4138
7449 23:21:25.769740 20 : 4252, 4027
7450 23:21:25.769823 24 : 4360, 4138
7451 23:21:25.769889 28 : 4253, 4027
7452 23:21:25.772648 32 : 4250, 4027
7453 23:21:25.772731 36 : 4250, 4027
7454 23:21:25.776304 40 : 4365, 4140
7455 23:21:25.776387 44 : 4361, 4138
7456 23:21:25.779707 48 : 4250, 4026
7457 23:21:25.779791 52 : 4252, 4027
7458 23:21:25.782686 56 : 4250, 4027
7459 23:21:25.782769 60 : 4250, 4026
7460 23:21:25.782835 64 : 4252, 4030
7461 23:21:25.786255 68 : 4360, 4137
7462 23:21:25.786338 72 : 4250, 4027
7463 23:21:25.789649 76 : 4250, 4027
7464 23:21:25.789731 80 : 4250, 4026
7465 23:21:25.792584 84 : 4252, 4030
7466 23:21:25.792667 88 : 4250, 4026
7467 23:21:25.792733 92 : 4361, 4137
7468 23:21:25.796135 96 : 4361, 3273
7469 23:21:25.796217 100 : 4250, 0
7470 23:21:25.799776 104 : 4250, 0
7471 23:21:25.799860 108 : 4250, 0
7472 23:21:25.799927 112 : 4361, 0
7473 23:21:25.802704 116 : 4360, 0
7474 23:21:25.802787 120 : 4363, 0
7475 23:21:25.805918 124 : 4250, 0
7476 23:21:25.806023 128 : 4250, 0
7477 23:21:25.806122 132 : 4252, 0
7478 23:21:25.809278 136 : 4250, 0
7479 23:21:25.809362 140 : 4249, 0
7480 23:21:25.812784 144 : 4363, 0
7481 23:21:25.812868 148 : 4250, 0
7482 23:21:25.812973 152 : 4360, 0
7483 23:21:25.815995 156 : 4250, 0
7484 23:21:25.816078 160 : 4250, 0
7485 23:21:25.819528 164 : 4250, 0
7486 23:21:25.819612 168 : 4360, 0
7487 23:21:25.819678 172 : 4361, 0
7488 23:21:25.822452 176 : 4250, 0
7489 23:21:25.822536 180 : 4250, 0
7490 23:21:25.826140 184 : 4252, 0
7491 23:21:25.826223 188 : 4250, 0
7492 23:21:25.826289 192 : 4250, 0
7493 23:21:25.829002 196 : 4363, 0
7494 23:21:25.829099 200 : 4250, 0
7495 23:21:25.829168 204 : 4361, 0
7496 23:21:25.832517 208 : 4250, 0
7497 23:21:25.832599 212 : 4250, 56
7498 23:21:25.836024 216 : 4360, 3487
7499 23:21:25.836107 220 : 4250, 4026
7500 23:21:25.839288 224 : 4250, 4027
7501 23:21:25.839370 228 : 4361, 4138
7502 23:21:25.842522 232 : 4250, 4027
7503 23:21:25.842633 236 : 4250, 4026
7504 23:21:25.846172 240 : 4250, 4027
7505 23:21:25.846274 244 : 4252, 4030
7506 23:21:25.846367 248 : 4250, 4027
7507 23:21:25.849657 252 : 4250, 4026
7508 23:21:25.849762 256 : 4361, 4137
7509 23:21:25.852748 260 : 4250, 4027
7510 23:21:25.852858 264 : 4250, 4027
7511 23:21:25.855914 268 : 4360, 4137
7512 23:21:25.855999 272 : 4250, 4026
7513 23:21:25.858947 276 : 4250, 4027
7514 23:21:25.859030 280 : 4363, 4140
7515 23:21:25.862353 284 : 4250, 4027
7516 23:21:25.862476 288 : 4250, 4026
7517 23:21:25.865756 292 : 4250, 4027
7518 23:21:25.865839 296 : 4252, 4030
7519 23:21:25.869066 300 : 4250, 4027
7520 23:21:25.869149 304 : 4250, 4026
7521 23:21:25.869215 308 : 4361, 4137
7522 23:21:25.872550 312 : 4250, 4027
7523 23:21:25.872633 316 : 4250, 4027
7524 23:21:25.875659 320 : 4360, 4137
7525 23:21:25.875742 324 : 4250, 4026
7526 23:21:25.879103 328 : 4252, 4027
7527 23:21:25.879186 332 : 4363, 3416
7528 23:21:25.882711 336 : 4250, 238
7529 23:21:25.882794
7530 23:21:25.882859 MIOCK jitter meter ch=0
7531 23:21:25.882919
7532 23:21:25.885747 1T = (336-100) = 236 dly cells
7533 23:21:25.892195 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7534 23:21:25.892280 ==
7535 23:21:25.895851 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 23:21:25.898866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 23:21:25.898949 ==
7538 23:21:25.906077 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7539 23:21:25.909057 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7540 23:21:25.915423 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7541 23:21:25.918924 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7542 23:21:25.929003 [CA 0] Center 44 (14~75) winsize 62
7543 23:21:25.932563 [CA 1] Center 44 (14~74) winsize 61
7544 23:21:25.935652 [CA 2] Center 39 (10~68) winsize 59
7545 23:21:25.939411 [CA 3] Center 38 (9~68) winsize 60
7546 23:21:25.942265 [CA 4] Center 37 (7~67) winsize 61
7547 23:21:25.945467 [CA 5] Center 37 (7~67) winsize 61
7548 23:21:25.945549
7549 23:21:25.949088 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7550 23:21:25.949170
7551 23:21:25.952221 [CATrainingPosCal] consider 1 rank data
7552 23:21:25.955913 u2DelayCellTimex100 = 275/100 ps
7553 23:21:25.958885 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7554 23:21:25.965934 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7555 23:21:25.969199 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7556 23:21:25.972565 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
7557 23:21:25.975811 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7558 23:21:25.979113 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7559 23:21:25.979195
7560 23:21:25.982432 CA PerBit enable=1, Macro0, CA PI delay=37
7561 23:21:25.982527
7562 23:21:25.985860 [CBTSetCACLKResult] CA Dly = 37
7563 23:21:25.988811 CS Dly: 11 (0~42)
7564 23:21:25.992561 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7565 23:21:25.995967 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7566 23:21:25.996049 ==
7567 23:21:25.998869 Dram Type= 6, Freq= 0, CH_0, rank 1
7568 23:21:26.002593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 23:21:26.002675 ==
7570 23:21:26.009240 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7571 23:21:26.012740 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7572 23:21:26.019062 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7573 23:21:26.022838 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7574 23:21:26.032568 [CA 0] Center 44 (14~75) winsize 62
7575 23:21:26.036292 [CA 1] Center 44 (14~75) winsize 62
7576 23:21:26.039166 [CA 2] Center 40 (11~69) winsize 59
7577 23:21:26.042582 [CA 3] Center 39 (10~69) winsize 60
7578 23:21:26.046021 [CA 4] Center 38 (8~68) winsize 61
7579 23:21:26.049590 [CA 5] Center 37 (7~67) winsize 61
7580 23:21:26.049673
7581 23:21:26.052695 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7582 23:21:26.052799
7583 23:21:26.056119 [CATrainingPosCal] consider 2 rank data
7584 23:21:26.059229 u2DelayCellTimex100 = 275/100 ps
7585 23:21:26.062540 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7586 23:21:26.069409 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7587 23:21:26.072852 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7588 23:21:26.076123 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7589 23:21:26.079234 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7590 23:21:26.082657 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7591 23:21:26.082759
7592 23:21:26.085839 CA PerBit enable=1, Macro0, CA PI delay=37
7593 23:21:26.085943
7594 23:21:26.089419 [CBTSetCACLKResult] CA Dly = 37
7595 23:21:26.092937 CS Dly: 12 (0~44)
7596 23:21:26.095885 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7597 23:21:26.099270 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7598 23:21:26.099373
7599 23:21:26.102930 ----->DramcWriteLeveling(PI) begin...
7600 23:21:26.103038 ==
7601 23:21:26.105827 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 23:21:26.109203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 23:21:26.112882 ==
7604 23:21:26.112985 Write leveling (Byte 0): 32 => 32
7605 23:21:26.116418 Write leveling (Byte 1): 26 => 26
7606 23:21:26.119339 DramcWriteLeveling(PI) end<-----
7607 23:21:26.119439
7608 23:21:26.119566 ==
7609 23:21:26.122753 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 23:21:26.129149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 23:21:26.129256 ==
7612 23:21:26.132628 [Gating] SW mode calibration
7613 23:21:26.139395 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7614 23:21:26.142862 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7615 23:21:26.149441 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 23:21:26.152880 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 23:21:26.156213 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 23:21:26.159216 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 23:21:26.166485 1 4 16 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7620 23:21:26.169377 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7621 23:21:26.172788 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7622 23:21:26.179533 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7623 23:21:26.183080 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7624 23:21:26.185930 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7625 23:21:26.192866 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7626 23:21:26.196289 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7627 23:21:26.199695 1 5 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7628 23:21:26.206135 1 5 20 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
7629 23:21:26.209723 1 5 24 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
7630 23:21:26.212737 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 23:21:26.219380 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 23:21:26.222814 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 23:21:26.226392 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 23:21:26.229879 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 23:21:26.236478 1 6 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7636 23:21:26.239370 1 6 20 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7637 23:21:26.242918 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7638 23:21:26.249470 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 23:21:26.252889 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 23:21:26.256588 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 23:21:26.262960 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 23:21:26.266366 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 23:21:26.269426 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7644 23:21:26.276118 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7645 23:21:26.279764 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7646 23:21:26.283120 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 23:21:26.289796 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 23:21:26.293023 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 23:21:26.296475 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 23:21:26.303156 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 23:21:26.306842 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 23:21:26.310147 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 23:21:26.313279 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 23:21:26.319661 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 23:21:26.323168 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 23:21:26.326790 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 23:21:26.333236 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 23:21:26.336185 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 23:21:26.339683 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7660 23:21:26.346705 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7661 23:21:26.346793 Total UI for P1: 0, mck2ui 16
7662 23:21:26.353113 best dqsien dly found for B0: ( 1, 9, 16)
7663 23:21:26.356638 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 23:21:26.360321 Total UI for P1: 0, mck2ui 16
7665 23:21:26.363245 best dqsien dly found for B1: ( 1, 9, 20)
7666 23:21:26.366717 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7667 23:21:26.369700 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7668 23:21:26.369800
7669 23:21:26.373221 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7670 23:21:26.376578 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7671 23:21:26.379947 [Gating] SW calibration Done
7672 23:21:26.380046 ==
7673 23:21:26.383157 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 23:21:26.386931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 23:21:26.390053 ==
7676 23:21:26.390199 RX Vref Scan: 0
7677 23:21:26.390266
7678 23:21:26.393428 RX Vref 0 -> 0, step: 1
7679 23:21:26.393524
7680 23:21:26.393634 RX Delay 0 -> 252, step: 8
7681 23:21:26.399955 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7682 23:21:26.403495 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7683 23:21:26.406528 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7684 23:21:26.409924 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
7685 23:21:26.413505 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7686 23:21:26.419917 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7687 23:21:26.423582 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7688 23:21:26.426884 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7689 23:21:26.430237 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7690 23:21:26.433411 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7691 23:21:26.440050 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7692 23:21:26.443586 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7693 23:21:26.446536 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7694 23:21:26.449965 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
7695 23:21:26.453594 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7696 23:21:26.459976 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7697 23:21:26.460059 ==
7698 23:21:26.463737 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 23:21:26.466654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 23:21:26.466766 ==
7701 23:21:26.466834 DQS Delay:
7702 23:21:26.470082 DQS0 = 0, DQS1 = 0
7703 23:21:26.470158 DQM Delay:
7704 23:21:26.473091 DQM0 = 132, DQM1 = 123
7705 23:21:26.473166 DQ Delay:
7706 23:21:26.476557 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
7707 23:21:26.480136 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7708 23:21:26.483030 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7709 23:21:26.486621 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7710 23:21:26.486720
7711 23:21:26.486809
7712 23:21:26.489590 ==
7713 23:21:26.493211 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 23:21:26.496618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 23:21:26.496724 ==
7716 23:21:26.496824
7717 23:21:26.496917
7718 23:21:26.500250 TX Vref Scan disable
7719 23:21:26.500351 == TX Byte 0 ==
7720 23:21:26.506600 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7721 23:21:26.510011 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7722 23:21:26.510087 == TX Byte 1 ==
7723 23:21:26.516735 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7724 23:21:26.519747 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7725 23:21:26.519828 ==
7726 23:21:26.523271 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 23:21:26.526214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 23:21:26.526318 ==
7729 23:21:26.540539
7730 23:21:26.543490 TX Vref early break, caculate TX vref
7731 23:21:26.547145 TX Vref=16, minBit 7, minWin=21, winSum=356
7732 23:21:26.550119 TX Vref=18, minBit 0, minWin=22, winSum=364
7733 23:21:26.553651 TX Vref=20, minBit 4, minWin=22, winSum=373
7734 23:21:26.557109 TX Vref=22, minBit 1, minWin=23, winSum=383
7735 23:21:26.560771 TX Vref=24, minBit 7, minWin=23, winSum=395
7736 23:21:26.567428 TX Vref=26, minBit 0, minWin=24, winSum=407
7737 23:21:26.570292 TX Vref=28, minBit 4, minWin=24, winSum=415
7738 23:21:26.573817 TX Vref=30, minBit 4, minWin=24, winSum=408
7739 23:21:26.576604 TX Vref=32, minBit 0, minWin=24, winSum=405
7740 23:21:26.580281 TX Vref=34, minBit 0, minWin=23, winSum=391
7741 23:21:26.586681 [TxChooseVref] Worse bit 4, Min win 24, Win sum 415, Final Vref 28
7742 23:21:26.586770
7743 23:21:26.590021 Final TX Range 0 Vref 28
7744 23:21:26.590106
7745 23:21:26.590192 ==
7746 23:21:26.593554 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 23:21:26.597157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 23:21:26.597244 ==
7749 23:21:26.597331
7750 23:21:26.597413
7751 23:21:26.600182 TX Vref Scan disable
7752 23:21:26.606536 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7753 23:21:26.606620 == TX Byte 0 ==
7754 23:21:26.610226 u2DelayCellOfst[0]=14 cells (4 PI)
7755 23:21:26.613381 u2DelayCellOfst[1]=17 cells (5 PI)
7756 23:21:26.616972 u2DelayCellOfst[2]=10 cells (3 PI)
7757 23:21:26.619778 u2DelayCellOfst[3]=10 cells (3 PI)
7758 23:21:26.623532 u2DelayCellOfst[4]=7 cells (2 PI)
7759 23:21:26.626451 u2DelayCellOfst[5]=0 cells (0 PI)
7760 23:21:26.629817 u2DelayCellOfst[6]=17 cells (5 PI)
7761 23:21:26.633355 u2DelayCellOfst[7]=17 cells (5 PI)
7762 23:21:26.636591 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7763 23:21:26.639969 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7764 23:21:26.643433 == TX Byte 1 ==
7765 23:21:26.643537 u2DelayCellOfst[8]=0 cells (0 PI)
7766 23:21:26.646808 u2DelayCellOfst[9]=0 cells (0 PI)
7767 23:21:26.649609 u2DelayCellOfst[10]=7 cells (2 PI)
7768 23:21:26.653440 u2DelayCellOfst[11]=0 cells (0 PI)
7769 23:21:26.656625 u2DelayCellOfst[12]=10 cells (3 PI)
7770 23:21:26.660153 u2DelayCellOfst[13]=10 cells (3 PI)
7771 23:21:26.663034 u2DelayCellOfst[14]=17 cells (5 PI)
7772 23:21:26.666680 u2DelayCellOfst[15]=10 cells (3 PI)
7773 23:21:26.670178 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7774 23:21:26.676475 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7775 23:21:26.676581 DramC Write-DBI on
7776 23:21:26.676674 ==
7777 23:21:26.680167 Dram Type= 6, Freq= 0, CH_0, rank 0
7778 23:21:26.683056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7779 23:21:26.686600 ==
7780 23:21:26.686703
7781 23:21:26.686794
7782 23:21:26.686881 TX Vref Scan disable
7783 23:21:26.690185 == TX Byte 0 ==
7784 23:21:26.693378 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7785 23:21:26.696301 == TX Byte 1 ==
7786 23:21:26.699875 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7787 23:21:26.702923 DramC Write-DBI off
7788 23:21:26.703057
7789 23:21:26.703178 [DATLAT]
7790 23:21:26.703298 Freq=1600, CH0 RK0
7791 23:21:26.703413
7792 23:21:26.706378 DATLAT Default: 0xf
7793 23:21:26.706520 0, 0xFFFF, sum = 0
7794 23:21:26.709953 1, 0xFFFF, sum = 0
7795 23:21:26.710111 2, 0xFFFF, sum = 0
7796 23:21:26.713208 3, 0xFFFF, sum = 0
7797 23:21:26.716170 4, 0xFFFF, sum = 0
7798 23:21:26.716340 5, 0xFFFF, sum = 0
7799 23:21:26.720057 6, 0xFFFF, sum = 0
7800 23:21:26.720164 7, 0xFFFF, sum = 0
7801 23:21:26.723010 8, 0xFFFF, sum = 0
7802 23:21:26.723112 9, 0xFFFF, sum = 0
7803 23:21:26.726676 10, 0xFFFF, sum = 0
7804 23:21:26.726753 11, 0xFFFF, sum = 0
7805 23:21:26.729704 12, 0xFFFF, sum = 0
7806 23:21:26.729808 13, 0xFFFF, sum = 0
7807 23:21:26.733022 14, 0x0, sum = 1
7808 23:21:26.733126 15, 0x0, sum = 2
7809 23:21:26.736393 16, 0x0, sum = 3
7810 23:21:26.736499 17, 0x0, sum = 4
7811 23:21:26.739817 best_step = 15
7812 23:21:26.739888
7813 23:21:26.739950 ==
7814 23:21:26.743144 Dram Type= 6, Freq= 0, CH_0, rank 0
7815 23:21:26.746618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7816 23:21:26.746700 ==
7817 23:21:26.746765 RX Vref Scan: 1
7818 23:21:26.750251
7819 23:21:26.750353 Set Vref Range= 24 -> 127
7820 23:21:26.750453
7821 23:21:26.752934 RX Vref 24 -> 127, step: 1
7822 23:21:26.753032
7823 23:21:26.756235 RX Delay 11 -> 252, step: 4
7824 23:21:26.756334
7825 23:21:26.759533 Set Vref, RX VrefLevel [Byte0]: 24
7826 23:21:26.763345 [Byte1]: 24
7827 23:21:26.763422
7828 23:21:26.766640 Set Vref, RX VrefLevel [Byte0]: 25
7829 23:21:26.769811 [Byte1]: 25
7830 23:21:26.769897
7831 23:21:26.773334 Set Vref, RX VrefLevel [Byte0]: 26
7832 23:21:26.776136 [Byte1]: 26
7833 23:21:26.780338
7834 23:21:26.780415 Set Vref, RX VrefLevel [Byte0]: 27
7835 23:21:26.783304 [Byte1]: 27
7836 23:21:26.788096
7837 23:21:26.788200 Set Vref, RX VrefLevel [Byte0]: 28
7838 23:21:26.791359 [Byte1]: 28
7839 23:21:26.795542
7840 23:21:26.795648 Set Vref, RX VrefLevel [Byte0]: 29
7841 23:21:26.798745 [Byte1]: 29
7842 23:21:26.803439
7843 23:21:26.803523 Set Vref, RX VrefLevel [Byte0]: 30
7844 23:21:26.806179 [Byte1]: 30
7845 23:21:26.810908
7846 23:21:26.811015 Set Vref, RX VrefLevel [Byte0]: 31
7847 23:21:26.813784 [Byte1]: 31
7848 23:21:26.818501
7849 23:21:26.818601 Set Vref, RX VrefLevel [Byte0]: 32
7850 23:21:26.821381 [Byte1]: 32
7851 23:21:26.825907
7852 23:21:26.826007 Set Vref, RX VrefLevel [Byte0]: 33
7853 23:21:26.829011 [Byte1]: 33
7854 23:21:26.833666
7855 23:21:26.833765 Set Vref, RX VrefLevel [Byte0]: 34
7856 23:21:26.837106 [Byte1]: 34
7857 23:21:26.841015
7858 23:21:26.841117 Set Vref, RX VrefLevel [Byte0]: 35
7859 23:21:26.844475 [Byte1]: 35
7860 23:21:26.849035
7861 23:21:26.849109 Set Vref, RX VrefLevel [Byte0]: 36
7862 23:21:26.851873 [Byte1]: 36
7863 23:21:26.856361
7864 23:21:26.856463 Set Vref, RX VrefLevel [Byte0]: 37
7865 23:21:26.859397 [Byte1]: 37
7866 23:21:26.863790
7867 23:21:26.863871 Set Vref, RX VrefLevel [Byte0]: 38
7868 23:21:26.867263 [Byte1]: 38
7869 23:21:26.871587
7870 23:21:26.871688 Set Vref, RX VrefLevel [Byte0]: 39
7871 23:21:26.875044 [Byte1]: 39
7872 23:21:26.879215
7873 23:21:26.879295 Set Vref, RX VrefLevel [Byte0]: 40
7874 23:21:26.882664 [Byte1]: 40
7875 23:21:26.886742
7876 23:21:26.886848 Set Vref, RX VrefLevel [Byte0]: 41
7877 23:21:26.889788 [Byte1]: 41
7878 23:21:26.894706
7879 23:21:26.894784 Set Vref, RX VrefLevel [Byte0]: 42
7880 23:21:26.897657 [Byte1]: 42
7881 23:21:26.902241
7882 23:21:26.902353 Set Vref, RX VrefLevel [Byte0]: 43
7883 23:21:26.905523 [Byte1]: 43
7884 23:21:26.909797
7885 23:21:26.909895 Set Vref, RX VrefLevel [Byte0]: 44
7886 23:21:26.912808 [Byte1]: 44
7887 23:21:26.917499
7888 23:21:26.917591 Set Vref, RX VrefLevel [Byte0]: 45
7889 23:21:26.920259 [Byte1]: 45
7890 23:21:26.924882
7891 23:21:26.924963 Set Vref, RX VrefLevel [Byte0]: 46
7892 23:21:26.927961 [Byte1]: 46
7893 23:21:26.932547
7894 23:21:26.932627 Set Vref, RX VrefLevel [Byte0]: 47
7895 23:21:26.935955 [Byte1]: 47
7896 23:21:26.939895
7897 23:21:26.939969 Set Vref, RX VrefLevel [Byte0]: 48
7898 23:21:26.943292 [Byte1]: 48
7899 23:21:26.947787
7900 23:21:26.947864 Set Vref, RX VrefLevel [Byte0]: 49
7901 23:21:26.950936 [Byte1]: 49
7902 23:21:26.955604
7903 23:21:26.955680 Set Vref, RX VrefLevel [Byte0]: 50
7904 23:21:26.958409 [Byte1]: 50
7905 23:21:26.963044
7906 23:21:26.963136 Set Vref, RX VrefLevel [Byte0]: 51
7907 23:21:26.966159 [Byte1]: 51
7908 23:21:26.970699
7909 23:21:26.970773 Set Vref, RX VrefLevel [Byte0]: 52
7910 23:21:26.973973 [Byte1]: 52
7911 23:21:26.977883
7912 23:21:26.977987 Set Vref, RX VrefLevel [Byte0]: 53
7913 23:21:26.981256 [Byte1]: 53
7914 23:21:26.985589
7915 23:21:26.985673 Set Vref, RX VrefLevel [Byte0]: 54
7916 23:21:26.989228 [Byte1]: 54
7917 23:21:26.993256
7918 23:21:26.993385 Set Vref, RX VrefLevel [Byte0]: 55
7919 23:21:26.996988 [Byte1]: 55
7920 23:21:27.000961
7921 23:21:27.001060 Set Vref, RX VrefLevel [Byte0]: 56
7922 23:21:27.003961 [Byte1]: 56
7923 23:21:27.008563
7924 23:21:27.008665 Set Vref, RX VrefLevel [Byte0]: 57
7925 23:21:27.011630 [Byte1]: 57
7926 23:21:27.016490
7927 23:21:27.016565 Set Vref, RX VrefLevel [Byte0]: 58
7928 23:21:27.019537 [Byte1]: 58
7929 23:21:27.024008
7930 23:21:27.024098 Set Vref, RX VrefLevel [Byte0]: 59
7931 23:21:27.027551 [Byte1]: 59
7932 23:21:27.031612
7933 23:21:27.031700 Set Vref, RX VrefLevel [Byte0]: 60
7934 23:21:27.034669 [Byte1]: 60
7935 23:21:27.038832
7936 23:21:27.038904 Set Vref, RX VrefLevel [Byte0]: 61
7937 23:21:27.042584 [Byte1]: 61
7938 23:21:27.046762
7939 23:21:27.046837 Set Vref, RX VrefLevel [Byte0]: 62
7940 23:21:27.049900 [Byte1]: 62
7941 23:21:27.054122
7942 23:21:27.054227 Set Vref, RX VrefLevel [Byte0]: 63
7943 23:21:27.057451 [Byte1]: 63
7944 23:21:27.062108
7945 23:21:27.062211 Set Vref, RX VrefLevel [Byte0]: 64
7946 23:21:27.065138 [Byte1]: 64
7947 23:21:27.069330
7948 23:21:27.069427 Set Vref, RX VrefLevel [Byte0]: 65
7949 23:21:27.072770 [Byte1]: 65
7950 23:21:27.076827
7951 23:21:27.076920 Set Vref, RX VrefLevel [Byte0]: 66
7952 23:21:27.080566 [Byte1]: 66
7953 23:21:27.084791
7954 23:21:27.084908 Set Vref, RX VrefLevel [Byte0]: 67
7955 23:21:27.087853 [Byte1]: 67
7956 23:21:27.092604
7957 23:21:27.092729 Set Vref, RX VrefLevel [Byte0]: 68
7958 23:21:27.095385 [Byte1]: 68
7959 23:21:27.099946
7960 23:21:27.100097 Set Vref, RX VrefLevel [Byte0]: 69
7961 23:21:27.103120 [Byte1]: 69
7962 23:21:27.107170
7963 23:21:27.107291 Set Vref, RX VrefLevel [Byte0]: 70
7964 23:21:27.110731 [Byte1]: 70
7965 23:21:27.114799
7966 23:21:27.114915 Set Vref, RX VrefLevel [Byte0]: 71
7967 23:21:27.118066 [Byte1]: 71
7968 23:21:27.122608
7969 23:21:27.122729 Set Vref, RX VrefLevel [Byte0]: 72
7970 23:21:27.126004 [Byte1]: 72
7971 23:21:27.130110
7972 23:21:27.130206 Set Vref, RX VrefLevel [Byte0]: 73
7973 23:21:27.133671 [Byte1]: 73
7974 23:21:27.137906
7975 23:21:27.138003 Set Vref, RX VrefLevel [Byte0]: 74
7976 23:21:27.141479 [Byte1]: 74
7977 23:21:27.145710
7978 23:21:27.145830 Set Vref, RX VrefLevel [Byte0]: 75
7979 23:21:27.149074 [Byte1]: 75
7980 23:21:27.153459
7981 23:21:27.153552 Set Vref, RX VrefLevel [Byte0]: 76
7982 23:21:27.156546 [Byte1]: 76
7983 23:21:27.161002
7984 23:21:27.161107 Final RX Vref Byte 0 = 61 to rank0
7985 23:21:27.163925 Final RX Vref Byte 1 = 63 to rank0
7986 23:21:27.167445 Final RX Vref Byte 0 = 61 to rank1
7987 23:21:27.170725 Final RX Vref Byte 1 = 63 to rank1==
7988 23:21:27.173932 Dram Type= 6, Freq= 0, CH_0, rank 0
7989 23:21:27.177633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7990 23:21:27.180597 ==
7991 23:21:27.180691 DQS Delay:
7992 23:21:27.180829 DQS0 = 0, DQS1 = 0
7993 23:21:27.183970 DQM Delay:
7994 23:21:27.184082 DQM0 = 129, DQM1 = 121
7995 23:21:27.187654 DQ Delay:
7996 23:21:27.191068 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7997 23:21:27.193855 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7998 23:21:27.197985 DQ8 =110, DQ9 =108, DQ10 =122, DQ11 =116
7999 23:21:27.201179 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
8000 23:21:27.201292
8001 23:21:27.201415
8002 23:21:27.201533
8003 23:21:27.205167 [DramC_TX_OE_Calibration] TA2
8004 23:21:27.207442 Original DQ_B0 (3 6) =30, OEN = 27
8005 23:21:27.211230 Original DQ_B1 (3 6) =30, OEN = 27
8006 23:21:27.214068 24, 0x0, End_B0=24 End_B1=24
8007 23:21:27.214188 25, 0x0, End_B0=25 End_B1=25
8008 23:21:27.217785 26, 0x0, End_B0=26 End_B1=26
8009 23:21:27.220913 27, 0x0, End_B0=27 End_B1=27
8010 23:21:27.223807 28, 0x0, End_B0=28 End_B1=28
8011 23:21:27.223928 29, 0x0, End_B0=29 End_B1=29
8012 23:21:27.227199 30, 0x0, End_B0=30 End_B1=30
8013 23:21:27.230507 31, 0x4545, End_B0=30 End_B1=30
8014 23:21:27.233717 Byte0 end_step=30 best_step=27
8015 23:21:27.237292 Byte1 end_step=30 best_step=27
8016 23:21:27.240793 Byte0 TX OE(2T, 0.5T) = (3, 3)
8017 23:21:27.240869 Byte1 TX OE(2T, 0.5T) = (3, 3)
8018 23:21:27.240939
8019 23:21:27.243873
8020 23:21:27.250755 [DQSOSCAuto] RK0, (LSB)MR18= 0x1206, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
8021 23:21:27.253868 CH0 RK0: MR19=303, MR18=1206
8022 23:21:27.260746 CH0_RK0: MR19=0x303, MR18=0x1206, DQSOSC=400, MR23=63, INC=23, DEC=15
8023 23:21:27.260849
8024 23:21:27.264133 ----->DramcWriteLeveling(PI) begin...
8025 23:21:27.264233 ==
8026 23:21:27.267580 Dram Type= 6, Freq= 0, CH_0, rank 1
8027 23:21:27.270742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8028 23:21:27.270859 ==
8029 23:21:27.274388 Write leveling (Byte 0): 32 => 32
8030 23:21:27.277508 Write leveling (Byte 1): 26 => 26
8031 23:21:27.280670 DramcWriteLeveling(PI) end<-----
8032 23:21:27.280765
8033 23:21:27.280855 ==
8034 23:21:27.284162 Dram Type= 6, Freq= 0, CH_0, rank 1
8035 23:21:27.287265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 23:21:27.287360 ==
8037 23:21:27.290696 [Gating] SW mode calibration
8038 23:21:27.297314 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8039 23:21:27.304221 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8040 23:21:27.307818 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 23:21:27.311306 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 23:21:27.317423 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 23:21:27.320676 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8044 23:21:27.324144 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8045 23:21:27.330919 1 4 20 | B1->B0 | 2d2d 3434 | 0 1 | (1 1) (1 1)
8046 23:21:27.334144 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 23:21:27.337652 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 23:21:27.340975 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 23:21:27.347719 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8050 23:21:27.350658 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8051 23:21:27.354165 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8052 23:21:27.360635 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8053 23:21:27.364267 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8054 23:21:27.367257 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8055 23:21:27.373991 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 23:21:27.377576 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 23:21:27.380627 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 23:21:27.387287 1 6 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
8059 23:21:27.390842 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8060 23:21:27.394512 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8061 23:21:27.400854 1 6 20 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8062 23:21:27.403873 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 23:21:27.407242 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 23:21:27.413664 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 23:21:27.417194 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 23:21:27.420720 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 23:21:27.427637 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8068 23:21:27.430743 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8069 23:21:27.433968 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8070 23:21:27.440280 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 23:21:27.443915 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 23:21:27.447427 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 23:21:27.453833 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 23:21:27.457007 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 23:21:27.460417 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 23:21:27.464286 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 23:21:27.470923 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 23:21:27.473780 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 23:21:27.477211 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 23:21:27.483646 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 23:21:27.487196 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 23:21:27.490341 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8083 23:21:27.497274 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8084 23:21:27.497379 Total UI for P1: 0, mck2ui 16
8085 23:21:27.504333 best dqsien dly found for B0: ( 1, 9, 8)
8086 23:21:27.507328 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8087 23:21:27.510928 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8088 23:21:27.517434 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8089 23:21:27.520801 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 23:21:27.524608 Total UI for P1: 0, mck2ui 16
8091 23:21:27.527228 best dqsien dly found for B1: ( 1, 9, 22)
8092 23:21:27.530644 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8093 23:21:27.534029 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
8094 23:21:27.534123
8095 23:21:27.537545 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8096 23:21:27.540539 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
8097 23:21:27.543954 [Gating] SW calibration Done
8098 23:21:27.544052 ==
8099 23:21:27.547097 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 23:21:27.550773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 23:21:27.550874 ==
8102 23:21:27.553922 RX Vref Scan: 0
8103 23:21:27.554019
8104 23:21:27.557599 RX Vref 0 -> 0, step: 1
8105 23:21:27.557705
8106 23:21:27.557797 RX Delay 0 -> 252, step: 8
8107 23:21:27.563973 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8108 23:21:27.567502 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8109 23:21:27.570796 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8110 23:21:27.573986 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8111 23:21:27.577066 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8112 23:21:27.583679 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8113 23:21:27.587351 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8114 23:21:27.590978 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8115 23:21:27.594089 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8116 23:21:27.597393 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8117 23:21:27.603845 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8118 23:21:27.607248 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8119 23:21:27.610817 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8120 23:21:27.613706 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8121 23:21:27.617384 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8122 23:21:27.623746 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8123 23:21:27.623845 ==
8124 23:21:27.627254 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 23:21:27.630894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 23:21:27.630991 ==
8127 23:21:27.631057 DQS Delay:
8128 23:21:27.634269 DQS0 = 0, DQS1 = 0
8129 23:21:27.634376 DQM Delay:
8130 23:21:27.637159 DQM0 = 131, DQM1 = 123
8131 23:21:27.637252 DQ Delay:
8132 23:21:27.640526 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =127
8133 23:21:27.644241 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8134 23:21:27.647067 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8135 23:21:27.650376 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8136 23:21:27.650517
8137 23:21:27.650662
8138 23:21:27.653753 ==
8139 23:21:27.653867 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 23:21:27.660710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 23:21:27.660817 ==
8142 23:21:27.660969
8143 23:21:27.661074
8144 23:21:27.663932 TX Vref Scan disable
8145 23:21:27.664014 == TX Byte 0 ==
8146 23:21:27.667531 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8147 23:21:27.673935 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8148 23:21:27.674041 == TX Byte 1 ==
8149 23:21:27.677456 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8150 23:21:27.683943 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8151 23:21:27.684044 ==
8152 23:21:27.687648 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 23:21:27.690896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 23:21:27.690996 ==
8155 23:21:27.704995
8156 23:21:27.708356 TX Vref early break, caculate TX vref
8157 23:21:27.711895 TX Vref=16, minBit 1, minWin=22, winSum=368
8158 23:21:27.715117 TX Vref=18, minBit 1, minWin=22, winSum=373
8159 23:21:27.718173 TX Vref=20, minBit 1, minWin=23, winSum=387
8160 23:21:27.721916 TX Vref=22, minBit 1, minWin=24, winSum=395
8161 23:21:27.725277 TX Vref=24, minBit 1, minWin=24, winSum=404
8162 23:21:27.731788 TX Vref=26, minBit 4, minWin=24, winSum=412
8163 23:21:27.735171 TX Vref=28, minBit 2, minWin=24, winSum=413
8164 23:21:27.738026 TX Vref=30, minBit 0, minWin=25, winSum=412
8165 23:21:27.741360 TX Vref=32, minBit 1, minWin=23, winSum=406
8166 23:21:27.745055 TX Vref=34, minBit 0, minWin=23, winSum=398
8167 23:21:27.748014 TX Vref=36, minBit 0, minWin=23, winSum=389
8168 23:21:27.755089 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 30
8169 23:21:27.755229
8170 23:21:27.758333 Final TX Range 0 Vref 30
8171 23:21:27.758471
8172 23:21:27.758538 ==
8173 23:21:27.761675 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 23:21:27.765111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 23:21:27.765260 ==
8176 23:21:27.765388
8177 23:21:27.765508
8178 23:21:27.768494 TX Vref Scan disable
8179 23:21:27.775218 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8180 23:21:27.775341 == TX Byte 0 ==
8181 23:21:27.778504 u2DelayCellOfst[0]=14 cells (4 PI)
8182 23:21:27.782083 u2DelayCellOfst[1]=17 cells (5 PI)
8183 23:21:27.784949 u2DelayCellOfst[2]=10 cells (3 PI)
8184 23:21:27.788343 u2DelayCellOfst[3]=10 cells (3 PI)
8185 23:21:27.791680 u2DelayCellOfst[4]=10 cells (3 PI)
8186 23:21:27.795200 u2DelayCellOfst[5]=0 cells (0 PI)
8187 23:21:27.798290 u2DelayCellOfst[6]=21 cells (6 PI)
8188 23:21:27.801873 u2DelayCellOfst[7]=21 cells (6 PI)
8189 23:21:27.804872 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8190 23:21:27.808331 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8191 23:21:27.811934 == TX Byte 1 ==
8192 23:21:27.814803 u2DelayCellOfst[8]=0 cells (0 PI)
8193 23:21:27.814946 u2DelayCellOfst[9]=0 cells (0 PI)
8194 23:21:27.818337 u2DelayCellOfst[10]=3 cells (1 PI)
8195 23:21:27.821536 u2DelayCellOfst[11]=0 cells (0 PI)
8196 23:21:27.824788 u2DelayCellOfst[12]=10 cells (3 PI)
8197 23:21:27.828137 u2DelayCellOfst[13]=10 cells (3 PI)
8198 23:21:27.831430 u2DelayCellOfst[14]=14 cells (4 PI)
8199 23:21:27.834746 u2DelayCellOfst[15]=10 cells (3 PI)
8200 23:21:27.838206 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8201 23:21:27.844970 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8202 23:21:27.845080 DramC Write-DBI on
8203 23:21:27.845173 ==
8204 23:21:27.848051 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 23:21:27.855097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 23:21:27.855176 ==
8207 23:21:27.855243
8208 23:21:27.855303
8209 23:21:27.855360 TX Vref Scan disable
8210 23:21:27.858841 == TX Byte 0 ==
8211 23:21:27.861861 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8212 23:21:27.865877 == TX Byte 1 ==
8213 23:21:27.869324 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8214 23:21:27.869420 DramC Write-DBI off
8215 23:21:27.872403
8216 23:21:27.872478 [DATLAT]
8217 23:21:27.872541 Freq=1600, CH0 RK1
8218 23:21:27.872599
8219 23:21:27.875427 DATLAT Default: 0xf
8220 23:21:27.875522 0, 0xFFFF, sum = 0
8221 23:21:27.878998 1, 0xFFFF, sum = 0
8222 23:21:27.879096 2, 0xFFFF, sum = 0
8223 23:21:27.882240 3, 0xFFFF, sum = 0
8224 23:21:27.882335 4, 0xFFFF, sum = 0
8225 23:21:27.885226 5, 0xFFFF, sum = 0
8226 23:21:27.888877 6, 0xFFFF, sum = 0
8227 23:21:27.888975 7, 0xFFFF, sum = 0
8228 23:21:27.892525 8, 0xFFFF, sum = 0
8229 23:21:27.892596 9, 0xFFFF, sum = 0
8230 23:21:27.895488 10, 0xFFFF, sum = 0
8231 23:21:27.895591 11, 0xFFFF, sum = 0
8232 23:21:27.899202 12, 0xFFFF, sum = 0
8233 23:21:27.899277 13, 0xFFFF, sum = 0
8234 23:21:27.902093 14, 0x0, sum = 1
8235 23:21:27.902196 15, 0x0, sum = 2
8236 23:21:27.905495 16, 0x0, sum = 3
8237 23:21:27.905595 17, 0x0, sum = 4
8238 23:21:27.905696 best_step = 15
8239 23:21:27.908786
8240 23:21:27.908892 ==
8241 23:21:27.912137 Dram Type= 6, Freq= 0, CH_0, rank 1
8242 23:21:27.915541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8243 23:21:27.915633 ==
8244 23:21:27.915698 RX Vref Scan: 0
8245 23:21:27.915758
8246 23:21:27.919005 RX Vref 0 -> 0, step: 1
8247 23:21:27.919074
8248 23:21:27.922334 RX Delay 11 -> 252, step: 4
8249 23:21:27.925440 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8250 23:21:27.928825 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8251 23:21:27.935652 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8252 23:21:27.938581 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8253 23:21:27.942105 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8254 23:21:27.945473 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8255 23:21:27.948829 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8256 23:21:27.955928 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8257 23:21:27.958739 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8258 23:21:27.962344 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8259 23:21:27.965445 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8260 23:21:27.968937 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8261 23:21:27.975901 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8262 23:21:27.979127 iDelay=191, Bit 13, Center 126 (71 ~ 182) 112
8263 23:21:27.982186 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8264 23:21:27.986291 iDelay=191, Bit 15, Center 132 (75 ~ 190) 116
8265 23:21:27.986388 ==
8266 23:21:27.988907 Dram Type= 6, Freq= 0, CH_0, rank 1
8267 23:21:27.995784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8268 23:21:27.995864 ==
8269 23:21:27.995929 DQS Delay:
8270 23:21:27.996004 DQS0 = 0, DQS1 = 0
8271 23:21:27.998769 DQM Delay:
8272 23:21:27.998870 DQM0 = 127, DQM1 = 122
8273 23:21:28.002492 DQ Delay:
8274 23:21:28.005906 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8275 23:21:28.008927 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =134
8276 23:21:28.012432 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8277 23:21:28.015901 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
8278 23:21:28.015999
8279 23:21:28.016100
8280 23:21:28.016187
8281 23:21:28.019209 [DramC_TX_OE_Calibration] TA2
8282 23:21:28.022340 Original DQ_B0 (3 6) =30, OEN = 27
8283 23:21:28.026006 Original DQ_B1 (3 6) =30, OEN = 27
8284 23:21:28.029279 24, 0x0, End_B0=24 End_B1=24
8285 23:21:28.029382 25, 0x0, End_B0=25 End_B1=25
8286 23:21:28.032356 26, 0x0, End_B0=26 End_B1=26
8287 23:21:28.035842 27, 0x0, End_B0=27 End_B1=27
8288 23:21:28.039559 28, 0x0, End_B0=28 End_B1=28
8289 23:21:28.039629 29, 0x0, End_B0=29 End_B1=29
8290 23:21:28.042442 30, 0x0, End_B0=30 End_B1=30
8291 23:21:28.045552 31, 0x4545, End_B0=30 End_B1=30
8292 23:21:28.049218 Byte0 end_step=30 best_step=27
8293 23:21:28.052362 Byte1 end_step=30 best_step=27
8294 23:21:28.055507 Byte0 TX OE(2T, 0.5T) = (3, 3)
8295 23:21:28.055606 Byte1 TX OE(2T, 0.5T) = (3, 3)
8296 23:21:28.055695
8297 23:21:28.058844
8298 23:21:28.065483 [DQSOSCAuto] RK1, (LSB)MR18= 0x1409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8299 23:21:28.069225 CH0 RK1: MR19=303, MR18=1409
8300 23:21:28.075796 CH0_RK1: MR19=0x303, MR18=0x1409, DQSOSC=399, MR23=63, INC=23, DEC=15
8301 23:21:28.079314 [RxdqsGatingPostProcess] freq 1600
8302 23:21:28.082371 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8303 23:21:28.085627 best DQS0 dly(2T, 0.5T) = (1, 1)
8304 23:21:28.088816 best DQS1 dly(2T, 0.5T) = (1, 1)
8305 23:21:28.092410 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8306 23:21:28.095388 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8307 23:21:28.098993 best DQS0 dly(2T, 0.5T) = (1, 1)
8308 23:21:28.102165 best DQS1 dly(2T, 0.5T) = (1, 1)
8309 23:21:28.105324 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8310 23:21:28.109192 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8311 23:21:28.109293 Pre-setting of DQS Precalculation
8312 23:21:28.115767 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8313 23:21:28.115875 ==
8314 23:21:28.119226 Dram Type= 6, Freq= 0, CH_1, rank 0
8315 23:21:28.122194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 23:21:28.122290 ==
8317 23:21:28.128734 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8318 23:21:28.132169 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8319 23:21:28.135888 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8320 23:21:28.142103 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8321 23:21:28.151628 [CA 0] Center 42 (13~71) winsize 59
8322 23:21:28.154990 [CA 1] Center 42 (13~71) winsize 59
8323 23:21:28.158532 [CA 2] Center 37 (8~66) winsize 59
8324 23:21:28.161425 [CA 3] Center 35 (6~65) winsize 60
8325 23:21:28.164875 [CA 4] Center 37 (7~67) winsize 61
8326 23:21:28.168108 [CA 5] Center 36 (7~66) winsize 60
8327 23:21:28.168182
8328 23:21:28.171842 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8329 23:21:28.171912
8330 23:21:28.175252 [CATrainingPosCal] consider 1 rank data
8331 23:21:28.178197 u2DelayCellTimex100 = 275/100 ps
8332 23:21:28.181521 CA0 delay=42 (13~71),Diff = 7 PI (24 cell)
8333 23:21:28.188171 CA1 delay=42 (13~71),Diff = 7 PI (24 cell)
8334 23:21:28.191821 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8335 23:21:28.194973 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8336 23:21:28.198389 CA4 delay=37 (7~67),Diff = 2 PI (7 cell)
8337 23:21:28.201333 CA5 delay=36 (7~66),Diff = 1 PI (3 cell)
8338 23:21:28.201434
8339 23:21:28.204828 CA PerBit enable=1, Macro0, CA PI delay=35
8340 23:21:28.204935
8341 23:21:28.208418 [CBTSetCACLKResult] CA Dly = 35
8342 23:21:28.211704 CS Dly: 9 (0~40)
8343 23:21:28.214908 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8344 23:21:28.217941 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8345 23:21:28.218049 ==
8346 23:21:28.221276 Dram Type= 6, Freq= 0, CH_1, rank 1
8347 23:21:28.225015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 23:21:28.228005 ==
8349 23:21:28.231531 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8350 23:21:28.234569 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8351 23:21:28.241405 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8352 23:21:28.244558 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8353 23:21:28.255060 [CA 0] Center 42 (13~72) winsize 60
8354 23:21:28.258067 [CA 1] Center 43 (14~72) winsize 59
8355 23:21:28.261516 [CA 2] Center 38 (9~67) winsize 59
8356 23:21:28.265135 [CA 3] Center 37 (8~66) winsize 59
8357 23:21:28.268046 [CA 4] Center 37 (8~67) winsize 60
8358 23:21:28.271474 [CA 5] Center 36 (7~66) winsize 60
8359 23:21:28.271554
8360 23:21:28.275018 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8361 23:21:28.275117
8362 23:21:28.277993 [CATrainingPosCal] consider 2 rank data
8363 23:21:28.281391 u2DelayCellTimex100 = 275/100 ps
8364 23:21:28.284830 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8365 23:21:28.291570 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8366 23:21:28.294827 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8367 23:21:28.298513 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8368 23:21:28.301598 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8369 23:21:28.304717 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8370 23:21:28.304828
8371 23:21:28.308255 CA PerBit enable=1, Macro0, CA PI delay=36
8372 23:21:28.308357
8373 23:21:28.311304 [CBTSetCACLKResult] CA Dly = 36
8374 23:21:28.314893 CS Dly: 10 (0~43)
8375 23:21:28.317977 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8376 23:21:28.321339 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8377 23:21:28.321442
8378 23:21:28.324656 ----->DramcWriteLeveling(PI) begin...
8379 23:21:28.324734 ==
8380 23:21:28.328137 Dram Type= 6, Freq= 0, CH_1, rank 0
8381 23:21:28.331537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8382 23:21:28.334716 ==
8383 23:21:28.334789 Write leveling (Byte 0): 26 => 26
8384 23:21:28.338328 Write leveling (Byte 1): 30 => 30
8385 23:21:28.341959 DramcWriteLeveling(PI) end<-----
8386 23:21:28.342057
8387 23:21:28.342148 ==
8388 23:21:28.344834 Dram Type= 6, Freq= 0, CH_1, rank 0
8389 23:21:28.351277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8390 23:21:28.351383 ==
8391 23:21:28.351478 [Gating] SW mode calibration
8392 23:21:28.361165 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8393 23:21:28.364722 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8394 23:21:28.367837 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 23:21:28.374720 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 23:21:28.378208 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 23:21:28.381586 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 23:21:28.388105 1 4 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8399 23:21:28.391772 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 23:21:28.394619 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 23:21:28.401432 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 23:21:28.405140 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 23:21:28.408110 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 23:21:28.415038 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 23:21:28.418501 1 5 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8406 23:21:28.421814 1 5 16 | B1->B0 | 3030 3333 | 0 1 | (1 0) (1 0)
8407 23:21:28.428076 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 23:21:28.431529 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 23:21:28.434672 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 23:21:28.441702 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 23:21:28.444715 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 23:21:28.448208 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 23:21:28.454728 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 23:21:28.458258 1 6 16 | B1->B0 | 3636 3030 | 0 0 | (0 0) (0 0)
8415 23:21:28.461617 1 6 20 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8416 23:21:28.465059 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 23:21:28.471398 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 23:21:28.474851 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 23:21:28.478224 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 23:21:28.484860 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 23:21:28.488171 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8422 23:21:28.491701 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8423 23:21:28.498017 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8424 23:21:28.501623 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 23:21:28.505294 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 23:21:28.511388 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 23:21:28.514717 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 23:21:28.518042 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 23:21:28.525042 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 23:21:28.527984 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 23:21:28.531231 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 23:21:28.537815 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 23:21:28.541366 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 23:21:28.544505 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 23:21:28.551728 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 23:21:28.554819 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 23:21:28.558308 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 23:21:28.561197 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8439 23:21:28.568080 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 23:21:28.571521 Total UI for P1: 0, mck2ui 16
8441 23:21:28.574939 best dqsien dly found for B0: ( 1, 9, 16)
8442 23:21:28.577923 Total UI for P1: 0, mck2ui 16
8443 23:21:28.581609 best dqsien dly found for B1: ( 1, 9, 16)
8444 23:21:28.585123 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8445 23:21:28.588033 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8446 23:21:28.588108
8447 23:21:28.591883 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8448 23:21:28.595108 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8449 23:21:28.598599 [Gating] SW calibration Done
8450 23:21:28.598677 ==
8451 23:21:28.601538 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 23:21:28.605005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 23:21:28.605082 ==
8454 23:21:28.608453 RX Vref Scan: 0
8455 23:21:28.608590
8456 23:21:28.608688 RX Vref 0 -> 0, step: 1
8457 23:21:28.608776
8458 23:21:28.611520 RX Delay 0 -> 252, step: 8
8459 23:21:28.614821 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8460 23:21:28.621720 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8461 23:21:28.624621 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8462 23:21:28.627988 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8463 23:21:28.631333 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8464 23:21:28.635001 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8465 23:21:28.641507 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8466 23:21:28.644882 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8467 23:21:28.648703 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8468 23:21:28.651662 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8469 23:21:28.654747 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8470 23:21:28.661225 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8471 23:21:28.664953 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8472 23:21:28.667873 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8473 23:21:28.671336 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8474 23:21:28.674878 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8475 23:21:28.677931 ==
8476 23:21:28.678040 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 23:21:28.684701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 23:21:28.684801 ==
8479 23:21:28.684902 DQS Delay:
8480 23:21:28.688233 DQS0 = 0, DQS1 = 0
8481 23:21:28.688339 DQM Delay:
8482 23:21:28.691221 DQM0 = 135, DQM1 = 127
8483 23:21:28.691324 DQ Delay:
8484 23:21:28.694595 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8485 23:21:28.697782 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8486 23:21:28.701261 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8487 23:21:28.704853 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8488 23:21:28.704943
8489 23:21:28.705007
8490 23:21:28.705067 ==
8491 23:21:28.707971 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 23:21:28.714554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 23:21:28.714663 ==
8494 23:21:28.714756
8495 23:21:28.714843
8496 23:21:28.714941 TX Vref Scan disable
8497 23:21:28.718382 == TX Byte 0 ==
8498 23:21:28.721416 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8499 23:21:28.724942 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8500 23:21:28.728273 == TX Byte 1 ==
8501 23:21:28.731829 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8502 23:21:28.734829 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8503 23:21:28.738330 ==
8504 23:21:28.741559 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 23:21:28.745025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 23:21:28.745101 ==
8507 23:21:28.758482
8508 23:21:28.761951 TX Vref early break, caculate TX vref
8509 23:21:28.765376 TX Vref=16, minBit 8, minWin=20, winSum=359
8510 23:21:28.768423 TX Vref=18, minBit 8, minWin=21, winSum=370
8511 23:21:28.771834 TX Vref=20, minBit 8, minWin=22, winSum=373
8512 23:21:28.774959 TX Vref=22, minBit 8, minWin=22, winSum=387
8513 23:21:28.778468 TX Vref=24, minBit 5, minWin=24, winSum=399
8514 23:21:28.785001 TX Vref=26, minBit 5, minWin=25, winSum=412
8515 23:21:28.788383 TX Vref=28, minBit 5, minWin=25, winSum=414
8516 23:21:28.791558 TX Vref=30, minBit 5, minWin=25, winSum=415
8517 23:21:28.794933 TX Vref=32, minBit 11, minWin=24, winSum=405
8518 23:21:28.798326 TX Vref=34, minBit 3, minWin=24, winSum=396
8519 23:21:28.802065 TX Vref=36, minBit 6, minWin=23, winSum=388
8520 23:21:28.808869 [TxChooseVref] Worse bit 5, Min win 25, Win sum 415, Final Vref 30
8521 23:21:28.808979
8522 23:21:28.811580 Final TX Range 0 Vref 30
8523 23:21:28.811653
8524 23:21:28.811720 ==
8525 23:21:28.815078 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 23:21:28.818775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 23:21:28.818852 ==
8528 23:21:28.818916
8529 23:21:28.818991
8530 23:21:28.821520 TX Vref Scan disable
8531 23:21:28.828581 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8532 23:21:28.828683 == TX Byte 0 ==
8533 23:21:28.831705 u2DelayCellOfst[0]=17 cells (5 PI)
8534 23:21:28.835159 u2DelayCellOfst[1]=14 cells (4 PI)
8535 23:21:28.838775 u2DelayCellOfst[2]=0 cells (0 PI)
8536 23:21:28.841624 u2DelayCellOfst[3]=7 cells (2 PI)
8537 23:21:28.844846 u2DelayCellOfst[4]=7 cells (2 PI)
8538 23:21:28.848246 u2DelayCellOfst[5]=17 cells (5 PI)
8539 23:21:28.851693 u2DelayCellOfst[6]=17 cells (5 PI)
8540 23:21:28.851772 u2DelayCellOfst[7]=7 cells (2 PI)
8541 23:21:28.858578 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8542 23:21:28.861809 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8543 23:21:28.861889 == TX Byte 1 ==
8544 23:21:28.865473 u2DelayCellOfst[8]=0 cells (0 PI)
8545 23:21:28.868468 u2DelayCellOfst[9]=3 cells (1 PI)
8546 23:21:28.871828 u2DelayCellOfst[10]=7 cells (2 PI)
8547 23:21:28.875347 u2DelayCellOfst[11]=3 cells (1 PI)
8548 23:21:28.878846 u2DelayCellOfst[12]=10 cells (3 PI)
8549 23:21:28.881927 u2DelayCellOfst[13]=14 cells (4 PI)
8550 23:21:28.885230 u2DelayCellOfst[14]=17 cells (5 PI)
8551 23:21:28.888857 u2DelayCellOfst[15]=17 cells (5 PI)
8552 23:21:28.891801 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8553 23:21:28.898292 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8554 23:21:28.898373 DramC Write-DBI on
8555 23:21:28.898477 ==
8556 23:21:28.901730 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 23:21:28.905356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 23:21:28.905435 ==
8559 23:21:28.905500
8560 23:21:28.908274
8561 23:21:28.908400 TX Vref Scan disable
8562 23:21:28.911723 == TX Byte 0 ==
8563 23:21:28.915377 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8564 23:21:28.918679 == TX Byte 1 ==
8565 23:21:28.921824 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8566 23:21:28.921921 DramC Write-DBI off
8567 23:21:28.922011
8568 23:21:28.925127 [DATLAT]
8569 23:21:28.925227 Freq=1600, CH1 RK0
8570 23:21:28.925320
8571 23:21:28.928276 DATLAT Default: 0xf
8572 23:21:28.928352 0, 0xFFFF, sum = 0
8573 23:21:28.931851 1, 0xFFFF, sum = 0
8574 23:21:28.931997 2, 0xFFFF, sum = 0
8575 23:21:28.935257 3, 0xFFFF, sum = 0
8576 23:21:28.935360 4, 0xFFFF, sum = 0
8577 23:21:28.938633 5, 0xFFFF, sum = 0
8578 23:21:28.938714 6, 0xFFFF, sum = 0
8579 23:21:28.941760 7, 0xFFFF, sum = 0
8580 23:21:28.941862 8, 0xFFFF, sum = 0
8581 23:21:28.945073 9, 0xFFFF, sum = 0
8582 23:21:28.948555 10, 0xFFFF, sum = 0
8583 23:21:28.948655 11, 0xFFFF, sum = 0
8584 23:21:28.951904 12, 0xFFFF, sum = 0
8585 23:21:28.951987 13, 0xFFFF, sum = 0
8586 23:21:28.955333 14, 0x0, sum = 1
8587 23:21:28.955453 15, 0x0, sum = 2
8588 23:21:28.958738 16, 0x0, sum = 3
8589 23:21:28.958856 17, 0x0, sum = 4
8590 23:21:28.958922 best_step = 15
8591 23:21:28.958982
8592 23:21:28.961802 ==
8593 23:21:28.965246 Dram Type= 6, Freq= 0, CH_1, rank 0
8594 23:21:28.968959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8595 23:21:28.969040 ==
8596 23:21:28.969104 RX Vref Scan: 1
8597 23:21:28.969163
8598 23:21:28.972162 Set Vref Range= 24 -> 127
8599 23:21:28.972253
8600 23:21:28.975792 RX Vref 24 -> 127, step: 1
8601 23:21:28.975873
8602 23:21:28.978975 RX Delay 11 -> 252, step: 4
8603 23:21:28.979055
8604 23:21:28.982007 Set Vref, RX VrefLevel [Byte0]: 24
8605 23:21:28.985745 [Byte1]: 24
8606 23:21:28.985850
8607 23:21:28.988546 Set Vref, RX VrefLevel [Byte0]: 25
8608 23:21:28.991706 [Byte1]: 25
8609 23:21:28.991792
8610 23:21:28.995200 Set Vref, RX VrefLevel [Byte0]: 26
8611 23:21:28.998709 [Byte1]: 26
8612 23:21:29.001764
8613 23:21:29.001862 Set Vref, RX VrefLevel [Byte0]: 27
8614 23:21:29.005234 [Byte1]: 27
8615 23:21:29.009284
8616 23:21:29.009384 Set Vref, RX VrefLevel [Byte0]: 28
8617 23:21:29.012782 [Byte1]: 28
8618 23:21:29.016917
8619 23:21:29.017027 Set Vref, RX VrefLevel [Byte0]: 29
8620 23:21:29.020710 [Byte1]: 29
8621 23:21:29.024828
8622 23:21:29.024929 Set Vref, RX VrefLevel [Byte0]: 30
8623 23:21:29.028166 [Byte1]: 30
8624 23:21:29.032241
8625 23:21:29.032356 Set Vref, RX VrefLevel [Byte0]: 31
8626 23:21:29.035790 [Byte1]: 31
8627 23:21:29.039668
8628 23:21:29.039745 Set Vref, RX VrefLevel [Byte0]: 32
8629 23:21:29.043132 [Byte1]: 32
8630 23:21:29.047726
8631 23:21:29.047818 Set Vref, RX VrefLevel [Byte0]: 33
8632 23:21:29.050785 [Byte1]: 33
8633 23:21:29.055763
8634 23:21:29.055869 Set Vref, RX VrefLevel [Byte0]: 34
8635 23:21:29.058196 [Byte1]: 34
8636 23:21:29.062998
8637 23:21:29.063101 Set Vref, RX VrefLevel [Byte0]: 35
8638 23:21:29.065983 [Byte1]: 35
8639 23:21:29.070613
8640 23:21:29.070709 Set Vref, RX VrefLevel [Byte0]: 36
8641 23:21:29.073654 [Byte1]: 36
8642 23:21:29.078317
8643 23:21:29.078457 Set Vref, RX VrefLevel [Byte0]: 37
8644 23:21:29.081368 [Byte1]: 37
8645 23:21:29.085729
8646 23:21:29.085827 Set Vref, RX VrefLevel [Byte0]: 38
8647 23:21:29.089423 [Byte1]: 38
8648 23:21:29.093397
8649 23:21:29.093493 Set Vref, RX VrefLevel [Byte0]: 39
8650 23:21:29.096367 [Byte1]: 39
8651 23:21:29.101195
8652 23:21:29.101275 Set Vref, RX VrefLevel [Byte0]: 40
8653 23:21:29.104303 [Byte1]: 40
8654 23:21:29.108688
8655 23:21:29.108778 Set Vref, RX VrefLevel [Byte0]: 41
8656 23:21:29.111619 [Byte1]: 41
8657 23:21:29.116717
8658 23:21:29.116816 Set Vref, RX VrefLevel [Byte0]: 42
8659 23:21:29.119567 [Byte1]: 42
8660 23:21:29.124070
8661 23:21:29.124145 Set Vref, RX VrefLevel [Byte0]: 43
8662 23:21:29.126858 [Byte1]: 43
8663 23:21:29.131485
8664 23:21:29.131561 Set Vref, RX VrefLevel [Byte0]: 44
8665 23:21:29.134469 [Byte1]: 44
8666 23:21:29.138947
8667 23:21:29.139025 Set Vref, RX VrefLevel [Byte0]: 45
8668 23:21:29.142245 [Byte1]: 45
8669 23:21:29.146832
8670 23:21:29.146933 Set Vref, RX VrefLevel [Byte0]: 46
8671 23:21:29.149911 [Byte1]: 46
8672 23:21:29.153982
8673 23:21:29.157194 Set Vref, RX VrefLevel [Byte0]: 47
8674 23:21:29.157290 [Byte1]: 47
8675 23:21:29.161920
8676 23:21:29.162017 Set Vref, RX VrefLevel [Byte0]: 48
8677 23:21:29.164855 [Byte1]: 48
8678 23:21:29.169134
8679 23:21:29.169214 Set Vref, RX VrefLevel [Byte0]: 49
8680 23:21:29.172697 [Byte1]: 49
8681 23:21:29.176807
8682 23:21:29.176902 Set Vref, RX VrefLevel [Byte0]: 50
8683 23:21:29.180342 [Byte1]: 50
8684 23:21:29.184418
8685 23:21:29.184534 Set Vref, RX VrefLevel [Byte0]: 51
8686 23:21:29.187961 [Byte1]: 51
8687 23:21:29.192597
8688 23:21:29.192693 Set Vref, RX VrefLevel [Byte0]: 52
8689 23:21:29.195351 [Byte1]: 52
8690 23:21:29.200253
8691 23:21:29.200350 Set Vref, RX VrefLevel [Byte0]: 53
8692 23:21:29.202953 [Byte1]: 53
8693 23:21:29.207571
8694 23:21:29.207652 Set Vref, RX VrefLevel [Byte0]: 54
8695 23:21:29.211305 [Byte1]: 54
8696 23:21:29.215113
8697 23:21:29.215208 Set Vref, RX VrefLevel [Byte0]: 55
8698 23:21:29.218192 [Byte1]: 55
8699 23:21:29.222901
8700 23:21:29.222997 Set Vref, RX VrefLevel [Byte0]: 56
8701 23:21:29.225904 [Byte1]: 56
8702 23:21:29.230481
8703 23:21:29.230569 Set Vref, RX VrefLevel [Byte0]: 57
8704 23:21:29.233936 [Byte1]: 57
8705 23:21:29.238094
8706 23:21:29.238176 Set Vref, RX VrefLevel [Byte0]: 58
8707 23:21:29.240916 [Byte1]: 58
8708 23:21:29.245487
8709 23:21:29.245569 Set Vref, RX VrefLevel [Byte0]: 59
8710 23:21:29.248543 [Byte1]: 59
8711 23:21:29.253322
8712 23:21:29.253404 Set Vref, RX VrefLevel [Byte0]: 60
8713 23:21:29.256857 [Byte1]: 60
8714 23:21:29.261073
8715 23:21:29.261155 Set Vref, RX VrefLevel [Byte0]: 61
8716 23:21:29.264028 [Byte1]: 61
8717 23:21:29.268096
8718 23:21:29.268178 Set Vref, RX VrefLevel [Byte0]: 62
8719 23:21:29.271983 [Byte1]: 62
8720 23:21:29.275870
8721 23:21:29.275951 Set Vref, RX VrefLevel [Byte0]: 63
8722 23:21:29.279461 [Byte1]: 63
8723 23:21:29.284113
8724 23:21:29.284195 Set Vref, RX VrefLevel [Byte0]: 64
8725 23:21:29.289942 [Byte1]: 64
8726 23:21:29.290027
8727 23:21:29.293524 Set Vref, RX VrefLevel [Byte0]: 65
8728 23:21:29.296830 [Byte1]: 65
8729 23:21:29.296934
8730 23:21:29.299856 Set Vref, RX VrefLevel [Byte0]: 66
8731 23:21:29.303214 [Byte1]: 66
8732 23:21:29.303291
8733 23:21:29.306945 Set Vref, RX VrefLevel [Byte0]: 67
8734 23:21:29.311216 [Byte1]: 67
8735 23:21:29.314093
8736 23:21:29.314201 Set Vref, RX VrefLevel [Byte0]: 68
8737 23:21:29.317566 [Byte1]: 68
8738 23:21:29.321745
8739 23:21:29.321854 Set Vref, RX VrefLevel [Byte0]: 69
8740 23:21:29.324736 [Byte1]: 69
8741 23:21:29.329367
8742 23:21:29.329483 Set Vref, RX VrefLevel [Byte0]: 70
8743 23:21:29.332460 [Byte1]: 70
8744 23:21:29.337142
8745 23:21:29.337257 Set Vref, RX VrefLevel [Byte0]: 71
8746 23:21:29.339910 [Byte1]: 71
8747 23:21:29.344765
8748 23:21:29.344862 Set Vref, RX VrefLevel [Byte0]: 72
8749 23:21:29.347732 [Byte1]: 72
8750 23:21:29.351875
8751 23:21:29.351979 Set Vref, RX VrefLevel [Byte0]: 73
8752 23:21:29.355152 [Byte1]: 73
8753 23:21:29.359626
8754 23:21:29.359711 Set Vref, RX VrefLevel [Byte0]: 74
8755 23:21:29.362829 [Byte1]: 74
8756 23:21:29.367270
8757 23:21:29.367355 Final RX Vref Byte 0 = 56 to rank0
8758 23:21:29.370634 Final RX Vref Byte 1 = 58 to rank0
8759 23:21:29.373995 Final RX Vref Byte 0 = 56 to rank1
8760 23:21:29.377114 Final RX Vref Byte 1 = 58 to rank1==
8761 23:21:29.380657 Dram Type= 6, Freq= 0, CH_1, rank 0
8762 23:21:29.386965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8763 23:21:29.387077 ==
8764 23:21:29.387182 DQS Delay:
8765 23:21:29.387282 DQS0 = 0, DQS1 = 0
8766 23:21:29.390790 DQM Delay:
8767 23:21:29.390907 DQM0 = 130, DQM1 = 124
8768 23:21:29.393702 DQ Delay:
8769 23:21:29.397068 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8770 23:21:29.400338 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =126
8771 23:21:29.403818 DQ8 =110, DQ9 =114, DQ10 =128, DQ11 =118
8772 23:21:29.406932 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8773 23:21:29.407020
8774 23:21:29.407109
8775 23:21:29.407192
8776 23:21:29.410553 [DramC_TX_OE_Calibration] TA2
8777 23:21:29.413776 Original DQ_B0 (3 6) =30, OEN = 27
8778 23:21:29.416871 Original DQ_B1 (3 6) =30, OEN = 27
8779 23:21:29.420493 24, 0x0, End_B0=24 End_B1=24
8780 23:21:29.420664 25, 0x0, End_B0=25 End_B1=25
8781 23:21:29.423904 26, 0x0, End_B0=26 End_B1=26
8782 23:21:29.427373 27, 0x0, End_B0=27 End_B1=27
8783 23:21:29.430280 28, 0x0, End_B0=28 End_B1=28
8784 23:21:29.430367 29, 0x0, End_B0=29 End_B1=29
8785 23:21:29.433777 30, 0x0, End_B0=30 End_B1=30
8786 23:21:29.437445 31, 0x4141, End_B0=30 End_B1=30
8787 23:21:29.440324 Byte0 end_step=30 best_step=27
8788 23:21:29.443779 Byte1 end_step=30 best_step=27
8789 23:21:29.447175 Byte0 TX OE(2T, 0.5T) = (3, 3)
8790 23:21:29.447256 Byte1 TX OE(2T, 0.5T) = (3, 3)
8791 23:21:29.447339
8792 23:21:29.450836
8793 23:21:29.457145 [DQSOSCAuto] RK0, (LSB)MR18= 0x14fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 399 ps
8794 23:21:29.460682 CH1 RK0: MR19=302, MR18=14FE
8795 23:21:29.467353 CH1_RK0: MR19=0x302, MR18=0x14FE, DQSOSC=399, MR23=63, INC=23, DEC=15
8796 23:21:29.467443
8797 23:21:29.470548 ----->DramcWriteLeveling(PI) begin...
8798 23:21:29.470653 ==
8799 23:21:29.474068 Dram Type= 6, Freq= 0, CH_1, rank 1
8800 23:21:29.477132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 23:21:29.477236 ==
8802 23:21:29.480860 Write leveling (Byte 0): 25 => 25
8803 23:21:29.483672 Write leveling (Byte 1): 28 => 28
8804 23:21:29.487241 DramcWriteLeveling(PI) end<-----
8805 23:21:29.487313
8806 23:21:29.487375 ==
8807 23:21:29.490720 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 23:21:29.493953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 23:21:29.494061 ==
8810 23:21:29.497601 [Gating] SW mode calibration
8811 23:21:29.503826 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8812 23:21:29.510225 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8813 23:21:29.513852 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 23:21:29.517135 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 23:21:29.523643 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8816 23:21:29.527123 1 4 12 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
8817 23:21:29.530371 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 23:21:29.537609 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 23:21:29.540439 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 23:21:29.543480 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8821 23:21:29.550274 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8822 23:21:29.553703 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8823 23:21:29.557365 1 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
8824 23:21:29.563887 1 5 12 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
8825 23:21:29.566983 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 23:21:29.570405 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 23:21:29.573845 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 23:21:29.580710 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 23:21:29.583834 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 23:21:29.587160 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 23:21:29.593793 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
8832 23:21:29.597052 1 6 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
8833 23:21:29.600540 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 23:21:29.607088 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 23:21:29.610448 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 23:21:29.613684 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 23:21:29.620393 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 23:21:29.624241 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 23:21:29.627128 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8840 23:21:29.634084 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8841 23:21:29.637515 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 23:21:29.640474 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 23:21:29.647659 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 23:21:29.650515 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 23:21:29.653618 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 23:21:29.656978 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 23:21:29.664053 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 23:21:29.667015 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 23:21:29.670627 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 23:21:29.677203 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 23:21:29.680284 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 23:21:29.683243 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 23:21:29.690301 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 23:21:29.693274 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8855 23:21:29.696720 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8856 23:21:29.703717 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8857 23:21:29.707014 Total UI for P1: 0, mck2ui 16
8858 23:21:29.710226 best dqsien dly found for B0: ( 1, 9, 6)
8859 23:21:29.713496 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8860 23:21:29.716635 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8861 23:21:29.720020 Total UI for P1: 0, mck2ui 16
8862 23:21:29.723487 best dqsien dly found for B1: ( 1, 9, 14)
8863 23:21:29.727217 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8864 23:21:29.730333 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8865 23:21:29.730458
8866 23:21:29.736753 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8867 23:21:29.740049 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8868 23:21:29.743351 [Gating] SW calibration Done
8869 23:21:29.743429 ==
8870 23:21:29.747074 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 23:21:29.750546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 23:21:29.750622 ==
8873 23:21:29.750685 RX Vref Scan: 0
8874 23:21:29.750752
8875 23:21:29.753423 RX Vref 0 -> 0, step: 1
8876 23:21:29.753498
8877 23:21:29.756932 RX Delay 0 -> 252, step: 8
8878 23:21:29.760579 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8879 23:21:29.763414 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8880 23:21:29.766771 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8881 23:21:29.773409 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8882 23:21:29.776789 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8883 23:21:29.780449 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8884 23:21:29.783359 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8885 23:21:29.786993 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8886 23:21:29.793410 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8887 23:21:29.796979 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8888 23:21:29.800341 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8889 23:21:29.803740 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8890 23:21:29.806810 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8891 23:21:29.813778 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8892 23:21:29.816834 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8893 23:21:29.820090 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8894 23:21:29.820176 ==
8895 23:21:29.823420 Dram Type= 6, Freq= 0, CH_1, rank 1
8896 23:21:29.827052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8897 23:21:29.827137 ==
8898 23:21:29.830324 DQS Delay:
8899 23:21:29.830435 DQS0 = 0, DQS1 = 0
8900 23:21:29.833951 DQM Delay:
8901 23:21:29.834035 DQM0 = 132, DQM1 = 129
8902 23:21:29.834146 DQ Delay:
8903 23:21:29.837161 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8904 23:21:29.843950 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8905 23:21:29.846929 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8906 23:21:29.850252 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8907 23:21:29.850360
8908 23:21:29.850472
8909 23:21:29.850552 ==
8910 23:21:29.854044 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 23:21:29.857006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 23:21:29.857092 ==
8913 23:21:29.857178
8914 23:21:29.857259
8915 23:21:29.860603 TX Vref Scan disable
8916 23:21:29.863391 == TX Byte 0 ==
8917 23:21:29.866820 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8918 23:21:29.870209 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8919 23:21:29.873959 == TX Byte 1 ==
8920 23:21:29.876928 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8921 23:21:29.880360 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8922 23:21:29.880442 ==
8923 23:21:29.883291 Dram Type= 6, Freq= 0, CH_1, rank 1
8924 23:21:29.886839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8925 23:21:29.886921 ==
8926 23:21:29.902434
8927 23:21:29.905774 TX Vref early break, caculate TX vref
8928 23:21:29.908817 TX Vref=16, minBit 8, minWin=22, winSum=376
8929 23:21:29.912535 TX Vref=18, minBit 8, minWin=22, winSum=383
8930 23:21:29.915599 TX Vref=20, minBit 8, minWin=23, winSum=391
8931 23:21:29.918749 TX Vref=22, minBit 8, minWin=23, winSum=404
8932 23:21:29.922253 TX Vref=24, minBit 11, minWin=24, winSum=412
8933 23:21:29.928846 TX Vref=26, minBit 9, minWin=24, winSum=417
8934 23:21:29.932256 TX Vref=28, minBit 5, minWin=25, winSum=419
8935 23:21:29.935692 TX Vref=30, minBit 15, minWin=25, winSum=422
8936 23:21:29.939440 TX Vref=32, minBit 0, minWin=25, winSum=414
8937 23:21:29.942287 TX Vref=34, minBit 0, minWin=24, winSum=401
8938 23:21:29.945252 TX Vref=36, minBit 0, minWin=24, winSum=394
8939 23:21:29.952363 [TxChooseVref] Worse bit 15, Min win 25, Win sum 422, Final Vref 30
8940 23:21:29.952478
8941 23:21:29.955602 Final TX Range 0 Vref 30
8942 23:21:29.955693
8943 23:21:29.955758 ==
8944 23:21:29.959039 Dram Type= 6, Freq= 0, CH_1, rank 1
8945 23:21:29.962072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8946 23:21:29.962173 ==
8947 23:21:29.962272
8948 23:21:29.962360
8949 23:21:29.965534 TX Vref Scan disable
8950 23:21:29.972165 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8951 23:21:29.972266 == TX Byte 0 ==
8952 23:21:29.975485 u2DelayCellOfst[0]=17 cells (5 PI)
8953 23:21:29.978745 u2DelayCellOfst[1]=14 cells (4 PI)
8954 23:21:29.982192 u2DelayCellOfst[2]=0 cells (0 PI)
8955 23:21:29.985983 u2DelayCellOfst[3]=7 cells (2 PI)
8956 23:21:29.988804 u2DelayCellOfst[4]=10 cells (3 PI)
8957 23:21:29.992470 u2DelayCellOfst[5]=17 cells (5 PI)
8958 23:21:29.995471 u2DelayCellOfst[6]=17 cells (5 PI)
8959 23:21:29.998889 u2DelayCellOfst[7]=7 cells (2 PI)
8960 23:21:30.002489 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8961 23:21:30.005570 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8962 23:21:30.009176 == TX Byte 1 ==
8963 23:21:30.009257 u2DelayCellOfst[8]=0 cells (0 PI)
8964 23:21:30.012723 u2DelayCellOfst[9]=7 cells (2 PI)
8965 23:21:30.016189 u2DelayCellOfst[10]=10 cells (3 PI)
8966 23:21:30.018859 u2DelayCellOfst[11]=7 cells (2 PI)
8967 23:21:30.021933 u2DelayCellOfst[12]=14 cells (4 PI)
8968 23:21:30.025511 u2DelayCellOfst[13]=14 cells (4 PI)
8969 23:21:30.028807 u2DelayCellOfst[14]=17 cells (5 PI)
8970 23:21:30.032006 u2DelayCellOfst[15]=14 cells (4 PI)
8971 23:21:30.035729 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8972 23:21:30.041888 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8973 23:21:30.041975 DramC Write-DBI on
8974 23:21:30.042042 ==
8975 23:21:30.045336 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 23:21:30.048852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 23:21:30.052121 ==
8978 23:21:30.052203
8979 23:21:30.052268
8980 23:21:30.052327 TX Vref Scan disable
8981 23:21:30.055943 == TX Byte 0 ==
8982 23:21:30.058922 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8983 23:21:30.062616 == TX Byte 1 ==
8984 23:21:30.065751 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8985 23:21:30.069041 DramC Write-DBI off
8986 23:21:30.069138
8987 23:21:30.069207 [DATLAT]
8988 23:21:30.069275 Freq=1600, CH1 RK1
8989 23:21:30.069334
8990 23:21:30.072497 DATLAT Default: 0xf
8991 23:21:30.072577 0, 0xFFFF, sum = 0
8992 23:21:30.076015 1, 0xFFFF, sum = 0
8993 23:21:30.076116 2, 0xFFFF, sum = 0
8994 23:21:30.079028 3, 0xFFFF, sum = 0
8995 23:21:30.079117 4, 0xFFFF, sum = 0
8996 23:21:30.082375 5, 0xFFFF, sum = 0
8997 23:21:30.085842 6, 0xFFFF, sum = 0
8998 23:21:30.085928 7, 0xFFFF, sum = 0
8999 23:21:30.089380 8, 0xFFFF, sum = 0
9000 23:21:30.089464 9, 0xFFFF, sum = 0
9001 23:21:30.092453 10, 0xFFFF, sum = 0
9002 23:21:30.092555 11, 0xFFFF, sum = 0
9003 23:21:30.095942 12, 0xFFFF, sum = 0
9004 23:21:30.096095 13, 0xFFFF, sum = 0
9005 23:21:30.098820 14, 0x0, sum = 1
9006 23:21:30.098905 15, 0x0, sum = 2
9007 23:21:30.102549 16, 0x0, sum = 3
9008 23:21:30.102678 17, 0x0, sum = 4
9009 23:21:30.105847 best_step = 15
9010 23:21:30.105960
9011 23:21:30.106038 ==
9012 23:21:30.109426 Dram Type= 6, Freq= 0, CH_1, rank 1
9013 23:21:30.112366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9014 23:21:30.112450 ==
9015 23:21:30.112515 RX Vref Scan: 0
9016 23:21:30.112574
9017 23:21:30.115913 RX Vref 0 -> 0, step: 1
9018 23:21:30.115988
9019 23:21:30.119344 RX Delay 11 -> 252, step: 4
9020 23:21:30.122759 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
9021 23:21:30.129148 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9022 23:21:30.132833 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9023 23:21:30.135787 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9024 23:21:30.139289 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
9025 23:21:30.142956 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9026 23:21:30.145709 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9027 23:21:30.152769 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9028 23:21:30.155591 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9029 23:21:30.159331 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9030 23:21:30.162482 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9031 23:21:30.166118 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
9032 23:21:30.172471 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9033 23:21:30.175859 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9034 23:21:30.179694 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
9035 23:21:30.182845 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9036 23:21:30.182923 ==
9037 23:21:30.185835 Dram Type= 6, Freq= 0, CH_1, rank 1
9038 23:21:30.192959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9039 23:21:30.193071 ==
9040 23:21:30.193140 DQS Delay:
9041 23:21:30.193237 DQS0 = 0, DQS1 = 0
9042 23:21:30.196489 DQM Delay:
9043 23:21:30.196576 DQM0 = 129, DQM1 = 126
9044 23:21:30.199403 DQ Delay:
9045 23:21:30.202828 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
9046 23:21:30.205849 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =124
9047 23:21:30.209245 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9048 23:21:30.212401 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
9049 23:21:30.212508
9050 23:21:30.212616
9051 23:21:30.212713
9052 23:21:30.216010 [DramC_TX_OE_Calibration] TA2
9053 23:21:30.219591 Original DQ_B0 (3 6) =30, OEN = 27
9054 23:21:30.222335 Original DQ_B1 (3 6) =30, OEN = 27
9055 23:21:30.225877 24, 0x0, End_B0=24 End_B1=24
9056 23:21:30.225958 25, 0x0, End_B0=25 End_B1=25
9057 23:21:30.229383 26, 0x0, End_B0=26 End_B1=26
9058 23:21:30.232842 27, 0x0, End_B0=27 End_B1=27
9059 23:21:30.235911 28, 0x0, End_B0=28 End_B1=28
9060 23:21:30.235989 29, 0x0, End_B0=29 End_B1=29
9061 23:21:30.239409 30, 0x0, End_B0=30 End_B1=30
9062 23:21:30.242921 31, 0x4545, End_B0=30 End_B1=30
9063 23:21:30.245892 Byte0 end_step=30 best_step=27
9064 23:21:30.248972 Byte1 end_step=30 best_step=27
9065 23:21:30.252452 Byte0 TX OE(2T, 0.5T) = (3, 3)
9066 23:21:30.252532 Byte1 TX OE(2T, 0.5T) = (3, 3)
9067 23:21:30.255969
9068 23:21:30.256044
9069 23:21:30.262522 [DQSOSCAuto] RK1, (LSB)MR18= 0xd13, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
9070 23:21:30.265899 CH1 RK1: MR19=303, MR18=D13
9071 23:21:30.272421 CH1_RK1: MR19=0x303, MR18=0xD13, DQSOSC=400, MR23=63, INC=23, DEC=15
9072 23:21:30.275849 [RxdqsGatingPostProcess] freq 1600
9073 23:21:30.279011 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9074 23:21:30.282479 best DQS0 dly(2T, 0.5T) = (1, 1)
9075 23:21:30.285805 best DQS1 dly(2T, 0.5T) = (1, 1)
9076 23:21:30.289417 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9077 23:21:30.292901 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9078 23:21:30.296611 best DQS0 dly(2T, 0.5T) = (1, 1)
9079 23:21:30.298836 best DQS1 dly(2T, 0.5T) = (1, 1)
9080 23:21:30.302153 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9081 23:21:30.305475 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9082 23:21:30.305560 Pre-setting of DQS Precalculation
9083 23:21:30.312440 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9084 23:21:30.319088 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9085 23:21:30.326110 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9086 23:21:30.326189
9087 23:21:30.326261
9088 23:21:30.329417 [Calibration Summary] 3200 Mbps
9089 23:21:30.332256 CH 0, Rank 0
9090 23:21:30.332336 SW Impedance : PASS
9091 23:21:30.335778 DUTY Scan : NO K
9092 23:21:30.339169 ZQ Calibration : PASS
9093 23:21:30.339273 Jitter Meter : NO K
9094 23:21:30.342794 CBT Training : PASS
9095 23:21:30.342867 Write leveling : PASS
9096 23:21:30.345798 RX DQS gating : PASS
9097 23:21:30.349086 RX DQ/DQS(RDDQC) : PASS
9098 23:21:30.349163 TX DQ/DQS : PASS
9099 23:21:30.352882 RX DATLAT : PASS
9100 23:21:30.355781 RX DQ/DQS(Engine): PASS
9101 23:21:30.355877 TX OE : PASS
9102 23:21:30.359104 All Pass.
9103 23:21:30.359184
9104 23:21:30.359248 CH 0, Rank 1
9105 23:21:30.362557 SW Impedance : PASS
9106 23:21:30.362634 DUTY Scan : NO K
9107 23:21:30.365995 ZQ Calibration : PASS
9108 23:21:30.369577 Jitter Meter : NO K
9109 23:21:30.369685 CBT Training : PASS
9110 23:21:30.373144 Write leveling : PASS
9111 23:21:30.376201 RX DQS gating : PASS
9112 23:21:30.376277 RX DQ/DQS(RDDQC) : PASS
9113 23:21:30.379060 TX DQ/DQS : PASS
9114 23:21:30.379139 RX DATLAT : PASS
9115 23:21:30.382574 RX DQ/DQS(Engine): PASS
9116 23:21:30.385941 TX OE : PASS
9117 23:21:30.386018 All Pass.
9118 23:21:30.386082
9119 23:21:30.386140 CH 1, Rank 0
9120 23:21:30.389180 SW Impedance : PASS
9121 23:21:30.392688 DUTY Scan : NO K
9122 23:21:30.392770 ZQ Calibration : PASS
9123 23:21:30.396239 Jitter Meter : NO K
9124 23:21:30.399269 CBT Training : PASS
9125 23:21:30.399343 Write leveling : PASS
9126 23:21:30.402672 RX DQS gating : PASS
9127 23:21:30.405914 RX DQ/DQS(RDDQC) : PASS
9128 23:21:30.405998 TX DQ/DQS : PASS
9129 23:21:30.409296 RX DATLAT : PASS
9130 23:21:30.412716 RX DQ/DQS(Engine): PASS
9131 23:21:30.412792 TX OE : PASS
9132 23:21:30.412864 All Pass.
9133 23:21:30.415864
9134 23:21:30.416011 CH 1, Rank 1
9135 23:21:30.419459 SW Impedance : PASS
9136 23:21:30.419541 DUTY Scan : NO K
9137 23:21:30.422431 ZQ Calibration : PASS
9138 23:21:30.422522 Jitter Meter : NO K
9139 23:21:30.426121 CBT Training : PASS
9140 23:21:30.429502 Write leveling : PASS
9141 23:21:30.429603 RX DQS gating : PASS
9142 23:21:30.432696 RX DQ/DQS(RDDQC) : PASS
9143 23:21:30.435945 TX DQ/DQS : PASS
9144 23:21:30.436020 RX DATLAT : PASS
9145 23:21:30.439220 RX DQ/DQS(Engine): PASS
9146 23:21:30.442718 TX OE : PASS
9147 23:21:30.442801 All Pass.
9148 23:21:30.442865
9149 23:21:30.446190 DramC Write-DBI on
9150 23:21:30.446262 PER_BANK_REFRESH: Hybrid Mode
9151 23:21:30.449190 TX_TRACKING: ON
9152 23:21:30.456342 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9153 23:21:30.466118 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9154 23:21:30.472971 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9155 23:21:30.475971 [FAST_K] Save calibration result to emmc
9156 23:21:30.479289 sync common calibartion params.
9157 23:21:30.482662 sync cbt_mode0:1, 1:1
9158 23:21:30.482745 dram_init: ddr_geometry: 2
9159 23:21:30.486150 dram_init: ddr_geometry: 2
9160 23:21:30.489151 dram_init: ddr_geometry: 2
9161 23:21:30.489228 0:dram_rank_size:100000000
9162 23:21:30.492439 1:dram_rank_size:100000000
9163 23:21:30.499545 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9164 23:21:30.502363 DFS_SHUFFLE_HW_MODE: ON
9165 23:21:30.505743 dramc_set_vcore_voltage set vcore to 725000
9166 23:21:30.505835 Read voltage for 1600, 0
9167 23:21:30.509413 Vio18 = 0
9168 23:21:30.509499 Vcore = 725000
9169 23:21:30.509594 Vdram = 0
9170 23:21:30.512881 Vddq = 0
9171 23:21:30.512976 Vmddr = 0
9172 23:21:30.516074 switch to 3200 Mbps bootup
9173 23:21:30.516154 [DramcRunTimeConfig]
9174 23:21:30.516241 PHYPLL
9175 23:21:30.519467 DPM_CONTROL_AFTERK: ON
9176 23:21:30.519554 PER_BANK_REFRESH: ON
9177 23:21:30.522864 REFRESH_OVERHEAD_REDUCTION: ON
9178 23:21:30.526192 CMD_PICG_NEW_MODE: OFF
9179 23:21:30.526271 XRTWTW_NEW_MODE: ON
9180 23:21:30.529188 XRTRTR_NEW_MODE: ON
9181 23:21:30.529274 TX_TRACKING: ON
9182 23:21:30.533153 RDSEL_TRACKING: OFF
9183 23:21:30.536322 DQS Precalculation for DVFS: ON
9184 23:21:30.536402 RX_TRACKING: OFF
9185 23:21:30.539579 HW_GATING DBG: ON
9186 23:21:30.539660 ZQCS_ENABLE_LP4: ON
9187 23:21:30.542595 RX_PICG_NEW_MODE: ON
9188 23:21:30.546182 TX_PICG_NEW_MODE: ON
9189 23:21:30.546264 ENABLE_RX_DCM_DPHY: ON
9190 23:21:30.549188 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9191 23:21:30.552785 DUMMY_READ_FOR_TRACKING: OFF
9192 23:21:30.556157 !!! SPM_CONTROL_AFTERK: OFF
9193 23:21:30.556252 !!! SPM could not control APHY
9194 23:21:30.559673 IMPEDANCE_TRACKING: ON
9195 23:21:30.559773 TEMP_SENSOR: ON
9196 23:21:30.562600 HW_SAVE_FOR_SR: OFF
9197 23:21:30.566134 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9198 23:21:30.569538 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9199 23:21:30.572775 Read ODT Tracking: ON
9200 23:21:30.572855 Refresh Rate DeBounce: ON
9201 23:21:30.576011 DFS_NO_QUEUE_FLUSH: ON
9202 23:21:30.579591 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9203 23:21:30.582638 ENABLE_DFS_RUNTIME_MRW: OFF
9204 23:21:30.582715 DDR_RESERVE_NEW_MODE: ON
9205 23:21:30.585959 MR_CBT_SWITCH_FREQ: ON
9206 23:21:30.589613 =========================
9207 23:21:30.607146 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9208 23:21:30.610230 dram_init: ddr_geometry: 2
9209 23:21:30.628562 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9210 23:21:30.631640 dram_init: dram init end (result: 0)
9211 23:21:30.638257 DRAM-K: Full calibration passed in 24584 msecs
9212 23:21:30.641767 MRC: failed to locate region type 0.
9213 23:21:30.641848 DRAM rank0 size:0x100000000,
9214 23:21:30.645384 DRAM rank1 size=0x100000000
9215 23:21:30.655255 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9216 23:21:30.661692 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9217 23:21:30.668618 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9218 23:21:30.675206 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9219 23:21:30.678648 DRAM rank0 size:0x100000000,
9220 23:21:30.681990 DRAM rank1 size=0x100000000
9221 23:21:30.682065 CBMEM:
9222 23:21:30.685698 IMD: root @ 0xfffff000 254 entries.
9223 23:21:30.689112 IMD: root @ 0xffffec00 62 entries.
9224 23:21:30.692082 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9225 23:21:30.695137 WARNING: RO_VPD is uninitialized or empty.
9226 23:21:30.702213 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9227 23:21:30.708382 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9228 23:21:30.721195 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9229 23:21:30.733062 BS: romstage times (exec / console): total (unknown) / 24090 ms
9230 23:21:30.733167
9231 23:21:30.733239
9232 23:21:30.743397 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9233 23:21:30.746521 ARM64: Exception handlers installed.
9234 23:21:30.749835 ARM64: Testing exception
9235 23:21:30.749953 ARM64: Done test exception
9236 23:21:30.752911 Enumerating buses...
9237 23:21:30.756374 Show all devs... Before device enumeration.
9238 23:21:30.759437 Root Device: enabled 1
9239 23:21:30.762658 CPU_CLUSTER: 0: enabled 1
9240 23:21:30.762810 CPU: 00: enabled 1
9241 23:21:30.766273 Compare with tree...
9242 23:21:30.766387 Root Device: enabled 1
9243 23:21:30.769715 CPU_CLUSTER: 0: enabled 1
9244 23:21:30.769837 CPU: 00: enabled 1
9245 23:21:30.773113 Root Device scanning...
9246 23:21:30.776422 scan_static_bus for Root Device
9247 23:21:30.780164 CPU_CLUSTER: 0 enabled
9248 23:21:30.782936 scan_static_bus for Root Device done
9249 23:21:30.786411 scan_bus: bus Root Device finished in 8 msecs
9250 23:21:30.786501 done
9251 23:21:30.792935 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9252 23:21:30.796392 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9253 23:21:30.799798 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9254 23:21:30.806728 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9255 23:21:30.810152 Allocating resources...
9256 23:21:30.810259 Reading resources...
9257 23:21:30.813174 Root Device read_resources bus 0 link: 0
9258 23:21:30.816708 DRAM rank0 size:0x100000000,
9259 23:21:30.820310 DRAM rank1 size=0x100000000
9260 23:21:30.823287 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9261 23:21:30.826806 CPU: 00 missing read_resources
9262 23:21:30.830019 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9263 23:21:30.833428 Root Device read_resources bus 0 link: 0 done
9264 23:21:30.836447 Done reading resources.
9265 23:21:30.842982 Show resources in subtree (Root Device)...After reading.
9266 23:21:30.846473 Root Device child on link 0 CPU_CLUSTER: 0
9267 23:21:30.850039 CPU_CLUSTER: 0 child on link 0 CPU: 00
9268 23:21:30.856541 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9269 23:21:30.860012 CPU: 00
9270 23:21:30.863261 Root Device assign_resources, bus 0 link: 0
9271 23:21:30.866301 CPU_CLUSTER: 0 missing set_resources
9272 23:21:30.870104 Root Device assign_resources, bus 0 link: 0 done
9273 23:21:30.873137 Done setting resources.
9274 23:21:30.879782 Show resources in subtree (Root Device)...After assigning values.
9275 23:21:30.883512 Root Device child on link 0 CPU_CLUSTER: 0
9276 23:21:30.886580 CPU_CLUSTER: 0 child on link 0 CPU: 00
9277 23:21:30.893463 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9278 23:21:30.896322 CPU: 00
9279 23:21:30.899779 Done allocating resources.
9280 23:21:30.903145 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9281 23:21:30.906774 Enabling resources...
9282 23:21:30.906875 done.
9283 23:21:30.909680 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9284 23:21:30.913251 Initializing devices...
9285 23:21:30.913356 Root Device init
9286 23:21:30.916719 init hardware done!
9287 23:21:30.919857 0x00000018: ctrlr->caps
9288 23:21:30.919942 52.000 MHz: ctrlr->f_max
9289 23:21:30.923275 0.400 MHz: ctrlr->f_min
9290 23:21:30.926283 0x40ff8080: ctrlr->voltages
9291 23:21:30.926387 sclk: 390625
9292 23:21:30.926474 Bus Width = 1
9293 23:21:30.929595 sclk: 390625
9294 23:21:30.929677 Bus Width = 1
9295 23:21:30.933361 Early init status = 3
9296 23:21:30.936429 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9297 23:21:30.940035 in-header: 03 fc 00 00 01 00 00 00
9298 23:21:30.943674 in-data: 00
9299 23:21:30.946743 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9300 23:21:30.951407 in-header: 03 fd 00 00 00 00 00 00
9301 23:21:30.954805 in-data:
9302 23:21:30.958392 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9303 23:21:30.961964 in-header: 03 fc 00 00 01 00 00 00
9304 23:21:30.965003 in-data: 00
9305 23:21:30.968530 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9306 23:21:30.972833 in-header: 03 fd 00 00 00 00 00 00
9307 23:21:30.976309 in-data:
9308 23:21:30.980077 [SSUSB] Setting up USB HOST controller...
9309 23:21:30.983280 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9310 23:21:30.986318 [SSUSB] phy power-on done.
9311 23:21:30.989471 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9312 23:21:30.996405 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9313 23:21:30.999741 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9314 23:21:31.006890 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9315 23:21:31.013547 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9316 23:21:31.019900 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9317 23:21:31.026162 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9318 23:21:31.033471 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9319 23:21:31.033581 SPM: binary array size = 0x9dc
9320 23:21:31.040124 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9321 23:21:31.046816 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9322 23:21:31.053273 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9323 23:21:31.056377 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9324 23:21:31.059991 configure_display: Starting display init
9325 23:21:31.096013 anx7625_power_on_init: Init interface.
9326 23:21:31.099492 anx7625_disable_pd_protocol: Disabled PD feature.
9327 23:21:31.102767 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9328 23:21:31.130942 anx7625_start_dp_work: Secure OCM version=00
9329 23:21:31.133894 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9330 23:21:31.149162 sp_tx_get_edid_block: EDID Block = 1
9331 23:21:31.251455 Extracted contents:
9332 23:21:31.255080 header: 00 ff ff ff ff ff ff 00
9333 23:21:31.258164 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9334 23:21:31.261190 version: 01 04
9335 23:21:31.265080 basic params: 95 1f 11 78 0a
9336 23:21:31.268314 chroma info: 76 90 94 55 54 90 27 21 50 54
9337 23:21:31.271192 established: 00 00 00
9338 23:21:31.278106 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9339 23:21:31.281224 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9340 23:21:31.287966 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9341 23:21:31.295040 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9342 23:21:31.301471 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9343 23:21:31.304468 extensions: 00
9344 23:21:31.304547 checksum: fb
9345 23:21:31.304619
9346 23:21:31.307930 Manufacturer: IVO Model 57d Serial Number 0
9347 23:21:31.311496 Made week 0 of 2020
9348 23:21:31.311573 EDID version: 1.4
9349 23:21:31.315163 Digital display
9350 23:21:31.317919 6 bits per primary color channel
9351 23:21:31.317996 DisplayPort interface
9352 23:21:31.321480 Maximum image size: 31 cm x 17 cm
9353 23:21:31.321567 Gamma: 220%
9354 23:21:31.324519 Check DPMS levels
9355 23:21:31.328317 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9356 23:21:31.331385 First detailed timing is preferred timing
9357 23:21:31.334657 Established timings supported:
9358 23:21:31.338167 Standard timings supported:
9359 23:21:31.338252 Detailed timings
9360 23:21:31.344573 Hex of detail: 383680a07038204018303c0035ae10000019
9361 23:21:31.347830 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9362 23:21:31.351656 0780 0798 07c8 0820 hborder 0
9363 23:21:31.357857 0438 043b 0447 0458 vborder 0
9364 23:21:31.357947 -hsync -vsync
9365 23:21:31.361660 Did detailed timing
9366 23:21:31.364838 Hex of detail: 000000000000000000000000000000000000
9367 23:21:31.368210 Manufacturer-specified data, tag 0
9368 23:21:31.374717 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9369 23:21:31.374805 ASCII string: InfoVision
9370 23:21:31.381196 Hex of detail: 000000fe00523134304e574635205248200a
9371 23:21:31.381284 ASCII string: R140NWF5 RH
9372 23:21:31.384650 Checksum
9373 23:21:31.384736 Checksum: 0xfb (valid)
9374 23:21:31.391160 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9375 23:21:31.391244 DSI data_rate: 832800000 bps
9376 23:21:31.399269 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9377 23:21:31.402321 anx7625_parse_edid: pixelclock(138800).
9378 23:21:31.405644 hactive(1920), hsync(48), hfp(24), hbp(88)
9379 23:21:31.409097 vactive(1080), vsync(12), vfp(3), vbp(17)
9380 23:21:31.412191 anx7625_dsi_config: config dsi.
9381 23:21:31.419362 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9382 23:21:31.433324 anx7625_dsi_config: success to config DSI
9383 23:21:31.436647 anx7625_dp_start: MIPI phy setup OK.
9384 23:21:31.440294 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9385 23:21:31.443290 mtk_ddp_mode_set invalid vrefresh 60
9386 23:21:31.446766 main_disp_path_setup
9387 23:21:31.446847 ovl_layer_smi_id_en
9388 23:21:31.450324 ovl_layer_smi_id_en
9389 23:21:31.450453 ccorr_config
9390 23:21:31.450538 aal_config
9391 23:21:31.453187 gamma_config
9392 23:21:31.453262 postmask_config
9393 23:21:31.456588 dither_config
9394 23:21:31.459983 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9395 23:21:31.466566 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9396 23:21:31.470052 Root Device init finished in 551 msecs
9397 23:21:31.470137 CPU_CLUSTER: 0 init
9398 23:21:31.480200 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9399 23:21:31.483387 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9400 23:21:31.486777 APU_MBOX 0x190000b0 = 0x10001
9401 23:21:31.490467 APU_MBOX 0x190001b0 = 0x10001
9402 23:21:31.493221 APU_MBOX 0x190005b0 = 0x10001
9403 23:21:31.496891 APU_MBOX 0x190006b0 = 0x10001
9404 23:21:31.499973 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9405 23:21:31.512263 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9406 23:21:31.524791 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9407 23:21:31.531902 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9408 23:21:31.543616 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9409 23:21:31.552021 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9410 23:21:31.555752 CPU_CLUSTER: 0 init finished in 81 msecs
9411 23:21:31.558710 Devices initialized
9412 23:21:31.562022 Show all devs... After init.
9413 23:21:31.562125 Root Device: enabled 1
9414 23:21:31.565546 CPU_CLUSTER: 0: enabled 1
9415 23:21:31.568654 CPU: 00: enabled 1
9416 23:21:31.572607 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9417 23:21:31.575240 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9418 23:21:31.578749 ELOG: NV offset 0x57f000 size 0x1000
9419 23:21:31.585637 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9420 23:21:31.592393 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9421 23:21:31.596150 ELOG: Event(17) added with size 13 at 2024-04-03 23:21:32 UTC
9422 23:21:31.598899 out: cmd=0x121: 03 db 21 01 00 00 00 00
9423 23:21:31.602986 in-header: 03 d1 00 00 2c 00 00 00
9424 23:21:31.616724 in-data: 8e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9425 23:21:31.623126 ELOG: Event(A1) added with size 10 at 2024-04-03 23:21:32 UTC
9426 23:21:31.629664 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9427 23:21:31.636692 ELOG: Event(A0) added with size 9 at 2024-04-03 23:21:32 UTC
9428 23:21:31.639722 elog_add_boot_reason: Logged dev mode boot
9429 23:21:31.643135 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9430 23:21:31.646445 Finalize devices...
9431 23:21:31.646531 Devices finalized
9432 23:21:31.652999 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9433 23:21:31.656441 Writing coreboot table at 0xffe64000
9434 23:21:31.660089 0. 000000000010a000-0000000000113fff: RAMSTAGE
9435 23:21:31.663565 1. 0000000040000000-00000000400fffff: RAM
9436 23:21:31.666455 2. 0000000040100000-000000004032afff: RAMSTAGE
9437 23:21:31.673198 3. 000000004032b000-00000000545fffff: RAM
9438 23:21:31.676574 4. 0000000054600000-000000005465ffff: BL31
9439 23:21:31.679812 5. 0000000054660000-00000000ffe63fff: RAM
9440 23:21:31.683058 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9441 23:21:31.689962 7. 0000000100000000-000000023fffffff: RAM
9442 23:21:31.690055 Passing 5 GPIOs to payload:
9443 23:21:31.696743 NAME | PORT | POLARITY | VALUE
9444 23:21:31.700074 EC in RW | 0x000000aa | low | undefined
9445 23:21:31.706408 EC interrupt | 0x00000005 | low | undefined
9446 23:21:31.709904 TPM interrupt | 0x000000ab | high | undefined
9447 23:21:31.713081 SD card detect | 0x00000011 | high | undefined
9448 23:21:31.719565 speaker enable | 0x00000093 | high | undefined
9449 23:21:31.722946 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9450 23:21:31.726373 in-header: 03 f9 00 00 02 00 00 00
9451 23:21:31.726471 in-data: 02 00
9452 23:21:31.729940 ADC[4]: Raw value=900590 ID=7
9453 23:21:31.732886 ADC[3]: Raw value=213336 ID=1
9454 23:21:31.732971 RAM Code: 0x71
9455 23:21:31.736588 ADC[6]: Raw value=74926 ID=0
9456 23:21:31.739646 ADC[5]: Raw value=212229 ID=1
9457 23:21:31.739730 SKU Code: 0x1
9458 23:21:31.746335 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a82b
9459 23:21:31.750007 coreboot table: 964 bytes.
9460 23:21:31.753158 IMD ROOT 0. 0xfffff000 0x00001000
9461 23:21:31.756411 IMD SMALL 1. 0xffffe000 0x00001000
9462 23:21:31.759878 RO MCACHE 2. 0xffffc000 0x00001104
9463 23:21:31.763196 CONSOLE 3. 0xfff7c000 0x00080000
9464 23:21:31.766208 FMAP 4. 0xfff7b000 0x00000452
9465 23:21:31.769788 TIME STAMP 5. 0xfff7a000 0x00000910
9466 23:21:31.773264 VBOOT WORK 6. 0xfff66000 0x00014000
9467 23:21:31.776258 RAMOOPS 7. 0xffe66000 0x00100000
9468 23:21:31.779656 COREBOOT 8. 0xffe64000 0x00002000
9469 23:21:31.779739 IMD small region:
9470 23:21:31.783030 IMD ROOT 0. 0xffffec00 0x00000400
9471 23:21:31.786261 VPD 1. 0xffffeb80 0x0000006c
9472 23:21:31.789479 MMC STATUS 2. 0xffffeb60 0x00000004
9473 23:21:31.796321 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9474 23:21:31.796406 Probing TPM: done!
9475 23:21:31.803208 Connected to device vid:did:rid of 1ae0:0028:00
9476 23:21:31.810418 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9477 23:21:31.813479 Initialized TPM device CR50 revision 0
9478 23:21:31.817075 Checking cr50 for pending updates
9479 23:21:31.822508 Reading cr50 TPM mode
9480 23:21:31.831208 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9481 23:21:31.837892 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9482 23:21:31.877803 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9483 23:21:31.881591 Checking segment from ROM address 0x40100000
9484 23:21:31.884580 Checking segment from ROM address 0x4010001c
9485 23:21:31.891343 Loading segment from ROM address 0x40100000
9486 23:21:31.891425 code (compression=0)
9487 23:21:31.897963 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9488 23:21:31.908610 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9489 23:21:31.908699 it's not compressed!
9490 23:21:31.915128 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9491 23:21:31.918642 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9492 23:21:31.938549 Loading segment from ROM address 0x4010001c
9493 23:21:31.938660 Entry Point 0x80000000
9494 23:21:31.941821 Loaded segments
9495 23:21:31.945099 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9496 23:21:31.951879 Jumping to boot code at 0x80000000(0xffe64000)
9497 23:21:31.958948 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9498 23:21:31.965129 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9499 23:21:31.972873 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9500 23:21:31.976425 Checking segment from ROM address 0x40100000
9501 23:21:31.979392 Checking segment from ROM address 0x4010001c
9502 23:21:31.986034 Loading segment from ROM address 0x40100000
9503 23:21:31.986120 code (compression=1)
9504 23:21:31.992920 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9505 23:21:32.003070 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9506 23:21:32.003156 using LZMA
9507 23:21:32.011302 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9508 23:21:32.017668 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9509 23:21:32.021141 Loading segment from ROM address 0x4010001c
9510 23:21:32.021227 Entry Point 0x54601000
9511 23:21:32.024792 Loaded segments
9512 23:21:32.027583 NOTICE: MT8192 bl31_setup
9513 23:21:32.034869 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9514 23:21:32.038320 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9515 23:21:32.041637 WARNING: region 0:
9516 23:21:32.045112 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9517 23:21:32.045196 WARNING: region 1:
9518 23:21:32.051716 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9519 23:21:32.051811 WARNING: region 2:
9520 23:21:32.058403 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9521 23:21:32.061835 WARNING: region 3:
9522 23:21:32.064939 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9523 23:21:32.068584 WARNING: region 4:
9524 23:21:32.071884 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9525 23:21:32.075148 WARNING: region 5:
9526 23:21:32.078533 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 23:21:32.082259 WARNING: region 6:
9528 23:21:32.085135 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 23:21:32.085240 WARNING: region 7:
9530 23:21:32.091941 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9531 23:21:32.098367 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9532 23:21:32.101492 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9533 23:21:32.104719 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9534 23:21:32.111606 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9535 23:21:32.114905 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9536 23:21:32.118384 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9537 23:21:32.125038 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9538 23:21:32.128736 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9539 23:21:32.132030 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9540 23:21:32.138642 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9541 23:21:32.142236 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9542 23:21:32.145545 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9543 23:21:32.151817 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9544 23:21:32.155474 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9545 23:21:32.162300 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9546 23:21:32.165320 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9547 23:21:32.168972 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9548 23:21:32.175770 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9549 23:21:32.178841 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9550 23:21:32.182207 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9551 23:21:32.188966 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9552 23:21:32.192384 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9553 23:21:32.199063 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9554 23:21:32.202110 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9555 23:21:32.205597 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9556 23:21:32.212362 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9557 23:21:32.216078 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9558 23:21:32.219252 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9559 23:21:32.225689 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9560 23:21:32.228958 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9561 23:21:32.235715 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9562 23:21:32.239273 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9563 23:21:32.242956 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9564 23:21:32.246335 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9565 23:21:32.252667 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9566 23:21:32.256262 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9567 23:21:32.259246 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9568 23:21:32.262635 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9569 23:21:32.269598 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9570 23:21:32.272797 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9571 23:21:32.276308 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9572 23:21:32.279812 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9573 23:21:32.286391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9574 23:21:32.289840 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9575 23:21:32.293339 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9576 23:21:32.296534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9577 23:21:32.299695 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9578 23:21:32.306493 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9579 23:21:32.309810 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9580 23:21:32.316742 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9581 23:21:32.320103 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9582 23:21:32.323208 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9583 23:21:32.329976 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9584 23:21:32.333233 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9585 23:21:32.340273 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9586 23:21:32.343692 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9587 23:21:32.347154 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9588 23:21:32.353440 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9589 23:21:32.356932 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9590 23:21:32.364027 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9591 23:21:32.367526 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9592 23:21:32.373903 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9593 23:21:32.377540 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9594 23:21:32.380810 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9595 23:21:32.387080 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9596 23:21:32.390619 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9597 23:21:32.397564 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9598 23:21:32.400661 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9599 23:21:32.407349 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9600 23:21:32.410361 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9601 23:21:32.413960 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9602 23:21:32.420784 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9603 23:21:32.424542 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9604 23:21:32.430885 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9605 23:21:32.434272 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9606 23:21:32.440614 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9607 23:21:32.443997 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9608 23:21:32.447619 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9609 23:21:32.454288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9610 23:21:32.457723 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9611 23:21:32.464148 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9612 23:21:32.467794 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9613 23:21:32.471082 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9614 23:21:32.477736 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9615 23:21:32.481214 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9616 23:21:32.487651 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9617 23:21:32.491259 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9618 23:21:32.497636 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9619 23:21:32.501074 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9620 23:21:32.504771 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9621 23:21:32.511177 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9622 23:21:32.514351 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9623 23:21:32.521403 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9624 23:21:32.524345 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9625 23:21:32.531020 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9626 23:21:32.535042 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9627 23:21:32.537958 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9628 23:21:32.544722 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9629 23:21:32.548178 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9630 23:21:32.551210 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9631 23:21:32.554717 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9632 23:21:32.561618 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9633 23:21:32.564818 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9634 23:21:32.568052 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9635 23:21:32.574984 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9636 23:21:32.578785 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9637 23:21:32.584917 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9638 23:21:32.588645 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9639 23:21:32.591630 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9640 23:21:32.598543 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9641 23:21:32.601419 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9642 23:21:32.604957 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9643 23:21:32.611498 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9644 23:21:32.615014 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9645 23:21:32.621867 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9646 23:21:32.625057 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9647 23:21:32.628551 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9648 23:21:32.635110 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9649 23:21:32.638570 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9650 23:21:32.642056 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9651 23:21:32.645671 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9652 23:21:32.652352 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9653 23:21:32.655481 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9654 23:21:32.658941 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9655 23:21:32.662421 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9656 23:21:32.668848 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9657 23:21:32.672274 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9658 23:21:32.678873 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9659 23:21:32.682429 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9660 23:21:32.685781 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9661 23:21:32.692521 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9662 23:21:32.695889 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9663 23:21:32.698756 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9664 23:21:32.705582 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9665 23:21:32.708853 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9666 23:21:32.715972 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9667 23:21:32.719422 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9668 23:21:32.722692 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9669 23:21:32.729396 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9670 23:21:32.733009 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9671 23:21:32.735848 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9672 23:21:32.742914 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9673 23:21:32.746378 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9674 23:21:32.752878 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9675 23:21:32.756089 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9676 23:21:32.759572 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9677 23:21:32.766173 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9678 23:21:32.769842 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9679 23:21:32.773240 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9680 23:21:32.779708 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9681 23:21:32.783079 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9682 23:21:32.789600 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9683 23:21:32.793277 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9684 23:21:32.796651 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9685 23:21:32.803461 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9686 23:21:32.806709 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9687 23:21:32.810083 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9688 23:21:32.818204 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9689 23:21:32.820592 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9690 23:21:32.823632 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9691 23:21:32.830570 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9692 23:21:32.833588 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9693 23:21:32.840451 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9694 23:21:32.843480 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9695 23:21:32.846959 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9696 23:21:32.853551 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9697 23:21:32.856958 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9698 23:21:32.863614 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9699 23:21:32.866950 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9700 23:21:32.870039 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9701 23:21:32.876992 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9702 23:21:32.880589 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9703 23:21:32.883297 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9704 23:21:32.890414 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9705 23:21:32.893347 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9706 23:21:32.900322 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9707 23:21:32.903285 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9708 23:21:32.906614 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9709 23:21:32.913863 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9710 23:21:32.916882 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9711 23:21:32.923479 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9712 23:21:32.926870 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9713 23:21:32.929940 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9714 23:21:32.936612 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9715 23:21:32.940327 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9716 23:21:32.946986 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9717 23:21:32.950354 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9718 23:21:32.953305 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9719 23:21:32.960319 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9720 23:21:32.963370 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9721 23:21:32.970336 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9722 23:21:32.973976 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9723 23:21:32.976853 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9724 23:21:32.983822 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9725 23:21:32.986786 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9726 23:21:32.993994 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9727 23:21:32.996950 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9728 23:21:33.000213 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9729 23:21:33.006844 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9730 23:21:33.010316 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9731 23:21:33.016837 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9732 23:21:33.020288 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9733 23:21:33.023367 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9734 23:21:33.030191 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9735 23:21:33.033668 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9736 23:21:33.040181 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9737 23:21:33.043952 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9738 23:21:33.047149 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9739 23:21:33.053559 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9740 23:21:33.056961 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9741 23:21:33.063985 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9742 23:21:33.067215 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9743 23:21:33.070458 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9744 23:21:33.077280 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9745 23:21:33.080561 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9746 23:21:33.087193 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9747 23:21:33.090765 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9748 23:21:33.097214 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9749 23:21:33.100632 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9750 23:21:33.103641 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9751 23:21:33.110789 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9752 23:21:33.113590 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9753 23:21:33.120739 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9754 23:21:33.123808 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9755 23:21:33.127181 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9756 23:21:33.133676 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9757 23:21:33.137152 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9758 23:21:33.143820 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9759 23:21:33.147409 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9760 23:21:33.150355 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9761 23:21:33.153788 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9762 23:21:33.160901 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9763 23:21:33.163826 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9764 23:21:33.167040 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9765 23:21:33.170639 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9766 23:21:33.177199 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9767 23:21:33.180430 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9768 23:21:33.186968 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9769 23:21:33.190298 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9770 23:21:33.193732 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9771 23:21:33.200532 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9772 23:21:33.203810 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9773 23:21:33.207419 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9774 23:21:33.213541 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9775 23:21:33.217127 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9776 23:21:33.220857 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9777 23:21:33.227159 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9778 23:21:33.230624 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9779 23:21:33.234249 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9780 23:21:33.240535 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9781 23:21:33.244102 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9782 23:21:33.250588 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9783 23:21:33.254239 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9784 23:21:33.257124 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9785 23:21:33.264002 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9786 23:21:33.267461 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9787 23:21:33.270972 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9788 23:21:33.277467 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9789 23:21:33.280409 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9790 23:21:33.284020 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9791 23:21:33.290477 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9792 23:21:33.293719 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9793 23:21:33.300684 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9794 23:21:33.303690 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9795 23:21:33.307501 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9796 23:21:33.313829 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9797 23:21:33.317313 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9798 23:21:33.320312 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9799 23:21:33.327320 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9800 23:21:33.330497 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9801 23:21:33.333335 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9802 23:21:33.336726 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9803 23:21:33.343517 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9804 23:21:33.347089 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9805 23:21:33.350046 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9806 23:21:33.353770 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9807 23:21:33.360393 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9808 23:21:33.363810 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9809 23:21:33.367234 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9810 23:21:33.370010 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9811 23:21:33.376908 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9812 23:21:33.379884 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9813 23:21:33.383392 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9814 23:21:33.390044 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9815 23:21:33.393569 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9816 23:21:33.400076 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9817 23:21:33.403601 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9818 23:21:33.406768 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9819 23:21:33.413581 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9820 23:21:33.416907 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9821 23:21:33.423463 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9822 23:21:33.426994 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9823 23:21:33.430095 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9824 23:21:33.437060 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9825 23:21:33.440522 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9826 23:21:33.446916 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9827 23:21:33.450199 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9828 23:21:33.453577 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9829 23:21:33.460071 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9830 23:21:33.463885 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9831 23:21:33.470174 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9832 23:21:33.473221 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9833 23:21:33.476675 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9834 23:21:33.483390 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9835 23:21:33.487202 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9836 23:21:33.493686 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9837 23:21:33.497335 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9838 23:21:33.500162 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9839 23:21:33.507177 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9840 23:21:33.510187 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9841 23:21:33.517123 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9842 23:21:33.520269 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9843 23:21:33.523547 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9844 23:21:33.530204 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9845 23:21:33.533694 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9846 23:21:33.540489 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9847 23:21:33.543492 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9848 23:21:33.546884 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9849 23:21:33.554051 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9850 23:21:33.556833 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9851 23:21:33.563806 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9852 23:21:33.566930 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9853 23:21:33.570865 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9854 23:21:33.576935 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9855 23:21:33.580269 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9856 23:21:33.586818 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9857 23:21:33.590182 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9858 23:21:33.593727 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9859 23:21:33.600803 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9860 23:21:33.603608 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9861 23:21:33.610740 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9862 23:21:33.613685 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9863 23:21:33.617376 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9864 23:21:33.623819 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9865 23:21:33.626986 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9866 23:21:33.634103 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9867 23:21:33.637503 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9868 23:21:33.640558 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9869 23:21:33.647038 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9870 23:21:33.650245 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9871 23:21:33.657094 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9872 23:21:33.660614 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9873 23:21:33.663633 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9874 23:21:33.670538 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9875 23:21:33.674011 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9876 23:21:33.680572 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9877 23:21:33.684359 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9878 23:21:33.687436 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9879 23:21:33.694082 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9880 23:21:33.697302 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9881 23:21:33.703848 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9882 23:21:33.707161 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9883 23:21:33.710690 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9884 23:21:33.717589 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9885 23:21:33.720427 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9886 23:21:33.727686 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9887 23:21:33.730681 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9888 23:21:33.737242 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9889 23:21:33.740460 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9890 23:21:33.744298 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9891 23:21:33.750832 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9892 23:21:33.754313 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9893 23:21:33.760661 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9894 23:21:33.764016 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9895 23:21:33.767697 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9896 23:21:33.774227 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9897 23:21:33.777680 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9898 23:21:33.783940 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9899 23:21:33.787927 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9900 23:21:33.793861 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9901 23:21:33.797385 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9902 23:21:33.800964 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9903 23:21:33.807387 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9904 23:21:33.810626 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9905 23:21:33.817741 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9906 23:21:33.820796 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9907 23:21:33.827266 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9908 23:21:33.830978 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9909 23:21:33.834022 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9910 23:21:33.840766 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9911 23:21:33.843810 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9912 23:21:33.850458 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9913 23:21:33.853919 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9914 23:21:33.860660 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9915 23:21:33.863995 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9916 23:21:33.867776 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9917 23:21:33.874085 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9918 23:21:33.877605 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9919 23:21:33.884038 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9920 23:21:33.887510 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9921 23:21:33.894104 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9922 23:21:33.897757 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9923 23:21:33.903826 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9924 23:21:33.907192 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9925 23:21:33.910746 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9926 23:21:33.917436 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9927 23:21:33.920719 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9928 23:21:33.927269 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9929 23:21:33.930951 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9930 23:21:33.937320 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9931 23:21:33.940980 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9932 23:21:33.944152 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9933 23:21:33.950615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9934 23:21:33.954228 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9935 23:21:33.960628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9936 23:21:33.963931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9937 23:21:33.967074 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9938 23:21:33.973733 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9939 23:21:33.977113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9940 23:21:33.984211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9941 23:21:33.987278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9942 23:21:33.993686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9943 23:21:33.997392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9944 23:21:34.003997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9945 23:21:34.006971 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9946 23:21:34.013958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9947 23:21:34.017478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9948 23:21:34.023864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9949 23:21:34.027459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9950 23:21:34.034044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9951 23:21:34.037364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9952 23:21:34.043973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9953 23:21:34.047340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9954 23:21:34.054302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9955 23:21:34.057107 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9956 23:21:34.064062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9957 23:21:34.067085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9958 23:21:34.074188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9959 23:21:34.077439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9960 23:21:34.084131 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9961 23:21:34.087726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9962 23:21:34.093965 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9963 23:21:34.097227 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9964 23:21:34.104005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9965 23:21:34.107533 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9966 23:21:34.107615 INFO: [APUAPC] vio 0
9967 23:21:34.114660 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9968 23:21:34.118172 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9969 23:21:34.121020 INFO: [APUAPC] D0_APC_0: 0x400510
9970 23:21:34.124657 INFO: [APUAPC] D0_APC_1: 0x0
9971 23:21:34.128058 INFO: [APUAPC] D0_APC_2: 0x1540
9972 23:21:34.131667 INFO: [APUAPC] D0_APC_3: 0x0
9973 23:21:34.134605 INFO: [APUAPC] D1_APC_0: 0xffffffff
9974 23:21:34.138094 INFO: [APUAPC] D1_APC_1: 0xffffffff
9975 23:21:34.141567 INFO: [APUAPC] D1_APC_2: 0x3fffff
9976 23:21:34.144413 INFO: [APUAPC] D1_APC_3: 0x0
9977 23:21:34.148033 INFO: [APUAPC] D2_APC_0: 0xffffffff
9978 23:21:34.150941 INFO: [APUAPC] D2_APC_1: 0xffffffff
9979 23:21:34.154290 INFO: [APUAPC] D2_APC_2: 0x3fffff
9980 23:21:34.157735 INFO: [APUAPC] D2_APC_3: 0x0
9981 23:21:34.161227 INFO: [APUAPC] D3_APC_0: 0xffffffff
9982 23:21:34.164284 INFO: [APUAPC] D3_APC_1: 0xffffffff
9983 23:21:34.167903 INFO: [APUAPC] D3_APC_2: 0x3fffff
9984 23:21:34.167983 INFO: [APUAPC] D3_APC_3: 0x0
9985 23:21:34.174251 INFO: [APUAPC] D4_APC_0: 0xffffffff
9986 23:21:34.177891 INFO: [APUAPC] D4_APC_1: 0xffffffff
9987 23:21:34.181397 INFO: [APUAPC] D4_APC_2: 0x3fffff
9988 23:21:34.181479 INFO: [APUAPC] D4_APC_3: 0x0
9989 23:21:34.184466 INFO: [APUAPC] D5_APC_0: 0xffffffff
9990 23:21:34.187850 INFO: [APUAPC] D5_APC_1: 0xffffffff
9991 23:21:34.191380 INFO: [APUAPC] D5_APC_2: 0x3fffff
9992 23:21:34.194482 INFO: [APUAPC] D5_APC_3: 0x0
9993 23:21:34.197706 INFO: [APUAPC] D6_APC_0: 0xffffffff
9994 23:21:34.200847 INFO: [APUAPC] D6_APC_1: 0xffffffff
9995 23:21:34.204389 INFO: [APUAPC] D6_APC_2: 0x3fffff
9996 23:21:34.207911 INFO: [APUAPC] D6_APC_3: 0x0
9997 23:21:34.211085 INFO: [APUAPC] D7_APC_0: 0xffffffff
9998 23:21:34.214408 INFO: [APUAPC] D7_APC_1: 0xffffffff
9999 23:21:34.218220 INFO: [APUAPC] D7_APC_2: 0x3fffff
10000 23:21:34.221409 INFO: [APUAPC] D7_APC_3: 0x0
10001 23:21:34.224716 INFO: [APUAPC] D8_APC_0: 0xffffffff
10002 23:21:34.228109 INFO: [APUAPC] D8_APC_1: 0xffffffff
10003 23:21:34.231303 INFO: [APUAPC] D8_APC_2: 0x3fffff
10004 23:21:34.234726 INFO: [APUAPC] D8_APC_3: 0x0
10005 23:21:34.238330 INFO: [APUAPC] D9_APC_0: 0xffffffff
10006 23:21:34.241239 INFO: [APUAPC] D9_APC_1: 0xffffffff
10007 23:21:34.244625 INFO: [APUAPC] D9_APC_2: 0x3fffff
10008 23:21:34.248119 INFO: [APUAPC] D9_APC_3: 0x0
10009 23:21:34.251136 INFO: [APUAPC] D10_APC_0: 0xffffffff
10010 23:21:34.254403 INFO: [APUAPC] D10_APC_1: 0xffffffff
10011 23:21:34.257892 INFO: [APUAPC] D10_APC_2: 0x3fffff
10012 23:21:34.261737 INFO: [APUAPC] D10_APC_3: 0x0
10013 23:21:34.264979 INFO: [APUAPC] D11_APC_0: 0xffffffff
10014 23:21:34.268316 INFO: [APUAPC] D11_APC_1: 0xffffffff
10015 23:21:34.271387 INFO: [APUAPC] D11_APC_2: 0x3fffff
10016 23:21:34.274945 INFO: [APUAPC] D11_APC_3: 0x0
10017 23:21:34.278380 INFO: [APUAPC] D12_APC_0: 0xffffffff
10018 23:21:34.281357 INFO: [APUAPC] D12_APC_1: 0xffffffff
10019 23:21:34.284535 INFO: [APUAPC] D12_APC_2: 0x3fffff
10020 23:21:34.288107 INFO: [APUAPC] D12_APC_3: 0x0
10021 23:21:34.291431 INFO: [APUAPC] D13_APC_0: 0xffffffff
10022 23:21:34.294971 INFO: [APUAPC] D13_APC_1: 0xffffffff
10023 23:21:34.298264 INFO: [APUAPC] D13_APC_2: 0x3fffff
10024 23:21:34.301518 INFO: [APUAPC] D13_APC_3: 0x0
10025 23:21:34.304948 INFO: [APUAPC] D14_APC_0: 0xffffffff
10026 23:21:34.307880 INFO: [APUAPC] D14_APC_1: 0xffffffff
10027 23:21:34.311408 INFO: [APUAPC] D14_APC_2: 0x3fffff
10028 23:21:34.314889 INFO: [APUAPC] D14_APC_3: 0x0
10029 23:21:34.317802 INFO: [APUAPC] D15_APC_0: 0xffffffff
10030 23:21:34.321640 INFO: [APUAPC] D15_APC_1: 0xffffffff
10031 23:21:34.324469 INFO: [APUAPC] D15_APC_2: 0x3fffff
10032 23:21:34.327901 INFO: [APUAPC] D15_APC_3: 0x0
10033 23:21:34.331751 INFO: [APUAPC] APC_CON: 0x4
10034 23:21:34.335286 INFO: [NOCDAPC] D0_APC_0: 0x0
10035 23:21:34.335367 INFO: [NOCDAPC] D0_APC_1: 0x0
10036 23:21:34.338200 INFO: [NOCDAPC] D1_APC_0: 0x0
10037 23:21:34.341405 INFO: [NOCDAPC] D1_APC_1: 0xfff
10038 23:21:34.344787 INFO: [NOCDAPC] D2_APC_0: 0x0
10039 23:21:34.348234 INFO: [NOCDAPC] D2_APC_1: 0xfff
10040 23:21:34.351315 INFO: [NOCDAPC] D3_APC_0: 0x0
10041 23:21:34.354804 INFO: [NOCDAPC] D3_APC_1: 0xfff
10042 23:21:34.358152 INFO: [NOCDAPC] D4_APC_0: 0x0
10043 23:21:34.361380 INFO: [NOCDAPC] D4_APC_1: 0xfff
10044 23:21:34.361461 INFO: [NOCDAPC] D5_APC_0: 0x0
10045 23:21:34.365114 INFO: [NOCDAPC] D5_APC_1: 0xfff
10046 23:21:34.368359 INFO: [NOCDAPC] D6_APC_0: 0x0
10047 23:21:34.371352 INFO: [NOCDAPC] D6_APC_1: 0xfff
10048 23:21:34.374920 INFO: [NOCDAPC] D7_APC_0: 0x0
10049 23:21:34.378043 INFO: [NOCDAPC] D7_APC_1: 0xfff
10050 23:21:34.381478 INFO: [NOCDAPC] D8_APC_0: 0x0
10051 23:21:34.385027 INFO: [NOCDAPC] D8_APC_1: 0xfff
10052 23:21:34.388012 INFO: [NOCDAPC] D9_APC_0: 0x0
10053 23:21:34.391562 INFO: [NOCDAPC] D9_APC_1: 0xfff
10054 23:21:34.395085 INFO: [NOCDAPC] D10_APC_0: 0x0
10055 23:21:34.398594 INFO: [NOCDAPC] D10_APC_1: 0xfff
10056 23:21:34.398707 INFO: [NOCDAPC] D11_APC_0: 0x0
10057 23:21:34.401508 INFO: [NOCDAPC] D11_APC_1: 0xfff
10058 23:21:34.404924 INFO: [NOCDAPC] D12_APC_0: 0x0
10059 23:21:34.408690 INFO: [NOCDAPC] D12_APC_1: 0xfff
10060 23:21:34.411637 INFO: [NOCDAPC] D13_APC_0: 0x0
10061 23:21:34.415272 INFO: [NOCDAPC] D13_APC_1: 0xfff
10062 23:21:34.418353 INFO: [NOCDAPC] D14_APC_0: 0x0
10063 23:21:34.421881 INFO: [NOCDAPC] D14_APC_1: 0xfff
10064 23:21:34.424776 INFO: [NOCDAPC] D15_APC_0: 0x0
10065 23:21:34.428675 INFO: [NOCDAPC] D15_APC_1: 0xfff
10066 23:21:34.431507 INFO: [NOCDAPC] APC_CON: 0x4
10067 23:21:34.435082 INFO: [APUAPC] set_apusys_apc done
10068 23:21:34.438511 INFO: [DEVAPC] devapc_init done
10069 23:21:34.441532 INFO: GICv3 without legacy support detected.
10070 23:21:34.445021 INFO: ARM GICv3 driver initialized in EL3
10071 23:21:34.448352 INFO: Maximum SPI INTID supported: 639
10072 23:21:34.451757 INFO: BL31: Initializing runtime services
10073 23:21:34.458638 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10074 23:21:34.462010 INFO: SPM: enable CPC mode
10075 23:21:34.465221 INFO: mcdi ready for mcusys-off-idle and system suspend
10076 23:21:34.471854 INFO: BL31: Preparing for EL3 exit to normal world
10077 23:21:34.475113 INFO: Entry point address = 0x80000000
10078 23:21:34.475220 INFO: SPSR = 0x8
10079 23:21:34.482520
10080 23:21:34.482622
10081 23:21:34.482713
10082 23:21:34.483586 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10083 23:21:34.483724 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10084 23:21:34.483842 Setting prompt string to ['asurada:']
10085 23:21:34.483950 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10086 23:21:34.485987 Starting depthcharge on Spherion...
10087 23:21:34.486123
10088 23:21:34.486216 Wipe memory regions:
10089 23:21:34.486302
10090 23:21:34.489528 [0x00000040000000, 0x00000054600000)
10091 23:21:34.611772
10092 23:21:34.611897 [0x00000054660000, 0x00000080000000)
10093 23:21:34.872233
10094 23:21:34.872366 [0x000000821a7280, 0x000000ffe64000)
10095 23:21:35.616663
10096 23:21:35.616833 [0x00000100000000, 0x00000240000000)
10097 23:21:37.507221
10098 23:21:37.510531 Initializing XHCI USB controller at 0x11200000.
10099 23:21:38.548096
10100 23:21:38.551505 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10101 23:21:38.551623
10102 23:21:38.551725
10103 23:21:38.551815
10104 23:21:38.552134 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10106 23:21:38.652499 asurada: tftpboot 192.168.201.1 13248464/tftp-deploy-vppbiez6/kernel/image.itb 13248464/tftp-deploy-vppbiez6/kernel/cmdline
10107 23:21:38.652679 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10108 23:21:38.652802 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10109 23:21:38.656993 tftpboot 192.168.201.1 13248464/tftp-deploy-vppbiez6/kernel/image.itbtp-deploy-vppbiez6/kernel/cmdline
10110 23:21:38.657156
10111 23:21:38.657251 Waiting for link
10112 23:21:38.817512
10113 23:21:38.817684 R8152: Initializing
10114 23:21:38.817782
10115 23:21:38.820992 Version 6 (ocp_data = 5c30)
10116 23:21:38.821096
10117 23:21:38.824384 R8152: Done initializing
10118 23:21:38.824488
10119 23:21:38.824587 Adding net device
10120 23:21:40.852204
10121 23:21:40.852370 done.
10122 23:21:40.852448
10123 23:21:40.852550 MAC: 00:24:32:30:78:52
10124 23:21:40.852641
10125 23:21:40.855757 Sending DHCP discover... done.
10126 23:21:40.855872
10127 23:21:40.859473 Waiting for reply... done.
10128 23:21:40.859577
10129 23:21:40.862358 Sending DHCP request... done.
10130 23:21:40.862456
10131 23:21:40.930685 Waiting for reply... done.
10132 23:21:40.930840
10133 23:21:40.930911 My ip is 192.168.201.14
10134 23:21:40.930974
10135 23:21:40.934225 The DHCP server ip is 192.168.201.1
10136 23:21:40.934343
10137 23:21:40.940700 TFTP server IP predefined by user: 192.168.201.1
10138 23:21:40.940811
10139 23:21:40.947582 Bootfile predefined by user: 13248464/tftp-deploy-vppbiez6/kernel/image.itb
10140 23:21:40.947675
10141 23:21:40.950392 Sending tftp read request... done.
10142 23:21:40.950602
10143 23:21:40.954204 Waiting for the transfer...
10144 23:21:40.954364
10145 23:21:41.474303 00000000 ################################################################
10146 23:21:41.474477
10147 23:21:41.993018 00080000 ################################################################
10148 23:21:41.993164
10149 23:21:42.511801 00100000 ################################################################
10150 23:21:42.511953
10151 23:21:43.030111 00180000 ################################################################
10152 23:21:43.030258
10153 23:21:43.548524 00200000 ################################################################
10154 23:21:43.548661
10155 23:21:44.067743 00280000 ################################################################
10156 23:21:44.067879
10157 23:21:44.594177 00300000 ################################################################
10158 23:21:44.594330
10159 23:21:45.115331 00380000 ################################################################
10160 23:21:45.115514
10161 23:21:45.634100 00400000 ################################################################
10162 23:21:45.634287
10163 23:21:46.168661 00480000 ################################################################
10164 23:21:46.168804
10165 23:21:46.700910 00500000 ################################################################
10166 23:21:46.701048
10167 23:21:47.234789 00580000 ################################################################
10168 23:21:47.234928
10169 23:21:47.752905 00600000 ################################################################
10170 23:21:47.753046
10171 23:21:48.271692 00680000 ################################################################
10172 23:21:48.271843
10173 23:21:48.792175 00700000 ################################################################
10174 23:21:48.792332
10175 23:21:49.310357 00780000 ################################################################
10176 23:21:49.310546
10177 23:21:49.826406 00800000 ################################################################
10178 23:21:49.826570
10179 23:21:50.347688 00880000 ################################################################
10180 23:21:50.347830
10181 23:21:50.890742 00900000 ################################################################
10182 23:21:50.890899
10183 23:21:51.407644 00980000 ################################################################
10184 23:21:51.407809
10185 23:21:51.931070 00a00000 ################################################################
10186 23:21:51.931203
10187 23:21:52.457697 00a80000 ################################################################
10188 23:21:52.457838
10189 23:21:52.975250 00b00000 ################################################################
10190 23:21:52.975397
10191 23:21:53.497437 00b80000 ################################################################
10192 23:21:53.497581
10193 23:21:54.026541 00c00000 ################################################################
10194 23:21:54.026699
10195 23:21:54.563925 00c80000 ################################################################
10196 23:21:54.564080
10197 23:21:55.088552 00d00000 ################################################################
10198 23:21:55.088699
10199 23:21:55.611435 00d80000 ################################################################
10200 23:21:55.611584
10201 23:21:56.141940 00e00000 ################################################################
10202 23:21:56.142095
10203 23:21:56.664798 00e80000 ################################################################
10204 23:21:56.664948
10205 23:21:57.182154 00f00000 ################################################################
10206 23:21:57.182335
10207 23:21:57.714116 00f80000 ################################################################
10208 23:21:57.714296
10209 23:21:58.244333 01000000 ################################################################
10210 23:21:58.244498
10211 23:21:58.783202 01080000 ################################################################
10212 23:21:58.783349
10213 23:21:59.342452 01100000 ################################################################
10214 23:21:59.342602
10215 23:21:59.890392 01180000 ################################################################
10216 23:21:59.890566
10217 23:22:00.426814 01200000 ################################################################
10218 23:22:00.426953
10219 23:22:00.960742 01280000 ################################################################
10220 23:22:00.960877
10221 23:22:01.514793 01300000 ################################################################
10222 23:22:01.514959
10223 23:22:02.068287 01380000 ################################################################
10224 23:22:02.068462
10225 23:22:02.606062 01400000 ################################################################
10226 23:22:02.606228
10227 23:22:03.145040 01480000 ################################################################
10228 23:22:03.145174
10229 23:22:03.684662 01500000 ################################################################
10230 23:22:03.684807
10231 23:22:04.229299 01580000 ################################################################
10232 23:22:04.229452
10233 23:22:04.753601 01600000 ################################################################
10234 23:22:04.753769
10235 23:22:05.299761 01680000 ################################################################
10236 23:22:05.299911
10237 23:22:05.850666 01700000 ################################################################
10238 23:22:05.850805
10239 23:22:06.402764 01780000 ################################################################
10240 23:22:06.402914
10241 23:22:06.943827 01800000 ################################################################
10242 23:22:06.943968
10243 23:22:07.469424 01880000 ################################################################
10244 23:22:07.469579
10245 23:22:07.998247 01900000 ################################################################
10246 23:22:07.998458
10247 23:22:08.526287 01980000 ################################################################
10248 23:22:08.526443
10249 23:22:09.067272 01a00000 ################################################################
10250 23:22:09.067424
10251 23:22:09.620926 01a80000 ################################################################
10252 23:22:09.621065
10253 23:22:10.170667 01b00000 ################################################################
10254 23:22:10.170811
10255 23:22:10.730833 01b80000 ################################################################
10256 23:22:10.731001
10257 23:22:11.290887 01c00000 ################################################################
10258 23:22:11.291028
10259 23:22:11.861586 01c80000 ################################################################
10260 23:22:11.861737
10261 23:22:12.410779 01d00000 ################################################################
10262 23:22:12.410914
10263 23:22:12.966913 01d80000 ################################################################
10264 23:22:12.967064
10265 23:22:13.251269 01e00000 ################################## done.
10266 23:22:13.251428
10267 23:22:13.254997 The bootfile was 31729838 bytes long.
10268 23:22:13.255081
10269 23:22:13.257416 Sending tftp read request... done.
10270 23:22:13.257499
10271 23:22:13.260595 Waiting for the transfer...
10272 23:22:13.260705
10273 23:22:13.260771 00000000 # done.
10274 23:22:13.263869
10275 23:22:13.270684 Command line loaded dynamically from TFTP file: 13248464/tftp-deploy-vppbiez6/kernel/cmdline
10276 23:22:13.270764
10277 23:22:13.290744 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13248464/extract-nfsrootfs-huwavqnr,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10278 23:22:13.293919
10279 23:22:13.293997 Loading FIT.
10280 23:22:13.294070
10281 23:22:13.297653 Image ramdisk-1 has 18773303 bytes.
10282 23:22:13.297740
10283 23:22:13.300776 Image fdt-1 has 47230 bytes.
10284 23:22:13.300864
10285 23:22:13.300930 Image kernel-1 has 12907270 bytes.
10286 23:22:13.304072
10287 23:22:13.310735 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10288 23:22:13.310817
10289 23:22:13.327169 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10290 23:22:13.330798
10291 23:22:13.334135 Choosing best match conf-1 for compat google,spherion-rev2.
10292 23:22:13.338244
10293 23:22:13.342842 Connected to device vid:did:rid of 1ae0:0028:00
10294 23:22:13.350024
10295 23:22:13.353001 tpm_get_response: command 0x17b, return code 0x0
10296 23:22:13.353082
10297 23:22:13.356481 ec_init: CrosEC protocol v3 supported (256, 248)
10298 23:22:13.361285
10299 23:22:13.363882 tpm_cleanup: add release locality here.
10300 23:22:13.363964
10301 23:22:13.364030 Shutting down all USB controllers.
10302 23:22:13.367252
10303 23:22:13.367333 Removing current net device
10304 23:22:13.367398
10305 23:22:13.374161 Exiting depthcharge with code 4 at timestamp: 68296170
10306 23:22:13.374242
10307 23:22:13.377705 LZMA decompressing kernel-1 to 0x821a6718
10308 23:22:13.377787
10309 23:22:13.380828 LZMA decompressing kernel-1 to 0x40000000
10310 23:22:14.973430
10311 23:22:14.973608 jumping to kernel
10312 23:22:14.974212 end: 2.2.4 bootloader-commands (duration 00:00:40) [common]
10313 23:22:14.974326 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10314 23:22:14.974413 Setting prompt string to ['Linux version [0-9]']
10315 23:22:14.974514 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10316 23:22:14.974613 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10317 23:22:15.055922
10318 23:22:15.058996 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10319 23:22:15.062380 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10320 23:22:15.062563 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10321 23:22:15.062662 Setting prompt string to []
10322 23:22:15.062766 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10323 23:22:15.062869 Using line separator: #'\n'#
10324 23:22:15.062956 No login prompt set.
10325 23:22:15.063045 Parsing kernel messages
10326 23:22:15.063129 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10327 23:22:15.063296 [login-action] Waiting for messages, (timeout 00:03:45)
10328 23:22:15.063363 Waiting using forced prompt support (timeout 00:01:52)
10329 23:22:15.082187 [ 0.000000] Linux version 6.1.83-cip18 (KernelCI@build-j154450-arm64-gcc-10-defconfig-arm64-chromebook-z5l88) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024
10330 23:22:15.085849 [ 0.000000] random: crng init done
10331 23:22:15.092020 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10332 23:22:15.092103 [ 0.000000] efi: UEFI not found.
10333 23:22:15.102262 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10334 23:22:15.109044 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10335 23:22:15.118875 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10336 23:22:15.128879 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10337 23:22:15.135576 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10338 23:22:15.138985 [ 0.000000] printk: bootconsole [mtk8250] enabled
10339 23:22:15.147446 [ 0.000000] NUMA: No NUMA configuration found
10340 23:22:15.153850 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10341 23:22:15.160456 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10342 23:22:15.160534 [ 0.000000] Zone ranges:
10343 23:22:15.167180 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10344 23:22:15.170866 [ 0.000000] DMA32 empty
10345 23:22:15.177180 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10346 23:22:15.181074 [ 0.000000] Movable zone start for each node
10347 23:22:15.183860 [ 0.000000] Early memory node ranges
10348 23:22:15.190390 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10349 23:22:15.197349 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10350 23:22:15.204067 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10351 23:22:15.210649 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10352 23:22:15.217469 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10353 23:22:15.223975 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10354 23:22:15.280275 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10355 23:22:15.286667 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10356 23:22:15.293630 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10357 23:22:15.296748 [ 0.000000] psci: probing for conduit method from DT.
10358 23:22:15.303591 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10359 23:22:15.306866 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10360 23:22:15.313253 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10361 23:22:15.316749 [ 0.000000] psci: SMC Calling Convention v1.2
10362 23:22:15.323105 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10363 23:22:15.326688 [ 0.000000] Detected VIPT I-cache on CPU0
10364 23:22:15.333215 [ 0.000000] CPU features: detected: GIC system register CPU interface
10365 23:22:15.339978 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10366 23:22:15.346596 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10367 23:22:15.353218 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10368 23:22:15.359641 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10369 23:22:15.369633 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10370 23:22:15.373085 [ 0.000000] alternatives: applying boot alternatives
10371 23:22:15.379754 [ 0.000000] Fallback order for Node 0: 0
10372 23:22:15.386224 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10373 23:22:15.389790 [ 0.000000] Policy zone: Normal
10374 23:22:15.409794 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13248464/extract-nfsrootfs-huwavqnr,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10375 23:22:15.423175 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10376 23:22:15.433164 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10377 23:22:15.443208 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10378 23:22:15.449665 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10379 23:22:15.453074 <6>[ 0.000000] software IO TLB: area num 8.
10380 23:22:15.509542 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10381 23:22:15.659621 <6>[ 0.000000] Memory: 7946236K/8385536K available (18048K kernel code, 4118K rwdata, 22284K rodata, 8448K init, 616K bss, 406532K reserved, 32768K cma-reserved)
10382 23:22:15.666320 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10383 23:22:15.672600 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10384 23:22:15.675742 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10385 23:22:15.682873 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10386 23:22:15.689291 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10387 23:22:15.692603 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10388 23:22:15.702916 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10389 23:22:15.709347 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10390 23:22:15.712845 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10391 23:22:15.720663 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10392 23:22:15.723669 <6>[ 0.000000] GICv3: 608 SPIs implemented
10393 23:22:15.730247 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10394 23:22:15.733940 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10395 23:22:15.736900 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10396 23:22:15.747145 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10397 23:22:15.756759 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10398 23:22:15.770097 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10399 23:22:15.777241 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10400 23:22:15.785705 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10401 23:22:15.799228 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10402 23:22:15.805411 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10403 23:22:15.811958 <6>[ 0.009179] Console: colour dummy device 80x25
10404 23:22:15.822524 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10405 23:22:15.828949 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10406 23:22:15.832525 <6>[ 0.029239] LSM: Security Framework initializing
10407 23:22:15.838976 <6>[ 0.034209] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10408 23:22:15.849339 <6>[ 0.042023] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10409 23:22:15.855822 <6>[ 0.051442] cblist_init_generic: Setting adjustable number of callback queues.
10410 23:22:15.862050 <6>[ 0.058933] cblist_init_generic: Setting shift to 3 and lim to 1.
10411 23:22:15.872513 <6>[ 0.065310] cblist_init_generic: Setting adjustable number of callback queues.
10412 23:22:15.875669 <6>[ 0.072737] cblist_init_generic: Setting shift to 3 and lim to 1.
10413 23:22:15.882158 <6>[ 0.079178] rcu: Hierarchical SRCU implementation.
10414 23:22:15.888888 <6>[ 0.084193] rcu: Max phase no-delay instances is 1000.
10415 23:22:15.895621 <6>[ 0.091215] EFI services will not be available.
10416 23:22:15.899223 <6>[ 0.096175] smp: Bringing up secondary CPUs ...
10417 23:22:15.906860 <6>[ 0.101224] Detected VIPT I-cache on CPU1
10418 23:22:15.913638 <6>[ 0.101297] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10419 23:22:15.920067 <6>[ 0.101328] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10420 23:22:15.923455 <6>[ 0.101667] Detected VIPT I-cache on CPU2
10421 23:22:15.930579 <6>[ 0.101713] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10422 23:22:15.936889 <6>[ 0.101731] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10423 23:22:15.943395 <6>[ 0.101977] Detected VIPT I-cache on CPU3
10424 23:22:15.949929 <6>[ 0.102020] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10425 23:22:15.956722 <6>[ 0.102035] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10426 23:22:15.960342 <6>[ 0.102332] CPU features: detected: Spectre-v4
10427 23:22:15.966777 <6>[ 0.102339] CPU features: detected: Spectre-BHB
10428 23:22:15.970230 <6>[ 0.102344] Detected PIPT I-cache on CPU4
10429 23:22:15.976400 <6>[ 0.102405] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10430 23:22:15.983004 <6>[ 0.102422] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10431 23:22:15.989898 <6>[ 0.102711] Detected PIPT I-cache on CPU5
10432 23:22:15.996648 <6>[ 0.102773] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10433 23:22:16.002748 <6>[ 0.102789] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10434 23:22:16.006022 <6>[ 0.103070] Detected PIPT I-cache on CPU6
10435 23:22:16.012966 <6>[ 0.103134] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10436 23:22:16.019625 <6>[ 0.103151] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10437 23:22:16.025945 <6>[ 0.103447] Detected PIPT I-cache on CPU7
10438 23:22:16.033198 <6>[ 0.103513] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10439 23:22:16.039625 <6>[ 0.103529] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10440 23:22:16.042788 <6>[ 0.103576] smp: Brought up 1 node, 8 CPUs
10441 23:22:16.049110 <6>[ 0.244865] SMP: Total of 8 processors activated.
10442 23:22:16.052610 <6>[ 0.249786] CPU features: detected: 32-bit EL0 Support
10443 23:22:16.062824 <6>[ 0.255149] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10444 23:22:16.069226 <6>[ 0.264004] CPU features: detected: Common not Private translations
10445 23:22:16.072680 <6>[ 0.270520] CPU features: detected: CRC32 instructions
10446 23:22:16.079633 <6>[ 0.275905] CPU features: detected: RCpc load-acquire (LDAPR)
10447 23:22:16.085891 <6>[ 0.281902] CPU features: detected: LSE atomic instructions
10448 23:22:16.092591 <6>[ 0.287684] CPU features: detected: Privileged Access Never
10449 23:22:16.095827 <6>[ 0.293464] CPU features: detected: RAS Extension Support
10450 23:22:16.106054 <6>[ 0.299072] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10451 23:22:16.109014 <6>[ 0.306292] CPU: All CPU(s) started at EL2
10452 23:22:16.116036 <6>[ 0.310609] alternatives: applying system-wide alternatives
10453 23:22:16.124713 <6>[ 0.321446] devtmpfs: initialized
10454 23:22:16.137018 <6>[ 0.330345] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10455 23:22:16.147086 <6>[ 0.340305] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10456 23:22:16.153625 <6>[ 0.348329] pinctrl core: initialized pinctrl subsystem
10457 23:22:16.156424 <6>[ 0.355000] DMI not present or invalid.
10458 23:22:16.163440 <6>[ 0.359411] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10459 23:22:16.173588 <6>[ 0.366302] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10460 23:22:16.180055 <6>[ 0.373890] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10461 23:22:16.190039 <6>[ 0.382101] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10462 23:22:16.193436 <6>[ 0.390343] audit: initializing netlink subsys (disabled)
10463 23:22:16.203180 <5>[ 0.396035] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10464 23:22:16.210135 <6>[ 0.396745] thermal_sys: Registered thermal governor 'step_wise'
10465 23:22:16.216551 <6>[ 0.404002] thermal_sys: Registered thermal governor 'power_allocator'
10466 23:22:16.219706 <6>[ 0.410259] cpuidle: using governor menu
10467 23:22:16.223087 <6>[ 0.421216] NET: Registered PF_QIPCRTR protocol family
10468 23:22:16.232965 <6>[ 0.426715] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10469 23:22:16.236727 <6>[ 0.433818] ASID allocator initialised with 32768 entries
10470 23:22:16.243840 <6>[ 0.440392] Serial: AMBA PL011 UART driver
10471 23:22:16.252062 <4>[ 0.449224] Trying to register duplicate clock ID: 134
10472 23:22:16.306614 <6>[ 0.506992] KASLR enabled
10473 23:22:16.321099 <6>[ 0.514757] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10474 23:22:16.327604 <6>[ 0.521771] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10475 23:22:16.334513 <6>[ 0.528260] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10476 23:22:16.341310 <6>[ 0.535267] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10477 23:22:16.347728 <6>[ 0.541751] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10478 23:22:16.354431 <6>[ 0.548758] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10479 23:22:16.361161 <6>[ 0.555246] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10480 23:22:16.367534 <6>[ 0.562248] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10481 23:22:16.371132 <6>[ 0.569774] ACPI: Interpreter disabled.
10482 23:22:16.379250 <6>[ 0.576284] iommu: Default domain type: Translated
10483 23:22:16.386099 <6>[ 0.581395] iommu: DMA domain TLB invalidation policy: strict mode
10484 23:22:16.389174 <5>[ 0.588022] SCSI subsystem initialized
10485 23:22:16.396078 <6>[ 0.592187] usbcore: registered new interface driver usbfs
10486 23:22:16.402475 <6>[ 0.597920] usbcore: registered new interface driver hub
10487 23:22:16.405709 <6>[ 0.603472] usbcore: registered new device driver usb
10488 23:22:16.412588 <6>[ 0.609574] pps_core: LinuxPPS API ver. 1 registered
10489 23:22:16.422522 <6>[ 0.614767] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10490 23:22:16.426143 <6>[ 0.624114] PTP clock support registered
10491 23:22:16.429093 <6>[ 0.628358] EDAC MC: Ver: 3.0.0
10492 23:22:16.436715 <6>[ 0.633533] FPGA manager framework
10493 23:22:16.443230 <6>[ 0.637211] Advanced Linux Sound Architecture Driver Initialized.
10494 23:22:16.446523 <6>[ 0.643988] vgaarb: loaded
10495 23:22:16.452982 <6>[ 0.647172] clocksource: Switched to clocksource arch_sys_counter
10496 23:22:16.456392 <5>[ 0.653610] VFS: Disk quotas dquot_6.6.0
10497 23:22:16.463414 <6>[ 0.657794] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10498 23:22:16.466166 <6>[ 0.664985] pnp: PnP ACPI: disabled
10499 23:22:16.474883 <6>[ 0.671612] NET: Registered PF_INET protocol family
10500 23:22:16.484577 <6>[ 0.677217] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10501 23:22:16.495889 <6>[ 0.689536] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10502 23:22:16.505903 <6>[ 0.698344] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10503 23:22:16.512700 <6>[ 0.706311] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10504 23:22:16.522462 <6>[ 0.715011] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10505 23:22:16.528868 <6>[ 0.724768] TCP: Hash tables configured (established 65536 bind 65536)
10506 23:22:16.535569 <6>[ 0.731627] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10507 23:22:16.545484 <6>[ 0.738823] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10508 23:22:16.549128 <6>[ 0.746522] NET: Registered PF_UNIX/PF_LOCAL protocol family
10509 23:22:16.555749 <6>[ 0.752669] RPC: Registered named UNIX socket transport module.
10510 23:22:16.562913 <6>[ 0.758826] RPC: Registered udp transport module.
10511 23:22:16.565963 <6>[ 0.763759] RPC: Registered tcp transport module.
10512 23:22:16.572064 <6>[ 0.768689] RPC: Registered tcp NFSv4.1 backchannel transport module.
10513 23:22:16.578761 <6>[ 0.775352] PCI: CLS 0 bytes, default 64
10514 23:22:16.582304 <6>[ 0.779672] Unpacking initramfs...
10515 23:22:16.605772 <6>[ 0.799295] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10516 23:22:16.615884 <6>[ 0.807974] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10517 23:22:16.619344 <6>[ 0.816865] kvm [1]: IPA Size Limit: 40 bits
10518 23:22:16.625982 <6>[ 0.821394] kvm [1]: GICv3: no GICV resource entry
10519 23:22:16.629230 <6>[ 0.826415] kvm [1]: disabling GICv2 emulation
10520 23:22:16.635626 <6>[ 0.831105] kvm [1]: GIC system register CPU interface enabled
10521 23:22:16.639238 <6>[ 0.837278] kvm [1]: vgic interrupt IRQ18
10522 23:22:16.645726 <6>[ 0.841638] kvm [1]: VHE mode initialized successfully
10523 23:22:16.652590 <5>[ 0.848096] Initialise system trusted keyrings
10524 23:22:16.659261 <6>[ 0.852919] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10525 23:22:16.665966 <6>[ 0.863022] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10526 23:22:16.673000 <5>[ 0.869458] NFS: Registering the id_resolver key type
10527 23:22:16.676073 <5>[ 0.874762] Key type id_resolver registered
10528 23:22:16.682968 <5>[ 0.879174] Key type id_legacy registered
10529 23:22:16.689283 <6>[ 0.883455] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10530 23:22:16.695829 <6>[ 0.890377] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10531 23:22:16.702691 <6>[ 0.898109] 9p: Installing v9fs 9p2000 file system support
10532 23:22:16.738899 <5>[ 0.936071] Key type asymmetric registered
10533 23:22:16.742542 <5>[ 0.940407] Asymmetric key parser 'x509' registered
10534 23:22:16.752458 <6>[ 0.945566] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10535 23:22:16.755919 <6>[ 0.953184] io scheduler mq-deadline registered
10536 23:22:16.759213 <6>[ 0.957961] io scheduler kyber registered
10537 23:22:16.778147 <6>[ 0.975391] EINJ: ACPI disabled.
10538 23:22:16.811352 <4>[ 1.001385] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10539 23:22:16.820894 <4>[ 1.012018] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10540 23:22:16.836157 <6>[ 1.032896] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10541 23:22:16.843787 <6>[ 1.040884] printk: console [ttyS0] disabled
10542 23:22:16.871785 <6>[ 1.065511] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10543 23:22:16.878771 <6>[ 1.074982] printk: console [ttyS0] enabled
10544 23:22:16.881722 <6>[ 1.074982] printk: console [ttyS0] enabled
10545 23:22:16.888692 <6>[ 1.083876] printk: bootconsole [mtk8250] disabled
10546 23:22:16.891845 <6>[ 1.083876] printk: bootconsole [mtk8250] disabled
10547 23:22:16.898706 <6>[ 1.095175] SuperH (H)SCI(F) driver initialized
10548 23:22:16.901526 <6>[ 1.100459] msm_serial: driver initialized
10549 23:22:16.915706 <6>[ 1.109469] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10550 23:22:16.925867 <6>[ 1.118018] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10551 23:22:16.932680 <6>[ 1.126560] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10552 23:22:16.942493 <6>[ 1.135188] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10553 23:22:16.949480 <6>[ 1.143895] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10554 23:22:16.959078 <6>[ 1.152608] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10555 23:22:16.969006 <6>[ 1.161156] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10556 23:22:16.975802 <6>[ 1.169961] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10557 23:22:16.985602 <6>[ 1.178504] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10558 23:22:16.993573 <6>[ 1.193974] loop: module loaded
10559 23:22:17.002937 <6>[ 1.199997] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10560 23:22:17.026461 <4>[ 1.223451] mtk-pmic-keys: Failed to locate of_node [id: -1]
10561 23:22:17.033771 <6>[ 1.230555] megasas: 07.719.03.00-rc1
10562 23:22:17.043574 <6>[ 1.240449] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10563 23:22:17.050469 <6>[ 1.246552] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10564 23:22:17.066523 <6>[ 1.263231] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10565 23:22:17.123191 <6>[ 1.313380] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10566 23:22:17.378304 <6>[ 1.575344] Freeing initrd memory: 18332K
10567 23:22:17.389863 <6>[ 1.586943] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10568 23:22:17.400632 <6>[ 1.597748] tun: Universal TUN/TAP device driver, 1.6
10569 23:22:17.404230 <6>[ 1.603816] thunder_xcv, ver 1.0
10570 23:22:17.407319 <6>[ 1.607318] thunder_bgx, ver 1.0
10571 23:22:17.410616 <6>[ 1.610827] nicpf, ver 1.0
10572 23:22:17.421418 <6>[ 1.614852] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10573 23:22:17.424712 <6>[ 1.622328] hns3: Copyright (c) 2017 Huawei Corporation.
10574 23:22:17.428190 <6>[ 1.627918] hclge is initializing
10575 23:22:17.434675 <6>[ 1.631498] e1000: Intel(R) PRO/1000 Network Driver
10576 23:22:17.441223 <6>[ 1.636627] e1000: Copyright (c) 1999-2006 Intel Corporation.
10577 23:22:17.445064 <6>[ 1.642640] e1000e: Intel(R) PRO/1000 Network Driver
10578 23:22:17.451060 <6>[ 1.647855] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10579 23:22:17.458167 <6>[ 1.654040] igb: Intel(R) Gigabit Ethernet Network Driver
10580 23:22:17.464397 <6>[ 1.659690] igb: Copyright (c) 2007-2014 Intel Corporation.
10581 23:22:17.471277 <6>[ 1.665527] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10582 23:22:17.477992 <6>[ 1.672045] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10583 23:22:17.481179 <6>[ 1.678515] sky2: driver version 1.30
10584 23:22:17.487590 <6>[ 1.683526] VFIO - User Level meta-driver version: 0.3
10585 23:22:17.494730 <6>[ 1.691801] usbcore: registered new interface driver usb-storage
10586 23:22:17.501284 <6>[ 1.698247] usbcore: registered new device driver onboard-usb-hub
10587 23:22:17.510426 <6>[ 1.707399] mt6397-rtc mt6359-rtc: registered as rtc0
10588 23:22:17.520283 <6>[ 1.712862] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-03T23:22:18 UTC (1712186538)
10589 23:22:17.523646 <6>[ 1.722430] i2c_dev: i2c /dev entries driver
10590 23:22:17.540659 <6>[ 1.734142] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10591 23:22:17.547192 <4>[ 1.742873] cpu cpu0: supply cpu not found, using dummy regulator
10592 23:22:17.553639 <4>[ 1.749319] cpu cpu1: supply cpu not found, using dummy regulator
10593 23:22:17.560578 <4>[ 1.755723] cpu cpu2: supply cpu not found, using dummy regulator
10594 23:22:17.567566 <4>[ 1.762125] cpu cpu3: supply cpu not found, using dummy regulator
10595 23:22:17.573835 <4>[ 1.768526] cpu cpu4: supply cpu not found, using dummy regulator
10596 23:22:17.580703 <4>[ 1.774934] cpu cpu5: supply cpu not found, using dummy regulator
10597 23:22:17.583967 <4>[ 1.781333] cpu cpu6: supply cpu not found, using dummy regulator
10598 23:22:17.590973 <4>[ 1.787751] cpu cpu7: supply cpu not found, using dummy regulator
10599 23:22:17.611646 <6>[ 1.808382] cpu cpu0: EM: created perf domain
10600 23:22:17.614627 <6>[ 1.813324] cpu cpu4: EM: created perf domain
10601 23:22:17.621682 <6>[ 1.818897] sdhci: Secure Digital Host Controller Interface driver
10602 23:22:17.628646 <6>[ 1.825329] sdhci: Copyright(c) Pierre Ossman
10603 23:22:17.635254 <6>[ 1.830287] Synopsys Designware Multimedia Card Interface Driver
10604 23:22:17.641941 <6>[ 1.836931] sdhci-pltfm: SDHCI platform and OF driver helper
10605 23:22:17.645512 <6>[ 1.837036] mmc0: CQHCI version 5.10
10606 23:22:17.652015 <6>[ 1.846902] ledtrig-cpu: registered to indicate activity on CPUs
10607 23:22:17.658596 <6>[ 1.854005] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10608 23:22:17.665745 <6>[ 1.861068] usbcore: registered new interface driver usbhid
10609 23:22:17.668739 <6>[ 1.866893] usbhid: USB HID core driver
10610 23:22:17.675864 <6>[ 1.871097] spi_master spi0: will run message pump with realtime priority
10611 23:22:17.720681 <6>[ 1.911029] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10612 23:22:17.735542 <6>[ 1.926029] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10613 23:22:17.743075 <6>[ 1.939620] mmc0: Command Queue Engine enabled
10614 23:22:17.749566 <6>[ 1.944367] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10615 23:22:17.756188 <6>[ 1.951295] cros-ec-spi spi0.0: Chrome EC device registered
10616 23:22:17.759842 <6>[ 1.951595] mmcblk0: mmc0:0001 DA4128 116 GiB
10617 23:22:17.769162 <6>[ 1.966154] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10618 23:22:17.776238 <6>[ 1.973515] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10619 23:22:17.783093 <6>[ 1.979343] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10620 23:22:17.789524 <6>[ 1.985235] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10621 23:22:17.804950 <6>[ 1.998340] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10622 23:22:17.811684 <6>[ 2.008976] NET: Registered PF_PACKET protocol family
10623 23:22:17.815426 <6>[ 2.014382] 9pnet: Installing 9P2000 support
10624 23:22:17.822009 <5>[ 2.018949] Key type dns_resolver registered
10625 23:22:17.825325 <6>[ 2.023968] registered taskstats version 1
10626 23:22:17.832084 <5>[ 2.028349] Loading compiled-in X.509 certificates
10627 23:22:17.862749 <4>[ 2.052876] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10628 23:22:17.872630 <4>[ 2.063720] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10629 23:22:17.879202 <3>[ 2.074264] debugfs: File 'uA_load' in directory '/' already present!
10630 23:22:17.885992 <3>[ 2.080968] debugfs: File 'min_uV' in directory '/' already present!
10631 23:22:17.892400 <3>[ 2.087576] debugfs: File 'max_uV' in directory '/' already present!
10632 23:22:17.899094 <3>[ 2.094182] debugfs: File 'constraint_flags' in directory '/' already present!
10633 23:22:17.910194 <3>[ 2.103898] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10634 23:22:17.919714 <6>[ 2.116531] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10635 23:22:17.926044 <6>[ 2.123280] xhci-mtk 11200000.usb: xHCI Host Controller
10636 23:22:17.932895 <6>[ 2.128795] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10637 23:22:17.943168 <6>[ 2.136638] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10638 23:22:17.949573 <6>[ 2.146064] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10639 23:22:17.956383 <6>[ 2.152135] xhci-mtk 11200000.usb: xHCI Host Controller
10640 23:22:17.962961 <6>[ 2.157614] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10641 23:22:17.970089 <6>[ 2.165261] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10642 23:22:17.976494 <6>[ 2.173164] hub 1-0:1.0: USB hub found
10643 23:22:17.979831 <6>[ 2.177189] hub 1-0:1.0: 1 port detected
10644 23:22:17.986374 <6>[ 2.181468] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10645 23:22:17.993115 <6>[ 2.190221] hub 2-0:1.0: USB hub found
10646 23:22:17.996689 <6>[ 2.194244] hub 2-0:1.0: 1 port detected
10647 23:22:18.005607 <6>[ 2.202244] mtk-msdc 11f70000.mmc: Got CD GPIO
10648 23:22:18.018034 <6>[ 2.211625] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10649 23:22:18.024873 <6>[ 2.219644] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10650 23:22:18.034442 <4>[ 2.227538] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10651 23:22:18.041420 <6>[ 2.237062] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10652 23:22:18.051167 <6>[ 2.245138] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10653 23:22:18.057923 <6>[ 2.253147] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10654 23:22:18.068502 <6>[ 2.261066] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10655 23:22:18.074717 <6>[ 2.268883] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10656 23:22:18.084677 <6>[ 2.276702] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10657 23:22:18.091940 <6>[ 2.287068] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10658 23:22:18.101771 <6>[ 2.295428] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10659 23:22:18.108131 <6>[ 2.303771] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10660 23:22:18.118071 <6>[ 2.312108] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10661 23:22:18.128403 <6>[ 2.320445] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10662 23:22:18.134656 <6>[ 2.328782] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10663 23:22:18.144874 <6>[ 2.337119] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10664 23:22:18.151274 <6>[ 2.345457] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10665 23:22:18.161283 <6>[ 2.353794] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10666 23:22:18.168321 <6>[ 2.362132] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10667 23:22:18.178315 <6>[ 2.370469] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10668 23:22:18.184796 <6>[ 2.378818] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10669 23:22:18.195156 <6>[ 2.387155] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10670 23:22:18.201372 <6>[ 2.395493] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10671 23:22:18.211398 <6>[ 2.403831] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10672 23:22:18.217993 <6>[ 2.412598] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10673 23:22:18.224707 <6>[ 2.419774] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10674 23:22:18.231515 <6>[ 2.426543] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10675 23:22:18.238066 <6>[ 2.433342] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10676 23:22:18.244474 <6>[ 2.440278] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10677 23:22:18.254275 <6>[ 2.447132] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10678 23:22:18.264072 <6>[ 2.456263] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10679 23:22:18.271254 <6>[ 2.465382] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10680 23:22:18.281381 <6>[ 2.474676] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10681 23:22:18.290999 <6>[ 2.484142] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10682 23:22:18.300957 <6>[ 2.493608] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10683 23:22:18.310645 <6>[ 2.502750] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10684 23:22:18.320522 <6>[ 2.512218] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10685 23:22:18.327545 <6>[ 2.521336] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10686 23:22:18.337428 <6>[ 2.530630] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10687 23:22:18.350367 <6>[ 2.540790] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10688 23:22:18.357022 <6>[ 2.552358] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10689 23:22:18.364787 <6>[ 2.562061] Trying to probe devices needed for running init ...
10690 23:22:18.385715 <6>[ 2.579466] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10691 23:22:18.413970 <6>[ 2.610763] hub 2-1:1.0: USB hub found
10692 23:22:18.417033 <6>[ 2.615221] hub 2-1:1.0: 3 ports detected
10693 23:22:18.425116 <6>[ 2.622291] hub 2-1:1.0: USB hub found
10694 23:22:18.428395 <6>[ 2.626618] hub 2-1:1.0: 3 ports detected
10695 23:22:18.537558 <6>[ 2.731442] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10696 23:22:18.692280 <6>[ 2.889360] hub 1-1:1.0: USB hub found
10697 23:22:18.695251 <6>[ 2.893842] hub 1-1:1.0: 4 ports detected
10698 23:22:18.704935 <6>[ 2.902187] hub 1-1:1.0: USB hub found
10699 23:22:18.708475 <6>[ 2.906640] hub 1-1:1.0: 4 ports detected
10700 23:22:18.777682 <6>[ 2.971703] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10701 23:22:19.029951 <6>[ 3.223491] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10702 23:22:19.162201 <6>[ 3.359296] hub 1-1.4:1.0: USB hub found
10703 23:22:19.165632 <6>[ 3.363956] hub 1-1.4:1.0: 2 ports detected
10704 23:22:19.175222 <6>[ 3.372486] hub 1-1.4:1.0: USB hub found
10705 23:22:19.178479 <6>[ 3.377093] hub 1-1.4:1.0: 2 ports detected
10706 23:22:19.477759 <6>[ 3.671437] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10707 23:22:19.669080 <6>[ 3.863469] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10708 23:22:30.663264 <6>[ 14.864858] ALSA device list:
10709 23:22:30.669724 <6>[ 14.868147] No soundcards found.
10710 23:22:30.677371 <6>[ 14.875572] Freeing unused kernel memory: 8448K
10711 23:22:30.681426 <6>[ 14.880601] Run /init as init process
10712 23:22:30.690499 Loading, please wait...
10713 23:22:30.716616 Starting systemd-udevd version 252.22-1~deb12u1
10714 23:22:30.716713
10715 23:22:30.950094 <6>[ 15.145517] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10716 23:22:30.957613 <6>[ 15.145672] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10717 23:22:30.966960 <6>[ 15.158054] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10718 23:22:30.973622 <6>[ 15.169464] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10719 23:22:30.983214 <3>[ 15.172655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 23:22:30.986829 <6>[ 15.183833] remoteproc remoteproc0: scp is available
10721 23:22:30.996703 <3>[ 15.186634] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 23:22:30.999936 <6>[ 15.191623] remoteproc remoteproc0: powering up scp
10723 23:22:31.010254 <3>[ 15.199975] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 23:22:31.017006 <4>[ 15.202456] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10725 23:22:31.023784 <4>[ 15.202697] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10726 23:22:31.033371 <6>[ 15.204773] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10727 23:22:31.036437 <6>[ 15.204800] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10728 23:22:31.043105 <6>[ 15.205342] mc: Linux media interface: v0.10
10729 23:22:31.050394 <6>[ 15.205577] usbcore: registered new device driver r8152-cfgselector
10730 23:22:31.057174 <6>[ 15.210084] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10731 23:22:31.063903 <3>[ 15.225912] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 23:22:31.073772 <4>[ 15.232558] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10733 23:22:31.077598 <4>[ 15.232558] Fallback method does not support PEC.
10734 23:22:31.088349 <3>[ 15.236054] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 23:22:31.094855 <3>[ 15.259021] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10736 23:22:31.104587 <3>[ 15.260594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10737 23:22:31.108321 <6>[ 15.261354] videodev: Linux video capture interface: v2.00
10738 23:22:31.118303 <3>[ 15.290661] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10739 23:22:31.124620 <6>[ 15.296535] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10740 23:22:31.131208 <6>[ 15.296540] pci_bus 0000:00: root bus resource [bus 00-ff]
10741 23:22:31.137528 <6>[ 15.296545] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10742 23:22:31.147727 <6>[ 15.296547] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10743 23:22:31.154113 <6>[ 15.296575] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10744 23:22:31.161215 <6>[ 15.296588] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10745 23:22:31.164126 <6>[ 15.296661] pci 0000:00:00.0: supports D1 D2
10746 23:22:31.174348 <6>[ 15.296665] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10747 23:22:31.181388 <6>[ 15.297826] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10748 23:22:31.187753 <6>[ 15.297920] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10749 23:22:31.194079 <6>[ 15.297946] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10750 23:22:31.200767 <6>[ 15.297962] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10751 23:22:31.210987 <6>[ 15.297978] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10752 23:22:31.213997 <6>[ 15.298087] pci 0000:01:00.0: supports D1 D2
10753 23:22:31.221042 <6>[ 15.298089] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10754 23:22:31.231409 <3>[ 15.299120] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10755 23:22:31.238133 <6>[ 15.311313] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10756 23:22:31.244696 <6>[ 15.311726] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10757 23:22:31.254300 <3>[ 15.312971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 23:22:31.261150 <6>[ 15.319801] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10759 23:22:31.271093 <6>[ 15.321832] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10760 23:22:31.280637 <6>[ 15.321937] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10761 23:22:31.290655 <6>[ 15.322296] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10762 23:22:31.297094 <3>[ 15.328899] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10763 23:22:31.303806 <6>[ 15.334349] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10764 23:22:31.313798 <3>[ 15.341533] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 23:22:31.324090 <4>[ 15.343636] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10766 23:22:31.330927 <4>[ 15.343646] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10767 23:22:31.337068 <6>[ 15.348684] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10768 23:22:31.347438 <6>[ 15.351424] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10769 23:22:31.350789 <6>[ 15.355562] Bluetooth: Core ver 2.22
10770 23:22:31.357364 <6>[ 15.355618] NET: Registered PF_BLUETOOTH protocol family
10771 23:22:31.363788 <6>[ 15.355619] Bluetooth: HCI device and connection manager initialized
10772 23:22:31.367184 <6>[ 15.355633] Bluetooth: HCI socket layer initialized
10773 23:22:31.374208 <6>[ 15.355637] Bluetooth: L2CAP socket layer initialized
10774 23:22:31.377336 <6>[ 15.355642] Bluetooth: SCO socket layer initialized
10775 23:22:31.386929 <3>[ 15.357636] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 23:22:31.393716 <6>[ 15.358934] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10777 23:22:31.403637 <6>[ 15.360711] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10778 23:22:31.410469 <6>[ 15.365111] remoteproc remoteproc0: remote processor scp is now up
10779 23:22:31.417099 <3>[ 15.369629] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 23:22:31.423521 <6>[ 15.370272] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10781 23:22:31.433125 <6>[ 15.370315] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10782 23:22:31.440015 <6>[ 15.370332] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10783 23:22:31.447000 <6>[ 15.370351] pci 0000:00:00.0: PCI bridge to [bus 01]
10784 23:22:31.453353 <6>[ 15.370366] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10785 23:22:31.459856 <6>[ 15.370597] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10786 23:22:31.466451 <6>[ 15.371613] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10787 23:22:31.473254 <6>[ 15.371863] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10788 23:22:31.479589 <6>[ 15.386644] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10789 23:22:31.486689 <3>[ 15.391060] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10790 23:22:31.493251 <6>[ 15.391333] r8152 2-1.3:1.0 eth0: v1.12.13
10791 23:22:31.496353 <6>[ 15.391406] usbcore: registered new interface driver r8152
10792 23:22:31.506342 <5>[ 15.394283] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10793 23:22:31.516447 <6>[ 15.400021] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10794 23:22:31.526512 <3>[ 15.405971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10795 23:22:31.532628 <3>[ 15.405978] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10796 23:22:31.542708 <3>[ 15.405984] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10797 23:22:31.549155 <3>[ 15.405987] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10798 23:22:31.559620 <3>[ 15.406010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10799 23:22:31.565800 <5>[ 15.406844] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10800 23:22:31.569322 <6>[ 15.407291] usbcore: registered new interface driver btusb
10801 23:22:31.579499 <5>[ 15.407448] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10802 23:22:31.585786 <6>[ 15.407471] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10803 23:22:31.595724 <4>[ 15.407646] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10804 23:22:31.599295 <6>[ 15.407666] cfg80211: failed to load regulatory.db
10805 23:22:31.609289 <4>[ 15.408947] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10806 23:22:31.615702 <3>[ 15.408958] Bluetooth: hci0: Failed to load firmware file (-2)
10807 23:22:31.622266 <3>[ 15.408963] Bluetooth: hci0: Failed to set up firmware (-2)
10808 23:22:31.632393 <4>[ 15.408969] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10809 23:22:31.639432 <6>[ 15.413765] usbcore: registered new interface driver uvcvideo
10810 23:22:31.645742 <6>[ 15.413963] usbcore: registered new interface driver cdc_ether
10811 23:22:31.649005 <6>[ 15.418503] usbcore: registered new interface driver r8153_ecm
10812 23:22:31.659413 <6>[ 15.500481] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10813 23:22:31.662505 <6>[ 15.514219] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10814 23:22:31.668820 <6>[ 15.517279] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10815 23:22:31.692683 <6>[ 15.891337] mt7921e 0000:01:00.0: ASIC revision: 79610010
10816 23:22:31.795554 <6>[ 15.990660] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10817 23:22:31.798611 <6>[ 15.990660]
10818 23:22:31.813979 Begin: Loading essential drivers ... done.
10819 23:22:31.816826 Begin: Running /scripts/init-premount ... done.
10820 23:22:31.823603 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10821 23:22:31.833376 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10822 23:22:31.836709 Device /sys/class/net/enx002432307852 found
10823 23:22:31.836791 done.
10824 23:22:31.843248 Begin: Waiting up to 180 secs for any network device to become available ... done.
10825 23:22:31.907828 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10826 23:22:32.064659 <6>[ 16.260243] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10827 23:22:32.776743 <6>[ 16.975826] r8152 2-1.3:1.0 enx002432307852: carrier on
10828 23:22:32.932356 <6>[ 17.131369] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10829 23:22:33.014621 IP-Config: no response after 2 secs - giving up
10830 23:22:33.044869 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:3d mtu 1500 DHCP
10831 23:22:33.743567 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10832 23:22:33.750014 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10833 23:22:33.757071 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10834 23:22:33.763362 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10835 23:22:33.770383 host : mt8192-asurada-spherion-r0-cbg-3
10836 23:22:33.776713 domain : lava-rack
10837 23:22:33.780288 rootserver: 192.168.201.1 rootpath:
10838 23:22:33.783085 filename :
10839 23:22:33.884800 done.
10840 23:22:33.892293 Begin: Running /scripts/nfs-bottom ... done.
10841 23:22:33.912546 Begin: Running /scripts/init-bottom ... done.
10842 23:22:35.289994 <6>[ 19.488873] NET: Registered PF_INET6 protocol family
10843 23:22:35.297515 <6>[ 19.496380] Segment Routing with IPv6
10844 23:22:35.300576 <6>[ 19.500386] In-situ OAM (IOAM) with IPv6
10845 23:22:35.480089 <30>[ 19.652517] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10846 23:22:35.486427 <30>[ 19.685618] systemd[1]: Detected architecture arm64.
10847 23:22:35.494868
10848 23:22:35.498214 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10849 23:22:35.498346
10850 23:22:35.498454
10851 23:22:35.521521 <30>[ 19.720668] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10852 23:22:36.630671 <30>[ 20.826442] systemd[1]: Queued start job for default target graphical.target.
10853 23:22:36.661252 <30>[ 20.856843] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10854 23:22:36.667591 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10855 23:22:36.667676
10856 23:22:36.689282 <30>[ 20.885275] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10857 23:22:36.699319 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10858 23:22:36.699404
10859 23:22:36.717326 <30>[ 20.913189] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10860 23:22:36.727537 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10861 23:22:36.727630
10862 23:22:36.744864 <30>[ 20.940776] systemd[1]: Created slice user.slice - User and Session Slice.
10863 23:22:36.751523 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10864 23:22:36.751605
10865 23:22:36.775791 <30>[ 20.968331] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10866 23:22:36.782727 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10867 23:22:36.782812
10868 23:22:36.803046 <30>[ 20.995693] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10869 23:22:36.809553 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10870 23:22:36.809637
10871 23:22:36.837992 <30>[ 21.024122] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10872 23:22:36.848264 <30>[ 21.044042] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10873 23:22:36.854473 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10874 23:22:36.854555
10875 23:22:36.871430 <30>[ 21.067465] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10876 23:22:36.878054 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10877 23:22:36.878155
10878 23:22:36.895695 <30>[ 21.091537] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10879 23:22:36.905428 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10880 23:22:36.905514
10881 23:22:36.920219 <30>[ 21.119558] systemd[1]: Reached target paths.target - Path Units.
10882 23:22:36.927023 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10883 23:22:36.930121
10884 23:22:36.948420 <30>[ 21.143905] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10885 23:22:36.954173 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10886 23:22:36.954278
10887 23:22:36.968170 <30>[ 21.167452] systemd[1]: Reached target slices.target - Slice Units.
10888 23:22:36.978107 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10889 23:22:36.978190
10890 23:22:36.992653 <30>[ 21.191943] systemd[1]: Reached target swap.target - Swaps.
10891 23:22:36.999470 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10892 23:22:36.999592
10893 23:22:37.019999 <30>[ 21.215967] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10894 23:22:37.029835 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10895 23:22:37.029920
10896 23:22:37.048473 <30>[ 21.244442] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10897 23:22:37.058469 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10898 23:22:37.058554
10899 23:22:37.078518 <30>[ 21.274424] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10900 23:22:37.088867 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10901 23:22:37.088951
10902 23:22:37.104861 <30>[ 21.301054] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10903 23:22:37.115134 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10904 23:22:37.115218
10905 23:22:37.132260 <30>[ 21.328266] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10906 23:22:37.138847 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10907 23:22:37.138929
10908 23:22:37.157141 <30>[ 21.352941] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10909 23:22:37.166825 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10910 23:22:37.166909
10911 23:22:37.186488 <30>[ 21.382601] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10912 23:22:37.196463 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10913 23:22:37.196548
10914 23:22:37.211877 <30>[ 21.407938] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10915 23:22:37.218777 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10916 23:22:37.222519
10917 23:22:37.263628 <30>[ 21.459917] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10918 23:22:37.270673 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10919 23:22:37.270762
10920 23:22:37.290110 <30>[ 21.486271] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10921 23:22:37.296813 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10922 23:22:37.296899
10923 23:22:37.344207 <30>[ 21.539985] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10924 23:22:37.350832 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10925 23:22:37.350947
10926 23:22:37.378480 <30>[ 21.568049] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10927 23:22:37.394621 <30>[ 21.590169] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10928 23:22:37.403823 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10929 23:22:37.403912
10930 23:22:37.425217 <30>[ 21.621053] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10931 23:22:37.431995 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10932 23:22:37.432079
10933 23:22:37.457429 <30>[ 21.653450] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10934 23:22:37.463845 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10935 23:22:37.463930
10936 23:22:37.491274 <30>[ 21.687300] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10937 23:22:37.497944 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10938 23:22:37.507574 <6>[ 21.702020] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10939 23:22:37.507659
10940 23:22:37.552380 <30>[ 21.748301] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10941 23:22:37.562247 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10942 23:22:37.562360
10943 23:22:37.585965 <30>[ 21.781794] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10944 23:22:37.592745 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10945 23:22:37.592936
10946 23:22:37.636322 <6>[ 21.834783] fuse: init (API version 7.37)
10947 23:22:37.645517 <30>[ 21.840620] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10948 23:22:37.652574 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10949 23:22:37.653098
10950 23:22:37.677654 <30>[ 21.873120] systemd[1]: Starting systemd-journald.service - Journal Service...
10951 23:22:37.684108 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10952 23:22:37.684575
10953 23:22:37.717985 <30>[ 21.913603] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10954 23:22:37.724736 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10955 23:22:37.725170
10956 23:22:37.755384 <30>[ 21.947527] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10957 23:22:37.761554 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10958 23:22:37.761986
10959 23:22:37.783888 <30>[ 21.979065] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10960 23:22:37.793627 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10961 23:22:37.794059
10962 23:22:37.817436 <30>[ 22.013320] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10963 23:22:37.824074 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10964 23:22:37.824508
10965 23:22:37.849887 <30>[ 22.045377] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10966 23:22:37.857205 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10967 23:22:37.857650
10968 23:22:37.867214 <3>[ 22.060651] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 23:22:37.877378 <30>[ 22.072199] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10970 23:22:37.883735 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10971 23:22:37.884175
10972 23:22:37.894843 <3>[ 22.090487] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 23:22:37.905417 <30>[ 22.100024] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10974 23:22:37.911097 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10975 23:22:37.911539
10976 23:22:37.932482 <30>[ 22.128222] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10977 23:22:37.943066 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10978 23:22:37.943535
10979 23:22:37.949845 <3>[ 22.146192] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 23:22:37.961061 <30>[ 22.156548] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10981 23:22:37.967859 <30>[ 22.164448] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10982 23:22:37.981501 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 22.176114] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 23:22:37.984918 onfigfs…[0m - Load Kernel Module configfs.
10984 23:22:37.988289
10985 23:22:38.001520 <30>[ 22.196396] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10986 23:22:38.011088 <3>[ 22.206330] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 23:22:38.021047 <30>[ 22.216451] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10988 23:22:38.027963 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10989 23:22:38.028489
10990 23:22:38.048796 <3>[ 22.244194] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10991 23:22:38.055432 <30>[ 22.244307] systemd[1]: modprobe@drm.service: Deactivated successfully.
10992 23:22:38.065474 <30>[ 22.260493] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10993 23:22:38.079556 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m -<3>[ 22.273706] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 23:22:38.083079 Load Kernel Module drm.
10995 23:22:38.083659
10996 23:22:38.101835 <30>[ 22.296512] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10997 23:22:38.108938 <3>[ 22.303529] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10998 23:22:38.118784 <30>[ 22.304808] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10999 23:22:38.125740 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11000 23:22:38.126322
11001 23:22:38.137735 <3>[ 22.333227] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11002 23:22:38.148243 <30>[ 22.344093] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11003 23:22:38.154787 <30>[ 22.351839] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11004 23:22:38.163177 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11005 23:22:38.165474
11006 23:22:38.177883 <3>[ 22.373460] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 23:22:38.188871 <30>[ 22.384102] systemd[1]: modprobe@loop.service: Deactivated successfully.
11008 23:22:38.196008 <30>[ 22.391952] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11009 23:22:38.205662 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11010 23:22:38.206172
11011 23:22:38.229468 <30>[ 22.424942] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
11012 23:22:38.238887 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11013 23:22:38.239361
11014 23:22:38.256937 <30>[ 22.452066] systemd[1]: Started systemd-journald.service - Journal Service.
11015 23:22:38.280511 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Serv<4>[ 22.466122] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11016 23:22:38.286921 <3>[ 22.482678] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11017 23:22:38.287344 ice.
11018 23:22:38.287668
11019 23:22:38.315915 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11020 23:22:38.316468
11021 23:22:38.333598 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11022 23:22:38.334130
11023 23:22:38.353863 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11024 23:22:38.354475
11025 23:22:38.378539 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11026 23:22:38.379094
11027 23:22:38.436924 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11028 23:22:38.437622
11029 23:22:38.458504 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11030 23:22:38.458960
11031 23:22:38.479511 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11032 23:22:38.480000
11033 23:22:38.504187 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11034 23:22:38.504712
11035 23:22:38.537427 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11036 23:22:38.537869
11037 23:22:38.558339 <46>[ 22.754307] systemd-journald[311]: Received client request to flush runtime journal.
11038 23:22:38.576783 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11039 23:22:38.577496
11040 23:22:38.613877 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11041 23:22:38.614140
11042 23:22:38.636552 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11043 23:22:38.636745
11044 23:22:38.656946 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11045 23:22:38.657129
11046 23:22:38.676865 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11047 23:22:38.677059
11048 23:22:39.949830 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11049 23:22:39.950003
11050 23:22:39.969384 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11051 23:22:39.969472
11052 23:22:40.025483 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11053 23:22:40.025615
11054 23:22:40.118147 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11055 23:22:40.118263
11056 23:22:40.136337 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11057 23:22:40.136452
11058 23:22:40.155456 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11059 23:22:40.155541
11060 23:22:40.216066 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11061 23:22:40.216159
11062 23:22:40.242820 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11063 23:22:40.242937
11064 23:22:40.479579 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11065 23:22:40.479728
11066 23:22:40.525925 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11067 23:22:40.526025
11068 23:22:40.564879 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11069 23:22:40.564995
11070 23:22:40.917756 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11071 23:22:40.917930
11072 23:22:40.997300 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11073 23:22:40.997469
11074 23:22:41.047906 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11075 23:22:41.048026
11076 23:22:41.100263 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11077 23:22:41.100402
11078 23:22:41.126086 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11079 23:22:41.126208
11080 23:22:41.144227 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11081 23:22:41.144313
11082 23:22:41.163278 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11083 23:22:41.163364
11084 23:22:41.202530 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11085 23:22:41.202640
11086 23:22:41.251874 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11087 23:22:41.251989
11088 23:22:41.286136 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11089 23:22:41.286253
11090 23:22:41.307632 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11091 23:22:41.307720
11092 23:22:41.324360 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11093 23:22:41.324472
11094 23:22:41.357889 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11095 23:22:41.357975
11096 23:22:41.483038 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11097 23:22:41.483184
11098 23:22:41.499760 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11099 23:22:41.499869
11100 23:22:41.522536 [[0;32m OK [0m] Started [0;1;39msystemd-tmp<46>[ 25.718907] systemd-journald[311]: Time jumped backwards, rotating.
11101 23:22:41.526016 files-c… Cleanup of Temporary Directories.
11102 23:22:41.526104
11103 23:22:41.543149 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11104 23:22:41.543233
11105 23:22:41.567441 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11106 23:22:41.567528
11107 23:22:41.930341 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11108 23:22:41.930540
11109 23:22:41.947519 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11110 23:22:41.947609
11111 23:22:42.287231 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11112 23:22:42.287378
11113 23:22:42.620211 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11114 23:22:42.620386
11115 23:22:42.639591 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11116 23:22:42.639700
11117 23:22:42.906204 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11118 23:22:42.906377
11119 23:22:42.926900 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11120 23:22:42.926998
11121 23:22:42.947172 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11122 23:22:42.947268
11123 23:22:43.012726 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11124 23:22:43.012846
11125 23:22:43.076428 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11126 23:22:43.076542
11127 23:22:43.161174 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11128 23:22:43.161318
11129 23:22:43.184074 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11130 23:22:43.184159
11131 23:22:43.345163 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11132 23:22:43.345334
11133 23:22:43.403670 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11134 23:22:43.403785
11135 23:22:43.426978 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11136 23:22:43.427066
11137 23:22:43.444344 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11138 23:22:43.444461
11139 23:22:43.470587 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11140 23:22:43.470674
11141 23:22:43.489421 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11142 23:22:43.489528
11143 23:22:43.529364 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11144 23:22:43.529483
11145 23:22:43.564211 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11146 23:22:43.564299
11147 23:22:43.584116 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11148 23:22:43.584199
11149 23:22:43.646668 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11150 23:22:43.646771
11151 23:22:43.672719 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11152 23:22:43.672837
11153 23:22:43.774639 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11154 23:22:43.774779
11155 23:22:43.797828 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11156 23:22:43.797912
11157 23:22:43.898115
11158 23:22:43.898227
11159 23:22:43.901313 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11160 23:22:43.901421
11161 23:22:43.904709 debian-bookworm-arm64 login: root (automatic login)
11162 23:22:43.904816
11163 23:22:43.904908
11164 23:22:44.189149 Linux debian-bookworm-arm64 6.1.83-cip18 #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024 aarch64
11165 23:22:44.189681
11166 23:22:44.195424 The programs included with the Debian GNU/Linux system are free software;
11167 23:22:44.201784 the exact distribution terms for each program are described in the
11168 23:22:44.205061 individual files in /usr/share/doc/*/copyright.
11169 23:22:44.205596
11170 23:22:44.211972 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11171 23:22:44.214807 permitted by applicable law.
11172 23:22:44.349717 Matched prompt #10: / #
11174 23:22:44.351145 Setting prompt string to ['/ #']
11175 23:22:44.351590 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11177 23:22:44.352574 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11178 23:22:44.353011 start: 2.2.6 expect-shell-connection (timeout 00:03:15) [common]
11179 23:22:44.353421 Setting prompt string to ['/ #']
11180 23:22:44.353736 Forcing a shell prompt, looking for ['/ #']
11182 23:22:44.404494 / #
11183 23:22:44.404998 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11184 23:22:44.405363 Waiting using forced prompt support (timeout 00:02:30)
11185 23:22:44.411012
11186 23:22:44.411780 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11187 23:22:44.412239 start: 2.2.7 export-device-env (timeout 00:03:15) [common]
11189 23:22:44.513459 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13248464/extract-nfsrootfs-huwavqnr'
11190 23:22:44.520052 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13248464/extract-nfsrootfs-huwavqnr'
11192 23:22:44.621442 / # export NFS_SERVER_IP='192.168.201.1'
11193 23:22:44.628120 export NFS_SERVER_IP='192.168.201.1'
11194 23:22:44.628895 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11195 23:22:44.629376 end: 2.2 depthcharge-retry (duration 00:01:45) [common]
11196 23:22:44.629802 end: 2 depthcharge-action (duration 00:01:45) [common]
11197 23:22:44.630256 start: 3 lava-test-retry (timeout 00:01:00) [common]
11198 23:22:44.630756 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11199 23:22:44.631131 Using namespace: common
11201 23:22:44.732165 / # #
11202 23:22:44.732803 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11203 23:22:44.738362 #
11204 23:22:44.739130 Using /lava-13248464
11206 23:22:44.840093 / # export SHELL=/bin/sh
11207 23:22:44.846844 export SHELL=/bin/sh
11209 23:22:44.948421 / # . /lava-13248464/environment
11210 23:22:44.954717 . /lava-13248464/environment
11212 23:22:45.062514 / # /lava-13248464/bin/lava-test-runner /lava-13248464/0
11213 23:22:45.063038 Test shell timeout: 10s (minimum of the action and connection timeout)
11214 23:22:45.068810 /lava-13248464/bin/lava-test-runner /lava-13248464/0
11215 23:22:45.348871 + export TESTRUN_ID=0_dmesg
11216 23:22:45.352293 + cd /lava-13248464/0/tests/0_dmesg
11217 23:22:45.355598 + cat uuid
11218 23:22:45.369307 + <8>[ 29.569748] <LAVA_SIGNAL_STARTRUN 0_dmesg 13248464_1.6.2.3.1>
11219 23:22:45.369574 Received signal: <STARTRUN> 0_dmesg 13248464_1.6.2.3.1
11220 23:22:45.369653 Starting test lava.0_dmesg (13248464_1.6.2.3.1)
11221 23:22:45.369740 Skipping test definition patterns.
11222 23:22:45.373112 UUID=13248464_1.6.2.3.1
11223 23:22:45.373194 + set +x
11224 23:22:45.378968 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11225 23:22:45.503516 <8>[ 29.700409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11226 23:22:45.503828 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11228 23:22:45.590616 <8>[ 29.787249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11229 23:22:45.590909 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11231 23:22:45.675968 <8>[ 29.872786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11232 23:22:45.676254 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11234 23:22:45.682213 + <8>[ 29.882698] <LAVA_SIGNAL_ENDRUN 0_dmesg 13248464_1.6.2.3.1>
11235 23:22:45.682328 set +x
11236 23:22:45.682636 Received signal: <ENDRUN> 0_dmesg 13248464_1.6.2.3.1
11237 23:22:45.682740 Ending use of test pattern.
11238 23:22:45.682827 Ending test lava.0_dmesg (13248464_1.6.2.3.1), duration 0.31
11240 23:22:45.689815 <LAVA_TEST_RUNNER EXIT>
11241 23:22:45.690065 ok: lava_test_shell seems to have completed
11242 23:22:45.690167 alert: pass
crit: pass
emerg: pass
11243 23:22:45.690255 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11244 23:22:45.690335 end: 3 lava-test-retry (duration 00:00:01) [common]
11245 23:22:45.690446 start: 4 finalize (timeout 00:07:48) [common]
11246 23:22:45.690550 start: 4.1 power-off (timeout 00:00:30) [common]
11247 23:22:45.690699 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11248 23:22:45.767766 >> Command sent successfully.
11249 23:22:45.770214 Returned 0 in 0 seconds
11250 23:22:45.870602 end: 4.1 power-off (duration 00:00:00) [common]
11252 23:22:45.870927 start: 4.2 read-feedback (timeout 00:07:47) [common]
11253 23:22:45.871201 Listened to connection for namespace 'common' for up to 1s
11254 23:22:46.872131 Finalising connection for namespace 'common'
11255 23:22:46.872344 Disconnecting from shell: Finalise
11256 23:22:46.872450 / #
11257 23:22:46.972813 end: 4.2 read-feedback (duration 00:00:01) [common]
11258 23:22:46.972976 end: 4 finalize (duration 00:00:01) [common]
11259 23:22:46.973096 Cleaning after the job
11260 23:22:46.973195 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248464/tftp-deploy-vppbiez6/ramdisk
11261 23:22:46.975998 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248464/tftp-deploy-vppbiez6/kernel
11262 23:22:46.989697 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248464/tftp-deploy-vppbiez6/dtb
11263 23:22:46.989880 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248464/tftp-deploy-vppbiez6/nfsrootfs
11264 23:22:47.065189 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248464/tftp-deploy-vppbiez6/modules
11265 23:22:47.072520 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13248464
11266 23:22:47.453300 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13248464
11267 23:22:47.453514 Job finished correctly