Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
- Kernel Errors: 31
- Boot result: PASS
1 23:17:43.774361 lava-dispatcher, installed at version: 2024.01
2 23:17:43.774592 start: 0 validate
3 23:17:43.774724 Start time: 2024-04-03 23:17:43.774716+00:00 (UTC)
4 23:17:43.774853 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:17:43.774985 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-cros-ec%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:17:44.028961 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:17:44.029684 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:17:44.292268 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:17:44.292998 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:18:11.962162 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:18:11.962892 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.83-cip18%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:18:12.491793 validate duration: 28.72
14 23:18:12.493112 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:18:12.493660 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:18:12.494153 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:18:12.494778 Not decompressing ramdisk as can be used compressed.
18 23:18:12.495254 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-cros-ec/20240313.0/arm64/rootfs.cpio.gz
19 23:18:12.495612 saving as /var/lib/lava/dispatcher/tmp/13248414/tftp-deploy-dekbzbsg/ramdisk/rootfs.cpio.gz
20 23:18:12.496001 total size: 39026414 (37 MB)
21 23:18:22.423918 progress 0 % (0 MB)
22 23:18:22.467975 progress 5 % (1 MB)
23 23:18:22.484325 progress 10 % (3 MB)
24 23:18:22.495900 progress 15 % (5 MB)
25 23:18:22.506075 progress 20 % (7 MB)
26 23:18:22.516148 progress 25 % (9 MB)
27 23:18:22.526155 progress 30 % (11 MB)
28 23:18:22.536120 progress 35 % (13 MB)
29 23:18:22.546337 progress 40 % (14 MB)
30 23:18:22.556571 progress 45 % (16 MB)
31 23:18:22.566725 progress 50 % (18 MB)
32 23:18:22.576854 progress 55 % (20 MB)
33 23:18:22.586903 progress 60 % (22 MB)
34 23:18:22.597098 progress 65 % (24 MB)
35 23:18:22.607120 progress 70 % (26 MB)
36 23:18:22.617203 progress 75 % (27 MB)
37 23:18:22.627029 progress 80 % (29 MB)
38 23:18:22.637141 progress 85 % (31 MB)
39 23:18:22.647333 progress 90 % (33 MB)
40 23:18:22.657381 progress 95 % (35 MB)
41 23:18:22.667416 progress 100 % (37 MB)
42 23:18:22.667736 37 MB downloaded in 10.17 s (3.66 MB/s)
43 23:18:22.667913 end: 1.1.1 http-download (duration 00:00:10) [common]
45 23:18:22.668153 end: 1.1 download-retry (duration 00:00:10) [common]
46 23:18:22.668238 start: 1.2 download-retry (timeout 00:09:50) [common]
47 23:18:22.668320 start: 1.2.1 http-download (timeout 00:09:50) [common]
48 23:18:22.668459 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:18:22.668527 saving as /var/lib/lava/dispatcher/tmp/13248414/tftp-deploy-dekbzbsg/kernel/Image
50 23:18:22.668587 total size: 54286848 (51 MB)
51 23:18:22.668647 No compression specified
52 23:18:22.669754 progress 0 % (0 MB)
53 23:18:22.683487 progress 5 % (2 MB)
54 23:18:22.697559 progress 10 % (5 MB)
55 23:18:22.711761 progress 15 % (7 MB)
56 23:18:22.725950 progress 20 % (10 MB)
57 23:18:22.739928 progress 25 % (12 MB)
58 23:18:22.754070 progress 30 % (15 MB)
59 23:18:22.768115 progress 35 % (18 MB)
60 23:18:22.782403 progress 40 % (20 MB)
61 23:18:22.796465 progress 45 % (23 MB)
62 23:18:22.810418 progress 50 % (25 MB)
63 23:18:22.824591 progress 55 % (28 MB)
64 23:18:22.838811 progress 60 % (31 MB)
65 23:18:22.852754 progress 65 % (33 MB)
66 23:18:22.866826 progress 70 % (36 MB)
67 23:18:22.880990 progress 75 % (38 MB)
68 23:18:22.895326 progress 80 % (41 MB)
69 23:18:22.909507 progress 85 % (44 MB)
70 23:18:22.923595 progress 90 % (46 MB)
71 23:18:22.937410 progress 95 % (49 MB)
72 23:18:22.951337 progress 100 % (51 MB)
73 23:18:22.951577 51 MB downloaded in 0.28 s (182.95 MB/s)
74 23:18:22.951735 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:18:22.951966 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:18:22.952052 start: 1.3 download-retry (timeout 00:09:50) [common]
78 23:18:22.952142 start: 1.3.1 http-download (timeout 00:09:50) [common]
79 23:18:22.952286 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:18:22.952356 saving as /var/lib/lava/dispatcher/tmp/13248414/tftp-deploy-dekbzbsg/dtb/mt8192-asurada-spherion-r0.dtb
81 23:18:22.952417 total size: 47230 (0 MB)
82 23:18:22.952478 No compression specified
83 23:18:23.220985 progress 69 % (0 MB)
84 23:18:23.222472 progress 100 % (0 MB)
85 23:18:23.223369 0 MB downloaded in 0.27 s (0.17 MB/s)
86 23:18:23.224110 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:18:23.225396 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:18:23.225869 start: 1.4 download-retry (timeout 00:09:49) [common]
90 23:18:23.226329 start: 1.4.1 http-download (timeout 00:09:49) [common]
91 23:18:23.226980 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.83-cip18/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:18:23.227362 saving as /var/lib/lava/dispatcher/tmp/13248414/tftp-deploy-dekbzbsg/modules/modules.tar
93 23:18:23.227731 total size: 8629908 (8 MB)
94 23:18:23.228206 Using unxz to decompress xz
95 23:18:23.489723 progress 0 % (0 MB)
96 23:18:23.508917 progress 5 % (0 MB)
97 23:18:23.533279 progress 10 % (0 MB)
98 23:18:23.557205 progress 15 % (1 MB)
99 23:18:23.580686 progress 20 % (1 MB)
100 23:18:23.605351 progress 25 % (2 MB)
101 23:18:23.630877 progress 30 % (2 MB)
102 23:18:23.654797 progress 35 % (2 MB)
103 23:18:23.680021 progress 40 % (3 MB)
104 23:18:23.703714 progress 45 % (3 MB)
105 23:18:23.728411 progress 50 % (4 MB)
106 23:18:23.752744 progress 55 % (4 MB)
107 23:18:23.780636 progress 60 % (4 MB)
108 23:18:23.805492 progress 65 % (5 MB)
109 23:18:23.830124 progress 70 % (5 MB)
110 23:18:23.853956 progress 75 % (6 MB)
111 23:18:23.878899 progress 80 % (6 MB)
112 23:18:23.904460 progress 85 % (7 MB)
113 23:18:23.932118 progress 90 % (7 MB)
114 23:18:23.960815 progress 95 % (7 MB)
115 23:18:23.987940 progress 100 % (8 MB)
116 23:18:23.993332 8 MB downloaded in 0.77 s (10.75 MB/s)
117 23:18:23.993583 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:18:23.993843 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:18:23.993937 start: 1.5 prepare-tftp-overlay (timeout 00:09:48) [common]
121 23:18:23.994033 start: 1.5.1 extract-nfsrootfs (timeout 00:09:48) [common]
122 23:18:23.994116 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:18:23.994204 start: 1.5.2 lava-overlay (timeout 00:09:48) [common]
124 23:18:23.994434 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7
125 23:18:23.994573 makedir: /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin
126 23:18:23.994678 makedir: /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/tests
127 23:18:23.994778 makedir: /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/results
128 23:18:23.994896 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-add-keys
129 23:18:23.995045 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-add-sources
130 23:18:23.995177 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-background-process-start
131 23:18:23.995308 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-background-process-stop
132 23:18:23.995435 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-common-functions
133 23:18:23.995563 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-echo-ipv4
134 23:18:23.995729 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-install-packages
135 23:18:23.995856 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-installed-packages
136 23:18:23.996008 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-os-build
137 23:18:23.996166 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-probe-channel
138 23:18:23.996295 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-probe-ip
139 23:18:23.996423 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-target-ip
140 23:18:23.996548 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-target-mac
141 23:18:23.996673 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-target-storage
142 23:18:23.996803 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-test-case
143 23:18:23.996928 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-test-event
144 23:18:23.997051 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-test-feedback
145 23:18:23.997177 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-test-raise
146 23:18:23.997306 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-test-reference
147 23:18:23.997431 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-test-runner
148 23:18:23.997555 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-test-set
149 23:18:23.997682 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-test-shell
150 23:18:23.997812 Updating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-install-packages (oe)
151 23:18:23.997966 Updating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/bin/lava-installed-packages (oe)
152 23:18:23.998091 Creating /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/environment
153 23:18:23.998189 LAVA metadata
154 23:18:23.998264 - LAVA_JOB_ID=13248414
155 23:18:23.998328 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:18:23.998435 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:48) [common]
157 23:18:23.998500 skipped lava-vland-overlay
158 23:18:23.998573 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:18:23.998650 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
160 23:18:23.998712 skipped lava-multinode-overlay
161 23:18:23.998786 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:18:23.998877 start: 1.5.2.3 test-definition (timeout 00:09:48) [common]
163 23:18:23.998951 Loading test definitions
164 23:18:23.999040 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:48) [common]
165 23:18:23.999111 Using /lava-13248414 at stage 0
166 23:18:23.999437 uuid=13248414_1.5.2.3.1 testdef=None
167 23:18:23.999526 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:18:23.999609 start: 1.5.2.3.2 test-overlay (timeout 00:09:48) [common]
169 23:18:24.000169 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:18:24.000391 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:48) [common]
172 23:18:24.001006 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:18:24.001232 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
175 23:18:24.001825 runner path: /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/0/tests/0_cros-ec test_uuid 13248414_1.5.2.3.1
176 23:18:24.001983 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:18:24.002186 Creating lava-test-runner.conf files
179 23:18:24.002249 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13248414/lava-overlay-elv8j5a7/lava-13248414/0 for stage 0
180 23:18:24.002338 - 0_cros-ec
181 23:18:24.002435 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:18:24.002518 start: 1.5.2.4 compress-overlay (timeout 00:09:48) [common]
183 23:18:24.009742 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:18:24.009852 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:48) [common]
185 23:18:24.009940 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:18:24.010024 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:18:24.010111 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:48) [common]
188 23:18:25.268948 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 23:18:25.269334 start: 1.5.4 extract-modules (timeout 00:09:47) [common]
190 23:18:25.269451 extracting modules file /var/lib/lava/dispatcher/tmp/13248414/tftp-deploy-dekbzbsg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13248414/extract-overlay-ramdisk-c2udg_tv/ramdisk
191 23:18:25.511101 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:18:25.511277 start: 1.5.5 apply-overlay-tftp (timeout 00:09:47) [common]
193 23:18:25.511371 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248414/compress-overlay-xwaiu_br/overlay-1.5.2.4.tar.gz to ramdisk
194 23:18:25.511444 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13248414/compress-overlay-xwaiu_br/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13248414/extract-overlay-ramdisk-c2udg_tv/ramdisk
195 23:18:25.518203 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:18:25.518315 start: 1.5.6 configure-preseed-file (timeout 00:09:47) [common]
197 23:18:25.518405 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:18:25.518496 start: 1.5.7 compress-ramdisk (timeout 00:09:47) [common]
199 23:18:25.518568 Building ramdisk /var/lib/lava/dispatcher/tmp/13248414/extract-overlay-ramdisk-c2udg_tv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13248414/extract-overlay-ramdisk-c2udg_tv/ramdisk
200 23:18:26.405924 >> 336129 blocks
201 23:18:31.646727 rename /var/lib/lava/dispatcher/tmp/13248414/extract-overlay-ramdisk-c2udg_tv/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13248414/tftp-deploy-dekbzbsg/ramdisk/ramdisk.cpio.gz
202 23:18:31.647279 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 23:18:31.647447 start: 1.5.8 prepare-kernel (timeout 00:09:41) [common]
204 23:18:31.647593 start: 1.5.8.1 prepare-fit (timeout 00:09:41) [common]
205 23:18:31.647749 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13248414/tftp-deploy-dekbzbsg/kernel/Image'
206 23:18:44.543453 Returned 0 in 12 seconds
207 23:18:44.644276 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13248414/tftp-deploy-dekbzbsg/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13248414/tftp-deploy-dekbzbsg/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13248414/tftp-deploy-dekbzbsg/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13248414/tftp-deploy-dekbzbsg/kernel/image.itb
208 23:18:45.472589 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:18:45.473079 output: Created: Thu Apr 4 00:18:45 2024
210 23:18:45.473193 output: Image 0 (kernel-1)
211 23:18:45.473292 output: Description:
212 23:18:45.473388 output: Created: Thu Apr 4 00:18:45 2024
213 23:18:45.473482 output: Type: Kernel Image
214 23:18:45.473576 output: Compression: lzma compressed
215 23:18:45.473667 output: Data Size: 12907270 Bytes = 12604.76 KiB = 12.31 MiB
216 23:18:45.473758 output: Architecture: AArch64
217 23:18:45.473848 output: OS: Linux
218 23:18:45.473936 output: Load Address: 0x00000000
219 23:18:45.474028 output: Entry Point: 0x00000000
220 23:18:45.474122 output: Hash algo: crc32
221 23:18:45.474217 output: Hash value: d7c9dcc1
222 23:18:45.474311 output: Image 1 (fdt-1)
223 23:18:45.474406 output: Description: mt8192-asurada-spherion-r0
224 23:18:45.474496 output: Created: Thu Apr 4 00:18:45 2024
225 23:18:45.474584 output: Type: Flat Device Tree
226 23:18:45.474671 output: Compression: uncompressed
227 23:18:45.474759 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
228 23:18:45.474847 output: Architecture: AArch64
229 23:18:45.474934 output: Hash algo: crc32
230 23:18:45.475021 output: Hash value: 4bf0d1ac
231 23:18:45.475109 output: Image 2 (ramdisk-1)
232 23:18:45.475197 output: Description: unavailable
233 23:18:45.475285 output: Created: Thu Apr 4 00:18:45 2024
234 23:18:45.475373 output: Type: RAMDisk Image
235 23:18:45.475461 output: Compression: Unknown Compression
236 23:18:45.475549 output: Data Size: 52177970 Bytes = 50955.05 KiB = 49.76 MiB
237 23:18:45.475637 output: Architecture: AArch64
238 23:18:45.475769 output: OS: Linux
239 23:18:45.475859 output: Load Address: unavailable
240 23:18:45.475947 output: Entry Point: unavailable
241 23:18:45.476034 output: Hash algo: crc32
242 23:18:45.476120 output: Hash value: ee8c8d0c
243 23:18:45.476208 output: Default Configuration: 'conf-1'
244 23:18:45.476296 output: Configuration 0 (conf-1)
245 23:18:45.476382 output: Description: mt8192-asurada-spherion-r0
246 23:18:45.476470 output: Kernel: kernel-1
247 23:18:45.476557 output: Init Ramdisk: ramdisk-1
248 23:18:45.476643 output: FDT: fdt-1
249 23:18:45.476729 output: Loadables: kernel-1
250 23:18:45.476816 output:
251 23:18:45.477090 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 23:18:45.477236 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 23:18:45.477390 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 23:18:45.477530 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:27) [common]
255 23:18:45.477652 No LXC device requested
256 23:18:45.477775 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:18:45.477902 start: 1.7 deploy-device-env (timeout 00:09:27) [common]
258 23:18:45.478018 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:18:45.478122 Checking files for TFTP limit of 4294967296 bytes.
260 23:18:45.478816 end: 1 tftp-deploy (duration 00:00:33) [common]
261 23:18:45.478957 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:18:45.479086 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:18:45.479265 substitutions:
264 23:18:45.479367 - {DTB}: 13248414/tftp-deploy-dekbzbsg/dtb/mt8192-asurada-spherion-r0.dtb
265 23:18:45.479465 - {INITRD}: 13248414/tftp-deploy-dekbzbsg/ramdisk/ramdisk.cpio.gz
266 23:18:45.479555 - {KERNEL}: 13248414/tftp-deploy-dekbzbsg/kernel/Image
267 23:18:45.479646 - {LAVA_MAC}: None
268 23:18:45.479742 - {PRESEED_CONFIG}: None
269 23:18:45.479833 - {PRESEED_LOCAL}: None
270 23:18:45.479923 - {RAMDISK}: 13248414/tftp-deploy-dekbzbsg/ramdisk/ramdisk.cpio.gz
271 23:18:45.480012 - {ROOT_PART}: None
272 23:18:45.480101 - {ROOT}: None
273 23:18:45.480190 - {SERVER_IP}: 192.168.201.1
274 23:18:45.480278 - {TEE}: None
275 23:18:45.480367 Parsed boot commands:
276 23:18:45.480455 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:18:45.480701 Parsed boot commands: tftpboot 192.168.201.1 13248414/tftp-deploy-dekbzbsg/kernel/image.itb 13248414/tftp-deploy-dekbzbsg/kernel/cmdline
278 23:18:45.480833 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:18:45.480959 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:18:45.481096 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:18:45.481224 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:18:45.481333 Not connected, no need to disconnect.
283 23:18:45.481444 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:18:45.481564 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:18:45.481665 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 23:18:45.486492 Setting prompt string to ['lava-test: # ']
287 23:18:45.486980 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:18:45.487137 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:18:45.487278 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:18:45.487411 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:18:45.487721 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 23:18:50.626452 >> Command sent successfully.
293 23:18:50.629009 Returned 0 in 5 seconds
294 23:18:50.729431 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:18:50.729823 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:18:50.729942 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:18:50.730049 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:18:50.730127 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:18:50.730216 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:18:50.730604 [Enter `^Ec?' for help]
302 23:18:50.904735
303 23:18:50.904901
304 23:18:50.905006 F0: 102B 0000
305 23:18:50.905096
306 23:18:50.909175 F3: 1001 0000 [0200]
307 23:18:50.909268
308 23:18:50.909357 F3: 1001 0000
309 23:18:50.909441
310 23:18:50.909522 F7: 102D 0000
311 23:18:50.909602
312 23:18:50.912516 F1: 0000 0000
313 23:18:50.912603
314 23:18:50.912691 V0: 0000 0000 [0001]
315 23:18:50.912778
316 23:18:50.912859 00: 0007 8000
317 23:18:50.912943
318 23:18:50.916507 01: 0000 0000
319 23:18:50.916616
320 23:18:50.916701 BP: 0C00 0209 [0000]
321 23:18:50.916782
322 23:18:50.919613 G0: 1182 0000
323 23:18:50.919764
324 23:18:50.919853 EC: 0000 0021 [4000]
325 23:18:50.919935
326 23:18:50.923535 S7: 0000 0000 [0000]
327 23:18:50.923623
328 23:18:50.923761 CC: 0000 0000 [0001]
329 23:18:50.923863
330 23:18:50.926702 T0: 0000 0040 [010F]
331 23:18:50.926805
332 23:18:50.926906 Jump to BL
333 23:18:50.927006
334 23:18:50.952622
335 23:18:50.952774
336 23:18:50.952870
337 23:18:50.960340 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 23:18:50.962185 ARM64: Exception handlers installed.
339 23:18:50.966207 ARM64: Testing exception
340 23:18:50.969494 ARM64: Done test exception
341 23:18:50.977599 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 23:18:50.987438 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 23:18:50.994342 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 23:18:51.003936 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 23:18:51.010561 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 23:18:51.017222 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 23:18:51.028814 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 23:18:51.035148 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 23:18:51.054423 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 23:18:51.058143 WDT: Last reset was cold boot
351 23:18:51.061482 SPI1(PAD0) initialized at 2873684 Hz
352 23:18:51.065099 SPI5(PAD0) initialized at 992727 Hz
353 23:18:51.068119 VBOOT: Loading verstage.
354 23:18:51.074752 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 23:18:51.078068 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 23:18:51.081574 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 23:18:51.084949 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 23:18:51.092976 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 23:18:51.098703 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 23:18:51.110043 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 23:18:51.110150
362 23:18:51.110218
363 23:18:51.119878 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 23:18:51.123253 ARM64: Exception handlers installed.
365 23:18:51.126511 ARM64: Testing exception
366 23:18:51.126597 ARM64: Done test exception
367 23:18:51.133595 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 23:18:51.137464 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 23:18:51.150765 Probing TPM: . done!
370 23:18:51.150880 TPM ready after 0 ms
371 23:18:51.155849 Connected to device vid:did:rid of 1ae0:0028:00
372 23:18:51.167061 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 23:18:51.220937 Initialized TPM device CR50 revision 0
374 23:18:51.232731 tlcl_send_startup: Startup return code is 0
375 23:18:51.232870 TPM: setup succeeded
376 23:18:51.244617 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 23:18:51.252998 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 23:18:51.260785 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 23:18:51.275411 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 23:18:51.278439 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 23:18:51.285630 in-header: 03 07 00 00 08 00 00 00
382 23:18:51.289179 in-data: aa e4 47 04 13 02 00 00
383 23:18:51.293253 Chrome EC: UHEPI supported
384 23:18:51.299683 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 23:18:51.305146 in-header: 03 ad 00 00 08 00 00 00
386 23:18:51.307080 in-data: 00 20 20 08 00 00 00 00
387 23:18:51.307186 Phase 1
388 23:18:51.310957 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 23:18:51.318233 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 23:18:51.321902 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 23:18:51.325178 Recovery requested (1009000e)
392 23:18:51.334802 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 23:18:51.340775 tlcl_extend: response is 0
394 23:18:51.350672 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 23:18:51.356463 tlcl_extend: response is 0
396 23:18:51.362969 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 23:18:51.383989 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 23:18:51.391095 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 23:18:51.391199
400 23:18:51.391267
401 23:18:51.401322 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 23:18:51.404884 ARM64: Exception handlers installed.
403 23:18:51.404974 ARM64: Testing exception
404 23:18:51.408453 ARM64: Done test exception
405 23:18:51.429846 pmic_efuse_setting: Set efuses in 11 msecs
406 23:18:51.432564 pmwrap_interface_init: Select PMIF_VLD_RDY
407 23:18:51.438927 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 23:18:51.443031 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 23:18:51.449591 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 23:18:51.453516 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 23:18:51.456757 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 23:18:51.464286 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 23:18:51.468117 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 23:18:51.471599 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 23:18:51.475406 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 23:18:51.483073 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 23:18:51.486032 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 23:18:51.489843 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 23:18:51.493091 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 23:18:51.501816 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 23:18:51.508751 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 23:18:51.512372 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 23:18:51.519023 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 23:18:51.522704 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 23:18:51.530586 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 23:18:51.534027 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 23:18:51.541494 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 23:18:51.544971 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 23:18:51.552626 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 23:18:51.556890 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 23:18:51.563572 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 23:18:51.567113 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 23:18:51.574069 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 23:18:51.578023 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 23:18:51.581757 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 23:18:51.588531 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 23:18:51.592284 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 23:18:51.599460 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 23:18:51.603084 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 23:18:51.606457 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 23:18:51.613902 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 23:18:51.617896 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 23:18:51.624445 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 23:18:51.628410 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 23:18:51.632345 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 23:18:51.635378 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 23:18:51.642894 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 23:18:51.646187 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 23:18:51.650053 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 23:18:51.653918 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 23:18:51.657734 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 23:18:51.664706 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 23:18:51.668673 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 23:18:51.672000 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 23:18:51.675879 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 23:18:51.679382 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 23:18:51.683240 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 23:18:51.690540 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 23:18:51.702020 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 23:18:51.705025 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 23:18:51.713157 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 23:18:51.723642 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 23:18:51.726911 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 23:18:51.730783 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:18:51.733889 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 23:18:51.743047 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x0
467 23:18:51.749777 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 23:18:51.752245 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 23:18:51.755698 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 23:18:51.766683 [RTC]rtc_get_frequency_meter,154: input=15, output=835
471 23:18:51.775967 [RTC]rtc_get_frequency_meter,154: input=7, output=708
472 23:18:51.785293 [RTC]rtc_get_frequency_meter,154: input=11, output=771
473 23:18:51.795036 [RTC]rtc_get_frequency_meter,154: input=13, output=803
474 23:18:51.804865 [RTC]rtc_get_frequency_meter,154: input=12, output=787
475 23:18:51.813925 [RTC]rtc_get_frequency_meter,154: input=12, output=787
476 23:18:51.823294 [RTC]rtc_get_frequency_meter,154: input=13, output=803
477 23:18:51.826625 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 23:18:51.834359 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 23:18:51.838338 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 23:18:51.842656 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 23:18:51.844998 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 23:18:51.848705 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 23:18:51.851975 ADC[4]: Raw value=905618 ID=7
484 23:18:51.856107 ADC[3]: Raw value=212912 ID=1
485 23:18:51.856204 RAM Code: 0x71
486 23:18:51.859823 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 23:18:51.866475 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 23:18:51.874010 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 23:18:51.881430 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 23:18:51.884918 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 23:18:51.888143 in-header: 03 07 00 00 08 00 00 00
492 23:18:51.892228 in-data: aa e4 47 04 13 02 00 00
493 23:18:51.892323 Chrome EC: UHEPI supported
494 23:18:51.899445 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 23:18:51.904011 in-header: 03 ed 00 00 08 00 00 00
496 23:18:51.906792 in-data: 80 20 60 08 00 00 00 00
497 23:18:51.910751 MRC: failed to locate region type 0.
498 23:18:51.917726 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 23:18:51.921794 DRAM-K: Running full calibration
500 23:18:51.925724 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 23:18:51.928915 header.status = 0x0
502 23:18:51.932750 header.version = 0x6 (expected: 0x6)
503 23:18:51.936445 header.size = 0xd00 (expected: 0xd00)
504 23:18:51.936533 header.flags = 0x0
505 23:18:51.943542 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 23:18:51.961859 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 23:18:51.967883 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 23:18:51.971985 dram_init: ddr_geometry: 2
509 23:18:51.972080 [EMI] MDL number = 2
510 23:18:51.975245 [EMI] Get MDL freq = 0
511 23:18:51.975332 dram_init: ddr_type: 0
512 23:18:51.979293 is_discrete_lpddr4: 1
513 23:18:51.982771 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 23:18:51.982860
515 23:18:51.982926
516 23:18:51.986523 [Bian_co] ETT version 0.0.0.1
517 23:18:51.990632 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 23:18:51.990723
519 23:18:51.994818 dramc_set_vcore_voltage set vcore to 650000
520 23:18:51.994904 Read voltage for 800, 4
521 23:18:51.997658 Vio18 = 0
522 23:18:51.997742 Vcore = 650000
523 23:18:51.997809 Vdram = 0
524 23:18:52.001824 Vddq = 0
525 23:18:52.001912 Vmddr = 0
526 23:18:52.005065 dram_init: config_dvfs: 1
527 23:18:52.009204 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 23:18:52.012796 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 23:18:52.016663 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
530 23:18:52.020579 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
531 23:18:52.024102 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 23:18:52.027520 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 23:18:52.031542 MEM_TYPE=3, freq_sel=18
534 23:18:52.035128 sv_algorithm_assistance_LP4_1600
535 23:18:52.039037 ============ PULL DRAM RESETB DOWN ============
536 23:18:52.042365 ========== PULL DRAM RESETB DOWN end =========
537 23:18:52.045466 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 23:18:52.049159 ===================================
539 23:18:52.051975 LPDDR4 DRAM CONFIGURATION
540 23:18:52.055884 ===================================
541 23:18:52.058617 EX_ROW_EN[0] = 0x0
542 23:18:52.058704 EX_ROW_EN[1] = 0x0
543 23:18:52.062190 LP4Y_EN = 0x0
544 23:18:52.062274 WORK_FSP = 0x0
545 23:18:52.065567 WL = 0x2
546 23:18:52.065652 RL = 0x2
547 23:18:52.068610 BL = 0x2
548 23:18:52.068695 RPST = 0x0
549 23:18:52.072562 RD_PRE = 0x0
550 23:18:52.072647 WR_PRE = 0x1
551 23:18:52.075293 WR_PST = 0x0
552 23:18:52.075377 DBI_WR = 0x0
553 23:18:52.078526 DBI_RD = 0x0
554 23:18:52.082166 OTF = 0x1
555 23:18:52.085990 ===================================
556 23:18:52.089237 ===================================
557 23:18:52.089322 ANA top config
558 23:18:52.092124 ===================================
559 23:18:52.095387 DLL_ASYNC_EN = 0
560 23:18:52.095472 ALL_SLAVE_EN = 1
561 23:18:52.098599 NEW_RANK_MODE = 1
562 23:18:52.102306 DLL_IDLE_MODE = 1
563 23:18:52.105270 LP45_APHY_COMB_EN = 1
564 23:18:52.109272 TX_ODT_DIS = 1
565 23:18:52.109358 NEW_8X_MODE = 1
566 23:18:52.111766 ===================================
567 23:18:52.115426 ===================================
568 23:18:52.118483 data_rate = 1600
569 23:18:52.121814 CKR = 1
570 23:18:52.125008 DQ_P2S_RATIO = 8
571 23:18:52.128273 ===================================
572 23:18:52.131459 CA_P2S_RATIO = 8
573 23:18:52.135351 DQ_CA_OPEN = 0
574 23:18:52.135436 DQ_SEMI_OPEN = 0
575 23:18:52.138499 CA_SEMI_OPEN = 0
576 23:18:52.141372 CA_FULL_RATE = 0
577 23:18:52.145585 DQ_CKDIV4_EN = 1
578 23:18:52.148237 CA_CKDIV4_EN = 1
579 23:18:52.151470 CA_PREDIV_EN = 0
580 23:18:52.151555 PH8_DLY = 0
581 23:18:52.155217 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 23:18:52.158323 DQ_AAMCK_DIV = 4
583 23:18:52.161251 CA_AAMCK_DIV = 4
584 23:18:52.164866 CA_ADMCK_DIV = 4
585 23:18:52.167957 DQ_TRACK_CA_EN = 0
586 23:18:52.168042 CA_PICK = 800
587 23:18:52.171426 CA_MCKIO = 800
588 23:18:52.175162 MCKIO_SEMI = 0
589 23:18:52.178424 PLL_FREQ = 3068
590 23:18:52.182105 DQ_UI_PI_RATIO = 32
591 23:18:52.185596 CA_UI_PI_RATIO = 0
592 23:18:52.185681 ===================================
593 23:18:52.189282 ===================================
594 23:18:52.193187 memory_type:LPDDR4
595 23:18:52.197222 GP_NUM : 10
596 23:18:52.197308 SRAM_EN : 1
597 23:18:52.200644 MD32_EN : 0
598 23:18:52.204496 ===================================
599 23:18:52.204580 [ANA_INIT] >>>>>>>>>>>>>>
600 23:18:52.207970 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 23:18:52.212182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 23:18:52.215287 ===================================
603 23:18:52.218493 data_rate = 1600,PCW = 0X7600
604 23:18:52.221826 ===================================
605 23:18:52.225360 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 23:18:52.228870 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:18:52.235139 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 23:18:52.238389 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 23:18:52.241896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:18:52.245643 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 23:18:52.248784 [ANA_INIT] flow start
612 23:18:52.251399 [ANA_INIT] PLL >>>>>>>>
613 23:18:52.251484 [ANA_INIT] PLL <<<<<<<<
614 23:18:52.255359 [ANA_INIT] MIDPI >>>>>>>>
615 23:18:52.258186 [ANA_INIT] MIDPI <<<<<<<<
616 23:18:52.258271 [ANA_INIT] DLL >>>>>>>>
617 23:18:52.261477 [ANA_INIT] flow end
618 23:18:52.264574 ============ LP4 DIFF to SE enter ============
619 23:18:52.271216 ============ LP4 DIFF to SE exit ============
620 23:18:52.271300 [ANA_INIT] <<<<<<<<<<<<<
621 23:18:52.274940 [Flow] Enable top DCM control >>>>>
622 23:18:52.278607 [Flow] Enable top DCM control <<<<<
623 23:18:52.281993 Enable DLL master slave shuffle
624 23:18:52.287932 ==============================================================
625 23:18:52.288020 Gating Mode config
626 23:18:52.294669 ==============================================================
627 23:18:52.298086 Config description:
628 23:18:52.305190 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 23:18:52.314326 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 23:18:52.317704 SELPH_MODE 0: By rank 1: By Phase
631 23:18:52.324394 ==============================================================
632 23:18:52.327399 GAT_TRACK_EN = 1
633 23:18:52.327483 RX_GATING_MODE = 2
634 23:18:52.330813 RX_GATING_TRACK_MODE = 2
635 23:18:52.333996 SELPH_MODE = 1
636 23:18:52.337560 PICG_EARLY_EN = 1
637 23:18:52.341141 VALID_LAT_VALUE = 1
638 23:18:52.347668 ==============================================================
639 23:18:52.350854 Enter into Gating configuration >>>>
640 23:18:52.354682 Exit from Gating configuration <<<<
641 23:18:52.357301 Enter into DVFS_PRE_config >>>>>
642 23:18:52.366985 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 23:18:52.370391 Exit from DVFS_PRE_config <<<<<
644 23:18:52.374244 Enter into PICG configuration >>>>
645 23:18:52.377144 Exit from PICG configuration <<<<
646 23:18:52.380307 [RX_INPUT] configuration >>>>>
647 23:18:52.384330 [RX_INPUT] configuration <<<<<
648 23:18:52.386772 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 23:18:52.394163 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 23:18:52.401360 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 23:18:52.404548 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 23:18:52.411057 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 23:18:52.417174 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 23:18:52.420684 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 23:18:52.424104 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 23:18:52.430647 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 23:18:52.434757 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 23:18:52.437884 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 23:18:52.444144 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 23:18:52.447093 ===================================
661 23:18:52.447178 LPDDR4 DRAM CONFIGURATION
662 23:18:52.450515 ===================================
663 23:18:52.453955 EX_ROW_EN[0] = 0x0
664 23:18:52.457004 EX_ROW_EN[1] = 0x0
665 23:18:52.457088 LP4Y_EN = 0x0
666 23:18:52.460539 WORK_FSP = 0x0
667 23:18:52.460623 WL = 0x2
668 23:18:52.464224 RL = 0x2
669 23:18:52.464308 BL = 0x2
670 23:18:52.466899 RPST = 0x0
671 23:18:52.466982 RD_PRE = 0x0
672 23:18:52.470843 WR_PRE = 0x1
673 23:18:52.470927 WR_PST = 0x0
674 23:18:52.473630 DBI_WR = 0x0
675 23:18:52.473713 DBI_RD = 0x0
676 23:18:52.477382 OTF = 0x1
677 23:18:52.480835 ===================================
678 23:18:52.484096 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 23:18:52.487099 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 23:18:52.493898 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 23:18:52.496906 ===================================
682 23:18:52.496991 LPDDR4 DRAM CONFIGURATION
683 23:18:52.500286 ===================================
684 23:18:52.504096 EX_ROW_EN[0] = 0x10
685 23:18:52.504180 EX_ROW_EN[1] = 0x0
686 23:18:52.506686 LP4Y_EN = 0x0
687 23:18:52.509987 WORK_FSP = 0x0
688 23:18:52.510070 WL = 0x2
689 23:18:52.513415 RL = 0x2
690 23:18:52.513500 BL = 0x2
691 23:18:52.517162 RPST = 0x0
692 23:18:52.517274 RD_PRE = 0x0
693 23:18:52.520143 WR_PRE = 0x1
694 23:18:52.520227 WR_PST = 0x0
695 23:18:52.524316 DBI_WR = 0x0
696 23:18:52.524401 DBI_RD = 0x0
697 23:18:52.526800 OTF = 0x1
698 23:18:52.529654 ===================================
699 23:18:52.536468 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 23:18:52.539795 nWR fixed to 40
701 23:18:52.539880 [ModeRegInit_LP4] CH0 RK0
702 23:18:52.542899 [ModeRegInit_LP4] CH0 RK1
703 23:18:52.547387 [ModeRegInit_LP4] CH1 RK0
704 23:18:52.547470 [ModeRegInit_LP4] CH1 RK1
705 23:18:52.549757 match AC timing 13
706 23:18:52.553092 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 23:18:52.556604 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 23:18:52.562883 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 23:18:52.566438 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 23:18:52.573065 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 23:18:52.573150 [EMI DOE] emi_dcm 0
712 23:18:52.579438 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 23:18:52.579526 ==
714 23:18:52.583282 Dram Type= 6, Freq= 0, CH_0, rank 0
715 23:18:52.586983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 23:18:52.587067 ==
717 23:18:52.592626 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 23:18:52.596110 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 23:18:52.606566 [CA 0] Center 37 (7~68) winsize 62
720 23:18:52.609747 [CA 1] Center 37 (6~68) winsize 63
721 23:18:52.613552 [CA 2] Center 34 (4~65) winsize 62
722 23:18:52.616883 [CA 3] Center 34 (4~65) winsize 62
723 23:18:52.619720 [CA 4] Center 33 (3~64) winsize 62
724 23:18:52.623618 [CA 5] Center 33 (3~64) winsize 62
725 23:18:52.623771
726 23:18:52.626741 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 23:18:52.626824
728 23:18:52.630212 [CATrainingPosCal] consider 1 rank data
729 23:18:52.632799 u2DelayCellTimex100 = 270/100 ps
730 23:18:52.636198 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 23:18:52.643338 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 23:18:52.646510 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 23:18:52.650516 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 23:18:52.653060 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 23:18:52.656053 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 23:18:52.656135
737 23:18:52.660013 CA PerBit enable=1, Macro0, CA PI delay=33
738 23:18:52.660095
739 23:18:52.663362 [CBTSetCACLKResult] CA Dly = 33
740 23:18:52.663443 CS Dly: 7 (0~38)
741 23:18:52.666423 ==
742 23:18:52.669935 Dram Type= 6, Freq= 0, CH_0, rank 1
743 23:18:52.673424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 23:18:52.673507 ==
745 23:18:52.676080 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 23:18:52.682742 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 23:18:52.692881 [CA 0] Center 37 (6~68) winsize 63
748 23:18:52.696114 [CA 1] Center 37 (7~68) winsize 62
749 23:18:52.699470 [CA 2] Center 34 (4~65) winsize 62
750 23:18:52.702869 [CA 3] Center 34 (4~65) winsize 62
751 23:18:52.706141 [CA 4] Center 33 (3~64) winsize 62
752 23:18:52.709448 [CA 5] Center 33 (3~64) winsize 62
753 23:18:52.709532
754 23:18:52.712888 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 23:18:52.712972
756 23:18:52.715866 [CATrainingPosCal] consider 2 rank data
757 23:18:52.719149 u2DelayCellTimex100 = 270/100 ps
758 23:18:52.722676 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 23:18:52.729850 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 23:18:52.732572 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 23:18:52.735588 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 23:18:52.739259 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 23:18:52.742872 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 23:18:52.742957
765 23:18:52.745343 CA PerBit enable=1, Macro0, CA PI delay=33
766 23:18:52.745427
767 23:18:52.748843 [CBTSetCACLKResult] CA Dly = 33
768 23:18:52.748927 CS Dly: 7 (0~38)
769 23:18:52.752268
770 23:18:52.757075 ----->DramcWriteLeveling(PI) begin...
771 23:18:52.757163 ==
772 23:18:52.760276 Dram Type= 6, Freq= 0, CH_0, rank 0
773 23:18:52.762960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 23:18:52.763044 ==
775 23:18:52.766871 Write leveling (Byte 0): 33 => 33
776 23:18:52.769313 Write leveling (Byte 1): 29 => 29
777 23:18:52.769399 DramcWriteLeveling(PI) end<-----
778 23:18:52.772872
779 23:18:52.772955 ==
780 23:18:52.777609 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:18:52.780196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 23:18:52.780281 ==
783 23:18:52.783353 [Gating] SW mode calibration
784 23:18:52.791379 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 23:18:52.794508 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 23:18:52.797936 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 23:18:52.804354 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 23:18:52.807640 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 23:18:52.811211 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 23:18:52.817150 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:18:52.820752 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:18:52.823715 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:18:52.830959 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:18:52.833741 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:18:52.837865 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:18:52.843903 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:18:52.847423 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:18:52.850445 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:18:52.857934 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:18:52.860490 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:18:52.864011 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:18:52.870392 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:18:52.873688 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 23:18:52.876897 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 23:18:52.883854 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
806 23:18:52.887178 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:18:52.890286 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:18:52.897296 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:18:52.900735 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:18:52.903457 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:18:52.906446 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 23:18:52.913044 0 9 8 | B1->B0 | 2322 2e2e | 1 1 | (0 0) (1 1)
813 23:18:52.916917 0 9 12 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
814 23:18:52.920322 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 23:18:52.926903 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 23:18:52.929553 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 23:18:52.933083 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 23:18:52.939556 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 23:18:52.942846 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 23:18:52.945956 0 10 8 | B1->B0 | 3232 2626 | 1 0 | (1 0) (1 0)
821 23:18:52.952872 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
822 23:18:52.956192 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:18:52.959443 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:18:52.967286 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:18:52.969313 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:18:52.973100 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:18:52.979926 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 23:18:52.982529 0 11 8 | B1->B0 | 2525 3939 | 0 0 | (0 0) (1 1)
829 23:18:52.986292 0 11 12 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
830 23:18:52.992723 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 23:18:52.996044 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:18:52.999091 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 23:18:53.005807 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 23:18:53.009020 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 23:18:53.012166 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 23:18:53.018871 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 23:18:53.022481 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 23:18:53.026365 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:18:53.032376 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:18:53.035550 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:18:53.039055 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:18:53.045631 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:18:53.048983 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:18:53.052181 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:18:53.059274 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:18:53.062537 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:18:53.065793 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:18:53.072501 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:18:53.075799 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:18:53.078930 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:18:53.085500 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 23:18:53.088609 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 23:18:53.092408 Total UI for P1: 0, mck2ui 16
854 23:18:53.095056 best dqsien dly found for B0: ( 0, 14, 6)
855 23:18:53.098802 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
856 23:18:53.105154 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 23:18:53.105238 Total UI for P1: 0, mck2ui 16
858 23:18:53.108650 best dqsien dly found for B1: ( 0, 14, 10)
859 23:18:53.115371 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
860 23:18:53.118481 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 23:18:53.118566
862 23:18:53.123094 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
863 23:18:53.125846 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 23:18:53.128860 [Gating] SW calibration Done
865 23:18:53.128944 ==
866 23:18:53.131642 Dram Type= 6, Freq= 0, CH_0, rank 0
867 23:18:53.135441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 23:18:53.135526 ==
869 23:18:53.138339 RX Vref Scan: 0
870 23:18:53.138423
871 23:18:53.138490 RX Vref 0 -> 0, step: 1
872 23:18:53.138552
873 23:18:53.141896 RX Delay -130 -> 252, step: 16
874 23:18:53.145281 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 23:18:53.151608 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 23:18:53.155003 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 23:18:53.158401 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 23:18:53.161772 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 23:18:53.165061 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
880 23:18:53.171667 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
881 23:18:53.174770 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
882 23:18:53.178649 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
883 23:18:53.182072 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
884 23:18:53.184953 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
885 23:18:53.191571 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 23:18:53.194947 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
887 23:18:53.198720 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
888 23:18:53.201707 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 23:18:53.205030 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
890 23:18:53.208012 ==
891 23:18:53.211744 Dram Type= 6, Freq= 0, CH_0, rank 0
892 23:18:53.214746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 23:18:53.214830 ==
894 23:18:53.214896 DQS Delay:
895 23:18:53.218088 DQS0 = 0, DQS1 = 0
896 23:18:53.218199 DQM Delay:
897 23:18:53.222139 DQM0 = 85, DQM1 = 74
898 23:18:53.222224 DQ Delay:
899 23:18:53.224551 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 23:18:53.228310 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
901 23:18:53.231966 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
902 23:18:53.234622 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
903 23:18:53.234706
904 23:18:53.234771
905 23:18:53.234832 ==
906 23:18:53.238411 Dram Type= 6, Freq= 0, CH_0, rank 0
907 23:18:53.241147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 23:18:53.241232 ==
909 23:18:53.241298
910 23:18:53.241359
911 23:18:53.244626 TX Vref Scan disable
912 23:18:53.247848 == TX Byte 0 ==
913 23:18:53.251596 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
914 23:18:53.254784 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
915 23:18:53.257639 == TX Byte 1 ==
916 23:18:53.261925 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
917 23:18:53.264706 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
918 23:18:53.264790 ==
919 23:18:53.268693 Dram Type= 6, Freq= 0, CH_0, rank 0
920 23:18:53.271433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 23:18:53.274591 ==
922 23:18:53.286043 TX Vref=22, minBit 5, minWin=27, winSum=442
923 23:18:53.289231 TX Vref=24, minBit 4, minWin=27, winSum=443
924 23:18:53.292911 TX Vref=26, minBit 8, minWin=27, winSum=446
925 23:18:53.296181 TX Vref=28, minBit 10, minWin=27, winSum=450
926 23:18:53.299534 TX Vref=30, minBit 8, minWin=27, winSum=445
927 23:18:53.306626 TX Vref=32, minBit 4, minWin=27, winSum=445
928 23:18:53.309523 [TxChooseVref] Worse bit 10, Min win 27, Win sum 450, Final Vref 28
929 23:18:53.309606
930 23:18:53.312610 Final TX Range 1 Vref 28
931 23:18:53.312693
932 23:18:53.312759 ==
933 23:18:53.316171 Dram Type= 6, Freq= 0, CH_0, rank 0
934 23:18:53.319180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 23:18:53.323160 ==
936 23:18:53.323303
937 23:18:53.323411
938 23:18:53.323533 TX Vref Scan disable
939 23:18:53.326594 == TX Byte 0 ==
940 23:18:53.330028 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
941 23:18:53.336715 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
942 23:18:53.336801 == TX Byte 1 ==
943 23:18:53.339497 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
944 23:18:53.346531 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
945 23:18:53.346620
946 23:18:53.346687 [DATLAT]
947 23:18:53.346747 Freq=800, CH0 RK0
948 23:18:53.346806
949 23:18:53.349878 DATLAT Default: 0xa
950 23:18:53.349960 0, 0xFFFF, sum = 0
951 23:18:53.352462 1, 0xFFFF, sum = 0
952 23:18:53.352546 2, 0xFFFF, sum = 0
953 23:18:53.355903 3, 0xFFFF, sum = 0
954 23:18:53.359481 4, 0xFFFF, sum = 0
955 23:18:53.359565 5, 0xFFFF, sum = 0
956 23:18:53.362677 6, 0xFFFF, sum = 0
957 23:18:53.362761 7, 0xFFFF, sum = 0
958 23:18:53.366005 8, 0xFFFF, sum = 0
959 23:18:53.366089 9, 0x0, sum = 1
960 23:18:53.369301 10, 0x0, sum = 2
961 23:18:53.369385 11, 0x0, sum = 3
962 23:18:53.369452 12, 0x0, sum = 4
963 23:18:53.372401 best_step = 10
964 23:18:53.372483
965 23:18:53.372548 ==
966 23:18:53.375855 Dram Type= 6, Freq= 0, CH_0, rank 0
967 23:18:53.379419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 23:18:53.379502 ==
969 23:18:53.382444 RX Vref Scan: 1
970 23:18:53.382526
971 23:18:53.385973 Set Vref Range= 32 -> 127
972 23:18:53.386057
973 23:18:53.386123 RX Vref 32 -> 127, step: 1
974 23:18:53.386184
975 23:18:53.389423 RX Delay -95 -> 252, step: 8
976 23:18:53.389511
977 23:18:53.392506 Set Vref, RX VrefLevel [Byte0]: 32
978 23:18:53.395663 [Byte1]: 32
979 23:18:53.399618
980 23:18:53.399709 Set Vref, RX VrefLevel [Byte0]: 33
981 23:18:53.402618 [Byte1]: 33
982 23:18:53.406843
983 23:18:53.406926 Set Vref, RX VrefLevel [Byte0]: 34
984 23:18:53.413473 [Byte1]: 34
985 23:18:53.413557
986 23:18:53.416275 Set Vref, RX VrefLevel [Byte0]: 35
987 23:18:53.419512 [Byte1]: 35
988 23:18:53.419596
989 23:18:53.423125 Set Vref, RX VrefLevel [Byte0]: 36
990 23:18:53.426654 [Byte1]: 36
991 23:18:53.426739
992 23:18:53.430565 Set Vref, RX VrefLevel [Byte0]: 37
993 23:18:53.433328 [Byte1]: 37
994 23:18:53.437785
995 23:18:53.437870 Set Vref, RX VrefLevel [Byte0]: 38
996 23:18:53.444021 [Byte1]: 38
997 23:18:53.444113
998 23:18:53.448142 Set Vref, RX VrefLevel [Byte0]: 39
999 23:18:53.451234 [Byte1]: 39
1000 23:18:53.451319
1001 23:18:53.455522 Set Vref, RX VrefLevel [Byte0]: 40
1002 23:18:53.458023 [Byte1]: 40
1003 23:18:53.458108
1004 23:18:53.461833 Set Vref, RX VrefLevel [Byte0]: 41
1005 23:18:53.465360 [Byte1]: 41
1006 23:18:53.465444
1007 23:18:53.468798 Set Vref, RX VrefLevel [Byte0]: 42
1008 23:18:53.471639 [Byte1]: 42
1009 23:18:53.475009
1010 23:18:53.475092 Set Vref, RX VrefLevel [Byte0]: 43
1011 23:18:53.478299 [Byte1]: 43
1012 23:18:53.482551
1013 23:18:53.482636 Set Vref, RX VrefLevel [Byte0]: 44
1014 23:18:53.485798 [Byte1]: 44
1015 23:18:53.490825
1016 23:18:53.490929 Set Vref, RX VrefLevel [Byte0]: 45
1017 23:18:53.493230 [Byte1]: 45
1018 23:18:53.497754
1019 23:18:53.497841 Set Vref, RX VrefLevel [Byte0]: 46
1020 23:18:53.502058 [Byte1]: 46
1021 23:18:53.505706
1022 23:18:53.505790 Set Vref, RX VrefLevel [Byte0]: 47
1023 23:18:53.508810 [Byte1]: 47
1024 23:18:53.512662
1025 23:18:53.512753 Set Vref, RX VrefLevel [Byte0]: 48
1026 23:18:53.516250 [Byte1]: 48
1027 23:18:53.520248
1028 23:18:53.520331 Set Vref, RX VrefLevel [Byte0]: 49
1029 23:18:53.524112 [Byte1]: 49
1030 23:18:53.528246
1031 23:18:53.528331 Set Vref, RX VrefLevel [Byte0]: 50
1032 23:18:53.531386 [Byte1]: 50
1033 23:18:53.535572
1034 23:18:53.535705 Set Vref, RX VrefLevel [Byte0]: 51
1035 23:18:53.539635 [Byte1]: 51
1036 23:18:53.543357
1037 23:18:53.543439 Set Vref, RX VrefLevel [Byte0]: 52
1038 23:18:53.546348 [Byte1]: 52
1039 23:18:53.550966
1040 23:18:53.551049 Set Vref, RX VrefLevel [Byte0]: 53
1041 23:18:53.554247 [Byte1]: 53
1042 23:18:53.558495
1043 23:18:53.558579 Set Vref, RX VrefLevel [Byte0]: 54
1044 23:18:53.561992 [Byte1]: 54
1045 23:18:53.566471
1046 23:18:53.566580 Set Vref, RX VrefLevel [Byte0]: 55
1047 23:18:53.569326 [Byte1]: 55
1048 23:18:53.574043
1049 23:18:53.574125 Set Vref, RX VrefLevel [Byte0]: 56
1050 23:18:53.577282 [Byte1]: 56
1051 23:18:53.582191
1052 23:18:53.582274 Set Vref, RX VrefLevel [Byte0]: 57
1053 23:18:53.584323 [Byte1]: 57
1054 23:18:53.589161
1055 23:18:53.589243 Set Vref, RX VrefLevel [Byte0]: 58
1056 23:18:53.591952 [Byte1]: 58
1057 23:18:53.596658
1058 23:18:53.596741 Set Vref, RX VrefLevel [Byte0]: 59
1059 23:18:53.599702 [Byte1]: 59
1060 23:18:53.603701
1061 23:18:53.603784 Set Vref, RX VrefLevel [Byte0]: 60
1062 23:18:53.607289 [Byte1]: 60
1063 23:18:53.612055
1064 23:18:53.612138 Set Vref, RX VrefLevel [Byte0]: 61
1065 23:18:53.614948 [Byte1]: 61
1066 23:18:53.619860
1067 23:18:53.619944 Set Vref, RX VrefLevel [Byte0]: 62
1068 23:18:53.622365 [Byte1]: 62
1069 23:18:53.627423
1070 23:18:53.627509 Set Vref, RX VrefLevel [Byte0]: 63
1071 23:18:53.630218 [Byte1]: 63
1072 23:18:53.634600
1073 23:18:53.634683 Set Vref, RX VrefLevel [Byte0]: 64
1074 23:18:53.637932 [Byte1]: 64
1075 23:18:53.641668
1076 23:18:53.644857 Set Vref, RX VrefLevel [Byte0]: 65
1077 23:18:53.648329 [Byte1]: 65
1078 23:18:53.648412
1079 23:18:53.651780 Set Vref, RX VrefLevel [Byte0]: 66
1080 23:18:53.654959 [Byte1]: 66
1081 23:18:53.655041
1082 23:18:53.659182 Set Vref, RX VrefLevel [Byte0]: 67
1083 23:18:53.662272 [Byte1]: 67
1084 23:18:53.662355
1085 23:18:53.665059 Set Vref, RX VrefLevel [Byte0]: 68
1086 23:18:53.668227 [Byte1]: 68
1087 23:18:53.673698
1088 23:18:53.673782 Set Vref, RX VrefLevel [Byte0]: 69
1089 23:18:53.675790 [Byte1]: 69
1090 23:18:53.680408
1091 23:18:53.680495 Set Vref, RX VrefLevel [Byte0]: 70
1092 23:18:53.683151 [Byte1]: 70
1093 23:18:53.687718
1094 23:18:53.687802 Set Vref, RX VrefLevel [Byte0]: 71
1095 23:18:53.690857 [Byte1]: 71
1096 23:18:53.695554
1097 23:18:53.695636 Set Vref, RX VrefLevel [Byte0]: 72
1098 23:18:53.698775 [Byte1]: 72
1099 23:18:53.702869
1100 23:18:53.702952 Set Vref, RX VrefLevel [Byte0]: 73
1101 23:18:53.706708 [Byte1]: 73
1102 23:18:53.710625
1103 23:18:53.710707 Set Vref, RX VrefLevel [Byte0]: 74
1104 23:18:53.713582 [Byte1]: 74
1105 23:18:53.717763
1106 23:18:53.717846 Set Vref, RX VrefLevel [Byte0]: 75
1107 23:18:53.721311 [Byte1]: 75
1108 23:18:53.725805
1109 23:18:53.725892 Set Vref, RX VrefLevel [Byte0]: 76
1110 23:18:53.729883 [Byte1]: 76
1111 23:18:53.733686
1112 23:18:53.733771 Set Vref, RX VrefLevel [Byte0]: 77
1113 23:18:53.736892 [Byte1]: 77
1114 23:18:53.740706
1115 23:18:53.740794 Set Vref, RX VrefLevel [Byte0]: 78
1116 23:18:53.745032 [Byte1]: 78
1117 23:18:53.748729
1118 23:18:53.748814 Set Vref, RX VrefLevel [Byte0]: 79
1119 23:18:53.751491 [Byte1]: 79
1120 23:18:53.756136
1121 23:18:53.756220 Final RX Vref Byte 0 = 69 to rank0
1122 23:18:53.759532 Final RX Vref Byte 1 = 63 to rank0
1123 23:18:53.763444 Final RX Vref Byte 0 = 69 to rank1
1124 23:18:53.766187 Final RX Vref Byte 1 = 63 to rank1==
1125 23:18:53.769235 Dram Type= 6, Freq= 0, CH_0, rank 0
1126 23:18:53.775975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1127 23:18:53.776062 ==
1128 23:18:53.776129 DQS Delay:
1129 23:18:53.776191 DQS0 = 0, DQS1 = 0
1130 23:18:53.779645 DQM Delay:
1131 23:18:53.779744 DQM0 = 88, DQM1 = 75
1132 23:18:53.782807 DQ Delay:
1133 23:18:53.785831 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1134 23:18:53.789859 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1135 23:18:53.792646 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =72
1136 23:18:53.796225 DQ12 =84, DQ13 =76, DQ14 =84, DQ15 =80
1137 23:18:53.796307
1138 23:18:53.796374
1139 23:18:53.802370 [DQSOSCAuto] RK0, (LSB)MR18= 0x4325, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
1140 23:18:53.805807 CH0 RK0: MR19=606, MR18=4325
1141 23:18:53.812449 CH0_RK0: MR19=0x606, MR18=0x4325, DQSOSC=393, MR23=63, INC=95, DEC=63
1142 23:18:53.812538
1143 23:18:53.815996 ----->DramcWriteLeveling(PI) begin...
1144 23:18:53.816081 ==
1145 23:18:53.818719 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 23:18:53.822307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 23:18:53.822390 ==
1148 23:18:53.865878 Write leveling (Byte 0): 32 => 32
1149 23:18:53.866027 Write leveling (Byte 1): 29 => 29
1150 23:18:53.866451 DramcWriteLeveling(PI) end<-----
1151 23:18:53.866535
1152 23:18:53.866600 ==
1153 23:18:53.866848 Dram Type= 6, Freq= 0, CH_0, rank 1
1154 23:18:53.866917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1155 23:18:53.866980 ==
1156 23:18:53.867038 [Gating] SW mode calibration
1157 23:18:53.867107 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1158 23:18:53.867406 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1159 23:18:53.867500 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1160 23:18:53.868229 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1161 23:18:53.871445 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1162 23:18:53.871529 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:18:53.877545 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:18:53.881157 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:18:53.884925 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 23:18:53.891390 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 23:18:53.894310 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:18:53.897597 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:18:53.904681 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:18:53.908196 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:18:53.911382 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:18:53.917597 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:18:53.921161 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:18:53.924731 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:18:53.931143 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 23:18:53.934906 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1177 23:18:53.937333 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1178 23:18:53.944211 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1179 23:18:53.948095 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 23:18:53.950516 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 23:18:53.957796 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 23:18:53.960393 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 23:18:53.963648 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 23:18:53.971010 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 23:18:53.974084 0 9 8 | B1->B0 | 2323 2c2c | 1 1 | (1 1) (1 1)
1186 23:18:53.977523 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (1 1) (1 1)
1187 23:18:53.983853 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 23:18:53.986914 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 23:18:53.990056 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 23:18:53.996937 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 23:18:54.000018 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 23:18:54.003361 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
1193 23:18:54.011694 0 10 8 | B1->B0 | 3232 2a2a | 1 0 | (1 0) (0 0)
1194 23:18:54.014802 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1195 23:18:54.017514 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 23:18:54.021870 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 23:18:54.024974 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 23:18:54.032130 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 23:18:54.035287 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 23:18:54.039014 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 23:18:54.042549 0 11 8 | B1->B0 | 3131 3939 | 0 0 | (0 0) (0 0)
1202 23:18:54.049353 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1203 23:18:54.052587 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 23:18:54.055606 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 23:18:54.062606 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 23:18:54.065506 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 23:18:54.069543 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 23:18:54.076720 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 23:18:54.079137 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1210 23:18:54.082809 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1211 23:18:54.089127 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:18:54.092445 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:18:54.096188 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 23:18:54.102098 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 23:18:54.105705 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 23:18:54.108703 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 23:18:54.115810 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 23:18:54.118602 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 23:18:54.122303 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 23:18:54.129056 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 23:18:54.131928 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 23:18:54.135976 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 23:18:54.141972 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 23:18:54.145983 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1225 23:18:54.149113 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1226 23:18:54.155598 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1227 23:18:54.155696 Total UI for P1: 0, mck2ui 16
1228 23:18:54.159319 best dqsien dly found for B0: ( 0, 14, 6)
1229 23:18:54.165081 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1230 23:18:54.169232 Total UI for P1: 0, mck2ui 16
1231 23:18:54.171820 best dqsien dly found for B1: ( 0, 14, 10)
1232 23:18:54.175078 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1233 23:18:54.178643 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1234 23:18:54.178727
1235 23:18:54.181950 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1236 23:18:54.185249 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1237 23:18:54.188949 [Gating] SW calibration Done
1238 23:18:54.189031 ==
1239 23:18:54.191653 Dram Type= 6, Freq= 0, CH_0, rank 1
1240 23:18:54.195021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1241 23:18:54.195104 ==
1242 23:18:54.198784 RX Vref Scan: 0
1243 23:18:54.198866
1244 23:18:54.201916 RX Vref 0 -> 0, step: 1
1245 23:18:54.201998
1246 23:18:54.202063 RX Delay -130 -> 252, step: 16
1247 23:18:54.208499 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1248 23:18:54.211848 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1249 23:18:54.214857 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1250 23:18:54.218071 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1251 23:18:54.225037 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1252 23:18:54.228242 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1253 23:18:54.231242 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1254 23:18:54.234597 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1255 23:18:54.238194 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1256 23:18:54.241398 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1257 23:18:54.248014 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1258 23:18:54.251013 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1259 23:18:54.254768 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1260 23:18:54.258568 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1261 23:18:54.264243 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1262 23:18:54.267644 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1263 23:18:54.267795 ==
1264 23:18:54.270770 Dram Type= 6, Freq= 0, CH_0, rank 1
1265 23:18:54.274128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1266 23:18:54.274210 ==
1267 23:18:54.277749 DQS Delay:
1268 23:18:54.277846 DQS0 = 0, DQS1 = 0
1269 23:18:54.277924 DQM Delay:
1270 23:18:54.281187 DQM0 = 83, DQM1 = 77
1271 23:18:54.281270 DQ Delay:
1272 23:18:54.284286 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1273 23:18:54.288172 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1274 23:18:54.290828 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1275 23:18:54.294837 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1276 23:18:54.294919
1277 23:18:54.294984
1278 23:18:54.295044 ==
1279 23:18:54.297630 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 23:18:54.304246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 23:18:54.304330 ==
1282 23:18:54.304395
1283 23:18:54.304455
1284 23:18:54.304512 TX Vref Scan disable
1285 23:18:54.307414 == TX Byte 0 ==
1286 23:18:54.311471 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1287 23:18:54.318086 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1288 23:18:54.318171 == TX Byte 1 ==
1289 23:18:54.321213 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1290 23:18:54.327697 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1291 23:18:54.327800 ==
1292 23:18:54.330751 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 23:18:54.333741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 23:18:54.333824 ==
1295 23:18:54.347371 TX Vref=22, minBit 8, minWin=26, winSum=442
1296 23:18:54.350461 TX Vref=24, minBit 8, minWin=27, winSum=446
1297 23:18:54.354473 TX Vref=26, minBit 9, minWin=27, winSum=448
1298 23:18:54.357357 TX Vref=28, minBit 8, minWin=27, winSum=447
1299 23:18:54.360322 TX Vref=30, minBit 8, minWin=27, winSum=445
1300 23:18:54.367105 TX Vref=32, minBit 9, minWin=27, winSum=445
1301 23:18:54.370714 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 26
1302 23:18:54.370799
1303 23:18:54.373632 Final TX Range 1 Vref 26
1304 23:18:54.373714
1305 23:18:54.373778 ==
1306 23:18:54.377084 Dram Type= 6, Freq= 0, CH_0, rank 1
1307 23:18:54.380084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1308 23:18:54.380168 ==
1309 23:18:54.383960
1310 23:18:54.384048
1311 23:18:54.384113 TX Vref Scan disable
1312 23:18:54.387073 == TX Byte 0 ==
1313 23:18:54.390487 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1314 23:18:54.396830 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1315 23:18:54.396914 == TX Byte 1 ==
1316 23:18:54.399965 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1317 23:18:54.406801 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1318 23:18:54.406884
1319 23:18:54.406949 [DATLAT]
1320 23:18:54.407010 Freq=800, CH0 RK1
1321 23:18:54.407068
1322 23:18:54.410036 DATLAT Default: 0xa
1323 23:18:54.410117 0, 0xFFFF, sum = 0
1324 23:18:54.413911 1, 0xFFFF, sum = 0
1325 23:18:54.413995 2, 0xFFFF, sum = 0
1326 23:18:54.417868 3, 0xFFFF, sum = 0
1327 23:18:54.419874 4, 0xFFFF, sum = 0
1328 23:18:54.419992 5, 0xFFFF, sum = 0
1329 23:18:54.423360 6, 0xFFFF, sum = 0
1330 23:18:54.423442 7, 0xFFFF, sum = 0
1331 23:18:54.426513 8, 0xFFFF, sum = 0
1332 23:18:54.426598 9, 0x0, sum = 1
1333 23:18:54.430314 10, 0x0, sum = 2
1334 23:18:54.430397 11, 0x0, sum = 3
1335 23:18:54.430464 12, 0x0, sum = 4
1336 23:18:54.433341 best_step = 10
1337 23:18:54.433422
1338 23:18:54.433486 ==
1339 23:18:54.436374 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 23:18:54.440010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 23:18:54.440093 ==
1342 23:18:54.443358 RX Vref Scan: 0
1343 23:18:54.443439
1344 23:18:54.446197 RX Vref 0 -> 0, step: 1
1345 23:18:54.446279
1346 23:18:54.446343 RX Delay -95 -> 252, step: 8
1347 23:18:54.453417 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1348 23:18:54.456836 iDelay=217, Bit 1, Center 88 (-23 ~ 200) 224
1349 23:18:54.460636 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1350 23:18:54.463386 iDelay=217, Bit 3, Center 76 (-39 ~ 192) 232
1351 23:18:54.466646 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1352 23:18:54.473659 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1353 23:18:54.477180 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1354 23:18:54.479997 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1355 23:18:54.483841 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1356 23:18:54.486944 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1357 23:18:54.493991 iDelay=217, Bit 10, Center 80 (-31 ~ 192) 224
1358 23:18:54.497092 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1359 23:18:54.500137 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1360 23:18:54.503568 iDelay=217, Bit 13, Center 80 (-31 ~ 192) 224
1361 23:18:54.510354 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1362 23:18:54.513050 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1363 23:18:54.513134 ==
1364 23:18:54.516531 Dram Type= 6, Freq= 0, CH_0, rank 1
1365 23:18:54.519478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 23:18:54.519559 ==
1367 23:18:54.522833 DQS Delay:
1368 23:18:54.522914 DQS0 = 0, DQS1 = 0
1369 23:18:54.522978 DQM Delay:
1370 23:18:54.526343 DQM0 = 84, DQM1 = 76
1371 23:18:54.526425 DQ Delay:
1372 23:18:54.529343 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =76
1373 23:18:54.532799 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1374 23:18:54.535945 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1375 23:18:54.539651 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1376 23:18:54.539770
1377 23:18:54.539834
1378 23:18:54.549124 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f06, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1379 23:18:54.552368 CH0 RK1: MR19=606, MR18=3F06
1380 23:18:54.556345 CH0_RK1: MR19=0x606, MR18=0x3F06, DQSOSC=393, MR23=63, INC=95, DEC=63
1381 23:18:54.559080 [RxdqsGatingPostProcess] freq 800
1382 23:18:54.566085 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1383 23:18:54.569082 Pre-setting of DQS Precalculation
1384 23:18:54.573844 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1385 23:18:54.575396 ==
1386 23:18:54.575482 Dram Type= 6, Freq= 0, CH_1, rank 0
1387 23:18:54.581968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1388 23:18:54.582051 ==
1389 23:18:54.585135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1390 23:18:54.591665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1391 23:18:54.602200 [CA 0] Center 36 (6~67) winsize 62
1392 23:18:54.605254 [CA 1] Center 36 (6~67) winsize 62
1393 23:18:54.608704 [CA 2] Center 34 (4~65) winsize 62
1394 23:18:54.612370 [CA 3] Center 34 (3~65) winsize 63
1395 23:18:54.614964 [CA 4] Center 34 (4~65) winsize 62
1396 23:18:54.618349 [CA 5] Center 34 (4~65) winsize 62
1397 23:18:54.618437
1398 23:18:54.621736 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1399 23:18:54.621823
1400 23:18:54.624701 [CATrainingPosCal] consider 1 rank data
1401 23:18:54.627918 u2DelayCellTimex100 = 270/100 ps
1402 23:18:54.634905 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1403 23:18:54.638325 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1404 23:18:54.641751 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1405 23:18:54.644504 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1406 23:18:54.648072 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1407 23:18:54.651590 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1408 23:18:54.651680
1409 23:18:54.654775 CA PerBit enable=1, Macro0, CA PI delay=34
1410 23:18:54.654858
1411 23:18:54.657936 [CBTSetCACLKResult] CA Dly = 34
1412 23:18:54.661353 CS Dly: 4 (0~35)
1413 23:18:54.661435 ==
1414 23:18:54.664509 Dram Type= 6, Freq= 0, CH_1, rank 1
1415 23:18:54.668890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 23:18:54.668974 ==
1417 23:18:54.674246 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1418 23:18:54.677582 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1419 23:18:54.688749 [CA 0] Center 36 (6~67) winsize 62
1420 23:18:54.692083 [CA 1] Center 36 (6~67) winsize 62
1421 23:18:54.695801 [CA 2] Center 34 (4~65) winsize 62
1422 23:18:54.699159 [CA 3] Center 34 (4~65) winsize 62
1423 23:18:54.703190 [CA 4] Center 34 (4~65) winsize 62
1424 23:18:54.706585 [CA 5] Center 34 (3~65) winsize 63
1425 23:18:54.706739
1426 23:18:54.710578 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1427 23:18:54.710660
1428 23:18:54.714283 [CATrainingPosCal] consider 2 rank data
1429 23:18:54.714366 u2DelayCellTimex100 = 270/100 ps
1430 23:18:54.720471 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1431 23:18:54.724021 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1432 23:18:54.726929 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1433 23:18:54.730584 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1434 23:18:54.733615 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1435 23:18:54.737142 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1436 23:18:54.737260
1437 23:18:54.740671 CA PerBit enable=1, Macro0, CA PI delay=34
1438 23:18:54.740755
1439 23:18:54.743921 [CBTSetCACLKResult] CA Dly = 34
1440 23:18:54.747120 CS Dly: 5 (0~38)
1441 23:18:54.747202
1442 23:18:54.750547 ----->DramcWriteLeveling(PI) begin...
1443 23:18:54.750631 ==
1444 23:18:54.754050 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 23:18:54.756987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 23:18:54.757071 ==
1447 23:18:54.760853 Write leveling (Byte 0): 27 => 27
1448 23:18:54.763295 Write leveling (Byte 1): 30 => 30
1449 23:18:54.767034 DramcWriteLeveling(PI) end<-----
1450 23:18:54.767116
1451 23:18:54.767181 ==
1452 23:18:54.770074 Dram Type= 6, Freq= 0, CH_1, rank 0
1453 23:18:54.773477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1454 23:18:54.773561 ==
1455 23:18:54.776816 [Gating] SW mode calibration
1456 23:18:54.783613 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1457 23:18:54.790383 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1458 23:18:54.793200 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1459 23:18:54.797121 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1460 23:18:54.803074 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1461 23:18:54.806411 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:18:54.809588 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:18:54.816298 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 23:18:54.820640 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:18:54.823236 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:18:54.830203 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 23:18:54.833614 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:18:54.836162 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:18:54.843177 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:18:54.846244 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:18:54.849613 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:18:54.856586 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:18:54.859638 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 23:18:54.863180 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1475 23:18:54.869505 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1476 23:18:54.872700 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 23:18:54.876648 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 23:18:54.882759 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 23:18:54.885849 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 23:18:54.889541 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 23:18:54.895881 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 23:18:54.900148 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 23:18:54.902850 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 23:18:54.909185 0 9 8 | B1->B0 | 2c2c 3434 | 0 0 | (0 0) (0 0)
1485 23:18:54.912510 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 23:18:54.915951 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 23:18:54.922431 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 23:18:54.925932 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 23:18:54.929433 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 23:18:54.935532 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 23:18:54.938938 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1492 23:18:54.942238 0 10 8 | B1->B0 | 2e2e 2727 | 0 0 | (0 0) (0 0)
1493 23:18:54.949065 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 23:18:54.952540 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 23:18:54.955551 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 23:18:54.962463 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 23:18:54.965787 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 23:18:54.968861 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 23:18:54.975221 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1500 23:18:54.978740 0 11 8 | B1->B0 | 3636 3e3e | 1 0 | (1 1) (0 0)
1501 23:18:54.982396 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 23:18:54.988754 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 23:18:54.992479 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 23:18:54.996142 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 23:18:55.002194 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 23:18:55.005632 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 23:18:55.008706 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1508 23:18:55.015095 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1509 23:18:55.018488 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:18:55.021521 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:18:55.028201 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:18:55.032126 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 23:18:55.035220 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 23:18:55.042703 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 23:18:55.044846 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 23:18:55.048174 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 23:18:55.054885 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 23:18:55.058097 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 23:18:55.061082 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 23:18:55.068112 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 23:18:55.071701 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 23:18:55.075130 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1523 23:18:55.077604 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1524 23:18:55.084463 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1525 23:18:55.088169 Total UI for P1: 0, mck2ui 16
1526 23:18:55.091415 best dqsien dly found for B0: ( 0, 14, 2)
1527 23:18:55.094167 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 23:18:55.097692 Total UI for P1: 0, mck2ui 16
1529 23:18:55.101395 best dqsien dly found for B1: ( 0, 14, 8)
1530 23:18:55.104325 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1531 23:18:55.107662 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1532 23:18:55.107802
1533 23:18:55.111570 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1534 23:18:55.114271 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1535 23:18:55.118282 [Gating] SW calibration Done
1536 23:18:55.118389 ==
1537 23:18:55.120904 Dram Type= 6, Freq= 0, CH_1, rank 0
1538 23:18:55.127522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1539 23:18:55.127656 ==
1540 23:18:55.127768 RX Vref Scan: 0
1541 23:18:55.127831
1542 23:18:55.130678 RX Vref 0 -> 0, step: 1
1543 23:18:55.130765
1544 23:18:55.134707 RX Delay -130 -> 252, step: 16
1545 23:18:55.137753 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1546 23:18:55.140784 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1547 23:18:55.144124 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1548 23:18:55.151112 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1549 23:18:55.153919 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1550 23:18:55.156938 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1551 23:18:55.160669 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1552 23:18:55.164268 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1553 23:18:55.170457 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1554 23:18:55.173685 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1555 23:18:55.177229 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1556 23:18:55.181187 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1557 23:18:55.183618 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1558 23:18:55.190209 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1559 23:18:55.194281 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1560 23:18:55.197580 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1561 23:18:55.197662 ==
1562 23:18:55.200325 Dram Type= 6, Freq= 0, CH_1, rank 0
1563 23:18:55.203592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1564 23:18:55.207131 ==
1565 23:18:55.207212 DQS Delay:
1566 23:18:55.207278 DQS0 = 0, DQS1 = 0
1567 23:18:55.210048 DQM Delay:
1568 23:18:55.210130 DQM0 = 88, DQM1 = 78
1569 23:18:55.213370 DQ Delay:
1570 23:18:55.217199 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1571 23:18:55.219973 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1572 23:18:55.223316 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1573 23:18:55.226555 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1574 23:18:55.226656
1575 23:18:55.226725
1576 23:18:55.226785 ==
1577 23:18:55.229725 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 23:18:55.233508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 23:18:55.233609 ==
1580 23:18:55.233677
1581 23:18:55.233738
1582 23:18:55.236761 TX Vref Scan disable
1583 23:18:55.236858 == TX Byte 0 ==
1584 23:18:55.242993 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1585 23:18:55.247077 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1586 23:18:55.247209 == TX Byte 1 ==
1587 23:18:55.253029 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1588 23:18:55.256115 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1589 23:18:55.256227 ==
1590 23:18:55.259998 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 23:18:55.263209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 23:18:55.263317 ==
1593 23:18:55.277396 TX Vref=22, minBit 8, minWin=26, winSum=441
1594 23:18:55.280222 TX Vref=24, minBit 8, minWin=27, winSum=446
1595 23:18:55.283498 TX Vref=26, minBit 9, minWin=27, winSum=450
1596 23:18:55.286792 TX Vref=28, minBit 8, minWin=27, winSum=450
1597 23:18:55.290287 TX Vref=30, minBit 8, minWin=27, winSum=450
1598 23:18:55.297271 TX Vref=32, minBit 8, minWin=27, winSum=443
1599 23:18:55.301025 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 26
1600 23:18:55.301271
1601 23:18:55.303423 Final TX Range 1 Vref 26
1602 23:18:55.303616
1603 23:18:55.303784 ==
1604 23:18:55.307333 Dram Type= 6, Freq= 0, CH_1, rank 0
1605 23:18:55.310464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1606 23:18:55.314085 ==
1607 23:18:55.314242
1608 23:18:55.314367
1609 23:18:55.314484 TX Vref Scan disable
1610 23:18:55.316831 == TX Byte 0 ==
1611 23:18:55.323756 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1612 23:18:55.326538 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1613 23:18:55.326697 == TX Byte 1 ==
1614 23:18:55.330636 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1615 23:18:55.337144 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1616 23:18:55.337305
1617 23:18:55.337430 [DATLAT]
1618 23:18:55.337547 Freq=800, CH1 RK0
1619 23:18:55.337661
1620 23:18:55.340197 DATLAT Default: 0xa
1621 23:18:55.340422 0, 0xFFFF, sum = 0
1622 23:18:55.343565 1, 0xFFFF, sum = 0
1623 23:18:55.346555 2, 0xFFFF, sum = 0
1624 23:18:55.346825 3, 0xFFFF, sum = 0
1625 23:18:55.350471 4, 0xFFFF, sum = 0
1626 23:18:55.350736 5, 0xFFFF, sum = 0
1627 23:18:55.353584 6, 0xFFFF, sum = 0
1628 23:18:55.353816 7, 0xFFFF, sum = 0
1629 23:18:55.356625 8, 0xFFFF, sum = 0
1630 23:18:55.356792 9, 0x0, sum = 1
1631 23:18:55.359772 10, 0x0, sum = 2
1632 23:18:55.360026 11, 0x0, sum = 3
1633 23:18:55.360263 12, 0x0, sum = 4
1634 23:18:55.363471 best_step = 10
1635 23:18:55.363723
1636 23:18:55.363953 ==
1637 23:18:55.367220 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 23:18:55.370413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 23:18:55.370660 ==
1640 23:18:55.373924 RX Vref Scan: 1
1641 23:18:55.374187
1642 23:18:55.376716 Set Vref Range= 32 -> 127
1643 23:18:55.376918
1644 23:18:55.377134 RX Vref 32 -> 127, step: 1
1645 23:18:55.377378
1646 23:18:55.380287 RX Delay -95 -> 252, step: 8
1647 23:18:55.380555
1648 23:18:55.383379 Set Vref, RX VrefLevel [Byte0]: 32
1649 23:18:55.386567 [Byte1]: 32
1650 23:18:55.389731
1651 23:18:55.389939 Set Vref, RX VrefLevel [Byte0]: 33
1652 23:18:55.392975 [Byte1]: 33
1653 23:18:55.397910
1654 23:18:55.398170 Set Vref, RX VrefLevel [Byte0]: 34
1655 23:18:55.400679 [Byte1]: 34
1656 23:18:55.404897
1657 23:18:55.405155 Set Vref, RX VrefLevel [Byte0]: 35
1658 23:18:55.408405 [Byte1]: 35
1659 23:18:55.412992
1660 23:18:55.413245 Set Vref, RX VrefLevel [Byte0]: 36
1661 23:18:55.415682 [Byte1]: 36
1662 23:18:55.419911
1663 23:18:55.420129 Set Vref, RX VrefLevel [Byte0]: 37
1664 23:18:55.423639 [Byte1]: 37
1665 23:18:55.427321
1666 23:18:55.427489 Set Vref, RX VrefLevel [Byte0]: 38
1667 23:18:55.431634 [Byte1]: 38
1668 23:18:55.435472
1669 23:18:55.435633 Set Vref, RX VrefLevel [Byte0]: 39
1670 23:18:55.438857 [Byte1]: 39
1671 23:18:55.442760
1672 23:18:55.442854 Set Vref, RX VrefLevel [Byte0]: 40
1673 23:18:55.446037 [Byte1]: 40
1674 23:18:55.451119
1675 23:18:55.451215 Set Vref, RX VrefLevel [Byte0]: 41
1676 23:18:55.454019 [Byte1]: 41
1677 23:18:55.458144
1678 23:18:55.458230 Set Vref, RX VrefLevel [Byte0]: 42
1679 23:18:55.461119 [Byte1]: 42
1680 23:18:55.466013
1681 23:18:55.466094 Set Vref, RX VrefLevel [Byte0]: 43
1682 23:18:55.469100 [Byte1]: 43
1683 23:18:55.473578
1684 23:18:55.473660 Set Vref, RX VrefLevel [Byte0]: 44
1685 23:18:55.476792 [Byte1]: 44
1686 23:18:55.480699
1687 23:18:55.480780 Set Vref, RX VrefLevel [Byte0]: 45
1688 23:18:55.487545 [Byte1]: 45
1689 23:18:55.487653
1690 23:18:55.490818 Set Vref, RX VrefLevel [Byte0]: 46
1691 23:18:55.493640 [Byte1]: 46
1692 23:18:55.493722
1693 23:18:55.497242 Set Vref, RX VrefLevel [Byte0]: 47
1694 23:18:55.500514 [Byte1]: 47
1695 23:18:55.503812
1696 23:18:55.503916 Set Vref, RX VrefLevel [Byte0]: 48
1697 23:18:55.507204 [Byte1]: 48
1698 23:18:55.511101
1699 23:18:55.511182 Set Vref, RX VrefLevel [Byte0]: 49
1700 23:18:55.514574 [Byte1]: 49
1701 23:18:55.518904
1702 23:18:55.518986 Set Vref, RX VrefLevel [Byte0]: 50
1703 23:18:55.522525 [Byte1]: 50
1704 23:18:55.526589
1705 23:18:55.526671 Set Vref, RX VrefLevel [Byte0]: 51
1706 23:18:55.529849 [Byte1]: 51
1707 23:18:55.534583
1708 23:18:55.534666 Set Vref, RX VrefLevel [Byte0]: 52
1709 23:18:55.537152 [Byte1]: 52
1710 23:18:55.542147
1711 23:18:55.542229 Set Vref, RX VrefLevel [Byte0]: 53
1712 23:18:55.545519 [Byte1]: 53
1713 23:18:55.549053
1714 23:18:55.549135 Set Vref, RX VrefLevel [Byte0]: 54
1715 23:18:55.552507 [Byte1]: 54
1716 23:18:55.556705
1717 23:18:55.556787 Set Vref, RX VrefLevel [Byte0]: 55
1718 23:18:55.560155 [Byte1]: 55
1719 23:18:55.564922
1720 23:18:55.565004 Set Vref, RX VrefLevel [Byte0]: 56
1721 23:18:55.567617 [Byte1]: 56
1722 23:18:55.571976
1723 23:18:55.572058 Set Vref, RX VrefLevel [Byte0]: 57
1724 23:18:55.575479 [Byte1]: 57
1725 23:18:55.579790
1726 23:18:55.579872 Set Vref, RX VrefLevel [Byte0]: 58
1727 23:18:55.582840 [Byte1]: 58
1728 23:18:55.587345
1729 23:18:55.587426 Set Vref, RX VrefLevel [Byte0]: 59
1730 23:18:55.590752 [Byte1]: 59
1731 23:18:55.594566
1732 23:18:55.594647 Set Vref, RX VrefLevel [Byte0]: 60
1733 23:18:55.598122 [Byte1]: 60
1734 23:18:55.602582
1735 23:18:55.602664 Set Vref, RX VrefLevel [Byte0]: 61
1736 23:18:55.605517 [Byte1]: 61
1737 23:18:55.610173
1738 23:18:55.610255 Set Vref, RX VrefLevel [Byte0]: 62
1739 23:18:55.613353 [Byte1]: 62
1740 23:18:55.617574
1741 23:18:55.617656 Set Vref, RX VrefLevel [Byte0]: 63
1742 23:18:55.621608 [Byte1]: 63
1743 23:18:55.625869
1744 23:18:55.625951 Set Vref, RX VrefLevel [Byte0]: 64
1745 23:18:55.628959 [Byte1]: 64
1746 23:18:55.633107
1747 23:18:55.633188 Set Vref, RX VrefLevel [Byte0]: 65
1748 23:18:55.636045 [Byte1]: 65
1749 23:18:55.640740
1750 23:18:55.640851 Set Vref, RX VrefLevel [Byte0]: 66
1751 23:18:55.643555 [Byte1]: 66
1752 23:18:55.648240
1753 23:18:55.648323 Set Vref, RX VrefLevel [Byte0]: 67
1754 23:18:55.651453 [Byte1]: 67
1755 23:18:55.655849
1756 23:18:55.655959 Set Vref, RX VrefLevel [Byte0]: 68
1757 23:18:55.659167 [Byte1]: 68
1758 23:18:55.663369
1759 23:18:55.663452 Set Vref, RX VrefLevel [Byte0]: 69
1760 23:18:55.666543 [Byte1]: 69
1761 23:18:55.671242
1762 23:18:55.671324 Set Vref, RX VrefLevel [Byte0]: 70
1763 23:18:55.674093 [Byte1]: 70
1764 23:18:55.678293
1765 23:18:55.678375 Set Vref, RX VrefLevel [Byte0]: 71
1766 23:18:55.683604 [Byte1]: 71
1767 23:18:55.685868
1768 23:18:55.685950 Set Vref, RX VrefLevel [Byte0]: 72
1769 23:18:55.689198 [Byte1]: 72
1770 23:18:55.693338
1771 23:18:55.693420 Set Vref, RX VrefLevel [Byte0]: 73
1772 23:18:55.697068 [Byte1]: 73
1773 23:18:55.701486
1774 23:18:55.701607 Set Vref, RX VrefLevel [Byte0]: 74
1775 23:18:55.704713 [Byte1]: 74
1776 23:18:55.710034
1777 23:18:55.710116 Set Vref, RX VrefLevel [Byte0]: 75
1778 23:18:55.711690 [Byte1]: 75
1779 23:18:55.716312
1780 23:18:55.716394 Final RX Vref Byte 0 = 56 to rank0
1781 23:18:55.719602 Final RX Vref Byte 1 = 63 to rank0
1782 23:18:55.722862 Final RX Vref Byte 0 = 56 to rank1
1783 23:18:55.726546 Final RX Vref Byte 1 = 63 to rank1==
1784 23:18:55.729252 Dram Type= 6, Freq= 0, CH_1, rank 0
1785 23:18:55.736391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1786 23:18:55.736478 ==
1787 23:18:55.736544 DQS Delay:
1788 23:18:55.736605 DQS0 = 0, DQS1 = 0
1789 23:18:55.739606 DQM Delay:
1790 23:18:55.739730 DQM0 = 86, DQM1 = 79
1791 23:18:55.742672 DQ Delay:
1792 23:18:55.746424 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1793 23:18:55.749426 DQ4 =80, DQ5 =100, DQ6 =100, DQ7 =80
1794 23:18:55.752835 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1795 23:18:55.756284 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1796 23:18:55.756371
1797 23:18:55.756437
1798 23:18:55.762430 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
1799 23:18:55.765898 CH1 RK0: MR19=606, MR18=2A16
1800 23:18:55.772684 CH1_RK0: MR19=0x606, MR18=0x2A16, DQSOSC=399, MR23=63, INC=92, DEC=61
1801 23:18:55.772768
1802 23:18:55.775993 ----->DramcWriteLeveling(PI) begin...
1803 23:18:55.776077 ==
1804 23:18:55.779417 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 23:18:55.782367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 23:18:55.782533 ==
1807 23:18:55.786537 Write leveling (Byte 0): 23 => 23
1808 23:18:55.789540 Write leveling (Byte 1): 29 => 29
1809 23:18:55.792682 DramcWriteLeveling(PI) end<-----
1810 23:18:55.792834
1811 23:18:55.792976 ==
1812 23:18:55.795693 Dram Type= 6, Freq= 0, CH_1, rank 1
1813 23:18:55.799487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 23:18:55.799639 ==
1815 23:18:55.802380 [Gating] SW mode calibration
1816 23:18:55.809146 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1817 23:18:55.815602 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1818 23:18:55.818871 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1819 23:18:55.825699 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1820 23:18:55.828894 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1821 23:18:55.832367 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 23:18:55.838714 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 23:18:55.842423 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:18:55.845701 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 23:18:55.852414 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 23:18:55.855532 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 23:18:55.858871 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 23:18:55.865176 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 23:18:55.868221 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 23:18:55.871952 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 23:18:55.878576 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 23:18:55.881674 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 23:18:55.884764 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 23:18:55.891804 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:18:55.895024 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1836 23:18:55.898003 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:18:55.904995 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:18:55.908645 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:18:55.911476 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 23:18:55.917886 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 23:18:55.921163 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 23:18:55.924826 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 23:18:55.931010 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 23:18:55.934743 0 9 8 | B1->B0 | 3232 2828 | 1 1 | (0 0) (1 1)
1845 23:18:55.937781 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 23:18:55.944405 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 23:18:55.947881 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 23:18:55.951293 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 23:18:55.958371 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 23:18:55.960848 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 23:18:55.964740 0 10 4 | B1->B0 | 3131 3434 | 0 0 | (0 1) (0 1)
1852 23:18:55.967592 0 10 8 | B1->B0 | 2929 2f2f | 0 0 | (1 0) (0 0)
1853 23:18:55.974631 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 23:18:55.978127 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 23:18:55.981741 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 23:18:55.987526 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 23:18:55.991782 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 23:18:55.994180 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 23:18:56.000899 0 11 4 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
1860 23:18:56.004401 0 11 8 | B1->B0 | 3e3e 3636 | 0 0 | (0 0) (0 0)
1861 23:18:56.007511 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 23:18:56.014094 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 23:18:56.017228 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 23:18:56.020516 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 23:18:56.027332 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 23:18:56.030965 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 23:18:56.034579 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1868 23:18:56.040805 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1869 23:18:56.043932 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 23:18:56.047137 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 23:18:56.053818 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 23:18:56.057345 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 23:18:56.060949 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 23:18:56.067178 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 23:18:56.070766 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 23:18:56.074295 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 23:18:56.080312 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 23:18:56.084486 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 23:18:56.086919 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 23:18:56.093951 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 23:18:56.097076 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 23:18:56.100547 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 23:18:56.106967 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1884 23:18:56.110110 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 23:18:56.113359 Total UI for P1: 0, mck2ui 16
1886 23:18:56.116678 best dqsien dly found for B0: ( 0, 14, 4)
1887 23:18:56.120425 Total UI for P1: 0, mck2ui 16
1888 23:18:56.123520 best dqsien dly found for B1: ( 0, 14, 4)
1889 23:18:56.126866 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1890 23:18:56.130517 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1891 23:18:56.130680
1892 23:18:56.133531 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1893 23:18:56.136768 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1894 23:18:56.139968 [Gating] SW calibration Done
1895 23:18:56.140124 ==
1896 23:18:56.143294 Dram Type= 6, Freq= 0, CH_1, rank 1
1897 23:18:56.146383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1898 23:18:56.146539 ==
1899 23:18:56.149754 RX Vref Scan: 0
1900 23:18:56.149907
1901 23:18:56.153021 RX Vref 0 -> 0, step: 1
1902 23:18:56.153174
1903 23:18:56.156257 RX Delay -130 -> 252, step: 16
1904 23:18:56.160130 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1905 23:18:56.163558 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1906 23:18:56.166284 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1907 23:18:56.169893 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1908 23:18:56.176247 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1909 23:18:56.179520 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1910 23:18:56.182580 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1911 23:18:56.186232 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1912 23:18:56.189331 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1913 23:18:56.196413 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1914 23:18:56.200043 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1915 23:18:56.202664 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1916 23:18:56.206216 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1917 23:18:56.212618 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1918 23:18:56.215920 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1919 23:18:56.219537 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1920 23:18:56.219696 ==
1921 23:18:56.222895 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 23:18:56.226027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 23:18:56.226182 ==
1924 23:18:56.228880 DQS Delay:
1925 23:18:56.229040 DQS0 = 0, DQS1 = 0
1926 23:18:56.232260 DQM Delay:
1927 23:18:56.232415 DQM0 = 86, DQM1 = 78
1928 23:18:56.232558 DQ Delay:
1929 23:18:56.235344 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1930 23:18:56.238893 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1931 23:18:56.242248 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1932 23:18:56.245533 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1933 23:18:56.245692
1934 23:18:56.245838
1935 23:18:56.249359 ==
1936 23:18:56.252410 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 23:18:56.255359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 23:18:56.255516 ==
1939 23:18:56.255660
1940 23:18:56.255841
1941 23:18:56.258787 TX Vref Scan disable
1942 23:18:56.258874 == TX Byte 0 ==
1943 23:18:56.266540 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1944 23:18:56.268646 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1945 23:18:56.268729 == TX Byte 1 ==
1946 23:18:56.275129 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1947 23:18:56.278408 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1948 23:18:56.278491 ==
1949 23:18:56.282817 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 23:18:56.286122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 23:18:56.286206 ==
1952 23:18:56.299666 TX Vref=22, minBit 0, minWin=26, winSum=433
1953 23:18:56.302737 TX Vref=24, minBit 0, minWin=26, winSum=434
1954 23:18:56.306329 TX Vref=26, minBit 0, minWin=27, winSum=444
1955 23:18:56.308912 TX Vref=28, minBit 1, minWin=27, winSum=443
1956 23:18:56.312305 TX Vref=30, minBit 0, minWin=27, winSum=445
1957 23:18:56.318844 TX Vref=32, minBit 1, minWin=27, winSum=444
1958 23:18:56.322823 [TxChooseVref] Worse bit 0, Min win 27, Win sum 445, Final Vref 30
1959 23:18:56.322907
1960 23:18:56.325769 Final TX Range 1 Vref 30
1961 23:18:56.325852
1962 23:18:56.325918 ==
1963 23:18:56.328733 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 23:18:56.332199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 23:18:56.335148 ==
1966 23:18:56.335230
1967 23:18:56.335295
1968 23:18:56.335355 TX Vref Scan disable
1969 23:18:56.339257 == TX Byte 0 ==
1970 23:18:56.343113 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1971 23:18:56.348766 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1972 23:18:56.348851 == TX Byte 1 ==
1973 23:18:56.352365 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1974 23:18:56.359409 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1975 23:18:56.359495
1976 23:18:56.359561 [DATLAT]
1977 23:18:56.359622 Freq=800, CH1 RK1
1978 23:18:56.359711
1979 23:18:56.362110 DATLAT Default: 0xa
1980 23:18:56.362193 0, 0xFFFF, sum = 0
1981 23:18:56.365567 1, 0xFFFF, sum = 0
1982 23:18:56.369344 2, 0xFFFF, sum = 0
1983 23:18:56.369427 3, 0xFFFF, sum = 0
1984 23:18:56.372555 4, 0xFFFF, sum = 0
1985 23:18:56.372639 5, 0xFFFF, sum = 0
1986 23:18:56.375739 6, 0xFFFF, sum = 0
1987 23:18:56.375823 7, 0xFFFF, sum = 0
1988 23:18:56.379127 8, 0xFFFF, sum = 0
1989 23:18:56.379210 9, 0x0, sum = 1
1990 23:18:56.382756 10, 0x0, sum = 2
1991 23:18:56.382845 11, 0x0, sum = 3
1992 23:18:56.382913 12, 0x0, sum = 4
1993 23:18:56.385331 best_step = 10
1994 23:18:56.385414
1995 23:18:56.385478 ==
1996 23:18:56.388470 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 23:18:56.392725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 23:18:56.392823 ==
1999 23:18:56.395379 RX Vref Scan: 0
2000 23:18:56.395462
2001 23:18:56.398651 RX Vref 0 -> 0, step: 1
2002 23:18:56.398733
2003 23:18:56.398798 RX Delay -95 -> 252, step: 8
2004 23:18:56.406234 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2005 23:18:56.409075 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2006 23:18:56.412669 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2007 23:18:56.415905 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2008 23:18:56.420057 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2009 23:18:56.425913 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2010 23:18:56.429004 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2011 23:18:56.432641 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2012 23:18:56.435571 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2013 23:18:56.442455 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2014 23:18:56.445360 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2015 23:18:56.448917 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2016 23:18:56.452316 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2017 23:18:56.455803 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2018 23:18:56.462353 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2019 23:18:56.465423 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2020 23:18:56.465505 ==
2021 23:18:56.468602 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 23:18:56.472330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 23:18:56.472413 ==
2024 23:18:56.475014 DQS Delay:
2025 23:18:56.475096 DQS0 = 0, DQS1 = 0
2026 23:18:56.475161 DQM Delay:
2027 23:18:56.479086 DQM0 = 87, DQM1 = 79
2028 23:18:56.479168 DQ Delay:
2029 23:18:56.482297 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2030 23:18:56.485361 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2031 23:18:56.488698 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
2032 23:18:56.491659 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
2033 23:18:56.491763
2034 23:18:56.491827
2035 23:18:56.502131 [DQSOSCAuto] RK1, (LSB)MR18= 0x1912, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2036 23:18:56.505166 CH1 RK1: MR19=606, MR18=1912
2037 23:18:56.508269 CH1_RK1: MR19=0x606, MR18=0x1912, DQSOSC=403, MR23=63, INC=90, DEC=60
2038 23:18:56.511944 [RxdqsGatingPostProcess] freq 800
2039 23:18:56.519380 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2040 23:18:56.521664 Pre-setting of DQS Precalculation
2041 23:18:56.525278 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2042 23:18:56.534614 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2043 23:18:56.541955 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2044 23:18:56.542037
2045 23:18:56.542102
2046 23:18:56.544638 [Calibration Summary] 1600 Mbps
2047 23:18:56.544721 CH 0, Rank 0
2048 23:18:56.548429 SW Impedance : PASS
2049 23:18:56.548511 DUTY Scan : NO K
2050 23:18:56.551563 ZQ Calibration : PASS
2051 23:18:56.554600 Jitter Meter : NO K
2052 23:18:56.554682 CBT Training : PASS
2053 23:18:56.558857 Write leveling : PASS
2054 23:18:56.561369 RX DQS gating : PASS
2055 23:18:56.561451 RX DQ/DQS(RDDQC) : PASS
2056 23:18:56.564696 TX DQ/DQS : PASS
2057 23:18:56.568359 RX DATLAT : PASS
2058 23:18:56.568441 RX DQ/DQS(Engine): PASS
2059 23:18:56.571418 TX OE : NO K
2060 23:18:56.571499 All Pass.
2061 23:18:56.571563
2062 23:18:56.574582 CH 0, Rank 1
2063 23:18:56.574663 SW Impedance : PASS
2064 23:18:56.578224 DUTY Scan : NO K
2065 23:18:56.581989 ZQ Calibration : PASS
2066 23:18:56.582070 Jitter Meter : NO K
2067 23:18:56.584346 CBT Training : PASS
2068 23:18:56.584427 Write leveling : PASS
2069 23:18:56.587803 RX DQS gating : PASS
2070 23:18:56.590964 RX DQ/DQS(RDDQC) : PASS
2071 23:18:56.591045 TX DQ/DQS : PASS
2072 23:18:56.594340 RX DATLAT : PASS
2073 23:18:56.597746 RX DQ/DQS(Engine): PASS
2074 23:18:56.597827 TX OE : NO K
2075 23:18:56.601238 All Pass.
2076 23:18:56.601350
2077 23:18:56.601417 CH 1, Rank 0
2078 23:18:56.604213 SW Impedance : PASS
2079 23:18:56.604294 DUTY Scan : NO K
2080 23:18:56.608057 ZQ Calibration : PASS
2081 23:18:56.610990 Jitter Meter : NO K
2082 23:18:56.611071 CBT Training : PASS
2083 23:18:56.614820 Write leveling : PASS
2084 23:18:56.617530 RX DQS gating : PASS
2085 23:18:56.617612 RX DQ/DQS(RDDQC) : PASS
2086 23:18:56.620779 TX DQ/DQS : PASS
2087 23:18:56.625189 RX DATLAT : PASS
2088 23:18:56.625272 RX DQ/DQS(Engine): PASS
2089 23:18:56.627885 TX OE : NO K
2090 23:18:56.627969 All Pass.
2091 23:18:56.628034
2092 23:18:56.630825 CH 1, Rank 1
2093 23:18:56.630907 SW Impedance : PASS
2094 23:18:56.634219 DUTY Scan : NO K
2095 23:18:56.637825 ZQ Calibration : PASS
2096 23:18:56.637916 Jitter Meter : NO K
2097 23:18:56.640982 CBT Training : PASS
2098 23:18:56.644263 Write leveling : PASS
2099 23:18:56.644391 RX DQS gating : PASS
2100 23:18:56.647413 RX DQ/DQS(RDDQC) : PASS
2101 23:18:56.647497 TX DQ/DQS : PASS
2102 23:18:56.650593 RX DATLAT : PASS
2103 23:18:56.653633 RX DQ/DQS(Engine): PASS
2104 23:18:56.653717 TX OE : NO K
2105 23:18:56.657472 All Pass.
2106 23:18:56.657557
2107 23:18:56.657623 DramC Write-DBI off
2108 23:18:56.660692 PER_BANK_REFRESH: Hybrid Mode
2109 23:18:56.664098 TX_TRACKING: ON
2110 23:18:56.667979 [GetDramInforAfterCalByMRR] Vendor 6.
2111 23:18:56.671500 [GetDramInforAfterCalByMRR] Revision 606.
2112 23:18:56.674442 [GetDramInforAfterCalByMRR] Revision 2 0.
2113 23:18:56.674798 MR0 0x3b3b
2114 23:18:56.675082 MR8 0x5151
2115 23:18:56.680857 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 23:18:56.681312
2117 23:18:56.681618 MR0 0x3b3b
2118 23:18:56.681879 MR8 0x5151
2119 23:18:56.684209 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 23:18:56.684572
2121 23:18:56.694322 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2122 23:18:56.697281 [FAST_K] Save calibration result to emmc
2123 23:18:56.701566 [FAST_K] Save calibration result to emmc
2124 23:18:56.704415 dram_init: config_dvfs: 1
2125 23:18:56.707602 dramc_set_vcore_voltage set vcore to 662500
2126 23:18:56.710515 Read voltage for 1200, 2
2127 23:18:56.710999 Vio18 = 0
2128 23:18:56.714268 Vcore = 662500
2129 23:18:56.714751 Vdram = 0
2130 23:18:56.715061 Vddq = 0
2131 23:18:56.715348 Vmddr = 0
2132 23:18:56.720256 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2133 23:18:56.726991 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2134 23:18:56.727514 MEM_TYPE=3, freq_sel=15
2135 23:18:56.730337 sv_algorithm_assistance_LP4_1600
2136 23:18:56.733572 ============ PULL DRAM RESETB DOWN ============
2137 23:18:56.740166 ========== PULL DRAM RESETB DOWN end =========
2138 23:18:56.743475 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2139 23:18:56.746736 ===================================
2140 23:18:56.750127 LPDDR4 DRAM CONFIGURATION
2141 23:18:56.753575 ===================================
2142 23:18:56.753966 EX_ROW_EN[0] = 0x0
2143 23:18:56.756898 EX_ROW_EN[1] = 0x0
2144 23:18:56.757286 LP4Y_EN = 0x0
2145 23:18:56.760325 WORK_FSP = 0x0
2146 23:18:56.763278 WL = 0x4
2147 23:18:56.763661 RL = 0x4
2148 23:18:56.766975 BL = 0x2
2149 23:18:56.767361 RPST = 0x0
2150 23:18:56.770377 RD_PRE = 0x0
2151 23:18:56.770797 WR_PRE = 0x1
2152 23:18:56.773632 WR_PST = 0x0
2153 23:18:56.774015 DBI_WR = 0x0
2154 23:18:56.776665 DBI_RD = 0x0
2155 23:18:56.777049 OTF = 0x1
2156 23:18:56.779641 ===================================
2157 23:18:56.783543 ===================================
2158 23:18:56.786743 ANA top config
2159 23:18:56.789568 ===================================
2160 23:18:56.789958 DLL_ASYNC_EN = 0
2161 23:18:56.793441 ALL_SLAVE_EN = 0
2162 23:18:56.796163 NEW_RANK_MODE = 1
2163 23:18:56.799667 DLL_IDLE_MODE = 1
2164 23:18:56.803405 LP45_APHY_COMB_EN = 1
2165 23:18:56.803833 TX_ODT_DIS = 1
2166 23:18:56.807355 NEW_8X_MODE = 1
2167 23:18:56.809531 ===================================
2168 23:18:56.813146 ===================================
2169 23:18:56.816253 data_rate = 2400
2170 23:18:56.819843 CKR = 1
2171 23:18:56.823347 DQ_P2S_RATIO = 8
2172 23:18:56.826696 ===================================
2173 23:18:56.827115 CA_P2S_RATIO = 8
2174 23:18:56.830111 DQ_CA_OPEN = 0
2175 23:18:56.833057 DQ_SEMI_OPEN = 0
2176 23:18:56.836350 CA_SEMI_OPEN = 0
2177 23:18:56.839443 CA_FULL_RATE = 0
2178 23:18:56.843163 DQ_CKDIV4_EN = 0
2179 23:18:56.843719 CA_CKDIV4_EN = 0
2180 23:18:56.846897 CA_PREDIV_EN = 0
2181 23:18:56.849946 PH8_DLY = 17
2182 23:18:56.852768 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2183 23:18:56.856396 DQ_AAMCK_DIV = 4
2184 23:18:56.859310 CA_AAMCK_DIV = 4
2185 23:18:56.859787 CA_ADMCK_DIV = 4
2186 23:18:56.862810 DQ_TRACK_CA_EN = 0
2187 23:18:56.866329 CA_PICK = 1200
2188 23:18:56.869892 CA_MCKIO = 1200
2189 23:18:56.872930 MCKIO_SEMI = 0
2190 23:18:56.876575 PLL_FREQ = 2366
2191 23:18:56.879196 DQ_UI_PI_RATIO = 32
2192 23:18:56.879613 CA_UI_PI_RATIO = 0
2193 23:18:56.883071 ===================================
2194 23:18:56.887510 ===================================
2195 23:18:56.890105 memory_type:LPDDR4
2196 23:18:56.892640 GP_NUM : 10
2197 23:18:56.893064 SRAM_EN : 1
2198 23:18:56.896200 MD32_EN : 0
2199 23:18:56.899646 ===================================
2200 23:18:56.902587 [ANA_INIT] >>>>>>>>>>>>>>
2201 23:18:56.906432 <<<<<< [CONFIGURE PHASE]: ANA_TX
2202 23:18:56.909276 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2203 23:18:56.913725 ===================================
2204 23:18:56.914242 data_rate = 2400,PCW = 0X5b00
2205 23:18:56.915926 ===================================
2206 23:18:56.919226 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2207 23:18:56.925907 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 23:18:56.932147 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2209 23:18:56.936284 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2210 23:18:56.938733 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2211 23:18:56.942741 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2212 23:18:56.945903 [ANA_INIT] flow start
2213 23:18:56.949552 [ANA_INIT] PLL >>>>>>>>
2214 23:18:56.950066 [ANA_INIT] PLL <<<<<<<<
2215 23:18:56.953052 [ANA_INIT] MIDPI >>>>>>>>
2216 23:18:56.956373 [ANA_INIT] MIDPI <<<<<<<<
2217 23:18:56.956795 [ANA_INIT] DLL >>>>>>>>
2218 23:18:56.959089 [ANA_INIT] DLL <<<<<<<<
2219 23:18:56.962748 [ANA_INIT] flow end
2220 23:18:56.966040 ============ LP4 DIFF to SE enter ============
2221 23:18:56.968877 ============ LP4 DIFF to SE exit ============
2222 23:18:56.972029 [ANA_INIT] <<<<<<<<<<<<<
2223 23:18:56.975306 [Flow] Enable top DCM control >>>>>
2224 23:18:56.978655 [Flow] Enable top DCM control <<<<<
2225 23:18:56.982078 Enable DLL master slave shuffle
2226 23:18:56.985252 ==============================================================
2227 23:18:56.989271 Gating Mode config
2228 23:18:56.995514 ==============================================================
2229 23:18:56.996107 Config description:
2230 23:18:57.005359 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2231 23:18:57.012107 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2232 23:18:57.018778 SELPH_MODE 0: By rank 1: By Phase
2233 23:18:57.022101 ==============================================================
2234 23:18:57.025120 GAT_TRACK_EN = 1
2235 23:18:57.028527 RX_GATING_MODE = 2
2236 23:18:57.031811 RX_GATING_TRACK_MODE = 2
2237 23:18:57.034732 SELPH_MODE = 1
2238 23:18:57.038631 PICG_EARLY_EN = 1
2239 23:18:57.041734 VALID_LAT_VALUE = 1
2240 23:18:57.045109 ==============================================================
2241 23:18:57.048287 Enter into Gating configuration >>>>
2242 23:18:57.051830 Exit from Gating configuration <<<<
2243 23:18:57.054889 Enter into DVFS_PRE_config >>>>>
2244 23:18:57.068592 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2245 23:18:57.071816 Exit from DVFS_PRE_config <<<<<
2246 23:18:57.074977 Enter into PICG configuration >>>>
2247 23:18:57.075525 Exit from PICG configuration <<<<
2248 23:18:57.078366 [RX_INPUT] configuration >>>>>
2249 23:18:57.081592 [RX_INPUT] configuration <<<<<
2250 23:18:57.088529 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2251 23:18:57.091651 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2252 23:18:57.098179 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 23:18:57.104716 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 23:18:57.111116 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2255 23:18:57.117714 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2256 23:18:57.120669 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2257 23:18:57.124113 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2258 23:18:57.130964 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2259 23:18:57.135290 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2260 23:18:57.137902 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2261 23:18:57.140876 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2262 23:18:57.144256 ===================================
2263 23:18:57.147122 LPDDR4 DRAM CONFIGURATION
2264 23:18:57.151394 ===================================
2265 23:18:57.154497 EX_ROW_EN[0] = 0x0
2266 23:18:57.155010 EX_ROW_EN[1] = 0x0
2267 23:18:57.157136 LP4Y_EN = 0x0
2268 23:18:57.157549 WORK_FSP = 0x0
2269 23:18:57.160558 WL = 0x4
2270 23:18:57.160969 RL = 0x4
2271 23:18:57.163879 BL = 0x2
2272 23:18:57.164289 RPST = 0x0
2273 23:18:57.167433 RD_PRE = 0x0
2274 23:18:57.168012 WR_PRE = 0x1
2275 23:18:57.170822 WR_PST = 0x0
2276 23:18:57.173945 DBI_WR = 0x0
2277 23:18:57.174464 DBI_RD = 0x0
2278 23:18:57.177138 OTF = 0x1
2279 23:18:57.180413 ===================================
2280 23:18:57.183878 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2281 23:18:57.187080 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2282 23:18:57.190431 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2283 23:18:57.193733 ===================================
2284 23:18:57.196901 LPDDR4 DRAM CONFIGURATION
2285 23:18:57.200192 ===================================
2286 23:18:57.203530 EX_ROW_EN[0] = 0x10
2287 23:18:57.204098 EX_ROW_EN[1] = 0x0
2288 23:18:57.207063 LP4Y_EN = 0x0
2289 23:18:57.207611 WORK_FSP = 0x0
2290 23:18:57.210426 WL = 0x4
2291 23:18:57.210938 RL = 0x4
2292 23:18:57.213743 BL = 0x2
2293 23:18:57.214154 RPST = 0x0
2294 23:18:57.216779 RD_PRE = 0x0
2295 23:18:57.217193 WR_PRE = 0x1
2296 23:18:57.220073 WR_PST = 0x0
2297 23:18:57.220483 DBI_WR = 0x0
2298 23:18:57.223537 DBI_RD = 0x0
2299 23:18:57.226857 OTF = 0x1
2300 23:18:57.229837 ===================================
2301 23:18:57.233541 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2302 23:18:57.236272 ==
2303 23:18:57.236703 Dram Type= 6, Freq= 0, CH_0, rank 0
2304 23:18:57.243069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2305 23:18:57.243461 ==
2306 23:18:57.246475 [Duty_Offset_Calibration]
2307 23:18:57.246991 B0:1 B1:-1 CA:0
2308 23:18:57.247313
2309 23:18:57.249759 [DutyScan_Calibration_Flow] k_type=0
2310 23:18:57.259782
2311 23:18:57.260193 ==CLK 0==
2312 23:18:57.262593 Final CLK duty delay cell = 0
2313 23:18:57.266385 [0] MAX Duty = 5125%(X100), DQS PI = 24
2314 23:18:57.268920 [0] MIN Duty = 4875%(X100), DQS PI = 8
2315 23:18:57.269286 [0] AVG Duty = 5000%(X100)
2316 23:18:57.272750
2317 23:18:57.275868 CH0 CLK Duty spec in!! Max-Min= 250%
2318 23:18:57.278989 [DutyScan_Calibration_Flow] ====Done====
2319 23:18:57.279419
2320 23:18:57.283169 [DutyScan_Calibration_Flow] k_type=1
2321 23:18:57.297583
2322 23:18:57.298107 ==DQS 0 ==
2323 23:18:57.300080 Final DQS duty delay cell = -4
2324 23:18:57.303848 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2325 23:18:57.307452 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2326 23:18:57.310659 [-4] AVG Duty = 4968%(X100)
2327 23:18:57.311196
2328 23:18:57.311526 ==DQS 1 ==
2329 23:18:57.313585 Final DQS duty delay cell = -4
2330 23:18:57.317018 [-4] MAX Duty = 5000%(X100), DQS PI = 8
2331 23:18:57.320830 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2332 23:18:57.323346 [-4] AVG Duty = 4938%(X100)
2333 23:18:57.323800
2334 23:18:57.326876 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2335 23:18:57.327387
2336 23:18:57.330348 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2337 23:18:57.333348 [DutyScan_Calibration_Flow] ====Done====
2338 23:18:57.333874
2339 23:18:57.336721 [DutyScan_Calibration_Flow] k_type=3
2340 23:18:57.355535
2341 23:18:57.356119 ==DQM 0 ==
2342 23:18:57.359152 Final DQM duty delay cell = 0
2343 23:18:57.361901 [0] MAX Duty = 5062%(X100), DQS PI = 18
2344 23:18:57.364892 [0] MIN Duty = 4875%(X100), DQS PI = 6
2345 23:18:57.365616 [0] AVG Duty = 4968%(X100)
2346 23:18:57.368466
2347 23:18:57.368964 ==DQM 1 ==
2348 23:18:57.371607 Final DQM duty delay cell = 4
2349 23:18:57.375943 [4] MAX Duty = 5187%(X100), DQS PI = 14
2350 23:18:57.378090 [4] MIN Duty = 5000%(X100), DQS PI = 24
2351 23:18:57.378504 [4] AVG Duty = 5093%(X100)
2352 23:18:57.382271
2353 23:18:57.385184 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2354 23:18:57.385601
2355 23:18:57.388421 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2356 23:18:57.391630 [DutyScan_Calibration_Flow] ====Done====
2357 23:18:57.392191
2358 23:18:57.395707 [DutyScan_Calibration_Flow] k_type=2
2359 23:18:57.410125
2360 23:18:57.410631 ==DQ 0 ==
2361 23:18:57.413598 Final DQ duty delay cell = -4
2362 23:18:57.416702 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2363 23:18:57.419829 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2364 23:18:57.423180 [-4] AVG Duty = 4969%(X100)
2365 23:18:57.423849
2366 23:18:57.424200 ==DQ 1 ==
2367 23:18:57.426609 Final DQ duty delay cell = -4
2368 23:18:57.429650 [-4] MAX Duty = 5000%(X100), DQS PI = 56
2369 23:18:57.432790 [-4] MIN Duty = 4876%(X100), DQS PI = 26
2370 23:18:57.436395 [-4] AVG Duty = 4938%(X100)
2371 23:18:57.436811
2372 23:18:57.439890 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2373 23:18:57.440463
2374 23:18:57.443024 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2375 23:18:57.446745 [DutyScan_Calibration_Flow] ====Done====
2376 23:18:57.447258 ==
2377 23:18:57.449572 Dram Type= 6, Freq= 0, CH_1, rank 0
2378 23:18:57.453019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2379 23:18:57.453455 ==
2380 23:18:57.456484 [Duty_Offset_Calibration]
2381 23:18:57.456898 B0:-1 B1:1 CA:1
2382 23:18:57.459269
2383 23:18:57.462836 [DutyScan_Calibration_Flow] k_type=0
2384 23:18:57.470755
2385 23:18:57.471266 ==CLK 0==
2386 23:18:57.473729 Final CLK duty delay cell = 0
2387 23:18:57.476792 [0] MAX Duty = 5156%(X100), DQS PI = 22
2388 23:18:57.480630 [0] MIN Duty = 4969%(X100), DQS PI = 62
2389 23:18:57.481147 [0] AVG Duty = 5062%(X100)
2390 23:18:57.483872
2391 23:18:57.487400 CH1 CLK Duty spec in!! Max-Min= 187%
2392 23:18:57.490626 [DutyScan_Calibration_Flow] ====Done====
2393 23:18:57.491143
2394 23:18:57.493612 [DutyScan_Calibration_Flow] k_type=1
2395 23:18:57.510094
2396 23:18:57.510604 ==DQS 0 ==
2397 23:18:57.513249 Final DQS duty delay cell = 0
2398 23:18:57.516643 [0] MAX Duty = 5125%(X100), DQS PI = 48
2399 23:18:57.519593 [0] MIN Duty = 4907%(X100), DQS PI = 6
2400 23:18:57.523352 [0] AVG Duty = 5016%(X100)
2401 23:18:57.523979
2402 23:18:57.524322 ==DQS 1 ==
2403 23:18:57.527105 Final DQS duty delay cell = 0
2404 23:18:57.529729 [0] MAX Duty = 5062%(X100), DQS PI = 10
2405 23:18:57.533617 [0] MIN Duty = 4969%(X100), DQS PI = 58
2406 23:18:57.536417 [0] AVG Duty = 5015%(X100)
2407 23:18:57.536856
2408 23:18:57.539561 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2409 23:18:57.540032
2410 23:18:57.542926 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2411 23:18:57.546187 [DutyScan_Calibration_Flow] ====Done====
2412 23:18:57.546713
2413 23:18:57.549716 [DutyScan_Calibration_Flow] k_type=3
2414 23:18:57.565435
2415 23:18:57.565946 ==DQM 0 ==
2416 23:18:57.569207 Final DQM duty delay cell = -4
2417 23:18:57.572373 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2418 23:18:57.575512 [-4] MIN Duty = 4876%(X100), DQS PI = 8
2419 23:18:57.579452 [-4] AVG Duty = 4969%(X100)
2420 23:18:57.580014
2421 23:18:57.580351 ==DQM 1 ==
2422 23:18:57.581914 Final DQM duty delay cell = 0
2423 23:18:57.585310 [0] MAX Duty = 5156%(X100), DQS PI = 4
2424 23:18:57.588790 [0] MIN Duty = 5000%(X100), DQS PI = 26
2425 23:18:57.591643 [0] AVG Duty = 5078%(X100)
2426 23:18:57.592090
2427 23:18:57.595413 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2428 23:18:57.595888
2429 23:18:57.598689 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2430 23:18:57.602657 [DutyScan_Calibration_Flow] ====Done====
2431 23:18:57.603172
2432 23:18:57.605244 [DutyScan_Calibration_Flow] k_type=2
2433 23:18:57.622180
2434 23:18:57.622686 ==DQ 0 ==
2435 23:18:57.625268 Final DQ duty delay cell = 0
2436 23:18:57.628979 [0] MAX Duty = 5187%(X100), DQS PI = 30
2437 23:18:57.632625 [0] MIN Duty = 4876%(X100), DQS PI = 8
2438 23:18:57.633143 [0] AVG Duty = 5031%(X100)
2439 23:18:57.633475
2440 23:18:57.635166 ==DQ 1 ==
2441 23:18:57.638880 Final DQ duty delay cell = 0
2442 23:18:57.642201 [0] MAX Duty = 5124%(X100), DQS PI = 10
2443 23:18:57.645676 [0] MIN Duty = 4969%(X100), DQS PI = 58
2444 23:18:57.646092 [0] AVG Duty = 5046%(X100)
2445 23:18:57.646421
2446 23:18:57.649890 CH1 DQ 0 Duty spec in!! Max-Min= 311%
2447 23:18:57.652298
2448 23:18:57.655414 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2449 23:18:57.658575 [DutyScan_Calibration_Flow] ====Done====
2450 23:18:57.662144 nWR fixed to 30
2451 23:18:57.662560 [ModeRegInit_LP4] CH0 RK0
2452 23:18:57.665503 [ModeRegInit_LP4] CH0 RK1
2453 23:18:57.668296 [ModeRegInit_LP4] CH1 RK0
2454 23:18:57.671861 [ModeRegInit_LP4] CH1 RK1
2455 23:18:57.672278 match AC timing 7
2456 23:18:57.678450 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2457 23:18:57.681808 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2458 23:18:57.684725 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2459 23:18:57.692015 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2460 23:18:57.694627 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2461 23:18:57.695045 ==
2462 23:18:57.698076 Dram Type= 6, Freq= 0, CH_0, rank 0
2463 23:18:57.701564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2464 23:18:57.701982 ==
2465 23:18:57.708049 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2466 23:18:57.715250 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2467 23:18:57.722196 [CA 0] Center 39 (9~70) winsize 62
2468 23:18:57.725621 [CA 1] Center 39 (9~70) winsize 62
2469 23:18:57.728617 [CA 2] Center 35 (5~66) winsize 62
2470 23:18:57.731917 [CA 3] Center 35 (5~65) winsize 61
2471 23:18:57.735448 [CA 4] Center 33 (3~64) winsize 62
2472 23:18:57.739059 [CA 5] Center 33 (4~63) winsize 60
2473 23:18:57.739579
2474 23:18:57.742139 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2475 23:18:57.742653
2476 23:18:57.744919 [CATrainingPosCal] consider 1 rank data
2477 23:18:57.748586 u2DelayCellTimex100 = 270/100 ps
2478 23:18:57.755190 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2479 23:18:57.758154 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2480 23:18:57.761812 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2481 23:18:57.765153 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2482 23:18:57.767804 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2483 23:18:57.771265 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2484 23:18:57.771823
2485 23:18:57.774878 CA PerBit enable=1, Macro0, CA PI delay=33
2486 23:18:57.775391
2487 23:18:57.778205 [CBTSetCACLKResult] CA Dly = 33
2488 23:18:57.781382 CS Dly: 8 (0~39)
2489 23:18:57.781798 ==
2490 23:18:57.784995 Dram Type= 6, Freq= 0, CH_0, rank 1
2491 23:18:57.788575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2492 23:18:57.789093 ==
2493 23:18:57.794370 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2494 23:18:57.797592 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2495 23:18:57.807983 [CA 0] Center 39 (9~70) winsize 62
2496 23:18:57.811493 [CA 1] Center 39 (9~70) winsize 62
2497 23:18:57.814495 [CA 2] Center 35 (5~66) winsize 62
2498 23:18:57.817584 [CA 3] Center 34 (4~65) winsize 62
2499 23:18:57.821255 [CA 4] Center 33 (3~64) winsize 62
2500 23:18:57.823960 [CA 5] Center 33 (3~63) winsize 61
2501 23:18:57.824441
2502 23:18:57.827946 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2503 23:18:57.828458
2504 23:18:57.834037 [CATrainingPosCal] consider 2 rank data
2505 23:18:57.834552 u2DelayCellTimex100 = 270/100 ps
2506 23:18:57.840497 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2507 23:18:57.844170 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2508 23:18:57.847445 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2509 23:18:57.850359 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2510 23:18:57.853329 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2511 23:18:57.857062 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2512 23:18:57.857480
2513 23:18:57.860431 CA PerBit enable=1, Macro0, CA PI delay=33
2514 23:18:57.860845
2515 23:18:57.863251 [CBTSetCACLKResult] CA Dly = 33
2516 23:18:57.867110 CS Dly: 9 (0~41)
2517 23:18:57.867520
2518 23:18:57.870674 ----->DramcWriteLeveling(PI) begin...
2519 23:18:57.871110 ==
2520 23:18:57.873275 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 23:18:57.876886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 23:18:57.877302 ==
2523 23:18:57.879939 Write leveling (Byte 0): 33 => 33
2524 23:18:57.883316 Write leveling (Byte 1): 30 => 30
2525 23:18:57.887379 DramcWriteLeveling(PI) end<-----
2526 23:18:57.887943
2527 23:18:57.888568 ==
2528 23:18:57.890110 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 23:18:57.893331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 23:18:57.893760 ==
2531 23:18:57.896291 [Gating] SW mode calibration
2532 23:18:57.903667 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2533 23:18:57.910025 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2534 23:18:57.913111 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2535 23:18:57.916635 0 15 4 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
2536 23:18:57.923043 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 23:18:57.926209 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 23:18:57.933126 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 23:18:57.936674 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 23:18:57.939619 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 23:18:57.942500 0 15 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
2542 23:18:57.949698 1 0 0 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
2543 23:18:57.953516 1 0 4 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
2544 23:18:57.956041 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 23:18:57.962928 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 23:18:57.966157 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 23:18:57.969766 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 23:18:57.975952 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 23:18:57.979898 1 0 28 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
2550 23:18:57.982459 1 1 0 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2551 23:18:57.989257 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
2552 23:18:57.992596 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 23:18:57.995538 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 23:18:58.002484 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 23:18:58.005600 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 23:18:58.009368 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 23:18:58.015321 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 23:18:58.018940 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2559 23:18:58.022415 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2560 23:18:58.029020 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 23:18:58.031969 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 23:18:58.036011 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 23:18:58.042848 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 23:18:58.045477 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 23:18:58.048376 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 23:18:58.055884 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 23:18:58.059200 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 23:18:58.062059 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 23:18:58.068657 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 23:18:58.072246 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 23:18:58.075414 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 23:18:58.082165 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2573 23:18:58.085050 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2574 23:18:58.089515 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2575 23:18:58.092262 Total UI for P1: 0, mck2ui 16
2576 23:18:58.095408 best dqsien dly found for B0: ( 1, 3, 26)
2577 23:18:58.101838 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2578 23:18:58.104914 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 23:18:58.108208 Total UI for P1: 0, mck2ui 16
2580 23:18:58.111842 best dqsien dly found for B1: ( 1, 4, 2)
2581 23:18:58.114868 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2582 23:18:58.118923 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2583 23:18:58.119441
2584 23:18:58.121825 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2585 23:18:58.124860 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2586 23:18:58.128242 [Gating] SW calibration Done
2587 23:18:58.128771 ==
2588 23:18:58.131210 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 23:18:58.134652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 23:18:58.138299 ==
2591 23:18:58.138929 RX Vref Scan: 0
2592 23:18:58.139279
2593 23:18:58.141387 RX Vref 0 -> 0, step: 1
2594 23:18:58.141885
2595 23:18:58.144512 RX Delay -40 -> 252, step: 8
2596 23:18:58.147873 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2597 23:18:58.151312 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2598 23:18:58.154116 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2599 23:18:58.157498 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2600 23:18:58.164273 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2601 23:18:58.167581 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2602 23:18:58.170958 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2603 23:18:58.174159 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2604 23:18:58.176908 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2605 23:18:58.184241 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2606 23:18:58.187313 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2607 23:18:58.190930 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2608 23:18:58.193898 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2609 23:18:58.200647 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2610 23:18:58.204044 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2611 23:18:58.207353 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2612 23:18:58.207909 ==
2613 23:18:58.210238 Dram Type= 6, Freq= 0, CH_0, rank 0
2614 23:18:58.213668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2615 23:18:58.214184 ==
2616 23:18:58.217205 DQS Delay:
2617 23:18:58.217722 DQS0 = 0, DQS1 = 0
2618 23:18:58.220184 DQM Delay:
2619 23:18:58.220604 DQM0 = 119, DQM1 = 106
2620 23:18:58.220938 DQ Delay:
2621 23:18:58.227176 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2622 23:18:58.229968 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2623 23:18:58.233292 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2624 23:18:58.236796 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2625 23:18:58.237345
2626 23:18:58.237702
2627 23:18:58.238012 ==
2628 23:18:58.239879 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 23:18:58.243117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 23:18:58.243543 ==
2631 23:18:58.243917
2632 23:18:58.244232
2633 23:18:58.246532 TX Vref Scan disable
2634 23:18:58.250062 == TX Byte 0 ==
2635 23:18:58.253348 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2636 23:18:58.256995 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2637 23:18:58.259788 == TX Byte 1 ==
2638 23:18:58.263091 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2639 23:18:58.266783 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2640 23:18:58.267299 ==
2641 23:18:58.270261 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 23:18:58.273181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 23:18:58.275981 ==
2644 23:18:58.287731 TX Vref=22, minBit 5, minWin=25, winSum=415
2645 23:18:58.290060 TX Vref=24, minBit 1, minWin=25, winSum=424
2646 23:18:58.293333 TX Vref=26, minBit 4, minWin=26, winSum=430
2647 23:18:58.296743 TX Vref=28, minBit 5, minWin=26, winSum=435
2648 23:18:58.300385 TX Vref=30, minBit 10, minWin=26, winSum=431
2649 23:18:58.307169 TX Vref=32, minBit 4, minWin=26, winSum=429
2650 23:18:58.310183 [TxChooseVref] Worse bit 5, Min win 26, Win sum 435, Final Vref 28
2651 23:18:58.310704
2652 23:18:58.313987 Final TX Range 1 Vref 28
2653 23:18:58.314508
2654 23:18:58.314842 ==
2655 23:18:58.316373 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 23:18:58.320352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 23:18:58.320875 ==
2658 23:18:58.323286
2659 23:18:58.323958
2660 23:18:58.324305 TX Vref Scan disable
2661 23:18:58.327114 == TX Byte 0 ==
2662 23:18:58.330015 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2663 23:18:58.337051 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2664 23:18:58.337568 == TX Byte 1 ==
2665 23:18:58.339474 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2666 23:18:58.346192 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2667 23:18:58.346691
2668 23:18:58.347035 [DATLAT]
2669 23:18:58.347350 Freq=1200, CH0 RK0
2670 23:18:58.347654
2671 23:18:58.349485 DATLAT Default: 0xd
2672 23:18:58.349919 0, 0xFFFF, sum = 0
2673 23:18:58.353060 1, 0xFFFF, sum = 0
2674 23:18:58.357091 2, 0xFFFF, sum = 0
2675 23:18:58.357646 3, 0xFFFF, sum = 0
2676 23:18:58.359435 4, 0xFFFF, sum = 0
2677 23:18:58.359944 5, 0xFFFF, sum = 0
2678 23:18:58.362809 6, 0xFFFF, sum = 0
2679 23:18:58.363234 7, 0xFFFF, sum = 0
2680 23:18:58.366256 8, 0xFFFF, sum = 0
2681 23:18:58.366686 9, 0xFFFF, sum = 0
2682 23:18:58.369579 10, 0xFFFF, sum = 0
2683 23:18:58.370136 11, 0xFFFF, sum = 0
2684 23:18:58.372549 12, 0x0, sum = 1
2685 23:18:58.372979 13, 0x0, sum = 2
2686 23:18:58.376109 14, 0x0, sum = 3
2687 23:18:58.376634 15, 0x0, sum = 4
2688 23:18:58.379491 best_step = 13
2689 23:18:58.380134
2690 23:18:58.380615 ==
2691 23:18:58.382598 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 23:18:58.385893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 23:18:58.386320 ==
2694 23:18:58.389384 RX Vref Scan: 1
2695 23:18:58.389899
2696 23:18:58.390241 Set Vref Range= 32 -> 127
2697 23:18:58.390556
2698 23:18:58.392231 RX Vref 32 -> 127, step: 1
2699 23:18:58.392652
2700 23:18:58.396081 RX Delay -21 -> 252, step: 4
2701 23:18:58.396502
2702 23:18:58.399021 Set Vref, RX VrefLevel [Byte0]: 32
2703 23:18:58.402299 [Byte1]: 32
2704 23:18:58.402880
2705 23:18:58.406368 Set Vref, RX VrefLevel [Byte0]: 33
2706 23:18:58.409761 [Byte1]: 33
2707 23:18:58.413013
2708 23:18:58.413531 Set Vref, RX VrefLevel [Byte0]: 34
2709 23:18:58.416431 [Byte1]: 34
2710 23:18:58.421345
2711 23:18:58.421867 Set Vref, RX VrefLevel [Byte0]: 35
2712 23:18:58.423779 [Byte1]: 35
2713 23:18:58.428880
2714 23:18:58.429394 Set Vref, RX VrefLevel [Byte0]: 36
2715 23:18:58.432369 [Byte1]: 36
2716 23:18:58.436651
2717 23:18:58.437075 Set Vref, RX VrefLevel [Byte0]: 37
2718 23:18:58.440223 [Byte1]: 37
2719 23:18:58.444497
2720 23:18:58.444918 Set Vref, RX VrefLevel [Byte0]: 38
2721 23:18:58.447872 [Byte1]: 38
2722 23:18:58.452358
2723 23:18:58.452865 Set Vref, RX VrefLevel [Byte0]: 39
2724 23:18:58.456038 [Byte1]: 39
2725 23:18:58.461064
2726 23:18:58.461479 Set Vref, RX VrefLevel [Byte0]: 40
2727 23:18:58.463899 [Byte1]: 40
2728 23:18:58.468856
2729 23:18:58.469373 Set Vref, RX VrefLevel [Byte0]: 41
2730 23:18:58.471441 [Byte1]: 41
2731 23:18:58.477231
2732 23:18:58.477744 Set Vref, RX VrefLevel [Byte0]: 42
2733 23:18:58.479648 [Byte1]: 42
2734 23:18:58.484185
2735 23:18:58.484733 Set Vref, RX VrefLevel [Byte0]: 43
2736 23:18:58.490889 [Byte1]: 43
2737 23:18:58.491403
2738 23:18:58.494617 Set Vref, RX VrefLevel [Byte0]: 44
2739 23:18:58.496974 [Byte1]: 44
2740 23:18:58.497439
2741 23:18:58.500836 Set Vref, RX VrefLevel [Byte0]: 45
2742 23:18:58.503927 [Byte1]: 45
2743 23:18:58.508057
2744 23:18:58.508565 Set Vref, RX VrefLevel [Byte0]: 46
2745 23:18:58.511442 [Byte1]: 46
2746 23:18:58.516075
2747 23:18:58.516501 Set Vref, RX VrefLevel [Byte0]: 47
2748 23:18:58.519348 [Byte1]: 47
2749 23:18:58.523846
2750 23:18:58.524266 Set Vref, RX VrefLevel [Byte0]: 48
2751 23:18:58.527169 [Byte1]: 48
2752 23:18:58.531868
2753 23:18:58.532380 Set Vref, RX VrefLevel [Byte0]: 49
2754 23:18:58.535398 [Byte1]: 49
2755 23:18:58.539520
2756 23:18:58.539994 Set Vref, RX VrefLevel [Byte0]: 50
2757 23:18:58.542783 [Byte1]: 50
2758 23:18:58.547825
2759 23:18:58.548332 Set Vref, RX VrefLevel [Byte0]: 51
2760 23:18:58.551505 [Byte1]: 51
2761 23:18:58.555817
2762 23:18:58.556327 Set Vref, RX VrefLevel [Byte0]: 52
2763 23:18:58.559398 [Byte1]: 52
2764 23:18:58.564314
2765 23:18:58.564828 Set Vref, RX VrefLevel [Byte0]: 53
2766 23:18:58.566752 [Byte1]: 53
2767 23:18:58.571485
2768 23:18:58.572052 Set Vref, RX VrefLevel [Byte0]: 54
2769 23:18:58.574571 [Byte1]: 54
2770 23:18:58.579759
2771 23:18:58.580267 Set Vref, RX VrefLevel [Byte0]: 55
2772 23:18:58.582609 [Byte1]: 55
2773 23:18:58.587531
2774 23:18:58.588109 Set Vref, RX VrefLevel [Byte0]: 56
2775 23:18:58.590732 [Byte1]: 56
2776 23:18:58.595528
2777 23:18:58.596098 Set Vref, RX VrefLevel [Byte0]: 57
2778 23:18:58.598544 [Byte1]: 57
2779 23:18:58.603002
2780 23:18:58.603518 Set Vref, RX VrefLevel [Byte0]: 58
2781 23:18:58.607145 [Byte1]: 58
2782 23:18:58.611332
2783 23:18:58.611885 Set Vref, RX VrefLevel [Byte0]: 59
2784 23:18:58.614549 [Byte1]: 59
2785 23:18:58.619122
2786 23:18:58.619786 Set Vref, RX VrefLevel [Byte0]: 60
2787 23:18:58.622174 [Byte1]: 60
2788 23:18:58.626559
2789 23:18:58.626972 Set Vref, RX VrefLevel [Byte0]: 61
2790 23:18:58.630347 [Byte1]: 61
2791 23:18:58.635082
2792 23:18:58.635848 Set Vref, RX VrefLevel [Byte0]: 62
2793 23:18:58.638521 [Byte1]: 62
2794 23:18:58.644774
2795 23:18:58.645233 Set Vref, RX VrefLevel [Byte0]: 63
2796 23:18:58.646223 [Byte1]: 63
2797 23:18:58.650335
2798 23:18:58.650751 Set Vref, RX VrefLevel [Byte0]: 64
2799 23:18:58.654714 [Byte1]: 64
2800 23:18:58.658450
2801 23:18:58.658877 Set Vref, RX VrefLevel [Byte0]: 65
2802 23:18:58.661502 [Byte1]: 65
2803 23:18:58.666941
2804 23:18:58.667353 Set Vref, RX VrefLevel [Byte0]: 66
2805 23:18:58.669954 [Byte1]: 66
2806 23:18:58.675637
2807 23:18:58.676185 Set Vref, RX VrefLevel [Byte0]: 67
2808 23:18:58.678300 [Byte1]: 67
2809 23:18:58.682506
2810 23:18:58.683024 Set Vref, RX VrefLevel [Byte0]: 68
2811 23:18:58.685611 [Byte1]: 68
2812 23:18:58.690898
2813 23:18:58.691409 Set Vref, RX VrefLevel [Byte0]: 69
2814 23:18:58.694218 [Byte1]: 69
2815 23:18:58.697964
2816 23:18:58.698377 Set Vref, RX VrefLevel [Byte0]: 70
2817 23:18:58.701444 [Byte1]: 70
2818 23:18:58.706324
2819 23:18:58.706836 Set Vref, RX VrefLevel [Byte0]: 71
2820 23:18:58.710028 [Byte1]: 71
2821 23:18:58.714886
2822 23:18:58.715400 Set Vref, RX VrefLevel [Byte0]: 72
2823 23:18:58.718089 [Byte1]: 72
2824 23:18:58.722421
2825 23:18:58.722938 Set Vref, RX VrefLevel [Byte0]: 73
2826 23:18:58.725468 [Byte1]: 73
2827 23:18:58.730041
2828 23:18:58.730552 Set Vref, RX VrefLevel [Byte0]: 74
2829 23:18:58.733277 [Byte1]: 74
2830 23:18:58.738068
2831 23:18:58.738578 Set Vref, RX VrefLevel [Byte0]: 75
2832 23:18:58.741372 [Byte1]: 75
2833 23:18:58.746376
2834 23:18:58.746889 Set Vref, RX VrefLevel [Byte0]: 76
2835 23:18:58.749323 [Byte1]: 76
2836 23:18:58.754041
2837 23:18:58.754549 Set Vref, RX VrefLevel [Byte0]: 77
2838 23:18:58.756753 [Byte1]: 77
2839 23:18:58.761390
2840 23:18:58.761947 Final RX Vref Byte 0 = 56 to rank0
2841 23:18:58.765108 Final RX Vref Byte 1 = 57 to rank0
2842 23:18:58.768128 Final RX Vref Byte 0 = 56 to rank1
2843 23:18:58.772014 Final RX Vref Byte 1 = 57 to rank1==
2844 23:18:58.775215 Dram Type= 6, Freq= 0, CH_0, rank 0
2845 23:18:58.781403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 23:18:58.781909 ==
2847 23:18:58.782246 DQS Delay:
2848 23:18:58.782557 DQS0 = 0, DQS1 = 0
2849 23:18:58.784620 DQM Delay:
2850 23:18:58.785042 DQM0 = 118, DQM1 = 108
2851 23:18:58.788262 DQ Delay:
2852 23:18:58.792134 DQ0 =118, DQ1 =120, DQ2 =116, DQ3 =114
2853 23:18:58.795087 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2854 23:18:58.798256 DQ8 =96, DQ9 =94, DQ10 =112, DQ11 =104
2855 23:18:58.801876 DQ12 =114, DQ13 =112, DQ14 =122, DQ15 =114
2856 23:18:58.802301
2857 23:18:58.802632
2858 23:18:58.811348 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2859 23:18:58.811830 CH0 RK0: MR19=403, MR18=10FC
2860 23:18:58.817899 CH0_RK0: MR19=0x403, MR18=0x10FC, DQSOSC=403, MR23=63, INC=40, DEC=26
2861 23:18:58.818415
2862 23:18:58.821390 ----->DramcWriteLeveling(PI) begin...
2863 23:18:58.821818 ==
2864 23:18:58.824285 Dram Type= 6, Freq= 0, CH_0, rank 1
2865 23:18:58.831270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2866 23:18:58.831885 ==
2867 23:18:58.835313 Write leveling (Byte 0): 30 => 30
2868 23:18:58.835917 Write leveling (Byte 1): 30 => 30
2869 23:18:58.837729 DramcWriteLeveling(PI) end<-----
2870 23:18:58.838283
2871 23:18:58.838653 ==
2872 23:18:58.841111 Dram Type= 6, Freq= 0, CH_0, rank 1
2873 23:18:58.847873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2874 23:18:58.848419 ==
2875 23:18:58.851442 [Gating] SW mode calibration
2876 23:18:58.857795 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2877 23:18:58.861033 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2878 23:18:58.869077 0 15 0 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2879 23:18:58.870971 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2880 23:18:58.874816 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2881 23:18:58.881039 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2882 23:18:58.884886 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 23:18:58.887614 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 23:18:58.894630 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 23:18:58.897410 0 15 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2886 23:18:58.900937 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2887 23:18:58.907638 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2888 23:18:58.910968 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2889 23:18:58.914093 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 23:18:58.921281 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 23:18:58.924327 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 23:18:58.927891 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 23:18:58.934266 1 0 28 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
2894 23:18:58.937008 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2895 23:18:58.940657 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 23:18:58.946592 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 23:18:58.950033 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 23:18:58.953695 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 23:18:58.960534 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 23:18:58.963559 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 23:18:58.966866 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2902 23:18:58.973215 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2903 23:18:58.976734 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 23:18:58.980621 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 23:18:58.986766 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 23:18:58.990241 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 23:18:58.993105 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 23:18:59.000448 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 23:18:59.002710 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 23:18:59.006460 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 23:18:59.012810 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 23:18:59.016312 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 23:18:59.020303 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 23:18:59.026433 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 23:18:59.030086 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 23:18:59.032932 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2917 23:18:59.036224 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2918 23:18:59.042782 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2919 23:18:59.045756 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 23:18:59.049254 Total UI for P1: 0, mck2ui 16
2921 23:18:59.053077 best dqsien dly found for B0: ( 1, 3, 28)
2922 23:18:59.056048 Total UI for P1: 0, mck2ui 16
2923 23:18:59.059411 best dqsien dly found for B1: ( 1, 3, 30)
2924 23:18:59.062916 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2925 23:18:59.067429 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2926 23:18:59.067908
2927 23:18:59.069091 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2928 23:18:59.075932 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2929 23:18:59.076369 [Gating] SW calibration Done
2930 23:18:59.076816 ==
2931 23:18:59.080239 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 23:18:59.085870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 23:18:59.086305 ==
2934 23:18:59.086748 RX Vref Scan: 0
2935 23:18:59.087166
2936 23:18:59.089593 RX Vref 0 -> 0, step: 1
2937 23:18:59.090022
2938 23:18:59.092551 RX Delay -40 -> 252, step: 8
2939 23:18:59.096207 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2940 23:18:59.099243 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2941 23:18:59.102945 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2942 23:18:59.106357 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2943 23:18:59.113045 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2944 23:18:59.115873 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2945 23:18:59.119165 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2946 23:18:59.122312 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2947 23:18:59.125695 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2948 23:18:59.132811 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2949 23:18:59.135457 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2950 23:18:59.139025 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2951 23:18:59.142515 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2952 23:18:59.145993 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2953 23:18:59.152241 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2954 23:18:59.155572 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2955 23:18:59.156038 ==
2956 23:18:59.159557 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 23:18:59.162011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 23:18:59.162446 ==
2959 23:18:59.165655 DQS Delay:
2960 23:18:59.166082 DQS0 = 0, DQS1 = 0
2961 23:18:59.166522 DQM Delay:
2962 23:18:59.169006 DQM0 = 117, DQM1 = 108
2963 23:18:59.169561 DQ Delay:
2964 23:18:59.172233 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
2965 23:18:59.175867 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2966 23:18:59.179220 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2967 23:18:59.185502 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2968 23:18:59.186039
2969 23:18:59.186491
2970 23:18:59.186906 ==
2971 23:18:59.188863 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 23:18:59.192602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 23:18:59.193139 ==
2974 23:18:59.193591
2975 23:18:59.194009
2976 23:18:59.195596 TX Vref Scan disable
2977 23:18:59.196060 == TX Byte 0 ==
2978 23:18:59.202397 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2979 23:18:59.206004 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2980 23:18:59.206550 == TX Byte 1 ==
2981 23:18:59.212650 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2982 23:18:59.215650 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2983 23:18:59.216130 ==
2984 23:18:59.218855 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 23:18:59.222297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 23:18:59.222840 ==
2987 23:18:59.235459 TX Vref=22, minBit 5, minWin=25, winSum=420
2988 23:18:59.238390 TX Vref=24, minBit 4, minWin=25, winSum=422
2989 23:18:59.242001 TX Vref=26, minBit 1, minWin=26, winSum=426
2990 23:18:59.245360 TX Vref=28, minBit 2, minWin=26, winSum=431
2991 23:18:59.247809 TX Vref=30, minBit 13, minWin=25, winSum=431
2992 23:18:59.255067 TX Vref=32, minBit 11, minWin=26, winSum=431
2993 23:18:59.258928 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 28
2994 23:18:59.259453
2995 23:18:59.262074 Final TX Range 1 Vref 28
2996 23:18:59.262493
2997 23:18:59.262823 ==
2998 23:18:59.264697 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 23:18:59.268215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 23:18:59.272143 ==
3001 23:18:59.272676
3002 23:18:59.273126
3003 23:18:59.273545 TX Vref Scan disable
3004 23:18:59.274939 == TX Byte 0 ==
3005 23:18:59.278729 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3006 23:18:59.285108 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3007 23:18:59.285653 == TX Byte 1 ==
3008 23:18:59.287915 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3009 23:18:59.295176 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3010 23:18:59.295751
3011 23:18:59.296201 [DATLAT]
3012 23:18:59.296615 Freq=1200, CH0 RK1
3013 23:18:59.297023
3014 23:18:59.297765 DATLAT Default: 0xd
3015 23:18:59.298131 0, 0xFFFF, sum = 0
3016 23:18:59.301687 1, 0xFFFF, sum = 0
3017 23:18:59.304863 2, 0xFFFF, sum = 0
3018 23:18:59.305304 3, 0xFFFF, sum = 0
3019 23:18:59.308023 4, 0xFFFF, sum = 0
3020 23:18:59.308570 5, 0xFFFF, sum = 0
3021 23:18:59.312480 6, 0xFFFF, sum = 0
3022 23:18:59.313021 7, 0xFFFF, sum = 0
3023 23:18:59.314989 8, 0xFFFF, sum = 0
3024 23:18:59.315525 9, 0xFFFF, sum = 0
3025 23:18:59.318331 10, 0xFFFF, sum = 0
3026 23:18:59.318873 11, 0xFFFF, sum = 0
3027 23:18:59.321948 12, 0x0, sum = 1
3028 23:18:59.322486 13, 0x0, sum = 2
3029 23:18:59.324404 14, 0x0, sum = 3
3030 23:18:59.324843 15, 0x0, sum = 4
3031 23:18:59.328291 best_step = 13
3032 23:18:59.328825
3033 23:18:59.329274 ==
3034 23:18:59.331751 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 23:18:59.334692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 23:18:59.335130 ==
3037 23:18:59.335569 RX Vref Scan: 0
3038 23:18:59.336021
3039 23:18:59.338672 RX Vref 0 -> 0, step: 1
3040 23:18:59.339264
3041 23:18:59.341358 RX Delay -21 -> 252, step: 4
3042 23:18:59.344407 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3043 23:18:59.351426 iDelay=195, Bit 1, Center 120 (51 ~ 190) 140
3044 23:18:59.355144 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3045 23:18:59.357781 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3046 23:18:59.361172 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3047 23:18:59.365294 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3048 23:18:59.371400 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3049 23:18:59.374659 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3050 23:18:59.378279 iDelay=195, Bit 8, Center 98 (31 ~ 166) 136
3051 23:18:59.381139 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3052 23:18:59.384035 iDelay=195, Bit 10, Center 114 (47 ~ 182) 136
3053 23:18:59.391015 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3054 23:18:59.394978 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3055 23:18:59.398595 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3056 23:18:59.400897 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3057 23:18:59.408310 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3058 23:18:59.408874 ==
3059 23:18:59.410710 Dram Type= 6, Freq= 0, CH_0, rank 1
3060 23:18:59.414915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 23:18:59.415482 ==
3062 23:18:59.415901 DQS Delay:
3063 23:18:59.418022 DQS0 = 0, DQS1 = 0
3064 23:18:59.418578 DQM Delay:
3065 23:18:59.421044 DQM0 = 116, DQM1 = 110
3066 23:18:59.421512 DQ Delay:
3067 23:18:59.423843 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =114
3068 23:18:59.427610 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3069 23:18:59.430437 DQ8 =98, DQ9 =94, DQ10 =114, DQ11 =104
3070 23:18:59.433818 DQ12 =116, DQ13 =114, DQ14 =122, DQ15 =118
3071 23:18:59.434250
3072 23:18:59.434691
3073 23:18:59.444347 [DQSOSCAuto] RK1, (LSB)MR18= 0xae5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
3074 23:18:59.447496 CH0 RK1: MR19=403, MR18=AE5
3075 23:18:59.450475 CH0_RK1: MR19=0x403, MR18=0xAE5, DQSOSC=406, MR23=63, INC=39, DEC=26
3076 23:18:59.454592 [RxdqsGatingPostProcess] freq 1200
3077 23:18:59.461042 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3078 23:18:59.463880 best DQS0 dly(2T, 0.5T) = (0, 11)
3079 23:18:59.467830 best DQS1 dly(2T, 0.5T) = (0, 12)
3080 23:18:59.470987 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3081 23:18:59.474505 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3082 23:18:59.476853 best DQS0 dly(2T, 0.5T) = (0, 11)
3083 23:18:59.480807 best DQS1 dly(2T, 0.5T) = (0, 11)
3084 23:18:59.484062 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3085 23:18:59.486599 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3086 23:18:59.490764 Pre-setting of DQS Precalculation
3087 23:18:59.494072 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3088 23:18:59.494604 ==
3089 23:18:59.496836 Dram Type= 6, Freq= 0, CH_1, rank 0
3090 23:18:59.500332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3091 23:18:59.500767 ==
3092 23:18:59.506664 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3093 23:18:59.513171 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3094 23:18:59.521333 [CA 0] Center 37 (7~68) winsize 62
3095 23:18:59.524643 [CA 1] Center 37 (7~68) winsize 62
3096 23:18:59.527983 [CA 2] Center 34 (4~64) winsize 61
3097 23:18:59.531646 [CA 3] Center 33 (3~64) winsize 62
3098 23:18:59.534467 [CA 4] Center 34 (4~64) winsize 61
3099 23:18:59.537783 [CA 5] Center 33 (3~64) winsize 62
3100 23:18:59.538361
3101 23:18:59.541149 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3102 23:18:59.541625
3103 23:18:59.544265 [CATrainingPosCal] consider 1 rank data
3104 23:18:59.547614 u2DelayCellTimex100 = 270/100 ps
3105 23:18:59.551204 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3106 23:18:59.557510 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3107 23:18:59.560627 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3108 23:18:59.563750 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3109 23:18:59.567138 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3110 23:18:59.570978 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3111 23:18:59.571508
3112 23:18:59.574137 CA PerBit enable=1, Macro0, CA PI delay=33
3113 23:18:59.574652
3114 23:18:59.577126 [CBTSetCACLKResult] CA Dly = 33
3115 23:18:59.580458 CS Dly: 5 (0~36)
3116 23:18:59.580875 ==
3117 23:18:59.584696 Dram Type= 6, Freq= 0, CH_1, rank 1
3118 23:18:59.587045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 23:18:59.587571 ==
3120 23:18:59.594103 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3121 23:18:59.596944 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3122 23:18:59.607065 [CA 0] Center 37 (7~68) winsize 62
3123 23:18:59.610271 [CA 1] Center 38 (8~68) winsize 61
3124 23:18:59.613309 [CA 2] Center 34 (4~65) winsize 62
3125 23:18:59.616869 [CA 3] Center 33 (3~64) winsize 62
3126 23:18:59.620130 [CA 4] Center 34 (4~65) winsize 62
3127 23:18:59.623707 [CA 5] Center 33 (3~64) winsize 62
3128 23:18:59.624260
3129 23:18:59.627204 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3130 23:18:59.627824
3131 23:18:59.629924 [CATrainingPosCal] consider 2 rank data
3132 23:18:59.632944 u2DelayCellTimex100 = 270/100 ps
3133 23:18:59.636488 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3134 23:18:59.643007 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3135 23:18:59.646059 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3136 23:18:59.649827 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3137 23:18:59.652824 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3138 23:18:59.656570 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3139 23:18:59.657081
3140 23:18:59.659783 CA PerBit enable=1, Macro0, CA PI delay=33
3141 23:18:59.660300
3142 23:18:59.662693 [CBTSetCACLKResult] CA Dly = 33
3143 23:18:59.666617 CS Dly: 7 (0~40)
3144 23:18:59.667174
3145 23:18:59.670013 ----->DramcWriteLeveling(PI) begin...
3146 23:18:59.670584 ==
3147 23:18:59.672694 Dram Type= 6, Freq= 0, CH_1, rank 0
3148 23:18:59.676244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3149 23:18:59.676837 ==
3150 23:18:59.679363 Write leveling (Byte 0): 24 => 24
3151 23:18:59.682306 Write leveling (Byte 1): 26 => 26
3152 23:18:59.686429 DramcWriteLeveling(PI) end<-----
3153 23:18:59.687013
3154 23:18:59.687508 ==
3155 23:18:59.689440 Dram Type= 6, Freq= 0, CH_1, rank 0
3156 23:18:59.693057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3157 23:18:59.693639 ==
3158 23:18:59.696157 [Gating] SW mode calibration
3159 23:18:59.703089 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3160 23:18:59.709190 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3161 23:18:59.712819 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3162 23:18:59.716138 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3163 23:18:59.722508 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 23:18:59.726364 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 23:18:59.729086 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 23:18:59.735397 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 23:18:59.739417 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
3168 23:18:59.742541 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
3169 23:18:59.749238 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 23:18:59.752271 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3171 23:18:59.756565 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 23:18:59.763064 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 23:18:59.765924 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 23:18:59.769246 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 23:18:59.775338 1 0 24 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (0 0)
3176 23:18:59.778925 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3177 23:18:59.782370 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 23:18:59.788765 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 23:18:59.792136 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 23:18:59.795452 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 23:18:59.802771 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 23:18:59.805549 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 23:18:59.808606 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3184 23:18:59.812208 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3185 23:18:59.819024 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 23:18:59.822564 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 23:18:59.825387 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 23:18:59.831818 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 23:18:59.835147 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 23:18:59.838533 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 23:18:59.845029 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 23:18:59.848397 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 23:18:59.851843 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 23:18:59.858455 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 23:18:59.861670 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 23:18:59.864836 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 23:18:59.871756 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 23:18:59.874930 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 23:18:59.878074 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3200 23:18:59.884942 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3201 23:18:59.888111 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 23:18:59.891358 Total UI for P1: 0, mck2ui 16
3203 23:18:59.894865 best dqsien dly found for B0: ( 1, 3, 26)
3204 23:18:59.898151 Total UI for P1: 0, mck2ui 16
3205 23:18:59.901675 best dqsien dly found for B1: ( 1, 3, 28)
3206 23:18:59.904841 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3207 23:18:59.908630 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3208 23:18:59.909175
3209 23:18:59.911834 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3210 23:18:59.915279 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3211 23:18:59.918209 [Gating] SW calibration Done
3212 23:18:59.918728 ==
3213 23:18:59.921339 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 23:18:59.928414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 23:18:59.928984 ==
3216 23:18:59.929355 RX Vref Scan: 0
3217 23:18:59.929698
3218 23:18:59.931466 RX Vref 0 -> 0, step: 1
3219 23:18:59.931916
3220 23:18:59.934687 RX Delay -40 -> 252, step: 8
3221 23:18:59.937891 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3222 23:18:59.941203 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3223 23:18:59.944737 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3224 23:18:59.947969 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3225 23:18:59.954956 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3226 23:18:59.958030 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3227 23:18:59.961457 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3228 23:18:59.964542 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3229 23:18:59.967536 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3230 23:18:59.974488 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3231 23:18:59.978014 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3232 23:18:59.981445 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3233 23:18:59.984307 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3234 23:18:59.987801 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3235 23:18:59.994996 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3236 23:18:59.998220 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3237 23:18:59.998866 ==
3238 23:19:00.001453 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 23:19:00.004030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 23:19:00.004455 ==
3241 23:19:00.007654 DQS Delay:
3242 23:19:00.008106 DQS0 = 0, DQS1 = 0
3243 23:19:00.008445 DQM Delay:
3244 23:19:00.010971 DQM0 = 117, DQM1 = 110
3245 23:19:00.011496 DQ Delay:
3246 23:19:00.014362 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3247 23:19:00.017552 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3248 23:19:00.022302 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3249 23:19:00.027738 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3250 23:19:00.028268
3251 23:19:00.028611
3252 23:19:00.028940 ==
3253 23:19:00.030713 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 23:19:00.034871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 23:19:00.035423 ==
3256 23:19:00.035831
3257 23:19:00.036157
3258 23:19:00.037516 TX Vref Scan disable
3259 23:19:00.037938 == TX Byte 0 ==
3260 23:19:00.043979 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3261 23:19:00.047545 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3262 23:19:00.048089 == TX Byte 1 ==
3263 23:19:00.053801 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3264 23:19:00.057809 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3265 23:19:00.058339 ==
3266 23:19:00.060389 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 23:19:00.063960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 23:19:00.064489 ==
3269 23:19:00.077169 TX Vref=22, minBit 9, minWin=25, winSum=416
3270 23:19:00.080256 TX Vref=24, minBit 9, minWin=25, winSum=423
3271 23:19:00.083303 TX Vref=26, minBit 9, minWin=25, winSum=423
3272 23:19:00.086874 TX Vref=28, minBit 9, minWin=26, winSum=433
3273 23:19:00.089778 TX Vref=30, minBit 9, minWin=25, winSum=432
3274 23:19:00.096594 TX Vref=32, minBit 9, minWin=25, winSum=425
3275 23:19:00.099846 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 28
3276 23:19:00.100615
3277 23:19:00.103139 Final TX Range 1 Vref 28
3278 23:19:00.103749
3279 23:19:00.104127 ==
3280 23:19:00.107115 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 23:19:00.110010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 23:19:00.110569 ==
3283 23:19:00.113140
3284 23:19:00.113693
3285 23:19:00.114063 TX Vref Scan disable
3286 23:19:00.115968 == TX Byte 0 ==
3287 23:19:00.119645 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3288 23:19:00.126290 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3289 23:19:00.126812 == TX Byte 1 ==
3290 23:19:00.129657 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3291 23:19:00.135831 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3292 23:19:00.136330
3293 23:19:00.136664 [DATLAT]
3294 23:19:00.136976 Freq=1200, CH1 RK0
3295 23:19:00.137280
3296 23:19:00.139748 DATLAT Default: 0xd
3297 23:19:00.142145 0, 0xFFFF, sum = 0
3298 23:19:00.142571 1, 0xFFFF, sum = 0
3299 23:19:00.145714 2, 0xFFFF, sum = 0
3300 23:19:00.146137 3, 0xFFFF, sum = 0
3301 23:19:00.149127 4, 0xFFFF, sum = 0
3302 23:19:00.149620 5, 0xFFFF, sum = 0
3303 23:19:00.152232 6, 0xFFFF, sum = 0
3304 23:19:00.152656 7, 0xFFFF, sum = 0
3305 23:19:00.155440 8, 0xFFFF, sum = 0
3306 23:19:00.155897 9, 0xFFFF, sum = 0
3307 23:19:00.159384 10, 0xFFFF, sum = 0
3308 23:19:00.159853 11, 0xFFFF, sum = 0
3309 23:19:00.162266 12, 0x0, sum = 1
3310 23:19:00.162689 13, 0x0, sum = 2
3311 23:19:00.165760 14, 0x0, sum = 3
3312 23:19:00.166182 15, 0x0, sum = 4
3313 23:19:00.169117 best_step = 13
3314 23:19:00.169668
3315 23:19:00.170062 ==
3316 23:19:00.172466 Dram Type= 6, Freq= 0, CH_1, rank 0
3317 23:19:00.175627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3318 23:19:00.176074 ==
3319 23:19:00.178392 RX Vref Scan: 1
3320 23:19:00.178813
3321 23:19:00.179143 Set Vref Range= 32 -> 127
3322 23:19:00.179452
3323 23:19:00.182097 RX Vref 32 -> 127, step: 1
3324 23:19:00.182512
3325 23:19:00.185114 RX Delay -21 -> 252, step: 4
3326 23:19:00.185534
3327 23:19:00.188348 Set Vref, RX VrefLevel [Byte0]: 32
3328 23:19:00.192202 [Byte1]: 32
3329 23:19:00.192621
3330 23:19:00.195567 Set Vref, RX VrefLevel [Byte0]: 33
3331 23:19:00.198709 [Byte1]: 33
3332 23:19:00.202684
3333 23:19:00.203100 Set Vref, RX VrefLevel [Byte0]: 34
3334 23:19:00.206413 [Byte1]: 34
3335 23:19:00.211048
3336 23:19:00.211630 Set Vref, RX VrefLevel [Byte0]: 35
3337 23:19:00.213865 [Byte1]: 35
3338 23:19:00.218368
3339 23:19:00.218884 Set Vref, RX VrefLevel [Byte0]: 36
3340 23:19:00.221943 [Byte1]: 36
3341 23:19:00.226600
3342 23:19:00.227017 Set Vref, RX VrefLevel [Byte0]: 37
3343 23:19:00.229735 [Byte1]: 37
3344 23:19:00.234502
3345 23:19:00.234918 Set Vref, RX VrefLevel [Byte0]: 38
3346 23:19:00.237781 [Byte1]: 38
3347 23:19:00.242406
3348 23:19:00.242926 Set Vref, RX VrefLevel [Byte0]: 39
3349 23:19:00.245264 [Byte1]: 39
3350 23:19:00.250002
3351 23:19:00.250592 Set Vref, RX VrefLevel [Byte0]: 40
3352 23:19:00.253149 [Byte1]: 40
3353 23:19:00.258960
3354 23:19:00.259512 Set Vref, RX VrefLevel [Byte0]: 41
3355 23:19:00.261557 [Byte1]: 41
3356 23:19:00.266087
3357 23:19:00.266502 Set Vref, RX VrefLevel [Byte0]: 42
3358 23:19:00.269717 [Byte1]: 42
3359 23:19:00.274580
3360 23:19:00.275097 Set Vref, RX VrefLevel [Byte0]: 43
3361 23:19:00.277062 [Byte1]: 43
3362 23:19:00.281979
3363 23:19:00.282502 Set Vref, RX VrefLevel [Byte0]: 44
3364 23:19:00.285349 [Byte1]: 44
3365 23:19:00.290332
3366 23:19:00.290854 Set Vref, RX VrefLevel [Byte0]: 45
3367 23:19:00.293420 [Byte1]: 45
3368 23:19:00.297934
3369 23:19:00.298460 Set Vref, RX VrefLevel [Byte0]: 46
3370 23:19:00.300710 [Byte1]: 46
3371 23:19:00.305486
3372 23:19:00.306036 Set Vref, RX VrefLevel [Byte0]: 47
3373 23:19:00.308489 [Byte1]: 47
3374 23:19:00.314099
3375 23:19:00.314618 Set Vref, RX VrefLevel [Byte0]: 48
3376 23:19:00.316536 [Byte1]: 48
3377 23:19:00.321373
3378 23:19:00.321898 Set Vref, RX VrefLevel [Byte0]: 49
3379 23:19:00.326045 [Byte1]: 49
3380 23:19:00.329771
3381 23:19:00.330186 Set Vref, RX VrefLevel [Byte0]: 50
3382 23:19:00.332606 [Byte1]: 50
3383 23:19:00.337354
3384 23:19:00.337869 Set Vref, RX VrefLevel [Byte0]: 51
3385 23:19:00.341154 [Byte1]: 51
3386 23:19:00.345322
3387 23:19:00.345835 Set Vref, RX VrefLevel [Byte0]: 52
3388 23:19:00.348254 [Byte1]: 52
3389 23:19:00.353380
3390 23:19:00.353903 Set Vref, RX VrefLevel [Byte0]: 53
3391 23:19:00.356610 [Byte1]: 53
3392 23:19:00.361520
3393 23:19:00.361999 Set Vref, RX VrefLevel [Byte0]: 54
3394 23:19:00.364149 [Byte1]: 54
3395 23:19:00.368700
3396 23:19:00.369116 Set Vref, RX VrefLevel [Byte0]: 55
3397 23:19:00.373052 [Byte1]: 55
3398 23:19:00.376849
3399 23:19:00.377372 Set Vref, RX VrefLevel [Byte0]: 56
3400 23:19:00.381260 [Byte1]: 56
3401 23:19:00.384389
3402 23:19:00.384807 Set Vref, RX VrefLevel [Byte0]: 57
3403 23:19:00.388566 [Byte1]: 57
3404 23:19:00.392393
3405 23:19:00.392916 Set Vref, RX VrefLevel [Byte0]: 58
3406 23:19:00.395944 [Byte1]: 58
3407 23:19:00.401080
3408 23:19:00.401624 Set Vref, RX VrefLevel [Byte0]: 59
3409 23:19:00.403783 [Byte1]: 59
3410 23:19:00.408958
3411 23:19:00.409474 Set Vref, RX VrefLevel [Byte0]: 60
3412 23:19:00.411845 [Byte1]: 60
3413 23:19:00.415988
3414 23:19:00.416408 Set Vref, RX VrefLevel [Byte0]: 61
3415 23:19:00.419712 [Byte1]: 61
3416 23:19:00.424635
3417 23:19:00.425149 Set Vref, RX VrefLevel [Byte0]: 62
3418 23:19:00.427226 [Byte1]: 62
3419 23:19:00.433181
3420 23:19:00.433691 Set Vref, RX VrefLevel [Byte0]: 63
3421 23:19:00.435488 [Byte1]: 63
3422 23:19:00.440765
3423 23:19:00.441279 Set Vref, RX VrefLevel [Byte0]: 64
3424 23:19:00.444060 [Byte1]: 64
3425 23:19:00.448353
3426 23:19:00.448820 Set Vref, RX VrefLevel [Byte0]: 65
3427 23:19:00.451547 [Byte1]: 65
3428 23:19:00.456302
3429 23:19:00.456862 Set Vref, RX VrefLevel [Byte0]: 66
3430 23:19:00.459469 [Byte1]: 66
3431 23:19:00.464105
3432 23:19:00.464694 Set Vref, RX VrefLevel [Byte0]: 67
3433 23:19:00.467499 [Byte1]: 67
3434 23:19:00.472709
3435 23:19:00.473266 Final RX Vref Byte 0 = 46 to rank0
3436 23:19:00.475547 Final RX Vref Byte 1 = 60 to rank0
3437 23:19:00.479397 Final RX Vref Byte 0 = 46 to rank1
3438 23:19:00.482181 Final RX Vref Byte 1 = 60 to rank1==
3439 23:19:00.485722 Dram Type= 6, Freq= 0, CH_1, rank 0
3440 23:19:00.491768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3441 23:19:00.492286 ==
3442 23:19:00.492624 DQS Delay:
3443 23:19:00.492938 DQS0 = 0, DQS1 = 0
3444 23:19:00.495328 DQM Delay:
3445 23:19:00.495899 DQM0 = 115, DQM1 = 112
3446 23:19:00.498913 DQ Delay:
3447 23:19:00.502301 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3448 23:19:00.505220 DQ4 =112, DQ5 =126, DQ6 =126, DQ7 =114
3449 23:19:00.508130 DQ8 =100, DQ9 =100, DQ10 =116, DQ11 =102
3450 23:19:00.512591 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =120
3451 23:19:00.513109
3452 23:19:00.513446
3453 23:19:00.521870 [DQSOSCAuto] RK0, (LSB)MR18= 0xfff3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3454 23:19:00.522389 CH1 RK0: MR19=303, MR18=FFF3
3455 23:19:00.528554 CH1_RK0: MR19=0x303, MR18=0xFFF3, DQSOSC=410, MR23=63, INC=39, DEC=26
3456 23:19:00.529095
3457 23:19:00.531393 ----->DramcWriteLeveling(PI) begin...
3458 23:19:00.531985 ==
3459 23:19:00.535461 Dram Type= 6, Freq= 0, CH_1, rank 1
3460 23:19:00.541750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3461 23:19:00.542359 ==
3462 23:19:00.544524 Write leveling (Byte 0): 24 => 24
3463 23:19:00.548042 Write leveling (Byte 1): 27 => 27
3464 23:19:00.548634 DramcWriteLeveling(PI) end<-----
3465 23:19:00.549136
3466 23:19:00.551402 ==
3467 23:19:00.555090 Dram Type= 6, Freq= 0, CH_1, rank 1
3468 23:19:00.558232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3469 23:19:00.558818 ==
3470 23:19:00.560870 [Gating] SW mode calibration
3471 23:19:00.568639 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3472 23:19:00.571109 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3473 23:19:00.577725 0 15 0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
3474 23:19:00.581912 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3475 23:19:00.584361 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 23:19:00.591657 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3477 23:19:00.594199 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 23:19:00.597364 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 23:19:00.604139 0 15 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 0) (0 0)
3480 23:19:00.607118 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (1 0) (1 0)
3481 23:19:00.610768 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 23:19:00.616962 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 23:19:00.620575 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 23:19:00.623629 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 23:19:00.630461 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 23:19:00.633266 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 23:19:00.636640 1 0 24 | B1->B0 | 3535 2525 | 0 0 | (0 0) (0 0)
3488 23:19:00.643052 1 0 28 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
3489 23:19:00.646685 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 23:19:00.649873 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 23:19:00.655970 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 23:19:00.659874 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 23:19:00.665874 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 23:19:00.669558 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 23:19:00.673131 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 23:19:00.675959 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3497 23:19:00.682324 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 23:19:00.685536 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 23:19:00.692053 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 23:19:00.695664 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 23:19:00.699066 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 23:19:00.705430 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 23:19:00.708784 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 23:19:00.711905 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 23:19:00.718365 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 23:19:00.721445 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 23:19:00.724809 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 23:19:00.731534 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 23:19:00.735182 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 23:19:00.737716 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 23:19:00.744358 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3512 23:19:00.747796 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3513 23:19:00.750910 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 23:19:00.754719 Total UI for P1: 0, mck2ui 16
3515 23:19:00.757538 best dqsien dly found for B0: ( 1, 3, 26)
3516 23:19:00.761468 Total UI for P1: 0, mck2ui 16
3517 23:19:00.764186 best dqsien dly found for B1: ( 1, 3, 26)
3518 23:19:00.767922 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3519 23:19:00.771119 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3520 23:19:00.771201
3521 23:19:00.777684 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3522 23:19:00.781361 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3523 23:19:00.781504 [Gating] SW calibration Done
3524 23:19:00.784399 ==
3525 23:19:00.787385 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 23:19:00.790827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 23:19:00.790929 ==
3528 23:19:00.791022 RX Vref Scan: 0
3529 23:19:00.791114
3530 23:19:00.794430 RX Vref 0 -> 0, step: 1
3531 23:19:00.794530
3532 23:19:00.797561 RX Delay -40 -> 252, step: 8
3533 23:19:00.800426 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3534 23:19:00.804045 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3535 23:19:00.810500 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3536 23:19:00.814959 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3537 23:19:00.817509 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3538 23:19:00.820831 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3539 23:19:00.823992 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3540 23:19:00.830124 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3541 23:19:00.833691 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3542 23:19:00.837380 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3543 23:19:00.840969 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3544 23:19:00.843432 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3545 23:19:00.850493 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3546 23:19:00.853506 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3547 23:19:00.857009 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3548 23:19:00.859807 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3549 23:19:00.859888 ==
3550 23:19:00.863161 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 23:19:00.869934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 23:19:00.870101 ==
3553 23:19:00.870226 DQS Delay:
3554 23:19:00.873298 DQS0 = 0, DQS1 = 0
3555 23:19:00.873429 DQM Delay:
3556 23:19:00.873554 DQM0 = 117, DQM1 = 110
3557 23:19:00.877003 DQ Delay:
3558 23:19:00.879457 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3559 23:19:00.882941 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3560 23:19:00.886258 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3561 23:19:00.889458 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3562 23:19:00.889588
3563 23:19:00.889705
3564 23:19:00.889820 ==
3565 23:19:00.892634 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 23:19:00.899065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 23:19:00.899191 ==
3568 23:19:00.899303
3569 23:19:00.899420
3570 23:19:00.899531 TX Vref Scan disable
3571 23:19:00.903007 == TX Byte 0 ==
3572 23:19:00.906102 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3573 23:19:00.912761 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3574 23:19:00.912863 == TX Byte 1 ==
3575 23:19:00.916088 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3576 23:19:00.922550 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3577 23:19:00.922650 ==
3578 23:19:00.925877 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 23:19:00.928749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 23:19:00.928852 ==
3581 23:19:00.940424 TX Vref=22, minBit 0, minWin=26, winSum=424
3582 23:19:00.943792 TX Vref=24, minBit 10, minWin=26, winSum=433
3583 23:19:00.947043 TX Vref=26, minBit 9, minWin=26, winSum=432
3584 23:19:00.950953 TX Vref=28, minBit 9, minWin=26, winSum=435
3585 23:19:00.953817 TX Vref=30, minBit 9, minWin=26, winSum=437
3586 23:19:00.960728 TX Vref=32, minBit 9, minWin=25, winSum=434
3587 23:19:00.964238 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
3588 23:19:00.964321
3589 23:19:00.966866 Final TX Range 1 Vref 30
3590 23:19:00.966973
3591 23:19:00.967069 ==
3592 23:19:00.970237 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 23:19:00.974703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 23:19:00.977089 ==
3595 23:19:00.977269
3596 23:19:00.977362
3597 23:19:00.977449 TX Vref Scan disable
3598 23:19:00.980402 == TX Byte 0 ==
3599 23:19:00.983734 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3600 23:19:00.990397 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3601 23:19:00.990616 == TX Byte 1 ==
3602 23:19:00.994669 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3603 23:19:01.000286 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3604 23:19:01.000548
3605 23:19:01.000703 [DATLAT]
3606 23:19:01.000842 Freq=1200, CH1 RK1
3607 23:19:01.000975
3608 23:19:01.003741 DATLAT Default: 0xd
3609 23:19:01.007917 0, 0xFFFF, sum = 0
3610 23:19:01.008259 1, 0xFFFF, sum = 0
3611 23:19:01.010193 2, 0xFFFF, sum = 0
3612 23:19:01.010530 3, 0xFFFF, sum = 0
3613 23:19:01.014175 4, 0xFFFF, sum = 0
3614 23:19:01.014577 5, 0xFFFF, sum = 0
3615 23:19:01.017149 6, 0xFFFF, sum = 0
3616 23:19:01.017596 7, 0xFFFF, sum = 0
3617 23:19:01.021282 8, 0xFFFF, sum = 0
3618 23:19:01.021783 9, 0xFFFF, sum = 0
3619 23:19:01.023951 10, 0xFFFF, sum = 0
3620 23:19:01.024422 11, 0xFFFF, sum = 0
3621 23:19:01.027244 12, 0x0, sum = 1
3622 23:19:01.027908 13, 0x0, sum = 2
3623 23:19:01.030170 14, 0x0, sum = 3
3624 23:19:01.030642 15, 0x0, sum = 4
3625 23:19:01.033377 best_step = 13
3626 23:19:01.033907
3627 23:19:01.034243 ==
3628 23:19:01.036551 Dram Type= 6, Freq= 0, CH_1, rank 1
3629 23:19:01.040280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3630 23:19:01.040752 ==
3631 23:19:01.043715 RX Vref Scan: 0
3632 23:19:01.044268
3633 23:19:01.044741 RX Vref 0 -> 0, step: 1
3634 23:19:01.045188
3635 23:19:01.046427 RX Delay -21 -> 252, step: 4
3636 23:19:01.053309 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3637 23:19:01.056495 iDelay=199, Bit 1, Center 110 (47 ~ 174) 128
3638 23:19:01.059997 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3639 23:19:01.062961 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3640 23:19:01.066478 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3641 23:19:01.073654 iDelay=199, Bit 5, Center 126 (63 ~ 190) 128
3642 23:19:01.076359 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3643 23:19:01.079634 iDelay=199, Bit 7, Center 112 (47 ~ 178) 132
3644 23:19:01.082902 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3645 23:19:01.086644 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3646 23:19:01.092887 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3647 23:19:01.096679 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3648 23:19:01.099415 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3649 23:19:01.102868 iDelay=199, Bit 13, Center 118 (55 ~ 182) 128
3650 23:19:01.109992 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3651 23:19:01.113304 iDelay=199, Bit 15, Center 122 (55 ~ 190) 136
3652 23:19:01.113833 ==
3653 23:19:01.115959 Dram Type= 6, Freq= 0, CH_1, rank 1
3654 23:19:01.120404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3655 23:19:01.121006 ==
3656 23:19:01.121362 DQS Delay:
3657 23:19:01.122935 DQS0 = 0, DQS1 = 0
3658 23:19:01.123357 DQM Delay:
3659 23:19:01.126925 DQM0 = 116, DQM1 = 111
3660 23:19:01.127451 DQ Delay:
3661 23:19:01.129875 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3662 23:19:01.132399 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =112
3663 23:19:01.135875 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =102
3664 23:19:01.142817 DQ12 =120, DQ13 =118, DQ14 =120, DQ15 =122
3665 23:19:01.143344
3666 23:19:01.143736
3667 23:19:01.148912 [DQSOSCAuto] RK1, (LSB)MR18= 0xf2ed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3668 23:19:01.152437 CH1 RK1: MR19=303, MR18=F2ED
3669 23:19:01.159219 CH1_RK1: MR19=0x303, MR18=0xF2ED, DQSOSC=415, MR23=63, INC=38, DEC=25
3670 23:19:01.162010 [RxdqsGatingPostProcess] freq 1200
3671 23:19:01.165426 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3672 23:19:01.169551 best DQS0 dly(2T, 0.5T) = (0, 11)
3673 23:19:01.172231 best DQS1 dly(2T, 0.5T) = (0, 11)
3674 23:19:01.175921 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3675 23:19:01.178534 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3676 23:19:01.182523 best DQS0 dly(2T, 0.5T) = (0, 11)
3677 23:19:01.185438 best DQS1 dly(2T, 0.5T) = (0, 11)
3678 23:19:01.189455 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3679 23:19:01.192025 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3680 23:19:01.195423 Pre-setting of DQS Precalculation
3681 23:19:01.198453 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3682 23:19:01.208596 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3683 23:19:01.214869 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3684 23:19:01.215486
3685 23:19:01.215910
3686 23:19:01.217855 [Calibration Summary] 2400 Mbps
3687 23:19:01.218319 CH 0, Rank 0
3688 23:19:01.221178 SW Impedance : PASS
3689 23:19:01.224820 DUTY Scan : NO K
3690 23:19:01.225341 ZQ Calibration : PASS
3691 23:19:01.228052 Jitter Meter : NO K
3692 23:19:01.228473 CBT Training : PASS
3693 23:19:01.231356 Write leveling : PASS
3694 23:19:01.234566 RX DQS gating : PASS
3695 23:19:01.235092 RX DQ/DQS(RDDQC) : PASS
3696 23:19:01.237930 TX DQ/DQS : PASS
3697 23:19:01.241778 RX DATLAT : PASS
3698 23:19:01.242312 RX DQ/DQS(Engine): PASS
3699 23:19:01.244841 TX OE : NO K
3700 23:19:01.245367 All Pass.
3701 23:19:01.245867
3702 23:19:01.247892 CH 0, Rank 1
3703 23:19:01.248313 SW Impedance : PASS
3704 23:19:01.251535 DUTY Scan : NO K
3705 23:19:01.254245 ZQ Calibration : PASS
3706 23:19:01.254674 Jitter Meter : NO K
3707 23:19:01.258250 CBT Training : PASS
3708 23:19:01.260934 Write leveling : PASS
3709 23:19:01.261358 RX DQS gating : PASS
3710 23:19:01.264355 RX DQ/DQS(RDDQC) : PASS
3711 23:19:01.267554 TX DQ/DQS : PASS
3712 23:19:01.268041 RX DATLAT : PASS
3713 23:19:01.271070 RX DQ/DQS(Engine): PASS
3714 23:19:01.273966 TX OE : NO K
3715 23:19:01.274390 All Pass.
3716 23:19:01.274724
3717 23:19:01.275037 CH 1, Rank 0
3718 23:19:01.277305 SW Impedance : PASS
3719 23:19:01.280835 DUTY Scan : NO K
3720 23:19:01.281257 ZQ Calibration : PASS
3721 23:19:01.283708 Jitter Meter : NO K
3722 23:19:01.288483 CBT Training : PASS
3723 23:19:01.288909 Write leveling : PASS
3724 23:19:01.290305 RX DQS gating : PASS
3725 23:19:01.293427 RX DQ/DQS(RDDQC) : PASS
3726 23:19:01.293852 TX DQ/DQS : PASS
3727 23:19:01.296969 RX DATLAT : PASS
3728 23:19:01.300369 RX DQ/DQS(Engine): PASS
3729 23:19:01.300790 TX OE : NO K
3730 23:19:01.301126 All Pass.
3731 23:19:01.303523
3732 23:19:01.303966 CH 1, Rank 1
3733 23:19:01.307511 SW Impedance : PASS
3734 23:19:01.308103 DUTY Scan : NO K
3735 23:19:01.310801 ZQ Calibration : PASS
3736 23:19:01.311225 Jitter Meter : NO K
3737 23:19:01.314095 CBT Training : PASS
3738 23:19:01.317352 Write leveling : PASS
3739 23:19:01.317773 RX DQS gating : PASS
3740 23:19:01.320277 RX DQ/DQS(RDDQC) : PASS
3741 23:19:01.323445 TX DQ/DQS : PASS
3742 23:19:01.323906 RX DATLAT : PASS
3743 23:19:01.326473 RX DQ/DQS(Engine): PASS
3744 23:19:01.329960 TX OE : NO K
3745 23:19:01.330383 All Pass.
3746 23:19:01.330719
3747 23:19:01.333121 DramC Write-DBI off
3748 23:19:01.333542 PER_BANK_REFRESH: Hybrid Mode
3749 23:19:01.336836 TX_TRACKING: ON
3750 23:19:01.346824 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3751 23:19:01.349704 [FAST_K] Save calibration result to emmc
3752 23:19:01.352664 dramc_set_vcore_voltage set vcore to 650000
3753 23:19:01.356265 Read voltage for 600, 5
3754 23:19:01.356686 Vio18 = 0
3755 23:19:01.357021 Vcore = 650000
3756 23:19:01.359599 Vdram = 0
3757 23:19:01.360068 Vddq = 0
3758 23:19:01.360403 Vmddr = 0
3759 23:19:01.366003 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3760 23:19:01.369688 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3761 23:19:01.373046 MEM_TYPE=3, freq_sel=19
3762 23:19:01.376238 sv_algorithm_assistance_LP4_1600
3763 23:19:01.379430 ============ PULL DRAM RESETB DOWN ============
3764 23:19:01.383017 ========== PULL DRAM RESETB DOWN end =========
3765 23:19:01.388988 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3766 23:19:01.393250 ===================================
3767 23:19:01.393818 LPDDR4 DRAM CONFIGURATION
3768 23:19:01.396588 ===================================
3769 23:19:01.399582 EX_ROW_EN[0] = 0x0
3770 23:19:01.402202 EX_ROW_EN[1] = 0x0
3771 23:19:01.402746 LP4Y_EN = 0x0
3772 23:19:01.405610 WORK_FSP = 0x0
3773 23:19:01.406164 WL = 0x2
3774 23:19:01.409047 RL = 0x2
3775 23:19:01.409634 BL = 0x2
3776 23:19:01.412629 RPST = 0x0
3777 23:19:01.413087 RD_PRE = 0x0
3778 23:19:01.415584 WR_PRE = 0x1
3779 23:19:01.416184 WR_PST = 0x0
3780 23:19:01.418703 DBI_WR = 0x0
3781 23:19:01.419158 DBI_RD = 0x0
3782 23:19:01.422292 OTF = 0x1
3783 23:19:01.425744 ===================================
3784 23:19:01.428715 ===================================
3785 23:19:01.429201 ANA top config
3786 23:19:01.432257 ===================================
3787 23:19:01.435878 DLL_ASYNC_EN = 0
3788 23:19:01.438907 ALL_SLAVE_EN = 1
3789 23:19:01.442655 NEW_RANK_MODE = 1
3790 23:19:01.443182 DLL_IDLE_MODE = 1
3791 23:19:01.445235 LP45_APHY_COMB_EN = 1
3792 23:19:01.449232 TX_ODT_DIS = 1
3793 23:19:01.451893 NEW_8X_MODE = 1
3794 23:19:01.455148 ===================================
3795 23:19:01.458617 ===================================
3796 23:19:01.461808 data_rate = 1200
3797 23:19:01.465026 CKR = 1
3798 23:19:01.465486 DQ_P2S_RATIO = 8
3799 23:19:01.469829 ===================================
3800 23:19:01.471722 CA_P2S_RATIO = 8
3801 23:19:01.475170 DQ_CA_OPEN = 0
3802 23:19:01.479470 DQ_SEMI_OPEN = 0
3803 23:19:01.482138 CA_SEMI_OPEN = 0
3804 23:19:01.484623 CA_FULL_RATE = 0
3805 23:19:01.485085 DQ_CKDIV4_EN = 1
3806 23:19:01.488465 CA_CKDIV4_EN = 1
3807 23:19:01.492063 CA_PREDIV_EN = 0
3808 23:19:01.495353 PH8_DLY = 0
3809 23:19:01.498568 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3810 23:19:01.501387 DQ_AAMCK_DIV = 4
3811 23:19:01.501849 CA_AAMCK_DIV = 4
3812 23:19:01.504671 CA_ADMCK_DIV = 4
3813 23:19:01.508134 DQ_TRACK_CA_EN = 0
3814 23:19:01.511447 CA_PICK = 600
3815 23:19:01.514584 CA_MCKIO = 600
3816 23:19:01.517853 MCKIO_SEMI = 0
3817 23:19:01.521615 PLL_FREQ = 2288
3818 23:19:01.522175 DQ_UI_PI_RATIO = 32
3819 23:19:01.524524 CA_UI_PI_RATIO = 0
3820 23:19:01.528049 ===================================
3821 23:19:01.531570 ===================================
3822 23:19:01.534397 memory_type:LPDDR4
3823 23:19:01.538387 GP_NUM : 10
3824 23:19:01.538949 SRAM_EN : 1
3825 23:19:01.541505 MD32_EN : 0
3826 23:19:01.545487 ===================================
3827 23:19:01.547858 [ANA_INIT] >>>>>>>>>>>>>>
3828 23:19:01.548426 <<<<<< [CONFIGURE PHASE]: ANA_TX
3829 23:19:01.554247 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3830 23:19:01.557877 ===================================
3831 23:19:01.558445 data_rate = 1200,PCW = 0X5800
3832 23:19:01.560833 ===================================
3833 23:19:01.564133 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3834 23:19:01.570735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3835 23:19:01.577333 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3836 23:19:01.580749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3837 23:19:01.583555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3838 23:19:01.587531 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3839 23:19:01.590845 [ANA_INIT] flow start
3840 23:19:01.591413 [ANA_INIT] PLL >>>>>>>>
3841 23:19:01.593781 [ANA_INIT] PLL <<<<<<<<
3842 23:19:01.597091 [ANA_INIT] MIDPI >>>>>>>>
3843 23:19:01.600405 [ANA_INIT] MIDPI <<<<<<<<
3844 23:19:01.600967 [ANA_INIT] DLL >>>>>>>>
3845 23:19:01.603784 [ANA_INIT] flow end
3846 23:19:01.607246 ============ LP4 DIFF to SE enter ============
3847 23:19:01.611032 ============ LP4 DIFF to SE exit ============
3848 23:19:01.614082 [ANA_INIT] <<<<<<<<<<<<<
3849 23:19:01.617485 [Flow] Enable top DCM control >>>>>
3850 23:19:01.620316 [Flow] Enable top DCM control <<<<<
3851 23:19:01.623505 Enable DLL master slave shuffle
3852 23:19:01.630519 ==============================================================
3853 23:19:01.631080 Gating Mode config
3854 23:19:01.636917 ==============================================================
3855 23:19:01.637481 Config description:
3856 23:19:01.646092 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3857 23:19:01.652749 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3858 23:19:01.660254 SELPH_MODE 0: By rank 1: By Phase
3859 23:19:01.666186 ==============================================================
3860 23:19:01.666756 GAT_TRACK_EN = 1
3861 23:19:01.669791 RX_GATING_MODE = 2
3862 23:19:01.672459 RX_GATING_TRACK_MODE = 2
3863 23:19:01.675902 SELPH_MODE = 1
3864 23:19:01.679714 PICG_EARLY_EN = 1
3865 23:19:01.682564 VALID_LAT_VALUE = 1
3866 23:19:01.689635 ==============================================================
3867 23:19:01.692400 Enter into Gating configuration >>>>
3868 23:19:01.695882 Exit from Gating configuration <<<<
3869 23:19:01.699070 Enter into DVFS_PRE_config >>>>>
3870 23:19:01.708827 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3871 23:19:01.712243 Exit from DVFS_PRE_config <<<<<
3872 23:19:01.715485 Enter into PICG configuration >>>>
3873 23:19:01.718733 Exit from PICG configuration <<<<
3874 23:19:01.721951 [RX_INPUT] configuration >>>>>
3875 23:19:01.725700 [RX_INPUT] configuration <<<<<
3876 23:19:01.728583 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3877 23:19:01.736151 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3878 23:19:01.742265 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3879 23:19:01.749118 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3880 23:19:01.751834 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3881 23:19:01.758374 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3882 23:19:01.761861 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3883 23:19:01.768546 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3884 23:19:01.771845 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3885 23:19:01.775488 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3886 23:19:01.778034 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3887 23:19:01.784622 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3888 23:19:01.787641 ===================================
3889 23:19:01.791498 LPDDR4 DRAM CONFIGURATION
3890 23:19:01.794324 ===================================
3891 23:19:01.794791 EX_ROW_EN[0] = 0x0
3892 23:19:01.797883 EX_ROW_EN[1] = 0x0
3893 23:19:01.798453 LP4Y_EN = 0x0
3894 23:19:01.801427 WORK_FSP = 0x0
3895 23:19:01.801893 WL = 0x2
3896 23:19:01.804536 RL = 0x2
3897 23:19:01.805172 BL = 0x2
3898 23:19:01.808142 RPST = 0x0
3899 23:19:01.808693 RD_PRE = 0x0
3900 23:19:01.811466 WR_PRE = 0x1
3901 23:19:01.811928 WR_PST = 0x0
3902 23:19:01.814768 DBI_WR = 0x0
3903 23:19:01.818387 DBI_RD = 0x0
3904 23:19:01.818948 OTF = 0x1
3905 23:19:01.821326 ===================================
3906 23:19:01.824384 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3907 23:19:01.827755 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3908 23:19:01.834598 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3909 23:19:01.837816 ===================================
3910 23:19:01.841284 LPDDR4 DRAM CONFIGURATION
3911 23:19:01.844135 ===================================
3912 23:19:01.844650 EX_ROW_EN[0] = 0x10
3913 23:19:01.847313 EX_ROW_EN[1] = 0x0
3914 23:19:01.847871 LP4Y_EN = 0x0
3915 23:19:01.850715 WORK_FSP = 0x0
3916 23:19:01.851231 WL = 0x2
3917 23:19:01.853829 RL = 0x2
3918 23:19:01.854246 BL = 0x2
3919 23:19:01.857339 RPST = 0x0
3920 23:19:01.860263 RD_PRE = 0x0
3921 23:19:01.860678 WR_PRE = 0x1
3922 23:19:01.863779 WR_PST = 0x0
3923 23:19:01.864316 DBI_WR = 0x0
3924 23:19:01.867085 DBI_RD = 0x0
3925 23:19:01.867572 OTF = 0x1
3926 23:19:01.870141 ===================================
3927 23:19:01.876466 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3928 23:19:01.880613 nWR fixed to 30
3929 23:19:01.883786 [ModeRegInit_LP4] CH0 RK0
3930 23:19:01.884223 [ModeRegInit_LP4] CH0 RK1
3931 23:19:01.887429 [ModeRegInit_LP4] CH1 RK0
3932 23:19:01.891086 [ModeRegInit_LP4] CH1 RK1
3933 23:19:01.891662 match AC timing 17
3934 23:19:01.897017 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3935 23:19:01.900815 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3936 23:19:01.904008 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3937 23:19:01.910426 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3938 23:19:01.913957 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3939 23:19:01.914524 ==
3940 23:19:01.917328 Dram Type= 6, Freq= 0, CH_0, rank 0
3941 23:19:01.920090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3942 23:19:01.920557 ==
3943 23:19:01.926644 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3944 23:19:01.933737 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3945 23:19:01.936541 [CA 0] Center 36 (6~66) winsize 61
3946 23:19:01.939873 [CA 1] Center 36 (6~66) winsize 61
3947 23:19:01.943757 [CA 2] Center 34 (4~64) winsize 61
3948 23:19:01.946230 [CA 3] Center 34 (4~65) winsize 62
3949 23:19:01.949635 [CA 4] Center 33 (3~64) winsize 62
3950 23:19:01.954020 [CA 5] Center 33 (3~64) winsize 62
3951 23:19:01.954593
3952 23:19:01.956353 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3953 23:19:01.956962
3954 23:19:01.960153 [CATrainingPosCal] consider 1 rank data
3955 23:19:01.963620 u2DelayCellTimex100 = 270/100 ps
3956 23:19:01.966353 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3957 23:19:01.969572 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3958 23:19:01.973348 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3959 23:19:01.979917 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3960 23:19:01.983595 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3961 23:19:01.986331 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3962 23:19:01.986955
3963 23:19:01.990546 CA PerBit enable=1, Macro0, CA PI delay=33
3964 23:19:01.991101
3965 23:19:01.993439 [CBTSetCACLKResult] CA Dly = 33
3966 23:19:01.993907 CS Dly: 6 (0~37)
3967 23:19:01.994273 ==
3968 23:19:01.996649 Dram Type= 6, Freq= 0, CH_0, rank 1
3969 23:19:02.002875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 23:19:02.003432 ==
3971 23:19:02.006492 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3972 23:19:02.012893 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3973 23:19:02.016151 [CA 0] Center 36 (6~66) winsize 61
3974 23:19:02.019538 [CA 1] Center 36 (6~66) winsize 61
3975 23:19:02.023245 [CA 2] Center 34 (4~65) winsize 62
3976 23:19:02.026106 [CA 3] Center 33 (3~64) winsize 62
3977 23:19:02.029405 [CA 4] Center 33 (2~64) winsize 63
3978 23:19:02.032346 [CA 5] Center 33 (2~64) winsize 63
3979 23:19:02.033020
3980 23:19:02.036182 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3981 23:19:02.036737
3982 23:19:02.038924 [CATrainingPosCal] consider 2 rank data
3983 23:19:02.042388 u2DelayCellTimex100 = 270/100 ps
3984 23:19:02.046037 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3985 23:19:02.052501 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3986 23:19:02.055783 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3987 23:19:02.058780 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3988 23:19:02.062692 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3989 23:19:02.065546 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3990 23:19:02.066009
3991 23:19:02.069252 CA PerBit enable=1, Macro0, CA PI delay=33
3992 23:19:02.069742
3993 23:19:02.072186 [CBTSetCACLKResult] CA Dly = 33
3994 23:19:02.075477 CS Dly: 6 (0~37)
3995 23:19:02.076092
3996 23:19:02.079037 ----->DramcWriteLeveling(PI) begin...
3997 23:19:02.079598 ==
3998 23:19:02.082480 Dram Type= 6, Freq= 0, CH_0, rank 0
3999 23:19:02.085629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 23:19:02.086096 ==
4001 23:19:02.089036 Write leveling (Byte 0): 32 => 32
4002 23:19:02.092439 Write leveling (Byte 1): 31 => 31
4003 23:19:02.095135 DramcWriteLeveling(PI) end<-----
4004 23:19:02.095612
4005 23:19:02.096025 ==
4006 23:19:02.098988 Dram Type= 6, Freq= 0, CH_0, rank 0
4007 23:19:02.101892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 23:19:02.102357 ==
4009 23:19:02.105390 [Gating] SW mode calibration
4010 23:19:02.113092 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4011 23:19:02.119647 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4012 23:19:02.122355 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4013 23:19:02.125444 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 23:19:02.131524 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4015 23:19:02.135106 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4016 23:19:02.138409 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
4017 23:19:02.145252 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 23:19:02.148008 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 23:19:02.151791 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 23:19:02.157909 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 23:19:02.162018 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 23:19:02.164873 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 23:19:02.171771 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4024 23:19:02.174536 0 10 16 | B1->B0 | 3636 4242 | 1 0 | (0 0) (0 0)
4025 23:19:02.178341 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 23:19:02.184355 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 23:19:02.188405 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 23:19:02.191406 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 23:19:02.198049 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 23:19:02.200824 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 23:19:02.204181 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 23:19:02.211719 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4033 23:19:02.214803 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 23:19:02.218078 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 23:19:02.224935 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 23:19:02.228102 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 23:19:02.231096 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 23:19:02.237876 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 23:19:02.241628 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 23:19:02.244462 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 23:19:02.250880 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 23:19:02.254115 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 23:19:02.258294 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 23:19:02.264408 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 23:19:02.267103 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 23:19:02.270882 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 23:19:02.277563 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4048 23:19:02.280892 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4049 23:19:02.283820 Total UI for P1: 0, mck2ui 16
4050 23:19:02.287255 best dqsien dly found for B0: ( 0, 13, 12)
4051 23:19:02.290896 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 23:19:02.293906 Total UI for P1: 0, mck2ui 16
4053 23:19:02.297249 best dqsien dly found for B1: ( 0, 13, 16)
4054 23:19:02.300010 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4055 23:19:02.303317 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4056 23:19:02.303852
4057 23:19:02.310661 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4058 23:19:02.313375 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4059 23:19:02.313933 [Gating] SW calibration Done
4060 23:19:02.316766 ==
4061 23:19:02.319937 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 23:19:02.323628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 23:19:02.324239 ==
4064 23:19:02.324612 RX Vref Scan: 0
4065 23:19:02.324957
4066 23:19:02.326297 RX Vref 0 -> 0, step: 1
4067 23:19:02.326759
4068 23:19:02.329726 RX Delay -230 -> 252, step: 16
4069 23:19:02.333006 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4070 23:19:02.336451 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4071 23:19:02.343511 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4072 23:19:02.346215 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4073 23:19:02.349669 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4074 23:19:02.352763 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4075 23:19:02.359618 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4076 23:19:02.363251 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4077 23:19:02.366047 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4078 23:19:02.370018 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4079 23:19:02.372957 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4080 23:19:02.380325 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4081 23:19:02.383306 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4082 23:19:02.385975 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4083 23:19:02.392758 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4084 23:19:02.396023 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4085 23:19:02.396445 ==
4086 23:19:02.398908 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 23:19:02.402669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 23:19:02.403090 ==
4089 23:19:02.405780 DQS Delay:
4090 23:19:02.406201 DQS0 = 0, DQS1 = 0
4091 23:19:02.406532 DQM Delay:
4092 23:19:02.408964 DQM0 = 44, DQM1 = 31
4093 23:19:02.409380 DQ Delay:
4094 23:19:02.412239 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =41
4095 23:19:02.415976 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4096 23:19:02.418679 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4097 23:19:02.422272 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4098 23:19:02.422691
4099 23:19:02.423020
4100 23:19:02.423328 ==
4101 23:19:02.425546 Dram Type= 6, Freq= 0, CH_0, rank 0
4102 23:19:02.432134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4103 23:19:02.432551 ==
4104 23:19:02.432882
4105 23:19:02.433186
4106 23:19:02.433481 TX Vref Scan disable
4107 23:19:02.435954 == TX Byte 0 ==
4108 23:19:02.438958 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4109 23:19:02.445313 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4110 23:19:02.445739 == TX Byte 1 ==
4111 23:19:02.448465 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4112 23:19:02.456476 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4113 23:19:02.456908 ==
4114 23:19:02.459063 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 23:19:02.461965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 23:19:02.462542 ==
4117 23:19:02.463061
4118 23:19:02.463379
4119 23:19:02.465657 TX Vref Scan disable
4120 23:19:02.468797 == TX Byte 0 ==
4121 23:19:02.472187 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4122 23:19:02.474939 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4123 23:19:02.478958 == TX Byte 1 ==
4124 23:19:02.482262 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4125 23:19:02.485531 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4126 23:19:02.485951
4127 23:19:02.486280 [DATLAT]
4128 23:19:02.488376 Freq=600, CH0 RK0
4129 23:19:02.488794
4130 23:19:02.492034 DATLAT Default: 0x9
4131 23:19:02.492450 0, 0xFFFF, sum = 0
4132 23:19:02.495778 1, 0xFFFF, sum = 0
4133 23:19:02.496203 2, 0xFFFF, sum = 0
4134 23:19:02.498307 3, 0xFFFF, sum = 0
4135 23:19:02.498728 4, 0xFFFF, sum = 0
4136 23:19:02.501760 5, 0xFFFF, sum = 0
4137 23:19:02.502203 6, 0xFFFF, sum = 0
4138 23:19:02.504435 7, 0xFFFF, sum = 0
4139 23:19:02.504955 8, 0x0, sum = 1
4140 23:19:02.508914 9, 0x0, sum = 2
4141 23:19:02.509428 10, 0x0, sum = 3
4142 23:19:02.511526 11, 0x0, sum = 4
4143 23:19:02.511995 best_step = 9
4144 23:19:02.512337
4145 23:19:02.512699 ==
4146 23:19:02.514901 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 23:19:02.518080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 23:19:02.518504 ==
4149 23:19:02.521596 RX Vref Scan: 1
4150 23:19:02.522104
4151 23:19:02.524939 RX Vref 0 -> 0, step: 1
4152 23:19:02.525358
4153 23:19:02.525705 RX Delay -195 -> 252, step: 8
4154 23:19:02.528352
4155 23:19:02.528861 Set Vref, RX VrefLevel [Byte0]: 56
4156 23:19:02.531599 [Byte1]: 57
4157 23:19:02.536181
4158 23:19:02.536775 Final RX Vref Byte 0 = 56 to rank0
4159 23:19:02.539137 Final RX Vref Byte 1 = 57 to rank0
4160 23:19:02.542850 Final RX Vref Byte 0 = 56 to rank1
4161 23:19:02.546305 Final RX Vref Byte 1 = 57 to rank1==
4162 23:19:02.549375 Dram Type= 6, Freq= 0, CH_0, rank 0
4163 23:19:02.557254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 23:19:02.557852 ==
4165 23:19:02.558255 DQS Delay:
4166 23:19:02.559065 DQS0 = 0, DQS1 = 0
4167 23:19:02.559754 DQM Delay:
4168 23:19:02.560370 DQM0 = 44, DQM1 = 32
4169 23:19:02.562488 DQ Delay:
4170 23:19:02.565503 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4171 23:19:02.568876 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4172 23:19:02.571983 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4173 23:19:02.575833 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4174 23:19:02.576397
4175 23:19:02.576771
4176 23:19:02.582381 [DQSOSCAuto] RK0, (LSB)MR18= 0x633b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4177 23:19:02.585243 CH0 RK0: MR19=808, MR18=633B
4178 23:19:02.592557 CH0_RK0: MR19=0x808, MR18=0x633B, DQSOSC=391, MR23=63, INC=171, DEC=114
4179 23:19:02.593114
4180 23:19:02.595391 ----->DramcWriteLeveling(PI) begin...
4181 23:19:02.595992 ==
4182 23:19:02.598840 Dram Type= 6, Freq= 0, CH_0, rank 1
4183 23:19:02.602117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 23:19:02.602677 ==
4185 23:19:02.605404 Write leveling (Byte 0): 33 => 33
4186 23:19:02.608550 Write leveling (Byte 1): 35 => 35
4187 23:19:02.612656 DramcWriteLeveling(PI) end<-----
4188 23:19:02.613212
4189 23:19:02.613578 ==
4190 23:19:02.614760 Dram Type= 6, Freq= 0, CH_0, rank 1
4191 23:19:02.621777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 23:19:02.622336 ==
4193 23:19:02.622707 [Gating] SW mode calibration
4194 23:19:02.632344 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4195 23:19:02.635031 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4196 23:19:02.638930 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4197 23:19:02.644600 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4198 23:19:02.647823 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4199 23:19:02.651815 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4200 23:19:02.658100 0 9 16 | B1->B0 | 2e2e 2727 | 0 0 | (1 1) (1 1)
4201 23:19:02.661140 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 23:19:02.664168 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 23:19:02.670679 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 23:19:02.674200 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 23:19:02.678378 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 23:19:02.684522 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 23:19:02.688186 0 10 12 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
4208 23:19:02.691062 0 10 16 | B1->B0 | 3838 4141 | 0 0 | (0 0) (0 0)
4209 23:19:02.697618 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 23:19:02.701282 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 23:19:02.704534 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 23:19:02.710970 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 23:19:02.714403 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 23:19:02.717579 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 23:19:02.724074 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4216 23:19:02.727181 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4217 23:19:02.730887 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 23:19:02.736972 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 23:19:02.740362 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 23:19:02.744146 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 23:19:02.750931 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 23:19:02.753877 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 23:19:02.756855 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 23:19:02.764149 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 23:19:02.767311 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 23:19:02.770253 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 23:19:02.777593 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 23:19:02.780753 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 23:19:02.784066 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 23:19:02.790103 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 23:19:02.793420 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4232 23:19:02.796505 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4233 23:19:02.800586 Total UI for P1: 0, mck2ui 16
4234 23:19:02.803092 best dqsien dly found for B0: ( 0, 13, 12)
4235 23:19:02.809375 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 23:19:02.809824 Total UI for P1: 0, mck2ui 16
4237 23:19:02.816291 best dqsien dly found for B1: ( 0, 13, 14)
4238 23:19:02.819288 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4239 23:19:02.823266 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4240 23:19:02.823723
4241 23:19:02.826294 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4242 23:19:02.829323 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4243 23:19:02.832658 [Gating] SW calibration Done
4244 23:19:02.833077 ==
4245 23:19:02.836265 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 23:19:02.839563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 23:19:02.840049 ==
4248 23:19:02.843245 RX Vref Scan: 0
4249 23:19:02.843635
4250 23:19:02.845915 RX Vref 0 -> 0, step: 1
4251 23:19:02.846271
4252 23:19:02.846592 RX Delay -230 -> 252, step: 16
4253 23:19:02.852462 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4254 23:19:02.856265 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4255 23:19:02.859241 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4256 23:19:02.862052 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4257 23:19:02.869207 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4258 23:19:02.872511 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4259 23:19:02.875738 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4260 23:19:02.878773 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4261 23:19:02.885513 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4262 23:19:02.888779 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4263 23:19:02.892213 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4264 23:19:02.895115 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4265 23:19:02.902167 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4266 23:19:02.905151 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4267 23:19:02.908468 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4268 23:19:02.912316 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4269 23:19:02.912736 ==
4270 23:19:02.915614 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 23:19:02.921580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 23:19:02.922001 ==
4273 23:19:02.922331 DQS Delay:
4274 23:19:02.925534 DQS0 = 0, DQS1 = 0
4275 23:19:02.925948 DQM Delay:
4276 23:19:02.926276 DQM0 = 43, DQM1 = 35
4277 23:19:02.928323 DQ Delay:
4278 23:19:02.931516 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4279 23:19:02.935198 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4280 23:19:02.938892 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4281 23:19:02.941769 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4282 23:19:02.942184
4283 23:19:02.942512
4284 23:19:02.942814 ==
4285 23:19:02.944778 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 23:19:02.949057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 23:19:02.949574 ==
4288 23:19:02.949908
4289 23:19:02.950211
4290 23:19:02.952062 TX Vref Scan disable
4291 23:19:02.954895 == TX Byte 0 ==
4292 23:19:02.957920 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4293 23:19:02.961428 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4294 23:19:02.964993 == TX Byte 1 ==
4295 23:19:02.967867 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4296 23:19:02.971515 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4297 23:19:02.971982 ==
4298 23:19:02.975569 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 23:19:02.977767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 23:19:02.981231 ==
4301 23:19:02.981647
4302 23:19:02.981978
4303 23:19:02.982286 TX Vref Scan disable
4304 23:19:02.985230 == TX Byte 0 ==
4305 23:19:02.988404 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4306 23:19:02.995609 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4307 23:19:02.996095 == TX Byte 1 ==
4308 23:19:02.998627 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4309 23:19:03.004503 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4310 23:19:03.004920
4311 23:19:03.005246 [DATLAT]
4312 23:19:03.005550 Freq=600, CH0 RK1
4313 23:19:03.005920
4314 23:19:03.008211 DATLAT Default: 0x9
4315 23:19:03.011387 0, 0xFFFF, sum = 0
4316 23:19:03.011857 1, 0xFFFF, sum = 0
4317 23:19:03.014560 2, 0xFFFF, sum = 0
4318 23:19:03.014983 3, 0xFFFF, sum = 0
4319 23:19:03.018001 4, 0xFFFF, sum = 0
4320 23:19:03.018428 5, 0xFFFF, sum = 0
4321 23:19:03.021430 6, 0xFFFF, sum = 0
4322 23:19:03.021856 7, 0xFFFF, sum = 0
4323 23:19:03.024956 8, 0x0, sum = 1
4324 23:19:03.025482 9, 0x0, sum = 2
4325 23:19:03.028120 10, 0x0, sum = 3
4326 23:19:03.028546 11, 0x0, sum = 4
4327 23:19:03.028882 best_step = 9
4328 23:19:03.029186
4329 23:19:03.031086 ==
4330 23:19:03.034261 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 23:19:03.038124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 23:19:03.038669 ==
4333 23:19:03.039005 RX Vref Scan: 0
4334 23:19:03.039313
4335 23:19:03.041148 RX Vref 0 -> 0, step: 1
4336 23:19:03.041575
4337 23:19:03.045034 RX Delay -195 -> 252, step: 8
4338 23:19:03.051449 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4339 23:19:03.055582 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4340 23:19:03.058214 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4341 23:19:03.061238 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4342 23:19:03.064407 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4343 23:19:03.071372 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4344 23:19:03.074052 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4345 23:19:03.077683 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4346 23:19:03.081073 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4347 23:19:03.087386 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4348 23:19:03.091039 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4349 23:19:03.094012 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4350 23:19:03.097092 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4351 23:19:03.104018 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4352 23:19:03.107169 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4353 23:19:03.110919 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4354 23:19:03.111437 ==
4355 23:19:03.114213 Dram Type= 6, Freq= 0, CH_0, rank 1
4356 23:19:03.117019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 23:19:03.120900 ==
4358 23:19:03.121440 DQS Delay:
4359 23:19:03.121772 DQS0 = 0, DQS1 = 0
4360 23:19:03.123568 DQM Delay:
4361 23:19:03.124132 DQM0 = 42, DQM1 = 35
4362 23:19:03.126929 DQ Delay:
4363 23:19:03.130417 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4364 23:19:03.130942 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4365 23:19:03.133158 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4366 23:19:03.140253 DQ12 =40, DQ13 =44, DQ14 =44, DQ15 =40
4367 23:19:03.140741
4368 23:19:03.141075
4369 23:19:03.146240 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f12, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4370 23:19:03.149487 CH0 RK1: MR19=808, MR18=5F12
4371 23:19:03.156128 CH0_RK1: MR19=0x808, MR18=0x5F12, DQSOSC=391, MR23=63, INC=171, DEC=114
4372 23:19:03.159582 [RxdqsGatingPostProcess] freq 600
4373 23:19:03.162468 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4374 23:19:03.166085 Pre-setting of DQS Precalculation
4375 23:19:03.172526 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4376 23:19:03.173089 ==
4377 23:19:03.176042 Dram Type= 6, Freq= 0, CH_1, rank 0
4378 23:19:03.179829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 23:19:03.180258 ==
4380 23:19:03.185914 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4381 23:19:03.192985 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4382 23:19:03.196091 [CA 0] Center 35 (5~66) winsize 62
4383 23:19:03.199137 [CA 1] Center 35 (5~66) winsize 62
4384 23:19:03.201799 [CA 2] Center 34 (4~65) winsize 62
4385 23:19:03.205800 [CA 3] Center 33 (3~64) winsize 62
4386 23:19:03.208737 [CA 4] Center 34 (4~65) winsize 62
4387 23:19:03.211743 [CA 5] Center 33 (3~64) winsize 62
4388 23:19:03.212166
4389 23:19:03.215524 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4390 23:19:03.216297
4391 23:19:03.218429 [CATrainingPosCal] consider 1 rank data
4392 23:19:03.222072 u2DelayCellTimex100 = 270/100 ps
4393 23:19:03.225318 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4394 23:19:03.228510 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4395 23:19:03.231771 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4396 23:19:03.234753 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4397 23:19:03.238479 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4398 23:19:03.241603 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4399 23:19:03.244694
4400 23:19:03.248185 CA PerBit enable=1, Macro0, CA PI delay=33
4401 23:19:03.248488
4402 23:19:03.251433 [CBTSetCACLKResult] CA Dly = 33
4403 23:19:03.251807 CS Dly: 4 (0~35)
4404 23:19:03.252127 ==
4405 23:19:03.254716 Dram Type= 6, Freq= 0, CH_1, rank 1
4406 23:19:03.257888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 23:19:03.258118 ==
4408 23:19:03.264610 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4409 23:19:03.270944 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4410 23:19:03.275087 [CA 0] Center 35 (5~66) winsize 62
4411 23:19:03.278571 [CA 1] Center 36 (6~66) winsize 61
4412 23:19:03.281566 [CA 2] Center 34 (4~65) winsize 62
4413 23:19:03.284226 [CA 3] Center 34 (3~65) winsize 63
4414 23:19:03.287916 [CA 4] Center 34 (4~65) winsize 62
4415 23:19:03.290800 [CA 5] Center 34 (3~65) winsize 63
4416 23:19:03.291089
4417 23:19:03.294421 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4418 23:19:03.294649
4419 23:19:03.297262 [CATrainingPosCal] consider 2 rank data
4420 23:19:03.301061 u2DelayCellTimex100 = 270/100 ps
4421 23:19:03.304381 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4422 23:19:03.307265 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4423 23:19:03.310839 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4424 23:19:03.317177 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4425 23:19:03.320390 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4426 23:19:03.323748 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4427 23:19:03.323978
4428 23:19:03.326909 CA PerBit enable=1, Macro0, CA PI delay=33
4429 23:19:03.327136
4430 23:19:03.330364 [CBTSetCACLKResult] CA Dly = 33
4431 23:19:03.330641 CS Dly: 4 (0~36)
4432 23:19:03.330826
4433 23:19:03.333727 ----->DramcWriteLeveling(PI) begin...
4434 23:19:03.337052 ==
4435 23:19:03.337275 Dram Type= 6, Freq= 0, CH_1, rank 0
4436 23:19:03.343693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 23:19:03.344017 ==
4438 23:19:03.347089 Write leveling (Byte 0): 30 => 30
4439 23:19:03.350517 Write leveling (Byte 1): 30 => 30
4440 23:19:03.353457 DramcWriteLeveling(PI) end<-----
4441 23:19:03.353843
4442 23:19:03.354125 ==
4443 23:19:03.357100 Dram Type= 6, Freq= 0, CH_1, rank 0
4444 23:19:03.360247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4445 23:19:03.360605 ==
4446 23:19:03.363334 [Gating] SW mode calibration
4447 23:19:03.369993 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4448 23:19:03.376878 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4449 23:19:03.380085 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4450 23:19:03.384346 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4451 23:19:03.389981 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4452 23:19:03.393206 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
4453 23:19:03.396932 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4454 23:19:03.403048 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 23:19:03.406387 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 23:19:03.409476 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 23:19:03.416674 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 23:19:03.420222 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 23:19:03.423177 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 23:19:03.429623 0 10 12 | B1->B0 | 3232 3636 | 0 0 | (0 0) (0 0)
4461 23:19:03.432951 0 10 16 | B1->B0 | 4443 4646 | 1 0 | (0 0) (0 0)
4462 23:19:03.436496 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 23:19:03.443182 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 23:19:03.446123 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 23:19:03.449582 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 23:19:03.456093 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 23:19:03.459399 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 23:19:03.462628 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4469 23:19:03.469527 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 23:19:03.472171 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 23:19:03.475573 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 23:19:03.482257 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 23:19:03.485484 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 23:19:03.489189 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 23:19:03.496042 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 23:19:03.498474 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 23:19:03.502250 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 23:19:03.508544 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 23:19:03.511572 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 23:19:03.514937 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 23:19:03.521757 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 23:19:03.525251 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 23:19:03.528343 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4484 23:19:03.535288 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4485 23:19:03.538037 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 23:19:03.541667 Total UI for P1: 0, mck2ui 16
4487 23:19:03.544668 best dqsien dly found for B0: ( 0, 13, 10)
4488 23:19:03.547939 Total UI for P1: 0, mck2ui 16
4489 23:19:03.551404 best dqsien dly found for B1: ( 0, 13, 12)
4490 23:19:03.554623 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4491 23:19:03.557894 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4492 23:19:03.558353
4493 23:19:03.561775 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4494 23:19:03.565137 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4495 23:19:03.568393 [Gating] SW calibration Done
4496 23:19:03.568836 ==
4497 23:19:03.571397 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 23:19:03.574392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 23:19:03.578063 ==
4500 23:19:03.578483 RX Vref Scan: 0
4501 23:19:03.578816
4502 23:19:03.580930 RX Vref 0 -> 0, step: 1
4503 23:19:03.581348
4504 23:19:03.584475 RX Delay -230 -> 252, step: 16
4505 23:19:03.588423 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4506 23:19:03.591541 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4507 23:19:03.594309 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4508 23:19:03.601063 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4509 23:19:03.604306 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4510 23:19:03.607775 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4511 23:19:03.610936 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4512 23:19:03.617399 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4513 23:19:03.620762 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4514 23:19:03.624455 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4515 23:19:03.627498 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4516 23:19:03.634285 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4517 23:19:03.637023 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4518 23:19:03.640946 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4519 23:19:03.644345 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4520 23:19:03.650359 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4521 23:19:03.650890 ==
4522 23:19:03.654300 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 23:19:03.657042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 23:19:03.657464 ==
4525 23:19:03.657795 DQS Delay:
4526 23:19:03.660135 DQS0 = 0, DQS1 = 0
4527 23:19:03.660651 DQM Delay:
4528 23:19:03.663850 DQM0 = 47, DQM1 = 40
4529 23:19:03.664271 DQ Delay:
4530 23:19:03.666184 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4531 23:19:03.669641 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4532 23:19:03.673156 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =25
4533 23:19:03.676070 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4534 23:19:03.676484
4535 23:19:03.676813
4536 23:19:03.677122 ==
4537 23:19:03.679391 Dram Type= 6, Freq= 0, CH_1, rank 0
4538 23:19:03.683491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4539 23:19:03.684067 ==
4540 23:19:03.686096
4541 23:19:03.686549
4542 23:19:03.686909 TX Vref Scan disable
4543 23:19:03.689781 == TX Byte 0 ==
4544 23:19:03.693191 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4545 23:19:03.696181 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4546 23:19:03.699885 == TX Byte 1 ==
4547 23:19:03.703330 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4548 23:19:03.707070 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4549 23:19:03.709972 ==
4550 23:19:03.712835 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 23:19:03.716363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 23:19:03.716928 ==
4553 23:19:03.717299
4554 23:19:03.717641
4555 23:19:03.719307 TX Vref Scan disable
4556 23:19:03.719814 == TX Byte 0 ==
4557 23:19:03.725737 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4558 23:19:03.729478 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4559 23:19:03.730045 == TX Byte 1 ==
4560 23:19:03.736192 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4561 23:19:03.739740 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4562 23:19:03.740220
4563 23:19:03.740588 [DATLAT]
4564 23:19:03.742347 Freq=600, CH1 RK0
4565 23:19:03.742809
4566 23:19:03.743218 DATLAT Default: 0x9
4567 23:19:03.745593 0, 0xFFFF, sum = 0
4568 23:19:03.746096 1, 0xFFFF, sum = 0
4569 23:19:03.749181 2, 0xFFFF, sum = 0
4570 23:19:03.752877 3, 0xFFFF, sum = 0
4571 23:19:03.753307 4, 0xFFFF, sum = 0
4572 23:19:03.755785 5, 0xFFFF, sum = 0
4573 23:19:03.756213 6, 0xFFFF, sum = 0
4574 23:19:03.759197 7, 0xFFFF, sum = 0
4575 23:19:03.759788 8, 0x0, sum = 1
4576 23:19:03.760145 9, 0x0, sum = 2
4577 23:19:03.762370 10, 0x0, sum = 3
4578 23:19:03.762799 11, 0x0, sum = 4
4579 23:19:03.765388 best_step = 9
4580 23:19:03.766035
4581 23:19:03.766576 ==
4582 23:19:03.768563 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 23:19:03.772022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 23:19:03.772450 ==
4585 23:19:03.775338 RX Vref Scan: 1
4586 23:19:03.775757
4587 23:19:03.776113 RX Vref 0 -> 0, step: 1
4588 23:19:03.776486
4589 23:19:03.778942 RX Delay -179 -> 252, step: 8
4590 23:19:03.779455
4591 23:19:03.781802 Set Vref, RX VrefLevel [Byte0]: 46
4592 23:19:03.785534 [Byte1]: 60
4593 23:19:03.790003
4594 23:19:03.790607 Final RX Vref Byte 0 = 46 to rank0
4595 23:19:03.793172 Final RX Vref Byte 1 = 60 to rank0
4596 23:19:03.796802 Final RX Vref Byte 0 = 46 to rank1
4597 23:19:03.799729 Final RX Vref Byte 1 = 60 to rank1==
4598 23:19:03.803199 Dram Type= 6, Freq= 0, CH_1, rank 0
4599 23:19:03.810478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 23:19:03.810899 ==
4601 23:19:03.811229 DQS Delay:
4602 23:19:03.812663 DQS0 = 0, DQS1 = 0
4603 23:19:03.813107 DQM Delay:
4604 23:19:03.813563 DQM0 = 47, DQM1 = 37
4605 23:19:03.816172 DQ Delay:
4606 23:19:03.819131 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =44
4607 23:19:03.822430 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =40
4608 23:19:03.825779 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4609 23:19:03.829433 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4610 23:19:03.829851
4611 23:19:03.830177
4612 23:19:03.835656 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b31, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4613 23:19:03.838935 CH1 RK0: MR19=808, MR18=4B31
4614 23:19:03.845514 CH1_RK0: MR19=0x808, MR18=0x4B31, DQSOSC=395, MR23=63, INC=168, DEC=112
4615 23:19:03.845933
4616 23:19:03.849579 ----->DramcWriteLeveling(PI) begin...
4617 23:19:03.850001 ==
4618 23:19:03.852619 Dram Type= 6, Freq= 0, CH_1, rank 1
4619 23:19:03.855652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 23:19:03.856099 ==
4621 23:19:03.858601 Write leveling (Byte 0): 28 => 28
4622 23:19:03.862240 Write leveling (Byte 1): 31 => 31
4623 23:19:03.865211 DramcWriteLeveling(PI) end<-----
4624 23:19:03.865631
4625 23:19:03.865958 ==
4626 23:19:03.868633 Dram Type= 6, Freq= 0, CH_1, rank 1
4627 23:19:03.872156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 23:19:03.875141 ==
4629 23:19:03.875603 [Gating] SW mode calibration
4630 23:19:03.885266 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4631 23:19:03.888748 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4632 23:19:03.892655 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4633 23:19:03.898877 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4634 23:19:03.901625 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4635 23:19:03.905208 0 9 12 | B1->B0 | 3030 3232 | 0 0 | (1 0) (0 0)
4636 23:19:03.911821 0 9 16 | B1->B0 | 2424 2a2a | 0 1 | (0 0) (1 0)
4637 23:19:03.915294 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 23:19:03.918713 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 23:19:03.924811 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 23:19:03.927859 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 23:19:03.932119 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 23:19:03.938436 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 23:19:03.941576 0 10 12 | B1->B0 | 3636 2a2a | 0 0 | (1 1) (0 0)
4644 23:19:03.944629 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4645 23:19:03.951142 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 23:19:03.954126 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 23:19:03.957714 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 23:19:03.964719 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 23:19:03.967489 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 23:19:03.971324 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 23:19:03.977872 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4652 23:19:03.980736 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 23:19:03.984229 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 23:19:03.990535 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 23:19:03.993854 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 23:19:03.997377 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 23:19:04.004058 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 23:19:04.007163 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 23:19:04.010433 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 23:19:04.017351 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 23:19:04.020499 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 23:19:04.023611 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 23:19:04.029882 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 23:19:04.033884 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 23:19:04.036852 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 23:19:04.043123 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 23:19:04.047081 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4668 23:19:04.049773 Total UI for P1: 0, mck2ui 16
4669 23:19:04.053072 best dqsien dly found for B1: ( 0, 13, 10)
4670 23:19:04.056580 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4671 23:19:04.063186 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 23:19:04.063660 Total UI for P1: 0, mck2ui 16
4673 23:19:04.069823 best dqsien dly found for B0: ( 0, 13, 14)
4674 23:19:04.073661 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4675 23:19:04.076946 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4676 23:19:04.077367
4677 23:19:04.079997 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4678 23:19:04.082682 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4679 23:19:04.087052 [Gating] SW calibration Done
4680 23:19:04.087470 ==
4681 23:19:04.090250 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 23:19:04.092932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 23:19:04.093412 ==
4684 23:19:04.096225 RX Vref Scan: 0
4685 23:19:04.096659
4686 23:19:04.099430 RX Vref 0 -> 0, step: 1
4687 23:19:04.100003
4688 23:19:04.100532 RX Delay -230 -> 252, step: 16
4689 23:19:04.106025 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4690 23:19:04.109431 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4691 23:19:04.113569 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4692 23:19:04.116104 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4693 23:19:04.123106 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4694 23:19:04.125560 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4695 23:19:04.129372 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4696 23:19:04.132372 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4697 23:19:04.139914 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4698 23:19:04.142663 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4699 23:19:04.145414 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4700 23:19:04.149268 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4701 23:19:04.155977 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4702 23:19:04.159233 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4703 23:19:04.162386 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4704 23:19:04.165931 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4705 23:19:04.166350 ==
4706 23:19:04.168458 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 23:19:04.175329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 23:19:04.175880 ==
4709 23:19:04.176220 DQS Delay:
4710 23:19:04.178595 DQS0 = 0, DQS1 = 0
4711 23:19:04.179121 DQM Delay:
4712 23:19:04.179458 DQM0 = 42, DQM1 = 36
4713 23:19:04.183069 DQ Delay:
4714 23:19:04.185273 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4715 23:19:04.189452 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =33
4716 23:19:04.192119 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4717 23:19:04.195517 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4718 23:19:04.196105
4719 23:19:04.196445
4720 23:19:04.196755 ==
4721 23:19:04.198780 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 23:19:04.201943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 23:19:04.202476 ==
4724 23:19:04.202814
4725 23:19:04.203121
4726 23:19:04.205537 TX Vref Scan disable
4727 23:19:04.208680 == TX Byte 0 ==
4728 23:19:04.212052 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4729 23:19:04.214946 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4730 23:19:04.218564 == TX Byte 1 ==
4731 23:19:04.222872 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4732 23:19:04.225443 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4733 23:19:04.225965 ==
4734 23:19:04.228613 Dram Type= 6, Freq= 0, CH_1, rank 1
4735 23:19:04.231982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4736 23:19:04.235453 ==
4737 23:19:04.236052
4738 23:19:04.236446
4739 23:19:04.236766 TX Vref Scan disable
4740 23:19:04.239020 == TX Byte 0 ==
4741 23:19:04.241843 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4742 23:19:04.249012 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4743 23:19:04.249536 == TX Byte 1 ==
4744 23:19:04.252030 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4745 23:19:04.258601 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4746 23:19:04.259128
4747 23:19:04.259462 [DATLAT]
4748 23:19:04.259917 Freq=600, CH1 RK1
4749 23:19:04.260259
4750 23:19:04.261843 DATLAT Default: 0x9
4751 23:19:04.265669 0, 0xFFFF, sum = 0
4752 23:19:04.266198 1, 0xFFFF, sum = 0
4753 23:19:04.268443 2, 0xFFFF, sum = 0
4754 23:19:04.268874 3, 0xFFFF, sum = 0
4755 23:19:04.271469 4, 0xFFFF, sum = 0
4756 23:19:04.271990 5, 0xFFFF, sum = 0
4757 23:19:04.275338 6, 0xFFFF, sum = 0
4758 23:19:04.275806 7, 0xFFFF, sum = 0
4759 23:19:04.278763 8, 0x0, sum = 1
4760 23:19:04.279189 9, 0x0, sum = 2
4761 23:19:04.281770 10, 0x0, sum = 3
4762 23:19:04.282287 11, 0x0, sum = 4
4763 23:19:04.282668 best_step = 9
4764 23:19:04.283012
4765 23:19:04.284970 ==
4766 23:19:04.287821 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 23:19:04.292175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 23:19:04.292739 ==
4769 23:19:04.293109 RX Vref Scan: 0
4770 23:19:04.293451
4771 23:19:04.295602 RX Vref 0 -> 0, step: 1
4772 23:19:04.296117
4773 23:19:04.298346 RX Delay -195 -> 252, step: 8
4774 23:19:04.304461 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4775 23:19:04.307791 iDelay=205, Bit 1, Center 40 (-107 ~ 188) 296
4776 23:19:04.312039 iDelay=205, Bit 2, Center 32 (-115 ~ 180) 296
4777 23:19:04.314469 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4778 23:19:04.321230 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4779 23:19:04.324351 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4780 23:19:04.328059 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4781 23:19:04.331818 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4782 23:19:04.334385 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4783 23:19:04.340781 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4784 23:19:04.344223 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4785 23:19:04.347552 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4786 23:19:04.350690 iDelay=205, Bit 12, Center 48 (-107 ~ 204) 312
4787 23:19:04.357272 iDelay=205, Bit 13, Center 48 (-107 ~ 204) 312
4788 23:19:04.360302 iDelay=205, Bit 14, Center 48 (-107 ~ 204) 312
4789 23:19:04.364254 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4790 23:19:04.364811 ==
4791 23:19:04.367532 Dram Type= 6, Freq= 0, CH_1, rank 1
4792 23:19:04.370424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4793 23:19:04.373492 ==
4794 23:19:04.374022 DQS Delay:
4795 23:19:04.374517 DQS0 = 0, DQS1 = 0
4796 23:19:04.377028 DQM Delay:
4797 23:19:04.377487 DQM0 = 45, DQM1 = 38
4798 23:19:04.380281 DQ Delay:
4799 23:19:04.380840 DQ0 =52, DQ1 =40, DQ2 =32, DQ3 =40
4800 23:19:04.383733 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4801 23:19:04.387295 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4802 23:19:04.390425 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4803 23:19:04.393801
4804 23:19:04.394358
4805 23:19:04.400384 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4806 23:19:04.403929 CH1 RK1: MR19=808, MR18=2D21
4807 23:19:04.410865 CH1_RK1: MR19=0x808, MR18=0x2D21, DQSOSC=401, MR23=63, INC=163, DEC=108
4808 23:19:04.413678 [RxdqsGatingPostProcess] freq 600
4809 23:19:04.417074 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4810 23:19:04.419981 Pre-setting of DQS Precalculation
4811 23:19:04.426651 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4812 23:19:04.433747 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4813 23:19:04.440331 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4814 23:19:04.440894
4815 23:19:04.441257
4816 23:19:04.444510 [Calibration Summary] 1200 Mbps
4817 23:19:04.445075 CH 0, Rank 0
4818 23:19:04.447276 SW Impedance : PASS
4819 23:19:04.449832 DUTY Scan : NO K
4820 23:19:04.450392 ZQ Calibration : PASS
4821 23:19:04.453148 Jitter Meter : NO K
4822 23:19:04.456317 CBT Training : PASS
4823 23:19:04.456796 Write leveling : PASS
4824 23:19:04.459472 RX DQS gating : PASS
4825 23:19:04.463486 RX DQ/DQS(RDDQC) : PASS
4826 23:19:04.464009 TX DQ/DQS : PASS
4827 23:19:04.466454 RX DATLAT : PASS
4828 23:19:04.469262 RX DQ/DQS(Engine): PASS
4829 23:19:04.469897 TX OE : NO K
4830 23:19:04.470302 All Pass.
4831 23:19:04.472902
4832 23:19:04.473398 CH 0, Rank 1
4833 23:19:04.475907 SW Impedance : PASS
4834 23:19:04.476365 DUTY Scan : NO K
4835 23:19:04.479495 ZQ Calibration : PASS
4836 23:19:04.480003 Jitter Meter : NO K
4837 23:19:04.482395 CBT Training : PASS
4838 23:19:04.485987 Write leveling : PASS
4839 23:19:04.486404 RX DQS gating : PASS
4840 23:19:04.489268 RX DQ/DQS(RDDQC) : PASS
4841 23:19:04.492962 TX DQ/DQS : PASS
4842 23:19:04.493425 RX DATLAT : PASS
4843 23:19:04.495782 RX DQ/DQS(Engine): PASS
4844 23:19:04.499264 TX OE : NO K
4845 23:19:04.499851 All Pass.
4846 23:19:04.500197
4847 23:19:04.500505 CH 1, Rank 0
4848 23:19:04.502145 SW Impedance : PASS
4849 23:19:04.506224 DUTY Scan : NO K
4850 23:19:04.506658 ZQ Calibration : PASS
4851 23:19:04.509087 Jitter Meter : NO K
4852 23:19:04.512824 CBT Training : PASS
4853 23:19:04.513247 Write leveling : PASS
4854 23:19:04.515648 RX DQS gating : PASS
4855 23:19:04.519474 RX DQ/DQS(RDDQC) : PASS
4856 23:19:04.519944 TX DQ/DQS : PASS
4857 23:19:04.522301 RX DATLAT : PASS
4858 23:19:04.525726 RX DQ/DQS(Engine): PASS
4859 23:19:04.526153 TX OE : NO K
4860 23:19:04.528756 All Pass.
4861 23:19:04.529233
4862 23:19:04.529569 CH 1, Rank 1
4863 23:19:04.532419 SW Impedance : PASS
4864 23:19:04.532747 DUTY Scan : NO K
4865 23:19:04.535036 ZQ Calibration : PASS
4866 23:19:04.539011 Jitter Meter : NO K
4867 23:19:04.539412 CBT Training : PASS
4868 23:19:04.542148 Write leveling : PASS
4869 23:19:04.545403 RX DQS gating : PASS
4870 23:19:04.545607 RX DQ/DQS(RDDQC) : PASS
4871 23:19:04.548764 TX DQ/DQS : PASS
4872 23:19:04.548845 RX DATLAT : PASS
4873 23:19:04.551377 RX DQ/DQS(Engine): PASS
4874 23:19:04.554983 TX OE : NO K
4875 23:19:04.555064 All Pass.
4876 23:19:04.555128
4877 23:19:04.558339 DramC Write-DBI off
4878 23:19:04.558420 PER_BANK_REFRESH: Hybrid Mode
4879 23:19:04.561789 TX_TRACKING: ON
4880 23:19:04.571500 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4881 23:19:04.575230 [FAST_K] Save calibration result to emmc
4882 23:19:04.578642 dramc_set_vcore_voltage set vcore to 662500
4883 23:19:04.581129 Read voltage for 933, 3
4884 23:19:04.581210 Vio18 = 0
4885 23:19:04.581274 Vcore = 662500
4886 23:19:04.581335 Vdram = 0
4887 23:19:04.584682 Vddq = 0
4888 23:19:04.584762 Vmddr = 0
4889 23:19:04.590945 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4890 23:19:04.594882 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4891 23:19:04.597716 MEM_TYPE=3, freq_sel=17
4892 23:19:04.600882 sv_algorithm_assistance_LP4_1600
4893 23:19:04.605108 ============ PULL DRAM RESETB DOWN ============
4894 23:19:04.607546 ========== PULL DRAM RESETB DOWN end =========
4895 23:19:04.615147 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4896 23:19:04.617491 ===================================
4897 23:19:04.617615 LPDDR4 DRAM CONFIGURATION
4898 23:19:04.620969 ===================================
4899 23:19:04.624391 EX_ROW_EN[0] = 0x0
4900 23:19:04.627358 EX_ROW_EN[1] = 0x0
4901 23:19:04.627511 LP4Y_EN = 0x0
4902 23:19:04.631027 WORK_FSP = 0x0
4903 23:19:04.631178 WL = 0x3
4904 23:19:04.634429 RL = 0x3
4905 23:19:04.634612 BL = 0x2
4906 23:19:04.637963 RPST = 0x0
4907 23:19:04.638164 RD_PRE = 0x0
4908 23:19:04.640651 WR_PRE = 0x1
4909 23:19:04.640911 WR_PST = 0x0
4910 23:19:04.643821 DBI_WR = 0x0
4911 23:19:04.644064 DBI_RD = 0x0
4912 23:19:04.647532 OTF = 0x1
4913 23:19:04.650591 ===================================
4914 23:19:04.654611 ===================================
4915 23:19:04.655046 ANA top config
4916 23:19:04.657561 ===================================
4917 23:19:04.661103 DLL_ASYNC_EN = 0
4918 23:19:04.664066 ALL_SLAVE_EN = 1
4919 23:19:04.667177 NEW_RANK_MODE = 1
4920 23:19:04.667563 DLL_IDLE_MODE = 1
4921 23:19:04.670529 LP45_APHY_COMB_EN = 1
4922 23:19:04.673772 TX_ODT_DIS = 1
4923 23:19:04.676858 NEW_8X_MODE = 1
4924 23:19:04.680418 ===================================
4925 23:19:04.683977 ===================================
4926 23:19:04.687082 data_rate = 1866
4927 23:19:04.690538 CKR = 1
4928 23:19:04.690930 DQ_P2S_RATIO = 8
4929 23:19:04.694052 ===================================
4930 23:19:04.696730 CA_P2S_RATIO = 8
4931 23:19:04.699871 DQ_CA_OPEN = 0
4932 23:19:04.703407 DQ_SEMI_OPEN = 0
4933 23:19:04.706870 CA_SEMI_OPEN = 0
4934 23:19:04.709800 CA_FULL_RATE = 0
4935 23:19:04.710188 DQ_CKDIV4_EN = 1
4936 23:19:04.713251 CA_CKDIV4_EN = 1
4937 23:19:04.716379 CA_PREDIV_EN = 0
4938 23:19:04.719966 PH8_DLY = 0
4939 23:19:04.723143 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4940 23:19:04.726694 DQ_AAMCK_DIV = 4
4941 23:19:04.727079 CA_AAMCK_DIV = 4
4942 23:19:04.730189 CA_ADMCK_DIV = 4
4943 23:19:04.733176 DQ_TRACK_CA_EN = 0
4944 23:19:04.736262 CA_PICK = 933
4945 23:19:04.740101 CA_MCKIO = 933
4946 23:19:04.742997 MCKIO_SEMI = 0
4947 23:19:04.746691 PLL_FREQ = 3732
4948 23:19:04.747100 DQ_UI_PI_RATIO = 32
4949 23:19:04.749556 CA_UI_PI_RATIO = 0
4950 23:19:04.752878 ===================================
4951 23:19:04.756652 ===================================
4952 23:19:04.759549 memory_type:LPDDR4
4953 23:19:04.762810 GP_NUM : 10
4954 23:19:04.763192 SRAM_EN : 1
4955 23:19:04.766014 MD32_EN : 0
4956 23:19:04.769100 ===================================
4957 23:19:04.773075 [ANA_INIT] >>>>>>>>>>>>>>
4958 23:19:04.773460 <<<<<< [CONFIGURE PHASE]: ANA_TX
4959 23:19:04.779526 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4960 23:19:04.783281 ===================================
4961 23:19:04.783818 data_rate = 1866,PCW = 0X8f00
4962 23:19:04.785835 ===================================
4963 23:19:04.789001 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4964 23:19:04.795415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4965 23:19:04.802992 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4966 23:19:04.805464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4967 23:19:04.809470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4968 23:19:04.812209 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4969 23:19:04.816095 [ANA_INIT] flow start
4970 23:19:04.819733 [ANA_INIT] PLL >>>>>>>>
4971 23:19:04.820226 [ANA_INIT] PLL <<<<<<<<
4972 23:19:04.822596 [ANA_INIT] MIDPI >>>>>>>>
4973 23:19:04.825499 [ANA_INIT] MIDPI <<<<<<<<
4974 23:19:04.825984 [ANA_INIT] DLL >>>>>>>>
4975 23:19:04.828619 [ANA_INIT] flow end
4976 23:19:04.832548 ============ LP4 DIFF to SE enter ============
4977 23:19:04.836229 ============ LP4 DIFF to SE exit ============
4978 23:19:04.839621 [ANA_INIT] <<<<<<<<<<<<<
4979 23:19:04.841944 [Flow] Enable top DCM control >>>>>
4980 23:19:04.845389 [Flow] Enable top DCM control <<<<<
4981 23:19:04.848491 Enable DLL master slave shuffle
4982 23:19:04.855370 ==============================================================
4983 23:19:04.855825 Gating Mode config
4984 23:19:04.862200 ==============================================================
4985 23:19:04.862592 Config description:
4986 23:19:04.871349 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4987 23:19:04.877978 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4988 23:19:04.884609 SELPH_MODE 0: By rank 1: By Phase
4989 23:19:04.892444 ==============================================================
4990 23:19:04.894302 GAT_TRACK_EN = 1
4991 23:19:04.894703 RX_GATING_MODE = 2
4992 23:19:04.897949 RX_GATING_TRACK_MODE = 2
4993 23:19:04.901342 SELPH_MODE = 1
4994 23:19:04.904800 PICG_EARLY_EN = 1
4995 23:19:04.907904 VALID_LAT_VALUE = 1
4996 23:19:04.914347 ==============================================================
4997 23:19:04.917342 Enter into Gating configuration >>>>
4998 23:19:04.921473 Exit from Gating configuration <<<<
4999 23:19:04.923983 Enter into DVFS_PRE_config >>>>>
5000 23:19:04.933794 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5001 23:19:04.937392 Exit from DVFS_PRE_config <<<<<
5002 23:19:04.940916 Enter into PICG configuration >>>>
5003 23:19:04.943733 Exit from PICG configuration <<<<
5004 23:19:04.947176 [RX_INPUT] configuration >>>>>
5005 23:19:04.950864 [RX_INPUT] configuration <<<<<
5006 23:19:04.953800 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5007 23:19:04.960209 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5008 23:19:04.967248 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5009 23:19:04.973603 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5010 23:19:04.976497 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5011 23:19:04.983191 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5012 23:19:04.989704 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5013 23:19:04.993275 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5014 23:19:04.996494 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5015 23:19:05.000028 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5016 23:19:05.006181 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5017 23:19:05.009849 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5018 23:19:05.013872 ===================================
5019 23:19:05.016225 LPDDR4 DRAM CONFIGURATION
5020 23:19:05.019403 ===================================
5021 23:19:05.019702 EX_ROW_EN[0] = 0x0
5022 23:19:05.023351 EX_ROW_EN[1] = 0x0
5023 23:19:05.023789 LP4Y_EN = 0x0
5024 23:19:05.026584 WORK_FSP = 0x0
5025 23:19:05.026950 WL = 0x3
5026 23:19:05.030426 RL = 0x3
5027 23:19:05.030795 BL = 0x2
5028 23:19:05.033948 RPST = 0x0
5029 23:19:05.036323 RD_PRE = 0x0
5030 23:19:05.036688 WR_PRE = 0x1
5031 23:19:05.040138 WR_PST = 0x0
5032 23:19:05.040603 DBI_WR = 0x0
5033 23:19:05.043087 DBI_RD = 0x0
5034 23:19:05.043642 OTF = 0x1
5035 23:19:05.046404 ===================================
5036 23:19:05.049507 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5037 23:19:05.056337 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5038 23:19:05.059571 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5039 23:19:05.062265 ===================================
5040 23:19:05.065927 LPDDR4 DRAM CONFIGURATION
5041 23:19:05.068782 ===================================
5042 23:19:05.069250 EX_ROW_EN[0] = 0x10
5043 23:19:05.071947 EX_ROW_EN[1] = 0x0
5044 23:19:05.072414 LP4Y_EN = 0x0
5045 23:19:05.075303 WORK_FSP = 0x0
5046 23:19:05.075819 WL = 0x3
5047 23:19:05.079258 RL = 0x3
5048 23:19:05.082545 BL = 0x2
5049 23:19:05.083098 RPST = 0x0
5050 23:19:05.085417 RD_PRE = 0x0
5051 23:19:05.085881 WR_PRE = 0x1
5052 23:19:05.088742 WR_PST = 0x0
5053 23:19:05.089207 DBI_WR = 0x0
5054 23:19:05.092298 DBI_RD = 0x0
5055 23:19:05.092763 OTF = 0x1
5056 23:19:05.095401 ===================================
5057 23:19:05.101562 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5058 23:19:05.106565 nWR fixed to 30
5059 23:19:05.109373 [ModeRegInit_LP4] CH0 RK0
5060 23:19:05.109797 [ModeRegInit_LP4] CH0 RK1
5061 23:19:05.112373 [ModeRegInit_LP4] CH1 RK0
5062 23:19:05.115568 [ModeRegInit_LP4] CH1 RK1
5063 23:19:05.116147 match AC timing 9
5064 23:19:05.122518 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5065 23:19:05.126161 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5066 23:19:05.129121 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5067 23:19:05.135831 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5068 23:19:05.138633 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5069 23:19:05.139061 ==
5070 23:19:05.142265 Dram Type= 6, Freq= 0, CH_0, rank 0
5071 23:19:05.145656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5072 23:19:05.146082 ==
5073 23:19:05.152397 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5074 23:19:05.158952 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5075 23:19:05.161762 [CA 0] Center 37 (7~68) winsize 62
5076 23:19:05.166317 [CA 1] Center 37 (7~68) winsize 62
5077 23:19:05.169061 [CA 2] Center 34 (4~65) winsize 62
5078 23:19:05.172028 [CA 3] Center 35 (5~65) winsize 61
5079 23:19:05.175571 [CA 4] Center 33 (3~64) winsize 62
5080 23:19:05.178738 [CA 5] Center 33 (4~63) winsize 60
5081 23:19:05.179125
5082 23:19:05.181719 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5083 23:19:05.182255
5084 23:19:05.185146 [CATrainingPosCal] consider 1 rank data
5085 23:19:05.188681 u2DelayCellTimex100 = 270/100 ps
5086 23:19:05.191573 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5087 23:19:05.195043 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5088 23:19:05.198164 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5089 23:19:05.204570 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5090 23:19:05.207832 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5091 23:19:05.211084 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5092 23:19:05.211507
5093 23:19:05.214978 CA PerBit enable=1, Macro0, CA PI delay=33
5094 23:19:05.215495
5095 23:19:05.217796 [CBTSetCACLKResult] CA Dly = 33
5096 23:19:05.218308 CS Dly: 7 (0~38)
5097 23:19:05.222836 ==
5098 23:19:05.223261 Dram Type= 6, Freq= 0, CH_0, rank 1
5099 23:19:05.227873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 23:19:05.228384 ==
5101 23:19:05.230993 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5102 23:19:05.237387 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5103 23:19:05.240947 [CA 0] Center 37 (7~68) winsize 62
5104 23:19:05.244850 [CA 1] Center 37 (7~68) winsize 62
5105 23:19:05.247866 [CA 2] Center 34 (4~65) winsize 62
5106 23:19:05.250855 [CA 3] Center 34 (4~65) winsize 62
5107 23:19:05.255005 [CA 4] Center 33 (3~64) winsize 62
5108 23:19:05.257168 [CA 5] Center 32 (2~63) winsize 62
5109 23:19:05.257691
5110 23:19:05.261001 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5111 23:19:05.261558
5112 23:19:05.268061 [CATrainingPosCal] consider 2 rank data
5113 23:19:05.268623 u2DelayCellTimex100 = 270/100 ps
5114 23:19:05.273739 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5115 23:19:05.278538 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5116 23:19:05.280525 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5117 23:19:05.284173 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5118 23:19:05.287630 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5119 23:19:05.290611 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5120 23:19:05.291172
5121 23:19:05.293966 CA PerBit enable=1, Macro0, CA PI delay=33
5122 23:19:05.294524
5123 23:19:05.297660 [CBTSetCACLKResult] CA Dly = 33
5124 23:19:05.300377 CS Dly: 7 (0~39)
5125 23:19:05.300843
5126 23:19:05.304135 ----->DramcWriteLeveling(PI) begin...
5127 23:19:05.304697 ==
5128 23:19:05.306916 Dram Type= 6, Freq= 0, CH_0, rank 0
5129 23:19:05.310157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5130 23:19:05.310629 ==
5131 23:19:05.314184 Write leveling (Byte 0): 34 => 34
5132 23:19:05.316911 Write leveling (Byte 1): 31 => 31
5133 23:19:05.319947 DramcWriteLeveling(PI) end<-----
5134 23:19:05.320517
5135 23:19:05.320891 ==
5136 23:19:05.323805 Dram Type= 6, Freq= 0, CH_0, rank 0
5137 23:19:05.327246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5138 23:19:05.327878 ==
5139 23:19:05.332653 [Gating] SW mode calibration
5140 23:19:05.336397 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5141 23:19:05.343657 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5142 23:19:05.346450 0 14 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5143 23:19:05.353091 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5144 23:19:05.357159 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 23:19:05.359111 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 23:19:05.366557 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 23:19:05.369640 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5148 23:19:05.372773 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 23:19:05.379555 0 14 28 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
5150 23:19:05.382699 0 15 0 | B1->B0 | 3030 2828 | 1 1 | (1 1) (1 0)
5151 23:19:05.386043 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5152 23:19:05.392397 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 23:19:05.395726 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 23:19:05.399253 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 23:19:05.406005 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5156 23:19:05.408623 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 23:19:05.412083 0 15 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
5158 23:19:05.418785 1 0 0 | B1->B0 | 3030 4444 | 1 0 | (0 0) (0 0)
5159 23:19:05.422284 1 0 4 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
5160 23:19:05.425368 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 23:19:05.432046 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 23:19:05.435097 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 23:19:05.438300 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 23:19:05.445117 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 23:19:05.448635 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 23:19:05.451873 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5167 23:19:05.457738 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 23:19:05.461825 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 23:19:05.465021 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 23:19:05.471108 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 23:19:05.474437 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 23:19:05.478399 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 23:19:05.484659 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 23:19:05.488001 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 23:19:05.491463 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 23:19:05.498130 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 23:19:05.501052 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 23:19:05.504891 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 23:19:05.511176 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 23:19:05.514638 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 23:19:05.517314 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5182 23:19:05.524281 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5183 23:19:05.527547 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 23:19:05.531106 Total UI for P1: 0, mck2ui 16
5185 23:19:05.533957 best dqsien dly found for B0: ( 1, 2, 30)
5186 23:19:05.537490 Total UI for P1: 0, mck2ui 16
5187 23:19:05.540644 best dqsien dly found for B1: ( 1, 2, 30)
5188 23:19:05.544038 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5189 23:19:05.546985 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5190 23:19:05.547541
5191 23:19:05.550653 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5192 23:19:05.554587 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5193 23:19:05.557504 [Gating] SW calibration Done
5194 23:19:05.557968 ==
5195 23:19:05.560025 Dram Type= 6, Freq= 0, CH_0, rank 0
5196 23:19:05.567713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5197 23:19:05.568432 ==
5198 23:19:05.568816 RX Vref Scan: 0
5199 23:19:05.569166
5200 23:19:05.569853 RX Vref 0 -> 0, step: 1
5201 23:19:05.570215
5202 23:19:05.573163 RX Delay -80 -> 252, step: 8
5203 23:19:05.576791 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5204 23:19:05.579899 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5205 23:19:05.583489 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5206 23:19:05.587005 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5207 23:19:05.589916 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5208 23:19:05.597430 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5209 23:19:05.600182 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5210 23:19:05.603414 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5211 23:19:05.606576 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5212 23:19:05.609587 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5213 23:19:05.616665 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5214 23:19:05.619556 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5215 23:19:05.622729 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5216 23:19:05.626523 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5217 23:19:05.629748 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5218 23:19:05.636113 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5219 23:19:05.636629 ==
5220 23:19:05.639331 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 23:19:05.642881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 23:19:05.643400 ==
5223 23:19:05.643805 DQS Delay:
5224 23:19:05.645962 DQS0 = 0, DQS1 = 0
5225 23:19:05.646408 DQM Delay:
5226 23:19:05.649213 DQM0 = 97, DQM1 = 85
5227 23:19:05.649731 DQ Delay:
5228 23:19:05.652643 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5229 23:19:05.655975 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5230 23:19:05.659485 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5231 23:19:05.662368 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5232 23:19:05.662792
5233 23:19:05.663124
5234 23:19:05.663434 ==
5235 23:19:05.665499 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 23:19:05.672360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 23:19:05.672864 ==
5238 23:19:05.673203
5239 23:19:05.673514
5240 23:19:05.673814 TX Vref Scan disable
5241 23:19:05.676507 == TX Byte 0 ==
5242 23:19:05.679760 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5243 23:19:05.686343 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5244 23:19:05.686860 == TX Byte 1 ==
5245 23:19:05.688809 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5246 23:19:05.695366 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5247 23:19:05.695905 ==
5248 23:19:05.698777 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 23:19:05.702326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 23:19:05.702891 ==
5251 23:19:05.703265
5252 23:19:05.703607
5253 23:19:05.704908 TX Vref Scan disable
5254 23:19:05.708331 == TX Byte 0 ==
5255 23:19:05.711305 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5256 23:19:05.715068 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5257 23:19:05.718516 == TX Byte 1 ==
5258 23:19:05.721126 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5259 23:19:05.724969 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5260 23:19:05.725390
5261 23:19:05.725722 [DATLAT]
5262 23:19:05.728262 Freq=933, CH0 RK0
5263 23:19:05.728803
5264 23:19:05.731199 DATLAT Default: 0xd
5265 23:19:05.731614 0, 0xFFFF, sum = 0
5266 23:19:05.735190 1, 0xFFFF, sum = 0
5267 23:19:05.735749 2, 0xFFFF, sum = 0
5268 23:19:05.737825 3, 0xFFFF, sum = 0
5269 23:19:05.738407 4, 0xFFFF, sum = 0
5270 23:19:05.741146 5, 0xFFFF, sum = 0
5271 23:19:05.741572 6, 0xFFFF, sum = 0
5272 23:19:05.744283 7, 0xFFFF, sum = 0
5273 23:19:05.744723 8, 0xFFFF, sum = 0
5274 23:19:05.748185 9, 0xFFFF, sum = 0
5275 23:19:05.748609 10, 0x0, sum = 1
5276 23:19:05.751405 11, 0x0, sum = 2
5277 23:19:05.751973 12, 0x0, sum = 3
5278 23:19:05.754355 13, 0x0, sum = 4
5279 23:19:05.754780 best_step = 11
5280 23:19:05.755113
5281 23:19:05.755423 ==
5282 23:19:05.758106 Dram Type= 6, Freq= 0, CH_0, rank 0
5283 23:19:05.761538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 23:19:05.764056 ==
5285 23:19:05.764475 RX Vref Scan: 1
5286 23:19:05.764807
5287 23:19:05.767341 RX Vref 0 -> 0, step: 1
5288 23:19:05.767819
5289 23:19:05.771175 RX Delay -61 -> 252, step: 4
5290 23:19:05.771651
5291 23:19:05.774233 Set Vref, RX VrefLevel [Byte0]: 56
5292 23:19:05.777996 [Byte1]: 57
5293 23:19:05.778605
5294 23:19:05.780857 Final RX Vref Byte 0 = 56 to rank0
5295 23:19:05.783830 Final RX Vref Byte 1 = 57 to rank0
5296 23:19:05.787474 Final RX Vref Byte 0 = 56 to rank1
5297 23:19:05.790623 Final RX Vref Byte 1 = 57 to rank1==
5298 23:19:05.794119 Dram Type= 6, Freq= 0, CH_0, rank 0
5299 23:19:05.796877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 23:19:05.797299 ==
5301 23:19:05.800355 DQS Delay:
5302 23:19:05.800776 DQS0 = 0, DQS1 = 0
5303 23:19:05.801108 DQM Delay:
5304 23:19:05.803983 DQM0 = 97, DQM1 = 86
5305 23:19:05.804359 DQ Delay:
5306 23:19:05.806905 DQ0 =96, DQ1 =96, DQ2 =94, DQ3 =92
5307 23:19:05.810426 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5308 23:19:05.813494 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =84
5309 23:19:05.817145 DQ12 =90, DQ13 =88, DQ14 =100, DQ15 =90
5310 23:19:05.817535
5311 23:19:05.817776
5312 23:19:05.827481 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c13, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
5313 23:19:05.830472 CH0 RK0: MR19=505, MR18=2C13
5314 23:19:05.836427 CH0_RK0: MR19=0x505, MR18=0x2C13, DQSOSC=408, MR23=63, INC=65, DEC=43
5315 23:19:05.836828
5316 23:19:05.840239 ----->DramcWriteLeveling(PI) begin...
5317 23:19:05.840629 ==
5318 23:19:05.843772 Dram Type= 6, Freq= 0, CH_0, rank 1
5319 23:19:05.846979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 23:19:05.847494 ==
5321 23:19:05.850185 Write leveling (Byte 0): 31 => 31
5322 23:19:05.853198 Write leveling (Byte 1): 30 => 30
5323 23:19:05.856544 DramcWriteLeveling(PI) end<-----
5324 23:19:05.857050
5325 23:19:05.857380 ==
5326 23:19:05.860311 Dram Type= 6, Freq= 0, CH_0, rank 1
5327 23:19:05.863394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 23:19:05.864005 ==
5329 23:19:05.866148 [Gating] SW mode calibration
5330 23:19:05.873284 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5331 23:19:05.879268 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5332 23:19:05.882781 0 14 0 | B1->B0 | 2a2a 3333 | 0 1 | (0 0) (1 1)
5333 23:19:05.886534 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 23:19:05.893233 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 23:19:05.896141 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 23:19:05.899593 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 23:19:05.906431 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 23:19:05.909669 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 23:19:05.912976 0 14 28 | B1->B0 | 3434 2e2e | 0 1 | (0 0) (1 1)
5340 23:19:05.919472 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5341 23:19:05.922550 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 23:19:05.926470 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 23:19:05.932686 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 23:19:05.936005 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 23:19:05.939259 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5346 23:19:05.945450 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 23:19:05.949115 0 15 28 | B1->B0 | 2828 2f2f | 0 1 | (0 0) (0 0)
5348 23:19:05.952210 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5349 23:19:05.958810 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 23:19:05.961869 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 23:19:05.965802 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 23:19:05.971554 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 23:19:05.975083 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 23:19:05.978190 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 23:19:05.985185 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5356 23:19:05.988061 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5357 23:19:05.992042 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 23:19:05.998524 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 23:19:06.001744 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 23:19:06.005463 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 23:19:06.011230 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 23:19:06.015066 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 23:19:06.017978 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 23:19:06.024857 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 23:19:06.028400 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 23:19:06.031593 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 23:19:06.037556 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 23:19:06.041703 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 23:19:06.044902 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 23:19:06.051504 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 23:19:06.054624 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5372 23:19:06.057350 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5373 23:19:06.060989 Total UI for P1: 0, mck2ui 16
5374 23:19:06.064285 best dqsien dly found for B0: ( 1, 2, 28)
5375 23:19:06.071720 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 23:19:06.073975 Total UI for P1: 0, mck2ui 16
5377 23:19:06.077046 best dqsien dly found for B1: ( 1, 2, 30)
5378 23:19:06.080595 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5379 23:19:06.084028 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5380 23:19:06.084641
5381 23:19:06.086998 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5382 23:19:06.090347 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5383 23:19:06.094108 [Gating] SW calibration Done
5384 23:19:06.094533 ==
5385 23:19:06.097096 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 23:19:06.100440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 23:19:06.100870 ==
5388 23:19:06.103656 RX Vref Scan: 0
5389 23:19:06.104115
5390 23:19:06.106968 RX Vref 0 -> 0, step: 1
5391 23:19:06.107495
5392 23:19:06.107892 RX Delay -80 -> 252, step: 8
5393 23:19:06.113873 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5394 23:19:06.117323 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5395 23:19:06.120619 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5396 23:19:06.124037 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5397 23:19:06.126981 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5398 23:19:06.129756 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5399 23:19:06.136752 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5400 23:19:06.140180 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5401 23:19:06.143100 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5402 23:19:06.146871 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5403 23:19:06.149779 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5404 23:19:06.156627 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5405 23:19:06.159627 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5406 23:19:06.163448 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5407 23:19:06.166687 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5408 23:19:06.169929 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5409 23:19:06.170497 ==
5410 23:19:06.172678 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 23:19:06.179338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 23:19:06.179858 ==
5413 23:19:06.180344 DQS Delay:
5414 23:19:06.183174 DQS0 = 0, DQS1 = 0
5415 23:19:06.183640 DQM Delay:
5416 23:19:06.184202 DQM0 = 97, DQM1 = 89
5417 23:19:06.185806 DQ Delay:
5418 23:19:06.189806 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5419 23:19:06.192487 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5420 23:19:06.195872 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5421 23:19:06.199386 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5422 23:19:06.199994
5423 23:19:06.200446
5424 23:19:06.200863 ==
5425 23:19:06.202156 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 23:19:06.205668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 23:19:06.206194 ==
5428 23:19:06.206533
5429 23:19:06.206842
5430 23:19:06.209400 TX Vref Scan disable
5431 23:19:06.212688 == TX Byte 0 ==
5432 23:19:06.215347 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5433 23:19:06.218915 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5434 23:19:06.222670 == TX Byte 1 ==
5435 23:19:06.226027 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5436 23:19:06.229046 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5437 23:19:06.229573 ==
5438 23:19:06.232200 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 23:19:06.239042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 23:19:06.239606 ==
5441 23:19:06.240036
5442 23:19:06.240383
5443 23:19:06.240709 TX Vref Scan disable
5444 23:19:06.243329 == TX Byte 0 ==
5445 23:19:06.246523 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5446 23:19:06.252729 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5447 23:19:06.253285 == TX Byte 1 ==
5448 23:19:06.256268 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5449 23:19:06.263081 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5450 23:19:06.263641
5451 23:19:06.264072 [DATLAT]
5452 23:19:06.264426 Freq=933, CH0 RK1
5453 23:19:06.264765
5454 23:19:06.265659 DATLAT Default: 0xb
5455 23:19:06.270084 0, 0xFFFF, sum = 0
5456 23:19:06.270648 1, 0xFFFF, sum = 0
5457 23:19:06.272368 2, 0xFFFF, sum = 0
5458 23:19:06.272842 3, 0xFFFF, sum = 0
5459 23:19:06.275518 4, 0xFFFF, sum = 0
5460 23:19:06.276105 5, 0xFFFF, sum = 0
5461 23:19:06.279773 6, 0xFFFF, sum = 0
5462 23:19:06.280250 7, 0xFFFF, sum = 0
5463 23:19:06.282259 8, 0xFFFF, sum = 0
5464 23:19:06.282744 9, 0xFFFF, sum = 0
5465 23:19:06.286073 10, 0x0, sum = 1
5466 23:19:06.286546 11, 0x0, sum = 2
5467 23:19:06.289045 12, 0x0, sum = 3
5468 23:19:06.289610 13, 0x0, sum = 4
5469 23:19:06.292431 best_step = 11
5470 23:19:06.292891
5471 23:19:06.293252 ==
5472 23:19:06.295222 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 23:19:06.299524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 23:19:06.300039 ==
5475 23:19:06.300408 RX Vref Scan: 0
5476 23:19:06.300747
5477 23:19:06.301773 RX Vref 0 -> 0, step: 1
5478 23:19:06.302193
5479 23:19:06.305267 RX Delay -61 -> 252, step: 4
5480 23:19:06.311652 iDelay=199, Bit 0, Center 92 (3 ~ 182) 180
5481 23:19:06.315631 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5482 23:19:06.318697 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5483 23:19:06.321856 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5484 23:19:06.325227 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5485 23:19:06.328265 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5486 23:19:06.335807 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5487 23:19:06.338373 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5488 23:19:06.341294 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5489 23:19:06.344522 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5490 23:19:06.347663 iDelay=199, Bit 10, Center 90 (-5 ~ 186) 192
5491 23:19:06.354743 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5492 23:19:06.357857 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5493 23:19:06.360949 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5494 23:19:06.364321 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5495 23:19:06.371151 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5496 23:19:06.371756 ==
5497 23:19:06.374474 Dram Type= 6, Freq= 0, CH_0, rank 1
5498 23:19:06.377466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 23:19:06.378178 ==
5500 23:19:06.378690 DQS Delay:
5501 23:19:06.380893 DQS0 = 0, DQS1 = 0
5502 23:19:06.381465 DQM Delay:
5503 23:19:06.384256 DQM0 = 95, DQM1 = 88
5504 23:19:06.384734 DQ Delay:
5505 23:19:06.387713 DQ0 =92, DQ1 =98, DQ2 =90, DQ3 =94
5506 23:19:06.390620 DQ4 =96, DQ5 =88, DQ6 =104, DQ7 =104
5507 23:19:06.393837 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =82
5508 23:19:06.397902 DQ12 =90, DQ13 =92, DQ14 =100, DQ15 =92
5509 23:19:06.398476
5510 23:19:06.398964
5511 23:19:06.407748 [DQSOSCAuto] RK1, (LSB)MR18= 0x23f3, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 410 ps
5512 23:19:06.408332 CH0 RK1: MR19=504, MR18=23F3
5513 23:19:06.413606 CH0_RK1: MR19=0x504, MR18=0x23F3, DQSOSC=410, MR23=63, INC=64, DEC=42
5514 23:19:06.417627 [RxdqsGatingPostProcess] freq 933
5515 23:19:06.423657 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5516 23:19:06.427715 best DQS0 dly(2T, 0.5T) = (0, 10)
5517 23:19:06.430206 best DQS1 dly(2T, 0.5T) = (0, 10)
5518 23:19:06.433831 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5519 23:19:06.437380 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5520 23:19:06.440296 best DQS0 dly(2T, 0.5T) = (0, 10)
5521 23:19:06.440873 best DQS1 dly(2T, 0.5T) = (0, 10)
5522 23:19:06.443791 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5523 23:19:06.447088 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5524 23:19:06.450385 Pre-setting of DQS Precalculation
5525 23:19:06.457385 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5526 23:19:06.457973 ==
5527 23:19:06.459708 Dram Type= 6, Freq= 0, CH_1, rank 0
5528 23:19:06.462916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 23:19:06.463396 ==
5530 23:19:06.469657 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5531 23:19:06.475993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5532 23:19:06.479667 [CA 0] Center 37 (7~67) winsize 61
5533 23:19:06.482715 [CA 1] Center 37 (7~68) winsize 62
5534 23:19:06.486286 [CA 2] Center 34 (4~65) winsize 62
5535 23:19:06.489395 [CA 3] Center 33 (3~64) winsize 62
5536 23:19:06.493046 [CA 4] Center 34 (4~65) winsize 62
5537 23:19:06.495930 [CA 5] Center 33 (3~64) winsize 62
5538 23:19:06.496407
5539 23:19:06.499491 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5540 23:19:06.500018
5541 23:19:06.502593 [CATrainingPosCal] consider 1 rank data
5542 23:19:06.505886 u2DelayCellTimex100 = 270/100 ps
5543 23:19:06.509284 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5544 23:19:06.512303 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5545 23:19:06.515769 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5546 23:19:06.519325 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5547 23:19:06.522512 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5548 23:19:06.529361 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5549 23:19:06.529919
5550 23:19:06.532934 CA PerBit enable=1, Macro0, CA PI delay=33
5551 23:19:06.533495
5552 23:19:06.535759 [CBTSetCACLKResult] CA Dly = 33
5553 23:19:06.536224 CS Dly: 6 (0~37)
5554 23:19:06.536593 ==
5555 23:19:06.538887 Dram Type= 6, Freq= 0, CH_1, rank 1
5556 23:19:06.542479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 23:19:06.545535 ==
5558 23:19:06.548799 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5559 23:19:06.555607 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5560 23:19:06.559117 [CA 0] Center 36 (6~67) winsize 62
5561 23:19:06.562037 [CA 1] Center 37 (7~68) winsize 62
5562 23:19:06.565288 [CA 2] Center 34 (4~65) winsize 62
5563 23:19:06.569002 [CA 3] Center 34 (4~65) winsize 62
5564 23:19:06.572190 [CA 4] Center 34 (4~65) winsize 62
5565 23:19:06.575238 [CA 5] Center 33 (3~64) winsize 62
5566 23:19:06.575844
5567 23:19:06.578758 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5568 23:19:06.579386
5569 23:19:06.581948 [CATrainingPosCal] consider 2 rank data
5570 23:19:06.585308 u2DelayCellTimex100 = 270/100 ps
5571 23:19:06.588424 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5572 23:19:06.591477 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5573 23:19:06.594860 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5574 23:19:06.601603 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5575 23:19:06.604906 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5576 23:19:06.608520 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5577 23:19:06.609035
5578 23:19:06.611062 CA PerBit enable=1, Macro0, CA PI delay=33
5579 23:19:06.611481
5580 23:19:06.614726 [CBTSetCACLKResult] CA Dly = 33
5581 23:19:06.615241 CS Dly: 7 (0~39)
5582 23:19:06.615576
5583 23:19:06.618702 ----->DramcWriteLeveling(PI) begin...
5584 23:19:06.621190 ==
5585 23:19:06.624656 Dram Type= 6, Freq= 0, CH_1, rank 0
5586 23:19:06.628243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5587 23:19:06.628836 ==
5588 23:19:06.631317 Write leveling (Byte 0): 28 => 28
5589 23:19:06.634627 Write leveling (Byte 1): 29 => 29
5590 23:19:06.637858 DramcWriteLeveling(PI) end<-----
5591 23:19:06.638371
5592 23:19:06.638703 ==
5593 23:19:06.641282 Dram Type= 6, Freq= 0, CH_1, rank 0
5594 23:19:06.644023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5595 23:19:06.644447 ==
5596 23:19:06.647829 [Gating] SW mode calibration
5597 23:19:06.654703 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5598 23:19:06.660591 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5599 23:19:06.664570 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 23:19:06.667055 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 23:19:06.673737 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 23:19:06.677423 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 23:19:06.680702 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 23:19:06.687441 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 23:19:06.690427 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
5606 23:19:06.694670 0 14 28 | B1->B0 | 2c2c 2727 | 0 0 | (0 1) (0 0)
5607 23:19:06.700668 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 23:19:06.704069 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 23:19:06.706827 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 23:19:06.713745 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 23:19:06.717025 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 23:19:06.720463 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 23:19:06.726893 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5614 23:19:06.730845 0 15 28 | B1->B0 | 3939 3b3b | 1 0 | (0 0) (0 0)
5615 23:19:06.733757 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 23:19:06.740094 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 23:19:06.743987 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 23:19:06.746803 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 23:19:06.753853 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 23:19:06.756294 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 23:19:06.760594 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5622 23:19:06.766792 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5623 23:19:06.769868 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 23:19:06.772776 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 23:19:06.779574 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 23:19:06.782845 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 23:19:06.786027 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 23:19:06.793659 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 23:19:06.795735 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 23:19:06.798789 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 23:19:06.805953 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 23:19:06.809335 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 23:19:06.812135 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 23:19:06.818992 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 23:19:06.822077 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 23:19:06.825745 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 23:19:06.832037 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5638 23:19:06.835623 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5639 23:19:06.838732 Total UI for P1: 0, mck2ui 16
5640 23:19:06.841947 best dqsien dly found for B0: ( 1, 2, 24)
5641 23:19:06.845352 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 23:19:06.848367 Total UI for P1: 0, mck2ui 16
5643 23:19:06.852519 best dqsien dly found for B1: ( 1, 2, 26)
5644 23:19:06.854725 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5645 23:19:06.858140 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5646 23:19:06.858225
5647 23:19:06.864420 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5648 23:19:06.867822 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5649 23:19:06.870891 [Gating] SW calibration Done
5650 23:19:06.870972 ==
5651 23:19:06.874139 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 23:19:06.878491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 23:19:06.878573 ==
5654 23:19:06.878637 RX Vref Scan: 0
5655 23:19:06.878698
5656 23:19:06.880781 RX Vref 0 -> 0, step: 1
5657 23:19:06.880908
5658 23:19:06.883968 RX Delay -80 -> 252, step: 8
5659 23:19:06.887430 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5660 23:19:06.890436 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5661 23:19:06.897443 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5662 23:19:06.900232 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5663 23:19:06.903985 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5664 23:19:06.907189 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5665 23:19:06.910315 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5666 23:19:06.913793 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5667 23:19:06.920325 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5668 23:19:06.923582 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5669 23:19:06.926905 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5670 23:19:06.930812 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5671 23:19:06.933557 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5672 23:19:06.940188 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5673 23:19:06.943583 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5674 23:19:06.946772 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5675 23:19:06.946855 ==
5676 23:19:06.949738 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 23:19:06.953232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 23:19:06.953315 ==
5679 23:19:06.956560 DQS Delay:
5680 23:19:06.956642 DQS0 = 0, DQS1 = 0
5681 23:19:06.960031 DQM Delay:
5682 23:19:06.960112 DQM0 = 102, DQM1 = 91
5683 23:19:06.960177 DQ Delay:
5684 23:19:06.963549 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =103
5685 23:19:06.966447 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5686 23:19:06.969813 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5687 23:19:06.976790 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5688 23:19:06.976872
5689 23:19:06.976936
5690 23:19:06.976995 ==
5691 23:19:06.979590 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 23:19:06.983183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 23:19:06.983265 ==
5694 23:19:06.983330
5695 23:19:06.983389
5696 23:19:06.986138 TX Vref Scan disable
5697 23:19:06.986219 == TX Byte 0 ==
5698 23:19:06.992885 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5699 23:19:06.996319 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5700 23:19:06.996401 == TX Byte 1 ==
5701 23:19:07.002387 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5702 23:19:07.005705 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5703 23:19:07.005787 ==
5704 23:19:07.009753 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 23:19:07.012589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 23:19:07.012675 ==
5707 23:19:07.012739
5708 23:19:07.015681
5709 23:19:07.015798 TX Vref Scan disable
5710 23:19:07.019286 == TX Byte 0 ==
5711 23:19:07.022741 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5712 23:19:07.025783 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5713 23:19:07.029090 == TX Byte 1 ==
5714 23:19:07.032333 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5715 23:19:07.039308 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5716 23:19:07.039389
5717 23:19:07.039453 [DATLAT]
5718 23:19:07.039513 Freq=933, CH1 RK0
5719 23:19:07.039571
5720 23:19:07.042434 DATLAT Default: 0xd
5721 23:19:07.042514 0, 0xFFFF, sum = 0
5722 23:19:07.045671 1, 0xFFFF, sum = 0
5723 23:19:07.048747 2, 0xFFFF, sum = 0
5724 23:19:07.048829 3, 0xFFFF, sum = 0
5725 23:19:07.052065 4, 0xFFFF, sum = 0
5726 23:19:07.052147 5, 0xFFFF, sum = 0
5727 23:19:07.055516 6, 0xFFFF, sum = 0
5728 23:19:07.055598 7, 0xFFFF, sum = 0
5729 23:19:07.058638 8, 0xFFFF, sum = 0
5730 23:19:07.058721 9, 0xFFFF, sum = 0
5731 23:19:07.062145 10, 0x0, sum = 1
5732 23:19:07.062228 11, 0x0, sum = 2
5733 23:19:07.065645 12, 0x0, sum = 3
5734 23:19:07.065727 13, 0x0, sum = 4
5735 23:19:07.065792 best_step = 11
5736 23:19:07.068773
5737 23:19:07.068856 ==
5738 23:19:07.072194 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 23:19:07.075279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 23:19:07.075361 ==
5741 23:19:07.075426 RX Vref Scan: 1
5742 23:19:07.075486
5743 23:19:07.078488 RX Vref 0 -> 0, step: 1
5744 23:19:07.078569
5745 23:19:07.081803 RX Delay -69 -> 252, step: 4
5746 23:19:07.081884
5747 23:19:07.085365 Set Vref, RX VrefLevel [Byte0]: 46
5748 23:19:07.088373 [Byte1]: 60
5749 23:19:07.091970
5750 23:19:07.092051 Final RX Vref Byte 0 = 46 to rank0
5751 23:19:07.094789 Final RX Vref Byte 1 = 60 to rank0
5752 23:19:07.098579 Final RX Vref Byte 0 = 46 to rank1
5753 23:19:07.101768 Final RX Vref Byte 1 = 60 to rank1==
5754 23:19:07.104614 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 23:19:07.111233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 23:19:07.111314 ==
5757 23:19:07.111379 DQS Delay:
5758 23:19:07.114491 DQS0 = 0, DQS1 = 0
5759 23:19:07.114572 DQM Delay:
5760 23:19:07.114637 DQM0 = 102, DQM1 = 95
5761 23:19:07.117874 DQ Delay:
5762 23:19:07.121429 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5763 23:19:07.124301 DQ4 =100, DQ5 =114, DQ6 =110, DQ7 =98
5764 23:19:07.127794 DQ8 =82, DQ9 =86, DQ10 =98, DQ11 =86
5765 23:19:07.130671 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5766 23:19:07.130752
5767 23:19:07.130816
5768 23:19:07.140656 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a0a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5769 23:19:07.140738 CH1 RK0: MR19=505, MR18=1A0A
5770 23:19:07.148374 CH1_RK0: MR19=0x505, MR18=0x1A0A, DQSOSC=413, MR23=63, INC=63, DEC=42
5771 23:19:07.148456
5772 23:19:07.150772 ----->DramcWriteLeveling(PI) begin...
5773 23:19:07.150858 ==
5774 23:19:07.154037 Dram Type= 6, Freq= 0, CH_1, rank 1
5775 23:19:07.161009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 23:19:07.161091 ==
5777 23:19:07.163861 Write leveling (Byte 0): 29 => 29
5778 23:19:07.163942 Write leveling (Byte 1): 29 => 29
5779 23:19:07.168063 DramcWriteLeveling(PI) end<-----
5780 23:19:07.168144
5781 23:19:07.168207 ==
5782 23:19:07.170480 Dram Type= 6, Freq= 0, CH_1, rank 1
5783 23:19:07.177400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 23:19:07.177481 ==
5785 23:19:07.180471 [Gating] SW mode calibration
5786 23:19:07.186664 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5787 23:19:07.190581 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5788 23:19:07.197138 0 14 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5789 23:19:07.200459 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 23:19:07.203509 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5791 23:19:07.209929 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5792 23:19:07.213144 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 23:19:07.216639 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 23:19:07.223369 0 14 24 | B1->B0 | 3232 3434 | 0 1 | (0 1) (1 0)
5795 23:19:07.226959 0 14 28 | B1->B0 | 2b2b 2f2f | 1 0 | (0 0) (1 1)
5796 23:19:07.230200 0 15 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
5797 23:19:07.236795 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 23:19:07.239986 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 23:19:07.243132 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5800 23:19:07.249530 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 23:19:07.253680 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 23:19:07.256221 0 15 24 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5803 23:19:07.262702 0 15 28 | B1->B0 | 3b3b 2b2b | 1 1 | (0 0) (0 0)
5804 23:19:07.266451 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5805 23:19:07.269233 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 23:19:07.275975 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 23:19:07.279378 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 23:19:07.282554 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 23:19:07.289056 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 23:19:07.292535 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5811 23:19:07.295546 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5812 23:19:07.302066 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 23:19:07.305531 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 23:19:07.309728 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 23:19:07.316210 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 23:19:07.318560 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 23:19:07.321915 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 23:19:07.328760 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 23:19:07.332207 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 23:19:07.335208 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 23:19:07.341696 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 23:19:07.345202 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 23:19:07.348545 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 23:19:07.355360 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 23:19:07.357992 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 23:19:07.361935 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5827 23:19:07.368865 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5828 23:19:07.371637 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5829 23:19:07.374833 Total UI for P1: 0, mck2ui 16
5830 23:19:07.377967 best dqsien dly found for B1: ( 1, 2, 26)
5831 23:19:07.381210 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 23:19:07.384545 Total UI for P1: 0, mck2ui 16
5833 23:19:07.388059 best dqsien dly found for B0: ( 1, 2, 30)
5834 23:19:07.391560 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5835 23:19:07.395062 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5836 23:19:07.397692
5837 23:19:07.401077 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5838 23:19:07.404133 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5839 23:19:07.408384 [Gating] SW calibration Done
5840 23:19:07.408466 ==
5841 23:19:07.410962 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 23:19:07.413939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 23:19:07.414022 ==
5844 23:19:07.417681 RX Vref Scan: 0
5845 23:19:07.417763
5846 23:19:07.417828 RX Vref 0 -> 0, step: 1
5847 23:19:07.417888
5848 23:19:07.420906 RX Delay -80 -> 252, step: 8
5849 23:19:07.424122 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5850 23:19:07.427818 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5851 23:19:07.433849 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5852 23:19:07.437666 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5853 23:19:07.440580 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5854 23:19:07.443905 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5855 23:19:07.447372 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5856 23:19:07.453531 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5857 23:19:07.456855 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5858 23:19:07.461863 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5859 23:19:07.464460 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5860 23:19:07.466744 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5861 23:19:07.473942 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5862 23:19:07.477187 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5863 23:19:07.480359 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5864 23:19:07.482907 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5865 23:19:07.483015 ==
5866 23:19:07.486345 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 23:19:07.489723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 23:19:07.493836 ==
5869 23:19:07.493917 DQS Delay:
5870 23:19:07.493982 DQS0 = 0, DQS1 = 0
5871 23:19:07.496689 DQM Delay:
5872 23:19:07.496770 DQM0 = 99, DQM1 = 92
5873 23:19:07.499581 DQ Delay:
5874 23:19:07.499712 DQ0 =107, DQ1 =91, DQ2 =87, DQ3 =99
5875 23:19:07.503165 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5876 23:19:07.506445 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5877 23:19:07.512980 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =99
5878 23:19:07.513088
5879 23:19:07.513180
5880 23:19:07.513270 ==
5881 23:19:07.516088 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 23:19:07.520066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 23:19:07.520148 ==
5884 23:19:07.520213
5885 23:19:07.520272
5886 23:19:07.523155 TX Vref Scan disable
5887 23:19:07.523236 == TX Byte 0 ==
5888 23:19:07.529246 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5889 23:19:07.532633 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5890 23:19:07.532715 == TX Byte 1 ==
5891 23:19:07.538998 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5892 23:19:07.542876 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5893 23:19:07.542958 ==
5894 23:19:07.545970 Dram Type= 6, Freq= 0, CH_1, rank 1
5895 23:19:07.549710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5896 23:19:07.549792 ==
5897 23:19:07.552699
5898 23:19:07.552779
5899 23:19:07.552844 TX Vref Scan disable
5900 23:19:07.555866 == TX Byte 0 ==
5901 23:19:07.558832 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5902 23:19:07.565403 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5903 23:19:07.565488 == TX Byte 1 ==
5904 23:19:07.568963 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5905 23:19:07.575549 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5906 23:19:07.575630
5907 23:19:07.575701 [DATLAT]
5908 23:19:07.575762 Freq=933, CH1 RK1
5909 23:19:07.575820
5910 23:19:07.578819 DATLAT Default: 0xb
5911 23:19:07.578900 0, 0xFFFF, sum = 0
5912 23:19:07.582108 1, 0xFFFF, sum = 0
5913 23:19:07.585053 2, 0xFFFF, sum = 0
5914 23:19:07.585136 3, 0xFFFF, sum = 0
5915 23:19:07.589591 4, 0xFFFF, sum = 0
5916 23:19:07.589675 5, 0xFFFF, sum = 0
5917 23:19:07.591929 6, 0xFFFF, sum = 0
5918 23:19:07.592012 7, 0xFFFF, sum = 0
5919 23:19:07.595605 8, 0xFFFF, sum = 0
5920 23:19:07.595728 9, 0xFFFF, sum = 0
5921 23:19:07.599164 10, 0x0, sum = 1
5922 23:19:07.599247 11, 0x0, sum = 2
5923 23:19:07.602044 12, 0x0, sum = 3
5924 23:19:07.602154 13, 0x0, sum = 4
5925 23:19:07.602255 best_step = 11
5926 23:19:07.605060
5927 23:19:07.605141 ==
5928 23:19:07.608456 Dram Type= 6, Freq= 0, CH_1, rank 1
5929 23:19:07.612054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5930 23:19:07.612137 ==
5931 23:19:07.612202 RX Vref Scan: 0
5932 23:19:07.612262
5933 23:19:07.615884 RX Vref 0 -> 0, step: 1
5934 23:19:07.615974
5935 23:19:07.618967 RX Delay -61 -> 252, step: 4
5936 23:19:07.625183 iDelay=203, Bit 0, Center 106 (19 ~ 194) 176
5937 23:19:07.628134 iDelay=203, Bit 1, Center 96 (11 ~ 182) 172
5938 23:19:07.632143 iDelay=203, Bit 2, Center 92 (7 ~ 178) 172
5939 23:19:07.635433 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5940 23:19:07.638896 iDelay=203, Bit 4, Center 100 (11 ~ 190) 180
5941 23:19:07.641590 iDelay=203, Bit 5, Center 112 (27 ~ 198) 172
5942 23:19:07.648168 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5943 23:19:07.651996 iDelay=203, Bit 7, Center 96 (7 ~ 186) 180
5944 23:19:07.654583 iDelay=203, Bit 8, Center 86 (-1 ~ 174) 176
5945 23:19:07.658183 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5946 23:19:07.662409 iDelay=203, Bit 10, Center 96 (7 ~ 186) 180
5947 23:19:07.665017 iDelay=203, Bit 11, Center 88 (3 ~ 174) 172
5948 23:19:07.671262 iDelay=203, Bit 12, Center 104 (15 ~ 194) 180
5949 23:19:07.674497 iDelay=203, Bit 13, Center 102 (11 ~ 194) 184
5950 23:19:07.678229 iDelay=203, Bit 14, Center 104 (15 ~ 194) 180
5951 23:19:07.681230 iDelay=203, Bit 15, Center 102 (11 ~ 194) 184
5952 23:19:07.681312 ==
5953 23:19:07.685580 Dram Type= 6, Freq= 0, CH_1, rank 1
5954 23:19:07.691212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5955 23:19:07.691295 ==
5956 23:19:07.691360 DQS Delay:
5957 23:19:07.694193 DQS0 = 0, DQS1 = 0
5958 23:19:07.694275 DQM Delay:
5959 23:19:07.697886 DQM0 = 101, DQM1 = 96
5960 23:19:07.697968 DQ Delay:
5961 23:19:07.701051 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5962 23:19:07.704370 DQ4 =100, DQ5 =112, DQ6 =114, DQ7 =96
5963 23:19:07.707561 DQ8 =86, DQ9 =88, DQ10 =96, DQ11 =88
5964 23:19:07.710997 DQ12 =104, DQ13 =102, DQ14 =104, DQ15 =102
5965 23:19:07.711079
5966 23:19:07.711143
5967 23:19:07.720927 [DQSOSCAuto] RK1, (LSB)MR18= 0x903, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
5968 23:19:07.721010 CH1 RK1: MR19=505, MR18=903
5969 23:19:07.727517 CH1_RK1: MR19=0x505, MR18=0x903, DQSOSC=419, MR23=63, INC=61, DEC=41
5970 23:19:07.730740 [RxdqsGatingPostProcess] freq 933
5971 23:19:07.737138 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5972 23:19:07.740002 best DQS0 dly(2T, 0.5T) = (0, 10)
5973 23:19:07.743428 best DQS1 dly(2T, 0.5T) = (0, 10)
5974 23:19:07.747024 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5975 23:19:07.750461 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5976 23:19:07.753436 best DQS0 dly(2T, 0.5T) = (0, 10)
5977 23:19:07.753518 best DQS1 dly(2T, 0.5T) = (0, 10)
5978 23:19:07.756854 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5979 23:19:07.760173 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5980 23:19:07.763756 Pre-setting of DQS Precalculation
5981 23:19:07.770494 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5982 23:19:07.776235 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5983 23:19:07.783129 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5984 23:19:07.783212
5985 23:19:07.783276
5986 23:19:07.786355 [Calibration Summary] 1866 Mbps
5987 23:19:07.790079 CH 0, Rank 0
5988 23:19:07.790160 SW Impedance : PASS
5989 23:19:07.793321 DUTY Scan : NO K
5990 23:19:07.796278 ZQ Calibration : PASS
5991 23:19:07.796385 Jitter Meter : NO K
5992 23:19:07.799817 CBT Training : PASS
5993 23:19:07.799900 Write leveling : PASS
5994 23:19:07.802916 RX DQS gating : PASS
5995 23:19:07.806045 RX DQ/DQS(RDDQC) : PASS
5996 23:19:07.806126 TX DQ/DQS : PASS
5997 23:19:07.810052 RX DATLAT : PASS
5998 23:19:07.813127 RX DQ/DQS(Engine): PASS
5999 23:19:07.813208 TX OE : NO K
6000 23:19:07.816701 All Pass.
6001 23:19:07.816782
6002 23:19:07.816846 CH 0, Rank 1
6003 23:19:07.820283 SW Impedance : PASS
6004 23:19:07.820364 DUTY Scan : NO K
6005 23:19:07.822995 ZQ Calibration : PASS
6006 23:19:07.826007 Jitter Meter : NO K
6007 23:19:07.826088 CBT Training : PASS
6008 23:19:07.828967 Write leveling : PASS
6009 23:19:07.833181 RX DQS gating : PASS
6010 23:19:07.833263 RX DQ/DQS(RDDQC) : PASS
6011 23:19:07.835688 TX DQ/DQS : PASS
6012 23:19:07.839183 RX DATLAT : PASS
6013 23:19:07.839264 RX DQ/DQS(Engine): PASS
6014 23:19:07.842384 TX OE : NO K
6015 23:19:07.842465 All Pass.
6016 23:19:07.842529
6017 23:19:07.845711 CH 1, Rank 0
6018 23:19:07.845792 SW Impedance : PASS
6019 23:19:07.849069 DUTY Scan : NO K
6020 23:19:07.852044 ZQ Calibration : PASS
6021 23:19:07.852125 Jitter Meter : NO K
6022 23:19:07.855307 CBT Training : PASS
6023 23:19:07.859023 Write leveling : PASS
6024 23:19:07.859104 RX DQS gating : PASS
6025 23:19:07.861940 RX DQ/DQS(RDDQC) : PASS
6026 23:19:07.865632 TX DQ/DQS : PASS
6027 23:19:07.865713 RX DATLAT : PASS
6028 23:19:07.868873 RX DQ/DQS(Engine): PASS
6029 23:19:07.871969 TX OE : NO K
6030 23:19:07.872051 All Pass.
6031 23:19:07.872115
6032 23:19:07.872175 CH 1, Rank 1
6033 23:19:07.875354 SW Impedance : PASS
6034 23:19:07.878577 DUTY Scan : NO K
6035 23:19:07.878658 ZQ Calibration : PASS
6036 23:19:07.881809 Jitter Meter : NO K
6037 23:19:07.885333 CBT Training : PASS
6038 23:19:07.885414 Write leveling : PASS
6039 23:19:07.888816 RX DQS gating : PASS
6040 23:19:07.888897 RX DQ/DQS(RDDQC) : PASS
6041 23:19:07.892219 TX DQ/DQS : PASS
6042 23:19:07.894962 RX DATLAT : PASS
6043 23:19:07.895046 RX DQ/DQS(Engine): PASS
6044 23:19:07.898810 TX OE : NO K
6045 23:19:07.898892 All Pass.
6046 23:19:07.898956
6047 23:19:07.901779 DramC Write-DBI off
6048 23:19:07.905088 PER_BANK_REFRESH: Hybrid Mode
6049 23:19:07.905173 TX_TRACKING: ON
6050 23:19:07.914986 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6051 23:19:07.917873 [FAST_K] Save calibration result to emmc
6052 23:19:07.921858 dramc_set_vcore_voltage set vcore to 650000
6053 23:19:07.924758 Read voltage for 400, 6
6054 23:19:07.924838 Vio18 = 0
6055 23:19:07.929101 Vcore = 650000
6056 23:19:07.929182 Vdram = 0
6057 23:19:07.929247 Vddq = 0
6058 23:19:07.929307 Vmddr = 0
6059 23:19:07.934393 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6060 23:19:07.941460 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6061 23:19:07.941541 MEM_TYPE=3, freq_sel=20
6062 23:19:07.944520 sv_algorithm_assistance_LP4_800
6063 23:19:07.948072 ============ PULL DRAM RESETB DOWN ============
6064 23:19:07.954243 ========== PULL DRAM RESETB DOWN end =========
6065 23:19:07.957987 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6066 23:19:07.960708 ===================================
6067 23:19:07.964607 LPDDR4 DRAM CONFIGURATION
6068 23:19:07.967380 ===================================
6069 23:19:07.967460 EX_ROW_EN[0] = 0x0
6070 23:19:07.970702 EX_ROW_EN[1] = 0x0
6071 23:19:07.970783 LP4Y_EN = 0x0
6072 23:19:07.974039 WORK_FSP = 0x0
6073 23:19:07.977776 WL = 0x2
6074 23:19:07.977857 RL = 0x2
6075 23:19:07.980429 BL = 0x2
6076 23:19:07.980510 RPST = 0x0
6077 23:19:07.984008 RD_PRE = 0x0
6078 23:19:07.984091 WR_PRE = 0x1
6079 23:19:07.987366 WR_PST = 0x0
6080 23:19:07.987447 DBI_WR = 0x0
6081 23:19:07.990395 DBI_RD = 0x0
6082 23:19:07.990475 OTF = 0x1
6083 23:19:07.994192 ===================================
6084 23:19:07.996835 ===================================
6085 23:19:08.000798 ANA top config
6086 23:19:08.003566 ===================================
6087 23:19:08.003683 DLL_ASYNC_EN = 0
6088 23:19:08.007141 ALL_SLAVE_EN = 1
6089 23:19:08.009928 NEW_RANK_MODE = 1
6090 23:19:08.013345 DLL_IDLE_MODE = 1
6091 23:19:08.016895 LP45_APHY_COMB_EN = 1
6092 23:19:08.016976 TX_ODT_DIS = 1
6093 23:19:08.020893 NEW_8X_MODE = 1
6094 23:19:08.023881 ===================================
6095 23:19:08.026891 ===================================
6096 23:19:08.029967 data_rate = 800
6097 23:19:08.033037 CKR = 1
6098 23:19:08.037670 DQ_P2S_RATIO = 4
6099 23:19:08.040207 ===================================
6100 23:19:08.043803 CA_P2S_RATIO = 4
6101 23:19:08.043884 DQ_CA_OPEN = 0
6102 23:19:08.046668 DQ_SEMI_OPEN = 1
6103 23:19:08.049588 CA_SEMI_OPEN = 1
6104 23:19:08.052888 CA_FULL_RATE = 0
6105 23:19:08.056123 DQ_CKDIV4_EN = 0
6106 23:19:08.059878 CA_CKDIV4_EN = 1
6107 23:19:08.059979 CA_PREDIV_EN = 0
6108 23:19:08.062999 PH8_DLY = 0
6109 23:19:08.066749 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6110 23:19:08.070312 DQ_AAMCK_DIV = 0
6111 23:19:08.073196 CA_AAMCK_DIV = 0
6112 23:19:08.076125 CA_ADMCK_DIV = 4
6113 23:19:08.076207 DQ_TRACK_CA_EN = 0
6114 23:19:08.079455 CA_PICK = 800
6115 23:19:08.082561 CA_MCKIO = 400
6116 23:19:08.086148 MCKIO_SEMI = 400
6117 23:19:08.089301 PLL_FREQ = 3016
6118 23:19:08.092790 DQ_UI_PI_RATIO = 32
6119 23:19:08.095856 CA_UI_PI_RATIO = 32
6120 23:19:08.099165 ===================================
6121 23:19:08.102419 ===================================
6122 23:19:08.105551 memory_type:LPDDR4
6123 23:19:08.105632 GP_NUM : 10
6124 23:19:08.109313 SRAM_EN : 1
6125 23:19:08.109394 MD32_EN : 0
6126 23:19:08.112357 ===================================
6127 23:19:08.115318 [ANA_INIT] >>>>>>>>>>>>>>
6128 23:19:08.118911 <<<<<< [CONFIGURE PHASE]: ANA_TX
6129 23:19:08.122531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6130 23:19:08.125959 ===================================
6131 23:19:08.128763 data_rate = 800,PCW = 0X7400
6132 23:19:08.132287 ===================================
6133 23:19:08.135826 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6134 23:19:08.141598 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6135 23:19:08.151605 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6136 23:19:08.155308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6137 23:19:08.158537 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6138 23:19:08.165638 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6139 23:19:08.165720 [ANA_INIT] flow start
6140 23:19:08.168558 [ANA_INIT] PLL >>>>>>>>
6141 23:19:08.171613 [ANA_INIT] PLL <<<<<<<<
6142 23:19:08.171733 [ANA_INIT] MIDPI >>>>>>>>
6143 23:19:08.174753 [ANA_INIT] MIDPI <<<<<<<<
6144 23:19:08.177734 [ANA_INIT] DLL >>>>>>>>
6145 23:19:08.177815 [ANA_INIT] flow end
6146 23:19:08.184691 ============ LP4 DIFF to SE enter ============
6147 23:19:08.187914 ============ LP4 DIFF to SE exit ============
6148 23:19:08.187996 [ANA_INIT] <<<<<<<<<<<<<
6149 23:19:08.191315 [Flow] Enable top DCM control >>>>>
6150 23:19:08.194493 [Flow] Enable top DCM control <<<<<
6151 23:19:08.197667 Enable DLL master slave shuffle
6152 23:19:08.204635 ==============================================================
6153 23:19:08.207928 Gating Mode config
6154 23:19:08.210890 ==============================================================
6155 23:19:08.213987 Config description:
6156 23:19:08.224470 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6157 23:19:08.230686 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6158 23:19:08.233873 SELPH_MODE 0: By rank 1: By Phase
6159 23:19:08.240756 ==============================================================
6160 23:19:08.244276 GAT_TRACK_EN = 0
6161 23:19:08.247555 RX_GATING_MODE = 2
6162 23:19:08.250916 RX_GATING_TRACK_MODE = 2
6163 23:19:08.254005 SELPH_MODE = 1
6164 23:19:08.254090 PICG_EARLY_EN = 1
6165 23:19:08.257588 VALID_LAT_VALUE = 1
6166 23:19:08.263422 ==============================================================
6167 23:19:08.266675 Enter into Gating configuration >>>>
6168 23:19:08.270637 Exit from Gating configuration <<<<
6169 23:19:08.273510 Enter into DVFS_PRE_config >>>>>
6170 23:19:08.283593 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6171 23:19:08.286747 Exit from DVFS_PRE_config <<<<<
6172 23:19:08.290254 Enter into PICG configuration >>>>
6173 23:19:08.293474 Exit from PICG configuration <<<<
6174 23:19:08.296614 [RX_INPUT] configuration >>>>>
6175 23:19:08.299619 [RX_INPUT] configuration <<<<<
6176 23:19:08.303306 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6177 23:19:08.310042 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6178 23:19:08.316644 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6179 23:19:08.323273 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6180 23:19:08.329934 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6181 23:19:08.336570 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6182 23:19:08.340123 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6183 23:19:08.343058 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6184 23:19:08.346415 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6185 23:19:08.353048 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6186 23:19:08.356157 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6187 23:19:08.360080 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6188 23:19:08.362571 ===================================
6189 23:19:08.366398 LPDDR4 DRAM CONFIGURATION
6190 23:19:08.369676 ===================================
6191 23:19:08.369758 EX_ROW_EN[0] = 0x0
6192 23:19:08.372797 EX_ROW_EN[1] = 0x0
6193 23:19:08.375994 LP4Y_EN = 0x0
6194 23:19:08.376076 WORK_FSP = 0x0
6195 23:19:08.380046 WL = 0x2
6196 23:19:08.380127 RL = 0x2
6197 23:19:08.382574 BL = 0x2
6198 23:19:08.382654 RPST = 0x0
6199 23:19:08.385803 RD_PRE = 0x0
6200 23:19:08.385883 WR_PRE = 0x1
6201 23:19:08.389531 WR_PST = 0x0
6202 23:19:08.389611 DBI_WR = 0x0
6203 23:19:08.392886 DBI_RD = 0x0
6204 23:19:08.392966 OTF = 0x1
6205 23:19:08.395942 ===================================
6206 23:19:08.399249 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6207 23:19:08.405524 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6208 23:19:08.409823 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6209 23:19:08.412257 ===================================
6210 23:19:08.415918 LPDDR4 DRAM CONFIGURATION
6211 23:19:08.420230 ===================================
6212 23:19:08.420312 EX_ROW_EN[0] = 0x10
6213 23:19:08.422348 EX_ROW_EN[1] = 0x0
6214 23:19:08.422428 LP4Y_EN = 0x0
6215 23:19:08.425747 WORK_FSP = 0x0
6216 23:19:08.428866 WL = 0x2
6217 23:19:08.428946 RL = 0x2
6218 23:19:08.432445 BL = 0x2
6219 23:19:08.432526 RPST = 0x0
6220 23:19:08.435695 RD_PRE = 0x0
6221 23:19:08.435775 WR_PRE = 0x1
6222 23:19:08.439043 WR_PST = 0x0
6223 23:19:08.439124 DBI_WR = 0x0
6224 23:19:08.442064 DBI_RD = 0x0
6225 23:19:08.442145 OTF = 0x1
6226 23:19:08.445573 ===================================
6227 23:19:08.451904 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6228 23:19:08.456174 nWR fixed to 30
6229 23:19:08.459623 [ModeRegInit_LP4] CH0 RK0
6230 23:19:08.459747 [ModeRegInit_LP4] CH0 RK1
6231 23:19:08.462606 [ModeRegInit_LP4] CH1 RK0
6232 23:19:08.466066 [ModeRegInit_LP4] CH1 RK1
6233 23:19:08.466147 match AC timing 19
6234 23:19:08.473069 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6235 23:19:08.476014 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6236 23:19:08.478946 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6237 23:19:08.485945 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6238 23:19:08.489031 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6239 23:19:08.489113 ==
6240 23:19:08.493078 Dram Type= 6, Freq= 0, CH_0, rank 0
6241 23:19:08.495547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6242 23:19:08.495629 ==
6243 23:19:08.502479 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6244 23:19:08.509127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6245 23:19:08.513415 [CA 0] Center 36 (8~64) winsize 57
6246 23:19:08.515614 [CA 1] Center 36 (8~64) winsize 57
6247 23:19:08.518592 [CA 2] Center 36 (8~64) winsize 57
6248 23:19:08.522231 [CA 3] Center 36 (8~64) winsize 57
6249 23:19:08.525283 [CA 4] Center 36 (8~64) winsize 57
6250 23:19:08.528922 [CA 5] Center 36 (8~64) winsize 57
6251 23:19:08.529004
6252 23:19:08.532310 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6253 23:19:08.532391
6254 23:19:08.535903 [CATrainingPosCal] consider 1 rank data
6255 23:19:08.538803 u2DelayCellTimex100 = 270/100 ps
6256 23:19:08.541457 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 23:19:08.545109 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 23:19:08.548151 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 23:19:08.551203 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 23:19:08.554840 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 23:19:08.558330 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 23:19:08.558412
6263 23:19:08.564626 CA PerBit enable=1, Macro0, CA PI delay=36
6264 23:19:08.564707
6265 23:19:08.568057 [CBTSetCACLKResult] CA Dly = 36
6266 23:19:08.568138 CS Dly: 1 (0~32)
6267 23:19:08.568202 ==
6268 23:19:08.571352 Dram Type= 6, Freq= 0, CH_0, rank 1
6269 23:19:08.574650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6270 23:19:08.574733 ==
6271 23:19:08.581171 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6272 23:19:08.587585 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6273 23:19:08.591123 [CA 0] Center 36 (8~64) winsize 57
6274 23:19:08.594432 [CA 1] Center 36 (8~64) winsize 57
6275 23:19:08.597506 [CA 2] Center 36 (8~64) winsize 57
6276 23:19:08.600904 [CA 3] Center 36 (8~64) winsize 57
6277 23:19:08.604747 [CA 4] Center 36 (8~64) winsize 57
6278 23:19:08.607993 [CA 5] Center 36 (8~64) winsize 57
6279 23:19:08.608076
6280 23:19:08.611366 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6281 23:19:08.611448
6282 23:19:08.614184 [CATrainingPosCal] consider 2 rank data
6283 23:19:08.617476 u2DelayCellTimex100 = 270/100 ps
6284 23:19:08.620859 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 23:19:08.623957 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 23:19:08.627448 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 23:19:08.630858 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 23:19:08.634307 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 23:19:08.637198 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 23:19:08.637279
6291 23:19:08.640400 CA PerBit enable=1, Macro0, CA PI delay=36
6292 23:19:08.643983
6293 23:19:08.644063 [CBTSetCACLKResult] CA Dly = 36
6294 23:19:08.647349 CS Dly: 1 (0~32)
6295 23:19:08.647430
6296 23:19:08.650941 ----->DramcWriteLeveling(PI) begin...
6297 23:19:08.651024 ==
6298 23:19:08.653597 Dram Type= 6, Freq= 0, CH_0, rank 0
6299 23:19:08.657541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6300 23:19:08.657622 ==
6301 23:19:08.660524 Write leveling (Byte 0): 40 => 8
6302 23:19:08.663554 Write leveling (Byte 1): 32 => 0
6303 23:19:08.667070 DramcWriteLeveling(PI) end<-----
6304 23:19:08.667151
6305 23:19:08.667215 ==
6306 23:19:08.670317 Dram Type= 6, Freq= 0, CH_0, rank 0
6307 23:19:08.673772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 23:19:08.676408 ==
6309 23:19:08.676489 [Gating] SW mode calibration
6310 23:19:08.687383 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6311 23:19:08.690075 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6312 23:19:08.693557 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6313 23:19:08.699587 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6314 23:19:08.702818 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6315 23:19:08.706120 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6316 23:19:08.712888 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6317 23:19:08.716026 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6318 23:19:08.719923 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6319 23:19:08.726963 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6320 23:19:08.729233 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6321 23:19:08.732235 Total UI for P1: 0, mck2ui 16
6322 23:19:08.735723 best dqsien dly found for B0: ( 0, 14, 24)
6323 23:19:08.738918 Total UI for P1: 0, mck2ui 16
6324 23:19:08.742342 best dqsien dly found for B1: ( 0, 14, 24)
6325 23:19:08.745611 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6326 23:19:08.749553 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6327 23:19:08.749633
6328 23:19:08.752126 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6329 23:19:08.758842 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6330 23:19:08.758952 [Gating] SW calibration Done
6331 23:19:08.759039 ==
6332 23:19:08.761970 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 23:19:08.769047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 23:19:08.769128 ==
6335 23:19:08.769192 RX Vref Scan: 0
6336 23:19:08.769252
6337 23:19:08.772329 RX Vref 0 -> 0, step: 1
6338 23:19:08.772410
6339 23:19:08.775552 RX Delay -410 -> 252, step: 16
6340 23:19:08.778995 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6341 23:19:08.782481 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6342 23:19:08.788491 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6343 23:19:08.792019 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6344 23:19:08.795571 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6345 23:19:08.798456 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6346 23:19:08.805111 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6347 23:19:08.807973 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6348 23:19:08.811799 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6349 23:19:08.814816 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6350 23:19:08.821789 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6351 23:19:08.825030 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6352 23:19:08.828216 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6353 23:19:08.835092 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6354 23:19:08.838039 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6355 23:19:08.841463 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6356 23:19:08.841545 ==
6357 23:19:08.844265 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 23:19:08.847981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 23:19:08.851646 ==
6360 23:19:08.851765 DQS Delay:
6361 23:19:08.851832 DQS0 = 43, DQS1 = 59
6362 23:19:08.854303 DQM Delay:
6363 23:19:08.854384 DQM0 = 10, DQM1 = 13
6364 23:19:08.857505 DQ Delay:
6365 23:19:08.857586 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6366 23:19:08.861021 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6367 23:19:08.864488 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6368 23:19:08.867584 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6369 23:19:08.867666
6370 23:19:08.867741
6371 23:19:08.871035 ==
6372 23:19:08.874256 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 23:19:08.877759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 23:19:08.877868 ==
6375 23:19:08.877973
6376 23:19:08.878070
6377 23:19:08.880628 TX Vref Scan disable
6378 23:19:08.880730 == TX Byte 0 ==
6379 23:19:08.883935 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6380 23:19:08.890880 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6381 23:19:08.890983 == TX Byte 1 ==
6382 23:19:08.893917 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6383 23:19:08.901009 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6384 23:19:08.901109 ==
6385 23:19:08.903594 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 23:19:08.907350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 23:19:08.907450 ==
6388 23:19:08.907545
6389 23:19:08.907635
6390 23:19:08.910407 TX Vref Scan disable
6391 23:19:08.910512 == TX Byte 0 ==
6392 23:19:08.917051 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6393 23:19:08.920409 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6394 23:19:08.920508 == TX Byte 1 ==
6395 23:19:08.926983 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6396 23:19:08.930717 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6397 23:19:08.930816
6398 23:19:08.930907 [DATLAT]
6399 23:19:08.933300 Freq=400, CH0 RK0
6400 23:19:08.933404
6401 23:19:08.933497 DATLAT Default: 0xf
6402 23:19:08.936953 0, 0xFFFF, sum = 0
6403 23:19:08.937027 1, 0xFFFF, sum = 0
6404 23:19:08.940526 2, 0xFFFF, sum = 0
6405 23:19:08.940626 3, 0xFFFF, sum = 0
6406 23:19:08.943632 4, 0xFFFF, sum = 0
6407 23:19:08.943731 5, 0xFFFF, sum = 0
6408 23:19:08.946999 6, 0xFFFF, sum = 0
6409 23:19:08.947095 7, 0xFFFF, sum = 0
6410 23:19:08.949709 8, 0xFFFF, sum = 0
6411 23:19:08.953152 9, 0xFFFF, sum = 0
6412 23:19:08.953249 10, 0xFFFF, sum = 0
6413 23:19:08.956714 11, 0xFFFF, sum = 0
6414 23:19:08.956792 12, 0xFFFF, sum = 0
6415 23:19:08.959867 13, 0x0, sum = 1
6416 23:19:08.959939 14, 0x0, sum = 2
6417 23:19:08.963119 15, 0x0, sum = 3
6418 23:19:08.963217 16, 0x0, sum = 4
6419 23:19:08.963310 best_step = 14
6420 23:19:08.967221
6421 23:19:08.967321 ==
6422 23:19:08.969934 Dram Type= 6, Freq= 0, CH_0, rank 0
6423 23:19:08.973667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 23:19:08.973768 ==
6425 23:19:08.973859 RX Vref Scan: 1
6426 23:19:08.973951
6427 23:19:08.976621 RX Vref 0 -> 0, step: 1
6428 23:19:08.976716
6429 23:19:08.979496 RX Delay -359 -> 252, step: 8
6430 23:19:08.979592
6431 23:19:08.982969 Set Vref, RX VrefLevel [Byte0]: 56
6432 23:19:08.986211 [Byte1]: 57
6433 23:19:08.990176
6434 23:19:08.990280 Final RX Vref Byte 0 = 56 to rank0
6435 23:19:08.993560 Final RX Vref Byte 1 = 57 to rank0
6436 23:19:08.996700 Final RX Vref Byte 0 = 56 to rank1
6437 23:19:09.000914 Final RX Vref Byte 1 = 57 to rank1==
6438 23:19:09.003594 Dram Type= 6, Freq= 0, CH_0, rank 0
6439 23:19:09.010118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6440 23:19:09.010220 ==
6441 23:19:09.010324 DQS Delay:
6442 23:19:09.013147 DQS0 = 44, DQS1 = 60
6443 23:19:09.013253 DQM Delay:
6444 23:19:09.013348 DQM0 = 8, DQM1 = 12
6445 23:19:09.016773 DQ Delay:
6446 23:19:09.019545 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6447 23:19:09.019643 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6448 23:19:09.023224 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6449 23:19:09.026256 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6450 23:19:09.026354
6451 23:19:09.029541
6452 23:19:09.036481 [DQSOSCAuto] RK0, (LSB)MR18= 0xbb7f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6453 23:19:09.039823 CH0 RK0: MR19=C0C, MR18=BB7F
6454 23:19:09.045753 CH0_RK0: MR19=0xC0C, MR18=0xBB7F, DQSOSC=386, MR23=63, INC=396, DEC=264
6455 23:19:09.045855 ==
6456 23:19:09.049147 Dram Type= 6, Freq= 0, CH_0, rank 1
6457 23:19:09.053076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 23:19:09.053150 ==
6459 23:19:09.056276 [Gating] SW mode calibration
6460 23:19:09.062436 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6461 23:19:09.068893 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6462 23:19:09.072624 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6463 23:19:09.076121 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6464 23:19:09.082510 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6465 23:19:09.085695 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6466 23:19:09.089022 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6467 23:19:09.095556 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6468 23:19:09.098889 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6469 23:19:09.101977 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6470 23:19:09.108670 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6471 23:19:09.111613 Total UI for P1: 0, mck2ui 16
6472 23:19:09.115172 best dqsien dly found for B0: ( 0, 14, 24)
6473 23:19:09.118471 Total UI for P1: 0, mck2ui 16
6474 23:19:09.121891 best dqsien dly found for B1: ( 0, 14, 24)
6475 23:19:09.125004 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6476 23:19:09.128255 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6477 23:19:09.128344
6478 23:19:09.131615 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6479 23:19:09.134813 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6480 23:19:09.138148 [Gating] SW calibration Done
6481 23:19:09.138246 ==
6482 23:19:09.141839 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 23:19:09.144837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 23:19:09.144939 ==
6485 23:19:09.148015 RX Vref Scan: 0
6486 23:19:09.148086
6487 23:19:09.151581 RX Vref 0 -> 0, step: 1
6488 23:19:09.151686
6489 23:19:09.151764 RX Delay -410 -> 252, step: 16
6490 23:19:09.157819 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6491 23:19:09.161450 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6492 23:19:09.164637 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6493 23:19:09.171453 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6494 23:19:09.174690 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6495 23:19:09.178100 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6496 23:19:09.180938 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6497 23:19:09.187595 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6498 23:19:09.191850 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6499 23:19:09.194229 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6500 23:19:09.197607 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6501 23:19:09.204470 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6502 23:19:09.207917 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6503 23:19:09.211223 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6504 23:19:09.214072 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6505 23:19:09.220747 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6506 23:19:09.220830 ==
6507 23:19:09.224395 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 23:19:09.227620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 23:19:09.227753 ==
6510 23:19:09.227820 DQS Delay:
6511 23:19:09.230556 DQS0 = 43, DQS1 = 59
6512 23:19:09.230638 DQM Delay:
6513 23:19:09.234517 DQM0 = 10, DQM1 = 15
6514 23:19:09.234599 DQ Delay:
6515 23:19:09.237487 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6516 23:19:09.241226 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6517 23:19:09.244080 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6518 23:19:09.247353 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6519 23:19:09.247435
6520 23:19:09.247500
6521 23:19:09.247560 ==
6522 23:19:09.250533 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 23:19:09.253740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 23:19:09.253822 ==
6525 23:19:09.256810
6526 23:19:09.256891
6527 23:19:09.256956 TX Vref Scan disable
6528 23:19:09.260784 == TX Byte 0 ==
6529 23:19:09.263708 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6530 23:19:09.266905 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6531 23:19:09.270371 == TX Byte 1 ==
6532 23:19:09.273230 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6533 23:19:09.277058 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6534 23:19:09.277140 ==
6535 23:19:09.280390 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 23:19:09.283265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 23:19:09.286725 ==
6538 23:19:09.286808
6539 23:19:09.286872
6540 23:19:09.286932 TX Vref Scan disable
6541 23:19:09.290146 == TX Byte 0 ==
6542 23:19:09.293149 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6543 23:19:09.296709 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6544 23:19:09.299592 == TX Byte 1 ==
6545 23:19:09.303071 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6546 23:19:09.306436 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6547 23:19:09.306527
6548 23:19:09.309738 [DATLAT]
6549 23:19:09.309819 Freq=400, CH0 RK1
6550 23:19:09.309885
6551 23:19:09.313105 DATLAT Default: 0xe
6552 23:19:09.313187 0, 0xFFFF, sum = 0
6553 23:19:09.316585 1, 0xFFFF, sum = 0
6554 23:19:09.316668 2, 0xFFFF, sum = 0
6555 23:19:09.319863 3, 0xFFFF, sum = 0
6556 23:19:09.319947 4, 0xFFFF, sum = 0
6557 23:19:09.323135 5, 0xFFFF, sum = 0
6558 23:19:09.323218 6, 0xFFFF, sum = 0
6559 23:19:09.326332 7, 0xFFFF, sum = 0
6560 23:19:09.326422 8, 0xFFFF, sum = 0
6561 23:19:09.329801 9, 0xFFFF, sum = 0
6562 23:19:09.329884 10, 0xFFFF, sum = 0
6563 23:19:09.333091 11, 0xFFFF, sum = 0
6564 23:19:09.333174 12, 0xFFFF, sum = 0
6565 23:19:09.336639 13, 0x0, sum = 1
6566 23:19:09.336722 14, 0x0, sum = 2
6567 23:19:09.339533 15, 0x0, sum = 3
6568 23:19:09.339616 16, 0x0, sum = 4
6569 23:19:09.343387 best_step = 14
6570 23:19:09.343468
6571 23:19:09.343532 ==
6572 23:19:09.346544 Dram Type= 6, Freq= 0, CH_0, rank 1
6573 23:19:09.349366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 23:19:09.349449 ==
6575 23:19:09.352946 RX Vref Scan: 0
6576 23:19:09.353027
6577 23:19:09.353092 RX Vref 0 -> 0, step: 1
6578 23:19:09.353153
6579 23:19:09.356011 RX Delay -359 -> 252, step: 8
6580 23:19:09.364360 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6581 23:19:09.367642 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6582 23:19:09.370820 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6583 23:19:09.377609 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6584 23:19:09.380719 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6585 23:19:09.383921 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6586 23:19:09.387148 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6587 23:19:09.393952 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6588 23:19:09.397374 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6589 23:19:09.400410 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6590 23:19:09.404505 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6591 23:19:09.410081 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6592 23:19:09.413906 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6593 23:19:09.416779 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6594 23:19:09.424053 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6595 23:19:09.426737 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6596 23:19:09.426816 ==
6597 23:19:09.429963 Dram Type= 6, Freq= 0, CH_0, rank 1
6598 23:19:09.433378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6599 23:19:09.433458 ==
6600 23:19:09.436454 DQS Delay:
6601 23:19:09.436531 DQS0 = 44, DQS1 = 56
6602 23:19:09.436594 DQM Delay:
6603 23:19:09.439826 DQM0 = 9, DQM1 = 11
6604 23:19:09.439897 DQ Delay:
6605 23:19:09.443092 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =8
6606 23:19:09.446637 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6607 23:19:09.449954 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6608 23:19:09.453206 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6609 23:19:09.453308
6610 23:19:09.453398
6611 23:19:09.462992 [DQSOSCAuto] RK1, (LSB)MR18= 0xae3b, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps
6612 23:19:09.463096 CH0 RK1: MR19=C0C, MR18=AE3B
6613 23:19:09.469598 CH0_RK1: MR19=0xC0C, MR18=0xAE3B, DQSOSC=388, MR23=63, INC=392, DEC=261
6614 23:19:09.472754 [RxdqsGatingPostProcess] freq 400
6615 23:19:09.480081 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6616 23:19:09.482836 best DQS0 dly(2T, 0.5T) = (0, 10)
6617 23:19:09.486635 best DQS1 dly(2T, 0.5T) = (0, 10)
6618 23:19:09.490099 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6619 23:19:09.492673 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6620 23:19:09.495974 best DQS0 dly(2T, 0.5T) = (0, 10)
6621 23:19:09.498913 best DQS1 dly(2T, 0.5T) = (0, 10)
6622 23:19:09.502586 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6623 23:19:09.505513 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6624 23:19:09.505610 Pre-setting of DQS Precalculation
6625 23:19:09.512522 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6626 23:19:09.512620 ==
6627 23:19:09.515802 Dram Type= 6, Freq= 0, CH_1, rank 0
6628 23:19:09.518961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6629 23:19:09.519057 ==
6630 23:19:09.525482 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6631 23:19:09.532753 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6632 23:19:09.536225 [CA 0] Center 36 (8~64) winsize 57
6633 23:19:09.538702 [CA 1] Center 36 (8~64) winsize 57
6634 23:19:09.542020 [CA 2] Center 36 (8~64) winsize 57
6635 23:19:09.545645 [CA 3] Center 36 (8~64) winsize 57
6636 23:19:09.548327 [CA 4] Center 36 (8~64) winsize 57
6637 23:19:09.548403 [CA 5] Center 36 (8~64) winsize 57
6638 23:19:09.548471
6639 23:19:09.555975 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6640 23:19:09.556076
6641 23:19:09.558247 [CATrainingPosCal] consider 1 rank data
6642 23:19:09.562112 u2DelayCellTimex100 = 270/100 ps
6643 23:19:09.564704 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 23:19:09.567949 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 23:19:09.571806 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 23:19:09.574791 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 23:19:09.578333 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 23:19:09.581660 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 23:19:09.581760
6650 23:19:09.584651 CA PerBit enable=1, Macro0, CA PI delay=36
6651 23:19:09.588066
6652 23:19:09.588168 [CBTSetCACLKResult] CA Dly = 36
6653 23:19:09.591341 CS Dly: 1 (0~32)
6654 23:19:09.591448 ==
6655 23:19:09.594369 Dram Type= 6, Freq= 0, CH_1, rank 1
6656 23:19:09.597686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6657 23:19:09.597789 ==
6658 23:19:09.604678 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6659 23:19:09.611236 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6660 23:19:09.614406 [CA 0] Center 36 (8~64) winsize 57
6661 23:19:09.617463 [CA 1] Center 36 (8~64) winsize 57
6662 23:19:09.620753 [CA 2] Center 36 (8~64) winsize 57
6663 23:19:09.624326 [CA 3] Center 36 (8~64) winsize 57
6664 23:19:09.624426 [CA 4] Center 36 (8~64) winsize 57
6665 23:19:09.627521 [CA 5] Center 36 (8~64) winsize 57
6666 23:19:09.627618
6667 23:19:09.633976 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6668 23:19:09.634085
6669 23:19:09.636907 [CATrainingPosCal] consider 2 rank data
6670 23:19:09.640619 u2DelayCellTimex100 = 270/100 ps
6671 23:19:09.644045 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 23:19:09.647071 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 23:19:09.650339 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 23:19:09.653612 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 23:19:09.657147 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 23:19:09.660557 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 23:19:09.660630
6678 23:19:09.664224 CA PerBit enable=1, Macro0, CA PI delay=36
6679 23:19:09.666477
6680 23:19:09.666585 [CBTSetCACLKResult] CA Dly = 36
6681 23:19:09.669951 CS Dly: 1 (0~32)
6682 23:19:09.670060
6683 23:19:09.673308 ----->DramcWriteLeveling(PI) begin...
6684 23:19:09.673409 ==
6685 23:19:09.677262 Dram Type= 6, Freq= 0, CH_1, rank 0
6686 23:19:09.680261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6687 23:19:09.680361 ==
6688 23:19:09.683478 Write leveling (Byte 0): 40 => 8
6689 23:19:09.686172 Write leveling (Byte 1): 32 => 0
6690 23:19:09.689977 DramcWriteLeveling(PI) end<-----
6691 23:19:09.690080
6692 23:19:09.690171 ==
6693 23:19:09.693225 Dram Type= 6, Freq= 0, CH_1, rank 0
6694 23:19:09.696081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 23:19:09.699549 ==
6696 23:19:09.699648 [Gating] SW mode calibration
6697 23:19:09.706609 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6698 23:19:09.712895 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6699 23:19:09.715798 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6700 23:19:09.722708 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6701 23:19:09.726449 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6702 23:19:09.729762 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6703 23:19:09.735645 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6704 23:19:09.739038 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6705 23:19:09.742858 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6706 23:19:09.749241 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6707 23:19:09.752100 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6708 23:19:09.756271 Total UI for P1: 0, mck2ui 16
6709 23:19:09.759024 best dqsien dly found for B0: ( 0, 14, 24)
6710 23:19:09.762029 Total UI for P1: 0, mck2ui 16
6711 23:19:09.765791 best dqsien dly found for B1: ( 0, 14, 24)
6712 23:19:09.768851 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6713 23:19:09.772039 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6714 23:19:09.772108
6715 23:19:09.775392 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6716 23:19:09.781742 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6717 23:19:09.781845 [Gating] SW calibration Done
6718 23:19:09.781937 ==
6719 23:19:09.785176 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 23:19:09.791866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 23:19:09.791955 ==
6722 23:19:09.792048 RX Vref Scan: 0
6723 23:19:09.792137
6724 23:19:09.795335 RX Vref 0 -> 0, step: 1
6725 23:19:09.795437
6726 23:19:09.798400 RX Delay -410 -> 252, step: 16
6727 23:19:09.801626 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6728 23:19:09.805154 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6729 23:19:09.811829 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6730 23:19:09.814810 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6731 23:19:09.818252 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6732 23:19:09.821926 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6733 23:19:09.828259 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6734 23:19:09.831130 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6735 23:19:09.834392 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6736 23:19:09.837505 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6737 23:19:09.844198 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6738 23:19:09.847766 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6739 23:19:09.851189 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6740 23:19:09.857845 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6741 23:19:09.861074 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6742 23:19:09.864720 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6743 23:19:09.864823 ==
6744 23:19:09.867622 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 23:19:09.873836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 23:19:09.873934 ==
6747 23:19:09.874027 DQS Delay:
6748 23:19:09.877058 DQS0 = 43, DQS1 = 51
6749 23:19:09.877153 DQM Delay:
6750 23:19:09.877243 DQM0 = 12, DQM1 = 14
6751 23:19:09.880313 DQ Delay:
6752 23:19:09.884046 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6753 23:19:09.884145 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6754 23:19:09.886827 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6755 23:19:09.890102 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6756 23:19:09.890200
6757 23:19:09.890297
6758 23:19:09.893662 ==
6759 23:19:09.896798 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 23:19:09.900260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 23:19:09.900366 ==
6762 23:19:09.900458
6763 23:19:09.900548
6764 23:19:09.903575 TX Vref Scan disable
6765 23:19:09.903703 == TX Byte 0 ==
6766 23:19:09.906462 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6767 23:19:09.913804 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6768 23:19:09.913903 == TX Byte 1 ==
6769 23:19:09.916750 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6770 23:19:09.923660 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6771 23:19:09.923741 ==
6772 23:19:09.926956 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 23:19:09.930190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 23:19:09.930262 ==
6775 23:19:09.930324
6776 23:19:09.930381
6777 23:19:09.933552 TX Vref Scan disable
6778 23:19:09.933623 == TX Byte 0 ==
6779 23:19:09.939456 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6780 23:19:09.942991 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6781 23:19:09.943087 == TX Byte 1 ==
6782 23:19:09.949456 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6783 23:19:09.952505 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6784 23:19:09.952601
6785 23:19:09.952694 [DATLAT]
6786 23:19:09.955967 Freq=400, CH1 RK0
6787 23:19:09.956063
6788 23:19:09.956154 DATLAT Default: 0xf
6789 23:19:09.959955 0, 0xFFFF, sum = 0
6790 23:19:09.960029 1, 0xFFFF, sum = 0
6791 23:19:09.962998 2, 0xFFFF, sum = 0
6792 23:19:09.963129 3, 0xFFFF, sum = 0
6793 23:19:09.966004 4, 0xFFFF, sum = 0
6794 23:19:09.966103 5, 0xFFFF, sum = 0
6795 23:19:09.969195 6, 0xFFFF, sum = 0
6796 23:19:09.969294 7, 0xFFFF, sum = 0
6797 23:19:09.972645 8, 0xFFFF, sum = 0
6798 23:19:09.976187 9, 0xFFFF, sum = 0
6799 23:19:09.976258 10, 0xFFFF, sum = 0
6800 23:19:09.979261 11, 0xFFFF, sum = 0
6801 23:19:09.979334 12, 0xFFFF, sum = 0
6802 23:19:09.982646 13, 0x0, sum = 1
6803 23:19:09.982746 14, 0x0, sum = 2
6804 23:19:09.985577 15, 0x0, sum = 3
6805 23:19:09.985687 16, 0x0, sum = 4
6806 23:19:09.985779 best_step = 14
6807 23:19:09.989447
6808 23:19:09.989556 ==
6809 23:19:09.992750 Dram Type= 6, Freq= 0, CH_1, rank 0
6810 23:19:09.995919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 23:19:09.996019 ==
6812 23:19:09.996109 RX Vref Scan: 1
6813 23:19:09.996207
6814 23:19:09.999254 RX Vref 0 -> 0, step: 1
6815 23:19:09.999360
6816 23:19:10.003073 RX Delay -343 -> 252, step: 8
6817 23:19:10.003174
6818 23:19:10.005656 Set Vref, RX VrefLevel [Byte0]: 46
6819 23:19:10.008489 [Byte1]: 60
6820 23:19:10.012991
6821 23:19:10.013099 Final RX Vref Byte 0 = 46 to rank0
6822 23:19:10.016173 Final RX Vref Byte 1 = 60 to rank0
6823 23:19:10.020068 Final RX Vref Byte 0 = 46 to rank1
6824 23:19:10.022912 Final RX Vref Byte 1 = 60 to rank1==
6825 23:19:10.026740 Dram Type= 6, Freq= 0, CH_1, rank 0
6826 23:19:10.032337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6827 23:19:10.032429 ==
6828 23:19:10.032494 DQS Delay:
6829 23:19:10.035593 DQS0 = 44, DQS1 = 56
6830 23:19:10.035697 DQM Delay:
6831 23:19:10.035761 DQM0 = 7, DQM1 = 12
6832 23:19:10.039189 DQ Delay:
6833 23:19:10.042678 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6834 23:19:10.042772 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =0
6835 23:19:10.045786 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6836 23:19:10.049031 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24
6837 23:19:10.049129
6838 23:19:10.052591
6839 23:19:10.059412 [DQSOSCAuto] RK0, (LSB)MR18= 0x8f65, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6840 23:19:10.062201 CH1 RK0: MR19=C0C, MR18=8F65
6841 23:19:10.068826 CH1_RK0: MR19=0xC0C, MR18=0x8F65, DQSOSC=391, MR23=63, INC=386, DEC=257
6842 23:19:10.068903 ==
6843 23:19:10.072442 Dram Type= 6, Freq= 0, CH_1, rank 1
6844 23:19:10.075405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 23:19:10.075503 ==
6846 23:19:10.078371 [Gating] SW mode calibration
6847 23:19:10.085118 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6848 23:19:10.091921 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6849 23:19:10.094906 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6850 23:19:10.098487 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6851 23:19:10.105162 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6852 23:19:10.108643 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6853 23:19:10.111475 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6854 23:19:10.118061 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6855 23:19:10.121848 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6856 23:19:10.124880 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6857 23:19:10.131089 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6858 23:19:10.135478 Total UI for P1: 0, mck2ui 16
6859 23:19:10.138156 best dqsien dly found for B0: ( 0, 14, 24)
6860 23:19:10.138265 Total UI for P1: 0, mck2ui 16
6861 23:19:10.145225 best dqsien dly found for B1: ( 0, 14, 24)
6862 23:19:10.147618 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6863 23:19:10.150935 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6864 23:19:10.151033
6865 23:19:10.154415 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6866 23:19:10.158574 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6867 23:19:10.161023 [Gating] SW calibration Done
6868 23:19:10.161118 ==
6869 23:19:10.164685 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 23:19:10.168103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 23:19:10.168174 ==
6872 23:19:10.171026 RX Vref Scan: 0
6873 23:19:10.171121
6874 23:19:10.171211 RX Vref 0 -> 0, step: 1
6875 23:19:10.174544
6876 23:19:10.174642 RX Delay -410 -> 252, step: 16
6877 23:19:10.181171 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6878 23:19:10.185023 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6879 23:19:10.187584 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6880 23:19:10.193972 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6881 23:19:10.197174 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6882 23:19:10.200829 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6883 23:19:10.203641 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6884 23:19:10.210582 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6885 23:19:10.213543 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6886 23:19:10.217040 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6887 23:19:10.220212 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6888 23:19:10.226820 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6889 23:19:10.229733 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6890 23:19:10.233287 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6891 23:19:10.236403 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6892 23:19:10.243472 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6893 23:19:10.243583 ==
6894 23:19:10.246309 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 23:19:10.250077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 23:19:10.250158 ==
6897 23:19:10.253157 DQS Delay:
6898 23:19:10.253238 DQS0 = 43, DQS1 = 59
6899 23:19:10.253305 DQM Delay:
6900 23:19:10.256427 DQM0 = 12, DQM1 = 22
6901 23:19:10.256530 DQ Delay:
6902 23:19:10.259988 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6903 23:19:10.262931 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6904 23:19:10.266732 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6905 23:19:10.269602 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6906 23:19:10.269703
6907 23:19:10.269802
6908 23:19:10.269894 ==
6909 23:19:10.273630 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 23:19:10.275972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 23:19:10.279624 ==
6912 23:19:10.279771
6913 23:19:10.279864
6914 23:19:10.279951 TX Vref Scan disable
6915 23:19:10.282666 == TX Byte 0 ==
6916 23:19:10.286946 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6917 23:19:10.289274 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6918 23:19:10.292757 == TX Byte 1 ==
6919 23:19:10.296303 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6920 23:19:10.299643 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6921 23:19:10.299784 ==
6922 23:19:10.302625 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 23:19:10.308873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 23:19:10.308985 ==
6925 23:19:10.309078
6926 23:19:10.309167
6927 23:19:10.309265 TX Vref Scan disable
6928 23:19:10.312519 == TX Byte 0 ==
6929 23:19:10.315639 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6930 23:19:10.318857 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6931 23:19:10.323156 == TX Byte 1 ==
6932 23:19:10.325719 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6933 23:19:10.328863 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6934 23:19:10.328935
6935 23:19:10.332099 [DATLAT]
6936 23:19:10.332199 Freq=400, CH1 RK1
6937 23:19:10.332289
6938 23:19:10.335910 DATLAT Default: 0xe
6939 23:19:10.335998 0, 0xFFFF, sum = 0
6940 23:19:10.339536 1, 0xFFFF, sum = 0
6941 23:19:10.339645 2, 0xFFFF, sum = 0
6942 23:19:10.342508 3, 0xFFFF, sum = 0
6943 23:19:10.342622 4, 0xFFFF, sum = 0
6944 23:19:10.346177 5, 0xFFFF, sum = 0
6945 23:19:10.346271 6, 0xFFFF, sum = 0
6946 23:19:10.348899 7, 0xFFFF, sum = 0
6947 23:19:10.349000 8, 0xFFFF, sum = 0
6948 23:19:10.352306 9, 0xFFFF, sum = 0
6949 23:19:10.355266 10, 0xFFFF, sum = 0
6950 23:19:10.355377 11, 0xFFFF, sum = 0
6951 23:19:10.358891 12, 0xFFFF, sum = 0
6952 23:19:10.359004 13, 0x0, sum = 1
6953 23:19:10.361895 14, 0x0, sum = 2
6954 23:19:10.362004 15, 0x0, sum = 3
6955 23:19:10.365480 16, 0x0, sum = 4
6956 23:19:10.365579 best_step = 14
6957 23:19:10.365681
6958 23:19:10.365767 ==
6959 23:19:10.368322 Dram Type= 6, Freq= 0, CH_1, rank 1
6960 23:19:10.371489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6961 23:19:10.371589 ==
6962 23:19:10.374703 RX Vref Scan: 0
6963 23:19:10.374773
6964 23:19:10.378526 RX Vref 0 -> 0, step: 1
6965 23:19:10.378641
6966 23:19:10.378733 RX Delay -359 -> 252, step: 8
6967 23:19:10.387407 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6968 23:19:10.390783 iDelay=217, Bit 1, Center -40 (-279 ~ 200) 480
6969 23:19:10.393624 iDelay=217, Bit 2, Center -48 (-287 ~ 192) 480
6970 23:19:10.400502 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6971 23:19:10.403828 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6972 23:19:10.406617 iDelay=217, Bit 5, Center -24 (-263 ~ 216) 480
6973 23:19:10.409820 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6974 23:19:10.417025 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6975 23:19:10.419975 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6976 23:19:10.423188 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6977 23:19:10.426479 iDelay=217, Bit 10, Center -44 (-295 ~ 208) 504
6978 23:19:10.433844 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6979 23:19:10.436295 iDelay=217, Bit 12, Center -36 (-287 ~ 216) 504
6980 23:19:10.440159 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6981 23:19:10.443616 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6982 23:19:10.449747 iDelay=217, Bit 15, Center -36 (-287 ~ 216) 504
6983 23:19:10.449826 ==
6984 23:19:10.453162 Dram Type= 6, Freq= 0, CH_1, rank 1
6985 23:19:10.456217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6986 23:19:10.456291 ==
6987 23:19:10.456356 DQS Delay:
6988 23:19:10.459527 DQS0 = 48, DQS1 = 56
6989 23:19:10.459634 DQM Delay:
6990 23:19:10.462767 DQM0 = 12, DQM1 = 11
6991 23:19:10.462865 DQ Delay:
6992 23:19:10.466456 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6993 23:19:10.470088 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6994 23:19:10.472798 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6995 23:19:10.475886 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6996 23:19:10.475959
6997 23:19:10.476033
6998 23:19:10.486001 [DQSOSCAuto] RK1, (LSB)MR18= 0x604e, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 397 ps
6999 23:19:10.486108 CH1 RK1: MR19=C0C, MR18=604E
7000 23:19:10.493031 CH1_RK1: MR19=0xC0C, MR18=0x604E, DQSOSC=397, MR23=63, INC=374, DEC=249
7001 23:19:10.496200 [RxdqsGatingPostProcess] freq 400
7002 23:19:10.502476 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7003 23:19:10.506237 best DQS0 dly(2T, 0.5T) = (0, 10)
7004 23:19:10.508936 best DQS1 dly(2T, 0.5T) = (0, 10)
7005 23:19:10.512668 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7006 23:19:10.516021 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7007 23:19:10.519004 best DQS0 dly(2T, 0.5T) = (0, 10)
7008 23:19:10.519080 best DQS1 dly(2T, 0.5T) = (0, 10)
7009 23:19:10.522422 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7010 23:19:10.525616 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7011 23:19:10.529001 Pre-setting of DQS Precalculation
7012 23:19:10.535491 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7013 23:19:10.541770 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7014 23:19:10.549032 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7015 23:19:10.549106
7016 23:19:10.549167
7017 23:19:10.551681 [Calibration Summary] 800 Mbps
7018 23:19:10.555369 CH 0, Rank 0
7019 23:19:10.555472 SW Impedance : PASS
7020 23:19:10.558410 DUTY Scan : NO K
7021 23:19:10.562442 ZQ Calibration : PASS
7022 23:19:10.562540 Jitter Meter : NO K
7023 23:19:10.564855 CBT Training : PASS
7024 23:19:10.568447 Write leveling : PASS
7025 23:19:10.568552 RX DQS gating : PASS
7026 23:19:10.572104 RX DQ/DQS(RDDQC) : PASS
7027 23:19:10.572200 TX DQ/DQS : PASS
7028 23:19:10.575798 RX DATLAT : PASS
7029 23:19:10.578773 RX DQ/DQS(Engine): PASS
7030 23:19:10.578878 TX OE : NO K
7031 23:19:10.581470 All Pass.
7032 23:19:10.581575
7033 23:19:10.581665 CH 0, Rank 1
7034 23:19:10.584561 SW Impedance : PASS
7035 23:19:10.584630 DUTY Scan : NO K
7036 23:19:10.588382 ZQ Calibration : PASS
7037 23:19:10.591421 Jitter Meter : NO K
7038 23:19:10.591518 CBT Training : PASS
7039 23:19:10.595037 Write leveling : NO K
7040 23:19:10.597913 RX DQS gating : PASS
7041 23:19:10.598009 RX DQ/DQS(RDDQC) : PASS
7042 23:19:10.601208 TX DQ/DQS : PASS
7043 23:19:10.604617 RX DATLAT : PASS
7044 23:19:10.604715 RX DQ/DQS(Engine): PASS
7045 23:19:10.607704 TX OE : NO K
7046 23:19:10.607790 All Pass.
7047 23:19:10.607849
7048 23:19:10.611470 CH 1, Rank 0
7049 23:19:10.611570 SW Impedance : PASS
7050 23:19:10.614950 DUTY Scan : NO K
7051 23:19:10.617793 ZQ Calibration : PASS
7052 23:19:10.617893 Jitter Meter : NO K
7053 23:19:10.620965 CBT Training : PASS
7054 23:19:10.624522 Write leveling : PASS
7055 23:19:10.624593 RX DQS gating : PASS
7056 23:19:10.627588 RX DQ/DQS(RDDQC) : PASS
7057 23:19:10.630796 TX DQ/DQS : PASS
7058 23:19:10.630866 RX DATLAT : PASS
7059 23:19:10.634273 RX DQ/DQS(Engine): PASS
7060 23:19:10.638148 TX OE : NO K
7061 23:19:10.638245 All Pass.
7062 23:19:10.638336
7063 23:19:10.638425 CH 1, Rank 1
7064 23:19:10.641090 SW Impedance : PASS
7065 23:19:10.644326 DUTY Scan : NO K
7066 23:19:10.644423 ZQ Calibration : PASS
7067 23:19:10.647577 Jitter Meter : NO K
7068 23:19:10.650271 CBT Training : PASS
7069 23:19:10.650367 Write leveling : NO K
7070 23:19:10.654309 RX DQS gating : PASS
7071 23:19:10.657208 RX DQ/DQS(RDDQC) : PASS
7072 23:19:10.657281 TX DQ/DQS : PASS
7073 23:19:10.660416 RX DATLAT : PASS
7074 23:19:10.660513 RX DQ/DQS(Engine): PASS
7075 23:19:10.663976 TX OE : NO K
7076 23:19:10.664048 All Pass.
7077 23:19:10.664115
7078 23:19:10.667014 DramC Write-DBI off
7079 23:19:10.670403 PER_BANK_REFRESH: Hybrid Mode
7080 23:19:10.670508 TX_TRACKING: ON
7081 23:19:10.680404 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7082 23:19:10.683437 [FAST_K] Save calibration result to emmc
7083 23:19:10.686865 dramc_set_vcore_voltage set vcore to 725000
7084 23:19:10.691101 Read voltage for 1600, 0
7085 23:19:10.691206 Vio18 = 0
7086 23:19:10.693606 Vcore = 725000
7087 23:19:10.693712 Vdram = 0
7088 23:19:10.693803 Vddq = 0
7089 23:19:10.693890 Vmddr = 0
7090 23:19:10.700550 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7091 23:19:10.706314 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7092 23:19:10.706416 MEM_TYPE=3, freq_sel=13
7093 23:19:10.709604 sv_algorithm_assistance_LP4_3733
7094 23:19:10.713403 ============ PULL DRAM RESETB DOWN ============
7095 23:19:10.719746 ========== PULL DRAM RESETB DOWN end =========
7096 23:19:10.723059 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7097 23:19:10.726677 ===================================
7098 23:19:10.729582 LPDDR4 DRAM CONFIGURATION
7099 23:19:10.733635 ===================================
7100 23:19:10.733733 EX_ROW_EN[0] = 0x0
7101 23:19:10.736548 EX_ROW_EN[1] = 0x0
7102 23:19:10.739652 LP4Y_EN = 0x0
7103 23:19:10.739734 WORK_FSP = 0x1
7104 23:19:10.742890 WL = 0x5
7105 23:19:10.742959 RL = 0x5
7106 23:19:10.746408 BL = 0x2
7107 23:19:10.746511 RPST = 0x0
7108 23:19:10.749511 RD_PRE = 0x0
7109 23:19:10.749581 WR_PRE = 0x1
7110 23:19:10.752786 WR_PST = 0x1
7111 23:19:10.752860 DBI_WR = 0x0
7112 23:19:10.755800 DBI_RD = 0x0
7113 23:19:10.755871 OTF = 0x1
7114 23:19:10.758956 ===================================
7115 23:19:10.762568 ===================================
7116 23:19:10.765910 ANA top config
7117 23:19:10.768841 ===================================
7118 23:19:10.772128 DLL_ASYNC_EN = 0
7119 23:19:10.772201 ALL_SLAVE_EN = 0
7120 23:19:10.775973 NEW_RANK_MODE = 1
7121 23:19:10.779037 DLL_IDLE_MODE = 1
7122 23:19:10.782907 LP45_APHY_COMB_EN = 1
7123 23:19:10.783007 TX_ODT_DIS = 0
7124 23:19:10.786078 NEW_8X_MODE = 1
7125 23:19:10.789005 ===================================
7126 23:19:10.792131 ===================================
7127 23:19:10.795811 data_rate = 3200
7128 23:19:10.799244 CKR = 1
7129 23:19:10.802008 DQ_P2S_RATIO = 8
7130 23:19:10.805634 ===================================
7131 23:19:10.808639 CA_P2S_RATIO = 8
7132 23:19:10.808735 DQ_CA_OPEN = 0
7133 23:19:10.811955 DQ_SEMI_OPEN = 0
7134 23:19:10.815226 CA_SEMI_OPEN = 0
7135 23:19:10.818469 CA_FULL_RATE = 0
7136 23:19:10.822518 DQ_CKDIV4_EN = 0
7137 23:19:10.825119 CA_CKDIV4_EN = 0
7138 23:19:10.825219 CA_PREDIV_EN = 0
7139 23:19:10.829192 PH8_DLY = 12
7140 23:19:10.831974 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7141 23:19:10.835773 DQ_AAMCK_DIV = 4
7142 23:19:10.838710 CA_AAMCK_DIV = 4
7143 23:19:10.842443 CA_ADMCK_DIV = 4
7144 23:19:10.842544 DQ_TRACK_CA_EN = 0
7145 23:19:10.844914 CA_PICK = 1600
7146 23:19:10.848277 CA_MCKIO = 1600
7147 23:19:10.851978 MCKIO_SEMI = 0
7148 23:19:10.854722 PLL_FREQ = 3068
7149 23:19:10.858189 DQ_UI_PI_RATIO = 32
7150 23:19:10.861791 CA_UI_PI_RATIO = 0
7151 23:19:10.864453 ===================================
7152 23:19:10.868811 ===================================
7153 23:19:10.871836 memory_type:LPDDR4
7154 23:19:10.871907 GP_NUM : 10
7155 23:19:10.874697 SRAM_EN : 1
7156 23:19:10.874793 MD32_EN : 0
7157 23:19:10.878673 ===================================
7158 23:19:10.881003 [ANA_INIT] >>>>>>>>>>>>>>
7159 23:19:10.884361 <<<<<< [CONFIGURE PHASE]: ANA_TX
7160 23:19:10.887883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7161 23:19:10.891521 ===================================
7162 23:19:10.894797 data_rate = 3200,PCW = 0X7600
7163 23:19:10.897958 ===================================
7164 23:19:10.901069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7165 23:19:10.907760 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7166 23:19:10.910752 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7167 23:19:10.917641 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7168 23:19:10.920754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7169 23:19:10.924096 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7170 23:19:10.924168 [ANA_INIT] flow start
7171 23:19:10.927181 [ANA_INIT] PLL >>>>>>>>
7172 23:19:10.930963 [ANA_INIT] PLL <<<<<<<<
7173 23:19:10.931061 [ANA_INIT] MIDPI >>>>>>>>
7174 23:19:10.933732 [ANA_INIT] MIDPI <<<<<<<<
7175 23:19:10.937108 [ANA_INIT] DLL >>>>>>>>
7176 23:19:10.940211 [ANA_INIT] DLL <<<<<<<<
7177 23:19:10.940310 [ANA_INIT] flow end
7178 23:19:10.944135 ============ LP4 DIFF to SE enter ============
7179 23:19:10.950497 ============ LP4 DIFF to SE exit ============
7180 23:19:10.950597 [ANA_INIT] <<<<<<<<<<<<<
7181 23:19:10.953837 [Flow] Enable top DCM control >>>>>
7182 23:19:10.956510 [Flow] Enable top DCM control <<<<<
7183 23:19:10.960846 Enable DLL master slave shuffle
7184 23:19:10.966948 ==============================================================
7185 23:19:10.967047 Gating Mode config
7186 23:19:10.972996 ==============================================================
7187 23:19:10.976491 Config description:
7188 23:19:10.986221 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7189 23:19:10.993049 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7190 23:19:10.997005 SELPH_MODE 0: By rank 1: By Phase
7191 23:19:11.002998 ==============================================================
7192 23:19:11.006057 GAT_TRACK_EN = 1
7193 23:19:11.009600 RX_GATING_MODE = 2
7194 23:19:11.013052 RX_GATING_TRACK_MODE = 2
7195 23:19:11.013165 SELPH_MODE = 1
7196 23:19:11.016097 PICG_EARLY_EN = 1
7197 23:19:11.019541 VALID_LAT_VALUE = 1
7198 23:19:11.025911 ==============================================================
7199 23:19:11.029023 Enter into Gating configuration >>>>
7200 23:19:11.032479 Exit from Gating configuration <<<<
7201 23:19:11.036060 Enter into DVFS_PRE_config >>>>>
7202 23:19:11.045594 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7203 23:19:11.048828 Exit from DVFS_PRE_config <<<<<
7204 23:19:11.052337 Enter into PICG configuration >>>>
7205 23:19:11.055496 Exit from PICG configuration <<<<
7206 23:19:11.059178 [RX_INPUT] configuration >>>>>
7207 23:19:11.062249 [RX_INPUT] configuration <<<<<
7208 23:19:11.068297 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7209 23:19:11.071522 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7210 23:19:11.078656 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7211 23:19:11.085192 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7212 23:19:11.091582 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7213 23:19:11.098084 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7214 23:19:11.101979 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7215 23:19:11.104896 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7216 23:19:11.107919 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7217 23:19:11.114271 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7218 23:19:11.117574 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7219 23:19:11.121047 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7220 23:19:11.124835 ===================================
7221 23:19:11.127608 LPDDR4 DRAM CONFIGURATION
7222 23:19:11.131935 ===================================
7223 23:19:11.133902 EX_ROW_EN[0] = 0x0
7224 23:19:11.133973 EX_ROW_EN[1] = 0x0
7225 23:19:11.138098 LP4Y_EN = 0x0
7226 23:19:11.138198 WORK_FSP = 0x1
7227 23:19:11.140854 WL = 0x5
7228 23:19:11.140952 RL = 0x5
7229 23:19:11.144083 BL = 0x2
7230 23:19:11.144179 RPST = 0x0
7231 23:19:11.147629 RD_PRE = 0x0
7232 23:19:11.147754 WR_PRE = 0x1
7233 23:19:11.150868 WR_PST = 0x1
7234 23:19:11.150942 DBI_WR = 0x0
7235 23:19:11.154130 DBI_RD = 0x0
7236 23:19:11.154229 OTF = 0x1
7237 23:19:11.157075 ===================================
7238 23:19:11.163589 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7239 23:19:11.168029 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7240 23:19:11.170714 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7241 23:19:11.173781 ===================================
7242 23:19:11.177386 LPDDR4 DRAM CONFIGURATION
7243 23:19:11.180512 ===================================
7244 23:19:11.183822 EX_ROW_EN[0] = 0x10
7245 23:19:11.183896 EX_ROW_EN[1] = 0x0
7246 23:19:11.186814 LP4Y_EN = 0x0
7247 23:19:11.186887 WORK_FSP = 0x1
7248 23:19:11.190295 WL = 0x5
7249 23:19:11.190393 RL = 0x5
7250 23:19:11.193087 BL = 0x2
7251 23:19:11.193184 RPST = 0x0
7252 23:19:11.196906 RD_PRE = 0x0
7253 23:19:11.197009 WR_PRE = 0x1
7254 23:19:11.200053 WR_PST = 0x1
7255 23:19:11.200150 DBI_WR = 0x0
7256 23:19:11.203369 DBI_RD = 0x0
7257 23:19:11.206307 OTF = 0x1
7258 23:19:11.209691 ===================================
7259 23:19:11.213139 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7260 23:19:11.213237 ==
7261 23:19:11.216409 Dram Type= 6, Freq= 0, CH_0, rank 0
7262 23:19:11.222788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7263 23:19:11.222867 ==
7264 23:19:11.222956 [Duty_Offset_Calibration]
7265 23:19:11.226435 B0:1 B1:-1 CA:0
7266 23:19:11.226535
7267 23:19:11.229710 [DutyScan_Calibration_Flow] k_type=0
7268 23:19:11.239749
7269 23:19:11.239830 ==CLK 0==
7270 23:19:11.242625 Final CLK duty delay cell = 0
7271 23:19:11.245976 [0] MAX Duty = 5124%(X100), DQS PI = 22
7272 23:19:11.248872 [0] MIN Duty = 4907%(X100), DQS PI = 4
7273 23:19:11.252509 [0] AVG Duty = 5015%(X100)
7274 23:19:11.252583
7275 23:19:11.255600 CH0 CLK Duty spec in!! Max-Min= 217%
7276 23:19:11.258969 [DutyScan_Calibration_Flow] ====Done====
7277 23:19:11.259046
7278 23:19:11.261942 [DutyScan_Calibration_Flow] k_type=1
7279 23:19:11.278609
7280 23:19:11.278714 ==DQS 0 ==
7281 23:19:11.281557 Final DQS duty delay cell = -4
7282 23:19:11.284866 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7283 23:19:11.288363 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7284 23:19:11.291654 [-4] AVG Duty = 4906%(X100)
7285 23:19:11.291770
7286 23:19:11.291833 ==DQS 1 ==
7287 23:19:11.295627 Final DQS duty delay cell = 0
7288 23:19:11.298143 [0] MAX Duty = 5156%(X100), DQS PI = 0
7289 23:19:11.301875 [0] MIN Duty = 5031%(X100), DQS PI = 20
7290 23:19:11.305007 [0] AVG Duty = 5093%(X100)
7291 23:19:11.305105
7292 23:19:11.308749 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7293 23:19:11.308863
7294 23:19:11.311865 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7295 23:19:11.314677 [DutyScan_Calibration_Flow] ====Done====
7296 23:19:11.314776
7297 23:19:11.317825 [DutyScan_Calibration_Flow] k_type=3
7298 23:19:11.335849
7299 23:19:11.335925 ==DQM 0 ==
7300 23:19:11.339288 Final DQM duty delay cell = 0
7301 23:19:11.342441 [0] MAX Duty = 5093%(X100), DQS PI = 18
7302 23:19:11.346181 [0] MIN Duty = 4907%(X100), DQS PI = 8
7303 23:19:11.349098 [0] AVG Duty = 5000%(X100)
7304 23:19:11.349170
7305 23:19:11.349238 ==DQM 1 ==
7306 23:19:11.352519 Final DQM duty delay cell = 0
7307 23:19:11.355768 [0] MAX Duty = 5031%(X100), DQS PI = 54
7308 23:19:11.359247 [0] MIN Duty = 4813%(X100), DQS PI = 20
7309 23:19:11.362585 [0] AVG Duty = 4922%(X100)
7310 23:19:11.362683
7311 23:19:11.365857 CH0 DQM 0 Duty spec in!! Max-Min= 186%
7312 23:19:11.365955
7313 23:19:11.369561 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7314 23:19:11.372559 [DutyScan_Calibration_Flow] ====Done====
7315 23:19:11.372656
7316 23:19:11.375833 [DutyScan_Calibration_Flow] k_type=2
7317 23:19:11.392393
7318 23:19:11.392499 ==DQ 0 ==
7319 23:19:11.395728 Final DQ duty delay cell = -4
7320 23:19:11.398991 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7321 23:19:11.402442 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7322 23:19:11.405804 [-4] AVG Duty = 4953%(X100)
7323 23:19:11.405905
7324 23:19:11.405994 ==DQ 1 ==
7325 23:19:11.408692 Final DQ duty delay cell = 0
7326 23:19:11.412414 [0] MAX Duty = 5125%(X100), DQS PI = 2
7327 23:19:11.415919 [0] MIN Duty = 5000%(X100), DQS PI = 38
7328 23:19:11.419123 [0] AVG Duty = 5062%(X100)
7329 23:19:11.419225
7330 23:19:11.422334 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7331 23:19:11.422435
7332 23:19:11.425531 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7333 23:19:11.428397 [DutyScan_Calibration_Flow] ====Done====
7334 23:19:11.428495 ==
7335 23:19:11.431885 Dram Type= 6, Freq= 0, CH_1, rank 0
7336 23:19:11.435502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7337 23:19:11.435602 ==
7338 23:19:11.438532 [Duty_Offset_Calibration]
7339 23:19:11.438630 B0:-1 B1:1 CA:2
7340 23:19:11.438724
7341 23:19:11.442020 [DutyScan_Calibration_Flow] k_type=0
7342 23:19:11.453060
7343 23:19:11.453167 ==CLK 0==
7344 23:19:11.456245 Final CLK duty delay cell = 0
7345 23:19:11.459738 [0] MAX Duty = 5187%(X100), DQS PI = 22
7346 23:19:11.462619 [0] MIN Duty = 5031%(X100), DQS PI = 32
7347 23:19:11.466251 [0] AVG Duty = 5109%(X100)
7348 23:19:11.466355
7349 23:19:11.469086 CH1 CLK Duty spec in!! Max-Min= 156%
7350 23:19:11.472983 [DutyScan_Calibration_Flow] ====Done====
7351 23:19:11.473078
7352 23:19:11.476136 [DutyScan_Calibration_Flow] k_type=1
7353 23:19:11.492552
7354 23:19:11.492665 ==DQS 0 ==
7355 23:19:11.495915 Final DQS duty delay cell = 0
7356 23:19:11.499092 [0] MAX Duty = 5156%(X100), DQS PI = 20
7357 23:19:11.502841 [0] MIN Duty = 4907%(X100), DQS PI = 40
7358 23:19:11.505731 [0] AVG Duty = 5031%(X100)
7359 23:19:11.505832
7360 23:19:11.505934 ==DQS 1 ==
7361 23:19:11.509279 Final DQS duty delay cell = 0
7362 23:19:11.512965 [0] MAX Duty = 5093%(X100), DQS PI = 6
7363 23:19:11.515895 [0] MIN Duty = 5000%(X100), DQS PI = 24
7364 23:19:11.519131 [0] AVG Duty = 5046%(X100)
7365 23:19:11.519240
7366 23:19:11.521921 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7367 23:19:11.522018
7368 23:19:11.525883 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7369 23:19:11.528809 [DutyScan_Calibration_Flow] ====Done====
7370 23:19:11.528907
7371 23:19:11.532148 [DutyScan_Calibration_Flow] k_type=3
7372 23:19:11.549729
7373 23:19:11.549828 ==DQM 0 ==
7374 23:19:11.552735 Final DQM duty delay cell = 0
7375 23:19:11.556176 [0] MAX Duty = 5187%(X100), DQS PI = 4
7376 23:19:11.560067 [0] MIN Duty = 5000%(X100), DQS PI = 42
7377 23:19:11.562670 [0] AVG Duty = 5093%(X100)
7378 23:19:11.562775
7379 23:19:11.562866 ==DQM 1 ==
7380 23:19:11.566083 Final DQM duty delay cell = 0
7381 23:19:11.569488 [0] MAX Duty = 5187%(X100), DQS PI = 34
7382 23:19:11.572713 [0] MIN Duty = 4969%(X100), DQS PI = 0
7383 23:19:11.575674 [0] AVG Duty = 5078%(X100)
7384 23:19:11.575804
7385 23:19:11.579716 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7386 23:19:11.579827
7387 23:19:11.582457 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7388 23:19:11.585299 [DutyScan_Calibration_Flow] ====Done====
7389 23:19:11.585393
7390 23:19:11.588853 [DutyScan_Calibration_Flow] k_type=2
7391 23:19:11.606560
7392 23:19:11.606662 ==DQ 0 ==
7393 23:19:11.609409 Final DQ duty delay cell = 0
7394 23:19:11.612797 [0] MAX Duty = 5156%(X100), DQS PI = 0
7395 23:19:11.616720 [0] MIN Duty = 4906%(X100), DQS PI = 40
7396 23:19:11.616816 [0] AVG Duty = 5031%(X100)
7397 23:19:11.619055
7398 23:19:11.619154 ==DQ 1 ==
7399 23:19:11.623726 Final DQ duty delay cell = 0
7400 23:19:11.626742 [0] MAX Duty = 5125%(X100), DQS PI = 40
7401 23:19:11.629344 [0] MIN Duty = 4969%(X100), DQS PI = 26
7402 23:19:11.629442 [0] AVG Duty = 5047%(X100)
7403 23:19:11.632926
7404 23:19:11.635885 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7405 23:19:11.635978
7406 23:19:11.639504 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7407 23:19:11.642005 [DutyScan_Calibration_Flow] ====Done====
7408 23:19:11.645770 nWR fixed to 30
7409 23:19:11.648748 [ModeRegInit_LP4] CH0 RK0
7410 23:19:11.648844 [ModeRegInit_LP4] CH0 RK1
7411 23:19:11.652066 [ModeRegInit_LP4] CH1 RK0
7412 23:19:11.655746 [ModeRegInit_LP4] CH1 RK1
7413 23:19:11.655836 match AC timing 5
7414 23:19:11.662230 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7415 23:19:11.665061 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7416 23:19:11.669278 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7417 23:19:11.675388 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7418 23:19:11.678913 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7419 23:19:11.679013 [MiockJmeterHQA]
7420 23:19:11.679104
7421 23:19:11.681926 [DramcMiockJmeter] u1RxGatingPI = 0
7422 23:19:11.685266 0 : 4253, 4026
7423 23:19:11.685371 4 : 4363, 4137
7424 23:19:11.689082 8 : 4252, 4027
7425 23:19:11.689185 12 : 4362, 4137
7426 23:19:11.692403 16 : 4363, 4138
7427 23:19:11.692504 20 : 4253, 4026
7428 23:19:11.692596 24 : 4252, 4027
7429 23:19:11.695937 28 : 4252, 4027
7430 23:19:11.696035 32 : 4363, 4137
7431 23:19:11.699650 36 : 4252, 4027
7432 23:19:11.699792 40 : 4363, 4137
7433 23:19:11.701693 44 : 4252, 4027
7434 23:19:11.701799 48 : 4252, 4026
7435 23:19:11.705477 52 : 4253, 4026
7436 23:19:11.705576 56 : 4255, 4030
7437 23:19:11.705666 60 : 4363, 4137
7438 23:19:11.708471 64 : 4253, 4029
7439 23:19:11.708572 68 : 4360, 4137
7440 23:19:11.711675 72 : 4250, 4026
7441 23:19:11.711805 76 : 4250, 4027
7442 23:19:11.715487 80 : 4250, 4026
7443 23:19:11.715595 84 : 4361, 4137
7444 23:19:11.718279 88 : 4250, 4026
7445 23:19:11.718381 92 : 4361, 344
7446 23:19:11.718477 96 : 4253, 0
7447 23:19:11.721833 100 : 4252, 0
7448 23:19:11.721932 104 : 4363, 0
7449 23:19:11.722035 108 : 4250, 0
7450 23:19:11.725167 112 : 4249, 0
7451 23:19:11.725272 116 : 4250, 0
7452 23:19:11.728846 120 : 4250, 0
7453 23:19:11.728955 124 : 4253, 0
7454 23:19:11.729047 128 : 4361, 0
7455 23:19:11.731311 132 : 4250, 0
7456 23:19:11.731417 136 : 4249, 0
7457 23:19:11.734965 140 : 4360, 0
7458 23:19:11.735073 144 : 4361, 0
7459 23:19:11.735166 148 : 4362, 0
7460 23:19:11.738387 152 : 4252, 0
7461 23:19:11.738494 156 : 4360, 0
7462 23:19:11.742098 160 : 4250, 0
7463 23:19:11.742208 164 : 4249, 0
7464 23:19:11.742303 168 : 4250, 0
7465 23:19:11.744600 172 : 4250, 0
7466 23:19:11.744701 176 : 4252, 0
7467 23:19:11.748039 180 : 4361, 0
7468 23:19:11.748113 184 : 4250, 0
7469 23:19:11.748200 188 : 4361, 0
7470 23:19:11.751853 192 : 4360, 0
7471 23:19:11.751951 196 : 4361, 0
7472 23:19:11.752045 200 : 4363, 0
7473 23:19:11.754970 204 : 4250, 0
7474 23:19:11.755068 208 : 4250, 0
7475 23:19:11.757713 212 : 4362, 0
7476 23:19:11.757810 216 : 4250, 0
7477 23:19:11.757900 220 : 4253, 0
7478 23:19:11.761341 224 : 4250, 257
7479 23:19:11.761438 228 : 4361, 3423
7480 23:19:11.764672 232 : 4250, 4027
7481 23:19:11.764742 236 : 4360, 4138
7482 23:19:11.767995 240 : 4249, 4027
7483 23:19:11.768064 244 : 4250, 4026
7484 23:19:11.771066 248 : 4250, 4027
7485 23:19:11.771177 252 : 4252, 4030
7486 23:19:11.774323 256 : 4250, 4027
7487 23:19:11.774421 260 : 4250, 4026
7488 23:19:11.777800 264 : 4250, 4027
7489 23:19:11.777898 268 : 4252, 4030
7490 23:19:11.780812 272 : 4249, 4027
7491 23:19:11.780918 276 : 4361, 4137
7492 23:19:11.784404 280 : 4361, 4137
7493 23:19:11.784504 284 : 4250, 4027
7494 23:19:11.784600 288 : 4360, 4138
7495 23:19:11.787917 292 : 4361, 4137
7496 23:19:11.788026 296 : 4250, 4026
7497 23:19:11.791144 300 : 4250, 4027
7498 23:19:11.791253 304 : 4252, 4030
7499 23:19:11.794467 308 : 4250, 4026
7500 23:19:11.794572 312 : 4250, 4026
7501 23:19:11.797268 316 : 4250, 4027
7502 23:19:11.797370 320 : 4250, 4027
7503 23:19:11.801117 324 : 4250, 4026
7504 23:19:11.801217 328 : 4361, 4137
7505 23:19:11.803923 332 : 4361, 4137
7506 23:19:11.804022 336 : 4250, 3680
7507 23:19:11.808030 340 : 4363, 1692
7508 23:19:11.808101
7509 23:19:11.808168 MIOCK jitter meter ch=0
7510 23:19:11.808229
7511 23:19:11.810487 1T = (340-92) = 248 dly cells
7512 23:19:11.816861 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7513 23:19:11.816933 ==
7514 23:19:11.821116 Dram Type= 6, Freq= 0, CH_0, rank 0
7515 23:19:11.823802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7516 23:19:11.823901 ==
7517 23:19:11.831197 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7518 23:19:11.833824 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7519 23:19:11.837005 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7520 23:19:11.844410 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7521 23:19:11.853386 [CA 0] Center 43 (13~74) winsize 62
7522 23:19:11.856783 [CA 1] Center 43 (13~74) winsize 62
7523 23:19:11.859800 [CA 2] Center 39 (10~69) winsize 60
7524 23:19:11.862897 [CA 3] Center 38 (9~68) winsize 60
7525 23:19:11.866181 [CA 4] Center 37 (8~66) winsize 59
7526 23:19:11.870696 [CA 5] Center 36 (7~66) winsize 60
7527 23:19:11.870781
7528 23:19:11.873342 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7529 23:19:11.873439
7530 23:19:11.879616 [CATrainingPosCal] consider 1 rank data
7531 23:19:11.879759 u2DelayCellTimex100 = 262/100 ps
7532 23:19:11.886636 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7533 23:19:11.889344 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7534 23:19:11.892924 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7535 23:19:11.896170 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7536 23:19:11.899342 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7537 23:19:11.902859 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7538 23:19:11.902963
7539 23:19:11.905997 CA PerBit enable=1, Macro0, CA PI delay=36
7540 23:19:11.906093
7541 23:19:11.908994 [CBTSetCACLKResult] CA Dly = 36
7542 23:19:11.912580 CS Dly: 11 (0~42)
7543 23:19:11.916210 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7544 23:19:11.919250 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7545 23:19:11.919327 ==
7546 23:19:11.922165 Dram Type= 6, Freq= 0, CH_0, rank 1
7547 23:19:11.929517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7548 23:19:11.929622 ==
7549 23:19:11.932412 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7550 23:19:11.938904 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7551 23:19:11.942866 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7552 23:19:11.949134 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7553 23:19:11.957135 [CA 0] Center 43 (13~74) winsize 62
7554 23:19:11.960598 [CA 1] Center 44 (14~74) winsize 61
7555 23:19:11.963676 [CA 2] Center 38 (9~68) winsize 60
7556 23:19:11.967748 [CA 3] Center 38 (9~68) winsize 60
7557 23:19:11.970141 [CA 4] Center 36 (7~66) winsize 60
7558 23:19:11.973771 [CA 5] Center 36 (6~66) winsize 61
7559 23:19:11.973872
7560 23:19:11.977041 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7561 23:19:11.977140
7562 23:19:11.983336 [CATrainingPosCal] consider 2 rank data
7563 23:19:11.983439 u2DelayCellTimex100 = 262/100 ps
7564 23:19:11.989884 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7565 23:19:11.993078 CA1 delay=44 (14~74),Diff = 8 PI (29 cell)
7566 23:19:11.996252 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7567 23:19:11.999639 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7568 23:19:12.002565 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7569 23:19:12.006590 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7570 23:19:12.006691
7571 23:19:12.009623 CA PerBit enable=1, Macro0, CA PI delay=36
7572 23:19:12.009724
7573 23:19:12.012572 [CBTSetCACLKResult] CA Dly = 36
7574 23:19:12.016308 CS Dly: 12 (0~44)
7575 23:19:12.019305 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7576 23:19:12.022443 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7577 23:19:12.022539
7578 23:19:12.026256 ----->DramcWriteLeveling(PI) begin...
7579 23:19:12.029382 ==
7580 23:19:12.032396 Dram Type= 6, Freq= 0, CH_0, rank 0
7581 23:19:12.035998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7582 23:19:12.036099 ==
7583 23:19:12.038827 Write leveling (Byte 0): 35 => 35
7584 23:19:12.043010 Write leveling (Byte 1): 27 => 27
7585 23:19:12.046135 DramcWriteLeveling(PI) end<-----
7586 23:19:12.046234
7587 23:19:12.046323 ==
7588 23:19:12.049280 Dram Type= 6, Freq= 0, CH_0, rank 0
7589 23:19:12.052120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7590 23:19:12.052190 ==
7591 23:19:12.055989 [Gating] SW mode calibration
7592 23:19:12.062136 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7593 23:19:12.069264 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7594 23:19:12.072765 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 23:19:12.075915 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 23:19:12.081960 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 23:19:12.085265 1 4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7598 23:19:12.088479 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7599 23:19:12.095167 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7600 23:19:12.098613 1 4 24 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
7601 23:19:12.101986 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7602 23:19:12.108421 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7603 23:19:12.111308 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7604 23:19:12.114845 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7605 23:19:12.121184 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
7606 23:19:12.124510 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7607 23:19:12.128160 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7608 23:19:12.134269 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7609 23:19:12.137910 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 23:19:12.141028 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 23:19:12.147777 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 23:19:12.150962 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 23:19:12.154337 1 6 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7614 23:19:12.160782 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7615 23:19:12.164594 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7616 23:19:12.167394 1 6 24 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7617 23:19:12.174130 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 23:19:12.177302 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 23:19:12.180768 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 23:19:12.187460 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 23:19:12.190536 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7622 23:19:12.194249 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7623 23:19:12.200431 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7624 23:19:12.203852 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7625 23:19:12.206775 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 23:19:12.214113 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 23:19:12.216750 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 23:19:12.220426 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 23:19:12.227041 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 23:19:12.230090 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 23:19:12.233501 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 23:19:12.240284 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 23:19:12.242975 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 23:19:12.246586 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 23:19:12.253180 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 23:19:12.256185 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7637 23:19:12.259732 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7638 23:19:12.266126 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7639 23:19:12.266231 Total UI for P1: 0, mck2ui 16
7640 23:19:12.272513 best dqsien dly found for B0: ( 1, 9, 10)
7641 23:19:12.276147 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7642 23:19:12.279474 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7643 23:19:12.285978 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 23:19:12.286078 Total UI for P1: 0, mck2ui 16
7645 23:19:12.293128 best dqsien dly found for B1: ( 1, 9, 20)
7646 23:19:12.295900 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7647 23:19:12.299254 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7648 23:19:12.299351
7649 23:19:12.302729 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7650 23:19:12.305686 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7651 23:19:12.309023 [Gating] SW calibration Done
7652 23:19:12.309121 ==
7653 23:19:12.312346 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 23:19:12.315577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 23:19:12.315701 ==
7656 23:19:12.319059 RX Vref Scan: 0
7657 23:19:12.319153
7658 23:19:12.322723 RX Vref 0 -> 0, step: 1
7659 23:19:12.322819
7660 23:19:12.322908 RX Delay 0 -> 252, step: 8
7661 23:19:12.328500 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7662 23:19:12.332059 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7663 23:19:12.335298 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7664 23:19:12.338287 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7665 23:19:12.341626 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7666 23:19:12.348788 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7667 23:19:12.351886 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7668 23:19:12.354768 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7669 23:19:12.358244 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7670 23:19:12.361574 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7671 23:19:12.369339 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7672 23:19:12.371392 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7673 23:19:12.375083 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7674 23:19:12.377649 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7675 23:19:12.384413 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7676 23:19:12.387934 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7677 23:19:12.388041 ==
7678 23:19:12.391525 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 23:19:12.394480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 23:19:12.394579 ==
7681 23:19:12.397861 DQS Delay:
7682 23:19:12.397960 DQS0 = 0, DQS1 = 0
7683 23:19:12.398051 DQM Delay:
7684 23:19:12.401065 DQM0 = 135, DQM1 = 127
7685 23:19:12.401159 DQ Delay:
7686 23:19:12.404755 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7687 23:19:12.407590 DQ4 =135, DQ5 =123, DQ6 =143, DQ7 =147
7688 23:19:12.410720 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7689 23:19:12.417347 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7690 23:19:12.417446
7691 23:19:12.417538
7692 23:19:12.417625 ==
7693 23:19:12.421051 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 23:19:12.424307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 23:19:12.424386 ==
7696 23:19:12.424477
7697 23:19:12.424565
7698 23:19:12.428039 TX Vref Scan disable
7699 23:19:12.428138 == TX Byte 0 ==
7700 23:19:12.434125 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7701 23:19:12.437358 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7702 23:19:12.441067 == TX Byte 1 ==
7703 23:19:12.444125 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7704 23:19:12.447026 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7705 23:19:12.447125 ==
7706 23:19:12.450403 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 23:19:12.453680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 23:19:12.453781 ==
7709 23:19:12.469218
7710 23:19:12.472315 TX Vref early break, caculate TX vref
7711 23:19:12.475932 TX Vref=16, minBit 0, minWin=23, winSum=376
7712 23:19:12.478592 TX Vref=18, minBit 6, minWin=23, winSum=381
7713 23:19:12.481972 TX Vref=20, minBit 3, minWin=23, winSum=389
7714 23:19:12.485575 TX Vref=22, minBit 3, minWin=24, winSum=403
7715 23:19:12.488827 TX Vref=24, minBit 7, minWin=24, winSum=407
7716 23:19:12.494950 TX Vref=26, minBit 0, minWin=25, winSum=416
7717 23:19:12.498239 TX Vref=28, minBit 4, minWin=25, winSum=418
7718 23:19:12.501773 TX Vref=30, minBit 0, minWin=24, winSum=409
7719 23:19:12.505217 TX Vref=32, minBit 4, minWin=23, winSum=397
7720 23:19:12.508277 TX Vref=34, minBit 4, minWin=23, winSum=388
7721 23:19:12.514538 [TxChooseVref] Worse bit 4, Min win 25, Win sum 418, Final Vref 28
7722 23:19:12.514641
7723 23:19:12.518504 Final TX Range 0 Vref 28
7724 23:19:12.518580
7725 23:19:12.518676 ==
7726 23:19:12.521533 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 23:19:12.525224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 23:19:12.525331 ==
7729 23:19:12.525436
7730 23:19:12.525526
7731 23:19:12.528572 TX Vref Scan disable
7732 23:19:12.534722 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7733 23:19:12.534827 == TX Byte 0 ==
7734 23:19:12.538422 u2DelayCellOfst[0]=11 cells (3 PI)
7735 23:19:12.541174 u2DelayCellOfst[1]=14 cells (4 PI)
7736 23:19:12.544680 u2DelayCellOfst[2]=11 cells (3 PI)
7737 23:19:12.548190 u2DelayCellOfst[3]=11 cells (3 PI)
7738 23:19:12.551002 u2DelayCellOfst[4]=7 cells (2 PI)
7739 23:19:12.554296 u2DelayCellOfst[5]=0 cells (0 PI)
7740 23:19:12.557595 u2DelayCellOfst[6]=18 cells (5 PI)
7741 23:19:12.560902 u2DelayCellOfst[7]=18 cells (5 PI)
7742 23:19:12.564450 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7743 23:19:12.567324 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7744 23:19:12.571326 == TX Byte 1 ==
7745 23:19:12.574208 u2DelayCellOfst[8]=0 cells (0 PI)
7746 23:19:12.577382 u2DelayCellOfst[9]=0 cells (0 PI)
7747 23:19:12.577487 u2DelayCellOfst[10]=3 cells (1 PI)
7748 23:19:12.580806 u2DelayCellOfst[11]=0 cells (0 PI)
7749 23:19:12.584340 u2DelayCellOfst[12]=11 cells (3 PI)
7750 23:19:12.587616 u2DelayCellOfst[13]=11 cells (3 PI)
7751 23:19:12.590560 u2DelayCellOfst[14]=14 cells (4 PI)
7752 23:19:12.593993 u2DelayCellOfst[15]=11 cells (3 PI)
7753 23:19:12.600711 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7754 23:19:12.603941 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7755 23:19:12.604043 DramC Write-DBI on
7756 23:19:12.604146 ==
7757 23:19:12.607357 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 23:19:12.613987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 23:19:12.614091 ==
7760 23:19:12.614184
7761 23:19:12.614272
7762 23:19:12.617753 TX Vref Scan disable
7763 23:19:12.617826 == TX Byte 0 ==
7764 23:19:12.623513 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7765 23:19:12.623620 == TX Byte 1 ==
7766 23:19:12.627111 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7767 23:19:12.629979 DramC Write-DBI off
7768 23:19:12.630079
7769 23:19:12.630172 [DATLAT]
7770 23:19:12.633486 Freq=1600, CH0 RK0
7771 23:19:12.633584
7772 23:19:12.633676 DATLAT Default: 0xf
7773 23:19:12.636611 0, 0xFFFF, sum = 0
7774 23:19:12.636714 1, 0xFFFF, sum = 0
7775 23:19:12.640094 2, 0xFFFF, sum = 0
7776 23:19:12.640195 3, 0xFFFF, sum = 0
7777 23:19:12.643120 4, 0xFFFF, sum = 0
7778 23:19:12.643222 5, 0xFFFF, sum = 0
7779 23:19:12.646280 6, 0xFFFF, sum = 0
7780 23:19:12.650355 7, 0xFFFF, sum = 0
7781 23:19:12.650458 8, 0xFFFF, sum = 0
7782 23:19:12.653424 9, 0xFFFF, sum = 0
7783 23:19:12.653529 10, 0xFFFF, sum = 0
7784 23:19:12.656915 11, 0xFFFF, sum = 0
7785 23:19:12.656993 12, 0xFFFF, sum = 0
7786 23:19:12.659979 13, 0xFFFF, sum = 0
7787 23:19:12.660052 14, 0x0, sum = 1
7788 23:19:12.663424 15, 0x0, sum = 2
7789 23:19:12.663525 16, 0x0, sum = 3
7790 23:19:12.666180 17, 0x0, sum = 4
7791 23:19:12.666281 best_step = 15
7792 23:19:12.666375
7793 23:19:12.666462 ==
7794 23:19:12.669474 Dram Type= 6, Freq= 0, CH_0, rank 0
7795 23:19:12.676087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7796 23:19:12.676175 ==
7797 23:19:12.676240 RX Vref Scan: 1
7798 23:19:12.676301
7799 23:19:12.679273 Set Vref Range= 24 -> 127
7800 23:19:12.679375
7801 23:19:12.682601 RX Vref 24 -> 127, step: 1
7802 23:19:12.682699
7803 23:19:12.682806 RX Delay 19 -> 252, step: 4
7804 23:19:12.682914
7805 23:19:12.685626 Set Vref, RX VrefLevel [Byte0]: 24
7806 23:19:12.689025 [Byte1]: 24
7807 23:19:12.693693
7808 23:19:12.693803 Set Vref, RX VrefLevel [Byte0]: 25
7809 23:19:12.700129 [Byte1]: 25
7810 23:19:12.700240
7811 23:19:12.703004 Set Vref, RX VrefLevel [Byte0]: 26
7812 23:19:12.706481 [Byte1]: 26
7813 23:19:12.706590
7814 23:19:12.709483 Set Vref, RX VrefLevel [Byte0]: 27
7815 23:19:12.713111 [Byte1]: 27
7816 23:19:12.713213
7817 23:19:12.716297 Set Vref, RX VrefLevel [Byte0]: 28
7818 23:19:12.719469 [Byte1]: 28
7819 23:19:12.723871
7820 23:19:12.723944 Set Vref, RX VrefLevel [Byte0]: 29
7821 23:19:12.726834 [Byte1]: 29
7822 23:19:12.731057
7823 23:19:12.731166 Set Vref, RX VrefLevel [Byte0]: 30
7824 23:19:12.734659 [Byte1]: 30
7825 23:19:12.738928
7826 23:19:12.739031 Set Vref, RX VrefLevel [Byte0]: 31
7827 23:19:12.742187 [Byte1]: 31
7828 23:19:12.746352
7829 23:19:12.746455 Set Vref, RX VrefLevel [Byte0]: 32
7830 23:19:12.749118 [Byte1]: 32
7831 23:19:12.753896
7832 23:19:12.753970 Set Vref, RX VrefLevel [Byte0]: 33
7833 23:19:12.756818 [Byte1]: 33
7834 23:19:12.761294
7835 23:19:12.761397 Set Vref, RX VrefLevel [Byte0]: 34
7836 23:19:12.764817 [Byte1]: 34
7837 23:19:12.768756
7838 23:19:12.768854 Set Vref, RX VrefLevel [Byte0]: 35
7839 23:19:12.772702 [Byte1]: 35
7840 23:19:12.776333
7841 23:19:12.776419 Set Vref, RX VrefLevel [Byte0]: 36
7842 23:19:12.780066 [Byte1]: 36
7843 23:19:12.784418
7844 23:19:12.784509 Set Vref, RX VrefLevel [Byte0]: 37
7845 23:19:12.788239 [Byte1]: 37
7846 23:19:12.791615
7847 23:19:12.791733 Set Vref, RX VrefLevel [Byte0]: 38
7848 23:19:12.794975 [Byte1]: 38
7849 23:19:12.800215
7850 23:19:12.800314 Set Vref, RX VrefLevel [Byte0]: 39
7851 23:19:12.802677 [Byte1]: 39
7852 23:19:12.806705
7853 23:19:12.806807 Set Vref, RX VrefLevel [Byte0]: 40
7854 23:19:12.810758 [Byte1]: 40
7855 23:19:12.815194
7856 23:19:12.815294 Set Vref, RX VrefLevel [Byte0]: 41
7857 23:19:12.818508 [Byte1]: 41
7858 23:19:12.821821
7859 23:19:12.821921 Set Vref, RX VrefLevel [Byte0]: 42
7860 23:19:12.825225 [Byte1]: 42
7861 23:19:12.829594
7862 23:19:12.829697 Set Vref, RX VrefLevel [Byte0]: 43
7863 23:19:12.832788 [Byte1]: 43
7864 23:19:12.837476
7865 23:19:12.837578 Set Vref, RX VrefLevel [Byte0]: 44
7866 23:19:12.840543 [Byte1]: 44
7867 23:19:12.844958
7868 23:19:12.845061 Set Vref, RX VrefLevel [Byte0]: 45
7869 23:19:12.848106 [Byte1]: 45
7870 23:19:12.852331
7871 23:19:12.852433 Set Vref, RX VrefLevel [Byte0]: 46
7872 23:19:12.855202 [Byte1]: 46
7873 23:19:12.859800
7874 23:19:12.859900 Set Vref, RX VrefLevel [Byte0]: 47
7875 23:19:12.862918 [Byte1]: 47
7876 23:19:12.867915
7877 23:19:12.868015 Set Vref, RX VrefLevel [Byte0]: 48
7878 23:19:12.870498 [Byte1]: 48
7879 23:19:12.875211
7880 23:19:12.875316 Set Vref, RX VrefLevel [Byte0]: 49
7881 23:19:12.878140 [Byte1]: 49
7882 23:19:12.882619
7883 23:19:12.882728 Set Vref, RX VrefLevel [Byte0]: 50
7884 23:19:12.885566 [Byte1]: 50
7885 23:19:12.890500
7886 23:19:12.890605 Set Vref, RX VrefLevel [Byte0]: 51
7887 23:19:12.893208 [Byte1]: 51
7888 23:19:12.897609
7889 23:19:12.897711 Set Vref, RX VrefLevel [Byte0]: 52
7890 23:19:12.900826 [Byte1]: 52
7891 23:19:12.905285
7892 23:19:12.905383 Set Vref, RX VrefLevel [Byte0]: 53
7893 23:19:12.909184 [Byte1]: 53
7894 23:19:12.912914
7895 23:19:12.912985 Set Vref, RX VrefLevel [Byte0]: 54
7896 23:19:12.916097 [Byte1]: 54
7897 23:19:12.920648
7898 23:19:12.920718 Set Vref, RX VrefLevel [Byte0]: 55
7899 23:19:12.923591 [Byte1]: 55
7900 23:19:12.928145
7901 23:19:12.928249 Set Vref, RX VrefLevel [Byte0]: 56
7902 23:19:12.931014 [Byte1]: 56
7903 23:19:12.935510
7904 23:19:12.935618 Set Vref, RX VrefLevel [Byte0]: 57
7905 23:19:12.939160 [Byte1]: 57
7906 23:19:12.943341
7907 23:19:12.943440 Set Vref, RX VrefLevel [Byte0]: 58
7908 23:19:12.946691 [Byte1]: 58
7909 23:19:12.950809
7910 23:19:12.950901 Set Vref, RX VrefLevel [Byte0]: 59
7911 23:19:12.954337 [Byte1]: 59
7912 23:19:12.958605
7913 23:19:12.958706 Set Vref, RX VrefLevel [Byte0]: 60
7914 23:19:12.961486 [Byte1]: 60
7915 23:19:12.965774
7916 23:19:12.965873 Set Vref, RX VrefLevel [Byte0]: 61
7917 23:19:12.969142 [Byte1]: 61
7918 23:19:12.973801
7919 23:19:12.973908 Set Vref, RX VrefLevel [Byte0]: 62
7920 23:19:12.976695 [Byte1]: 62
7921 23:19:12.980735
7922 23:19:12.980834 Set Vref, RX VrefLevel [Byte0]: 63
7923 23:19:12.984327 [Byte1]: 63
7924 23:19:12.988285
7925 23:19:12.988374 Set Vref, RX VrefLevel [Byte0]: 64
7926 23:19:12.991762 [Byte1]: 64
7927 23:19:12.996404
7928 23:19:12.996477 Set Vref, RX VrefLevel [Byte0]: 65
7929 23:19:12.999822 [Byte1]: 65
7930 23:19:13.004063
7931 23:19:13.004133 Set Vref, RX VrefLevel [Byte0]: 66
7932 23:19:13.007266 [Byte1]: 66
7933 23:19:13.010971
7934 23:19:13.011079 Set Vref, RX VrefLevel [Byte0]: 67
7935 23:19:13.014755 [Byte1]: 67
7936 23:19:13.018625
7937 23:19:13.018726 Set Vref, RX VrefLevel [Byte0]: 68
7938 23:19:13.022233 [Byte1]: 68
7939 23:19:13.026944
7940 23:19:13.027043 Set Vref, RX VrefLevel [Byte0]: 69
7941 23:19:13.029631 [Byte1]: 69
7942 23:19:13.033965
7943 23:19:13.034064 Set Vref, RX VrefLevel [Byte0]: 70
7944 23:19:13.037483 [Byte1]: 70
7945 23:19:13.041627
7946 23:19:13.041727 Set Vref, RX VrefLevel [Byte0]: 71
7947 23:19:13.044718 [Byte1]: 71
7948 23:19:13.048820
7949 23:19:13.048894 Set Vref, RX VrefLevel [Byte0]: 72
7950 23:19:13.052476 [Byte1]: 72
7951 23:19:13.057410
7952 23:19:13.057516 Set Vref, RX VrefLevel [Byte0]: 73
7953 23:19:13.060095 [Byte1]: 73
7954 23:19:13.064030
7955 23:19:13.064105 Set Vref, RX VrefLevel [Byte0]: 74
7956 23:19:13.067817 [Byte1]: 74
7957 23:19:13.071769
7958 23:19:13.071843 Set Vref, RX VrefLevel [Byte0]: 75
7959 23:19:13.074879 [Byte1]: 75
7960 23:19:13.079804
7961 23:19:13.079903 Set Vref, RX VrefLevel [Byte0]: 76
7962 23:19:13.082531 [Byte1]: 76
7963 23:19:13.087099
7964 23:19:13.087201 Set Vref, RX VrefLevel [Byte0]: 77
7965 23:19:13.090620 [Byte1]: 77
7966 23:19:13.094582
7967 23:19:13.094670 Set Vref, RX VrefLevel [Byte0]: 78
7968 23:19:13.098089 [Byte1]: 78
7969 23:19:13.102185
7970 23:19:13.102287 Set Vref, RX VrefLevel [Byte0]: 79
7971 23:19:13.105853 [Byte1]: 79
7972 23:19:13.109782
7973 23:19:13.109880 Final RX Vref Byte 0 = 60 to rank0
7974 23:19:13.112872 Final RX Vref Byte 1 = 61 to rank0
7975 23:19:13.116213 Final RX Vref Byte 0 = 60 to rank1
7976 23:19:13.119651 Final RX Vref Byte 1 = 61 to rank1==
7977 23:19:13.122844 Dram Type= 6, Freq= 0, CH_0, rank 0
7978 23:19:13.129550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 23:19:13.129625 ==
7980 23:19:13.129694 DQS Delay:
7981 23:19:13.132514 DQS0 = 0, DQS1 = 0
7982 23:19:13.132589 DQM Delay:
7983 23:19:13.132654 DQM0 = 132, DQM1 = 123
7984 23:19:13.136163 DQ Delay:
7985 23:19:13.139753 DQ0 =130, DQ1 =132, DQ2 =128, DQ3 =130
7986 23:19:13.142769 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =142
7987 23:19:13.146210 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
7988 23:19:13.149441 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128
7989 23:19:13.149543
7990 23:19:13.149638
7991 23:19:13.149728
7992 23:19:13.152561 [DramC_TX_OE_Calibration] TA2
7993 23:19:13.155619 Original DQ_B0 (3 6) =30, OEN = 27
7994 23:19:13.159586 Original DQ_B1 (3 6) =30, OEN = 27
7995 23:19:13.162151 24, 0x0, End_B0=24 End_B1=24
7996 23:19:13.165460 25, 0x0, End_B0=25 End_B1=25
7997 23:19:13.165562 26, 0x0, End_B0=26 End_B1=26
7998 23:19:13.169432 27, 0x0, End_B0=27 End_B1=27
7999 23:19:13.172212 28, 0x0, End_B0=28 End_B1=28
8000 23:19:13.175297 29, 0x0, End_B0=29 End_B1=29
8001 23:19:13.175394 30, 0x0, End_B0=30 End_B1=30
8002 23:19:13.178841 31, 0x4141, End_B0=30 End_B1=30
8003 23:19:13.182363 Byte0 end_step=30 best_step=27
8004 23:19:13.186364 Byte1 end_step=30 best_step=27
8005 23:19:13.189351 Byte0 TX OE(2T, 0.5T) = (3, 3)
8006 23:19:13.192081 Byte1 TX OE(2T, 0.5T) = (3, 3)
8007 23:19:13.192162
8008 23:19:13.192235
8009 23:19:13.198439 [DQSOSCAuto] RK0, (LSB)MR18= 0x2011, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
8010 23:19:13.201715 CH0 RK0: MR19=303, MR18=2011
8011 23:19:13.208529 CH0_RK0: MR19=0x303, MR18=0x2011, DQSOSC=393, MR23=63, INC=23, DEC=15
8012 23:19:13.208622
8013 23:19:13.211660 ----->DramcWriteLeveling(PI) begin...
8014 23:19:13.211810 ==
8015 23:19:13.214942 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 23:19:13.218540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 23:19:13.218645 ==
8018 23:19:13.222248 Write leveling (Byte 0): 33 => 33
8019 23:19:13.224913 Write leveling (Byte 1): 30 => 30
8020 23:19:13.228457 DramcWriteLeveling(PI) end<-----
8021 23:19:13.228557
8022 23:19:13.228658 ==
8023 23:19:13.231758 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 23:19:13.234785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 23:19:13.238182 ==
8026 23:19:13.238278 [Gating] SW mode calibration
8027 23:19:13.248680 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8028 23:19:13.251839 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8029 23:19:13.254785 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 23:19:13.261572 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 23:19:13.264273 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 23:19:13.271244 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 23:19:13.274083 1 4 16 | B1->B0 | 2323 3333 | 1 1 | (0 0) (1 1)
8034 23:19:13.277629 1 4 20 | B1->B0 | 3231 3434 | 1 1 | (1 1) (1 1)
8035 23:19:13.284375 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8036 23:19:13.287090 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 23:19:13.290881 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 23:19:13.297365 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8039 23:19:13.300400 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8040 23:19:13.304293 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8041 23:19:13.307090 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
8042 23:19:13.314673 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8043 23:19:13.317216 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 23:19:13.320519 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 23:19:13.327374 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 23:19:13.330659 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 23:19:13.334149 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 23:19:13.340214 1 6 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8049 23:19:13.343642 1 6 16 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
8050 23:19:13.346685 1 6 20 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
8051 23:19:13.353326 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 23:19:13.356481 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 23:19:13.363134 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 23:19:13.366533 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 23:19:13.370250 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 23:19:13.373442 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8057 23:19:13.380015 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8058 23:19:13.383228 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 23:19:13.386367 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 23:19:13.393730 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 23:19:13.396314 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 23:19:13.399807 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 23:19:13.406013 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 23:19:13.409706 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 23:19:13.415849 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 23:19:13.420256 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 23:19:13.422911 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 23:19:13.429232 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 23:19:13.432885 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 23:19:13.435620 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 23:19:13.442092 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8072 23:19:13.445428 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8073 23:19:13.449043 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8074 23:19:13.455327 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8075 23:19:13.455436 Total UI for P1: 0, mck2ui 16
8076 23:19:13.458708 best dqsien dly found for B0: ( 1, 9, 12)
8077 23:19:13.465288 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 23:19:13.468757 Total UI for P1: 0, mck2ui 16
8079 23:19:13.471929 best dqsien dly found for B1: ( 1, 9, 20)
8080 23:19:13.475485 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8081 23:19:13.478212 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8082 23:19:13.478310
8083 23:19:13.481867 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8084 23:19:13.485526 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8085 23:19:13.488392 [Gating] SW calibration Done
8086 23:19:13.488495 ==
8087 23:19:13.491930 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 23:19:13.494955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 23:19:13.498491 ==
8090 23:19:13.498599 RX Vref Scan: 0
8091 23:19:13.498695
8092 23:19:13.501951 RX Vref 0 -> 0, step: 1
8093 23:19:13.502049
8094 23:19:13.504678 RX Delay 0 -> 252, step: 8
8095 23:19:13.507940 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8096 23:19:13.511582 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8097 23:19:13.514742 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8098 23:19:13.517872 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8099 23:19:13.524251 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8100 23:19:13.528183 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8101 23:19:13.531134 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8102 23:19:13.534487 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8103 23:19:13.537905 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8104 23:19:13.544261 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8105 23:19:13.547937 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8106 23:19:13.550910 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8107 23:19:13.554787 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8108 23:19:13.561025 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8109 23:19:13.563908 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8110 23:19:13.567564 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8111 23:19:13.567788 ==
8112 23:19:13.570342 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 23:19:13.573935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 23:19:13.574038 ==
8115 23:19:13.577005 DQS Delay:
8116 23:19:13.577113 DQS0 = 0, DQS1 = 0
8117 23:19:13.580592 DQM Delay:
8118 23:19:13.580737 DQM0 = 133, DQM1 = 127
8119 23:19:13.583586 DQ Delay:
8120 23:19:13.586594 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
8121 23:19:13.590361 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8122 23:19:13.593607 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8123 23:19:13.596759 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8124 23:19:13.596928
8125 23:19:13.597057
8126 23:19:13.597158 ==
8127 23:19:13.599843 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 23:19:13.603705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 23:19:13.603831 ==
8130 23:19:13.603964
8131 23:19:13.606328
8132 23:19:13.606428 TX Vref Scan disable
8133 23:19:13.610176 == TX Byte 0 ==
8134 23:19:13.612889 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8135 23:19:13.616610 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8136 23:19:13.619722 == TX Byte 1 ==
8137 23:19:13.623197 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8138 23:19:13.626973 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8139 23:19:13.627083 ==
8140 23:19:13.629743 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 23:19:13.636364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 23:19:13.636481 ==
8143 23:19:13.648318
8144 23:19:13.651506 TX Vref early break, caculate TX vref
8145 23:19:13.654462 TX Vref=16, minBit 1, minWin=22, winSum=378
8146 23:19:13.657825 TX Vref=18, minBit 1, minWin=23, winSum=388
8147 23:19:13.661586 TX Vref=20, minBit 1, minWin=23, winSum=399
8148 23:19:13.664869 TX Vref=22, minBit 1, minWin=24, winSum=406
8149 23:19:13.667597 TX Vref=24, minBit 1, minWin=24, winSum=412
8150 23:19:13.675056 TX Vref=26, minBit 1, minWin=24, winSum=418
8151 23:19:13.677872 TX Vref=28, minBit 4, minWin=24, winSum=417
8152 23:19:13.681091 TX Vref=30, minBit 4, minWin=24, winSum=406
8153 23:19:13.685045 TX Vref=32, minBit 5, minWin=23, winSum=398
8154 23:19:13.688003 TX Vref=34, minBit 0, minWin=23, winSum=394
8155 23:19:13.694567 [TxChooseVref] Worse bit 1, Min win 24, Win sum 418, Final Vref 26
8156 23:19:13.694670
8157 23:19:13.697380 Final TX Range 0 Vref 26
8158 23:19:13.697477
8159 23:19:13.697543 ==
8160 23:19:13.701047 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 23:19:13.704612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 23:19:13.704712 ==
8163 23:19:13.704802
8164 23:19:13.704870
8165 23:19:13.707500 TX Vref Scan disable
8166 23:19:13.714198 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8167 23:19:13.714301 == TX Byte 0 ==
8168 23:19:13.717228 u2DelayCellOfst[0]=11 cells (3 PI)
8169 23:19:13.720446 u2DelayCellOfst[1]=18 cells (5 PI)
8170 23:19:13.724557 u2DelayCellOfst[2]=11 cells (3 PI)
8171 23:19:13.728252 u2DelayCellOfst[3]=11 cells (3 PI)
8172 23:19:13.730640 u2DelayCellOfst[4]=7 cells (2 PI)
8173 23:19:13.734226 u2DelayCellOfst[5]=0 cells (0 PI)
8174 23:19:13.737416 u2DelayCellOfst[6]=18 cells (5 PI)
8175 23:19:13.740440 u2DelayCellOfst[7]=18 cells (5 PI)
8176 23:19:13.743835 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8177 23:19:13.746646 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8178 23:19:13.750258 == TX Byte 1 ==
8179 23:19:13.753698 u2DelayCellOfst[8]=0 cells (0 PI)
8180 23:19:13.757142 u2DelayCellOfst[9]=3 cells (1 PI)
8181 23:19:13.760084 u2DelayCellOfst[10]=11 cells (3 PI)
8182 23:19:13.763590 u2DelayCellOfst[11]=3 cells (1 PI)
8183 23:19:13.763697 u2DelayCellOfst[12]=14 cells (4 PI)
8184 23:19:13.766516 u2DelayCellOfst[13]=14 cells (4 PI)
8185 23:19:13.770463 u2DelayCellOfst[14]=18 cells (5 PI)
8186 23:19:13.773422 u2DelayCellOfst[15]=14 cells (4 PI)
8187 23:19:13.779926 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8188 23:19:13.783102 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8189 23:19:13.783205 DramC Write-DBI on
8190 23:19:13.786423 ==
8191 23:19:13.789982 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 23:19:13.793096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 23:19:13.793198 ==
8194 23:19:13.793288
8195 23:19:13.793379
8196 23:19:13.796692 TX Vref Scan disable
8197 23:19:13.796769 == TX Byte 0 ==
8198 23:19:13.803195 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8199 23:19:13.803297 == TX Byte 1 ==
8200 23:19:13.806007 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8201 23:19:13.809472 DramC Write-DBI off
8202 23:19:13.809580
8203 23:19:13.809671 [DATLAT]
8204 23:19:13.812667 Freq=1600, CH0 RK1
8205 23:19:13.812751
8206 23:19:13.812818 DATLAT Default: 0xf
8207 23:19:13.816231 0, 0xFFFF, sum = 0
8208 23:19:13.816305 1, 0xFFFF, sum = 0
8209 23:19:13.819641 2, 0xFFFF, sum = 0
8210 23:19:13.822673 3, 0xFFFF, sum = 0
8211 23:19:13.822773 4, 0xFFFF, sum = 0
8212 23:19:13.825663 5, 0xFFFF, sum = 0
8213 23:19:13.825770 6, 0xFFFF, sum = 0
8214 23:19:13.829272 7, 0xFFFF, sum = 0
8215 23:19:13.829373 8, 0xFFFF, sum = 0
8216 23:19:13.832412 9, 0xFFFF, sum = 0
8217 23:19:13.832492 10, 0xFFFF, sum = 0
8218 23:19:13.836036 11, 0xFFFF, sum = 0
8219 23:19:13.836110 12, 0xFFFF, sum = 0
8220 23:19:13.839929 13, 0xFFFF, sum = 0
8221 23:19:13.840006 14, 0x0, sum = 1
8222 23:19:13.842994 15, 0x0, sum = 2
8223 23:19:13.843094 16, 0x0, sum = 3
8224 23:19:13.846232 17, 0x0, sum = 4
8225 23:19:13.846330 best_step = 15
8226 23:19:13.846420
8227 23:19:13.846506 ==
8228 23:19:13.849899 Dram Type= 6, Freq= 0, CH_0, rank 1
8229 23:19:13.855353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 23:19:13.855453 ==
8231 23:19:13.855549 RX Vref Scan: 0
8232 23:19:13.855637
8233 23:19:13.858474 RX Vref 0 -> 0, step: 1
8234 23:19:13.858570
8235 23:19:13.862510 RX Delay 11 -> 252, step: 4
8236 23:19:13.865601 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8237 23:19:13.868677 iDelay=195, Bit 1, Center 134 (83 ~ 186) 104
8238 23:19:13.871909 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8239 23:19:13.878868 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8240 23:19:13.881909 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8241 23:19:13.885507 iDelay=195, Bit 5, Center 122 (67 ~ 178) 112
8242 23:19:13.888448 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8243 23:19:13.891790 iDelay=195, Bit 7, Center 140 (91 ~ 190) 100
8244 23:19:13.898560 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8245 23:19:13.901585 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8246 23:19:13.905069 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8247 23:19:13.908388 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8248 23:19:13.915157 iDelay=195, Bit 12, Center 128 (75 ~ 182) 108
8249 23:19:13.918335 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8250 23:19:13.921569 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8251 23:19:13.925223 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8252 23:19:13.925334 ==
8253 23:19:13.928549 Dram Type= 6, Freq= 0, CH_0, rank 1
8254 23:19:13.935251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 23:19:13.935363 ==
8256 23:19:13.935457 DQS Delay:
8257 23:19:13.935546 DQS0 = 0, DQS1 = 0
8258 23:19:13.937863 DQM Delay:
8259 23:19:13.937962 DQM0 = 130, DQM1 = 125
8260 23:19:13.941310 DQ Delay:
8261 23:19:13.944355 DQ0 =128, DQ1 =134, DQ2 =126, DQ3 =128
8262 23:19:13.947486 DQ4 =130, DQ5 =122, DQ6 =138, DQ7 =140
8263 23:19:13.951834 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8264 23:19:13.955202 DQ12 =128, DQ13 =132, DQ14 =136, DQ15 =132
8265 23:19:13.955301
8266 23:19:13.955392
8267 23:19:13.955480
8268 23:19:13.957669 [DramC_TX_OE_Calibration] TA2
8269 23:19:13.961333 Original DQ_B0 (3 6) =30, OEN = 27
8270 23:19:13.964029 Original DQ_B1 (3 6) =30, OEN = 27
8271 23:19:13.967470 24, 0x0, End_B0=24 End_B1=24
8272 23:19:13.970992 25, 0x0, End_B0=25 End_B1=25
8273 23:19:13.971092 26, 0x0, End_B0=26 End_B1=26
8274 23:19:13.973951 27, 0x0, End_B0=27 End_B1=27
8275 23:19:13.977265 28, 0x0, End_B0=28 End_B1=28
8276 23:19:13.980953 29, 0x0, End_B0=29 End_B1=29
8277 23:19:13.981054 30, 0x0, End_B0=30 End_B1=30
8278 23:19:13.984584 31, 0x4141, End_B0=30 End_B1=30
8279 23:19:13.988209 Byte0 end_step=30 best_step=27
8280 23:19:13.991014 Byte1 end_step=30 best_step=27
8281 23:19:13.993871 Byte0 TX OE(2T, 0.5T) = (3, 3)
8282 23:19:13.997248 Byte1 TX OE(2T, 0.5T) = (3, 3)
8283 23:19:13.997347
8284 23:19:13.997445
8285 23:19:14.004089 [DQSOSCAuto] RK1, (LSB)MR18= 0x2004, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8286 23:19:14.007046 CH0 RK1: MR19=303, MR18=2004
8287 23:19:14.014086 CH0_RK1: MR19=0x303, MR18=0x2004, DQSOSC=393, MR23=63, INC=23, DEC=15
8288 23:19:14.017437 [RxdqsGatingPostProcess] freq 1600
8289 23:19:14.020220 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8290 23:19:14.023599 best DQS0 dly(2T, 0.5T) = (1, 1)
8291 23:19:14.026941 best DQS1 dly(2T, 0.5T) = (1, 1)
8292 23:19:14.030799 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8293 23:19:14.033625 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8294 23:19:14.036761 best DQS0 dly(2T, 0.5T) = (1, 1)
8295 23:19:14.040243 best DQS1 dly(2T, 0.5T) = (1, 1)
8296 23:19:14.043325 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8297 23:19:14.046532 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8298 23:19:14.050227 Pre-setting of DQS Precalculation
8299 23:19:14.053884 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8300 23:19:14.053981 ==
8301 23:19:14.056646 Dram Type= 6, Freq= 0, CH_1, rank 0
8302 23:19:14.063287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8303 23:19:14.063387 ==
8304 23:19:14.066521 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8305 23:19:14.072937 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8306 23:19:14.076718 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8307 23:19:14.082793 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8308 23:19:14.090742 [CA 0] Center 42 (13~72) winsize 60
8309 23:19:14.094715 [CA 1] Center 42 (13~72) winsize 60
8310 23:19:14.097303 [CA 2] Center 38 (9~67) winsize 59
8311 23:19:14.100711 [CA 3] Center 36 (7~66) winsize 60
8312 23:19:14.104034 [CA 4] Center 37 (8~67) winsize 60
8313 23:19:14.107603 [CA 5] Center 37 (8~67) winsize 60
8314 23:19:14.107743
8315 23:19:14.111135 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8316 23:19:14.111243
8317 23:19:14.113706 [CATrainingPosCal] consider 1 rank data
8318 23:19:14.117609 u2DelayCellTimex100 = 262/100 ps
8319 23:19:14.124068 CA0 delay=42 (13~72),Diff = 6 PI (22 cell)
8320 23:19:14.126936 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8321 23:19:14.130449 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8322 23:19:14.133490 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8323 23:19:14.137414 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8324 23:19:14.140227 CA5 delay=37 (8~67),Diff = 1 PI (3 cell)
8325 23:19:14.140313
8326 23:19:14.145969 CA PerBit enable=1, Macro0, CA PI delay=36
8327 23:19:14.146066
8328 23:19:14.146657 [CBTSetCACLKResult] CA Dly = 36
8329 23:19:14.149607 CS Dly: 9 (0~40)
8330 23:19:14.153886 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8331 23:19:14.156484 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8332 23:19:14.156585 ==
8333 23:19:14.160430 Dram Type= 6, Freq= 0, CH_1, rank 1
8334 23:19:14.166251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 23:19:14.166351 ==
8336 23:19:14.169517 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8337 23:19:14.175990 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8338 23:19:14.179400 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8339 23:19:14.186221 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8340 23:19:14.194534 [CA 0] Center 43 (14~72) winsize 59
8341 23:19:14.197791 [CA 1] Center 43 (13~73) winsize 61
8342 23:19:14.200901 [CA 2] Center 38 (9~67) winsize 59
8343 23:19:14.203596 [CA 3] Center 37 (8~67) winsize 60
8344 23:19:14.207455 [CA 4] Center 38 (9~67) winsize 59
8345 23:19:14.210518 [CA 5] Center 37 (8~67) winsize 60
8346 23:19:14.210617
8347 23:19:14.213413 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8348 23:19:14.213509
8349 23:19:14.220329 [CATrainingPosCal] consider 2 rank data
8350 23:19:14.220431 u2DelayCellTimex100 = 262/100 ps
8351 23:19:14.226993 CA0 delay=43 (14~72),Diff = 6 PI (22 cell)
8352 23:19:14.230225 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8353 23:19:14.234206 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8354 23:19:14.237103 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8355 23:19:14.240130 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8356 23:19:14.243893 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8357 23:19:14.243964
8358 23:19:14.246755 CA PerBit enable=1, Macro0, CA PI delay=37
8359 23:19:14.246855
8360 23:19:14.249893 [CBTSetCACLKResult] CA Dly = 37
8361 23:19:14.253238 CS Dly: 10 (0~43)
8362 23:19:14.256659 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8363 23:19:14.259967 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8364 23:19:14.260039
8365 23:19:14.264131 ----->DramcWriteLeveling(PI) begin...
8366 23:19:14.264219 ==
8367 23:19:14.266467 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 23:19:14.273212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 23:19:14.273314 ==
8370 23:19:14.276095 Write leveling (Byte 0): 24 => 24
8371 23:19:14.279650 Write leveling (Byte 1): 26 => 26
8372 23:19:14.279794 DramcWriteLeveling(PI) end<-----
8373 23:19:14.283127
8374 23:19:14.283224 ==
8375 23:19:14.286048 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 23:19:14.289464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 23:19:14.289563 ==
8378 23:19:14.292802 [Gating] SW mode calibration
8379 23:19:14.299888 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8380 23:19:14.303226 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8381 23:19:14.309482 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 23:19:14.313239 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 23:19:14.316222 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 23:19:14.322796 1 4 12 | B1->B0 | 2e2e 3333 | 0 1 | (0 0) (0 0)
8385 23:19:14.325751 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 23:19:14.329316 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 23:19:14.335885 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 23:19:14.339348 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 23:19:14.342552 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 23:19:14.348857 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 23:19:14.352300 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8392 23:19:14.355432 1 5 12 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 1)
8393 23:19:14.362079 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 23:19:14.365690 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 23:19:14.369305 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 23:19:14.375534 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 23:19:14.378562 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 23:19:14.381732 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 23:19:14.388324 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 23:19:14.392105 1 6 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8401 23:19:14.395042 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 23:19:14.402220 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 23:19:14.405095 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 23:19:14.408246 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 23:19:14.415603 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 23:19:14.418474 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 23:19:14.421889 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8408 23:19:14.428963 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8409 23:19:14.431768 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8410 23:19:14.434782 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 23:19:14.441403 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 23:19:14.444738 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 23:19:14.448084 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 23:19:14.454631 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 23:19:14.458689 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 23:19:14.461379 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 23:19:14.467964 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 23:19:14.470921 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 23:19:14.474379 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 23:19:14.480758 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 23:19:14.485248 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 23:19:14.487586 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 23:19:14.494223 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8424 23:19:14.497296 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8425 23:19:14.500735 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 23:19:14.503526 Total UI for P1: 0, mck2ui 16
8427 23:19:14.507280 best dqsien dly found for B0: ( 1, 9, 10)
8428 23:19:14.510736 Total UI for P1: 0, mck2ui 16
8429 23:19:14.513549 best dqsien dly found for B1: ( 1, 9, 12)
8430 23:19:14.516828 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8431 23:19:14.524576 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8432 23:19:14.524677
8433 23:19:14.527064 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8434 23:19:14.530476 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8435 23:19:14.533636 [Gating] SW calibration Done
8436 23:19:14.533735 ==
8437 23:19:14.536636 Dram Type= 6, Freq= 0, CH_1, rank 0
8438 23:19:14.539988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8439 23:19:14.540088 ==
8440 23:19:14.543579 RX Vref Scan: 0
8441 23:19:14.543681
8442 23:19:14.543744 RX Vref 0 -> 0, step: 1
8443 23:19:14.543811
8444 23:19:14.546741 RX Delay 0 -> 252, step: 8
8445 23:19:14.550578 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8446 23:19:14.554128 iDelay=208, Bit 1, Center 135 (88 ~ 183) 96
8447 23:19:14.560034 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8448 23:19:14.563603 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8449 23:19:14.566729 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8450 23:19:14.569698 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8451 23:19:14.573146 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8452 23:19:14.579625 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8453 23:19:14.582814 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8454 23:19:14.586057 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8455 23:19:14.589296 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8456 23:19:14.596351 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8457 23:19:14.599332 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8458 23:19:14.602594 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8459 23:19:14.606254 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8460 23:19:14.609629 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8461 23:19:14.613061 ==
8462 23:19:14.616253 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 23:19:14.619500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 23:19:14.619609 ==
8465 23:19:14.619741 DQS Delay:
8466 23:19:14.622425 DQS0 = 0, DQS1 = 0
8467 23:19:14.622533 DQM Delay:
8468 23:19:14.625891 DQM0 = 138, DQM1 = 130
8469 23:19:14.625994 DQ Delay:
8470 23:19:14.629250 DQ0 =139, DQ1 =135, DQ2 =127, DQ3 =139
8471 23:19:14.632419 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8472 23:19:14.635522 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8473 23:19:14.639365 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8474 23:19:14.639463
8475 23:19:14.639557
8476 23:19:14.642705 ==
8477 23:19:14.642777 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 23:19:14.648826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 23:19:14.648925 ==
8480 23:19:14.649017
8481 23:19:14.649106
8482 23:19:14.652045 TX Vref Scan disable
8483 23:19:14.652117 == TX Byte 0 ==
8484 23:19:14.656146 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8485 23:19:14.661883 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8486 23:19:14.661984 == TX Byte 1 ==
8487 23:19:14.665557 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8488 23:19:14.672331 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8489 23:19:14.672440 ==
8490 23:19:14.675623 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 23:19:14.679122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 23:19:14.679228 ==
8493 23:19:14.691409
8494 23:19:14.694710 TX Vref early break, caculate TX vref
8495 23:19:14.698030 TX Vref=16, minBit 0, minWin=22, winSum=374
8496 23:19:14.701210 TX Vref=18, minBit 0, minWin=22, winSum=387
8497 23:19:14.704559 TX Vref=20, minBit 0, minWin=23, winSum=395
8498 23:19:14.707922 TX Vref=22, minBit 5, minWin=23, winSum=404
8499 23:19:14.711108 TX Vref=24, minBit 5, minWin=24, winSum=414
8500 23:19:14.717530 TX Vref=26, minBit 0, minWin=25, winSum=420
8501 23:19:14.721684 TX Vref=28, minBit 0, minWin=25, winSum=421
8502 23:19:14.724296 TX Vref=30, minBit 0, minWin=25, winSum=414
8503 23:19:14.727889 TX Vref=32, minBit 1, minWin=23, winSum=403
8504 23:19:14.730949 TX Vref=34, minBit 5, minWin=23, winSum=395
8505 23:19:14.737276 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
8506 23:19:14.737380
8507 23:19:14.740951 Final TX Range 0 Vref 28
8508 23:19:14.741074
8509 23:19:14.741220 ==
8510 23:19:14.744078 Dram Type= 6, Freq= 0, CH_1, rank 0
8511 23:19:14.747528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8512 23:19:14.747627 ==
8513 23:19:14.747756
8514 23:19:14.747846
8515 23:19:14.750753 TX Vref Scan disable
8516 23:19:14.757293 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8517 23:19:14.757402 == TX Byte 0 ==
8518 23:19:14.760599 u2DelayCellOfst[0]=18 cells (5 PI)
8519 23:19:14.763794 u2DelayCellOfst[1]=14 cells (4 PI)
8520 23:19:14.767538 u2DelayCellOfst[2]=0 cells (0 PI)
8521 23:19:14.770678 u2DelayCellOfst[3]=7 cells (2 PI)
8522 23:19:14.773692 u2DelayCellOfst[4]=7 cells (2 PI)
8523 23:19:14.777468 u2DelayCellOfst[5]=22 cells (6 PI)
8524 23:19:14.780991 u2DelayCellOfst[6]=18 cells (5 PI)
8525 23:19:14.783564 u2DelayCellOfst[7]=7 cells (2 PI)
8526 23:19:14.787524 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8527 23:19:14.790309 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8528 23:19:14.793619 == TX Byte 1 ==
8529 23:19:14.796979 u2DelayCellOfst[8]=0 cells (0 PI)
8530 23:19:14.797051 u2DelayCellOfst[9]=3 cells (1 PI)
8531 23:19:14.800288 u2DelayCellOfst[10]=11 cells (3 PI)
8532 23:19:14.803661 u2DelayCellOfst[11]=3 cells (1 PI)
8533 23:19:14.807084 u2DelayCellOfst[12]=14 cells (4 PI)
8534 23:19:14.810518 u2DelayCellOfst[13]=18 cells (5 PI)
8535 23:19:14.814205 u2DelayCellOfst[14]=18 cells (5 PI)
8536 23:19:14.816614 u2DelayCellOfst[15]=18 cells (5 PI)
8537 23:19:14.823462 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8538 23:19:14.826649 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8539 23:19:14.826748 DramC Write-DBI on
8540 23:19:14.826850 ==
8541 23:19:14.829781 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 23:19:14.837054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 23:19:14.837164 ==
8544 23:19:14.837256
8545 23:19:14.837353
8546 23:19:14.839713 TX Vref Scan disable
8547 23:19:14.839788 == TX Byte 0 ==
8548 23:19:14.846278 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8549 23:19:14.846376 == TX Byte 1 ==
8550 23:19:14.849371 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8551 23:19:14.852642 DramC Write-DBI off
8552 23:19:14.852715
8553 23:19:14.852776 [DATLAT]
8554 23:19:14.855897 Freq=1600, CH1 RK0
8555 23:19:14.856004
8556 23:19:14.856073 DATLAT Default: 0xf
8557 23:19:14.859523 0, 0xFFFF, sum = 0
8558 23:19:14.859621 1, 0xFFFF, sum = 0
8559 23:19:14.863124 2, 0xFFFF, sum = 0
8560 23:19:14.863222 3, 0xFFFF, sum = 0
8561 23:19:14.866132 4, 0xFFFF, sum = 0
8562 23:19:14.866237 5, 0xFFFF, sum = 0
8563 23:19:14.869452 6, 0xFFFF, sum = 0
8564 23:19:14.869558 7, 0xFFFF, sum = 0
8565 23:19:14.872901 8, 0xFFFF, sum = 0
8566 23:19:14.876184 9, 0xFFFF, sum = 0
8567 23:19:14.876257 10, 0xFFFF, sum = 0
8568 23:19:14.879084 11, 0xFFFF, sum = 0
8569 23:19:14.879183 12, 0xFFFF, sum = 0
8570 23:19:14.882547 13, 0xFFFF, sum = 0
8571 23:19:14.882649 14, 0x0, sum = 1
8572 23:19:14.885752 15, 0x0, sum = 2
8573 23:19:14.885851 16, 0x0, sum = 3
8574 23:19:14.889341 17, 0x0, sum = 4
8575 23:19:14.889412 best_step = 15
8576 23:19:14.889477
8577 23:19:14.889537 ==
8578 23:19:14.892079 Dram Type= 6, Freq= 0, CH_1, rank 0
8579 23:19:14.895556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8580 23:19:14.899037 ==
8581 23:19:14.899108 RX Vref Scan: 1
8582 23:19:14.899173
8583 23:19:14.902463 Set Vref Range= 24 -> 127
8584 23:19:14.902559
8585 23:19:14.905440 RX Vref 24 -> 127, step: 1
8586 23:19:14.905512
8587 23:19:14.905579 RX Delay 19 -> 252, step: 4
8588 23:19:14.905641
8589 23:19:14.908818 Set Vref, RX VrefLevel [Byte0]: 24
8590 23:19:14.912075 [Byte1]: 24
8591 23:19:14.915658
8592 23:19:14.915778 Set Vref, RX VrefLevel [Byte0]: 25
8593 23:19:14.919227 [Byte1]: 25
8594 23:19:14.923468
8595 23:19:14.923566 Set Vref, RX VrefLevel [Byte0]: 26
8596 23:19:14.926659 [Byte1]: 26
8597 23:19:14.930893
8598 23:19:14.930976 Set Vref, RX VrefLevel [Byte0]: 27
8599 23:19:14.934307 [Byte1]: 27
8600 23:19:14.938922
8601 23:19:14.939019 Set Vref, RX VrefLevel [Byte0]: 28
8602 23:19:14.942756 [Byte1]: 28
8603 23:19:14.946503
8604 23:19:14.946600 Set Vref, RX VrefLevel [Byte0]: 29
8605 23:19:14.949165 [Byte1]: 29
8606 23:19:14.953374
8607 23:19:14.953446 Set Vref, RX VrefLevel [Byte0]: 30
8608 23:19:14.957101 [Byte1]: 30
8609 23:19:14.961178
8610 23:19:14.961278 Set Vref, RX VrefLevel [Byte0]: 31
8611 23:19:14.964644 [Byte1]: 31
8612 23:19:14.968992
8613 23:19:14.969093 Set Vref, RX VrefLevel [Byte0]: 32
8614 23:19:14.972078 [Byte1]: 32
8615 23:19:14.976936
8616 23:19:14.977042 Set Vref, RX VrefLevel [Byte0]: 33
8617 23:19:14.980386 [Byte1]: 33
8618 23:19:14.983847
8619 23:19:14.983930 Set Vref, RX VrefLevel [Byte0]: 34
8620 23:19:14.986985 [Byte1]: 34
8621 23:19:14.991859
8622 23:19:14.991936 Set Vref, RX VrefLevel [Byte0]: 35
8623 23:19:14.995014 [Byte1]: 35
8624 23:19:14.999037
8625 23:19:14.999137 Set Vref, RX VrefLevel [Byte0]: 36
8626 23:19:15.002330 [Byte1]: 36
8627 23:19:15.006654
8628 23:19:15.006752 Set Vref, RX VrefLevel [Byte0]: 37
8629 23:19:15.010323 [Byte1]: 37
8630 23:19:15.014318
8631 23:19:15.014417 Set Vref, RX VrefLevel [Byte0]: 38
8632 23:19:15.017474 [Byte1]: 38
8633 23:19:15.022293
8634 23:19:15.022396 Set Vref, RX VrefLevel [Byte0]: 39
8635 23:19:15.025118 [Byte1]: 39
8636 23:19:15.029515
8637 23:19:15.029624 Set Vref, RX VrefLevel [Byte0]: 40
8638 23:19:15.033013 [Byte1]: 40
8639 23:19:15.037073
8640 23:19:15.040246 Set Vref, RX VrefLevel [Byte0]: 41
8641 23:19:15.043845 [Byte1]: 41
8642 23:19:15.043923
8643 23:19:15.047062 Set Vref, RX VrefLevel [Byte0]: 42
8644 23:19:15.050333 [Byte1]: 42
8645 23:19:15.050435
8646 23:19:15.053205 Set Vref, RX VrefLevel [Byte0]: 43
8647 23:19:15.057353 [Byte1]: 43
8648 23:19:15.059857
8649 23:19:15.059967 Set Vref, RX VrefLevel [Byte0]: 44
8650 23:19:15.062837 [Byte1]: 44
8651 23:19:15.067345
8652 23:19:15.067443 Set Vref, RX VrefLevel [Byte0]: 45
8653 23:19:15.070433 [Byte1]: 45
8654 23:19:15.074936
8655 23:19:15.075036 Set Vref, RX VrefLevel [Byte0]: 46
8656 23:19:15.078587 [Byte1]: 46
8657 23:19:15.082213
8658 23:19:15.082321 Set Vref, RX VrefLevel [Byte0]: 47
8659 23:19:15.085730 [Byte1]: 47
8660 23:19:15.089817
8661 23:19:15.089923 Set Vref, RX VrefLevel [Byte0]: 48
8662 23:19:15.093403 [Byte1]: 48
8663 23:19:15.097402
8664 23:19:15.097490 Set Vref, RX VrefLevel [Byte0]: 49
8665 23:19:15.101043 [Byte1]: 49
8666 23:19:15.105257
8667 23:19:15.105339 Set Vref, RX VrefLevel [Byte0]: 50
8668 23:19:15.108905 [Byte1]: 50
8669 23:19:15.112653
8670 23:19:15.112734 Set Vref, RX VrefLevel [Byte0]: 51
8671 23:19:15.116177 [Byte1]: 51
8672 23:19:15.120180
8673 23:19:15.120286 Set Vref, RX VrefLevel [Byte0]: 52
8674 23:19:15.123550 [Byte1]: 52
8675 23:19:15.127648
8676 23:19:15.127770 Set Vref, RX VrefLevel [Byte0]: 53
8677 23:19:15.130946 [Byte1]: 53
8678 23:19:15.135889
8679 23:19:15.135970 Set Vref, RX VrefLevel [Byte0]: 54
8680 23:19:15.138707 [Byte1]: 54
8681 23:19:15.143444
8682 23:19:15.143525 Set Vref, RX VrefLevel [Byte0]: 55
8683 23:19:15.146055 [Byte1]: 55
8684 23:19:15.151016
8685 23:19:15.151097 Set Vref, RX VrefLevel [Byte0]: 56
8686 23:19:15.153743 [Byte1]: 56
8687 23:19:15.158761
8688 23:19:15.158866 Set Vref, RX VrefLevel [Byte0]: 57
8689 23:19:15.161489 [Byte1]: 57
8690 23:19:15.165562
8691 23:19:15.165663 Set Vref, RX VrefLevel [Byte0]: 58
8692 23:19:15.171937 [Byte1]: 58
8693 23:19:15.172040
8694 23:19:15.175594 Set Vref, RX VrefLevel [Byte0]: 59
8695 23:19:15.178551 [Byte1]: 59
8696 23:19:15.178649
8697 23:19:15.182349 Set Vref, RX VrefLevel [Byte0]: 60
8698 23:19:15.185432 [Byte1]: 60
8699 23:19:15.185532
8700 23:19:15.188689 Set Vref, RX VrefLevel [Byte0]: 61
8701 23:19:15.191655 [Byte1]: 61
8702 23:19:15.196173
8703 23:19:15.196247 Set Vref, RX VrefLevel [Byte0]: 62
8704 23:19:15.199405 [Byte1]: 62
8705 23:19:15.204012
8706 23:19:15.204086 Set Vref, RX VrefLevel [Byte0]: 63
8707 23:19:15.206995 [Byte1]: 63
8708 23:19:15.211762
8709 23:19:15.211839 Set Vref, RX VrefLevel [Byte0]: 64
8710 23:19:15.214298 [Byte1]: 64
8711 23:19:15.218570
8712 23:19:15.218673 Set Vref, RX VrefLevel [Byte0]: 65
8713 23:19:15.222487 [Byte1]: 65
8714 23:19:15.226167
8715 23:19:15.226267 Set Vref, RX VrefLevel [Byte0]: 66
8716 23:19:15.229730 [Byte1]: 66
8717 23:19:15.233605
8718 23:19:15.233687 Set Vref, RX VrefLevel [Byte0]: 67
8719 23:19:15.237659 [Byte1]: 67
8720 23:19:15.241636
8721 23:19:15.241718 Set Vref, RX VrefLevel [Byte0]: 68
8722 23:19:15.244463 [Byte1]: 68
8723 23:19:15.249065
8724 23:19:15.249164 Set Vref, RX VrefLevel [Byte0]: 69
8725 23:19:15.252085 [Byte1]: 69
8726 23:19:15.256294
8727 23:19:15.256366 Set Vref, RX VrefLevel [Byte0]: 70
8728 23:19:15.260554 [Byte1]: 70
8729 23:19:15.264075
8730 23:19:15.264164 Set Vref, RX VrefLevel [Byte0]: 71
8731 23:19:15.267615 [Byte1]: 71
8732 23:19:15.271412
8733 23:19:15.271484 Set Vref, RX VrefLevel [Byte0]: 72
8734 23:19:15.275152 [Byte1]: 72
8735 23:19:15.279402
8736 23:19:15.279500 Set Vref, RX VrefLevel [Byte0]: 73
8737 23:19:15.282951 [Byte1]: 73
8738 23:19:15.286929
8739 23:19:15.287028 Set Vref, RX VrefLevel [Byte0]: 74
8740 23:19:15.289937 [Byte1]: 74
8741 23:19:15.294468
8742 23:19:15.294568 Final RX Vref Byte 0 = 54 to rank0
8743 23:19:15.298544 Final RX Vref Byte 1 = 60 to rank0
8744 23:19:15.301321 Final RX Vref Byte 0 = 54 to rank1
8745 23:19:15.304037 Final RX Vref Byte 1 = 60 to rank1==
8746 23:19:15.307418 Dram Type= 6, Freq= 0, CH_1, rank 0
8747 23:19:15.314347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8748 23:19:15.314451 ==
8749 23:19:15.314548 DQS Delay:
8750 23:19:15.317486 DQS0 = 0, DQS1 = 0
8751 23:19:15.317583 DQM Delay:
8752 23:19:15.317672 DQM0 = 134, DQM1 = 129
8753 23:19:15.320795 DQ Delay:
8754 23:19:15.323857 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8755 23:19:15.327058 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8756 23:19:15.330541 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =118
8757 23:19:15.333877 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =138
8758 23:19:15.333977
8759 23:19:15.334066
8760 23:19:15.334157
8761 23:19:15.337405 [DramC_TX_OE_Calibration] TA2
8762 23:19:15.340298 Original DQ_B0 (3 6) =30, OEN = 27
8763 23:19:15.343645 Original DQ_B1 (3 6) =30, OEN = 27
8764 23:19:15.347234 24, 0x0, End_B0=24 End_B1=24
8765 23:19:15.350143 25, 0x0, End_B0=25 End_B1=25
8766 23:19:15.350243 26, 0x0, End_B0=26 End_B1=26
8767 23:19:15.353374 27, 0x0, End_B0=27 End_B1=27
8768 23:19:15.356848 28, 0x0, End_B0=28 End_B1=28
8769 23:19:15.360842 29, 0x0, End_B0=29 End_B1=29
8770 23:19:15.360930 30, 0x0, End_B0=30 End_B1=30
8771 23:19:15.363606 31, 0x4141, End_B0=30 End_B1=30
8772 23:19:15.366635 Byte0 end_step=30 best_step=27
8773 23:19:15.370095 Byte1 end_step=30 best_step=27
8774 23:19:15.373091 Byte0 TX OE(2T, 0.5T) = (3, 3)
8775 23:19:15.376660 Byte1 TX OE(2T, 0.5T) = (3, 3)
8776 23:19:15.376733
8777 23:19:15.376804
8778 23:19:15.383049 [DQSOSCAuto] RK0, (LSB)MR18= 0x190f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8779 23:19:15.386093 CH1 RK0: MR19=303, MR18=190F
8780 23:19:15.392864 CH1_RK0: MR19=0x303, MR18=0x190F, DQSOSC=397, MR23=63, INC=23, DEC=15
8781 23:19:15.392939
8782 23:19:15.396640 ----->DramcWriteLeveling(PI) begin...
8783 23:19:15.396735 ==
8784 23:19:15.399522 Dram Type= 6, Freq= 0, CH_1, rank 1
8785 23:19:15.402380 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8786 23:19:15.405887 ==
8787 23:19:15.405978 Write leveling (Byte 0): 24 => 24
8788 23:19:15.409040 Write leveling (Byte 1): 27 => 27
8789 23:19:15.412582 DramcWriteLeveling(PI) end<-----
8790 23:19:15.412656
8791 23:19:15.412718 ==
8792 23:19:15.415825 Dram Type= 6, Freq= 0, CH_1, rank 1
8793 23:19:15.422706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8794 23:19:15.422809 ==
8795 23:19:15.425411 [Gating] SW mode calibration
8796 23:19:15.432417 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8797 23:19:15.436141 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8798 23:19:15.442131 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 23:19:15.445495 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 23:19:15.448990 1 4 8 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
8801 23:19:15.455533 1 4 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8802 23:19:15.459169 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 23:19:15.461767 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 23:19:15.469002 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 23:19:15.471981 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 23:19:15.475085 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 23:19:15.481740 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 23:19:15.484811 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8809 23:19:15.488691 1 5 12 | B1->B0 | 2323 3434 | 0 1 | (1 0) (1 0)
8810 23:19:15.495395 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8811 23:19:15.498461 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 23:19:15.501677 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 23:19:15.508501 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 23:19:15.511829 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 23:19:15.514882 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 23:19:15.521203 1 6 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8817 23:19:15.525491 1 6 12 | B1->B0 | 4646 2323 | 0 0 | (0 0) (0 0)
8818 23:19:15.527694 1 6 16 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8819 23:19:15.534427 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 23:19:15.537709 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 23:19:15.542076 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 23:19:15.548057 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 23:19:15.550888 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 23:19:15.554265 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8825 23:19:15.560912 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8826 23:19:15.564344 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8827 23:19:15.567847 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8828 23:19:15.574120 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 23:19:15.577195 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 23:19:15.580618 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 23:19:15.587560 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 23:19:15.590456 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 23:19:15.593928 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 23:19:15.600204 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 23:19:15.605334 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 23:19:15.606976 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 23:19:15.614304 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 23:19:15.616667 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 23:19:15.619922 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 23:19:15.626938 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8841 23:19:15.630278 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8842 23:19:15.633006 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 23:19:15.636916 Total UI for P1: 0, mck2ui 16
8844 23:19:15.639545 best dqsien dly found for B0: ( 1, 9, 12)
8845 23:19:15.643075 Total UI for P1: 0, mck2ui 16
8846 23:19:15.646621 best dqsien dly found for B1: ( 1, 9, 10)
8847 23:19:15.649573 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8848 23:19:15.653816 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8849 23:19:15.653916
8850 23:19:15.659770 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8851 23:19:15.662726 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8852 23:19:15.666261 [Gating] SW calibration Done
8853 23:19:15.666362 ==
8854 23:19:15.669975 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 23:19:15.672661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 23:19:15.672763 ==
8857 23:19:15.672855 RX Vref Scan: 0
8858 23:19:15.676480
8859 23:19:15.676554 RX Vref 0 -> 0, step: 1
8860 23:19:15.676644
8861 23:19:15.679536 RX Delay 0 -> 252, step: 8
8862 23:19:15.683208 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8863 23:19:15.686733 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8864 23:19:15.692456 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8865 23:19:15.695991 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8866 23:19:15.699114 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8867 23:19:15.702631 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8868 23:19:15.706693 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8869 23:19:15.713016 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8870 23:19:15.716442 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8871 23:19:15.719342 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8872 23:19:15.722237 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8873 23:19:15.725499 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8874 23:19:15.732838 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8875 23:19:15.735587 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8876 23:19:15.739346 iDelay=208, Bit 14, Center 135 (72 ~ 199) 128
8877 23:19:15.742166 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8878 23:19:15.742257 ==
8879 23:19:15.745729 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 23:19:15.751838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 23:19:15.751939 ==
8882 23:19:15.752042 DQS Delay:
8883 23:19:15.755283 DQS0 = 0, DQS1 = 0
8884 23:19:15.755380 DQM Delay:
8885 23:19:15.758436 DQM0 = 136, DQM1 = 129
8886 23:19:15.758531 DQ Delay:
8887 23:19:15.762150 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8888 23:19:15.764985 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8889 23:19:15.768547 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8890 23:19:15.771674 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8891 23:19:15.771777
8892 23:19:15.771878
8893 23:19:15.771965 ==
8894 23:19:15.775277 Dram Type= 6, Freq= 0, CH_1, rank 1
8895 23:19:15.781641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8896 23:19:15.781724 ==
8897 23:19:15.781789
8898 23:19:15.781849
8899 23:19:15.781906 TX Vref Scan disable
8900 23:19:15.785355 == TX Byte 0 ==
8901 23:19:15.788152 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8902 23:19:15.795262 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8903 23:19:15.795368 == TX Byte 1 ==
8904 23:19:15.798627 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8905 23:19:15.804745 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8906 23:19:15.804852 ==
8907 23:19:15.807846 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 23:19:15.811696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 23:19:15.811851 ==
8910 23:19:15.824164
8911 23:19:15.827593 TX Vref early break, caculate TX vref
8912 23:19:15.830600 TX Vref=16, minBit 5, minWin=22, winSum=381
8913 23:19:15.834342 TX Vref=18, minBit 0, minWin=23, winSum=392
8914 23:19:15.837092 TX Vref=20, minBit 1, minWin=23, winSum=398
8915 23:19:15.840482 TX Vref=22, minBit 1, minWin=24, winSum=410
8916 23:19:15.844020 TX Vref=24, minBit 5, minWin=25, winSum=417
8917 23:19:15.850084 TX Vref=26, minBit 1, minWin=25, winSum=422
8918 23:19:15.853760 TX Vref=28, minBit 0, minWin=25, winSum=423
8919 23:19:15.856992 TX Vref=30, minBit 0, minWin=25, winSum=415
8920 23:19:15.860395 TX Vref=32, minBit 0, minWin=23, winSum=407
8921 23:19:15.863607 TX Vref=34, minBit 0, minWin=23, winSum=397
8922 23:19:15.869992 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
8923 23:19:15.870096
8924 23:19:15.873188 Final TX Range 0 Vref 28
8925 23:19:15.873292
8926 23:19:15.873388 ==
8927 23:19:15.876764 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 23:19:15.880226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 23:19:15.880330 ==
8930 23:19:15.880456
8931 23:19:15.880549
8932 23:19:15.883231 TX Vref Scan disable
8933 23:19:15.890104 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8934 23:19:15.890211 == TX Byte 0 ==
8935 23:19:15.893202 u2DelayCellOfst[0]=22 cells (6 PI)
8936 23:19:15.896741 u2DelayCellOfst[1]=11 cells (3 PI)
8937 23:19:15.900117 u2DelayCellOfst[2]=0 cells (0 PI)
8938 23:19:15.903267 u2DelayCellOfst[3]=7 cells (2 PI)
8939 23:19:15.906728 u2DelayCellOfst[4]=7 cells (2 PI)
8940 23:19:15.909890 u2DelayCellOfst[5]=22 cells (6 PI)
8941 23:19:15.913282 u2DelayCellOfst[6]=22 cells (6 PI)
8942 23:19:15.916471 u2DelayCellOfst[7]=3 cells (1 PI)
8943 23:19:15.919811 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8944 23:19:15.923225 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8945 23:19:15.926204 == TX Byte 1 ==
8946 23:19:15.929194 u2DelayCellOfst[8]=0 cells (0 PI)
8947 23:19:15.929279 u2DelayCellOfst[9]=3 cells (1 PI)
8948 23:19:15.933242 u2DelayCellOfst[10]=11 cells (3 PI)
8949 23:19:15.935828 u2DelayCellOfst[11]=3 cells (1 PI)
8950 23:19:15.939986 u2DelayCellOfst[12]=14 cells (4 PI)
8951 23:19:15.942979 u2DelayCellOfst[13]=14 cells (4 PI)
8952 23:19:15.946302 u2DelayCellOfst[14]=14 cells (4 PI)
8953 23:19:15.949324 u2DelayCellOfst[15]=14 cells (4 PI)
8954 23:19:15.955803 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8955 23:19:15.959214 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8956 23:19:15.959300 DramC Write-DBI on
8957 23:19:15.959386 ==
8958 23:19:15.963218 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 23:19:15.969474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 23:19:15.969559 ==
8961 23:19:15.969646
8962 23:19:15.969727
8963 23:19:15.972137 TX Vref Scan disable
8964 23:19:15.972222 == TX Byte 0 ==
8965 23:19:15.978695 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8966 23:19:15.978781 == TX Byte 1 ==
8967 23:19:15.982160 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8968 23:19:15.985771 DramC Write-DBI off
8969 23:19:15.985855
8970 23:19:15.985942 [DATLAT]
8971 23:19:15.988618 Freq=1600, CH1 RK1
8972 23:19:15.988727
8973 23:19:15.988813 DATLAT Default: 0xf
8974 23:19:15.991860 0, 0xFFFF, sum = 0
8975 23:19:15.991972 1, 0xFFFF, sum = 0
8976 23:19:15.995120 2, 0xFFFF, sum = 0
8977 23:19:15.995206 3, 0xFFFF, sum = 0
8978 23:19:15.998854 4, 0xFFFF, sum = 0
8979 23:19:15.998940 5, 0xFFFF, sum = 0
8980 23:19:16.001846 6, 0xFFFF, sum = 0
8981 23:19:16.001931 7, 0xFFFF, sum = 0
8982 23:19:16.004956 8, 0xFFFF, sum = 0
8983 23:19:16.008626 9, 0xFFFF, sum = 0
8984 23:19:16.008712 10, 0xFFFF, sum = 0
8985 23:19:16.011594 11, 0xFFFF, sum = 0
8986 23:19:16.011748 12, 0xFFFF, sum = 0
8987 23:19:16.014975 13, 0xFFFF, sum = 0
8988 23:19:16.015061 14, 0x0, sum = 1
8989 23:19:16.018962 15, 0x0, sum = 2
8990 23:19:16.019065 16, 0x0, sum = 3
8991 23:19:16.021975 17, 0x0, sum = 4
8992 23:19:16.022060 best_step = 15
8993 23:19:16.022147
8994 23:19:16.022229 ==
8995 23:19:16.025456 Dram Type= 6, Freq= 0, CH_1, rank 1
8996 23:19:16.028549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8997 23:19:16.028634 ==
8998 23:19:16.031958 RX Vref Scan: 0
8999 23:19:16.032042
9000 23:19:16.034822 RX Vref 0 -> 0, step: 1
9001 23:19:16.034907
9002 23:19:16.034993 RX Delay 11 -> 252, step: 4
9003 23:19:16.042299 iDelay=199, Bit 0, Center 140 (87 ~ 194) 108
9004 23:19:16.045790 iDelay=199, Bit 1, Center 128 (75 ~ 182) 108
9005 23:19:16.048660 iDelay=199, Bit 2, Center 122 (67 ~ 178) 112
9006 23:19:16.051951 iDelay=199, Bit 3, Center 130 (79 ~ 182) 104
9007 23:19:16.058612 iDelay=199, Bit 4, Center 134 (79 ~ 190) 112
9008 23:19:16.062125 iDelay=199, Bit 5, Center 146 (95 ~ 198) 104
9009 23:19:16.065385 iDelay=199, Bit 6, Center 144 (91 ~ 198) 108
9010 23:19:16.068489 iDelay=199, Bit 7, Center 130 (79 ~ 182) 104
9011 23:19:16.071928 iDelay=199, Bit 8, Center 112 (55 ~ 170) 116
9012 23:19:16.078761 iDelay=199, Bit 9, Center 116 (63 ~ 170) 108
9013 23:19:16.081811 iDelay=199, Bit 10, Center 128 (75 ~ 182) 108
9014 23:19:16.084794 iDelay=199, Bit 11, Center 116 (63 ~ 170) 108
9015 23:19:16.088659 iDelay=199, Bit 12, Center 134 (79 ~ 190) 112
9016 23:19:16.092083 iDelay=199, Bit 13, Center 136 (83 ~ 190) 108
9017 23:19:16.099005 iDelay=199, Bit 14, Center 134 (79 ~ 190) 112
9018 23:19:16.101878 iDelay=199, Bit 15, Center 138 (83 ~ 194) 112
9019 23:19:16.101967 ==
9020 23:19:16.105414 Dram Type= 6, Freq= 0, CH_1, rank 1
9021 23:19:16.108145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9022 23:19:16.108231 ==
9023 23:19:16.111423 DQS Delay:
9024 23:19:16.111508 DQS0 = 0, DQS1 = 0
9025 23:19:16.111610 DQM Delay:
9026 23:19:16.114572 DQM0 = 134, DQM1 = 126
9027 23:19:16.114656 DQ Delay:
9028 23:19:16.117951 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9029 23:19:16.121304 DQ4 =134, DQ5 =146, DQ6 =144, DQ7 =130
9030 23:19:16.128363 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =116
9031 23:19:16.131439 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =138
9032 23:19:16.131524
9033 23:19:16.131626
9034 23:19:16.131758
9035 23:19:16.134663 [DramC_TX_OE_Calibration] TA2
9036 23:19:16.137812 Original DQ_B0 (3 6) =30, OEN = 27
9037 23:19:16.140981 Original DQ_B1 (3 6) =30, OEN = 27
9038 23:19:16.141066 24, 0x0, End_B0=24 End_B1=24
9039 23:19:16.145063 25, 0x0, End_B0=25 End_B1=25
9040 23:19:16.147684 26, 0x0, End_B0=26 End_B1=26
9041 23:19:16.150821 27, 0x0, End_B0=27 End_B1=27
9042 23:19:16.150907 28, 0x0, End_B0=28 End_B1=28
9043 23:19:16.154312 29, 0x0, End_B0=29 End_B1=29
9044 23:19:16.157779 30, 0x0, End_B0=30 End_B1=30
9045 23:19:16.160834 31, 0x4545, End_B0=30 End_B1=30
9046 23:19:16.164068 Byte0 end_step=30 best_step=27
9047 23:19:16.167509 Byte1 end_step=30 best_step=27
9048 23:19:16.167618 Byte0 TX OE(2T, 0.5T) = (3, 3)
9049 23:19:16.171044 Byte1 TX OE(2T, 0.5T) = (3, 3)
9050 23:19:16.171128
9051 23:19:16.171214
9052 23:19:16.181513 [DQSOSCAuto] RK1, (LSB)MR18= 0x905, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 405 ps
9053 23:19:16.183966 CH1 RK1: MR19=303, MR18=905
9054 23:19:16.187189 CH1_RK1: MR19=0x303, MR18=0x905, DQSOSC=405, MR23=63, INC=22, DEC=15
9055 23:19:16.191233 [RxdqsGatingPostProcess] freq 1600
9056 23:19:16.197601 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9057 23:19:16.200445 best DQS0 dly(2T, 0.5T) = (1, 1)
9058 23:19:16.204110 best DQS1 dly(2T, 0.5T) = (1, 1)
9059 23:19:16.207016 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9060 23:19:16.210436 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9061 23:19:16.214239 best DQS0 dly(2T, 0.5T) = (1, 1)
9062 23:19:16.216624 best DQS1 dly(2T, 0.5T) = (1, 1)
9063 23:19:16.220355 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9064 23:19:16.220440 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9065 23:19:16.223521 Pre-setting of DQS Precalculation
9066 23:19:16.230410 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9067 23:19:16.237117 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9068 23:19:16.243636 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9069 23:19:16.243736
9070 23:19:16.243802
9071 23:19:16.246672 [Calibration Summary] 3200 Mbps
9072 23:19:16.249853 CH 0, Rank 0
9073 23:19:16.249936 SW Impedance : PASS
9074 23:19:16.253434 DUTY Scan : NO K
9075 23:19:16.256683 ZQ Calibration : PASS
9076 23:19:16.256819 Jitter Meter : NO K
9077 23:19:16.259633 CBT Training : PASS
9078 23:19:16.263468 Write leveling : PASS
9079 23:19:16.263550 RX DQS gating : PASS
9080 23:19:16.266258 RX DQ/DQS(RDDQC) : PASS
9081 23:19:16.269639 TX DQ/DQS : PASS
9082 23:19:16.269722 RX DATLAT : PASS
9083 23:19:16.273370 RX DQ/DQS(Engine): PASS
9084 23:19:16.273452 TX OE : PASS
9085 23:19:16.276171 All Pass.
9086 23:19:16.276253
9087 23:19:16.276318 CH 0, Rank 1
9088 23:19:16.279494 SW Impedance : PASS
9089 23:19:16.279576 DUTY Scan : NO K
9090 23:19:16.283260 ZQ Calibration : PASS
9091 23:19:16.287063 Jitter Meter : NO K
9092 23:19:16.287145 CBT Training : PASS
9093 23:19:16.289673 Write leveling : PASS
9094 23:19:16.292597 RX DQS gating : PASS
9095 23:19:16.292707 RX DQ/DQS(RDDQC) : PASS
9096 23:19:16.296820 TX DQ/DQS : PASS
9097 23:19:16.299602 RX DATLAT : PASS
9098 23:19:16.299725 RX DQ/DQS(Engine): PASS
9099 23:19:16.303265 TX OE : PASS
9100 23:19:16.303348 All Pass.
9101 23:19:16.303413
9102 23:19:16.306618 CH 1, Rank 0
9103 23:19:16.306700 SW Impedance : PASS
9104 23:19:16.309739 DUTY Scan : NO K
9105 23:19:16.312982 ZQ Calibration : PASS
9106 23:19:16.313064 Jitter Meter : NO K
9107 23:19:16.315709 CBT Training : PASS
9108 23:19:16.319646 Write leveling : PASS
9109 23:19:16.319767 RX DQS gating : PASS
9110 23:19:16.323540 RX DQ/DQS(RDDQC) : PASS
9111 23:19:16.325919 TX DQ/DQS : PASS
9112 23:19:16.326005 RX DATLAT : PASS
9113 23:19:16.329652 RX DQ/DQS(Engine): PASS
9114 23:19:16.329736 TX OE : PASS
9115 23:19:16.332774 All Pass.
9116 23:19:16.332858
9117 23:19:16.332945 CH 1, Rank 1
9118 23:19:16.335831 SW Impedance : PASS
9119 23:19:16.339257 DUTY Scan : NO K
9120 23:19:16.339343 ZQ Calibration : PASS
9121 23:19:16.342304 Jitter Meter : NO K
9122 23:19:16.342390 CBT Training : PASS
9123 23:19:16.345773 Write leveling : PASS
9124 23:19:16.349648 RX DQS gating : PASS
9125 23:19:16.349733 RX DQ/DQS(RDDQC) : PASS
9126 23:19:16.352123 TX DQ/DQS : PASS
9127 23:19:16.355435 RX DATLAT : PASS
9128 23:19:16.355519 RX DQ/DQS(Engine): PASS
9129 23:19:16.359208 TX OE : PASS
9130 23:19:16.359293 All Pass.
9131 23:19:16.359379
9132 23:19:16.362168 DramC Write-DBI on
9133 23:19:16.365617 PER_BANK_REFRESH: Hybrid Mode
9134 23:19:16.365701 TX_TRACKING: ON
9135 23:19:16.375892 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9136 23:19:16.381778 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9137 23:19:16.391585 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9138 23:19:16.395272 [FAST_K] Save calibration result to emmc
9139 23:19:16.395408 sync common calibartion params.
9140 23:19:16.398897 sync cbt_mode0:1, 1:1
9141 23:19:16.401807 dram_init: ddr_geometry: 2
9142 23:19:16.405234 dram_init: ddr_geometry: 2
9143 23:19:16.405319 dram_init: ddr_geometry: 2
9144 23:19:16.408597 0:dram_rank_size:100000000
9145 23:19:16.412153 1:dram_rank_size:100000000
9146 23:19:16.415598 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9147 23:19:16.417941 DFS_SHUFFLE_HW_MODE: ON
9148 23:19:16.421488 dramc_set_vcore_voltage set vcore to 725000
9149 23:19:16.424957 Read voltage for 1600, 0
9150 23:19:16.425072 Vio18 = 0
9151 23:19:16.427663 Vcore = 725000
9152 23:19:16.427753 Vdram = 0
9153 23:19:16.427818 Vddq = 0
9154 23:19:16.431374 Vmddr = 0
9155 23:19:16.431482 switch to 3200 Mbps bootup
9156 23:19:16.434742 [DramcRunTimeConfig]
9157 23:19:16.434824 PHYPLL
9158 23:19:16.438135 DPM_CONTROL_AFTERK: ON
9159 23:19:16.438216 PER_BANK_REFRESH: ON
9160 23:19:16.441129 REFRESH_OVERHEAD_REDUCTION: ON
9161 23:19:16.444792 CMD_PICG_NEW_MODE: OFF
9162 23:19:16.444874 XRTWTW_NEW_MODE: ON
9163 23:19:16.448315 XRTRTR_NEW_MODE: ON
9164 23:19:16.448397 TX_TRACKING: ON
9165 23:19:16.451922 RDSEL_TRACKING: OFF
9166 23:19:16.454661 DQS Precalculation for DVFS: ON
9167 23:19:16.454743 RX_TRACKING: OFF
9168 23:19:16.458148 HW_GATING DBG: ON
9169 23:19:16.458230 ZQCS_ENABLE_LP4: ON
9170 23:19:16.461093 RX_PICG_NEW_MODE: ON
9171 23:19:16.461253 TX_PICG_NEW_MODE: ON
9172 23:19:16.464557 ENABLE_RX_DCM_DPHY: ON
9173 23:19:16.467752 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9174 23:19:16.471255 DUMMY_READ_FOR_TRACKING: OFF
9175 23:19:16.471336 !!! SPM_CONTROL_AFTERK: OFF
9176 23:19:16.474085 !!! SPM could not control APHY
9177 23:19:16.477508 IMPEDANCE_TRACKING: ON
9178 23:19:16.477592 TEMP_SENSOR: ON
9179 23:19:16.481122 HW_SAVE_FOR_SR: OFF
9180 23:19:16.484370 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9181 23:19:16.487102 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9182 23:19:16.490840 Read ODT Tracking: ON
9183 23:19:16.490925 Refresh Rate DeBounce: ON
9184 23:19:16.493998 DFS_NO_QUEUE_FLUSH: ON
9185 23:19:16.497330 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9186 23:19:16.500900 ENABLE_DFS_RUNTIME_MRW: OFF
9187 23:19:16.500984 DDR_RESERVE_NEW_MODE: ON
9188 23:19:16.503865 MR_CBT_SWITCH_FREQ: ON
9189 23:19:16.507488 =========================
9190 23:19:16.524929 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9191 23:19:16.528348 dram_init: ddr_geometry: 2
9192 23:19:16.546282 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9193 23:19:16.549693 dram_init: dram init end (result: 0)
9194 23:19:16.556219 DRAM-K: Full calibration passed in 24623 msecs
9195 23:19:16.559636 MRC: failed to locate region type 0.
9196 23:19:16.559730 DRAM rank0 size:0x100000000,
9197 23:19:16.563377 DRAM rank1 size=0x100000000
9198 23:19:16.572704 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9199 23:19:16.578986 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9200 23:19:16.586057 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9201 23:19:16.595544 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9202 23:19:16.595668 DRAM rank0 size:0x100000000,
9203 23:19:16.598808 DRAM rank1 size=0x100000000
9204 23:19:16.598893 CBMEM:
9205 23:19:16.602230 IMD: root @ 0xfffff000 254 entries.
9206 23:19:16.605667 IMD: root @ 0xffffec00 62 entries.
9207 23:19:16.608671 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9208 23:19:16.615064 WARNING: RO_VPD is uninitialized or empty.
9209 23:19:16.618632 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9210 23:19:16.626261 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9211 23:19:16.639110 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9212 23:19:16.650274 BS: romstage times (exec / console): total (unknown) / 24126 ms
9213 23:19:16.650357
9214 23:19:16.650423
9215 23:19:16.660843 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9216 23:19:16.663126 ARM64: Exception handlers installed.
9217 23:19:16.666939 ARM64: Testing exception
9218 23:19:16.670507 ARM64: Done test exception
9219 23:19:16.670590 Enumerating buses...
9220 23:19:16.673760 Show all devs... Before device enumeration.
9221 23:19:16.676549 Root Device: enabled 1
9222 23:19:16.679817 CPU_CLUSTER: 0: enabled 1
9223 23:19:16.679899 CPU: 00: enabled 1
9224 23:19:16.683007 Compare with tree...
9225 23:19:16.683089 Root Device: enabled 1
9226 23:19:16.686260 CPU_CLUSTER: 0: enabled 1
9227 23:19:16.689550 CPU: 00: enabled 1
9228 23:19:16.689633 Root Device scanning...
9229 23:19:16.693103 scan_static_bus for Root Device
9230 23:19:16.696517 CPU_CLUSTER: 0 enabled
9231 23:19:16.699662 scan_static_bus for Root Device done
9232 23:19:16.703446 scan_bus: bus Root Device finished in 8 msecs
9233 23:19:16.703528 done
9234 23:19:16.710110 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9235 23:19:16.712621 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9236 23:19:16.719041 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9237 23:19:16.726784 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9238 23:19:16.726867 Allocating resources...
9239 23:19:16.729132 Reading resources...
9240 23:19:16.732936 Root Device read_resources bus 0 link: 0
9241 23:19:16.736680 DRAM rank0 size:0x100000000,
9242 23:19:16.736762 DRAM rank1 size=0x100000000
9243 23:19:16.742297 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9244 23:19:16.742380 CPU: 00 missing read_resources
9245 23:19:16.749266 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9246 23:19:16.752352 Root Device read_resources bus 0 link: 0 done
9247 23:19:16.756298 Done reading resources.
9248 23:19:16.759309 Show resources in subtree (Root Device)...After reading.
9249 23:19:16.762084 Root Device child on link 0 CPU_CLUSTER: 0
9250 23:19:16.765213 CPU_CLUSTER: 0 child on link 0 CPU: 00
9251 23:19:16.775467 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9252 23:19:16.775568 CPU: 00
9253 23:19:16.782387 Root Device assign_resources, bus 0 link: 0
9254 23:19:16.785450 CPU_CLUSTER: 0 missing set_resources
9255 23:19:16.788318 Root Device assign_resources, bus 0 link: 0 done
9256 23:19:16.791446 Done setting resources.
9257 23:19:16.796132 Show resources in subtree (Root Device)...After assigning values.
9258 23:19:16.801466 Root Device child on link 0 CPU_CLUSTER: 0
9259 23:19:16.805144 CPU_CLUSTER: 0 child on link 0 CPU: 00
9260 23:19:16.811419 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9261 23:19:16.814538 CPU: 00
9262 23:19:16.814620 Done allocating resources.
9263 23:19:16.821654 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9264 23:19:16.824301 Enabling resources...
9265 23:19:16.824383 done.
9266 23:19:16.827618 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9267 23:19:16.831159 Initializing devices...
9268 23:19:16.831241 Root Device init
9269 23:19:16.835194 init hardware done!
9270 23:19:16.837471 0x00000018: ctrlr->caps
9271 23:19:16.837556 52.000 MHz: ctrlr->f_max
9272 23:19:16.841095 0.400 MHz: ctrlr->f_min
9273 23:19:16.844323 0x40ff8080: ctrlr->voltages
9274 23:19:16.844406 sclk: 390625
9275 23:19:16.844471 Bus Width = 1
9276 23:19:16.847507 sclk: 390625
9277 23:19:16.847589 Bus Width = 1
9278 23:19:16.851249 Early init status = 3
9279 23:19:16.854342 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9280 23:19:16.858094 in-header: 03 fc 00 00 01 00 00 00
9281 23:19:16.862572 in-data: 00
9282 23:19:16.864151 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9283 23:19:16.869316 in-header: 03 fd 00 00 00 00 00 00
9284 23:19:16.872478 in-data:
9285 23:19:16.875515 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9286 23:19:16.879468 in-header: 03 fc 00 00 01 00 00 00
9287 23:19:16.882775 in-data: 00
9288 23:19:16.885768 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9289 23:19:16.891186 in-header: 03 fd 00 00 00 00 00 00
9290 23:19:16.894548 in-data:
9291 23:19:16.898192 [SSUSB] Setting up USB HOST controller...
9292 23:19:16.901242 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9293 23:19:16.904517 [SSUSB] phy power-on done.
9294 23:19:16.907524 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9295 23:19:16.915392 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9296 23:19:16.917589 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9297 23:19:16.924421 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9298 23:19:16.930662 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9299 23:19:16.937098 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9300 23:19:16.943916 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9301 23:19:16.950596 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9302 23:19:16.953974 SPM: binary array size = 0x9dc
9303 23:19:16.957246 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9304 23:19:16.965098 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9305 23:19:16.970448 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9306 23:19:16.976699 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9307 23:19:16.980891 configure_display: Starting display init
9308 23:19:17.014630 anx7625_power_on_init: Init interface.
9309 23:19:17.017845 anx7625_disable_pd_protocol: Disabled PD feature.
9310 23:19:17.021020 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9311 23:19:17.049698 anx7625_start_dp_work: Secure OCM version=00
9312 23:19:17.052186 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9313 23:19:17.067608 sp_tx_get_edid_block: EDID Block = 1
9314 23:19:17.169487 Extracted contents:
9315 23:19:17.172806 header: 00 ff ff ff ff ff ff 00
9316 23:19:17.176804 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9317 23:19:17.180380 version: 01 04
9318 23:19:17.182462 basic params: 95 1f 11 78 0a
9319 23:19:17.186375 chroma info: 76 90 94 55 54 90 27 21 50 54
9320 23:19:17.188911 established: 00 00 00
9321 23:19:17.195526 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9322 23:19:17.202760 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9323 23:19:17.206116 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9324 23:19:17.212382 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9325 23:19:17.218898 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9326 23:19:17.222306 extensions: 00
9327 23:19:17.222388 checksum: fb
9328 23:19:17.222453
9329 23:19:17.228953 Manufacturer: IVO Model 57d Serial Number 0
9330 23:19:17.229036 Made week 0 of 2020
9331 23:19:17.231976 EDID version: 1.4
9332 23:19:17.232095 Digital display
9333 23:19:17.235002 6 bits per primary color channel
9334 23:19:17.238630 DisplayPort interface
9335 23:19:17.238712 Maximum image size: 31 cm x 17 cm
9336 23:19:17.241907 Gamma: 220%
9337 23:19:17.241988 Check DPMS levels
9338 23:19:17.248719 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9339 23:19:17.251818 First detailed timing is preferred timing
9340 23:19:17.255127 Established timings supported:
9341 23:19:17.255208 Standard timings supported:
9342 23:19:17.258738 Detailed timings
9343 23:19:17.261589 Hex of detail: 383680a07038204018303c0035ae10000019
9344 23:19:17.268753 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9345 23:19:17.271533 0780 0798 07c8 0820 hborder 0
9346 23:19:17.274478 0438 043b 0447 0458 vborder 0
9347 23:19:17.277982 -hsync -vsync
9348 23:19:17.278064 Did detailed timing
9349 23:19:17.284675 Hex of detail: 000000000000000000000000000000000000
9350 23:19:17.287861 Manufacturer-specified data, tag 0
9351 23:19:17.291762 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9352 23:19:17.294650 ASCII string: InfoVision
9353 23:19:17.297890 Hex of detail: 000000fe00523134304e574635205248200a
9354 23:19:17.301149 ASCII string: R140NWF5 RH
9355 23:19:17.301250 Checksum
9356 23:19:17.304531 Checksum: 0xfb (valid)
9357 23:19:17.308084 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9358 23:19:17.311114 DSI data_rate: 832800000 bps
9359 23:19:17.317736 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9360 23:19:17.321344 anx7625_parse_edid: pixelclock(138800).
9361 23:19:17.324284 hactive(1920), hsync(48), hfp(24), hbp(88)
9362 23:19:17.327642 vactive(1080), vsync(12), vfp(3), vbp(17)
9363 23:19:17.330967 anx7625_dsi_config: config dsi.
9364 23:19:17.337930 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9365 23:19:17.351535 anx7625_dsi_config: success to config DSI
9366 23:19:17.354697 anx7625_dp_start: MIPI phy setup OK.
9367 23:19:17.358062 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9368 23:19:17.361658 mtk_ddp_mode_set invalid vrefresh 60
9369 23:19:17.364660 main_disp_path_setup
9370 23:19:17.364742 ovl_layer_smi_id_en
9371 23:19:17.368042 ovl_layer_smi_id_en
9372 23:19:17.368124 ccorr_config
9373 23:19:17.368189 aal_config
9374 23:19:17.372188 gamma_config
9375 23:19:17.372270 postmask_config
9376 23:19:17.374941 dither_config
9377 23:19:17.377993 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9378 23:19:17.385342 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9379 23:19:17.387862 Root Device init finished in 552 msecs
9380 23:19:17.391709 CPU_CLUSTER: 0 init
9381 23:19:17.397524 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9382 23:19:17.404312 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9383 23:19:17.404396 APU_MBOX 0x190000b0 = 0x10001
9384 23:19:17.408381 APU_MBOX 0x190001b0 = 0x10001
9385 23:19:17.411033 APU_MBOX 0x190005b0 = 0x10001
9386 23:19:17.414097 APU_MBOX 0x190006b0 = 0x10001
9387 23:19:17.420343 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9388 23:19:17.430946 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9389 23:19:17.442926 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9390 23:19:17.449484 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9391 23:19:17.461359 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9392 23:19:17.470309 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9393 23:19:17.473719 CPU_CLUSTER: 0 init finished in 81 msecs
9394 23:19:17.476938 Devices initialized
9395 23:19:17.480349 Show all devs... After init.
9396 23:19:17.480436 Root Device: enabled 1
9397 23:19:17.483586 CPU_CLUSTER: 0: enabled 1
9398 23:19:17.486782 CPU: 00: enabled 1
9399 23:19:17.489902 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9400 23:19:17.492973 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9401 23:19:17.496807 ELOG: NV offset 0x57f000 size 0x1000
9402 23:19:17.504164 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9403 23:19:17.510265 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9404 23:19:17.513161 ELOG: Event(17) added with size 13 at 2024-04-03 23:19:18 UTC
9405 23:19:17.519599 out: cmd=0x121: 03 db 21 01 00 00 00 00
9406 23:19:17.523186 in-header: 03 a1 00 00 2c 00 00 00
9407 23:19:17.536310 in-data: be 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9408 23:19:17.540465 ELOG: Event(A1) added with size 10 at 2024-04-03 23:19:18 UTC
9409 23:19:17.549465 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9410 23:19:17.553000 ELOG: Event(A0) added with size 9 at 2024-04-03 23:19:18 UTC
9411 23:19:17.556525 elog_add_boot_reason: Logged dev mode boot
9412 23:19:17.563061 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9413 23:19:17.563145 Finalize devices...
9414 23:19:17.566159 Devices finalized
9415 23:19:17.569544 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9416 23:19:17.572377 Writing coreboot table at 0xffe64000
9417 23:19:17.579031 0. 000000000010a000-0000000000113fff: RAMSTAGE
9418 23:19:17.583085 1. 0000000040000000-00000000400fffff: RAM
9419 23:19:17.586280 2. 0000000040100000-000000004032afff: RAMSTAGE
9420 23:19:17.588936 3. 000000004032b000-00000000545fffff: RAM
9421 23:19:17.595940 4. 0000000054600000-000000005465ffff: BL31
9422 23:19:17.599187 5. 0000000054660000-00000000ffe63fff: RAM
9423 23:19:17.602653 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9424 23:19:17.606166 7. 0000000100000000-000000023fffffff: RAM
9425 23:19:17.608694 Passing 5 GPIOs to payload:
9426 23:19:17.615957 NAME | PORT | POLARITY | VALUE
9427 23:19:17.618539 EC in RW | 0x000000aa | low | undefined
9428 23:19:17.621966 EC interrupt | 0x00000005 | low | undefined
9429 23:19:17.628503 TPM interrupt | 0x000000ab | high | undefined
9430 23:19:17.633455 SD card detect | 0x00000011 | high | undefined
9431 23:19:17.638565 speaker enable | 0x00000093 | high | undefined
9432 23:19:17.641617 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9433 23:19:17.644908 in-header: 03 f9 00 00 02 00 00 00
9434 23:19:17.644990 in-data: 02 00
9435 23:19:17.648176 ADC[4]: Raw value=903400 ID=7
9436 23:19:17.651554 ADC[3]: Raw value=214021 ID=1
9437 23:19:17.651635 RAM Code: 0x71
9438 23:19:17.655201 ADC[6]: Raw value=75036 ID=0
9439 23:19:17.658424 ADC[5]: Raw value=213282 ID=1
9440 23:19:17.658507 SKU Code: 0x1
9441 23:19:17.664671 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum dda9
9442 23:19:17.667832 coreboot table: 964 bytes.
9443 23:19:17.671400 IMD ROOT 0. 0xfffff000 0x00001000
9444 23:19:17.674534 IMD SMALL 1. 0xffffe000 0x00001000
9445 23:19:17.677675 RO MCACHE 2. 0xffffc000 0x00001104
9446 23:19:17.681424 CONSOLE 3. 0xfff7c000 0x00080000
9447 23:19:17.684580 FMAP 4. 0xfff7b000 0x00000452
9448 23:19:17.688049 TIME STAMP 5. 0xfff7a000 0x00000910
9449 23:19:17.691044 VBOOT WORK 6. 0xfff66000 0x00014000
9450 23:19:17.694264 RAMOOPS 7. 0xffe66000 0x00100000
9451 23:19:17.697639 COREBOOT 8. 0xffe64000 0x00002000
9452 23:19:17.697723 IMD small region:
9453 23:19:17.701510 IMD ROOT 0. 0xffffec00 0x00000400
9454 23:19:17.704616 VPD 1. 0xffffeb80 0x0000006c
9455 23:19:17.707354 MMC STATUS 2. 0xffffeb60 0x00000004
9456 23:19:17.714539 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9457 23:19:17.717995 Probing TPM: done!
9458 23:19:17.720655 Connected to device vid:did:rid of 1ae0:0028:00
9459 23:19:17.731038 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9460 23:19:17.733766 Initialized TPM device CR50 revision 0
9461 23:19:17.737738 Checking cr50 for pending updates
9462 23:19:17.741722 Reading cr50 TPM mode
9463 23:19:17.749458 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9464 23:19:17.756385 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9465 23:19:17.796488 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9466 23:19:17.799568 Checking segment from ROM address 0x40100000
9467 23:19:17.803415 Checking segment from ROM address 0x4010001c
9468 23:19:17.810027 Loading segment from ROM address 0x40100000
9469 23:19:17.810110 code (compression=0)
9470 23:19:17.819412 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9471 23:19:17.826080 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9472 23:19:17.826192 it's not compressed!
9473 23:19:17.833040 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9474 23:19:17.839253 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9475 23:19:17.856556 Loading segment from ROM address 0x4010001c
9476 23:19:17.856639 Entry Point 0x80000000
9477 23:19:17.860034 Loaded segments
9478 23:19:17.863590 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9479 23:19:17.869911 Jumping to boot code at 0x80000000(0xffe64000)
9480 23:19:17.876762 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9481 23:19:17.883043 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9482 23:19:17.891912 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9483 23:19:17.894526 Checking segment from ROM address 0x40100000
9484 23:19:17.897519 Checking segment from ROM address 0x4010001c
9485 23:19:17.904523 Loading segment from ROM address 0x40100000
9486 23:19:17.904606 code (compression=1)
9487 23:19:17.911037 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9488 23:19:17.921299 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9489 23:19:17.921381 using LZMA
9490 23:19:17.929597 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9491 23:19:17.936099 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9492 23:19:17.939489 Loading segment from ROM address 0x4010001c
9493 23:19:17.939570 Entry Point 0x54601000
9494 23:19:17.942835 Loaded segments
9495 23:19:17.945960 NOTICE: MT8192 bl31_setup
9496 23:19:17.953213 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9497 23:19:17.956722 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9498 23:19:17.959674 WARNING: region 0:
9499 23:19:17.963507 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 23:19:17.963590 WARNING: region 1:
9501 23:19:17.970118 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9502 23:19:17.973571 WARNING: region 2:
9503 23:19:17.976177 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9504 23:19:17.979603 WARNING: region 3:
9505 23:19:17.983083 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9506 23:19:17.986165 WARNING: region 4:
9507 23:19:17.993249 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9508 23:19:17.993331 WARNING: region 5:
9509 23:19:17.996230 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9510 23:19:17.999353 WARNING: region 6:
9511 23:19:18.003079 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 23:19:18.006299 WARNING: region 7:
9513 23:19:18.009297 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 23:19:18.015990 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9515 23:19:18.019115 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9516 23:19:18.025585 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9517 23:19:18.029417 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9518 23:19:18.032222 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9519 23:19:18.038846 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9520 23:19:18.042112 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9521 23:19:18.045683 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9522 23:19:18.052702 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9523 23:19:18.055610 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9524 23:19:18.062412 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9525 23:19:18.065897 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9526 23:19:18.069155 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9527 23:19:18.075637 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9528 23:19:18.079157 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9529 23:19:18.082387 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9530 23:19:18.088525 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9531 23:19:18.092016 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9532 23:19:18.098693 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9533 23:19:18.102164 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9534 23:19:18.105860 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9535 23:19:18.112224 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9536 23:19:18.115250 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9537 23:19:18.122110 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9538 23:19:18.124914 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9539 23:19:18.128879 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9540 23:19:18.136025 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9541 23:19:18.138399 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9542 23:19:18.145124 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9543 23:19:18.148763 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9544 23:19:18.152159 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9545 23:19:18.158837 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9546 23:19:18.161944 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9547 23:19:18.164903 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9548 23:19:18.168419 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9549 23:19:18.174985 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9550 23:19:18.178432 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9551 23:19:18.182149 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9552 23:19:18.184979 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9553 23:19:18.191915 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9554 23:19:18.195474 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9555 23:19:18.198531 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9556 23:19:18.202149 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9557 23:19:18.207985 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9558 23:19:18.211287 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9559 23:19:18.214679 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9560 23:19:18.221595 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9561 23:19:18.224731 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9562 23:19:18.227880 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9563 23:19:18.234877 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9564 23:19:18.239207 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9565 23:19:18.244741 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9566 23:19:18.248216 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9567 23:19:18.251093 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9568 23:19:18.257833 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9569 23:19:18.260882 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9570 23:19:18.267503 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9571 23:19:18.271421 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9572 23:19:18.278436 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9573 23:19:18.281005 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9574 23:19:18.287635 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9575 23:19:18.290968 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9576 23:19:18.294157 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9577 23:19:18.300596 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9578 23:19:18.304996 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9579 23:19:18.310923 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9580 23:19:18.314133 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9581 23:19:18.320648 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9582 23:19:18.323846 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9583 23:19:18.328109 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9584 23:19:18.334739 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9585 23:19:18.338099 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9586 23:19:18.344227 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9587 23:19:18.347206 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9588 23:19:18.354082 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9589 23:19:18.357524 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9590 23:19:18.360579 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9591 23:19:18.367680 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9592 23:19:18.370727 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9593 23:19:18.377100 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9594 23:19:18.380790 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9595 23:19:18.387427 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9596 23:19:18.390205 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9597 23:19:18.397196 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9598 23:19:18.400446 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9599 23:19:18.404246 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9600 23:19:18.410053 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9601 23:19:18.413557 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9602 23:19:18.421051 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9603 23:19:18.423504 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9604 23:19:18.430445 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9605 23:19:18.433325 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9606 23:19:18.440003 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9607 23:19:18.443382 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9608 23:19:18.449707 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9609 23:19:18.453441 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9610 23:19:18.456435 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9611 23:19:18.463120 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9612 23:19:18.466222 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9613 23:19:18.469774 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9614 23:19:18.472880 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9615 23:19:18.479573 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9616 23:19:18.483870 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9617 23:19:18.489760 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9618 23:19:18.493176 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9619 23:19:18.496172 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9620 23:19:18.503246 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9621 23:19:18.506206 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9622 23:19:18.512430 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9623 23:19:18.515971 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9624 23:19:18.519603 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9625 23:19:18.526139 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9626 23:19:18.529747 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9627 23:19:18.535695 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9628 23:19:18.538905 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9629 23:19:18.542786 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9630 23:19:18.549165 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9631 23:19:18.552801 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9632 23:19:18.555449 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9633 23:19:18.562359 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9634 23:19:18.565291 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9635 23:19:18.569303 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9636 23:19:18.571839 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9637 23:19:18.579229 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9638 23:19:18.582064 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9639 23:19:18.585335 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9640 23:19:18.591779 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9641 23:19:18.595101 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9642 23:19:18.601507 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9643 23:19:18.605418 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9644 23:19:18.608317 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9645 23:19:18.614806 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9646 23:19:18.618192 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9647 23:19:18.624744 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9648 23:19:18.628278 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9649 23:19:18.631588 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9650 23:19:18.638109 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9651 23:19:18.641559 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9652 23:19:18.648302 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9653 23:19:18.651117 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9654 23:19:18.655096 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9655 23:19:18.661472 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9656 23:19:18.664535 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9657 23:19:18.671119 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9658 23:19:18.674900 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9659 23:19:18.677923 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9660 23:19:18.684719 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9661 23:19:18.687777 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9662 23:19:18.694901 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9663 23:19:18.698685 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9664 23:19:18.701387 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9665 23:19:18.708077 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9666 23:19:18.710897 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9667 23:19:18.714513 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9668 23:19:18.721071 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9669 23:19:18.724232 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9670 23:19:18.730911 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9671 23:19:18.733999 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9672 23:19:18.737454 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9673 23:19:18.744223 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9674 23:19:18.747127 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9675 23:19:18.753710 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9676 23:19:18.757870 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9677 23:19:18.760980 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9678 23:19:18.767172 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9679 23:19:18.770558 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9680 23:19:18.777235 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9681 23:19:18.780298 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9682 23:19:18.783875 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9683 23:19:18.790133 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9684 23:19:18.793714 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9685 23:19:18.800502 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9686 23:19:18.803836 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9687 23:19:18.807113 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9688 23:19:18.813479 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9689 23:19:18.816960 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9690 23:19:18.823262 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9691 23:19:18.826443 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9692 23:19:18.830029 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9693 23:19:18.836117 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9694 23:19:18.839838 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9695 23:19:18.846021 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9696 23:19:18.849836 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9697 23:19:18.853296 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9698 23:19:18.859523 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9699 23:19:18.863434 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9700 23:19:18.869081 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9701 23:19:18.872548 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9702 23:19:18.879200 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9703 23:19:18.882719 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9704 23:19:18.885460 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9705 23:19:18.892118 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9706 23:19:18.895646 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9707 23:19:18.902764 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9708 23:19:18.905779 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9709 23:19:18.912391 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9710 23:19:18.915877 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9711 23:19:18.918412 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9712 23:19:18.925321 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9713 23:19:18.928260 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9714 23:19:18.935169 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9715 23:19:18.938208 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9716 23:19:18.944645 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9717 23:19:18.947814 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9718 23:19:18.951656 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9719 23:19:18.957853 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9720 23:19:18.961057 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9721 23:19:18.968961 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9722 23:19:18.971087 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9723 23:19:18.978140 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9724 23:19:18.981124 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9725 23:19:18.985025 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9726 23:19:18.990709 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9727 23:19:18.993923 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9728 23:19:19.000685 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9729 23:19:19.004144 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9730 23:19:19.010870 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9731 23:19:19.014331 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9732 23:19:19.017602 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9733 23:19:19.024202 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9734 23:19:19.026801 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9735 23:19:19.033579 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9736 23:19:19.037024 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9737 23:19:19.043158 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9738 23:19:19.046603 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9739 23:19:19.053072 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9740 23:19:19.056450 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9741 23:19:19.059512 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9742 23:19:19.066980 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9743 23:19:19.069503 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9744 23:19:19.073014 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9745 23:19:19.076067 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9746 23:19:19.082503 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9747 23:19:19.086316 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9748 23:19:19.089564 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9749 23:19:19.095603 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9750 23:19:19.099254 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9751 23:19:19.106399 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9752 23:19:19.109019 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9753 23:19:19.112501 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9754 23:19:19.119614 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9755 23:19:19.122655 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9756 23:19:19.125842 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9757 23:19:19.132271 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9758 23:19:19.135703 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9759 23:19:19.139299 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9760 23:19:19.145762 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9761 23:19:19.148767 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9762 23:19:19.155427 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9763 23:19:19.158886 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9764 23:19:19.162337 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9765 23:19:19.168573 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9766 23:19:19.171876 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9767 23:19:19.175160 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9768 23:19:19.181868 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9769 23:19:19.185045 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9770 23:19:19.191797 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9771 23:19:19.195468 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9772 23:19:19.198393 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9773 23:19:19.205055 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9774 23:19:19.207937 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9775 23:19:19.214376 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9776 23:19:19.217843 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9777 23:19:19.221510 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9778 23:19:19.227665 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9779 23:19:19.231396 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9780 23:19:19.234682 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9781 23:19:19.241158 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9782 23:19:19.244398 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9783 23:19:19.247527 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9784 23:19:19.253839 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9785 23:19:19.258023 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9786 23:19:19.260565 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9787 23:19:19.264269 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9788 23:19:19.267466 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9789 23:19:19.273957 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9790 23:19:19.277161 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9791 23:19:19.280576 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9792 23:19:19.287454 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9793 23:19:19.290297 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9794 23:19:19.294059 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9795 23:19:19.297185 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9796 23:19:19.303467 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9797 23:19:19.306979 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9798 23:19:19.313375 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9799 23:19:19.316760 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9800 23:19:19.323842 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9801 23:19:19.327345 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9802 23:19:19.330259 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9803 23:19:19.337095 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9804 23:19:19.340013 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9805 23:19:19.346625 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9806 23:19:19.350206 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9807 23:19:19.353462 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9808 23:19:19.359794 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9809 23:19:19.362961 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9810 23:19:19.369595 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9811 23:19:19.373027 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9812 23:19:19.376526 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9813 23:19:19.383323 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9814 23:19:19.385930 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9815 23:19:19.393005 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9816 23:19:19.396515 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9817 23:19:19.402537 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9818 23:19:19.405835 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9819 23:19:19.409592 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9820 23:19:19.415856 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9821 23:19:19.419449 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9822 23:19:19.426161 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9823 23:19:19.428900 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9824 23:19:19.435625 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9825 23:19:19.438807 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9826 23:19:19.442164 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9827 23:19:19.449127 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9828 23:19:19.452086 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9829 23:19:19.458847 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9830 23:19:19.462527 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9831 23:19:19.465873 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9832 23:19:19.472088 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9833 23:19:19.475220 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9834 23:19:19.482139 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9835 23:19:19.485013 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9836 23:19:19.489091 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9837 23:19:19.494692 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9838 23:19:19.498607 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9839 23:19:19.505307 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9840 23:19:19.507915 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9841 23:19:19.514696 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9842 23:19:19.517873 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9843 23:19:19.521862 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9844 23:19:19.527490 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9845 23:19:19.531236 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9846 23:19:19.537756 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9847 23:19:19.540918 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9848 23:19:19.547999 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9849 23:19:19.551107 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9850 23:19:19.554528 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9851 23:19:19.561319 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9852 23:19:19.564805 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9853 23:19:19.571137 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9854 23:19:19.574590 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9855 23:19:19.580560 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9856 23:19:19.583840 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9857 23:19:19.586965 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9858 23:19:19.593521 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9859 23:19:19.597171 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9860 23:19:19.603556 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9861 23:19:19.607782 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9862 23:19:19.610273 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9863 23:19:19.616648 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9864 23:19:19.620117 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9865 23:19:19.626866 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9866 23:19:19.629841 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9867 23:19:19.633421 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9868 23:19:19.639904 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9869 23:19:19.643240 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9870 23:19:19.650219 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9871 23:19:19.653223 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9872 23:19:19.659781 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9873 23:19:19.663349 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9874 23:19:19.669454 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9875 23:19:19.673122 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9876 23:19:19.676719 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9877 23:19:19.683189 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9878 23:19:19.686642 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9879 23:19:19.692989 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9880 23:19:19.697544 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9881 23:19:19.703123 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9882 23:19:19.706182 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9883 23:19:19.712576 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9884 23:19:19.715977 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9885 23:19:19.719486 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9886 23:19:19.726382 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9887 23:19:19.729173 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9888 23:19:19.735665 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9889 23:19:19.739064 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9890 23:19:19.746058 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9891 23:19:19.749982 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9892 23:19:19.752218 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9893 23:19:19.758803 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9894 23:19:19.762065 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9895 23:19:19.768649 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9896 23:19:19.772204 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9897 23:19:19.778652 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9898 23:19:19.781863 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9899 23:19:19.788589 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9900 23:19:19.791890 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9901 23:19:19.798856 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9902 23:19:19.802846 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9903 23:19:19.805256 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9904 23:19:19.811488 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9905 23:19:19.814724 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9906 23:19:19.822011 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9907 23:19:19.824710 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9908 23:19:19.831754 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9909 23:19:19.834686 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9910 23:19:19.841397 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9911 23:19:19.844922 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9912 23:19:19.847802 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9913 23:19:19.854228 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9914 23:19:19.858186 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9915 23:19:19.864650 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9916 23:19:19.867467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9917 23:19:19.871245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9918 23:19:19.878163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9919 23:19:19.880557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9920 23:19:19.887254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9921 23:19:19.890899 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9922 23:19:19.897122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9923 23:19:19.900746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9924 23:19:19.907055 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9925 23:19:19.910261 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9926 23:19:19.917847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9927 23:19:19.920928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9928 23:19:19.926890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9929 23:19:19.930435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9930 23:19:19.936839 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9931 23:19:19.940373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9932 23:19:19.946844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9933 23:19:19.950284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9934 23:19:19.957220 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9935 23:19:19.959807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9936 23:19:19.966851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9937 23:19:19.970079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9938 23:19:19.976226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9939 23:19:19.980007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9940 23:19:19.986346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9941 23:19:19.989416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9942 23:19:19.996373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9943 23:19:19.999100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9944 23:19:20.006009 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9945 23:19:20.013344 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9946 23:19:20.015766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9947 23:19:20.022298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9948 23:19:20.025440 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9949 23:19:20.025511 INFO: [APUAPC] vio 0
9950 23:19:20.033099 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9951 23:19:20.036110 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9952 23:19:20.039464 INFO: [APUAPC] D0_APC_0: 0x400510
9953 23:19:20.043414 INFO: [APUAPC] D0_APC_1: 0x0
9954 23:19:20.046320 INFO: [APUAPC] D0_APC_2: 0x1540
9955 23:19:20.049631 INFO: [APUAPC] D0_APC_3: 0x0
9956 23:19:20.052568 INFO: [APUAPC] D1_APC_0: 0xffffffff
9957 23:19:20.055776 INFO: [APUAPC] D1_APC_1: 0xffffffff
9958 23:19:20.060029 INFO: [APUAPC] D1_APC_2: 0x3fffff
9959 23:19:20.062386 INFO: [APUAPC] D1_APC_3: 0x0
9960 23:19:20.066396 INFO: [APUAPC] D2_APC_0: 0xffffffff
9961 23:19:20.069614 INFO: [APUAPC] D2_APC_1: 0xffffffff
9962 23:19:20.072515 INFO: [APUAPC] D2_APC_2: 0x3fffff
9963 23:19:20.076005 INFO: [APUAPC] D2_APC_3: 0x0
9964 23:19:20.078906 INFO: [APUAPC] D3_APC_0: 0xffffffff
9965 23:19:20.082531 INFO: [APUAPC] D3_APC_1: 0xffffffff
9966 23:19:20.085600 INFO: [APUAPC] D3_APC_2: 0x3fffff
9967 23:19:20.089141 INFO: [APUAPC] D3_APC_3: 0x0
9968 23:19:20.092089 INFO: [APUAPC] D4_APC_0: 0xffffffff
9969 23:19:20.095277 INFO: [APUAPC] D4_APC_1: 0xffffffff
9970 23:19:20.098601 INFO: [APUAPC] D4_APC_2: 0x3fffff
9971 23:19:20.102123 INFO: [APUAPC] D4_APC_3: 0x0
9972 23:19:20.105634 INFO: [APUAPC] D5_APC_0: 0xffffffff
9973 23:19:20.108836 INFO: [APUAPC] D5_APC_1: 0xffffffff
9974 23:19:20.111942 INFO: [APUAPC] D5_APC_2: 0x3fffff
9975 23:19:20.115656 INFO: [APUAPC] D5_APC_3: 0x0
9976 23:19:20.118629 INFO: [APUAPC] D6_APC_0: 0xffffffff
9977 23:19:20.121420 INFO: [APUAPC] D6_APC_1: 0xffffffff
9978 23:19:20.125286 INFO: [APUAPC] D6_APC_2: 0x3fffff
9979 23:19:20.128298 INFO: [APUAPC] D6_APC_3: 0x0
9980 23:19:20.132329 INFO: [APUAPC] D7_APC_0: 0xffffffff
9981 23:19:20.134966 INFO: [APUAPC] D7_APC_1: 0xffffffff
9982 23:19:20.138903 INFO: [APUAPC] D7_APC_2: 0x3fffff
9983 23:19:20.138979 INFO: [APUAPC] D7_APC_3: 0x0
9984 23:19:20.144822 INFO: [APUAPC] D8_APC_0: 0xffffffff
9985 23:19:20.148016 INFO: [APUAPC] D8_APC_1: 0xffffffff
9986 23:19:20.151314 INFO: [APUAPC] D8_APC_2: 0x3fffff
9987 23:19:20.151393 INFO: [APUAPC] D8_APC_3: 0x0
9988 23:19:20.154612 INFO: [APUAPC] D9_APC_0: 0xffffffff
9989 23:19:20.161016 INFO: [APUAPC] D9_APC_1: 0xffffffff
9990 23:19:20.164892 INFO: [APUAPC] D9_APC_2: 0x3fffff
9991 23:19:20.164967 INFO: [APUAPC] D9_APC_3: 0x0
9992 23:19:20.168159 INFO: [APUAPC] D10_APC_0: 0xffffffff
9993 23:19:20.174425 INFO: [APUAPC] D10_APC_1: 0xffffffff
9994 23:19:20.177442 INFO: [APUAPC] D10_APC_2: 0x3fffff
9995 23:19:20.177514 INFO: [APUAPC] D10_APC_3: 0x0
9996 23:19:20.184802 INFO: [APUAPC] D11_APC_0: 0xffffffff
9997 23:19:20.187264 INFO: [APUAPC] D11_APC_1: 0xffffffff
9998 23:19:20.190931 INFO: [APUAPC] D11_APC_2: 0x3fffff
9999 23:19:20.194067 INFO: [APUAPC] D11_APC_3: 0x0
10000 23:19:20.197668 INFO: [APUAPC] D12_APC_0: 0xffffffff
10001 23:19:20.200992 INFO: [APUAPC] D12_APC_1: 0xffffffff
10002 23:19:20.204318 INFO: [APUAPC] D12_APC_2: 0x3fffff
10003 23:19:20.208133 INFO: [APUAPC] D12_APC_3: 0x0
10004 23:19:20.210606 INFO: [APUAPC] D13_APC_0: 0xffffffff
10005 23:19:20.213659 INFO: [APUAPC] D13_APC_1: 0xffffffff
10006 23:19:20.217232 INFO: [APUAPC] D13_APC_2: 0x3fffff
10007 23:19:20.220409 INFO: [APUAPC] D13_APC_3: 0x0
10008 23:19:20.224090 INFO: [APUAPC] D14_APC_0: 0xffffffff
10009 23:19:20.226816 INFO: [APUAPC] D14_APC_1: 0xffffffff
10010 23:19:20.230342 INFO: [APUAPC] D14_APC_2: 0x3fffff
10011 23:19:20.233689 INFO: [APUAPC] D14_APC_3: 0x0
10012 23:19:20.237059 INFO: [APUAPC] D15_APC_0: 0xffffffff
10013 23:19:20.240253 INFO: [APUAPC] D15_APC_1: 0xffffffff
10014 23:19:20.243410 INFO: [APUAPC] D15_APC_2: 0x3fffff
10015 23:19:20.247195 INFO: [APUAPC] D15_APC_3: 0x0
10016 23:19:20.250337 INFO: [APUAPC] APC_CON: 0x4
10017 23:19:20.250413 INFO: [NOCDAPC] D0_APC_0: 0x0
10018 23:19:20.253368 INFO: [NOCDAPC] D0_APC_1: 0x0
10019 23:19:20.257048 INFO: [NOCDAPC] D1_APC_0: 0x0
10020 23:19:20.260022 INFO: [NOCDAPC] D1_APC_1: 0xfff
10021 23:19:20.264184 INFO: [NOCDAPC] D2_APC_0: 0x0
10022 23:19:20.266637 INFO: [NOCDAPC] D2_APC_1: 0xfff
10023 23:19:20.269777 INFO: [NOCDAPC] D3_APC_0: 0x0
10024 23:19:20.273660 INFO: [NOCDAPC] D3_APC_1: 0xfff
10025 23:19:20.276654 INFO: [NOCDAPC] D4_APC_0: 0x0
10026 23:19:20.280228 INFO: [NOCDAPC] D4_APC_1: 0xfff
10027 23:19:20.283202 INFO: [NOCDAPC] D5_APC_0: 0x0
10028 23:19:20.286387 INFO: [NOCDAPC] D5_APC_1: 0xfff
10029 23:19:20.286460 INFO: [NOCDAPC] D6_APC_0: 0x0
10030 23:19:20.289984 INFO: [NOCDAPC] D6_APC_1: 0xfff
10031 23:19:20.292684 INFO: [NOCDAPC] D7_APC_0: 0x0
10032 23:19:20.296468 INFO: [NOCDAPC] D7_APC_1: 0xfff
10033 23:19:20.299394 INFO: [NOCDAPC] D8_APC_0: 0x0
10034 23:19:20.302741 INFO: [NOCDAPC] D8_APC_1: 0xfff
10035 23:19:20.305926 INFO: [NOCDAPC] D9_APC_0: 0x0
10036 23:19:20.309436 INFO: [NOCDAPC] D9_APC_1: 0xfff
10037 23:19:20.312661 INFO: [NOCDAPC] D10_APC_0: 0x0
10038 23:19:20.315767 INFO: [NOCDAPC] D10_APC_1: 0xfff
10039 23:19:20.319207 INFO: [NOCDAPC] D11_APC_0: 0x0
10040 23:19:20.322771 INFO: [NOCDAPC] D11_APC_1: 0xfff
10041 23:19:20.326357 INFO: [NOCDAPC] D12_APC_0: 0x0
10042 23:19:20.326433 INFO: [NOCDAPC] D12_APC_1: 0xfff
10043 23:19:20.329403 INFO: [NOCDAPC] D13_APC_0: 0x0
10044 23:19:20.332461 INFO: [NOCDAPC] D13_APC_1: 0xfff
10045 23:19:20.335655 INFO: [NOCDAPC] D14_APC_0: 0x0
10046 23:19:20.339328 INFO: [NOCDAPC] D14_APC_1: 0xfff
10047 23:19:20.342275 INFO: [NOCDAPC] D15_APC_0: 0x0
10048 23:19:20.345727 INFO: [NOCDAPC] D15_APC_1: 0xfff
10049 23:19:20.349602 INFO: [NOCDAPC] APC_CON: 0x4
10050 23:19:20.352492 INFO: [APUAPC] set_apusys_apc done
10051 23:19:20.356151 INFO: [DEVAPC] devapc_init done
10052 23:19:20.358752 INFO: GICv3 without legacy support detected.
10053 23:19:20.362518 INFO: ARM GICv3 driver initialized in EL3
10054 23:19:20.368727 INFO: Maximum SPI INTID supported: 639
10055 23:19:20.372070 INFO: BL31: Initializing runtime services
10056 23:19:20.378460 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10057 23:19:20.378578 INFO: SPM: enable CPC mode
10058 23:19:20.385690 INFO: mcdi ready for mcusys-off-idle and system suspend
10059 23:19:20.388175 INFO: BL31: Preparing for EL3 exit to normal world
10060 23:19:20.392207 INFO: Entry point address = 0x80000000
10061 23:19:20.395102 INFO: SPSR = 0x8
10062 23:19:20.400725
10063 23:19:20.400810
10064 23:19:20.400877
10065 23:19:20.404199 Starting depthcharge on Spherion...
10066 23:19:20.404274
10067 23:19:20.404344 Wipe memory regions:
10068 23:19:20.404407
10069 23:19:20.405096 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10070 23:19:20.405197 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10071 23:19:20.405282 Setting prompt string to ['asurada:']
10072 23:19:20.405361 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10073 23:19:20.407407 [0x00000040000000, 0x00000054600000)
10074 23:19:20.529982
10075 23:19:20.530101 [0x00000054660000, 0x00000080000000)
10076 23:19:20.791307
10077 23:19:20.791434 [0x000000821a7280, 0x000000ffe64000)
10078 23:19:21.535910
10079 23:19:21.536043 [0x00000100000000, 0x00000240000000)
10080 23:19:23.426278
10081 23:19:23.428939 Initializing XHCI USB controller at 0x11200000.
10082 23:19:24.466988
10083 23:19:24.470235 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10084 23:19:24.470317
10085 23:19:24.470382
10086 23:19:24.470452
10087 23:19:24.470772 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10089 23:19:24.571146 asurada: tftpboot 192.168.201.1 13248414/tftp-deploy-dekbzbsg/kernel/image.itb 13248414/tftp-deploy-dekbzbsg/kernel/cmdline
10090 23:19:24.571265 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10091 23:19:24.571359 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10092 23:19:24.575991 tftpboot 192.168.201.1 13248414/tftp-deploy-dekbzbsg/kernel/image.ittp-deploy-dekbzbsg/kernel/cmdline
10093 23:19:24.576117
10094 23:19:24.576199 Waiting for link
10095 23:19:24.736089
10096 23:19:24.736214 R8152: Initializing
10097 23:19:24.736283
10098 23:19:24.739362 Version 6 (ocp_data = 5c30)
10099 23:19:24.739477
10100 23:19:24.742870 R8152: Done initializing
10101 23:19:24.742945
10102 23:19:24.743016 Adding net device
10103 23:19:26.646056
10104 23:19:26.646204 done.
10105 23:19:26.646295
10106 23:19:26.646387 MAC: 00:e0:4c:68:02:81
10107 23:19:26.646487
10108 23:19:26.649365 Sending DHCP discover... done.
10109 23:19:26.649452
10110 23:19:26.652355 Waiting for reply... done.
10111 23:19:26.652442
10112 23:19:26.655844 Sending DHCP request... done.
10113 23:19:26.655920
10114 23:19:26.660756 Waiting for reply... done.
10115 23:19:26.660832
10116 23:19:26.660905 My ip is 192.168.201.14
10117 23:19:26.660965
10118 23:19:26.664244 The DHCP server ip is 192.168.201.1
10119 23:19:26.664324
10120 23:19:26.670440 TFTP server IP predefined by user: 192.168.201.1
10121 23:19:26.670518
10122 23:19:26.677057 Bootfile predefined by user: 13248414/tftp-deploy-dekbzbsg/kernel/image.itb
10123 23:19:26.677137
10124 23:19:26.680322 Sending tftp read request... done.
10125 23:19:26.680396
10126 23:19:26.684350 Waiting for the transfer...
10127 23:19:26.684420
10128 23:19:27.256720 00000000 ################################################################
10129 23:19:27.256868
10130 23:19:27.838461 00080000 ################################################################
10131 23:19:27.838595
10132 23:19:28.422656 00100000 ################################################################
10133 23:19:28.422805
10134 23:19:29.010132 00180000 ################################################################
10135 23:19:29.010279
10136 23:19:29.592610 00200000 ################################################################
10137 23:19:29.592759
10138 23:19:30.175066 00280000 ################################################################
10139 23:19:30.175203
10140 23:19:30.747264 00300000 ################################################################
10141 23:19:30.747402
10142 23:19:31.334114 00380000 ################################################################
10143 23:19:31.334259
10144 23:19:31.917501 00400000 ################################################################
10145 23:19:31.917652
10146 23:19:32.483573 00480000 ################################################################
10147 23:19:32.483747
10148 23:19:33.051788 00500000 ################################################################
10149 23:19:33.051935
10150 23:19:33.624144 00580000 ################################################################
10151 23:19:33.624276
10152 23:19:34.199799 00600000 ################################################################
10153 23:19:34.199934
10154 23:19:34.773587 00680000 ################################################################
10155 23:19:34.773731
10156 23:19:35.341933 00700000 ################################################################
10157 23:19:35.342078
10158 23:19:35.903647 00780000 ################################################################
10159 23:19:35.903797
10160 23:19:36.471454 00800000 ################################################################
10161 23:19:36.471611
10162 23:19:37.046742 00880000 ################################################################
10163 23:19:37.046885
10164 23:19:37.603448 00900000 ################################################################
10165 23:19:37.603592
10166 23:19:38.190411 00980000 ################################################################
10167 23:19:38.190556
10168 23:19:38.766206 00a00000 ################################################################
10169 23:19:38.766357
10170 23:19:39.345748 00a80000 ################################################################
10171 23:19:39.345884
10172 23:19:39.917484 00b00000 ################################################################
10173 23:19:39.917615
10174 23:19:40.496804 00b80000 ################################################################
10175 23:19:40.496938
10176 23:19:41.049370 00c00000 ################################################################
10177 23:19:41.049504
10178 23:19:41.631774 00c80000 ################################################################
10179 23:19:41.631913
10180 23:19:42.210446 00d00000 ################################################################
10181 23:19:42.210589
10182 23:19:42.776630 00d80000 ################################################################
10183 23:19:42.776813
10184 23:19:43.353510 00e00000 ################################################################
10185 23:19:43.353670
10186 23:19:43.923070 00e80000 ################################################################
10187 23:19:43.923238
10188 23:19:44.499580 00f00000 ################################################################
10189 23:19:44.499738
10190 23:19:45.079115 00f80000 ################################################################
10191 23:19:45.079256
10192 23:19:45.658850 01000000 ################################################################
10193 23:19:45.659027
10194 23:19:46.244751 01080000 ################################################################
10195 23:19:46.244921
10196 23:19:46.819242 01100000 ################################################################
10197 23:19:46.819377
10198 23:19:47.404654 01180000 ################################################################
10199 23:19:47.404792
10200 23:19:47.987187 01200000 ################################################################
10201 23:19:47.987333
10202 23:19:48.568262 01280000 ################################################################
10203 23:19:48.568491
10204 23:19:49.150726 01300000 ################################################################
10205 23:19:49.150857
10206 23:19:49.742616 01380000 ################################################################
10207 23:19:49.742761
10208 23:19:50.322591 01400000 ################################################################
10209 23:19:50.322739
10210 23:19:50.897354 01480000 ################################################################
10211 23:19:50.897560
10212 23:19:51.450349 01500000 ################################################################
10213 23:19:51.450502
10214 23:19:52.023335 01580000 ################################################################
10215 23:19:52.023476
10216 23:19:52.604227 01600000 ################################################################
10217 23:19:52.604374
10218 23:19:53.188238 01680000 ################################################################
10219 23:19:53.188389
10220 23:19:53.760848 01700000 ################################################################
10221 23:19:53.760986
10222 23:19:54.333339 01780000 ################################################################
10223 23:19:54.333483
10224 23:19:54.914877 01800000 ################################################################
10225 23:19:54.915021
10226 23:19:55.501261 01880000 ################################################################
10227 23:19:55.501416
10228 23:19:56.076142 01900000 ################################################################
10229 23:19:56.076285
10230 23:19:56.652093 01980000 ################################################################
10231 23:19:56.652226
10232 23:19:57.229565 01a00000 ################################################################
10233 23:19:57.229707
10234 23:19:57.806666 01a80000 ################################################################
10235 23:19:57.806813
10236 23:19:58.385787 01b00000 ################################################################
10237 23:19:58.385936
10238 23:19:58.958282 01b80000 ################################################################
10239 23:19:58.958430
10240 23:19:59.515472 01c00000 ################################################################
10241 23:19:59.515640
10242 23:20:00.087898 01c80000 ################################################################
10243 23:20:00.088031
10244 23:20:00.666797 01d00000 ################################################################
10245 23:20:00.666938
10246 23:20:01.241827 01d80000 ################################################################
10247 23:20:01.241996
10248 23:20:01.816706 01e00000 ################################################################
10249 23:20:01.816853
10250 23:20:02.391724 01e80000 ################################################################
10251 23:20:02.391866
10252 23:20:02.957059 01f00000 ################################################################
10253 23:20:02.957197
10254 23:20:03.526197 01f80000 ################################################################
10255 23:20:03.526332
10256 23:20:04.105990 02000000 ################################################################
10257 23:20:04.106132
10258 23:20:04.677555 02080000 ################################################################
10259 23:20:04.677704
10260 23:20:05.253483 02100000 ################################################################
10261 23:20:05.253630
10262 23:20:05.816604 02180000 ################################################################
10263 23:20:05.816743
10264 23:20:06.396783 02200000 ################################################################
10265 23:20:06.396925
10266 23:20:06.972447 02280000 ################################################################
10267 23:20:06.972587
10268 23:20:07.539789 02300000 ################################################################
10269 23:20:07.539934
10270 23:20:08.112359 02380000 ################################################################
10271 23:20:08.112505
10272 23:20:08.696044 02400000 ################################################################
10273 23:20:08.696196
10274 23:20:09.410831 02480000 ################################################################
10275 23:20:09.411554
10276 23:20:10.130395 02500000 ################################################################
10277 23:20:10.130970
10278 23:20:10.857987 02580000 ################################################################
10279 23:20:10.858502
10280 23:20:11.484592 02600000 ################################################################
10281 23:20:11.484871
10282 23:20:12.073645 02680000 ################################################################
10283 23:20:12.073782
10284 23:20:12.704105 02700000 ################################################################
10285 23:20:12.704696
10286 23:20:13.430821 02780000 ################################################################
10287 23:20:13.431392
10288 23:20:14.164353 02800000 ################################################################
10289 23:20:14.164926
10290 23:20:14.909047 02880000 ################################################################
10291 23:20:14.909593
10292 23:20:15.604208 02900000 ################################################################
10293 23:20:15.604427
10294 23:20:16.240851 02980000 ################################################################
10295 23:20:16.241342
10296 23:20:16.870613 02a00000 ################################################################
10297 23:20:16.870792
10298 23:20:17.560732 02a80000 ################################################################
10299 23:20:17.561372
10300 23:20:18.270631 02b00000 ################################################################
10301 23:20:18.271170
10302 23:20:18.996964 02b80000 ################################################################
10303 23:20:18.997515
10304 23:20:19.719934 02c00000 ################################################################
10305 23:20:19.720487
10306 23:20:20.452127 02c80000 ################################################################
10307 23:20:20.452675
10308 23:20:21.191043 02d00000 ################################################################
10309 23:20:21.191772
10310 23:20:21.910022 02d80000 ################################################################
10311 23:20:21.910566
10312 23:20:22.631788 02e00000 ################################################################
10313 23:20:22.632312
10314 23:20:23.340975 02e80000 ################################################################
10315 23:20:23.341495
10316 23:20:24.052375 02f00000 ################################################################
10317 23:20:24.053052
10318 23:20:24.781304 02f80000 ################################################################
10319 23:20:24.781823
10320 23:20:25.503808 03000000 ################################################################
10321 23:20:25.504395
10322 23:20:26.226907 03080000 ################################################################
10323 23:20:26.227456
10324 23:20:26.970132 03100000 ################################################################
10325 23:20:26.970708
10326 23:20:27.677802 03180000 ################################################################
10327 23:20:27.678322
10328 23:20:28.397739 03200000 ################################################################
10329 23:20:28.398272
10330 23:20:29.114535 03280000 ################################################################
10331 23:20:29.115073
10332 23:20:29.846886 03300000 ################################################################
10333 23:20:29.847479
10334 23:20:30.558562 03380000 ################################################################
10335 23:20:30.559260
10336 23:20:31.227062 03400000 ################################################################
10337 23:20:31.227447
10338 23:20:31.903090 03480000 ################################################################
10339 23:20:31.903583
10340 23:20:32.601180 03500000 ################################################################
10341 23:20:32.601693
10342 23:20:33.310770 03580000 ################################################################
10343 23:20:33.311372
10344 23:20:34.001876 03600000 ################################################################
10345 23:20:34.002253
10346 23:20:34.628011 03680000 ################################################################
10347 23:20:34.628175
10348 23:20:35.324108 03700000 ################################################################
10349 23:20:35.324610
10350 23:20:36.050738 03780000 ################################################################
10351 23:20:36.051264
10352 23:20:36.756766 03800000 ################################################################
10353 23:20:36.757292
10354 23:20:37.478796 03880000 ################################################################
10355 23:20:37.479302
10356 23:20:38.208393 03900000 ################################################################
10357 23:20:38.208902
10358 23:20:38.933255 03980000 ################################################################
10359 23:20:38.933816
10360 23:20:39.654494 03a00000 ################################################################
10361 23:20:39.655020
10362 23:20:40.382881 03a80000 ################################################################
10363 23:20:40.383420
10364 23:20:41.111714 03b00000 ################################################################
10365 23:20:41.112299
10366 23:20:41.849759 03b80000 ################################################################
10367 23:20:41.850320
10368 23:20:42.567601 03c00000 ################################################################
10369 23:20:42.568208
10370 23:20:43.272745 03c80000 ################################################################
10371 23:20:43.273312
10372 23:20:44.004920 03d00000 ################################################################
10373 23:20:44.005509
10374 23:20:44.725698 03d80000 ################################################################
10375 23:20:44.726261
10376 23:20:44.900140 03e00000 ############### done.
10377 23:20:44.900705
10378 23:20:44.903580 The bootfile was 65134506 bytes long.
10379 23:20:44.904108
10380 23:20:44.906659 Sending tftp read request... done.
10381 23:20:44.907116
10382 23:20:44.911822 Waiting for the transfer...
10383 23:20:44.912285
10384 23:20:44.912648 00000000 # done.
10385 23:20:44.912996
10386 23:20:44.917800 Command line loaded dynamically from TFTP file: 13248414/tftp-deploy-dekbzbsg/kernel/cmdline
10387 23:20:44.921137
10388 23:20:44.934665 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10389 23:20:44.935208
10390 23:20:44.935541 Loading FIT.
10391 23:20:44.935905
10392 23:20:44.937459 Image ramdisk-1 has 52177970 bytes.
10393 23:20:44.937801
10394 23:20:44.940800 Image fdt-1 has 47230 bytes.
10395 23:20:44.941474
10396 23:20:44.944107 Image kernel-1 has 12907270 bytes.
10397 23:20:44.944522
10398 23:20:44.950801 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10399 23:20:44.951233
10400 23:20:44.970316 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10401 23:20:44.970867
10402 23:20:44.973915 Choosing best match conf-1 for compat google,spherion-rev2.
10403 23:20:44.979576
10404 23:20:44.982942 Connected to device vid:did:rid of 1ae0:0028:00
10405 23:20:44.990649
10406 23:20:44.993774 tpm_get_response: command 0x17b, return code 0x0
10407 23:20:44.994293
10408 23:20:44.996658 ec_init: CrosEC protocol v3 supported (256, 248)
10409 23:20:45.001559
10410 23:20:45.004932 tpm_cleanup: add release locality here.
10411 23:20:45.005358
10412 23:20:45.007939 Shutting down all USB controllers.
10413 23:20:45.008380
10414 23:20:45.008717 Removing current net device
10415 23:20:45.009033
10416 23:20:45.014075 Exiting depthcharge with code 4 at timestamp: 114058203
10417 23:20:45.014494
10418 23:20:45.017965 LZMA decompressing kernel-1 to 0x821a6718
10419 23:20:45.018484
10420 23:20:45.020867 LZMA decompressing kernel-1 to 0x40000000
10421 23:20:46.614260
10422 23:20:46.614821 jumping to kernel
10423 23:20:46.617127 end: 2.2.4 bootloader-commands (duration 00:01:26) [common]
10424 23:20:46.617674 start: 2.2.5 auto-login-action (timeout 00:02:59) [common]
10425 23:20:46.618169 Setting prompt string to ['Linux version [0-9]']
10426 23:20:46.618564 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10427 23:20:46.618960 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10428 23:20:46.696768
10429 23:20:46.699962 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10430 23:20:46.704348 start: 2.2.5.1 login-action (timeout 00:02:59) [common]
10431 23:20:46.704948 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10432 23:20:46.705353 Setting prompt string to []
10433 23:20:46.705786 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10434 23:20:46.706190 Using line separator: #'\n'#
10435 23:20:46.706530 No login prompt set.
10436 23:20:46.706876 Parsing kernel messages
10437 23:20:46.707186 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10438 23:20:46.707790 [login-action] Waiting for messages, (timeout 00:02:59)
10439 23:20:46.708158 Waiting using forced prompt support (timeout 00:01:29)
10440 23:20:46.723278 [ 0.000000] Linux version 6.1.83-cip18 (KernelCI@build-j154450-arm64-gcc-10-defconfig-arm64-chromebook-z5l88) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024
10441 23:20:46.726024 [ 0.000000] random: crng init done
10442 23:20:46.732738 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10443 23:20:46.736509 [ 0.000000] efi: UEFI not found.
10444 23:20:46.742482 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10445 23:20:46.752400 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10446 23:20:46.758929 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10447 23:20:46.769072 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10448 23:20:46.775104 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10449 23:20:46.781931 [ 0.000000] printk: bootconsole [mtk8250] enabled
10450 23:20:46.788547 [ 0.000000] NUMA: No NUMA configuration found
10451 23:20:46.795251 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10452 23:20:46.801917 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10453 23:20:46.802484 [ 0.000000] Zone ranges:
10454 23:20:46.808619 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10455 23:20:46.811625 [ 0.000000] DMA32 empty
10456 23:20:46.818190 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10457 23:20:46.821695 [ 0.000000] Movable zone start for each node
10458 23:20:46.824714 [ 0.000000] Early memory node ranges
10459 23:20:46.832107 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10460 23:20:46.838263 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10461 23:20:46.844525 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10462 23:20:46.851932 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10463 23:20:46.858270 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10464 23:20:46.863863 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10465 23:20:46.920870 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10466 23:20:46.928325 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10467 23:20:46.934203 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10468 23:20:46.937792 [ 0.000000] psci: probing for conduit method from DT.
10469 23:20:46.944218 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10470 23:20:46.947453 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10471 23:20:46.953943 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10472 23:20:46.957059 [ 0.000000] psci: SMC Calling Convention v1.2
10473 23:20:46.964157 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10474 23:20:46.967771 [ 0.000000] Detected VIPT I-cache on CPU0
10475 23:20:46.973579 [ 0.000000] CPU features: detected: GIC system register CPU interface
10476 23:20:46.980647 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10477 23:20:46.987416 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10478 23:20:46.993531 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10479 23:20:47.003593 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10480 23:20:47.010216 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10481 23:20:47.013258 [ 0.000000] alternatives: applying boot alternatives
10482 23:20:47.020286 [ 0.000000] Fallback order for Node 0: 0
10483 23:20:47.026682 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10484 23:20:47.029873 [ 0.000000] Policy zone: Normal
10485 23:20:47.043315 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10486 23:20:47.053378 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10487 23:20:47.065801 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10488 23:20:47.075774 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10489 23:20:47.082015 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10490 23:20:47.085427 <6>[ 0.000000] software IO TLB: area num 8.
10491 23:20:47.142207 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10492 23:20:47.291596 <6>[ 0.000000] Memory: 7913612K/8385536K available (18048K kernel code, 4118K rwdata, 22284K rodata, 8448K init, 616K bss, 439156K reserved, 32768K cma-reserved)
10493 23:20:47.298350 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10494 23:20:47.304733 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10495 23:20:47.308367 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10496 23:20:47.314825 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10497 23:20:47.321332 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10498 23:20:47.324346 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10499 23:20:47.333984 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10500 23:20:47.341047 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10501 23:20:47.347714 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10502 23:20:47.354376 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10503 23:20:47.357169 <6>[ 0.000000] GICv3: 608 SPIs implemented
10504 23:20:47.361094 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10505 23:20:47.367516 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10506 23:20:47.370987 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10507 23:20:47.377452 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10508 23:20:47.390230 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10509 23:20:47.403392 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10510 23:20:47.409748 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10511 23:20:47.418307 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10512 23:20:47.430864 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10513 23:20:47.437387 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10514 23:20:47.444321 <6>[ 0.009183] Console: colour dummy device 80x25
10515 23:20:47.454400 <6>[ 0.013939] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10516 23:20:47.460353 <6>[ 0.024381] pid_max: default: 32768 minimum: 301
10517 23:20:47.463650 <6>[ 0.029253] LSM: Security Framework initializing
10518 23:20:47.471114 <6>[ 0.034193] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10519 23:20:47.480109 <6>[ 0.042008] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10520 23:20:47.490195 <6>[ 0.051437] cblist_init_generic: Setting adjustable number of callback queues.
10521 23:20:47.496519 <6>[ 0.058882] cblist_init_generic: Setting shift to 3 and lim to 1.
10522 23:20:47.503076 <6>[ 0.065222] cblist_init_generic: Setting adjustable number of callback queues.
10523 23:20:47.509595 <6>[ 0.072649] cblist_init_generic: Setting shift to 3 and lim to 1.
10524 23:20:47.513311 <6>[ 0.079050] rcu: Hierarchical SRCU implementation.
10525 23:20:47.519155 <6>[ 0.084065] rcu: Max phase no-delay instances is 1000.
10526 23:20:47.526242 <6>[ 0.091086] EFI services will not be available.
10527 23:20:47.529410 <6>[ 0.096040] smp: Bringing up secondary CPUs ...
10528 23:20:47.538802 <6>[ 0.101119] Detected VIPT I-cache on CPU1
10529 23:20:47.545070 <6>[ 0.101192] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10530 23:20:47.552112 <6>[ 0.101224] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10531 23:20:47.555044 <6>[ 0.101535] Detected VIPT I-cache on CPU2
10532 23:20:47.564649 <6>[ 0.101580] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10533 23:20:47.571447 <6>[ 0.101598] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10534 23:20:47.575040 <6>[ 0.101850] Detected VIPT I-cache on CPU3
10535 23:20:47.580913 <6>[ 0.101898] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10536 23:20:47.587871 <6>[ 0.101913] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10537 23:20:47.594538 <6>[ 0.102214] CPU features: detected: Spectre-v4
10538 23:20:47.597470 <6>[ 0.102221] CPU features: detected: Spectre-BHB
10539 23:20:47.601282 <6>[ 0.102226] Detected PIPT I-cache on CPU4
10540 23:20:47.610999 <6>[ 0.102284] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10541 23:20:47.617291 <6>[ 0.102301] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10542 23:20:47.620496 <6>[ 0.102589] Detected PIPT I-cache on CPU5
10543 23:20:47.627879 <6>[ 0.102651] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10544 23:20:47.633564 <6>[ 0.102667] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10545 23:20:47.637149 <6>[ 0.102943] Detected PIPT I-cache on CPU6
10546 23:20:47.646858 <6>[ 0.103011] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10547 23:20:47.653685 <6>[ 0.103027] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10548 23:20:47.656832 <6>[ 0.103321] Detected PIPT I-cache on CPU7
10549 23:20:47.664047 <6>[ 0.103386] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10550 23:20:47.670005 <6>[ 0.103403] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10551 23:20:47.673465 <6>[ 0.103451] smp: Brought up 1 node, 8 CPUs
10552 23:20:47.680151 <6>[ 0.244785] SMP: Total of 8 processors activated.
10553 23:20:47.686551 <6>[ 0.249707] CPU features: detected: 32-bit EL0 Support
10554 23:20:47.693316 <6>[ 0.255070] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10555 23:20:47.699857 <6>[ 0.263870] CPU features: detected: Common not Private translations
10556 23:20:47.706758 <6>[ 0.270346] CPU features: detected: CRC32 instructions
10557 23:20:47.713321 <6>[ 0.275698] CPU features: detected: RCpc load-acquire (LDAPR)
10558 23:20:47.716103 <6>[ 0.281659] CPU features: detected: LSE atomic instructions
10559 23:20:47.722631 <6>[ 0.287440] CPU features: detected: Privileged Access Never
10560 23:20:47.729467 <6>[ 0.293220] CPU features: detected: RAS Extension Support
10561 23:20:47.736083 <6>[ 0.298864] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10562 23:20:47.739163 <6>[ 0.306127] CPU: All CPU(s) started at EL2
10563 23:20:47.745548 <6>[ 0.310443] alternatives: applying system-wide alternatives
10564 23:20:47.756194 <6>[ 0.321228] devtmpfs: initialized
10565 23:20:47.771517 <6>[ 0.330072] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10566 23:20:47.778707 <6>[ 0.340034] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10567 23:20:47.784826 <6>[ 0.348247] pinctrl core: initialized pinctrl subsystem
10568 23:20:47.788346 <6>[ 0.354917] DMI not present or invalid.
10569 23:20:47.795103 <6>[ 0.359325] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10570 23:20:47.804875 <6>[ 0.366206] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10571 23:20:47.811394 <6>[ 0.373801] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10572 23:20:47.821268 <6>[ 0.382031] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10573 23:20:47.824355 <6>[ 0.390273] audit: initializing netlink subsys (disabled)
10574 23:20:47.834919 <5>[ 0.395969] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10575 23:20:47.840974 <6>[ 0.396674] thermal_sys: Registered thermal governor 'step_wise'
10576 23:20:47.847639 <6>[ 0.403934] thermal_sys: Registered thermal governor 'power_allocator'
10577 23:20:47.851100 <6>[ 0.410187] cpuidle: using governor menu
10578 23:20:47.857776 <6>[ 0.421147] NET: Registered PF_QIPCRTR protocol family
10579 23:20:47.863994 <6>[ 0.426636] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10580 23:20:47.870522 <6>[ 0.433740] ASID allocator initialised with 32768 entries
10581 23:20:47.873903 <6>[ 0.440309] Serial: AMBA PL011 UART driver
10582 23:20:47.884376 <4>[ 0.449121] Trying to register duplicate clock ID: 134
10583 23:20:47.938401 <6>[ 0.506834] KASLR enabled
10584 23:20:47.952890 <6>[ 0.514610] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10585 23:20:47.959793 <6>[ 0.521625] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10586 23:20:47.966218 <6>[ 0.528114] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10587 23:20:47.972893 <6>[ 0.535119] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10588 23:20:47.979233 <6>[ 0.541602] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10589 23:20:47.985952 <6>[ 0.548603] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10590 23:20:47.992167 <6>[ 0.555087] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10591 23:20:47.999120 <6>[ 0.562087] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10592 23:20:48.002315 <6>[ 0.569613] ACPI: Interpreter disabled.
10593 23:20:48.011183 <6>[ 0.576090] iommu: Default domain type: Translated
10594 23:20:48.018201 <6>[ 0.581202] iommu: DMA domain TLB invalidation policy: strict mode
10595 23:20:48.020944 <5>[ 0.587858] SCSI subsystem initialized
10596 23:20:48.027527 <6>[ 0.592019] usbcore: registered new interface driver usbfs
10597 23:20:48.034249 <6>[ 0.597750] usbcore: registered new interface driver hub
10598 23:20:48.037690 <6>[ 0.603304] usbcore: registered new device driver usb
10599 23:20:48.044388 <6>[ 0.609408] pps_core: LinuxPPS API ver. 1 registered
10600 23:20:48.054260 <6>[ 0.614602] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10601 23:20:48.057939 <6>[ 0.623949] PTP clock support registered
10602 23:20:48.061423 <6>[ 0.628191] EDAC MC: Ver: 3.0.0
10603 23:20:48.068593 <6>[ 0.633355] FPGA manager framework
10604 23:20:48.075186 <6>[ 0.637036] Advanced Linux Sound Architecture Driver Initialized.
10605 23:20:48.078677 <6>[ 0.643815] vgaarb: loaded
10606 23:20:48.085131 <6>[ 0.646979] clocksource: Switched to clocksource arch_sys_counter
10607 23:20:48.088461 <5>[ 0.653413] VFS: Disk quotas dquot_6.6.0
10608 23:20:48.095066 <6>[ 0.657599] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10609 23:20:48.097817 <6>[ 0.664789] pnp: PnP ACPI: disabled
10610 23:20:48.106696 <6>[ 0.671379] NET: Registered PF_INET protocol family
10611 23:20:48.117093 <6>[ 0.676975] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10612 23:20:48.128108 <6>[ 0.689282] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10613 23:20:48.137587 <6>[ 0.698092] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10614 23:20:48.144464 <6>[ 0.706063] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10615 23:20:48.154122 <6>[ 0.714764] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10616 23:20:48.160144 <6>[ 0.724515] TCP: Hash tables configured (established 65536 bind 65536)
10617 23:20:48.166941 <6>[ 0.731376] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10618 23:20:48.176786 <6>[ 0.738575] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10619 23:20:48.183446 <6>[ 0.746271] NET: Registered PF_UNIX/PF_LOCAL protocol family
10620 23:20:48.190632 <6>[ 0.752418] RPC: Registered named UNIX socket transport module.
10621 23:20:48.193047 <6>[ 0.758571] RPC: Registered udp transport module.
10622 23:20:48.200627 <6>[ 0.763505] RPC: Registered tcp transport module.
10623 23:20:48.206978 <6>[ 0.768436] RPC: Registered tcp NFSv4.1 backchannel transport module.
10624 23:20:48.210447 <6>[ 0.775102] PCI: CLS 0 bytes, default 64
10625 23:20:48.213223 <6>[ 0.779445] Unpacking initramfs...
10626 23:20:48.237436 <6>[ 0.799091] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10627 23:20:48.247647 <6>[ 0.807760] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10628 23:20:48.251091 <6>[ 0.816613] kvm [1]: IPA Size Limit: 40 bits
10629 23:20:48.257852 <6>[ 0.821141] kvm [1]: GICv3: no GICV resource entry
10630 23:20:48.260370 <6>[ 0.826163] kvm [1]: disabling GICv2 emulation
10631 23:20:48.267134 <6>[ 0.830847] kvm [1]: GIC system register CPU interface enabled
10632 23:20:48.270601 <6>[ 0.837012] kvm [1]: vgic interrupt IRQ18
10633 23:20:48.276880 <6>[ 0.841370] kvm [1]: VHE mode initialized successfully
10634 23:20:48.283636 <5>[ 0.847883] Initialise system trusted keyrings
10635 23:20:48.289916 <6>[ 0.852735] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10636 23:20:48.297941 <6>[ 0.862763] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10637 23:20:48.304507 <5>[ 0.869147] NFS: Registering the id_resolver key type
10638 23:20:48.307783 <5>[ 0.874448] Key type id_resolver registered
10639 23:20:48.314001 <5>[ 0.878860] Key type id_legacy registered
10640 23:20:48.320844 <6>[ 0.883143] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10641 23:20:48.327536 <6>[ 0.890067] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10642 23:20:48.333632 <6>[ 0.897792] 9p: Installing v9fs 9p2000 file system support
10643 23:20:48.370097 <5>[ 0.934986] Key type asymmetric registered
10644 23:20:48.372944 <5>[ 0.939316] Asymmetric key parser 'x509' registered
10645 23:20:48.383102 <6>[ 0.944496] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10646 23:20:48.386602 <6>[ 0.952124] io scheduler mq-deadline registered
10647 23:20:48.390170 <6>[ 0.956893] io scheduler kyber registered
10648 23:20:48.409218 <6>[ 0.974085] EINJ: ACPI disabled.
10649 23:20:48.441297 <4>[ 0.999729] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10650 23:20:48.451517 <4>[ 1.010360] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10651 23:20:48.466147 <6>[ 1.030989] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10652 23:20:48.474377 <6>[ 1.039036] printk: console [ttyS0] disabled
10653 23:20:48.502008 <6>[ 1.063660] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10654 23:20:48.509035 <6>[ 1.073136] printk: console [ttyS0] enabled
10655 23:20:48.511750 <6>[ 1.073136] printk: console [ttyS0] enabled
10656 23:20:48.518751 <6>[ 1.082030] printk: bootconsole [mtk8250] disabled
10657 23:20:48.521611 <6>[ 1.082030] printk: bootconsole [mtk8250] disabled
10658 23:20:48.527955 <6>[ 1.093391] SuperH (H)SCI(F) driver initialized
10659 23:20:48.531446 <6>[ 1.098682] msm_serial: driver initialized
10660 23:20:48.546181 <6>[ 1.107678] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10661 23:20:48.556024 <6>[ 1.116225] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10662 23:20:48.561937 <6>[ 1.124767] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10663 23:20:48.572760 <6>[ 1.133396] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10664 23:20:48.581936 <6>[ 1.142102] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10665 23:20:48.588787 <6>[ 1.150822] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10666 23:20:48.599128 <6>[ 1.159362] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10667 23:20:48.605175 <6>[ 1.168165] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10668 23:20:48.614938 <6>[ 1.176708] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10669 23:20:48.626960 <6>[ 1.192422] loop: module loaded
10670 23:20:48.633536 <6>[ 1.198420] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10671 23:20:48.656780 <4>[ 1.221750] mtk-pmic-keys: Failed to locate of_node [id: -1]
10672 23:20:48.663643 <6>[ 1.228658] megasas: 07.719.03.00-rc1
10673 23:20:48.673174 <6>[ 1.238256] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10674 23:20:48.681832 <6>[ 1.246367] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10675 23:20:48.698054 <6>[ 1.262696] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10676 23:20:48.757798 <6>[ 1.316362] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10677 23:20:50.442632 <6>[ 3.007755] Freeing initrd memory: 50952K
10678 23:20:50.454651 <6>[ 3.019430] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10679 23:20:50.465120 <6>[ 3.030360] tun: Universal TUN/TAP device driver, 1.6
10680 23:20:50.468975 <6>[ 3.036437] thunder_xcv, ver 1.0
10681 23:20:50.471466 <6>[ 3.039946] thunder_bgx, ver 1.0
10682 23:20:50.475504 <6>[ 3.043440] nicpf, ver 1.0
10683 23:20:50.485550 <6>[ 3.047464] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10684 23:20:50.488625 <6>[ 3.054940] hns3: Copyright (c) 2017 Huawei Corporation.
10685 23:20:50.495507 <6>[ 3.060526] hclge is initializing
10686 23:20:50.498983 <6>[ 3.064107] e1000: Intel(R) PRO/1000 Network Driver
10687 23:20:50.505659 <6>[ 3.069236] e1000: Copyright (c) 1999-2006 Intel Corporation.
10688 23:20:50.508664 <6>[ 3.075249] e1000e: Intel(R) PRO/1000 Network Driver
10689 23:20:50.515237 <6>[ 3.080465] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10690 23:20:50.521529 <6>[ 3.086649] igb: Intel(R) Gigabit Ethernet Network Driver
10691 23:20:50.528301 <6>[ 3.092299] igb: Copyright (c) 2007-2014 Intel Corporation.
10692 23:20:50.535403 <6>[ 3.098138] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10693 23:20:50.541489 <6>[ 3.104656] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10694 23:20:50.545485 <6>[ 3.111125] sky2: driver version 1.30
10695 23:20:50.551326 <6>[ 3.116133] VFIO - User Level meta-driver version: 0.3
10696 23:20:50.559206 <6>[ 3.124424] usbcore: registered new interface driver usb-storage
10697 23:20:50.565526 <6>[ 3.130871] usbcore: registered new device driver onboard-usb-hub
10698 23:20:50.574974 <6>[ 3.140017] mt6397-rtc mt6359-rtc: registered as rtc0
10699 23:20:50.584970 <6>[ 3.145481] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-03T23:20:51 UTC (1712186451)
10700 23:20:50.588609 <6>[ 3.155056] i2c_dev: i2c /dev entries driver
10701 23:20:50.604758 <6>[ 3.166811] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10702 23:20:50.611602 <4>[ 3.175561] cpu cpu0: supply cpu not found, using dummy regulator
10703 23:20:50.618472 <4>[ 3.181983] cpu cpu1: supply cpu not found, using dummy regulator
10704 23:20:50.625652 <4>[ 3.188386] cpu cpu2: supply cpu not found, using dummy regulator
10705 23:20:50.631503 <4>[ 3.194805] cpu cpu3: supply cpu not found, using dummy regulator
10706 23:20:50.637571 <4>[ 3.201204] cpu cpu4: supply cpu not found, using dummy regulator
10707 23:20:50.644668 <4>[ 3.207603] cpu cpu5: supply cpu not found, using dummy regulator
10708 23:20:50.651172 <4>[ 3.214000] cpu cpu6: supply cpu not found, using dummy regulator
10709 23:20:50.657393 <4>[ 3.220394] cpu cpu7: supply cpu not found, using dummy regulator
10710 23:20:50.676864 <6>[ 3.242053] cpu cpu0: EM: created perf domain
10711 23:20:50.680540 <6>[ 3.247015] cpu cpu4: EM: created perf domain
10712 23:20:50.687613 <6>[ 3.252304] sdhci: Secure Digital Host Controller Interface driver
10713 23:20:50.693974 <6>[ 3.258737] sdhci: Copyright(c) Pierre Ossman
10714 23:20:50.700203 <6>[ 3.263687] Synopsys Designware Multimedia Card Interface Driver
10715 23:20:50.707152 <6>[ 3.270327] sdhci-pltfm: SDHCI platform and OF driver helper
10716 23:20:50.710229 <6>[ 3.270393] mmc0: CQHCI version 5.10
10717 23:20:50.717160 <6>[ 3.280423] ledtrig-cpu: registered to indicate activity on CPUs
10718 23:20:50.723237 <6>[ 3.287552] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10719 23:20:50.729648 <6>[ 3.294627] usbcore: registered new interface driver usbhid
10720 23:20:50.733008 <6>[ 3.300451] usbhid: USB HID core driver
10721 23:20:50.739799 <6>[ 3.304646] spi_master spi0: will run message pump with realtime priority
10722 23:20:50.783190 <6>[ 3.341968] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10723 23:20:50.802374 <6>[ 3.357688] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10724 23:20:50.810197 <6>[ 3.373755] cros-ec-spi spi0.0: Chrome EC device registered
10725 23:20:50.813507 <6>[ 3.379815] mmc0: Command Queue Engine enabled
10726 23:20:50.819296 <6>[ 3.384559] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10727 23:20:50.826593 <6>[ 3.392273] mmcblk0: mmc0:0001 DA4128 116 GiB
10728 23:20:50.837350 <6>[ 3.402167] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10729 23:20:50.844715 <6>[ 3.409772] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10730 23:20:50.853895 <6>[ 3.413591] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10731 23:20:50.857570 <6>[ 3.415693] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10732 23:20:50.864091 <6>[ 3.425585] NET: Registered PF_PACKET protocol family
10733 23:20:50.870961 <6>[ 3.430175] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10734 23:20:50.874397 <6>[ 3.434925] 9pnet: Installing 9P2000 support
10735 23:20:50.882145 <5>[ 3.445925] Key type dns_resolver registered
10736 23:20:50.885181 <6>[ 3.450912] registered taskstats version 1
10737 23:20:50.890811 <5>[ 3.455296] Loading compiled-in X.509 certificates
10738 23:20:50.919830 <4>[ 3.478331] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10739 23:20:50.929172 <4>[ 3.489095] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10740 23:20:50.936679 <3>[ 3.499634] debugfs: File 'uA_load' in directory '/' already present!
10741 23:20:50.942961 <3>[ 3.506405] debugfs: File 'min_uV' in directory '/' already present!
10742 23:20:50.949390 <3>[ 3.513027] debugfs: File 'max_uV' in directory '/' already present!
10743 23:20:50.955854 <3>[ 3.519640] debugfs: File 'constraint_flags' in directory '/' already present!
10744 23:20:50.967578 <3>[ 3.529509] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10745 23:20:50.977230 <6>[ 3.542438] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10746 23:20:50.983464 <6>[ 3.549208] xhci-mtk 11200000.usb: xHCI Host Controller
10747 23:20:50.993595 <6>[ 3.554699] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10748 23:20:51.000164 <6>[ 3.562539] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10749 23:20:51.007488 <6>[ 3.571954] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10750 23:20:51.013170 <6>[ 3.578017] xhci-mtk 11200000.usb: xHCI Host Controller
10751 23:20:51.020557 <6>[ 3.583492] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10752 23:20:51.029755 <6>[ 3.591139] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10753 23:20:51.032838 <6>[ 3.598784] hub 1-0:1.0: USB hub found
10754 23:20:51.035960 <6>[ 3.602795] hub 1-0:1.0: 1 port detected
10755 23:20:51.046277 <6>[ 3.607070] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10756 23:20:51.049267 <6>[ 3.615621] hub 2-0:1.0: USB hub found
10757 23:20:51.052876 <6>[ 3.619636] hub 2-0:1.0: 1 port detected
10758 23:20:51.061171 <6>[ 3.626825] mtk-msdc 11f70000.mmc: Got CD GPIO
10759 23:20:51.073006 <6>[ 3.634533] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10760 23:20:51.079107 <6>[ 3.642564] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10761 23:20:51.089179 <4>[ 3.650471] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10762 23:20:51.098896 <6>[ 3.659997] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10763 23:20:51.105706 <6>[ 3.668074] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10764 23:20:51.115556 <6>[ 3.676107] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10765 23:20:51.122463 <6>[ 3.684038] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10766 23:20:51.128691 <6>[ 3.691855] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10767 23:20:51.138572 <6>[ 3.699673] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10768 23:20:51.148608 <6>[ 3.709928] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10769 23:20:51.155867 <6>[ 3.718316] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10770 23:20:51.164530 <6>[ 3.726661] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10771 23:20:51.171814 <6>[ 3.735007] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10772 23:20:51.181111 <6>[ 3.743345] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10773 23:20:51.191408 <6>[ 3.751685] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10774 23:20:51.197921 <6>[ 3.760022] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10775 23:20:51.208216 <6>[ 3.768360] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10776 23:20:51.214179 <6>[ 3.776698] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10777 23:20:51.224280 <6>[ 3.785034] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10778 23:20:51.230658 <6>[ 3.793372] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10779 23:20:51.240590 <6>[ 3.801710] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10780 23:20:51.247293 <6>[ 3.810047] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10781 23:20:51.257738 <6>[ 3.818384] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10782 23:20:51.264140 <6>[ 3.826721] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10783 23:20:51.270119 <6>[ 3.835496] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10784 23:20:51.277683 <6>[ 3.842748] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10785 23:20:51.284513 <6>[ 3.849626] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10786 23:20:51.294189 <6>[ 3.856478] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10787 23:20:51.300766 <6>[ 3.863483] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10788 23:20:51.310550 <6>[ 3.870338] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10789 23:20:51.317282 <6>[ 3.879474] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10790 23:20:51.327460 <6>[ 3.888610] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10791 23:20:51.337204 <6>[ 3.897904] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10792 23:20:51.347594 <6>[ 3.907371] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10793 23:20:51.356870 <6>[ 3.916839] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10794 23:20:51.364205 <6>[ 3.925958] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10795 23:20:51.373185 <6>[ 3.935427] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10796 23:20:51.383335 <6>[ 3.944546] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10797 23:20:51.393063 <6>[ 3.953841] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10798 23:20:51.403457 <6>[ 3.964002] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10799 23:20:51.413642 <6>[ 3.975924] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10800 23:20:51.465326 <6>[ 4.027258] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10801 23:20:51.620059 <6>[ 4.185366] hub 1-1:1.0: USB hub found
10802 23:20:51.623297 <6>[ 4.189893] hub 1-1:1.0: 4 ports detected
10803 23:20:51.632885 <6>[ 4.198384] hub 1-1:1.0: USB hub found
10804 23:20:51.636654 <6>[ 4.202716] hub 1-1:1.0: 4 ports detected
10805 23:20:51.745813 <6>[ 4.307631] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10806 23:20:51.771241 <6>[ 4.336713] hub 2-1:1.0: USB hub found
10807 23:20:51.774358 <6>[ 4.341212] hub 2-1:1.0: 3 ports detected
10808 23:20:51.784183 <6>[ 4.349239] hub 2-1:1.0: USB hub found
10809 23:20:51.787065 <6>[ 4.353707] hub 2-1:1.0: 3 ports detected
10810 23:20:51.961196 <6>[ 4.523297] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10811 23:20:52.092987 <6>[ 4.658518] hub 1-1.4:1.0: USB hub found
10812 23:20:52.096582 <6>[ 4.663088] hub 1-1.4:1.0: 2 ports detected
10813 23:20:52.106183 <6>[ 4.671345] hub 1-1.4:1.0: USB hub found
10814 23:20:52.109353 <6>[ 4.675915] hub 1-1.4:1.0: 2 ports detected
10815 23:20:52.177146 <6>[ 4.739385] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10816 23:20:52.405021 <6>[ 4.967375] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10817 23:20:52.596796 <6>[ 5.159306] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10818 23:21:03.702670 <6>[ 16.272293] ALSA device list:
10819 23:21:03.708641 <6>[ 16.275582] No soundcards found.
10820 23:21:03.716616 <6>[ 16.283601] Freeing unused kernel memory: 8448K
10821 23:21:03.719765 <6>[ 16.289097] Run /init as init process
10822 23:21:03.751630 <6>[ 16.318922] NET: Registered PF_INET6 protocol family
10823 23:21:03.758434 <6>[ 16.325382] Segment Routing with IPv6
10824 23:21:03.761781 <6>[ 16.329359] In-situ OAM (IOAM) with IPv6
10825 23:21:03.803525 <30>[ 16.344255] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10826 23:21:03.809900 <30>[ 16.377415] systemd[1]: Detected architecture arm64.
10827 23:21:03.810023
10828 23:21:03.817585 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10829 23:21:03.817674
10830 23:21:03.817761
10831 23:21:03.832038 <30>[ 16.399328] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10832 23:21:03.975928 <30>[ 16.539571] systemd[1]: Queued start job for default target graphical.target.
10833 23:21:04.012901 <30>[ 16.577174] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10834 23:21:04.020050 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10835 23:21:04.020227
10836 23:21:04.040478 <30>[ 16.604325] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10837 23:21:04.050635 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10838 23:21:04.050776
10839 23:21:04.072924 <30>[ 16.636765] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10840 23:21:04.082937 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10841 23:21:04.083117
10842 23:21:04.101603 <30>[ 16.665176] systemd[1]: Created slice user.slice - User and Session Slice.
10843 23:21:04.108160 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10844 23:21:04.108307
10845 23:21:04.131648 <30>[ 16.692150] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10846 23:21:04.141492 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10847 23:21:04.141640
10848 23:21:04.159212 <30>[ 16.719517] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10849 23:21:04.166020 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10850 23:21:04.166167
10851 23:21:04.194000 <30>[ 16.747827] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10852 23:21:04.204080 <30>[ 16.767781] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10853 23:21:04.210555 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10854 23:21:04.210691
10855 23:21:04.228038 <30>[ 16.791676] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10856 23:21:04.237774 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10857 23:21:04.237905
10858 23:21:04.255859 <30>[ 16.819810] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10859 23:21:04.265552 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10860 23:21:04.265684
10861 23:21:04.281124 <30>[ 16.847779] systemd[1]: Reached target paths.target - Path Units.
10862 23:21:04.290351 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10863 23:21:04.290482
10864 23:21:04.307633 <30>[ 16.871747] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10865 23:21:04.314706 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10866 23:21:04.314905
10867 23:21:04.328481 <30>[ 16.895308] systemd[1]: Reached target slices.target - Slice Units.
10868 23:21:04.338304 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10869 23:21:04.338462
10870 23:21:04.352579 <30>[ 16.919774] systemd[1]: Reached target swap.target - Swaps.
10871 23:21:04.359089 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10872 23:21:04.359271
10873 23:21:04.380290 <30>[ 16.943783] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10874 23:21:04.390037 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10875 23:21:04.390239
10876 23:21:04.408318 <30>[ 16.972261] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10877 23:21:04.417889 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10878 23:21:04.418085
10879 23:21:04.438210 <30>[ 17.001560] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10880 23:21:04.447352 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10881 23:21:04.447577
10882 23:21:04.464939 <30>[ 17.028087] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10883 23:21:04.474207 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10884 23:21:04.474382
10885 23:21:04.495652 <30>[ 17.059992] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10886 23:21:04.502477 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10887 23:21:04.502641
10888 23:21:04.520132 <30>[ 17.084011] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10889 23:21:04.530059 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10890 23:21:04.530232
10891 23:21:04.548699 <30>[ 17.112695] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10892 23:21:04.558592 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10893 23:21:04.558765
10894 23:21:04.576154 <30>[ 17.140391] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10895 23:21:04.586182 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10896 23:21:04.586334
10897 23:21:04.631829 <30>[ 17.195615] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10898 23:21:04.638306 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10899 23:21:04.638516
10900 23:21:04.659442 <30>[ 17.223578] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10901 23:21:04.666410 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10902 23:21:04.666604
10903 23:21:04.723852 <30>[ 17.287406] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10904 23:21:04.729878 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10905 23:21:04.730085
10906 23:21:04.754034 <30>[ 17.311780] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10907 23:21:04.767636 <30>[ 17.331871] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10908 23:21:04.777560 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10909 23:21:04.777755
10910 23:21:04.800544 <30>[ 17.364359] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10911 23:21:04.807221 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10912 23:21:04.807388
10913 23:21:04.832191 <30>[ 17.396114] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10914 23:21:04.848357 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod..<6>[ 17.410221] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10915 23:21:04.848515 .
10916 23:21:04.848585
10917 23:21:04.896092 <30>[ 17.459582] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10918 23:21:04.901984 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10919 23:21:04.902137
10920 23:21:04.923455 <30>[ 17.487449] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10921 23:21:04.929908 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10922 23:21:04.933286
10923 23:21:04.987911 <30>[ 17.551885] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10924 23:21:04.994553 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10925 23:21:04.994738
10926 23:21:05.024058 <30>[ 17.588118] systemd[1]: Starting systemd-journald.service - Journal Service...
10927 23:21:05.031306 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10928 23:21:05.031458
10929 23:21:05.050289 <30>[ 17.614443] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10930 23:21:05.056556 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10931 23:21:05.056707
10932 23:21:05.081502 <30>[ 17.642442] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10933 23:21:05.088617 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10934 23:21:05.088768
10935 23:21:05.111643 <30>[ 17.676041] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10936 23:21:05.121925 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10937 23:21:05.122094
10938 23:21:05.141296 <30>[ 17.705650] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10939 23:21:05.151639 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10940 23:21:05.151835
10941 23:21:05.176381 <30>[ 17.740617] systemd[1]: Started systemd-journald.service - Journal Service.
10942 23:21:05.183503 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10943 23:21:05.183736
10944 23:21:05.205207 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10945 23:21:05.205398
10946 23:21:05.228491 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10947 23:21:05.228685
10948 23:21:05.252307 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10949 23:21:05.252496
10950 23:21:05.276124 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10951 23:21:05.276329
10952 23:21:05.302457 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10953 23:21:05.302639
10954 23:21:05.322915 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10955 23:21:05.323134
10956 23:21:05.342724 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10957 23:21:05.342913
10958 23:21:05.362989 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10959 23:21:05.363140
10960 23:21:05.387635 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10961 23:21:05.387796
10962 23:21:05.409937 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10963 23:21:05.410093
10964 23:21:05.432518 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10965 23:21:05.432683
10966 23:21:05.457780 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10967 23:21:05.457926
10968 23:21:05.472345 See 'systemctl status systemd-remount-fs.service' for details.
10969 23:21:05.472540
10970 23:21:05.492866 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10971 23:21:05.493028
10972 23:21:05.513578 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10973 23:21:05.513776
10974 23:21:05.551684 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10975 23:21:05.551864
10976 23:21:05.569097 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10977 23:21:05.569262
10978 23:21:05.583976 <46>[ 18.148260] systemd-journald[181]: Received client request to flush runtime journal.
10979 23:21:05.596197 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10980 23:21:05.596384
10981 23:21:05.618335 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10982 23:21:05.618526
10983 23:21:05.642947 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10984 23:21:05.643135
10985 23:21:05.674541 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10986 23:21:05.674732
10987 23:21:05.697188 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10988 23:21:05.697384
10989 23:21:05.716447 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10990 23:21:05.716640
10991 23:21:05.737035 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10992 23:21:05.737227
10993 23:21:05.756350 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10994 23:21:05.756538
10995 23:21:05.820019 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10996 23:21:05.820213
10997 23:21:05.843828 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10998 23:21:05.844015
10999 23:21:05.867978 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11000 23:21:05.868176
11001 23:21:05.882876 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11002 23:21:05.883069
11003 23:21:05.948033 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11004 23:21:05.948228
11005 23:21:05.974044 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11006 23:21:05.974243
11007 23:21:05.998711 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11008 23:21:05.998907
11009 23:21:06.056443 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11010 23:21:06.056634
11011 23:21:06.086218 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11012 23:21:06.086409
11013 23:21:06.111494 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11014 23:21:06.111717
11015 23:21:06.137470 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11016 23:21:06.137661
11017 23:21:06.177675 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11018 23:21:06.177873
11019 23:21:06.208933 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11020 23:21:06.209114
11021 23:21:06.310811 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11022 23:21:06.311020
11023 23:21:06.328614 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11024 23:21:06.328833
11025 23:21:06.348434 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11026 23:21:06.348671
11027 23:21:06.370284 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11028 23:21:06.370432
11029 23:21:06.383343 <6>[ 18.947647] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11030 23:21:06.390038 <3>[ 18.953164] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11031 23:21:06.399688 <6>[ 18.955646] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11032 23:21:06.406620 <3>[ 18.963753] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11033 23:21:06.416283 <6>[ 18.972282] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11034 23:21:06.426191 <3>[ 18.980309] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11035 23:21:06.432615 <3>[ 18.989577] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11036 23:21:06.442564 [[0;32m OK [<3>[ 19.005867] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11037 23:21:06.452505 0m] Reached targ<3>[ 19.015295] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11038 23:21:06.461953 et [0;1;39mtime<3>[ 19.025329] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11039 23:21:06.472258 rs.target[0m - <3>[ 19.035237] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11040 23:21:06.472408 Timer Units.
11041 23:21:06.472479
11042 23:21:06.475494 <6>[ 19.045075] mc: Linux media interface: v0.10
11043 23:21:06.485901 <4>[ 19.045878] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11044 23:21:06.492074 <6>[ 19.047378] usbcore: registered new device driver r8152-cfgselector
11045 23:21:06.498929 <3>[ 19.048671] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11046 23:21:06.508611 <3>[ 19.049961] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11047 23:21:06.515129 <4>[ 19.061644] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11048 23:21:06.521667 <3>[ 19.063594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11049 23:21:06.531534 <3>[ 19.063605] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11050 23:21:06.538715 <3>[ 19.068928] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11051 23:21:06.548080 <6>[ 19.072109] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11052 23:21:06.554392 <3>[ 19.079899] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11053 23:21:06.564336 <3>[ 19.079907] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11054 23:21:06.571017 <3>[ 19.079917] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11055 23:21:06.577688 <3>[ 19.079923] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11056 23:21:06.588388 <3>[ 19.088746] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11057 23:21:06.595066 <4>[ 19.117269] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11058 23:21:06.601730 <4>[ 19.117269] Fallback method does not support PEC.
11059 23:21:06.608695 <6>[ 19.120015] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11060 23:21:06.614696 <6>[ 19.136170] videodev: Linux video capture interface: v2.00
11061 23:21:06.625067 <6>[ 19.139475] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11062 23:21:06.631404 <6>[ 19.139707] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11063 23:21:06.637953 <6>[ 19.143548] pci_bus 0000:00: root bus resource [bus 00-ff]
11064 23:21:06.648164 <3>[ 19.159741] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11065 23:21:06.654788 <6>[ 19.173344] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11066 23:21:06.665132 <6>[ 19.173348] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11067 23:21:06.670996 <6>[ 19.173378] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11068 23:21:06.681295 <6>[ 19.179235] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11069 23:21:06.687791 <6>[ 19.186836] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11070 23:21:06.694137 <6>[ 19.196043] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11071 23:21:06.697772 <6>[ 19.196114] pci 0000:00:00.0: supports D1 D2
11072 23:21:06.708446 <6>[ 19.208840] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11073 23:21:06.715606 <6>[ 19.210841] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11074 23:21:06.718763 <6>[ 19.213711] remoteproc remoteproc0: scp is available
11075 23:21:06.725707 <6>[ 19.214014] remoteproc remoteproc0: powering up scp
11076 23:21:06.732615 <6>[ 19.214026] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11077 23:21:06.738979 <6>[ 19.214102] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11078 23:21:06.742200 <6>[ 19.228955] Bluetooth: Core ver 2.22
11079 23:21:06.749190 <6>[ 19.238143] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11080 23:21:06.759186 <4>[ 19.242515] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11081 23:21:06.769450 <4>[ 19.242526] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11082 23:21:06.773397 <6>[ 19.242999] NET: Registered PF_BLUETOOTH protocol family
11083 23:21:06.779057 <6>[ 19.252345] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11084 23:21:06.785586 <6>[ 19.253094] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11085 23:21:06.799425 <6>[ 19.254137] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11086 23:21:06.806240 <6>[ 19.254231] usbcore: registered new interface driver uvcvideo
11087 23:21:06.813852 <6>[ 19.259531] Bluetooth: HCI device and connection manager initialized
11088 23:21:06.819866 <6>[ 19.267032] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11089 23:21:06.823184 <6>[ 19.271543] Bluetooth: HCI socket layer initialized
11090 23:21:06.833390 <6>[ 19.279883] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11091 23:21:06.839692 <6>[ 19.279898] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11092 23:21:06.843412 <6>[ 19.280018] pci 0000:01:00.0: supports D1 D2
11093 23:21:06.850036 <6>[ 19.286769] Bluetooth: L2CAP socket layer initialized
11094 23:21:06.853569 <6>[ 19.287173] r8152 2-1.3:1.0 eth0: v1.12.13
11095 23:21:06.859918 <6>[ 19.287275] usbcore: registered new interface driver r8152
11096 23:21:06.867181 <3>[ 19.290070] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11097 23:21:06.877092 <3>[ 19.290863] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11098 23:21:06.886683 <3>[ 19.291712] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11099 23:21:06.893552 <6>[ 19.291978] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11100 23:21:06.900327 <3>[ 19.294279] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11101 23:21:06.906717 <6>[ 19.297117] Bluetooth: SCO socket layer initialized
11102 23:21:06.910402 <6>[ 19.298163] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11103 23:21:06.917240 <6>[ 19.311523] usbcore: registered new interface driver cdc_ether
11104 23:21:06.924320 <6>[ 19.319198] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11105 23:21:06.934391 <3>[ 19.330745] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11106 23:21:06.941438 <6>[ 19.332351] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11107 23:21:06.947630 <6>[ 19.332811] usbcore: registered new interface driver r8153_ecm
11108 23:21:06.954649 <6>[ 19.344172] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11109 23:21:06.961317 <6>[ 19.344178] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11110 23:21:06.967702 <6>[ 19.344187] remoteproc remoteproc0: remote processor scp is now up
11111 23:21:06.978344 <6>[ 19.345981] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11112 23:21:06.985055 <6>[ 19.345997] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11113 23:21:06.991303 <6>[ 19.360117] usbcore: registered new interface driver btusb
11114 23:21:07.001146 <4>[ 19.360929] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11115 23:21:07.007709 <3>[ 19.360945] Bluetooth: hci0: Failed to load firmware file (-2)
11116 23:21:07.014942 <3>[ 19.360951] Bluetooth: hci0: Failed to set up firmware (-2)
11117 23:21:07.024241 <4>[ 19.360956] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11118 23:21:07.031116 <6>[ 19.361115] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11119 23:21:07.040840 <6>[ 19.362575] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11120 23:21:07.048215 <3>[ 19.367558] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11121 23:21:07.054057 <6>[ 19.369372] r8152 2-1.3:1.0 enx00e04c680281: renamed from eth0
11122 23:21:07.064484 <6>[ 19.371711] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11123 23:21:07.071046 <3>[ 19.389190] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11124 23:21:07.080979 <6>[ 19.391778] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11125 23:21:07.087569 <3>[ 19.418200] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11126 23:21:07.094027 <6>[ 19.421668] pci 0000:00:00.0: PCI bridge to [bus 01]
11127 23:21:07.100255 <6>[ 19.421673] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11128 23:21:07.110772 <3>[ 19.447820] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11129 23:21:07.118083 <6>[ 19.449435] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11130 23:21:07.123510 [[0;32m OK [<6>[ 19.690260] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11131 23:21:07.133452 0m] Listening on<6>[ 19.698024] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11132 23:21:07.137242 [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11133 23:21:07.137372
11134 23:21:07.153188 <5>[ 19.717403] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11135 23:21:07.159617 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11136 23:21:07.159782
11137 23:21:07.178370 <5>[ 19.742663] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11138 23:21:07.184836 <5>[ 19.750003] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11139 23:21:07.194554 <4>[ 19.758780] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11140 23:21:07.202049 <6>[ 19.769953] cfg80211: failed to load regulatory.db
11141 23:21:07.220768 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11142 23:21:07.220954
11143 23:21:07.244009 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - B<6>[ 19.809034] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11144 23:21:07.246743 asic System.
11145 23:21:07.246888
11146 23:21:07.253445 <6>[ 19.817779] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11147 23:21:07.270831 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11148 23:21:07.270979
11149 23:21:07.277242 <6>[ 19.843048] mt7921e 0000:01:00.0: ASIC revision: 79610010
11150 23:21:07.295020 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11151 23:21:07.295172
11152 23:21:07.311876 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11153 23:21:07.312026
11154 23:21:07.331631 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11155 23:21:07.331821
11156 23:21:07.384552 <6>[ 19.948737] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11157 23:21:07.387733 <6>[ 19.948737]
11158 23:21:07.412617 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11159 23:21:07.412788
11160 23:21:07.435269 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11161 23:21:07.435426
11162 23:21:07.452205 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11163 23:21:07.452387
11164 23:21:07.468674 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11165 23:21:07.471937
11166 23:21:07.488345 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11167 23:21:07.488500
11168 23:21:07.561075 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11169 23:21:07.561231
11170 23:21:07.585927 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11171 23:21:07.586085
11172 23:21:07.608490 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11173 23:21:07.608760
11174 23:21:07.630219 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11175 23:21:07.630374
11176 23:21:07.651220 <6>[ 20.215758] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11177 23:21:07.693642 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11178 23:21:07.693795
11179 23:21:07.714660 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11180 23:21:07.714816
11181 23:21:07.731557 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11182 23:21:07.731754
11183 23:21:07.751364 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11184 23:21:07.751563
11185 23:21:07.772136 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11186 23:21:07.772332
11187 23:21:07.833896 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11188 23:21:07.834056
11189 23:21:07.857877 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11190 23:21:07.858044
11191 23:21:07.879923 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11192 23:21:07.880112
11193 23:21:07.920740 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11194 23:21:07.920894
11195 23:21:07.961065
11196 23:21:07.961218
11197 23:21:07.964101 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11198 23:21:07.964247
11199 23:21:07.967551 debian-bookworm-arm64 login: root (automatic login)
11200 23:21:07.967721
11201 23:21:07.967798
11202 23:21:07.982613 Linux debian-bookworm-arm64 6.1.83-cip18 #1 SMP PREEMPT Wed Apr 3 23:03:14 UTC 2024 aarch64
11203 23:21:07.982762
11204 23:21:07.989014 The programs included with the Debian GNU/Linux system are free software;
11205 23:21:07.995181 the exact distribution terms for each program are described in the
11206 23:21:07.998982 individual files in /usr/share/doc/*/copyright.
11207 23:21:07.999152
11208 23:21:08.005823 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11209 23:21:08.008359 permitted by applicable law.
11210 23:21:08.008825 Matched prompt #10: / #
11212 23:21:08.009041 Setting prompt string to ['/ #']
11213 23:21:08.009138 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11215 23:21:08.009334 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11216 23:21:08.009424 start: 2.2.6 expect-shell-connection (timeout 00:02:37) [common]
11217 23:21:08.009499 Setting prompt string to ['/ #']
11218 23:21:08.009561 Forcing a shell prompt, looking for ['/ #']
11220 23:21:08.059746 / #
11221 23:21:08.059931 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11222 23:21:08.060022 Waiting using forced prompt support (timeout 00:02:30)
11223 23:21:08.065226
11224 23:21:08.065608 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11225 23:21:08.065733 start: 2.2.7 export-device-env (timeout 00:02:37) [common]
11226 23:21:08.065880 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11227 23:21:08.066019 end: 2.2 depthcharge-retry (duration 00:02:23) [common]
11228 23:21:08.066153 end: 2 depthcharge-action (duration 00:02:23) [common]
11229 23:21:08.066306 start: 3 lava-test-retry (timeout 00:05:00) [common]
11230 23:21:08.066448 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11231 23:21:08.066569 Using namespace: common
11233 23:21:08.166991 / # #
11234 23:21:08.167225 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11235 23:21:08.172312 #
11236 23:21:08.172656 Using /lava-13248414
11238 23:21:08.273003 / # export SHELL=/bin/sh
11239 23:21:08.278774 export SHELL=/bin/sh
11241 23:21:08.379387 / # . /lava-13248414/environment
11242 23:21:08.379668 <6>[ 20.898427] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c680281: link becomes ready
11243 23:21:08.379861 . /lava-<6>[ 20.906401] r8152 2-1.3:1.0 enx00e04c680281: carrier on
11244 23:21:08.384769 13248414/environment
11246 23:21:08.485487 / # /lava-13248414/bin/lava-test-runner /lava-13248414/0
11247 23:21:08.485689 Test shell timeout: 10s (minimum of the action and connection timeout)
11248 23:21:08.490379 /lava-13248414/bin/lava-test-runner /lava-13248414/0
11249 23:21:08.511425 <6>[ 21.079519] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11250 23:21:08.515191 + export TESTRUN_ID=0_cros-ec
11251 23:21:08.521453 +<8>[ 21.086907] <LAVA_SIGNAL_STARTRUN 0_cros-ec 13248414_1.5.2.3.1>
11252 23:21:08.521869 Received signal: <STARTRUN> 0_cros-ec 13248414_1.5.2.3.1
11253 23:21:08.522001 Starting test lava.0_cros-ec (13248414_1.5.2.3.1)
11254 23:21:08.522142 Skipping test definition patterns.
11255 23:21:08.524613 cd /lava-13248414/0/tests/0_cros-ec
11256 23:21:08.524754 + cat uuid
11257 23:21:08.527935 + UUID=13248414_1.5.2.3.1
11258 23:21:08.528099 + set +x
11259 23:21:08.531278 + python3 -m cros.runners.lava_runner -v
11260 23:21:08.992400 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_abi)
11261 23:21:08.999090 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11262 23:21:08.999284
11263 23:21:09.006184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11264 23:21:09.006570 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11266 23:21:09.019470 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_data_is_valid)
11267 23:21:09.026028 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11268 23:21:09.026222
11269 23:21:09.032293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11270 23:21:09.032666 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11272 23:21:09.042153 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro.test_cros_ec_gyro_iio_abi)
11273 23:21:09.048494 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11274 23:21:09.048687
11275 23:21:09.055583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11276 23:21:09.056000 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11278 23:21:09.061804 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_abi)
11279 23:21:09.068196 Checks the standard ABI for the main Embedded Controller. ... ok
11280 23:21:09.068397
11281 23:21:09.071889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11282 23:21:09.072232 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11284 23:21:09.078601 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_chardev)
11285 23:21:09.084605 Checks the main Embedded controller character device. ... ok
11286 23:21:09.084753
11287 23:21:09.091535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11288 23:21:09.091870 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11290 23:21:09.098230 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_hello)
11291 23:21:09.104322 Checks basic comunication with the main Embedded controller. ... ok
11292 23:21:09.104471
11293 23:21:09.110763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11294 23:21:09.111080 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11296 23:21:09.118068 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_abi)
11297 23:21:09.124509 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11298 23:21:09.124655
11299 23:21:09.130972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11300 23:21:09.131292 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11302 23:21:09.137525 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_hello)
11303 23:21:09.143874 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11304 23:21:09.144017
11305 23:21:09.150733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11306 23:21:09.151059 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11308 23:21:09.156985 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_reboot)
11309 23:21:09.163646 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11310 23:21:09.163805
11311 23:21:09.170176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11312 23:21:09.170512 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11314 23:21:09.177012 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_abi)
11315 23:21:09.186794 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11316 23:21:09.186944
11317 23:21:09.190362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11318 23:21:09.190645 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11320 23:21:09.196596 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_hello)
11321 23:21:09.206574 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11322 23:21:09.206718
11323 23:21:09.213445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11324 23:21:09.213759 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11326 23:21:09.220032 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_abi)
11327 23:21:09.226292 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11328 23:21:09.226432
11329 23:21:09.233013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11330 23:21:09.233331 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11332 23:21:09.239787 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_hello)
11333 23:21:09.246606 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11334 23:21:09.246745
11335 23:21:09.252665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11336 23:21:09.252983 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11338 23:21:09.262891 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM.test_cros_ec_pwm_backlight)
11339 23:21:09.269507 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11340 23:21:09.269660
11341 23:21:09.275967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11342 23:21:09.276350 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11344 23:21:09.285661 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_battery_abi)
11345 23:21:09.289391 Check the cros battery ABI. ... skipped 'No BAT found'
11346 23:21:09.289557
11347 23:21:09.295599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11348 23:21:09.296001 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11350 23:21:09.305400 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_usbpd_charger_abi)
11351 23:21:09.312072 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11352 23:21:09.312287
11353 23:21:09.318650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11354 23:21:09.318989 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11356 23:21:09.328589 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC.test_cros_ec_rtc_abi)
11357 23:21:09.335736 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11358 23:21:09.335912
11359 23:21:09.338720 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11361 23:21:09.341961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11362 23:21:09.348493 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon.test_cros_ec_extcon_usbc_abi)
11363 23:21:09.355008 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11364 23:21:09.355193
11365 23:21:09.361740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11366 23:21:09.361954
11367 23:21:09.362283 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11369 23:21:09.368659 ----------<8>[ 21.935774] <LAVA_SIGNAL_ENDRUN 0_cros-ec 13248414_1.5.2.3.1>
11370 23:21:09.369020 Received signal: <ENDRUN> 0_cros-ec 13248414_1.5.2.3.1
11371 23:21:09.369116 Ending use of test pattern.
11372 23:21:09.369179 Ending test lava.0_cros-ec (13248414_1.5.2.3.1), duration 0.85
11374 23:21:09.374979 ------------------------------------------------------------
11375 23:21:09.378590 Ran 18 tests in 0.338s
11376 23:21:09.378751
11377 23:21:09.378862 OK (skipped=15)
11378 23:21:09.378950 + set +x
11379 23:21:09.381334 <LAVA_TEST_RUNNER EXIT>
11380 23:21:09.381657 ok: lava_test_shell seems to have completed
11381 23:21:09.381954 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11382 23:21:09.382098 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11383 23:21:09.382235 end: 3 lava-test-retry (duration 00:00:01) [common]
11384 23:21:09.382370 start: 4 finalize (timeout 00:07:03) [common]
11385 23:21:09.382508 start: 4.1 power-off (timeout 00:00:30) [common]
11386 23:21:09.382748 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11387 23:21:09.461362 >> Command sent successfully.
11388 23:21:09.464680 Returned 0 in 0 seconds
11389 23:21:09.565157 end: 4.1 power-off (duration 00:00:00) [common]
11391 23:21:09.565664 start: 4.2 read-feedback (timeout 00:07:03) [common]
11392 23:21:09.566053 Listened to connection for namespace 'common' for up to 1s
11393 23:21:10.566970 Finalising connection for namespace 'common'
11394 23:21:10.567152 Disconnecting from shell: Finalise
11395 23:21:10.567237 / #
11396 23:21:10.667588 end: 4.2 read-feedback (duration 00:00:01) [common]
11397 23:21:10.667814 end: 4 finalize (duration 00:00:01) [common]
11398 23:21:10.667939 Cleaning after the job
11399 23:21:10.668038 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248414/tftp-deploy-dekbzbsg/ramdisk
11400 23:21:10.676103 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248414/tftp-deploy-dekbzbsg/kernel
11401 23:21:10.686051 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248414/tftp-deploy-dekbzbsg/dtb
11402 23:21:10.686295 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13248414/tftp-deploy-dekbzbsg/modules
11403 23:21:10.693766 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13248414
11404 23:21:10.799847 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13248414
11405 23:21:10.800029 Job finished correctly